What is an address translation in powerISA jarogn ?
Section 5.7.3 "Storage accesses in real, hypervisor real, and virtual real addressing modes are performed in a manner that depends on the contents of MSR HV , VPM, VRMASD, HRMOR, RMLS, RMOR (see Chapter 2), bit 0 of the effective address (EA0)," Hello 1. If MSR_IR = 0 and MSR_DR = 0, does it mean that addresses are not translated by the MMU ? 2. If EA0 is the 63-rd bit of the effective address e address ? Does this mean that the translation model is derived from the address ? a non privileged context may access privileged memory. thank you
Re: Looking for architecture papers
So,if we're talk about address...
EA0 is actually bit 63 for any kernel address. This means[1] the
effective address is
the real address ( the physical address), because MSR_HV=1.
1. What does it mean PA=EA ? How does the translation work now ?
2. in interrupts, the program counter is set to EA 0c00, ==> EA=0.
So, in interrupt there's a different addressing model ?
[1]. Section 5.7.3, PowerISA 2.07B.
On Mon, Oct 8, 2018 at 10:59 PM Gustavo Romero
wrote:
>
> Hi Raz,
>
> On 10/04/2018 04:41 AM, Raz wrote:
> > Frankly, the more I read the more perplexed I get. For example,
> > according to BOOK III-S, chapter 3,
> > the MSR bits are differ from the ones described in
> > arch/powerpc/include/asm/reg.h.
> > Bit zero, is LE, but in the book it is 64-bit mode.
> >
> > Would someone be kind to explain what I do not understand?
>
> Yes, I know that can be confusing at the first sight when one is used to, for
> instance, x86.
>
> x86 documents use LSB 0 notation, which means (as others already pointed out)
> that the least significant bit of a value is marked as being bit 0.
>
> On the other hand Power documents use MSB 0 notation, which means that the
> most
> significant bit of a value is marked as being bit 0 and as a consequence the
> least significant bit in that notation in a 64-bit platform is bit 63, not bit
> 0. MSB 0 notation is also known as IBM bit notation/bit numbering.
>
> Historically LSB 0 notation tend to be used on docs about little-endian
> architectures (for instance, x86), whilst MSB 0 notation tend to be used on
> docs
> about big-endian architectures (for instance, Power - Power is actually a
> little
> different because it's now bi-endian actually).
>
> However LSB 0 and MSB 0 are only different notations, so LSB 0 can be employed
> on a big-endian architecture documentation, and vice versa.
>
> It happens that kernel code is written in C and for shifts, etc, it's
> convenient
> the LSB 0 notation, not the MSB 0 notation, so it's convenient to use LSB 0
> notation when creating a mask, like in arch/powerpc/include/asm/reg.h), i.e.
> it's convenient to employ bit positions as '63 - '.
>
> So, as another example, in the following gcc macro '_TEXASR_EXTRACT_BITS'
> takes
> a bit position 'BITNUM' as found in the PowerISA documentation but then for
> the
> shift right it uses '63 - BITNUM':
>
> https://github.com/gcc-mirror/gcc/blob/master/gcc/config/rs6000/htmintrin.h#L44-L45
>
> I think it's also important to mention that on PowerISA the elements also
> follow
> the MSB 0 notation. So byte, word, and dword elements in a register found in
> the
> instruction descriptions when referred to 0 are the element "at the left tip",
> i.e. "the most significant elements", so to speak. For instance, take
> instruction "vperm": doc says 'index' takes bits 3:7 of a byte from [byte]
> element 'i'. So for a byte element i=0 it means the most significant byte
> ("on the left tip") of vector register operand 'VRC'. Moreover, specified bits
> in that byte element, i.e. bits 3:7, also follow the MSB 0, so for the
> little-endian addicted thought they are bits 4:0 (LSB 0 notation).
>
> Now, if bits 4:0 = 0b00011 (decimal 3), we grab byte element 3 from 'src'
> (256-bit). However byte element 3 is also in MSB 0 notation, so it means third
> byte of 'src' but starting counting bytes from 0 from the left to the right
> (which in IMO looks indeed more natural since we count, for instance, Natural
> Numbers on the 'x' axis similarly).
>
> Hence, it's like to say that 'vperm' instruction in a certain sense has a
> "big-endian semantics" for the byte indices. The 'vpermr' instruction
> introduced
> by PowerISA v3.0 is meant to cope with that, so 'vpermr' byte indices have a
> "little-endian semantics", so for bits 3:7 MSB 0 (or bits 4:0 in LSB 0
> notation) =
> 0b00011 (decimal 3), on the 'vpermr' instruction it really means we must count
> bytes starting from right to left as in the LSB 0 notation and grab the third
> byte
> element from right to left.
>
> So, for instance:
>
> vr0uint128 = 0x
> vr1uint128 = 0x00102030405060708090a0b0c0d0e0f0
> vr2uint128 = 0x0111223344556677aabbccddeeff
> vr3uint128 = 0x0300
>
> we have 'src' as:
>
> MSB 0: v--- byte 0, 1, 2, 3, ...
> LSB 0:
&
Re: Looking for architecture papers
Both systemsim and my powerpc server boots with MSR_HV=1, i.e, hypervisor state. Is there away to fix that ? writing to the MSR cannot work according the documentation ( and reality ). On Sat, Oct 6, 2018 at 3:27 PM Segher Boessenkool wrote: > > On Sat, Oct 06, 2018 at 12:19:45PM +0300, Raz wrote: > > Hey > > How does HVSC works ? > > I looked in the code and LoPAR documentation. It looks like there is > > vector called > > system_call_pSeries ( at 0xc00 ) that is supposed to be called when we > > invoke HVSC from kernel > > mode. > > Now, I wrote a NULL call HSVC and patched the exceptions-64s.S to > > return RFID immediately. > > This does not work. > > Would you be so kind to explain how HVSC works ? > > thank you > > If your kernel is not running in hypervisor mode, sc 1 does not call the > kernel (but the hypervisor, instead). If your kernel _is_ running in > hypervisor mode, sc 1 does the same as sc 0, a normal system call. > > I don't know which it is for you; you didn't say. > > I have no idea what "a NULL call HSVC" means. If you make exception c00 > return immediately (as you suggest) then you have made all system calls > non-functional, which indeed is unlikely to work as you want. > > > Segher
Re: Looking for architecture papers
Hey How does HVSC works ? I looked in the code and LoPAR documentation. It looks like there is vector called system_call_pSeries ( at 0xc00 ) that is supposed to be called when we invoke HVSC from kernel mode. Now, I wrote a NULL call HSVC and patched the exceptions-64s.S to return RFID immediately. This does not work. Would you be so kind to explain how HVSC works ? thank you On Thu, Oct 4, 2018 at 1:16 PM Gabriel Paubert wrote: > > On Thu, Oct 04, 2018 at 10:41:13AM +0300, Raz wrote: > > Frankly, the more I read the more perplexed I get. For example, > > according to BOOK III-S, chapter 3, > > the MSR bits are differ from the ones described in > > arch/powerpc/include/asm/reg.h. > > Bit zero, is LE, but in the book it is 64-bit mode. > > Just a problem of bit order definitions: IBM hardware definitions use > big-endian bit ordering, where bit 0 is the most significant bit. > > > > > Would someone be kind to explain what I do not understand? > > > > Thank you > > Gabriel
Re: Looking for architecture papers
Frankly, the more I read the more perplexed I get. For example, according to BOOK III-S, chapter 3, the MSR bits are differ from the ones described in arch/powerpc/include/asm/reg.h. Bit zero, is LE, but in the book it is 64-bit mode. Would someone be kind to explain what I do not understand? Thank you On Wed, Oct 3, 2018 at 7:07 AM Michael Ellerman wrote: > > Raz writes: > > > Hello > > > > I want to learn about powerpc architecture, mainly hypervisor and > > partioning. I download the books (1,2, and 3 ) but I feel it lacks > > a lot of information. Are there other books ? > > The ISA describes how the CPU works to allow you to implement a > hypervisor, but it doesn't describe any of the HV/Kernel APIs. > > That's mostly covered in "LoPAPR": > > https://members.openpowerfoundation.org/document/dl/469 > > > Although that's not been updated for Power9. > > cheers
Re: Looking for architecture papers
First, thank you. And another question, is there a development environment that resembles Fixed Virtual Platform for ARM ( FVP ARM) ? On Sun, Sep 30, 2018 at 1:13 AM Segher Boessenkool wrote: > > Hi Raz, > > On Sun, Sep 30, 2018 at 12:24:35AM +0300, Raz wrote: > > I want to learn about powerpc architecture, mainly hypervisor and > > partioning. I download the books (1,2, and 3 ) but I feel it lacks > > a lot of information. Are there other books ? > > I suspect you are looking at an ancient version of the architecture. > The current version is 3.0B, available here: > https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0 > > Good luck and have fun, > > > Segher
Looking for architecture papers
Hello I want to learn about powerpc architecture, mainly hypervisor and partioning. I download the books (1,2, and 3 ) but I feel it lacks a lot of information. Are there other books ? Kind regards
Re: node /dev/ttyCPM2 not created
Thanks, I don't see any mdev process running. Just wonder who is creating /dev/ttyCPM1 since in the device table file (device_table.txt) I have only node: 204 (major) 46 (minor) defined. But I can see /dev/ttyCPM1 (204 47) Liran. On Fri, Mar 13, 2009 at 4:18 PM, Timur Tabi wrote: > On Fri, Mar 13, 2009 at 1:56 PM, liran raz > wrote: > > > Does anyone know what I'm missing? or what do I need to configure > > in order to have: /dev/ttyCPM2 ? > > My guess is that you don't have udev or mdev running. > > > -- > Timur Tabi > Linux kernel developer at Freescale > ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
node /dev/ttyCPM2 not created
hi, I've configured SCC1 to be serial uart driver. (in addition to SMC1 & SMC2 that were already configured as UARTs). Now I can see these defines in .config file: CONFIG_SERIAL_CPM_SCC1=y CONFIG_SERIAL_CPM_SMC1=y CONFIG_SERIAL_CPM_SMC2=y When the kernal starts I see these log messages: ttyCPM0 at MMIO 0xc505ca80 (irq = 17) is a CPM UART ttyCPM1 at MMIO 0xc5060a90 (irq = 16) is a CPM UART ttyCPM2 at MMIO 0xc5064a00 (irq = 40) is a CPM UART But when I list the devices: [r...@urm dev]# ll ttyCPM* crw-rw-rw-1 root root 204, 46 Dec 31 17:00 ttyCPM0 crw-rw-rw-1 root root 204, 47 Dec 31 17:00 ttyCPM1 I can't see ttyCPM2. Does anyone know what I'm missing? or what do I need to configure in order to have: /dev/ttyCPM2 ? Thanks, Liran. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
node /dev/ttyCPM2 not created
hi, I've configured SCC1 to be serial uart driver. (in addition to SMC1 & SMC2 that were already configured as UARTs). Now I can see these defines in .config file: CONFIG_SERIAL_CPM_SCC1=y CONFIG_SERIAL_CPM_SMC1=y CONFIG_SERIAL_CPM_SMC2=y When the kernal starts I see these log messages: ttyCPM0 at MMIO 0xc505ca80 (irq = 17) is a CPM UART ttyCPM1 at MMIO 0xc5060a90 (irq = 16) is a CPM UART ttyCPM2 at MMIO 0xc5064a00 (irq = 40) is a CPM UART But when I list the devices: [r...@urm dev]# ll ttyCPM* crw-rw-rw-1 root root 204, 46 Dec 31 17:00 ttyCPM0 crw-rw-rw-1 root root 204, 47 Dec 31 17:00 ttyCPM1 I can't see ttyCPM2. Does anyone know what I'm missing? or what do I need to configure in order to have: /dev/ttyCPM2 ? Thanks, Liran. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
