[PATCHv4] Xilinx Virtex 4 FX Soft FPU support
This patch enables support for Xilinx Virtex 4 FX singe-float FPU. This patch enables support for Xilinx Virtex 4 FX singe-float FPU. Changelog v3-v4 -Added help for CONFIG_XILINX_SOFTFPU option -Made kernel math emulation dependent on !PPC_FPU. Changelog v2-v3: -Fixed whitespaces for SAVE_FPR/REST_FPR. -Changed description of MSR_AP bit. -Removed the stub for APU unavailable exception. Changelog v1-v2: -Added MSR_AP bit definition -Renamed CONFIG_XILINX_FPU to CONFIG_XILINX_SOFTFPU, moved it to 'Platform support' and made it Virtex4-FX-only. -Changed SAVE_FPR/REST_FPR definition style. Caveats: - Hard-float binaries which rely on in-kernel math emulation will give wrong results since they expect 64-bit double-precision instead of 32-bit single-precision numbers which Xilinx V4-FX Soft FPU produces. Signed-off-by: Sergey Temerkhanovtemerkha...@cifronik.ru diff -r df25ff2b70a4 arch/powerpc/Kconfig --- a/arch/powerpc/Kconfig Fri Aug 27 21:10:12 2010 +0400 +++ b/arch/powerpc/Kconfig Fri Sep 10 13:08:13 2010 +0400 @@ -293,7 +293,7 @@ config MATH_EMULATION bool Math emulation - depends on 4xx || 8xx || E200 || PPC_MPC832x || E500 + depends on (4xx || 8xx || E200 || PPC_MPC832x || E500) !PPC_FPU ---help--- Some PowerPC chips designed for embedded applications do not have a floating-point unit and therefore do not implement the diff -r df25ff2b70a4 arch/powerpc/include/asm/ppc_asm.h --- a/arch/powerpc/include/asm/ppc_asm.hFri Aug 27 21:10:12 2010 +0400 +++ b/arch/powerpc/include/asm/ppc_asm.hFri Sep 10 13:08:13 2010 +0400 @@ -85,13 +85,21 @@ #define REST_8GPRS(n, base)REST_4GPRS(n, base); REST_4GPRS(n+4, base) #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) -#define SAVE_FPR(n, base) stfdn,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) + +#ifdef CONFIG_XILINX_SOFTFPU +#define SAVE_FPR(n, base) stfs n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#define REST_FPR(n, base) lfs n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#else +#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#endif + #define SAVE_2FPRS(n, base)SAVE_FPR(n, base); SAVE_FPR(n+1, base) #define SAVE_4FPRS(n, base)SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) #define SAVE_8FPRS(n, base)SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) -#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) + #define REST_2FPRS(n, base)REST_FPR(n, base); REST_FPR(n+1, base) #define REST_4FPRS(n, base)REST_2FPRS(n, base); REST_2FPRS(n+2, base) #define REST_8FPRS(n, base)REST_4FPRS(n, base); REST_4FPRS(n+4, base) diff -r df25ff2b70a4 arch/powerpc/include/asm/reg.h --- a/arch/powerpc/include/asm/reg.hFri Aug 27 21:10:12 2010 +0400 +++ b/arch/powerpc/include/asm/reg.hFri Sep 10 13:08:13 2010 +0400 @@ -30,6 +30,7 @@ #define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */ #define MSR_HV_LG 60 /* Hypervisor state */ #define MSR_VEC_LG 25 /* Enable AltiVec */ +#define MSR_AP_LG 25 /* Enable APU */ #define MSR_VSX_LG 23 /* Enable VSX */ #define MSR_POW_LG 18 /* Enable Power Management */ #define MSR_WE_LG 18 /* Wait State Enable */ @@ -71,6 +72,7 @@ #define MSR_HV 0 #endif +#define MSR_AP __MASK(MSR_AP_LG) /* Enable APU */ #define MSR_VEC__MASK(MSR_VEC_LG) /* Enable AltiVec */ #define MSR_VSX__MASK(MSR_VSX_LG) /* Enable VSX */ #define MSR_POW__MASK(MSR_POW_LG) /* Enable Power Management */ diff -r df25ff2b70a4 arch/powerpc/kernel/fpu.S --- a/arch/powerpc/kernel/fpu.S Fri Aug 27 21:10:12 2010 +0400 +++ b/arch/powerpc/kernel/fpu.S Fri Sep 10 13:08:13 2010 +0400 @@ -57,6 +57,9 @@ _GLOBAL(load_up_fpu) mfmsr r5 ori r5,r5,MSR_FP +#ifdef CONFIG_XILINX_SOFTFPU + orisr5,r5,msr...@h +#endif #ifdef CONFIG_VSX BEGIN_FTR_SECTION orisr5,r5,msr_...@h @@ -85,6 +88,9 @@ toreal(r5) PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) li r10,MSR_FP|MSR_FE0|MSR_FE1 +#ifdef CONFIG_XILINX_SOFTFPU + orisr10,r10,msr...@h +#endif andcr4,r4,r10 /* disable FP for previous task */ PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 1: @@ -94,6 +100,9 @@ mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ lwz r4,THREAD_FPEXC_MODE(r5) ori r9,r9,MSR_FP/* enable FP for current */ +#ifdef CONFIG_XILINX_SOFTFPU +
[PATCHv4] Xilinx Virtex 4 FX Soft FPU support
This patch enables support for Xilinx Virtex 4 FX singe-float FPU. This patch enables support for Xilinx Virtex 4 FX singe-float FPU. Changelog v3-v4 -Added help for CONFIG_XILINX_SOFTFPU option -Made kernel math emulation dependent on !PPC_FPU. Changelog v2-v3: -Fixed whitespaces for SAVE_FPR/REST_FPR. -Changed description of MSR_AP bit. -Removed the stub for APU unavailable exception. Changelog v1-v2: -Added MSR_AP bit definition -Renamed CONFIG_XILINX_FPU to CONFIG_XILINX_SOFTFPU, moved it to 'Platform support' and made it Virtex4-FX-only. -Changed SAVE_FPR/REST_FPR definition style. Caveats: - Hard-float binaries which rely on in-kernel math emulation will give wrong results since they expect 64-bit double-precision instead of 32-bit single-precision numbers which Xilinx V4-FX Soft FPU produces. Signed-off-by: Sergey Temerkhanovtemerkha...@cifronik.ru diff -r df25ff2b70a4 arch/powerpc/Kconfig --- a/arch/powerpc/Kconfig Fri Aug 27 21:10:12 2010 +0400 +++ b/arch/powerpc/Kconfig Fri Sep 10 13:08:13 2010 +0400 @@ -293,7 +293,7 @@ config MATH_EMULATION bool Math emulation - depends on 4xx || 8xx || E200 || PPC_MPC832x || E500 + depends on (4xx || 8xx || E200 || PPC_MPC832x || E500) !PPC_FPU ---help--- Some PowerPC chips designed for embedded applications do not have a floating-point unit and therefore do not implement the diff -r df25ff2b70a4 arch/powerpc/include/asm/ppc_asm.h --- a/arch/powerpc/include/asm/ppc_asm.hFri Aug 27 21:10:12 2010 +0400 +++ b/arch/powerpc/include/asm/ppc_asm.hFri Sep 10 13:08:13 2010 +0400 @@ -85,13 +85,21 @@ #define REST_8GPRS(n, base)REST_4GPRS(n, base); REST_4GPRS(n+4, base) #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) -#define SAVE_FPR(n, base) stfdn,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) + +#ifdef CONFIG_XILINX_SOFTFPU +#define SAVE_FPR(n, base) stfs n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#define REST_FPR(n, base) lfs n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#else +#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#endif + #define SAVE_2FPRS(n, base)SAVE_FPR(n, base); SAVE_FPR(n+1, base) #define SAVE_4FPRS(n, base)SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) #define SAVE_8FPRS(n, base)SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) -#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) + #define REST_2FPRS(n, base)REST_FPR(n, base); REST_FPR(n+1, base) #define REST_4FPRS(n, base)REST_2FPRS(n, base); REST_2FPRS(n+2, base) #define REST_8FPRS(n, base)REST_4FPRS(n, base); REST_4FPRS(n+4, base) diff -r df25ff2b70a4 arch/powerpc/include/asm/reg.h --- a/arch/powerpc/include/asm/reg.hFri Aug 27 21:10:12 2010 +0400 +++ b/arch/powerpc/include/asm/reg.hFri Sep 10 13:08:13 2010 +0400 @@ -30,6 +30,7 @@ #define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */ #define MSR_HV_LG 60 /* Hypervisor state */ #define MSR_VEC_LG 25 /* Enable AltiVec */ +#define MSR_AP_LG 25 /* Enable APU */ #define MSR_VSX_LG 23 /* Enable VSX */ #define MSR_POW_LG 18 /* Enable Power Management */ #define MSR_WE_LG 18 /* Wait State Enable */ @@ -71,6 +72,7 @@ #define MSR_HV 0 #endif +#define MSR_AP __MASK(MSR_AP_LG) /* Enable APU */ #define MSR_VEC__MASK(MSR_VEC_LG) /* Enable AltiVec */ #define MSR_VSX__MASK(MSR_VSX_LG) /* Enable VSX */ #define MSR_POW__MASK(MSR_POW_LG) /* Enable Power Management */ diff -r df25ff2b70a4 arch/powerpc/kernel/fpu.S --- a/arch/powerpc/kernel/fpu.S Fri Aug 27 21:10:12 2010 +0400 +++ b/arch/powerpc/kernel/fpu.S Fri Sep 10 13:08:13 2010 +0400 @@ -57,6 +57,9 @@ _GLOBAL(load_up_fpu) mfmsr r5 ori r5,r5,MSR_FP +#ifdef CONFIG_XILINX_SOFTFPU + orisr5,r5,msr...@h +#endif #ifdef CONFIG_VSX BEGIN_FTR_SECTION orisr5,r5,msr_...@h @@ -85,6 +88,9 @@ toreal(r5) PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) li r10,MSR_FP|MSR_FE0|MSR_FE1 +#ifdef CONFIG_XILINX_SOFTFPU + orisr10,r10,msr...@h +#endif andcr4,r4,r10 /* disable FP for previous task */ PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 1: @@ -94,6 +100,9 @@ mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ lwz r4,THREAD_FPEXC_MODE(r5) ori r9,r9,MSR_FP/* enable FP for current */ +#ifdef CONFIG_XILINX_SOFTFPU +
[Resend][PATCHv3] Xilinx Virtex 4 FX Soft FPU support
+420,19 @@ addir3,r1,STACK_FRAME_OVERHEAD EXC_XFER_STD(0x700, program_check_exception) +/* 0x0800 - FPU unavailable Exception */ +#ifdef CONFIG_PPC_FPU + START_EXCEPTION(0x0800, FloatingPointUnavailable) + NORMAL_EXCEPTION_PROLOG + beq 1f; \ + bl load_up_fpu;/* if from user, just load it up */ \ + b fast_exception_return;\ +1: addir3,r1,STACK_FRAME_OVERHEAD; \ + EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception) +#else EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_EE) +#endif + EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_EE) EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_EE) EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_EE) @@ -821,8 +833,10 @@ * The PowerPC 4xx family of processors do not have an FPU, so this just * returns. */ +#ifndef CONFIG_PPC_FPU _ENTRY(giveup_fpu) blr +#endif /* This is where the main kernel code starts. */ diff -r 626de0d94469 arch/powerpc/platforms/Kconfig --- a/arch/powerpc/platforms/KconfigWed May 26 15:33:32 2010 +0400 +++ b/arch/powerpc/platforms/KconfigWed May 26 20:30:43 2010 +0400 @@ -333,4 +333,9 @@ bool Xilinx PCI host bridge support depends on PCI XILINX_VIRTEX +config XILINX_SOFTFPU + bool Xilinx Soft FPU + select PPC_FPU + depends on XILINX_VIRTEX_4_FX !PPC40x_SIMPLE !405GP !405GPR + endmenu -- Regards, Sergey Temerkhanov ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCHv2] [RFC] Xilinx Virtex 4 FX Soft FPU support
On Wednesday 26 May 2010 01:38:47 Grant Likely wrote: (cc'ing Josh Boyer and John Linn) On Thu, May 20, 2010 at 4:01 AM, Sergey Temerkhanov temerkha...@cifronik.ru wrote: This patch enables support for Xilinx Virtex 4 FX singe-float FPU. Changelog v1-v2: -Added MSR_AP bit definition -Renamed CONFIG_XILINX_FPU to CONFIG_XILINX_SOFTFPU, moved it to 'Platform support' and made it Virtex4-FX-only. -Changed SAVE_FPR/REST_FPR definition style. Caveats: - Hard-float binaries which rely on in-kernel math emulation will give wrong results since they expect 64-bit double-precision instead of 32-bit single-precision numbers which Xilinx V4-FX Soft FPU produces. Regards, Sergey Temerkhanov Hi Sergey. Comments below. First off, see if you can use 'git mail' or some other way to inline your patches. Patches as attachments are awkward to deal with and the patch description is getting separated from the patch itself. Signed-off-by: Sergey Temerkhanovtemerkha...@cifronik.ru diff -r b59861a64e13 arch/powerpc/include/asm/ppc_asm.h --- a/arch/powerpc/include/asm/ppc_asm.hThu May 20 13:24:53 2010 +0400 +++ b/arch/powerpc/include/asm/ppc_asm.hThu May 20 13:55:10 2010 +0400 @@ -85,13 +85,21 @@ #define REST_8GPRS(n, base)REST_4GPRS(n, base); REST_4GPRS(n+4, base) #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) -#define SAVE_FPR(n, base) stfdn,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) + +#ifdef CONFIG_XILINX_SOFTFPU +#define SAVE_FPR(n, base) stfs n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#define REST_FPR(n, base) lfs n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#else +#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#endif + Hint: If you don't change the whitespace on the SAVE_FPR() line, then diff will realize it is unchanged and reviewers will have more context queues as to what you are doing. Otherwise, this looks better. Agreed, I've missed it somehow. #define SAVE_2FPRS(n, base)SAVE_FPR(n, base); SAVE_FPR(n+1, base) #define SAVE_4FPRS(n, base)SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) #define SAVE_8FPRS(n, base)SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) -#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) + #define REST_2FPRS(n, base)REST_FPR(n, base); REST_FPR(n+1, base) #define REST_4FPRS(n, base)REST_2FPRS(n, base); REST_2FPRS(n+2, base) #define REST_8FPRS(n, base)REST_4FPRS(n, base); REST_4FPRS(n+4, base) diff -r b59861a64e13 arch/powerpc/include/asm/reg.h --- a/arch/powerpc/include/asm/reg.hThu May 20 13:24:53 2010 +0400 +++ b/arch/powerpc/include/asm/reg.hThu May 20 13:55:10 2010 +0400 @@ -30,6 +30,7 @@ #define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */ #define MSR_HV_LG 60 /* Hypervisor state */ #define MSR_VEC_LG 25 /* Enable AltiVec */ +#define MSR_AP_LG 25 /* Enable APU */ #define MSR_VSX_LG 23 /* Enable VSX */ #define MSR_POW_LG 18 /* Enable Power Management */ #define MSR_WE_LG 18 /* Wait State Enable */ @@ -71,6 +72,7 @@ #define MSR_HV 0 #endif +#define MSR_AP __MASK(MSR_AP_LG) /* Enable APU */ Need to be more specific: Enable Xilinx Virtex 405 APU. Same goes for MSR_AP_LG line above. This bit is also defined for PPC405 cores other than Xilinx, so I think it will be better as Enable PPC405 APU. #define MSR_VEC__MASK(MSR_VEC_LG) /* Enable AltiVec */ #define MSR_VSX__MASK(MSR_VSX_LG) /* Enable VSX */ #define MSR_POW__MASK(MSR_POW_LG) /* Enable Power Management */ diff -r b59861a64e13 arch/powerpc/kernel/fpu.S --- a/arch/powerpc/kernel/fpu.S Thu May 20 13:24:53 2010 +0400 +++ b/arch/powerpc/kernel/fpu.S Thu May 20 13:55:10 2010 +0400 @@ -57,6 +57,9 @@ _GLOBAL(load_up_fpu) mfmsr r5 ori r5,r5,MSR_FP +#ifdef CONFIG_XILINX_SOFTFPU + orisr5,r5,msr...@h +#endif #ifdef CONFIG_VSX BEGIN_FTR_SECTION orisr5,r5,msr_...@h @@ -85,6 +88,9 @@ toreal(r5) PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) li r10,MSR_FP|MSR_FE0|MSR_FE1 +#ifdef CONFIG_XILINX_SOFTFPU + orisr10,r10,msr...@h +#endif andcr4,r4,r10 /* disable FP for previous task */ PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 1: @@ -94,6 +100,9 @@ mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ lwz r4,THREAD_FPEXC_MODE
[PATCHv3] [RFC] Xilinx Virtex 4 FX Soft FPU support
+420,19 @@ addir3,r1,STACK_FRAME_OVERHEAD EXC_XFER_STD(0x700, program_check_exception) +/* 0x0800 - FPU unavailable Exception */ +#ifdef CONFIG_PPC_FPU + START_EXCEPTION(0x0800, FloatingPointUnavailable) + NORMAL_EXCEPTION_PROLOG + beq 1f; \ + bl load_up_fpu;/* if from user, just load it up */ \ + b fast_exception_return;\ +1: addir3,r1,STACK_FRAME_OVERHEAD; \ + EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception) +#else EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_EE) +#endif + EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_EE) EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_EE) EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_EE) @@ -821,8 +833,10 @@ * The PowerPC 4xx family of processors do not have an FPU, so this just * returns. */ +#ifndef CONFIG_PPC_FPU _ENTRY(giveup_fpu) blr +#endif /* This is where the main kernel code starts. */ diff -r 626de0d94469 arch/powerpc/platforms/Kconfig --- a/arch/powerpc/platforms/KconfigWed May 26 15:33:32 2010 +0400 +++ b/arch/powerpc/platforms/KconfigWed May 26 20:30:43 2010 +0400 @@ -333,4 +333,9 @@ bool Xilinx PCI host bridge support depends on PCI XILINX_VIRTEX +config XILINX_SOFTFPU + bool Xilinx Soft FPU + select PPC_FPU + depends on XILINX_VIRTEX_4_FX !PPC40x_SIMPLE !405GP !405GPR + endmenu -- Regards, Sergey Temerkhanov, Cifronic ZAO ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] [RFC] Xilinx Virtex 4 FX Soft FPU support
On Wednesday 19 May 2010 20:52:01 Grant Likely wrote: Hi Sergey. Comments below. diff -r 9d9ac97e095d .config --- a/.config Thu Feb 25 21:23:42 2010 +0300 +++ b/.config Thu Feb 25 21:49:02 2010 +0300 .config changes should not appear in your patch file. diff -r 9d9ac97e095d arch/powerpc/include/asm/ppc_asm.h --- a/arch/powerpc/include/asm/ppc_asm.hThu Feb 25 21:23:42 2010 +0300 +++ b/arch/powerpc/include/asm/ppc_asm.hThu Feb 25 21:49:02 2010 +0300 @@ -85,13 +85,23 @@ #define REST_8GPRS(n, base)REST_4GPRS(n, base); REST_4GPRS(n+4, base) #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) -#define SAVE_FPR(n, base) stfdn,THREAD_FPR0+8*TS_FPRWIDTH*(n) (base) + +#ifdef CONFIG_XILINX_FPU +#define stfr stfs +#define lfr lfs +#else +#define stfr stfd +#define lfr lfd +#endif the stfr/lfr redirect is a little weird. Why not simply: + +#ifdef CONFIG_XILINX_FPU +#define SAVE_FPR(n, base) stfsn,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#define REST_FPR(n, base) lfs n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#else +#define SAVE_FPR(n, base) stfdn,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#endif A comment here describing that only single precision works with the XILINX 405 FPU wouldn't go amiss either. Agreed. diff -r 9d9ac97e095d arch/powerpc/kernel/fpu.S --- a/arch/powerpc/kernel/fpu.S Thu Feb 25 21:23:42 2010 +0300 +++ b/arch/powerpc/kernel/fpu.S Thu Feb 25 21:49:02 2010 +0300 @@ -57,6 +57,9 @@ _GLOBAL(load_up_fpu) mfmsr r5 ori r5,r5,MSR_FP +#ifdef CONFIG_XILINX_FPU + oris r5,r5,msr_...@h +#endif So AltiVec is being enabled here, but double precision is not supported? That bit means 'APU enabled' for PowerPC 405 core. I've simply used existing #define. As Xilinx uses APU facilities for their FPU this bit must be set too. What instructions are supported? Only single precision is supported for Virtex-4 FPU. Double presicion opcodes work as single precision there. Also, please stick with the same whitespace convention used in the lines above (tab indent instead of a space). Again, a comment would not go amiss. #ifdef CONFIG_VSX BEGIN_FTR_SECTION orisr5,r5,msr_...@h @@ -85,6 +88,9 @@ toreal(r5) PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) li r10,MSR_FP|MSR_FE0|MSR_FE1 +#ifdef CONFIG_XILINX_FPU + orisr10,r10,msr_...@h +#endif andcr4,r4,r10 /* disable FP for previous task */ PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 1: @@ -94,6 +100,9 @@ mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ lwz r4,THREAD_FPEXC_MODE(r5) ori r9,r9,MSR_FP/* enable FP for current */ +#ifdef CONFIG_XILINX_FPU + orisr9,r9,msr_...@h +#endif or r9,r9,r4 #else ld r4,PACACURRENT(r13) @@ -124,6 +133,9 @@ _GLOBAL(giveup_fpu) mfmsr r5 ori r5,r5,MSR_FP +#ifdef CONFIG_XILINX_FPU + orisr5,r5,msr_...@h +#endif #ifdef CONFIG_VSX BEGIN_FTR_SECTION orisr5,r5,msr_...@h @@ -145,6 +157,9 @@ beq 1f PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) li r3,MSR_FP|MSR_FE0|MSR_FE1 +#ifdef CONFIG_XILINX_FPU + orisr3,r3,msr_...@h +#endif #ifdef CONFIG_VSX BEGIN_FTR_SECTION orisr3,r3,msr_...@h diff -r 9d9ac97e095d arch/powerpc/kernel/head_40x.S --- a/arch/powerpc/kernel/head_40x.SThu Feb 25 21:23:42 2010 +0300 +++ b/arch/powerpc/kernel/head_40x.SThu Feb 25 21:49:02 2010 +0300 @@ -420,7 +420,19 @@ addir3,r1,STACK_FRAME_OVERHEAD EXC_XFER_STD(0x700, program_check_exception) +/* 0x0800 - FPU unavailable Exception */ +#ifdef CONFIG_PPC_FPU + START_EXCEPTION(0x0800, FloatingPointUnavailable) + NORMAL_EXCEPTION_PROLOG + beq 1f; \ + bl load_up_fpu;/* if from user, just load it up */ \ + b fast_exception_return;\ +1: addir3,r1,STACK_FRAME_OVERHEAD; \ + EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception) +#else EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_EE) +#endif + EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_EE) EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_EE) EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_EE) @@ -432,7 +444,7 @@ EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_EE) EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_EE) + EXCEPTION(0x0F20, Trap_0F, unknown_exception, EXC_XFER_EE) Why? Xilinx UG011 and IBM PowerPC
[PATCHv2] [RFC] Xilinx Virtex 4 FX Soft FPU support
This patch enables support for Xilinx Virtex 4 FX singe-float FPU. Changelog v1-v2: -Added MSR_AP bit definition -Renamed CONFIG_XILINX_FPU to CONFIG_XILINX_SOFTFPU, moved it to 'Platform support' and made it Virtex4-FX-only. -Changed SAVE_FPR/REST_FPR definition style. Caveats: - Hard-float binaries which rely on in-kernel math emulation will give wrong results since they expect 64-bit double-precision instead of 32-bit single-precision numbers which Xilinx V4-FX Soft FPU produces. Regards, Sergey Temerkhanov Signed-off-by: Sergey Temerkhanovtemerkha...@cifronik.ru diff -r b59861a64e13 arch/powerpc/include/asm/ppc_asm.h --- a/arch/powerpc/include/asm/ppc_asm.h Thu May 20 13:24:53 2010 +0400 +++ b/arch/powerpc/include/asm/ppc_asm.h Thu May 20 13:55:10 2010 +0400 @@ -85,13 +85,21 @@ #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) -#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) + +#ifdef CONFIG_XILINX_SOFTFPU +#define SAVE_FPR(n, base) stfs n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#define REST_FPR(n, base) lfs n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#else +#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#endif + #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) -#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) + #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) diff -r b59861a64e13 arch/powerpc/include/asm/reg.h --- a/arch/powerpc/include/asm/reg.h Thu May 20 13:24:53 2010 +0400 +++ b/arch/powerpc/include/asm/reg.h Thu May 20 13:55:10 2010 +0400 @@ -30,6 +30,7 @@ #define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */ #define MSR_HV_LG 60 /* Hypervisor state */ #define MSR_VEC_LG 25 /* Enable AltiVec */ +#define MSR_AP_LG 25 /* Enable APU */ #define MSR_VSX_LG 23 /* Enable VSX */ #define MSR_POW_LG 18 /* Enable Power Management */ #define MSR_WE_LG 18 /* Wait State Enable */ @@ -71,6 +72,7 @@ #define MSR_HV 0 #endif +#define MSR_AP __MASK(MSR_AP_LG) /* Enable APU */ #define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */ #define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */ #define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */ diff -r b59861a64e13 arch/powerpc/kernel/fpu.S --- a/arch/powerpc/kernel/fpu.S Thu May 20 13:24:53 2010 +0400 +++ b/arch/powerpc/kernel/fpu.S Thu May 20 13:55:10 2010 +0400 @@ -57,6 +57,9 @@ _GLOBAL(load_up_fpu) mfmsr r5 ori r5,r5,MSR_FP +#ifdef CONFIG_XILINX_SOFTFPU + oris r5,r5,msr...@h +#endif #ifdef CONFIG_VSX BEGIN_FTR_SECTION oris r5,r5,msr_...@h @@ -85,6 +88,9 @@ toreal(r5) PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) li r10,MSR_FP|MSR_FE0|MSR_FE1 +#ifdef CONFIG_XILINX_SOFTFPU + oris r10,r10,msr...@h +#endif andc r4,r4,r10 /* disable FP for previous task */ PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 1: @@ -94,6 +100,9 @@ mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ lwz r4,THREAD_FPEXC_MODE(r5) ori r9,r9,MSR_FP /* enable FP for current */ +#ifdef CONFIG_XILINX_SOFTFPU + oris r9,r9,msr...@h +#endif or r9,r9,r4 #else ld r4,PACACURRENT(r13) @@ -124,6 +133,9 @@ _GLOBAL(giveup_fpu) mfmsr r5 ori r5,r5,MSR_FP +#ifdef CONFIG_XILINX_SOFTFPU + oris r5,r5,msr...@h +#endif #ifdef CONFIG_VSX BEGIN_FTR_SECTION oris r5,r5,msr_...@h @@ -145,6 +157,9 @@ beq 1f PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) li r3,MSR_FP|MSR_FE0|MSR_FE1 +#ifdef CONFIG_XILINX_SOFTFPU + oris r3,r3,msr...@h +#endif #ifdef CONFIG_VSX BEGIN_FTR_SECTION oris r3,r3,msr_...@h diff -r b59861a64e13 arch/powerpc/kernel/head_40x.S --- a/arch/powerpc/kernel/head_40x.S Thu May 20 13:24:53 2010 +0400 +++ b/arch/powerpc/kernel/head_40x.S Thu May 20 13:55:10 2010 +0400 @@ -420,7 +420,19 @@ addi r3,r1,STACK_FRAME_OVERHEAD EXC_XFER_STD(0x700, program_check_exception) +/* 0x0800 - FPU unavailable Exception */ +#ifdef CONFIG_PPC_FPU + START_EXCEPTION(0x0800, FloatingPointUnavailable) + NORMAL_EXCEPTION_PROLOG + beq 1f; \ + bl load_up_fpu; /* if from user, just load it up */ \ + b fast_exception_return; \ +1: addi r3,r1,STACK_FRAME_OVERHEAD; \ + EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception) +#else EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_EE) +#endif + EXCEPTION(0x0900, Trap_09
Re: [microblaze-uclinux] [PATCHv2] [RFC] Xilinx MPMC SDMA subsystem
On Wednesday 28 April 2010 09:13:06 you wrote:
Hi Sergey and Steven,
On Tue, Apr 27, 2010 at 8:29 PM, Steven J. Magnani
st...@digidescorp.com wrote:
On Wed, 2010-04-28 at 02:06 +0400, Sergey Temerkhanov wrote:
This is the 2nd version of Xilinx MPMC LocalLink SDMA subsystem
Changelog v2:
* Changed the functions and struct definition prefix from sdma_ to
xllsdma_ * Platform bus bindings and various changes by Steven J.
Magnani. * Moved source files from arch/powerpc/sysdev to global
locations and added CONFIG_XLLSDMA option.
Regards, Sergey Temerkhanov,
Cifronic ZAO
diff -r baced9e29ab5 drivers/dma/Kconfig
--- a/drivers/dma/Kconfig Tue Apr 27 20:48:50 2010 +0400
+++ b/drivers/dma/Kconfig Wed Apr 28 02:00:51 2010 +0400
@@ -97,6 +97,14 @@
Support the TXx9 SoC internal DMA controller. This can be
integrated in chips such as the Toshiba TX4927/38/39.
+config XLLSDMA
I'd prefer XILINX_LLSDMA. XLLSDMA could be ambiguous in the global
namespace (for a human reader), particularly as it is something that
few people will actually see.
I've changed it to XILINX_SDMA in the current version.
+ bool Xilinx MPMC DMA support
+ depends on XILINX_VIRTEX || MICROBLAZE
+ select DMA_ENGINE
+ help
+ Support fot Xilinx MPMC LocalLink SDMA. Virtex FPGA family
+ has it integrated or fabric-based.
+
fot -- for
Since the xllsdma driver provides services to other drivers - not to
userland - I think this would be better as a silent option, selected
automatically when something like ll_temac or the forthcoming Xilinx DMA
engine is selected. If we do it that way, note that XLLSDMA is
independent of DMA_ENGINE so drivers/Makefile will need to be patched so
that the dma subdirectory is always y.
Agreed. However, looking at this code, I don't see anything that
actually uses DMA_ENGINE here. Am I missing something?
It's because the appropriate line in drivers/Makefile is
obj-$(CONFIG_DMA_ENGINE) += dma/
instead of
obj-$(CONFIG_DMADEVICES) += dma/
diff -r baced9e29ab5 drivers/dma/Makefile
--- a/drivers/dma/MakefileTue Apr 27 20:48:50 2010 +0400
+++ b/drivers/dma/MakefileWed Apr 28 02:00:51 2010 +0400
@@ -10,3 +10,4 @@
obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
obj-$(CONFIG_MX3_IPU) += ipu/
obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
+obj-$(CONFIG_XLLSDMA) += xllsdma.o
diff -r baced9e29ab5 drivers/dma/xllsdma.c
--- /dev/null Thu Jan 01 00:00:00 1970 +
+++ b/drivers/dma/xllsdma.c Wed Apr 28 02:00:51 2010 +0400
@@ -0,0 +1,887 @@
+/*
+ * SDMA subsystem support for Xilinx MPMC.
+ *
+ * Author: Sergey Temerkhanov
+ * Platform Bus by Steven J. Magnani
+ *
+ * Copyright (c) 2008-2010 Cifronic ZAO
+ *
+ * This program is free software; you can redistribute it and/or
modify it + * under the terms of the GNU General Public License as
published by the + * Free Software Foundation; either version 2 of the
License, or (at your + * option) any later version.
+ *
+ */
+
+#include linux/delay.h
+#include linux/kernel.h
+#include linux/init.h
+#include linux/module.h
+#include linux/init.h
+#include linux/errno.h
+#include linux/interrupt.h
+#include linux/mutex.h
+#include linux/wait.h
+#include linux/list.h
+#include linux/io.h
+#include linux/xllsdma.h
+
+#include linux/of_device.h
+#include linux/of_platform.h
+
+#define DRV_VERSION 0.1.0
Irrelevant, can be dropped
+#define DRV_NAME sdma
Used only once, drop.
+
+MODULE_AUTHOR(Sergey Temerkhanov temerkha...@cifronik.ru);
+MODULE_DESCRIPTION(Xilinx SDMA driver);
+MODULE_LICENSE(GPL);
+MODULE_VERSION(DRV_VERSION);
+
+LIST_HEAD(mpmc_devs);
+DEFINE_MUTEX(mpmc_devs_lock);
+
+void xllsdma_tx_irq_enable(struct xllsdma_device *sdma)
+{
+ u32 tx_cr;
+ unsigned long flags;
+
+ BUG_ON(sdma-tx_irq == NO_IRQ);
+
+ spin_lock_irqsave(sdma-lock, flags);
+ tx_cr = xllsdma_tx_in32(sdma, XLLSDMA_CR);
+ xllsdma_tx_out32(sdma, XLLSDMA_CR, tx_cr | XLLSDMA_CR_IRQ_EN);
+ spin_unlock_irqrestore(sdma-lock, flags);
This pattern is used a lot. Might be worth while to implement
xllsdma_tx_* variants of setbits32, clrbits32 and clrsetbits32.
Also, there are a lot of these little functions; really trivial and
small. Would it be better to have them as static inlines in the
header file instead of exported globals?
Well, I can do this but it will require moving of register definitions to
xllsdma.h
+}
+EXPORT_SYMBOL_GPL(xllsdma_tx_irq_enable);
+
+void xllsdma_rx_irq_enable(struct xllsdma_device *sdma)
+{
+ u32 rx_cr;
+ unsigned long flags;
+
+ BUG_ON(sdma-rx_irq == NO_IRQ);
+
+ spin_lock_irqsave(sdma-lock, flags);
+ rx_cr = xllsdma_rx_in32(sdma, XLLSDMA_CR);
+ xllsdma_rx_out32(sdma, XLLSDMA_CR, rx_cr | XLLSDMA_CR_IRQ_EN
Re: [PATCH] [RFC] Xilinx MPMC SDMA subsystem
, Steven J. Magnani I claim this network for MARS! www.digidescorp.com Earthling, return my space modulator! #include standard.disclaimer Regards, Sergey Temerkhanov, Cifronic ZAO. -- Regards, Sergey Temerkhanov, Cifronic ZAO ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCHv2] [RFC] Xilinx MPMC SDMA subsystem
This is the 2nd version of Xilinx MPMC LocalLink SDMA subsystem
Changelog v2:
* Changed the functions and struct definition prefix from sdma_ to xllsdma_
* Platform bus bindings and various changes by Steven J. Magnani.
* Moved source files from arch/powerpc/sysdev to global locations and added
CONFIG_XLLSDMA option.
Regards, Sergey Temerkhanov,
Cifronic ZAO
diff -r baced9e29ab5 drivers/dma/Kconfig
--- a/drivers/dma/Kconfig Tue Apr 27 20:48:50 2010 +0400
+++ b/drivers/dma/Kconfig Wed Apr 28 02:00:51 2010 +0400
@@ -97,6 +97,14 @@
Support the TXx9 SoC internal DMA controller. This can be
integrated in chips such as the Toshiba TX4927/38/39.
+config XLLSDMA
+ bool Xilinx MPMC DMA support
+ depends on XILINX_VIRTEX || MICROBLAZE
+ select DMA_ENGINE
+ help
+ Support fot Xilinx MPMC LocalLink SDMA. Virtex FPGA family
+ has it integrated or fabric-based.
+
config DMA_ENGINE
bool
@@ -133,3 +141,5 @@
DMA Device driver.
endif
+
+
diff -r baced9e29ab5 drivers/dma/Makefile
--- a/drivers/dma/Makefile Tue Apr 27 20:48:50 2010 +0400
+++ b/drivers/dma/Makefile Wed Apr 28 02:00:51 2010 +0400
@@ -10,3 +10,4 @@
obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
obj-$(CONFIG_MX3_IPU) += ipu/
obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
+obj-$(CONFIG_XLLSDMA) += xllsdma.o
diff -r baced9e29ab5 drivers/dma/xllsdma.c
--- /dev/null Thu Jan 01 00:00:00 1970 +
+++ b/drivers/dma/xllsdma.c Wed Apr 28 02:00:51 2010 +0400
@@ -0,0 +1,887 @@
+/*
+ * SDMA subsystem support for Xilinx MPMC.
+ *
+ * Author: Sergey Temerkhanov
+ * Platform Bus by Steven J. Magnani
+ *
+ * Copyright (c) 2008-2010 Cifronic ZAO
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include linux/delay.h
+#include linux/kernel.h
+#include linux/init.h
+#include linux/module.h
+#include linux/init.h
+#include linux/errno.h
+#include linux/interrupt.h
+#include linux/mutex.h
+#include linux/wait.h
+#include linux/list.h
+#include linux/io.h
+#include linux/xllsdma.h
+
+#include linux/of_device.h
+#include linux/of_platform.h
+
+#define DRV_VERSION 0.1.0
+#define DRV_NAME sdma
+
+MODULE_AUTHOR(Sergey Temerkhanov temerkha...@cifronik.ru);
+MODULE_DESCRIPTION(Xilinx SDMA driver);
+MODULE_LICENSE(GPL);
+MODULE_VERSION(DRV_VERSION);
+
+LIST_HEAD(mpmc_devs);
+DEFINE_MUTEX(mpmc_devs_lock);
+
+enum {
+ XLLSDMA_TX_REGS = 0x00, /* TX channel registers beginning */
+ XLLSDMA_RX_REGS = 0x20, /* RX channel registers beginning */
+ XLLSDMA_DMACR = 0x40, /* DMA control register */
+
+ XLLSDMA_NDESCR = 0x00, /* Next descriptor address */
+ XLLSDMA_BUFA = 0x04, /* Current buffer address */
+ XLLSDMA_BUFL = 0x08, /* Current buffer length */
+ XLLSDMA_CDESCR = 0x0C, /* Current descriptor address */
+ XLLSDMA_TDESCR = 0x10, /* Tail descriptor address */
+ XLLSDMA_CR = 0x14, /* Channel control */
+ XLLSDMA_IRQ = 0x18, /* Interrupt register */
+ XLLSDMA_SR = 0x1C, /* Status */
+};
+
+enum {
+ XLLSDMA_CR_IRQ_TIMEOUT_MSK = (0xFF 24), /* Interrupt coalesce timeout */
+ XLLSDMA_CR_IRQ_THRESHOLD_MSK = (0xFF 16), /* Interrupt coalesce count */
+ XLLSDMA_CR_MSB_ADDR_MSK = (0xF 12), /* MSB for 36 bit addressing */
+ XLLSDMA_CR_APP_EN = (1 11), /* Application data mask enable */
+ XLLSDMA_CR_1_BIT_CNT = (1 10), /* All interrupt counters are 1-bit */
+ XLLSDMA_CR_INT_ON_END = (1 9), /* Interrupt-on-end */
+ XLLSDMA_CR_LD_IRQ_CNT = (1 8), /* Load IRQ_COUNT */
+ XLLSDMA_CR_IRQ_EN = (1 7), /* Master interrupt enable */
+ XLLSDMA_CR_IRQ_ERROR = (1 2), /* Error interrupt enable */
+ XLLSDMA_CR_IRQ_TIMEOUT = (1 1), /* Coalesce timeout interrupt enable */
+ XLLSDMA_CR_IRQ_THRESHOLD = (1 0), /* Coalesce threshold interrupt enable */
+
+ XLLSDMA_CR_IRQ_ALL = XLLSDMA_CR_IRQ_EN | XLLSDMA_CR_IRQ_ERROR |
+ XLLSDMA_CR_IRQ_TIMEOUT | XLLSDMA_CR_IRQ_THRESHOLD,
+
+ XLLSDMA_CR_IRQ_TIMEOUT_SH = 24,
+ XLLSDMA_CR_IRQ_THRESHOLD_SH = 16,
+ XLLSDMA_CR_MSB_ADDR_SH = 12,
+
+ XLLSDMA_IRQ_WRQ_EMPTY = (1 14), /* Write Command Queue Empty (rx) */
+ XLLSDMA_IRQ_PLB_RD_ERROR = (1 4), /* PLB Read Error IRQ */
+ XLLSDMA_IRQ_PLB_WR_ERROR = (1 3), /* PLB Write Error IRQ */
+ XLLSDMA_IRQ_ERROR = (1 2), /* Error IRQ */
+ XLLSDMA_IRQ_TIMEOUT = (1 1), /* Coalesce timeout IRQ */
+ XLLSDMA_IRQ_THRESHOLD = (1 0), /* Coalesce threshold IRQ */
+
+ XLLSDMA_IRQ_ALL_ERR = 0x1C, /* All error interrupt */
+ XLLSDMA_IRQ_ALL = 0x1F, /* All interrupt bits */
+ XLLSDMA_IRQ_ALL_DONE = 0x3, /* All work complete interrupt bits */
+
+
+#define XLLSDMA_IRQ_COALESCE_COUNT(x) ((x 10) 0xF)
+#define XLLSDMA_IRQ_DELAY_COUNT(x) ((x 8) 0x3)
+
+ XLLSDMA_SR_ERR_TDESCR = (1 21), /* Tail descriptor pointer is invalid */
+ XLLSDMA_SR_ERR_CMPL = (1 20), /* Complete bit is set */
+ XLLSDMA_SR_ERR_BUFA = (1 19), /* Buffer address is invalid
Re: [PATCH] [RFC] Xilinx MPMC SDMA subsystem
On Monday 29 March 2010 19:56:15 Grant Likely wrote: On Mon, Mar 29, 2010 at 9:42 AM, Steven J. Magnani st...@digidescorp.com wrote: On Fri, 2010-03-26 at 17:53 -0600, Grant Likely wrote: I've not got time to review this patch right now, but Sergey and Steven, you both posted MPMC drivers on the same day; Steven on the microblaze list and Sergey on the powerpc list. Can you two please coordinate and figure out how to mork toward a single driver that will meet both your needs? I don't want to have 2 drivers (3 if you count the ll_temac driver) in mainline for the same hardware interface. I don't think we'll end up with a single driver. A MPMC DMA Engine driver is useful only on loopback SDMA ports. Sergey's code looks like a nice generic interface to Xilinx SDMA HW that could be used by the xlldma and ll_temac drivers, for instance. Both of those will get smaller, but won't go away. Yes, it's like having IBM EMAC driver and MAL layer or something For this to be useful to me, it would need to be located somewhere more accessible than arch/powerpc and it would need to have initialization methods that don't depend on OF. In my build I would have platform code that binds to the xlldma platform attachment, which would call Sergey's SDMA code to assign it the proper resources. That should be fine. Well, I'll look at my old code for the platform interface bindings. I remember it worked well on arch/ppc with my other drivers. Any objections to having Sergey's code live in drivers/dma, and putting sdma.h out in include/linux? Might need to tweak the file/function names some to head off namespace issues. Or is there some other strategy for managing Xilinx-related drivers common to both Microblaze and PowerPC? I have no objections. This sounds like a good plan. Or we can put Xilinx-related headers to, i.e., include/linux/xilinx. There might be some other candidates for this. g. Regards, Sergey Temerkhanov, Cifronic ZAO ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] [RFC] Xilinx Virtex 4 FX Soft FPU support
This patch enables support for Xilinx Virtex 4 FX singe-float FPU. Caveats: - Hard-float binaries which rely on in-kernel math emulation will give wrong results since they expect 64-bit double-precision instead of 32-bit single- precision numbers. Regards, Sergey Temerkhanov ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] [RFC] Xilinx Virtex 4 FX Soft FPU support
The patch. Regards, Resgey Temerkhanov diff -r 9d9ac97e095d .config --- a/.config Thu Feb 25 21:23:42 2010 +0300 +++ b/.config Thu Feb 25 21:49:02 2010 +0300 @@ -14,10 +14,12 @@ CONFIG_40x=y # CONFIG_44x is not set # CONFIG_E200 is not set +CONFIG_PPC_FPU=y CONFIG_4xx=y CONFIG_PPC_MMU_NOHASH=y # CONFIG_PPC_MM_SLICES is not set CONFIG_NOT_COHERENT_CACHE=y +CONFIG_XILINX_FPU=y CONFIG_PPC32=y CONFIG_WORD_SIZE=32 # CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set @@ -227,7 +229,7 @@ CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y # CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set -CONFIG_MATH_EMULATION=y +# CONFIG_MATH_EMULATION is not set # CONFIG_IOMMU_HELPER is not set # CONFIG_SWIOTLB is not set CONFIG_PPC_NEED_DMA_SYNC_OPS=y diff -r 9d9ac97e095d arch/powerpc/include/asm/ppc_asm.h --- a/arch/powerpc/include/asm/ppc_asm.h Thu Feb 25 21:23:42 2010 +0300 +++ b/arch/powerpc/include/asm/ppc_asm.h Thu Feb 25 21:49:02 2010 +0300 @@ -85,13 +85,23 @@ #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) -#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) + +#ifdef CONFIG_XILINX_FPU +#define stfr stfs +#define lfr lfs +#else +#define stfr stfd +#define lfr lfd +#endif + + +#define SAVE_FPR(n, base) stfr n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) -#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) +#define REST_FPR(n, base) lfr n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) diff -r 9d9ac97e095d arch/powerpc/kernel/fpu.S --- a/arch/powerpc/kernel/fpu.S Thu Feb 25 21:23:42 2010 +0300 +++ b/arch/powerpc/kernel/fpu.S Thu Feb 25 21:49:02 2010 +0300 @@ -57,6 +57,9 @@ _GLOBAL(load_up_fpu) mfmsr r5 ori r5,r5,MSR_FP +#ifdef CONFIG_XILINX_FPU + oris r5,r5,msr_...@h +#endif #ifdef CONFIG_VSX BEGIN_FTR_SECTION oris r5,r5,msr_...@h @@ -85,6 +88,9 @@ toreal(r5) PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) li r10,MSR_FP|MSR_FE0|MSR_FE1 +#ifdef CONFIG_XILINX_FPU + oris r10,r10,msr_...@h +#endif andc r4,r4,r10 /* disable FP for previous task */ PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5) 1: @@ -94,6 +100,9 @@ mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ lwz r4,THREAD_FPEXC_MODE(r5) ori r9,r9,MSR_FP /* enable FP for current */ +#ifdef CONFIG_XILINX_FPU + oris r9,r9,msr_...@h +#endif or r9,r9,r4 #else ld r4,PACACURRENT(r13) @@ -124,6 +133,9 @@ _GLOBAL(giveup_fpu) mfmsr r5 ori r5,r5,MSR_FP +#ifdef CONFIG_XILINX_FPU + oris r5,r5,msr_...@h +#endif #ifdef CONFIG_VSX BEGIN_FTR_SECTION oris r5,r5,msr_...@h @@ -145,6 +157,9 @@ beq 1f PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5) li r3,MSR_FP|MSR_FE0|MSR_FE1 +#ifdef CONFIG_XILINX_FPU + oris r3,r3,msr_...@h +#endif #ifdef CONFIG_VSX BEGIN_FTR_SECTION oris r3,r3,msr_...@h diff -r 9d9ac97e095d arch/powerpc/kernel/head_40x.S --- a/arch/powerpc/kernel/head_40x.S Thu Feb 25 21:23:42 2010 +0300 +++ b/arch/powerpc/kernel/head_40x.S Thu Feb 25 21:49:02 2010 +0300 @@ -420,7 +420,19 @@ addi r3,r1,STACK_FRAME_OVERHEAD EXC_XFER_STD(0x700, program_check_exception) +/* 0x0800 - FPU unavailable Exception */ +#ifdef CONFIG_PPC_FPU + START_EXCEPTION(0x0800, FloatingPointUnavailable) + NORMAL_EXCEPTION_PROLOG + beq 1f; \ + bl load_up_fpu; /* if from user, just load it up */ \ + b fast_exception_return; \ +1: addi r3,r1,STACK_FRAME_OVERHEAD; \ + EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception) +#else EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_EE) +#endif + EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_EE) EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_EE) EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_EE) @@ -432,7 +444,7 @@ EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_EE) EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_EE) - EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_EE) + EXCEPTION(0x0F20, Trap_0F, unknown_exception, EXC_XFER_EE) /* 0x1000 - Programmable Interval Timer (PIT) Exception */ START_EXCEPTION(0x1000, Decrementer) @@ -821,8 +833,10 @@ * The PowerPC 4xx family of processors do not have an FPU, so this just * returns. */ +#ifndef CONFIG_PPC_FPU _ENTRY(giveup_fpu) blr +#endif /* This is where the main kernel code starts. */ diff -r 9d9ac97e095d arch/powerpc/platforms/Kconfig.cputype --- a/arch/powerpc/platforms/Kconfig.cputype
[PATCH] [RFC] Xilinx MPMC SDMA subsystem
This patch adds generic support for Xilinx MPMC SoftDMA channels which are
used by, e.g., LLTEMAC and other IP cores (including custom cores). So, the
implemented functions include only SDMA channels enumeration and control
(finding device by phandle property, channel reset, initialization of RX/TX
links, enabling/disabling IRQs, IRQ coalescing control and submission of
descriptors (struct sdma_desc).
The users of this subsystem are supposed to get the pointer to the struct
sdma_device by phandle (using sdma_find_device() function), fill the struct
sdma_client with pointers to the callback functions which are called on rx/tx
completion, on error, and when sdma_reset is called by any client and then
register the client with add_client() (sdma_del_client can be used to
unregister the struct sdma_client)
Also, some auxiliary functions are provided to check the status of descriptors
(busy, done, start of packet, end of packet).
The user is also responsible for maintenance of linked descriptors queue,
proper initialization of their fields, and submission of the descriptors list
to SDMA channel. IRQ acknowledge must be performed by user too (calling
sdma_[rx|tx]_irq_ack respectively in [rx|tx]_complete callbacks). Also on RX
side user must check the __be32 user[4] fields of descriptors to get the
information supplied by SDMA channel.
This code uses SDMA channels in Tail pointer fashion, i.e. the call to
sdma_[rx|tx]_init is performed only once after reset and then only sdma_[rx|
tx]_submit calls are used to update the pointer to the last descriptor in SDMA
channel.
Simple bus driver for MPMC is also added by this patch.
This code is in production use with our internal LLTEMAC driver implementation
since 2008 and with a few custom cores drivers since 2009.
This code currently supports only soft MPMCs, i.e., only SDMA channels with
memory-mapped registers. In order to support channels with DCR, a few
modifications are needed.
Any comments and suggestions are appreciated.
Regards, Sergey Temerkhanov, Cifronic ZAO
* * *
* * *
diff --git a/arch/powerpc/include/asm/sdma.h b/arch/powerpc/include/asm/sdma.h
new file mode 100644
--- /dev/null
+++ b/arch/powerpc/include/asm/sdma.h
@@ -0,0 +1,173 @@
+#ifndef __SDMA_H__
+#define __SDMA_H__
+
+/*
+ * SDMA subsystem support for Xilinx MPMC.
+ *
+ * Author: Sergey Temerkhanov
+ *
+ * Copyright (c) 2008-2010 Cifronic ZAO
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include linux/types.h
+#include linux/dma-mapping.h
+#include asm/dcr.h
+
+#define SDMA_ALIGNMENT 0x40
+
+struct sdma_desc {
+ __be32 next;
+ __be32 address;
+ __be32 length;
+ __be32 stat_ctl;
+ __be32 user[4];
+ void *virt;
+ u32 flags;
+} __attribute__((aligned(SDMA_ALIGNMENT)));
+
+
+enum {
+ SDMA_STSCTL_ERROR = (1 31), /* DMA error */
+ SDMA_STSCTL_IOE = (1 30), /* Interrupt on end */
+ SDMA_STSCTL_SOE = (1 29), /* Stop on end */
+ SDMA_STSCTL_DONE = (1 28), /* DMA completed */
+ SDMA_STSCTL_SOP = (1 27), /* Start of packet */
+ SDMA_STSCTL_EOP = (1 26), /* End of packet */
+ SDMA_STSCTL_BUSY = (1 25), /* DMA busy */
+ SDMA_STSCTL_CSUM = (1 0), /* Checksum enable */
+
+ SDMA_STSCTL_MSK = (0xFF 24), /*Status/control field */
+};
+
+/* SDMA client operations */
+struct sdma_client {
+ void *data;
+ void (*tx_complete) (void *data);
+ void (*rx_complete) (void *data);
+ void (*error) (void *data);
+ void (*reset) (void *data);
+ struct list_head item;
+};
+
+struct sdma_coalesce {
+ int tx_threshold;
+ int tx_timeout;
+
+ int rx_threshold;
+ int rx_timeout;
+};
+
+#define DEFINE_SDMA_COALESCE(x) struct sdma_coalesce x = { \
+ .tx_timeout = 0, \
+ .tx_threshold = 1, \
+ .rx_timeout = 0, \
+ .rx_threshold = 1, };
+
+struct mpmc_device {
+ void __iomem *ioaddr;
+
+ struct resource memregion;
+ int irq;
+
+ int registered;
+ struct list_head item;
+
+ struct mutex devs_lock;
+ struct list_head sdma_devs;
+};
+
+struct sdma_device {
+ void __iomem *ioaddr;
+ wait_queue_head_t wait;
+
+ spinlock_t lock;
+
+ dcr_host_t dcr_host;
+
+ struct resource memregion;
+ int rx_irq;
+ int tx_irq;
+ int rx_ack;
+ int tx_ack;
+ int phandle;
+
+ int registered;
+ struct mpmc_device *parent;
+
+ struct sdma_coalesce coal;
+ struct list_head item;
+
+ struct mutex clients_lock;
+ struct list_head clients;
+};
+
+static inline void sdma_add_client(struct sdma_device *sdma, struct sdma_client *client)
+{
+ mutex_lock(sdma-clients_lock);
+ list_add(client-item, sdma-clients);
+ mutex_unlock(sdma-clients_lock);
+}
+
+static inline void sdma_del_client(struct sdma_device *sdma, struct sdma_client *client)
+{
+ mutex_lock(sdma-clients_lock);
+ list_del(client-item);
+ mutex_unlock(sdma-clients_lock);
+}
+
+struct sdma_device
Re: DMA to User-Space
On Wednesday 04 November 2009 02:37:38 Jonathan Haws wrote: All, I have what may be an unconventional question: Our application consists of data being captured by an FPGA, processed, and transferred to SDRAM. I simply give the FPGA an address of where I want it stored in SDRAM and it simply DMAs the data over and interrupts me when finished. I then take that data and store it to disk. I have code in user space that handles all of the writing to disk nicely and fast enough for my application (I am capturing data at about 35-40 Mbytes/sec). My question is this: is it possible to give a user-space pointer to the FPGA to DMA to? It seems like I would have problems with alignment, address manipulation, and a whole slew of other issues. Well, it's possible: you'll have to use zero-copy I/O. Here's an article on this subject: http://lwn.net/Articles/28548/. Have a look at drivers/scsi/st.c at sgl_get_user_pages() or drivers/infiniband/hw/ipath/ipath_user_pages.c for example of how to use that. Regards, Sergey Temerkhanov. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] [RFC] Fix level IRQ handling on Xilinx INTC with ARCH=powerpc
This fixes the missing acknowledge at the end of handle_level_irq().
It adds a field flags to struct irq_chip. If IRQ_CHIP_UNMASK_ACK is set in
this field, acknowledge is performed before unmasking.
diff -r 6b0915754563 arch/powerpc/sysdev/xilinx_intc.c
--- a/arch/powerpc/sysdev/xilinx_intc.c Mon Jul 28 19:59:22 2008 +0400
+++ b/arch/powerpc/sysdev/xilinx_intc.c Fri Aug 08 13:13:52 2008 +0400
@@ -73,6 +73,7 @@
.mask = xilinx_intc_mask,
.unmask = xilinx_intc_unmask,
.ack = xilinx_intc_ack,
+ .flags = IRQ_CHIP_UNMASK_ACK,
};
/*
@@ -107,8 +108,8 @@
}
regs = ioremap(res.start, 32);
- printk(KERN_INFO Xilinx intc at 0x%08LX mapped to 0x%p\n,
- res.start, regs);
+ printk(KERN_INFO Xilinx intc at 0x%p mapped to 0x%p\n,
+ (void *)res.start, regs);
/* Setup interrupt controller */
out_be32(regs + XINTC_IER, 0); /* disable all irqs */
diff -r 6b0915754563 include/linux/irq.h
--- a/include/linux/irq.h Mon Jul 28 19:59:22 2008 +0400
+++ b/include/linux/irq.h Fri Aug 08 13:13:52 2008 +0400
@@ -114,6 +114,9 @@
int (*retrigger)(unsigned int irq);
int (*set_type)(unsigned int irq, unsigned int flow_type);
int (*set_wake)(unsigned int irq, unsigned int on);
+
+ unsigned int flags;
+#define IRQ_CHIP_UNMASK_ACK 0x0001
/* Currently used only by UML, might disappear one day.*/
#ifdef CONFIG_IRQ_RELEASE_METHOD
diff -r 6b0915754563 kernel/irq/chip.c
--- a/kernel/irq/chip.c Mon Jul 28 19:59:22 2008 +0400
+++ b/kernel/irq/chip.c Fri Aug 08 13:13:52 2008 +0400
@@ -377,8 +377,12 @@
spin_lock(desc-lock);
desc-status = ~IRQ_INPROGRESS;
- if (!(desc-status IRQ_DISABLED) desc-chip-unmask)
- desc-chip-unmask(irq);
+ if (!(desc-status IRQ_DISABLED)) {
+ if (desc-chip-flags IRQ_CHIP_UNMASK_ACK)
+ desc-chip-ack(irq);
+ if (desc-chip-unmask)
+ desc-chip-unmask(irq);
+ }
out_unlock:
spin_unlock(desc-lock);
}
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Re: [PATCH] [RFC] Fix level IRQ handling on Xilinx INTC with ARCH=powerpc
On Monday 25 August 2008 18:26:54 Grant Likely wrote: This patch unconditionally adds what is essentially a device specific fixup to *every* Linux platform. I cannot see that flying very far. I know that. But without IRQ_CHIP_UNMASK_ACK set this fixup won'be applied so setups that are not affected should work as before. This problem was already discussed before: http://www.nabble.com/Level-IRQ-handling-on-Xilinx-INTC-with-ARCH%3Dpowerpc-td18711173.html Of course, I can just modify xilinx_intc_unmask() routine to perform acknowledge as I did before, but it seems a hack to me. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH] Re: Level IRQ handling on Xilinx INTC with ARCH=powerpc
I've prepared the patch to fix the problem being discussed. It adds a field
flags to struct irq_chip. If IRQ_CHIP_UNMASK_ACK is set in this field,
acknowledge is performed before unmasking.
The patch is against 2.6.26
diff -r 6b0915754563 arch/powerpc/sysdev/xilinx_intc.c
--- a/arch/powerpc/sysdev/xilinx_intc.c Mon Jul 28 19:59:22 2008 +0400
+++ b/arch/powerpc/sysdev/xilinx_intc.c Fri Aug 08 13:13:52 2008 +0400
@@ -73,6 +73,7 @@
.mask = xilinx_intc_mask,
.unmask = xilinx_intc_unmask,
.ack = xilinx_intc_ack,
+ .flags = IRQ_CHIP_UNMASK_ACK,
};
/*
@@ -107,8 +108,8 @@
}
regs = ioremap(res.start, 32);
- printk(KERN_INFO Xilinx intc at 0x%08LX mapped to 0x%p\n,
- res.start, regs);
+ printk(KERN_INFO Xilinx intc at 0x%p mapped to 0x%p\n,
+ (void *)res.start, regs);
/* Setup interrupt controller */
out_be32(regs + XINTC_IER, 0); /* disable all irqs */
diff -r 6b0915754563 include/linux/irq.h
--- a/include/linux/irq.h Mon Jul 28 19:59:22 2008 +0400
+++ b/include/linux/irq.h Fri Aug 08 13:13:52 2008 +0400
@@ -114,6 +114,9 @@
int (*retrigger)(unsigned int irq);
int (*set_type)(unsigned int irq, unsigned int flow_type);
int (*set_wake)(unsigned int irq, unsigned int on);
+
+ unsigned int flags;
+#define IRQ_CHIP_UNMASK_ACK 0x0001
/* Currently used only by UML, might disappear one day.*/
#ifdef CONFIG_IRQ_RELEASE_METHOD
diff -r 6b0915754563 kernel/irq/chip.c
--- a/kernel/irq/chip.c Mon Jul 28 19:59:22 2008 +0400
+++ b/kernel/irq/chip.c Fri Aug 08 13:13:52 2008 +0400
@@ -377,8 +377,12 @@
spin_lock(desc-lock);
desc-status = ~IRQ_INPROGRESS;
- if (!(desc-status IRQ_DISABLED) desc-chip-unmask)
- desc-chip-unmask(irq);
+ if (!(desc-status IRQ_DISABLED)) {
+ if (desc-chip-flags IRQ_CHIP_UNMASK_ACK)
+ desc-chip-ack(irq);
+ if (desc-chip-unmask)
+ desc-chip-unmask(irq);
+ }
out_unlock:
spin_unlock(desc-lock);
}
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Level IRQ handling on Xilinx INTC with ARCH=powerpc
Hi, all! I'm currently in process of development of Xilinx I2C IP core driver and I've run into the problem: the ISR for level-based IRQ is called twice. It looks like level IRQ handling on Xilinx INTC with ARCH=powerpc is currently broken as Xilinx INTC requires IRQ acknowledge with IRQ signal deasserted (i.e. after ISR call). ISR is supposed to acknowledge level IRQ in the core which asserted it thus deasserting appropriate IRQ signal. And handle_level_irq() which is currently used as high-level IRQ handler for Xilinx INTC only tries to acknowledge IRQ before ISR call. So that the IRQ remains asserted in INTC and after the call to desc-chip-unmask() causes spurious attempt to process the same IRQ again. However, call to desc-chip-ack() this time finishes the required procedure of IRQ acknowledge. I see a few ways to resolve this: 1. Change high-level handler to __do_IRQ() (as for ARCH=ppc) with proper methods modification (which is deprecated). 2. Change handle_level_irq() so that it calls desc-chip-ack() or desc-chip-end() (and set chip-end to point to xilinx_intc_ack() for Xilinx INTC) before desc-chip-unmask() (may potentially cause breakage for other arches. But I've tried it and it works). 3. Acknowledge IRQ at INTC in ISR (quick'n'dirty hack). Regards, Sergey Temerkhanov ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: May I ask some questions?
vencent2006 wrote: I am Michael from China.A few days ago, I was supposed to debug executable.elf with xmd while some problems happened.It said like that: xmd% dow executable.elf Failed to download ELF file ERROR(1053):UNABLE TO READ ELF FILE.THE ELF FILE MAYBE CORRUPTED :executable.elf You need to install updates for EDK. xmd 9.1 without updates is known to have broken ELF loader I wanna ask u to point out what causes this problem. There is another question about xparameters.h and xparameters_ml300.h. When I have generated BSP, there are two xparameters.h files in project which have the same name while different size(eg: one is 22k ,the other is 4k). Which one is the proper? And when I add xparameters.h and xparameters_ml300.h to the kernel, some compiling error occurs. eg: arch/ppc/syslib/virtex_devices.c:116: error: 'XPAR_UARTNS550_0_CLOCK_FREQ_HZ' undeclared here (not in a function) arch/ppc/syslib/virtex_devices.c:119: error: 'XPAR_UARTNS550_1_CLOCK_FREQ_HZ' undeclared here (not in a function) I don't understand where to define them and whether i need them or not. my eldk is:eldk/4.2/ppc-linux-x86 using Xilinx EDK/ISE 9.1 Linux 2.6.24 These macros must be defined in xparameters_ml300.h. You need them as they define base frequency for UARTNS550 and proper configuration of baud rates depends on it -- ?? http://popme.163.com/link/004304_0515_8953.html ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
