Re: Latest GCC/GLIBC working combo for a Linux 2.4.x kernel?
In message <[EMAIL PROTECTED]> you wrote: > > Does anybody have any working version using newer versions of the 2.4 kernel > and newer GCC versions for a powerpc-603e target? One motivation is to use > BusyBox-1.5.1, but I am told on that list that GCC 2/x is too old (I tried > before I asked, it doesn't compile). Did you have a look at the ELDK? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [EMAIL PROTECTED] There are bugs and then there are bugs. And then there are bugs. - Karl Lehenbauer ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
taiga/7448 questions
OK, I built 2.6.20.11 and 2.6.21.1 for taiga...with the supplied config (and I didn't know about the dtc for powerpc until I booted and nothing happened). I changed a few things (like /proc/config.gz) A few issues I've seen: 1) after we start booting, the console turns off until the login message appears: taiga login: [0.00] Zone PFN ranges: 00] Normal 131072 -> 131072 [0.00] early_node_map[1] active PFN ranges [0.00] 0:0 -> 131072 [0.00] Built 1 zonelists. Total pages: 130048 [0.00] Kernel command line: root=/dev/sda2 console=ttyS0,11520 [0.00] mpic: Setting up MPIC "Tsi108_PIC" version 1.2 at c0007400, max 4 CPUs [0.00] mpic: ISU size: 24, shift: 5, mask: 1f [0.00] mpic: Initializing for 24 sources [0.00] PID hash table entries: 2048 (order: 11, 8192 bytes) Linux System Kernel 2.6.21.1 on an ppc Version: #2 Thu May 24 14:37:53 EDT 2007 This is consistent on 2.6.20.11 and 2.6.21.1... 2) Does "reboot" work? Even when I do a it doesn't want to boot until I do a hardware reset 3) It seems 2.6.21.1 consistently works, 2.6.20.11 sometimes hangs (and since I can't see the console, I don't know what's hanging and why) 4) The dtb strategy seems to a little clumsy...is there a way to embed a default dtc into a kernel (so if you just tftp one file, something happens?) I like the ability to do fewer operations (i.e. initramfs embedded in the image) -- I like reducing steps into of increasing them... Is there a way to tell the kernel "use a default dtb if you don't have one better?" marty ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: [RFC 3/3] Re: [PATCH] mpc52xx_psc_spi: fix it for CONFIG_PPC_MERGE
On 25/05/07 09:34 -0700, David Brownell wrote:
> On Friday 25 May 2007, Domen Puncer wrote:
>
> > For clk.h, it does seem quite some code, compared what's there currently.
>
> You're using it wrong then ...
I meant this + the clock.c part.
>
>
> > --- work-powerpc.git.orig/drivers/spi/mpc52xx_psc_spi.c
> > +++ work-powerpc.git/drivers/spi/mpc52xx_psc_spi.c
> > @@ -18,6 +18,7 @@
> >
> > #if defined(CONFIG_PPC_MERGE)
> > #include
> > +#include
> > #else
> > #include
> > #endif
> > @@ -106,13 +107,52 @@ static void mpc52xx_psc_spi_activate_cs(
> > /* Set clock frequency and bits per word
> > * Because psc->ccr is defined as 16bit register instead of 32bit
> > * just set the lower byte of BitClkDiv
> > +* Because BitClkDiv is 8-bit on mpc5200. Lets stay compatible.
> > */
> > +#if defined(CONFIG_PPC_MERGE)
> > ccr = in_be16(&psc->ccr);
> > ccr &= 0xFF00;
> > + {
> > + u8 bitclkdiv = 2; /* minimum bitclkdiv */
> > + int speed = cs->speed_hz ? cs->speed_hz : 100;
> > + char clk_name[10];
> > + struct clk *clk;// TODO into mps, clk_get, clk_put
> > + int mclk;
> > + int system;
> > + /*
> > +* pscclk = mclk/(bitclkdiv+1)) bitclkdiv is 8-bit, >= 2
> > +* mclk = fsys/(mclkdiv+1) mclkdiv is 9-bit, >= 1
> > +* as mclkdiv has higher precision, we want is as big as
> > possible
> > +* => we get < 0.002*clock error
> > +*/
> > +
> > + snprintf(clk_name, 10, "psc%i_mclk", spi->master->bus_num);
> > +
> > + clk = clk_get(&spi->dev, clk_name);
>
> Don't expect spi->dev to have a clock. Instead, the host controller
> has a clock, which would be looked up the probe() routine, then released
> in remove(): clock = clk_get(dev, "clockname"), with the clock framework
> using "dev" to identify which clock it returns. (That is, the function
> clock for all SPI controllers would have the same name ... not for
> example "spi1_fclk", "spi2_fclk", etc. but instead "spi_fclk".)
Aha, so that's what struct dev* is for. :-)
Now I see two options:
- create something like at91_clock_associate(), and call it from
_probe (of_devices are created automatically from device tree,
so we can't call it the way at91_clock_associate is).
- in clk_get() call dev_get_drvdata(dev), cast it to spi_master *,
_hope_ it really is that, use bus_id.
Sure there must be a third, right one?
Domen
>
>
> > + if (!clk)
> > + dev_err(&spi->dev, "couldn't get %s clock\n", clk_name);
> > +
> > + system = clk_get_rate(clk_get_parent(clk)); // TODO,
> > checking, refcounting
> > + mclk = speed * (bitclkdiv+1);
> > + if (system/mclk > 512) { /* bigger than mclkdiv */
> > + bitclkdiv = system/512/speed;
> > + mclk = speed * (bitclkdiv+1);
> > + }
> > +
> > + if (clk_set_rate(clk, mclk))
> > + dev_err(&spi->dev, "couldn't set %s's rate\n",
> > clk_name);
> > +
> > + dev_info(&spi->dev, "clock: wanted: %i, got: %li\n", speed,
> > + clk_round_rate(clk, mclk) / (bitclkdiv+1));
> > +
> > + ccr |= bitclkdiv;
> > + }
> > +#else
> > if (cs->speed_hz)
> > ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
> > else /* by default SPI Clk 1MHz */
> > ccr |= (MCLK / 100 - 1) & 0xFF;
> > +#endif
> > out_be16(&psc->ccr, ccr);
> > mps->bits_per_word = cs->bits_per_word;
> >
> \
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Re: [RFC 1/3] Re: [PATCH] mpc52xx_psc_spi: fix it for CONFIG_PPC_MERGE
On 5/25/07, Sylvain Munaut <[EMAIL PROTECTED]> wrote: > NACK > > Not at all what I meant ... > > We should not modify port config in any automatic way, just let the boot > loader set it up. > If it known not to do it propertly, then in the platform file > (lite5200b, efika, ...) > adjust port config according to what's really on the board. I second that NACK. Drivers must *never* touch port config. g. -- Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd. [EMAIL PROTECTED] (403) 399-0195 ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Advice needed
I'm having a little trouble with memory mapped registers in both a NAND chip and a CPLD on an 8541 design where the kernel is based on linux-2.6.17.11 and mpc85xx_cds_common. The NAND and CPLD are obviously not part of the memory map of the mpc85xx_cds_common, and in our case are at local memory addresses NAND=0xFF008000, 32K and CPLD=0xFF00, 32K. Both need to be mapped into memory in Linux. I am looking at arch/ppc/platforms/85xx/mpc85xx_cds_common.c around platform_init. I wonder if a Freescale person could give me an opinion of where the appropriate place is to call settlbcam to allow access to these two 32K memory regions? Charles Krinke ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: [RFC 3/3] Re: [PATCH] mpc52xx_psc_spi: fix it for CONFIG_PPC_MERGE
On Friday 25 May 2007, Domen Puncer wrote:
> For clk.h, it does seem quite some code, compared what's there currently.
You're using it wrong then ...
> --- work-powerpc.git.orig/drivers/spi/mpc52xx_psc_spi.c
> +++ work-powerpc.git/drivers/spi/mpc52xx_psc_spi.c
> @@ -18,6 +18,7 @@
>
> #if defined(CONFIG_PPC_MERGE)
> #include
> +#include
> #else
> #include
> #endif
> @@ -106,13 +107,52 @@ static void mpc52xx_psc_spi_activate_cs(
> /* Set clock frequency and bits per word
>* Because psc->ccr is defined as 16bit register instead of 32bit
>* just set the lower byte of BitClkDiv
> + * Because BitClkDiv is 8-bit on mpc5200. Lets stay compatible.
>*/
> +#if defined(CONFIG_PPC_MERGE)
> ccr = in_be16(&psc->ccr);
> ccr &= 0xFF00;
> + {
> + u8 bitclkdiv = 2; /* minimum bitclkdiv */
> + int speed = cs->speed_hz ? cs->speed_hz : 100;
> + char clk_name[10];
> + struct clk *clk;// TODO into mps, clk_get, clk_put
> + int mclk;
> + int system;
> + /*
> + * pscclk = mclk/(bitclkdiv+1)) bitclkdiv is 8-bit, >= 2
> + * mclk = fsys/(mclkdiv+1) mclkdiv is 9-bit, >= 1
> + * as mclkdiv has higher precision, we want is as big as
> possible
> + * => we get < 0.002*clock error
> + */
> +
> + snprintf(clk_name, 10, "psc%i_mclk", spi->master->bus_num);
> +
> + clk = clk_get(&spi->dev, clk_name);
Don't expect spi->dev to have a clock. Instead, the host controller
has a clock, which would be looked up the probe() routine, then released
in remove(): clock = clk_get(dev, "clockname"), with the clock framework
using "dev" to identify which clock it returns. (That is, the function
clock for all SPI controllers would have the same name ... not for
example "spi1_fclk", "spi2_fclk", etc. but instead "spi_fclk".)
> + if (!clk)
> + dev_err(&spi->dev, "couldn't get %s clock\n", clk_name);
> +
> + system = clk_get_rate(clk_get_parent(clk)); // TODO,
> checking, refcounting
> + mclk = speed * (bitclkdiv+1);
> + if (system/mclk > 512) { /* bigger than mclkdiv */
> + bitclkdiv = system/512/speed;
> + mclk = speed * (bitclkdiv+1);
> + }
> +
> + if (clk_set_rate(clk, mclk))
> + dev_err(&spi->dev, "couldn't set %s's rate\n",
> clk_name);
> +
> + dev_info(&spi->dev, "clock: wanted: %i, got: %li\n", speed,
> + clk_round_rate(clk, mclk) / (bitclkdiv+1));
> +
> + ccr |= bitclkdiv;
> + }
> +#else
> if (cs->speed_hz)
> ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
> else /* by default SPI Clk 1MHz */
> ccr |= (MCLK / 100 - 1) & 0xFF;
> +#endif
> out_be16(&psc->ccr, ccr);
> mps->bits_per_word = cs->bits_per_word;
>
\
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Re: zImage.elf loads but does not start
Hi Andrei, Thank you very much for your suggestion. I am very grateful for all of your hints. They were always very valuable to me. I have set as you mentioned: #define XPAR_DDR_0_SIZE 0x200 And now all works fine The root file system is mounted and I can execute whatever I like from the rootfile system. It was just my mistake that I did not noticed the memory size was wrong :( After all of that I would like to use the GPIO driver to talk to the FPGA part of the board. Do you have some experience with that. in my xparameters_ml403.h I have two devices defined: LEDs and SWITCHES as listed below /* Definitions for peripheral LEDS_8BIT */ #define XPAR_LEDS_8BIT_BASEADDR 0x4000 #define XPAR_LEDS_8BIT_HIGHADDR 0x4000 #define XPAR_LEDS_8BIT_DEVICE_ID 0 #define XPAR_LEDS_8BIT_INTERRUPT_PRESENT 0 #define XPAR_LEDS_8BIT_IS_DUAL 0 /* Definitions for peripheral DIP_SWITCHES_8BIT */ #define XPAR_DIP_SWITCHES_8BIT_BASEADDR 0x4002 #define XPAR_DIP_SWITCHES_8BIT_HIGHADDR 0x4002 #define XPAR_DIP_SWITCHES_8BIT_DEVICE_ID 1 #define XPAR_DIP_SWITCHES_8BIT_INTERRUPT_PRESENT 0 #define XPAR_DIP_SWITCHES_8BIT_IS_DUAL 0 #define XPAR_GPIO_0_BASEADDR XPAR_LEDS_8BIT_BASEADDR #define XPAR_GPIO_0_HIGHADDR XPAR_LEDS_8BIT_HIGHADDR #define XPAR_GPIO_0_IS_DUAL XPAR_LEDS_8BIT_IS_DUAL #define XPAR_GPIO_0_DEVICE_ID XPAR_LEDS_8BIT_DEVICE_ID #define XPAR_GPIO_1_BASEADDR XPAR_DIP_SWITCHES_8BIT_BASEADDR #define XPAR_GPIO_1_HIGHADDR XPAR_DIP_SWITCHES_8BIT_HIGHADDR #define XPAR_GPIO_1_IS_DUAL XPAR_DIP_SWITCHES_8BIT_IS_DUAL #define XPAR_GPIO_1_DEVICE_ID XPAR_DIP_SWITCHES_8BIT_DEVICE_ID but I do not know how exactly to talk to them by means of the xgpio driver. Best Regards and many many thanks for your support Mirek Andrei Konovalov wrote: > > Mirek, > > Miroslaw Dach wrote: >> I do not know however if the stack is properly configured since I did not >> see any parameter in kernel which refers to the stack or heap. >> >> My bsp i.e xparameteres_ml403.h contains two macros: >> #define XPAR_DDR_SDRAM_1_MEM0_BASEADDR 0x >> #define XPAR_DDR_SDRAM_1_MEM0_HIGHADDR 0x01FF >> >> I have the feeling that they are ignored because I did not find anywhere >> in the kernel source those names. >> >> When kernel boots it prints at the beginning: >> loaded at: 0040 004F9138 >> board data at: 004F7120 004F7138 >> relocated to: 00404064 0040407C >> zimage at: 00404DF1 004F6BBB >> avail ram: 004FA000 0400 > > Have you fixed this? > > For 32 MBytes of DRAM you should have >#define XPAR_DDR_0_SIZE 0x200 > in your xparameters_ml403.h file. > I can't recall the whole story, but EDK 8.2 doesn't > add this #define when generating the xparameters file, > so I had to add this line by hand for EDK 8.2 generated > files. Probably earlier EDK versions did that automatically. > > But your kernel (the bootwrapper to be precise) wouldn't compile > if XPAR_DDR_0_SIZE were not defined... > Do you use uboot? > > Thanks, > Andrei > > > ___ > Linuxppc-embedded mailing list > Linuxppc-embedded@ozlabs.org > https://ozlabs.org/mailman/listinfo/linuxppc-embedded > > -- View this message in context: http://www.nabble.com/zImage.elf-loads-but-not-starts-tf3607582.html#a10805157 Sent from the linuxppc-embedded mailing list archive at Nabble.com. ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: [RFC 1/3] Re: [PATCH] mpc52xx_psc_spi: fix it for CONFIG_PPC_MERGE
NACK
Not at all what I meant ...
We should not modify port config in any automatic way, just let the boot
loader set it up.
If it known not to do it propertly, then in the platform file
(lite5200b, efika, ...)
adjust port config according to what's really on the board.
Sylvain
Domen Puncer wrote:
> Hi!
>
> I tried to fix these issues, like suggested.
>
> On 16/05/07 10:19 +0200, Sylvain Munaut wrote:
>
>> - Chaning port_config in the driver is just wrong ... you should _not_
>> do that. That should have been setup by the bootloader or at worse in
>> the platform setup code.
>>
>
> [ trimming spi-devel and dbrownell from cc: ]
>
> Setup gpio->port_config to match PSC's set in device tree.
>
> Signed-off-by: Domen Puncer <[EMAIL PROTECTED]>
>
> ---
> arch/powerpc/platforms/52xx/mpc52xx_common.c | 64
> +++
> 1 file changed, 64 insertions(+)
>
> Index: work-powerpc.git/arch/powerpc/platforms/52xx/mpc52xx_common.c
> ===
> --- work-powerpc.git.orig/arch/powerpc/platforms/52xx/mpc52xx_common.c
> +++ work-powerpc.git/arch/powerpc/platforms/52xx/mpc52xx_common.c
> @@ -75,6 +75,68 @@ mpc52xx_find_ipb_freq(struct device_node
> }
> EXPORT_SYMBOL(mpc52xx_find_ipb_freq);
>
> +void __init
> +mpc52xx_setup_port_config(void)
> +{
> + struct mpc52xx_gpio __iomem *gpio;
> + struct device_node *np, *child = NULL;
> + u32 port_config;
> +
> + /* Map zones */
> + gpio = mpc52xx_find_and_map("mpc5200-gpio");
> + if (!gpio) {
> + printk(KERN_ERR __FILE__ ": "
> + "Error while mapping GPIO register for port config. "
> + "Expect some abnormal behavior\n");
> + return;
> + }
> +
> + /* Set port config */
> + port_config = in_be32(&gpio->port_config);
> +
> + np = of_find_node_by_type(NULL, "soc");
> + if (!np) {
> + printk(KERN_ERR "%s: %i can't find node with type 'soc'\n",
> + __func__, __LINE__);
> + iounmap(gpio);
> + return;
> + }
> +
> + while ((child = of_get_next_child(np, child))) {
> + if (of_device_is_compatible(child, "mpc5200-psc")) {
> + int ci = -1;
> + const int *pci;
> +
> + pci = of_get_property(child, "cell-index", NULL);
> + if (pci)
> + ci = *pci;
> + if (ci < 0 || ci > 5 || ci == 3 || ci == 4) {
> + printk(KERN_ALERT "%s: %i psc node '%s' has
> invalid "
> + "cell-index: %i\n", __func__,
> __LINE__,
> + child->name, ci);
> + continue;
> + }
> +
> + port_config &= ~(0x7 << ci*4);
> + if (strcmp(child->name, "ac97") == 0)
> + port_config |= 0x2 << ci*4; /* AC97
> functionality */
> + else if (strcmp(child->name, "serial") == 0)
> + port_config |= 0x5 << ci*4; /* UARTe with
> CD */
> + else if (strcmp(child->name, "spi") == 0)
> + port_config |= 0x7 << ci*4; /* CODEC with
> MCLK */
> + else
> + printk(KERN_ALERT "%s: %i psc node '%s' not
> handled\n",
> + __func__, __LINE__,
> child->name);
> + }
> + }
> + of_node_put(np);
> +
> + pr_debug("port_config: old:%x new:%x\n",
> + in_be32(&gpio->port_config), port_config);
> + out_be32(&gpio->port_config, port_config);
> +
> + iounmap(gpio);
> +}
>
> void __init
> mpc52xx_setup_cpu(void)
> @@ -114,6 +176,8 @@ mpc52xx_setup_cpu(void)
> unmap_regs:
> if (cdm) iounmap(cdm);
> if (xlb) iounmap(xlb);
> +
> + mpc52xx_setup_port_config();
> }
>
> void __init
>
>
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Re: zImage.elf loads but does not start
Mirek, Miroslaw Dach wrote: > I do not know however if the stack is properly configured since I did not > see any parameter in kernel which refers to the stack or heap. > > My bsp i.e xparameteres_ml403.h contains two macros: > #define XPAR_DDR_SDRAM_1_MEM0_BASEADDR 0x > #define XPAR_DDR_SDRAM_1_MEM0_HIGHADDR 0x01FF > > I have the feeling that they are ignored because I did not find anywhere > in the kernel source those names. > > When kernel boots it prints at the beginning: > loaded at: 0040 004F9138 > board data at: 004F7120 004F7138 > relocated to: 00404064 0040407C > zimage at: 00404DF1 004F6BBB > avail ram: 004FA000 0400 Have you fixed this? For 32 MBytes of DRAM you should have #define XPAR_DDR_0_SIZE 0x200 in your xparameters_ml403.h file. I can't recall the whole story, but EDK 8.2 doesn't add this #define when generating the xparameters file, so I had to add this line by hand for EDK 8.2 generated files. Probably earlier EDK versions did that automatically. But your kernel (the bootwrapper to be precise) wouldn't compile if XPAR_DDR_0_SIZE were not defined... Do you use uboot? Thanks, Andrei ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: Latest GCC/GLIBC working combo for a Linux 2.4.x kernel?
Hi, Sasvata! > We are using a RHEL/386 machine to cross-compile for Debian/PowerPC > (8260) target, a few year old embedded system that we inherited. The > kernel is 2.4.9. Using crosstools, and following Dan Kegel's notes, the > combo we have is gcc-2.95-3/glibc-2.2.5. > > Does anybody have any working version using newer versions of the 2.4 > kernel and newer GCC versions for a powerpc-603e target? One motivation > is to use BusyBox-1.5.1, but I am told on that list that GCC 2/x is too > old (I tried before I asked, it doesn't compile). It's propably painful to work your way through crosstools with such an old toolchain. I would have a look if one of the ELDK's from http://www.denx.de can be used for your board - at least for a good start. If you run into problems with older linux-2.4 kernel version with the newer ELDK's, you can also go back to some older version? > Any help, pointers, example config files for crosstools, etc. would be > really appreciated! You are always welcome at their mailing list. See: http://kegel.com/crosstool Best greets, -- Clemens Koller __ R&D Imaging Devices Anagramm GmbH Rupert-Mayer-Straße 45/1 Linhof Werksgelände D-81379 München Tel.089-741518-50 Fax 089-741518-19 http://www.anagramm-technology.com ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: MPC8560 Gianfar driver hangs after soft reboot
Hi, Bill! Bill Farrow schrieb: > The Gianfar driver is hanging during boot-up after a soft reboot. It > works fine when the board is power cycled. > > Any hints on where to look further on this issue? I have had some rare issues with PHY initialization on the PM854 with the u-boot-1.2.0 not being able to download something via TFTP. There is an entry somewhere in the U-Boot wiki (I think) that the TQM8540 board can have some issues... well the boards are quite similar. Pushing the reset button (Never needed to power that off) solves the issue. > 3. After rebooting, the system starts up Linux and it hangs after: > > eth0: Gianfar Ethernet Controller Version 1.2, 00:40:42:01:00:00 > eth0: Running with NAPI enabled > eth0: 256/256 RX/TX BD ring size The Kernels I 've tried (2.6.13 up to 2.6.21-rc5 and some latest gits) never stopped there... I would just try another kernel. Checkout the code in the latest git. > Also tried soft rebooting without the network cable and the kernel boots > without hanging, but the network does not work when the re-connected. > The PHY seems to be working because when we plug the cable back in it > detects the link and writes this console message: > > [ 1557.465085] PHY: 0:01 - Link is Up - 100/Full > > Note that there are two Ethernet controllers on the board (eth0 and > eth1). Only eth1 is connected to the network. What PHY's do you have on these ports? (MV88E over here) > Background info: > Kernel version 2.6.20.4 PPC > Uboot version 1.2.0 > Busybox version 1.5.0 > ELDK: 4.1 > JTAG: BDI-2000 > Board : Microsys PM856 - with MPC8560 processor. Looks good. I am using the PM854. Well, some other thing: I had some instabilities on my prototyping hardware in the beginnging, but I guess due to EMI and the sloppy setup. After I got all the stuff nailed down onto some aluminum-plate, the boards is working _very_ stable (24/7). Greets, -- Clemens Koller __ R&D Imaging Devices Anagramm GmbH Rupert-Mayer-Straße 45/1 Linhof Werksgelände D-81379 München Tel.089-741518-50 Fax 089-741518-19 http://www.anagramm-technology.com ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: zImage.elf loads but does not start
Hi All, I have done more research on the problem with my ml403 board. I use linux 2.6.21rc6 by Grant. I have configured the kernel to mount the rootfile system via NFS. The kernel boots properly up to the point to execute init. My Last observation is as following. I have written my own statically build init just to printf some strings to the screen. The message is printed as expected. The size of my executable is around 520 Kbytes. When I have added more code to have a bigger executable I reached the point when my init was sometimes executed and some times not (ie. the system hanged and ping did not work) . This happens when the executable is around 647 Kbytes large. I have aslo noticed that when the code is bigger than 700 Kbytes the system hangs always. To have more evidence I have compiled klibc rootfile system which is very small but it uses dynamically linked library libc.so which is around 111 Kbytes. In such a case the init was executed fine so it seems to be the problem of the file size the system is going to execute (load via NFS). I suspect that it is the Temac which causes the problem. I do not however know it is possible to adjust some temac parameters like the FIFOs size or so. Maybe it is the Temac driver? It could be also that NFS client server communication which brakes due to unknown reason. My eteral program which I used to monitor the network traffic on the NFS server shows that NFS server works all the time and it sends periodically the packets to the client even if the client hags. Would you have some idea what could be wrong? Best Regards Mirek Mirek23 wrote: > >> Anyway, you could try adding >>nfsroot=,rsize=1024,wsize=1024 >> to your cmdline just in case... > > I have tried that but it did not help :( > > Best Regards > > Mirek > -- View this message in context: http://www.nabble.com/zImage.elf-loads-but-not-starts-tf3607582.html#a10801964 Sent from the linuxppc-embedded mailing list archive at Nabble.com. ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
[RFC 3/3] Re: [PATCH] mpc52xx_psc_spi: fix it for CONFIG_PPC_MERGE
On 16/05/07 10:19 +0200, Sylvain Munaut wrote:
>
> Well, this comment is not about the patch but about the driver it self,
> I didn't see it before today.
> So here's a few things I see from a quick glance at the code :
>
> - Chaning port_config in the driver is just wrong ... you should _not_
> do that. That should have been setup by the bootloader or at worse in
> the platform setup code.
> - You do read/write/modify operation on CDM shared register
> (clk_enables) from a driver, you should have added something in common
> 52xx code to do theses with proper locking.
> - MPC52xx_PA(MPC52xx_PSCx_OFFSET(...)) ??? You should get that from the
> resource of the platform_device. This macro is just there for early
> console stuff.
> - You can get f_system from the device tree instead of just assuming
> it's 512 MHz. It probably need to be done the same way it's done to find
> ipb_freq.
> - Would have been nice to be able to somehow configure MCLK rather than
> #define it
> - I hope to remove all arch/ppc stuff by 2.6.23 if I can make the
> cuimage stuff work in arch/powerpc so just including the platform code
> stuff for 1 kernel version ...
>
>
> Sylvain
[ trimming spi-devel from cc: ]
For clk.h, it does seem quite some code, compared what's there currently.
Comments?
Use previous two patches (port_config, clk.h).
Signed-off-by: Domen Puncer <[EMAIL PROTECTED]>
---
drivers/spi/mpc52xx_psc_spi.c | 49 +-
1 file changed, 44 insertions(+), 5 deletions(-)
Index: work-powerpc.git/drivers/spi/mpc52xx_psc_spi.c
===
--- work-powerpc.git.orig/drivers/spi/mpc52xx_psc_spi.c
+++ work-powerpc.git/drivers/spi/mpc52xx_psc_spi.c
@@ -18,6 +18,7 @@
#if defined(CONFIG_PPC_MERGE)
#include
+#include
#else
#include
#endif
@@ -106,13 +107,52 @@ static void mpc52xx_psc_spi_activate_cs(
/* Set clock frequency and bits per word
* Because psc->ccr is defined as 16bit register instead of 32bit
* just set the lower byte of BitClkDiv
+* Because BitClkDiv is 8-bit on mpc5200. Lets stay compatible.
*/
+#if defined(CONFIG_PPC_MERGE)
ccr = in_be16(&psc->ccr);
ccr &= 0xFF00;
+ {
+ u8 bitclkdiv = 2; /* minimum bitclkdiv */
+ int speed = cs->speed_hz ? cs->speed_hz : 100;
+ char clk_name[10];
+ struct clk *clk;// TODO into mps, clk_get, clk_put
+ int mclk;
+ int system;
+ /*
+* pscclk = mclk/(bitclkdiv+1)) bitclkdiv is 8-bit, >= 2
+* mclk = fsys/(mclkdiv+1) mclkdiv is 9-bit, >= 1
+* as mclkdiv has higher precision, we want is as big as
possible
+* => we get < 0.002*clock error
+*/
+
+ snprintf(clk_name, 10, "psc%i_mclk", spi->master->bus_num);
+
+ clk = clk_get(&spi->dev, clk_name);
+ if (!clk)
+ dev_err(&spi->dev, "couldn't get %s clock\n", clk_name);
+
+ system = clk_get_rate(clk_get_parent(clk)); // TODO,
checking, refcounting
+ mclk = speed * (bitclkdiv+1);
+ if (system/mclk > 512) { /* bigger than mclkdiv */
+ bitclkdiv = system/512/speed;
+ mclk = speed * (bitclkdiv+1);
+ }
+
+ if (clk_set_rate(clk, mclk))
+ dev_err(&spi->dev, "couldn't set %s's rate\n",
clk_name);
+
+ dev_info(&spi->dev, "clock: wanted: %i, got: %li\n", speed,
+ clk_round_rate(clk, mclk) / (bitclkdiv+1));
+
+ ccr |= bitclkdiv;
+ }
+#else
if (cs->speed_hz)
ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
else /* by default SPI Clk 1MHz */
ccr |= (MCLK / 100 - 1) & 0xFF;
+#endif
out_be16(&psc->ccr, ccr);
mps->bits_per_word = cs->bits_per_word;
@@ -328,13 +368,9 @@ static int mpc52xx_psc_spi_port_config(i
u32 mclken_div;
int ret = 0;
-#if defined(CONFIG_PPC_MERGE)
- cdm = mpc52xx_find_and_map("mpc5200-cdm");
- gpio = mpc52xx_find_and_map("mpc5200-gpio");
-#else
+#if !defined(CONFIG_PPC_MERGE)
cdm = ioremap(MPC52xx_PA(MPC52xx_CDM_OFFSET), MPC52xx_CDM_SIZE);
gpio = ioremap(MPC52xx_PA(MPC52xx_GPIO_OFFSET), MPC52xx_GPIO_SIZE);
-#endif
if (!cdm || !gpio) {
printk(KERN_ERR "Error mapping CDM/GPIO\n");
ret = -EFAULT;
@@ -390,6 +426,7 @@ static int mpc52xx_psc_spi_port_config(i
ret = -EINVAL;
goto unmap_regs;
}
+#endif
/* Reset the PSC into a known state */
out_8(&psc->command, MPC52xx_PSC_RST_RX);
@@ -413,11 +450,13 @@ static int mpc52xx_psc_spi_port_config(i
mps->bits_per_word = 8;
+#if !
[RFC 2/3] Re: [PATCH] mpc52xx_psc_spi: fix it for CONFIG_PPC_MERGE
On 16/05/07 10:19 +0200, Sylvain Munaut wrote:
> - You do read/write/modify operation on CDM shared register
> (clk_enables) from a driver, you should have added something in common
> 52xx code to do theses with proper locking.
> - MPC52xx_PA(MPC52xx_PSCx_OFFSET(...)) ??? You should get that from the
> resource of the platform_device. This macro is just there for early
> console stuff.
> - You can get f_system from the device tree instead of just assuming
> it's 512 MHz. It probably need to be done the same way it's done to find
> ipb_freq.
> - Would have been nice to be able to somehow configure MCLK rather than
> #define it
[ trimming spi-devel from cc: ]
Use clk.h interface for mpc52xx.
Parse device tree for Fsystem, or leave it default 528 (yes, not 512).
Currently only psc_mclks are defined.
Signed-off-by: Domen Puncer <[EMAIL PROTECTED]>
---
arch/powerpc/platforms/52xx/Makefile |2
arch/powerpc/platforms/52xx/clock.c | 311 +++
2 files changed, 312 insertions(+), 1 deletion(-)
Index: work-powerpc.git/arch/powerpc/platforms/52xx/Makefile
===
--- work-powerpc.git.orig/arch/powerpc/platforms/52xx/Makefile
+++ work-powerpc.git/arch/powerpc/platforms/52xx/Makefile
@@ -2,7 +2,7 @@
# Makefile for 52xx based boards
#
ifeq ($(CONFIG_PPC_MERGE),y)
-obj-y += mpc52xx_pic.o mpc52xx_common.o
+obj-y += mpc52xx_pic.o mpc52xx_common.o clock.o
obj-$(CONFIG_PCI) += mpc52xx_pci.o
obj-$(CONFIG_PPC_BESTCOMM) += bestcomm.o
obj-$(CONFIG_FEC_MPC52xx) += sdma_fec_rx_task.o sdma_fec_tx_task.o fec.o
Index: work-powerpc.git/arch/powerpc/platforms/52xx/clock.c
===
--- /dev/null
+++ work-powerpc.git/arch/powerpc/platforms/52xx/clock.c
@@ -0,0 +1,311 @@
+/*
+ * arch/powerpc/platforms/52xx/clock.c
+ * based on linux/arch/arm/mach-at91/clock.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+
+struct clk {
+ struct list_head node;
+ const char *name; /* unique clock name */
+ unsigned long rate_hz;
+ struct clk *parent;
+ void(*mode)(struct clk *, int);
+ u16 users;
+ int cdm_id; /* == bit number in datasheet, or 0 */
+ long(*set_rate)(struct clk *, unsigned long rate, int
round_only);
+};
+
+#define CDM_ID_PSC3 24
+#define CDM_ID_PSC2 25
+#define CDM_ID_PSC1 26
+#define CDM_ID_PSC6 27
+
+long psc_set_rate(struct clk *clk, unsigned long rate, int round_only);
+
+static struct clk clk_system = {
+ .name = "system",
+ .rate_hz= 52800,/* default if there's no
system-frequency in dts */
+ .users = 1,/* always on */
+};
+static struct clk clk_psc1 = {
+ .name = "psc1_mclk",
+ .cdm_id = CDM_ID_PSC1,
+ .parent = &clk_system,
+ .set_rate = psc_set_rate,
+};
+static struct clk clk_psc2 = {
+ .name = "psc2_mclk",
+ .cdm_id = CDM_ID_PSC2,
+ .parent = &clk_system,
+ .set_rate = psc_set_rate,
+};
+static struct clk clk_psc3 = {
+ .name = "psc3_mclk",
+ .cdm_id = CDM_ID_PSC3,
+ .parent = &clk_system,
+ .set_rate = psc_set_rate,
+};
+static struct clk clk_psc6 = {
+ .name = "psc6_mclk",
+ .cdm_id = CDM_ID_PSC6,
+ .parent = &clk_system,
+ .set_rate = psc_set_rate,
+};
+
+
+
+static LIST_HEAD(clocks);
+static DEFINE_SPINLOCK(clk_lock);
+
+static struct mpc52xx_cdm __iomem *cdm;
+static DEFINE_SPINLOCK(cdm_lock);
+
+
+long psc_set_rate(struct clk *clk, unsigned long rate, int round_only)
+{
+ u16 mclkdiv;
+ u16 __iomem *divreg;
+
+ /* pick a divider that will get the closest clock */
+ mclkdiv = (clk->parent->rate_hz + rate/2) / rate - 1;
+
+ /* trim to closest possible. or should we return an error? */
+ mclkdiv = min(mclkdiv, (u16)0x1ff);
+ mclkdiv = max(mclkdiv, (u16)1);
+
+ rate = clk->parent->rate_hz / (mclkdiv + 1);
+ mclkdiv |= 0x8000; /* enable (this is not clk_enable!) */
+
+ if (round_only)
+ return rate;
+
+ if (clk->cdm_id == CDM_ID_PSC1)
+ divreg = &cdm->mclken_div_psc1;
+ else if (clk->cdm_id == CDM_ID_PSC2)
+ divreg = &cdm->mclken_div_psc2;
+ else if (clk->cdm_id == CDM_ID_PSC3)
+ divreg = &cdm->mclken_div_psc3;
+ else if (clk->cdm_id == CDM_ID_PSC6)
+ divreg = &cdm->mclken_div_psc6;
+ else
+ return -ENODEV;
+
+ out_be16(divreg, mclkdiv);
+
+ return 0;
+}
+
+/* clocks cannot be de-registered no refcounting necessary */
+struct
[RFC 1/3] Re: [PATCH] mpc52xx_psc_spi: fix it for CONFIG_PPC_MERGE
Hi!
I tried to fix these issues, like suggested.
On 16/05/07 10:19 +0200, Sylvain Munaut wrote:
> - Chaning port_config in the driver is just wrong ... you should _not_
> do that. That should have been setup by the bootloader or at worse in
> the platform setup code.
[ trimming spi-devel and dbrownell from cc: ]
Setup gpio->port_config to match PSC's set in device tree.
Signed-off-by: Domen Puncer <[EMAIL PROTECTED]>
---
arch/powerpc/platforms/52xx/mpc52xx_common.c | 64 +++
1 file changed, 64 insertions(+)
Index: work-powerpc.git/arch/powerpc/platforms/52xx/mpc52xx_common.c
===
--- work-powerpc.git.orig/arch/powerpc/platforms/52xx/mpc52xx_common.c
+++ work-powerpc.git/arch/powerpc/platforms/52xx/mpc52xx_common.c
@@ -75,6 +75,68 @@ mpc52xx_find_ipb_freq(struct device_node
}
EXPORT_SYMBOL(mpc52xx_find_ipb_freq);
+void __init
+mpc52xx_setup_port_config(void)
+{
+ struct mpc52xx_gpio __iomem *gpio;
+ struct device_node *np, *child = NULL;
+ u32 port_config;
+
+ /* Map zones */
+ gpio = mpc52xx_find_and_map("mpc5200-gpio");
+ if (!gpio) {
+ printk(KERN_ERR __FILE__ ": "
+ "Error while mapping GPIO register for port config. "
+ "Expect some abnormal behavior\n");
+ return;
+ }
+
+ /* Set port config */
+ port_config = in_be32(&gpio->port_config);
+
+ np = of_find_node_by_type(NULL, "soc");
+ if (!np) {
+ printk(KERN_ERR "%s: %i can't find node with type 'soc'\n",
+ __func__, __LINE__);
+ iounmap(gpio);
+ return;
+ }
+
+ while ((child = of_get_next_child(np, child))) {
+ if (of_device_is_compatible(child, "mpc5200-psc")) {
+ int ci = -1;
+ const int *pci;
+
+ pci = of_get_property(child, "cell-index", NULL);
+ if (pci)
+ ci = *pci;
+ if (ci < 0 || ci > 5 || ci == 3 || ci == 4) {
+ printk(KERN_ALERT "%s: %i psc node '%s' has
invalid "
+ "cell-index: %i\n", __func__,
__LINE__,
+ child->name, ci);
+ continue;
+ }
+
+ port_config &= ~(0x7 << ci*4);
+ if (strcmp(child->name, "ac97") == 0)
+ port_config |= 0x2 << ci*4; /* AC97
functionality */
+ else if (strcmp(child->name, "serial") == 0)
+ port_config |= 0x5 << ci*4; /* UARTe with
CD */
+ else if (strcmp(child->name, "spi") == 0)
+ port_config |= 0x7 << ci*4; /* CODEC with
MCLK */
+ else
+ printk(KERN_ALERT "%s: %i psc node '%s' not
handled\n",
+ __func__, __LINE__,
child->name);
+ }
+ }
+ of_node_put(np);
+
+ pr_debug("port_config: old:%x new:%x\n",
+in_be32(&gpio->port_config), port_config);
+ out_be32(&gpio->port_config, port_config);
+
+ iounmap(gpio);
+}
void __init
mpc52xx_setup_cpu(void)
@@ -114,6 +176,8 @@ mpc52xx_setup_cpu(void)
unmap_regs:
if (cdm) iounmap(cdm);
if (xlb) iounmap(xlb);
+
+ mpc52xx_setup_port_config();
}
void __init
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RE: console problem while initializing form ramdisk
Hi, did you create a /dev/console device node ? crw--- 1 root tty 5, 1 May 25 07:36 /dev/console Even, if you are working with udev, you have to create this mode manually, because its needed at an early stage of the init process. -- Mit freundlichen Gruessen / Best regards Claus Gindhart Kontron Modular Computers GmbH Sudetenstrasse 7, 87600 Kaufbeuren, Germany Phone: +49 (8341) 803 374 Fax: +49 (8341) 803 40 374 www.kontron.com -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of [EMAIL PROTECTED] Sent: Freitag, 25. Mai 2007 09:05 To: Linuxppc-embedded@ozlabs.org Subject: console problem while initializing form ramdisk Hi,all I am trying to run linux2.6 on Xilinx ML403.I have builded and loaded zImage.initrd.elf successfully into the board and when the kernel was booting to the point initializing form ramdisk,I got the problem as follow. loaded at: 0040 0063213C board data at: 00630124 0063013C relocated to: 004050E8 00405100 zimage at: 004058B9 004C645D initrd at: 004C7000 0062FE44 avail ram: 00633000 0400 Linux/PPC load: console=ttyS0,9600 root=/dev/ram rw Uncompressing Linux...done. Now booting the kernel Linux version 2.6.17-rc4-smp ([EMAIL PROTECTED]) (gcc version 3.3.1 (MontaVista 3 .3.1-3.0.10.0300532 2003-12-24)) #4 Fri May 25 11:29:41 CST 2007 Xilinx ML403 Reference System (Virtex-4 FX) Built 1 zonelists Kernel command line: console=ttyS0,9600 root=/dev/ram rw Xilinx INTC #0 at 0x4120 mapped to 0xFDFFE000 PID hash table entries: 512 (order: 9, 2048 bytes) Console: colour dummy device 80x25 Dentry cache hash table entries: 8192 (order: 3, 32768 bytes) Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) Memory: 61420k available (1240k kernel code, 716k data, 84k init, 0k highmem) Security Framework v1.0.0 initialized Mount-cache hash table entries: 512 checking if image is initramfs...it isn't (no cpio magic); looks like an initrd Freeing initrd memory: 1443k freed VFS: Disk quotas dquot_6.5.1 Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) Initializing Cryptographic API io scheduler noop registered io scheduler anticipatory registered (default) io scheduler deadline registered io scheduler cfq registered Macintosh non-volatile memory driver v1.1 Linux agpgart interface v0.101 (c) Dave Jones Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled serial8250.0: ttyS0 at MMIO 0x40401003 (irq = 1) is a 16450 RAMDISK driver initialized: 1 RAM disks of 8192K size 1024 blocksize loop: loaded (max 8 devices) i8042.c: No controller found. mice: PS/2 mouse device common for all mice md: md driver 0.90.3 MAX_MD_DEVS=256, MD_SB_DISKS=27 md: bitmap version 4.39 md: Autodetecting RAID arrays. md: autorun ... md: ... autorun DONE. RAMDISK: Compressed image found at block 0 VFS: Mounted root (ext2 filesystem). Freeing unused kernel memory: 84k init Warning: unable to open an initial console. I configured bootloader like this: [*]Default bootloader kernel arguments (console=ttyS0,9600 root=dev/ram rw)Initial kernel command string I don't know where the problem comes from and how to solve it. Any help from you is appreciated.Thank you! linyao ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded Kontron Modular Computers GmbH Geschftsfhrer: Ulrich Gehrmann, Thomas Sabisch Sitz der Gesellschaft: Kaufbeuren / Rechtsform: GmbH Amtsgericht Kempten / HRB Nr. 6195 Kontron Modular Computers GmbH Managing Directors: Ulrich Gehrmann, Thomas Sabisch Registered Office: Kaufbeuren, Germany / Legal Form: GmbH Local District Court: Kempten / Trade Register No. 6195
console problem while initializing form ramdisk
Hi,all I am trying to run linux2.6 on Xilinx ML403.I have builded and loaded zImage.initrd.elf successfully into the board and when the kernel was booting to the point initializing form ramdisk,I got the problem as follow. loaded at: 0040 0063213C board data at: 00630124 0063013C relocated to: 004050E8 00405100 zimage at: 004058B9 004C645D initrd at: 004C7000 0062FE44 avail ram: 00633000 0400 Linux/PPC load: console=ttyS0,9600 root=/dev/ram rw Uncompressing Linux...done. Now booting the kernel Linux version 2.6.17-rc4-smp ([EMAIL PROTECTED]) (gcc version 3.3.1 (MontaVista 3 .3.1-3.0.10.0300532 2003-12-24)) #4 Fri May 25 11:29:41 CST 2007 Xilinx ML403 Reference System (Virtex-4 FX) Built 1 zonelists Kernel command line: console=ttyS0,9600 root=/dev/ram rw Xilinx INTC #0 at 0x4120 mapped to 0xFDFFE000 PID hash table entries: 512 (order: 9, 2048 bytes) Console: colour dummy device 80x25 Dentry cache hash table entries: 8192 (order: 3, 32768 bytes) Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) Memory: 61420k available (1240k kernel code, 716k data, 84k init, 0k highmem) Security Framework v1.0.0 initialized Mount-cache hash table entries: 512 checking if image is initramfs...it isn't (no cpio magic); looks like an initrd Freeing initrd memory: 1443k freed VFS: Disk quotas dquot_6.5.1 Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) Initializing Cryptographic API io scheduler noop registered io scheduler anticipatory registered (default) io scheduler deadline registered io scheduler cfq registered Macintosh non-volatile memory driver v1.1 Linux agpgart interface v0.101 (c) Dave Jones Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled serial8250.0: ttyS0 at MMIO 0x40401003 (irq = 1) is a 16450 RAMDISK driver initialized: 1 RAM disks of 8192K size 1024 blocksize loop: loaded (max 8 devices) i8042.c: No controller found. mice: PS/2 mouse device common for all mice md: md driver 0.90.3 MAX_MD_DEVS=256, MD_SB_DISKS=27 md: bitmap version 4.39 md: Autodetecting RAID arrays. md: autorun ... md: ... autorun DONE. RAMDISK: Compressed image found at block 0 VFS: Mounted root (ext2 filesystem). Freeing unused kernel memory: 84k init Warning: unable to open an initial console. I configured bootloader like this: [*]Default bootloader kernel arguments (console=ttyS0,9600 root=dev/ram rw)Initial kernel command string I don't know where the problem comes from and how to solve it. Any help from you is appreciated.Thank you! linyao ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
