Re: [Lldb-commits] [PATCH] D21064: [LLDB][MIPS] Fix Emulation of Compact branch and ADDIU instructions

[Jaydeep Patil via lldb-commits]

jaydeep accepted this revision.
jaydeep added a comment.
This revision is now accepted and ready to land.

Looks good to me.


Repository:
  rL LLVM

http://reviews.llvm.org/D21064



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D20368: Remove Platform usages from NativeProcessLinux

[Jaydeep Patil via lldb-commits]

jaydeep added a comment.





Comment at: source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp:53
@@ -22,2 +52,3 @@
+
 NativeRegisterContextLinux::NativeRegisterContextLinux(NativeThreadProtocol 
&native_thread,
uint32_t 
concrete_frame_idx,

We have tried executing ptrace(NT_PRSTATUS) on MIPS with 3.18. It is able to 
detect the arch correctly (64->64 and 64->32). However with 3.10 it fails with 
EIO. Is there any fallback method when ptrace(NT_PRSTATUS) fails?


http://reviews.llvm.org/D20368



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D17597: [LLDB][MIPS] Fix TestDisassembleBreakpoint

[Jaydeep Patil via lldb-commits]

jaydeep accepted this revision.
jaydeep added a comment.
This revision is now accepted and ready to land.

Looks good to me.


Repository:
  rL LLVM

http://reviews.llvm.org/D17597



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D16840: [LLDB][MIPS] Generalise MIPS arch names

[Jaydeep Patil via lldb-commits]

jaydeep accepted this revision.
jaydeep added a comment.
This revision is now accepted and ready to land.

Looks good to me


Repository:
  rL LLVM

http://reviews.llvm.org/D16840



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D15488: [LLDB][MIPS] Mark TestConcurrentEvents.py expected failure, as MIPS atomic sequences are yet to be supported in LLDB

[Jaydeep Patil via lldb-commits]

jaydeep accepted this revision.
jaydeep added a comment.
This revision is now accepted and ready to land.

Looks good to me.


Repository:
  rL LLVM

http://reviews.llvm.org/D15488



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D15487: [LLDB][MIPS] Added support for MIPS1, MIPS2, MIPS3, MIPS4 and MIPS5 instruction sets

[Jaydeep Patil via lldb-commits]

jaydeep accepted this revision.
jaydeep added a comment.
This revision is now accepted and ready to land.

Looks good to me.


Repository:
  rL LLVM

http://reviews.llvm.org/D15487



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D15182: [MIPS] Fix TestCrashDuringStep.py for MIPS

[Jaydeep Patil via lldb-commits]

jaydeep closed this revision.
jaydeep added a comment.

Closed by commit http://reviews.llvm.org/rL254710


Repository:
  rL LLVM

http://reviews.llvm.org/D15182



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r254710 - [LLDB][MIPS] XFAIL TestCrashDuringStep.py for MIPS

[Jaydeep Patil via lldb-commits]

Author: jaydeep
Date: Fri Dec  4 03:56:36 2015
New Revision: 254710

URL: http://llvm.org/viewvc/llvm-project?rev=254710&view=rev
Log:
[LLDB][MIPS] XFAIL TestCrashDuringStep.py for MIPS
SUMMARY:
Marked TestCrashDuringStep.py as XFAIL for MIPS. The test generates IO 
error due to breakpoint at invalid address.

Reviewers: clayborg, labath
Subscribers: nitesh.jain, mohit.bhakkad, sagar, bhushan and lldb-commits
Differential Revision: http://reviews.llvm.org/D15182

Modified:

lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py?rev=254710&r1=254709&r2=254710&view=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py
 Fri Dec  4 03:56:36 2015
@@ -21,6 +21,7 @@ class CreateDuringStepTestCase(TestBase)
 
 @expectedFailureWindows("llvm.org/pr24778")
 @expectedFailureAndroid("llvm.org/pr24497", archs=['arm', 'aarch64'])
+@expectedFailureAll(archs=['mips', 'mipsel', 'mips64', 'mips64el'])# 
IO error due to breakpoint at invalid address
 def test_step_inst_with(self):
 """Test thread creation during step-inst handling."""
 self.build(dictionary=self.getBuildFlags())


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D15182: [MIPS] Fix TestCrashDuringStep.py for MIPS

[Jaydeep Patil via lldb-commits]

jaydeep updated this revision to Diff 41840.
jaydeep added a comment.

Marked as XFAIL


Repository:
  rL LLVM

http://reviews.llvm.org/D15182

Files:
  
packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py

Index: 
packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py
===
--- 
packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py
+++ 
packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py
@@ -21,6 +21,7 @@
 
 @expectedFailureWindows("llvm.org/pr24778")
 @expectedFailureAndroid("llvm.org/pr24497", archs=['arm', 'aarch64'])
+@expectedFailureAll(archs=['mips', 'mipsel', 'mips64', 'mips64el'])# 
IO error due to breakpoint at invalid address
 def test_step_inst_with(self):
 """Test thread creation during step-inst handling."""
 self.build(dictionary=self.getBuildFlags())


Index: packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py
===
--- packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py
+++ packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py
@@ -21,6 +21,7 @@
 
 @expectedFailureWindows("llvm.org/pr24778")
 @expectedFailureAndroid("llvm.org/pr24497", archs=['arm', 'aarch64'])
+@expectedFailureAll(archs=['mips', 'mipsel', 'mips64', 'mips64el'])# IO error due to breakpoint at invalid address
 def test_step_inst_with(self):
 """Test thread creation during step-inst handling."""
 self.build(dictionary=self.getBuildFlags())
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [PATCH] D15182: [MIPS] Fix TestCrashDuringStep.py for MIPS

[Jaydeep Patil via lldb-commits]

jaydeep created this revision.
jaydeep added a reviewer: clayborg.
jaydeep added subscribers: bhushan, sagar, mohit.bhakkad, nitesh.jain, 
lldb-commits.
jaydeep set the repository for this revision to rL LLVM.

Single stepping requires setting software breakpoint at address 0x0. This 
results in input/output error instead of SIGSEGV. Using “continue” instead of 
single stepping avoids setting of software breakpoint at address 0x0.


Repository:
  rL LLVM

http://reviews.llvm.org/D15182

Files:
  
packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py

Index: 
packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py
===
--- 
packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py
+++ 
packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py
@@ -43,9 +43,16 @@
 thread = process.GetThreadAtIndex(0)
 self.assertTrue(thread and thread.IsValid(), "Thread is valid")
 
-# Keep stepping until the inferior crashes
-while process.GetState() == lldb.eStateStopped and not 
lldbutil.is_thread_crashed(self, thread):
-thread.StepInstruction(False)
+# Single stepping requires setting software breakpoint at address 0x0. 
+# This results in input/output error instead of SIGSEGV. Using 
"continue" 
+# instead of single stepping avoids setting of software breakpoint at 
address 0x0.
+arch = self.getArchitecture()
+if re.match("mips", arch):
+self.runCmd("continue")
+else:
+# Keep stepping until the inferior crashes
+while process.GetState() == lldb.eStateStopped and not 
lldbutil.is_thread_crashed(self, thread):
+thread.StepInstruction(False)
 
 self.assertEqual(process.GetState(), lldb.eStateStopped, 
PROCESS_STOPPED)
 self.assertTrue(lldbutil.is_thread_crashed(self, thread), "Thread has 
crashed")


Index: packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py
===
--- packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py
+++ packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py
@@ -43,9 +43,16 @@
 thread = process.GetThreadAtIndex(0)
 self.assertTrue(thread and thread.IsValid(), "Thread is valid")
 
-# Keep stepping until the inferior crashes
-while process.GetState() == lldb.eStateStopped and not lldbutil.is_thread_crashed(self, thread):
-thread.StepInstruction(False)
+# Single stepping requires setting software breakpoint at address 0x0. 
+# This results in input/output error instead of SIGSEGV. Using "continue" 
+# instead of single stepping avoids setting of software breakpoint at address 0x0.
+arch = self.getArchitecture()
+if re.match("mips", arch):
+self.runCmd("continue")
+else:
+# Keep stepping until the inferior crashes
+while process.GetState() == lldb.eStateStopped and not lldbutil.is_thread_crashed(self, thread):
+thread.StepInstruction(False)
 
 self.assertEqual(process.GetState(), lldb.eStateStopped, PROCESS_STOPPED)
 self.assertTrue(lldbutil.is_thread_crashed(self, thread), "Thread has crashed")
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r254590 - [LLDB][MIPS] Using enum instead of a constant to fetch PC and CAUSE registers.

[Jaydeep Patil via lldb-commits]

Author: jaydeep
Date: Thu Dec  3 00:41:24 2015
New Revision: 254590

URL: http://llvm.org/viewvc/llvm-project?rev=254590&view=rev
Log:
[LLDB][MIPS] Using enum instead of a constant to fetch PC and CAUSE registers.
SUMMARY:
Using enum instead of a constant to fetch PC and CAUSE registers.

Modified:

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp

Modified: 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp?rev=254590&r1=254589&r2=254590&view=diff
==
--- 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp 
(original)
+++ 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp 
Thu Dec  3 00:41:24 2015
@@ -494,7 +494,7 @@ NativeRegisterContextLinux_mips64::GetPC
 log->Printf ("NativeRegisterContextLinux_mips64::%s Reading PC from 
breakpoint location", __FUNCTION__);
 
 // PC register is at index 34 of the register array
-const RegisterInfo *const pc_info_p = GetRegisterInfoAtIndex (34);
+const RegisterInfo *const pc_info_p = GetRegisterInfoAtIndex 
(gpr_pc_mips64);
 
 error = ReadRegister (pc_info_p, pc_value);
 if (error.Success ())
@@ -502,7 +502,7 @@ NativeRegisterContextLinux_mips64::GetPC
 pc = pc_value.GetAsUInt64 ();
 
 // CAUSE register is at index 37 of the register array
-const RegisterInfo *const cause_info_p = GetRegisterInfoAtIndex (37);
+const RegisterInfo *const cause_info_p = GetRegisterInfoAtIndex 
(gpr_cause_mips64);
 RegisterValue cause_value;
 
 ReadRegister (cause_info_p, cause_value);


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D14978: [MIPS] Change ARCHFLAG for MIPS

[Jaydeep Patil via lldb-commits]

jaydeep closed this revision.
jaydeep added a comment.

Closed by commit http://reviews.llvm.org/rL254376


Repository:
  rL LLVM

http://reviews.llvm.org/D14978



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r254376 - [LLDB][MIPS] Change ARCHFLAG for MIPS

[Jaydeep Patil via lldb-commits]

Author: jaydeep
Date: Mon Nov 30 23:24:17 2015
New Revision: 254376

URL: http://llvm.org/viewvc/llvm-project?rev=254376&view=rev
Log:
[LLDB][MIPS] Change ARCHFLAG for MIPS
SUMMARY:
For MIPS, ARCH is specified without m.

Reviewers: clayborg
Subscribers: nitesh.jain, mohit.bhakkad, sagar, bhushan and lldb-commits
Differential Revision: http://reviews.llvm.org/D14978

Modified:
lldb/trunk/packages/Python/lldbsuite/test/make/Makefile.rules

Modified: lldb/trunk/packages/Python/lldbsuite/test/make/Makefile.rules
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/make/Makefile.rules?rev=254376&r1=254375&r2=254376&view=diff
==
--- lldb/trunk/packages/Python/lldbsuite/test/make/Makefile.rules (original)
+++ lldb/trunk/packages/Python/lldbsuite/test/make/Makefile.rules Mon Nov 30 
23:24:17 2015
@@ -168,6 +168,9 @@ else
override ARCH :=
override ARCHFLAG :=
endif
+   ifeq "$(findstring mips,$(ARCH))" "mips"
+   override ARCHFLAG := -
+   endif
 
ifeq "$(SPLIT_DEBUG_SYMBOLS)" "YES"
DSYM = $(EXE).debug


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [PATCH] D14978: [MIPS] Change ARCHFLAG for MIPS

[Jaydeep Patil via lldb-commits]

jaydeep created this revision.
jaydeep added a reviewer: clayborg.
jaydeep added subscribers: lldb-commits, bhushan, mohit.bhakkad, sagar, 
nitesh.jain.
jaydeep set the repository for this revision to rL LLVM.

For MIPS, ARCH is specified without 'm'.

Repository:
  rL LLVM

http://reviews.llvm.org/D14978

Files:
  packages/Python/lldbsuite/test/make/Makefile.rules

Index: packages/Python/lldbsuite/test/make/Makefile.rules
===
--- packages/Python/lldbsuite/test/make/Makefile.rules
+++ packages/Python/lldbsuite/test/make/Makefile.rules
@@ -168,6 +168,9 @@
override ARCH :=
override ARCHFLAG :=
endif
+   ifeq "$(findstring mips,$(ARCH))" "mips"
+   override ARCHFLAG := -
+   endif
 
ifeq "$(SPLIT_DEBUG_SYMBOLS)" "YES"
DSYM = $(EXE).debug


Index: packages/Python/lldbsuite/test/make/Makefile.rules
===
--- packages/Python/lldbsuite/test/make/Makefile.rules
+++ packages/Python/lldbsuite/test/make/Makefile.rules
@@ -168,6 +168,9 @@
 		override ARCH :=
 		override ARCHFLAG :=
 	endif
+	ifeq "$(findstring mips,$(ARCH))" "mips"
+		override ARCHFLAG := -
+	endif
 
 	ifeq "$(SPLIT_DEBUG_SYMBOLS)" "YES"
 		DSYM = $(EXE).debug
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D14860: [LLDB][MIPS] Getting 0 index for h/w watchpoint is not necessarily an error

[Jaydeep Patil via lldb-commits]

jaydeep accepted this revision.
jaydeep added a comment.
This revision is now accepted and ready to land.

Looks good to me.


Repository:
  rL LLVM

http://reviews.llvm.org/D14860



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [Diffusion] rL247773: [LLDB][MIPS] Debug bare-iron targets lacking support for qC /qfThreadInfo

[Jaydeep Patil via lldb-commits]

jaydeep added a comment.

Hi Dwan,

Could you please try  http://reviews.llvm.org/rL247968 and let me know if the 
issue persist?

Thanks,
Jaydeep


Users:
  jaydeep (Author)
  dawn (Auditor)

http://reviews.llvm.org/rL247773



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [Diffusion] rL247968: [LLDB][MIPS] Debug bare-iron targets lacking support for qC /qfThreadInfo

[Jaydeep Patil via lldb-commits]

jaydeep added a comment.

Hi Dawn,

Could you please provide more details on this?

Thanks,
Jaydeep


Users:
  jaydeep (Author)
  dawn (Auditor)

http://reviews.llvm.org/rL247968



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [Diffusion] rL247773: [LLDB][MIPS] Debug bare-iron targets lacking support for qC /qfThreadInfo

[Jaydeep Patil via lldb-commits]

jaydeep added a comment.

Hi Dawn,

Could you please provide more details on this?

Thanks,
Jaydeep


Users:
  jaydeep (Author)
  dawn (Auditor)

http://reviews.llvm.org/rL247773



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D13335: [LLDB][MIPS] Skip invalid size watchpoint testcase for MIPS

[Jaydeep Patil via lldb-commits]

jaydeep accepted this revision.
jaydeep added a comment.
This revision is now accepted and ready to land.

Looks good


Repository:
  rL LLVM

http://reviews.llvm.org/D13335



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [Diffusion] rL247968: [LLDB][MIPS] Debug bare-iron targets lacking support for qC /qfThreadInfo

[Jaydeep Patil via lldb-commits]

jaydeep added a comment.

Hi Dawn,

Let me check and get back to you.

Regards,
Jaydeep


Users:
  jaydeep (Author)
  dawn (Auditor)

http://reviews.llvm.org/rL247968



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D12079: [MIPS] microMIPS breakpoints, disassembly and compressed addresses

[Jaydeep Patil via lldb-commits]

jaydeep closed this revision.
jaydeep added a comment.

Closed by commit http://reviews.llvm.org/rL248248


Repository:
  rL LLVM

http://reviews.llvm.org/D12079



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r248248 - [LLDB][MIPS] microMIPS breakpoints, disassembly and compressed addresses

[Jaydeep Patil via lldb-commits]

Author: jaydeep
Date: Tue Sep 22 01:36:56 2015
New Revision: 248248

URL: http://llvm.org/viewvc/llvm-project?rev=248248&view=rev
Log:
[LLDB][MIPS] microMIPS breakpoints, disassembly and compressed addresses
SUMMARY:
This patch detects microMIPS symbols, sets breakpoints using un-compressed 
address and 
display disassembly in mixed mode for microMIPS applications (running on 
bare-iron targets).

Reviewers: clayborg
Subscribers: nitesh.jain, mohit.bhakkad, sagar, bhushan and lldb-commits
Differential Revision: http://reviews.llvm.org/D12079

Modified:
lldb/trunk/source/Core/Address.cpp
lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
lldb/trunk/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
lldb/trunk/source/Target/RegisterContext.cpp
lldb/trunk/source/Target/Target.cpp

Modified: lldb/trunk/source/Core/Address.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Core/Address.cpp?rev=248248&r1=248247&r2=248248&view=diff
==
--- lldb/trunk/source/Core/Address.cpp (original)
+++ lldb/trunk/source/Core/Address.cpp Tue Sep 22 01:36:56 2015
@@ -463,6 +463,20 @@ Address::Dump (Stream *s, ExecutionConte
 case DumpStyleLoadAddress:
 {
 addr_t load_addr = GetLoadAddress (target);
+
+/*
+ * MIPS:
+ * Display address in compressed form for MIPS16 or microMIPS
+ * if the address belongs to eAddressClassCodeAlternateISA.
+*/
+if (target)
+{
+const llvm::Triple::ArchType llvm_arch = 
target->GetArchitecture().GetMachine();
+if (llvm_arch == llvm::Triple::mips || llvm_arch == 
llvm::Triple::mipsel
+|| llvm_arch == llvm::Triple::mips64 || llvm_arch == 
llvm::Triple::mips64el)
+load_addr = GetCallableLoadAddress (target);
+}
+
 if (load_addr == LLDB_INVALID_ADDRESS)
 {
 if (fallback_style != DumpStyleInvalid)

Modified: lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp?rev=248248&r1=248247&r2=248248&view=diff
==
--- lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp (original)
+++ lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp Tue Sep 
22 01:36:56 2015
@@ -736,10 +736,6 @@ DisassemblerLLVMC::DisassemblerLLVMC (co
 features_str += "+dsp,";
 if (arch_flags & ArchSpec::eMIPSAse_dspr2)
 features_str += "+dspr2,";
-if (arch_flags & ArchSpec::eMIPSAse_mips16)
-features_str += "+mips16,";
-if (arch_flags & ArchSpec::eMIPSAse_micromips)
-features_str += "+micromips,";
 }
 
 m_disasm_ap.reset (new LLVMCDisassembler(triple_str, cpu, 
features_str.c_str(), flavor, *this));
@@ -750,14 +746,35 @@ DisassemblerLLVMC::DisassemblerLLVMC (co
 m_disasm_ap.reset();
 }
 
+llvm::Triple::ArchType llvm_arch = triple.getArch();
+
 // For arm CPUs that can execute arm or thumb instructions, also create a 
thumb instruction disassembler.
-if (triple.getArch() == llvm::Triple::arm)
+if (llvm_arch == llvm::Triple::arm)
 {
 std::string thumb_triple(thumb_arch.GetTriple().getTriple());
 m_alternate_disasm_ap.reset(new 
LLVMCDisassembler(thumb_triple.c_str(), "", "", flavor, *this));
 if (!m_alternate_disasm_ap->IsValid())
 {
 m_disasm_ap.reset();
+m_alternate_disasm_ap.reset();
+}
+}
+else if (llvm_arch == llvm::Triple::mips
+|| llvm_arch == llvm::Triple::mipsel
+|| llvm_arch == llvm::Triple::mips64
+|| llvm_arch == llvm::Triple::mips64el)
+{
+/* Create alternate disassembler for MIPS16 and microMIPS */
+uint32_t arch_flags = arch.GetFlags ();
+if (arch_flags & ArchSpec::eMIPSAse_mips16)
+features_str += "+mips16,";
+else if (arch_flags & ArchSpec::eMIPSAse_micromips)
+features_str += "+micromips,";
+
+m_alternate_disasm_ap.reset(new LLVMCDisassembler (triple_str, cpu, 
features_str.c_str(), flavor, *this));
+if (!m_alternate_disasm_ap->IsValid())
+{
+m_disasm_ap.reset();
 m_alternate_disasm_ap.reset();
 }
 }

Modified: lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp?rev=248248&r1=248247&r2=248248&view=diff
==
--- lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFi

Re: [Lldb-commits] [PATCH] D12876: [MIPS] Debug bare-iron targets lacking support for qC /qfThreadInfo

[Jaydeep Patil via lldb-commits]

jaydeep added a comment.

Changed "!response.IsNormalResponse()" to "response.IsUnsupportedResponse()" by 
commit http://reviews.llvm.org/rL247968


Repository:
  rL LLVM

http://reviews.llvm.org/D12876



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r247968 - [LLDB][MIPS] Debug bare-iron targets lacking support for qC /qfThreadInfo

[Jaydeep Patil via lldb-commits]

Author: jaydeep
Date: Fri Sep 18 00:32:54 2015
New Revision: 247968

URL: http://llvm.org/viewvc/llvm-project?rev=247968&view=rev
Log:
[LLDB][MIPS] Debug bare-iron targets lacking support for qC /qfThreadInfo
SUMMARY:
Using response.IsUnsupportedResponse instead of 
!response.IsNormalResponse().

Reviewers: clayborg, labath
Subscribers: nitesh.jain, mohit.bhakkad, sagar, bhushan and lldb-commits
Differential Revision: http://reviews.llvm.org/D12876

Modified:

lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp

Modified: 
lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp?rev=247968&r1=247967&r2=247968&view=diff
==
--- 
lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp 
(original)
+++ 
lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp 
Fri Sep 18 00:32:54 2015
@@ -3400,6 +3400,17 @@ GDBRemoteCommunicationClient::SetCurrent
 m_curr_tid = tid;
 return true;
 }
+
+/*
+ * Connected bare-iron target (like YAMON gdb-stub) may not have 
support for Hg packet.
+ * The reply from '?' packet could be as simple as 'S05'. There is no 
packet which can
+ * give us pid and/or tid. Assume pid=tid=1 in such cases.
+*/
+if (response.IsUnsupportedResponse() && IsConnected())
+{
+m_curr_tid = 1;
+return true;
+}
 }
 return false;
 }
@@ -3426,6 +3437,17 @@ GDBRemoteCommunicationClient::SetCurrent
 m_curr_tid_run = tid;
 return true;
 }
+
+/*
+ * Connected bare-iron target (like YAMON gdb-stub) may not have 
support for Hc packet.
+ * The reply from '?' packet could be as simple as 'S05'. There is no 
packet which can
+ * give us pid and/or tid. Assume pid=tid=1 in such cases.
+*/
+if (response.IsUnsupportedResponse() && IsConnected())
+{
+m_curr_tid_run = 1;
+return true;
+}
 }
 return false;
 }
@@ -3551,6 +3573,17 @@ GDBRemoteCommunicationClient::GetCurrent
 } while (ch == ',');// Make sure we got a comma 
separator
 }
 }
+
+/*
+ * Connected bare-iron target (like YAMON gdb-stub) may not have 
support for
+ * qProcessInfo, qC and qfThreadInfo packets. The reply from '?' 
packet could
+ * be as simple as 'S05'. There is no packet which can give us pid 
and/or tid.
+ * Assume pid=tid=1 in such cases.
+*/
+if (response.IsUnsupportedResponse() && thread_ids.size() == 0 && 
IsConnected())
+{
+thread_ids.push_back (1);
+}
 }
 else
 {


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D12079: [MIPS] microMIPS breakpoints, disassembly and compressed addresses

[Jaydeep Patil via lldb-commits]

jaydeep updated this revision to Diff 35059.
jaydeep added a comment.

Addressed review comments.


Repository:
  rL LLVM

http://reviews.llvm.org/D12079

Files:
  source/Core/Address.cpp
  source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
  source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
  source/Target/RegisterContext.cpp
  source/Target/Target.cpp

Index: source/Target/Target.cpp
===
--- source/Target/Target.cpp
+++ source/Target/Target.cpp
@@ -2092,6 +2092,27 @@
 addr_t code_addr = load_addr;
 switch (m_arch.GetMachine())
 {
+case llvm::Triple::mips:
+case llvm::Triple::mipsel:
+case llvm::Triple::mips64:
+case llvm::Triple::mips64el:
+switch (addr_class)
+{
+case eAddressClassData:
+case eAddressClassDebug:
+return LLDB_INVALID_ADDRESS;
+
+case eAddressClassUnknown:
+case eAddressClassInvalid:
+case eAddressClassCode:
+case eAddressClassCodeAlternateISA:
+case eAddressClassRuntime:
+if ((code_addr & 2ull) || (addr_class == eAddressClassCodeAlternateISA))
+code_addr |= 1ull;
+break;
+}
+break;
+
 case llvm::Triple::arm:
 case llvm::Triple::thumb:
 switch (addr_class)
@@ -2137,6 +2158,10 @@
 addr_t opcode_addr = load_addr;
 switch (m_arch.GetMachine())
 {
+case llvm::Triple::mips:
+case llvm::Triple::mipsel:
+case llvm::Triple::mips64:
+case llvm::Triple::mips64el:
 case llvm::Triple::arm:
 case llvm::Triple::thumb:
 switch (addr_class)
Index: source/Target/RegisterContext.cpp
===
--- source/Target/RegisterContext.cpp
+++ source/Target/RegisterContext.cpp
@@ -20,6 +20,7 @@
 #include "lldb/Target/StackFrame.h"
 #include "lldb/Target/Process.h"
 #include "lldb/Target/Thread.h"
+#include "lldb/Target/Target.h"
 
 using namespace lldb;
 using namespace lldb_private;
@@ -103,7 +104,20 @@
 RegisterContext::GetPC(uint64_t fail_value)
 {
 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
-return ReadRegisterAsUnsigned (reg, fail_value);
+uint64_t pc = ReadRegisterAsUnsigned (reg, fail_value);
+
+if (pc != fail_value)
+{
+TargetSP target_sp = m_thread.CalculateTarget();
+if (target_sp)
+{
+Target *target = target_sp.get();
+if (target)
+pc = target->GetOpcodeLoadAddress (pc, eAddressClassCode);
+}
+}
+
+return pc;
 }
 
 bool
Index: source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
===
--- source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
+++ source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
@@ -1128,6 +1128,7 @@
 {
 LineTable* line_table;
 std::unique_ptr sequence_ap;
+lldb::addr_t addr_mask;
 };
 
 //--
@@ -1157,7 +1158,7 @@
 assert(info->sequence_ap.get());
 }
 line_table->AppendLineEntryToSequence (info->sequence_ap.get(),
-   state.address,
+   state.address & info->addr_mask,
state.line,
state.column,
state.file,
@@ -1197,6 +1198,28 @@
 {
 ParseDWARFLineTableCallbackInfo info;
 info.line_table = line_table_ap.get();
+
+/*
+ * MIPS:
+ * The SymbolContext may not have a valid target, thus we may not be able
+ * to call Address::GetOpcodeLoadAddress() which would clear the bit #0
+ * for MIPS. Use ArchSpec to clear the bit #0.
+*/
+ArchSpec arch;
+GetObjectFile()->GetArchitecture(arch);
+switch (arch.GetMachine())
+{
+case llvm::Triple::mips:
+case llvm::Triple::mipsel:
+case llvm::Triple::mips64:
+case llvm::Triple::mips64el:
+info.addr_mask = ~((lldb::addr_t)1);
+break;
+default:
+info.addr_mask = ~((lldb::addr_t)0);
+break;
+}
+
 lldb::offset_t offset = cu_line_offset;
 DWARFDebugLine::ParseStatementTable(get_debug_line_data(), &offset, ParseDWARFLineTableCallback, &info);
 if (m_debug_map_symfile)
Index: source/Plugins/ObjectFile

Re: [Lldb-commits] [PATCH] D12876: [MIPS] Debug bare-iron targets lacking support for qC /qfThreadInfo

[Jaydeep Patil via lldb-commits]

jaydeep added inline comments.


Comment at: 
source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp:3579
@@ +3578,3 @@
+*/
+if (!response.IsNormalResponse() && thread_ids.size() == 0 && 
IsConnected())
+{

labath wrote:
> labath wrote:
> > The problem behind the failures seems to be this: when we connect to the 
> > remote lldb-server, it should not have any processes or threads running (we 
> > will start those with the A packet later). We verify this in 
> > ProcessGDBRemote.cpp:837. This translates to a qfThreadInfo packet, to 
> > which our stub responds with OK.
> > 
> > This sounds like a bug in the stub, as the protocol does not mention that 
> > as a possibility. I will prepare a patch for that shortly. Could you please 
> > wait with this patch a bit until the bugfix lands?
> > 
> > Also, this got me thinking.. What is the response of your stub to the 
> > qfThreadInfo packet. If it is something like '?', then we could check for 
> > `response.IsUnsupportedResponse()` and we will avoid an overly broad check 
> > for your corner case. What do you think?
> > The problem behind the failures seems to be this: when we connect to the 
> > remote lldb-server, it should not have any processes or threads running (we 
> > will start those with the A packet later). We verify this in 
> > ProcessGDBRemote.cpp:837. This translates to a qfThreadInfo packet, to 
> > which our stub responds with OK.
> 
> Hmm.. the debugserver seems to have this behavior as well. Greg, what do you 
> think should be the right response to this packet when we have no process 
> running? My feeling is that we should just send a "l" packet as if we have 
> just reached the end of the list. What do you think?
Response from the target is "$#00". I think we should check for 
IsUnsupportedResponse().



Repository:
  rL LLVM

http://reviews.llvm.org/D12876



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D12079: [MIPS] microMIPS breakpoints, disassembly and compressed addresses

[Jaydeep Patil via lldb-commits]

jaydeep updated this revision to Diff 34873.
jaydeep added a comment.

Addressed review comments


Repository:
  rL LLVM

http://reviews.llvm.org/D12079

Files:
  source/Core/Address.cpp
  source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
  source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
  source/Target/RegisterContext.cpp
  source/Target/Target.cpp

Index: source/Target/Target.cpp
===
--- source/Target/Target.cpp
+++ source/Target/Target.cpp
@@ -2092,6 +2092,27 @@
 addr_t code_addr = load_addr;
 switch (m_arch.GetMachine())
 {
+case llvm::Triple::mips:
+case llvm::Triple::mipsel:
+case llvm::Triple::mips64:
+case llvm::Triple::mips64el:
+switch (addr_class)
+{
+case eAddressClassData:
+case eAddressClassDebug:
+return LLDB_INVALID_ADDRESS;
+
+case eAddressClassUnknown:
+case eAddressClassInvalid:
+case eAddressClassCode:
+case eAddressClassCodeAlternateISA:
+case eAddressClassRuntime:
+if ((code_addr & 2ull) || (addr_class == eAddressClassCodeAlternateISA))
+code_addr |= 1ull;
+break;
+}
+break;
+
 case llvm::Triple::arm:
 case llvm::Triple::thumb:
 switch (addr_class)
@@ -2137,6 +2158,10 @@
 addr_t opcode_addr = load_addr;
 switch (m_arch.GetMachine())
 {
+case llvm::Triple::mips:
+case llvm::Triple::mipsel:
+case llvm::Triple::mips64:
+case llvm::Triple::mips64el:
 case llvm::Triple::arm:
 case llvm::Triple::thumb:
 switch (addr_class)
Index: source/Target/RegisterContext.cpp
===
--- source/Target/RegisterContext.cpp
+++ source/Target/RegisterContext.cpp
@@ -20,6 +20,7 @@
 #include "lldb/Target/StackFrame.h"
 #include "lldb/Target/Process.h"
 #include "lldb/Target/Thread.h"
+#include "lldb/Target/Target.h"
 
 using namespace lldb;
 using namespace lldb_private;
@@ -103,7 +104,20 @@
 RegisterContext::GetPC(uint64_t fail_value)
 {
 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
-return ReadRegisterAsUnsigned (reg, fail_value);
+uint64_t pc = ReadRegisterAsUnsigned (reg, fail_value);
+
+if (pc != fail_value)
+{
+TargetSP target_sp = m_thread.CalculateTarget();
+if (target_sp)
+{
+Target *target = target_sp.get();
+if (target)
+pc = target->GetOpcodeLoadAddress (pc, eAddressClassCode);
+}
+}
+
+return pc;
 }
 
 bool
Index: source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
===
--- source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
+++ source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
@@ -1128,6 +1128,7 @@
 {
 LineTable* line_table;
 std::unique_ptr sequence_ap;
+lldb::addr_t addr_mask;
 };
 
 //--
@@ -1157,7 +1158,7 @@
 assert(info->sequence_ap.get());
 }
 line_table->AppendLineEntryToSequence (info->sequence_ap.get(),
-   state.address,
+   state.address & info->addr_mask,
state.line,
state.column,
state.file,
@@ -1197,6 +1198,28 @@
 {
 ParseDWARFLineTableCallbackInfo info;
 info.line_table = line_table_ap.get();
+
+/*
+ * MIPS:
+ * The SymbolContext may not have a valid target, thus we may not be able
+ * to call Address::GetOpcodeLoadAddress() which would clear the bit #0
+ * for MIPS. Use ArchSpec to clear the bit #0.
+*/
+ArchSpec arch;
+GetObjectFile()->GetArchitecture(arch);
+switch (arch.GetMachine())
+{
+case llvm::Triple::mips:
+case llvm::Triple::mipsel:
+case llvm::Triple::mips64:
+case llvm::Triple::mips64el:
+info.addr_mask = ~((lldb::addr_t)1);
+break;
+default:
+info.addr_mask = ~((lldb::addr_t)0);
+break;
+}
+
 lldb::offset_t offset = cu_line_offset;
 DWARFDebugLine::ParseStatementTable(get_debug_line_data(), &offset, ParseDWARFLineTableCallback, &info);
 if (m_debug_map_symfile)
Index: source/Plugins/ObjectFile/

Re: [Lldb-commits] [PATCH] D12876: [MIPS] Debug bare-iron targets lacking support for qC /qfThreadInfo

[Jaydeep Patil via lldb-commits]

jaydeep closed this revision.
jaydeep added a comment.

Closed by commit http://reviews.llvm.org/rL247773


Repository:
  rL LLVM

http://reviews.llvm.org/D12876



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r247773 - [LLDB][MIPS] Debug bare-iron targets lacking support for qC /qfThreadInfo

[Jaydeep Patil via lldb-commits]

Author: jaydeep
Date: Tue Sep 15 23:04:01 2015
New Revision: 247773

URL: http://llvm.org/viewvc/llvm-project?rev=247773&view=rev
Log:
[LLDB][MIPS] Debug bare-iron targets lacking support for qC /qfThreadInfo
SUMMARY:
Refer to http://lists.llvm.org/pipermail/lldb-dev/2015-August/008024.html 
for discussion
on this topic. Bare-iron target like YAMON gdb-stub does not support 
qProcessInfo, qC,
qfThreadInfo, Hg and Hc packets. Reply from ? packet is as simple as S05. 
There is no 
packet which gives us process or threads information. In such cases, assume 
pid=tid=1.

Reviewers: clayborg
Subscribers: nitesh.jain, mohit.bhakkad, sagar, bhushan and lldb-commits
Differential Revision: http://reviews.llvm.org/D12876

Modified:

lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp

Modified: 
lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp?rev=247773&r1=247772&r2=247773&view=diff
==
--- 
lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp 
(original)
+++ 
lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp 
Tue Sep 15 23:04:01 2015
@@ -3396,6 +3396,17 @@ GDBRemoteCommunicationClient::SetCurrent
 m_curr_tid = tid;
 return true;
 }
+
+/*
+ * Connected bare-iron target (like YAMON gdb-stub) may not have 
support for Hg packet.
+ * The reply from '?' packet could be as simple as 'S05'. There is no 
packet which can
+ * give us pid and/or tid. Assume pid=tid=1 in such cases.
+*/
+if (!response.IsNormalResponse() && IsConnected())
+{
+m_curr_tid = 1;
+return true;
+}
 }
 return false;
 }
@@ -3422,6 +3433,17 @@ GDBRemoteCommunicationClient::SetCurrent
 m_curr_tid_run = tid;
 return true;
 }
+
+/*
+ * Connected bare-iron target (like YAMON gdb-stub) may not have 
support for Hc packet.
+ * The reply from '?' packet could be as simple as 'S05'. There is no 
packet which can
+ * give us pid and/or tid. Assume pid=tid=1 in such cases.
+*/
+if (!response.IsNormalResponse() && IsConnected())
+{
+m_curr_tid_run = 1;
+return true;
+}
 }
 return false;
 }
@@ -3547,6 +3569,17 @@ GDBRemoteCommunicationClient::GetCurrent
 } while (ch == ',');// Make sure we got a comma 
separator
 }
 }
+
+/*
+ * Connected bare-iron target (like YAMON gdb-stub) may not have 
support for
+ * qProcessInfo, qC and qfThreadInfo packets. The reply from '?' 
packet could
+ * be as simple as 'S05'. There is no packet which can give us pid 
and/or tid.
+ * Assume pid=tid=1 in such cases.
+*/
+if (!response.IsNormalResponse() && thread_ids.size() == 0 && 
IsConnected())
+{
+thread_ids.push_back (1);
+}
 }
 else
 {


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [PATCH] D12876: [MIPS] Debug bare-iron targets lacking support for qC /qfThreadInfo

[Jaydeep Patil via lldb-commits]

jaydeep created this revision.
jaydeep added a reviewer: clayborg.
jaydeep added subscribers: lldb-commits, bhushan, sagar, mohit.bhakkad, 
nitesh.jain.
jaydeep set the repository for this revision to rL LLVM.

Refer to  for 
discussion on this topic.

Bare-iron target like YAMON gdb-stub does not support qProcessInfo, qC, 
qfThreadInfo, Hg and Hc packets. Reply from ‘?’ packet is as simple as ‘S05’. 
There is no packet which gives us process or threads information. In such 
cases, assume pid=tid=1.



Repository:
  rL LLVM

http://reviews.llvm.org/D12876

Files:
  source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp

Index: source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
===
--- source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
+++ source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
@@ -3396,6 +3396,17 @@
 m_curr_tid = tid;
 return true;
 }
+
+/*
+ * Connected bare-iron target (like YAMON gdb-stub) may not have 
support for Hg packet.
+ * The reply from '?' packet could be as simple as 'S05'. There is no 
packet which can
+ * give us pid and/or tid. Assume pid=tid=1 in such cases.
+*/
+if (!response.IsNormalResponse() && IsConnected())
+{
+m_curr_tid = 1;
+return true;
+}
 }
 return false;
 }
@@ -3422,6 +3433,17 @@
 m_curr_tid_run = tid;
 return true;
 }
+
+/*
+ * Connected bare-iron target (like YAMON gdb-stub) may not have 
support for Hc packet.
+ * The reply from '?' packet could be as simple as 'S05'. There is no 
packet which can
+ * give us pid and/or tid. Assume pid=tid=1 in such cases.
+*/
+if (!response.IsNormalResponse() && IsConnected())
+{
+m_curr_tid_run = 1;
+return true;
+}
 }
 return false;
 }
@@ -3547,6 +3569,17 @@
 } while (ch == ',');// Make sure we got a comma 
separator
 }
 }
+
+/*
+ * Connected bare-iron target (like YAMON gdb-stub) may not have 
support for
+ * qProcessInfo, qC and qfThreadInfo packets. The reply from '?' 
packet could
+ * be as simple as 'S05'. There is no packet which can give us pid 
and/or tid.
+ * Assume pid=tid=1 in such cases.
+*/
+if (!response.IsNormalResponse() && thread_ids.size() == 0 && 
IsConnected())
+{
+thread_ids.push_back (1);
+}
 }
 else
 {


Index: source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
===
--- source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
+++ source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
@@ -3396,6 +3396,17 @@
 m_curr_tid = tid;
 return true;
 }
+
+/*
+ * Connected bare-iron target (like YAMON gdb-stub) may not have support for Hg packet.
+ * The reply from '?' packet could be as simple as 'S05'. There is no packet which can
+ * give us pid and/or tid. Assume pid=tid=1 in such cases.
+*/
+if (!response.IsNormalResponse() && IsConnected())
+{
+m_curr_tid = 1;
+return true;
+}
 }
 return false;
 }
@@ -3422,6 +3433,17 @@
 m_curr_tid_run = tid;
 return true;
 }
+
+/*
+ * Connected bare-iron target (like YAMON gdb-stub) may not have support for Hc packet.
+ * The reply from '?' packet could be as simple as 'S05'. There is no packet which can
+ * give us pid and/or tid. Assume pid=tid=1 in such cases.
+*/
+if (!response.IsNormalResponse() && IsConnected())
+{
+m_curr_tid_run = 1;
+return true;
+}
 }
 return false;
 }
@@ -3547,6 +3569,17 @@
 } while (ch == ',');// Make sure we got a comma separator
 }
 }
+
+/*
+ * Connected bare-iron target (like YAMON gdb-stub) may not have support for
+ * qProcessInfo, qC and qfThreadInfo packets. The reply from '?' packet could
+ * be as simple as 'S05'. There is no packet which can give us pid and/or tid.
+ * Assume pid=tid=1 in such cases.
+*/
+if (!response.IsNormalResponse() && thread_ids.size() == 0 && IsConnected())
+{
+thread_ids.push_back (1);
+}
 }
 else
 {
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D12079: [MIPS] microMIPS breakpoints, disassembly and compressed addresses

[Jaydeep Patil via lldb-commits]

jaydeep updated this revision to Diff 34782.
jaydeep added a comment.

Addressed review comments


Repository:
  rL LLVM

http://reviews.llvm.org/D12079

Files:
  source/Core/Address.cpp
  source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
  source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
  source/Target/RegisterContext.cpp
  source/Target/Target.cpp

Index: source/Target/Target.cpp
===
--- source/Target/Target.cpp
+++ source/Target/Target.cpp
@@ -2092,6 +2092,27 @@
 addr_t code_addr = load_addr;
 switch (m_arch.GetMachine())
 {
+case llvm::Triple::mips:
+case llvm::Triple::mipsel:
+case llvm::Triple::mips64:
+case llvm::Triple::mips64el:
+switch (addr_class)
+{
+case eAddressClassData:
+case eAddressClassDebug:
+return LLDB_INVALID_ADDRESS;
+
+case eAddressClassUnknown:
+case eAddressClassInvalid:
+case eAddressClassCode:
+case eAddressClassCodeAlternateISA:
+case eAddressClassRuntime:
+if ((code_addr & 2ull) || (addr_class == eAddressClassCodeAlternateISA))
+code_addr |= 1ull;
+break;
+}
+break;
+
 case llvm::Triple::arm:
 case llvm::Triple::thumb:
 switch (addr_class)
@@ -2137,6 +2158,10 @@
 addr_t opcode_addr = load_addr;
 switch (m_arch.GetMachine())
 {
+case llvm::Triple::mips:
+case llvm::Triple::mipsel:
+case llvm::Triple::mips64:
+case llvm::Triple::mips64el:
 case llvm::Triple::arm:
 case llvm::Triple::thumb:
 switch (addr_class)
Index: source/Target/RegisterContext.cpp
===
--- source/Target/RegisterContext.cpp
+++ source/Target/RegisterContext.cpp
@@ -20,6 +20,7 @@
 #include "lldb/Target/StackFrame.h"
 #include "lldb/Target/Process.h"
 #include "lldb/Target/Thread.h"
+#include "lldb/Target/Target.h"
 
 using namespace lldb;
 using namespace lldb_private;
@@ -103,7 +104,20 @@
 RegisterContext::GetPC(uint64_t fail_value)
 {
 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
-return ReadRegisterAsUnsigned (reg, fail_value);
+uint64_t pc = ReadRegisterAsUnsigned (reg, fail_value);
+
+if (pc != fail_value)
+{
+TargetSP target_sp = m_thread.CalculateTarget();
+if (target_sp)
+{
+Target *target = target_sp.get();
+if (target)
+pc = target->GetOpcodeLoadAddress (pc, eAddressClassCode);
+}
+}
+
+return pc;
 }
 
 bool
Index: source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
===
--- source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
+++ source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
@@ -1128,6 +1128,7 @@
 {
 LineTable* line_table;
 std::unique_ptr sequence_ap;
+ArchSpec arch;
 };
 
 //--
@@ -1156,8 +1157,20 @@
 info->sequence_ap.reset(line_table->CreateLineSequenceContainer());
 assert(info->sequence_ap.get());
 }
+
+/*
+ * MIPS:
+ * The SymbolContext may not have a valid target, thus we may not be able
+ * to call Address::GetOpcodeLoadAddress() which would clear the bit #0
+ * for MIPS. Use ArchSpec to clear the bit #0.
+*/
+lldb::addr_t file_addr = state.address;
+if (info->arch.GetMachine() == llvm::Triple::mips || info->arch.GetMachine() == llvm::Triple::mipsel
+   || info->arch.GetMachine() == llvm::Triple::mips64 || info->arch.GetMachine() == llvm::Triple::mips64el)
+file_addr = state.address & (~1ull);
+
 line_table->AppendLineEntryToSequence (info->sequence_ap.get(),
-   state.address,
+   file_addr,
state.line,
state.column,
state.file,
@@ -1197,6 +1210,7 @@
 {
 ParseDWARFLineTableCallbackInfo info;
 info.line_table = line_table_ap.get();
+GetObjectFile()->GetArchitecture(info.arch);
 lldb::offset_t offset = cu_line_offset;
 DWARFDebugLine::ParseStatementTable(get_debug_line_data(), &offset, ParseDWARFLineTableCallback, &info);
 if (m_debug_map_symfile)
Index: source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===
--- source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -1854,6 +1854,10 @@
 }
 }
 
+#

Re: [Lldb-commits] [PATCH] D12079: [MIPS] microMIPS breakpoints, disassembly and compressed addresses

[Jaydeep Patil via lldb-commits]

jaydeep added a comment.

Hi Greg,
Could you please find some time to review this?
Thanks


Repository:
  rL LLVM

http://reviews.llvm.org/D12079



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D12079: [MIPS] microMIPS breakpoints, disassembly and compressed addresses

[Jaydeep Patil via lldb-commits]

jaydeep updated this revision to Diff 34532.
jaydeep added a comment.

In this patch:
Modified DumpAddress() to print compressed address for microMIPS.


Repository:
  rL LLVM

http://reviews.llvm.org/D12079

Files:
  source/Core/FormatEntity.cpp
  source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
  source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
  source/Target/RegisterContext.cpp
  source/Target/Target.cpp

Index: source/Target/Target.cpp
===
--- source/Target/Target.cpp
+++ source/Target/Target.cpp
@@ -2065,6 +2065,27 @@
 addr_t code_addr = load_addr;
 switch (m_arch.GetMachine())
 {
+case llvm::Triple::mips:
+case llvm::Triple::mipsel:
+case llvm::Triple::mips64:
+case llvm::Triple::mips64el:
+switch (addr_class)
+{
+case eAddressClassData:
+case eAddressClassDebug:
+return LLDB_INVALID_ADDRESS;
+
+case eAddressClassUnknown:
+case eAddressClassInvalid:
+case eAddressClassCode:
+case eAddressClassCodeAlternateISA:
+case eAddressClassRuntime:
+if ((code_addr & 2ull) || (addr_class == eAddressClassCodeAlternateISA))
+code_addr |= 1ull;
+break;
+}
+break;
+
 case llvm::Triple::arm:
 case llvm::Triple::thumb:
 switch (addr_class)
@@ -2110,6 +2131,10 @@
 addr_t opcode_addr = load_addr;
 switch (m_arch.GetMachine())
 {
+case llvm::Triple::mips:
+case llvm::Triple::mipsel:
+case llvm::Triple::mips64:
+case llvm::Triple::mips64el:
 case llvm::Triple::arm:
 case llvm::Triple::thumb:
 switch (addr_class)
Index: source/Target/RegisterContext.cpp
===
--- source/Target/RegisterContext.cpp
+++ source/Target/RegisterContext.cpp
@@ -20,6 +20,7 @@
 #include "lldb/Target/StackFrame.h"
 #include "lldb/Target/Process.h"
 #include "lldb/Target/Thread.h"
+#include "lldb/Target/Target.h"
 
 using namespace lldb;
 using namespace lldb_private;
@@ -103,7 +104,20 @@
 RegisterContext::GetPC(uint64_t fail_value)
 {
 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
-return ReadRegisterAsUnsigned (reg, fail_value);
+uint64_t pc = ReadRegisterAsUnsigned (reg, fail_value);
+
+if (pc != fail_value)
+{
+TargetSP target_sp = m_thread.CalculateTarget();
+if (target_sp)
+{
+Target *target = target_sp.get();
+if (target)
+pc = target->GetOpcodeLoadAddress (pc, eAddressClassCode);
+}
+}
+
+return pc;
 }
 
 bool
Index: source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
===
--- source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
+++ source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
@@ -1394,6 +1394,7 @@
 {
 LineTable* line_table;
 std::unique_ptr sequence_ap;
+ArchSpec arch;
 };
 
 //--
@@ -1422,8 +1423,20 @@
 info->sequence_ap.reset(line_table->CreateLineSequenceContainer());
 assert(info->sequence_ap.get());
 }
+
+/*
+ * MIPS:
+ * The SymbolContext may not have a valid target, thus we may not be able
+ * to call Address::GetOpcodeLoadAddress() which would clear the bit #0
+ * for MIPS. Use ArchSpec to clear the bit #0.
+*/
+lldb::addr_t file_addr = state.address;
+if (info->arch.GetMachine() == llvm::Triple::mips || info->arch.GetMachine() == llvm::Triple::mipsel
+   || info->arch.GetMachine() == llvm::Triple::mips64 || info->arch.GetMachine() == llvm::Triple::mips64el)
+file_addr = state.address & (~1ull);
+
 line_table->AppendLineEntryToSequence (info->sequence_ap.get(),
-   state.address,
+   file_addr,
state.line,
state.column,
state.file,
@@ -1463,6 +1476,7 @@
 {
 ParseDWARFLineTableCallbackInfo info;
 info.line_table = line_table_ap.get();
+GetObjectFile()->GetArchitecture(info.arch);
 lldb::offset_t offset = cu_line_offset;
 DWARFDebugLine::ParseStatementTable(get_debug_line_data(), &offset, ParseDWARFLineTableCallback, &info);
 if (m_debug_map_symfile)
Index: source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===
--- source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ source/Plugins/ObjectFile

Re: [Lldb-commits] [PATCH] D12079: [MIPS] microMIPS breakpoints, disassembly and compressed addresses

[Jaydeep Patil via lldb-commits]

jaydeep added a comment.

In http://reviews.llvm.org/D12079#244059, @jaydeep wrote:

> In http://reviews.llvm.org/D12079#243390, @clayborg wrote:
>
> > In http://reviews.llvm.org/D12079#242998, @jaydeep wrote:
> >
> > > In http://reviews.llvm.org/D12079#242742, @clayborg wrote:
> > >
> > > > So DumpAddress() in FormatEntity.cpp is a generic "dump any address by 
> > > > describing it". You can't just change the code to suit your needs for 
> > > > MIPS. This address could be any address: code or data. If you want 
> > > > something that can take an address like 0x1000 and you ask for its 
> > > > AddressClass and it sees that its address class is 
> > > > eAddressClassCodeAlternateISA, and then you change it to be "0x1001", 
> > > > this will need to be a new format type.
> > > >
> > > > DumpAddress in FormatEntity.cpp is called for the following entities:
> > > >
> > > >   case Entry::Type::LineEntryStartAddress:
> > > >   case Entry::Type::LineEntryEndAddress:
> > > >   case Entry::Type::AddressFile:
> > > >   case Entry::Type::AddressLoad:
> > > >   case Entry::Type::AddressLoadOrFile:
> > > >   case Entry::Type::FrameRegisterPC
> > > >   
> > > >
> > > > So only the LineEntry ones should actually do what you did.
> > >
> > >
> > > We need to display all these entities in compressed address format. How 
> > > about a new MIPS specific function in Address and Target class which 
> > > would do this.
> > >
> > > Address Address::GetCallableAddress(Target *target);
> > >  lldb::addr_t Target::GetCallableAddress (lldb::addr_t load_addr, 
> > > AddressClass addr_class);
> >
> >
> > We already have this in Target:
> >
> >   lldb::addr_t
> >   GetCallableLoadAddress (lldb::addr_t load_addr, lldb::AddressClass 
> > addr_class = lldb::eAddressClassInvalid) const;
> >   
> >
> > So the solution here will be to modify Address::Dump() such that it detects 
> > when an address is eAddressClassCodeAlternateISA and when that happens it 
> > checks if the ExecutionContext parameter is non NULL, and if so, extract 
> > the target, and check the target's architecture is MIPS, then add the extra 
> > bit when displaying this address. As it seems that we would always want to 
> > describe a section offset address (lldb_private::Address object) in this 
> > way to show the MicroMIPS address space bit, right?
>
>
>
>
> In http://reviews.llvm.org/D12079#243390, @clayborg wrote:
>
> > In http://reviews.llvm.org/D12079#242998, @jaydeep wrote:
> >
> > > In http://reviews.llvm.org/D12079#242742, @clayborg wrote:
> > >
> > > > So DumpAddress() in FormatEntity.cpp is a generic "dump any address by 
> > > > describing it". You can't just change the code to suit your needs for 
> > > > MIPS. This address could be any address: code or data. If you want 
> > > > something that can take an address like 0x1000 and you ask for its 
> > > > AddressClass and it sees that its address class is 
> > > > eAddressClassCodeAlternateISA, and then you change it to be "0x1001", 
> > > > this will need to be a new format type.
> > > >
> > > > DumpAddress in FormatEntity.cpp is called for the following entities:
> > > >
> > > >   case Entry::Type::LineEntryStartAddress:
> > > >   case Entry::Type::LineEntryEndAddress:
> > > >   case Entry::Type::AddressFile:
> > > >   case Entry::Type::AddressLoad:
> > > >   case Entry::Type::AddressLoadOrFile:
> > > >   case Entry::Type::FrameRegisterPC
> > > >   
> > > >
> > > > So only the LineEntry ones should actually do what you did.
> > >
> > >
> > > We need to display all these entities in compressed address format. How 
> > > about a new MIPS specific function in Address and Target class which 
> > > would do this.
> > >
> > > Address Address::GetCallableAddress(Target *target);
> > >  lldb::addr_t Target::GetCallableAddress (lldb::addr_t load_addr, 
> > > AddressClass addr_class);
> >
> >
> > We already have this in Target:
> >
> >   lldb::addr_t
> >   GetCallableLoadAddress (lldb::addr_t load_addr, lldb::AddressClass 
> > addr_class = lldb::eAddressClassInvalid) const;
> >   
> >
> > So the solution here will be to modify Address::Dump() such that it detects 
> > when an address is eAddressClassCodeAlternateISA and when that happens it 
> > checks if the ExecutionContext parameter is non NULL, and if so, extract 
> > the target, and check the target's architecture is MIPS, then add the extra 
> > bit when displaying this address. As it seems that we would always want to 
> > describe a section offset address (lldb_private::Address object) in this 
> > way to show the MicroMIPS address space bit, right?
>
>
> Yes.


Instead of modifying Address::Dump() we should modify DumpAddress() so that

In http://reviews.llvm.org/D12079#244059, @jaydeep wrote:

> In http://reviews.llvm.org/D12079#243390, @clayborg wrote:
>
> > In http://reviews.llvm.org/D12079#242998, @jaydeep wrote:
> >
> > > In http://reviews.llvm.org/D12079#242742, @clayborg wrote:
> > >
> > > > So DumpAddress() in FormatEntity.cpp is a generic "dump

Re: [Lldb-commits] [PATCH] D12079: [MIPS] microMIPS breakpoints, disassembly and compressed addresses

[Jaydeep Patil via lldb-commits]

jaydeep added a comment.

In http://reviews.llvm.org/D12079#243390, @clayborg wrote:

> In http://reviews.llvm.org/D12079#242998, @jaydeep wrote:
>
> > In http://reviews.llvm.org/D12079#242742, @clayborg wrote:
> >
> > > So DumpAddress() in FormatEntity.cpp is a generic "dump any address by 
> > > describing it". You can't just change the code to suit your needs for 
> > > MIPS. This address could be any address: code or data. If you want 
> > > something that can take an address like 0x1000 and you ask for its 
> > > AddressClass and it sees that its address class is 
> > > eAddressClassCodeAlternateISA, and then you change it to be "0x1001", 
> > > this will need to be a new format type.
> > >
> > > DumpAddress in FormatEntity.cpp is called for the following entities:
> > >
> > >   case Entry::Type::LineEntryStartAddress:
> > >   case Entry::Type::LineEntryEndAddress:
> > >   case Entry::Type::AddressFile:
> > >   case Entry::Type::AddressLoad:
> > >   case Entry::Type::AddressLoadOrFile:
> > >   case Entry::Type::FrameRegisterPC
> > >   
> > >
> > > So only the LineEntry ones should actually do what you did.
> >
> >
> > We need to display all these entities in compressed address format. How 
> > about a new MIPS specific function in Address and Target class which would 
> > do this.
> >
> > Address Address::GetCallableAddress(Target *target);
> >  lldb::addr_t Target::GetCallableAddress (lldb::addr_t load_addr, 
> > AddressClass addr_class);
>
>
> We already have this in Target:
>
>   lldb::addr_t
>   GetCallableLoadAddress (lldb::addr_t load_addr, lldb::AddressClass 
> addr_class = lldb::eAddressClassInvalid) const;
>   
>
> So the solution here will be to modify Address::Dump() such that it detects 
> when an address is eAddressClassCodeAlternateISA and when that happens it 
> checks if the ExecutionContext parameter is non NULL, and if so, extract the 
> target, and check the target's architecture is MIPS, then add the extra bit 
> when displaying this address. As it seems that we would always want to 
> describe a section offset address (lldb_private::Address object) in this way 
> to show the MicroMIPS address space bit, right?




In http://reviews.llvm.org/D12079#243390, @clayborg wrote:

> In http://reviews.llvm.org/D12079#242998, @jaydeep wrote:
>
> > In http://reviews.llvm.org/D12079#242742, @clayborg wrote:
> >
> > > So DumpAddress() in FormatEntity.cpp is a generic "dump any address by 
> > > describing it". You can't just change the code to suit your needs for 
> > > MIPS. This address could be any address: code or data. If you want 
> > > something that can take an address like 0x1000 and you ask for its 
> > > AddressClass and it sees that its address class is 
> > > eAddressClassCodeAlternateISA, and then you change it to be "0x1001", 
> > > this will need to be a new format type.
> > >
> > > DumpAddress in FormatEntity.cpp is called for the following entities:
> > >
> > >   case Entry::Type::LineEntryStartAddress:
> > >   case Entry::Type::LineEntryEndAddress:
> > >   case Entry::Type::AddressFile:
> > >   case Entry::Type::AddressLoad:
> > >   case Entry::Type::AddressLoadOrFile:
> > >   case Entry::Type::FrameRegisterPC
> > >   
> > >
> > > So only the LineEntry ones should actually do what you did.
> >
> >
> > We need to display all these entities in compressed address format. How 
> > about a new MIPS specific function in Address and Target class which would 
> > do this.
> >
> > Address Address::GetCallableAddress(Target *target);
> >  lldb::addr_t Target::GetCallableAddress (lldb::addr_t load_addr, 
> > AddressClass addr_class);
>
>
> We already have this in Target:
>
>   lldb::addr_t
>   GetCallableLoadAddress (lldb::addr_t load_addr, lldb::AddressClass 
> addr_class = lldb::eAddressClassInvalid) const;
>   
>
> So the solution here will be to modify Address::Dump() such that it detects 
> when an address is eAddressClassCodeAlternateISA and when that happens it 
> checks if the ExecutionContext parameter is non NULL, and if so, extract the 
> target, and check the target's architecture is MIPS, then add the extra bit 
> when displaying this address. As it seems that we would always want to 
> describe a section offset address (lldb_private::Address object) in this way 
> to show the MicroMIPS address space bit, right?


Yes.


Repository:
  rL LLVM

http://reviews.llvm.org/D12079



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D12079: [MIPS] microMIPS breakpoints, disassembly and compressed addresses

[Jaydeep Patil via lldb-commits]

jaydeep added a comment.

In http://reviews.llvm.org/D12079#242742, @clayborg wrote:

> So DumpAddress() in FormatEntity.cpp is a generic "dump any address by 
> describing it". You can't just change the code to suit your needs for MIPS. 
> This address could be any address: code or data. If you want something that 
> can take an address like 0x1000 and you ask for its AddressClass and it sees 
> that its address class is eAddressClassCodeAlternateISA, and then you change 
> it to be "0x1001", this will need to be a new format type.
>
> DumpAddress in FormatEntity.cpp is called for the following entities:
>
>   case Entry::Type::LineEntryStartAddress:
>   case Entry::Type::LineEntryEndAddress:
>   case Entry::Type::AddressFile:
>   case Entry::Type::AddressLoad:
>   case Entry::Type::AddressLoadOrFile:
>   case Entry::Type::FrameRegisterPC
>   
>
> So only the LineEntry ones should actually do what you did.


We need to display all these entities in compressed address format. How about a 
new MIPS specific function in Address and Target class which would do this.

Address Address::GetCallableAddress(Target *target);
lldb::addr_t Target::GetCallableAddress (lldb::addr_t load_addr, AddressClass 
addr_class);


Repository:
  rL LLVM

http://reviews.llvm.org/D12079



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D12079: [MIPS] microMIPS breakpoints, disassembly and compressed addresses

[Jaydeep Patil via lldb-commits]

jaydeep added a comment.

In http://reviews.llvm.org/D12079#242751, @clayborg wrote:

> Actually not a new format type, but an extra arg will need to be passed to 
> DumpAddress like "bool addr_is_callable".
>
> Can you explain something to me? In the following example:
>
>   0x8020067d <+0>:  addiusp -16
>   0x8020067f <+2>:  sw $fp, 12($sp)
>   0x80200681 <+4>:  move   $fp, $sp
>
>
> Is the addiusp actually at 0x8020067c in memory? Then we just display 
> 0x8020067d to let people know this is MicroMIPS?


Yes, addiusp is actually at 0x8020067c, but processor (when running in 
microMIPS mode) strips bit #0 while fetching it from memory. We should display 
it at 0x8020067d to let user know that this is microMIPS.


Repository:
  rL LLVM

http://reviews.llvm.org/D12079



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D12079: [MIPS] microMIPS breakpoints, disassembly and compressed addresses

[Jaydeep Patil via lldb-commits]

jaydeep updated this revision to Diff 34292.
jaydeep added a comment.

In this patch:

- Removed MIPS comment from generic code
- Used Target::GetOpcodeLoadAddress to fixup the PC

Regarding change in FormatEntity.cpp:

We still need to do this. The bit #0 of ‘addr’ has already been striped and 
thus it does not represent its true address space (microMIPS or MIPS). We need 
to call GetCallableLoadAddress here because we want to set the bit #0 of this 
address if it belongs to eAddressClassCodeAlternateISA.

This change displays the microMIPS disassembly (and other addresses) in compact 
address space:

  0x8020067d <+0>:  addiusp -16
  0x8020067f <+2>:  sw $fp, 12($sp)
  0x80200681 <+4>:  move   $fp, $sp

- thread #1: tid = 0x0001, 0x802006c5 micro.elf`foo(a=0, b=0) + 16 at 
micro.c:19, stop reason = breakpoint 2.1 frame #0: 0x802006c5 
micro.elf`foo(a=0, b=0) + 16 at micro.c:19

Without this change the microMIPS disassembly would be displayed in uncompact 
(MIPS) address space:

  0x8020067c <+0>:  addiusp -16
  0x8020067e <+2>:  sw $fp, 12($sp)
  0x80200680 <+4>:  move   $fp, $sp

- thread #1: tid = 0x0001, 0x802006c4 micro.elf`foo(a=0, b=0) + 16 at 
micro.c:19, stop reason = breakpoint 2.1 frame #0: 0x802006c4 
micro.elf`foo(a=0, b=0) + 16 at micro.c:19


Repository:
  rL LLVM

http://reviews.llvm.org/D12079

Files:
  source/Core/FormatEntity.cpp
  source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
  source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
  source/Target/RegisterContext.cpp
  source/Target/Target.cpp

Index: source/Target/Target.cpp
===
--- source/Target/Target.cpp
+++ source/Target/Target.cpp
@@ -2065,6 +2065,27 @@
 addr_t code_addr = load_addr;
 switch (m_arch.GetMachine())
 {
+case llvm::Triple::mips:
+case llvm::Triple::mipsel:
+case llvm::Triple::mips64:
+case llvm::Triple::mips64el:
+switch (addr_class)
+{
+case eAddressClassData:
+case eAddressClassDebug:
+return LLDB_INVALID_ADDRESS;
+
+case eAddressClassUnknown:
+case eAddressClassInvalid:
+case eAddressClassCode:
+case eAddressClassCodeAlternateISA:
+case eAddressClassRuntime:
+if ((code_addr & 2ull) || (addr_class == eAddressClassCodeAlternateISA))
+code_addr |= 1ull;
+break;
+}
+break;
+
 case llvm::Triple::arm:
 case llvm::Triple::thumb:
 switch (addr_class)
@@ -2110,6 +2131,10 @@
 addr_t opcode_addr = load_addr;
 switch (m_arch.GetMachine())
 {
+case llvm::Triple::mips:
+case llvm::Triple::mipsel:
+case llvm::Triple::mips64:
+case llvm::Triple::mips64el:
 case llvm::Triple::arm:
 case llvm::Triple::thumb:
 switch (addr_class)
Index: source/Target/RegisterContext.cpp
===
--- source/Target/RegisterContext.cpp
+++ source/Target/RegisterContext.cpp
@@ -20,6 +20,7 @@
 #include "lldb/Target/StackFrame.h"
 #include "lldb/Target/Process.h"
 #include "lldb/Target/Thread.h"
+#include "lldb/Target/Target.h"
 
 using namespace lldb;
 using namespace lldb_private;
@@ -103,7 +104,20 @@
 RegisterContext::GetPC(uint64_t fail_value)
 {
 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
-return ReadRegisterAsUnsigned (reg, fail_value);
+uint64_t pc = ReadRegisterAsUnsigned (reg, fail_value);
+
+if (pc != fail_value)
+{
+TargetSP target_sp = m_thread.CalculateTarget();
+if (target_sp)
+{
+Target *target = target_sp.get();
+if (target)
+pc = target->GetOpcodeLoadAddress (pc, eAddressClassCode);
+}
+}
+
+return pc;
 }
 
 bool
Index: source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
===
--- source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
+++ source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
@@ -1394,6 +1394,7 @@
 {
 LineTable* line_table;
 std::unique_ptr sequence_ap;
+ArchSpec arch;
 };
 
 //--
@@ -1422,8 +1423,20 @@
 info->sequence_ap.reset(line_table->CreateLineSequenceContainer());
 assert(info->sequence_ap.get());
 }
+
+/*
+ * MIPS:
+ * The SymbolContext may not have a valid target, thus we may not be able
+ * to call Address::GetOpcodeLoadAddress() which would clear the bit #0
+ * for MIPS. Use ArchSpec to clear the bit #0.
+*/
+lldb::addr_t file_addr = state.address;
+if (info->arch.GetMachine() == llvm::Triple::mips || info->arch.GetMachine() == llvm::Triple::mipsel
+   || info->arch.GetMachine() == llvm::Triple::mips64 || info->arch

Re: [Lldb-commits] [PATCH] D12079: [MIPS] microMIPS breakpoints, disassembly and compressed addresses

[Jaydeep Patil via lldb-commits]

jaydeep updated this revision to Diff 34199.
jaydeep added a comment.

In this patch:

The bit #0 has been cleared from addresses in the line tables. However we are 
relying upon ArchSpec instead of Target while clearing this bit in 
ParseDWARFLineTableCallback because SymbolContext may not have a valid target 
to call Address::GetOpcodeLoadAddress().

Bare-iron targets (like YAMON, IASim, Qemu) return compressed address (bit #0 
set) when process is stopped in microMIPS address space. For example: bit #0 of 
PC is set when a breakpoint is hit. This bit has been cleared while reading the 
PC in RegisterContext::GetPC(). This would help us find breakpoints set using 
GetOpcodeLoadAddress (bit #0 clear),

DisassemblerLLVMC::DisassemblerLLVMC has been modified to create 
m_alternate_disasm_ap for microMIPS. This would display disassembly in either 
compressed (bit #0 set) or uncompressed (bit #0 clear) address space based on 
ISA mode.


Repository:
  rL LLVM

http://reviews.llvm.org/D12079

Files:
  source/Core/FormatEntity.cpp
  source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
  source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
  source/Target/RegisterContext.cpp
  source/Target/Target.cpp

Index: source/Target/Target.cpp
===
--- source/Target/Target.cpp
+++ source/Target/Target.cpp
@@ -2065,6 +2065,27 @@
 addr_t code_addr = load_addr;
 switch (m_arch.GetMachine())
 {
+case llvm::Triple::mips:
+case llvm::Triple::mipsel:
+case llvm::Triple::mips64:
+case llvm::Triple::mips64el:
+switch (addr_class)
+{
+case eAddressClassData:
+case eAddressClassDebug:
+return LLDB_INVALID_ADDRESS;
+
+case eAddressClassUnknown:
+case eAddressClassInvalid:
+case eAddressClassCode:
+case eAddressClassCodeAlternateISA:
+case eAddressClassRuntime:
+if ((code_addr & 2ull) || (addr_class == eAddressClassCodeAlternateISA))
+code_addr |= 1ull;
+break;
+}
+break;
+
 case llvm::Triple::arm:
 case llvm::Triple::thumb:
 switch (addr_class)
@@ -2110,6 +2131,10 @@
 addr_t opcode_addr = load_addr;
 switch (m_arch.GetMachine())
 {
+case llvm::Triple::mips:
+case llvm::Triple::mipsel:
+case llvm::Triple::mips64:
+case llvm::Triple::mips64el:
 case llvm::Triple::arm:
 case llvm::Triple::thumb:
 switch (addr_class)
Index: source/Target/RegisterContext.cpp
===
--- source/Target/RegisterContext.cpp
+++ source/Target/RegisterContext.cpp
@@ -103,7 +103,24 @@
 RegisterContext::GetPC(uint64_t fail_value)
 {
 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
-return ReadRegisterAsUnsigned (reg, fail_value);
+uint64_t pc = ReadRegisterAsUnsigned (reg, fail_value);
+
+if (pc != fail_value)
+{
+/*
+ * MIPS:
+ * When a breakpoint is hit in microMIPS address space, bit #0 of the PC
+ * is set by the target (CallableLoadAddress). However there is no trace
+ * of bit #0 elsewhere in the debugger. Clear bit #0 so that we can find
+ * breakpoints etc. set using OpcodeLoadAddress.
+*/
+TargetSP target_sp = m_thread.CalculateTarget();
+Target *target = target_sp.get();
+Address addr (pc);
+pc = addr.GetOpcodeLoadAddress (target);
+}
+
+return pc;
 }
 
 bool
Index: source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
===
--- source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
+++ source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
@@ -1394,6 +1394,7 @@
 {
 LineTable* line_table;
 std::unique_ptr sequence_ap;
+ArchSpec arch;
 };
 
 //--
@@ -1422,8 +1423,20 @@
 info->sequence_ap.reset(line_table->CreateLineSequenceContainer());
 assert(info->sequence_ap.get());
 }
+
+/*
+ * MIPS:
+ * The SymbolContext may not have a valid target, thus we may not be able
+ * to call Address::GetOpcodeLoadAddress() which would clear the bit #0
+ * for MIPS. Use ArchSpec to clear the bit #0.
+*/
+lldb::addr_t file_addr = state.address;
+if (info->arch.GetMachine() == llvm::Triple::mips || info->arch.GetMachine() == llvm::Triple::mipsel
+   || info->arch.GetMachine() == llvm::Triple::mips64 || info->arch.GetMachine() == llvm::Triple::mips64el)
+file_addr = state.address & (~1ull);
+
 line_table->AppendLineEntryToSequence (info->sequence_ap.get(),
-   state.address,
+  

Re: [Lldb-commits] [PATCH] D12079: [MIPS] microMIPS breakpoints, disassembly and compressed addresses

[Jaydeep Patil via lldb-commits]

jaydeep added inline comments.


Comment at: source/Target/RegisterContext.cpp:106-116
@@ -105,3 +105,13 @@
 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, 
LLDB_REGNUM_GENERIC_PC);
-return ReadRegisterAsUnsigned (reg, fail_value);
+uint64_t pc = ReadRegisterAsUnsigned (reg, fail_value);
+
+if (pc != fail_value)
+{
+TargetSP target_sp = m_thread.CalculateTarget();
+Target *target = target_sp.get();
+Address addr (pc);
+pc = addr.GetOpcodeLoadAddress (target);
+}
+
+return pc;
 }

clayborg wrote:
> Bit #0 should be stripped from the PC before it is figured out and the frame 
> might need to track the address class, so this change shouldn't be needed. We 
> don't want extra bits floating around in our code that we have to strip 
> everywhere. This should be done as the stack frames are being created. The 
> frame will need to keep track of the address class in case the address 
> doesn't map back to a shared library (JITed code might not have a module 
> describing the code). So this code should be removed and the backtracer will 
> need to sanitize the addresses as the PC values are unwound.
The breakpoint is set on OpcodeAddress (bit #0 clear), but target returns 
CallableAddress (bit #0 set) when breakpoint is hit. 

Set using:
StoppointLocation (loc_id, addr.GetOpcodeLoadAddress(&owner.GetTarget()), 
hardware)

Find using:
addr_t pc = thread_sp->GetRegisterContext()->GetPC() + m_breakpoint_pc_offset;
lldb::BreakpointSiteSP bp_site_sp = 
thread_sp->GetProcess()->GetBreakpointSiteList().FindByAddress(pc);

We either need to clear bit #0 from the PC we get or need to set the breakpoint 
on CallableAddress (which would need LineTable in CallableAddress form). 






Repository:
  rL LLVM

http://reviews.llvm.org/D12079



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D12079: [MIPS] microMIPS breakpoints, disassembly and compressed addresses

[Jaydeep Patil via lldb-commits]

jaydeep updated this revision to Diff 33793.
jaydeep added a comment.

Added GetCallableFileAddress for MIPS


Repository:
  rL LLVM

http://reviews.llvm.org/D12079

Files:
  include/lldb/Core/Address.h
  include/lldb/Symbol/Function.h
  include/lldb/Target/Target.h
  source/Breakpoint/BreakpointResolver.cpp
  source/Breakpoint/BreakpointResolverName.cpp
  source/Core/Address.cpp
  source/Core/AddressResolverName.cpp
  source/Core/FormatEntity.cpp
  source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  source/Symbol/Function.cpp
  source/Symbol/SymbolContext.cpp
  source/Target/RegisterContext.cpp
  source/Target/Target.cpp
  source/Target/ThreadPlanStepInRange.cpp

Index: source/Target/ThreadPlanStepInRange.cpp
===
--- source/Target/ThreadPlanStepInRange.cpp
+++ source/Target/ThreadPlanStepInRange.cpp
@@ -283,7 +283,7 @@
 {
 func_start_address = sc.function->GetAddressRange().GetBaseAddress();
 if (curr_addr == func_start_address.GetLoadAddress(m_thread.CalculateTarget().get()))
-bytes_to_skip = sc.function->GetPrologueByteSize();
+bytes_to_skip = sc.function->GetPrologueByteSize(m_thread.CalculateTarget().get());
 }
 else if (sc.symbol)
 {
Index: source/Target/Target.cpp
===
--- source/Target/Target.cpp
+++ source/Target/Target.cpp
@@ -2060,11 +2060,50 @@
 }
 
 lldb::addr_t
+Target::GetCallableFileAddress (lldb::addr_t load_addr, AddressClass addr_class) const
+{
+addr_t code_addr = load_addr;
+switch (m_arch.GetMachine())
+{
+case llvm::Triple::mips:
+case llvm::Triple::mipsel:
+case llvm::Triple::mips64:
+case llvm::Triple::mips64el:
+switch (addr_class)
+{
+case eAddressClassData:
+case eAddressClassDebug:
+return LLDB_INVALID_ADDRESS;
+
+case eAddressClassUnknown:
+case eAddressClassInvalid:
+case eAddressClassCode:
+case eAddressClassCodeAlternateISA:
+case eAddressClassRuntime:
+if ((code_addr & 2ull) || (addr_class == eAddressClassCodeAlternateISA))
+code_addr |= 1ull;
+break;
+}
+break;
+
+default:
+break;
+}
+return code_addr;
+}
+
+lldb::addr_t
 Target::GetCallableLoadAddress (lldb::addr_t load_addr, AddressClass addr_class) const
 {
 addr_t code_addr = load_addr;
 switch (m_arch.GetMachine())
 {
+case llvm::Triple::mips:
+case llvm::Triple::mipsel:
+case llvm::Triple::mips64:
+case llvm::Triple::mips64el:
+return GetCallableFileAddress (load_addr, addr_class);
+
 case llvm::Triple::arm:
 case llvm::Triple::thumb:
 switch (addr_class)
@@ -2110,6 +2149,10 @@
 addr_t opcode_addr = load_addr;
 switch (m_arch.GetMachine())
 {
+case llvm::Triple::mips:
+case llvm::Triple::mipsel:
+case llvm::Triple::mips64:
+case llvm::Triple::mips64el:
 case llvm::Triple::arm:
 case llvm::Triple::thumb:
 switch (addr_class)
Index: source/Target/RegisterContext.cpp
===
--- source/Target/RegisterContext.cpp
+++ source/Target/RegisterContext.cpp
@@ -103,7 +103,17 @@
 RegisterContext::GetPC(uint64_t fail_value)
 {
 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
-return ReadRegisterAsUnsigned (reg, fail_value);
+uint64_t pc = ReadRegisterAsUnsigned (reg, fail_value);
+
+if (pc != fail_value)
+{
+TargetSP target_sp = m_thread.CalculateTarget();
+Target *target = target_sp.get();
+Address addr (pc);
+pc = addr.GetOpcodeLoadAddress (target);
+}
+
+return pc;
 }
 
 bool
Index: source/Symbol/SymbolContext.cpp
===
--- source/Symbol/SymbolContext.cpp
+++ source/Symbol/SymbolContext.cpp
@@ -23,6 +23,7 @@
 #include "lldb/Symbol/SymbolVendor.h"
 #include "lldb/Symbol/Variable.h"
 #include "lldb/Target/Target.h"
+#include "lldb/Target/ExecutionContext.h"
 
 using namespace lldb;
 using namespace lldb_private;
@@ -173,7 +174,14 @@
 
 if (addr.IsValid())
 {
-const addr_t function_offset = addr.GetOffset() - function->GetAddressRange().GetBaseAddress().GetOffset();
+Target *target = nullptr;
+if (exe_scope)
+{
+ExecutionContext exe_ctx;
+exe_scope->CalculateExecutionContext (exe_ctx);
+target = Target::GetTargetFromContexts (&exe_ctx, this);
+}
+const addr_t function_offset = addr.GetOffset() - function->GetAddressRange().GetBaseAddress().GetCallableFileAddress(target).GetOffset();
 if (show_func

Re: [Lldb-commits] [PATCH] D12356: [MIPS64] Emulate MSA branch instructions

[Jaydeep Patil via lldb-commits]

jaydeep accepted this revision.
jaydeep added a comment.
This revision is now accepted and ready to land.

Looks good to me


Repository:
  rL LLVM

http://reviews.llvm.org/D12356



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D12427: [LLDB][MIPS] Aligning code with rL245831

[Jaydeep Patil via lldb-commits]

jaydeep accepted this revision.
jaydeep added a comment.
This revision is now accepted and ready to land.

Looks good to me.


Repository:
  rL LLVM

http://reviews.llvm.org/D12427



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D12079: [MIPS] microMIPS breakpoints, disassembly and compressed addresses

[Jaydeep Patil via lldb-commits]

jaydeep updated this revision to Diff 33301.
jaydeep added a comment.

Addressed review comments.
Address conversions are handled in Address class. This is a reduced version of 
the original patch where address conversions are handled for breakpoints only.


Repository:
  rL LLVM

http://reviews.llvm.org/D12079

Files:
  include/lldb/Core/Address.h
  include/lldb/Symbol/Function.h
  source/Breakpoint/BreakpointResolver.cpp
  source/Breakpoint/BreakpointResolverName.cpp
  source/Core/Address.cpp
  source/Core/AddressResolverName.cpp
  source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  source/Symbol/Function.cpp
  source/Symbol/SymbolContext.cpp
  source/Target/RegisterContext.cpp
  source/Target/Target.cpp
  source/Target/ThreadPlanStepInRange.cpp

Index: source/Target/ThreadPlanStepInRange.cpp
===
--- source/Target/ThreadPlanStepInRange.cpp
+++ source/Target/ThreadPlanStepInRange.cpp
@@ -283,7 +283,7 @@
 {
 func_start_address = sc.function->GetAddressRange().GetBaseAddress();
 if (curr_addr == func_start_address.GetLoadAddress(m_thread.CalculateTarget().get()))
-bytes_to_skip = sc.function->GetPrologueByteSize();
+bytes_to_skip = sc.function->GetPrologueByteSize(m_thread.CalculateTarget().get());
 }
 else if (sc.symbol)
 {
Index: source/Target/Target.cpp
===
--- source/Target/Target.cpp
+++ source/Target/Target.cpp
@@ -2065,6 +2065,31 @@
 addr_t code_addr = load_addr;
 switch (m_arch.GetMachine())
 {
+case llvm::Triple::mips:
+case llvm::Triple::mipsel:
+case llvm::Triple::mips64:
+case llvm::Triple::mips64el:
+switch (addr_class)
+{
+case eAddressClassData:
+case eAddressClassDebug:
+return LLDB_INVALID_ADDRESS;
+
+case eAddressClassUnknown:
+case eAddressClassInvalid:
+case eAddressClassCode:
+case eAddressClassRuntime:
+case eAddressClassCodeAlternateISA:
+{
+uint32_t arch_flags = m_arch.GetFlags ();
+if ((arch_flags & ArchSpec::eMIPSAse_micromips) ||
+(arch_flags & ArchSpec::eMIPSAse_mips16))
+code_addr |= 1ull;
+break;
+}
+}
+break;
+
 case llvm::Triple::arm:
 case llvm::Triple::thumb:
 switch (addr_class)
@@ -2110,6 +2135,10 @@
 addr_t opcode_addr = load_addr;
 switch (m_arch.GetMachine())
 {
+case llvm::Triple::mips:
+case llvm::Triple::mipsel:
+case llvm::Triple::mips64:
+case llvm::Triple::mips64el:
 case llvm::Triple::arm:
 case llvm::Triple::thumb:
 switch (addr_class)
Index: source/Target/RegisterContext.cpp
===
--- source/Target/RegisterContext.cpp
+++ source/Target/RegisterContext.cpp
@@ -103,7 +103,17 @@
 RegisterContext::GetPC(uint64_t fail_value)
 {
 uint32_t reg = ConvertRegisterKindToRegisterNumber (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
-return ReadRegisterAsUnsigned (reg, fail_value);
+uint64_t pc = ReadRegisterAsUnsigned (reg, fail_value);
+
+if (pc != fail_value)
+{
+TargetSP target_sp = m_thread.CalculateTarget();
+Target *target = target_sp.get();
+Address addr (pc);
+pc = addr.GetOpcodeLoadAddress (target);
+}
+
+return pc;
 }
 
 bool
Index: source/Symbol/SymbolContext.cpp
===
--- source/Symbol/SymbolContext.cpp
+++ source/Symbol/SymbolContext.cpp
@@ -23,6 +23,7 @@
 #include "lldb/Symbol/SymbolVendor.h"
 #include "lldb/Symbol/Variable.h"
 #include "lldb/Target/Target.h"
+#include "lldb/Target/ExecutionContext.h"
 
 using namespace lldb;
 using namespace lldb_private;
@@ -173,7 +174,14 @@
 
 if (addr.IsValid())
 {
-const addr_t function_offset = addr.GetOffset() - function->GetAddressRange().GetBaseAddress().GetOffset();
+Target *target = nullptr;
+if (exe_scope)
+{
+ExecutionContext exe_ctx;
+exe_scope->CalculateExecutionContext (exe_ctx);
+target = Target::GetTargetFromContexts (&exe_ctx, this);
+}
+const addr_t function_offset = addr.GetOffset() - function->GetAddressRange().GetBaseAddress().GetCallableFileAddress(target).GetOffset();
 if (show_function_name == false)
 {
 // Print +offset even if offset is 0
Index: source/Symbol/Function.cpp
===
--- source/Symbol/Function.cpp
+++ source/Symbol/Function.cpp
@@ -555,7 +555,7 @@
 }
 
 uint32_t
-Function::GetPrologueByteSize ()
+

Re: [Lldb-commits] [PATCH] D12356: [MIPS64] Emulate MSA branch instructions

[Jaydeep Patil via lldb-commits]

jaydeep requested changes to this revision.
This revision now requires changes to proceed.


Comment at: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp:3117
@@ +3116,3 @@
+else
+target = pc + 4;
+

This should be pc + 8. If branch is not taken then we need to skip the delay 
slot.



Repository:
  rL LLVM

http://reviews.llvm.org/D12356



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [PATCH] D12079: [MIPS] microMIPS breakpoints, disassembly and compressed addresses

[Jaydeep Patil via lldb-commits]

jaydeep created this revision.
jaydeep added a reviewer: clayborg.
jaydeep added subscribers: lldb-commits, bhushan, sagar, mohit.bhakkad, 
nitesh.jain.
jaydeep set the repository for this revision to rL LLVM.

This patch enables setting of breakpoints and disassembly for microMIPS 
applications running on bare-iron targets like IASim.

MIPS uses bit #0 (ISA bit) of an address for ISA mode (1 for microMIPS/MIPS16 
and 0 for MIPS). The resulting address is called as compressed address when ISA 
bit is set. This allows processor to switch between microMIPS and MIPS without 
any need for special mode-control register. This bit is then cleared by the 
processor while fetching the instruction from memory. However, apart from 
.debug_line, none of the ELF/DWARF sections set the ISA bit. 

In this patch:
1)  The symbol table is recorded in the form of compressed address for 
microMIPS symbols, so that corresponding debug_line can be decoded properly.
2)  Memory read/write of compressed address has been handled


Repository:
  rL LLVM

http://reviews.llvm.org/D12079

Files:
  source/Core/Disassembler.cpp
  source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
  source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp

Index: source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
===
--- source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
+++ source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
@@ -1273,6 +1273,51 @@
 
 assert(func_type == NULL || func_type != DIE_IS_BEING_PARSED);
 
+/*
+ * MIPS:
+ * The bit #0 of an address is used for ISA mode (1 for microMIPS, 0 for MIPS).
+ * This allows processer to switch between microMIPS and MIPS without any need
+ * for special mode-control register. However, apart from .debug_line, none of
+ * the ELF/DWARF sections set the ISA bit (for symbol or section).
+ *
+ * Find first symbol with name func_name and type FUNC. If this is a microMIPS
+ * symbol then adjust func_range accordingly.
+*/
+ArchSpec arch;
+GetObjectFile()->GetArchitecture(arch);
+
+if (arch.GetMachine() == llvm::Triple::mips64
+|| arch.GetMachine() == llvm::Triple::mips64el
+|| arch.GetMachine() == llvm::Triple::mips
+|| arch.GetMachine() == llvm::Triple::mipsel)
+{
+Symbol *microsym = NULL;
+if (m_obj_file)
+{
+Symtab *symtab = m_obj_file->GetSymtab ();
+if (symtab)
+{
+lldb::LanguageType language = ParseCompileUnitLanguage(sc);
+microsym = symtab->FindFirstSymbolWithNameAndType (func_name.GetDemangledName(language),
+   eSymbolTypeCode,
+   Symtab::eDebugNo,
+   Symtab::eVisibilityAny);
+
+if (microsym != NULL)
+{
+lldb::addr_t addr = microsym->GetFileAddress();
+
+// If address is compressed then it is a microMIPS symbol
+if (addr & 1)
+{
+Address &compressed_addr = func_range.GetBaseAddress();
+compressed_addr.SetOffset (compressed_addr.GetOffset() | 1);
+}
+}
+}
+}
+}
+
 if (FixupAddress (func_range.GetBaseAddress()))
 {
 const user_id_t func_user_id = MakeUserID(die->GetOffset());
Index: source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
===
--- source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+++ source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
@@ -3169,7 +3169,8 @@
 user_id_t site_id = bp_site->GetID();
 
 // Get the breakpoint address
-const addr_t addr = bp_site->GetLoadAddress();
+const addr_t load_addr = bp_site->GetLoadAddress();
+addr_t addr = load_addr;
 
 // Log that a breakpoint was requested
 if (log)
@@ -3183,6 +3184,24 @@
 return error;
 }
 
+/*
+ * MIPS:
+ * If bit #0 of an address (ISA bit) is set, then this is microMIPS or MIPS16 address.
+ * Processor clears this bit before fetching the instruction from memory. Set this
+ * breakpoint at uncompressed address.
+*/
+const ArchSpec target_arch = GetTarget().GetArchitecture();
+if (target_arch.GetMachine() == llvm::Triple::mips |

Re: [Lldb-commits] [PATCH] D10596: [MIPS] MIPS32 branch emulation and single-stepping

[Jaydeep Patil via lldb-commits]

jaydeep closed this revision.
jaydeep added a comment.

Closed by commit http://reviews.llvm.org/rL240373


Repository:
  rL LLVM

http://reviews.llvm.org/D10596



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D11133: [MIPS] Detect MIPS application specific extensions like micromips

[Jaydeep Patil via lldb-commits]

jaydeep closed this revision.
jaydeep added a comment.

Closed by commit http://reviews.llvm.org/rL242381


Repository:
  rL LLVM

http://reviews.llvm.org/D11133



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D11455: [MIPS] Create Unix Signals based on target architecture

[Jaydeep Patil via lldb-commits]

jaydeep closed this revision.
jaydeep added a comment.

Closed by commit http://reviews.llvm.org/rL243618


Repository:
  rL LLVM

http://reviews.llvm.org/D11455



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D11519: [MIPS] Use qfThreadID if qC packet is not supported by target

[Jaydeep Patil via lldb-commits]

jaydeep closed this revision.
jaydeep added a comment.

Closed by commit http://reviews.llvm.org/rL244866


Repository:
  rL LLVM

http://reviews.llvm.org/D11519



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D11672: [MIPS] Handle false positives for MIPS hardware watchpoints

[Jaydeep Patil via lldb-commits]

jaydeep closed this revision.
jaydeep added a comment.

Closed by commit http://reviews.llvm.org/rL244864


Repository:
  rL LLVM

http://reviews.llvm.org/D11672



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D11747: [MIPS] Support standard GDB remote stop reply packet for watchpoint

[Jaydeep Patil via lldb-commits]

jaydeep closed this revision.
jaydeep added a comment.

Closed by commit http://reviews.llvm.org/rL244865


Repository:
  rL LLVM

http://reviews.llvm.org/D11747



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r244866 - [LLDB][MIPS] Use qfThreadID if qC packet is not supported by target

[Jaydeep Patil via lldb-commits]

Author: jaydeep
Date: Wed Aug 12 22:46:36 2015
New Revision: 244866

URL: http://llvm.org/viewvc/llvm-project?rev=244866&view=rev
Log:
[LLDB][MIPS] Use qfThreadID if qC packet is not supported by target
SUMMARY:
The patch uses qfThreadID to get the thread IDs if qC packet is not 
supported by target.

Reviewers: jingham, clayborg
Subscribers: nitesh.jain, mohit.bhakkad, sagar, bhushan and lldb-commits
Differential Revision: http://reviews.llvm.org/D11519

Modified:

lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp

Modified: 
lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp?rev=244866&r1=244865&r2=244866&view=diff
==
--- 
lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp 
(original)
+++ 
lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp 
Wed Aug 12 22:46:36 2015
@@ -1459,6 +1459,21 @@ GDBRemoteCommunicationClient::GetCurrent
 }
 }
 }
+
+// If we don't get a response for $qC, check if $qfThreadID gives us a 
result.
+if (m_curr_pid == LLDB_INVALID_PROCESS_ID)
+{
+std::vector thread_ids;
+bool sequence_mutex_unavailable;
+size_t size;
+size = GetCurrentThreadIDs (thread_ids, 
sequence_mutex_unavailable);
+if (size && sequence_mutex_unavailable == false)
+{
+m_curr_pid = thread_ids.front();
+m_curr_pid_is_valid = eLazyBoolYes;
+return m_curr_pid;
+}
+}
 }
 
 return LLDB_INVALID_PROCESS_ID;


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r244865 - [LLDB][MIPS] Support standard GDB remote stop reply packet for watchpoint

[Jaydeep Patil via lldb-commits]

Author: jaydeep
Date: Wed Aug 12 22:46:01 2015
New Revision: 244865

URL: http://llvm.org/viewvc/llvm-project?rev=244865&view=rev
Log:
[LLDB][MIPS] Support standard GDB remote stop reply packet for watchpoint
SUMMARY:
The patch supports TAAwatch:addr packet. The patch also sets 
m_watchpoints_trigger_after_instruction 
to eLazyBoolNo when qHostInfo or qWatchpointSupportInfo is not supported by 
the target.

Reviewers: jingham, clayborg
Subscribers: nitesh.jain, mohit.bhakkad, sagar, bhushan and lldb-commits
Differential Revision: http://reviews.llvm.org/D11747

Modified:

lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h
lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp

Modified: 
lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp?rev=244865&r1=244864&r2=244865&view=diff
==
--- 
lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp 
(original)
+++ 
lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp 
Wed Aug 12 22:46:01 2015
@@ -2473,26 +2473,45 @@ GDBRemoteCommunicationClient::GetWatchpo
 }
 
 lldb_private::Error
-GDBRemoteCommunicationClient::GetWatchpointSupportInfo (uint32_t &num, bool& 
after)
+GDBRemoteCommunicationClient::GetWatchpointSupportInfo (uint32_t &num, bool& 
after, const ArchSpec &arch)
 {
 Error error(GetWatchpointSupportInfo(num));
 if (error.Success())
-error = GetWatchpointsTriggerAfterInstruction(after);
+error = GetWatchpointsTriggerAfterInstruction(after, arch);
 return error;
 }
 
 lldb_private::Error
-GDBRemoteCommunicationClient::GetWatchpointsTriggerAfterInstruction (bool 
&after)
+GDBRemoteCommunicationClient::GetWatchpointsTriggerAfterInstruction (bool 
&after, const ArchSpec &arch)
 {
 Error error;
+llvm::Triple::ArchType atype = arch.GetMachine();
 
 // we assume watchpoints will happen after running the relevant opcode
 // and we only want to override this behavior if we have explicitly
 // received a qHostInfo telling us otherwise
 if (m_qHostInfo_is_valid != eLazyBoolYes)
-after = true;
+{
+// On targets like MIPS, watchpoint exceptions are always generated 
+// before the instruction is executed. The connected target may not 
+// support qHostInfo or qWatchpointSupportInfo packets.
+if (atype == llvm::Triple::mips || atype == llvm::Triple::mipsel
+|| atype == llvm::Triple::mips64 || atype == 
llvm::Triple::mips64el)
+after = false;
+else
+after = true;
+}
 else
+{
+// For MIPS, set m_watchpoints_trigger_after_instruction to 
eLazyBoolNo 
+// if it is not calculated before.
+if (m_watchpoints_trigger_after_instruction == eLazyBoolCalculate &&
+(atype == llvm::Triple::mips || atype == llvm::Triple::mipsel
+|| atype == llvm::Triple::mips64 || atype == 
llvm::Triple::mips64el))
+m_watchpoints_trigger_after_instruction = eLazyBoolNo;
+
 after = (m_watchpoints_trigger_after_instruction != eLazyBoolNo);
+}
 return error;
 }
 

Modified: 
lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h?rev=244865&r1=244864&r2=244865&view=diff
==
--- lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h 
(original)
+++ lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h 
Wed Aug 12 22:46:01 2015
@@ -287,10 +287,10 @@ public:
 GetWatchpointSupportInfo (uint32_t &num); 
 
 Error
-GetWatchpointSupportInfo (uint32_t &num, bool& after);
+GetWatchpointSupportInfo (uint32_t &num, bool& after, const ArchSpec 
&arch);
 
 Error
-GetWatchpointsTriggerAfterInstruction (bool &after);
+GetWatchpointsTriggerAfterInstruction (bool &after, const ArchSpec &arch);
 
 const ArchSpec &
 GetHostArchitecture ();

Modified: lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp?rev=244865&r1=244864&r2=244865&view=diff
==
--- lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp (original)
+++ lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp Wed Aug 
12 22:46:01 2015
@@ -2484,6 +2484,21 @@ ProcessGDBRemote::SetThreadStopInfo (Str
   

[Lldb-commits] [lldb] r244864 - [LLDB][MIPS] Handle false positives for MIPS hardware watchpoints

[Jaydeep Patil via lldb-commits]

Author: jaydeep
Date: Wed Aug 12 22:44:09 2015
New Revision: 244864

URL: http://llvm.org/viewvc/llvm-project?rev=244864&view=rev
Log:
[LLDB][MIPS] Handle false positives for MIPS hardware watchpoints
SUMMARY:
Last 3bits of the watchpoint address are masked by the kernel. For example, 
n is 
at 0x120010d00 and m is 0x120010d04. When a watchpoint is set at m, then 
watch 
exception is generated even when n is read/written. To handle this case, 
instruction 
at PC is emulated to find the base address of the load/store instruction. 
This address 
is then appended to the description of the stop-info packet. Client then 
reads this 
information to check whether the user has set a watchpoint on this address.

Reviewers: jingham, clayborg
Subscribers: nitesh.jain, mohit.bhakkad, sagar, bhushan and lldb-commits
Differential Revision: http://reviews.llvm.org/D11672

Modified:
lldb/trunk/include/lldb/Host/common/NativeRegisterContext.h
lldb/trunk/include/lldb/Target/StopInfo.h
lldb/trunk/source/Host/common/NativeRegisterContext.cpp
lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h
lldb/trunk/source/Plugins/Process/Linux/NativeThreadLinux.cpp
lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
lldb/trunk/source/Target/StopInfo.cpp

Modified: lldb/trunk/include/lldb/Host/common/NativeRegisterContext.h
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/Host/common/NativeRegisterContext.h?rev=244864&r1=244863&r2=244864&view=diff
==
--- lldb/trunk/include/lldb/Host/common/NativeRegisterContext.h (original)
+++ lldb/trunk/include/lldb/Host/common/NativeRegisterContext.h Wed Aug 12 
22:44:09 2015
@@ -111,6 +111,19 @@ public:
 virtual lldb::addr_t
 GetWatchpointAddress (uint32_t wp_index);
 
+// MIPS Linux kernel returns a masked address (last 3bits are masked)
+// when a HW watchpoint is hit. However user may not have set a watchpoint
+// on this address. This function emulates the instruction at PC and 
+// finds the base address used in the load/store instruction. This gives 
the 
+// exact address used to read/write the variable being watched.
+// For example:
+// 'n' is at 0x120010d00 and 'm' is 0x120010d04. When a watchpoint is set 
at 'm', 
+// then watch exception is generated even when 'n' is read/written. This 
function
+// returns address of 'n' so that client can check whether a watchpoint is 
set
+// on this address or not.
+virtual lldb::addr_t
+GetWatchpointHitAddress (uint32_t wp_index);
+
 virtual bool
 HardwareSingleStep (bool enable);
 

Modified: lldb/trunk/include/lldb/Target/StopInfo.h
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/Target/StopInfo.h?rev=244864&r1=244863&r2=244864&view=diff
==
--- lldb/trunk/include/lldb/Target/StopInfo.h (original)
+++ lldb/trunk/include/lldb/Target/StopInfo.h Wed Aug 12 22:44:09 2015
@@ -161,7 +161,7 @@ public:
 CreateStopReasonWithBreakpointSiteID (Thread &thread, lldb::break_id_t 
break_id, bool should_stop);
 
 static lldb::StopInfoSP
-CreateStopReasonWithWatchpointID (Thread &thread, lldb::break_id_t 
watch_id);
+CreateStopReasonWithWatchpointID (Thread &thread, lldb::break_id_t 
watch_id, lldb::addr_t watch_hit_addr = LLDB_INVALID_ADDRESS);
 
 static lldb::StopInfoSP
 CreateStopReasonWithSignal (Thread &thread, int signo, const char 
*description = nullptr);

Modified: lldb/trunk/source/Host/common/NativeRegisterContext.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Host/common/NativeRegisterContext.cpp?rev=244864&r1=244863&r2=244864&view=diff
==
--- lldb/trunk/source/Host/common/NativeRegisterContext.cpp (original)
+++ lldb/trunk/source/Host/common/NativeRegisterContext.cpp Wed Aug 12 22:44:09 
2015
@@ -334,6 +334,12 @@ NativeRegisterContext::GetWatchpointAddr
 return LLDB_INVALID_ADDRESS;
 }
 
+lldb::addr_t
+NativeRegisterContext::GetWatchpointHitAddress (uint32_t wp_index)
+{
+return LLDB_INVALID_ADDRESS;
+}
+
 bool
 NativeRegisterContext::HardwareSingleStep (bool enable)
 {

Modified: 
lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp?rev=244864&r1=244863&r2=244864&view=diff
==
--- lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInst

Re: [Lldb-commits] [PATCH] D11747: [MIPS] Support standard GDB remote stop reply packet for watchpoint

[Jaydeep Patil via lldb-commits]

jaydeep updated this revision to Diff 31919.
jaydeep added a comment.

Addressed review comments.


Repository:
  rL LLVM

http://reviews.llvm.org/D11747

Files:
  source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
  source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h
  source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp

Index: source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
===
--- source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+++ source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
@@ -2483,6 +2483,21 @@
 }
 }
 }
+else if (key.compare("watch") == 0 || key.compare("rwatch") == 0 || key.compare("awatch") == 0)
+{
+// Support standard GDB remote stop reply packet 'TAAwatch:addr'
+lldb::addr_t wp_addr = StringConvert::ToUInt64 (value.c_str(), LLDB_INVALID_ADDRESS, 16);
+WatchpointSP wp_sp = GetTarget().GetWatchpointList().FindByAddress(wp_addr);
+uint32_t wp_index = LLDB_INVALID_INDEX32;
+
+if (wp_sp)
+wp_index = wp_sp->GetHardwareIndex();
+
+reason = "watchpoint";
+StreamString ostr;
+ostr.Printf("%" PRIu64 " %" PRIu32, wp_addr, wp_index);
+description = ostr.GetString().c_str();
+}
 else if (key.size() == 2 && ::isxdigit(key[0]) && ::isxdigit(key[1]))
 {
 uint32_t reg = StringConvert::ToUInt32 (key.c_str(), UINT32_MAX, 16);
@@ -3084,7 +3099,7 @@
 Error
 ProcessGDBRemote::GetWatchpointSupportInfo (uint32_t &num, bool& after)
 {
-Error error (m_gdb_comm.GetWatchpointSupportInfo (num, after));
+Error error (m_gdb_comm.GetWatchpointSupportInfo (num, after, GetTarget().GetArchitecture()));
 return error;
 }
 
Index: source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h
===
--- source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h
+++ source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h
@@ -287,10 +287,10 @@
 GetWatchpointSupportInfo (uint32_t &num); 
 
 Error
-GetWatchpointSupportInfo (uint32_t &num, bool& after);
+GetWatchpointSupportInfo (uint32_t &num, bool& after, const ArchSpec &arch);
 
 Error
-GetWatchpointsTriggerAfterInstruction (bool &after);
+GetWatchpointsTriggerAfterInstruction (bool &after, const ArchSpec &arch);
 
 const ArchSpec &
 GetHostArchitecture ();
Index: source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
===
--- source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
+++ source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
@@ -2473,26 +2473,45 @@
 }
 
 lldb_private::Error
-GDBRemoteCommunicationClient::GetWatchpointSupportInfo (uint32_t &num, bool& after)
+GDBRemoteCommunicationClient::GetWatchpointSupportInfo (uint32_t &num, bool& after, const ArchSpec &arch)
 {
 Error error(GetWatchpointSupportInfo(num));
 if (error.Success())
-error = GetWatchpointsTriggerAfterInstruction(after);
+error = GetWatchpointsTriggerAfterInstruction(after, arch);
 return error;
 }
 
 lldb_private::Error
-GDBRemoteCommunicationClient::GetWatchpointsTriggerAfterInstruction (bool &after)
+GDBRemoteCommunicationClient::GetWatchpointsTriggerAfterInstruction (bool &after, const ArchSpec &arch)
 {
 Error error;
+llvm::Triple::ArchType atype = arch.GetMachine();
 
 // we assume watchpoints will happen after running the relevant opcode
 // and we only want to override this behavior if we have explicitly
 // received a qHostInfo telling us otherwise
 if (m_qHostInfo_is_valid != eLazyBoolYes)
-after = true;
+{
+// On targets like MIPS, watchpoint exceptions are always generated 
+// before the instruction is executed. The connected target may not 
+// support qHostInfo or qWatchpointSupportInfo packets.
+if (atype == llvm::Triple::mips || atype == llvm::Triple::mipsel
+|| atype == llvm::Triple::mips64 || atype == llvm::Triple::mips64el)
+after = false;
+else
+after = true;
+}
 else
+{
+// For MIPS, set m_watchpoints_trigger_after_instruction to eLazyBoolNo 
+// if it is not calculated before.
+if (m_watchpoints_trigger_after_instruction == eLazyBoolCalculate &&
+(atype == llvm::Triple::mips || atype == llvm::Triple::mipsel
+|| atype == llvm::Triple::mips64 || atype == llvm::Triple::mips64el))
+m_watchpoints_trigger_after_instruction = eLazyBoolNo;
+
 after = (m_watchpoints_trigge

Re: [Lldb-commits] [PATCH] D11747: [MIPS] Support standard GDB remote stop reply packet for watchpoint

[Jaydeep Patil via lldb-commits]

jaydeep added inline comments.


Comment at: source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp:2498-2500
@@ +2497,5 @@
+reason = "watchpoint";
+std::ostringstream ostr;
+ostr << wp_addr << " " << wp_index;
+description = ostr.str();
+}

clayborg wrote:
> Not sure if you need to do this, try not setting this and see how the 
> description comes out. The watchpoint stop info should set this correctly?
We need "watchpoint" in the description so that SetThreadStopInfo can create 
CreateStopReasonWithWatchpointID.
 


Repository:
  rL LLVM

http://reviews.llvm.org/D11747



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D11519: [MIPS] Use qfThreadID if qC packet is not supported by target

[Jaydeep Patil via lldb-commits]

jaydeep updated this revision to Diff 31908.
jaydeep added a comment.

Addressed review comments.


Repository:
  rL LLVM

http://reviews.llvm.org/D11519

Files:
  source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp

Index: source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
===
--- source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
+++ source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
@@ -1459,6 +1459,21 @@
 }
 }
 }
+
+// If we don't get a response for $qC, check if $qfThreadID gives us a 
result.
+if (m_curr_pid == LLDB_INVALID_PROCESS_ID)
+{
+std::vector thread_ids;
+bool sequence_mutex_unavailable;
+size_t size;
+size = GetCurrentThreadIDs (thread_ids, 
sequence_mutex_unavailable);
+if (size && sequence_mutex_unavailable == false)
+{
+m_curr_pid = thread_ids.front();
+m_curr_pid_is_valid = eLazyBoolYes;
+return m_curr_pid;
+}
+}
 }
 
 return LLDB_INVALID_PROCESS_ID;


Index: source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
===
--- source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
+++ source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
@@ -1459,6 +1459,21 @@
 }
 }
 }
+
+// If we don't get a response for $qC, check if $qfThreadID gives us a result.
+if (m_curr_pid == LLDB_INVALID_PROCESS_ID)
+{
+std::vector thread_ids;
+bool sequence_mutex_unavailable;
+size_t size;
+size = GetCurrentThreadIDs (thread_ids, sequence_mutex_unavailable);
+if (size && sequence_mutex_unavailable == false)
+{
+m_curr_pid = thread_ids.front();
+m_curr_pid_is_valid = eLazyBoolYes;
+return m_curr_pid;
+}
+}
 }
 
 return LLDB_INVALID_PROCESS_ID;
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D11672: [MIPS] Handle false positives for MIPS hardware watchpoints

[Jaydeep Patil via lldb-commits]

jaydeep added a comment.

Hi jingham,
Could you please review this?
Thanks.


Repository:
  rL LLVM

http://reviews.llvm.org/D11672



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D11519: [MIPS] Use qfThreadID if qC packet is not supported by target

[Jaydeep Patil via lldb-commits]

jaydeep added inline comments.


Comment at: 
source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp:1463-1465
@@ +1462,5 @@
+
+// If we don't get a response for $qC, check if $qfThreadID gives us a 
result.
+if (m_curr_pid == LLDB_INVALID_PROCESS_ID && ostype == 
llvm::Triple::UnknownOS)
+{
+std::vector thread_ids;

clayborg wrote:
> How does checking the "ostype" with unknown help us to determine if this is 
> an OS where pid == tid? What if the user makes their target with:
> 
> ```
> (lldb) target create --arch x86_64-pc-linux ...
> ```
> 
> Then this code doesn't trigger?
In this case the target we are connected to is a bare-iron which does not 
support qC packet. Here pid == tid and only way to get this is using 
qfThreadID. If arch is likely to be unset during many of these calls then we 
need to find alternate way to implement this.




Repository:
  rL LLVM

http://reviews.llvm.org/D11519



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D11672: [MIPS] Handle false positives for MIPS hardware watchpoints

[Jaydeep Patil via lldb-commits]

jaydeep added a comment.

Could you please find some time to review this?
Thanks.


Repository:
  rL LLVM

http://reviews.llvm.org/D11672



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D11747: [MIPS] Support standard GDB remote stop reply packet for watchpoint

[Jaydeep Patil via lldb-commits]

jaydeep added a comment.

Could you please find some time to review this?
Thanks.


Repository:
  rL LLVM

http://reviews.llvm.org/D11747



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits