[Lldb-commits] [PATCH] D108937: [lldb] [ABI/X86] Support combining xmm* and ymm*h regs into ymm*

[Michał Górny via Phabricator via lldb-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG5352ea4a721e: [lldb] [ABI/X86] Support combining xmm* and 
ymm*h regs into ymm* (authored by mgorny).
Herald added a project: LLDB.

Changed prior to commit:
  https://reviews.llvm.org/D108937?vs=380453&id=380607#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108937/new/

https://reviews.llvm.org/D108937

Files:
  lldb/include/lldb/lldb-private-types.h
  lldb/source/Plugins/ABI/X86/ABIX86.cpp
  lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
  lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
  lldb/source/Target/DynamicRegisterInfo.cpp
  lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py

Index: lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
===
--- lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
+++ lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
@@ -199,6 +199,29 @@
 self.match("register read st0",
["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"])
 
+self.runCmd("register write xmm0 \"{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 "
+"0xf8 0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "
+"0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xb1 0xb2 0xb3 0xb4 0xb5 "
+"0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"])
+
+self.runCmd("register write ymm0h \"{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 "
+"0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "
+"0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xef 0xee 0xed 0xec 0xeb "
+"0xea 0xe9 0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"])
+
+self.runCmd("register write ymm0 \"{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 "
+"0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 "
+"0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec "
+"0xed 0xee 0xef}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 "
+"0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 "
+"0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef}"])
+
 @skipIfXmlSupportMissing
 @skipIfRemote
 @skipIfLLVMTargetMissing("X86")
@@ -361,6 +384,29 @@
 self.match("register read st0",
["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"])
 
+self.runCmd("register write xmm0 \"{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 "
+"0xf8 0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "
+"0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xb1 0xb2 0xb3 0xb4 0xb5 "
+"0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"])
+
+self.runCmd("register write ymm0h \"{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 "
+"0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "
+"0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xef 0xee 0xed 0xec 0xeb "
+"0xea 0xe9 0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"])
+
+self.runCmd("register write ymm0 \"{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 "
+"0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 "
+"0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec "
+"0xed 0xee 0xef}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 "
+"0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 "
+"0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef}"])
+
 @skipIfXmlSupportMissing
 @skipIfRemote
 @skipIfLLVMTargetMissing("AArch64")
Index: lldb/source/Target/DynamicRegisterInfo.cpp
===
--- lldb/source/Target/DynamicRegisterInfo.cpp
+++ lldb/source/Target/DynamicRegisterInfo.cpp
@@ -463,20 +463,11 @@
 m_sets[set].registers = m_set_reg_nums[set].data();
   }
 
-  // sort and unique all value registers and make sure each is terminated with
-  // LLDB_INVALID_REGNUM
+  // make sure value_regs are terminated with LLDB_INVALID_REGNUM
 
   for (reg_to_regs_map::iterator pos = m_value_regs_map.be

[Lldb-commits] [PATCH] D108937: [lldb] [ABI/X86] Support combining xmm* and ymm*h regs into ymm*

[Pavel Labath via Phabricator via lldb-commits]

labath accepted this revision.
labath added a comment.
This revision is now accepted and ready to land.

Looks good. Thanks for your patience.




Comment at: lldb/source/Plugins/ABI/X86/ABIX86.cpp:36-52
+enum RegKind {
+  GPR32,
   GPR16,
   GPR8h,
   GPR8,
+  MM,
+  YMM_YMMh,

anonymous namespace here


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[Lldb-commits] [PATCH] D108937: [lldb] [ABI/X86] Support combining xmm* and ymm*h regs into ymm*

[Michał Górny via Phabricator via lldb-commits]

mgorny updated this revision to Diff 380453.
mgorny retitled this revision from "[lldb] [ABI/X86] Support combining xmm* and 
ymm*h regs into ymm* [WIP]" to "[lldb] [ABI/X86] Support combining xmm* and 
ymm*h regs into ymm*".
mgorny added a comment.

Major refactoring of the generator function.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108937/new/

https://reviews.llvm.org/D108937

Files:
  lldb/include/lldb/lldb-private-types.h
  lldb/source/Plugins/ABI/X86/ABIX86.cpp
  lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
  lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
  lldb/source/Target/DynamicRegisterInfo.cpp
  lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py

Index: lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
===
--- lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
+++ lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
@@ -199,6 +199,29 @@
 self.match("register read st0",
["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"])
 
+self.runCmd("register write xmm0 \"{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 "
+"0xf8 0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "
+"0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xb1 0xb2 0xb3 0xb4 0xb5 "
+"0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"])
+
+self.runCmd("register write ymm0h \"{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 "
+"0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "
+"0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xef 0xee 0xed 0xec 0xeb "
+"0xea 0xe9 0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"])
+
+self.runCmd("register write ymm0 \"{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 "
+"0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 "
+"0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec "
+"0xed 0xee 0xef}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 "
+"0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 "
+"0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef}"])
+
 @skipIfXmlSupportMissing
 @skipIfRemote
 @skipIfLLVMTargetMissing("X86")
@@ -361,6 +384,29 @@
 self.match("register read st0",
["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"])
 
+self.runCmd("register write xmm0 \"{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 "
+"0xf8 0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "
+"0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xb1 0xb2 0xb3 0xb4 0xb5 "
+"0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"])
+
+self.runCmd("register write ymm0h \"{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 "
+"0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "
+"0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xef 0xee 0xed 0xec 0xeb "
+"0xea 0xe9 0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"])
+
+self.runCmd("register write ymm0 \"{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 "
+"0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 "
+"0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec "
+"0xed 0xee 0xef}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 "
+"0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 "
+"0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef}"])
+
 @skipIfXmlSupportMissing
 @skipIfRemote
 @skipIfLLVMTargetMissing("AArch64")
Index: lldb/source/Target/DynamicRegisterInfo.cpp
===
--- lldb/source/Target/DynamicRegisterInfo.cpp
+++ lldb/source/Target/DynamicRegisterInfo.cpp
@@ -463,20 +463,11 @@
 m_sets[set].registers = m_set_reg_nums[set].data();
   }
 
-  // sort and unique all value registers and make sure each is terminated with
-  // LLDB_INVALID_REGNUM
+  // make sure value_regs are terminated with LLDB_INVALID_REGNUM
 
   for (reg_to_regs_map::iterator pos = m_value_regs_map.begin(),
  end = m_val

[Lldb-commits] [PATCH] D108937: [lldb] [ABI/X86] Support combining xmm* and ymm*h regs into ymm* [WIP]

[Pavel Labath via Phabricator via lldb-commits]

labath added a comment.

I think I like this.




Comment at: lldb/source/Plugins/ABI/X86/ABIX86.cpp:261
+assert(subreg->base_index);
+uint32_t base_index = subreg->base_index.getValue();
+assert(base_index < regs.size());

llvm::Optional gives you this assert for free.



Comment at: lldb/source/Plugins/ABI/X86/ABIX86.cpp:321
+  llvm::SmallDenseSet subreg_name_set;
+  std::array, RegKindCount> subreg_by_kind;
+

It would be nice to have some comment explaining the purpose of this variable 
(I guess its there to ensure matching register order).


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[Lldb-commits] [PATCH] D108937: [lldb] [ABI/X86] Support combining xmm* and ymm*h regs into ymm* [WIP]

[Michał Górny via Phabricator via lldb-commits]

mgorny updated this revision to Diff 380366.
mgorny marked an inline comment as done.
mgorny retitled this revision from "[lldb] [ABI/X86] Support combining xmm* and 
ymm*h regs into ymm*" to "[lldb] [ABI/X86] Support combining xmm* and ymm*h 
regs into ymm* [WIP]".
mgorny added a comment.

WIP alternative approach.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108937/new/

https://reviews.llvm.org/D108937

Files:
  lldb/include/lldb/lldb-private-types.h
  lldb/source/Plugins/ABI/X86/ABIX86.cpp
  lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
  lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
  lldb/source/Target/DynamicRegisterInfo.cpp
  lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py

Index: lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
===
--- lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
+++ lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
@@ -199,6 +199,29 @@
 self.match("register read st0",
["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"])
 
+self.runCmd("register write xmm0 \"{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 "
+"0xf8 0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "
+"0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xb1 0xb2 0xb3 0xb4 0xb5 "
+"0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"])
+
+self.runCmd("register write ymm0h \"{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 "
+"0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "
+"0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xef 0xee 0xed 0xec 0xeb "
+"0xea 0xe9 0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"])
+
+self.runCmd("register write ymm0 \"{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 "
+"0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 "
+"0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec "
+"0xed 0xee 0xef}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 "
+"0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 "
+"0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef}"])
+
 @skipIfXmlSupportMissing
 @skipIfRemote
 @skipIfLLVMTargetMissing("X86")
@@ -361,6 +384,29 @@
 self.match("register read st0",
["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"])
 
+self.runCmd("register write xmm0 \"{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 "
+"0xf8 0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "
+"0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xb1 0xb2 0xb3 0xb4 0xb5 "
+"0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"])
+
+self.runCmd("register write ymm0h \"{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 "
+"0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "
+"0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xef 0xee 0xed 0xec 0xeb "
+"0xea 0xe9 0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"])
+
+self.runCmd("register write ymm0 \"{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 "
+"0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 "
+"0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec "
+"0xed 0xee 0xef}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 "
+"0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 "
+"0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef}"])
+
 @skipIfXmlSupportMissing
 @skipIfRemote
 @skipIfLLVMTargetMissing("AArch64")
Index: lldb/source/Target/DynamicRegisterInfo.cpp
===
--- lldb/source/Target/DynamicRegisterInfo.cpp
+++ lldb/source/Target/DynamicRegisterInfo.cpp
@@ -463,20 +463,11 @@
 m_sets[set].registers = m_set_reg_nums[set].data();
   }
 
-  // sort and unique all value registers and make sure each is terminated with
-  // LLDB_INVALID_REGNUM
+  // make sure value_regs are terminated with LLDB_INVALID_REGNUM
 
   for (reg_to_regs_map::iterator pos = m_value_regs_map.begin(),
   

[Lldb-commits] [PATCH] D108937: [lldb] [ABI/X86] Support combining xmm* and ymm*h regs into ymm*

[Michał Górny via Phabricator via lldb-commits]

mgorny marked an inline comment as done.
mgorny added a comment.

I'm not sure what exactly you're proposing and whether your proposal would work 
but I think it's a step in the right direction.

Let's start by reiterating what we need:

1. A way to iterate over all subregisters of given `RegKind`, sorted by base 
register index, yielding base register index and subregister name 
(`map>`.
2. A way to match register name against all *expected* subregisters in order to 
abort if any of them exists (`set`).
3. A way to match register name against all known base registers and store 
their indices (`map`).
4. We should be able to construct all of the above from some readable input.




Comment at: lldb/source/Plugins/ABI/X86/ABIX86.cpp:171
+  "xmm14",
+  "xmm15",
+  }};

labath wrote:
> For a simple list like this, I'd probably remove the trailing comma to have 
> clang-format format it more succinctly.
Heh, I was wondering why clang-format chooses one format sometimes, and the 
other sometimes but it wouldn't occur to me that it's due to the trailing comma 
;-).


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[Lldb-commits] [PATCH] D108937: [lldb] [ABI/X86] Support combining xmm* and ymm*h regs into ymm*

[Pavel Labath via Phabricator via lldb-commits]

labath added a comment.

I like the solution with multiple value_regs.

However, I am wondering if instead of the various piecemeal maps we couldn't 
just have one uber-map to rule them all. I'm imagining something like

  enum (class?) RegKind { GPR, FPR, XMM, ...};
  struct RegData {
size_t index;
StringRef name;
SmallVector subregs;
  };
  
  map, RegData> reg_map = makeRegMap(); // whichever 
kind of a map
  // or possibly, map> = ...
  
  for (const auto &kv : reg_map)
subreg_name_set.insert(kv.second.subregs.begin(), kv.second.subregs.end());
  
  for (const auto &x : llvm::enumerate(regs)) {
llvm::StringRef reg_name = x.value().name.GetStringRef();
if (llvm::is_contained(subreg_name_set, reg_name))
  return;
if (Optional> reg = get_reg(reg_name))
  reg_map[reg].index = x.index(); 
  }
  
  ...

This would allow us to factor out two tedious jobs (constructing the register 
map and identifying registers) into separate functions, leaving only the only 
(simplified, I hope) core logic for the main function. The `get_reg` function 
could use whichever method is easiest for the translation of register names, or 
even a combination of methods (a StringSwitch for gprs and some consume_fronts 
for the regularly-named registers).

WDYT?




Comment at: lldb/source/Plugins/ABI/X86/ABIX86.cpp:171
+  "xmm14",
+  "xmm15",
+  }};

For a simple list like this, I'd probably remove the trailing comma to have 
clang-format format it more succinctly.


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https://reviews.llvm.org/D108937

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[Lldb-commits] [PATCH] D108937: [lldb] [ABI/X86] Support combining xmm* and ymm*h regs into ymm*

[Michał Górny via Phabricator via lldb-commits]

mgorny updated this revision to Diff 380058.
mgorny retitled this revision from "[lldb] [Process/gdb-remote] Support 
combining xmm* and ymm*h regs into ymm*" to "[lldb] [ABI/X86] Support combining 
xmm* and ymm*h regs into ymm*".
mgorny added a comment.

Rebase to use the new `ABIX86::AugmentRegisterInfo()` API.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108937/new/

https://reviews.llvm.org/D108937

Files:
  lldb/include/lldb/lldb-private-types.h
  lldb/source/Plugins/ABI/X86/ABIX86.cpp
  lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
  lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
  lldb/source/Target/DynamicRegisterInfo.cpp
  lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py

Index: lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
===
--- lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
+++ lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
@@ -199,6 +199,29 @@
 self.match("register read st0",
["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"])
 
+self.runCmd("register write xmm0 \"{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 "
+"0xf8 0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "
+"0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xb1 0xb2 0xb3 0xb4 0xb5 "
+"0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"])
+
+self.runCmd("register write ymm0h \"{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 "
+"0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "
+"0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xef 0xee 0xed 0xec 0xeb "
+"0xea 0xe9 0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"])
+
+self.runCmd("register write ymm0 \"{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 "
+"0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 "
+"0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec "
+"0xed 0xee 0xef}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 "
+"0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 "
+"0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef}"])
+
 @skipIfXmlSupportMissing
 @skipIfRemote
 @skipIfLLVMTargetMissing("X86")
@@ -361,6 +384,29 @@
 self.match("register read st0",
["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"])
 
+self.runCmd("register write xmm0 \"{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 "
+"0xf8 0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "
+"0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xb1 0xb2 0xb3 0xb4 0xb5 "
+"0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"])
+
+self.runCmd("register write ymm0h \"{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 "
+"0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "
+"0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xef 0xee 0xed 0xec 0xeb "
+"0xea 0xe9 0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"])
+
+self.runCmd("register write ymm0 \"{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 "
+"0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 "
+"0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec "
+"0xed 0xee 0xef}\"")
+self.match("register read ymm0",
+   ["ymm0 = {0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 "
+"0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 "
+"0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef}"])
+
 @skipIfXmlSupportMissing
 @skipIfRemote
 @skipIfLLVMTargetMissing("AArch64")
Index: lldb/source/Target/DynamicRegisterInfo.cpp
===
--- lldb/source/Target/DynamicRegisterInfo.cpp
+++ lldb/source/Target/DynamicRegisterInfo.cpp
@@ -463,20 +463,11 @@
 m_sets[set].registers = m_set_reg_nums[set].data();
   }
 
-  // sort and unique all value registers and make sure each is terminated with
-  // LLDB_INVALID_REGNUM
+  // make sure value_regs are terminated with LLDB_INVALID_REGNUM
 
   for (reg_to_regs_map::iterator pos = m_value_regs_map.begin(),