[llvm-branch-commits] [llvm] 45ad6fa - [JITLink] Use edge kind names for fixups in EHFrameEdgeFixer.

[Lang Hames via llvm-branch-commits]

Author: Lang Hames
Date: 2021-01-24T15:38:04+11:00
New Revision: 45ad6fac6ad0dea2a1f7a1c6b65b64d230757667

URL: 
https://github.com/llvm/llvm-project/commit/45ad6fac6ad0dea2a1f7a1c6b65b64d230757667
DIFF: 
https://github.com/llvm/llvm-project/commit/45ad6fac6ad0dea2a1f7a1c6b65b64d230757667.diff

LOG: [JITLink] Use edge kind names for fixups in EHFrameEdgeFixer.

Previously FDE field names were used, but the fixup kind used for a field can
vary based on the pointer encoding.

This change will improve readability / maintainability when EH-frame support is
added to JITLink/ELF.

Added: 


Modified: 
llvm/lib/ExecutionEngine/JITLink/EHFrameSupport.cpp
llvm/lib/ExecutionEngine/JITLink/EHFrameSupportImpl.h
llvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp

Removed: 




diff  --git a/llvm/lib/ExecutionEngine/JITLink/EHFrameSupport.cpp 
b/llvm/lib/ExecutionEngine/JITLink/EHFrameSupport.cpp
index 7a89476687d2..8b730bc23ce0 100644
--- a/llvm/lib/ExecutionEngine/JITLink/EHFrameSupport.cpp
+++ b/llvm/lib/ExecutionEngine/JITLink/EHFrameSupport.cpp
@@ -119,10 +119,9 @@ Error EHFrameSplitter::processBlock(LinkGraph &G, Block &B,
 }
 
 EHFrameEdgeFixer::EHFrameEdgeFixer(StringRef EHFrameSectionName,
-   Edge::Kind FDEToCIE, Edge::Kind 
FDEToPCBegin,
-   Edge::Kind FDEToLSDA)
-: EHFrameSectionName(EHFrameSectionName), FDEToCIE(FDEToCIE),
-  FDEToPCBegin(FDEToPCBegin), FDEToLSDA(FDEToLSDA) {}
+   Edge::Kind Delta64, Edge::Kind NegDelta32)
+: EHFrameSectionName(EHFrameSectionName), Delta64(Delta64),
+  NegDelta32(NegDelta32) {}
 
 Error EHFrameEdgeFixer::operator()(LinkGraph &G) {
   auto *EHFrame = G.findSectionByName(EHFrameSectionName);
@@ -419,7 +418,7 @@ Error EHFrameEdgeFixer::processFDE(ParseContext &PC, Block 
&B,
   else
 return CIEInfoOrErr.takeError();
   assert(CIEInfo->CIESymbol && "CIEInfo has no CIE symbol set");
-  B.addEdge(FDEToCIE, RecordOffset + CIEDeltaFieldOffset,
+  B.addEdge(NegDelta32, RecordOffset + CIEDeltaFieldOffset,
 *CIEInfo->CIESymbol, 0);
 } else {
   LLVM_DEBUG({
@@ -459,8 +458,7 @@ Error EHFrameEdgeFixer::processFDE(ParseContext &PC, Block 
&B,
   auto PCBeginSym = getOrCreateSymbol(PC, PCBegin);
   if (!PCBeginSym)
 return PCBeginSym.takeError();
-  B.addEdge(FDEToPCBegin, RecordOffset + PCBeginFieldOffset, *PCBeginSym,
-0);
+  B.addEdge(Delta64, RecordOffset + PCBeginFieldOffset, *PCBeginSym, 0);
   PCBeginBlock = &PCBeginSym->getBlock();
 } else {
   auto &EI = PCEdgeItr->second;
@@ -521,7 +519,7 @@ Error EHFrameEdgeFixer::processFDE(ParseContext &PC, Block 
&B,
<< formatv("{0:x16}", RecordAddress + LSDAFieldOffset)
<< " to LSDA at " << formatv("{0:x16}", LSDA) << "\n";
   });
-  B.addEdge(FDEToLSDA, RecordOffset + LSDAFieldOffset, *LSDASym, 0);
+  B.addEdge(Delta64, RecordOffset + LSDAFieldOffset, *LSDASym, 0);
 } else {
   LLVM_DEBUG({
 auto &EI = LSDAEdgeItr->second;

diff  --git a/llvm/lib/ExecutionEngine/JITLink/EHFrameSupportImpl.h 
b/llvm/lib/ExecutionEngine/JITLink/EHFrameSupportImpl.h
index a8cd32c664dc..83f27a285998 100644
--- a/llvm/lib/ExecutionEngine/JITLink/EHFrameSupportImpl.h
+++ b/llvm/lib/ExecutionEngine/JITLink/EHFrameSupportImpl.h
@@ -40,8 +40,8 @@ class EHFrameSplitter {
 /// edges.
 class EHFrameEdgeFixer {
 public:
-  EHFrameEdgeFixer(StringRef EHFrameSectionName, Edge::Kind FDEToCIE,
-   Edge::Kind FDEToPCBegin, Edge::Kind FDEToLSDA);
+  EHFrameEdgeFixer(StringRef EHFrameSectionName, Edge::Kind Delta64,
+   Edge::Kind NegDelta32);
   Error operator()(LinkGraph &G);
 
 private:
@@ -101,9 +101,8 @@ class EHFrameEdgeFixer {
   Expected getOrCreateSymbol(ParseContext &PC, JITTargetAddress 
Addr);
 
   StringRef EHFrameSectionName;
-  Edge::Kind FDEToCIE;
-  Edge::Kind FDEToPCBegin;
-  Edge::Kind FDEToLSDA;
+  Edge::Kind Delta64;
+  Edge::Kind NegDelta32;
 };
 
 } // end namespace jitlink

diff  --git a/llvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp 
b/llvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp
index e32bf847014b..24559cc7e772 100644
--- a/llvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp
+++ b/llvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp
@@ -670,7 +670,7 @@ void link_MachO_x86_64(std::unique_ptr G,
 // Add eh-frame passses.
 Config.PrePrunePasses.push_back(EHFrameSplitter("__eh_frame"));
 Config.PrePrunePasses.push_back(
-EHFrameEdgeFixer("__eh_frame", NegDelta32, Delta64, Delta64));
+EHFrameEdgeFixer("__eh_frame", Delta64, NegDelta32));
 
 // Add a mark-live pass.
 if (auto MarkLive = Ctx->getMarkLivePass(G->getTargetTriple()))



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[llvm-branch-commits] [llvm] 2a4acf3 - [AVR] Optimize 8-bit int shift

[Ben Shi via llvm-branch-commits]

Author: Ben Shi
Date: 2021-01-24T11:04:37+08:00
New Revision: 2a4acf3ea8db19981284468c354aea2835fbfa08

URL: 
https://github.com/llvm/llvm-project/commit/2a4acf3ea8db19981284468c354aea2835fbfa08
DIFF: 
https://github.com/llvm/llvm-project/commit/2a4acf3ea8db19981284468c354aea2835fbfa08.diff

LOG: [AVR] Optimize 8-bit int shift

Reviewed By: dylanmckay

Differential Revision: https://reviews.llvm.org/D90678

Added: 


Modified: 
llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
llvm/lib/Target/AVR/AVRISelLowering.cpp
llvm/lib/Target/AVR/AVRISelLowering.h
llvm/lib/Target/AVR/AVRInstrInfo.td
llvm/test/CodeGen/AVR/shift.ll
llvm/test/CodeGen/AVR/smul-with-overflow.ll

Removed: 




diff  --git a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp 
b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
index d10f0148cb58..a48d3d134bb5 100644
--- a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
@@ -1476,6 +1476,111 @@ bool AVRExpandPseudo::expand(Block &MBB, 
BlockIt MBBI) {
   return true;
 }
 
+template <>
+bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) {
+  MachineInstr &MI = *MBBI;
+  Register DstReg = MI.getOperand(0).getReg();
+  bool DstIsDead = MI.getOperand(0).isDead();
+  bool DstIsKill = MI.getOperand(1).isKill();
+  bool ImpIsDead = MI.getOperand(2).isDead();
+
+  // ror r24
+  // clr r24
+  // ror r24
+
+  buildMI(MBB, MBBI, AVR::RORRd)
+  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+  .addReg(DstReg, getKillRegState(DstIsKill));
+
+  buildMI(MBB, MBBI, AVR::EORRdRr)
+  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+  .addReg(DstReg, getKillRegState(DstIsKill))
+  .addReg(DstReg, getKillRegState(DstIsKill));
+
+  auto MIRRC =
+  buildMI(MBB, MBBI, AVR::RORRd)
+  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+  .addReg(DstReg, getKillRegState(DstIsKill));
+
+  if (ImpIsDead)
+MIRRC->getOperand(2).setIsDead();
+
+  // SREG is always implicitly killed
+  MIRRC->getOperand(3).setIsKill();
+
+  MI.eraseFromParent();
+  return true;
+}
+
+template <>
+bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) {
+  MachineInstr &MI = *MBBI;
+  Register DstReg = MI.getOperand(0).getReg();
+  bool DstIsDead = MI.getOperand(0).isDead();
+  bool DstIsKill = MI.getOperand(1).isKill();
+  bool ImpIsDead = MI.getOperand(2).isDead();
+
+  // rol r24
+  // clr r24
+  // rol r24
+
+  buildMI(MBB, MBBI, AVR::ADCRdRr)
+  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+  .addReg(DstReg, getKillRegState(DstIsKill))
+  .addReg(DstReg, getKillRegState(DstIsKill));
+
+  buildMI(MBB, MBBI, AVR::EORRdRr)
+  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+  .addReg(DstReg, getKillRegState(DstIsKill))
+  .addReg(DstReg, getKillRegState(DstIsKill));
+
+  auto MIRRC =
+  buildMI(MBB, MBBI, AVR::ADCRdRr)
+  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+  .addReg(DstReg, getKillRegState(DstIsKill))
+  .addReg(DstReg, getKillRegState(DstIsKill));
+
+  if (ImpIsDead)
+MIRRC->getOperand(3).setIsDead();
+
+  // SREG is always implicitly killed
+  MIRRC->getOperand(4).setIsKill();
+
+  MI.eraseFromParent();
+  return true;
+}
+
+template <>
+bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) {
+  MachineInstr &MI = *MBBI;
+  Register DstReg = MI.getOperand(0).getReg();
+  bool DstIsDead = MI.getOperand(0).isDead();
+  bool DstIsKill = MI.getOperand(1).isKill();
+  bool ImpIsDead = MI.getOperand(2).isDead();
+
+  // lsl r24
+  // sbc r24, r24
+
+  buildMI(MBB, MBBI, AVR::ADDRdRr)
+  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+  .addReg(DstReg, getKillRegState(DstIsKill))
+  .addReg(DstReg, getKillRegState(DstIsKill));
+
+  auto MIRRC = buildMI(MBB, MBBI, AVR::SBCRdRr)
+  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+  .addReg(DstReg, getKillRegState(DstIsKill))
+  .addReg(DstReg, getKillRegState(DstIsKill));
+
+  if (ImpIsDead)
+MIRRC->getOperand(3).setIsDead();
+
+  // SREG is always implicitly killed
+  MIRRC->getOperand(4).setIsKill();
+
+  MI.eraseFromParent();
+  return true;
+}
+
 template <> bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   Register DstLoReg, DstHiReg;
@@ -1697,6 +1802,9 @@ bool AVRExpandPseudo::expandMI(Block &MBB, BlockIt MBBI) {
 EXPAND(AVR::RORWRd);
 EXPAND(AVR::ROLWRd);
 EXPAND(AVR::ASRWRd);
+EXPAND(AVR::LSLB7Rd);
+EXPAND(AVR::LSRB7Rd);
+EXPAND(AVR::ASRB7Rd);
 EXPAND(AVR::SEXT);
 EXPAND(AVR::ZEXT);
 EXPAND(AVR::SPREAD);

diff  --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp 
b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index d919e08e468a..3e7c2984655a 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AV

[llvm-branch-commits] [llvm] b890faf - [OpenMPIRBuilder] Silence compiler warning. NFC.

[Michael Kruse via llvm-branch-commits]

Author: Michael Kruse
Date: 2021-01-23T21:00:37-06:00
New Revision: b890fafe672c01daac4ca2b8f740cd0cade78060

URL: 
https://github.com/llvm/llvm-project/commit/b890fafe672c01daac4ca2b8f740cd0cade78060
DIFF: 
https://github.com/llvm/llvm-project/commit/b890fafe672c01daac4ca2b8f740cd0cade78060.diff

LOG: [OpenMPIRBuilder] Silence compiler warning. NFC.

Address the compiler warning
OMPIRBuilder.cpp:1232:27: comparison of integers of different signs: 'size_t' 
(aka 'unsigned long') and 'int' [-Wsign-compare]

Added: 


Modified: 
llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp

Removed: 




diff  --git a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp 
b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
index e70847b2f02c..1f67aecb57e9 100644
--- a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+++ b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
@@ -1228,9 +1228,9 @@ static void 
removeUnusedBlocksFromParent(ArrayRef BBs) {
 std::vector
 OpenMPIRBuilder::tileLoops(DebugLoc DL, ArrayRef Loops,
ArrayRef TileSizes) {
-  int NumLoops = Loops.size();
-  assert(TileSizes.size() == NumLoops &&
+  assert(TileSizes.size() == Loops.size() &&
  "Must pass as many tile sizes as there are loops");
+  int NumLoops = Loops.size();
   assert(NumLoops >= 1 && "At least one loop to tile required");
 
   CanonicalLoopInfo *OutermostLoop = Loops.front();



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[llvm-branch-commits] [llvm] b7dee66 - [OpenMPIRBuilder] Implement tileLoops.

[Michael Kruse via llvm-branch-commits]

Author: Michael Kruse
Date: 2021-01-23T19:39:29-06:00
New Revision: b7dee667b64ff7dea66b483a35883190798c7d72

URL: 
https://github.com/llvm/llvm-project/commit/b7dee667b64ff7dea66b483a35883190798c7d72
DIFF: 
https://github.com/llvm/llvm-project/commit/b7dee667b64ff7dea66b483a35883190798c7d72.diff

LOG: [OpenMPIRBuilder] Implement tileLoops.

The  tileLoops method implements the code generation part of the tile directive 
introduced in OpenMP 5.1. It takes a list of loops forming a loop nest, tiles 
it, and returns the CanonicalLoopInfo representing the generated loops.

The implementation takes n CanonicalLoopInfos, n tile size Values and returns 
2*n new CanonicalLoopInfos. The input CanonicalLoopInfos are invalidated and 
BBs not reused in the new loop nest removed from the function.

In a modified version of D76342, I was able to correctly compile and execute a 
tiled loop nest.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D92974

Added: 


Modified: 
llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
llvm/lib/IR/BasicBlock.cpp
llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp

Removed: 




diff  --git a/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h 
b/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
index 8e95226d3895..22204d9a9ccb 100644
--- a/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
+++ b/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
@@ -300,6 +300,53 @@ class OpenMPIRBuilder {
bool NeedsBarrier,
Value *Chunk = nullptr);
 
+  /// Tile a loop nest.
+  ///
+  /// Tiles the loops of \p Loops by the tile sizes in \p TileSizes. Loops in
+  /// \p/ Loops must be perfectly nested, from outermost to innermost loop
+  /// (i.e. Loops.front() is the outermost loop). The trip count llvm::Value
+  /// of every loop and every tile sizes must be usable in the outermost
+  /// loop's preheader. This implies that the loop nest is rectangular.
+  ///
+  /// Example:
+  /// \code
+  ///   for (int i = 0; i < 15; ++i) // Canonical loop "i"
+  /// for (int j = 0; j < 14; ++j) // Canonical loop "j"
+  /// body(i, j);
+  /// \endcode
+  ///
+  /// After tiling with Loops={i,j} and TileSizes={5,7}, the loop is changed to
+  /// \code
+  ///   for (int i1 = 0; i1 < 3; ++i1)
+  /// for (int j1 = 0; j1 < 2; ++j1)
+  ///   for (int i2 = 0; i2 < 5; ++i2)
+  /// for (int j2 = 0; j2 < 7; ++j2)
+  ///   body(i1*3+i2, j1*3+j2);
+  /// \endcode
+  ///
+  /// The returned vector are the loops {i1,j1,i2,j2}. The loops i1 and j1 are
+  /// referred to the floor, and the loops i2 and j2 are the tiles. Tiling also
+  /// handles non-constant trip counts, non-constant tile sizes and trip counts
+  /// that are not multiples of the tile size. In the latter case the tile loop
+  /// of the last floor-loop iteration will have fewer iterations than 
specified
+  /// as its tile size.
+  ///
+  ///
+  /// @param DLDebug location for instructions added by tiling, for
+  ///  instance the floor- and tile trip count computation.
+  /// @param Loops Loops to tile. The CanonicalLoopInfo objects are
+  ///  invalidated by this method, i.e. should not used after
+  ///  tiling.
+  /// @param TileSizes For each loop in \p Loops, the tile size for that
+  ///  dimensions.
+  ///
+  /// \returns A list of generated loops. Contains twice as many loops as the
+  ///  input loop nest; the first half are the floor loops and the
+  ///  second half are the tile loops.
+  std::vector
+  tileLoops(DebugLoc DL, ArrayRef Loops,
+ArrayRef TileSizes);
+
   /// Generator for '#omp flush'
   ///
   /// \param Loc The location where the flush directive was encountered
@@ -729,6 +776,12 @@ class CanonicalLoopInfo {
   BasicBlock *Exit;
   BasicBlock *After;
 
+  /// Add the control blocks of this loop to \p BBs.
+  ///
+  /// This does not include any block from the body, including the one returned
+  /// by getBody().
+  void collectControlBlocks(SmallVectorImpl &BBs);
+
 public:
   /// The preheader ensures that there is only a single edge entering the loop.
   /// Code that must be execute before any loop iteration can be emitted here,
@@ -781,6 +834,14 @@ class CanonicalLoopInfo {
 return IndVarPHI;
   }
 
+  /// Return the type of the induction variable (and the trip count).
+  Type *getIndVarType() const { return getIndVar()->getType(); }
+
+  /// Return the insertion point for user code before the loop.
+  OpenMPIRBuilder::InsertPointTy getPreheaderIP() const {
+return {Preheader, std::prev(Preheader->end())};
+  };
+
   /// Return the insertion point for user code in the body.
   OpenMPIRBuilder::InsertPointTy getBodyIP() const {
 ret

[llvm-branch-commits] [llvm] c7d5d8f - [RISCV] Group some Zbs isel patterns together and remove a stale comment. NFC

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2021-01-23T16:45:05-08:00
New Revision: c7d5d8fa33a0f23b262b695d17fdffdefa8dc940

URL: 
https://github.com/llvm/llvm-project/commit/c7d5d8fa33a0f23b262b695d17fdffdefa8dc940
DIFF: 
https://github.com/llvm/llvm-project/commit/c7d5d8fa33a0f23b262b695d17fdffdefa8dc940.diff

LOG: [RISCV] Group some Zbs isel patterns together and remove a stale comment. 
NFC

Added: 


Modified: 
llvm/lib/Target/RISCV/RISCVInstrInfoB.td

Removed: 




diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index 8740e61b1ee1..9940063d5f9a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -725,6 +725,9 @@ def : Pat<(or GPR:$rs1, BSETINVMask:$mask),
   (BSETI GPR:$rs1, (BSETINVXForm imm:$mask))>;
 def : Pat<(xor GPR:$rs1, BSETINVMask:$mask),
   (BINVI GPR:$rs1, (BSETINVXForm imm:$mask))>;
+
+def : Pat<(and (srl GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1)),
+  (BEXTI GPR:$rs1, uimmlog2xlen:$shamt)>;
 }
 
 let Predicates = [HasStdExtZbp] in {
@@ -743,12 +746,6 @@ def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
   (RORI GPR:$rs1, (ImmROTL2R uimmlog2xlen:$shamt))>;
 }
 
-// We don't pattern-match sbclri[w], sbseti[w], sbinvi[w] because they are
-// pattern-matched by simple andi, ori, and xori.
-let Predicates = [HasStdExtZbs] in
-def : Pat<(and (srl GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1)),
-  (BEXTI GPR:$rs1, uimmlog2xlen:$shamt)>;
-
 def riscv_grevi: SDNode<"RISCVISD::GREVI", SDTIntBinOp, []>;
 def riscv_greviw   : SDNode<"RISCVISD::GREVIW", SDTIntBinOp, []>;
 def riscv_gorci: SDNode<"RISCVISD::GORCI", SDTIntBinOp, []>;



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[llvm-branch-commits] [libcxx] 92bb81a - [SystemZ][ZOS] Provide PATH_MAX macro for libcxx

[Zbigniew Sarbinowski via llvm-branch-commits]

Author: Zbigniew Sarbinowski
Date: 2021-01-24T00:29:39Z
New Revision: 92bb81aac1f16e2e9633d101b8b3f83d9c91dd48

URL: 
https://github.com/llvm/llvm-project/commit/92bb81aac1f16e2e9633d101b8b3f83d9c91dd48
DIFF: 
https://github.com/llvm/llvm-project/commit/92bb81aac1f16e2e9633d101b8b3f83d9c91dd48.diff

LOG: [SystemZ][ZOS] Provide PATH_MAX macro for libcxx

Defining PATH_MAX to _XOPEN_PATH_MAX which is the closest macro available on 
z/OS.
Note that this value is 1024 which is 4 times smaller from same macro on Linux.

Reviewed By: #libc, ldionne, hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D92110

Added: 


Modified: 
libcxx/src/filesystem/operations.cpp

Removed: 




diff  --git a/libcxx/src/filesystem/operations.cpp 
b/libcxx/src/filesystem/operations.cpp
index 7db2d1ff0074..50a895dc2fae 100644
--- a/libcxx/src/filesystem/operations.cpp
+++ b/libcxx/src/filesystem/operations.cpp
@@ -634,7 +634,11 @@ path __canonical(path const& orig_p, error_code* ec) {
 return err.report(capture_errno());
   return {hold.get()};
 #else
-  char buff[PATH_MAX + 1];
+  #if defined(__MVS__) && !defined(PATH_MAX)
+char buff[ _XOPEN_PATH_MAX + 1 ];
+  #else
+char buff[PATH_MAX + 1];
+  #endif
   char* ret;
   if ((ret = ::realpath(p.c_str(), buff)) == nullptr)
 return err.report(capture_errno());



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[llvm-branch-commits] [llvm] 998057e - [RISCV] Add isel patterns to remove masks on SLO/SRO shift amounts.

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2021-01-23T15:57:41-08:00
New Revision: 998057ec06ae7e0fb1e0be0f2702df4d6338a128

URL: 
https://github.com/llvm/llvm-project/commit/998057ec06ae7e0fb1e0be0f2702df4d6338a128
DIFF: 
https://github.com/llvm/llvm-project/commit/998057ec06ae7e0fb1e0be0f2702df4d6338a128.diff

LOG: [RISCV] Add isel patterns to remove masks on SLO/SRO shift amounts.

Added: 


Modified: 
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/rv32Zbp.ll
llvm/test/CodeGen/RISCV/rv64Zbp.ll

Removed: 




diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index f075699c17f0..8740e61b1ee1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -694,9 +694,9 @@ def : Pat<(xor GPR:$rs1, (not GPR:$rs2)), (XNOR GPR:$rs1, 
GPR:$rs2)>;
 } // Predicates = [HasStdExtZbbOrZbp]
 
 let Predicates = [HasStdExtZbp] in {
-def : Pat<(not (shl (not GPR:$rs1), GPR:$rs2)),
+def : Pat<(not (shiftop (not GPR:$rs1), GPR:$rs2)),
   (SLO GPR:$rs1, GPR:$rs2)>;
-def : Pat<(not (srl (not GPR:$rs1), GPR:$rs2)),
+def : Pat<(not (shiftop (not GPR:$rs1), GPR:$rs2)),
   (SRO GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbp]
 
@@ -960,9 +960,9 @@ def : Pat<(add (SLLIUWPat GPR:$rs1, (XLenVT 3)), GPR:$rs2),
 } // Predicates = [HasStdExtZba, IsRV64]
 
 let Predicates = [HasStdExtZbp, IsRV64] in {
-def : Pat<(not (riscv_sllw (not GPR:$rs1), GPR:$rs2)),
+def : Pat<(not (shiftopw (not GPR:$rs1), GPR:$rs2)),
   (SLOW GPR:$rs1, GPR:$rs2)>;
-def : Pat<(not (riscv_srlw (not GPR:$rs1), GPR:$rs2)),
+def : Pat<(not (shiftopw (not GPR:$rs1), GPR:$rs2)),
   (SROW GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 

diff  --git a/llvm/test/CodeGen/RISCV/rv32Zbp.ll 
b/llvm/test/CodeGen/RISCV/rv32Zbp.ll
index 8fc772931f3a..de315dfb2d5a 100644
--- a/llvm/test/CodeGen/RISCV/rv32Zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv32Zbp.ll
@@ -39,13 +39,11 @@ define i32 @slo_i32_mask(i32 %a, i32 %b) nounwind {
 ;
 ; RV32IB-LABEL: slo_i32_mask:
 ; RV32IB:   # %bb.0:
-; RV32IB-NEXT:andi a1, a1, 31
 ; RV32IB-NEXT:slo a0, a0, a1
 ; RV32IB-NEXT:ret
 ;
 ; RV32IBP-LABEL: slo_i32_mask:
 ; RV32IBP:   # %bb.0:
-; RV32IBP-NEXT:andi a1, a1, 31
 ; RV32IBP-NEXT:slo a0, a0, a1
 ; RV32IBP-NEXT:ret
   %neg = xor i32 %a, -1
@@ -243,13 +241,11 @@ define i32 @sro_i32_mask(i32 %a, i32 %b) nounwind {
 ;
 ; RV32IB-LABEL: sro_i32_mask:
 ; RV32IB:   # %bb.0:
-; RV32IB-NEXT:andi a1, a1, 31
 ; RV32IB-NEXT:sro a0, a0, a1
 ; RV32IB-NEXT:ret
 ;
 ; RV32IBP-LABEL: sro_i32_mask:
 ; RV32IBP:   # %bb.0:
-; RV32IBP-NEXT:andi a1, a1, 31
 ; RV32IBP-NEXT:sro a0, a0, a1
 ; RV32IBP-NEXT:ret
   %neg = xor i32 %a, -1

diff  --git a/llvm/test/CodeGen/RISCV/rv64Zbp.ll 
b/llvm/test/CodeGen/RISCV/rv64Zbp.ll
index 243ebc17a86b..d2191afd5b79 100644
--- a/llvm/test/CodeGen/RISCV/rv64Zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv64Zbp.ll
@@ -86,13 +86,11 @@ define i64 @slo_i64_mask(i64 %a, i64 %b) nounwind {
 ;
 ; RV64IB-LABEL: slo_i64_mask:
 ; RV64IB:   # %bb.0:
-; RV64IB-NEXT:andi a1, a1, 63
 ; RV64IB-NEXT:slo a0, a0, a1
 ; RV64IB-NEXT:ret
 ;
 ; RV64IBP-LABEL: slo_i64_mask:
 ; RV64IBP:   # %bb.0:
-; RV64IBP-NEXT:andi a1, a1, 63
 ; RV64IBP-NEXT:slo a0, a0, a1
 ; RV64IBP-NEXT:ret
   %neg = xor i64 %a, -1
@@ -182,13 +180,11 @@ define i64 @sro_i64_mask(i64 %a, i64 %b) nounwind {
 ;
 ; RV64IB-LABEL: sro_i64_mask:
 ; RV64IB:   # %bb.0:
-; RV64IB-NEXT:andi a1, a1, 63
 ; RV64IB-NEXT:sro a0, a0, a1
 ; RV64IB-NEXT:ret
 ;
 ; RV64IBP-LABEL: sro_i64_mask:
 ; RV64IBP:   # %bb.0:
-; RV64IBP-NEXT:andi a1, a1, 63
 ; RV64IBP-NEXT:sro a0, a0, a1
 ; RV64IBP-NEXT:ret
   %neg = xor i64 %a, -1



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[llvm-branch-commits] [llvm] 5a73daf - [RISCV] Add test cases for SRO/SLO with shift amounts masked to bitwidth-1. NFC

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2021-01-23T15:45:51-08:00
New Revision: 5a73daf907873a8757213932f814361a59f02da5

URL: 
https://github.com/llvm/llvm-project/commit/5a73daf907873a8757213932f814361a59f02da5
DIFF: 
https://github.com/llvm/llvm-project/commit/5a73daf907873a8757213932f814361a59f02da5.diff

LOG: [RISCV] Add test cases for SRO/SLO with shift amounts masked to 
bitwidth-1. NFC

The sro/slo instructions ignore extra bits in the shift amount,
so we can ignore the mask just like we do for sll, srl, and sra.

Added: 


Modified: 
llvm/test/CodeGen/RISCV/rv32Zbp.ll
llvm/test/CodeGen/RISCV/rv64Zbp.ll

Removed: 




diff  --git a/llvm/test/CodeGen/RISCV/rv32Zbp.ll 
b/llvm/test/CodeGen/RISCV/rv32Zbp.ll
index 7e2c6ad46a15..8fc772931f3a 100644
--- a/llvm/test/CodeGen/RISCV/rv32Zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv32Zbp.ll
@@ -29,6 +29,32 @@ define i32 @slo_i32(i32 %a, i32 %b) nounwind {
   ret i32 %neg1
 }
 
+define i32 @slo_i32_mask(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: slo_i32_mask:
+; RV32I:   # %bb.0:
+; RV32I-NEXT:not a0, a0
+; RV32I-NEXT:sll a0, a0, a1
+; RV32I-NEXT:not a0, a0
+; RV32I-NEXT:ret
+;
+; RV32IB-LABEL: slo_i32_mask:
+; RV32IB:   # %bb.0:
+; RV32IB-NEXT:andi a1, a1, 31
+; RV32IB-NEXT:slo a0, a0, a1
+; RV32IB-NEXT:ret
+;
+; RV32IBP-LABEL: slo_i32_mask:
+; RV32IBP:   # %bb.0:
+; RV32IBP-NEXT:andi a1, a1, 31
+; RV32IBP-NEXT:slo a0, a0, a1
+; RV32IBP-NEXT:ret
+  %neg = xor i32 %a, -1
+  %and = and i32 %b, 31
+  %shl = shl i32 %neg, %and
+  %neg1 = xor i32 %shl, -1
+  ret i32 %neg1
+}
+
 ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
 ; don't have yet any matching bit manipulation instructions on RV32.
 ; This test is presented here in case future expansions of the experimental-b
@@ -39,12 +65,12 @@ define i64 @slo_i64(i64 %a, i64 %b) nounwind {
 ; RV32I:   # %bb.0:
 ; RV32I-NEXT:addi a3, a2, -32
 ; RV32I-NEXT:not a0, a0
-; RV32I-NEXT:bltz a3, .LBB1_2
+; RV32I-NEXT:bltz a3, .LBB2_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:mv a2, zero
 ; RV32I-NEXT:sll a1, a0, a3
-; RV32I-NEXT:j .LBB1_3
-; RV32I-NEXT:  .LBB1_2:
+; RV32I-NEXT:j .LBB2_3
+; RV32I-NEXT:  .LBB2_2:
 ; RV32I-NEXT:not a1, a1
 ; RV32I-NEXT:sll a1, a1, a2
 ; RV32I-NEXT:addi a3, zero, 31
@@ -53,7 +79,7 @@ define i64 @slo_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-NEXT:srl a3, a4, a3
 ; RV32I-NEXT:or a1, a1, a3
 ; RV32I-NEXT:sll a2, a0, a2
-; RV32I-NEXT:  .LBB1_3:
+; RV32I-NEXT:  .LBB2_3:
 ; RV32I-NEXT:not a1, a1
 ; RV32I-NEXT:not a0, a2
 ; RV32I-NEXT:ret
@@ -83,12 +109,12 @@ define i64 @slo_i64(i64 %a, i64 %b) nounwind {
 ; RV32IBP:   # %bb.0:
 ; RV32IBP-NEXT:addi a3, a2, -32
 ; RV32IBP-NEXT:not a0, a0
-; RV32IBP-NEXT:bltz a3, .LBB1_2
+; RV32IBP-NEXT:bltz a3, .LBB2_2
 ; RV32IBP-NEXT:  # %bb.1:
 ; RV32IBP-NEXT:mv a2, zero
 ; RV32IBP-NEXT:sll a1, a0, a3
-; RV32IBP-NEXT:j .LBB1_3
-; RV32IBP-NEXT:  .LBB1_2:
+; RV32IBP-NEXT:j .LBB2_3
+; RV32IBP-NEXT:  .LBB2_2:
 ; RV32IBP-NEXT:not a1, a1
 ; RV32IBP-NEXT:sll a1, a1, a2
 ; RV32IBP-NEXT:addi a3, zero, 31
@@ -97,7 +123,7 @@ define i64 @slo_i64(i64 %a, i64 %b) nounwind {
 ; RV32IBP-NEXT:srl a3, a4, a3
 ; RV32IBP-NEXT:or a1, a1, a3
 ; RV32IBP-NEXT:sll a2, a0, a2
-; RV32IBP-NEXT:  .LBB1_3:
+; RV32IBP-NEXT:  .LBB2_3:
 ; RV32IBP-NEXT:not a1, a1
 ; RV32IBP-NEXT:not a0, a2
 ; RV32IBP-NEXT:ret
@@ -107,6 +133,83 @@ define i64 @slo_i64(i64 %a, i64 %b) nounwind {
   ret i64 %neg1
 }
 
+define i64 @slo_i64_mask(i64 %a, i64 %b) nounwind {
+; RV32I-LABEL: slo_i64_mask:
+; RV32I:   # %bb.0:
+; RV32I-NEXT:andi a3, a2, 63
+; RV32I-NEXT:addi a4, a3, -32
+; RV32I-NEXT:not a0, a0
+; RV32I-NEXT:bltz a4, .LBB3_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:mv a2, zero
+; RV32I-NEXT:sll a1, a0, a4
+; RV32I-NEXT:j .LBB3_3
+; RV32I-NEXT:  .LBB3_2:
+; RV32I-NEXT:not a1, a1
+; RV32I-NEXT:sll a1, a1, a2
+; RV32I-NEXT:addi a4, zero, 31
+; RV32I-NEXT:sub a3, a4, a3
+; RV32I-NEXT:srli a4, a0, 1
+; RV32I-NEXT:srl a3, a4, a3
+; RV32I-NEXT:or a1, a1, a3
+; RV32I-NEXT:sll a2, a0, a2
+; RV32I-NEXT:  .LBB3_3:
+; RV32I-NEXT:not a1, a1
+; RV32I-NEXT:not a0, a2
+; RV32I-NEXT:ret
+;
+; RV32IB-LABEL: slo_i64_mask:
+; RV32IB:   # %bb.0:
+; RV32IB-NEXT:not a0, a0
+; RV32IB-NEXT:not a1, a1
+; RV32IB-NEXT:sll a1, a1, a2
+; RV32IB-NEXT:andi a3, a2, 63
+; RV32IB-NEXT:addi a4, zero, 31
+; RV32IB-NEXT:sub a4, a4, a3
+; RV32IB-NEXT:srli a5, a0, 1
+; RV32IB-NEXT:srl a4, a5, a4
+; RV32IB-NEXT:or a1, a1, a4
+; RV32IB-NEXT:addi a3, a3, -32
+; RV32IB-NEXT:sll a4, a0, a3
+; RV32IB-NEXT:slti a5, a3, 0
+; RV32IB-NEXT:cmov a1, a5, a1, a4
+; RV32IB-NEXT:sll a0, a0, a2
+; RV32IB-NEXT:srai a2, a3, 31
+; RV32IB-NEXT:

[llvm-branch-commits] [llvm] d2927f7 - [RISCV] Add isel patterns to remove (and X, 31) from sllw/srlw/sraw shift amounts.

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2021-01-23T15:08:18-08:00
New Revision: d2927f786e877410d90c1e6f0e0c7d99524529c5

URL: 
https://github.com/llvm/llvm-project/commit/d2927f786e877410d90c1e6f0e0c7d99524529c5
DIFF: 
https://github.com/llvm/llvm-project/commit/d2927f786e877410d90c1e6f0e0c7d99524529c5.diff

LOG: [RISCV] Add isel patterns to remove (and X, 31) from sllw/srlw/sraw shift 
amounts.

We try to do this during DAG combine with SimplifyDemandedBits,
but it fails if there are multiple nodes using the AND. For
example, multiple shifts using the same shift amount.

Added: 


Modified: 
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
llvm/test/CodeGen/RISCV/atomic-rmw.ll

Removed: 




diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 38a8e6a151a8..c03a406972a5 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -885,6 +885,10 @@ class shiftop
 : PatFrags<(ops node:$val, node:$count),
[(operator node:$val, node:$count),
 (operator node:$val, (and node:$count, immbottomxlenset))]>;
+class shiftopw
+: PatFrags<(ops node:$val, node:$count),
+   [(operator node:$val, node:$count),
+(operator node:$val, (and node:$count, (XLenVT 31)))]>;
 
 def : PatGprGpr, SLL>;
 def : PatGprGpr, SRL>;
@@ -1186,9 +1190,9 @@ def : Pat<(sra (sext_inreg GPR:$rs1, i32), uimm5:$shamt),
 def : Pat<(sra (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt),
   (SRAIW GPR:$rs1, (ImmSub32 uimm6gt32:$shamt))>;
 
-def : PatGprGpr;
-def : PatGprGpr;
-def : PatGprGpr;
+def : PatGprGpr, SLLW>;
+def : PatGprGpr, SRLW>;
+def : PatGprGpr, SRAW>;
 
 /// Loads
 

diff  --git a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll 
b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
index 6656e3d964d6..818b15a1ed9c 100644
--- a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
@@ -63,7 +63,6 @@ define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8 
%cmp, i8 %val) nounwind
 ; RV64IA:   # %bb.0:
 ; RV64IA-NEXT:andi a3, a0, -4
 ; RV64IA-NEXT:slli a0, a0, 3
-; RV64IA-NEXT:andi a0, a0, 24
 ; RV64IA-NEXT:addi a4, zero, 255
 ; RV64IA-NEXT:sllw a4, a4, a0
 ; RV64IA-NEXT:andi a1, a1, 255
@@ -141,7 +140,6 @@ define void @cmpxchg_i8_acquire_monotonic(i8* %ptr, i8 
%cmp, i8 %val) nounwind {
 ; RV64IA:   # %bb.0:
 ; RV64IA-NEXT:andi a3, a0, -4
 ; RV64IA-NEXT:slli a0, a0, 3
-; RV64IA-NEXT:andi a0, a0, 24
 ; RV64IA-NEXT:addi a4, zero, 255
 ; RV64IA-NEXT:sllw a4, a4, a0
 ; RV64IA-NEXT:andi a1, a1, 255
@@ -219,7 +217,6 @@ define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, 
i8 %val) nounwind {
 ; RV64IA:   # %bb.0:
 ; RV64IA-NEXT:andi a3, a0, -4
 ; RV64IA-NEXT:slli a0, a0, 3
-; RV64IA-NEXT:andi a0, a0, 24
 ; RV64IA-NEXT:addi a4, zero, 255
 ; RV64IA-NEXT:sllw a4, a4, a0
 ; RV64IA-NEXT:andi a1, a1, 255
@@ -297,7 +294,6 @@ define void @cmpxchg_i8_release_monotonic(i8* %ptr, i8 
%cmp, i8 %val) nounwind {
 ; RV64IA:   # %bb.0:
 ; RV64IA-NEXT:andi a3, a0, -4
 ; RV64IA-NEXT:slli a0, a0, 3
-; RV64IA-NEXT:andi a0, a0, 24
 ; RV64IA-NEXT:addi a4, zero, 255
 ; RV64IA-NEXT:sllw a4, a4, a0
 ; RV64IA-NEXT:andi a1, a1, 255
@@ -375,7 +371,6 @@ define void @cmpxchg_i8_release_acquire(i8* %ptr, i8 %cmp, 
i8 %val) nounwind {
 ; RV64IA:   # %bb.0:
 ; RV64IA-NEXT:andi a3, a0, -4
 ; RV64IA-NEXT:slli a0, a0, 3
-; RV64IA-NEXT:andi a0, a0, 24
 ; RV64IA-NEXT:addi a4, zero, 255
 ; RV64IA-NEXT:sllw a4, a4, a0
 ; RV64IA-NEXT:andi a1, a1, 255
@@ -453,7 +448,6 @@ define void @cmpxchg_i8_acq_rel_monotonic(i8* %ptr, i8 
%cmp, i8 %val) nounwind {
 ; RV64IA:   # %bb.0:
 ; RV64IA-NEXT:andi a3, a0, -4
 ; RV64IA-NEXT:slli a0, a0, 3
-; RV64IA-NEXT:andi a0, a0, 24
 ; RV64IA-NEXT:addi a4, zero, 255
 ; RV64IA-NEXT:sllw a4, a4, a0
 ; RV64IA-NEXT:andi a1, a1, 255
@@ -531,7 +525,6 @@ define void @cmpxchg_i8_acq_rel_acquire(i8* %ptr, i8 %cmp, 
i8 %val) nounwind {
 ; RV64IA:   # %bb.0:
 ; RV64IA-NEXT:andi a3, a0, -4
 ; RV64IA-NEXT:slli a0, a0, 3
-; RV64IA-NEXT:andi a0, a0, 24
 ; RV64IA-NEXT:addi a4, zero, 255
 ; RV64IA-NEXT:sllw a4, a4, a0
 ; RV64IA-NEXT:andi a1, a1, 255
@@ -609,7 +602,6 @@ define void @cmpxchg_i8_seq_cst_monotonic(i8* %ptr, i8 
%cmp, i8 %val) nounwind {
 ; RV64IA:   # %bb.0:
 ; RV64IA-NEXT:andi a3, a0, -4
 ; RV64IA-NEXT:slli a0, a0, 3
-; RV64IA-NEXT:andi a0, a0, 24
 ; RV64IA-NEXT:addi a4, zero, 255
 ; RV64IA-NEXT:sllw a4, a4, a0
 ; RV64IA-NEXT:andi a1, a1, 255
@@ -687,7 +679,6 @@ define void @cmpxchg_i8_seq_cst_acquire(i8* %ptr, i8 %cmp, 
i8 %val) nounwind {
 ; RV64IA:   # %bb.0:
 ; RV64IA-NEXT:andi a3, a0, -4
 ; RV64IA-NEXT:slli a0, a0, 3

[llvm-branch-commits] [openmp] dc70c56 - [libomptarget][amdgpu][nfc] Update comments

[Jon Chesterfield via llvm-branch-commits]

Author: Jon Chesterfield
Date: 2021-01-23T22:53:58Z
New Revision: dc70c56be5922b874b1408edc1315fcda40680ba

URL: 
https://github.com/llvm/llvm-project/commit/dc70c56be5922b874b1408edc1315fcda40680ba
DIFF: 
https://github.com/llvm/llvm-project/commit/dc70c56be5922b874b1408edc1315fcda40680ba.diff

LOG: [libomptarget][amdgpu][nfc] Update comments

[libomptarget][amdgpu][nfc] Update comments

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D95295

Added: 


Modified: 
openmp/libomptarget/plugins/amdgpu/impl/data.cpp
openmp/libomptarget/plugins/amdgpu/impl/machine.h
openmp/libomptarget/plugins/amdgpu/impl/rt.h
openmp/libomptarget/plugins/amdgpu/impl/system.cpp
openmp/libomptarget/plugins/amdgpu/src/rtl.cpp

Removed: 




diff  --git a/openmp/libomptarget/plugins/amdgpu/impl/data.cpp 
b/openmp/libomptarget/plugins/amdgpu/impl/data.cpp
index 39546fbae4b3..0d98d5c51ce1 100644
--- a/openmp/libomptarget/plugins/amdgpu/impl/data.cpp
+++ b/openmp/libomptarget/plugins/amdgpu/impl/data.cpp
@@ -51,7 +51,6 @@ hsa_amd_memory_pool_t 
get_memory_pool_by_mem_place(atmi_mem_place_t place) {
 void register_allocation(void *ptr, size_t size, atmi_mem_place_t place) {
   if (place.dev_type == ATMI_DEVTYPE_CPU)
 allow_access_to_all_gpu_agents(ptr);
-  // TODO(ashwinma): what if one GPU wants to access another GPU?
 }
 
 atmi_status_t Runtime::Malloc(void **ptr, size_t size, atmi_mem_place_t place) 
{

diff  --git a/openmp/libomptarget/plugins/amdgpu/impl/machine.h 
b/openmp/libomptarget/plugins/amdgpu/impl/machine.h
index 93169ed4eafb..9250c3b7c663 100644
--- a/openmp/libomptarget/plugins/amdgpu/impl/machine.h
+++ b/openmp/libomptarget/plugins/amdgpu/impl/machine.h
@@ -22,9 +22,6 @@ class ATLProcessor {
   }
   void addMemory(const ATLMemory &p);
   hsa_agent_t agent() const { return agent_; }
-  // TODO(ashwinma): Do we need this or are we building the machine structure
-  // just once in the program?
-  // void removeMemory(ATLMemory &p);
   const std::vector &memories() const;
   atmi_devtype_t type() const { return type_; }
 
@@ -86,7 +83,7 @@ template  T &get_processor(atmi_place_t place) {
   int dev_id = place.device_id;
   if (dev_id == -1) {
 // user is asking runtime to pick a device
-// TODO(ashwinma): best device of this type? pick 0 for now
+// best device of this type? pick 0 for now
 dev_id = 0;
   }
   return g_atl_machine.processors()[dev_id];

diff  --git a/openmp/libomptarget/plugins/amdgpu/impl/rt.h 
b/openmp/libomptarget/plugins/amdgpu/impl/rt.h
index 757919eb3a45..a857861307c6 100644
--- a/openmp/libomptarget/plugins/amdgpu/impl/rt.h
+++ b/openmp/libomptarget/plugins/amdgpu/impl/rt.h
@@ -26,10 +26,7 @@ class Environment {
   void GetEnvAll();
 
   int getMaxQueueSize() const { return max_queue_size_; }
-
-  // TODO(ashwinma): int may change to enum if we have more debug modes
   int getDebugMode() const { return debug_mode_; }
-  // TODO(ashwinma): int may change to enum if we have more profile modes
 
 private:
   std::string GetEnv(const char *name) {
@@ -69,10 +66,7 @@ class Runtime final {
   static atmi_status_t Memfree(void *);
   static atmi_status_t Malloc(void **, size_t, atmi_mem_place_t);
 
-  // environment variables
   int getMaxQueueSize() const { return env_.getMaxQueueSize(); }
-
-  // TODO(ashwinma): int may change to enum if we have more debug modes
   int getDebugMode() const { return env_.getDebugMode(); }
 
 protected:

diff  --git a/openmp/libomptarget/plugins/amdgpu/impl/system.cpp 
b/openmp/libomptarget/plugins/amdgpu/impl/system.cpp
index 913dc91b298d..1a126a186ff2 100644
--- a/openmp/libomptarget/plugins/amdgpu/impl/system.cpp
+++ b/openmp/libomptarget/plugins/amdgpu/impl/system.cpp
@@ -133,7 +133,7 @@ static const std::map 
ArgValueKind = {
 {"hidden_hostcall_buffer", KernelArgMD::ValueKind::HiddenHostcallBuffer},
 };
 
-// public variables -- TODO(ashwinma) move these to a runtime object?
+// global variables. TODO: Get rid of these
 atmi_machine_t g_atmi_machine;
 ATLMachine g_atl_machine;
 
@@ -210,8 +210,6 @@ atmi_status_t Runtime::Initialize() {
 }
 
 atmi_status_t Runtime::Finalize() {
-  // TODO(ashwinma): Finalize all processors, queues, signals, kernarg memory
-  // regions
   hsa_status_t err;
 
   for (uint32_t i = 0; i < g_executables.size(); i++) {
@@ -874,8 +872,6 @@ static hsa_status_t get_code_object_custom_metadata(void 
*binary,
 msgpackErrorCheck(iterate args map in kernel args metadata,
   msgpack_errors);
 
-// TODO(ashwinma): should the below population actions be done only for
-// non-implicit args?
 // populate info with sizes and offsets
 info.arg_sizes.push_back(lcArg.size_);
 // v3 has offset field and not align field

diff  --git a/openmp/libomptarget/plugins/amdgpu/src/rtl.cpp 
b/openmp/libomptarget/plugins/amdgpu/src/rtl.cpp
ind

[llvm-branch-commits] [mlir] 52586c4 - [mlir][CAPI] Add result type inference to the CAPI.

[Stella Laurenzo via llvm-branch-commits]

Author: Stella Laurenzo
Date: 2021-01-23T14:30:51-08:00
New Revision: 52586c46b0883600a332fd64731dc5287981f980

URL: 
https://github.com/llvm/llvm-project/commit/52586c46b0883600a332fd64731dc5287981f980
DIFF: 
https://github.com/llvm/llvm-project/commit/52586c46b0883600a332fd64731dc5287981f980.diff

LOG: [mlir][CAPI] Add result type inference to the CAPI.

* Adds a flag to MlirOperationState to enable result type inference using the 
InferTypeOpInterface.
* I chose this level of implementation for a couple of reasons:
  a) In the creation flow is naturally where generated and custom builder code 
will be invoking such a thing
  b) it is a bit more efficient to share the data structure and unpacking vs 
having a standalone entry-point
  c) we can always decide to expose more of these interfaces with first-class 
APIs, but that doesn't preclude that we will always want to use this one in 
this way (and less API surface area for common things is better for API 
stability and evolution).
* I struggled to find an appropriate way to test it since we don't link the 
test dialect into anything CAPI accessible at present. I opted instead for one 
of the simplest ops I found in a regular dialect which implements the interface.
* This does not do any trait-based type selection. That will be left to 
generated tablegen wrappers.

Differential Revision: https://reviews.llvm.org/D95283

Added: 


Modified: 
mlir/include/mlir-c/IR.h
mlir/lib/CAPI/IR/IR.cpp
mlir/test/CAPI/ir.c

Removed: 




diff  --git a/mlir/include/mlir-c/IR.h b/mlir/include/mlir-c/IR.h
index 13e32be049e4..39f42e4bf497 100644
--- a/mlir/include/mlir-c/IR.h
+++ b/mlir/include/mlir-c/IR.h
@@ -225,6 +225,7 @@ struct MlirOperationState {
   MlirBlock *successors;
   intptr_t nAttributes;
   MlirNamedAttribute *attributes;
+  bool enableResultTypeInference;
 };
 typedef struct MlirOperationState MlirOperationState;
 
@@ -249,6 +250,14 @@ MLIR_CAPI_EXPORTED void
 mlirOperationStateAddAttributes(MlirOperationState *state, intptr_t n,
 MlirNamedAttribute const *attributes);
 
+/// Enables result type inference for the operation under construction. If
+/// enabled, then the caller must not have called
+/// mlirOperationStateAddResults(). Note that if enabled, the
+/// mlirOperationCreate() call is failable: it will return a null operation
+/// on inference failure and will emit diagnostics.
+MLIR_CAPI_EXPORTED void
+mlirOperationStateEnableResultTypeInference(MlirOperationState *state);
+
 
//===--===//
 // Op Printing flags API.
 // While many of these are simple settings that could be represented in a
@@ -293,8 +302,14 @@ mlirOpPrintingFlagsUseLocalScope(MlirOpPrintingFlags 
flags);
 
//===--===//
 
 /// Creates an operation and transfers ownership to the caller.
-MLIR_CAPI_EXPORTED MlirOperation
-mlirOperationCreate(const MlirOperationState *state);
+/// Note that caller owned child objects are transferred in this call and must
+/// not be further used. Particularly, this applies to any regions added to
+/// the state (the implementation may invalidate any such pointers).
+///
+/// This call can fail under the following conditions, in which case, it will
+/// return a null operation and emit diagnostics:
+///   - Result type inference is enabled and cannot be performed.
+MLIR_CAPI_EXPORTED MlirOperation mlirOperationCreate(MlirOperationState 
*state);
 
 /// Takes an operation owned by the caller and destroys it.
 MLIR_CAPI_EXPORTED void mlirOperationDestroy(MlirOperation op);

diff  --git a/mlir/lib/CAPI/IR/IR.cpp b/mlir/lib/CAPI/IR/IR.cpp
index 30d4c8c41835..bf240046be25 100644
--- a/mlir/lib/CAPI/IR/IR.cpp
+++ b/mlir/lib/CAPI/IR/IR.cpp
@@ -18,6 +18,7 @@
 #include "mlir/IR/Operation.h"
 #include "mlir/IR/Types.h"
 #include "mlir/IR/Verifier.h"
+#include "mlir/Interfaces/InferTypeOpInterface.h"
 #include "mlir/Parser.h"
 
 using namespace mlir;
@@ -188,6 +189,7 @@ MlirOperationState mlirOperationStateGet(MlirStringRef 
name, MlirLocation loc) {
   state.successors = nullptr;
   state.nAttributes = 0;
   state.attributes = nullptr;
+  state.enableResultTypeInference = false;
   return state;
 }
 
@@ -219,11 +221,47 @@ void mlirOperationStateAddAttributes(MlirOperationState 
*state, intptr_t n,
   APPEND_ELEMS(MlirNamedAttribute, nAttributes, attributes);
 }
 
+void mlirOperationStateEnableResultTypeInference(MlirOperationState *state) {
+  state->enableResultTypeInference = true;
+}
+
 
//===--===//
 // Operation API.
 
//===--===//
 
-MlirOperation mlirOperationCreate(const MlirOperationState *state) {
+static LogicalResult inferOperationTypes(OperationState &

[llvm-branch-commits] [llvm] 6f27532 - [NFC][SimplifyCFG] Extract CloneInstructionsIntoPredecessorBlockAndUpdateSSAUses() out of PerformBranchToCommonDestFolding()

[Roman Lebedev via llvm-branch-commits]

Author: Roman Lebedev
Date: 2021-01-24T00:54:55+03:00
New Revision: 6f2753273ee6d891cabd11626e4efbce0d901661

URL: 
https://github.com/llvm/llvm-project/commit/6f2753273ee6d891cabd11626e4efbce0d901661
DIFF: 
https://github.com/llvm/llvm-project/commit/6f2753273ee6d891cabd11626e4efbce0d901661.diff

LOG: [NFC][SimplifyCFG] Extract 
CloneInstructionsIntoPredecessorBlockAndUpdateSSAUses() out of 
PerformBranchToCommonDestFolding()

To be used in PerformValueComparisonIntoPredecessorFolding()

Added: 


Modified: 
llvm/lib/Transforms/Utils/SimplifyCFG.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp 
b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 6dab65d3f063..7cfe17618cde 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -1049,6 +1049,55 @@ static void FitWeights(MutableArrayRef 
Weights) {
   }
 }
 
+static void CloneInstructionsIntoPredecessorBlockAndUpdateSSAUses(
+BasicBlock *BB, BasicBlock *PredBlock, ValueToValueMapTy &VMap) {
+  Instruction *PTI = PredBlock->getTerminator();
+
+  // If we have bonus instructions, clone them into the predecessor block.
+  // Note that there may be multiple predecessor blocks, so we cannot move
+  // bonus instructions to a predecessor block.
+  for (Instruction &BonusInst : *BB) {
+if (isa(BonusInst) || BonusInst.isTerminator())
+  continue;
+
+Instruction *NewBonusInst = BonusInst.clone();
+
+if (PTI->getDebugLoc() != NewBonusInst->getDebugLoc()) {
+  // Unless the instruction has the same !dbg location as the original
+  // branch, drop it. When we fold the bonus instructions we want to make
+  // sure we reset their debug locations in order to avoid stepping on
+  // dead code caused by folding dead branches.
+  NewBonusInst->setDebugLoc(DebugLoc());
+}
+
+RemapInstruction(NewBonusInst, VMap,
+ RF_NoModuleLevelChanges | RF_IgnoreMissingLocals);
+VMap[&BonusInst] = NewBonusInst;
+
+// If we moved a load, we cannot any longer claim any knowledge about
+// its potential value. The previous information might have been valid
+// only given the branch precondition.
+// For an analogous reason, we must also drop all the metadata whose
+// semantics we don't understand. We *can* preserve !annotation, because
+// it is tied to the instruction itself, not the value or position.
+NewBonusInst->dropUnknownNonDebugMetadata(LLVMContext::MD_annotation);
+
+PredBlock->getInstList().insert(PTI->getIterator(), NewBonusInst);
+NewBonusInst->takeName(&BonusInst);
+BonusInst.setName(NewBonusInst->getName() + ".old");
+
+// Update (liveout) uses of bonus instructions,
+// now that the bonus instruction has been cloned into predecessor.
+SSAUpdater SSAUpdate;
+SSAUpdate.Initialize(BonusInst.getType(),
+ (NewBonusInst->getName() + ".merge").str());
+SSAUpdate.AddAvailableValue(BB, &BonusInst);
+SSAUpdate.AddAvailableValue(PredBlock, NewBonusInst);
+for (Use &U : make_early_inc_range(BonusInst.uses()))
+  SSAUpdate.RewriteUseAfterInsertions(U);
+  }
+}
+
 bool SimplifyCFGOpt::PerformValueComparisonIntoPredecessorFolding(
 Instruction *TI, Value *&CV, Instruction *PTI, IRBuilder<> &Builder) {
   BasicBlock *BB = TI->getParent();
@@ -2890,50 +2939,8 @@ static bool PerformBranchToCommonDestFolding(BranchInst 
*BI, BranchInst *PBI,
   if (MDNode *LoopMD = BI->getMetadata(LLVMContext::MD_loop))
 PBI->setMetadata(LLVMContext::MD_loop, LoopMD);
 
-  // If we have bonus instructions, clone them into the predecessor block.
-  // Note that there may be multiple predecessor blocks, so we cannot move
-  // bonus instructions to a predecessor block.
   ValueToValueMapTy VMap; // maps original values to cloned values
-  for (Instruction &BonusInst : *BB) {
-if (isa(BonusInst) || isa(BonusInst))
-  continue;
-
-Instruction *NewBonusInst = BonusInst.clone();
-
-if (PBI->getDebugLoc() != NewBonusInst->getDebugLoc()) {
-  // Unless the instruction has the same !dbg location as the original
-  // branch, drop it. When we fold the bonus instructions we want to make
-  // sure we reset their debug locations in order to avoid stepping on
-  // dead code caused by folding dead branches.
-  NewBonusInst->setDebugLoc(DebugLoc());
-}
-
-RemapInstruction(NewBonusInst, VMap,
- RF_NoModuleLevelChanges | RF_IgnoreMissingLocals);
-VMap[&BonusInst] = NewBonusInst;
-
-// If we moved a load, we cannot any longer claim any knowledge about
-// its potential value. The previous information might have been valid
-// only given the branch precondition.
-// For an analogous reason, we must also drop all the metadata whose
-// semantics we don't understand. We *can* preserve !annotation, because
-  

[llvm-branch-commits] [llvm] 67f9c87 - [NFC][SimplifyCFG] Perform early-continue in FoldValueComparisonIntoPredecessors() per-pred loop

[Roman Lebedev via llvm-branch-commits]

Author: Roman Lebedev
Date: 2021-01-24T00:54:54+03:00
New Revision: 67f9c87a651a9c3a57a2b1bf32e6e0be2479ebc7

URL: 
https://github.com/llvm/llvm-project/commit/67f9c87a651a9c3a57a2b1bf32e6e0be2479ebc7
DIFF: 
https://github.com/llvm/llvm-project/commit/67f9c87a651a9c3a57a2b1bf32e6e0be2479ebc7.diff

LOG: [NFC][SimplifyCFG] Perform early-continue in 
FoldValueComparisonIntoPredecessors() per-pred loop

Added: 


Modified: 
llvm/lib/Transforms/Utils/SimplifyCFG.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp 
b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 318e6d5cf810..6dab65d3f063 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -1273,24 +1273,27 @@ bool 
SimplifyCFGOpt::FoldValueComparisonIntoPredecessors(Instruction *TI,
   SmallSetVector Preds(pred_begin(BB), pred_end(BB));
   while (!Preds.empty()) {
 BasicBlock *Pred = Preds.pop_back_val();
+Instruction *PTI = Pred->getTerminator();
+
+// Don't try to fold into itself.
+if (Pred == BB)
+  continue;
 
 // See if the predecessor is a comparison with the same value.
-Instruction *PTI = Pred->getTerminator();
 Value *PCV = isValueEqualityComparison(PTI); // PredCondVal
+if (PCV != CV)
+  continue;
 
-if (PCV == CV && TI != PTI) {
-  SmallSetVector FailBlocks;
-  if (!SafeToMergeTerminators(TI, PTI, &FailBlocks)) {
-for (auto *Succ : FailBlocks) {
-  if (!SplitBlockPredecessors(Succ, TI->getParent(), ".fold.split",
-  DTU))
-return false;
-}
+SmallSetVector FailBlocks;
+if (!SafeToMergeTerminators(TI, PTI, &FailBlocks)) {
+  for (auto *Succ : FailBlocks) {
+if (!SplitBlockPredecessors(Succ, TI->getParent(), ".fold.split", DTU))
+  return false;
   }
-
-  PerformValueComparisonIntoPredecessorFolding(TI, CV, PTI, Builder);
-  Changed = true;
 }
+
+PerformValueComparisonIntoPredecessorFolding(TI, CV, PTI, Builder);
+Changed = true;
   }
   return Changed;
 }



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[llvm-branch-commits] [llvm] a4e6c2e - [NFC][SimplifyCFG] Extract PerformValueComparisonIntoPredecessorFolding() out of FoldValueComparisonIntoPredecessors()

[Roman Lebedev via llvm-branch-commits]

Author: Roman Lebedev
Date: 2021-01-24T00:54:54+03:00
New Revision: a4e6c2e647b09dd8c2c5cf55bb05e3c7fd89646c

URL: 
https://github.com/llvm/llvm-project/commit/a4e6c2e647b09dd8c2c5cf55bb05e3c7fd89646c
DIFF: 
https://github.com/llvm/llvm-project/commit/a4e6c2e647b09dd8c2c5cf55bb05e3c7fd89646c.diff

LOG: [NFC][SimplifyCFG] Extract PerformValueComparisonIntoPredecessorFolding() 
out of FoldValueComparisonIntoPredecessors()

Less nested code is much easier to follow and modify.

Added: 


Modified: 
llvm/lib/Transforms/Utils/SimplifyCFG.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp 
b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index deaa0bbcf772..318e6d5cf810 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -229,6 +229,9 @@ class SimplifyCFGOpt {
   bool SimplifyEqualityComparisonWithOnlyPredecessor(Instruction *TI,
  BasicBlock *Pred,
  IRBuilder<> &Builder);
+  bool PerformValueComparisonIntoPredecessorFolding(Instruction *TI, Value 
*&CV,
+Instruction *PTI,
+IRBuilder<> &Builder);
   bool FoldValueComparisonIntoPredecessors(Instruction *TI,
IRBuilder<> &Builder);
 
@@ -1046,6 +1049,215 @@ static void FitWeights(MutableArrayRef 
Weights) {
   }
 }
 
+bool SimplifyCFGOpt::PerformValueComparisonIntoPredecessorFolding(
+Instruction *TI, Value *&CV, Instruction *PTI, IRBuilder<> &Builder) {
+  BasicBlock *BB = TI->getParent();
+  BasicBlock *Pred = PTI->getParent();
+
+  std::vector Updates;
+
+  // Figure out which 'cases' to copy from SI to PSI.
+  std::vector BBCases;
+  BasicBlock *BBDefault = GetValueEqualityComparisonCases(TI, BBCases);
+
+  std::vector PredCases;
+  BasicBlock *PredDefault = GetValueEqualityComparisonCases(PTI, PredCases);
+
+  // Based on whether the default edge from PTI goes to BB or not, fill in
+  // PredCases and PredDefault with the new switch cases we would like to
+  // build.
+  SmallMapVector NewSuccessors;
+
+  // Update the branch weight metadata along the way
+  SmallVector Weights;
+  bool PredHasWeights = HasBranchWeights(PTI);
+  bool SuccHasWeights = HasBranchWeights(TI);
+
+  if (PredHasWeights) {
+GetBranchWeights(PTI, Weights);
+// branch-weight metadata is inconsistent here.
+if (Weights.size() != 1 + PredCases.size())
+  PredHasWeights = SuccHasWeights = false;
+  } else if (SuccHasWeights)
+// If there are no predecessor weights but there are successor weights,
+// populate Weights with 1, which will later be scaled to the sum of
+// successor's weights
+Weights.assign(1 + PredCases.size(), 1);
+
+  SmallVector SuccWeights;
+  if (SuccHasWeights) {
+GetBranchWeights(TI, SuccWeights);
+// branch-weight metadata is inconsistent here.
+if (SuccWeights.size() != 1 + BBCases.size())
+  PredHasWeights = SuccHasWeights = false;
+  } else if (PredHasWeights)
+SuccWeights.assign(1 + BBCases.size(), 1);
+
+  if (PredDefault == BB) {
+// If this is the default destination from PTI, only the edges in TI
+// that don't occur in PTI, or that branch to BB will be activated.
+std::set PTIHandled;
+for (unsigned i = 0, e = PredCases.size(); i != e; ++i)
+  if (PredCases[i].Dest != BB)
+PTIHandled.insert(PredCases[i].Value);
+  else {
+// The default destination is BB, we don't need explicit targets.
+std::swap(PredCases[i], PredCases.back());
+
+if (PredHasWeights || SuccHasWeights) {
+  // Increase weight for the default case.
+  Weights[0] += Weights[i + 1];
+  std::swap(Weights[i + 1], Weights.back());
+  Weights.pop_back();
+}
+
+PredCases.pop_back();
+--i;
+--e;
+  }
+
+// Reconstruct the new switch statement we will be building.
+if (PredDefault != BBDefault) {
+  PredDefault->removePredecessor(Pred);
+  if (PredDefault != BB)
+Updates.push_back({DominatorTree::Delete, Pred, PredDefault});
+  PredDefault = BBDefault;
+  ++NewSuccessors[BBDefault];
+}
+
+unsigned CasesFromPred = Weights.size();
+uint64_t ValidTotalSuccWeight = 0;
+for (unsigned i = 0, e = BBCases.size(); i != e; ++i)
+  if (!PTIHandled.count(BBCases[i].Value) && BBCases[i].Dest != BBDefault) 
{
+PredCases.push_back(BBCases[i]);
+++NewSuccessors[BBCases[i].Dest];
+if (SuccHasWeights || PredHasWeights) {
+  // The default weight is at index 0, so weight for the ith case
+  // should be at index i+1. Scale the cases from successor by
+  // PredDefaultWeight (Weights[0]).
+  Weights.push_back(Weights[0] * Succ

[llvm-branch-commits] [llvm] c83cff4 - [IR] Add NoAliasScopeDeclInst (NFC)

[Nikita Popov via llvm-branch-commits]

Author: Nikita Popov
Date: 2021-01-23T22:40:32+01:00
New Revision: c83cff45c7a58010e65270d3f5bfb8c9a72ad832

URL: 
https://github.com/llvm/llvm-project/commit/c83cff45c7a58010e65270d3f5bfb8c9a72ad832
DIFF: 
https://github.com/llvm/llvm-project/commit/c83cff45c7a58010e65270d3f5bfb8c9a72ad832.diff

LOG: [IR] Add NoAliasScopeDeclInst (NFC)

Add an intrinsic type class to represent the
llvm.experimental.noalias.scope.decl intrinsic, to make code
working with it a bit nicer by hiding the metadata extraction
from view.

Added: 


Modified: 
llvm/include/llvm/IR/IntrinsicInst.h
llvm/lib/Transforms/Utils/InlineFunction.cpp
llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Removed: 




diff  --git a/llvm/include/llvm/IR/IntrinsicInst.h 
b/llvm/include/llvm/IR/IntrinsicInst.h
index 52504582dd1d..12c464f8b8ba 100644
--- a/llvm/include/llvm/IR/IntrinsicInst.h
+++ b/llvm/include/llvm/IR/IntrinsicInst.h
@@ -989,6 +989,24 @@ class PseudoProbeInst : public IntrinsicInst {
 return cast(const_cast(getArgOperand(1)));
   }
 };
+
+class NoAliasScopeDeclInst : public IntrinsicInst {
+public:
+  static bool classof(const IntrinsicInst *I) {
+return I->getIntrinsicID() == Intrinsic::experimental_noalias_scope_decl;
+  }
+
+  static bool classof(const Value *V) {
+return isa(V) && classof(cast(V));
+  }
+
+  MDNode *getScopeList() const {
+auto *MV =
+cast(getOperand(Intrinsic::NoAliasScopeDeclScopeArg));
+return cast(MV->getMetadata());
+  }
+};
+
 } // end namespace llvm
 
 #endif // LLVM_IR_INTRINSICINST_H

diff  --git a/llvm/lib/Transforms/Utils/InlineFunction.cpp 
b/llvm/lib/Transforms/Utils/InlineFunction.cpp
index abdd2b2361b7..2f8f3666d396 100644
--- a/llvm/lib/Transforms/Utils/InlineFunction.cpp
+++ b/llvm/lib/Transforms/Utils/InlineFunction.cpp
@@ -859,13 +859,8 @@ 
ScopedAliasMetadataDeepCloner::ScopedAliasMetadataDeepCloner(
 MD.insert(M);
 
   // We also need to clone the metadata in noalias intrinsics.
-  if (const auto *II = dyn_cast(&I))
-if (II->getIntrinsicID() == Intrinsic::experimental_noalias_scope_decl)
-  if (const auto *M = dyn_cast(
-  cast(
-  II->getOperand(Intrinsic::NoAliasScopeDeclScopeArg))
-  ->getMetadata()))
-MD.insert(M);
+  if (const auto *Decl = dyn_cast(&I))
+MD.insert(Decl->getScopeList());
 }
   }
   addRecursiveMetadataUses();
@@ -932,14 +927,11 @@ void 
ScopedAliasMetadataDeepCloner::remap(ValueToValueMapTy &VMap) {
 if (MDNode *M = I->getMetadata(LLVMContext::MD_noalias))
   I->setMetadata(LLVMContext::MD_noalias, MDMap[M]);
 
-if (auto *II = dyn_cast(I))
-  if (II->getIntrinsicID() == Intrinsic::experimental_noalias_scope_decl) {
-auto *MV = cast(
-II->getOperand(Intrinsic::NoAliasScopeDeclScopeArg));
-auto *NewMV = MetadataAsValue::get(
-II->getContext(), MDMap[cast(MV->getMetadata())]);
-II->setOperand(Intrinsic::NoAliasScopeDeclScopeArg, NewMV);
-  }
+if (auto *Decl = dyn_cast(I)) {
+  auto *NewMV =
+  MetadataAsValue::get(Decl->getContext(), 
MDMap[Decl->getScopeList()]);
+  Decl->setOperand(Intrinsic::NoAliasScopeDeclScopeArg, NewMV);
+}
   }
 }
 

diff  --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp 
b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
index 2b873954f88b..2ab0848193f6 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
@@ -947,9 +947,8 @@ bool LoopVectorizationLegality::blockCanBePredicated(
 // Do not let llvm.experimental.noalias.scope.decl block the vectorization.
 // TODO: there might be cases that it should block the vectorization. Let's
 // ignore those for now.
-if (match(&I, m_Intrinsic())) {
+if (isa(&I))
   continue;
-}
 
 // We might be able to hoist the load.
 if (I.mayReadFromMemory()) {

diff  --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp 
b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 9e157f3061b6..9373d40458f4 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -2882,10 +2882,9 @@ void 
InnerLoopVectorizer::scalarizeInstruction(Instruction *Instr, VPUser &User,
 
   // llvm.experimental.noalias.scope.decl intrinsics must only be duplicated 
for
   // the first lane and part.
-  if (auto *II = dyn_cast(Instr))
+  if (isa(Instr))
 if (Instance.Lane != 0 || Instance.Part != 0)
-  if (II->getIntrinsicID() == Intrinsic::experimental_noalias_scope_decl)
-return;
+  return;
 
   setDebugLocFromInst(Builder, Instr);
 



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[llvm-branch-commits] [llvm] c37dd3b - [NewPM][opt] Make -enable-new-pm default to LLVM_ENABLE_NEW_PASS_MANAGER

[Arthur Eubanks via llvm-branch-commits]

Author: Arthur Eubanks
Date: 2021-01-23T12:36:09-08:00
New Revision: c37dd3b6d553d7ae3afaf677f1c6abdf6b1ec74e

URL: 
https://github.com/llvm/llvm-project/commit/c37dd3b6d553d7ae3afaf677f1c6abdf6b1ec74e
DIFF: 
https://github.com/llvm/llvm-project/commit/c37dd3b6d553d7ae3afaf677f1c6abdf6b1ec74e.diff

LOG: [NewPM][opt] Make -enable-new-pm default to LLVM_ENABLE_NEW_PASS_MANAGER

This is controlled by the ENABLE_EXPERIMENTAL_NEW_PASS_MANAGER CMake flag.

https://lists.llvm.org/pipermail/llvm-dev/2021-January/147993.html

Reviewed By: ychen, asbirlea

Differential Revision: https://reviews.llvm.org/D95254

Added: 


Modified: 
llvm/tools/opt/opt.cpp

Removed: 




diff  --git a/llvm/tools/opt/opt.cpp b/llvm/tools/opt/opt.cpp
index 92df0bc19a30..5cb59f85ccf8 100644
--- a/llvm/tools/opt/opt.cpp
+++ b/llvm/tools/opt/opt.cpp
@@ -70,8 +70,10 @@ static codegen::RegisterCodeGenFlags CFG;
 static cl::list
 PassList(cl::desc("Optimizations available:"));
 
-static cl::opt EnableNewPassManager(
-"enable-new-pm", cl::desc("Enable the new pass manager"), cl::init(false));
+static cl::opt
+EnableNewPassManager("enable-new-pm",
+ cl::desc("Enable the new pass manager"),
+ cl::init(LLVM_ENABLE_NEW_PASS_MANAGER));
 
 // This flag specifies a textual description of the optimization pass pipeline
 // to run over the module. This flag switches opt to use the new pass manager



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[llvm-branch-commits] [llvm] a22ba5a - [test] Pin dead-calls-willreturn.ll to legacy PM

[Arthur Eubanks via llvm-branch-commits]

Author: Arthur Eubanks
Date: 2021-01-23T12:35:36-08:00
New Revision: a22ba5afc8d9e3ec00be3e374d40379d1648f53d

URL: 
https://github.com/llvm/llvm-project/commit/a22ba5afc8d9e3ec00be3e374d40379d1648f53d
DIFF: 
https://github.com/llvm/llvm-project/commit/a22ba5afc8d9e3ec00be3e374d40379d1648f53d.diff

LOG: [test] Pin dead-calls-willreturn.ll to legacy PM

The new PM inliner does not delete dead calls.

Added: 


Modified: 
llvm/test/Transforms/Inline/dead-calls-willreturn.ll

Removed: 




diff  --git a/llvm/test/Transforms/Inline/dead-calls-willreturn.ll 
b/llvm/test/Transforms/Inline/dead-calls-willreturn.ll
index c36d044b1ac3..ae714e16cd04 100644
--- a/llvm/test/Transforms/Inline/dead-calls-willreturn.ll
+++ b/llvm/test/Transforms/Inline/dead-calls-willreturn.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -inline -S %s | FileCheck %s
+; RUN: opt -inline -S -enable-new-pm=0 %s | FileCheck %s
 
 ; readnone but may not return according to attributes.
 define void @readnone_may_not_return() nounwind readnone ssp {



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[llvm-branch-commits] [openmp] 78b0630 - [libomptarget][cuda] Call v2 functions explicitly

[Jon Chesterfield via llvm-branch-commits]

Author: Jon Chesterfield
Date: 2021-01-23T20:33:13Z
New Revision: 78b0630b72a9742d62b07cef912b72f1743bfae9

URL: 
https://github.com/llvm/llvm-project/commit/78b0630b72a9742d62b07cef912b72f1743bfae9
DIFF: 
https://github.com/llvm/llvm-project/commit/78b0630b72a9742d62b07cef912b72f1743bfae9.diff

LOG: [libomptarget][cuda] Call v2 functions explicitly

[libomptarget][cuda] Call v2 functions explicitly

rtl.cpp calls functions like cuMemFree that are replaced by a macro
in cuda.h with cuMemFree_v2. This patch changes the source to use
the v2 names consistently.

See also D95104, D95155 for the idea. Alternatives are to use a mixture,
e.g. call the macro names and explictly dlopen the _v2 names, or to keep
the current status where the symbols are replaced by macros in both files

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D95274

Added: 


Modified: 
openmp/libomptarget/plugins/cuda/dynamic_cuda/cuda.h
openmp/libomptarget/plugins/cuda/src/rtl.cpp

Removed: 




diff  --git a/openmp/libomptarget/plugins/cuda/dynamic_cuda/cuda.h 
b/openmp/libomptarget/plugins/cuda/dynamic_cuda/cuda.h
index 832c26965144..dd579a1f7490 100644
--- a/openmp/libomptarget/plugins/cuda/dynamic_cuda/cuda.h
+++ b/openmp/libomptarget/plugins/cuda/dynamic_cuda/cuda.h
@@ -48,18 +48,6 @@ typedef enum CUctx_flags_enum {
   CU_CTX_SCHED_MASK = 0x07,
 } CUctx_flags;
 
-#define cuMemFree cuMemFree_v2
-#define cuMemAlloc cuMemAlloc_v2
-#define cuMemcpyDtoH cuMemcpyDtoH_v2
-#define cuMemcpyHtoD cuMemcpyHtoD_v2
-#define cuStreamDestroy cuStreamDestroy_v2
-#define cuModuleGetGlobal cuModuleGetGlobal_v2
-#define cuMemcpyDtoHAsync cuMemcpyDtoHAsync_v2
-#define cuMemcpyDtoDAsync cuMemcpyDtoDAsync_v2
-#define cuMemcpyHtoDAsync cuMemcpyHtoDAsync_v2
-#define cuDevicePrimaryCtxRelease cuDevicePrimaryCtxRelease_v2
-#define cuDevicePrimaryCtxSetFlags cuDevicePrimaryCtxSetFlags_v2
-
 CUresult cuCtxGetDevice(CUdevice *);
 CUresult cuDeviceGet(CUdevice *, int);
 CUresult cuDeviceGetAttribute(int *, CUdevice_attribute, CUdevice);
@@ -72,26 +60,26 @@ CUresult cuLaunchKernel(CUfunction, unsigned, unsigned, 
unsigned, unsigned,
 unsigned, unsigned, unsigned, CUstream, void **,
 void **);
 
-CUresult cuMemAlloc(CUdeviceptr *, size_t);
-CUresult cuMemcpyDtoDAsync(CUdeviceptr, CUdeviceptr, size_t, CUstream);
+CUresult cuMemAlloc_v2(CUdeviceptr *, size_t);
+CUresult cuMemcpyDtoDAsync_v2(CUdeviceptr, CUdeviceptr, size_t, CUstream);
 
-CUresult cuMemcpyDtoH(void *, CUdeviceptr, size_t);
-CUresult cuMemcpyDtoHAsync(void *, CUdeviceptr, size_t, CUstream);
-CUresult cuMemcpyHtoD(CUdeviceptr, const void *, size_t);
-CUresult cuMemcpyHtoDAsync(CUdeviceptr, const void *, size_t, CUstream);
+CUresult cuMemcpyDtoH_v2(void *, CUdeviceptr, size_t);
+CUresult cuMemcpyDtoHAsync_v2(void *, CUdeviceptr, size_t, CUstream);
+CUresult cuMemcpyHtoD_v2(CUdeviceptr, const void *, size_t);
+CUresult cuMemcpyHtoDAsync_v2(CUdeviceptr, const void *, size_t, CUstream);
 
-CUresult cuMemFree(CUdeviceptr);
+CUresult cuMemFree_v2(CUdeviceptr);
 CUresult cuModuleGetFunction(CUfunction *, CUmodule, const char *);
-CUresult cuModuleGetGlobal(CUdeviceptr *, size_t *, CUmodule, const char *);
+CUresult cuModuleGetGlobal_v2(CUdeviceptr *, size_t *, CUmodule, const char *);
 
 CUresult cuModuleUnload(CUmodule);
 CUresult cuStreamCreate(CUstream *, unsigned);
-CUresult cuStreamDestroy(CUstream);
+CUresult cuStreamDestroy_v2(CUstream);
 CUresult cuStreamSynchronize(CUstream);
 CUresult cuCtxSetCurrent(CUcontext);
-CUresult cuDevicePrimaryCtxRelease(CUdevice);
+CUresult cuDevicePrimaryCtxRelease_v2(CUdevice);
 CUresult cuDevicePrimaryCtxGetState(CUdevice, unsigned *, int *);
-CUresult cuDevicePrimaryCtxSetFlags(CUdevice, unsigned);
+CUresult cuDevicePrimaryCtxSetFlags_v2(CUdevice, unsigned);
 CUresult cuDevicePrimaryCtxRetain(CUcontext *, CUdevice);
 CUresult cuModuleLoadDataEx(CUmodule *, const void *, unsigned, void *,
 void **);

diff  --git a/openmp/libomptarget/plugins/cuda/src/rtl.cpp 
b/openmp/libomptarget/plugins/cuda/src/rtl.cpp
index e4ac1e0820e6..f83c9df920aa 100644
--- a/openmp/libomptarget/plugins/cuda/src/rtl.cpp
+++ b/openmp/libomptarget/plugins/cuda/src/rtl.cpp
@@ -110,8 +110,8 @@ bool checkResult(CUresult Err, const char *ErrMsg) {
 
 int memcpyDtoD(const void *SrcPtr, void *DstPtr, int64_t Size,
CUstream Stream) {
-  CUresult Err =
-  cuMemcpyDtoDAsync((CUdeviceptr)DstPtr, (CUdeviceptr)SrcPtr, Size, 
Stream);
+  CUresult Err = cuMemcpyDtoDAsync_v2((CUdeviceptr)DstPtr, (CUdeviceptr)SrcPtr,
+  Size, Stream);
 
   if (Err != CUDA_SUCCESS) {
 REPORT("Error when copying data from device to device. Pointers: src "
@@ -207,8 +207,8 @@ class StreamManagerTy {
 
   for (CUstream &S : StreamPool[I]) {
 if (S)
-  checkResult(

[llvm-branch-commits] [llvm] cd3d80e - [PhaseOrdering] Add tests for PR44461 and PR48844 (NFC)

[Nikita Popov via llvm-branch-commits]

Author: Nikita Popov
Date: 2021-01-23T21:24:54+01:00
New Revision: cd3d80eacebaad076d63df65650b3bd4c5a1b99e

URL: 
https://github.com/llvm/llvm-project/commit/cd3d80eacebaad076d63df65650b3bd4c5a1b99e
DIFF: 
https://github.com/llvm/llvm-project/commit/cd3d80eacebaad076d63df65650b3bd4c5a1b99e.diff

LOG: [PhaseOrdering] Add tests for PR44461 and PR48844 (NFC)

In both cases, optimization is prevented because
"br X == C || X == C2" is converted into a switch. In one case
loop rotation is blocked, in the other vectorization.

Added: 
llvm/test/Transforms/PhaseOrdering/X86/pr48844-br-to-switch-vectorization.ll
llvm/test/Transforms/PhaseOrdering/pr44461-br-to-switch-rotate.ll

Modified: 


Removed: 




diff  --git 
a/llvm/test/Transforms/PhaseOrdering/X86/pr48844-br-to-switch-vectorization.ll 
b/llvm/test/Transforms/PhaseOrdering/X86/pr48844-br-to-switch-vectorization.ll
new file mode 100644
index ..26fea2bb5f1d
--- /dev/null
+++ 
b/llvm/test/Transforms/PhaseOrdering/X86/pr48844-br-to-switch-vectorization.ll
@@ -0,0 +1,57 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -O2 -mattr=avx < %s | FileCheck %s
+; RUN: opt -S -passes='default' -mattr=avx < %s | FileCheck %s
+
+target datalayout = 
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+; FIXME: The br -> switch conversion blocks vectorization.
+
+define dso_local void @test(i32* %start, i32* %end) #0 {
+; CHECK-LABEL: @test(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:[[I11_NOT1:%.*]] = icmp eq i32* [[START:%.*]], [[END:%.*]]
+; CHECK-NEXT:br i1 [[I11_NOT1]], label [[EXIT:%.*]], label [[BB12:%.*]]
+; CHECK:   bb12:
+; CHECK-NEXT:[[PTR2:%.*]] = phi i32* [ [[PTR_NEXT:%.*]], [[LATCH:%.*]] ], 
[ [[START]], [[ENTRY:%.*]] ]
+; CHECK-NEXT:[[VAL:%.*]] = load i32, i32* [[PTR2]], align 4
+; CHECK-NEXT:switch i32 [[VAL]], label [[LATCH]] [
+; CHECK-NEXT:i32 -12, label [[STORE:%.*]]
+; CHECK-NEXT:i32 13, label [[STORE]]
+; CHECK-NEXT:]
+; CHECK:   store:
+; CHECK-NEXT:store i32 42, i32* [[PTR2]], align 4
+; CHECK-NEXT:br label [[LATCH]]
+; CHECK:   latch:
+; CHECK-NEXT:[[PTR_NEXT]] = getelementptr inbounds i32, i32* [[PTR2]], i64 
1
+; CHECK-NEXT:[[I11_NOT:%.*]] = icmp eq i32* [[PTR_NEXT]], [[END]]
+; CHECK-NEXT:br i1 [[I11_NOT]], label [[EXIT]], label [[BB12]]
+; CHECK:   exit:
+; CHECK-NEXT:ret void
+;
+entry:
+  br label %header
+
+header:
+  %ptr = phi i32* [ %start, %entry ], [ %ptr.next, %latch ]
+  %i11 = icmp ne i32* %ptr, %end
+  br i1 %i11, label %bb12, label %exit
+
+bb12:
+  %val = load i32, i32* %ptr, align 4
+  %c1 = icmp eq i32 %val, 13
+  %c2 = icmp eq i32 %val, -12
+  %c3 = or i1 %c1, %c2
+  br i1 %c3, label %store, label %latch
+
+store:
+  store i32 42, i32* %ptr, align 4
+  br label %latch
+
+latch:
+  %ptr.next = getelementptr inbounds i32, i32* %ptr, i32 1
+  br label %header
+
+exit:
+  ret void
+}

diff  --git a/llvm/test/Transforms/PhaseOrdering/pr44461-br-to-switch-rotate.ll 
b/llvm/test/Transforms/PhaseOrdering/pr44461-br-to-switch-rotate.ll
new file mode 100644
index ..474c5b7ab2f8
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/pr44461-br-to-switch-rotate.ll
@@ -0,0 +1,52 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -O2 < %s | FileCheck %s
+; RUN: opt -S -passes='default' < %s | FileCheck %s
+
+; FIXME: The br -> switch conversion blocks loop rotation.
+
+define i64 @test() {
+; CHECK-LABEL: @test(
+; CHECK-NEXT:  start:
+; CHECK-NEXT:br label [[BB10:%.*]]
+; CHECK:   bb10:
+; CHECK-NEXT:[[ITER1_SROA_5_0:%.*]] = phi i64 [ 10, [[START:%.*]] ], [ 
[[SPEC_SELECT:%.*]], [[BB3_I_I:%.*]] ]
+; CHECK-NEXT:[[ITER1_SROA_9_0:%.*]] = phi i2 [ -2, [[START]] ], [ 
[[TMP3:%.*]], [[BB3_I_I]] ]
+; CHECK-NEXT:[[COUNT_1:%.*]] = phi i64 [ 0, [[START]] ], [ [[TMP4:%.*]], 
[[BB3_I_I]] ]
+; CHECK-NEXT:switch i2 [[ITER1_SROA_9_0]], label [[BB12:%.*]] [
+; CHECK-NEXT:i2 -2, label [[BB3_I_I]]
+; CHECK-NEXT:i2 0, label [[BB3_I_I]]
+; CHECK-NEXT:]
+; CHECK:   bb3.i.i:
+; CHECK-NEXT:[[TMP2:%.*]] = icmp eq i64 [[ITER1_SROA_5_0]], 0
+; CHECK-NEXT:[[TMP3]] = zext i1 [[TMP2]] to i2
+; CHECK-NEXT:[[_5_0_I_I_I_I:%.*]] = add i64 [[ITER1_SROA_5_0]], -1
+; CHECK-NEXT:[[SPEC_SELECT]] = select i1 [[TMP2]], i64 0, i64 
[[_5_0_I_I_I_I]]
+; CHECK-NEXT:[[TMP4]] = add i64 [[COUNT_1]], [[ITER1_SROA_5_0]]
+; CHECK-NEXT:br label [[BB10]]
+; CHECK:   bb12:
+; CHECK-NEXT:ret i64 [[COUNT_1]]
+;
+start:
+  br label %bb10
+
+bb10: ; preds = %bb3.i.i, %bb6
+  %iter1.sroa.5.0 = phi i64 [ 10, %start ], [ %spec.select, %bb3.i.i ]
+  %iter1.sroa.9.0 = phi i8 [ 2, %start ], [ %tmp3, %bb3.i.i ]
+  %count.1 = phi i64 [ 0, %start ],

[llvm-branch-commits] [llvm] 5c62d66 - [SimplifyCFG] Regenerate test checks (NFC)

[Nikita Popov via llvm-branch-commits]

Author: Nikita Popov
Date: 2021-01-23T21:24:54+01:00
New Revision: 5c62d661312a8408af1d6acb4195240088323898

URL: 
https://github.com/llvm/llvm-project/commit/5c62d661312a8408af1d6acb4195240088323898
DIFF: 
https://github.com/llvm/llvm-project/commit/5c62d661312a8408af1d6acb4195240088323898.diff

LOG: [SimplifyCFG] Regenerate test checks (NFC)

Added: 


Modified: 
llvm/test/Transforms/SimplifyCFG/DeadSetCC.ll

Removed: 




diff  --git a/llvm/test/Transforms/SimplifyCFG/DeadSetCC.ll 
b/llvm/test/Transforms/SimplifyCFG/DeadSetCC.ll
index 8bfb0a007cc8..62dee74b248f 100644
--- a/llvm/test/Transforms/SimplifyCFG/DeadSetCC.ll
+++ b/llvm/test/Transforms/SimplifyCFG/DeadSetCC.ll
@@ -1,5 +1,5 @@
-; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | \
-; RUN:   not grep "icmp eq"
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | 
FileCheck %s
 
 ; Check that simplifycfg deletes a dead 'seteq' instruction when it
 ; folds a conditional branch into a switch instruction.
@@ -9,20 +9,31 @@ declare void @foo()
 declare void @bar()
 
 define void @testcfg(i32 %V) {
-%C = icmp eq i32 %V, 18 ;  [#uses=1]
-%D = icmp eq i32 %V, 180;  [#uses=1]
-%E = or i1 %C, %D   ;  [#uses=1]
-br i1 %E, label %L1, label %Sw
+; CHECK-LABEL: @testcfg(
+; CHECK-NEXT:[[V_OFF:%.*]] = add i32 [[V:%.*]], -15
+; CHECK-NEXT:[[SWITCH:%.*]] = icmp ult i32 [[V_OFF]], 2
+; CHECK-NEXT:br i1 [[SWITCH]], label [[L2:%.*]], label [[L1:%.*]]
+; CHECK:   L1:
+; CHECK-NEXT:call void @foo()
+; CHECK-NEXT:ret void
+; CHECK:   L2:
+; CHECK-NEXT:call void @bar()
+; CHECK-NEXT:ret void
+;
+  %C = icmp eq i32 %V, 18
+  %D = icmp eq i32 %V, 180
+  %E = or i1 %C, %D
+  br i1 %E, label %L1, label %Sw
 Sw: ; preds = %0
-switch i32 %V, label %L1 [
- i32 15, label %L2
- i32 16, label %L2
-]
+  switch i32 %V, label %L1 [
+  i32 15, label %L2
+  i32 16, label %L2
+  ]
 L1: ; preds = %Sw, %0
-call void @foo( )
-ret void
+  call void @foo( )
+  ret void
 L2: ; preds = %Sw, %Sw
-call void @bar( )
-ret void
+  call void @bar( )
+  ret void
 }
 



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[llvm-branch-commits] [clang] 5ad038a - [Clang][OpenMP][NVPTX] Replace `libomptarget-nvptx-path` with `libomptarget-nvptx-bc-path`

[Shilei Tian via llvm-branch-commits]

Author: Shilei Tian
Date: 2021-01-23T14:42:38-05:00
New Revision: 5ad038aafa3a07a4491bf12cf6edf2026f3f17d1

URL: 
https://github.com/llvm/llvm-project/commit/5ad038aafa3a07a4491bf12cf6edf2026f3f17d1
DIFF: 
https://github.com/llvm/llvm-project/commit/5ad038aafa3a07a4491bf12cf6edf2026f3f17d1.diff

LOG: [Clang][OpenMP][NVPTX] Replace `libomptarget-nvptx-path` with 
`libomptarget-nvptx-bc-path`

D94700 removed the static library so we no longer need to pass
`-llibomptarget-nvptx` to `nvlink`. Since the bitcode library is the only device
runtime for now, instead of emitting a warning when it is not found, an error
should be raised. We also set a new option `libomptarget-nvptx-bc-path` to let
user choose which bitcode library is being used.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D95161

Added: 
clang/test/Driver/Inputs/libomptarget/libomptarget-nvptx-test.bc

Modified: 
clang/docs/ClangCommandLineReference.rst
clang/include/clang/Basic/DiagnosticDriverKinds.td
clang/include/clang/Driver/Options.td
clang/lib/Driver/ToolChains/Cuda.cpp
clang/test/Driver/openmp-offload-gpu.c

Removed: 




diff  --git a/clang/docs/ClangCommandLineReference.rst 
b/clang/docs/ClangCommandLineReference.rst
index d8ad75ce..fc42bcfe3759 100644
--- a/clang/docs/ClangCommandLineReference.rst
+++ b/clang/docs/ClangCommandLineReference.rst
@@ -1143,9 +1143,9 @@ Set directory to include search path with prefix
 
 Add directory to SYSTEM include search path, absolute paths are relative to 
-isysroot
 
-.. option:: --libomptarget-nvptx-path=
+.. option:: --libomptarget-nvptx-bc-path=
 
-Path to libomptarget-nvptx libraries
+Path to libomptarget-nvptx bitcode library
 
 .. option:: --ptxas-path=
 

diff  --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td 
b/clang/include/clang/Basic/DiagnosticDriverKinds.td
index e92a4bf1dac5..d4ad278da6b7 100644
--- a/clang/include/clang/Basic/DiagnosticDriverKinds.td
+++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td
@@ -263,12 +263,12 @@ def err_drv_omp_host_target_not_supported : Error<
   "The target '%0' is not a supported OpenMP host target.">;
 def err_drv_expecting_fopenmp_with_fopenmp_targets : Error<
   "The option -fopenmp-targets must be used in conjunction with a -fopenmp 
option compatible with offloading, please use -fopenmp=libomp or 
-fopenmp=libiomp5.">;
+def err_drv_omp_offload_target_missingbcruntime : Error<
+  "No library '%0' found in the default clang lib directory or in 
LIBRARY_PATH. Please use --libomptarget-nvptx-bc-path to specify nvptx bitcode 
library.">;
+def err_drv_omp_offload_target_bcruntime_not_found : Error<"Bitcode library 
'%0' does not exist.">;
 def warn_drv_omp_offload_target_duplicate : Warning<
   "The OpenMP offloading target '%0' is similar to target '%1' already 
specified - will be ignored.">,
   InGroup;
-def warn_drv_omp_offload_target_missingbcruntime : Warning<
-  "No library '%0' found in the default clang lib directory or in 
LIBRARY_PATH. Expect degraded performance due to no inlining of runtime 
functions on target devices.">,
-  InGroup;
 def err_drv_unsupported_embed_bitcode
 : Error<"%0 is not supported with -fembed-bitcode">;
 def err_drv_bitcode_unsupported_on_toolchain : Error<

diff  --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 3bb545f84132..7685d343ab96 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -992,8 +992,8 @@ def gpu_max_threads_per_block_EQ : Joined<["--"], 
"gpu-max-threads-per-block=">,
 def gpu_instrument_lib_EQ : Joined<["--"], "gpu-instrument-lib=">,
   HelpText<"Instrument device library for HIP, which is a LLVM bitcode 
containing "
   "__cyg_profile_func_enter and __cyg_profile_func_exit">;
-def libomptarget_nvptx_path_EQ : Joined<["--"], "libomptarget-nvptx-path=">, 
Group,
-  HelpText<"Path to libomptarget-nvptx libraries">;
+def libomptarget_nvptx_bc_path_EQ : Joined<["--"], 
"libomptarget-nvptx-bc-path=">, Group,
+  HelpText<"Path to libomptarget-nvptx bitcode library">;
 def dD : Flag<["-"], "dD">, Group, Flags<[CC1Option]>,
   HelpText<"Print macro definitions in -E mode in addition to normal output">;
 def dI : Flag<["-"], "dI">, Group, Flags<[CC1Option]>,

diff  --git a/clang/lib/Driver/ToolChains/Cuda.cpp 
b/clang/lib/Driver/ToolChains/Cuda.cpp
index 95fd5a1fbfee..4c549bf91dea 100644
--- a/clang/lib/Driver/ToolChains/Cuda.cpp
+++ b/clang/lib/Driver/ToolChains/Cuda.cpp
@@ -600,11 +600,6 @@ void NVPTX::OpenMPLinker::ConstructJob(Compilation &C, 
const JobAction &JA,
   CmdArgs.push_back("-arch");
   CmdArgs.push_back(Args.MakeArgString(GPUArch));
 
-  // Assume that the directory specified with --libomptarget_nvptx_path
-  // contains the static library libomptarget-nvptx.a.
-  if (const Arg *A = Args.getLastArg(options::OPT_libomptarget_nvptx_path_EQ))
-

[llvm-branch-commits] [llvm] e4847a7 - Revert "[Target] Use llvm::append_range (NFC)"

[Kazu Hirata via llvm-branch-commits]

Author: Kazu Hirata
Date: 2021-01-23T11:25:27-08:00
New Revision: e4847a7fcf777eedc748d2476323726960ab29b7

URL: 
https://github.com/llvm/llvm-project/commit/e4847a7fcf777eedc748d2476323726960ab29b7
DIFF: 
https://github.com/llvm/llvm-project/commit/e4847a7fcf777eedc748d2476323726960ab29b7.diff

LOG: Revert "[Target] Use llvm::append_range (NFC)"

This reverts commit cc7a23828657f35f706343982cf96bb6583d4d73.

The X86WinEHState.cpp hunk seems to break certain builds.

Added: 


Modified: 
llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
llvm/lib/Target/ARM/ARMParallelDSP.cpp
llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
llvm/lib/Target/Hexagon/RDFDeadCode.cpp
llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
llvm/lib/Target/X86/X86PartialReduction.cpp
llvm/lib/Target/X86/X86WinEHState.cpp

Removed: 




diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
index 51af25050950..4fca8bec7423 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
@@ -81,7 +81,8 @@ recursivelyVisitUsers(GlobalValue &GV,
   continue;
 }
 
-append_range(Stack, U->users());
+for (User *UU : U->users())
+  Stack.push_back(UU);
   }
 }
 

diff  --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp 
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index e959c5f0f8d3..2ce1ac51c018 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -6208,10 +6208,12 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
   SmallVector Ops;
   if (BaseOpcode->Store || BaseOpcode->Atomic)
 Ops.push_back(VData); // vdata
-  if (UseNSA)
-append_range(Ops, VAddrs);
-  else
+  if (UseNSA) {
+for (const SDValue &Addr : VAddrs)
+  Ops.push_back(Addr);
+  } else {
 Ops.push_back(VAddr);
+  }
   Ops.push_back(Op.getOperand(ArgOffset + Intr->RsrcIndex));
   if (BaseOpcode->Sampler)
 Ops.push_back(Op.getOperand(ArgOffset + Intr->SampIndex));

diff  --git a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp 
b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
index 9570680ad9cb..18ab7d7cd555 100644
--- a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
@@ -177,8 +177,10 @@ class PhiIncomingAnalysis {
 }
   }
 
-  if (Divergent && PDT.dominates(&DefBlock, MBB))
-append_range(Stack, MBB->successors());
+  if (Divergent && PDT.dominates(&DefBlock, MBB)) {
+for (MachineBasicBlock *Succ : MBB->successors())
+  Stack.push_back(Succ);
+  }
 }
 
 while (!Stack.empty()) {
@@ -187,7 +189,8 @@ class PhiIncomingAnalysis {
 continue;
   ReachableOrdered.push_back(MBB);
 
-  append_range(Stack, MBB->successors());
+  for (MachineBasicBlock *Succ : MBB->successors())
+Stack.push_back(Succ);
 }
 
 for (MachineBasicBlock *MBB : ReachableOrdered) {

diff  --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp 
b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 397979b4ab1e..f6f8597f3a69 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -3556,7 +3556,8 @@ static bool allUsersAreInFunction(const Value *V, const 
Function *F) {
   while (!Worklist.empty()) {
 auto *U = Worklist.pop_back_val();
 if (isa(U)) {
-  append_range(Worklist, U->users());
+  for (auto *UU : U->users())
+Worklist.push_back(UU);
   continue;
 }
 
@@ -19125,7 +19126,8 @@ bool ARMTargetLowering::lowerInterleavedStore(StoreInst 
*SI,
 
   SmallVector Ops;
   Ops.push_back(Builder.CreateBitCast(BaseAddr, Int8Ptr));
-  append_range(Ops, Shuffles);
+  for (auto S : Shuffles)
+Ops.push_back(S);
   Ops.push_back(Builder.getInt32(SI->getAlignment()));
   Builder.CreateCall(VstNFunc, Ops);
 } else {
@@ -19141,7 +19143,8 @@ bool ARMTargetLowering::lowerInterleavedStore(StoreInst 
*SI,
 
   SmallVector Ops;
   Ops.push_back(Builder.CreateBitCast(BaseAddr, EltPtrTy));
-  append_range(Ops, Shuffles);
+  for (auto S : Shuffles)
+Ops.push_back(S);
   for (unsigned F = 0; F < Factor; F++) {
 Ops.push_back(Builder.getInt32(F));
 Builder.CreateCall(VstNFunc, Ops);

diff  --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp 
b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
index 61a924078f29..2b53f57a7f09 100644
--- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -143,7 +143,8 @@ namespace {
   // Insert exit blocks.
   SmallVector ExitBlocks;
   ML.getEx

[llvm-branch-commits] [libcxx] 99d5fad - [libc++] Remove invalid C++20 code from a test.

[Mark de Wever via llvm-branch-commits]

Author: Mark de Wever
Date: 2021-01-23T20:10:17+01:00
New Revision: 99d5fad7a5cabac39d8a93485d1ad0ef4ba2a579

URL: 
https://github.com/llvm/llvm-project/commit/99d5fad7a5cabac39d8a93485d1ad0ef4ba2a579
DIFF: 
https://github.com/llvm/llvm-project/commit/99d5fad7a5cabac39d8a93485d1ad0ef4ba2a579.diff

LOG: [libc++] Remove invalid C++20 code from a test.

During the review of D91986 it has been discovered the in C++11
deprecated `throw()` exception specification has been removed in
C++20. Removed the part of the test code using this feature.

Added: 


Modified: 
libcxx/test/std/concepts/concept.destructible/destructible.compile.pass.cpp

Removed: 




diff  --git 
a/libcxx/test/std/concepts/concept.destructible/destructible.compile.pass.cpp 
b/libcxx/test/std/concepts/concept.destructible/destructible.compile.pass.cpp
index 709972a391cb..06c1d893fd89 100644
--- 
a/libcxx/test/std/concepts/concept.destructible/destructible.compile.pass.cpp
+++ 
b/libcxx/test/std/concepts/concept.destructible/destructible.compile.pass.cpp
@@ -34,12 +34,6 @@ struct NoexceptFalse {
   ~NoexceptFalse() noexcept(false);
 };
 
-// Since C++17 dynamic exception specifications are no longer
-// part of the standard.
-struct Throw {
-  ~Throw() throw();
-};
-
 struct Protected {
 protected:
   ~Protected() = default;
@@ -69,8 +63,6 @@ void test() {
   test();
   test();
 
-  test();
-
   test();
   test();
 



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[llvm-branch-commits] [llvm] 166d40f - [FuzzMutate] Add mutator to modify instruction flags.

[Florian Hahn via llvm-branch-commits]

Author: Florian Hahn
Date: 2021-01-23T19:05:20Z
New Revision: 166d40f2ed3db1ddd2868b23d496b4e299d99533

URL: 
https://github.com/llvm/llvm-project/commit/166d40f2ed3db1ddd2868b23d496b4e299d99533
DIFF: 
https://github.com/llvm/llvm-project/commit/166d40f2ed3db1ddd2868b23d496b4e299d99533.diff

LOG: [FuzzMutate] Add mutator to modify instruction flags.

This patch adds a new InstModificationIRStrategy to mutate flags/options
for instructions. For example, it may add or remove nuw/nsw flags from
add, mul, sub, shl instructions or change the predicate for icmp
instructions.

Subtle changes such as those mentioned above should lead to a more
interesting range of inputs. The presence or absence of overflow flags
can expose subtle bugs, for example.

Reviewed By: bogner

Differential Revision: https://reviews.llvm.org/D94905

Added: 


Modified: 
llvm/include/llvm/FuzzMutate/IRMutator.h
llvm/lib/FuzzMutate/IRMutator.cpp
llvm/tools/llvm-opt-fuzzer/llvm-opt-fuzzer.cpp
llvm/unittests/FuzzMutate/StrategiesTest.cpp

Removed: 




diff  --git a/llvm/include/llvm/FuzzMutate/IRMutator.h 
b/llvm/include/llvm/FuzzMutate/IRMutator.h
index 40a1ce8aeec9..423582eace9b 100644
--- a/llvm/include/llvm/FuzzMutate/IRMutator.h
+++ b/llvm/include/llvm/FuzzMutate/IRMutator.h
@@ -102,6 +102,17 @@ class InstDeleterIRStrategy : public IRMutationStrategy {
   void mutate(Instruction &Inst, RandomIRBuilder &IB) override;
 };
 
+class InstModificationIRStrategy : public IRMutationStrategy {
+public:
+  uint64_t getWeight(size_t CurrentSize, size_t MaxSize,
+ uint64_t CurrentWeight) override {
+return 4;
+  }
+
+  using IRMutationStrategy::mutate;
+  void mutate(Instruction &Inst, RandomIRBuilder &IB) override;
+};
+
 } // end llvm namespace
 
 #endif // LLVM_FUZZMUTATE_IRMUTATOR_H

diff  --git a/llvm/lib/FuzzMutate/IRMutator.cpp 
b/llvm/lib/FuzzMutate/IRMutator.cpp
index 2fc65981f1db..33b90097ab2c 100644
--- a/llvm/lib/FuzzMutate/IRMutator.cpp
+++ b/llvm/lib/FuzzMutate/IRMutator.cpp
@@ -197,3 +197,46 @@ void InstDeleterIRStrategy::mutate(Instruction &Inst, 
RandomIRBuilder &IB) {
   Inst.replaceAllUsesWith(RS.getSelection());
   Inst.eraseFromParent();
 }
+
+void InstModificationIRStrategy::mutate(Instruction &Inst,
+RandomIRBuilder &IB) {
+  SmallVector, 8> Modifications;
+  CmpInst *CI = nullptr;
+  GetElementPtrInst *GEP = nullptr;
+  switch (Inst.getOpcode()) {
+  default:
+break;
+  case Instruction::Add:
+  case Instruction::Mul:
+  case Instruction::Sub:
+  case Instruction::Shl:
+Modifications.push_back([&Inst]() { Inst.setHasNoSignedWrap(true); }),
+Modifications.push_back([&Inst]() { Inst.setHasNoSignedWrap(false); });
+Modifications.push_back([&Inst]() { Inst.setHasNoUnsignedWrap(true); });
+Modifications.push_back([&Inst]() { Inst.setHasNoUnsignedWrap(false); });
+
+break;
+  case Instruction::ICmp:
+CI = cast(&Inst);
+Modifications.push_back([CI]() { CI->setPredicate(CmpInst::ICMP_EQ); });
+Modifications.push_back([CI]() { CI->setPredicate(CmpInst::ICMP_NE); });
+Modifications.push_back([CI]() { CI->setPredicate(CmpInst::ICMP_UGT); });
+Modifications.push_back([CI]() { CI->setPredicate(CmpInst::ICMP_UGE); });
+Modifications.push_back([CI]() { CI->setPredicate(CmpInst::ICMP_ULT); });
+Modifications.push_back([CI]() { CI->setPredicate(CmpInst::ICMP_ULE); });
+Modifications.push_back([CI]() { CI->setPredicate(CmpInst::ICMP_SGT); });
+Modifications.push_back([CI]() { CI->setPredicate(CmpInst::ICMP_SGE); });
+Modifications.push_back([CI]() { CI->setPredicate(CmpInst::ICMP_SLT); });
+Modifications.push_back([CI]() { CI->setPredicate(CmpInst::ICMP_SLE); });
+break;
+  case Instruction::GetElementPtr:
+GEP = cast(&Inst);
+Modifications.push_back([GEP]() { GEP->setIsInBounds(true); });
+Modifications.push_back([GEP]() { GEP->setIsInBounds(false); });
+break;
+  }
+
+  auto RS = makeSampler(IB.Rand, Modifications);
+  if (RS)
+RS.getSelection()();
+}

diff  --git a/llvm/tools/llvm-opt-fuzzer/llvm-opt-fuzzer.cpp 
b/llvm/tools/llvm-opt-fuzzer/llvm-opt-fuzzer.cpp
index c0688bc399f3..dbe396d23ce2 100644
--- a/llvm/tools/llvm-opt-fuzzer/llvm-opt-fuzzer.cpp
+++ b/llvm/tools/llvm-opt-fuzzer/llvm-opt-fuzzer.cpp
@@ -51,6 +51,7 @@ std::unique_ptr createOptMutator() {
   InjectorIRStrategy::getDefaultOps()));
   Strategies.push_back(
   std::make_unique());
+  Strategies.push_back(std::make_unique());
 
   return std::make_unique(std::move(Types), std::move(Strategies));
 }

diff  --git a/llvm/unittests/FuzzMutate/StrategiesTest.cpp 
b/llvm/unittests/FuzzMutate/StrategiesTest.cpp
index e710f4676225..562d08b9a1bd 100644
--- a/llvm/unittests/FuzzMutate/StrategiesTest.cpp
+++ b/llvm/unittests/FuzzMutate/StrategiesTest.cpp
@@ -49,6 +49,17 @@ std::unique_ptr createDeleterMutator() {

[llvm-branch-commits] [polly] 3b9677e - [Polly] Track defined behavior for PHI predecessor computation.

[Michael Kruse via llvm-branch-commits]

Author: Michael Kruse
Date: 2021-01-23T13:03:49-06:00
New Revision: 3b9677e1eced0eafc17bdf3f6a41f1fd7db9f120

URL: 
https://github.com/llvm/llvm-project/commit/3b9677e1eced0eafc17bdf3f6a41f1fd7db9f120
DIFF: 
https://github.com/llvm/llvm-project/commit/3b9677e1eced0eafc17bdf3f6a41f1fd7db9f120.diff

LOG: [Polly] Track defined behavior for PHI predecessor computation.

ZoneAlgorithms's computePHI relies on being provided with consistent a
schedule to compute the statement prodecessors of a statement containing
PHINodes. Otherwise unexpected results such as PHI nodes with multiple
predecessors can occur which would result in problems in the
algorithms expecting consistent data.

In the added test case, statement instances are scrubbed from the
SCoP their execution would result in undefined behavior (Due to a nsw
overflow). As already being undefined behavior in LLVM-IR, neither
AssumedContext nor InvalidContext are updated, giving computePHI no
means to avoid these cases.

Intoduce a new SCoP property, the DefinedBehaviorContext, that among
the runtime-checked conditions, also tracks the assumptions not needing
a runtime check, in particular those affecting the assumed control flow.
This replaces the manual combination of the 3 other contexts that was
already done in computePHI and setNewAccessRelation. Currently, the only
additional assumption is that loop induction variables will nsw flag for
not wrap, but potentially more can be added. Use in
hasFeasibleRuntimeContext, isl::ast_build and gisting are other
potential uses.

To limit computational complexity, the DefinedBehaviorContext is not
availabe if it grows too large (atm hardcoded to 8 disjuncts).

Possible other fixes include bailing out in computePHI when
inconsistencies are detected, choose an arbitrary value for inconsistent
cases (since it is undefined behavior anyways), or make the code
receiving the result from ComputePHI handle inconsistent data. All of
them reduce the quality of implementation having to bail out more often
and disabling the ability to assert on actually wrong results.

This fixes llvm.org/PR48783.

Added: 
polly/test/DeLICM/pr48783.ll

Modified: 
polly/include/polly/ScopInfo.h
polly/include/polly/Support/ScopHelper.h
polly/lib/Analysis/ScopBuilder.cpp
polly/lib/Analysis/ScopInfo.cpp
polly/lib/Support/ScopHelper.cpp
polly/lib/Transform/DeLICM.cpp
polly/lib/Transform/ForwardOpTree.cpp
polly/lib/Transform/ZoneAlgo.cpp
polly/test/DeLICM/pr41656.ll
polly/test/DeLICM/reduction_looprotate_hoisted.ll
polly/test/Isl/CodeGen/exprModDiv___%for.cond---%for.end.jscop
polly/test/Isl/CodeGen/exprModDiv___%for.cond---%for.end.jscop.pow2
polly/test/Isl/CodeGen/invariant_load_parameters_cyclic_dependence.ll
polly/test/Isl/CodeGen/param_div_div_div_2.ll

polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_1.ll

polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_2.ll

polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_3.ll

polly/test/ScopInfo/NonAffine/non_affine_conditional_surrounding_affine_loop.ll

polly/test/ScopInfo/NonAffine/non_affine_conditional_surrounding_non_affine_loop.ll
polly/test/ScopInfo/NonAffine/non_affine_float_compare.ll
polly/test/ScopInfo/NonAffine/non_affine_loop_condition.ll
polly/test/ScopInfo/NonAffine/non_affine_loop_used_later.ll
polly/test/ScopInfo/avoid_new_parameters_from_geps.ll
polly/test/ScopInfo/constant_functions_as_unknowns.ll
polly/test/ScopInfo/modulo_zext_1.ll
polly/test/ScopInfo/modulo_zext_2.ll
polly/test/ScopInfo/modulo_zext_3.ll
polly/test/ScopInfo/multidim_2d_with_modref_call.ll
polly/test/ScopInfo/multidim_2d_with_modref_call_2.ll
polly/test/ScopInfo/multidim_fold_constant_dim_zero.ll
polly/test/ScopInfo/multidim_fortran_2d_with_modref_call.ll

Removed: 




diff  --git a/polly/include/polly/ScopInfo.h b/polly/include/polly/ScopInfo.h
index b4b02552f511..dbebfb2aa40e 100644
--- a/polly/include/polly/ScopInfo.h
+++ b/polly/include/polly/ScopInfo.h
@@ -1805,6 +1805,22 @@ class Scop {
   /// need to be "false". Otherwise they behave the same.
   isl::set InvalidContext;
 
+  /// The context under which the SCoP must have defined behavior. Optimizer 
and
+  /// code generator can assume that the SCoP will only be executed with
+  /// parameter values within this context. This might be either because we can
+  /// prove that other values are impossible or explicitly have undefined
+  /// behavior, such as due to no-wrap flags. If this becomes too complex, can
+  /// also be nullptr.
+  ///
+  /// In contrast to Scop::AssumedContext and Scop::InvalidContext, these do 
not
+  /// need to be checked at runtime.
+  ///
+  /// Scop::Context on the other side is an overapproximation and does not
+  /// include all requirements, but is alw

[llvm-branch-commits] [polly] 02e8a5a - [Polly] Allow param sets for dumpPw().

[Michael Kruse via llvm-branch-commits]

Author: Michael Kruse
Date: 2021-01-23T13:03:48-06:00
New Revision: 02e8a5ad3c72ac53275e1dd4de9a2449f072051b

URL: 
https://github.com/llvm/llvm-project/commit/02e8a5ad3c72ac53275e1dd4de9a2449f072051b
DIFF: 
https://github.com/llvm/llvm-project/commit/02e8a5ad3c72ac53275e1dd4de9a2449f072051b.diff

LOG: [Polly] Allow param sets for dumpPw().

Added: 


Modified: 
polly/lib/Support/ISLTools.cpp

Removed: 




diff  --git a/polly/lib/Support/ISLTools.cpp b/polly/lib/Support/ISLTools.cpp
index 9d8278ac669f2..ec4d46b8de95c 100644
--- a/polly/lib/Support/ISLTools.cpp
+++ b/polly/lib/Support/ISLTools.cpp
@@ -668,11 +668,11 @@ static int structureCompare(const isl::space &ASpace, 
const isl::space &BSpace,
   }
 
   std::string AName;
-  if (ASpace.has_tuple_name(isl::dim::set))
+  if (!ASpace.is_params() && ASpace.has_tuple_name(isl::dim::set))
 AName = ASpace.get_tuple_name(isl::dim::set);
 
   std::string BName;
-  if (BSpace.has_tuple_name(isl::dim::set))
+  if (!BSpace.is_params() && BSpace.has_tuple_name(isl::dim::set))
 BName = BSpace.get_tuple_name(isl::dim::set);
 
   int NameCompare = AName.compare(BName);



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[llvm-branch-commits] [polly] de0457a - [Polly] Clean up hasFeasibleRuntimeContext.

[Michael Kruse via llvm-branch-commits]

Author: Michael Kruse
Date: 2021-01-23T13:03:48-06:00
New Revision: de0457a013a93d6470094194ece1a1bc4eec1bad

URL: 
https://github.com/llvm/llvm-project/commit/de0457a013a93d6470094194ece1a1bc4eec1bad
DIFF: 
https://github.com/llvm/llvm-project/commit/de0457a013a93d6470094194ece1a1bc4eec1bad.diff

LOG: [Polly] Clean up hasFeasibleRuntimeContext.

Added: 


Modified: 
polly/include/polly/ScopInfo.h
polly/lib/Analysis/ScopInfo.cpp

Removed: 




diff  --git a/polly/include/polly/ScopInfo.h b/polly/include/polly/ScopInfo.h
index cdc70e00fa88..b4b02552f511 100644
--- a/polly/include/polly/ScopInfo.h
+++ b/polly/include/polly/ScopInfo.h
@@ -1904,9 +1904,6 @@ class Scop {
   void init(AAResults &AA, AssumptionCache &AC, DominatorTree &DT,
 LoopInfo &LI);
 
-  /// Add parameter constraints to @p C that imply a non-empty domain.
-  isl::set addNonEmptyDomainConstraints(isl::set C) const;
-
   /// Return the access for the base ptr of @p MA if any.
   MemoryAccess *lookupBasePtrAccess(MemoryAccess *MA);
 

diff  --git a/polly/lib/Analysis/ScopInfo.cpp b/polly/lib/Analysis/ScopInfo.cpp
index 9d2dca4ba575..0ae91d81f42d 100644
--- a/polly/lib/Analysis/ScopInfo.cpp
+++ b/polly/lib/Analysis/ScopInfo.cpp
@@ -1977,28 +1977,15 @@ bool Scop::isProfitable(bool ScalarsAreUnprofitable) 
const {
 }
 
 bool Scop::hasFeasibleRuntimeContext() const {
-  auto PositiveContext = getAssumedContext();
-  auto NegativeContext = getInvalidContext();
-  PositiveContext = addNonEmptyDomainConstraints(PositiveContext);
-  // addNonEmptyDomainConstraints returns null if ScopStmts have a null domain
-  if (!PositiveContext)
+  if (Stmts.empty())
 return false;
 
-  bool IsFeasible = !(PositiveContext.is_empty() ||
-  PositiveContext.is_subset(NegativeContext));
-  if (!IsFeasible)
-return false;
-
-  auto DomainContext = getDomains().params();
-  IsFeasible = !DomainContext.is_subset(NegativeContext);
-  IsFeasible &= !getContext().is_subset(NegativeContext);
-
-  return IsFeasible;
-}
-
-isl::set Scop::addNonEmptyDomainConstraints(isl::set C) const {
-  isl::set DomainContext = getDomains().params();
-  return C.intersect_params(DomainContext);
+  isl::set PositiveContext = getAssumedContext();
+  isl::set NegativeContext = getInvalidContext();
+  PositiveContext = PositiveContext.intersect_params(Context);
+  PositiveContext = PositiveContext.intersect_params(getDomains().params());
+  return PositiveContext.is_empty().is_false() &&
+ PositiveContext.is_subset(NegativeContext).is_false();
 }
 
 MemoryAccess *Scop::lookupBasePtrAccess(MemoryAccess *MA) {



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[llvm-branch-commits] [polly] a5b8951 - [Polly] Gist new access relations using the SCoP context.

[Michael Kruse via llvm-branch-commits]

Author: Michael Kruse
Date: 2021-01-23T13:03:48-06:00
New Revision: a5b895110f02c69465dfa605c036abf420c5acc3

URL: 
https://github.com/llvm/llvm-project/commit/a5b895110f02c69465dfa605c036abf420c5acc3
DIFF: 
https://github.com/llvm/llvm-project/commit/a5b895110f02c69465dfa605c036abf420c5acc3.diff

LOG: [Polly] Gist new access relations using the SCoP context.

This simplifies the access relations.

Added: 


Modified: 
polly/lib/Analysis/ScopInfo.cpp
polly/test/DeLICM/reduction_looprotate_hoisted.ll
polly/test/Simplify/coalesce_3partials.ll
polly/test/Simplify/coalesce_disjointelements.ll
polly/test/Simplify/coalesce_overlapping.ll
polly/test/Simplify/coalesce_partial.ll

Removed: 




diff  --git a/polly/lib/Analysis/ScopInfo.cpp b/polly/lib/Analysis/ScopInfo.cpp
index 97321c018a120..9d2dca4ba5758 100644
--- a/polly/lib/Analysis/ScopInfo.cpp
+++ b/polly/lib/Analysis/ScopInfo.cpp
@@ -1109,6 +1109,7 @@ void MemoryAccess::setNewAccessRelation(isl::map 
NewAccess) {
  "Access dims must match array dims");
 #endif
 
+  NewAccess = NewAccess.gist_params(getStatement()->getParent()->getContext());
   NewAccess = NewAccess.gist_domain(getStatement()->getDomain());
   NewAccessRelation = NewAccess;
 }

diff  --git a/polly/test/DeLICM/reduction_looprotate_hoisted.ll 
b/polly/test/DeLICM/reduction_looprotate_hoisted.ll
index 47f449564508e..abfe41b55b3d2 100644
--- a/polly/test/DeLICM/reduction_looprotate_hoisted.ll
+++ b/polly/test/DeLICM/reduction_looprotate_hoisted.ll
@@ -70,7 +70,7 @@ return:
 ; CHECK-NEXT: Stmt_reduction_preheader
 ; CHECK-NEXT: MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 
1]
 ; CHECK-NEXT: [Start] -> { Stmt_reduction_preheader[i0] -> 
MemRef_phi__phi[] };
-; CHECK-NEXT:new: [Start] -> { Stmt_reduction_preheader[i0] -> 
MemRef_A[i0] : Start >= 2147483648 or Start <= 2147483646 };
+; CHECK-NEXT:new: [Start] -> { Stmt_reduction_preheader[i0] -> 
MemRef_A[i0] : Start <= 2147483646 };
 ; CHECK-NEXT: Stmt_reduction_for
 ; CHECK-NEXT: ReadAccess :=[Reduction Type: NONE] [Scalar: 1]
 ; CHECK-NEXT: [Start] -> { Stmt_reduction_for[i0, i1] -> 
MemRef_phi__phi[] };

diff  --git a/polly/test/Simplify/coalesce_3partials.ll 
b/polly/test/Simplify/coalesce_3partials.ll
index 7df5908750141..494743b530a38 100644
--- a/polly/test/Simplify/coalesce_3partials.ll
+++ b/polly/test/Simplify/coalesce_3partials.ll
@@ -44,5 +44,5 @@ return:
 ; CHECK-NEXT: Stmt_body
 ; CHECK-NEXT: MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 
0]
 ; CHECK-NEXT: [n] -> { Stmt_body[i0] -> MemRef_A[0] };
-; CHECK-NEXT:new: [n] -> { Stmt_body[i0] -> MemRef_A[0] : n <= 
2147483647 };
+; CHECK-NEXT:new: [n] -> { Stmt_body[i0] -> MemRef_A[0] };
 ; CHECK-NEXT: }

diff  --git a/polly/test/Simplify/coalesce_disjointelements.ll 
b/polly/test/Simplify/coalesce_disjointelements.ll
index 2581be6f96eed..2d07f0ccead73 100644
--- a/polly/test/Simplify/coalesce_disjointelements.ll
+++ b/polly/test/Simplify/coalesce_disjointelements.ll
@@ -49,8 +49,8 @@ return:
 ; CHECK-NEXT: Stmt_body
 ; CHECK-NEXT: MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 
0]
 ; CHECK-NEXT: [n] -> { Stmt_body[i0] -> MemRef_A[0] };
-; CHECK-NEXT:new: [n] -> { Stmt_body[i0] -> MemRef_A[0] : n <= 
2147483647 };
+; CHECK-NEXT:new: [n] -> { Stmt_body[i0] -> MemRef_A[0] };
 ; CHECK-NEXT: MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 
0]
 ; CHECK-NEXT: [n] -> { Stmt_body[i0] -> MemRef_A[1] };
-; CHECK-NEXT:new: [n] -> { Stmt_body[i0] -> MemRef_A[1] : n <= 
2147483647 };
+; CHECK-NEXT:new: [n] -> { Stmt_body[i0] -> MemRef_A[1] };
 ; CHECK-NEXT: }

diff  --git a/polly/test/Simplify/coalesce_overlapping.ll 
b/polly/test/Simplify/coalesce_overlapping.ll
index 6df11e71d2789..bcc26f0c7b836 100644
--- a/polly/test/Simplify/coalesce_overlapping.ll
+++ b/polly/test/Simplify/coalesce_overlapping.ll
@@ -42,5 +42,5 @@ return:
 ; CHECK-NEXT: Stmt_body
 ; CHECK-NEXT: MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 
0]
 ; CHECK-NEXT: [n] -> { Stmt_body[i0] -> MemRef_A[0] };
-; CHECK-NEXT:new: [n] -> { Stmt_body[i0] -> MemRef_A[0] : n <= 
2147483647 };
+; CHECK-NEXT:new: [n] -> { Stmt_body[i0] -> MemRef_A[0] };
 ; CHECK-NEXT: }

diff  --git a/polly/test/Simplify/coalesce_partial.ll 
b/polly/test/Simplify/coalesce_partial.ll
index e16488a1bcf1d..27ed2549e6b92 100644
--- a/polly/test/Simplify/coalesce_partial.ll
+++ b/polly/test/Simplify/coalesce_partial.ll
@@ -42,5 +42,5 @@ return:
 ; CHECK-NEXT: Stmt_body
 ; CHECK-NEXT: MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 
0]
 ; CHECK-NEXT: [n] -> { Stmt_body[i0] -> MemRe

[llvm-branch-commits] [llvm] 1238378 - [llvm] Use pop_back_val (NFC)

[Kazu Hirata via llvm-branch-commits]

Author: Kazu Hirata
Date: 2021-01-23T10:56:33-08:00
New Revision: 1238378f185069f0a988ef7ffe68966eb99b1170

URL: 
https://github.com/llvm/llvm-project/commit/1238378f185069f0a988ef7ffe68966eb99b1170
DIFF: 
https://github.com/llvm/llvm-project/commit/1238378f185069f0a988ef7ffe68966eb99b1170.diff

LOG: [llvm] Use pop_back_val (NFC)

Added: 


Modified: 
llvm/lib/Transforms/Coroutines/CoroFrame.cpp
llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
llvm/lib/Transforms/Scalar/NewGVN.cpp
llvm/lib/Transforms/Scalar/Reassociate.cpp
llvm/lib/Transforms/Scalar/SCCP.cpp
llvm/lib/Transforms/Utils/FixIrreducible.cpp
llvm/lib/Transforms/Utils/LoopUnrollAndJam.cpp
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp 
b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
index b12f53032fae..3f290f2f087b 100644
--- a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
+++ b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
@@ -913,8 +913,7 @@ struct AllocaUseVisitor : PtrUseVisitor {
   // StoreAliases contains aliases of the memory location stored into.
   SmallVector StoreAliases = {AI};
   while (!StoreAliases.empty()) {
-Instruction *I = StoreAliases.back();
-StoreAliases.pop_back();
+Instruction *I = StoreAliases.pop_back_val();
 for (User *U : I->users()) {
   // If we are loading from the memory location, we are creating an
   // alias of the original pointer.
@@ -2005,8 +2004,7 @@ static void sinkSpillUsesAfterCoroBegin(Function &F,
   }
   // Recursively collect users before coro.begin.
   while (!Worklist.empty()) {
-auto *Def = Worklist.back();
-Worklist.pop_back();
+auto *Def = Worklist.pop_back_val();
 for (User *U : Def->users()) {
   auto Inst = cast(U);
   if (Dom.dominates(CoroBegin, Inst))

diff  --git a/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp 
b/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
index 877515910dcf..7998a1ae5c6e 100644
--- a/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
+++ b/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
@@ -824,8 +824,7 @@ static bool canPaddingBeAccessed(Argument *arg) {
   // sanely.
   SmallVector WorkList(arg->users());
   while (!WorkList.empty()) {
-Value *V = WorkList.back();
-WorkList.pop_back();
+Value *V = WorkList.pop_back_val();
 if (isa(V) || isa(V)) {
   if (PtrValues.insert(V).second)
 llvm::append_range(WorkList, V->users());

diff  --git a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp 
b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
index 118cbbbd418d..5dec9b542076 100644
--- a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
@@ -507,8 +507,7 @@ void Formula::canonicalize(const Loop &L) {
 
   // Keep the invariant sum in BaseRegs and one of the variant sum in 
ScaledReg.
   if (!ScaledReg) {
-ScaledReg = BaseRegs.back();
-BaseRegs.pop_back();
+ScaledReg = BaseRegs.pop_back_val();
 Scale = 1;
   }
 

diff  --git a/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp 
b/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
index 812922c49cfa..8e251ca940a3 100644
--- a/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
+++ b/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
@@ -531,8 +531,7 @@ class LowerMatrixIntrinsics {
 // list.
 LLVM_DEBUG(dbgs() << "Forward-propagate shapes:\n");
 while (!WorkList.empty()) {
-  Instruction *Inst = WorkList.back();
-  WorkList.pop_back();
+  Instruction *Inst = WorkList.pop_back_val();
 
   // New entry, set the value and insert operands
   bool Propagate = false;
@@ -602,8 +601,7 @@ class LowerMatrixIntrinsics {
 // worklist.
 LLVM_DEBUG(dbgs() << "Backward-propagate shapes:\n");
 while (!WorkList.empty()) {
-  Value *V = WorkList.back();
-  WorkList.pop_back();
+  Value *V = WorkList.pop_back_val();
 
   size_t BeforeProcessingV = WorkList.size();
   if (!isa(V))

diff  --git a/llvm/lib/Transforms/Scalar/NewGVN.cpp 
b/llvm/lib/Transforms/Scalar/NewGVN.cpp
index 13afd3b72bea..281d47c8625f 100644
--- a/llvm/lib/Transforms/Scalar/NewGVN.cpp
+++ b/llvm/lib/Transforms/Scalar/NewGVN.cpp
@@ -2876,8 +2876,7 @@ void NewGVN::cleanupTables() {
   }
 
   while (!TempInst.empty()) {
-auto *I = TempInst.back();
-TempInst.pop_back();
+auto *I = TempInst.pop_back_val();
 I->deleteValue();
   }
 

diff  --git a/llvm/lib/Transforms/Scalar/Reassociate.cpp 
b/llvm/lib/Transforms/Scalar/Reassociate.cpp
index 04e7a59c0d0c..dffeb7cc227b 100644
--- a/llvm/lib/Transforms/Scalar/Reassociate.cpp
+++ b/llvm/lib/Transforms/Scalar/Reassociate.cpp
@@ -1128,8 +1128,7 @@ static Value *EmitAddTreeOfValue

[llvm-branch-commits] [llvm] 2f1ffa9 - [llvm] Forward-declare ICFLoopSafetyInfo (NFC)

[Kazu Hirata via llvm-branch-commits]

Author: Kazu Hirata
Date: 2021-01-23T10:56:30-08:00
New Revision: 2f1ffa94d74d03417b60caa8706f84d42ee66e22

URL: 
https://github.com/llvm/llvm-project/commit/2f1ffa94d74d03417b60caa8706f84d42ee66e22
DIFF: 
https://github.com/llvm/llvm-project/commit/2f1ffa94d74d03417b60caa8706f84d42ee66e22.diff

LOG: [llvm] Forward-declare ICFLoopSafetyInfo (NFC)

LoopUtils.h needs ICFLoopSafetyInfo but relies on a forward
declaration of ICFLoopSafetyInfo in IVDescriptors.h.  This patch adds
a forward declaration right in LoopUtils.h.

While we are at it, this patch removes the one in IVDescriptors.h,
where it is unnecessary.

Added: 


Modified: 
llvm/include/llvm/Analysis/IVDescriptors.h
llvm/include/llvm/Transforms/Utils/LoopUtils.h

Removed: 




diff  --git a/llvm/include/llvm/Analysis/IVDescriptors.h 
b/llvm/include/llvm/Analysis/IVDescriptors.h
index 6bb6c4cae0a2..28546110ba04 100644
--- a/llvm/include/llvm/Analysis/IVDescriptors.h
+++ b/llvm/include/llvm/Analysis/IVDescriptors.h
@@ -32,7 +32,6 @@ class PredicatedScalarEvolution;
 class ScalarEvolution;
 class SCEV;
 class DominatorTree;
-class ICFLoopSafetyInfo;
 
 /// These are the kinds of recurrences that we support.
 enum class RecurKind {

diff  --git a/llvm/include/llvm/Transforms/Utils/LoopUtils.h 
b/llvm/include/llvm/Transforms/Utils/LoopUtils.h
index 940747b5b2ea..951660bbab28 100644
--- a/llvm/include/llvm/Transforms/Utils/LoopUtils.h
+++ b/llvm/include/llvm/Transforms/Utils/LoopUtils.h
@@ -27,6 +27,7 @@ class AliasSet;
 class AliasSetTracker;
 class BasicBlock;
 class BlockFrequencyInfo;
+class ICFLoopSafetyInfo;
 class IRBuilderBase;
 class Loop;
 class LoopInfo;



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[llvm-branch-commits] [llvm] cc7a238 - [Target] Use llvm::append_range (NFC)

[Kazu Hirata via llvm-branch-commits]

Author: Kazu Hirata
Date: 2021-01-23T10:56:31-08:00
New Revision: cc7a23828657f35f706343982cf96bb6583d4d73

URL: 
https://github.com/llvm/llvm-project/commit/cc7a23828657f35f706343982cf96bb6583d4d73
DIFF: 
https://github.com/llvm/llvm-project/commit/cc7a23828657f35f706343982cf96bb6583d4d73.diff

LOG: [Target] Use llvm::append_range (NFC)

Added: 


Modified: 
llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
llvm/lib/Target/ARM/ARMParallelDSP.cpp
llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
llvm/lib/Target/Hexagon/RDFDeadCode.cpp
llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
llvm/lib/Target/X86/X86PartialReduction.cpp
llvm/lib/Target/X86/X86WinEHState.cpp

Removed: 




diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
index 4fca8bec7423..51af25050950 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
@@ -81,8 +81,7 @@ recursivelyVisitUsers(GlobalValue &GV,
   continue;
 }
 
-for (User *UU : U->users())
-  Stack.push_back(UU);
+append_range(Stack, U->users());
   }
 }
 

diff  --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp 
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 2ce1ac51c018..e959c5f0f8d3 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -6208,12 +6208,10 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
   SmallVector Ops;
   if (BaseOpcode->Store || BaseOpcode->Atomic)
 Ops.push_back(VData); // vdata
-  if (UseNSA) {
-for (const SDValue &Addr : VAddrs)
-  Ops.push_back(Addr);
-  } else {
+  if (UseNSA)
+append_range(Ops, VAddrs);
+  else
 Ops.push_back(VAddr);
-  }
   Ops.push_back(Op.getOperand(ArgOffset + Intr->RsrcIndex));
   if (BaseOpcode->Sampler)
 Ops.push_back(Op.getOperand(ArgOffset + Intr->SampIndex));

diff  --git a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp 
b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
index 18ab7d7cd555..9570680ad9cb 100644
--- a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
@@ -177,10 +177,8 @@ class PhiIncomingAnalysis {
 }
   }
 
-  if (Divergent && PDT.dominates(&DefBlock, MBB)) {
-for (MachineBasicBlock *Succ : MBB->successors())
-  Stack.push_back(Succ);
-  }
+  if (Divergent && PDT.dominates(&DefBlock, MBB))
+append_range(Stack, MBB->successors());
 }
 
 while (!Stack.empty()) {
@@ -189,8 +187,7 @@ class PhiIncomingAnalysis {
 continue;
   ReachableOrdered.push_back(MBB);
 
-  for (MachineBasicBlock *Succ : MBB->successors())
-Stack.push_back(Succ);
+  append_range(Stack, MBB->successors());
 }
 
 for (MachineBasicBlock *MBB : ReachableOrdered) {

diff  --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp 
b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index f6f8597f3a69..397979b4ab1e 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -3556,8 +3556,7 @@ static bool allUsersAreInFunction(const Value *V, const 
Function *F) {
   while (!Worklist.empty()) {
 auto *U = Worklist.pop_back_val();
 if (isa(U)) {
-  for (auto *UU : U->users())
-Worklist.push_back(UU);
+  append_range(Worklist, U->users());
   continue;
 }
 
@@ -19126,8 +19125,7 @@ bool ARMTargetLowering::lowerInterleavedStore(StoreInst 
*SI,
 
   SmallVector Ops;
   Ops.push_back(Builder.CreateBitCast(BaseAddr, Int8Ptr));
-  for (auto S : Shuffles)
-Ops.push_back(S);
+  append_range(Ops, Shuffles);
   Ops.push_back(Builder.getInt32(SI->getAlignment()));
   Builder.CreateCall(VstNFunc, Ops);
 } else {
@@ -19143,8 +19141,7 @@ bool ARMTargetLowering::lowerInterleavedStore(StoreInst 
*SI,
 
   SmallVector Ops;
   Ops.push_back(Builder.CreateBitCast(BaseAddr, EltPtrTy));
-  for (auto S : Shuffles)
-Ops.push_back(S);
+  append_range(Ops, Shuffles);
   for (unsigned F = 0; F < Factor; F++) {
 Ops.push_back(Builder.getInt32(F));
 Builder.CreateCall(VstNFunc, Ops);

diff  --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp 
b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
index 2b53f57a7f09..61a924078f29 100644
--- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -143,8 +143,7 @@ namespace {
   // Insert exit blocks.
   SmallVector ExitBlocks;
   ML.getExitBlocks(ExitBlocks);
-  for (auto *MBB : ExitBlocks)
-Order.push_back(MBB);
+  append_range(Order, ExitBlocks);
 

[llvm-branch-commits] [llvm] d60b74c - [InstCombine] Set MadeIRChange in replaceInstUsesWith.

[Florian Hahn via llvm-branch-commits]

Author: Florian Hahn
Date: 2021-01-23T17:52:59Z
New Revision: d60b74c28a076062259ba8a8b80a9bdd802c7497

URL: 
https://github.com/llvm/llvm-project/commit/d60b74c28a076062259ba8a8b80a9bdd802c7497
DIFF: 
https://github.com/llvm/llvm-project/commit/d60b74c28a076062259ba8a8b80a9bdd802c7497.diff

LOG: [InstCombine] Set MadeIRChange in replaceInstUsesWith.

Some utilities used by InstCombine, like SimplifyLibCalls, may add new
instructions and replace the uses of a call, but return nullptr because
the inserted call produces multiple results.

Previously, the replaced library calls would get removed by
InstCombine's deleter, but after
292077072ec1279d89d21873fe900061e55ef936 this may not happen, if the
willreturn attribute is missing.

As a work-around, update replaceInstUsesWith to set MadeIRChange, if it
replaces any uses. This catches the cases where it is used as replacer
by utilities used by InstCombine and seems useful in general; updating
uses will modify the IR.

This fixes an expensive-check failure when replacing
@__sinpif/@__cospifi with @__sincospif_sret.

Added: 


Modified: 
llvm/lib/Transforms/InstCombine/InstCombineInternal.h

Removed: 




diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h 
b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h
index 5e466c5e13e7..79e9d5c46c70 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h
+++ b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h
@@ -398,6 +398,7 @@ class LLVM_LIBRARY_VISIBILITY InstCombinerImpl final
   << "with " << *V << '\n');
 
 I.replaceAllUsesWith(V);
+MadeIRChange = true;
 return &I;
   }
 



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[llvm-branch-commits] [libcxx] a8e0636 - [libc++] Implements concept destructible

[Mark de Wever via llvm-branch-commits]

Author: Mark de Wever
Date: 2021-01-23T18:17:25+01:00
New Revision: a8e06361ddba6a25fb0c27596aaa03c5423d1868

URL: 
https://github.com/llvm/llvm-project/commit/a8e06361ddba6a25fb0c27596aaa03c5423d1868
DIFF: 
https://github.com/llvm/llvm-project/commit/a8e06361ddba6a25fb0c27596aaa03c5423d1868.diff

LOG: [libc++] Implements concept destructible

Implements parts of:
- P0898R3 Standard Library Concepts
- P1754 Rename concepts to standard_case for C++20, while we still can

Reviewed By: ldionne, miscco, #libc

Differential Revision: https://reviews.llvm.org/D91004

Added: 
libcxx/test/std/concepts/concept.destructible/destructible.compile.pass.cpp

Modified: 
libcxx/docs/Cxx2aStatusPaperStatus.csv
libcxx/include/concepts

Removed: 




diff  --git a/libcxx/docs/Cxx2aStatusPaperStatus.csv 
b/libcxx/docs/Cxx2aStatusPaperStatus.csv
index 495489c4c4c8..efdcb1b67161 100644
--- a/libcxx/docs/Cxx2aStatusPaperStatus.csv
+++ b/libcxx/docs/Cxx2aStatusPaperStatus.csv
@@ -43,7 +43,7 @@
 "`P0879R0 `__","LWG","Constexpr for swap and swap 
related functions Also resolves LWG issue 2800.","Rapperswil","",""
 "`P0887R1 `__","LWG","The identity 
metafunction","Rapperswil","|Complete|","8.0"
 "`P0892R2 
`__","CWG","explicit(bool)","Rapperswil","",""
-"`P0898R3 `__","LWG","Standard Library 
Concepts","Rapperswil","",""
+"`P0898R3 `__","LWG","Standard Library 
Concepts","Rapperswil","|In Progress|",""
 "`P0935R0 `__","LWG","Eradicating unnecessarily 
explicit default constructors from the standard 
library","Rapperswil","|Complete|","12.0"
 "`P0941R2 `__","CWG","Integrating feature-test 
macros into the C++ WD","Rapperswil","|In Progress|",""
 "`P1023R0 `__","LWG","constexpr comparison 
operators for std::array","Rapperswil","|Complete|","8.0"
@@ -131,7 +131,7 @@
 "`P1651 `__","LWG","bind_front should not unwrap 
reference_wrapper","Cologne","",""
 "`P1652 `__","LWG","Printf corner cases in 
std::format","Cologne","",""
 "`P1661 `__","LWG","Remove dedicated precalculated 
hash lookup interface","Cologne","|Nothing To Do|",""
-"`P1754 `__","LWG","Rename concepts to standard_case 
for C++20, while we still can","Cologne","",""
+"`P1754 `__","LWG","Rename concepts to standard_case 
for C++20, while we still can","Cologne","|In Progress|",""
 "","","","","",""
 "`P0883 `__","LWG","Fixing Atomic 
Initialization","Belfast","* *",""
 "`P1391 `__","LWG","Range constructor for 
std::string_view","Belfast","* *",""

diff  --git a/libcxx/include/concepts b/libcxx/include/concepts
index 047e2c290f4e..cf5f9d63971f 100644
--- a/libcxx/include/concepts
+++ b/libcxx/include/concepts
@@ -157,6 +157,11 @@ concept __same_as_impl = _VSTD::_IsSame<_Tp, _Up>::value;
 template
 concept same_as = __same_as_impl<_Tp, _Up> && __same_as_impl<_Up, _Tp>;
 
+// [concept.destructible]
+
+template
+concept destructible = _VSTD::is_nothrow_destructible_v<_Tp>;
+
 #endif //_LIBCPP_STD_VER > 17 && defined(__cpp_concepts) && __cpp_concepts >= 
201811L
 
 _LIBCPP_END_NAMESPACE_STD

diff  --git 
a/libcxx/test/std/concepts/concept.destructible/destructible.compile.pass.cpp 
b/libcxx/test/std/concepts/concept.destructible/destructible.compile.pass.cpp
new file mode 100644
index ..709972a391cb
--- /dev/null
+++ 
b/libcxx/test/std/concepts/concept.destructible/destructible.compile.pass.cpp
@@ -0,0 +1,87 @@
+//===--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+// UNSUPPORTED: c++03, c++11, c++14, c++17
+// UNSUPPORTED: libcpp-no-concepts
+
+// template
+// concept destructible = is_nothrow_destructible_v;
+
+#include 
+#include 
+
+struct Empty {};
+
+struct Defaulted {
+  ~Defaulted() = default;
+};
+struct Deleted {
+  ~Deleted() = delete;
+};
+
+struct Noexcept {
+  ~Noexcept() noexcept;
+};
+struct NoexceptTrue {
+  ~NoexceptTrue() noexcept(true);
+};
+struct NoexceptFalse {
+  ~NoexceptFalse() noexcept(false);
+};
+
+// Since C++17 dynamic exception specifications are no longer
+// part of the standard.
+struct Throw {
+  ~Throw() throw();
+};
+
+struct Protected {
+protected:
+  ~Protected() = default;
+};
+struct Private {
+private:
+  ~Private() = default;
+};
+
+template 
+struct NoexceptDependant {
+  ~NoexceptDependant() noexcept(std::is_same_v);
+};
+

[llvm-branch-commits] [compiler-rt] 757b93b - [ASan] Fix broken Windows build due to 596d534ac3524052df210be8d3c01a33b2260a42.

[Dan Liew via llvm-branch-commits]

Author: Dan Liew
Date: 2021-01-23T09:09:06-08:00
New Revision: 757b93bb7b384038a8dec35433f78f5c7c2ef8b0

URL: 
https://github.com/llvm/llvm-project/commit/757b93bb7b384038a8dec35433f78f5c7c2ef8b0
DIFF: 
https://github.com/llvm/llvm-project/commit/757b93bb7b384038a8dec35433f78f5c7c2ef8b0.diff

LOG: [ASan] Fix broken Windows build due to 
596d534ac3524052df210be8d3c01a33b2260a42.

In that change I forgot to update the call to
`AsanThread::ThreadStart()` in `asan_win.cpp`.

Added: 


Modified: 
compiler-rt/lib/asan/asan_win.cpp

Removed: 




diff  --git a/compiler-rt/lib/asan/asan_win.cpp 
b/compiler-rt/lib/asan/asan_win.cpp
index 8044ae16ff9b..1577c83cf994 100644
--- a/compiler-rt/lib/asan/asan_win.cpp
+++ b/compiler-rt/lib/asan/asan_win.cpp
@@ -134,7 +134,7 @@ INTERCEPTOR(int, _except_handler4, void *a, void *b, void 
*c, void *d) {
 static thread_return_t THREAD_CALLING_CONV asan_thread_start(void *arg) {
   AsanThread *t = (AsanThread *)arg;
   SetCurrentThread(t);
-  return t->ThreadStart(GetTid(), /* signal_thread_is_registered */ nullptr);
+  return t->ThreadStart(GetTid());
 }
 
 INTERCEPTOR_WINAPI(HANDLE, CreateThread, LPSECURITY_ATTRIBUTES security,



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[llvm-branch-commits] [llvm] 1eb8c5c - [AVR] Optimize 16-bit comparison with constant

[Ben Shi via llvm-branch-commits]

Author: Ben Shi
Date: 2021-01-24T00:38:57+08:00
New Revision: 1eb8c5cd35ed0f3e06ea77a93824901f680ca1ed

URL: 
https://github.com/llvm/llvm-project/commit/1eb8c5cd35ed0f3e06ea77a93824901f680ca1ed
DIFF: 
https://github.com/llvm/llvm-project/commit/1eb8c5cd35ed0f3e06ea77a93824901f680ca1ed.diff

LOG: [AVR] Optimize 16-bit comparison with constant

Reviewed By: dylanmckay

Differential Revision: https://reviews.llvm.org/D93976

Added: 


Modified: 
llvm/lib/Target/AVR/AVRISelLowering.cpp
llvm/lib/Target/AVR/AVRISelLowering.h
llvm/test/CodeGen/AVR/cmp.ll

Removed: 




diff  --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp 
b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index bd5fd266d395..d919e08e468a 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -455,6 +455,36 @@ static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC) {
   }
 }
 
+/// Returns appropriate CP/CPI/CPC nodes code for the given 8/16-bit operands.
+SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS,
+ SelectionDAG &DAG, SDLoc DL) const {
+  assert((LHS.getSimpleValueType() == RHS.getSimpleValueType()) &&
+ "LHS and RHS have 
diff erent types");
+  assert(((LHS.getSimpleValueType() == MVT::i16) ||
+  (LHS.getSimpleValueType() == MVT::i8)) && "invalid comparison type");
+
+  SDValue Cmp;
+
+  if (LHS.getSimpleValueType() == MVT::i16 && dyn_cast(RHS)) {
+// Generate a CPI/CPC pair if RHS is a 16-bit constant.
+SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
+DAG.getIntPtrConstant(0, DL));
+SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
+DAG.getIntPtrConstant(1, DL));
+SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
+DAG.getIntPtrConstant(0, DL));
+SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
+DAG.getIntPtrConstant(1, DL));
+Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
+Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
+  } else {
+// Generate ordinary 16-bit comparison.
+Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS);
+  }
+
+  return Cmp;
+}
+
 /// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
 /// the given operands.
 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode 
CC,
@@ -567,7 +597,7 @@ SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue 
RHS, ISD::CondCode CC,
 DAG.getIntPtrConstant(1, DL));
   Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
 } else {
-  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
+  Cmp = getAVRCmp(LHSlo, RHSlo, DAG, DL);
   Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
 }
   } else if (VT == MVT::i64) {
@@ -605,7 +635,7 @@ SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue 
RHS, ISD::CondCode CC,
 DAG.getIntPtrConstant(1, DL));
   Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
 } else {
-  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS0, RHS0);
+  Cmp = getAVRCmp(LHS0, RHS0, DAG, DL);
   Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp);
   Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp);
   Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp);
@@ -619,7 +649,7 @@ SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue 
RHS, ISD::CondCode CC,
 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8,
   LHS, DAG.getIntPtrConstant(1, DL)));
 } else {
-  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS);
+  Cmp = getAVRCmp(LHS, RHS, DAG, DL);
 }
   } else {
 llvm_unreachable("Invalid comparison size");

diff  --git a/llvm/lib/Target/AVR/AVRISelLowering.h 
b/llvm/lib/Target/AVR/AVRISelLowering.h
index ed9aea7a3297..29d814b6c952 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.h
+++ b/llvm/lib/Target/AVR/AVRISelLowering.h
@@ -138,6 +138,8 @@ class AVRTargetLowering : public TargetLowering {
 private:
   SDValue getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc,
 SelectionDAG &DAG, SDLoc dl) const;
+  SDValue getAVRCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
+SDLoc dl) const;
   SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;

diff  --git a/llvm/test/CodeGen/AVR/cmp.ll b/llvm/test/CodeGen/AVR/cmp.ll
index b3224087a689..e9769068f911 100644
--- a/llvm/test/CodeGen/AVR/cmp.ll
+++ b/ll

[llvm-branch-commits] [llvm] a6f0221 - [SLP] fix fast-math-flag propagation on FP reductions

[Sanjay Patel via llvm-branch-commits]

Author: Sanjay Patel
Date: 2021-01-23T11:17:20-05:00
New Revision: a6f02212764a76935ec5fb704fe86a1a76f65745

URL: 
https://github.com/llvm/llvm-project/commit/a6f02212764a76935ec5fb704fe86a1a76f65745
DIFF: 
https://github.com/llvm/llvm-project/commit/a6f02212764a76935ec5fb704fe86a1a76f65745.diff

LOG: [SLP] fix fast-math-flag propagation on FP reductions

As shown in the test diffs, we could miscompile by
propagating flags that did not exist in the original
code.

The flags required for fmin/fmax reductions will be
fixed in a follow-up patch.

Added: 


Modified: 
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll

Removed: 




diff  --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp 
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 78ce4870588c..6c2b10e5b9fa 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -6820,12 +6820,18 @@ class HorizontalReduction {
 if (NumReducedVals < 4)
   return false;
 
-// FIXME: Fast-math-flags should be set based on the instructions in the
-//reduction (not all of 'fast' are required).
+// Intersect the fast-math-flags from all reduction operations.
+FastMathFlags RdxFMF;
+RdxFMF.set();
+for (ReductionOpsType &RdxOp : ReductionOps) {
+  for (Value *RdxVal : RdxOp) {
+if (auto *FPMO = dyn_cast(RdxVal))
+  RdxFMF &= FPMO->getFastMathFlags();
+  }
+}
+
 IRBuilder<> Builder(cast(ReductionRoot));
-FastMathFlags Unsafe;
-Unsafe.setFast();
-Builder.setFastMathFlags(Unsafe);
+Builder.setFastMathFlags(RdxFMF);
 
 BoUpSLP::ExtraValueToDebugLocsMap ExternallyUsedValues;
 // The same extra argument may be used several times, so log each attempt
@@ -7071,9 +7077,6 @@ class HorizontalReduction {
 assert(isPowerOf2_32(ReduxWidth) &&
"We only handle power-of-two reductions for now");
 
-// FIXME: The builder should use an FMF guard. It should not be hard-coded
-//to 'fast'.
-assert(Builder.getFastMathFlags().isFast() && "Expected 'fast' FMF");
 return createSimpleTargetReduction(Builder, TTI, VectorizedValue, RdxKind,
ReductionOps.back());
   }

diff  --git a/llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll 
b/llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
index 38d36c676fa7..03ec04cb8cbe 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
@@ -1766,7 +1766,6 @@ bb.1:
   ret void
 }
 
-; FIXME: This is a miscompile.
 ; The FMF on the reduction should match the incoming insts.
 
 define float @fadd_v4f32_fmf(float* %p) {
@@ -1776,7 +1775,7 @@ define float @fadd_v4f32_fmf(float* %p) {
 ; CHECK-NEXT:[[P3:%.*]] = getelementptr inbounds float, float* [[P]], i64 3
 ; CHECK-NEXT:[[TMP1:%.*]] = bitcast float* [[P]] to <4 x float>*
 ; CHECK-NEXT:[[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 
4
-; CHECK-NEXT:[[TMP3:%.*]] = call fast float 
@llvm.vector.reduce.fadd.v4f32(float -0.00e+00, <4 x float> [[TMP2]])
+; CHECK-NEXT:[[TMP3:%.*]] = call reassoc nsz float 
@llvm.vector.reduce.fadd.v4f32(float -0.00e+00, <4 x float> [[TMP2]])
 ; CHECK-NEXT:ret float [[TMP3]]
 ;
 ; STORE-LABEL: @fadd_v4f32_fmf(
@@ -1785,7 +1784,7 @@ define float @fadd_v4f32_fmf(float* %p) {
 ; STORE-NEXT:[[P3:%.*]] = getelementptr inbounds float, float* [[P]], i64 3
 ; STORE-NEXT:[[TMP1:%.*]] = bitcast float* [[P]] to <4 x float>*
 ; STORE-NEXT:[[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 
4
-; STORE-NEXT:[[TMP3:%.*]] = call fast float 
@llvm.vector.reduce.fadd.v4f32(float -0.00e+00, <4 x float> [[TMP2]])
+; STORE-NEXT:[[TMP3:%.*]] = call reassoc nsz float 
@llvm.vector.reduce.fadd.v4f32(float -0.00e+00, <4 x float> [[TMP2]])
 ; STORE-NEXT:ret float [[TMP3]]
 ;
   %p1 = getelementptr inbounds float, float* %p, i64 1
@@ -1801,6 +1800,10 @@ define float @fadd_v4f32_fmf(float* %p) {
   ret float %add3
 }
 
+; The minimal FMF for fadd reduction are "reassoc nsz".
+; Only the common FMF of all operations in the reduction propagate to the 
result.
+; In this example, "contract nnan arcp" are dropped, but "ninf" transfers with 
the required flags.
+
 define float @fadd_v4f32_fmf_intersect(float* %p) {
 ; CHECK-LABEL: @fadd_v4f32_fmf_intersect(
 ; CHECK-NEXT:[[P1:%.*]] = getelementptr inbounds float, float* [[P:%.*]], 
i64 1
@@ -1808,7 +1811,7 @@ define float @fadd_v4f32_fmf_intersect(float* %p) {
 ; CHECK-NEXT:[[P3:%.*]] = getelementptr inbounds float, float* [[P]], i64 3
 ; CHECK-NEXT:[[TMP1:%.*]] = bitcast float* [[P]] to <4 x float>*
 ; CHECK-NEXT:[[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 
4
-; CHECK-NEXT:[[TMP3:%.*]] = cal

[llvm-branch-commits] [llvm] 39e1e53 - [SLP] add reduction test with mixed fast-math-flags; NFC

[Sanjay Patel via llvm-branch-commits]

Author: Sanjay Patel
Date: 2021-01-23T11:17:20-05:00
New Revision: 39e1e53a7c162652c6c138d1bcf50d2766fe9561

URL: 
https://github.com/llvm/llvm-project/commit/39e1e53a7c162652c6c138d1bcf50d2766fe9561
DIFF: 
https://github.com/llvm/llvm-project/commit/39e1e53a7c162652c6c138d1bcf50d2766fe9561.diff

LOG: [SLP] add reduction test with mixed fast-math-flags; NFC

Added: 


Modified: 
llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll

Removed: 




diff  --git a/llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll 
b/llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
index 8e175f1acda9..38d36c676fa7 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
@@ -1801,4 +1801,36 @@ define float @fadd_v4f32_fmf(float* %p) {
   ret float %add3
 }
 
+define float @fadd_v4f32_fmf_intersect(float* %p) {
+; CHECK-LABEL: @fadd_v4f32_fmf_intersect(
+; CHECK-NEXT:[[P1:%.*]] = getelementptr inbounds float, float* [[P:%.*]], 
i64 1
+; CHECK-NEXT:[[P2:%.*]] = getelementptr inbounds float, float* [[P]], i64 2
+; CHECK-NEXT:[[P3:%.*]] = getelementptr inbounds float, float* [[P]], i64 3
+; CHECK-NEXT:[[TMP1:%.*]] = bitcast float* [[P]] to <4 x float>*
+; CHECK-NEXT:[[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 
4
+; CHECK-NEXT:[[TMP3:%.*]] = call fast float 
@llvm.vector.reduce.fadd.v4f32(float -0.00e+00, <4 x float> [[TMP2]])
+; CHECK-NEXT:ret float [[TMP3]]
+;
+; STORE-LABEL: @fadd_v4f32_fmf_intersect(
+; STORE-NEXT:[[P1:%.*]] = getelementptr inbounds float, float* [[P:%.*]], 
i64 1
+; STORE-NEXT:[[P2:%.*]] = getelementptr inbounds float, float* [[P]], i64 2
+; STORE-NEXT:[[P3:%.*]] = getelementptr inbounds float, float* [[P]], i64 3
+; STORE-NEXT:[[TMP1:%.*]] = bitcast float* [[P]] to <4 x float>*
+; STORE-NEXT:[[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 
4
+; STORE-NEXT:[[TMP3:%.*]] = call fast float 
@llvm.vector.reduce.fadd.v4f32(float -0.00e+00, <4 x float> [[TMP2]])
+; STORE-NEXT:ret float [[TMP3]]
+;
+  %p1 = getelementptr inbounds float, float* %p, i64 1
+  %p2 = getelementptr inbounds float, float* %p, i64 2
+  %p3 = getelementptr inbounds float, float* %p, i64 3
+  %t0 = load float, float* %p, align 4
+  %t1 = load float, float* %p1, align 4
+  %t2 = load float, float* %p2, align 4
+  %t3 = load float, float* %p3, align 4
+  %add1 = fadd ninf reassoc nsz nnan float %t1, %t0
+  %add2 = fadd ninf reassoc nsz nnan arcp float %t2, %add1
+  %add3 = fadd ninf reassoc nsz contract float %t3, %add2
+  ret float %add3
+}
+
 declare i32 @__gxx_personality_v0(...)



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[llvm-branch-commits] [llvm] 2920770 - [Local] Treat calls that may not return as being alive.

[Florian Hahn via llvm-branch-commits]

Author: Florian Hahn
Date: 2021-01-23T16:05:14Z
New Revision: 292077072ec1279d89d21873fe900061e55ef936

URL: 
https://github.com/llvm/llvm-project/commit/292077072ec1279d89d21873fe900061e55ef936
DIFF: 
https://github.com/llvm/llvm-project/commit/292077072ec1279d89d21873fe900061e55ef936.diff

LOG: [Local] Treat calls that may not return as being alive.

With the addition of the `willreturn` attribute, functions that may
not return (e.g. due to an infinite loop) are well defined, if they are
not marked as `willreturn`.

This patch updates `wouldInstructionBeTriviallyDead` to not consider
calls that may not return as dead.

This patch still provides an escape hatch for intrinsics, which are
still assumed as willreturn unconditionally. It will be removed once
all intrinsics definitions have been reviewed and updated.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D94106

Added: 


Modified: 
llvm/include/llvm/IR/InstrTypes.h
llvm/lib/Transforms/Utils/Local.cpp
llvm/test/Feature/OperandBundles/early-cse.ll
llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll
llvm/test/Transforms/Attributor/align.ll
llvm/test/Transforms/Attributor/nocapture-1.ll
llvm/test/Transforms/Attributor/nocapture-2.ll
llvm/test/Transforms/Attributor/nonnull.ll
llvm/test/Transforms/Attributor/norecurse.ll
llvm/test/Transforms/Attributor/range.ll
llvm/test/Transforms/Attributor/readattrs.ll
llvm/test/Transforms/BDCE/basic.ll
llvm/test/Transforms/CodeGenPrepare/X86/delete-assume-dead-code.ll
llvm/test/Transforms/Coroutines/coro-split-00.ll
llvm/test/Transforms/Coroutines/coro-split-hidden.ll
llvm/test/Transforms/Coroutines/no-suspend.ll
llvm/test/Transforms/DeadStoreElimination/MSSA/simple.ll

llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/DeleteThrowableInst.ll
llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/simple.ll
llvm/test/Transforms/Inline/dead-calls-willreturn.ll
llvm/test/Transforms/InstCombine/constant-fold-libfunc.ll
llvm/test/Transforms/InstCombine/nothrow.ll
llvm/test/Transforms/InstSimplify/ConstProp/rint.ll
llvm/test/Transforms/InstSimplify/remove-dead-call.ll
llvm/test/Transforms/InstSimplify/returned.ll
llvm/test/Transforms/MemCpyOpt/memcpy.ll
llvm/test/Transforms/NewGVN/eliminate-callsite-inline.ll
llvm/test/Transforms/OpenMP/parallel_deletion.ll
llvm/test/Transforms/Reassociate/erase_inst_made_change.ll

Removed: 




diff  --git a/llvm/include/llvm/IR/InstrTypes.h 
b/llvm/include/llvm/IR/InstrTypes.h
index 7b99cc96b149..f42ef48de6b3 100644
--- a/llvm/include/llvm/IR/InstrTypes.h
+++ b/llvm/include/llvm/IR/InstrTypes.h
@@ -1756,6 +1756,10 @@ class CallBase : public Instruction {
   bool onlyReadsMemory() const {
 return doesNotAccessMemory() || hasFnAttr(Attribute::ReadOnly);
   }
+
+  /// Returns true if this function is guaranteed to return.
+  bool willReturn() const { return hasFnAttr(Attribute::WillReturn); }
+
   void setOnlyReadsMemory() {
 addAttribute(AttributeList::FunctionIndex, Attribute::ReadOnly);
   }

diff  --git a/llvm/lib/Transforms/Utils/Local.cpp 
b/llvm/lib/Transforms/Utils/Local.cpp
index 1f94c6191554..477ea458c763 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -420,6 +420,14 @@ bool llvm::wouldInstructionBeTriviallyDead(Instruction *I,
 return true;
   }
 
+  if (auto *CB = dyn_cast(I)) {
+// Treat calls that may not return as alive.
+// TODO: Remove the intrinsic escape hatch once all intrinsics set
+// willreturn properly.
+if (!CB->willReturn() && !isa(I))
+  return false;
+  }
+
   if (!I->mayHaveSideEffects())
 return true;
 

diff  --git a/llvm/test/Feature/OperandBundles/early-cse.ll 
b/llvm/test/Feature/OperandBundles/early-cse.ll
index cf06cd1e1f1d..1b93fe7312bf 100644
--- a/llvm/test/Feature/OperandBundles/early-cse.ll
+++ b/llvm/test/Feature/OperandBundles/early-cse.ll
@@ -5,8 +5,8 @@
 ; they're carrying unknown operand bundles since the presence of
 ; unknown operand bundles implies arbitrary memory effects.
 
-declare void @readonly_function() readonly nounwind
-declare void @readnone_function() readnone nounwind
+declare void @readonly_function() readonly nounwind willreturn
+declare void @readnone_function() readnone nounwind willreturn
 
 define i32 @test0(i32* %x) {
 ; CHECK-LABEL: @test0(

diff  --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll 
b/llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll
index 47c5eba84b77..cafdba142cac 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll
@@ -17,16 +17,32 @@ target triple = "x86_64-unknown-linux-gnu"
 @a = internal global %struct.Foo { i32 1, i64 2 }, align 8
 
 define void @run() {
-; NOT_CGSCC_NPM: Func

[llvm-branch-commits] [llvm] 25531a1 - [AVR] Optimize 8-bit logic left/right shifts

[Ben Shi via llvm-branch-commits]

Author: Ben Shi
Date: 2021-01-23T23:54:16+08:00
New Revision: 25531a1d9657897e648d93f776a3abb70e9816ef

URL: 
https://github.com/llvm/llvm-project/commit/25531a1d9657897e648d93f776a3abb70e9816ef
DIFF: 
https://github.com/llvm/llvm-project/commit/25531a1d9657897e648d93f776a3abb70e9816ef.diff

LOG: [AVR] Optimize 8-bit logic left/right shifts

Reviewed By: dylanmckay

Differential Revision: https://reviews.llvm.org/D89047

Added: 


Modified: 
llvm/lib/Target/AVR/AVRISelLowering.cpp
llvm/lib/Target/AVR/AVRISelLowering.h
llvm/lib/Target/AVR/AVRInstrInfo.td
llvm/test/CodeGen/AVR/ctlz.ll
llvm/test/CodeGen/AVR/ctpop.ll
llvm/test/CodeGen/AVR/cttz.ll
llvm/test/CodeGen/AVR/shift.ll

Removed: 




diff  --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp 
b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index 9a464d0a52d8..bd5fd266d395 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -334,6 +334,24 @@ SDValue AVRTargetLowering::LowerShifts(SDValue Op, 
SelectionDAG &DAG) const {
 llvm_unreachable("Invalid shift opcode");
   }
 
+  // Optimize int8 shifts.
+  if (VT.getSizeInBits() == 8) {
+if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) {
+  // Optimize LSL when 4 <= ShiftAmount <= 6.
+  Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
+  Victim =
+  DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0xf0, dl, VT));
+  ShiftAmount -= 4;
+} else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount &&
+   ShiftAmount < 7) {
+  // Optimize LSR when 4 <= ShiftAmount <= 6.
+  Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
+  Victim =
+  DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0x0f, dl, VT));
+  ShiftAmount -= 4;
+}
+  }
+
   while (ShiftAmount--) {
 Victim = DAG.getNode(Opc8, dl, VT, Victim);
   }

diff  --git a/llvm/lib/Target/AVR/AVRISelLowering.h 
b/llvm/lib/Target/AVR/AVRISelLowering.h
index d1eaf53b15e9..ed9aea7a3297 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.h
+++ b/llvm/lib/Target/AVR/AVRISelLowering.h
@@ -56,6 +56,8 @@ enum NodeType {
   CMPC,
   /// Test for zero or minus instruction.
   TST,
+  /// Swap Rd[7:4] <-> Rd[3:0].
+  SWAP,
   /// Operand 0 and operand 1 are selection variable, operand 2
   /// is condition code and operand 3 is flag operand.
   SELECT_CC

diff  --git a/llvm/lib/Target/AVR/AVRInstrInfo.td 
b/llvm/lib/Target/AVR/AVRInstrInfo.td
index 8de85f6b36c5..926d1f853a37 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.td
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -67,6 +67,9 @@ def AVRrolLoop : SDNode<"AVRISD::ROLLOOP", SDTIntShiftOp>;
 def AVRrorLoop : SDNode<"AVRISD::RORLOOP", SDTIntShiftOp>;
 def AVRasrLoop : SDNode<"AVRISD::ASRLOOP", SDTIntShiftOp>;
 
+// SWAP node.
+def AVRSwap : SDNode<"AVRISD::SWAP", SDTIntUnaryOp>;
+
 
//===--===//
 // AVR Operands, Complex Patterns and Transformations Definitions.
 
//===--===//
@@ -1729,7 +1732,7 @@ def SWAPRd : FRd<0b1001,
  (outs GPR8:$rd),
  (ins GPR8:$src),
  "swap\t$rd",
- [(set i8:$rd, (bswap i8:$src))]>;
+ [(set i8:$rd, (AVRSwap i8:$src))]>;
 
 // IO register bit set/clear operations.
 //:TODO: add patterns when popcount(imm)==2 to be expanded with 2 sbi/cbi

diff  --git a/llvm/test/CodeGen/AVR/ctlz.ll b/llvm/test/CodeGen/AVR/ctlz.ll
index 8681b8a3f1f5..93c2f0bdfa41 100644
--- a/llvm/test/CodeGen/AVR/ctlz.ll
+++ b/llvm/test/CodeGen/AVR/ctlz.ll
@@ -10,8 +10,7 @@ declare i8 @llvm.ctlz.i8(i8)
 
 ; CHECK-LABEL: count_leading_zeros:
 ; CHECK: cpi[[RESULT:r[0-9]+]], 0
-; CHECK: brne   .LBB0_1
-; CHECK: rjmp   .LBB0_2
+; CHECK: breq   .LBB0_2
 ; CHECK: mov[[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
 ; CHECK: lsr{{.*}}[[SCRATCH]]
 ; CHECK: or {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
@@ -20,10 +19,8 @@ declare i8 @llvm.ctlz.i8(i8)
 ; CHECK: lsr{{.*}}[[RESULT]]
 ; CHECK: or {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
 ; CHECK: mov{{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
-; CHECK: lsr{{.*}}[[SCRATCH]]
-; CHECK: lsr{{.*}}[[SCRATCH]]
-; CHECK: lsr{{.*}}[[SCRATCH]]
-; CHECK: lsr{{.*}}[[SCRATCH]]
+; CHECK: swap   {{.*}}[[SCRATCH]]
+; CHECK: andi   {{.*}}[[SCRATCH]], 15
 ; CHECK: or {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
 ; CHECK: com{{.*}}[[SCRATCH]]
 ; CHECK: mov{{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
@@ -37,10 +34,7 @@ declare i8 @llvm.ctlz.i8(i8)
 ; CHECK: andi   {{.*}}[[SCRATCH]], 51
 ; CHECK: add{{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
 ; CHECK: mov{{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
-; CHECK: lsr{{.*}}[[RESULT]]
-; CHECK: lsr{{.*}}[[RESULT]]
-; CHECK: lsr{{.*}}[[RESULT]]
-; CHECK: lsr{{.*}}[[RESULT]]
+; CHECK: swap 

[llvm-branch-commits] [lldb] 2bbc762 - [lldb/Lua] add 'Lua' before naming versions

[Pedro Tammela via llvm-branch-commits]

Author: Pedro Tammela
Date: 2021-01-23T15:20:54Z
New Revision: 2bbc762b8ff843cab89230c0a5feeb801c21c376

URL: 
https://github.com/llvm/llvm-project/commit/2bbc762b8ff843cab89230c0a5feeb801c21c376
DIFF: 
https://github.com/llvm/llvm-project/commit/2bbc762b8ff843cab89230c0a5feeb801c21c376.diff

LOG: [lldb/Lua] add 'Lua' before naming versions

NFC

Added: 


Modified: 
lldb/bindings/lua/lua-typemaps.swig

Removed: 




diff  --git a/lldb/bindings/lua/lua-typemaps.swig 
b/lldb/bindings/lua/lua-typemaps.swig
index 24983dc0061b..32435b9c5a6c 100644
--- a/lldb/bindings/lua/lua-typemaps.swig
+++ b/lldb/bindings/lua/lua-typemaps.swig
@@ -4,7 +4,7 @@
 
 
//===--===//
 
-// In 5.3 and beyond the VM supports integers, so we need to remap
+// In Lua 5.3 and beyond the VM supports integers, so we need to remap
 // SWIG's internal handling of integers.
 
 



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[llvm-branch-commits] [lldb] 5997e89 - [lldb/Lua] add initial Lua typemaps

[Pedro Tammela via llvm-branch-commits]

Author: Pedro Tammela
Date: 2021-01-23T14:53:11Z
New Revision: 5997e8987f681c54c266ab2d422528de9235b25f

URL: 
https://github.com/llvm/llvm-project/commit/5997e8987f681c54c266ab2d422528de9235b25f
DIFF: 
https://github.com/llvm/llvm-project/commit/5997e8987f681c54c266ab2d422528de9235b25f.diff

LOG: [lldb/Lua] add initial Lua typemaps

This patch adds the integer handling typemaps and the typemap for
string returning functions.

The integer handling typemaps overrides SWIG's own typemaps to distinct
the handling of integers from floating point.

The typemap for string returning functions is a port of Python's
typemap.

Differential Revision: https://reviews.llvm.org/D94937

Added: 


Modified: 
lldb/bindings/lua/lua-typemaps.swig

Removed: 




diff  --git a/lldb/bindings/lua/lua-typemaps.swig 
b/lldb/bindings/lua/lua-typemaps.swig
index 28d63fa2f402..24983dc0061b 100644
--- a/lldb/bindings/lua/lua-typemaps.swig
+++ b/lldb/bindings/lua/lua-typemaps.swig
@@ -1 +1,96 @@
 %include 
+
+// FIXME: We need to port more typemaps from Python
+
+//===--===//
+
+// In 5.3 and beyond the VM supports integers, so we need to remap
+// SWIG's internal handling of integers.
+
+
+%define LLDB_NUMBER_TYPEMAP(TYPE)
+
+// Primitive integer mapping
+%typemap(in,checkfn="lua_isinteger") TYPE
+%{ $1 = (TYPE)lua_tointeger(L, $input); %}
+%typemap(in,checkfn="lua_isinteger") const TYPE&($basetype temp)
+%{ temp=($basetype)lua_tointeger(L,$input); $1=&temp;%}
+%typemap(out) TYPE
+%{ lua_pushinteger(L, (lua_Integer) $1); SWIG_arg++;%}
+%typemap(out) const TYPE&
+%{ lua_pushinteger(L, (lua_Integer) $1); SWIG_arg++;%}
+
+// Pointer and reference mapping
+%typemap(in,checkfn="lua_isinteger") TYPE *INPUT($*ltype temp), TYPE 
&INPUT($*ltype temp)
+%{ temp = ($*ltype)lua_tointeger(L,$input);
+   $1 = &temp; %}
+%typemap(in, numinputs=0) TYPE *OUTPUT ($*ltype temp)
+%{ $1 = &temp; %}
+%typemap(argout) TYPE *OUTPUT
+%{  lua_pushinteger(L, (lua_Integer) *$1); SWIG_arg++;%}
+%typemap(in) TYPE *INOUT = TYPE *INPUT;
+%typemap(argout) TYPE *INOUT = TYPE *OUTPUT;
+%typemap(in) TYPE &OUTPUT = TYPE *OUTPUT;
+%typemap(argout) TYPE &OUTPUT = TYPE *OUTPUT;
+%typemap(in) TYPE &INOUT = TYPE *INPUT;
+%typemap(argout) TYPE &INOUT = TYPE *OUTPUT;
+%typemap(in,checkfn="lua_isinteger") const TYPE *INPUT($*ltype temp)
+%{ temp = ($*ltype)lua_tointeger(L,$input);
+   $1 = &temp; %}
+
+%enddef // LLDB_NUMBER_TYPEMAP
+
+LLDB_NUMBER_TYPEMAP(unsigned char);
+LLDB_NUMBER_TYPEMAP(signed char);
+LLDB_NUMBER_TYPEMAP(short);
+LLDB_NUMBER_TYPEMAP(unsigned short);
+LLDB_NUMBER_TYPEMAP(signed short);
+LLDB_NUMBER_TYPEMAP(int);
+LLDB_NUMBER_TYPEMAP(unsigned int);
+LLDB_NUMBER_TYPEMAP(signed int);
+LLDB_NUMBER_TYPEMAP(long);
+LLDB_NUMBER_TYPEMAP(unsigned long);
+LLDB_NUMBER_TYPEMAP(signed long);
+LLDB_NUMBER_TYPEMAP(long long);
+LLDB_NUMBER_TYPEMAP(unsigned long long);
+LLDB_NUMBER_TYPEMAP(signed long long);
+
+%apply unsigned long { size_t };
+%apply const unsigned long & { const size_t & };
+%apply long { ssize_t };
+%apply const long & { const ssize_t & };
+
+//===--===//
+
+// Typemap definitions to allow SWIG to properly handle char buffer.
+
+// typemap for a char buffer
+%typemap(in) (char *dst, size_t dst_len) {
+   $2 = luaL_checkinteger(L, $input);
+   if ($2 <= 0) {
+   return luaL_error(L, "Positive integer expected");
+   }
+   $1 = (char *) malloc($2);
+}
+
+// SBProcess::ReadCStringFromMemory() uses a void*, but needs to be treated
+// as char data instead of byte data.
+%typemap(in) (void *char_buf, size_t size) = (char *dst, size_t dst_len);
+
+// Return the char buffer.  Discarding any previous return result
+%typemap(argout) (char *dst, size_t dst_len) {
+   lua_pop(L, 1); // Blow away the previous result
+   if ($result == 0) {
+  lua_pushliteral(L, "");
+   } else {
+  lua_pushlstring(L, (const char *)$1, $result);
+   }
+   free($1);
+   // SWIG_arg was already incremented
+}
+
+// SBProcess::ReadCStringFromMemory() uses a void*, but needs to be treated
+// as char data instead of byte data.
+%typemap(argout) (void *char_buf, size_t size) = (char *dst, size_t dst_len);
+
+//===--===//



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[llvm-branch-commits] [llvm] d5c4de4 - [gn build] Port 0057cc5a215e

[LLVM GN Syncbot via llvm-branch-commits]

Author: LLVM GN Syncbot
Date: 2021-01-23T14:07:39Z
New Revision: d5c4de40c679f07c575db1fb5c5893cb93b3d30e

URL: 
https://github.com/llvm/llvm-project/commit/d5c4de40c679f07c575db1fb5c5893cb93b3d30e
DIFF: 
https://github.com/llvm/llvm-project/commit/d5c4de40c679f07c575db1fb5c5893cb93b3d30e.diff

LOG: [gn build] Port 0057cc5a215e

Added: 


Modified: 
llvm/utils/gn/secondary/clang/lib/Frontend/BUILD.gn

Removed: 




diff  --git a/llvm/utils/gn/secondary/clang/lib/Frontend/BUILD.gn 
b/llvm/utils/gn/secondary/clang/lib/Frontend/BUILD.gn
index 40755a40ada4..1e4d3679cd53 100644
--- a/llvm/utils/gn/secondary/clang/lib/Frontend/BUILD.gn
+++ b/llvm/utils/gn/secondary/clang/lib/Frontend/BUILD.gn
@@ -21,7 +21,6 @@ static_library("Frontend") {
 "ASTConsumers.cpp",
 "ASTMerge.cpp",
 "ASTUnit.cpp",
-"AssemblerInvocation.cpp",
 "ChainedDiagnosticConsumer.cpp",
 "ChainedIncludesSource.cpp",
 "CompilerInstance.cpp",



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[llvm-branch-commits] [clang] 0057cc5 - Revert "[Clang] Move assembler into a separate file"

[Ayke van Laethem via llvm-branch-commits]

Author: Ayke van Laethem
Date: 2021-01-23T15:04:27+01:00
New Revision: 0057cc5a215e5a26cfbd7e1707b55bf05fa9b6bf

URL: 
https://github.com/llvm/llvm-project/commit/0057cc5a215e5a26cfbd7e1707b55bf05fa9b6bf
DIFF: 
https://github.com/llvm/llvm-project/commit/0057cc5a215e5a26cfbd7e1707b55bf05fa9b6bf.diff

LOG: Revert "[Clang] Move assembler into a separate file"

This reverts commit 2325157c0568ffd16f3318ad54f947e4e2109ef6.

Unfortunately this commit produces linker errors on some builds:
http://lab.llvm.org:8011/#/builders/57/builds/3704
http://lab.llvm.org:8011/#/builders/112/builds/3216
http://lab.llvm.org:8011/#/builders/121/builds/3900

Added: 


Modified: 
clang/lib/Frontend/CMakeLists.txt
clang/tools/driver/cc1as_main.cpp

Removed: 
clang/include/clang/Frontend/AssemblerInvocation.h
clang/lib/Frontend/AssemblerInvocation.cpp



diff  --git a/clang/include/clang/Frontend/AssemblerInvocation.h 
b/clang/include/clang/Frontend/AssemblerInvocation.h
deleted file mode 100644
index 8644f6c14228..
--- a/clang/include/clang/Frontend/AssemblerInvocation.h
+++ /dev/null
@@ -1,126 +0,0 @@
-//===- AssemblerInvocation.h - Assembler Invocation Helper Data -*- C++ 
-*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===--===//
-
-#ifndef LLVM_CLANG_FRONTEND_ASSEMBLERINVOCATION_H
-#define LLVM_CLANG_FRONTEND_ASSEMBLERINVOCATION_H
-
-#include "llvm/MC/MCTargetOptions.h"
-
-namespace clang {
-
-/// Helper class for representing a single invocation of the assembler.
-struct AssemblerInvocation {
-  /// @name Target Options
-  /// @{
-
-  /// The name of the target triple to assemble for.
-  std::string Triple;
-
-  /// If given, the name of the target CPU to determine which instructions
-  /// are legal.
-  std::string CPU;
-
-  /// The list of target specific features to enable or disable -- this should
-  /// be a list of strings starting with '+' or '-'.
-  std::vector Features;
-
-  /// The list of symbol definitions.
-  std::vector SymbolDefs;
-
-  /// @}
-  /// @name Language Options
-  /// @{
-
-  std::vector IncludePaths;
-  unsigned NoInitialTextSection : 1;
-  unsigned SaveTemporaryLabels : 1;
-  unsigned GenDwarfForAssembly : 1;
-  unsigned RelaxELFRelocations : 1;
-  unsigned DwarfVersion;
-  std::string DwarfDebugFlags;
-  std::string DwarfDebugProducer;
-  std::string DebugCompilationDir;
-  std::map DebugPrefixMap;
-  llvm::DebugCompressionType CompressDebugSections =
-  llvm::DebugCompressionType::None;
-  std::string MainFileName;
-  std::string SplitDwarfOutput;
-
-  /// @}
-  /// @name Frontend Options
-  /// @{
-
-  std::string InputFile;
-  std::vector LLVMArgs;
-  std::string OutputPath;
-  enum FileType {
-FT_Asm,  ///< Assembly (.s) output, transliterate mode.
-FT_Null, ///< No output, for timing purposes.
-FT_Obj   ///< Object file output.
-  };
-  FileType OutputType;
-  unsigned ShowHelp : 1;
-  unsigned ShowVersion : 1;
-
-  /// @}
-  /// @name Transliterate Options
-  /// @{
-
-  unsigned OutputAsmVariant;
-  unsigned ShowEncoding : 1;
-  unsigned ShowInst : 1;
-
-  /// @}
-  /// @name Assembler Options
-  /// @{
-
-  unsigned RelaxAll : 1;
-  unsigned NoExecStack : 1;
-  unsigned FatalWarnings : 1;
-  unsigned NoWarn : 1;
-  unsigned IncrementalLinkerCompatible : 1;
-  unsigned EmbedBitcode : 1;
-
-  /// The name of the relocation model to use.
-  std::string RelocationModel;
-
-  /// The ABI targeted by the backend. Specified using -target-abi. Empty
-  /// otherwise.
-  std::string TargetABI;
-
-  /// @}
-
-public:
-  AssemblerInvocation() {
-Triple = "";
-NoInitialTextSection = 0;
-InputFile = "-";
-OutputPath = "-";
-OutputType = FT_Asm;
-OutputAsmVariant = 0;
-ShowInst = 0;
-ShowEncoding = 0;
-RelaxAll = 0;
-NoExecStack = 0;
-FatalWarnings = 0;
-NoWarn = 0;
-IncrementalLinkerCompatible = 0;
-DwarfVersion = 0;
-EmbedBitcode = 0;
-  }
-
-  static bool CreateFromArgs(AssemblerInvocation &Res,
- ArrayRef Argv,
- DiagnosticsEngine &Diags);
-};
-
-bool ExecuteAssembler(AssemblerInvocation &Opts, DiagnosticsEngine &Diags);
-
-} // namespace clang
-
-#endif // LLVM_CLANG_FRONTEND_ASSEMBLERINVOCATION_H

diff  --git a/clang/lib/Frontend/AssemblerInvocation.cpp 
b/clang/lib/Frontend/AssemblerInvocation.cpp
deleted file mode 100644
index 7f6944c60379..
--- a/clang/lib/Frontend/AssemblerInvocation.cpp
+++ /dev/null
@@ -1,432 +0,0 @@
-//===- AssemblerInvocation.cpp 
-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
-// See https

[llvm-branch-commits] [llvm] 022da61 - [SimplifyCFG] Change 'LoopHeaders' to be ArrayRef, not a naked set, thus avoiding dangling pointers

[Roman Lebedev via llvm-branch-commits]

Author: Roman Lebedev
Date: 2021-01-23T16:48:35+03:00
New Revision: 022da61f6b30626708e5b4c1c009afb453d12ebe

URL: 
https://github.com/llvm/llvm-project/commit/022da61f6b30626708e5b4c1c009afb453d12ebe
DIFF: 
https://github.com/llvm/llvm-project/commit/022da61f6b30626708e5b4c1c009afb453d12ebe.diff

LOG: [SimplifyCFG] Change 'LoopHeaders' to be ArrayRef, not a naked 
set, thus avoiding dangling pointers

If i change it to AssertingVH instead, a number of existing tests fail,
which means we don't consistently remove from the set when deleting blocks,
which means newly-created blocks may happen to appear in that set
if they happen to occupy the same memory chunk as did some block
that was in the set originally.

There are many places where we delete blocks,
and while we could probably consistently delete from LoopHeaders
when deleting a block in transforms located in SimplifyCFG.cpp itself,
transforms located elsewhere (Local.cpp/BasicBlockUtils.cpp) also may
delete blocks, and it doesn't seem good to teach them to deal with it.

Since we at most only ever delete from LoopHeaders,
let's just delegate to WeakVH to do that automatically.

But to be honest, personally, i'm not sure that the idea
behind LoopHeaders is sound.

Added: 


Modified: 
llvm/include/llvm/Transforms/Utils/Local.h
llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp
llvm/lib/Transforms/Utils/SimplifyCFG.cpp

Removed: 




diff  --git a/llvm/include/llvm/Transforms/Utils/Local.h 
b/llvm/include/llvm/Transforms/Utils/Local.h
index ebfb62a48bbf..c712dda483e4 100644
--- a/llvm/include/llvm/Transforms/Utils/Local.h
+++ b/llvm/include/llvm/Transforms/Utils/Local.h
@@ -16,7 +16,6 @@
 
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/STLExtras.h"
-#include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/TinyPtrVector.h"
 #include "llvm/Analysis/Utils/Local.h"
@@ -177,7 +176,7 @@ extern cl::opt RequireAndPreserveDomTree;
 bool simplifyCFG(BasicBlock *BB, const TargetTransformInfo &TTI,
  DomTreeUpdater *DTU = nullptr,
  const SimplifyCFGOptions &Options = {},
- SmallPtrSetImpl *LoopHeaders = nullptr);
+ ArrayRef LoopHeaders = {});
 
 /// This function is used to flatten a CFG. For example, it uses parallel-and
 /// and parallel-or mode to collapse if-conditions and merge if-regions with

diff  --git a/llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp 
b/llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp
index 0e1ec7194527..38e7109ead57 100644
--- a/llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp
+++ b/llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp
@@ -36,6 +36,7 @@
 #include "llvm/IR/Instructions.h"
 #include "llvm/IR/IntrinsicInst.h"
 #include "llvm/IR/Module.h"
+#include "llvm/IR/ValueHandle.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/CommandLine.h"
@@ -200,9 +201,12 @@ static bool iterativelySimplifyCFG(Function &F, const 
TargetTransformInfo &TTI,
 
   SmallVector, 32> Edges;
   FindFunctionBackedges(F, Edges);
-  SmallPtrSet LoopHeaders;
+  SmallPtrSet UniqueLoopHeaders;
   for (unsigned i = 0, e = Edges.size(); i != e; ++i)
-LoopHeaders.insert(const_cast(Edges[i].second));
+UniqueLoopHeaders.insert(const_cast(Edges[i].second));
+
+  SmallVector LoopHeaders(UniqueLoopHeaders.begin(),
+  UniqueLoopHeaders.end());
 
   while (LocalChange) {
 LocalChange = false;
@@ -219,7 +223,7 @@ static bool iterativelySimplifyCFG(Function &F, const 
TargetTransformInfo &TTI,
 while (BBIt != F.end() && DTU->isBBPendingDeletion(&*BBIt))
   ++BBIt;
   }
-  if (simplifyCFG(&BB, TTI, DTU, Options, &LoopHeaders)) {
+  if (simplifyCFG(&BB, TTI, DTU, Options, LoopHeaders)) {
 LocalChange = true;
 ++NumSimpl;
   }

diff  --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp 
b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index bad8d90cda65..deaa0bbcf772 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -61,6 +61,7 @@
 #include "llvm/IR/Use.h"
 #include "llvm/IR/User.h"
 #include "llvm/IR/Value.h"
+#include "llvm/IR/ValueHandle.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
@@ -218,7 +219,7 @@ class SimplifyCFGOpt {
   const TargetTransformInfo &TTI;
   DomTreeUpdater *DTU;
   const DataLayout &DL;
-  SmallPtrSetImpl *LoopHeaders;
+  ArrayRef LoopHeaders;
   const SimplifyCFGOptions &Options;
   bool Resimplify;
 
@@ -261,8 +262,7 @@ class SimplifyCFGOpt {
 
 public:
   SimplifyCFGOpt(const TargetTransformInfo &TTI, DomTreeUpdater *DTU,
- const DataLayout &DL,
- SmallPtrSetImpl *LoopHeaders,
+ const DataLayout &DL, ArrayRef LoopHeaders,
  const SimplifyCFGOptions &Opts)
   

[llvm-branch-commits] [llvm] dbf87da - [gn build] Port 2325157c0568

[LLVM GN Syncbot via llvm-branch-commits]

Author: LLVM GN Syncbot
Date: 2021-01-23T13:38:51Z
New Revision: dbf87da739ba8ce4a3abc1f893045006a62eecbf

URL: 
https://github.com/llvm/llvm-project/commit/dbf87da739ba8ce4a3abc1f893045006a62eecbf
DIFF: 
https://github.com/llvm/llvm-project/commit/dbf87da739ba8ce4a3abc1f893045006a62eecbf.diff

LOG: [gn build] Port 2325157c0568

Added: 


Modified: 
llvm/utils/gn/secondary/clang/lib/Frontend/BUILD.gn

Removed: 




diff  --git a/llvm/utils/gn/secondary/clang/lib/Frontend/BUILD.gn 
b/llvm/utils/gn/secondary/clang/lib/Frontend/BUILD.gn
index 1e4d3679cd53..40755a40ada4 100644
--- a/llvm/utils/gn/secondary/clang/lib/Frontend/BUILD.gn
+++ b/llvm/utils/gn/secondary/clang/lib/Frontend/BUILD.gn
@@ -21,6 +21,7 @@ static_library("Frontend") {
 "ASTConsumers.cpp",
 "ASTMerge.cpp",
 "ASTUnit.cpp",
+"AssemblerInvocation.cpp",
 "ChainedDiagnosticConsumer.cpp",
 "ChainedIncludesSource.cpp",
 "CompilerInstance.cpp",



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[llvm-branch-commits] [clang] 2325157 - [Clang] Move assembler into a separate file

[Ayke van Laethem via llvm-branch-commits]

Author: Ayke van Laethem
Date: 2021-01-23T14:34:23+01:00
New Revision: 2325157c0568ffd16f3318ad54f947e4e2109ef6

URL: 
https://github.com/llvm/llvm-project/commit/2325157c0568ffd16f3318ad54f947e4e2109ef6
DIFF: 
https://github.com/llvm/llvm-project/commit/2325157c0568ffd16f3318ad54f947e4e2109ef6.diff

LOG: [Clang] Move assembler into a separate file

This change adds an AssemblerInvocation class, similar to the
CompilerInvocation class. It can be used to invoke cc1as directly.

The project I'm working on wants to compile Clang and use it as a static
library. For that to work, there must be a way to invoke the assembler
programmatically, using the same arguments as you would otherwise pass
to cc1as.

Differential Revision: https://reviews.llvm.org/D63852

Added: 
clang/include/clang/Frontend/AssemblerInvocation.h
clang/lib/Frontend/AssemblerInvocation.cpp

Modified: 
clang/lib/Frontend/CMakeLists.txt
clang/tools/driver/cc1as_main.cpp

Removed: 




diff  --git a/clang/include/clang/Frontend/AssemblerInvocation.h 
b/clang/include/clang/Frontend/AssemblerInvocation.h
new file mode 100644
index ..8644f6c14228
--- /dev/null
+++ b/clang/include/clang/Frontend/AssemblerInvocation.h
@@ -0,0 +1,126 @@
+//===- AssemblerInvocation.h - Assembler Invocation Helper Data -*- C++ 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CLANG_FRONTEND_ASSEMBLERINVOCATION_H
+#define LLVM_CLANG_FRONTEND_ASSEMBLERINVOCATION_H
+
+#include "llvm/MC/MCTargetOptions.h"
+
+namespace clang {
+
+/// Helper class for representing a single invocation of the assembler.
+struct AssemblerInvocation {
+  /// @name Target Options
+  /// @{
+
+  /// The name of the target triple to assemble for.
+  std::string Triple;
+
+  /// If given, the name of the target CPU to determine which instructions
+  /// are legal.
+  std::string CPU;
+
+  /// The list of target specific features to enable or disable -- this should
+  /// be a list of strings starting with '+' or '-'.
+  std::vector Features;
+
+  /// The list of symbol definitions.
+  std::vector SymbolDefs;
+
+  /// @}
+  /// @name Language Options
+  /// @{
+
+  std::vector IncludePaths;
+  unsigned NoInitialTextSection : 1;
+  unsigned SaveTemporaryLabels : 1;
+  unsigned GenDwarfForAssembly : 1;
+  unsigned RelaxELFRelocations : 1;
+  unsigned DwarfVersion;
+  std::string DwarfDebugFlags;
+  std::string DwarfDebugProducer;
+  std::string DebugCompilationDir;
+  std::map DebugPrefixMap;
+  llvm::DebugCompressionType CompressDebugSections =
+  llvm::DebugCompressionType::None;
+  std::string MainFileName;
+  std::string SplitDwarfOutput;
+
+  /// @}
+  /// @name Frontend Options
+  /// @{
+
+  std::string InputFile;
+  std::vector LLVMArgs;
+  std::string OutputPath;
+  enum FileType {
+FT_Asm,  ///< Assembly (.s) output, transliterate mode.
+FT_Null, ///< No output, for timing purposes.
+FT_Obj   ///< Object file output.
+  };
+  FileType OutputType;
+  unsigned ShowHelp : 1;
+  unsigned ShowVersion : 1;
+
+  /// @}
+  /// @name Transliterate Options
+  /// @{
+
+  unsigned OutputAsmVariant;
+  unsigned ShowEncoding : 1;
+  unsigned ShowInst : 1;
+
+  /// @}
+  /// @name Assembler Options
+  /// @{
+
+  unsigned RelaxAll : 1;
+  unsigned NoExecStack : 1;
+  unsigned FatalWarnings : 1;
+  unsigned NoWarn : 1;
+  unsigned IncrementalLinkerCompatible : 1;
+  unsigned EmbedBitcode : 1;
+
+  /// The name of the relocation model to use.
+  std::string RelocationModel;
+
+  /// The ABI targeted by the backend. Specified using -target-abi. Empty
+  /// otherwise.
+  std::string TargetABI;
+
+  /// @}
+
+public:
+  AssemblerInvocation() {
+Triple = "";
+NoInitialTextSection = 0;
+InputFile = "-";
+OutputPath = "-";
+OutputType = FT_Asm;
+OutputAsmVariant = 0;
+ShowInst = 0;
+ShowEncoding = 0;
+RelaxAll = 0;
+NoExecStack = 0;
+FatalWarnings = 0;
+NoWarn = 0;
+IncrementalLinkerCompatible = 0;
+DwarfVersion = 0;
+EmbedBitcode = 0;
+  }
+
+  static bool CreateFromArgs(AssemblerInvocation &Res,
+ ArrayRef Argv,
+ DiagnosticsEngine &Diags);
+};
+
+bool ExecuteAssembler(AssemblerInvocation &Opts, DiagnosticsEngine &Diags);
+
+} // namespace clang
+
+#endif // LLVM_CLANG_FRONTEND_ASSEMBLERINVOCATION_H

diff  --git a/clang/lib/Frontend/AssemblerInvocation.cpp 
b/clang/lib/Frontend/AssemblerInvocation.cpp
new file mode 100644
index ..7f6944c60379
--- /dev/null
+++ b/clang/lib/Frontend/AssemblerInvocation.cpp
@@ -0,0 +1,432 @@
+//===- AssemblerInvocation.cpp 

[llvm-branch-commits] [llvm] a49a3a3 - [LSR] Add test for PR46943 (NFC)

[Nikita Popov via llvm-branch-commits]

Author: Nikita Popov
Date: 2021-01-23T13:53:09+01:00
New Revision: a49a3a3ed568244b12d6f553240485696e084f4a

URL: 
https://github.com/llvm/llvm-project/commit/a49a3a3ed568244b12d6f553240485696e084f4a
DIFF: 
https://github.com/llvm/llvm-project/commit/a49a3a3ed568244b12d6f553240485696e084f4a.diff

LOG: [LSR] Add test for PR46943 (NFC)

LSR should be dropping nowrap flags when adding new postinc users.

Added: 
llvm/test/Transforms/LoopStrengthReduce/X86/pr46943.ll

Modified: 


Removed: 




diff  --git a/llvm/test/Transforms/LoopStrengthReduce/X86/pr46943.ll 
b/llvm/test/Transforms/LoopStrengthReduce/X86/pr46943.ll
new file mode 100644
index ..e8f192d3c488
--- /dev/null
+++ b/llvm/test/Transforms/LoopStrengthReduce/X86/pr46943.ll
@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -loop-reduce < %s | FileCheck %s
+
+target datalayout = 
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+declare void @use(i8 zeroext)
+declare void @use_p(i8*)
+
+define i8 @drop_nuw() {
+; CHECK-LABEL: @drop_nuw(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:br label [[LOOP:%.*]]
+; CHECK:   loop:
+; CHECK-NEXT:[[IV:%.*]] = phi i8 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], 
[[LOOP]] ]
+; CHECK-NEXT:call void @use(i8 [[IV]])
+; CHECK-NEXT:[[IV_NEXT]] = add nuw i8 [[IV]], 1
+; CHECK-NEXT:[[CMP:%.*]] = icmp eq i8 [[IV_NEXT]], 0
+; CHECK-NEXT:br i1 [[CMP]], label [[EXIT:%.*]], label [[LOOP]]
+; CHECK:   exit:
+; CHECK-NEXT:[[TMP0:%.*]] = add i8 [[IV_NEXT]], -1
+; CHECK-NEXT:ret i8 [[TMP0]]
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i8 [ 0, %entry ], [ %iv.next, %loop ]
+  call void @use(i8 %iv)
+
+  %iv.next = add nuw i8 %iv, 1
+  %cmp = icmp eq i8 %iv, -1
+  br i1 %cmp, label %exit, label %loop
+
+exit:
+  ret i8 %iv
+}
+
+define i8 @drop_nsw() {
+; CHECK-LABEL: @drop_nsw(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:br label [[LOOP:%.*]]
+; CHECK:   loop:
+; CHECK-NEXT:[[IV:%.*]] = phi i8 [ 127, [[ENTRY:%.*]] ], [ 
[[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT:call void @use(i8 [[IV]])
+; CHECK-NEXT:[[IV_NEXT]] = add nsw i8 [[IV]], -1
+; CHECK-NEXT:[[CMP:%.*]] = icmp eq i8 [[IV_NEXT]], 127
+; CHECK-NEXT:br i1 [[CMP]], label [[EXIT:%.*]], label [[LOOP]]
+; CHECK:   exit:
+; CHECK-NEXT:[[TMP0:%.*]] = add i8 [[IV_NEXT]], 1
+; CHECK-NEXT:ret i8 [[TMP0]]
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i8 [ 127, %entry ], [ %iv.next, %loop ]
+  call void @use(i8 %iv)
+
+  %iv.next = add nsw i8 %iv, -1
+  %cmp = icmp eq i8 %iv, -128
+  br i1 %cmp, label %exit, label %loop
+
+exit:
+  ret i8 %iv
+}
+
+define i8 @already_postinc() {
+; CHECK-LABEL: @already_postinc(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:br label [[LOOP:%.*]]
+; CHECK:   loop:
+; CHECK-NEXT:[[IV:%.*]] = phi i8 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], 
[[LOOP]] ]
+; CHECK-NEXT:call void @use(i8 [[IV]])
+; CHECK-NEXT:[[IV_NEXT]] = add nuw i8 [[IV]], 1
+; CHECK-NEXT:[[CMP:%.*]] = icmp eq i8 [[IV_NEXT]], -1
+; CHECK-NEXT:br i1 [[CMP]], label [[EXIT:%.*]], label [[LOOP]]
+; CHECK:   exit:
+; CHECK-NEXT:[[TMP0:%.*]] = add i8 [[IV_NEXT]], -1
+; CHECK-NEXT:ret i8 [[TMP0]]
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i8 [ 0, %entry ], [ %iv.next, %loop ]
+  call void @use(i8 %iv)
+
+  %iv.next = add nuw i8 %iv, 1
+  %cmp = icmp eq i8 %iv.next, -1
+  br i1 %cmp, label %exit, label %loop
+
+exit:
+  ret i8 %iv
+}



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[llvm-branch-commits] [llvm] 08dbcc1 - [LTO] Store target attributes as vector of strings (NFC).

[Florian Hahn via llvm-branch-commits]

Author: Florian Hahn
Date: 2021-01-23T12:11:58Z
New Revision: 08dbcc14e254396cd5765994cab97274003611bb

URL: 
https://github.com/llvm/llvm-project/commit/08dbcc14e254396cd5765994cab97274003611bb
DIFF: 
https://github.com/llvm/llvm-project/commit/08dbcc14e254396cd5765994cab97274003611bb.diff

LOG: [LTO] Store target attributes as vector of strings (NFC).

The target features are obtained as a list of features/attributes.
Instead of storing them in a single string, store the vector. This
matches lto::Config's behavior and simplifies the transition to
lto::backend().

Reviewed By: tejohnson

Differential Revision: https://reviews.llvm.org/D95224

Added: 


Modified: 
llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h
llvm/lib/LTO/LTOCodeGenerator.cpp
llvm/tools/llvm-lto/llvm-lto.cpp
llvm/tools/lto/lto.cpp

Removed: 




diff  --git a/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h 
b/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h
index a817969abc58..f76cc5fbed49 100644
--- a/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h
+++ b/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h
@@ -93,7 +93,7 @@ struct LTOCodeGenerator {
   void setFileType(CodeGenFileType FT) { FileType = FT; }
 
   void setCpu(StringRef MCpu) { this->MCpu = std::string(MCpu); }
-  void setAttr(StringRef MAttr) { this->MAttr = std::string(MAttr); }
+  void setAttrs(std::vector MAttrs) { this->MAttrs = MAttrs; }
   void setOptLevel(unsigned OptLevel);
 
   void setShouldInternalize(bool Value) { ShouldInternalize = Value; }
@@ -223,7 +223,7 @@ struct LTOCodeGenerator {
   std::vector CodegenOptions;
   std::string FeatureStr;
   std::string MCpu;
-  std::string MAttr;
+  std::vector MAttrs;
   std::string NativeObjectPath;
   TargetOptions Options;
   CodeGenOpt::Level CGOptLevel = CodeGenOpt::Default;

diff  --git a/llvm/lib/LTO/LTOCodeGenerator.cpp 
b/llvm/lib/LTO/LTOCodeGenerator.cpp
index cb30db193259..bdde2baffb40 100644
--- a/llvm/lib/LTO/LTOCodeGenerator.cpp
+++ b/llvm/lib/LTO/LTOCodeGenerator.cpp
@@ -361,7 +361,7 @@ bool LTOCodeGenerator::determineTarget() {
 
   // Construct LTOModule, hand over ownership of module and target. Use MAttr 
as
   // the default set of features.
-  SubtargetFeatures Features(MAttr);
+  SubtargetFeatures Features(join(MAttrs, ""));
   Features.getDefaultSubtargetFeatures(Triple);
   FeatureStr = Features.getString();
   // Set a default CPU for Darwin triples.

diff  --git a/llvm/tools/llvm-lto/llvm-lto.cpp 
b/llvm/tools/llvm-lto/llvm-lto.cpp
index ad6b78bc46a6..912a88dfbd54 100644
--- a/llvm/tools/llvm-lto/llvm-lto.cpp
+++ b/llvm/tools/llvm-lto/llvm-lto.cpp
@@ -1011,12 +1011,7 @@ int main(int argc, char **argv) {
   CodeGen.setCpu(codegen::getMCPU().c_str());
 
   CodeGen.setOptLevel(OptLevel - '0');
-
-  auto MAttrs = codegen::getMAttrs();
-  if (!MAttrs.empty()) {
-std::string attrs = join(MAttrs, ",");
-CodeGen.setAttr(attrs);
-  }
+  CodeGen.setAttrs(codegen::getMAttrs());
 
   if (auto FT = codegen::getExplicitFileType())
 CodeGen.setFileType(FT.getValue());

diff  --git a/llvm/tools/lto/lto.cpp b/llvm/tools/lto/lto.cpp
index 81f64df403ab..b48bc922bc4b 100644
--- a/llvm/tools/lto/lto.cpp
+++ b/llvm/tools/lto/lto.cpp
@@ -146,11 +146,7 @@ DEFINE_SIMPLE_CONVERSION_FUNCTIONS(LTOModule, lto_module_t)
 // Convert the subtarget features into a string to pass to LTOCodeGenerator.
 static void lto_add_attrs(lto_code_gen_t cg) {
   LTOCodeGenerator *CG = unwrap(cg);
-  auto MAttrs = codegen::getMAttrs();
-  if (!MAttrs.empty()) {
-std::string attrs = join(MAttrs, ",");
-CG->setAttr(attrs);
-  }
+  CG->setAttrs(codegen::getMAttrs());
 
   if (OptLevel < '0' || OptLevel > '3')
 report_fatal_error("Optimization level must be between 0 and 3");



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[llvm-branch-commits] [llvm] 2b9a834 - [InlineFunction] Use llvm.experimental.noalias.scope.decl for noalias arguments.

[Jeroen Dobbelaere via llvm-branch-commits]

Author: Jeroen Dobbelaere
Date: 2021-01-23T12:10:57+01:00
New Revision: 2b9a834c43cb1f93d33958c14b695896bb4e9c1e

URL: 
https://github.com/llvm/llvm-project/commit/2b9a834c43cb1f93d33958c14b695896bb4e9c1e
DIFF: 
https://github.com/llvm/llvm-project/commit/2b9a834c43cb1f93d33958c14b695896bb4e9c1e.diff

LOG: [InlineFunction] Use llvm.experimental.noalias.scope.decl for noalias 
arguments.

Insert a llvm.experimental.noalias.scope.decl intrinsic that identifies where a 
noalias argument was inlined.

This patch includes some refactorings from D90104.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D93040

Added: 
llvm/test/Transforms/Inline/noalias-calls2.ll

Modified: 
clang/test/CodeGen/aarch64-ls64.c
llvm/lib/Transforms/Utils/InlineFunction.cpp
llvm/test/Transforms/Coroutines/ArgAddr.ll
llvm/test/Transforms/Coroutines/coro-retcon-resume-values.ll
llvm/test/Transforms/Coroutines/coro-retcon-value.ll
llvm/test/Transforms/Coroutines/coro-retcon.ll
llvm/test/Transforms/Coroutines/ex2.ll
llvm/test/Transforms/Coroutines/ex3.ll
llvm/test/Transforms/Coroutines/ex4.ll
llvm/test/Transforms/Inline/launder.invariant.group.ll
llvm/test/Transforms/Inline/noalias-calls-always.ll
llvm/test/Transforms/Inline/noalias-calls.ll
llvm/test/Transforms/Inline/noalias-cs.ll
llvm/test/Transforms/Inline/noalias.ll
llvm/test/Transforms/Inline/noalias2.ll
llvm/test/Transforms/PhaseOrdering/inlining-alignment-assumptions.ll
llvm/test/Transforms/PhaseOrdering/instcombine-sroa-inttoptr.ll
llvm/test/Transforms/PhaseOrdering/pr39282.ll

Removed: 




diff  --git a/clang/test/CodeGen/aarch64-ls64.c 
b/clang/test/CodeGen/aarch64-ls64.c
index 77e4b41fbd58..17fce0094ac9 100644
--- a/clang/test/CodeGen/aarch64-ls64.c
+++ b/clang/test/CodeGen/aarch64-ls64.c
@@ -21,6 +21,7 @@ uint64_t status;
 // CHECK-NEXT:[[__ADDR_ADDR_I:%.*]] = alloca i8*, align 8
 // CHECK-NEXT:[[REF_TMP:%.*]] = alloca [[STRUCT_DATA512_T:%.*]], align 8
 // CHECK-NEXT:[[TMP0:%.*]] = load i8*, i8** @addr, align 8
+// CHECK-NEXT:call void @llvm.experimental.noalias.scope.decl(metadata !6)
 // CHECK-NEXT:store i8* [[TMP0]], i8** [[__ADDR_ADDR_I]], align 8, 
!noalias !6
 // CHECK-NEXT:[[TMP1:%.*]] = load i8*, i8** [[__ADDR_ADDR_I]], align 8, 
!noalias !6
 // CHECK-NEXT:[[VAL_I:%.*]] = getelementptr inbounds [[STRUCT_DATA512_T]], 
%struct.data512_t* [[REF_TMP]], i32 0, i32 0

diff  --git a/llvm/lib/Transforms/Utils/InlineFunction.cpp 
b/llvm/lib/Transforms/Utils/InlineFunction.cpp
index 65bf6a3b32dc..abdd2b2361b7 100644
--- a/llvm/lib/Transforms/Utils/InlineFunction.cpp
+++ b/llvm/lib/Transforms/Utils/InlineFunction.cpp
@@ -79,6 +79,12 @@ EnableNoAliasConversion("enable-noalias-to-md-conversion", 
cl::init(true),
   cl::Hidden,
   cl::desc("Convert noalias attributes to metadata during inlining."));
 
+static cl::opt
+UseNoAliasIntrinsic("use-noalias-intrinsic-during-inlining", cl::Hidden,
+cl::ZeroOrMore, cl::init(true),
+cl::desc("Use the llvm.experimental.noalias.scope.decl 
"
+ "intrinsic during inlining."));
+
 // Disabled by default, because the added alignment assumptions may increase
 // compile-time and block optimizations. This option is not suitable for use
 // with frontends that emit comprehensive parameter alignment annotations.
@@ -821,91 +827,119 @@ static void PropagateCallSiteMetadata(CallBase &CB, 
ValueToValueMapTy &VMap) {
   }
 }
 
-/// When inlining a function that contains noalias scope metadata,
-/// this metadata needs to be cloned so that the inlined blocks
-/// have 
diff erent "unique scopes" at every call site. Were this not done, then
-/// aliasing scopes from a function inlined into a caller multiple times could
-/// not be 
diff erentiated (and this would lead to miscompiles because the
-/// non-aliasing property communicated by the metadata could have
-/// call-site-specific control dependencies).
-static void CloneAliasScopeMetadata(CallBase &CB, ValueToValueMapTy &VMap) {
-  const Function *CalledFunc = CB.getCalledFunction();
+/// Utility for cloning !noalias and !alias.scope metadata. When a code region
+/// using scoped alias metadata is inlined, the aliasing relationships may not
+/// hold between the two version. It is necessary to create a deep clone of the
+/// metadata, putting the two versions in separate scope domains.
+class ScopedAliasMetadataDeepCloner {
+  using MetadataMap = DenseMap;
   SetVector MD;
-
-  // Note: We could only clone the metadata if it is already used in the
-  // caller. I'm omitting that check here because it might confuse
-  // inter-procedural alias analysis passes. We can revisit this if it becomes
-  // an efficiency or overhead problem.
-
-  for (const BasicBlock &I : *CalledFunc)
-for (const Instruction &J : I) {

[llvm-branch-commits] [llvm] 344afa8 - [Support] TrigramIndex::insert - pass std::String argument by const reference. NFCI.

[Simon Pilgrim via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2021-01-23T11:04:00Z
New Revision: 344afa853fcfcc085cb5c957b4a07c7ea013bb1b

URL: 
https://github.com/llvm/llvm-project/commit/344afa853fcfcc085cb5c957b4a07c7ea013bb1b
DIFF: 
https://github.com/llvm/llvm-project/commit/344afa853fcfcc085cb5c957b4a07c7ea013bb1b.diff

LOG: [Support] TrigramIndex::insert - pass std::String argument by const 
reference. NFCI.

Avoid string copies and fix clang-tidy warning.

Added: 


Modified: 
llvm/include/llvm/Support/TrigramIndex.h
llvm/lib/Support/TrigramIndex.cpp

Removed: 




diff  --git a/llvm/include/llvm/Support/TrigramIndex.h 
b/llvm/include/llvm/Support/TrigramIndex.h
index 360ab9459790..0be6a1012718 100644
--- a/llvm/include/llvm/Support/TrigramIndex.h
+++ b/llvm/include/llvm/Support/TrigramIndex.h
@@ -38,7 +38,7 @@ class StringRef;
 class TrigramIndex {
  public:
   /// Inserts a new Regex into the index.
-  void insert(std::string Regex);
+  void insert(const std::string &Regex);
 
   /// Returns true, if special case list definitely does not have a line
   /// that matches the query. Returns false, if it's not sure.

diff  --git a/llvm/lib/Support/TrigramIndex.cpp 
b/llvm/lib/Support/TrigramIndex.cpp
index 1f1f3022b0b3..4370adc9c3e0 100644
--- a/llvm/lib/Support/TrigramIndex.cpp
+++ b/llvm/lib/Support/TrigramIndex.cpp
@@ -25,7 +25,7 @@ static bool isAdvancedMetachar(unsigned Char) {
   return strchr(RegexAdvancedMetachars, Char) != nullptr;
 }
 
-void TrigramIndex::insert(std::string Regex) {
+void TrigramIndex::insert(const std::string &Regex) {
   if (Defeated) return;
   std::set Was;
   unsigned Cnt = 0;



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[llvm-branch-commits] [llvm] d4ce062 - [RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer

[Roger Ferrer Ibanez via llvm-branch-commits]

Author: Roger Ferrer Ibanez
Date: 2021-01-23T09:10:03Z
New Revision: d4ce062340064c3f73b8f6136c7350a5abe83cac

URL: 
https://github.com/llvm/llvm-project/commit/d4ce062340064c3f73b8f6136c7350a5abe83cac
DIFF: 
https://github.com/llvm/llvm-project/commit/d4ce062340064c3f73b8f6136c7350a5abe83cac.diff

LOG: [RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid 
making them immediately unreachable from the stack pointer

In RISC-V there is a single addressing mode of the form imm(reg) where
imm is a signed integer of 12-bit with a range of [-2048..2047] bytes
from reg.

The test MultiSource/UnitTests/C++11/frame_layout of the LLVM test-suite
exercises several scenarios with the stack, including function calls
where the stack will need to be realigned to to a local variable having
a large alignment of 4096 bytes.

In situations of large stacks, the RISC-V backend (in
RISCVFrameLowering) reserves an extra emergency spill slot which can be
used (if no free register is found) by the register scavenger after the
frame indexes have been eliminated. PrologEpilogInserter already takes
care of keeping the emergency spill slots as close as possible to the
stack pointer or frame pointer (depending on what the function will
use). However there is a final alignment step to honour the maximum
alignment of the stack that, when using the stack pointer to access the
emergency spill slots, has the side effect of setting them farther from
the stack pointer.

In the case of the frame_layout testcase, the net result is that we do
have an emergency spill slot but it is so far from the stack pointer
(more than 2048 bytes due to the extra alignment of a variable to 4096
bytes) that it becomes unreachable via any immediate offset.

During elimination of the frame index, many (regular) offsets of the
stack may be immediately unreachable already. Their address needs to be
computed using a register. A virtual register is created and later
RegisterScavenger should be able to find an unused (physical) register.
However if no register is available, RegisterScavenger will pick a
physical register and spill it onto an emergency stack slot, while we
compute the offset (restoring the chosen register after all this). This
assumes that the emergency stack slot is easily reachable (this is,
without requiring another register!).

This is the assumption we seem to break when we perform the extra
alignment in PrologEpilogInserter.

We can "float" the emergency spill slots by increasing (in absolute
value) their offsets from the incoming stack pointer. This way the
emergency spill slots will remain close to the stack pointer (once the
function has allocated storage for the stack, including the needed
realignment). The new size computed in PrologEpilogInserter is padding
so it should be OK to move the emergency spill slots there. Also because
we're increasing the alignment, the new location should stay aligned for
the purpose of the emergency spill slots.

Note that this change also impacts other backends as shown by the tests.
Changes are minor adjustments to the emergency stack slot offset.

Differential Revision: https://reviews.llvm.org/D89239

Added: 
llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir

Modified: 
llvm/lib/CodeGen/PrologEpilogInserter.cpp
llvm/test/CodeGen/AArch64/framelayout-scavengingslot.mir
llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir
llvm/test/CodeGen/AArch64/swiftself-scavenger.ll
llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
llvm/test/CodeGen/Thumb/emergency-spill-slot.ll

Removed: 




diff  --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp 
b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index 65b2165bf2a0..378aaba2a65f 100644
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -1077,7 +1077,26 @@ void PEI::calculateFrameObjectOffsets(MachineFunction 
&MF) {
 // If the frame pointer is eliminated, all frame offsets will be relative 
to
 // SP not FP. Align to MaxAlign so this works.
 StackAlign = std::max(StackAlign, MaxAlign);
+int64_t OffsetBeforeAlignment = Offset;
 Offset = alignTo(Offset, StackAlign, Skew);
+
+// If we have increased the offset to fulfill the alignment constrants,
+// then the scavenging spill slots may become harder to reach from the
+// stack pointer, float them so they stay close.
+if (OffsetBeforeAlignment != Offset && RS && !EarlyScavengingSlots) {
+  SmallVector SFIs;
+  RS->getScavengingFrameIndices(SFIs);
+  LLVM_DEBUG(if (!SFIs.empty()) llvm::dbgs()
+ << "Adjusting emergency spill slots!\n";);
+  int64_t Delta = Offset - OffsetBeforeAlignment;
+  for (SmallVectorImpl::iterator I = SFIs.begin(), IE = SFIs.end();
+   I != IE; ++I) {
+LLVM_DEBUG(llvm::dbgs() << "Adjusting offset of emergency spill slot #"
+

[llvm-branch-commits] [llvm] 267a57a - [llvm-link] Fix for an assertion when linking global with appending linkage

[Sergey Dmitriev via llvm-branch-commits]

Author: Sergey Dmitriev
Date: 2021-01-23T00:10:42-08:00
New Revision: 267a57a64572cffbb74599878bdcc9f3b678ffa3

URL: 
https://github.com/llvm/llvm-project/commit/267a57a64572cffbb74599878bdcc9f3b678ffa3
DIFF: 
https://github.com/llvm/llvm-project/commit/267a57a64572cffbb74599878bdcc9f3b678ffa3.diff

LOG: [llvm-link] Fix for an assertion when linking global with appending linkage

This patch fixes llvm-link assertion when linking external variable
declaration with a definition with appending linkage.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D95126

Added: 
llvm/test/Linker/Inputs/appending-global.ll
llvm/test/Linker/appending-global-err1.ll
llvm/test/Linker/appending-global-err2.ll
llvm/test/Linker/appending-global-err3.ll
llvm/test/Linker/appending-global-err4.ll
llvm/test/Linker/appending-global-err5.ll
llvm/test/Linker/appending-global-proto.ll

Modified: 
llvm/lib/Linker/IRMover.cpp
llvm/lib/Linker/LinkModules.cpp

Removed: 




diff  --git a/llvm/lib/Linker/IRMover.cpp b/llvm/lib/Linker/IRMover.cpp
index 5eeba0c0c3e7..6a2f84bb48a0 100644
--- a/llvm/lib/Linker/IRMover.cpp
+++ b/llvm/lib/Linker/IRMover.cpp
@@ -843,6 +843,38 @@ static void getArrayElements(const Constant *C,
 Expected
 IRLinker::linkAppendingVarProto(GlobalVariable *DstGV,
 const GlobalVariable *SrcGV) {
+  // Check that both variables have compatible properties.
+  if (DstGV && !DstGV->isDeclaration() && !SrcGV->isDeclaration()) {
+if (!SrcGV->hasAppendingLinkage() || !DstGV->hasAppendingLinkage())
+  return stringErr(
+  "Linking globals named '" + SrcGV->getName() +
+  "': can only link appending global with another appending "
+  "global!");
+
+if (DstGV->isConstant() != SrcGV->isConstant())
+  return stringErr("Appending variables linked with 
diff erent const'ness!");
+
+if (DstGV->getAlignment() != SrcGV->getAlignment())
+  return stringErr(
+  "Appending variables with 
diff erent alignment need to be linked!");
+
+if (DstGV->getVisibility() != SrcGV->getVisibility())
+  return stringErr(
+  "Appending variables with 
diff erent visibility need to be linked!");
+
+if (DstGV->hasGlobalUnnamedAddr() != SrcGV->hasGlobalUnnamedAddr())
+  return stringErr(
+  "Appending variables with 
diff erent unnamed_addr need to be linked!");
+
+if (DstGV->getSection() != SrcGV->getSection())
+  return stringErr(
+  "Appending variables with 
diff erent section name need to be linked!");
+  }
+
+  // Do not need to do anything if source is a declaration.
+  if (SrcGV->isDeclaration())
+return DstGV;
+
   Type *EltTy = cast(TypeMap.get(SrcGV->getValueType()))
 ->getElementType();
 
@@ -868,37 +900,13 @@ IRLinker::linkAppendingVarProto(GlobalVariable *DstGV,
   }
 
   uint64_t DstNumElements = 0;
-  if (DstGV) {
+  if (DstGV && !DstGV->isDeclaration()) {
 ArrayType *DstTy = cast(DstGV->getValueType());
 DstNumElements = DstTy->getNumElements();
 
-if (!SrcGV->hasAppendingLinkage() || !DstGV->hasAppendingLinkage())
-  return stringErr(
-  "Linking globals named '" + SrcGV->getName() +
-  "': can only link appending global with another appending "
-  "global!");
-
 // Check to see that they two arrays agree on type.
 if (EltTy != DstTy->getElementType())
   return stringErr("Appending variables with 
diff erent element types!");
-if (DstGV->isConstant() != SrcGV->isConstant())
-  return stringErr("Appending variables linked with 
diff erent const'ness!");
-
-if (DstGV->getAlignment() != SrcGV->getAlignment())
-  return stringErr(
-  "Appending variables with 
diff erent alignment need to be linked!");
-
-if (DstGV->getVisibility() != SrcGV->getVisibility())
-  return stringErr(
-  "Appending variables with 
diff erent visibility need to be linked!");
-
-if (DstGV->hasGlobalUnnamedAddr() != SrcGV->hasGlobalUnnamedAddr())
-  return stringErr(
-  "Appending variables with 
diff erent unnamed_addr need to be linked!");
-
-if (DstGV->getSection() != SrcGV->getSection())
-  return stringErr(
-  "Appending variables with 
diff erent section name need to be linked!");
   }
 
   SmallVector SrcElements;
@@ -928,9 +936,10 @@ IRLinker::linkAppendingVarProto(GlobalVariable *DstGV,
 
   Constant *Ret = ConstantExpr::getBitCast(NG, TypeMap.get(SrcGV->getType()));
 
-  Mapper.scheduleMapAppendingVariable(*NG,
-  DstGV ? DstGV->getInitializer() : 
nullptr,
-  IsOldStructor, SrcElements);
+  Mapper.scheduleMapAppendingVariable(
+  *NG,
+  (DstGV && !DstGV->isDeclaration()) ? DstGV->getInitializer() : nullptr,
+  IsOldStructor, SrcElements);
 
   // Replace