[llvm-branch-commits] [clang] [analyzer][docs] Admit that the cleanup attribute is not supported (PR #81834)

[Tom Stellard via llvm-branch-commits]

https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/81834
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[llvm-branch-commits] [clang] c90f200 - [analyzer][docs] Admit that the cleanup attribute is not supported (#81834)

[via llvm-branch-commits]

Author: Balazs Benics
Date: 2024-02-15T22:16:19-08:00
New Revision: c90f200b1e6d116ae8e566aae8fd86f6aa0c3808

URL: 
https://github.com/llvm/llvm-project/commit/c90f200b1e6d116ae8e566aae8fd86f6aa0c3808
DIFF: 
https://github.com/llvm/llvm-project/commit/c90f200b1e6d116ae8e566aae8fd86f6aa0c3808.diff

LOG: [analyzer][docs] Admit that the cleanup attribute is not supported (#81834)

In fact, the cleanup attribute is only added to the CFG, but still
unhandled by CSA.
I propose dropping this false "support" statement from the docs.

Added: 


Modified: 
clang/docs/ReleaseNotes.rst

Removed: 




diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 22eceea5d265ef..9edbfbfbbac02e 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1369,9 +1369,6 @@ New features
   of static analysis tools, such as the Clang Static Analyzer.
   `Documentation 
`__.
 
-- Added support for the ``cleanup`` attribute.
-  `Documentation 
`__.
-
 - Support "Deducing this" (P0847R7). (Worked out of the box)
   (`af4751738db8 
`__)
 



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[llvm-branch-commits] [llvm] release/18.x: MipsAsmParser/O32: Don't add redundant $ to $-prefixed symbol in the la macro (#80644) (PR #81810)

[Tom Stellard via llvm-branch-commits]

https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/81810
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[llvm-branch-commits] [llvm] 9cf0c29 - MipsAsmParser/O32: Don't add redundant $ to $-prefixed symbol in the la macro (#80644)

[Tom Stellard via llvm-branch-commits]

Author: YunQiang Su
Date: 2024-02-15T22:13:32-08:00
New Revision: 9cf0c2962fd26b6fc9a665b75732b44b1603e1ee

URL: 
https://github.com/llvm/llvm-project/commit/9cf0c2962fd26b6fc9a665b75732b44b1603e1ee
DIFF: 
https://github.com/llvm/llvm-project/commit/9cf0c2962fd26b6fc9a665b75732b44b1603e1ee.diff

LOG: MipsAsmParser/O32: Don't add redundant $ to $-prefixed symbol in the la 
macro (#80644)

When parsing the `la` macro, we add a duplicate `$` prefix in
`getOrCreateSymbol`,
leading to `error: Undefined temporary symbol $$yy` for code like:

```
xx:
la  $2,$yy
$yy:
nop
```

Remove the duplicate prefix.

In addition, recognize `.L`-prefixed symbols as local for O32.

See: #65020.

-

Co-authored-by: Fangrui Song 
(cherry picked from commit c007fbb19879f9b597b47ae772c53e53cdc65f29)

Added: 


Modified: 
llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/test/CodeGen/Mips/hf1_body.ll
llvm/test/MC/Mips/macro-la-pic.s

Removed: 




diff  --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp 
b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 3c673ae938fdec..36aab383da68d2 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -2920,6 +2920,11 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr 
*SymExpr,
 (Res.getSymA()->getSymbol().isELF() &&
  cast(Res.getSymA()->getSymbol()).getBinding() ==
  ELF::STB_LOCAL);
+// For O32, "$"-prefixed symbols are recognized as temporary while
+// .L-prefixed symbols are not (PrivateGlobalPrefix is "$"). Recognize ".L"
+// manually.
+if (ABI.IsO32() && Res.getSymA()->getSymbol().getName().starts_with(".L"))
+  IsLocalSym = true;
 bool UseXGOT = STI->hasFeature(Mips::FeatureXGOT) && !IsLocalSym;
 
 // The case where the result register is $25 is somewhat special. If the
@@ -6359,7 +6364,7 @@ bool MipsAsmParser::parseOperand(OperandVector , 
StringRef Mnemonic) {
   return true;
 
 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
-MCSymbol *Sym = getContext().getOrCreateSymbol("$" + Identifier);
+MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
 // Otherwise create a symbol reference.
 const MCExpr *SymRef =
 MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());

diff  --git a/llvm/test/CodeGen/Mips/hf1_body.ll 
b/llvm/test/CodeGen/Mips/hf1_body.ll
index 184ea31bddc9d2..c3dea67896210a 100644
--- a/llvm/test/CodeGen/Mips/hf1_body.ll
+++ b/llvm/test/CodeGen/Mips/hf1_body.ll
@@ -23,8 +23,8 @@ entry:
 ; ALL:   .set reorder
 ; ALL:   .reloc 0, R_MIPS_NONE, v_sf
 ; GAS:   la $25, $__fn_local_v_sf
-; IAS:   lw $25, %got($$__fn_local_v_sf)($gp)
-; IAS:   addiu $25, $25, %lo($$__fn_local_v_sf)
+; IAS:   lw $25, %got($__fn_local_v_sf)($gp)
+; IAS:   addiu $25, $25, %lo($__fn_local_v_sf)
 ; ALL:   mfc1 $4, $f12
 ; ALL:   jr $25
 ; ALL:   .end __fn_stub_v_sf

diff  --git a/llvm/test/MC/Mips/macro-la-pic.s 
b/llvm/test/MC/Mips/macro-la-pic.s
index 2303f34c35bcfe..1875952d80c4e7 100644
--- a/llvm/test/MC/Mips/macro-la-pic.s
+++ b/llvm/test/MC/Mips/macro-la-pic.s
@@ -255,3 +255,25 @@ la $25, 2f
 # XN32: lw $25, %got_disp(.Ltmp1)($gp)  # encoding: [0x8f,0x99,A,A]
 # XN32: #   fixup A - offset: 0, value: 
%got_disp(.Ltmp1), kind: fixup_Mips_GOT_DISP
 2:
+
+la $2,.Lstr
+# O32:  lw  $2, %got(.Lstr)($gp)  # encoding: [0x8f,0x82,A,A]
+# O32-NEXT:   #   fixup A - offset: 0, value: 
%got(.Lstr), kind: fixup_Mips_GOT
+# O32-NEXT: addiu   $2, $2, %lo(.Lstr)# encoding: [0x24,0x42,A,A]
+# O32-NEXT:   #   fixup A - offset: 0, value: 
%lo(.Lstr), kind: fixup_Mips_LO16
+
+# N32:  lw  $2, %got_disp(.Lstr)($gp) # encoding: [0x8f,0x82,A,A]
+# N32-NEXT:   #   fixup A - offset: 0, value: 
%got_disp(.Lstr), kind: fixup_Mips_GOT_DISP
+
+la $2,$str2
+# O32:  lw  $2, %got($str2)($gp)  # encoding: [0x8f,0x82,A,A]
+# O32-NEXT: #   fixup A - offset: 0, value: %got($str2), kind: fixup_Mips_GOT
+# O32-NEXT: addiu   $2, $2, %lo($str2)# encoding: [0x24,0x42,A,A]
+# O32-NEXT: #   fixup A - offset: 0, value: %lo($str2), kind: fixup_Mips_LO16
+
+# N32:  lw  $2, %got_disp($str2)($gp) # encoding: [0x8f,0x82,A,A]
+# N32-NEXT:   #   fixup A - offset: 0, value: 
%got_disp($str2), kind: fixup_Mips_GOT_DISP
+
+.rodata
+.Lstr: .4byte 0
+$str2: .4byte 0



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[llvm-branch-commits] [llvm] release/18.x: MipsAsmParser/O32: Don't add redundant $ to $-prefixed symbol in the la macro (#80644) (PR #81810)

[via llvm-branch-commits]

https://github.com/llvmbot updated 
https://github.com/llvm/llvm-project/pull/81810

>From 9cf0c2962fd26b6fc9a665b75732b44b1603e1ee Mon Sep 17 00:00:00 2001
From: YunQiang Su 
Date: Thu, 15 Feb 2024 04:48:55 +0800
Subject: [PATCH] MipsAsmParser/O32: Don't add redundant $ to $-prefixed symbol
 in the la macro (#80644)

When parsing the `la` macro, we add a duplicate `$` prefix in
`getOrCreateSymbol`,
leading to `error: Undefined temporary symbol $$yy` for code like:

```
xx:
la  $2,$yy
$yy:
nop
```

Remove the duplicate prefix.

In addition, recognize `.L`-prefixed symbols as local for O32.

See: #65020.

-

Co-authored-by: Fangrui Song 
(cherry picked from commit c007fbb19879f9b597b47ae772c53e53cdc65f29)
---
 .../Target/Mips/AsmParser/MipsAsmParser.cpp   |  7 +-
 llvm/test/CodeGen/Mips/hf1_body.ll|  4 ++--
 llvm/test/MC/Mips/macro-la-pic.s  | 22 +++
 3 files changed, 30 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp 
b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 3c673ae938fdec..36aab383da68d2 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -2920,6 +2920,11 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr 
*SymExpr,
 (Res.getSymA()->getSymbol().isELF() &&
  cast(Res.getSymA()->getSymbol()).getBinding() ==
  ELF::STB_LOCAL);
+// For O32, "$"-prefixed symbols are recognized as temporary while
+// .L-prefixed symbols are not (PrivateGlobalPrefix is "$"). Recognize ".L"
+// manually.
+if (ABI.IsO32() && Res.getSymA()->getSymbol().getName().starts_with(".L"))
+  IsLocalSym = true;
 bool UseXGOT = STI->hasFeature(Mips::FeatureXGOT) && !IsLocalSym;
 
 // The case where the result register is $25 is somewhat special. If the
@@ -6359,7 +6364,7 @@ bool MipsAsmParser::parseOperand(OperandVector , 
StringRef Mnemonic) {
   return true;
 
 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
-MCSymbol *Sym = getContext().getOrCreateSymbol("$" + Identifier);
+MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
 // Otherwise create a symbol reference.
 const MCExpr *SymRef =
 MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
diff --git a/llvm/test/CodeGen/Mips/hf1_body.ll 
b/llvm/test/CodeGen/Mips/hf1_body.ll
index 184ea31bddc9d2..c3dea67896210a 100644
--- a/llvm/test/CodeGen/Mips/hf1_body.ll
+++ b/llvm/test/CodeGen/Mips/hf1_body.ll
@@ -23,8 +23,8 @@ entry:
 ; ALL:   .set reorder
 ; ALL:   .reloc 0, R_MIPS_NONE, v_sf
 ; GAS:   la $25, $__fn_local_v_sf
-; IAS:   lw $25, %got($$__fn_local_v_sf)($gp)
-; IAS:   addiu $25, $25, %lo($$__fn_local_v_sf)
+; IAS:   lw $25, %got($__fn_local_v_sf)($gp)
+; IAS:   addiu $25, $25, %lo($__fn_local_v_sf)
 ; ALL:   mfc1 $4, $f12
 ; ALL:   jr $25
 ; ALL:   .end __fn_stub_v_sf
diff --git a/llvm/test/MC/Mips/macro-la-pic.s b/llvm/test/MC/Mips/macro-la-pic.s
index 2303f34c35bcfe..1875952d80c4e7 100644
--- a/llvm/test/MC/Mips/macro-la-pic.s
+++ b/llvm/test/MC/Mips/macro-la-pic.s
@@ -255,3 +255,25 @@ la $25, 2f
 # XN32: lw $25, %got_disp(.Ltmp1)($gp)  # encoding: [0x8f,0x99,A,A]
 # XN32: #   fixup A - offset: 0, value: 
%got_disp(.Ltmp1), kind: fixup_Mips_GOT_DISP
 2:
+
+la $2,.Lstr
+# O32:  lw  $2, %got(.Lstr)($gp)  # encoding: [0x8f,0x82,A,A]
+# O32-NEXT:   #   fixup A - offset: 0, value: 
%got(.Lstr), kind: fixup_Mips_GOT
+# O32-NEXT: addiu   $2, $2, %lo(.Lstr)# encoding: [0x24,0x42,A,A]
+# O32-NEXT:   #   fixup A - offset: 0, value: 
%lo(.Lstr), kind: fixup_Mips_LO16
+
+# N32:  lw  $2, %got_disp(.Lstr)($gp) # encoding: [0x8f,0x82,A,A]
+# N32-NEXT:   #   fixup A - offset: 0, value: 
%got_disp(.Lstr), kind: fixup_Mips_GOT_DISP
+
+la $2,$str2
+# O32:  lw  $2, %got($str2)($gp)  # encoding: [0x8f,0x82,A,A]
+# O32-NEXT: #   fixup A - offset: 0, value: %got($str2), kind: fixup_Mips_GOT
+# O32-NEXT: addiu   $2, $2, %lo($str2)# encoding: [0x24,0x42,A,A]
+# O32-NEXT: #   fixup A - offset: 0, value: %lo($str2), kind: fixup_Mips_LO16
+
+# N32:  lw  $2, %got_disp($str2)($gp) # encoding: [0x8f,0x82,A,A]
+# N32-NEXT:   #   fixup A - offset: 0, value: 
%got_disp($str2), kind: fixup_Mips_GOT_DISP
+
+.rodata
+.Lstr: .4byte 0
+$str2: .4byte 0

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[llvm-branch-commits] [llvm] [CFI][annotation] Leave alone function pointers in function annotations (PR #81673)

[Tom Stellard via llvm-branch-commits]

https://github.com/tstellar updated 
https://github.com/llvm/llvm-project/pull/81673

>From da970525e79f099a1c8e22655958440d9c11d11f Mon Sep 17 00:00:00 2001
From: yozhu <101743168+yo...@users.noreply.github.com>
Date: Fri, 9 Feb 2024 13:55:08 -0800
Subject: [PATCH] [CFI][annotation] Leave alone function pointers in function
 annotations (#80173)

Function annotation, as part of llvm.metadata, is for the function
itself and doesn't apply to its corresponding jump table entry, so with
CFI we shouldn't replace function pointer in function annotation with
pointer to its corresponding jump table entry.

(cherry picked from commit c7a0db1e20251f436e3d500eac03bd9be1d88b45)
---
 llvm/lib/Transforms/IPO/LowerTypeTests.cpp| 28 +++-
 .../LowerTypeTests/cfi-annotation.ll  | 68 +++
 2 files changed, 94 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/Transforms/LowerTypeTests/cfi-annotation.ll

diff --git a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp 
b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp
index 733f290b1bc93a..633fcb3314c42f 100644
--- a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp
+++ b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp
@@ -470,6 +470,9 @@ class LowerTypeTestsModule {
 
   Function *WeakInitializerFn = nullptr;
 
+  GlobalVariable *GlobalAnnotation;
+  DenseSet FunctionAnnotations;
+
   bool shouldExportConstantsAsAbsoluteSymbols();
   uint8_t *exportTypeId(StringRef TypeId, const TypeIdLowering );
   TypeIdLowering importTypeId(StringRef TypeId);
@@ -531,6 +534,10 @@ class LowerTypeTestsModule {
   /// replace each use, which is a direct function call.
   void replaceDirectCalls(Value *Old, Value *New);
 
+  bool isFunctionAnnotation(Value *V) const {
+return FunctionAnnotations.contains(V);
+  }
+
 public:
   LowerTypeTestsModule(Module , ModuleAnalysisManager ,
ModuleSummaryIndex *ExportSummary,
@@ -1377,8 +1384,11 @@ void 
LowerTypeTestsModule::replaceWeakDeclarationWithJumpTablePtr(
   // (all?) targets. Switch to a runtime initializer.
   SmallSetVector GlobalVarUsers;
   findGlobalVariableUsersOf(F, GlobalVarUsers);
-  for (auto *GV : GlobalVarUsers)
+  for (auto *GV : GlobalVarUsers) {
+if (GV == GlobalAnnotation)
+  continue;
 moveInitializerToModuleConstructor(GV);
+  }
 
   // Can not RAUW F with an expression that uses F. Replace with a temporary
   // placeholder first.
@@ -1837,6 +1847,16 @@ LowerTypeTestsModule::LowerTypeTestsModule(
   }
   OS = TargetTriple.getOS();
   ObjectFormat = TargetTriple.getObjectFormat();
+
+  // Function annotation describes or applies to function itself, and
+  // shouldn't be associated with jump table thunk generated for CFI.
+  GlobalAnnotation = M.getGlobalVariable("llvm.global.annotations");
+  if (GlobalAnnotation && GlobalAnnotation->hasInitializer()) {
+const ConstantArray *CA =
+cast(GlobalAnnotation->getInitializer());
+for (Value *Op : CA->operands())
+  FunctionAnnotations.insert(Op);
+  }
 }
 
 bool LowerTypeTestsModule::runForTesting(Module , ModuleAnalysisManager ) 
{
@@ -1896,10 +1916,14 @@ void LowerTypeTestsModule::replaceCfiUses(Function 
*Old, Value *New,
 if (isa(U.getUser()))
   continue;
 
-// Skip direct calls to externally defined or non-dso_local functions
+// Skip direct calls to externally defined or non-dso_local functions.
 if (isDirectCall(U) && (Old->isDSOLocal() || !IsJumpTableCanonical))
   continue;
 
+// Skip function annotation.
+if (isFunctionAnnotation(U.getUser()))
+  continue;
+
 // Must handle Constants specially, we cannot call replaceUsesOfWith on a
 // constant because they are uniqued.
 if (auto *C = dyn_cast(U.getUser())) {
diff --git a/llvm/test/Transforms/LowerTypeTests/cfi-annotation.ll 
b/llvm/test/Transforms/LowerTypeTests/cfi-annotation.ll
new file mode 100644
index 00..034af89112cb63
--- /dev/null
+++ b/llvm/test/Transforms/LowerTypeTests/cfi-annotation.ll
@@ -0,0 +1,68 @@
+; REQUIRES: aarch64-registered-target
+
+; RUN: opt -passes=lowertypetests %s -o %t.o
+; RUN: llvm-dis %t.o -o - | FileCheck %s --check-prefix=CHECK-foobar
+; CHECK-foobar: {{llvm.global.annotations = .*[foo|bar], .*[foo|bar],}}
+; RUN: llvm-dis %t.o -o - | FileCheck %s --check-prefix=CHECK-cfi
+; CHECK-cfi-NOT: {{llvm.global.annotations = .*cfi.*}}
+
+target triple = "aarch64-none-linux-gnu"
+
+@.src = private unnamed_addr constant [7 x i8] c"test.c\00", align 1
+@.str = private unnamed_addr constant [30 x i8] 
c"annotation_string_literal_bar\00", section "llvm.metadata"
+@.str.1 = private unnamed_addr constant [7 x i8] c"test.c\00", section 
"llvm.metadata"
+@.str.2 = private unnamed_addr constant [30 x i8] 
c"annotation_string_literal_foo\00", section "llvm.metadata"
+@llvm.global.annotations = appending global [2 x { ptr, ptr, ptr, i32, ptr }] 
[{ ptr, ptr, ptr, i32, ptr } { ptr @bar, ptr @.str, ptr @.str.1, i32 2, ptr 
null }, { ptr, ptr, ptr, i32, ptr } { ptr @foo, ptr 

[llvm-branch-commits] [clang] [llvm] [PowerPC] Update V18.1.0 release notes (PR #81631)

[Tom Stellard via llvm-branch-commits]

https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/81631
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[llvm-branch-commits] [llvm] e3c6d5a - [PowerPC] Update V18.1.0 release notes (#81631)

[via llvm-branch-commits]

Author: Maryam Moghadas
Date: 2024-02-15T22:01:26-08:00
New Revision: e3c6d5abb1a8a4bfb40fdccc5ceda8e5377167b6

URL: 
https://github.com/llvm/llvm-project/commit/e3c6d5abb1a8a4bfb40fdccc5ceda8e5377167b6
DIFF: 
https://github.com/llvm/llvm-project/commit/e3c6d5abb1a8a4bfb40fdccc5ceda8e5377167b6.diff

LOG: [PowerPC] Update V18.1.0 release notes (#81631)

Adding PowerPC updates for clang and llvm into the V18.1.0 release
notes.

-

Co-authored-by: Maryam Moghadas 

Added: 


Modified: 
clang/docs/ReleaseNotes.rst
llvm/docs/ReleaseNotes.rst

Removed: 




diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 95d44951ae7ee6..22eceea5d265ef 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -304,6 +304,10 @@ Non-comprehensive list of changes in this release
 
 * The version of Unicode used by Clang (primarily to parse identifiers) has 
been updated to 15.1.
 
+* Clang now defines macro ``__LLVM_INSTR_PROFILE_GENERATE`` when compiling with
+  PGO instrumentation profile generation, and ``__LLVM_INSTR_PROFILE_USE`` when
+  compiling with PGO profile use.
+
 New Compiler Flags
 --
 
@@ -344,6 +348,8 @@ New Compiler Flags
   attribute the replaceable global new and delete operators behave normally
   (like other functions) with respect to visibility attributes, pragmas and
   options (e.g ``--fvisibility=``).
+* Full register names can be used when printing assembly via ``-mregnames``.
+  This option now matches the one used by GCC.
 
 Deprecated Compiler Flags
 -
@@ -363,6 +369,7 @@ Modified Compiler Flags
 * ``-fvisibility-global-new-delete-hidden`` is now a deprecated spelling of
   ``-fvisibility-global-new-delete=force-hidden`` 
(``-fvisibility-global-new-delete=``
   is new in this release).
+* ``-fprofile-update`` is enabled for ``-fprofile-generate``.
 
 Removed Compiler Flags
 -
@@ -860,6 +867,9 @@ Bug Fixes in This Version
   Fixes (`#78290 `_)
 - Fixed assertion failure with deleted overloaded unary operators.
   Fixes (`#78314 `_)
+- The XCOFF object file format does not support aliases to symbols having 
common
+  linkage. Clang now diagnoses the use of an alias for a common symbol when
+  compiling for AIX.
 
 - Clang now doesn't produce false-positive warning `-Wconstant-logical-operand`
   for logical operators in C23.
@@ -1261,6 +1271,16 @@ CUDA Support
 - Clang now supports CUDA SDK up to 12.3
 - Added support for sm_90a
 
+PowerPC Support
+^^^
+
+- Added ``nmmintrin.h`` to intrinsics headers.
+- Added ``__builtin_ppc_fence`` as barrier of code motion, and
+  ``__builtin_ppc_mffsl`` for corresponding instruction.
+- Supported ``__attribute__((target("tune=cpu")))``.
+- Emit ``float-abi`` module flag on 64-bit ELFv2 PowerPC targets if
+  ``long double`` type is used in current module.
+
 AIX Support
 ^^^
 
@@ -1269,6 +1289,10 @@ AIX Support
   base is encoded as an immediate operand.
   This access sequence is not used for TLS variables larger than 32KB, and is
   currently only supported on 64-bit mode.
+- Inline assembler supports VSR register in pure digits.
+- Enabled ThinLTO support. Requires AIX 7.2 TL5 SP7 or newer, or AIX 7.3 TL2
+  or newer. Similar to the LTO support on AIX, ThinLTO is implemented with
+  the libLTO.so plugin.
 
 WebAssembly Support
 ^^^
@@ -1332,6 +1356,8 @@ libclang
 - Exposed arguments of ``clang::annotate``.
 - ``clang::getCursorKindForDecl`` now recognizes linkage specifications such as
   ``extern "C"`` and reports them as ``CXCursor_LinkageSpec``.
+- Changed the libclang library on AIX to export only the necessary symbols to
+  prevent issues of resolving to the wrong duplicate symbol.
 
 Static Analyzer
 ---

diff  --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 82f4a7a15c9c13..5b3210138f2f89 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -164,6 +164,30 @@ Changes to the MIPS Backend
 Changes to the PowerPC Backend
 --
 
+* LLJIT's JIT linker now defaults to JITLink on 64-bit ELFv2 targets.
+* Initial-exec TLS model is supported on AIX.
+* Implemented new resource based scheduling model of POWER7 and POWER8.
+* ``frexp`` libcall now references correct symbol name for ``fp128``.
+* Optimized materialization of 64-bit immediates, code generation of
+  ``vec_promote`` and atomics.
+* Global constant strings are pooled in the TOC under one entry to reduce the
+  number of entries in the TOC.
+* Added a number of missing Power10 extended mnemonics.
+* Added the SCV instruction.
+* Fixed register class for the paddi instruction.
+* Optimize VPERM and fix code order for swapping vector operands on LE.
+* Added various bug fixes 

[llvm-branch-commits] [clang] [llvm] release/18.x: [AArch64][SME] Implement inline-asm clobbers for za/zt0 (#79276) (PR #81593)

[Tom Stellard via llvm-branch-commits]

https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/81593
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[llvm-branch-commits] [llvm] 8b7b3fb - [AArch64][SME] Implement inline-asm clobbers for za/zt0 (#79276)

[Tom Stellard via llvm-branch-commits]

Author: Matthew Devereau
Date: 2024-02-15T21:58:29-08:00
New Revision: 8b7b3fbe29051f5456334a9c6990e053fd3e59dc

URL: 
https://github.com/llvm/llvm-project/commit/8b7b3fbe29051f5456334a9c6990e053fd3e59dc
DIFF: 
https://github.com/llvm/llvm-project/commit/8b7b3fbe29051f5456334a9c6990e053fd3e59dc.diff

LOG: [AArch64][SME] Implement inline-asm clobbers for za/zt0 (#79276)

This enables specifing "za" or "zt0" to the clobber list for inline asm.
This complies with the acle SME addition to the asm extension here:
https://github.com/ARM-software/acle/pull/276

(cherry picked from commit d9c20e437fe110fb79b5ca73a52762e5b930b361)

Added: 
llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll

Modified: 
clang/lib/Basic/Targets/AArch64.cpp
clang/test/CodeGen/aarch64-inline-asm.c
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

Removed: 




diff  --git a/clang/lib/Basic/Targets/AArch64.cpp 
b/clang/lib/Basic/Targets/AArch64.cpp
index 336b7a5e3d727d..3036f461c1ded1 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -1187,6 +1187,8 @@ TargetInfo::BuiltinVaListKind 
AArch64TargetInfo::getBuiltinVaListKind() const {
 }
 
 const char *const AArch64TargetInfo::GCCRegNames[] = {
+// clang-format off
+
 // 32-bit Integer registers
 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", "w11",
 "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 
"w22",
@@ -1223,7 +1225,12 @@ const char *const AArch64TargetInfo::GCCRegNames[] = {
 
 // SVE predicate-as-counter registers
 "pn0",  "pn1",  "pn2",  "pn3",  "pn4",  "pn5",  "pn6",  "pn7",  "pn8",
-"pn9",  "pn10", "pn11", "pn12", "pn13", "pn14", "pn15"
+"pn9",  "pn10", "pn11", "pn12", "pn13", "pn14", "pn15",
+
+// SME registers
+"za", "zt0",
+
+// clang-format on
 };
 
 ArrayRef AArch64TargetInfo::getGCCRegNames() const {

diff  --git a/clang/test/CodeGen/aarch64-inline-asm.c 
b/clang/test/CodeGen/aarch64-inline-asm.c
index 75e9a8c46b8769..8ddee560b11da4 100644
--- a/clang/test/CodeGen/aarch64-inline-asm.c
+++ b/clang/test/CodeGen/aarch64-inline-asm.c
@@ -95,3 +95,11 @@ void test_reduced_gpr_constraints(int var32, long var64) {
 // CHECK: [[ARG2:%.+]] = load i64, ptr
 // CHECK: call void asm sideeffect "add x0, x0, $0", "@3Ucj,~{x0}"(i64 
[[ARG2]])
 }
+
+void test_sme_constraints(){
+  asm("movt zt0[3, mul vl], z0" : : : "za");
+// CHECK: call void asm sideeffect "movt zt0[3, mul vl], z0", "~{za}"()
+
+  asm("movt zt0[3, mul vl], z0" : : : "zt0");
+// CHECK: call void asm sideeffect "movt zt0[3, mul vl], z0", "~{zt0}"()
+}
\ No newline at end of file

diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp 
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index e97f5e32201488..bfce5bc92a9ad1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -10718,6 +10718,14 @@ AArch64TargetLowering::getRegForInlineAsmConstraint(
   parseConstraintCode(Constraint) != AArch64CC::Invalid)
 return std::make_pair(unsigned(AArch64::NZCV), ::CCRRegClass);
 
+  if (Constraint == "{za}") {
+return std::make_pair(unsigned(AArch64::ZA), ::MPRRegClass);
+  }
+
+  if (Constraint == "{zt0}") {
+return std::make_pair(unsigned(AArch64::ZT0), ::ZTRRegClass);
+  }
+
   // Use the default implementation in TargetLowering to convert the register
   // constraint into a member of a register class.
   std::pair Res;

diff  --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp 
b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index f86e6947c9cdb0..48e1c1bc73022c 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -507,6 +507,10 @@ bool AArch64RegisterInfo::isAsmClobberable(const 
MachineFunction ,
 MCRegisterInfo::regsOverlap(PhysReg, AArch64::X16))
 return true;
 
+  // ZA/ZT0 registers are reserved but may be permitted in the clobber list.
+  if (PhysReg == AArch64::ZA || PhysReg == AArch64::ZT0)
+return true;
+
   return !isReservedReg(MF, PhysReg);
 }
 

diff  --git a/llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll 
b/llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll
new file mode 100644
index 00..a8cba7dc9a91e9
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-none-linux-gnu -stop-after=aarch64-isel < %s -o - 
| FileCheck %s
+
+define void @alpha( %x) local_unnamed_addr {
+entry:
+; CHECK: INLINEASM &"movt zt0[3, mul vl], z0", 1 /* sideeffect attdialect */, 
12 /* clobber */, implicit-def early-clobber $za
+  tail call void asm sideeffect "movt zt0[3, mul vl], z0", "~{za}"()
+  ret void
+}
+
+define void @beta( %x) 

[llvm-branch-commits] [clang] [llvm] release/18.x: [AArch64][SME] Implement inline-asm clobbers for za/zt0 (#79276) (PR #81593)

[via llvm-branch-commits]

https://github.com/llvmbot updated 
https://github.com/llvm/llvm-project/pull/81593

>From 8b7b3fbe29051f5456334a9c6990e053fd3e59dc Mon Sep 17 00:00:00 2001
From: Matthew Devereau 
Date: Fri, 2 Feb 2024 08:12:05 +
Subject: [PATCH] [AArch64][SME] Implement inline-asm clobbers for za/zt0
 (#79276)

This enables specifing "za" or "zt0" to the clobber list for inline asm.
This complies with the acle SME addition to the asm extension here:
https://github.com/ARM-software/acle/pull/276

(cherry picked from commit d9c20e437fe110fb79b5ca73a52762e5b930b361)
---
 clang/lib/Basic/Targets/AArch64.cpp |  9 -
 clang/test/CodeGen/aarch64-inline-asm.c |  8 
 llvm/lib/Target/AArch64/AArch64ISelLowering.cpp |  8 
 llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp |  4 
 llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll | 16 
 5 files changed, 44 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll

diff --git a/clang/lib/Basic/Targets/AArch64.cpp 
b/clang/lib/Basic/Targets/AArch64.cpp
index 336b7a5e3d727d..3036f461c1ded1 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -1187,6 +1187,8 @@ TargetInfo::BuiltinVaListKind 
AArch64TargetInfo::getBuiltinVaListKind() const {
 }
 
 const char *const AArch64TargetInfo::GCCRegNames[] = {
+// clang-format off
+
 // 32-bit Integer registers
 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", "w11",
 "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 
"w22",
@@ -1223,7 +1225,12 @@ const char *const AArch64TargetInfo::GCCRegNames[] = {
 
 // SVE predicate-as-counter registers
 "pn0",  "pn1",  "pn2",  "pn3",  "pn4",  "pn5",  "pn6",  "pn7",  "pn8",
-"pn9",  "pn10", "pn11", "pn12", "pn13", "pn14", "pn15"
+"pn9",  "pn10", "pn11", "pn12", "pn13", "pn14", "pn15",
+
+// SME registers
+"za", "zt0",
+
+// clang-format on
 };
 
 ArrayRef AArch64TargetInfo::getGCCRegNames() const {
diff --git a/clang/test/CodeGen/aarch64-inline-asm.c 
b/clang/test/CodeGen/aarch64-inline-asm.c
index 75e9a8c46b8769..8ddee560b11da4 100644
--- a/clang/test/CodeGen/aarch64-inline-asm.c
+++ b/clang/test/CodeGen/aarch64-inline-asm.c
@@ -95,3 +95,11 @@ void test_reduced_gpr_constraints(int var32, long var64) {
 // CHECK: [[ARG2:%.+]] = load i64, ptr
 // CHECK: call void asm sideeffect "add x0, x0, $0", "@3Ucj,~{x0}"(i64 
[[ARG2]])
 }
+
+void test_sme_constraints(){
+  asm("movt zt0[3, mul vl], z0" : : : "za");
+// CHECK: call void asm sideeffect "movt zt0[3, mul vl], z0", "~{za}"()
+
+  asm("movt zt0[3, mul vl], z0" : : : "zt0");
+// CHECK: call void asm sideeffect "movt zt0[3, mul vl], z0", "~{zt0}"()
+}
\ No newline at end of file
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp 
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index e97f5e32201488..bfce5bc92a9ad1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -10718,6 +10718,14 @@ AArch64TargetLowering::getRegForInlineAsmConstraint(
   parseConstraintCode(Constraint) != AArch64CC::Invalid)
 return std::make_pair(unsigned(AArch64::NZCV), ::CCRRegClass);
 
+  if (Constraint == "{za}") {
+return std::make_pair(unsigned(AArch64::ZA), ::MPRRegClass);
+  }
+
+  if (Constraint == "{zt0}") {
+return std::make_pair(unsigned(AArch64::ZT0), ::ZTRRegClass);
+  }
+
   // Use the default implementation in TargetLowering to convert the register
   // constraint into a member of a register class.
   std::pair Res;
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp 
b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index f86e6947c9cdb0..48e1c1bc73022c 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -507,6 +507,10 @@ bool AArch64RegisterInfo::isAsmClobberable(const 
MachineFunction ,
 MCRegisterInfo::regsOverlap(PhysReg, AArch64::X16))
 return true;
 
+  // ZA/ZT0 registers are reserved but may be permitted in the clobber list.
+  if (PhysReg == AArch64::ZA || PhysReg == AArch64::ZT0)
+return true;
+
   return !isReservedReg(MF, PhysReg);
 }
 
diff --git a/llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll 
b/llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll
new file mode 100644
index 00..a8cba7dc9a91e9
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-none-linux-gnu -stop-after=aarch64-isel < %s -o - 
| FileCheck %s
+
+define void @alpha( %x) local_unnamed_addr {
+entry:
+; CHECK: INLINEASM &"movt zt0[3, mul vl], z0", 1 /* sideeffect attdialect */, 
12 /* clobber */, implicit-def early-clobber $za
+  tail call void asm sideeffect "movt zt0[3, mul vl], z0", "~{za}"()
+  ret void
+}
+
+define void @beta( %x) 

[llvm-branch-commits] [llvm] 325d4a1 - Revert "[RISCV] Recurse on first operand of two operand shuffles (#79180)" (#80238)

[via llvm-branch-commits]

Author: Philip Reames
Date: 2024-02-15T21:56:56-08:00
New Revision: 325d4a1985d2fc2ea1851b0c27d56cc691445a0e

URL: 
https://github.com/llvm/llvm-project/commit/325d4a1985d2fc2ea1851b0c27d56cc691445a0e
DIFF: 
https://github.com/llvm/llvm-project/commit/325d4a1985d2fc2ea1851b0c27d56cc691445a0e.diff

LOG: Revert "[RISCV] Recurse on first operand of two operand shuffles (#79180)" 
(#80238)

This reverts commit bdc41106ee48dce59c500c9a3957af947f30c8c3 on the
release/18.x branch.  This change was the first in a mini-series
and while I'm not aware of any particular problem from having it on
it's own in the branch, it seems safer to ship with the previous
known good state.

Added: 


Modified: 
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll

Removed: 




diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp 
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7895d74f06d12a..dba4df77663b07 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -5033,60 +5033,56 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, 
SelectionDAG ,
   MVT IndexContainerVT =
   ContainerVT.changeVectorElementType(IndexVT.getScalarType());
 
-  // Base case for the recursion just below - handle the worst case
-  // single source permutation.  Note that all the splat variants
-  // are handled above.
-  if (V2.isUndef()) {
+  SDValue Gather;
+  // TODO: This doesn't trigger for i64 vectors on RV32, since there we
+  // encounter a bitcasted BUILD_VECTOR with low/high i32 values.
+  if (SDValue SplatValue = DAG.getSplatValue(V1, /*LegalTypes*/ true)) {
+Gather = lowerScalarSplat(SDValue(), SplatValue, VL, ContainerVT, DL, DAG,
+  Subtarget);
+  } else {
 V1 = convertToScalableVector(ContainerVT, V1, DAG, Subtarget);
-SDValue LHSIndices = DAG.getBuildVector(IndexVT, DL, GatherIndicesLHS);
-LHSIndices = convertToScalableVector(IndexContainerVT, LHSIndices, DAG,
- Subtarget);
-SDValue Gather = DAG.getNode(GatherVVOpc, DL, ContainerVT, V1, LHSIndices,
- DAG.getUNDEF(ContainerVT), TrueMask, VL);
-return convertFromScalableVector(VT, Gather, DAG, Subtarget);
-  }
-
-  // Translate the gather index we computed above (and possibly swapped)
-  // back to a shuffle mask.  This step should disappear once we complete
-  // the migration to recursive design.
-  SmallVector ShuffleMaskLHS;
-  ShuffleMaskLHS.reserve(GatherIndicesLHS.size());
-  for (SDValue GatherIndex : GatherIndicesLHS) {
-if (GatherIndex.isUndef()) {
-  ShuffleMaskLHS.push_back(-1);
-  continue;
+// If only one index is used, we can use a "splat" vrgather.
+// TODO: We can splat the most-common index and fix-up any stragglers, if
+// that's beneficial.
+if (LHSIndexCounts.size() == 1) {
+  int SplatIndex = LHSIndexCounts.begin()->getFirst();
+  Gather = DAG.getNode(GatherVXOpc, DL, ContainerVT, V1,
+   DAG.getConstant(SplatIndex, DL, XLenVT),
+   DAG.getUNDEF(ContainerVT), TrueMask, VL);
+} else {
+  SDValue LHSIndices = DAG.getBuildVector(IndexVT, DL, GatherIndicesLHS);
+  LHSIndices =
+  convertToScalableVector(IndexContainerVT, LHSIndices, DAG, 
Subtarget);
+
+  Gather = DAG.getNode(GatherVVOpc, DL, ContainerVT, V1, LHSIndices,
+   DAG.getUNDEF(ContainerVT), TrueMask, VL);
 }
-auto *IdxC = cast(GatherIndex);
-ShuffleMaskLHS.push_back(IdxC->getZExtValue());
   }
 
-  // Recursively invoke lowering for the LHS as if there were no RHS.
-  // This allows us to leverage all of our single source permute tricks.
-  SDValue Gather =
-DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), ShuffleMaskLHS);
-  Gather = convertToScalableVector(ContainerVT, Gather, DAG, Subtarget);
+  // If a second vector operand is used by this shuffle, blend it in with an
+  // additional vrgather.
+  if (!V2.isUndef()) {
+V2 = convertToScalableVector(ContainerVT, V2, DAG, Subtarget);
 
-  // Blend in second vector source with an additional vrgather.
-  V2 = convertToScalableVector(ContainerVT, V2, DAG, Subtarget);
+MVT MaskContainerVT = ContainerVT.changeVectorElementType(MVT::i1);
+SelectMask =
+convertToScalableVector(MaskContainerVT, SelectMask, DAG, Subtarget);
 
-  MVT MaskContainerVT = ContainerVT.changeVectorElementType(MVT::i1);
-  SelectMask =
-convertToScalableVector(MaskContainerVT, SelectMask, DAG, Subtarget);
-
-  // If only one index is 

[llvm-branch-commits] [llvm] Revert "[RISCV] Recurse on first operand of two operand shuffles (#79180)" (PR #80238)

[Tom Stellard via llvm-branch-commits]

https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/80238
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[llvm-branch-commits] [clang] release/18.x: [clang-format] Don't remove parentheses in macro definitions (#81444) (PR #81566)

[Tom Stellard via llvm-branch-commits]

https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/81566
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[llvm-branch-commits] [clang] ab57f6c - [clang-format] Don't remove parentheses in macro definitions (#81444)

[Tom Stellard via llvm-branch-commits]

Author: Owen Pan
Date: 2024-02-15T21:54:37-08:00
New Revision: ab57f6ced6909c202446b265a7acb2e945e4f52b

URL: 
https://github.com/llvm/llvm-project/commit/ab57f6ced6909c202446b265a7acb2e945e4f52b
DIFF: 
https://github.com/llvm/llvm-project/commit/ab57f6ced6909c202446b265a7acb2e945e4f52b.diff

LOG: [clang-format] Don't remove parentheses in macro definitions (#81444)

Closes #81399.

(cherry picked from commit 4af24d4ab76539706bfbceec4b3923426fb1b9e7)

Added: 


Modified: 
clang/lib/Format/UnwrappedLineParser.cpp
clang/unittests/Format/FormatTest.cpp

Removed: 




diff  --git a/clang/lib/Format/UnwrappedLineParser.cpp 
b/clang/lib/Format/UnwrappedLineParser.cpp
index b904e0e56d9eb3..57391979887078 100644
--- a/clang/lib/Format/UnwrappedLineParser.cpp
+++ b/clang/lib/Format/UnwrappedLineParser.cpp
@@ -2515,7 +2515,7 @@ bool UnwrappedLineParser::parseParens(TokenType 
AmpAmpTokenType) {
 parseChildBlock();
   break;
 case tok::r_paren:
-  if (!MightBeStmtExpr &&
+  if (!MightBeStmtExpr && !Line->InMacroBody &&
   Style.RemoveParentheses > FormatStyle::RPS_Leave) {
 const auto *Prev = LeftParen->Previous;
 const auto *Next = Tokens->peekNextToken();

diff  --git a/clang/unittests/Format/FormatTest.cpp 
b/clang/unittests/Format/FormatTest.cpp
index a471e36f8d6825..0beba12dda62ae 100644
--- a/clang/unittests/Format/FormatTest.cpp
+++ b/clang/unittests/Format/FormatTest.cpp
@@ -26856,6 +26856,7 @@ TEST_F(FormatTest, RemoveParentheses) {
   EXPECT_EQ(Style.RemoveParentheses, FormatStyle::RPS_Leave);
 
   Style.RemoveParentheses = FormatStyle::RPS_MultipleParentheses;
+  verifyFormat("#define Foo(...) foo((__VA_ARGS__))", Style);
   verifyFormat("int x __attribute__((aligned(16))) = 0;", Style);
   verifyFormat("decltype((foo->bar)) baz;", Style);
   verifyFormat("class __declspec(dllimport) X {};",
@@ -26890,6 +26891,7 @@ TEST_F(FormatTest, RemoveParentheses) {
   verifyFormat("return (({ 0; }));", "return ((({ 0; })));", Style);
 
   Style.RemoveParentheses = FormatStyle::RPS_ReturnStatement;
+  verifyFormat("#define Return0 return (0);", Style);
   verifyFormat("return 0;", "return (0);", Style);
   verifyFormat("co_return 0;", "co_return ((0));", Style);
   verifyFormat("return 0;", "return (((0)));", Style);



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[llvm-branch-commits] [clang] release/18.x: [clang-format] Don't remove parentheses in macro definitions (#81444) (PR #81566)

[via llvm-branch-commits]

https://github.com/llvmbot updated 
https://github.com/llvm/llvm-project/pull/81566

>From ab57f6ced6909c202446b265a7acb2e945e4f52b Mon Sep 17 00:00:00 2001
From: Owen Pan 
Date: Mon, 12 Feb 2024 19:20:26 -0800
Subject: [PATCH] [clang-format] Don't remove parentheses in macro definitions
 (#81444)

Closes #81399.

(cherry picked from commit 4af24d4ab76539706bfbceec4b3923426fb1b9e7)
---
 clang/lib/Format/UnwrappedLineParser.cpp | 2 +-
 clang/unittests/Format/FormatTest.cpp| 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/clang/lib/Format/UnwrappedLineParser.cpp 
b/clang/lib/Format/UnwrappedLineParser.cpp
index b904e0e56d9eb3..57391979887078 100644
--- a/clang/lib/Format/UnwrappedLineParser.cpp
+++ b/clang/lib/Format/UnwrappedLineParser.cpp
@@ -2515,7 +2515,7 @@ bool UnwrappedLineParser::parseParens(TokenType 
AmpAmpTokenType) {
 parseChildBlock();
   break;
 case tok::r_paren:
-  if (!MightBeStmtExpr &&
+  if (!MightBeStmtExpr && !Line->InMacroBody &&
   Style.RemoveParentheses > FormatStyle::RPS_Leave) {
 const auto *Prev = LeftParen->Previous;
 const auto *Next = Tokens->peekNextToken();
diff --git a/clang/unittests/Format/FormatTest.cpp 
b/clang/unittests/Format/FormatTest.cpp
index a471e36f8d6825..0beba12dda62ae 100644
--- a/clang/unittests/Format/FormatTest.cpp
+++ b/clang/unittests/Format/FormatTest.cpp
@@ -26856,6 +26856,7 @@ TEST_F(FormatTest, RemoveParentheses) {
   EXPECT_EQ(Style.RemoveParentheses, FormatStyle::RPS_Leave);
 
   Style.RemoveParentheses = FormatStyle::RPS_MultipleParentheses;
+  verifyFormat("#define Foo(...) foo((__VA_ARGS__))", Style);
   verifyFormat("int x __attribute__((aligned(16))) = 0;", Style);
   verifyFormat("decltype((foo->bar)) baz;", Style);
   verifyFormat("class __declspec(dllimport) X {};",
@@ -26890,6 +26891,7 @@ TEST_F(FormatTest, RemoveParentheses) {
   verifyFormat("return (({ 0; }));", "return ((({ 0; })));", Style);
 
   Style.RemoveParentheses = FormatStyle::RPS_ReturnStatement;
+  verifyFormat("#define Return0 return (0);", Style);
   verifyFormat("return 0;", "return (0);", Style);
   verifyFormat("co_return 0;", "co_return ((0));", Style);
   verifyFormat("return 0;", "return (((0)));", Style);

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[llvm-branch-commits] [libcxx] release/18.x: [libc++][print] Moves is_terminal to the dylib. (#80464) (PR #81410)

[Tom Stellard via llvm-branch-commits]

https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/81410
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[llvm-branch-commits] [libcxx] 872fe20 - [libc++][print] Moves is_terminal to the dylib. (#80464)

[Tom Stellard via llvm-branch-commits]

Author: Mark de Wever
Date: 2024-02-15T21:35:51-08:00
New Revision: 872fe20dddfaa6e41d92f90c3a1b716dc9e32107

URL: 
https://github.com/llvm/llvm-project/commit/872fe20dddfaa6e41d92f90c3a1b716dc9e32107
DIFF: 
https://github.com/llvm/llvm-project/commit/872fe20dddfaa6e41d92f90c3a1b716dc9e32107.diff

LOG: [libc++][print] Moves is_terminal to the dylib. (#80464)

Having the test in the header requires including unistd.h on POSIX
platforms. This header has other declarations which may conflict with
code that uses named declarations provided by this header. For example
code using "int pipe;" would conflict with the function pipe in this
header.

Moving the code to the dylib means std::print would not be available on
Apple backdeployment targets. On POSIX platforms there is no transcoding
required so a not Standard conforming implementation is still a useful
and the observable differences are minimal. This behaviour has been done
for print before https://github.com/llvm/llvm-project/pull/76293.

Note questions have been raised in LWG4044 "Confusing requirements for
std::print on POSIX platforms", whether or not the isatty check on POSIX
platforms is required. When this LWG issue is resolved the
backdeployment targets could become Standard compliant.

This patch is intended to be backported to the LLVM-18 branch.

Fixes: https://github.com/llvm/llvm-project/issues/79782
(cherry picked from commit 4fb7b3301bfbd439eb3d30d6a36c7cdb26941a0d)

Added: 


Modified: 
libcxx/include/print
libcxx/lib/abi/CHANGELOG.TXT

libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist

libcxx/lib/abi/i686-linux-android21.libcxxabi.v1.stable.exceptions.nonew.abilist
libcxx/lib/abi/powerpc-ibm-aix.libcxxabi.v1.stable.exceptions.nonew.abilist

libcxx/lib/abi/powerpc64-ibm-aix.libcxxabi.v1.stable.exceptions.nonew.abilist

libcxx/lib/abi/x86_64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist

libcxx/lib/abi/x86_64-linux-android21.libcxxabi.v1.stable.exceptions.nonew.abilist

libcxx/lib/abi/x86_64-unknown-freebsd.libcxxabi.v1.stable.exceptions.nonew.abilist

libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.nonew.abilist

libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.noexceptions.nonew.abilist
libcxx/src/print.cpp

Removed: 




diff  --git a/libcxx/include/print b/libcxx/include/print
index 7f2b5bac3dcf61..543a540ee4f27d 100644
--- a/libcxx/include/print
+++ b/libcxx/include/print
@@ -32,6 +32,7 @@ namespace std {
 */
 
 #include <__assert> // all public C++ headers provide the assertion handler
+#include <__availability>
 #include <__concepts/same_as.h>
 #include <__config>
 #include <__system_error/system_error.h>
@@ -43,10 +44,6 @@ namespace std {
 #include 
 #include 
 
-#if __has_include()
-#  include 
-#endif
-
 #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER)
 #  pragma GCC system_header
 #endif
@@ -68,7 +65,8 @@ _LIBCPP_EXPORTED_FROM_ABI bool __is_windows_terminal(FILE* 
__stream);
 // Note the function is only implemented on the Windows platform.
 _LIBCPP_EXPORTED_FROM_ABI void __write_to_windows_console(FILE* __stream, 
wstring_view __view);
 #  endif // _LIBCPP_HAS_NO_WIDE_CHARACTERS
-
+#elif __has_include()
+_LIBCPP_EXPORTED_FROM_ABI bool __is_posix_terminal(FILE* __stream);
 #endif // _LIBCPP_WIN32API
 
 #if _LIBCPP_STD_VER >= 23
@@ -195,15 +193,17 @@ inline constexpr bool __use_unicode_execution_charset = 
_MSVC_EXECUTION_CHARACTE
 inline constexpr bool __use_unicode_execution_charset = true;
 #  endif
 
-_LIBCPP_HIDE_FROM_ABI inline bool __is_terminal(FILE* __stream) {
+_LIBCPP_HIDE_FROM_ABI inline bool __is_terminal([[maybe_unused]] FILE* 
__stream) {
   // The macro _LIBCPP_TESTING_PRINT_IS_TERMINAL is used to change
   // the behavior in the test. This is not part of the public API.
 #  ifdef _LIBCPP_TESTING_PRINT_IS_TERMINAL
   return _LIBCPP_TESTING_PRINT_IS_TERMINAL(__stream);
+#  elif _LIBCPP_AVAILABILITY_HAS_PRINT == 0
+  return false;
 #  elif defined(_LIBCPP_WIN32API)
   return std::__is_windows_terminal(__stream);
 #  elif __has_include()
-  return isatty(fileno(__stream));
+  return std::__is_posix_terminal(__stream);
 #  else
 #error "Provide a way to determine whether a FILE* is a terminal"
 #  endif

diff  --git a/libcxx/lib/abi/CHANGELOG.TXT b/libcxx/lib/abi/CHANGELOG.TXT
index 1179c253f18c8f..7ff604959f4d5c 100644
--- a/libcxx/lib/abi/CHANGELOG.TXT
+++ b/libcxx/lib/abi/CHANGELOG.TXT
@@ -16,6 +16,14 @@ New entries should be added directly below the "Version" 
header.
 Version 18.0
 
 
+* [libc++] Moves is_terminal to the dylib
+
+  The patch moves the POSIX implementation of is_terminal to the dylib. This is
+  needed to avoid using  in public headers.
+
+  All platforms
+  Symbol added: _ZNSt6__ndk119__is_posix_terminalEP7__sFILE
+
 * [libc++abi] Implement __cxa_init_primary_exception and 

[llvm-branch-commits] [libcxx] release/18.x: [libc++][print] Moves is_terminal to the dylib. (#80464) (PR #81410)

[via llvm-branch-commits]

https://github.com/llvmbot updated 
https://github.com/llvm/llvm-project/pull/81410

>From 872fe20dddfaa6e41d92f90c3a1b716dc9e32107 Mon Sep 17 00:00:00 2001
From: Mark de Wever 
Date: Sat, 10 Feb 2024 17:09:53 +0100
Subject: [PATCH] [libc++][print] Moves is_terminal to the dylib. (#80464)

Having the test in the header requires including unistd.h on POSIX
platforms. This header has other declarations which may conflict with
code that uses named declarations provided by this header. For example
code using "int pipe;" would conflict with the function pipe in this
header.

Moving the code to the dylib means std::print would not be available on
Apple backdeployment targets. On POSIX platforms there is no transcoding
required so a not Standard conforming implementation is still a useful
and the observable differences are minimal. This behaviour has been done
for print before https://github.com/llvm/llvm-project/pull/76293.

Note questions have been raised in LWG4044 "Confusing requirements for
std::print on POSIX platforms", whether or not the isatty check on POSIX
platforms is required. When this LWG issue is resolved the
backdeployment targets could become Standard compliant.

This patch is intended to be backported to the LLVM-18 branch.

Fixes: https://github.com/llvm/llvm-project/issues/79782
(cherry picked from commit 4fb7b3301bfbd439eb3d30d6a36c7cdb26941a0d)
---
 libcxx/include/print  | 14 +--
 libcxx/lib/abi/CHANGELOG.TXT  |  8 ++
 ...bcxxabi.v1.stable.exceptions.nonew.abilist |  1 +
 ...bcxxabi.v1.stable.exceptions.nonew.abilist |  1 +
 ...bcxxabi.v1.stable.exceptions.nonew.abilist |  1 +
 ...bcxxabi.v1.stable.exceptions.nonew.abilist |  1 +
 ...bcxxabi.v1.stable.exceptions.nonew.abilist |  1 +
 ...bcxxabi.v1.stable.exceptions.nonew.abilist |  1 +
 ...bcxxabi.v1.stable.exceptions.nonew.abilist |  1 +
 ...bcxxabi.v1.stable.exceptions.nonew.abilist |  1 +
 ...xxabi.v1.stable.noexceptions.nonew.abilist |  1 +
 libcxx/src/print.cpp  | 25 ---
 12 files changed, 40 insertions(+), 16 deletions(-)

diff --git a/libcxx/include/print b/libcxx/include/print
index 7f2b5bac3dcf61..543a540ee4f27d 100644
--- a/libcxx/include/print
+++ b/libcxx/include/print
@@ -32,6 +32,7 @@ namespace std {
 */
 
 #include <__assert> // all public C++ headers provide the assertion handler
+#include <__availability>
 #include <__concepts/same_as.h>
 #include <__config>
 #include <__system_error/system_error.h>
@@ -43,10 +44,6 @@ namespace std {
 #include 
 #include 
 
-#if __has_include()
-#  include 
-#endif
-
 #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER)
 #  pragma GCC system_header
 #endif
@@ -68,7 +65,8 @@ _LIBCPP_EXPORTED_FROM_ABI bool __is_windows_terminal(FILE* 
__stream);
 // Note the function is only implemented on the Windows platform.
 _LIBCPP_EXPORTED_FROM_ABI void __write_to_windows_console(FILE* __stream, 
wstring_view __view);
 #  endif // _LIBCPP_HAS_NO_WIDE_CHARACTERS
-
+#elif __has_include()
+_LIBCPP_EXPORTED_FROM_ABI bool __is_posix_terminal(FILE* __stream);
 #endif // _LIBCPP_WIN32API
 
 #if _LIBCPP_STD_VER >= 23
@@ -195,15 +193,17 @@ inline constexpr bool __use_unicode_execution_charset = 
_MSVC_EXECUTION_CHARACTE
 inline constexpr bool __use_unicode_execution_charset = true;
 #  endif
 
-_LIBCPP_HIDE_FROM_ABI inline bool __is_terminal(FILE* __stream) {
+_LIBCPP_HIDE_FROM_ABI inline bool __is_terminal([[maybe_unused]] FILE* 
__stream) {
   // The macro _LIBCPP_TESTING_PRINT_IS_TERMINAL is used to change
   // the behavior in the test. This is not part of the public API.
 #  ifdef _LIBCPP_TESTING_PRINT_IS_TERMINAL
   return _LIBCPP_TESTING_PRINT_IS_TERMINAL(__stream);
+#  elif _LIBCPP_AVAILABILITY_HAS_PRINT == 0
+  return false;
 #  elif defined(_LIBCPP_WIN32API)
   return std::__is_windows_terminal(__stream);
 #  elif __has_include()
-  return isatty(fileno(__stream));
+  return std::__is_posix_terminal(__stream);
 #  else
 #error "Provide a way to determine whether a FILE* is a terminal"
 #  endif
diff --git a/libcxx/lib/abi/CHANGELOG.TXT b/libcxx/lib/abi/CHANGELOG.TXT
index 1179c253f18c8f..7ff604959f4d5c 100644
--- a/libcxx/lib/abi/CHANGELOG.TXT
+++ b/libcxx/lib/abi/CHANGELOG.TXT
@@ -16,6 +16,14 @@ New entries should be added directly below the "Version" 
header.
 Version 18.0
 
 
+* [libc++] Moves is_terminal to the dylib
+
+  The patch moves the POSIX implementation of is_terminal to the dylib. This is
+  needed to avoid using  in public headers.
+
+  All platforms
+  Symbol added: _ZNSt6__ndk119__is_posix_terminalEP7__sFILE
+
 * [libc++abi] Implement __cxa_init_primary_exception and use it to optimize 
std::make_exception_ptr (#65534)
 
   This patch implements __cxa_init_primary_exception, an extension to the 
Itanium C++ ABI.
diff --git 
a/libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
 

[llvm-branch-commits] [lld] [LLD] [docs] Add a release note for the SOURCE_DATE_EPOCH support (PR #81388)

[Tom Stellard via llvm-branch-commits]

https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/81388
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[llvm-branch-commits] [lld] 8391421 - [LLD] [docs] Add a release note for the SOURCE_DATE_EPOCH support (#81388)

[via llvm-branch-commits]

Author: Martin Storsjö
Date: 2024-02-15T21:35:12-08:00
New Revision: 83914215322e6db125ee5621d2fb18d97bab82c9

URL: 
https://github.com/llvm/llvm-project/commit/83914215322e6db125ee5621d2fb18d97bab82c9
DIFF: 
https://github.com/llvm/llvm-project/commit/83914215322e6db125ee5621d2fb18d97bab82c9.diff

LOG: [LLD] [docs] Add a release note for the SOURCE_DATE_EPOCH support (#81388)

Added: 


Modified: 
lld/docs/ReleaseNotes.rst

Removed: 




diff  --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst
index fa0e7f2bc0b3ea..82f9d93b8e86ab 100644
--- a/lld/docs/ReleaseNotes.rst
+++ b/lld/docs/ReleaseNotes.rst
@@ -86,6 +86,11 @@ COFF Improvements
 * LLD now prefers library paths specified with ``-libpath:`` over the 
implicitly
   detected toolchain paths.
 
+* Use the ``SOURCE_DATE_EPOCH`` environment variable for the PE header and
+  debug directory timestamps, if neither the ``/Brepro`` nor ``/timestamp:``
+  options have been specified. This makes the linker output reproducible by
+  setting this environment variable.
+
 MinGW Improvements
 --
 



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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Make sure ADDI replacement in optimizeCondBranch has a virtual reg destination. (#81938) (PR #81953)

[Min-Yih Hsu via llvm-branch-commits]

https://github.com/mshockwave approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/81953
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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Make sure ADDI replacement in optimizeCondBranch has a virtual reg destination. (#81938) (PR #81953)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-backend-risc-v

Author: None (llvmbot)


Changes

Backport feee627974df81e4cbf15537e4c4688aed66b12f

Requested by: @topperc

---
Full diff: https://github.com/llvm/llvm-project/pull/81953.diff


2 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+2-1) 
- (added) llvm/test/CodeGen/RISCV/branch-opt.mir (+68) 


``diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 592962cebe8973..d5b1ddfbeb3dc9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1229,7 +1229,8 @@ bool RISCVInstrInfo::optimizeCondBranch(MachineInstr ) 
const {
 MachineBasicBlock::reverse_iterator II(), E = MBB->rend();
 auto DefC1 = std::find_if(++II, E, [&](const MachineInstr ) -> bool {
   int64_t Imm;
-  return isLoadImm(, Imm) && Imm == C1;
+  return isLoadImm(, Imm) && Imm == C1 &&
+ I.getOperand(0).getReg().isVirtual();
 });
 if (DefC1 != E)
   return DefC1->getOperand(0).getReg();
diff --git a/llvm/test/CodeGen/RISCV/branch-opt.mir 
b/llvm/test/CodeGen/RISCV/branch-opt.mir
new file mode 100644
index 00..ba3a20f2fbfcd3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/branch-opt.mir
@@ -0,0 +1,68 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 
UTC_ARGS: --version 4
+# RUN: llc %s -mtriple=riscv64 -run-pass=peephole-opt -o - | FileCheck %s
+
+# Make sure we shouldn't replace the %2 ADDI with the $x10 ADDI since it has a
+# physical register destination.
+
+--- |
+  define void @foo(i32 signext %0) {
+tail call void @bar(i32 1)
+%2 = icmp ugt i32 %0, 1
+br i1 %2, label %3, label %4
+
+  3:; preds = %1
+tail call void @bar(i32 3)
+ret void
+
+  4:; preds = %1
+ret void
+  }
+
+  declare void @bar(...)
+
+...
+---
+name:foo
+tracksRegLiveness: true
+body: |
+  ; CHECK-LABEL: name: foo
+  ; CHECK: bb.0 (%ir-block.1):
+  ; CHECK-NEXT:   successors: %bb.1(0x4000), %bb.2(0x4000)
+  ; CHECK-NEXT:   liveins: $x10
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x10
+  ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
+  ; CHECK-NEXT:   $x10 = ADDI $x0, 1
+  ; CHECK-NEXT:   PseudoCALL target-flags(riscv-call) @bar, csr_ilp32_lp64, 
implicit-def dead $x1, implicit $x10, implicit-def $x2
+  ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
+  ; CHECK-NEXT:   [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 2
+  ; CHECK-NEXT:   BLTU [[COPY]], killed [[ADDI]], %bb.2
+  ; CHECK-NEXT:   PseudoBR %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1 (%ir-block.3):
+  ; CHECK-NEXT:   $x10 = ADDI $x0, 3
+  ; CHECK-NEXT:   PseudoTAIL target-flags(riscv-call) @bar, implicit $x2, 
implicit $x10
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2 (%ir-block.4):
+  ; CHECK-NEXT:   PseudoRET
+  bb.0 (%ir-block.1):
+successors: %bb.1, %bb.2
+liveins: $x10
+
+%0:gpr = COPY $x10
+ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
+$x10 = ADDI $x0, 1
+PseudoCALL target-flags(riscv-call) @bar, csr_ilp32_lp64, implicit-def 
dead $x1, implicit $x10, implicit-def $x2
+ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
+%2:gpr = ADDI $x0, 2
+BLTU %0, killed %2, %bb.2
+PseudoBR %bb.1
+
+  bb.1 (%ir-block.3):
+$x10 = ADDI $x0, 3
+PseudoTAIL target-flags(riscv-call) @bar, implicit $x2, implicit $x10
+
+  bb.2 (%ir-block.4):
+PseudoRET
+
+...

``




https://github.com/llvm/llvm-project/pull/81953
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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Make sure ADDI replacement in optimizeCondBranch has a virtual reg destination. (#81938) (PR #81953)

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llvmbot wrote:

@mshockwave What do you think about merging this PR to the release branch?

https://github.com/llvm/llvm-project/pull/81953
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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Make sure ADDI replacement in optimizeCondBranch has a virtual reg destination. (#81938) (PR #81953)

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https://github.com/llvmbot milestoned 
https://github.com/llvm/llvm-project/pull/81953
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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Make sure ADDI replacement in optimizeCondBranch has a virtual reg destination. (#81938) (PR #81953)

[via llvm-branch-commits]

https://github.com/llvmbot created 
https://github.com/llvm/llvm-project/pull/81953

Backport feee627974df81e4cbf15537e4c4688aed66b12f

Requested by: @topperc

>From 3dcdbaf5321406f5438388041ec95014ae88814c Mon Sep 17 00:00:00 2001
From: Craig Topper 
Date: Thu, 15 Feb 2024 16:34:40 -0800
Subject: [PATCH] [RISCV] Make sure ADDI replacement in optimizeCondBranch has
 a virtual reg destination. (#81938)

If it isn't virtual, we may extend the live range of the physical
register past were it is valid. For example, across a call.

Found while trying to enable -riscv-enable-sink-fold which enables some
copy propagation in machine sink that led to ADDIs with physical
register destinations.

(cherry picked from commit feee627974df81e4cbf15537e4c4688aed66b12f)
---
 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp |  3 +-
 llvm/test/CodeGen/RISCV/branch-opt.mir   | 68 
 2 files changed, 70 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/RISCV/branch-opt.mir

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 592962cebe8973..d5b1ddfbeb3dc9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1229,7 +1229,8 @@ bool RISCVInstrInfo::optimizeCondBranch(MachineInstr ) 
const {
 MachineBasicBlock::reverse_iterator II(), E = MBB->rend();
 auto DefC1 = std::find_if(++II, E, [&](const MachineInstr ) -> bool {
   int64_t Imm;
-  return isLoadImm(, Imm) && Imm == C1;
+  return isLoadImm(, Imm) && Imm == C1 &&
+ I.getOperand(0).getReg().isVirtual();
 });
 if (DefC1 != E)
   return DefC1->getOperand(0).getReg();
diff --git a/llvm/test/CodeGen/RISCV/branch-opt.mir 
b/llvm/test/CodeGen/RISCV/branch-opt.mir
new file mode 100644
index 00..ba3a20f2fbfcd3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/branch-opt.mir
@@ -0,0 +1,68 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 
UTC_ARGS: --version 4
+# RUN: llc %s -mtriple=riscv64 -run-pass=peephole-opt -o - | FileCheck %s
+
+# Make sure we shouldn't replace the %2 ADDI with the $x10 ADDI since it has a
+# physical register destination.
+
+--- |
+  define void @foo(i32 signext %0) {
+tail call void @bar(i32 1)
+%2 = icmp ugt i32 %0, 1
+br i1 %2, label %3, label %4
+
+  3:; preds = %1
+tail call void @bar(i32 3)
+ret void
+
+  4:; preds = %1
+ret void
+  }
+
+  declare void @bar(...)
+
+...
+---
+name:foo
+tracksRegLiveness: true
+body: |
+  ; CHECK-LABEL: name: foo
+  ; CHECK: bb.0 (%ir-block.1):
+  ; CHECK-NEXT:   successors: %bb.1(0x4000), %bb.2(0x4000)
+  ; CHECK-NEXT:   liveins: $x10
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x10
+  ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
+  ; CHECK-NEXT:   $x10 = ADDI $x0, 1
+  ; CHECK-NEXT:   PseudoCALL target-flags(riscv-call) @bar, csr_ilp32_lp64, 
implicit-def dead $x1, implicit $x10, implicit-def $x2
+  ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
+  ; CHECK-NEXT:   [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 2
+  ; CHECK-NEXT:   BLTU [[COPY]], killed [[ADDI]], %bb.2
+  ; CHECK-NEXT:   PseudoBR %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1 (%ir-block.3):
+  ; CHECK-NEXT:   $x10 = ADDI $x0, 3
+  ; CHECK-NEXT:   PseudoTAIL target-flags(riscv-call) @bar, implicit $x2, 
implicit $x10
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2 (%ir-block.4):
+  ; CHECK-NEXT:   PseudoRET
+  bb.0 (%ir-block.1):
+successors: %bb.1, %bb.2
+liveins: $x10
+
+%0:gpr = COPY $x10
+ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
+$x10 = ADDI $x0, 1
+PseudoCALL target-flags(riscv-call) @bar, csr_ilp32_lp64, implicit-def 
dead $x1, implicit $x10, implicit-def $x2
+ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
+%2:gpr = ADDI $x0, 2
+BLTU %0, killed %2, %bb.2
+PseudoBR %bb.1
+
+  bb.1 (%ir-block.3):
+$x10 = ADDI $x0, 3
+PseudoTAIL target-flags(riscv-call) @bar, implicit $x2, implicit $x10
+
+  bb.2 (%ir-block.4):
+PseudoRET
+
+...

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[llvm-branch-commits] [Flang][OpenMP][MLIR] Extend derived (record) type map support in Flang OpenMP by adding some initial support for explicit member mapping (PR #81511)

[via llvm-branch-commits]

agozillon wrote:


Most recent updates were a rebase for the entire stack and an update of this 
current PR (Fortran level changes) to try and address the very good feedback. 
However, first time doing this using SPR, so if anyone notices any weirdness 
please don't hesitate to point it out!

The main changes from the update are:

* Attempting to remove the few cases of hard-coded SSA values from tests
* Early exitting where suggested and where possible
* Emission of assert when certain expected conditions are not met
* Movement of mapSymbols to a required argument for processMap, as we always 
end up generating the list in any case now as with the current implementation 
for finding prior mapped parents we need to keep track of the symbol list 
* Removal of seperate getOmpObj... function for parent, I've opted to just use 
getFirstName for this PR, I think it may need something a little more robust 
for nested derived types (I made an attempt at making something that'd retrieve 
the parent one up from the current element, but it's not required for this PR 
and I'd like to test it a bit more first), but no sense getting ahead of myself 
if I can keep it simple for now
* Better/clearer method of getting the derived type definition symbol that we 
utilise to access the member symbols for calculating the member indices 

https://github.com/llvm/llvm-project/pull/81511
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[llvm-branch-commits] [Flang][OpenMP][MLIR] Extend derived (record) type map support in Flang OpenMP by adding some initial support for explicit member mapping (PR #81511)

[via llvm-branch-commits]

https://github.com/agozillon updated 
https://github.com/llvm/llvm-project/pull/81511


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[llvm-branch-commits] [Flang][OpenMP][MLIR] Extend derived (record) type map support in Flang OpenMP by adding some initial support for explicit member mapping (PR #81511)

[via llvm-branch-commits]

https://github.com/agozillon updated 
https://github.com/llvm/llvm-project/pull/81511


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[llvm-branch-commits] [Flang][OpenMP][MLIR] Extend derived (record) type map support in Flang OpenMP by adding some initial support for explicit member mapping (PR #81511)

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https://github.com/agozillon updated 
https://github.com/llvm/llvm-project/pull/81511


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[llvm-branch-commits] [Flang][OpenMP][MLIR] Extend derived (record) type map support in Flang OpenMP by adding some initial support for explicit member mapping (PR #81511)

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https://github.com/agozillon updated 
https://github.com/llvm/llvm-project/pull/81511


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[llvm-branch-commits] [OpenMP][MLIR] Extend explicit derived type member mapping support for OpenMP dialects lowering to LLVM-IR (PR #81510)

[via llvm-branch-commits]

https://github.com/agozillon updated 
https://github.com/llvm/llvm-project/pull/81510


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[llvm-branch-commits] [OpenMP][MLIR] Extend explicit derived type member mapping support for OpenMP dialects lowering to LLVM-IR (PR #81510)

[via llvm-branch-commits]

https://github.com/agozillon updated 
https://github.com/llvm/llvm-project/pull/81510


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[llvm-branch-commits] [OpenMP][MLIR] Add new partial_map and members_index arguments to omp.map_info operations to help support record type mapping (PR #81509)

[via llvm-branch-commits]

https://github.com/agozillon updated 
https://github.com/llvm/llvm-project/pull/81509


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[llvm-branch-commits] [OpenMP][MLIR] Add new partial_map and members_index arguments to omp.map_info operations to help support record type mapping (PR #81509)

[via llvm-branch-commits]

https://github.com/agozillon updated 
https://github.com/llvm/llvm-project/pull/81509


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[llvm-branch-commits] [ELF] Support placing .lbss/.lrodata/.ldata after .bss (PR #81224)

[Arthur Eubanks via llvm-branch-commits]

@@ -1436,6 +1436,8 @@ static void readConfigs(opt::InputArgList ) {
   config->zInterpose = hasZOption(args, "interpose");
   config->zKeepTextSectionPrefix = getZFlag(
   args, "keep-text-section-prefix", "nokeep-text-section-prefix", false);
+  config->zLrodataAfterBss =
+  getZFlag(args, "lrodata-after-bss", "nolrodata-after-bss", false);

aeubanks wrote:

> With -z separate-code and a large max-page-size, one extra PT_LOAD can have a 
> significant waste.

This makes sense for the more common `-pie` case.

But *everybody* who's linking with `-no-pie` on x86-64 and has large sections 
is going to need `.lrodata` at the end of the binary so it doesn't affect small 
data relocations. This basically forces the user to pass `-z lrodata-after-bss` 
if they're passing `-no-pie`, which seems like a pointless burden on the user. 
I don't think people are generally concerned about exactly where `.lrodata` is 
in the binary, the whole point is that it's *somewhere* far away, doesn't 
really matter where.

https://github.com/llvm/llvm-project/pull/81224
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[llvm-branch-commits] [ELF] Support placing .lbss/.lrodata/.ldata after .bss (PR #81224)

[Fangrui Song via llvm-branch-commits]

@@ -1436,6 +1436,8 @@ static void readConfigs(opt::InputArgList ) {
   config->zInterpose = hasZOption(args, "interpose");
   config->zKeepTextSectionPrefix = getZFlag(
   args, "keep-text-section-prefix", "nokeep-text-section-prefix", false);
+  config->zLrodataAfterBss =
+  getZFlag(args, "lrodata-after-bss", "nolrodata-after-bss", false);

MaskRay wrote:

I have explained. The layout should not magically change if the user switches 
between -no-pie and -pie/-shared. There are a few options to change the layout 
(-z keep-text-section-prefix, -z separate-code, --no-rosegment, etc), but none 
does a "smart" choice. 

With -z separate-code and a large max-page-size, one extra PT_LOAD can have a 
significant waste. I was actually struggling with the default but now I feel 
that the current layout makes more sense as the default.

https://github.com/llvm/llvm-project/pull/81224
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[llvm-branch-commits] [llvm] [SROA] Use !tbaa instead of !tbaa.struct if op matches field. (PR #81289)

[Florian Hahn via llvm-branch-commits]

https://github.com/fhahn commented:

@dobbelaj-snps Added a substantial number of tests that should cover all cases 
now in 2a9b86cc10c3883cca51a5166aad6e2b755fa958

https://github.com/llvm/llvm-project/pull/81289
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[llvm-branch-commits] [llvm] [SROA] Use !tbaa instead of !tbaa.struct if op matches field. (PR #81289)

[Florian Hahn via llvm-branch-commits]

@@ -4561,6 +4577,10 @@ bool SROA::presplitLoadsAndStores(AllocaInst , 
AllocaSlices ) {
 PStore->copyMetadata(*SI, {LLVMContext::MD_mem_parallel_loop_access,
LLVMContext::MD_access_group,
LLVMContext::MD_DIAssignID});
+
+if (AATags)
+  PStore->setAAMetadata(

fhahn wrote:

Should be now, I added a number of additional tests that should cover all cases 
here

https://github.com/llvm/llvm-project/pull/81289
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[llvm-branch-commits] [llvm] [SROA] Use !tbaa instead of !tbaa.struct if op matches field. (PR #81289)

[Florian Hahn via llvm-branch-commits]

https://github.com/fhahn edited https://github.com/llvm/llvm-project/pull/81289
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[llvm-branch-commits] [llvm] [SROA] Use !tbaa instead of !tbaa.struct if op matches field. (PR #81289)

[Florian Hahn via llvm-branch-commits]

https://github.com/fhahn updated https://github.com/llvm/llvm-project/pull/81289

>From 90639e9131670863ebb4c199a9861b2b0094d601 Mon Sep 17 00:00:00 2001
From: Florian Hahn 
Date: Fri, 9 Feb 2024 15:17:09 +
Subject: [PATCH 1/2] [SROA] Use !tbaa instead of !tbaa.struct if op matches
 field.

If a split memory access introduced by SROA accesses precisely a single
field of the original operation's !tbaa.struct, use the !tbaa tag for
the accessed field directly instead of the full !tbaa.struct.

InstCombine already had a similar logic.

Motivation for this and follow-on patches is to improve codegen for
libc++, where using memcpy limits optimizations, like vectorization for
code iteration over std::vector>:
https://godbolt.org/z/f3vqYos3c

Depends on https://github.com/llvm/llvm-project/pull/81285.
---
 llvm/include/llvm/IR/Metadata.h  |  2 +
 llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp | 13 ++
 llvm/lib/Transforms/Scalar/SROA.cpp  | 48 ++--
 llvm/test/Transforms/SROA/tbaa-struct2.ll| 21 -
 llvm/test/Transforms/SROA/tbaa-struct3.ll| 16 +++
 5 files changed, 67 insertions(+), 33 deletions(-)

diff --git a/llvm/include/llvm/IR/Metadata.h b/llvm/include/llvm/IR/Metadata.h
index 6f23ac44dee968..33363a271d4823 100644
--- a/llvm/include/llvm/IR/Metadata.h
+++ b/llvm/include/llvm/IR/Metadata.h
@@ -849,6 +849,8 @@ struct AAMDNodes {
   /// If his AAMDNode has !tbaa.struct and \p AccessSize matches the size of 
the
   /// field at offset 0, get the TBAA tag describing the accessed field.
   AAMDNodes adjustForAccess(unsigned AccessSize);
+  AAMDNodes adjustForAccess(size_t Offset, Type *AccessTy,
+const DataLayout );
 };
 
 // Specialize DenseMapInfo for AAMDNodes.
diff --git a/llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp 
b/llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
index bfd70414c0340c..b2dc451d581939 100644
--- a/llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
+++ b/llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
@@ -833,3 +833,16 @@ AAMDNodes AAMDNodes::adjustForAccess(unsigned AccessSize) {
   }
   return New;
 }
+
+AAMDNodes AAMDNodes::adjustForAccess(size_t Offset, Type *AccessTy,
+ const DataLayout ) {
+
+  AAMDNodes New = shift(Offset);
+  if (!DL.typeSizeEqualsStoreSize(AccessTy))
+return New;
+  TypeSize Size = DL.getTypeStoreSize(AccessTy);
+  if (Size.isScalable())
+return New;
+
+  return New.adjustForAccess(Size.getKnownMinValue());
+}
diff --git a/llvm/lib/Transforms/Scalar/SROA.cpp 
b/llvm/lib/Transforms/Scalar/SROA.cpp
index 138dc38b5c14ce..f24cbbc1fe0591 100644
--- a/llvm/lib/Transforms/Scalar/SROA.cpp
+++ b/llvm/lib/Transforms/Scalar/SROA.cpp
@@ -2914,7 +2914,8 @@ class AllocaSliceRewriter : public 
InstVisitor {
 
   // Do this after copyMetadataForLoad() to preserve the TBAA shift.
   if (AATags)
-NewLI->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
+NewLI->setAAMetadata(AATags.adjustForAccess(
+NewBeginOffset - BeginOffset, NewLI->getType(), DL));
 
   // Try to preserve nonnull metadata
   V = NewLI;
@@ -2936,7 +2937,9 @@ class AllocaSliceRewriter : public 
InstVisitor {
   IRB.CreateAlignedLoad(TargetTy, getNewAllocaSlicePtr(IRB, LTy),
 getSliceAlign(), LI.isVolatile(), 
LI.getName());
   if (AATags)
-NewLI->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
+NewLI->setAAMetadata(AATags.adjustForAccess(
+NewBeginOffset - BeginOffset, NewLI->getType(), DL));
+
   if (LI.isVolatile())
 NewLI->setAtomic(LI.getOrdering(), LI.getSyncScopeID());
   NewLI->copyMetadata(LI, {LLVMContext::MD_mem_parallel_loop_access,
@@ -3011,7 +3014,8 @@ class AllocaSliceRewriter : public 
InstVisitor {
 Store->copyMetadata(SI, {LLVMContext::MD_mem_parallel_loop_access,
  LLVMContext::MD_access_group});
 if (AATags)
-  Store->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
+  Store->setAAMetadata(AATags.adjustForAccess(NewBeginOffset - BeginOffset,
+  V->getType(), DL));
 Pass.DeadInsts.push_back();
 
 // NOTE: Careful to use OrigV rather than V.
@@ -3038,7 +3042,8 @@ class AllocaSliceRewriter : public 
InstVisitor {
 Store->copyMetadata(SI, {LLVMContext::MD_mem_parallel_loop_access,
  LLVMContext::MD_access_group});
 if (AATags)
-  Store->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
+  Store->setAAMetadata(AATags.adjustForAccess(NewBeginOffset - BeginOffset,
+  V->getType(), DL));
 
 migrateDebugInfo(, IsSplit, NewBeginOffset * 8, SliceSize * 8, ,
  Store, Store->getPointerOperand(),
@@ -3097,8 +3102,10 @@ class AllocaSliceRewriter : public 
InstVisitor {
 }
 NewSI->copyMetadata(SI, 

[llvm-branch-commits] [mlir] c11e879 - Revert "[mlir][sparse] remove LevelType enum, construct LevelType from LevelF…"

[via llvm-branch-commits]

Author: Mehdi Amini
Date: 2024-02-15T13:26:07-08:00
New Revision: c11e879dec122a027ca9ab897fa9c6517cc3f33d

URL: 
https://github.com/llvm/llvm-project/commit/c11e879dec122a027ca9ab897fa9c6517cc3f33d
DIFF: 
https://github.com/llvm/llvm-project/commit/c11e879dec122a027ca9ab897fa9c6517cc3f33d.diff

LOG: Revert "[mlir][sparse] remove LevelType enum, construct LevelType from 
LevelF…"

This reverts commit 235ec0f791749d94ac1ca1441b8b06d4ba09792c.

Added: 


Modified: 
mlir/include/mlir/Dialect/SparseTensor/IR/Enums.h
mlir/lib/CAPI/Dialect/SparseTensor.cpp
mlir/lib/Dialect/SparseTensor/IR/Detail/LvlTypeParser.cpp
mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp
mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.cpp
mlir/lib/Dialect/SparseTensor/Utils/Merger.cpp
mlir/unittests/Dialect/SparseTensor/MergerTest.cpp

Removed: 




diff  --git a/mlir/include/mlir/Dialect/SparseTensor/IR/Enums.h 
b/mlir/include/mlir/Dialect/SparseTensor/IR/Enums.h
index a20a7906189d01..74cc0dee554a17 100644
--- a/mlir/include/mlir/Dialect/SparseTensor/IR/Enums.h
+++ b/mlir/include/mlir/Dialect/SparseTensor/IR/Enums.h
@@ -153,9 +153,45 @@ enum class Action : uint32_t {
   kSortCOOInPlace = 8,
 };
 
+/// This enum defines all the sparse representations supportable by
+/// the SparseTensor dialect. We use a lightweight encoding to encode
+/// the "format" per se (dense, compressed, singleton, loose_compressed,
+/// n-out-of-m), the "properties" (ordered, unique) as well as n and m when
+/// the format is NOutOfM.
+/// The encoding is chosen for performance of the runtime library, and thus may
+/// change in future versions; consequently, client code should use the
+/// predicate functions defined below, rather than relying on knowledge
+/// about the particular binary encoding.
+///
+/// The `Undef` "format" is a special value used internally for cases
+/// where we need to store an undefined or indeterminate `LevelType`.
+/// It should not be used externally, since it does not indicate an
+/// actual/representable format.
+///
+/// Bit manipulations for LevelType:
+///
+/// | 8-bit n | 8-bit m | 16-bit LevelFormat | 16-bit LevelProperty |
+///
+enum class LevelType : uint64_t {
+  Undef = 0x,
+  Dense = 0x0001,
+  Compressed = 0x0002,
+  CompressedNu = 0x00020001,
+  CompressedNo = 0x00020002,
+  CompressedNuNo = 0x00020003,
+  Singleton = 0x0004,
+  SingletonNu = 0x00040001,
+  SingletonNo = 0x00040002,
+  SingletonNuNo = 0x00040003,
+  LooseCompressed = 0x0008,
+  LooseCompressedNu = 0x00080001,
+  LooseCompressedNo = 0x00080002,
+  LooseCompressedNuNo = 0x00080003,
+  NOutOfM = 0x0010,
+};
+
 /// This enum defines all supported storage format without the level 
properties.
 enum class LevelFormat : uint64_t {
-  Undef = 0x,
   Dense = 0x0001,
   Compressed = 0x0002,
   Singleton = 0x0004,
@@ -163,240 +199,327 @@ enum class LevelFormat : uint64_t {
   NOutOfM = 0x0010,
 };
 
-template 
-constexpr bool isAnyOfFmt(LevelFormat fmt) {
-  return (... || (targets == fmt));
-}
-
-/// Returns string representation of the given level format.
-constexpr const char *toFormatString(LevelFormat lvlFmt) {
-  switch (lvlFmt) {
-  case LevelFormat::Undef:
-return "undef";
-  case LevelFormat::Dense:
-return "dense";
-  case LevelFormat::Compressed:
-return "compressed";
-  case LevelFormat::Singleton:
-return "singleton";
-  case LevelFormat::LooseCompressed:
-return "loose_compressed";
-  case LevelFormat::NOutOfM:
-return "structured";
-  }
-  return "";
-}
-
 /// This enum defines all the nondefault properties for storage formats.
-enum class LevelPropNonDefault : uint64_t {
+enum class LevelPropertyNondefault : uint64_t {
   Nonunique = 0x0001,
   Nonordered = 0x0002,
 };
 
-/// Returns string representation of the given level properties.
-constexpr const char *toPropString(LevelPropNonDefault lvlProp) {
-  switch (lvlProp) {
-  case LevelPropNonDefault::Nonunique:
-return "nonunique";
-  case LevelPropNonDefault::Nonordered:
-return "nonordered";
-  }
-  return "";
+/// Get N of NOutOfM level type.
+constexpr uint64_t getN(LevelType lt) {
+  return (static_cast(lt) >> 32) & 0xff;
 }
 
-/// This enum defines all the sparse representations supportable by
-/// the SparseTensor dialect. We use a lightweight encoding to encode
-/// the "format" per se (dense, compressed, singleton, loose_compressed,
-/// n-out-of-m), the "properties" (ordered, unique) as well as n and m when
-/// the format is NOutOfM.
-/// The encoding is chosen for performance of the runtime library, and thus may
-/// change in future versions; consequently, client code should use the
-/// predicate functions defined below, rather 

[llvm-branch-commits] [ELF] Support placing .lbss/.lrodata/.ldata after .bss (PR #81224)

[Arthur Eubanks via llvm-branch-commits]

@@ -1436,6 +1436,8 @@ static void readConfigs(opt::InputArgList ) {
   config->zInterpose = hasZOption(args, "interpose");
   config->zKeepTextSectionPrefix = getZFlag(
   args, "keep-text-section-prefix", "nokeep-text-section-prefix", false);
+  config->zLrodataAfterBss =
+  getZFlag(args, "lrodata-after-bss", "nolrodata-after-bss", false);

aeubanks wrote:

default to true makes sense, it works for more cases

https://github.com/llvm/llvm-project/pull/81224
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[llvm-branch-commits] [ELF] Support placing .lbss/.lrodata/.ldata after .bss (PR #81224)

[James Y Knight via llvm-branch-commits]

@@ -1436,6 +1436,8 @@ static void readConfigs(opt::InputArgList ) {
   config->zInterpose = hasZOption(args, "interpose");
   config->zKeepTextSectionPrefix = getZFlag(
   args, "keep-text-section-prefix", "nokeep-text-section-prefix", false);
+  config->zLrodataAfterBss =
+  getZFlag(args, "lrodata-after-bss", "nolrodata-after-bss", false);

jyknight wrote:

OK...then it ought to default to true, instead of false.

(And I do also wish you would explain better why you feel so strongly about not 
changing behavior based on pic vs not.)

https://github.com/llvm/llvm-project/pull/81224
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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Use APInt in useInversedSetcc to prevent crashes when mask is larger than UINT64_MAX. (#81888) (PR #81905)

[Alex Bradbury via llvm-branch-commits]

https://github.com/asb approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/81905
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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Use APInt in useInversedSetcc to prevent crashes when mask is larger than UINT64_MAX. (#81888) (PR #81905)

[via llvm-branch-commits]

https://github.com/llvmbot updated 
https://github.com/llvm/llvm-project/pull/81905

>From bdf12ae33343b8ac5561921071c27d9dd4a2182e Mon Sep 17 00:00:00 2001
From: Craig Topper 
Date: Thu, 15 Feb 2024 10:48:52 -0800
Subject: [PATCH] [RISCV] Use APInt in useInversedSetcc to prevent crashes when
 mask is larger than UINT64_MAX. (#81888)

There are no checks that the type is legal so we need to handle any
type.

(cherry picked from commit b57ba8ec514190b38eced26d541e8e25af66c485)
---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp |  4 +-
 llvm/test/CodeGen/RISCV/condops.ll  | 51 +
 2 files changed, 53 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp 
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7895d74f06d12a..6ce7215e03ff49 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -14658,8 +14658,8 @@ static SDValue useInversedSetcc(SDNode *N, SelectionDAG 
,
 ISD::CondCode CC = cast(Cond.getOperand(2))->get();
 if (CC == ISD::SETEQ && LHS.getOpcode() == ISD::AND &&
 isa(LHS.getOperand(1)) && isNullConstant(RHS)) {
-  uint64_t MaskVal = LHS.getConstantOperandVal(1);
-  if (isPowerOf2_64(MaskVal) && !isInt<12>(MaskVal))
+  const APInt  = LHS.getConstantOperandAPInt(1);
+  if (MaskVal.isPowerOf2() && !MaskVal.isSignedIntN(12))
 return DAG.getSelect(DL, VT,
  DAG.getSetCC(DL, CondVT, LHS, RHS, ISD::SETNE),
  False, True);
diff --git a/llvm/test/CodeGen/RISCV/condops.ll 
b/llvm/test/CodeGen/RISCV/condops.ll
index 8e53782b5dcd78..101cb5aeeb0940 100644
--- a/llvm/test/CodeGen/RISCV/condops.ll
+++ b/llvm/test/CodeGen/RISCV/condops.ll
@@ -3719,3 +3719,54 @@ entry:
   %cond = select i1 %tobool.not, i64 0, i64 %x
   ret i64 %cond
 }
+
+; Test that we don't crash on types larger than 64 bits.
+define i64 @single_bit3(i80 %x, i64 %y) {
+; RV32I-LABEL: single_bit3:
+; RV32I:   # %bb.0: # %entry
+; RV32I-NEXT:lw a0, 8(a0)
+; RV32I-NEXT:slli a0, a0, 31
+; RV32I-NEXT:srai a3, a0, 31
+; RV32I-NEXT:and a0, a3, a1
+; RV32I-NEXT:and a1, a3, a2
+; RV32I-NEXT:ret
+;
+; RV64I-LABEL: single_bit3:
+; RV64I:   # %bb.0: # %entry
+; RV64I-NEXT:slli a1, a1, 63
+; RV64I-NEXT:srai a0, a1, 63
+; RV64I-NEXT:and a0, a0, a2
+; RV64I-NEXT:ret
+;
+; RV64XVENTANACONDOPS-LABEL: single_bit3:
+; RV64XVENTANACONDOPS:   # %bb.0: # %entry
+; RV64XVENTANACONDOPS-NEXT:andi a1, a1, 1
+; RV64XVENTANACONDOPS-NEXT:vt.maskc a0, a2, a1
+; RV64XVENTANACONDOPS-NEXT:ret
+;
+; RV64XTHEADCONDMOV-LABEL: single_bit3:
+; RV64XTHEADCONDMOV:   # %bb.0: # %entry
+; RV64XTHEADCONDMOV-NEXT:slli a1, a1, 63
+; RV64XTHEADCONDMOV-NEXT:srai a0, a1, 63
+; RV64XTHEADCONDMOV-NEXT:and a0, a0, a2
+; RV64XTHEADCONDMOV-NEXT:ret
+;
+; RV32ZICOND-LABEL: single_bit3:
+; RV32ZICOND:   # %bb.0: # %entry
+; RV32ZICOND-NEXT:lw a0, 8(a0)
+; RV32ZICOND-NEXT:andi a3, a0, 1
+; RV32ZICOND-NEXT:czero.eqz a0, a1, a3
+; RV32ZICOND-NEXT:czero.eqz a1, a2, a3
+; RV32ZICOND-NEXT:ret
+;
+; RV64ZICOND-LABEL: single_bit3:
+; RV64ZICOND:   # %bb.0: # %entry
+; RV64ZICOND-NEXT:andi a1, a1, 1
+; RV64ZICOND-NEXT:czero.eqz a0, a2, a1
+; RV64ZICOND-NEXT:ret
+entry:
+  %and = and i80 %x, 18446744073709551616 ; 1 << 64
+  %tobool.not = icmp eq i80 %and, 0
+  %cond = select i1 %tobool.not, i64 0, i64 %y
+  ret i64 %cond
+}

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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Use APInt in useInversedSetcc to prevent crashes when mask is larger than UINT64_MAX. (#81888) (PR #81905)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-backend-risc-v

Author: None (llvmbot)


Changes

Backport b57ba8ec514190b38eced26d541e8e25af66c485

Requested by: @topperc

---
Full diff: https://github.com/llvm/llvm-project/pull/81905.diff


2 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+2-2) 
- (modified) llvm/test/CodeGen/RISCV/condops.ll (+51) 


``diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp 
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7895d74f06d12a..6ce7215e03ff49 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -14658,8 +14658,8 @@ static SDValue useInversedSetcc(SDNode *N, SelectionDAG 
,
 ISD::CondCode CC = cast(Cond.getOperand(2))->get();
 if (CC == ISD::SETEQ && LHS.getOpcode() == ISD::AND &&
 isa(LHS.getOperand(1)) && isNullConstant(RHS)) {
-  uint64_t MaskVal = LHS.getConstantOperandVal(1);
-  if (isPowerOf2_64(MaskVal) && !isInt<12>(MaskVal))
+  const APInt  = LHS.getConstantOperandAPInt(1);
+  if (MaskVal.isPowerOf2() && !MaskVal.isSignedIntN(12))
 return DAG.getSelect(DL, VT,
  DAG.getSetCC(DL, CondVT, LHS, RHS, ISD::SETNE),
  False, True);
diff --git a/llvm/test/CodeGen/RISCV/condops.ll 
b/llvm/test/CodeGen/RISCV/condops.ll
index 8e53782b5dcd78..101cb5aeeb0940 100644
--- a/llvm/test/CodeGen/RISCV/condops.ll
+++ b/llvm/test/CodeGen/RISCV/condops.ll
@@ -3719,3 +3719,54 @@ entry:
   %cond = select i1 %tobool.not, i64 0, i64 %x
   ret i64 %cond
 }
+
+; Test that we don't crash on types larger than 64 bits.
+define i64 @single_bit3(i80 %x, i64 %y) {
+; RV32I-LABEL: single_bit3:
+; RV32I:   # %bb.0: # %entry
+; RV32I-NEXT:lw a0, 8(a0)
+; RV32I-NEXT:slli a0, a0, 31
+; RV32I-NEXT:srai a3, a0, 31
+; RV32I-NEXT:and a0, a3, a1
+; RV32I-NEXT:and a1, a3, a2
+; RV32I-NEXT:ret
+;
+; RV64I-LABEL: single_bit3:
+; RV64I:   # %bb.0: # %entry
+; RV64I-NEXT:slli a1, a1, 63
+; RV64I-NEXT:srai a0, a1, 63
+; RV64I-NEXT:and a0, a0, a2
+; RV64I-NEXT:ret
+;
+; RV64XVENTANACONDOPS-LABEL: single_bit3:
+; RV64XVENTANACONDOPS:   # %bb.0: # %entry
+; RV64XVENTANACONDOPS-NEXT:andi a1, a1, 1
+; RV64XVENTANACONDOPS-NEXT:vt.maskc a0, a2, a1
+; RV64XVENTANACONDOPS-NEXT:ret
+;
+; RV64XTHEADCONDMOV-LABEL: single_bit3:
+; RV64XTHEADCONDMOV:   # %bb.0: # %entry
+; RV64XTHEADCONDMOV-NEXT:slli a1, a1, 63
+; RV64XTHEADCONDMOV-NEXT:srai a0, a1, 63
+; RV64XTHEADCONDMOV-NEXT:and a0, a0, a2
+; RV64XTHEADCONDMOV-NEXT:ret
+;
+; RV32ZICOND-LABEL: single_bit3:
+; RV32ZICOND:   # %bb.0: # %entry
+; RV32ZICOND-NEXT:lw a0, 8(a0)
+; RV32ZICOND-NEXT:andi a3, a0, 1
+; RV32ZICOND-NEXT:czero.eqz a0, a1, a3
+; RV32ZICOND-NEXT:czero.eqz a1, a2, a3
+; RV32ZICOND-NEXT:ret
+;
+; RV64ZICOND-LABEL: single_bit3:
+; RV64ZICOND:   # %bb.0: # %entry
+; RV64ZICOND-NEXT:andi a1, a1, 1
+; RV64ZICOND-NEXT:czero.eqz a0, a2, a1
+; RV64ZICOND-NEXT:ret
+entry:
+  %and = and i80 %x, 18446744073709551616 ; 1 << 64
+  %tobool.not = icmp eq i80 %and, 0
+  %cond = select i1 %tobool.not, i64 0, i64 %y
+  ret i64 %cond
+}

``




https://github.com/llvm/llvm-project/pull/81905
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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Use APInt in useInversedSetcc to prevent crashes when mask is larger than UINT64_MAX. (#81888) (PR #81905)

[via llvm-branch-commits]

https://github.com/llvmbot created 
https://github.com/llvm/llvm-project/pull/81905

Backport b57ba8ec514190b38eced26d541e8e25af66c485

Requested by: @topperc

>From a5e2945a3b0bb06c2c3d54cc000399a6bdb1b70f Mon Sep 17 00:00:00 2001
From: Craig Topper 
Date: Thu, 15 Feb 2024 10:48:52 -0800
Subject: [PATCH] [RISCV] Use APInt in useInversedSetcc to prevent crashes when
 mask is larger than UINT64_MAX. (#81888)

There are no checks that the type is legal so we need to handle any
type.

(cherry picked from commit b57ba8ec514190b38eced26d541e8e25af66c485)
---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp |  4 +-
 llvm/test/CodeGen/RISCV/condops.ll  | 51 +
 2 files changed, 53 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp 
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7895d74f06d12a..6ce7215e03ff49 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -14658,8 +14658,8 @@ static SDValue useInversedSetcc(SDNode *N, SelectionDAG 
,
 ISD::CondCode CC = cast(Cond.getOperand(2))->get();
 if (CC == ISD::SETEQ && LHS.getOpcode() == ISD::AND &&
 isa(LHS.getOperand(1)) && isNullConstant(RHS)) {
-  uint64_t MaskVal = LHS.getConstantOperandVal(1);
-  if (isPowerOf2_64(MaskVal) && !isInt<12>(MaskVal))
+  const APInt  = LHS.getConstantOperandAPInt(1);
+  if (MaskVal.isPowerOf2() && !MaskVal.isSignedIntN(12))
 return DAG.getSelect(DL, VT,
  DAG.getSetCC(DL, CondVT, LHS, RHS, ISD::SETNE),
  False, True);
diff --git a/llvm/test/CodeGen/RISCV/condops.ll 
b/llvm/test/CodeGen/RISCV/condops.ll
index 8e53782b5dcd78..101cb5aeeb0940 100644
--- a/llvm/test/CodeGen/RISCV/condops.ll
+++ b/llvm/test/CodeGen/RISCV/condops.ll
@@ -3719,3 +3719,54 @@ entry:
   %cond = select i1 %tobool.not, i64 0, i64 %x
   ret i64 %cond
 }
+
+; Test that we don't crash on types larger than 64 bits.
+define i64 @single_bit3(i80 %x, i64 %y) {
+; RV32I-LABEL: single_bit3:
+; RV32I:   # %bb.0: # %entry
+; RV32I-NEXT:lw a0, 8(a0)
+; RV32I-NEXT:slli a0, a0, 31
+; RV32I-NEXT:srai a3, a0, 31
+; RV32I-NEXT:and a0, a3, a1
+; RV32I-NEXT:and a1, a3, a2
+; RV32I-NEXT:ret
+;
+; RV64I-LABEL: single_bit3:
+; RV64I:   # %bb.0: # %entry
+; RV64I-NEXT:slli a1, a1, 63
+; RV64I-NEXT:srai a0, a1, 63
+; RV64I-NEXT:and a0, a0, a2
+; RV64I-NEXT:ret
+;
+; RV64XVENTANACONDOPS-LABEL: single_bit3:
+; RV64XVENTANACONDOPS:   # %bb.0: # %entry
+; RV64XVENTANACONDOPS-NEXT:andi a1, a1, 1
+; RV64XVENTANACONDOPS-NEXT:vt.maskc a0, a2, a1
+; RV64XVENTANACONDOPS-NEXT:ret
+;
+; RV64XTHEADCONDMOV-LABEL: single_bit3:
+; RV64XTHEADCONDMOV:   # %bb.0: # %entry
+; RV64XTHEADCONDMOV-NEXT:slli a1, a1, 63
+; RV64XTHEADCONDMOV-NEXT:srai a0, a1, 63
+; RV64XTHEADCONDMOV-NEXT:and a0, a0, a2
+; RV64XTHEADCONDMOV-NEXT:ret
+;
+; RV32ZICOND-LABEL: single_bit3:
+; RV32ZICOND:   # %bb.0: # %entry
+; RV32ZICOND-NEXT:lw a0, 8(a0)
+; RV32ZICOND-NEXT:andi a3, a0, 1
+; RV32ZICOND-NEXT:czero.eqz a0, a1, a3
+; RV32ZICOND-NEXT:czero.eqz a1, a2, a3
+; RV32ZICOND-NEXT:ret
+;
+; RV64ZICOND-LABEL: single_bit3:
+; RV64ZICOND:   # %bb.0: # %entry
+; RV64ZICOND-NEXT:andi a1, a1, 1
+; RV64ZICOND-NEXT:czero.eqz a0, a2, a1
+; RV64ZICOND-NEXT:ret
+entry:
+  %and = and i80 %x, 18446744073709551616 ; 1 << 64
+  %tobool.not = icmp eq i80 %and, 0
+  %cond = select i1 %tobool.not, i64 0, i64 %y
+  ret i64 %cond
+}

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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Use APInt in useInversedSetcc to prevent crashes when mask is larger than UINT64_MAX. (#81888) (PR #81905)

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llvmbot wrote:

@asb What do you think about merging this PR to the release branch?

https://github.com/llvm/llvm-project/pull/81905
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[llvm-branch-commits] [llvm] Backport ARM64EC variadic args fixes to LLVM 18 (PR #81800)

[Daniel Paoliello via llvm-branch-commits]

dpaoliello wrote:

> I was sort of waiting until the discussion on #80994 resolves... we might end 
> up reverting parts of #80595 .
> 
> I guess it won't do any harm to land as-is, though.

I'll wait - I'd rather not drop something into the release branch if we know it 
may cause issues.

https://github.com/llvm/llvm-project/pull/81800
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[llvm-branch-commits] [ELF] Support placing .lbss/.lrodata/.ldata after .bss (PR #81224)

[Fangrui Song via llvm-branch-commits]

@@ -1436,6 +1436,8 @@ static void readConfigs(opt::InputArgList ) {
   config->zInterpose = hasZOption(args, "interpose");
   config->zKeepTextSectionPrefix = getZFlag(
   args, "keep-text-section-prefix", "nokeep-text-section-prefix", false);
+  config->zLrodataAfterBss =
+  getZFlag(args, "lrodata-after-bss", "nolrodata-after-bss", false);

MaskRay wrote:

Sorry, but no. I don't think the x86-64 -fno-pic case justifies changing the 
tradition that -no-pie/-pie does not change the layout (internal linker 
script). `-z lrodata-after-bss` is a common ground that we both can accept and 
it has its own merit to test two layouts for file-backed transparent huge pages.

https://github.com/llvm/llvm-project/pull/81224
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[llvm-branch-commits] [llvm] [asan] isInterestingAlloca: remove the isAllocaPromotable condition (PR #77221)

[Fangrui Song via llvm-branch-commits]

https://github.com/MaskRay closed 
https://github.com/llvm/llvm-project/pull/77221
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[llvm-branch-commits] [llvm] [asan] isInterestingAlloca: remove the isAllocaPromotable condition (PR #77221)

[Vitaly Buka via llvm-branch-commits]

@@ -1279,9 +1278,6 @@ bool AddressSanitizer::isInterestingAlloca(const 
AllocaInst ) {
   (AI.getAllocatedType()->isSized() &&

vitalybuka wrote:

Yes, either keep as ClSkipPromotableAllocas=false, just in case, or remove it.
Something similar but not the same is not needed.

https://github.com/llvm/llvm-project/pull/77221
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[llvm-branch-commits] [llvm] [asan] isInterestingAlloca: remove the isAllocaPromotable condition (PR #77221)

[Vitaly Buka via llvm-branch-commits]

https://github.com/vitalybuka edited 
https://github.com/llvm/llvm-project/pull/77221
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[llvm-branch-commits] [llvm] [asan] isInterestingAlloca: remove the isAllocaPromotable condition (PR #77221)

[Vitaly Buka via llvm-branch-commits]

https://github.com/vitalybuka approved this pull request.


https://github.com/llvm/llvm-project/pull/77221
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[llvm-branch-commits] [clang] [analyzer][docs] Admit that the cleanup attribute is not supported (PR #81834)

[Gábor Horváth via llvm-branch-commits]

https://github.com/Xazax-hun approved this pull request.


https://github.com/llvm/llvm-project/pull/81834
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[llvm-branch-commits] [OpenMP][MLIR] Extend explicit derived type member mapping support for OpenMP dialects lowering to LLVM-IR (PR #81510)

[Kareem Ergawy via llvm-branch-commits]

@@ -1783,6 +1783,98 @@ void collectMapDataFromMapOperands(MapInfoData ,
   }
 }
 
+static int getMapDataMemberIdx(MapInfoData ,
+   mlir::omp::MapInfoOp memberOp) {
+  int memberDataIdx = -1;
+  for (size_t i = 0; i < mapData.MapClause.size(); ++i) {
+if (mapData.MapClause[i] == memberOp)
+  memberDataIdx = i;
+  }
+  return memberDataIdx;
+}
+
+static mlir::omp::MapInfoOp
+getFirstOrLastMappedMemberPtr(mlir::omp::MapInfoOp mapInfo, bool first) {
+  // Only 1 member has been mapped, we can return it.
+  if (mapInfo.getMembersIndex()->size() == 1)
+if (auto mapOp = mlir::dyn_cast(
+mapInfo.getMembers()[0].getDefiningOp()))
+  return mapOp;
+
+  int64_t curPos =
+  mapInfo.getMembersIndex()->begin()->cast().getInt();
+
+  int64_t idx = 1, curIdx = 0, memberPlacement = 0;
+  for (const auto *iter = std::next(mapInfo.getMembersIndex()->begin());
+   iter != mapInfo.getMembersIndex()->end(); iter++) {
+memberPlacement = iter->cast().getInt();
+if (first) {
+  if (memberPlacement < curPos) {
+curIdx = idx;
+curPos = memberPlacement;
+  }
+} else {
+  if (memberPlacement > curPos) {
+curIdx = idx;
+curPos = memberPlacement;
+  }
+}
+idx++;
+  }
+
+  if (auto mapOp = mlir::dyn_cast(
+  mapInfo.getMembers()[curIdx].getDefiningOp()))
+return mapOp;
+
+  return {};
+}
+
+std::vector
+calculateBoundsOffset(LLVM::ModuleTranslation ,

ergawy wrote:

There is quite some complicated logic in this function, can you add some 
documentation on the function to provide a high-level description? And in the 
function itself, can you add a few more comments explaining things like why you 
are iterating backwards in some cases?

https://github.com/llvm/llvm-project/pull/81510
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[llvm-branch-commits] [OpenMP][MLIR] Extend explicit derived type member mapping support for OpenMP dialects lowering to LLVM-IR (PR #81510)

[Kareem Ergawy via llvm-branch-commits]

@@ -1783,6 +1783,98 @@ void collectMapDataFromMapOperands(MapInfoData ,
   }
 }
 
+static int getMapDataMemberIdx(MapInfoData ,
+   mlir::omp::MapInfoOp memberOp) {
+  int memberDataIdx = -1;
+  for (size_t i = 0; i < mapData.MapClause.size(); ++i) {
+if (mapData.MapClause[i] == memberOp)
+  memberDataIdx = i;
+  }
+  return memberDataIdx;
+}
+
+static mlir::omp::MapInfoOp
+getFirstOrLastMappedMemberPtr(mlir::omp::MapInfoOp mapInfo, bool first) {
+  // Only 1 member has been mapped, we can return it.
+  if (mapInfo.getMembersIndex()->size() == 1)
+if (auto mapOp = mlir::dyn_cast(
+mapInfo.getMembers()[0].getDefiningOp()))
+  return mapOp;
+
+  int64_t curPos =
+  mapInfo.getMembersIndex()->begin()->cast().getInt();
+
+  int64_t idx = 1, curIdx = 0, memberPlacement = 0;
+  for (const auto *iter = std::next(mapInfo.getMembersIndex()->begin());
+   iter != mapInfo.getMembersIndex()->end(); iter++) {
+memberPlacement = iter->cast().getInt();
+if (first) {
+  if (memberPlacement < curPos) {
+curIdx = idx;
+curPos = memberPlacement;
+  }
+} else {
+  if (memberPlacement > curPos) {
+curIdx = idx;
+curPos = memberPlacement;
+  }
+}
+idx++;
+  }

ergawy wrote:

Can we instead sort `getMembersIndex()` somehow and fetch either the head or 
the tail based on `first`? Not sure how easy it is but my feeling is that it 
should be possible and would be easier to understand.

Or guarantee that it is always sorted on op creation/update. But maybe this is 
not worth it.

https://github.com/llvm/llvm-project/pull/81510
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[llvm-branch-commits] [OpenMP][MLIR] Extend explicit derived type member mapping support for OpenMP dialects lowering to LLVM-IR (PR #81510)

[Kareem Ergawy via llvm-branch-commits]

@@ -1783,6 +1783,98 @@ void collectMapDataFromMapOperands(MapInfoData ,
   }
 }
 
+static int getMapDataMemberIdx(MapInfoData ,
+   mlir::omp::MapInfoOp memberOp) {
+  int memberDataIdx = -1;
+  for (size_t i = 0; i < mapData.MapClause.size(); ++i) {
+if (mapData.MapClause[i] == memberOp)
+  memberDataIdx = i;
+  }
+  return memberDataIdx;
+}
+
+static mlir::omp::MapInfoOp
+getFirstOrLastMappedMemberPtr(mlir::omp::MapInfoOp mapInfo, bool first) {
+  // Only 1 member has been mapped, we can return it.
+  if (mapInfo.getMembersIndex()->size() == 1)
+if (auto mapOp = mlir::dyn_cast(
+mapInfo.getMembers()[0].getDefiningOp()))
+  return mapOp;
+
+  int64_t curPos =
+  mapInfo.getMembersIndex()->begin()->cast().getInt();
+
+  int64_t idx = 1, curIdx = 0, memberPlacement = 0;
+  for (const auto *iter = std::next(mapInfo.getMembersIndex()->begin());
+   iter != mapInfo.getMembersIndex()->end(); iter++) {
+memberPlacement = iter->cast().getInt();
+if (first) {
+  if (memberPlacement < curPos) {
+curIdx = idx;
+curPos = memberPlacement;
+  }
+} else {
+  if (memberPlacement > curPos) {
+curIdx = idx;
+curPos = memberPlacement;
+  }
+}
+idx++;
+  }
+
+  if (auto mapOp = mlir::dyn_cast(
+  mapInfo.getMembers()[curIdx].getDefiningOp()))
+return mapOp;
+
+  return {};
+}
+
+std::vector
+calculateBoundsOffset(LLVM::ModuleTranslation ,
+  llvm::IRBuilderBase , bool isArrayTy,
+  mlir::OperandRange bounds) {
+  std::vector idx;
+  llvm::Value *offsetAddress = nullptr;
+  if (!bounds.empty()) {
+idx.push_back(builder.getInt64(0));
+if (isArrayTy) {
+  for (int i = bounds.size() - 1; i >= 0; --i) {
+if (auto boundOp = mlir::dyn_cast_if_present(
+bounds[i].getDefiningOp())) {
+  
idx.push_back(moduleTranslation.lookupValue(boundOp.getLowerBound()));
+}
+  }
+} else {
+  std::vector dimensionIndexSizeOffset{builder.getInt64(1)};
+  for (size_t i = 1; i < bounds.size(); ++i) {
+if (auto boundOp = mlir::dyn_cast_if_present(
+bounds[i].getDefiningOp())) {
+  dimensionIndexSizeOffset.push_back(builder.CreateMul(
+  moduleTranslation.lookupValue(boundOp.getExtent()),
+  dimensionIndexSizeOffset[i - 1]));
+}
+  }
+
+  for (int i = bounds.size() - 1; i >= 0; --i) {
+if (auto boundOp = mlir::dyn_cast_if_present(
+bounds[i].getDefiningOp())) {
+  if (!offsetAddress)
+offsetAddress = builder.CreateMul(
+moduleTranslation.lookupValue(boundOp.getLowerBound()),
+dimensionIndexSizeOffset[i]);
+  else
+offsetAddress = builder.CreateAdd(
+offsetAddress, builder.CreateMul(moduleTranslation.lookupValue(
+ boundOp.getLowerBound()),
+ dimensionIndexSizeOffset[i]));

ergawy wrote:

I think you can get rid of `offsetAddress` this way:
```suggestion
  if (idx.empty())
idx.emplace_back(builder.CreateMul(
moduleTranslation.lookupValue(boundOp.getLowerBound()),
dimensionIndexSizeOffset[i]));
  else
offsetAddress.back() = builder.CreateAdd(
offsetAddress.back(), 
builder.CreateMul(moduleTranslation.lookupValue(
 boundOp.getLowerBound()),
 dimensionIndexSizeOffset[i]));
```

https://github.com/llvm/llvm-project/pull/81510
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[llvm-branch-commits] [OpenMP][MLIR] Extend explicit derived type member mapping support for OpenMP dialects lowering to LLVM-IR (PR #81510)

[Kareem Ergawy via llvm-branch-commits]

@@ -1783,6 +1783,98 @@ void collectMapDataFromMapOperands(MapInfoData ,
   }
 }
 
+static int getMapDataMemberIdx(MapInfoData ,
+   mlir::omp::MapInfoOp memberOp) {
+  int memberDataIdx = -1;
+  for (size_t i = 0; i < mapData.MapClause.size(); ++i) {
+if (mapData.MapClause[i] == memberOp)
+  memberDataIdx = i;
+  }
+  return memberDataIdx;
+}
+
+static mlir::omp::MapInfoOp
+getFirstOrLastMappedMemberPtr(mlir::omp::MapInfoOp mapInfo, bool first) {
+  // Only 1 member has been mapped, we can return it.
+  if (mapInfo.getMembersIndex()->size() == 1)
+if (auto mapOp = mlir::dyn_cast(
+mapInfo.getMembers()[0].getDefiningOp()))
+  return mapOp;
+
+  int64_t curPos =
+  mapInfo.getMembersIndex()->begin()->cast().getInt();
+
+  int64_t idx = 1, curIdx = 0, memberPlacement = 0;
+  for (const auto *iter = std::next(mapInfo.getMembersIndex()->begin());
+   iter != mapInfo.getMembersIndex()->end(); iter++) {
+memberPlacement = iter->cast().getInt();
+if (first) {
+  if (memberPlacement < curPos) {
+curIdx = idx;
+curPos = memberPlacement;
+  }
+} else {
+  if (memberPlacement > curPos) {
+curIdx = idx;
+curPos = memberPlacement;
+  }
+}
+idx++;
+  }
+
+  if (auto mapOp = mlir::dyn_cast(
+  mapInfo.getMembers()[curIdx].getDefiningOp()))
+return mapOp;
+
+  return {};
+}
+
+std::vector
+calculateBoundsOffset(LLVM::ModuleTranslation ,
+  llvm::IRBuilderBase , bool isArrayTy,
+  mlir::OperandRange bounds) {
+  std::vector idx;
+  llvm::Value *offsetAddress = nullptr;
+  if (!bounds.empty()) {

ergawy wrote:

```suggestion
  if (bounds.empty())
return idx;

```

https://github.com/llvm/llvm-project/pull/81510
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[llvm-branch-commits] [OpenMP][MLIR] Extend explicit derived type member mapping support for OpenMP dialects lowering to LLVM-IR (PR #81510)

[Kareem Ergawy via llvm-branch-commits]

@@ -1783,6 +1783,98 @@ void collectMapDataFromMapOperands(MapInfoData ,
   }
 }
 
+static int getMapDataMemberIdx(MapInfoData ,
+   mlir::omp::MapInfoOp memberOp) {
+  int memberDataIdx = -1;
+  for (size_t i = 0; i < mapData.MapClause.size(); ++i) {
+if (mapData.MapClause[i] == memberOp)
+  memberDataIdx = i;
+  }
+  return memberDataIdx;
+}

ergawy wrote:

`std::find_if(...)`, just like the other PR .

Also it seems like all the uses of this function assume that `-1` will not be 
returned (there has to be an element matching the search key). So, I would 
suggest:
```suggestion
static int getMapDataMemberIdx(MapInfoData ,
   mlir::omp::MapInfoOp memberOp) {
  auto res = llvm::find(mapData.MapClause, memberOp);
  assert(res != mapData.MapClause.end());
  return std::distance(mapData.MapClause.begin(), res);
}
```

https://github.com/llvm/llvm-project/pull/81510
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[llvm-branch-commits] [OpenMP][MLIR] Extend explicit derived type member mapping support for OpenMP dialects lowering to LLVM-IR (PR #81510)

[Kareem Ergawy via llvm-branch-commits]

@@ -1783,6 +1783,98 @@ void collectMapDataFromMapOperands(MapInfoData ,
   }
 }
 
+static int getMapDataMemberIdx(MapInfoData ,
+   mlir::omp::MapInfoOp memberOp) {
+  int memberDataIdx = -1;
+  for (size_t i = 0; i < mapData.MapClause.size(); ++i) {
+if (mapData.MapClause[i] == memberOp)
+  memberDataIdx = i;
+  }
+  return memberDataIdx;
+}
+
+static mlir::omp::MapInfoOp
+getFirstOrLastMappedMemberPtr(mlir::omp::MapInfoOp mapInfo, bool first) {
+  // Only 1 member has been mapped, we can return it.
+  if (mapInfo.getMembersIndex()->size() == 1)
+if (auto mapOp = mlir::dyn_cast(
+mapInfo.getMembers()[0].getDefiningOp()))
+  return mapOp;
+
+  int64_t curPos =
+  mapInfo.getMembersIndex()->begin()->cast().getInt();
+
+  int64_t idx = 1, curIdx = 0, memberPlacement = 0;
+  for (const auto *iter = std::next(mapInfo.getMembersIndex()->begin());
+   iter != mapInfo.getMembersIndex()->end(); iter++) {
+memberPlacement = iter->cast().getInt();
+if (first) {
+  if (memberPlacement < curPos) {
+curIdx = idx;
+curPos = memberPlacement;
+  }
+} else {
+  if (memberPlacement > curPos) {
+curIdx = idx;
+curPos = memberPlacement;
+  }
+}
+idx++;
+  }
+
+  if (auto mapOp = mlir::dyn_cast(
+  mapInfo.getMembers()[curIdx].getDefiningOp()))
+return mapOp;
+
+  return {};

ergawy wrote:

Apologies for repeating this, but I think it is better to `assert` if some 
assumption in the code is violated rather than returning an empty value.

https://github.com/llvm/llvm-project/pull/81510
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[llvm-branch-commits] [libcxx] release/18.x: [libc++][modules] Re-add build dir CMakeLists.txt. (#81370) (PR #81651)

[Louis Dionne via llvm-branch-commits]

ldionne wrote:

Approved after talking with Mark. This is important for early adopters of 
modules.

https://github.com/llvm/llvm-project/pull/81651
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[llvm-branch-commits] [ELF] Support placing .lbss/.lrodata/.ldata after .bss (PR #81224)

[James Y Knight via llvm-branch-commits]

@@ -1436,6 +1436,8 @@ static void readConfigs(opt::InputArgList ) {
   config->zInterpose = hasZOption(args, "interpose");
   config->zKeepTextSectionPrefix = getZFlag(
   args, "keep-text-section-prefix", "nokeep-text-section-prefix", false);
+  config->zLrodataAfterBss =
+  getZFlag(args, "lrodata-after-bss", "nolrodata-after-bss", false);

jyknight wrote:

Use `!config->isPic` as default value, instead of false? (moving below the 
assignment of `isPic`, of course)

https://github.com/llvm/llvm-project/pull/81224
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[llvm-branch-commits] [Flang][OpenMP][MLIR] Extend derived (record) type map support in Flang OpenMP by adding some initial support for explicit member mapping (PR #81511)

[via llvm-branch-commits]

@@ -0,0 +1,262 @@
+//===- OMPMapInfoFinalization.cpp
+//---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+/// \file
+/// An OpenMP dialect related pass for FIR/HLFIR which performs some
+/// pre-processing of MapInfoOp's after the module has been lowered to
+/// finalize them.
+///
+/// For example, it expands MapInfoOp's containing descriptor related
+/// types (fir::BoxType's) into multiple MapInfoOp's containing the parent
+/// descriptor and pointer member components for individual mapping,
+/// treating the descriptor type as a record type for later lowering in the
+/// OpenMP dialect.
+///
+/// The pass also adds MapInfoOp's that are members of a parent object but are
+/// not directly used in the body of a target region to it's BlockArgument list
+/// to maintain consistency across all MapInfoOp's tied to a region directly or
+/// indirectly via an parent object.
+//===--===//
+
+#include "flang/Optimizer/Builder/FIRBuilder.h"
+#include "flang/Optimizer/Dialect/FIRType.h"
+#include "flang/Optimizer/Dialect/Support/KindMapping.h"
+#include "flang/Optimizer/Transforms/Passes.h"
+#include "mlir/Dialect/Func/IR/FuncOps.h"
+#include "mlir/Dialect/OpenMP/OpenMPDialect.h"
+#include "mlir/IR/BuiltinDialect.h"
+#include "mlir/IR/BuiltinOps.h"
+#include "mlir/IR/Operation.h"
+#include "mlir/IR/SymbolTable.h"
+#include "mlir/Pass/Pass.h"
+#include "mlir/Support/LLVM.h"
+#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/Frontend/OpenMP/OMPConstants.h"
+#include 
+
+namespace fir {
+#define GEN_PASS_DEF_OMPMAPINFOFINALIZATIONPASS
+#include "flang/Optimizer/Transforms/Passes.h.inc"
+} // namespace fir
+
+namespace {
+class OMPMapInfoFinalizationPass
+: public fir::impl::OMPMapInfoFinalizationPassBase<
+  OMPMapInfoFinalizationPass> {
+
+  void genDescriptorMemberMaps(mlir::omp::MapInfoOp op,
+   fir::FirOpBuilder ,
+   mlir::Operation *target) {
+mlir::Location loc = builder.getUnknownLoc();
+mlir::Value descriptor = op.getVarPtr();
+
+// If we enter this function, but the mapped type itself is not the
+// descriptor, then it's likely the address of the descriptor so we
+// must retrieve the descriptor SSA.
+if (!fir::isTypeWithDescriptor(op.getVarType())) {
+  if (auto addrOp = mlir::dyn_cast_if_present(
+  op.getVarPtr().getDefiningOp())) {
+descriptor = addrOp.getVal();
+  }
+}
+
+// The fir::BoxOffsetOp only works with !fir.ref> types, as
+// allowing it to access non-reference box operations can cause some
+// problematic SSA IR. However, in the case of assumed shape's the type
+// is not a !fir.ref, in these cases to retrieve the appropriate
+// !fir.ref> to access the data we need to map we must
+// perform an alloca and then store to it and retrieve the data from the 
new
+// alloca.
+if (mlir::isa(descriptor.getType())) {
+  mlir::OpBuilder::InsertPoint insPt = builder.saveInsertionPoint();
+  builder.setInsertionPointToStart(builder.getAllocaBlock());
+  auto alloca = builder.create(loc, descriptor.getType());
+  builder.restoreInsertionPoint(insPt);
+  builder.create(loc, descriptor, alloca);
+  descriptor = alloca;
+}
+
+mlir::Value baseAddrAddr = builder.create(
+loc, descriptor, fir::BoxFieldAttr::base_addr);
+
+llvm::omp::OpenMPOffloadMappingFlags baseAddrMapFlag =
+llvm::omp::OpenMPOffloadMappingFlags(op.getMapType().value());
+baseAddrMapFlag |=
+llvm::omp::OpenMPOffloadMappingFlags::OMP_MAP_PTR_AND_OBJ;
+
+// Member of the descriptor pointing at the allocated data
+mlir::Value baseAddr = builder.create(
+loc, baseAddrAddr.getType(), descriptor,
+mlir::TypeAttr::get(llvm::cast(
+fir::unwrapRefType(baseAddrAddr.getType()))
+.getElementType()),
+baseAddrAddr, mlir::SmallVector{}, mlir::ArrayAttr{},
+op.getBounds(),
+builder.getIntegerAttr(
+builder.getIntegerType(64, false),
+static_cast<
+std::underlying_type_t>(
+baseAddrMapFlag)),
+builder.getAttr(
+mlir::omp::VariableCaptureKind::ByRef),
+builder.getStringAttr("") /*name*/,
+builder.getBoolAttr(false) /*partial_map*/);
+
+// TODO: map the addendum segment of the descriptor, similarly to the
+// above base address/data pointer member.
+
+if (auto 

[llvm-branch-commits] [llvm] [AArch64] Improve cost model for legal subvec insert/extract (PR #81135)

[Sander de Smalen via llvm-branch-commits]

@@ -568,6 +568,48 @@ AArch64TTIImpl::getIntrinsicInstrCost(const 
IntrinsicCostAttributes ,
 }
 return Cost;
   }
+  case Intrinsic::vector_extract: {
+// If both the vector argument and the return type are legal types and the
+// index is 0, then this should be a no-op or simple operation; return a
+// relatively low cost.
+
+// If arguments aren't actually supplied, then we cannot determine the
+// value of the index.
+if (ICA.getArgs().size() < 2)
+  break;
+LLVMContext  = RetTy->getContext();
+EVT MRTy = getTLI()->getValueType(DL, RetTy);
+EVT MPTy = getTLI()->getValueType(DL, ICA.getArgTypes()[0]);
+TargetLoweringBase::LegalizeKind RLK = getTLI()->getTypeConversion(C, 
MRTy);
+TargetLoweringBase::LegalizeKind PLK = getTLI()->getTypeConversion(C, 
MPTy);
+const ConstantInt *Idx = dyn_cast(ICA.getArgs()[1]);
+if (RLK.first == TargetLoweringBase::TypeLegal &&
+PLK.first == TargetLoweringBase::TypeLegal && Idx &&
+Idx->getZExtValue() == 0)
+  return InstructionCost(1);

sdesmalen-arm wrote:

Is there a reason this wouldn't this be zero-cost?

Also, stylistically to match the rest of this file, maybe return 
`TTI::TCC_Free` (if this is considered a cost of 0) or `TTI::TCC_Basic` (if 
this is considered a cost of 1) instead?

https://github.com/llvm/llvm-project/pull/81135
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[llvm-branch-commits] [llvm] [AArch64] Improve cost model for legal subvec insert/extract (PR #81135)

[Sander de Smalen via llvm-branch-commits]

@@ -568,6 +568,48 @@ AArch64TTIImpl::getIntrinsicInstrCost(const 
IntrinsicCostAttributes ,
 }
 return Cost;
   }
+  case Intrinsic::vector_extract: {
+// If both the vector argument and the return type are legal types and the
+// index is 0, then this should be a no-op or simple operation; return a
+// relatively low cost.
+
+// If arguments aren't actually supplied, then we cannot determine the
+// value of the index.
+if (ICA.getArgs().size() < 2)

sdesmalen-arm wrote:

nit:
```suggestion
if (ICA.getArgs().size() != 2)
```

https://github.com/llvm/llvm-project/pull/81135
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[llvm-branch-commits] [llvm] [AArch64] Improve cost model for legal subvec insert/extract (PR #81135)

[Sander de Smalen via llvm-branch-commits]

@@ -568,6 +568,32 @@ AArch64TTIImpl::getIntrinsicInstrCost(const 
IntrinsicCostAttributes ,
 }
 return Cost;
   }
+  case Intrinsic::vector_extract: {
+// If both the vector argument and the return type are legal types, then
+// this should be a no-op or simple operation; return a relatively low 
cost.
+LLVMContext  = RetTy->getContext();
+EVT MRTy = getTLI()->getValueType(DL, RetTy);
+EVT MPTy = getTLI()->getValueType(DL, ICA.getArgTypes()[0]);
+TargetLoweringBase::LegalizeKind RLK = getTLI()->getTypeConversion(C, 
MRTy);
+TargetLoweringBase::LegalizeKind PLK = getTLI()->getTypeConversion(C, 
MPTy);
+if (RLK.first == TargetLoweringBase::TypeLegal &&
+PLK.first == TargetLoweringBase::TypeLegal)
+  return InstructionCost(1);

sdesmalen-arm wrote:

Just pointing out that the code isn't updated yet to handle predicates 
differently, as those inserts/extracts are indeed not free.

https://github.com/llvm/llvm-project/pull/81135
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[llvm-branch-commits] [clang] [llvm] release/18.x: Backport Ampere1B support (#81297 , #81341, and #81744) (PR #81857)

[Philipp Tomsich via llvm-branch-commits]

https://github.com/ptomsich edited 
https://github.com/llvm/llvm-project/pull/81857
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[llvm-branch-commits] [clang] [llvm] release/18.x: Backport Ampere1B support (#81744) (PR #81857)

[Philipp Tomsich via llvm-branch-commits]

https://github.com/ptomsich edited 
https://github.com/llvm/llvm-project/pull/81857
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[llvm-branch-commits] [Flang][OpenMP][MLIR] Extend derived (record) type map support in Flang OpenMP by adding some initial support for explicit member mapping (PR #81511)

[Kareem Ergawy via llvm-branch-commits]

@@ -1906,8 +2036,22 @@ bool ClauseProcessor::processMap(
 
 for (const Fortran::parser::OmpObject  :
  std::get(mapClause->v.t).v) {
+  llvm::omp::OpenMPOffloadMappingFlags objectsMapTypeBits = 
mapTypeBits;
+  checkAndApplyDeclTargetMapFlags(converter, objectsMapTypeBits,
+  getOmpObjectSymbol(ompObject));
+
   llvm::SmallVector bounds;
   std::stringstream asFortran;
+  const Fortran::semantics::Symbol *parentSym = nullptr;
+
+  if (getOmpObjectSymbol(ompObject)->owner().IsDerivedType()) {
+memberPlacementIndices.push_back(
+firOpBuilder.getI64IntegerAttr(findComponenetMemberPlacement(
+getOmpObjectSymbol(ompObject)->owner().symbol(),

ergawy wrote:

 Aha, I see now. Thanks for clarifying this!

https://github.com/llvm/llvm-project/pull/81511
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[llvm-branch-commits] [Flang][OpenMP][MLIR] Extend derived (record) type map support in Flang OpenMP by adding some initial support for explicit member mapping (PR #81511)

[Kareem Ergawy via llvm-branch-commits]

@@ -1859,7 +1983,13 @@ bool ClauseProcessor::processMap(
 llvm::SmallVectorImpl *mapSymbols)
 const {
   fir::FirOpBuilder  = converter.getFirOpBuilder();
-  return findRepeatableClause(
+
+  llvm::SmallVector memberMaps;
+  llvm::SmallVector memberPlacementIndices;
+  llvm::SmallVector memberParentSyms,
+  mapSyms;

ergawy wrote:

Right, makes sense to keep it then since it is always passed to 
`insertChildMapInfoIntoParent`.

https://github.com/llvm/llvm-project/pull/81511
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[llvm-branch-commits] [Flang][OpenMP][MLIR] Extend derived (record) type map support in Flang OpenMP by adding some initial support for explicit member mapping (PR #81511)

[Kareem Ergawy via llvm-branch-commits]

https://github.com/ergawy commented:

I reviewed the entire PR and commented on all what I thought worth mentioning. 
But I will leave the approval to people working on this longer than I am. 
Hopefully my review makes other reviewers go over the PR faster.

One comment about the lit tests in the PR in general: I see in quite a few 
places, there are `CHECK` lines that use the SSA names directly (e.g. `%20`). I 
think this is fragile and it would be better to either capture the name of the 
SSA value if we care about it and want to check it later (i.e. using 
`%[[name:.*]]`) or capture and discard the name of the value in a generic way 
(i.e. using `%{{.*}}`).

Thanks Andrew for answering my questions.

https://github.com/llvm/llvm-project/pull/81511
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[llvm-branch-commits] [Flang][OpenMP][MLIR] Extend derived (record) type map support in Flang OpenMP by adding some initial support for explicit member mapping (PR #81511)

[Kareem Ergawy via llvm-branch-commits]

@@ -0,0 +1,262 @@
+//===- OMPMapInfoFinalization.cpp
+//---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+/// \file
+/// An OpenMP dialect related pass for FIR/HLFIR which performs some
+/// pre-processing of MapInfoOp's after the module has been lowered to
+/// finalize them.
+///
+/// For example, it expands MapInfoOp's containing descriptor related
+/// types (fir::BoxType's) into multiple MapInfoOp's containing the parent
+/// descriptor and pointer member components for individual mapping,
+/// treating the descriptor type as a record type for later lowering in the
+/// OpenMP dialect.
+///
+/// The pass also adds MapInfoOp's that are members of a parent object but are
+/// not directly used in the body of a target region to it's BlockArgument list
+/// to maintain consistency across all MapInfoOp's tied to a region directly or
+/// indirectly via an parent object.
+//===--===//
+
+#include "flang/Optimizer/Builder/FIRBuilder.h"
+#include "flang/Optimizer/Dialect/FIRType.h"
+#include "flang/Optimizer/Dialect/Support/KindMapping.h"
+#include "flang/Optimizer/Transforms/Passes.h"
+#include "mlir/Dialect/Func/IR/FuncOps.h"
+#include "mlir/Dialect/OpenMP/OpenMPDialect.h"
+#include "mlir/IR/BuiltinDialect.h"
+#include "mlir/IR/BuiltinOps.h"
+#include "mlir/IR/Operation.h"
+#include "mlir/IR/SymbolTable.h"
+#include "mlir/Pass/Pass.h"
+#include "mlir/Support/LLVM.h"
+#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/Frontend/OpenMP/OMPConstants.h"
+#include 
+
+namespace fir {
+#define GEN_PASS_DEF_OMPMAPINFOFINALIZATIONPASS
+#include "flang/Optimizer/Transforms/Passes.h.inc"
+} // namespace fir
+
+namespace {
+class OMPMapInfoFinalizationPass
+: public fir::impl::OMPMapInfoFinalizationPassBase<
+  OMPMapInfoFinalizationPass> {
+
+  void genDescriptorMemberMaps(mlir::omp::MapInfoOp op,
+   fir::FirOpBuilder ,
+   mlir::Operation *target) {
+mlir::Location loc = builder.getUnknownLoc();
+mlir::Value descriptor = op.getVarPtr();
+
+// If we enter this function, but the mapped type itself is not the
+// descriptor, then it's likely the address of the descriptor so we
+// must retrieve the descriptor SSA.
+if (!fir::isTypeWithDescriptor(op.getVarType())) {
+  if (auto addrOp = mlir::dyn_cast_if_present(
+  op.getVarPtr().getDefiningOp())) {
+descriptor = addrOp.getVal();
+  }
+}
+
+// The fir::BoxOffsetOp only works with !fir.ref> types, as
+// allowing it to access non-reference box operations can cause some
+// problematic SSA IR. However, in the case of assumed shape's the type
+// is not a !fir.ref, in these cases to retrieve the appropriate
+// !fir.ref> to access the data we need to map we must
+// perform an alloca and then store to it and retrieve the data from the 
new
+// alloca.
+if (mlir::isa(descriptor.getType())) {
+  mlir::OpBuilder::InsertPoint insPt = builder.saveInsertionPoint();
+  builder.setInsertionPointToStart(builder.getAllocaBlock());
+  auto alloca = builder.create(loc, descriptor.getType());
+  builder.restoreInsertionPoint(insPt);
+  builder.create(loc, descriptor, alloca);
+  descriptor = alloca;
+}
+
+mlir::Value baseAddrAddr = builder.create(
+loc, descriptor, fir::BoxFieldAttr::base_addr);
+
+llvm::omp::OpenMPOffloadMappingFlags baseAddrMapFlag =
+llvm::omp::OpenMPOffloadMappingFlags(op.getMapType().value());
+baseAddrMapFlag |=
+llvm::omp::OpenMPOffloadMappingFlags::OMP_MAP_PTR_AND_OBJ;
+
+// Member of the descriptor pointing at the allocated data
+mlir::Value baseAddr = builder.create(
+loc, baseAddrAddr.getType(), descriptor,
+mlir::TypeAttr::get(llvm::cast(
+fir::unwrapRefType(baseAddrAddr.getType()))
+.getElementType()),
+baseAddrAddr, mlir::SmallVector{}, mlir::ArrayAttr{},
+op.getBounds(),
+builder.getIntegerAttr(
+builder.getIntegerType(64, false),
+static_cast<
+std::underlying_type_t>(
+baseAddrMapFlag)),
+builder.getAttr(
+mlir::omp::VariableCaptureKind::ByRef),
+builder.getStringAttr("") /*name*/,
+builder.getBoolAttr(false) /*partial_map*/);
+
+// TODO: map the addendum segment of the descriptor, similarly to the
+// above base address/data pointer member.
+
+if (auto 

[llvm-branch-commits] [Flang][OpenMP][MLIR] Extend derived (record) type map support in Flang OpenMP by adding some initial support for explicit member mapping (PR #81511)

[Kareem Ergawy via llvm-branch-commits]

https://github.com/ergawy edited https://github.com/llvm/llvm-project/pull/81511
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[llvm-branch-commits] [llvm] Revert "[RISCV] Recurse on first operand of two operand shuffles (#79180)" (PR #80238)

[Alex Bradbury via llvm-branch-commits]

https://github.com/asb approved this pull request.

In case it's helpful, explicit LGTM from me on backporting this.

@preames looks like you need to rebase

https://github.com/llvm/llvm-project/pull/80238
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[llvm-branch-commits] [clang] [llvm] release/18.x: [NFC][AArch64] fix whitespace in AArch64SchedNeoverseV1 (#81744) (PR #81857)

[via llvm-branch-commits]

llvmbot wrote:



@llvm/pr-subscribers-clang

@llvm/pr-subscribers-backend-aarch64

Author: None (llvmbot)


Changes

Backport a52eea66795018550e95c4b060165a7250899298 
fbba818a78f591d89f25768ba31783714d526532 
dd1897c6cb028bda7d4d541d1bb33965eccf0a68 
3369e341288b3d9bb59827f9a2911ebf3d36408d

Requested by: @ptomsich

---

Patch is 631.69 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/81857.diff


40 Files Affected:

- (modified) clang/lib/Basic/Targets/AArch64.cpp (-1) 
- (modified) clang/test/CodeGen/aarch64-targetattr.c (+5-5) 
- (modified) clang/test/Driver/aarch64-cssc.c (+1) 
- (modified) clang/test/Misc/target-invalid-cpu-note.c (+2-2) 
- (modified) clang/test/Preprocessor/aarch64-target-features.c (+21-14) 
- (modified) llvm/include/llvm/TargetParser/AArch64TargetParser.h (+7-1) 
- (modified) llvm/lib/Target/AArch64/AArch64.td (+27) 
- (modified) llvm/lib/Target/AArch64/AArch64SchedA53.td (+1-1) 
- (modified) llvm/lib/Target/AArch64/AArch64SchedA57.td (+1-1) 
- (modified) llvm/lib/Target/AArch64/AArch64SchedA64FX.td (+2-1) 
- (added) llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td (+1149) 
- (modified) llvm/lib/Target/AArch64/AArch64SchedCyclone.td (+1-1) 
- (modified) llvm/lib/Target/AArch64/AArch64SchedExynosM3.td (+1-1) 
- (modified) llvm/lib/Target/AArch64/AArch64SchedExynosM4.td (+1-1) 
- (modified) llvm/lib/Target/AArch64/AArch64SchedExynosM5.td (+1-1) 
- (modified) llvm/lib/Target/AArch64/AArch64SchedFalkor.td (+1-1) 
- (modified) llvm/lib/Target/AArch64/AArch64SchedKryo.td (+1-1) 
- (modified) llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td (+1-1) 
- (modified) llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td (+1-1) 
- (modified) llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td (+2-1) 
- (modified) llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td (+2-1) 
- (modified) llvm/lib/Target/AArch64/AArch64SchedTSV110.td (+1-1) 
- (modified) llvm/lib/Target/AArch64/AArch64SchedThunderX.td (+1-1) 
- (modified) llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td (+1-1) 
- (modified) llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td (+1-1) 
- (modified) llvm/lib/Target/AArch64/AArch64Subtarget.cpp (+1) 
- (modified) llvm/lib/Target/AArch64/AArch64Subtarget.h (+1) 
- (modified) llvm/lib/TargetParser/Host.cpp (+1) 
- (modified) llvm/test/CodeGen/AArch64/cpus.ll (+1) 
- (modified) llvm/test/CodeGen/AArch64/neon-dot-product.ll (+1) 
- (modified) llvm/test/CodeGen/AArch64/remat.ll (+1) 
- (modified) llvm/test/MC/AArch64/armv8.2a-dotprod.s (+3) 
- (modified) llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt (+1) 
- (added) llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/basic-instructions.s 
(+3724) 
- (added) llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/cssc-instructions.s 
(+76) 
- (added) llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/mte-instructions.s 
(+349) 
- (added) llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/neon-instructions.s 
(+3235) 
- (added) llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/shifted-register.s 
(+31) 
- (modified) llvm/unittests/TargetParser/Host.cpp (+3) 
- (modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+46-22) 


``diff
diff --git a/clang/lib/Basic/Targets/AArch64.cpp 
b/clang/lib/Basic/Targets/AArch64.cpp
index 336b7a5e3d727d..72270167118390 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -258,7 +258,6 @@ void AArch64TargetInfo::getTargetDefinesARMV83A(const 
LangOptions ,
 MacroBuilder ) const {
   Builder.defineMacro("__ARM_FEATURE_COMPLEX", "1");
   Builder.defineMacro("__ARM_FEATURE_JCVT", "1");
-  Builder.defineMacro("__ARM_FEATURE_PAUTH", "1");
   // Also include the Armv8.2 defines
   getTargetDefinesARMV82A(Opts, Builder);
 }
diff --git a/clang/test/CodeGen/aarch64-targetattr.c 
b/clang/test/CodeGen/aarch64-targetattr.c
index 02da18264da0a3..1a3a84a73dbad1 100644
--- a/clang/test/CodeGen/aarch64-targetattr.c
+++ b/clang/test/CodeGen/aarch64-targetattr.c
@@ -97,19 +97,19 @@ void minusarch() {}
 // CHECK: attributes #0 = { {{.*}} 
"target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
 // CHECK: attributes #1 = { {{.*}} 
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a"
 }
 // CHECK: attributes #2 = { {{.*}} 
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a"
 }
-// CHECK: attributes #3 = { {{.*}} 
"target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
 }
+// CHECK: attributes #3 = { {{.*}} 
"target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
 }
 // CHECK: attributes #4 = { {{.*}} "target-cpu"="cortex-a710" 

[llvm-branch-commits] [clang] [llvm] release/18.x: [NFC][AArch64] fix whitespace in AArch64SchedNeoverseV1 (#81744) (PR #81857)

[via llvm-branch-commits]

llvmbot wrote:

@DavidSpickett @jthackray @davemgreen @davemgreen What do you think about 
merging this PR to the release branch?

https://github.com/llvm/llvm-project/pull/81857
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[llvm-branch-commits] [clang] [llvm] release/18.x: [NFC][AArch64] fix whitespace in AArch64SchedNeoverseV1 (#81744) (PR #81857)

[via llvm-branch-commits]

https://github.com/llvmbot milestoned 
https://github.com/llvm/llvm-project/pull/81857
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[llvm-branch-commits] [openmp] release/18.x: [OpenMP] [cmake] Don't use -fno-semantic-interposition on Windows (#81113) (PR #81332)

[Joseph Huber via llvm-branch-commits]

jhuber6 wrote:

Sure, LG

https://github.com/llvm/llvm-project/pull/81332
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[llvm-branch-commits] [openmp] release/18.x: [OpenMP] [cmake] Don't use -fno-semantic-interposition on Windows (#81113) (PR #81332)

[Martin Storsjö via llvm-branch-commits]

mstorsjo wrote:

Ping @jhuber6, can you ack this backport?

https://github.com/llvm/llvm-project/pull/81332
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[llvm-branch-commits] [AArch64][GlobalISel] Improve codegen for G_VECREDUCE_{SMIN, SMAX, UMIN, UMAX} for odd-sized vectors (PR #81831)

[Dhruv Chawla via llvm-branch-commits]

@@ -1070,6 +1070,13 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const 
AArch64Subtarget )
  {s16, v8s16},
  {s32, v2s32},
  {s32, v4s32}})
+  .moreElementsIf(

dc03-work wrote:

As I noted in my commit message, unfortunately that causes regressions for 
odd-sized `i8` vectors: 
https://gist.github.com/dc03-work/3d749a7be0dc893d86d2df0fbc31709a (except for 
the very last case... for some reason). I was noticing another test failure 
when I enabled it for even-sized vectors, however that seems to have gone away 
now.

https://github.com/llvm/llvm-project/pull/81831
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[llvm-branch-commits] [AArch64][GlobalISel] Improve codegen for G_VECREDUCE_{SMIN, SMAX, UMIN, UMAX} for odd-sized vectors (PR #81831)

[David Green via llvm-branch-commits]

@@ -1070,6 +1070,13 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const 
AArch64Subtarget )
  {s16, v8s16},
  {s32, v2s32},
  {s32, v4s32}})
+  .moreElementsIf(

davemgreen wrote:

I think this can happen for more than just odd numbers, if we have support in 
the legalizer. I think I would make it moreElementsToNextPow2 unless there is a 
big reason not to.

https://github.com/llvm/llvm-project/pull/81831
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[llvm-branch-commits] [clang] [analyzer][docs] Admit that the cleanup attribute is not supported (PR #81834)

[Balazs Benics via llvm-branch-commits]

https://github.com/steakhal milestoned 
https://github.com/llvm/llvm-project/pull/81834
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[llvm-branch-commits] [clang] [analyzer][docs] Admit that the cleanup attribute is not supported (PR #81834)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-clang

Author: Balazs Benics (steakhal)


Changes

In fact, the cleanup attribute is only added to the CFG, but still unhandled by 
CSA.
I propose dropping this false "support" statement from the docs.

---
Full diff: https://github.com/llvm/llvm-project/pull/81834.diff


1 Files Affected:

- (modified) clang/docs/ReleaseNotes.rst (-3) 


``diff
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 95d44951ae7ee6..b4cbe18aa150a9 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1343,9 +1343,6 @@ New features
   of static analysis tools, such as the Clang Static Analyzer.
   `Documentation 
`__.
 
-- Added support for the ``cleanup`` attribute.
-  `Documentation 
`__.
-
 - Support "Deducing this" (P0847R7). (Worked out of the box)
   (`af4751738db8 
`__)
 

``




https://github.com/llvm/llvm-project/pull/81834
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[llvm-branch-commits] [clang] [analyzer][docs] Admit that the cleanup attribute is not supported (PR #81834)

[Balazs Benics via llvm-branch-commits]

https://github.com/steakhal created 
https://github.com/llvm/llvm-project/pull/81834

In fact, the cleanup attribute is only added to the CFG, but still unhandled by 
CSA.
I propose dropping this false "support" statement from the docs.

>From 9676ef916e3617e879bb3f498472754031b3310b Mon Sep 17 00:00:00 2001
From: Balazs Benics 
Date: Thu, 15 Feb 2024 09:33:07 +0100
Subject: [PATCH] [analyzer][docs] Admit that the cleanup attribute is not
 supported

In fact, the cleanup attribute is only added to the CFG, but still
unhandled by CSA.
I propose dropping this false "support" statement from the docs.
---
 clang/docs/ReleaseNotes.rst | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 95d44951ae7ee6..b4cbe18aa150a9 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1343,9 +1343,6 @@ New features
   of static analysis tools, such as the Clang Static Analyzer.
   `Documentation 
`__.
 
-- Added support for the ``cleanup`` attribute.
-  `Documentation 
`__.
-
 - Support "Deducing this" (P0847R7). (Worked out of the box)
   (`af4751738db8 
`__)
 

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[llvm-branch-commits] [llvm] Use container on Linux to run llvm-project-tests workflow (#81349) (PR #81807)

[Nikita Popov via llvm-branch-commits]

https://github.com/nikic milestoned 
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[llvm-branch-commits] [llvm] Backport ARM64EC variadic args fixes to LLVM 18 (PR #81800)

[Nikita Popov via llvm-branch-commits]

https://github.com/nikic milestoned 
https://github.com/llvm/llvm-project/pull/81800
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[llvm-branch-commits] [llvm] [asan] isInterestingAlloca: remove the isAllocaPromotable condition (PR #77221)

[Fangrui Song via llvm-branch-commits]

https://github.com/MaskRay updated 
https://github.com/llvm/llvm-project/pull/77221

>From 46d21cd0327e352491be77bb86740167984c0209 Mon Sep 17 00:00:00 2001
From: Fangrui Song 
Date: Wed, 14 Feb 2024 23:26:34 -0800
Subject: [PATCH 1/2] fix cl::desc

Created using spr 1.3.4
---
 llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp 
b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
index 2e8d9bd748df82..029c07636d1784 100644
--- a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
@@ -347,7 +347,7 @@ static cl::opt
 
 static cl::opt ClInstrumentUninterestingAllocas(
 "asan-instrument-uninteresting-allocas",
-cl::desc("Do not instrument uninteresting allocas"), cl::Hidden);
+cl::desc("Instrument uninteresting allocas"), cl::Hidden);
 
 static cl::opt ClConstructorKind(
 "asan-constructor-kind",

>From c2eaeada2ce0d4d59810c497eda8e9c0d8a417c7 Mon Sep 17 00:00:00 2001
From: Fangrui Song 
Date: Thu, 15 Feb 2024 00:25:03 -0800
Subject: [PATCH 2/2] revert an undeeded  clang-format after restoring the
 original version of the patch

Created using spr 1.3.4
---
 llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp 
b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
index a115a8967dcb7d..4c29e02ea0df38 100644
--- a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
@@ -346,7 +346,8 @@ static cl::opt
cl::Hidden, cl::init(true));
 
 static cl::opt ClConstructorKind(
-"asan-constructor-kind", cl::desc("Sets the ASan constructor kind"),
+"asan-constructor-kind",
+cl::desc("Sets the ASan constructor kind"),
 cl::values(clEnumValN(AsanCtorKind::None, "none", "No constructors"),
clEnumValN(AsanCtorKind::Global, "global",
   "Use global constructors")),

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[llvm-branch-commits] [llvm] [asan] isInterestingAlloca: remove the isAllocaPromotable condition (PR #77221)

[Fangrui Song via llvm-branch-commits]

https://github.com/MaskRay updated 
https://github.com/llvm/llvm-project/pull/77221

>From 46d21cd0327e352491be77bb86740167984c0209 Mon Sep 17 00:00:00 2001
From: Fangrui Song 
Date: Wed, 14 Feb 2024 23:26:34 -0800
Subject: [PATCH] fix cl::desc

Created using spr 1.3.4
---
 llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp 
b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
index 2e8d9bd748df82..029c07636d1784 100644
--- a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
@@ -347,7 +347,7 @@ static cl::opt
 
 static cl::opt ClInstrumentUninterestingAllocas(
 "asan-instrument-uninteresting-allocas",
-cl::desc("Do not instrument uninteresting allocas"), cl::Hidden);
+cl::desc("Instrument uninteresting allocas"), cl::Hidden);
 
 static cl::opt ClConstructorKind(
 "asan-constructor-kind",

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[llvm-branch-commits] [llvm] [asan] isInterestingAlloca: remove the isAllocaPromotable condition (PR #77221)

[Fangrui Song via llvm-branch-commits]

https://github.com/MaskRay edited 
https://github.com/llvm/llvm-project/pull/77221
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[llvm-branch-commits] [llvm] [asan] isInterestingAlloca: remove the isAllocaPromotable condition (PR #77221)

[Fangrui Song via llvm-branch-commits]

https://github.com/MaskRay updated 
https://github.com/llvm/llvm-project/pull/77221

>From 46d21cd0327e352491be77bb86740167984c0209 Mon Sep 17 00:00:00 2001
From: Fangrui Song 
Date: Wed, 14 Feb 2024 23:26:34 -0800
Subject: [PATCH] fix cl::desc

Created using spr 1.3.4
---
 llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp 
b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
index 2e8d9bd748df82..029c07636d1784 100644
--- a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
@@ -347,7 +347,7 @@ static cl::opt
 
 static cl::opt ClInstrumentUninterestingAllocas(
 "asan-instrument-uninteresting-allocas",
-cl::desc("Do not instrument uninteresting allocas"), cl::Hidden);
+cl::desc("Instrument uninteresting allocas"), cl::Hidden);
 
 static cl::opt ClConstructorKind(
 "asan-constructor-kind",

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[llvm-branch-commits] [llvm] [asan] isInterestingAlloca: remove the isAllocaPromotable condition (PR #77221)

[Fangrui Song via llvm-branch-commits]

https://github.com/MaskRay edited 
https://github.com/llvm/llvm-project/pull/77221
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[llvm-branch-commits] [llvm] [asan] isInterestingAlloca: remove the isAllocaPromotable condition (PR #77221)

[Fangrui Song via llvm-branch-commits]

@@ -1279,9 +1278,6 @@ bool AddressSanitizer::isInterestingAlloca(const 
AllocaInst ) {
   (AI.getAllocatedType()->isSized() &&

MaskRay wrote:

In `ClInstrumentUninterestingAllocas=0 mode`, `!(SSGI && SSGI->isSafe(AI))` can 
ignore some `AllocaInst`s that `SSGI->stackAccessIsSafe(*Inst)` will return 
false.

My original thought is that `ClInstrumentUninterestingAllocas` isn't useful and 
we should just remove it.

If you think `ClInstrumentUninterestingAllocas` is unnecessary, I will remove 
it.

https://github.com/llvm/llvm-project/pull/77221
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[llvm-branch-commits] [ELF] Support placing .lbss/.lrodata/.ldata after .bss (PR #81224)

[Fangrui Song via llvm-branch-commits]

https://github.com/MaskRay updated 
https://github.com/llvm/llvm-project/pull/81224


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[llvm-branch-commits] [ELF] Support placing .lbss/.lrodata/.ldata after .bss (PR #81224)

[Fangrui Song via llvm-branch-commits]

https://github.com/MaskRay edited 
https://github.com/llvm/llvm-project/pull/81224
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[llvm-branch-commits] [ELF] Support placing .lbss/.lrodata/.ldata after .bss (PR #81224)

[Fangrui Song via llvm-branch-commits]

https://github.com/MaskRay updated 
https://github.com/llvm/llvm-project/pull/81224


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