[llvm-branch-commits] [llvm] release/18.x: Prepend all library intrinsics with `#` when building for Arm64EC (PR #88016)

[Daniel Paoliello via llvm-branch-commits]

dpaoliello wrote:

> Hi @dpaoliello I'm seeing some "Illegal Instruction" errors when running the 
> bolt tests on aarch64. Do you think there is any chance this commit could be 
> the cause? It's the only one between 18.1.3 and 18.1.4 that touches the 
> aarch64 code gen. Here is the full log:
> 
> https://kojipkgs.fedoraproject.org//work/tasks/3490/117353490/build.log

@tstellar I wouldn't think so: the code path being changed here is guarded by a 
check for the Arm64EC subtarget on Windows, so it should never be triggered 
when building for AArch64 Linux. Additionally, if somehow this code was 
triggered, it should only result in different names for intrinsics (leading to 
unresolved symbols) rather than any change to which instruction is emitted.

https://github.com/llvm/llvm-project/pull/88016
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[llvm-branch-commits] [llvm] [release/18.x] Backport fixes for ARM64EC thunk generation (PR #92580)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello milestoned 
https://github.com/llvm/llvm-project/pull/92580
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[llvm-branch-commits] [llvm] [release/18.x] Backport fixes for ARM64EC thunk generation (PR #92580)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello created 
https://github.com/llvm/llvm-project/pull/92580

Backports !90115 and !92326

Release notes:
Fixes issues where LLVM is either generating the incorrect thunk for a function 
with aligned parameters or didn't correctly pass through the return value when 
`StructRet` was used.

>From 5e0477fafd6aa8ea8451a7ea4968f407ca893aef Mon Sep 17 00:00:00 2001
From: Eli Friedman 
Date: Fri, 26 Apr 2024 11:06:11 -0700
Subject: [PATCH 1/2] [Arm64EC] Improve alignment mangling in arm64ec thunks.
 (#90115)

In some cases, MSVC's mangling for arm64ec thunks includes the alignment
of a struct. I added some code to try to match... but it never really
worked right. The issues:

- Alignment is only mangled if it's 16 or more (I guess the default is
supposed to be 8).
- Alignment isn't mangled on return values (since the memory is
allocated by the caller).

The current patch leaves hooks to make alignment mangling work... but
doesn't actually ever mangle alignment: clang never actually encodes a
relevant alignment into the IR. Once we get clang to emit the real
size/alignment of structs, we can start emitting it.
---
 llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp |  7 ---
 llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll  |  6 +++---
 llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll   | 10 +-
 3 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp 
b/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
index 55c5bbc66a3f4..d4dd28aecac48 100644
--- a/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
@@ -181,13 +181,14 @@ void AArch64Arm64ECCallLowering::getThunkArgTypes(
   }
 
   for (unsigned E = FT->getNumParams(); I != E; ++I) {
-Align ParamAlign = AttrList.getParamAlignment(I).valueOrOne();
 #if 0
 // FIXME: Need more information about argument size; see
 // https://reviews.llvm.org/D132926
 uint64_t ArgSizeBytes = AttrList.getParamArm64ECArgSizeBytes(I);
+Align ParamAlign = AttrList.getParamAlignment(I).valueOrOne();
 #else
 uint64_t ArgSizeBytes = 0;
+Align ParamAlign = Align();
 #endif
 Type *Arm64Ty, *X64Ty;
 canonicalizeThunkType(FT->getParamType(I), ParamAlign,
@@ -297,7 +298,7 @@ void AArch64Arm64ECCallLowering::canonicalizeThunkType(
 uint64_t TotalSizeBytes = ElementCnt * ElementSizePerBytes;
 if (ElementTy->isFloatTy() || ElementTy->isDoubleTy()) {
   Out << (ElementTy->isFloatTy() ? "F" : "D") << TotalSizeBytes;
-  if (Alignment.value() >= 8 && !T->isPointerTy())
+  if (Alignment.value() >= 16 && !Ret)
 Out << "a" << Alignment.value();
   Arm64Ty = T;
   if (TotalSizeBytes <= 8) {
@@ -328,7 +329,7 @@ void AArch64Arm64ECCallLowering::canonicalizeThunkType(
   Out << "m";
   if (TypeSize != 4)
 Out << TypeSize;
-  if (Alignment.value() >= 8 && !T->isPointerTy())
+  if (Alignment.value() >= 16 && !Ret)
 Out << "a" << Alignment.value();
   // FIXME: Try to canonicalize Arm64Ty more thoroughly?
   Arm64Ty = T;
diff --git a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll 
b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
index bb9ba05f7a272..c00c9bfe127e8 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
@@ -223,8 +223,8 @@ define i8 @matches_has_sret() nounwind {
 
 %TSRet = type { i64, i64 }
 define void @has_aligned_sret(ptr align 32 sret(%TSRet)) nounwind {
-; CHECK-LABEL:.def$ientry_thunk$cdecl$m16a32$v;
-; CHECK:  .section
.wowthk$aa,"xr",discard,$ientry_thunk$cdecl$m16a32$v
+; CHECK-LABEL:.def$ientry_thunk$cdecl$m16$v;
+; CHECK:  .section
.wowthk$aa,"xr",discard,$ientry_thunk$cdecl$m16$v
 ; CHECK:  // %bb.0:
 ; CHECK-NEXT: stp q6, q7, [sp, #-176]!// 32-byte Folded 
Spill
 ; CHECK-NEXT: .seh_save_any_reg_pxq6, 176
@@ -457,7 +457,7 @@ define %T2 @simple_struct(%T1 %0, %T2 %1, %T3, %T4) 
nounwind {
 ; CHECK-NEXT: .symidx $ientry_thunk$cdecl$i8$v
 ; CHECK-NEXT: .word   1
 ; CHECK-NEXT: .symidx "#has_aligned_sret"
-; CHECK-NEXT: .symidx $ientry_thunk$cdecl$m16a32$v
+; CHECK-NEXT: .symidx $ientry_thunk$cdecl$m16$v
 ; CHECK-NEXT: .word   1
 ; CHECK-NEXT: .symidx "#small_array"
 ; CHECK-NEXT: .symidx $ientry_thunk$cdecl$m2$m2F8
diff --git a/llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll 
b/llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
index 3b911e78aff2a..7a40fcd85ac58 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
@@ -236,8 +236,8 @@ declare void @has_sret(ptr sret([100 x i8])) nounwind;
 
 %TSRet = type { i64, i64 }
 declare void @has_aligned_sret(ptr align 32 sret(%TSRet)) nounwind;
-; CHECK-LABEL:.def$iexit_thunk$cdecl$m16a32$v;
-; CHECK:  .section
.wowthk$a

[llvm-branch-commits] [llvm] [release/18.x] Backport fixes for ARM64EC thunk generation (PR #92580)

[Daniel Paoliello via llvm-branch-commits]

dpaoliello wrote:

> @dpaoliello (or anyone else). If you would like to add a note about this fix 
> in the release notes (completely optional). Please reply to this comment with 
> a one or two sentence description of the fix. When you are done, please add 
> the release:note label to this PR.

Fixes issues where LLVM is either generating the incorrect thunk for a function 
with aligned parameters or didn't correctly pass through the return value when 
`StructRet` was used.

https://github.com/llvm/llvm-project/pull/92580
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[llvm-branch-commits] [llvm] CodeGen: Move current call site out of MachineModuleInfo (PR #100369)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello requested changes to this pull request.


https://github.com/llvm/llvm-project/pull/100369
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[llvm-branch-commits] [llvm] CodeGen: Move current call site out of MachineModuleInfo (PR #100369)

[Daniel Paoliello via llvm-branch-commits]

@@ -183,11 +183,28 @@ class FunctionLoweringInfo {
   std::vector > PHINodesToUpdate;
   unsigned OrigNumPHINodesToUpdate;
 
+  /// \name Exception Handling

dpaoliello wrote:

I don't think we need to keep this

https://github.com/llvm/llvm-project/pull/100369
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[llvm-branch-commits] [llvm] CodeGen: Move current call site out of MachineModuleInfo (PR #100369)

[Daniel Paoliello via llvm-branch-commits]

@@ -183,11 +183,28 @@ class FunctionLoweringInfo {
   std::vector > PHINodesToUpdate;
   unsigned OrigNumPHINodesToUpdate;
 
+  /// \name Exception Handling
+  /// \{
+
   /// If the current MBB is a landing pad, the exception pointer and exception
   /// selector registers are copied into these virtual registers by
   /// SelectionDAGISel::PrepareEHLandingPad().
   unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg;
 
+  /// The current call site index being processed, if any. 0 if none.
+  unsigned CurCallSite = 0;
+  // TODO: Ideally, what we'd like is to have a switch that allows emitting
+  // synchronous (precise at call-sites only) CFA into .eh_frame. However,
+  // even under this switch, we'd like .debug_frame to be precise when using
+  // -g. At this moment, there's no way to specify that some CFI directives
+  // go into .eh_frame only, while others go into .debug_frame only.
+
+  /// Set the call site currently being processed.
+  void setCurrentCallSite(unsigned Site) { CurCallSite = Site; }

dpaoliello wrote:

Please move these down next to the rest of the functions

https://github.com/llvm/llvm-project/pull/100369
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[llvm-branch-commits] [llvm] CodeGen: Move current call site out of MachineModuleInfo (PR #100369)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello approved this pull request.


https://github.com/llvm/llvm-project/pull/100369
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[llvm-branch-commits] [llvm] Backport ARM64EC variadic args fixes to LLVM 18 (PR #81800)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello created 
https://github.com/llvm/llvm-project/pull/81800

Backports two fixes for ARM64EC variadic args:
* 
* 

>From 45fbf96034992f7e5e1e6678bfb2988c58a9c0ae Mon Sep 17 00:00:00 2001
From: Billy Laws 
Date: Wed, 31 Jan 2024 02:32:15 +
Subject: [PATCH 1/2] [AArch64] Fix variadic tail-calls on ARM64EC (#79774)

ARM64EC varargs calls expect that x4 = sp at entry, special handling is
needed to ensure this with tail calls since they occur after the
epilogue and the x4 write happens before.

I tried going through AArch64MachineFrameLowering for this, hoping to
avoid creating the dummy object but this was the best I could do since
the stack info that uses isn't populated at this stage,
CreateFixedObject also explicitly forbids 0 sized objects.
---
 .../Target/AArch64/AArch64ISelLowering.cpp| 10 -
 llvm/test/CodeGen/AArch64/arm64ec-varargs.ll  | 37 +++
 llvm/test/CodeGen/AArch64/vararg-tallcall.ll  |  8 
 3 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp 
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index e97f5e32201488..957b556edaf312 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -8007,11 +8007,19 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
   }
 
   if (IsVarArg && Subtarget->isWindowsArm64EC()) {
+SDValue ParamPtr = StackPtr;
+if (IsTailCall) {
+  // Create a dummy object at the top of the stack that can be used to get
+  // the SP after the epilogue
+  int FI = MF.getFrameInfo().CreateFixedObject(1, FPDiff, true);
+  ParamPtr = DAG.getFrameIndex(FI, PtrVT);
+}
+
 // For vararg calls, the Arm64EC ABI requires values in x4 and x5
 // describing the argument list.  x4 contains the address of the
 // first stack parameter. x5 contains the size in bytes of all parameters
 // passed on the stack.
-RegsToPass.emplace_back(AArch64::X4, StackPtr);
+RegsToPass.emplace_back(AArch64::X4, ParamPtr);
 RegsToPass.emplace_back(AArch64::X5,
 DAG.getConstant(NumBytes, DL, MVT::i64));
   }
diff --git a/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll 
b/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
index dc16b3a1a0f270..844fc52ddade63 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
@@ -100,5 +100,42 @@ define void @varargs_many_argscalleer() nounwind {
   ret void
 }
 
+define void @varargs_caller_tail() nounwind {
+; CHECK-LABEL: varargs_caller_tail:
+; CHECK:// %bb.0:
+; CHECK-NEXT:sub sp, sp, #48
+; CHECK-NEXT:mov x4, sp
+; CHECK-NEXT:add x8, sp, #16
+; CHECK-NEXT:mov x9, #4617315517961601024// 
=0x4014
+; CHECK-NEXT:mov x0, #4607182418800017408// 
=0x3ff0
+; CHECK-NEXT:mov w1, #2  // =0x2
+; CHECK-NEXT:mov x2, #4613937818241073152// 
=0x4008
+; CHECK-NEXT:mov w3, #4  // =0x4
+; CHECK-NEXT:mov w5, #16 // =0x10
+; CHECK-NEXT:stp xzr, x30, [sp, #24] // 8-byte Folded 
Spill
+; CHECK-NEXT:stp x9, x8, [sp]
+; CHECK-NEXT:str xzr, [sp, #16]
+; CHECK-NEXT:.weak_anti_dep  varargs_callee
+; CHECK-NEXT:.set varargs_callee, "#varargs_callee"@WEAKREF
+; CHECK-NEXT:.weak_anti_dep  "#varargs_callee"
+; CHECK-NEXT:.set "#varargs_callee", varargs_callee@WEAKREF
+; CHECK-NEXT:bl  "#varargs_callee"
+; CHECK-NEXT:ldr x30, [sp, #32]  // 8-byte Folded 
Reload
+; CHECK-NEXT:add x4, sp, #48
+; CHECK-NEXT:mov x0, #4607182418800017408// 
=0x3ff0
+; CHECK-NEXT:mov w1, #4  // =0x4
+; CHECK-NEXT:mov w2, #3  // =0x3
+; CHECK-NEXT:mov w3, #2  // =0x2
+; CHECK-NEXT:mov x5, xzr
+; CHECK-NEXT:add sp, sp, #48
+; CHECK-NEXT:.weak_anti_dep  varargs_callee
+; CHECK-NEXT:.set varargs_callee, "#varargs_callee"@WEAKREF
+; CHECK-NEXT:.weak_anti_dep  "#varargs_callee"
+; CHECK-NEXT:.set "#varargs_callee", varargs_callee@WEAKREF
+; CHECK-NEXT:b   "#varargs_callee"
+  call void (double, ...) @varargs_callee(double 1.0, i32 2, double 3.0, i32 
4, double 5.0, <2 x double> )
+  tail call void (double, ...) @varargs_callee(double 1.0, i32 4, i32 3, i32 2)
+  ret void
+}
 
 declare void @llvm.va_start(ptr)
diff --git a/llvm/test/CodeGen/AArch64/vararg-tallcall.ll 
b/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
index 2d6db1642247d7..812837639196e6 100644
--- a/llvm/test/CodeGen/AArch6

[llvm-branch-commits] [llvm] PR for llvm/llvm-project#80752 (PR #80754)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello closed 
https://github.com/llvm/llvm-project/pull/80754
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[llvm-branch-commits] [llvm] PR for llvm/llvm-project#80752 (PR #80754)

[Daniel Paoliello via llvm-branch-commits]

dpaoliello wrote:

Superseded by https://github.com/llvm/llvm-project/pull/81800

https://github.com/llvm/llvm-project/pull/80754
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[llvm-branch-commits] [llvm] Backport ARM64EC variadic args fixes to LLVM 18 (PR #81800)

[Daniel Paoliello via llvm-branch-commits]

dpaoliello wrote:

> I was sort of waiting until the discussion on #80994 resolves... we might end 
> up reverting parts of #80595 .
> 
> I guess it won't do any harm to land as-is, though.

I'll wait - I'd rather not drop something into the release branch if we know it 
may cause issues.

https://github.com/llvm/llvm-project/pull/81800
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[llvm-branch-commits] [llvm] Backport ARM64EC variadic args fixes to LLVM 18 (PR #81800)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello updated 
https://github.com/llvm/llvm-project/pull/81800

>From 10ed6a8e268c296901093f90bae4018faf90d27d Mon Sep 17 00:00:00 2001
From: Billy Laws 
Date: Wed, 31 Jan 2024 02:32:15 +
Subject: [PATCH 1/3] [AArch64] Fix variadic tail-calls on ARM64EC (#79774)

ARM64EC varargs calls expect that x4 = sp at entry, special handling is
needed to ensure this with tail calls since they occur after the
epilogue and the x4 write happens before.

I tried going through AArch64MachineFrameLowering for this, hoping to
avoid creating the dummy object but this was the best I could do since
the stack info that uses isn't populated at this stage,
CreateFixedObject also explicitly forbids 0 sized objects.
---
 .../Target/AArch64/AArch64ISelLowering.cpp| 10 -
 llvm/test/CodeGen/AArch64/arm64ec-varargs.ll  | 37 +++
 llvm/test/CodeGen/AArch64/vararg-tallcall.ll  |  8 
 3 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp 
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 0287856560e91a..196aa50cf4060b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -8007,11 +8007,19 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
   }
 
   if (IsVarArg && Subtarget->isWindowsArm64EC()) {
+SDValue ParamPtr = StackPtr;
+if (IsTailCall) {
+  // Create a dummy object at the top of the stack that can be used to get
+  // the SP after the epilogue
+  int FI = MF.getFrameInfo().CreateFixedObject(1, FPDiff, true);
+  ParamPtr = DAG.getFrameIndex(FI, PtrVT);
+}
+
 // For vararg calls, the Arm64EC ABI requires values in x4 and x5
 // describing the argument list.  x4 contains the address of the
 // first stack parameter. x5 contains the size in bytes of all parameters
 // passed on the stack.
-RegsToPass.emplace_back(AArch64::X4, StackPtr);
+RegsToPass.emplace_back(AArch64::X4, ParamPtr);
 RegsToPass.emplace_back(AArch64::X5,
 DAG.getConstant(NumBytes, DL, MVT::i64));
   }
diff --git a/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll 
b/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
index dc16b3a1a0f270..844fc52ddade63 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
@@ -100,5 +100,42 @@ define void @varargs_many_argscalleer() nounwind {
   ret void
 }
 
+define void @varargs_caller_tail() nounwind {
+; CHECK-LABEL: varargs_caller_tail:
+; CHECK:// %bb.0:
+; CHECK-NEXT:sub sp, sp, #48
+; CHECK-NEXT:mov x4, sp
+; CHECK-NEXT:add x8, sp, #16
+; CHECK-NEXT:mov x9, #4617315517961601024// 
=0x4014
+; CHECK-NEXT:mov x0, #4607182418800017408// 
=0x3ff0
+; CHECK-NEXT:mov w1, #2  // =0x2
+; CHECK-NEXT:mov x2, #4613937818241073152// 
=0x4008
+; CHECK-NEXT:mov w3, #4  // =0x4
+; CHECK-NEXT:mov w5, #16 // =0x10
+; CHECK-NEXT:stp xzr, x30, [sp, #24] // 8-byte Folded 
Spill
+; CHECK-NEXT:stp x9, x8, [sp]
+; CHECK-NEXT:str xzr, [sp, #16]
+; CHECK-NEXT:.weak_anti_dep  varargs_callee
+; CHECK-NEXT:.set varargs_callee, "#varargs_callee"@WEAKREF
+; CHECK-NEXT:.weak_anti_dep  "#varargs_callee"
+; CHECK-NEXT:.set "#varargs_callee", varargs_callee@WEAKREF
+; CHECK-NEXT:bl  "#varargs_callee"
+; CHECK-NEXT:ldr x30, [sp, #32]  // 8-byte Folded 
Reload
+; CHECK-NEXT:add x4, sp, #48
+; CHECK-NEXT:mov x0, #4607182418800017408// 
=0x3ff0
+; CHECK-NEXT:mov w1, #4  // =0x4
+; CHECK-NEXT:mov w2, #3  // =0x3
+; CHECK-NEXT:mov w3, #2  // =0x2
+; CHECK-NEXT:mov x5, xzr
+; CHECK-NEXT:add sp, sp, #48
+; CHECK-NEXT:.weak_anti_dep  varargs_callee
+; CHECK-NEXT:.set varargs_callee, "#varargs_callee"@WEAKREF
+; CHECK-NEXT:.weak_anti_dep  "#varargs_callee"
+; CHECK-NEXT:.set "#varargs_callee", varargs_callee@WEAKREF
+; CHECK-NEXT:b   "#varargs_callee"
+  call void (double, ...) @varargs_callee(double 1.0, i32 2, double 3.0, i32 
4, double 5.0, <2 x double> )
+  tail call void (double, ...) @varargs_callee(double 1.0, i32 4, i32 3, i32 2)
+  ret void
+}
 
 declare void @llvm.va_start(ptr)
diff --git a/llvm/test/CodeGen/AArch64/vararg-tallcall.ll 
b/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
index 2d6db1642247d7..812837639196e6 100644
--- a/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
+++ b/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
@@ -1,5 +1,6 @@
 ; RUN: llc -mtriple=aarch64-windows-msvc %s -o - | FileCheck %s

[llvm-branch-commits] [llvm] Backport ARM64EC variadic args fixes to LLVM 18 (PR #81800)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello edited 
https://github.com/llvm/llvm-project/pull/81800
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[llvm-branch-commits] [llvm] Backport ARM64EC variadic args fixes to LLVM 18 (PR #81800)

[Daniel Paoliello via llvm-branch-commits]

dpaoliello wrote:

@efriedma-quic I think this is ready to land, the MacOS test failure is a known 
issue.

https://github.com/llvm/llvm-project/pull/81800
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[llvm-branch-commits] [llvm] Backport ARM64EC variadic args fixes to LLVM 18 (PR #81800)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello updated 
https://github.com/llvm/llvm-project/pull/81800

>From 064dd621c19b3738af5db29afd5b986a6d739ab1 Mon Sep 17 00:00:00 2001
From: Billy Laws 
Date: Wed, 31 Jan 2024 02:32:15 +
Subject: [PATCH 1/3] [AArch64] Fix variadic tail-calls on ARM64EC (#79774)

ARM64EC varargs calls expect that x4 = sp at entry, special handling is
needed to ensure this with tail calls since they occur after the
epilogue and the x4 write happens before.

I tried going through AArch64MachineFrameLowering for this, hoping to
avoid creating the dummy object but this was the best I could do since
the stack info that uses isn't populated at this stage,
CreateFixedObject also explicitly forbids 0 sized objects.
---
 .../Target/AArch64/AArch64ISelLowering.cpp| 10 -
 llvm/test/CodeGen/AArch64/arm64ec-varargs.ll  | 37 +++
 llvm/test/CodeGen/AArch64/vararg-tallcall.ll  |  8 
 3 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp 
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 0287856560e91a..196aa50cf4060b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -8007,11 +8007,19 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
   }
 
   if (IsVarArg && Subtarget->isWindowsArm64EC()) {
+SDValue ParamPtr = StackPtr;
+if (IsTailCall) {
+  // Create a dummy object at the top of the stack that can be used to get
+  // the SP after the epilogue
+  int FI = MF.getFrameInfo().CreateFixedObject(1, FPDiff, true);
+  ParamPtr = DAG.getFrameIndex(FI, PtrVT);
+}
+
 // For vararg calls, the Arm64EC ABI requires values in x4 and x5
 // describing the argument list.  x4 contains the address of the
 // first stack parameter. x5 contains the size in bytes of all parameters
 // passed on the stack.
-RegsToPass.emplace_back(AArch64::X4, StackPtr);
+RegsToPass.emplace_back(AArch64::X4, ParamPtr);
 RegsToPass.emplace_back(AArch64::X5,
 DAG.getConstant(NumBytes, DL, MVT::i64));
   }
diff --git a/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll 
b/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
index dc16b3a1a0f270..844fc52ddade63 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
@@ -100,5 +100,42 @@ define void @varargs_many_argscalleer() nounwind {
   ret void
 }
 
+define void @varargs_caller_tail() nounwind {
+; CHECK-LABEL: varargs_caller_tail:
+; CHECK:// %bb.0:
+; CHECK-NEXT:sub sp, sp, #48
+; CHECK-NEXT:mov x4, sp
+; CHECK-NEXT:add x8, sp, #16
+; CHECK-NEXT:mov x9, #4617315517961601024// 
=0x4014
+; CHECK-NEXT:mov x0, #4607182418800017408// 
=0x3ff0
+; CHECK-NEXT:mov w1, #2  // =0x2
+; CHECK-NEXT:mov x2, #4613937818241073152// 
=0x4008
+; CHECK-NEXT:mov w3, #4  // =0x4
+; CHECK-NEXT:mov w5, #16 // =0x10
+; CHECK-NEXT:stp xzr, x30, [sp, #24] // 8-byte Folded 
Spill
+; CHECK-NEXT:stp x9, x8, [sp]
+; CHECK-NEXT:str xzr, [sp, #16]
+; CHECK-NEXT:.weak_anti_dep  varargs_callee
+; CHECK-NEXT:.set varargs_callee, "#varargs_callee"@WEAKREF
+; CHECK-NEXT:.weak_anti_dep  "#varargs_callee"
+; CHECK-NEXT:.set "#varargs_callee", varargs_callee@WEAKREF
+; CHECK-NEXT:bl  "#varargs_callee"
+; CHECK-NEXT:ldr x30, [sp, #32]  // 8-byte Folded 
Reload
+; CHECK-NEXT:add x4, sp, #48
+; CHECK-NEXT:mov x0, #4607182418800017408// 
=0x3ff0
+; CHECK-NEXT:mov w1, #4  // =0x4
+; CHECK-NEXT:mov w2, #3  // =0x3
+; CHECK-NEXT:mov w3, #2  // =0x2
+; CHECK-NEXT:mov x5, xzr
+; CHECK-NEXT:add sp, sp, #48
+; CHECK-NEXT:.weak_anti_dep  varargs_callee
+; CHECK-NEXT:.set varargs_callee, "#varargs_callee"@WEAKREF
+; CHECK-NEXT:.weak_anti_dep  "#varargs_callee"
+; CHECK-NEXT:.set "#varargs_callee", varargs_callee@WEAKREF
+; CHECK-NEXT:b   "#varargs_callee"
+  call void (double, ...) @varargs_callee(double 1.0, i32 2, double 3.0, i32 
4, double 5.0, <2 x double> )
+  tail call void (double, ...) @varargs_callee(double 1.0, i32 4, i32 3, i32 2)
+  ret void
+}
 
 declare void @llvm.va_start(ptr)
diff --git a/llvm/test/CodeGen/AArch64/vararg-tallcall.ll 
b/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
index 2d6db1642247d7..812837639196e6 100644
--- a/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
+++ b/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
@@ -1,5 +1,6 @@
 ; RUN: llc -mtriple=aarch64-windows-msvc %s -o - | FileCheck %s

[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello created 
https://github.com/llvm/llvm-project/pull/84590

Backports fixes to be able to generate import libraries for ARM64EC:
* 
* 
* 

>From 8f5a8fc5340687eb6ea943ec8460de56d141ede9 Mon Sep 17 00:00:00 2001
From: Jacek Caban 
Date: Tue, 6 Feb 2024 13:47:58 +0100
Subject: [PATCH 1/3] [llvm-readobj][Object][COFF] Print COFF import library
 symbol export name. (#78769)

getExportName implementation is based on lld-link. In its current form,
it's mostly about convenience, but it will be more useful for EXPORTAS
support, for which export name is not possible to deduce from other
printed properties.
---
 lld/test/COFF/def-export-cpp.s|  1 +
 lld/test/COFF/def-export-stdcall.s| 13 ++
 lld/test/COFF/dllexport.s |  4 +++
 llvm/include/llvm/Object/COFFImportFile.h |  1 +
 llvm/lib/Object/COFFImportFile.cpp| 26 +++
 .../tools/llvm-dlltool/coff-decorated.def |  7 +
 llvm/test/tools/llvm-dlltool/coff-exports.def |  3 +++
 llvm/test/tools/llvm-dlltool/coff-noname.def  |  1 +
 .../llvm-dlltool/no-leading-underscore.def|  2 ++
 llvm/test/tools/llvm-lib/arm64ec-implib.test  |  2 ++
 .../tools/llvm-readobj/COFF/file-headers.test |  1 +
 llvm/tools/llvm-readobj/COFFImportDumper.cpp  |  3 +++
 12 files changed, 64 insertions(+)

diff --git a/lld/test/COFF/def-export-cpp.s b/lld/test/COFF/def-export-cpp.s
index e00b35b1c5b39b..370b8ddba4104b 100644
--- a/lld/test/COFF/def-export-cpp.s
+++ b/lld/test/COFF/def-export-cpp.s
@@ -10,6 +10,7 @@
 
 # IMPLIB: File: foo.dll
 # IMPLIB: Name type: undecorate
+# IMPLIB-NEXT: Export name: GetPathOnDisk
 # IMPLIB-NEXT: Symbol: __imp_?GetPathOnDisk@@YA_NPEA_W@Z
 # IMPLIB-NEXT: Symbol: ?GetPathOnDisk@@YA_NPEA_W@Z
 
diff --git a/lld/test/COFF/def-export-stdcall.s 
b/lld/test/COFF/def-export-stdcall.s
index f015e205c74a33..7e4e04c77cbe7a 100644
--- a/lld/test/COFF/def-export-stdcall.s
+++ b/lld/test/COFF/def-export-stdcall.s
@@ -6,15 +6,19 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
UNDECORATED-EXPORTS %s
 
 # UNDECORATED-IMPLIB: Name type: noprefix
+# UNDECORATED-IMPLIB-NEXT: Export name: _underscored
 # UNDECORATED-IMPLIB-NEXT: __imp___underscored
 # UNDECORATED-IMPLIB-NEXT: __underscored
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: fastcall
 # UNDECORATED-IMPLIB-NEXT: __imp_@fastcall@8
 # UNDECORATED-IMPLIB-NEXT: fastcall@8
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: stdcall
 # UNDECORATED-IMPLIB-NEXT: __imp__stdcall@8
 # UNDECORATED-IMPLIB-NEXT: _stdcall@8
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: vectorcall
 # UNDECORATED-IMPLIB-NEXT: __imp_vectorcall@@8
 # UNDECORATED-IMPLIB-NEXT: vectorcall@@8
 
@@ -30,12 +34,15 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
DECORATED-EXPORTS %s
 
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: @fastcall@8
 # DECORATED-IMPLIB-NEXT: __imp_@fastcall@8
 # DECORATED-IMPLIB-NEXT: @fastcall@8
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: _stdcall@8
 # DECORATED-IMPLIB-NEXT: __imp__stdcall@8
 # DECORATED-IMPLIB-NEXT: _stdcall@8
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: vectorcall@@8
 # DECORATED-IMPLIB-NEXT: __imp_vectorcall@@8
 # DECORATED-IMPLIB-NEXT: vectorcall@@8
 
@@ -51,14 +58,17 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
DECORATED-MINGW-EXPORTS %s
 
 # DECORATED-MINGW-IMPLIB: Name type: name
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: @fastcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp_@fastcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: fastcall@8
 # DECORATED-MINGW-IMPLIB: Name type: noprefix
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: stdcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp__stdcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: _stdcall@8
 # GNU tools don't support vectorcall, but this test is just to track that
 # lld's behaviour remains consistent over time.
 # DECORATED-MINGW-IMPLIB: Name type: name
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: vectorcall@@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp_vectorcall@@8
 # DECORATED-MINGW-IMPLIB-NEXT: vectorcall@@8
 
@@ -75,14 +85,17 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
MINGW-KILL-AT-EXPORTS %s
 
 # MINGW-KILL-AT-IMPLIB: Name type: noprefix
+# MINGW-KILL-AT-IMPLIB: Export name: fastcall
 # MINGW-KILL-AT-IMPLIB: __imp__fastcall
 # MINGW-KILL-AT-IMPLIB-NEXT: _fastcall
 # MINGW-KILL-AT-IMPLIB: Name type: noprefix
+# MINGW-KILL-AT-IMPLIB-NEXT: Export name: stdcall
 # MINGW-KILL-AT-IMPLIB-NEXT: __imp__stdcall
 # MINGW-KILL-AT-IMPLIB-NEXT: _stdcall
 # GNU tools don't support vectorcall, but this test is just to track tha

[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

[Daniel Paoliello via llvm-branch-commits]

dpaoliello wrote:

Blocking to wait for 

https://github.com/llvm/llvm-project/pull/84590
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[llvm-branch-commits] [llvm] Backport ARM64EC variadic args fixes to LLVM 18 (PR #81800)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello updated 
https://github.com/llvm/llvm-project/pull/81800

>From a276993409f867760dbc1993acb54063fd8a0fbb Mon Sep 17 00:00:00 2001
From: Billy Laws 
Date: Wed, 31 Jan 2024 02:32:15 +
Subject: [PATCH 1/3] [AArch64] Fix variadic tail-calls on ARM64EC (#79774)

ARM64EC varargs calls expect that x4 = sp at entry, special handling is
needed to ensure this with tail calls since they occur after the
epilogue and the x4 write happens before.

I tried going through AArch64MachineFrameLowering for this, hoping to
avoid creating the dummy object but this was the best I could do since
the stack info that uses isn't populated at this stage,
CreateFixedObject also explicitly forbids 0 sized objects.
---
 .../Target/AArch64/AArch64ISelLowering.cpp| 10 -
 llvm/test/CodeGen/AArch64/arm64ec-varargs.ll  | 37 +++
 llvm/test/CodeGen/AArch64/vararg-tallcall.ll  |  8 
 3 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp 
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 0287856560e91a..196aa50cf4060b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -8007,11 +8007,19 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
   }
 
   if (IsVarArg && Subtarget->isWindowsArm64EC()) {
+SDValue ParamPtr = StackPtr;
+if (IsTailCall) {
+  // Create a dummy object at the top of the stack that can be used to get
+  // the SP after the epilogue
+  int FI = MF.getFrameInfo().CreateFixedObject(1, FPDiff, true);
+  ParamPtr = DAG.getFrameIndex(FI, PtrVT);
+}
+
 // For vararg calls, the Arm64EC ABI requires values in x4 and x5
 // describing the argument list.  x4 contains the address of the
 // first stack parameter. x5 contains the size in bytes of all parameters
 // passed on the stack.
-RegsToPass.emplace_back(AArch64::X4, StackPtr);
+RegsToPass.emplace_back(AArch64::X4, ParamPtr);
 RegsToPass.emplace_back(AArch64::X5,
 DAG.getConstant(NumBytes, DL, MVT::i64));
   }
diff --git a/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll 
b/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
index dc16b3a1a0f270..844fc52ddade63 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
@@ -100,5 +100,42 @@ define void @varargs_many_argscalleer() nounwind {
   ret void
 }
 
+define void @varargs_caller_tail() nounwind {
+; CHECK-LABEL: varargs_caller_tail:
+; CHECK:// %bb.0:
+; CHECK-NEXT:sub sp, sp, #48
+; CHECK-NEXT:mov x4, sp
+; CHECK-NEXT:add x8, sp, #16
+; CHECK-NEXT:mov x9, #4617315517961601024// 
=0x4014
+; CHECK-NEXT:mov x0, #4607182418800017408// 
=0x3ff0
+; CHECK-NEXT:mov w1, #2  // =0x2
+; CHECK-NEXT:mov x2, #4613937818241073152// 
=0x4008
+; CHECK-NEXT:mov w3, #4  // =0x4
+; CHECK-NEXT:mov w5, #16 // =0x10
+; CHECK-NEXT:stp xzr, x30, [sp, #24] // 8-byte Folded 
Spill
+; CHECK-NEXT:stp x9, x8, [sp]
+; CHECK-NEXT:str xzr, [sp, #16]
+; CHECK-NEXT:.weak_anti_dep  varargs_callee
+; CHECK-NEXT:.set varargs_callee, "#varargs_callee"@WEAKREF
+; CHECK-NEXT:.weak_anti_dep  "#varargs_callee"
+; CHECK-NEXT:.set "#varargs_callee", varargs_callee@WEAKREF
+; CHECK-NEXT:bl  "#varargs_callee"
+; CHECK-NEXT:ldr x30, [sp, #32]  // 8-byte Folded 
Reload
+; CHECK-NEXT:add x4, sp, #48
+; CHECK-NEXT:mov x0, #4607182418800017408// 
=0x3ff0
+; CHECK-NEXT:mov w1, #4  // =0x4
+; CHECK-NEXT:mov w2, #3  // =0x3
+; CHECK-NEXT:mov w3, #2  // =0x2
+; CHECK-NEXT:mov x5, xzr
+; CHECK-NEXT:add sp, sp, #48
+; CHECK-NEXT:.weak_anti_dep  varargs_callee
+; CHECK-NEXT:.set varargs_callee, "#varargs_callee"@WEAKREF
+; CHECK-NEXT:.weak_anti_dep  "#varargs_callee"
+; CHECK-NEXT:.set "#varargs_callee", varargs_callee@WEAKREF
+; CHECK-NEXT:b   "#varargs_callee"
+  call void (double, ...) @varargs_callee(double 1.0, i32 2, double 3.0, i32 
4, double 5.0, <2 x double> )
+  tail call void (double, ...) @varargs_callee(double 1.0, i32 4, i32 3, i32 2)
+  ret void
+}
 
 declare void @llvm.va_start(ptr)
diff --git a/llvm/test/CodeGen/AArch64/vararg-tallcall.ll 
b/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
index 2d6db1642247d7..812837639196e6 100644
--- a/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
+++ b/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
@@ -1,5 +1,6 @@
 ; RUN: llc -mtriple=aarch64-windows-msvc %s -o - | FileCheck %s

[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

[Daniel Paoliello via llvm-branch-commits]

dpaoliello wrote:

Sorry, I've got to disagree with this: this is blocking Rust's use of Arm64EC 
since it can generate import libraries on-the-fly using this functionality 
(rather than requiring that users install the Windows SDK).

I've tested Arm64EC with Rust, and this is the only blocking issue that I've 
found.

https://github.com/llvm/llvm-project/pull/84590
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[llvm-branch-commits] [llvm] Backport ARM64EC variadic args fixes to LLVM 18 (PR #81800)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello updated 
https://github.com/llvm/llvm-project/pull/81800

>From d7a9810f9c14e6598265ab41519be9b861228450 Mon Sep 17 00:00:00 2001
From: Billy Laws 
Date: Wed, 31 Jan 2024 02:32:15 +
Subject: [PATCH 1/3] [AArch64] Fix variadic tail-calls on ARM64EC (#79774)

ARM64EC varargs calls expect that x4 = sp at entry, special handling is
needed to ensure this with tail calls since they occur after the
epilogue and the x4 write happens before.

I tried going through AArch64MachineFrameLowering for this, hoping to
avoid creating the dummy object but this was the best I could do since
the stack info that uses isn't populated at this stage,
CreateFixedObject also explicitly forbids 0 sized objects.
---
 .../Target/AArch64/AArch64ISelLowering.cpp| 10 -
 llvm/test/CodeGen/AArch64/arm64ec-varargs.ll  | 37 +++
 llvm/test/CodeGen/AArch64/vararg-tallcall.ll  |  8 
 3 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp 
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 0287856560e91a..196aa50cf4060b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -8007,11 +8007,19 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
   }
 
   if (IsVarArg && Subtarget->isWindowsArm64EC()) {
+SDValue ParamPtr = StackPtr;
+if (IsTailCall) {
+  // Create a dummy object at the top of the stack that can be used to get
+  // the SP after the epilogue
+  int FI = MF.getFrameInfo().CreateFixedObject(1, FPDiff, true);
+  ParamPtr = DAG.getFrameIndex(FI, PtrVT);
+}
+
 // For vararg calls, the Arm64EC ABI requires values in x4 and x5
 // describing the argument list.  x4 contains the address of the
 // first stack parameter. x5 contains the size in bytes of all parameters
 // passed on the stack.
-RegsToPass.emplace_back(AArch64::X4, StackPtr);
+RegsToPass.emplace_back(AArch64::X4, ParamPtr);
 RegsToPass.emplace_back(AArch64::X5,
 DAG.getConstant(NumBytes, DL, MVT::i64));
   }
diff --git a/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll 
b/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
index dc16b3a1a0f270..844fc52ddade63 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
@@ -100,5 +100,42 @@ define void @varargs_many_argscalleer() nounwind {
   ret void
 }
 
+define void @varargs_caller_tail() nounwind {
+; CHECK-LABEL: varargs_caller_tail:
+; CHECK:// %bb.0:
+; CHECK-NEXT:sub sp, sp, #48
+; CHECK-NEXT:mov x4, sp
+; CHECK-NEXT:add x8, sp, #16
+; CHECK-NEXT:mov x9, #4617315517961601024// 
=0x4014
+; CHECK-NEXT:mov x0, #4607182418800017408// 
=0x3ff0
+; CHECK-NEXT:mov w1, #2  // =0x2
+; CHECK-NEXT:mov x2, #4613937818241073152// 
=0x4008
+; CHECK-NEXT:mov w3, #4  // =0x4
+; CHECK-NEXT:mov w5, #16 // =0x10
+; CHECK-NEXT:stp xzr, x30, [sp, #24] // 8-byte Folded 
Spill
+; CHECK-NEXT:stp x9, x8, [sp]
+; CHECK-NEXT:str xzr, [sp, #16]
+; CHECK-NEXT:.weak_anti_dep  varargs_callee
+; CHECK-NEXT:.set varargs_callee, "#varargs_callee"@WEAKREF
+; CHECK-NEXT:.weak_anti_dep  "#varargs_callee"
+; CHECK-NEXT:.set "#varargs_callee", varargs_callee@WEAKREF
+; CHECK-NEXT:bl  "#varargs_callee"
+; CHECK-NEXT:ldr x30, [sp, #32]  // 8-byte Folded 
Reload
+; CHECK-NEXT:add x4, sp, #48
+; CHECK-NEXT:mov x0, #4607182418800017408// 
=0x3ff0
+; CHECK-NEXT:mov w1, #4  // =0x4
+; CHECK-NEXT:mov w2, #3  // =0x3
+; CHECK-NEXT:mov w3, #2  // =0x2
+; CHECK-NEXT:mov x5, xzr
+; CHECK-NEXT:add sp, sp, #48
+; CHECK-NEXT:.weak_anti_dep  varargs_callee
+; CHECK-NEXT:.set varargs_callee, "#varargs_callee"@WEAKREF
+; CHECK-NEXT:.weak_anti_dep  "#varargs_callee"
+; CHECK-NEXT:.set "#varargs_callee", varargs_callee@WEAKREF
+; CHECK-NEXT:b   "#varargs_callee"
+  call void (double, ...) @varargs_callee(double 1.0, i32 2, double 3.0, i32 
4, double 5.0, <2 x double> )
+  tail call void (double, ...) @varargs_callee(double 1.0, i32 4, i32 3, i32 2)
+  ret void
+}
 
 declare void @llvm.va_start(ptr)
diff --git a/llvm/test/CodeGen/AArch64/vararg-tallcall.ll 
b/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
index 2d6db1642247d7..812837639196e6 100644
--- a/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
+++ b/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
@@ -1,5 +1,6 @@
 ; RUN: llc -mtriple=aarch64-windows-msvc %s -o - | FileCheck %s

[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

[Daniel Paoliello via llvm-branch-commits]

dpaoliello wrote:

> So your use-case is basically equivalent to using llvm-dlltool, except not 
> using the text parser?

Yep.

> If this is actually enough to make Rust targets usable, then I guess we could 
> consider it, but the fixes aren't structured in a way to make it obvious this 
> won't impact non-ARM64EC targets.

That's fair enough.

@cjacek you have more experience in this area than I do - what's your 
confidence level with backporting these changes?

https://github.com/llvm/llvm-project/pull/84590
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[llvm-branch-commits] [llvm] Backport ARM64EC variadic args fixes to LLVM 18 (PR #81800)

[Daniel Paoliello via llvm-branch-commits]

dpaoliello wrote:

@tstellar can we please get this merged into the v18 release branch?

https://github.com/llvm/llvm-project/pull/81800
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[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello updated 
https://github.com/llvm/llvm-project/pull/84590

>From e84cbe53501ae106c25ca7233e48ad3c5daf539a Mon Sep 17 00:00:00 2001
From: Jacek Caban 
Date: Tue, 6 Feb 2024 13:47:58 +0100
Subject: [PATCH 1/4] [llvm-readobj][Object][COFF] Print COFF import library
 symbol export name. (#78769)

getExportName implementation is based on lld-link. In its current form,
it's mostly about convenience, but it will be more useful for EXPORTAS
support, for which export name is not possible to deduce from other
printed properties.
---
 lld/test/COFF/def-export-cpp.s|  1 +
 lld/test/COFF/def-export-stdcall.s| 13 ++
 lld/test/COFF/dllexport.s |  4 +++
 llvm/include/llvm/Object/COFFImportFile.h |  1 +
 llvm/lib/Object/COFFImportFile.cpp| 26 +++
 .../tools/llvm-dlltool/coff-decorated.def |  7 +
 llvm/test/tools/llvm-dlltool/coff-exports.def |  3 +++
 llvm/test/tools/llvm-dlltool/coff-noname.def  |  1 +
 .../llvm-dlltool/no-leading-underscore.def|  2 ++
 llvm/test/tools/llvm-lib/arm64ec-implib.test  |  2 ++
 .../tools/llvm-readobj/COFF/file-headers.test |  1 +
 llvm/tools/llvm-readobj/COFFImportDumper.cpp  |  3 +++
 12 files changed, 64 insertions(+)

diff --git a/lld/test/COFF/def-export-cpp.s b/lld/test/COFF/def-export-cpp.s
index e00b35b1c5b39b..370b8ddba4104b 100644
--- a/lld/test/COFF/def-export-cpp.s
+++ b/lld/test/COFF/def-export-cpp.s
@@ -10,6 +10,7 @@
 
 # IMPLIB: File: foo.dll
 # IMPLIB: Name type: undecorate
+# IMPLIB-NEXT: Export name: GetPathOnDisk
 # IMPLIB-NEXT: Symbol: __imp_?GetPathOnDisk@@YA_NPEA_W@Z
 # IMPLIB-NEXT: Symbol: ?GetPathOnDisk@@YA_NPEA_W@Z
 
diff --git a/lld/test/COFF/def-export-stdcall.s 
b/lld/test/COFF/def-export-stdcall.s
index f015e205c74a33..7e4e04c77cbe7a 100644
--- a/lld/test/COFF/def-export-stdcall.s
+++ b/lld/test/COFF/def-export-stdcall.s
@@ -6,15 +6,19 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
UNDECORATED-EXPORTS %s
 
 # UNDECORATED-IMPLIB: Name type: noprefix
+# UNDECORATED-IMPLIB-NEXT: Export name: _underscored
 # UNDECORATED-IMPLIB-NEXT: __imp___underscored
 # UNDECORATED-IMPLIB-NEXT: __underscored
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: fastcall
 # UNDECORATED-IMPLIB-NEXT: __imp_@fastcall@8
 # UNDECORATED-IMPLIB-NEXT: fastcall@8
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: stdcall
 # UNDECORATED-IMPLIB-NEXT: __imp__stdcall@8
 # UNDECORATED-IMPLIB-NEXT: _stdcall@8
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: vectorcall
 # UNDECORATED-IMPLIB-NEXT: __imp_vectorcall@@8
 # UNDECORATED-IMPLIB-NEXT: vectorcall@@8
 
@@ -30,12 +34,15 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
DECORATED-EXPORTS %s
 
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: @fastcall@8
 # DECORATED-IMPLIB-NEXT: __imp_@fastcall@8
 # DECORATED-IMPLIB-NEXT: @fastcall@8
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: _stdcall@8
 # DECORATED-IMPLIB-NEXT: __imp__stdcall@8
 # DECORATED-IMPLIB-NEXT: _stdcall@8
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: vectorcall@@8
 # DECORATED-IMPLIB-NEXT: __imp_vectorcall@@8
 # DECORATED-IMPLIB-NEXT: vectorcall@@8
 
@@ -51,14 +58,17 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
DECORATED-MINGW-EXPORTS %s
 
 # DECORATED-MINGW-IMPLIB: Name type: name
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: @fastcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp_@fastcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: fastcall@8
 # DECORATED-MINGW-IMPLIB: Name type: noprefix
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: stdcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp__stdcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: _stdcall@8
 # GNU tools don't support vectorcall, but this test is just to track that
 # lld's behaviour remains consistent over time.
 # DECORATED-MINGW-IMPLIB: Name type: name
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: vectorcall@@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp_vectorcall@@8
 # DECORATED-MINGW-IMPLIB-NEXT: vectorcall@@8
 
@@ -75,14 +85,17 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
MINGW-KILL-AT-EXPORTS %s
 
 # MINGW-KILL-AT-IMPLIB: Name type: noprefix
+# MINGW-KILL-AT-IMPLIB: Export name: fastcall
 # MINGW-KILL-AT-IMPLIB: __imp__fastcall
 # MINGW-KILL-AT-IMPLIB-NEXT: _fastcall
 # MINGW-KILL-AT-IMPLIB: Name type: noprefix
+# MINGW-KILL-AT-IMPLIB-NEXT: Export name: stdcall
 # MINGW-KILL-AT-IMPLIB-NEXT: __imp__stdcall
 # MINGW-KILL-AT-IMPLIB-NEXT: _stdcall
 # GNU tools don't support vectorcall, but this test is just to track that
 # lld's behaviour remains consistent over time.
 # MINGW-KILL-AT-IMPLIB: Name type: noprefix
+# MINGW-KILL-AT-IMPLIB-NEXT: Export name: vectorcall
 # MINGW-KILL-AT-IMPLIB-NEXT: __imp__vectorcall
 # MINGW-KILL-AT-IMPLIB-NEXT

[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

[Daniel Paoliello via llvm-branch-commits]

dpaoliello wrote:

 has been merged into master 
and cherry-picked here, so this is ready to land.

> One thing we could consider is to skip .def file parser part of it. 

I'd rather not modify commits since they've already been tested in master and 
it makes subsequent cherry-picks more difficult.

https://github.com/llvm/llvm-project/pull/84590
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[llvm-branch-commits] [llvm] d7a9810 - [AArch64] Fix variadic tail-calls on ARM64EC (#79774)

[Daniel Paoliello via llvm-branch-commits]

Author: Billy Laws
Date: 2024-03-11T14:29:51-07:00
New Revision: d7a9810f9c14e6598265ab41519be9b861228450

URL: 
https://github.com/llvm/llvm-project/commit/d7a9810f9c14e6598265ab41519be9b861228450
DIFF: 
https://github.com/llvm/llvm-project/commit/d7a9810f9c14e6598265ab41519be9b861228450.diff

LOG: [AArch64] Fix variadic tail-calls on ARM64EC (#79774)

ARM64EC varargs calls expect that x4 = sp at entry, special handling is
needed to ensure this with tail calls since they occur after the
epilogue and the x4 write happens before.

I tried going through AArch64MachineFrameLowering for this, hoping to
avoid creating the dummy object but this was the best I could do since
the stack info that uses isn't populated at this stage,
CreateFixedObject also explicitly forbids 0 sized objects.

Added: 


Modified: 
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
llvm/test/CodeGen/AArch64/vararg-tallcall.ll

Removed: 




diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp 
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 0287856560e91a..196aa50cf4060b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -8007,11 +8007,19 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
   }
 
   if (IsVarArg && Subtarget->isWindowsArm64EC()) {
+SDValue ParamPtr = StackPtr;
+if (IsTailCall) {
+  // Create a dummy object at the top of the stack that can be used to get
+  // the SP after the epilogue
+  int FI = MF.getFrameInfo().CreateFixedObject(1, FPDiff, true);
+  ParamPtr = DAG.getFrameIndex(FI, PtrVT);
+}
+
 // For vararg calls, the Arm64EC ABI requires values in x4 and x5
 // describing the argument list.  x4 contains the address of the
 // first stack parameter. x5 contains the size in bytes of all parameters
 // passed on the stack.
-RegsToPass.emplace_back(AArch64::X4, StackPtr);
+RegsToPass.emplace_back(AArch64::X4, ParamPtr);
 RegsToPass.emplace_back(AArch64::X5,
 DAG.getConstant(NumBytes, DL, MVT::i64));
   }

diff  --git a/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll 
b/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
index dc16b3a1a0f270..844fc52ddade63 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
@@ -100,5 +100,42 @@ define void @varargs_many_argscalleer() nounwind {
   ret void
 }
 
+define void @varargs_caller_tail() nounwind {
+; CHECK-LABEL: varargs_caller_tail:
+; CHECK:// %bb.0:
+; CHECK-NEXT:sub sp, sp, #48
+; CHECK-NEXT:mov x4, sp
+; CHECK-NEXT:add x8, sp, #16
+; CHECK-NEXT:mov x9, #4617315517961601024// 
=0x4014
+; CHECK-NEXT:mov x0, #4607182418800017408// 
=0x3ff0
+; CHECK-NEXT:mov w1, #2  // =0x2
+; CHECK-NEXT:mov x2, #4613937818241073152// 
=0x4008
+; CHECK-NEXT:mov w3, #4  // =0x4
+; CHECK-NEXT:mov w5, #16 // =0x10
+; CHECK-NEXT:stp xzr, x30, [sp, #24] // 8-byte Folded 
Spill
+; CHECK-NEXT:stp x9, x8, [sp]
+; CHECK-NEXT:str xzr, [sp, #16]
+; CHECK-NEXT:.weak_anti_dep  varargs_callee
+; CHECK-NEXT:.set varargs_callee, "#varargs_callee"@WEAKREF
+; CHECK-NEXT:.weak_anti_dep  "#varargs_callee"
+; CHECK-NEXT:.set "#varargs_callee", varargs_callee@WEAKREF
+; CHECK-NEXT:bl  "#varargs_callee"
+; CHECK-NEXT:ldr x30, [sp, #32]  // 8-byte Folded 
Reload
+; CHECK-NEXT:add x4, sp, #48
+; CHECK-NEXT:mov x0, #4607182418800017408// 
=0x3ff0
+; CHECK-NEXT:mov w1, #4  // =0x4
+; CHECK-NEXT:mov w2, #3  // =0x3
+; CHECK-NEXT:mov w3, #2  // =0x2
+; CHECK-NEXT:mov x5, xzr
+; CHECK-NEXT:add sp, sp, #48
+; CHECK-NEXT:.weak_anti_dep  varargs_callee
+; CHECK-NEXT:.set varargs_callee, "#varargs_callee"@WEAKREF
+; CHECK-NEXT:.weak_anti_dep  "#varargs_callee"
+; CHECK-NEXT:.set "#varargs_callee", varargs_callee@WEAKREF
+; CHECK-NEXT:b   "#varargs_callee"
+  call void (double, ...) @varargs_callee(double 1.0, i32 2, double 3.0, i32 
4, double 5.0, <2 x double> )
+  tail call void (double, ...) @varargs_callee(double 1.0, i32 4, i32 3, i32 2)
+  ret void
+}
 
 declare void @llvm.va_start(ptr)

diff  --git a/llvm/test/CodeGen/AArch64/vararg-tallcall.ll 
b/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
index 2d6db1642247d7..812837639196e6 100644
--- a/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
+++ b/llvm/test/CodeGen/AArch

[llvm-branch-commits] [llvm] 42c599a - [AArch64] Fix generated types for ARM64EC variadic entry thunk targets (#80595)

[Daniel Paoliello via llvm-branch-commits]

Author: Billy Laws
Date: 2024-03-11T14:29:51-07:00
New Revision: 42c599ab365b6d413d7e35a40f6e4ab98f523b67

URL: 
https://github.com/llvm/llvm-project/commit/42c599ab365b6d413d7e35a40f6e4ab98f523b67
DIFF: 
https://github.com/llvm/llvm-project/commit/42c599ab365b6d413d7e35a40f6e4ab98f523b67.diff

LOG: [AArch64] Fix generated types for ARM64EC variadic entry thunk targets 
(#80595)

ISel handles filling in x4/x5 when calling variadic functions as they
don't correspond to the 5th/6th X64 arguments but rather to the end of
the shadow space on the stack and the size in bytes of all stack
parameters (ignored and written as 0 for calls from entry thunks).

Will PR a follow up with ISel handling after this is merged.

Added: 


Modified: 
llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll

Removed: 




diff  --git a/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp 
b/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
index 11248bb7aef31f..91b4f18c73c935 100644
--- a/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
@@ -43,6 +43,8 @@ static cl::opt 
GenerateThunks("arm64ec-generate-thunks", cl::Hidden,
 
 namespace {
 
+enum class ThunkType { GuestExit, Entry, Exit };
+
 class AArch64Arm64ECCallLowering : public ModulePass {
 public:
   static char ID;
@@ -69,14 +71,14 @@ class AArch64Arm64ECCallLowering : public ModulePass {
   Type *I64Ty;
   Type *VoidTy;
 
-  void getThunkType(FunctionType *FT, AttributeList AttrList, bool EntryThunk,
+  void getThunkType(FunctionType *FT, AttributeList AttrList, ThunkType TT,
 raw_ostream &Out, FunctionType *&Arm64Ty,
 FunctionType *&X64Ty);
   void getThunkRetType(FunctionType *FT, AttributeList AttrList,
raw_ostream &Out, Type *&Arm64RetTy, Type *&X64RetTy,
SmallVectorImpl &Arm64ArgTypes,
SmallVectorImpl &X64ArgTypes, bool &HasSretPtr);
-  void getThunkArgTypes(FunctionType *FT, AttributeList AttrList,
+  void getThunkArgTypes(FunctionType *FT, AttributeList AttrList, ThunkType TT,
 raw_ostream &Out,
 SmallVectorImpl &Arm64ArgTypes,
 SmallVectorImpl &X64ArgTypes, bool HasSretPtr);
@@ -89,10 +91,11 @@ class AArch64Arm64ECCallLowering : public ModulePass {
 
 void AArch64Arm64ECCallLowering::getThunkType(FunctionType *FT,
   AttributeList AttrList,
-  bool EntryThunk, raw_ostream 
&Out,
+  ThunkType TT, raw_ostream &Out,
   FunctionType *&Arm64Ty,
   FunctionType *&X64Ty) {
-  Out << (EntryThunk ? "$ientry_thunk$cdecl$" : "$iexit_thunk$cdecl$");
+  Out << (TT == ThunkType::Entry ? "$ientry_thunk$cdecl$"
+ : "$iexit_thunk$cdecl$");
 
   Type *Arm64RetTy;
   Type *X64RetTy;
@@ -102,8 +105,8 @@ void AArch64Arm64ECCallLowering::getThunkType(FunctionType 
*FT,
 
   // The first argument to a thunk is the called function, stored in x9.
   // For exit thunks, we pass the called function down to the emulator;
-  // for entry thunks, we just call the Arm64 function directly.
-  if (!EntryThunk)
+  // for entry/guest exit thunks, we just call the Arm64 function directly.
+  if (TT == ThunkType::Exit)
 Arm64ArgTypes.push_back(PtrTy);
   X64ArgTypes.push_back(PtrTy);
 
@@ -111,14 +114,16 @@ void 
AArch64Arm64ECCallLowering::getThunkType(FunctionType *FT,
   getThunkRetType(FT, AttrList, Out, Arm64RetTy, X64RetTy, Arm64ArgTypes,
   X64ArgTypes, HasSretPtr);
 
-  getThunkArgTypes(FT, AttrList, Out, Arm64ArgTypes, X64ArgTypes, HasSretPtr);
+  getThunkArgTypes(FT, AttrList, TT, Out, Arm64ArgTypes, X64ArgTypes,
+   HasSretPtr);
 
-  Arm64Ty = FunctionType::get(Arm64RetTy, Arm64ArgTypes, false);
+  Arm64Ty = FunctionType::get(Arm64RetTy, Arm64ArgTypes,
+  TT == ThunkType::Entry && FT->isVarArg());
   X64Ty = FunctionType::get(X64RetTy, X64ArgTypes, false);
 }
 
 void AArch64Arm64ECCallLowering::getThunkArgTypes(
-FunctionType *FT, AttributeList AttrList, raw_ostream &Out,
+FunctionType *FT, AttributeList AttrList, ThunkType TT, raw_ostream &Out,
 SmallVectorImpl &Arm64ArgTypes,
 SmallVectorImpl &X64ArgTypes, bool HasSretPtr) {
 
@@ -151,14 +156,16 @@ void AArch64Arm64ECCallLowering::getThunkArgTypes(
   X64ArgTypes.push_back(I64Ty);
 }
 
-// x4
-Arm64ArgTypes.push_back(PtrTy);
-X64ArgTypes.push_back(PtrTy);
-// x5
-Arm64ArgTypes.push_back(I64Ty);
-// FIXME: x5 isn't actually passed/used by the x64 side; revisit once we
-// have pr

[llvm-branch-commits] [llvm] 89d5432 - [AArch64] Skip over shadow space for ARM64EC entry thunk variadic calls (#80994)

[Daniel Paoliello via llvm-branch-commits]

Author: Billy Laws
Date: 2024-03-11T14:29:51-07:00
New Revision: 89d543227a324d9925c68caf5d75c8c1e46c02a4

URL: 
https://github.com/llvm/llvm-project/commit/89d543227a324d9925c68caf5d75c8c1e46c02a4
DIFF: 
https://github.com/llvm/llvm-project/commit/89d543227a324d9925c68caf5d75c8c1e46c02a4.diff

LOG: [AArch64] Skip over shadow space for ARM64EC entry thunk variadic calls 
(#80994)

When in an entry thunk the x64 SP is passed in x4 but this cannot be
directly passed through since x64 varargs calls have a 32 byte shadow
store at SP followed by the in-stack parameters. ARM64EC varargs calls
on the other hand expect x4 to point to the first in-stack parameter.

Added: 


Modified: 
llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
llvm/lib/Target/AArch64/AArch64CallingConvention.td
llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll

Removed: 




diff  --git a/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp 
b/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
index 91b4f18c73c935..03d641d04413ef 100644
--- a/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
@@ -117,8 +117,8 @@ void AArch64Arm64ECCallLowering::getThunkType(FunctionType 
*FT,
   getThunkArgTypes(FT, AttrList, TT, Out, Arm64ArgTypes, X64ArgTypes,
HasSretPtr);
 
-  Arm64Ty = FunctionType::get(Arm64RetTy, Arm64ArgTypes,
-  TT == ThunkType::Entry && FT->isVarArg());
+  Arm64Ty = FunctionType::get(Arm64RetTy, Arm64ArgTypes, false);
+
   X64Ty = FunctionType::get(X64RetTy, X64ArgTypes, false);
 }
 
@@ -156,13 +156,13 @@ void AArch64Arm64ECCallLowering::getThunkArgTypes(
   X64ArgTypes.push_back(I64Ty);
 }
 
+// x4
+Arm64ArgTypes.push_back(PtrTy);
+X64ArgTypes.push_back(PtrTy);
+// x5
+Arm64ArgTypes.push_back(I64Ty);
 if (TT != ThunkType::Entry) {
-  // x4
-  Arm64ArgTypes.push_back(PtrTy);
-  X64ArgTypes.push_back(PtrTy);
-  // x5
-  Arm64ArgTypes.push_back(I64Ty);
-  // FIXME: x5 isn't actually passed/used by the x64 side; revisit once we
+  // FIXME: x5 isn't actually used by the x64 side; revisit once we
   // have proper isel for varargs
   X64ArgTypes.push_back(I64Ty);
 }
@@ -471,10 +471,11 @@ Function 
*AArch64Arm64ECCallLowering::buildEntryThunk(Function *F) {
 
   bool TransformDirectToSRet = X64RetType->isVoidTy() && !RetTy->isVoidTy();
   unsigned ThunkArgOffset = TransformDirectToSRet ? 2 : 1;
+  unsigned PassthroughArgSize = F->isVarArg() ? 5 : Thunk->arg_size();
 
   // Translate arguments to call.
   SmallVector Args;
-  for (unsigned i = ThunkArgOffset, e = Thunk->arg_size(); i != e; ++i) {
+  for (unsigned i = ThunkArgOffset, e = PassthroughArgSize; i != e; ++i) {
 Value *Arg = Thunk->getArg(i);
 Type *ArgTy = Arm64Ty->getParamType(i - ThunkArgOffset);
 if (ArgTy->isArrayTy() || ArgTy->isStructTy() ||
@@ -491,6 +492,22 @@ Function 
*AArch64Arm64ECCallLowering::buildEntryThunk(Function *F) {
 Args.push_back(Arg);
   }
 
+  if (F->isVarArg()) {
+// The 5th argument to variadic entry thunks is used to model the x64 sp
+// which is passed to the thunk in x4, this can be passed to the callee as
+// the variadic argument start address after skipping over the 32 byte
+// shadow store.
+
+// The EC thunk CC will assign any argument marked as InReg to x4.
+Thunk->addParamAttr(5, Attribute::InReg);
+Value *Arg = Thunk->getArg(5);
+Arg = IRB.CreatePtrAdd(Arg, IRB.getInt64(0x20));
+Args.push_back(Arg);
+
+// Pass in a zero variadic argument size (in x5).
+Args.push_back(IRB.getInt64(0));
+  }
+
   // Call the function passed to the thunk.
   Value *Callee = Thunk->getArg(0);
   Callee = IRB.CreateBitCast(Callee, PtrTy);

diff  --git a/llvm/lib/Target/AArch64/AArch64CallingConvention.td 
b/llvm/lib/Target/AArch64/AArch64CallingConvention.td
index 78ea4a5180f703..8e67f0f5c8815f 100644
--- a/llvm/lib/Target/AArch64/AArch64CallingConvention.td
+++ b/llvm/lib/Target/AArch64/AArch64CallingConvention.td
@@ -213,6 +213,9 @@ def CC_AArch64_Arm64EC_VarArg : CallingConv<[
 // address is passed in X9.
 let Entry = 1 in
 def CC_AArch64_Arm64EC_Thunk : CallingConv<[
+  // ARM64EC-specific: the InReg attribute can be used to access the x64 sp 
passed into entry thunks in x4 from the IR.
+  CCIfInReg>>,
+
   // Byval aggregates are passed by pointer
   CCIfByVal>,
 

diff  --git a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll 
b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
index 0083818def1514..bb9ba05f7a2724 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
@@ -147,7 +147,7 @@ define void @has_varargs(...) nounwind {
 ; CHECK-NEXT: add x29, sp, #160
 ; CHECK-NEXT: .seh_add_fp 160
 ; CHECK-NEXT: .seh_endprologue

[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello updated 
https://github.com/llvm/llvm-project/pull/84590

>From e96d29f7e80a89204ba541a8af516bf47698d93f Mon Sep 17 00:00:00 2001
From: Jacek Caban 
Date: Tue, 6 Feb 2024 13:47:58 +0100
Subject: [PATCH 1/4] [llvm-readobj][Object][COFF] Print COFF import library
 symbol export name. (#78769)

getExportName implementation is based on lld-link. In its current form,
it's mostly about convenience, but it will be more useful for EXPORTAS
support, for which export name is not possible to deduce from other
printed properties.
---
 lld/test/COFF/def-export-cpp.s|  1 +
 lld/test/COFF/def-export-stdcall.s| 13 ++
 lld/test/COFF/dllexport.s |  4 +++
 llvm/include/llvm/Object/COFFImportFile.h |  1 +
 llvm/lib/Object/COFFImportFile.cpp| 26 +++
 .../tools/llvm-dlltool/coff-decorated.def |  7 +
 llvm/test/tools/llvm-dlltool/coff-exports.def |  3 +++
 llvm/test/tools/llvm-dlltool/coff-noname.def  |  1 +
 .../llvm-dlltool/no-leading-underscore.def|  2 ++
 llvm/test/tools/llvm-lib/arm64ec-implib.test  |  2 ++
 .../tools/llvm-readobj/COFF/file-headers.test |  1 +
 llvm/tools/llvm-readobj/COFFImportDumper.cpp  |  3 +++
 12 files changed, 64 insertions(+)

diff --git a/lld/test/COFF/def-export-cpp.s b/lld/test/COFF/def-export-cpp.s
index e00b35b1c5b39b..370b8ddba4104b 100644
--- a/lld/test/COFF/def-export-cpp.s
+++ b/lld/test/COFF/def-export-cpp.s
@@ -10,6 +10,7 @@
 
 # IMPLIB: File: foo.dll
 # IMPLIB: Name type: undecorate
+# IMPLIB-NEXT: Export name: GetPathOnDisk
 # IMPLIB-NEXT: Symbol: __imp_?GetPathOnDisk@@YA_NPEA_W@Z
 # IMPLIB-NEXT: Symbol: ?GetPathOnDisk@@YA_NPEA_W@Z
 
diff --git a/lld/test/COFF/def-export-stdcall.s 
b/lld/test/COFF/def-export-stdcall.s
index f015e205c74a33..7e4e04c77cbe7a 100644
--- a/lld/test/COFF/def-export-stdcall.s
+++ b/lld/test/COFF/def-export-stdcall.s
@@ -6,15 +6,19 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
UNDECORATED-EXPORTS %s
 
 # UNDECORATED-IMPLIB: Name type: noprefix
+# UNDECORATED-IMPLIB-NEXT: Export name: _underscored
 # UNDECORATED-IMPLIB-NEXT: __imp___underscored
 # UNDECORATED-IMPLIB-NEXT: __underscored
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: fastcall
 # UNDECORATED-IMPLIB-NEXT: __imp_@fastcall@8
 # UNDECORATED-IMPLIB-NEXT: fastcall@8
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: stdcall
 # UNDECORATED-IMPLIB-NEXT: __imp__stdcall@8
 # UNDECORATED-IMPLIB-NEXT: _stdcall@8
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: vectorcall
 # UNDECORATED-IMPLIB-NEXT: __imp_vectorcall@@8
 # UNDECORATED-IMPLIB-NEXT: vectorcall@@8
 
@@ -30,12 +34,15 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
DECORATED-EXPORTS %s
 
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: @fastcall@8
 # DECORATED-IMPLIB-NEXT: __imp_@fastcall@8
 # DECORATED-IMPLIB-NEXT: @fastcall@8
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: _stdcall@8
 # DECORATED-IMPLIB-NEXT: __imp__stdcall@8
 # DECORATED-IMPLIB-NEXT: _stdcall@8
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: vectorcall@@8
 # DECORATED-IMPLIB-NEXT: __imp_vectorcall@@8
 # DECORATED-IMPLIB-NEXT: vectorcall@@8
 
@@ -51,14 +58,17 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
DECORATED-MINGW-EXPORTS %s
 
 # DECORATED-MINGW-IMPLIB: Name type: name
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: @fastcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp_@fastcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: fastcall@8
 # DECORATED-MINGW-IMPLIB: Name type: noprefix
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: stdcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp__stdcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: _stdcall@8
 # GNU tools don't support vectorcall, but this test is just to track that
 # lld's behaviour remains consistent over time.
 # DECORATED-MINGW-IMPLIB: Name type: name
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: vectorcall@@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp_vectorcall@@8
 # DECORATED-MINGW-IMPLIB-NEXT: vectorcall@@8
 
@@ -75,14 +85,17 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
MINGW-KILL-AT-EXPORTS %s
 
 # MINGW-KILL-AT-IMPLIB: Name type: noprefix
+# MINGW-KILL-AT-IMPLIB: Export name: fastcall
 # MINGW-KILL-AT-IMPLIB: __imp__fastcall
 # MINGW-KILL-AT-IMPLIB-NEXT: _fastcall
 # MINGW-KILL-AT-IMPLIB: Name type: noprefix
+# MINGW-KILL-AT-IMPLIB-NEXT: Export name: stdcall
 # MINGW-KILL-AT-IMPLIB-NEXT: __imp__stdcall
 # MINGW-KILL-AT-IMPLIB-NEXT: _stdcall
 # GNU tools don't support vectorcall, but this test is just to track that
 # lld's behaviour remains consistent over time.
 # MINGW-KILL-AT-IMPLIB: Name type: noprefix
+# MINGW-KILL-AT-IMPLIB-NEXT: Export name: vectorcall
 # MINGW-KILL-AT-IMPLIB-NEXT: __imp__vectorcall
 # MINGW-KILL-AT-IMPLIB-NEXT

[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

[Daniel Paoliello via llvm-branch-commits]

dpaoliello wrote:

@cjacek if you really want me to revert the def parser portion, then I can do 
that. Otherwise, can you please sign off?

https://github.com/llvm/llvm-project/pull/84590
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[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello edited 
https://github.com/llvm/llvm-project/pull/84590
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[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

[Daniel Paoliello via llvm-branch-commits]

@@ -91,6 +120,10 @@ struct COFFShortExport {
   /// file, this is "baz" in "EXPORTS\nfoo = bar == baz".
   std::string AliasTarget;
 
+  /// Specifies EXPORTAS name. In a .def file, this is "bar" in
+  /// "EXPORTS\nfoo EXPORTAS bar".
+  std::string ExportAs;

dpaoliello wrote:

If that's problematic, this specific part of the change isn't needed for Rust's 
scenario.

https://github.com/llvm/llvm-project/pull/84590
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[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

[Daniel Paoliello via llvm-branch-commits]

dpaoliello wrote:

@tstellar I'd like to get this merged into the v18 release branch, but there's 
some discussion of whether we should trim the changes down to just what is 
needed or leave them as they were merged into master. Can you please let me 
know what your preference is?

https://github.com/llvm/llvm-project/pull/84590
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[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello updated 
https://github.com/llvm/llvm-project/pull/84590

>From 37bee8feb128de231ed278fa2ca95dc46581c014 Mon Sep 17 00:00:00 2001
From: Jacek Caban 
Date: Tue, 6 Feb 2024 13:47:58 +0100
Subject: [PATCH 1/5] [llvm-readobj][Object][COFF] Print COFF import library
 symbol export name. (#78769)

getExportName implementation is based on lld-link. In its current form,
it's mostly about convenience, but it will be more useful for EXPORTAS
support, for which export name is not possible to deduce from other
printed properties.
---
 lld/test/COFF/def-export-cpp.s|  1 +
 lld/test/COFF/def-export-stdcall.s| 13 ++
 lld/test/COFF/dllexport.s |  4 +++
 llvm/include/llvm/Object/COFFImportFile.h |  1 +
 llvm/lib/Object/COFFImportFile.cpp| 26 +++
 .../tools/llvm-dlltool/coff-decorated.def |  7 +
 llvm/test/tools/llvm-dlltool/coff-exports.def |  3 +++
 llvm/test/tools/llvm-dlltool/coff-noname.def  |  1 +
 .../llvm-dlltool/no-leading-underscore.def|  2 ++
 llvm/test/tools/llvm-lib/arm64ec-implib.test  |  2 ++
 .../tools/llvm-readobj/COFF/file-headers.test |  1 +
 llvm/tools/llvm-readobj/COFFImportDumper.cpp  |  3 +++
 12 files changed, 64 insertions(+)

diff --git a/lld/test/COFF/def-export-cpp.s b/lld/test/COFF/def-export-cpp.s
index e00b35b1c5b39b..370b8ddba4104b 100644
--- a/lld/test/COFF/def-export-cpp.s
+++ b/lld/test/COFF/def-export-cpp.s
@@ -10,6 +10,7 @@
 
 # IMPLIB: File: foo.dll
 # IMPLIB: Name type: undecorate
+# IMPLIB-NEXT: Export name: GetPathOnDisk
 # IMPLIB-NEXT: Symbol: __imp_?GetPathOnDisk@@YA_NPEA_W@Z
 # IMPLIB-NEXT: Symbol: ?GetPathOnDisk@@YA_NPEA_W@Z
 
diff --git a/lld/test/COFF/def-export-stdcall.s 
b/lld/test/COFF/def-export-stdcall.s
index f015e205c74a33..7e4e04c77cbe7a 100644
--- a/lld/test/COFF/def-export-stdcall.s
+++ b/lld/test/COFF/def-export-stdcall.s
@@ -6,15 +6,19 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
UNDECORATED-EXPORTS %s
 
 # UNDECORATED-IMPLIB: Name type: noprefix
+# UNDECORATED-IMPLIB-NEXT: Export name: _underscored
 # UNDECORATED-IMPLIB-NEXT: __imp___underscored
 # UNDECORATED-IMPLIB-NEXT: __underscored
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: fastcall
 # UNDECORATED-IMPLIB-NEXT: __imp_@fastcall@8
 # UNDECORATED-IMPLIB-NEXT: fastcall@8
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: stdcall
 # UNDECORATED-IMPLIB-NEXT: __imp__stdcall@8
 # UNDECORATED-IMPLIB-NEXT: _stdcall@8
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: vectorcall
 # UNDECORATED-IMPLIB-NEXT: __imp_vectorcall@@8
 # UNDECORATED-IMPLIB-NEXT: vectorcall@@8
 
@@ -30,12 +34,15 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
DECORATED-EXPORTS %s
 
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: @fastcall@8
 # DECORATED-IMPLIB-NEXT: __imp_@fastcall@8
 # DECORATED-IMPLIB-NEXT: @fastcall@8
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: _stdcall@8
 # DECORATED-IMPLIB-NEXT: __imp__stdcall@8
 # DECORATED-IMPLIB-NEXT: _stdcall@8
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: vectorcall@@8
 # DECORATED-IMPLIB-NEXT: __imp_vectorcall@@8
 # DECORATED-IMPLIB-NEXT: vectorcall@@8
 
@@ -51,14 +58,17 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
DECORATED-MINGW-EXPORTS %s
 
 # DECORATED-MINGW-IMPLIB: Name type: name
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: @fastcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp_@fastcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: fastcall@8
 # DECORATED-MINGW-IMPLIB: Name type: noprefix
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: stdcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp__stdcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: _stdcall@8
 # GNU tools don't support vectorcall, but this test is just to track that
 # lld's behaviour remains consistent over time.
 # DECORATED-MINGW-IMPLIB: Name type: name
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: vectorcall@@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp_vectorcall@@8
 # DECORATED-MINGW-IMPLIB-NEXT: vectorcall@@8
 
@@ -75,14 +85,17 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
MINGW-KILL-AT-EXPORTS %s
 
 # MINGW-KILL-AT-IMPLIB: Name type: noprefix
+# MINGW-KILL-AT-IMPLIB: Export name: fastcall
 # MINGW-KILL-AT-IMPLIB: __imp__fastcall
 # MINGW-KILL-AT-IMPLIB-NEXT: _fastcall
 # MINGW-KILL-AT-IMPLIB: Name type: noprefix
+# MINGW-KILL-AT-IMPLIB-NEXT: Export name: stdcall
 # MINGW-KILL-AT-IMPLIB-NEXT: __imp__stdcall
 # MINGW-KILL-AT-IMPLIB-NEXT: _stdcall
 # GNU tools don't support vectorcall, but this test is just to track that
 # lld's behaviour remains consistent over time.
 # MINGW-KILL-AT-IMPLIB: Name type: noprefix
+# MINGW-KILL-AT-IMPLIB-NEXT: Export name: vectorcall
 # MINGW-KILL-AT-IMPLIB-NEXT: __imp__vectorcall
 # MINGW-KILL-AT-IMPLIB-NEXT

[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

[Daniel Paoliello via llvm-branch-commits]

@@ -91,6 +120,10 @@ struct COFFShortExport {
   /// file, this is "baz" in "EXPORTS\nfoo = bar == baz".
   std::string AliasTarget;
 
+  /// Specifies EXPORTAS name. In a .def file, this is "bar" in
+  /// "EXPORTS\nfoo EXPORTAS bar".
+  std::string ExportAs;

dpaoliello wrote:

Done

https://github.com/llvm/llvm-project/pull/84590
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[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello edited 
https://github.com/llvm/llvm-project/pull/84590
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[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

[Daniel Paoliello via llvm-branch-commits]

dpaoliello wrote:

@tstellar change made as requested, this is now ready to merge

https://github.com/llvm/llvm-project/pull/84590
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[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello updated 
https://github.com/llvm/llvm-project/pull/84590

>From 1a9bb5ccfd8f93be51d22fb00f38e86a01e82587 Mon Sep 17 00:00:00 2001
From: Jacek Caban 
Date: Tue, 6 Feb 2024 13:47:58 +0100
Subject: [PATCH 1/5] [llvm-readobj][Object][COFF] Print COFF import library
 symbol export name. (#78769)

getExportName implementation is based on lld-link. In its current form,
it's mostly about convenience, but it will be more useful for EXPORTAS
support, for which export name is not possible to deduce from other
printed properties.
---
 lld/test/COFF/def-export-cpp.s|  1 +
 lld/test/COFF/def-export-stdcall.s| 13 ++
 lld/test/COFF/dllexport.s |  4 +++
 llvm/include/llvm/Object/COFFImportFile.h |  1 +
 llvm/lib/Object/COFFImportFile.cpp| 26 +++
 .../tools/llvm-dlltool/coff-decorated.def |  7 +
 llvm/test/tools/llvm-dlltool/coff-exports.def |  3 +++
 llvm/test/tools/llvm-dlltool/coff-noname.def  |  1 +
 .../llvm-dlltool/no-leading-underscore.def|  2 ++
 llvm/test/tools/llvm-lib/arm64ec-implib.test  |  2 ++
 .../tools/llvm-readobj/COFF/file-headers.test |  1 +
 llvm/tools/llvm-readobj/COFFImportDumper.cpp  |  3 +++
 12 files changed, 64 insertions(+)

diff --git a/lld/test/COFF/def-export-cpp.s b/lld/test/COFF/def-export-cpp.s
index e00b35b1c5b39b..370b8ddba4104b 100644
--- a/lld/test/COFF/def-export-cpp.s
+++ b/lld/test/COFF/def-export-cpp.s
@@ -10,6 +10,7 @@
 
 # IMPLIB: File: foo.dll
 # IMPLIB: Name type: undecorate
+# IMPLIB-NEXT: Export name: GetPathOnDisk
 # IMPLIB-NEXT: Symbol: __imp_?GetPathOnDisk@@YA_NPEA_W@Z
 # IMPLIB-NEXT: Symbol: ?GetPathOnDisk@@YA_NPEA_W@Z
 
diff --git a/lld/test/COFF/def-export-stdcall.s 
b/lld/test/COFF/def-export-stdcall.s
index f015e205c74a33..7e4e04c77cbe7a 100644
--- a/lld/test/COFF/def-export-stdcall.s
+++ b/lld/test/COFF/def-export-stdcall.s
@@ -6,15 +6,19 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
UNDECORATED-EXPORTS %s
 
 # UNDECORATED-IMPLIB: Name type: noprefix
+# UNDECORATED-IMPLIB-NEXT: Export name: _underscored
 # UNDECORATED-IMPLIB-NEXT: __imp___underscored
 # UNDECORATED-IMPLIB-NEXT: __underscored
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: fastcall
 # UNDECORATED-IMPLIB-NEXT: __imp_@fastcall@8
 # UNDECORATED-IMPLIB-NEXT: fastcall@8
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: stdcall
 # UNDECORATED-IMPLIB-NEXT: __imp__stdcall@8
 # UNDECORATED-IMPLIB-NEXT: _stdcall@8
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: vectorcall
 # UNDECORATED-IMPLIB-NEXT: __imp_vectorcall@@8
 # UNDECORATED-IMPLIB-NEXT: vectorcall@@8
 
@@ -30,12 +34,15 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
DECORATED-EXPORTS %s
 
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: @fastcall@8
 # DECORATED-IMPLIB-NEXT: __imp_@fastcall@8
 # DECORATED-IMPLIB-NEXT: @fastcall@8
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: _stdcall@8
 # DECORATED-IMPLIB-NEXT: __imp__stdcall@8
 # DECORATED-IMPLIB-NEXT: _stdcall@8
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: vectorcall@@8
 # DECORATED-IMPLIB-NEXT: __imp_vectorcall@@8
 # DECORATED-IMPLIB-NEXT: vectorcall@@8
 
@@ -51,14 +58,17 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
DECORATED-MINGW-EXPORTS %s
 
 # DECORATED-MINGW-IMPLIB: Name type: name
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: @fastcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp_@fastcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: fastcall@8
 # DECORATED-MINGW-IMPLIB: Name type: noprefix
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: stdcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp__stdcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: _stdcall@8
 # GNU tools don't support vectorcall, but this test is just to track that
 # lld's behaviour remains consistent over time.
 # DECORATED-MINGW-IMPLIB: Name type: name
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: vectorcall@@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp_vectorcall@@8
 # DECORATED-MINGW-IMPLIB-NEXT: vectorcall@@8
 
@@ -75,14 +85,17 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
MINGW-KILL-AT-EXPORTS %s
 
 # MINGW-KILL-AT-IMPLIB: Name type: noprefix
+# MINGW-KILL-AT-IMPLIB: Export name: fastcall
 # MINGW-KILL-AT-IMPLIB: __imp__fastcall
 # MINGW-KILL-AT-IMPLIB-NEXT: _fastcall
 # MINGW-KILL-AT-IMPLIB: Name type: noprefix
+# MINGW-KILL-AT-IMPLIB-NEXT: Export name: stdcall
 # MINGW-KILL-AT-IMPLIB-NEXT: __imp__stdcall
 # MINGW-KILL-AT-IMPLIB-NEXT: _stdcall
 # GNU tools don't support vectorcall, but this test is just to track that
 # lld's behaviour remains consistent over time.
 # MINGW-KILL-AT-IMPLIB: Name type: noprefix
+# MINGW-KILL-AT-IMPLIB-NEXT: Export name: vectorcall
 # MINGW-KILL-AT-IMPLIB-NEXT: __imp__vectorcall
 # MINGW-KILL-AT-IMPLIB-NEXT

[llvm-branch-commits] [llvm] Backport: Prepend all library intrinsics with `#` when building for Arm64EC (PR #88016)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello created 
https://github.com/llvm/llvm-project/pull/88016

Backports #87542 to v18

While attempting to build some Rust code, I was getting linker errors due to 
missing functions that are implemented in `compiler-rt`. Turns out that when 
`compiler-rt` is built for Arm64EC, all its function names are mangled with the 
leading `#`.

This change removes the hard-coded list of library-implemented intrinsics to 
mangle for Arm64EC, and instead assumes that they all must be mangled.

>From eca4f2e3d538c5a0ff43e745181321ae8c9618f5 Mon Sep 17 00:00:00 2001
From: Daniel Paoliello 
Date: Fri, 5 Apr 2024 12:06:47 -0700
Subject: [PATCH] Prepend all library intrinsics with `#` when building for
 Arm64EC (#87542)

While attempting to build some Rust code, I was getting linker errors
due to missing functions that are implemented in `compiler-rt`. Turns
out that when `compiler-rt` is built for Arm64EC, all its function names
are mangled with the leading `#`.

This change removes the hard-coded list of library-implemented
intrinsics to mangle for Arm64EC, and instead assumes that they all must
be mangled.
---
 .../Target/AArch64/AArch64ISelLowering.cpp| 42 ---
 llvm/lib/Target/AArch64/AArch64ISelLowering.h |  3 ++
 2 files changed, 11 insertions(+), 34 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp 
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 196aa50cf4060b..95d8ab95b2c097 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1658,40 +1658,14 @@ AArch64TargetLowering::AArch64TargetLowering(const 
TargetMachine &TM,
   setMaxAtomicSizeInBitsSupported(128);
 
   if (Subtarget->isWindowsArm64EC()) {
-// FIXME: are there other intrinsics we need to add here?
-setLibcallName(RTLIB::MEMCPY, "#memcpy");
-setLibcallName(RTLIB::MEMSET, "#memset");
-setLibcallName(RTLIB::MEMMOVE, "#memmove");
-setLibcallName(RTLIB::REM_F32, "#fmodf");
-setLibcallName(RTLIB::REM_F64, "#fmod");
-setLibcallName(RTLIB::FMA_F32, "#fmaf");
-setLibcallName(RTLIB::FMA_F64, "#fma");
-setLibcallName(RTLIB::SQRT_F32, "#sqrtf");
-setLibcallName(RTLIB::SQRT_F64, "#sqrt");
-setLibcallName(RTLIB::CBRT_F32, "#cbrtf");
-setLibcallName(RTLIB::CBRT_F64, "#cbrt");
-setLibcallName(RTLIB::LOG_F32, "#logf");
-setLibcallName(RTLIB::LOG_F64, "#log");
-setLibcallName(RTLIB::LOG2_F32, "#log2f");
-setLibcallName(RTLIB::LOG2_F64, "#log2");
-setLibcallName(RTLIB::LOG10_F32, "#log10f");
-setLibcallName(RTLIB::LOG10_F64, "#log10");
-setLibcallName(RTLIB::EXP_F32, "#expf");
-setLibcallName(RTLIB::EXP_F64, "#exp");
-setLibcallName(RTLIB::EXP2_F32, "#exp2f");
-setLibcallName(RTLIB::EXP2_F64, "#exp2");
-setLibcallName(RTLIB::EXP10_F32, "#exp10f");
-setLibcallName(RTLIB::EXP10_F64, "#exp10");
-setLibcallName(RTLIB::SIN_F32, "#sinf");
-setLibcallName(RTLIB::SIN_F64, "#sin");
-setLibcallName(RTLIB::COS_F32, "#cosf");
-setLibcallName(RTLIB::COS_F64, "#cos");
-setLibcallName(RTLIB::POW_F32, "#powf");
-setLibcallName(RTLIB::POW_F64, "#pow");
-setLibcallName(RTLIB::LDEXP_F32, "#ldexpf");
-setLibcallName(RTLIB::LDEXP_F64, "#ldexp");
-setLibcallName(RTLIB::FREXP_F32, "#frexpf");
-setLibcallName(RTLIB::FREXP_F64, "#frexp");
+// FIXME: are there intrinsics we need to exclude from this?
+for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
+  auto code = static_cast(i);
+  auto libcallName = getLibcallName(code);
+  if ((libcallName != nullptr) && (libcallName[0] != '#')) {
+setLibcallName(code, Saver.save(Twine("#") + libcallName).data());
+  }
+}
   }
 }
 
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h 
b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 541a810fb5cba0..74d0c4bde8dd2e 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1001,6 +1001,9 @@ class AArch64TargetLowering : public TargetLowering {
   /// make the right decision when generating code for different targets.
   const AArch64Subtarget *Subtarget;
 
+  llvm::BumpPtrAllocator BumpAlloc;
+  llvm::StringSaver Saver{BumpAlloc};
+
   bool isExtFreeImpl(const Instruction *Ext) const override;
 
   void addTypeForNEON(MVT VT);

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[llvm-branch-commits] [llvm] Backport: Prepend all library intrinsics with `#` when building for Arm64EC (PR #88016)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello milestoned 
https://github.com/llvm/llvm-project/pull/88016
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[llvm-branch-commits] [llvm] Backport: Prepend all library intrinsics with `#` when building for Arm64EC (PR #88016)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello updated 
https://github.com/llvm/llvm-project/pull/88016

>From 83514c75b37e1e02b7f7aca0225072d1068eaffb Mon Sep 17 00:00:00 2001
From: Daniel Paoliello 
Date: Fri, 5 Apr 2024 12:06:47 -0700
Subject: [PATCH] Prepend all library intrinsics with `#` when building for
 Arm64EC (#87542)

While attempting to build some Rust code, I was getting linker errors
due to missing functions that are implemented in `compiler-rt`. Turns
out that when `compiler-rt` is built for Arm64EC, all its function names
are mangled with the leading `#`.

This change removes the hard-coded list of library-implemented
intrinsics to mangle for Arm64EC, and instead assumes that they all must
be mangled.
---
 .../Target/AArch64/AArch64ISelLowering.cpp| 42 ---
 llvm/lib/Target/AArch64/AArch64ISelLowering.h |  3 ++
 2 files changed, 11 insertions(+), 34 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp 
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 196aa50cf4060b..95d8ab95b2c097 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1658,40 +1658,14 @@ AArch64TargetLowering::AArch64TargetLowering(const 
TargetMachine &TM,
   setMaxAtomicSizeInBitsSupported(128);
 
   if (Subtarget->isWindowsArm64EC()) {
-// FIXME: are there other intrinsics we need to add here?
-setLibcallName(RTLIB::MEMCPY, "#memcpy");
-setLibcallName(RTLIB::MEMSET, "#memset");
-setLibcallName(RTLIB::MEMMOVE, "#memmove");
-setLibcallName(RTLIB::REM_F32, "#fmodf");
-setLibcallName(RTLIB::REM_F64, "#fmod");
-setLibcallName(RTLIB::FMA_F32, "#fmaf");
-setLibcallName(RTLIB::FMA_F64, "#fma");
-setLibcallName(RTLIB::SQRT_F32, "#sqrtf");
-setLibcallName(RTLIB::SQRT_F64, "#sqrt");
-setLibcallName(RTLIB::CBRT_F32, "#cbrtf");
-setLibcallName(RTLIB::CBRT_F64, "#cbrt");
-setLibcallName(RTLIB::LOG_F32, "#logf");
-setLibcallName(RTLIB::LOG_F64, "#log");
-setLibcallName(RTLIB::LOG2_F32, "#log2f");
-setLibcallName(RTLIB::LOG2_F64, "#log2");
-setLibcallName(RTLIB::LOG10_F32, "#log10f");
-setLibcallName(RTLIB::LOG10_F64, "#log10");
-setLibcallName(RTLIB::EXP_F32, "#expf");
-setLibcallName(RTLIB::EXP_F64, "#exp");
-setLibcallName(RTLIB::EXP2_F32, "#exp2f");
-setLibcallName(RTLIB::EXP2_F64, "#exp2");
-setLibcallName(RTLIB::EXP10_F32, "#exp10f");
-setLibcallName(RTLIB::EXP10_F64, "#exp10");
-setLibcallName(RTLIB::SIN_F32, "#sinf");
-setLibcallName(RTLIB::SIN_F64, "#sin");
-setLibcallName(RTLIB::COS_F32, "#cosf");
-setLibcallName(RTLIB::COS_F64, "#cos");
-setLibcallName(RTLIB::POW_F32, "#powf");
-setLibcallName(RTLIB::POW_F64, "#pow");
-setLibcallName(RTLIB::LDEXP_F32, "#ldexpf");
-setLibcallName(RTLIB::LDEXP_F64, "#ldexp");
-setLibcallName(RTLIB::FREXP_F32, "#frexpf");
-setLibcallName(RTLIB::FREXP_F64, "#frexp");
+// FIXME: are there intrinsics we need to exclude from this?
+for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
+  auto code = static_cast(i);
+  auto libcallName = getLibcallName(code);
+  if ((libcallName != nullptr) && (libcallName[0] != '#')) {
+setLibcallName(code, Saver.save(Twine("#") + libcallName).data());
+  }
+}
   }
 }
 
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h 
b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 541a810fb5cba0..74d0c4bde8dd2e 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1001,6 +1001,9 @@ class AArch64TargetLowering : public TargetLowering {
   /// make the right decision when generating code for different targets.
   const AArch64Subtarget *Subtarget;
 
+  llvm::BumpPtrAllocator BumpAlloc;
+  llvm::StringSaver Saver{BumpAlloc};
+
   bool isExtFreeImpl(const Instruction *Ext) const override;
 
   void addTypeForNEON(MVT VT);

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[llvm-branch-commits] [llvm] release/18.x: Prepend all library intrinsics with `#` when building for Arm64EC (PR #88016)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello edited 
https://github.com/llvm/llvm-project/pull/88016
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[llvm-branch-commits] [llvm] release/18.x: Prepend all library intrinsics with `#` when building for Arm64EC (PR #88016)

[Daniel Paoliello via llvm-branch-commits]

dpaoliello wrote:

@tstellar this is ready to land for 18

https://github.com/llvm/llvm-project/pull/88016
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[llvm-branch-commits] [llvm] release/18.x: Prepend all library intrinsics with `#` when building for Arm64EC (PR #88016)

[Daniel Paoliello via llvm-branch-commits]

dpaoliello wrote:

> Hi @dpaoliello (or anyone else). If you would like to add a note about this 
> fix in the release notes (completely optional). Please reply to this comment 
> with a one or two sentence description of the fix.

Fixes an issue with Arm64EC code generation where calls to some intrinsics 
implemented in `compiler-rt` used the wrong name mangling, eventually resulting 
in unresolved symbol errors during linking.

https://github.com/llvm/llvm-project/pull/88016
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[llvm-branch-commits] [clang] [COFF][Aarch64] Add _InterlockedAdd64 intrinsic (#81849) (PR #89951)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello milestoned 
https://github.com/llvm/llvm-project/pull/89951
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[llvm-branch-commits] [clang] [COFF][Aarch64] Add _InterlockedAdd64 intrinsic (#81849) (PR #89951)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello created 
https://github.com/llvm/llvm-project/pull/89951

Found when compiling openssl master branch using clang-cl.

This commit introduces usage of InterlockedAdd64:

https://github.com/openssl/openssl/commit/d0e1a0ae701cfaca7f3dd3bf28a3f934a6408813


https://learn.microsoft.com/en-us/cpp/intrinsics/interlockedadd-intrinsic-functions

>From cb4faf6d335095111b1265efd2c3cd87882cce41 Mon Sep 17 00:00:00 2001
From: Pierrick Bouvier 
Date: Fri, 16 Feb 2024 15:20:08 +0400
Subject: [PATCH] [COFF][Aarch64] Add _InterlockedAdd64 intrinsic (#81849)

Found when compiling openssl master branch using clang-cl.

This commit introduces usage of InterlockedAdd64:

https://github.com/openssl/openssl/commit/d0e1a0ae701cfaca7f3dd3bf28a3f934a6408813


https://learn.microsoft.com/en-us/cpp/intrinsics/interlockedadd-intrinsic-functions
---
 clang/include/clang/Basic/BuiltinsAArch64.def   |  1 +
 clang/lib/CodeGen/CGBuiltin.cpp |  3 ++-
 clang/lib/Headers/intrin.h  |  1 +
 clang/test/CodeGen/arm64-microsoft-intrinsics.c | 14 ++
 clang/test/CodeGen/ms-intrinsics-other.c|  9 +
 clang/test/CodeGen/ms-intrinsics-underaligned.c |  6 ++
 6 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/clang/include/clang/Basic/BuiltinsAArch64.def 
b/clang/include/clang/Basic/BuiltinsAArch64.def
index 31ec84143f65c1..b5cbe90c8fd6a3 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.def
+++ b/clang/include/clang/Basic/BuiltinsAArch64.def
@@ -139,6 +139,7 @@ TARGET_HEADER_BUILTIN(_BitScanForward64, "UcUNi*ULLi", 
"nh", INTRIN_H, ALL_MS_LA
 TARGET_HEADER_BUILTIN(_BitScanReverse64, "UcUNi*ULLi", "nh", INTRIN_H, 
ALL_MS_LANGUAGES, "")
 
 TARGET_HEADER_BUILTIN(_InterlockedAdd,   "NiNiD*Ni","nh", 
INTRIN_H, ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedAdd64, "LLiLLiD*LLi", "nh", 
INTRIN_H, ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedAnd64, "LLiLLiD*LLi", "nh", 
INTRIN_H, ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedDecrement64,   "LLiLLiD*","nh", 
INTRIN_H, ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedExchange64,"LLiLLiD*LLi", "nh", 
INTRIN_H, ALL_MS_LANGUAGES, "")
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index a4f26a6f0eb19b..05a898a24b5890 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -12044,7 +12044,8 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned 
BuiltinID,
 "vgetq_lane");
   }
 
-  case clang::AArch64::BI_InterlockedAdd: {
+  case clang::AArch64::BI_InterlockedAdd:
+  case clang::AArch64::BI_InterlockedAdd64: {
 Address DestAddr = CheckAtomicAlignment(*this, E);
 Value *Val = EmitScalarExpr(E->getArg(1));
 AtomicRMWInst *RMWI =
diff --git a/clang/lib/Headers/intrin.h b/clang/lib/Headers/intrin.h
index 9ebaea9fee9421..a6395143db54c2 100644
--- a/clang/lib/Headers/intrin.h
+++ b/clang/lib/Headers/intrin.h
@@ -551,6 +551,7 @@ static __inline__ void __DEFAULT_FN_ATTRS __nop(void) {
 #if defined(__aarch64__)
 unsigned __int64 __getReg(int);
 long _InterlockedAdd(long volatile *Addend, long Value);
+__int64 _InterlockedAdd64(__int64 volatile *Addend, __int64 Value);
 __int64 _ReadStatusReg(int);
 void _WriteStatusReg(int, __int64);
 
diff --git a/clang/test/CodeGen/arm64-microsoft-intrinsics.c 
b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
index 44b2ee28fe5681..a354ed948ca5f1 100644
--- a/clang/test/CodeGen/arm64-microsoft-intrinsics.c
+++ b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
@@ -21,6 +21,20 @@ long test_InterlockedAdd_constant(long volatile *Addend) {
 // CHECK-MSVC: ret i32 %[[NEWVAL:[0-9]+]]
 // CHECK-LINUX: error: call to undeclared function '_InterlockedAdd'
 
+__int64 test_InterlockedAdd64(__int64 volatile *Addend, __int64 Value) {
+  return _InterlockedAdd64(Addend, Value);
+}
+
+__int64 test_InterlockedAdd64_constant(__int64 volatile *Addend) {
+  return _InterlockedAdd64(Addend, -1);
+}
+
+// CHECK-LABEL: define {{.*}} i64 @test_InterlockedAdd64(ptr %Addend, i64 
%Value) {{.*}} {
+// CHECK-MSVC: %[[OLDVAL:[0-9]+]] = atomicrmw add ptr %1, i64 %2 seq_cst, 
align 8
+// CHECK-MSVC: %[[NEWVAL:[0-9]+]] = add i64 %[[OLDVAL:[0-9]+]], %2
+// CHECK-MSVC: ret i64 %[[NEWVAL:[0-9]+]]
+// CHECK-LINUX: error: call to undeclared function '_InterlockedAdd64'
+
 void check__dmb(void) {
   __dmb(0);
 }
diff --git a/clang/test/CodeGen/ms-intrinsics-other.c 
b/clang/test/CodeGen/ms-intrinsics-other.c
index 76f54add749669..36c40dddcbb4f5 100644
--- a/clang/test/CodeGen/ms-intrinsics-other.c
+++ b/clang/test/CodeGen/ms-intrinsics-other.c
@@ -240,6 +240,15 @@ LONG test_InterlockedAdd(LONG volatile *Addend, LONG 
Value) {
 // CHECK-ARM-ARM64: %[[OLDVAL:[0-9]+]] = atomicrmw add ptr %Addend, i32 %Value 
seq_cst, align 4
 // CHECK-ARM-ARM64: %[[NEWVAL:[0-9]+]] = add i32 %[[OLDVAL:[0-9]+]], %Value
 // CHECK-ARM-ARM64: ret

[llvm-branch-commits] [clang] [release/18.x][COFF][Aarch64] Add _InterlockedAdd64 intrinsic (#81849) (PR #89951)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello edited 
https://github.com/llvm/llvm-project/pull/89951
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[llvm-branch-commits] [clang] [release/18.x][COFF][Aarch64] Add _InterlockedAdd64 intrinsic (#81849) (PR #89951)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello edited 
https://github.com/llvm/llvm-project/pull/89951
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[llvm-branch-commits] [clang] [release/18.x][COFF][Aarch64] Add _InterlockedAdd64 intrinsic (#81849) (PR #89951)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello updated 
https://github.com/llvm/llvm-project/pull/89951

>From d1a4febc0974cb76bce1692be9d62aaa9a5dcefb Mon Sep 17 00:00:00 2001
From: Pierrick Bouvier 
Date: Fri, 16 Feb 2024 15:20:08 +0400
Subject: [PATCH] [COFF][Aarch64] Add _InterlockedAdd64 intrinsic (#81849)

Found when compiling openssl master branch using clang-cl.

This commit introduces usage of InterlockedAdd64:

https://github.com/openssl/openssl/commit/d0e1a0ae701cfaca7f3dd3bf28a3f934a6408813


https://learn.microsoft.com/en-us/cpp/intrinsics/interlockedadd-intrinsic-functions
---
 clang/include/clang/Basic/BuiltinsAArch64.def   |  1 +
 clang/lib/CodeGen/CGBuiltin.cpp |  3 ++-
 clang/lib/Headers/intrin.h  |  1 +
 clang/test/CodeGen/arm64-microsoft-intrinsics.c | 14 ++
 clang/test/CodeGen/ms-intrinsics-other.c|  9 +
 clang/test/CodeGen/ms-intrinsics-underaligned.c |  6 ++
 6 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/clang/include/clang/Basic/BuiltinsAArch64.def 
b/clang/include/clang/Basic/BuiltinsAArch64.def
index 31ec84143f65c1..b5cbe90c8fd6a3 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.def
+++ b/clang/include/clang/Basic/BuiltinsAArch64.def
@@ -139,6 +139,7 @@ TARGET_HEADER_BUILTIN(_BitScanForward64, "UcUNi*ULLi", 
"nh", INTRIN_H, ALL_MS_LA
 TARGET_HEADER_BUILTIN(_BitScanReverse64, "UcUNi*ULLi", "nh", INTRIN_H, 
ALL_MS_LANGUAGES, "")
 
 TARGET_HEADER_BUILTIN(_InterlockedAdd,   "NiNiD*Ni","nh", 
INTRIN_H, ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedAdd64, "LLiLLiD*LLi", "nh", 
INTRIN_H, ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedAnd64, "LLiLLiD*LLi", "nh", 
INTRIN_H, ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedDecrement64,   "LLiLLiD*","nh", 
INTRIN_H, ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedExchange64,"LLiLLiD*LLi", "nh", 
INTRIN_H, ALL_MS_LANGUAGES, "")
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index a4f26a6f0eb19b..05a898a24b5890 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -12044,7 +12044,8 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned 
BuiltinID,
 "vgetq_lane");
   }
 
-  case clang::AArch64::BI_InterlockedAdd: {
+  case clang::AArch64::BI_InterlockedAdd:
+  case clang::AArch64::BI_InterlockedAdd64: {
 Address DestAddr = CheckAtomicAlignment(*this, E);
 Value *Val = EmitScalarExpr(E->getArg(1));
 AtomicRMWInst *RMWI =
diff --git a/clang/lib/Headers/intrin.h b/clang/lib/Headers/intrin.h
index 9ebaea9fee9421..a6395143db54c2 100644
--- a/clang/lib/Headers/intrin.h
+++ b/clang/lib/Headers/intrin.h
@@ -551,6 +551,7 @@ static __inline__ void __DEFAULT_FN_ATTRS __nop(void) {
 #if defined(__aarch64__)
 unsigned __int64 __getReg(int);
 long _InterlockedAdd(long volatile *Addend, long Value);
+__int64 _InterlockedAdd64(__int64 volatile *Addend, __int64 Value);
 __int64 _ReadStatusReg(int);
 void _WriteStatusReg(int, __int64);
 
diff --git a/clang/test/CodeGen/arm64-microsoft-intrinsics.c 
b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
index 44b2ee28fe5681..a354ed948ca5f1 100644
--- a/clang/test/CodeGen/arm64-microsoft-intrinsics.c
+++ b/clang/test/CodeGen/arm64-microsoft-intrinsics.c
@@ -21,6 +21,20 @@ long test_InterlockedAdd_constant(long volatile *Addend) {
 // CHECK-MSVC: ret i32 %[[NEWVAL:[0-9]+]]
 // CHECK-LINUX: error: call to undeclared function '_InterlockedAdd'
 
+__int64 test_InterlockedAdd64(__int64 volatile *Addend, __int64 Value) {
+  return _InterlockedAdd64(Addend, Value);
+}
+
+__int64 test_InterlockedAdd64_constant(__int64 volatile *Addend) {
+  return _InterlockedAdd64(Addend, -1);
+}
+
+// CHECK-LABEL: define {{.*}} i64 @test_InterlockedAdd64(ptr %Addend, i64 
%Value) {{.*}} {
+// CHECK-MSVC: %[[OLDVAL:[0-9]+]] = atomicrmw add ptr %1, i64 %2 seq_cst, 
align 8
+// CHECK-MSVC: %[[NEWVAL:[0-9]+]] = add i64 %[[OLDVAL:[0-9]+]], %2
+// CHECK-MSVC: ret i64 %[[NEWVAL:[0-9]+]]
+// CHECK-LINUX: error: call to undeclared function '_InterlockedAdd64'
+
 void check__dmb(void) {
   __dmb(0);
 }
diff --git a/clang/test/CodeGen/ms-intrinsics-other.c 
b/clang/test/CodeGen/ms-intrinsics-other.c
index 76f54add749669..36c40dddcbb4f5 100644
--- a/clang/test/CodeGen/ms-intrinsics-other.c
+++ b/clang/test/CodeGen/ms-intrinsics-other.c
@@ -240,6 +240,15 @@ LONG test_InterlockedAdd(LONG volatile *Addend, LONG 
Value) {
 // CHECK-ARM-ARM64: %[[OLDVAL:[0-9]+]] = atomicrmw add ptr %Addend, i32 %Value 
seq_cst, align 4
 // CHECK-ARM-ARM64: %[[NEWVAL:[0-9]+]] = add i32 %[[OLDVAL:[0-9]+]], %Value
 // CHECK-ARM-ARM64: ret i32 %[[NEWVAL:[0-9]+]]
+
+__int64 test_InterlockedAdd64(__int64 volatile *Addend, __int64 Value) {
+  return _InterlockedAdd64(Addend, Value);
+}
+
+// CHECK-ARM-ARM64: define{{.*}}i64 @test_InterlockedAdd64(ptr{{[a-z_ 
]*}}%Addend, i64 noundef %Value) {{.*}} {
+// CHECK-ARM-ARM6

[llvm-branch-commits] [clang] [release/18.x][COFF][Aarch64] Add _InterlockedAdd64 intrinsic (#81849) (PR #89951)

[Daniel Paoliello via llvm-branch-commits]

dpaoliello wrote:

> I think BuiltinsAArch64.def is part of clang's ABI, so changing it violates 
> the backport rules.
> 
> Otherwise, I'd be inclined to accept; it's kind of late to request, but it's 
> low risk.

@tstellar can you please advise if this change is ok to backport?

https://github.com/llvm/llvm-project/pull/89951
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[llvm-branch-commits] [clang] [release/18.x][COFF][Aarch64] Add _InterlockedAdd64 intrinsic (#81849) (PR #89951)

[Daniel Paoliello via llvm-branch-commits]

dpaoliello wrote:

Closing this since it would be an ABI break

https://github.com/llvm/llvm-project/pull/89951
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[llvm-branch-commits] [clang] [release/18.x][COFF][Aarch64] Add _InterlockedAdd64 intrinsic (#81849) (PR #89951)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello closed 
https://github.com/llvm/llvm-project/pull/89951
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