[llvm-branch-commits] [llvm] release/18.x: [SystemZ] Handle address clobbering in splitMove(). (#92105) (PR #92221)
https://github.com/JonPsson1 approved this pull request. https://github.com/llvm/llvm-project/pull/92221 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [lld] [llvm] [openmp] SystemZ release notes for 18.x. (PR #84560)
JonPsson1 wrote: @tstellar This is intended for the 18-rel branch... https://github.com/llvm/llvm-project/pull/84560 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [lld] [llvm] [openmp] SystemZ release notes for 18.x. (PR #84560)
https://github.com/JonPsson1 updated
https://github.com/llvm/llvm-project/pull/84560
>From a4534dec8267040d1dc6ab887a20893e302b7300 Mon Sep 17 00:00:00 2001
From: Jonas Paulsson
Date: Fri, 8 Mar 2024 15:28:56 -0500
Subject: [PATCH] SystemZ release notes. llvm-objcopy and openmp release notes
---
clang/docs/ReleaseNotes.rst | 5 +
lld/docs/ReleaseNotes.rst| 5 +
llvm/docs/ReleaseNotes.rst | 11 +++
openmp/docs/ReleaseNotes.rst | 2 ++
4 files changed, 23 insertions(+)
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index fc27297aea2d6c..6a038ed4b635c7 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1325,6 +1325,11 @@ AIX Support
or newer. Similar to the LTO support on AIX, ThinLTO is implemented with
the libLTO.so plugin.
+SystemZ Support
+^^^
+- Properly support 16 byte atomic int/fp types and ops. Atomic __int128 (and
+ long double) variables are now aligned to 16 bytes by default (like gcc 14).
+
WebAssembly Support
^^^
diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst
index 56ba3463aeadc0..6ada711a20a6da 100644
--- a/lld/docs/ReleaseNotes.rst
+++ b/lld/docs/ReleaseNotes.rst
@@ -163,5 +163,10 @@ WebAssembly Improvements
is read from object files within the archive. This matches the behaviour of
the ELF linker.
+SystemZ
+---
+
+* Add target support for SystemZ (s390x).
+
Fixes
#
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 5b3210138f2f89..27d305d36199e7 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -215,6 +215,17 @@ Changes to the RISC-V Backend
* ``-mcpu=sifive-p670`` was added.
* Support for the Zicond extension is no longer experimental.
+Changes to the SystemZ Backend
+--
+
+* Properly support 16 byte atomic int/fp types and ops.
+* Support i128 as legal type in VRs.
+* Add an i128 cost model.
+* Support building individual functions with backchain using the
+ __attribute__((target("backchain"))) syntax.
+* Add exception handling for XPLINK.
+* Add support for llvm-objcopy.
+
Changes to the WebAssembly Backend
--
diff --git a/openmp/docs/ReleaseNotes.rst b/openmp/docs/ReleaseNotes.rst
index 3eeaf5c900d800..a5b39f61b0b64c 100644
--- a/openmp/docs/ReleaseNotes.rst
+++ b/openmp/docs/ReleaseNotes.rst
@@ -19,3 +19,5 @@ from the `LLVM releases web site
[llvm-branch-commits] [clang] [lld] [llvm] [openmp] SystemZ release notes for 18.x. (PR #84560)
https://github.com/JonPsson1 updated
https://github.com/llvm/llvm-project/pull/84560
>From a4534dec8267040d1dc6ab887a20893e302b7300 Mon Sep 17 00:00:00 2001
From: Jonas Paulsson
Date: Fri, 8 Mar 2024 15:28:56 -0500
Subject: [PATCH] SystemZ release notes. llvm-objcopy and openmp release notes
---
clang/docs/ReleaseNotes.rst | 5 +
lld/docs/ReleaseNotes.rst| 5 +
llvm/docs/ReleaseNotes.rst | 11 +++
openmp/docs/ReleaseNotes.rst | 2 ++
4 files changed, 23 insertions(+)
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index fc27297aea2d6c..6a038ed4b635c7 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1325,6 +1325,11 @@ AIX Support
or newer. Similar to the LTO support on AIX, ThinLTO is implemented with
the libLTO.so plugin.
+SystemZ Support
+^^^
+- Properly support 16 byte atomic int/fp types and ops. Atomic __int128 (and
+ long double) variables are now aligned to 16 bytes by default (like gcc 14).
+
WebAssembly Support
^^^
diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst
index 56ba3463aeadc0..6ada711a20a6da 100644
--- a/lld/docs/ReleaseNotes.rst
+++ b/lld/docs/ReleaseNotes.rst
@@ -163,5 +163,10 @@ WebAssembly Improvements
is read from object files within the archive. This matches the behaviour of
the ELF linker.
+SystemZ
+---
+
+* Add target support for SystemZ (s390x).
+
Fixes
#
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 5b3210138f2f89..27d305d36199e7 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -215,6 +215,17 @@ Changes to the RISC-V Backend
* ``-mcpu=sifive-p670`` was added.
* Support for the Zicond extension is no longer experimental.
+Changes to the SystemZ Backend
+--
+
+* Properly support 16 byte atomic int/fp types and ops.
+* Support i128 as legal type in VRs.
+* Add an i128 cost model.
+* Support building individual functions with backchain using the
+ __attribute__((target("backchain"))) syntax.
+* Add exception handling for XPLINK.
+* Add support for llvm-objcopy.
+
Changes to the WebAssembly Backend
--
diff --git a/openmp/docs/ReleaseNotes.rst b/openmp/docs/ReleaseNotes.rst
index 3eeaf5c900d800..a5b39f61b0b64c 100644
--- a/openmp/docs/ReleaseNotes.rst
+++ b/openmp/docs/ReleaseNotes.rst
@@ -19,3 +19,5 @@ from the `LLVM releases web site
[llvm-branch-commits] [clang] [lld] [llvm] [openmp] SystemZ release notes for 18.x. (PR #84560)
JonPsson1 wrote: Looks like https://github.com/llvm/llvm-project/pull/73511 "munaligned-symbols" 34dd8ec never made it into the 18-release branch... https://github.com/llvm/llvm-project/pull/84560 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [lld] [llvm] [openmp] SystemZ release notes for 18.x. (PR #84560)
https://github.com/JonPsson1 updated
https://github.com/llvm/llvm-project/pull/84560
>From 639dceb13cf824e3f4e0f627becf8fb8f5ecb29c Mon Sep 17 00:00:00 2001
From: Jonas Paulsson
Date: Fri, 8 Mar 2024 15:28:56 -0500
Subject: [PATCH 1/2] SystemZ release notes.
---
clang/docs/ReleaseNotes.rst | 5 +
lld/docs/ReleaseNotes.rst | 5 +
llvm/docs/ReleaseNotes.rst | 10 ++
3 files changed, 20 insertions(+)
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index fc27297aea2d6c..6a038ed4b635c7 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1325,6 +1325,11 @@ AIX Support
or newer. Similar to the LTO support on AIX, ThinLTO is implemented with
the libLTO.so plugin.
+SystemZ Support
+^^^
+- Properly support 16 byte atomic int/fp types and ops. Atomic __int128 (and
+ long double) variables are now aligned to 16 bytes by default (like gcc 14).
+
WebAssembly Support
^^^
diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst
index 56ba3463aeadc0..6ada711a20a6da 100644
--- a/lld/docs/ReleaseNotes.rst
+++ b/lld/docs/ReleaseNotes.rst
@@ -163,5 +163,10 @@ WebAssembly Improvements
is read from object files within the archive. This matches the behaviour of
the ELF linker.
+SystemZ
+---
+
+* Add target support for SystemZ (s390x).
+
Fixes
#
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 5b3210138f2f89..7cfa83fc8b0565 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -215,6 +215,16 @@ Changes to the RISC-V Backend
* ``-mcpu=sifive-p670`` was added.
* Support for the Zicond extension is no longer experimental.
+Changes to the SystemZ Backend
+--
+
+* Properly support 16 byte atomic int/fp types and ops.
+* Support i128 as legal type in VRs.
+* Add an i128 cost model.
+* Support building individual functions with backchain using the
+ __attribute__((target("backchain"))) syntax.
+* Add exception handling for XPLINK.
+
Changes to the WebAssembly Backend
--
>From 1588c515a1dfddbf9f6e1b8e67f4500aba22ee92 Mon Sep 17 00:00:00 2001
From: Jonas Paulsson
Date: Mon, 11 Mar 2024 09:28:14 -0400
Subject: [PATCH 2/2] llvm-objcopy and openmp release notes
---
llvm/docs/ReleaseNotes.rst | 1 +
openmp/docs/ReleaseNotes.rst | 2 ++
2 files changed, 3 insertions(+)
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 7cfa83fc8b0565..27d305d36199e7 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -224,6 +224,7 @@ Changes to the SystemZ Backend
* Support building individual functions with backchain using the
__attribute__((target("backchain"))) syntax.
* Add exception handling for XPLINK.
+* Add support for llvm-objcopy.
Changes to the WebAssembly Backend
--
diff --git a/openmp/docs/ReleaseNotes.rst b/openmp/docs/ReleaseNotes.rst
index 3eeaf5c900d800..a5b39f61b0b64c 100644
--- a/openmp/docs/ReleaseNotes.rst
+++ b/openmp/docs/ReleaseNotes.rst
@@ -19,3 +19,5 @@ from the `LLVM releases web site
[llvm-branch-commits] [clang] [lld] [llvm] SystemZ release notes for 18.x. (PR #84560)
https://github.com/JonPsson1 updated
https://github.com/llvm/llvm-project/pull/84560
>From 639dceb13cf824e3f4e0f627becf8fb8f5ecb29c Mon Sep 17 00:00:00 2001
From: Jonas Paulsson
Date: Fri, 8 Mar 2024 15:28:56 -0500
Subject: [PATCH] SystemZ release notes.
---
clang/docs/ReleaseNotes.rst | 5 +
lld/docs/ReleaseNotes.rst | 5 +
llvm/docs/ReleaseNotes.rst | 10 ++
3 files changed, 20 insertions(+)
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index fc27297aea2d6c..6a038ed4b635c7 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1325,6 +1325,11 @@ AIX Support
or newer. Similar to the LTO support on AIX, ThinLTO is implemented with
the libLTO.so plugin.
+SystemZ Support
+^^^
+- Properly support 16 byte atomic int/fp types and ops. Atomic __int128 (and
+ long double) variables are now aligned to 16 bytes by default (like gcc 14).
+
WebAssembly Support
^^^
diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst
index 56ba3463aeadc0..6ada711a20a6da 100644
--- a/lld/docs/ReleaseNotes.rst
+++ b/lld/docs/ReleaseNotes.rst
@@ -163,5 +163,10 @@ WebAssembly Improvements
is read from object files within the archive. This matches the behaviour of
the ELF linker.
+SystemZ
+---
+
+* Add target support for SystemZ (s390x).
+
Fixes
#
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 5b3210138f2f89..7cfa83fc8b0565 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -215,6 +215,16 @@ Changes to the RISC-V Backend
* ``-mcpu=sifive-p670`` was added.
* Support for the Zicond extension is no longer experimental.
+Changes to the SystemZ Backend
+--
+
+* Properly support 16 byte atomic int/fp types and ops.
+* Support i128 as legal type in VRs.
+* Add an i128 cost model.
+* Support building individual functions with backchain using the
+ __attribute__((target("backchain"))) syntax.
+* Add exception handling for XPLINK.
+
Changes to the WebAssembly Backend
--
___
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[llvm-branch-commits] [clang] [lld] [llvm] SystemZ release notes for 18.x. (PR #84560)
https://github.com/JonPsson1 created
https://github.com/llvm/llvm-project/pull/84560
None
>From b6bd83cace58517531380eb4e34594bddc973153 Mon Sep 17 00:00:00 2001
From: Jonas Paulsson
Date: Fri, 8 Mar 2024 15:28:56 -0500
Subject: [PATCH] SystemZ release notes.
---
clang/docs/ReleaseNotes.rst | 5 +
lld/docs/ReleaseNotes.rst | 6 ++
llvm/docs/ReleaseNotes.rst | 10 ++
3 files changed, 21 insertions(+)
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index fc27297aea2d6c..6a038ed4b635c7 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1325,6 +1325,11 @@ AIX Support
or newer. Similar to the LTO support on AIX, ThinLTO is implemented with
the libLTO.so plugin.
+SystemZ Support
+^^^
+- Properly support 16 byte atomic int/fp types and ops. Atomic __int128 (and
+ long double) variables are now aligned to 16 bytes by default (like gcc 14).
+
WebAssembly Support
^^^
diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst
index 56ba3463aeadc0..4de33363d0532b 100644
--- a/lld/docs/ReleaseNotes.rst
+++ b/lld/docs/ReleaseNotes.rst
@@ -163,5 +163,11 @@ WebAssembly Improvements
is read from object files within the archive. This matches the behaviour of
the ELF linker.
+SystemZ
+---
+
+* Add target support for SystemZ (s390x).
+
+
Fixes
#
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 5b3210138f2f89..7cfa83fc8b0565 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -215,6 +215,16 @@ Changes to the RISC-V Backend
* ``-mcpu=sifive-p670`` was added.
* Support for the Zicond extension is no longer experimental.
+Changes to the SystemZ Backend
+--
+
+* Properly support 16 byte atomic int/fp types and ops.
+* Support i128 as legal type in VRs.
+* Add an i128 cost model.
+* Support building individual functions with backchain using the
+ __attribute__((target("backchain"))) syntax.
+* Add exception handling for XPLINK.
+
Changes to the WebAssembly Backend
--
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[llvm-branch-commits] [llvm] da11d2a - [SystemZ] Clear NW flags on an ISD::SUB when reused as comparison.
Author: Jonas Paulsson
Date: 2023-03-14T19:44:02+01:00
New Revision: da11d2aaa7b7e89e33cda733e3299ece1efa2cdc
URL:
https://github.com/llvm/llvm-project/commit/da11d2aaa7b7e89e33cda733e3299ece1efa2cdc
DIFF:
https://github.com/llvm/llvm-project/commit/da11d2aaa7b7e89e33cda733e3299ece1efa2cdc.diff
LOG: [SystemZ] Clear NW flags on an ISD::SUB when reused as comparison.
The SystemZ backend will try to reuse an existing subtraction of two values
whenever they are to be compared for equality. This depends on the SystemZ
subtraction instruction setting the condition code, which can also signal
overflow.
A later pass will remove the compare and reuse the CC from the subtraction
directly. However, if that subtraction has the NSW flag set it will not
include the overflow bit in the updated CC user. That was a bug which can
lead to wrong results, as shown by a csmith program.
Fixes: https://github.com/llvm/llvm-project/issues/61268
Reviewed By: nikic, uweigand
Differential Revision: https://reviews.llvm.org/D145811
Added:
llvm/test/CodeGen/SystemZ/int-cmp-62.ll
Modified:
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
Removed:
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 04ba0db75789..350819488714 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -2423,6 +2423,12 @@ static void adjustForSubtraction(SelectionDAG ,
const SDLoc ,
if (N->getOpcode() == ISD::SUB &&
((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
(N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
+// Disable the nsw and nuw flags: the backend needs to handle
+// overflow as well during comparison elimination.
+SDNodeFlags Flags = N->getFlags();
+Flags.setNoSignedWrap(false);
+Flags.setNoUnsignedWrap(false);
+N->setFlags(Flags);
C.Op0 = SDValue(N, 0);
C.Op1 = DAG.getConstant(0, DL, N->getValueType(0));
return;
diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-62.ll
b/llvm/test/CodeGen/SystemZ/int-cmp-62.ll
new file mode 100644
index ..c57cf5777d0f
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/int-cmp-62.ll
@@ -0,0 +1,39 @@
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
+;
+; Test that a CC result of a sub that can overflow is tested with the right
predicate.
+
+define i32 @fun0(i32 %a, i32 %b, ptr %dest) {
+; CHECK-LABEL: fun0
+; CHECK: s %r2, 0(%r4)
+; CHECK: bner %r14
+entry:
+ %cur = load i32, ptr %dest
+ %res = sub nsw i32 %a, %cur
+ %cmp = icmp ne i32 %a, %cur
+ br i1 %cmp, label %exit, label %store
+
+store:
+ store i32 %b, ptr %dest
+ br label %exit
+
+exit:
+ ret i32 %res
+}
+
+define i32 @fun1(i32 %a, i32 %b, ptr %dest) {
+; CHECK-LABEL: fun1
+; CHECK: s %r2, 0(%r4)
+; CHECK: bner %r14
+entry:
+ %cur = load i32, ptr %dest
+ %res = sub nuw i32 %a, %cur
+ %cmp = icmp ne i32 %a, %cur
+ br i1 %cmp, label %exit, label %store
+
+store:
+ store i32 %b, ptr %dest
+ br label %exit
+
+exit:
+ ret i32 %res
+}
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[llvm-branch-commits] [llvm] ca7d6a6 - SystemZ release notes
Author: Jonas Paulsson Date: 2023-02-01T17:38:48+01:00 New Revision: ca7d6a62b68876c6c6bdb19b207413e34535ca19 URL: https://github.com/llvm/llvm-project/commit/ca7d6a62b68876c6c6bdb19b207413e34535ca19 DIFF: https://github.com/llvm/llvm-project/commit/ca7d6a62b68876c6c6bdb19b207413e34535ca19.diff LOG: SystemZ release notes Reviewed By: Ulrich Weigand Differential Revision: https://reviews.llvm.org/D142987 Added: Modified: llvm/docs/ReleaseNotes.rst Removed: diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 90c682fd9c7a..239d9e3b4374 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -203,6 +203,13 @@ Changes to the RISC-V Backend LoopStrengthReduce for loops with i32 induction variables, among other optimizations. +Changes to the SystemZ Backend +-- + +* The datalayout string now only depends on the target triple as expected. +* The GNU attribute for a visible vector ABI is now emitted. +* Align 128 bit integers to 8 bytes only, per the ABI. + Changes to the WebAssembly Backend -- ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] ddd0384 - [SystemZ] Clear Available set in SystemZPostRASchedStrategy::initialize().
Author: Jonas Paulsson
Date: 2021-01-13T18:18:27-06:00
New Revision: ddd03842c3472fedf164274c479272089c426ee5
URL:
https://github.com/llvm/llvm-project/commit/ddd03842c3472fedf164274c479272089c426ee5
DIFF:
https://github.com/llvm/llvm-project/commit/ddd03842c3472fedf164274c479272089c426ee5.diff
LOG: [SystemZ] Clear Available set in SystemZPostRASchedStrategy::initialize().
This needs to be done in order to not crash with -misched-cutoff.
Fixes https://bugs.llvm.org/show_bug.cgi?id=45928
Review: Ulrich Weigand
Differential Revision: https://reviews.llvm.org/D94383
Added:
llvm/test/CodeGen/SystemZ/misched-cutoff.ll
Modified:
llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
Removed:
diff --git a/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
b/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
index 3fc25034dded..9bee5e8d1864 100644
--- a/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
@@ -72,6 +72,7 @@ advanceTo(MachineBasicBlock::iterator NextBegin) {
}
void SystemZPostRASchedStrategy::initialize(ScheduleDAGMI *dag) {
+ Available.clear(); // -misched-cutoff.
LLVM_DEBUG(HazardRec->dumpState(););
}
diff --git a/llvm/test/CodeGen/SystemZ/misched-cutoff.ll
b/llvm/test/CodeGen/SystemZ/misched-cutoff.ll
new file mode 100644
index ..0de80a22c301
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/misched-cutoff.ll
@@ -0,0 +1,49 @@
+; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -misched-cutoff=1 -o /dev/null <
%s
+;
+; Test that the post-ra scheduler does not crash with -misched-cutoff.
+
+@g_184 = external dso_local global i16, align 2
+@g_294 = external dso_local global [1 x [9 x i32*]], align 8
+
+define void @fun() {
+bb:
+ br label %bb1
+
+bb1: ; preds = %bb1, %bb
+ %i = phi i64 [ 0, %bb ], [ %i22, %bb1 ]
+ %i2 = trunc i64 %i to i32
+ %i3 = lshr i32 %i2, 1
+ %i4 = select i1 false, i32 %i3, i32 undef
+ %i5 = lshr i32 %i4, 1
+ %i6 = xor i32 %i5, -306674912
+ %i7 = select i1 undef, i32 %i5, i32 %i6
+ %i8 = lshr i32 %i7, 1
+ %i9 = xor i32 %i8, -306674912
+ %i10 = select i1 undef, i32 %i8, i32 %i9
+ %i11 = lshr i32 %i10, 1
+ %i12 = xor i32 %i11, -306674912
+ %i13 = select i1 undef, i32 %i11, i32 %i12
+ %i14 = lshr i32 %i13, 1
+ %i15 = select i1 false, i32 %i14, i32 undef
+ %i16 = lshr i32 %i15, 1
+ %i17 = select i1 false, i32 %i16, i32 undef
+ %i18 = lshr i32 %i17, 1
+ %i19 = select i1 false, i32 %i18, i32 undef
+ %i20 = lshr i32 %i19, 1
+ %i21 = select i1 false, i32 %i20, i32 undef
+ store i32 %i21, i32* undef, align 4
+ %i22 = add nuw nsw i64 %i, 1
+ %i23 = icmp ult i64 %i, 255
+ br i1 %i23, label %bb1, label %bb24
+
+bb24: ; preds = %bb1
+ %i25 = load volatile i16, i16* undef
+ store i32* null, i32** undef, align 8
+ store i32 -10, i32* undef, align 4
+ store i32 -10, i32* null, align 4
+ store i32 -10, i32* undef, align 4
+ store i16 0, i16* @g_184, align 2
+ store i32* null, i32** getelementptr inbounds ([1 x [9 x i32*]], [1 x [9 x
i32*]]* @g_294, i64 0, i64 0, i64 2), align 8
+ store i32* null, i32** getelementptr inbounds ([1 x [9 x i32*]], [1 x [9 x
i32*]]* @g_294, i64 0, i64 0, i64 5), align 8
+ unreachable
+}
___
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[llvm-branch-commits] [llvm] 171771e - [SystemZ] Minor NFC fix in SchedModels.
Author: Jonas Paulsson Date: 2021-01-11T11:38:23-06:00 New Revision: 171771e0780fd5d028a24f8650a11299478df266 URL: https://github.com/llvm/llvm-project/commit/171771e0780fd5d028a24f8650a11299478df266 DIFF: https://github.com/llvm/llvm-project/commit/171771e0780fd5d028a24f8650a11299478df266.diff LOG: [SystemZ] Minor NFC fix in SchedModels. The unused LRMux opcode was removed by 8f8c381, but a regexp still matched for it in the scheduler files which is now removed. Review: Ulrich Weigand Added: Modified: llvm/lib/Target/SystemZ/SystemZScheduleZ13.td llvm/lib/Target/SystemZ/SystemZScheduleZ14.td llvm/lib/Target/SystemZ/SystemZScheduleZ15.td llvm/lib/Target/SystemZ/SystemZScheduleZ196.td llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td Removed: diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td index b3266051da4e1..de49106a5a601 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td @@ -204,7 +204,7 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLIL(F|H|L)$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "LG(F|H)I$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "LHI(Mux)?$")>; -def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR(Mux)?$")>; +def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR$")>; // Load and zero rightmost byte def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LZR(F|G)$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td index df7282a2961b8..5ea269cb891d6 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td @@ -205,7 +205,7 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLIL(F|H|L)$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "LG(F|H)I$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "LHI(Mux)?$")>; -def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR(Mux)?$")>; +def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR$")>; // Load and zero rightmost byte def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LZR(F|G)$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td index 56ceb88f35d4f..6a28aec6f846e 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td @@ -206,7 +206,7 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLIL(F|H|L)$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "LG(F|H)I$")>; def : InstRW<[WLat1, FXa, NormalGr], (instregex "LHI(Mux)?$")>; -def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR(Mux)?$")>; +def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR$")>; // Load and zero rightmost byte def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LZR(F|G)$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td index ca714ef1a702b..9a306591a34f7 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td @@ -182,7 +182,7 @@ def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLIL(F|H|L)$")>; def : InstRW<[WLat1, FXU, NormalGr], (instregex "LG(F|H)I$")>; def : InstRW<[WLat1, FXU, NormalGr], (instregex "LHI(Mux)?$")>; -def : InstRW<[WLat1, FXU, NormalGr], (instregex "LR(Mux)?$")>; +def : InstRW<[WLat1, FXU, NormalGr], (instregex "LR$")>; // Load and test def : InstRW<[WLat1LSU, WLat1LSU, LSU, FXU, NormalGr], (instregex "LT(G)?$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td index fb226be678dad..f3ff1dfaba75c 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td @@ -187,7 +187,7 @@ def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLIL(F|H|L)$")>; def : InstRW<[WLat1, FXU, NormalGr], (instregex "LG(F|H)I$")>; def : InstRW<[WLat1, FXU, NormalGr], (instregex "LHI(Mux)?$")>; -def : InstRW<[WLat1, FXU, NormalGr], (instregex "LR(Mux)?$")>; +def : InstRW<[WLat1, FXU, NormalGr], (instregex "LR$")>; // Load and trap def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "L(FH|G)?AT$")>; ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 653b976 - [SystemZ] Improve handling of backchain offset.
Author: Jonas Paulsson
Date: 2020-12-14T12:39:38-06:00
New Revision: 653b97690f0d5c26a93002fb94ddd86397ed6c1c
URL:
https://github.com/llvm/llvm-project/commit/653b97690f0d5c26a93002fb94ddd86397ed6c1c
DIFF:
https://github.com/llvm/llvm-project/commit/653b97690f0d5c26a93002fb94ddd86397ed6c1c.diff
LOG: [SystemZ] Improve handling of backchain offset.
- New function SDValue getBackchainAddress() used by
lowerDYNAMIC_STACKALLOC() and lowerSTACKRESTORE() to properly handle the
backchain offset also with packed-stack.
- Make a common function getBackchainOffset() for the computation of the
backchain offset and use in some places (NFC).
Review: Ulrich Weigand
Differential Revision: https://reviews.llvm.org/D93171
Added:
Modified:
llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
llvm/lib/Target/SystemZ/SystemZFrameLowering.h
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/lib/Target/SystemZ/SystemZISelLowering.h
llvm/test/CodeGen/SystemZ/backchain.ll
Removed:
diff --git a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
index d9e030de5af8..994f471b75b1 100644
--- a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
@@ -511,13 +511,10 @@ void SystemZFrameLowering::emitPrologue(MachineFunction
,
.addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D);
emitIncrement(MBB, MBBI, DL, SystemZ::R15D, Delta, ZII);
buildCFAOffs(MBB, MBBI, DL, SPOffsetFromCFA + Delta, ZII);
- if (StoreBackchain) {
-// The back chain is stored topmost with packed-stack.
-int Offset = usePackedStack(MF) ? SystemZMC::CallFrameSize - 8 : 0;
+ if (StoreBackchain)
BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG))
.addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D)
- .addImm(Offset).addReg(0);
- }
+ .addImm(getBackchainOffset(MF)).addReg(0);
}
SPOffsetFromCFA += Delta;
}
@@ -709,13 +706,10 @@ void
SystemZFrameLowering::inlineStackProbe(MachineFunction ,
if (Residual)
allocateAndProbe(*MBB, MBBI, Residual, true/*EmitCFI*/);
- if (StoreBackchain) {
-// The back chain is stored topmost with packed-stack.
-int Offset = usePackedStack(MF) ? SystemZMC::CallFrameSize - 8 : 0;
+ if (StoreBackchain)
BuildMI(*MBB, MBBI, DL, ZII->get(SystemZ::STG))
.addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D)
- .addImm(Offset).addReg(0);
- }
+ .addImm(getBackchainOffset(MF)).addReg(0);
StackAllocMI->eraseFromParent();
if (DoneMBB != nullptr) {
@@ -790,8 +784,7 @@ getOrCreateFramePointerSaveIndex(MachineFunction ) const
{
int FI = ZFI->getFramePointerSaveIndex();
if (!FI) {
MachineFrameInfo = MF.getFrameInfo();
-// The back chain is stored topmost with packed-stack.
-int Offset = usePackedStack(MF) ? -8 : -SystemZMC::CallFrameSize;
+int Offset = getBackchainOffset(MF) - SystemZMC::CallFrameSize;
FI = MFFrame.CreateFixedObject(8, Offset, false);
ZFI->setFramePointerSaveIndex(FI);
}
diff --git a/llvm/lib/Target/SystemZ/SystemZFrameLowering.h
b/llvm/lib/Target/SystemZ/SystemZFrameLowering.h
index 001d26d4d3bb..085c31ca0f18 100644
--- a/llvm/lib/Target/SystemZ/SystemZFrameLowering.h
+++ b/llvm/lib/Target/SystemZ/SystemZFrameLowering.h
@@ -9,6 +9,7 @@
#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZFRAMELOWERING_H
#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZFRAMELOWERING_H
+#include "MCTargetDesc/SystemZMCTargetDesc.h"
#include "llvm/ADT/IndexedMap.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/Support/TypeSize.h"
@@ -63,6 +64,12 @@ class SystemZFrameLowering : public TargetFrameLowering {
int getOrCreateFramePointerSaveIndex(MachineFunction ) const;
bool usePackedStack(MachineFunction ) const;
+
+ // Return the offset of the backchain.
+ unsigned getBackchainOffset(MachineFunction ) const {
+// The back chain is stored topmost with packed-stack.
+return usePackedStack(MF) ? SystemZMC::CallFrameSize - 8 : 0;
+ }
};
} // end namespace llvm
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 812fe80864ac..663af1d64943 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -3435,7 +3435,8 @@ lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG )
const {
// If we need a backchain, save it now.
SDValue Backchain;
if (StoreBackchain)
-Backchain = DAG.getLoad(MVT::i64, DL, Chain, OldSP, MachinePointerInfo());
+Backchain = DAG.getLoad(MVT::i64, DL, Chain, getBackchainAddress(OldSP,
DAG),
+MachinePointerInfo());
// Add extra space for alignment if needed.
if (ExtraAlignSpace)
@@ -3472,7 +3473,8 @@
[llvm-branch-commits] [llvm] 42f628c - Reapply "[SystemZFrameLowering] Don't overrwrite R1D (backchain) when probing."
Author: Jonas Paulsson
Date: 2020-12-11T18:25:47-06:00
New Revision: 42f628c8426958daececdd997869024aedc0a068
URL:
https://github.com/llvm/llvm-project/commit/42f628c8426958daececdd997869024aedc0a068
DIFF:
https://github.com/llvm/llvm-project/commit/42f628c8426958daececdd997869024aedc0a068.diff
LOG: Reapply "[SystemZFrameLowering] Don't overrwrite R1D (backchain) when
probing."
Fixed to properly compute the live-in lists of new blocks.
Review: Ulrich Weigand
Differential Revision: https://reviews.llvm.org/D92803
Added:
Modified:
llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
llvm/test/CodeGen/SystemZ/stack-clash-dynamic-alloca.ll
llvm/test/CodeGen/SystemZ/stack-clash-protection.ll
Removed:
diff --git a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
index 57529c8685de..d9e030de5af8 100644
--- a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
@@ -488,15 +488,6 @@ void SystemZFrameLowering::emitPrologue(MachineFunction
,
MFFrame.setStackSize(StackSize);
if (StackSize) {
-// Determine if we want to store a backchain.
-bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");
-
-// If we need backchain, save current stack pointer. R1 is free at this
-// point.
-if (StoreBackchain)
- BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR))
-.addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D);
-
// Allocate StackSize bytes.
int64_t Delta = -int64_t(StackSize);
const unsigned ProbeSize = TLI.getStackProbeSize(MF);
@@ -512,18 +503,23 @@ void SystemZFrameLowering::emitPrologue(MachineFunction
,
.addImm(StackSize);
}
else {
+ bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");
+ // If we need backchain, save current stack pointer. R1 is free at
+ // this point.
+ if (StoreBackchain)
+BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR))
+ .addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D);
emitIncrement(MBB, MBBI, DL, SystemZ::R15D, Delta, ZII);
buildCFAOffs(MBB, MBBI, DL, SPOffsetFromCFA + Delta, ZII);
+ if (StoreBackchain) {
+// The back chain is stored topmost with packed-stack.
+int Offset = usePackedStack(MF) ? SystemZMC::CallFrameSize - 8 : 0;
+BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG))
+ .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D)
+ .addImm(Offset).addReg(0);
+ }
}
SPOffsetFromCFA += Delta;
-
-if (StoreBackchain) {
- // The back chain is stored topmost with packed-stack.
- int Offset = usePackedStack(MF) ? SystemZMC::CallFrameSize - 8 : 0;
- BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG))
-.addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D)
-.addImm(Offset).addReg(0);
-}
}
if (HasFP) {
@@ -668,6 +664,13 @@ void
SystemZFrameLowering::inlineStackProbe(MachineFunction ,
.addMemOperand(MMO);
};
+ bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");
+ if (StoreBackchain)
+BuildMI(*MBB, MBBI, DL, ZII->get(SystemZ::LGR))
+ .addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D);
+
+ MachineBasicBlock *DoneMBB = nullptr;
+ MachineBasicBlock *LoopMBB = nullptr;
if (NumFullBlocks < 3) {
// Emit unrolled probe statements.
for (unsigned int i = 0; i < NumFullBlocks; i++)
@@ -677,15 +680,16 @@ void
SystemZFrameLowering::inlineStackProbe(MachineFunction ,
uint64_t LoopAlloc = ProbeSize * NumFullBlocks;
SPOffsetFromCFA -= LoopAlloc;
-BuildMI(*MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R1D)
+// Use R0D to hold the exit value.
+BuildMI(*MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R0D)
.addReg(SystemZ::R15D);
-buildDefCFAReg(*MBB, MBBI, DL, SystemZ::R1D, ZII);
-emitIncrement(*MBB, MBBI, DL, SystemZ::R1D, -int64_t(LoopAlloc), ZII);
+buildDefCFAReg(*MBB, MBBI, DL, SystemZ::R0D, ZII);
+emitIncrement(*MBB, MBBI, DL, SystemZ::R0D, -int64_t(LoopAlloc), ZII);
buildCFAOffs(*MBB, MBBI, DL, -int64_t(SystemZMC::CallFrameSize +
LoopAlloc),
ZII);
-MachineBasicBlock *DoneMBB = SystemZ::splitBlockBefore(MBBI, MBB);
-MachineBasicBlock *LoopMBB = SystemZ::emitBlockAfter(MBB);
+DoneMBB = SystemZ::splitBlockBefore(MBBI, MBB);
+LoopMBB = SystemZ::emitBlockAfter(MBB);
MBB->addSuccessor(LoopMBB);
LoopMBB->addSuccessor(LoopMBB);
LoopMBB->addSuccessor(DoneMBB);
@@ -693,22 +697,32 @@ void
SystemZFrameLowering::inlineStackProbe(MachineFunction ,
MBB = LoopMBB;
allocateAndProbe(*MBB, MBB->end(), ProbeSize, false/*EmitCFI*/);
BuildMI(*MBB, MBB->end(), DL, ZII->get(SystemZ::CLGR))
- .addReg(SystemZ::R15D).addReg(SystemZ::R1D);
+
[llvm-branch-commits] [llvm] 0c2d239 - [SystemZTTIImpl] Allow some non-prefetched accesses in getMinPrefetchStride().
Author: Jonas Paulsson Date: 2020-12-11T18:06:07-06:00 New Revision: 0c2d23933f06ed048191f84ecde889e9da93609c URL: https://github.com/llvm/llvm-project/commit/0c2d23933f06ed048191f84ecde889e9da93609c DIFF: https://github.com/llvm/llvm-project/commit/0c2d23933f06ed048191f84ecde889e9da93609c.diff LOG: [SystemZTTIImpl] Allow some non-prefetched accesses in getMinPrefetchStride(). The performance improvement on LBM previously achieved with improved software prefetching (36d4421) have gone lost recently with e00f189. There now is one memory access in the loop that LoopDataPrefetch cannot handle (while before there was none) which the heuristic rejects. This patch adds a small margin by allowing 1 non-prefetched memory access for every 32 prefetched ones, so that the heuristic doesn't bail in this type of case. Review: Ulrich Weigand Differential Revision: https://reviews.llvm.org/D92985 Added: Modified: llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp Removed: diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp index 2c6659b79cc3..e7ac2391512f 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp @@ -341,8 +341,8 @@ unsigned SystemZTTIImpl::getMinPrefetchStride(unsigned NumMemAccesses, // Emit prefetch instructions for smaller strides in cases where we think // the hardware prefetcher might not be able to keep up. - if (NumStridedMemAccesses > 32 && - NumStridedMemAccesses == NumMemAccesses && !HasCall) + if (NumStridedMemAccesses > 32 && !HasCall && + (NumMemAccesses - NumStridedMemAccesses) * 32 <= NumStridedMemAccesses) return 1; return ST->hasMiscellaneousExtensions3() ? 8192 : 2048; ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] bc7a61b - Revert "[SystemZFrameLowering] Don't overrwrite R1D (backchain) when probing."
Author: Jonas Paulsson
Date: 2020-12-10T18:05:51-06:00
New Revision: bc7a61b7036044636f9a2c91c916153532a551f8
URL:
https://github.com/llvm/llvm-project/commit/bc7a61b7036044636f9a2c91c916153532a551f8
DIFF:
https://github.com/llvm/llvm-project/commit/bc7a61b7036044636f9a2c91c916153532a551f8.diff
LOG: Revert "[SystemZFrameLowering] Don't overrwrite R1D (backchain) when
probing."
Temporarily reverted.
This reverts commit ea475c77ff9eab1de7d44684c8fb453b39f70081.
Added:
Modified:
llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
llvm/test/CodeGen/SystemZ/stack-clash-dynamic-alloca.ll
llvm/test/CodeGen/SystemZ/stack-clash-protection.ll
Removed:
diff --git a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
index 0bfab129edb1..57529c8685de 100644
--- a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
@@ -488,6 +488,15 @@ void SystemZFrameLowering::emitPrologue(MachineFunction
,
MFFrame.setStackSize(StackSize);
if (StackSize) {
+// Determine if we want to store a backchain.
+bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");
+
+// If we need backchain, save current stack pointer. R1 is free at this
+// point.
+if (StoreBackchain)
+ BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR))
+.addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D);
+
// Allocate StackSize bytes.
int64_t Delta = -int64_t(StackSize);
const unsigned ProbeSize = TLI.getStackProbeSize(MF);
@@ -503,23 +512,18 @@ void SystemZFrameLowering::emitPrologue(MachineFunction
,
.addImm(StackSize);
}
else {
- bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");
- // If we need backchain, save current stack pointer. R1 is free at
- // this point.
- if (StoreBackchain)
-BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR))
- .addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D);
emitIncrement(MBB, MBBI, DL, SystemZ::R15D, Delta, ZII);
buildCFAOffs(MBB, MBBI, DL, SPOffsetFromCFA + Delta, ZII);
- if (StoreBackchain) {
-// The back chain is stored topmost with packed-stack.
-int Offset = usePackedStack(MF) ? SystemZMC::CallFrameSize - 8 : 0;
-BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG))
- .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D)
- .addImm(Offset).addReg(0);
- }
}
SPOffsetFromCFA += Delta;
+
+if (StoreBackchain) {
+ // The back chain is stored topmost with packed-stack.
+ int Offset = usePackedStack(MF) ? SystemZMC::CallFrameSize - 8 : 0;
+ BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG))
+.addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D)
+.addImm(Offset).addReg(0);
+}
}
if (HasFP) {
@@ -664,11 +668,6 @@ void
SystemZFrameLowering::inlineStackProbe(MachineFunction ,
.addMemOperand(MMO);
};
- bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");
- if (StoreBackchain)
-BuildMI(*MBB, MBBI, DL, ZII->get(SystemZ::LGR))
- .addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D);
-
if (NumFullBlocks < 3) {
// Emit unrolled probe statements.
for (unsigned int i = 0; i < NumFullBlocks; i++)
@@ -678,11 +677,10 @@ void
SystemZFrameLowering::inlineStackProbe(MachineFunction ,
uint64_t LoopAlloc = ProbeSize * NumFullBlocks;
SPOffsetFromCFA -= LoopAlloc;
-// Use R0D to hold the exit value.
-BuildMI(*MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R0D)
+BuildMI(*MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R1D)
.addReg(SystemZ::R15D);
-buildDefCFAReg(*MBB, MBBI, DL, SystemZ::R0D, ZII);
-emitIncrement(*MBB, MBBI, DL, SystemZ::R0D, -int64_t(LoopAlloc), ZII);
+buildDefCFAReg(*MBB, MBBI, DL, SystemZ::R1D, ZII);
+emitIncrement(*MBB, MBBI, DL, SystemZ::R1D, -int64_t(LoopAlloc), ZII);
buildCFAOffs(*MBB, MBBI, DL, -int64_t(SystemZMC::CallFrameSize +
LoopAlloc),
ZII);
@@ -695,7 +693,7 @@ void SystemZFrameLowering::inlineStackProbe(MachineFunction
,
MBB = LoopMBB;
allocateAndProbe(*MBB, MBB->end(), ProbeSize, false/*EmitCFI*/);
BuildMI(*MBB, MBB->end(), DL, ZII->get(SystemZ::CLGR))
- .addReg(SystemZ::R15D).addReg(SystemZ::R0D);
+ .addReg(SystemZ::R15D).addReg(SystemZ::R1D);
BuildMI(*MBB, MBB->end(), DL, ZII->get(SystemZ::BRC))
.addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_GT).addMBB(MBB);
@@ -710,14 +708,6 @@ void
SystemZFrameLowering::inlineStackProbe(MachineFunction ,
if (Residual)
allocateAndProbe(*MBB, MBBI, Residual, true/*EmitCFI*/);
- if (StoreBackchain) {
-// The back chain is stored topmost with packed-stack.
-int Offset = usePackedStack(MF) ?
[llvm-branch-commits] [llvm] ea475c7 - [SystemZFrameLowering] Don't overrwrite R1D (backchain) when probing.
Author: Jonas Paulsson
Date: 2020-12-10T15:06:18-06:00
New Revision: ea475c77ff9eab1de7d44684c8fb453b39f70081
URL:
https://github.com/llvm/llvm-project/commit/ea475c77ff9eab1de7d44684c8fb453b39f70081
DIFF:
https://github.com/llvm/llvm-project/commit/ea475c77ff9eab1de7d44684c8fb453b39f70081.diff
LOG: [SystemZFrameLowering] Don't overrwrite R1D (backchain) when probing.
The loop-based probing done for stack clash protection altered R1D which
corrupted the backchain value to be stored after the probing was done.
By using R0D instead for the loop exit value, R1D is not modified.
Review: Ulrich Weigand.
Differential Revision: https://reviews.llvm.org/D92803
Added:
Modified:
llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
llvm/test/CodeGen/SystemZ/stack-clash-dynamic-alloca.ll
llvm/test/CodeGen/SystemZ/stack-clash-protection.ll
Removed:
diff --git a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
index 57529c8685de..0bfab129edb1 100644
--- a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
@@ -488,15 +488,6 @@ void SystemZFrameLowering::emitPrologue(MachineFunction
,
MFFrame.setStackSize(StackSize);
if (StackSize) {
-// Determine if we want to store a backchain.
-bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");
-
-// If we need backchain, save current stack pointer. R1 is free at this
-// point.
-if (StoreBackchain)
- BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR))
-.addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D);
-
// Allocate StackSize bytes.
int64_t Delta = -int64_t(StackSize);
const unsigned ProbeSize = TLI.getStackProbeSize(MF);
@@ -512,18 +503,23 @@ void SystemZFrameLowering::emitPrologue(MachineFunction
,
.addImm(StackSize);
}
else {
+ bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");
+ // If we need backchain, save current stack pointer. R1 is free at
+ // this point.
+ if (StoreBackchain)
+BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR))
+ .addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D);
emitIncrement(MBB, MBBI, DL, SystemZ::R15D, Delta, ZII);
buildCFAOffs(MBB, MBBI, DL, SPOffsetFromCFA + Delta, ZII);
+ if (StoreBackchain) {
+// The back chain is stored topmost with packed-stack.
+int Offset = usePackedStack(MF) ? SystemZMC::CallFrameSize - 8 : 0;
+BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG))
+ .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D)
+ .addImm(Offset).addReg(0);
+ }
}
SPOffsetFromCFA += Delta;
-
-if (StoreBackchain) {
- // The back chain is stored topmost with packed-stack.
- int Offset = usePackedStack(MF) ? SystemZMC::CallFrameSize - 8 : 0;
- BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG))
-.addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D)
-.addImm(Offset).addReg(0);
-}
}
if (HasFP) {
@@ -668,6 +664,11 @@ void
SystemZFrameLowering::inlineStackProbe(MachineFunction ,
.addMemOperand(MMO);
};
+ bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");
+ if (StoreBackchain)
+BuildMI(*MBB, MBBI, DL, ZII->get(SystemZ::LGR))
+ .addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D);
+
if (NumFullBlocks < 3) {
// Emit unrolled probe statements.
for (unsigned int i = 0; i < NumFullBlocks; i++)
@@ -677,10 +678,11 @@ void
SystemZFrameLowering::inlineStackProbe(MachineFunction ,
uint64_t LoopAlloc = ProbeSize * NumFullBlocks;
SPOffsetFromCFA -= LoopAlloc;
-BuildMI(*MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R1D)
+// Use R0D to hold the exit value.
+BuildMI(*MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R0D)
.addReg(SystemZ::R15D);
-buildDefCFAReg(*MBB, MBBI, DL, SystemZ::R1D, ZII);
-emitIncrement(*MBB, MBBI, DL, SystemZ::R1D, -int64_t(LoopAlloc), ZII);
+buildDefCFAReg(*MBB, MBBI, DL, SystemZ::R0D, ZII);
+emitIncrement(*MBB, MBBI, DL, SystemZ::R0D, -int64_t(LoopAlloc), ZII);
buildCFAOffs(*MBB, MBBI, DL, -int64_t(SystemZMC::CallFrameSize +
LoopAlloc),
ZII);
@@ -693,7 +695,7 @@ void SystemZFrameLowering::inlineStackProbe(MachineFunction
,
MBB = LoopMBB;
allocateAndProbe(*MBB, MBB->end(), ProbeSize, false/*EmitCFI*/);
BuildMI(*MBB, MBB->end(), DL, ZII->get(SystemZ::CLGR))
- .addReg(SystemZ::R15D).addReg(SystemZ::R1D);
+ .addReg(SystemZ::R15D).addReg(SystemZ::R0D);
BuildMI(*MBB, MBB->end(), DL, ZII->get(SystemZ::BRC))
.addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_GT).addMBB(MBB);
@@ -708,6 +710,14 @@ void
SystemZFrameLowering::inlineStackProbe(MachineFunction ,
if (Residual)
[llvm-branch-commits] [llvm] 9010b1b - Revert "[SystemZ] Bugfix for backchain with packed-stack"
Author: Jonas Paulsson
Date: 2020-03-03T15:00:31+01:00
New Revision: 9010b1b78a52e854b3dba8f0e0bc03eec5028a74
URL:
https://github.com/llvm/llvm-project/commit/9010b1b78a52e854b3dba8f0e0bc03eec5028a74
DIFF:
https://github.com/llvm/llvm-project/commit/9010b1b78a52e854b3dba8f0e0bc03eec5028a74.diff
LOG: Revert "[SystemZ] Bugfix for backchain with packed-stack"
This reverts commit 594f8e72700fb1ae244793e32ee328c8c8fc3d39.
Sorry - pushed my local branch instead of on master.
Added:
Modified:
llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
Removed:
llvm/test/CodeGen/SystemZ/frame-25.ll
diff --git a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
index 0f43ccf63097..9eeccc25e1e6 100644
--- a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
@@ -315,10 +315,9 @@ void SystemZFrameLowering::
processFunctionBeforeFrameFinalized(MachineFunction ,
RegScavenger *RS) const {
MachineFrameInfo = MF.getFrameInfo();
- bool BackChain = MF.getFunction().hasFnAttribute("backchain");
- if (!usePackedStack(MF) || BackChain)
-// Create the incoming register save area.
+ if (!usePackedStack(MF))
+// Always create the full incoming register save area.
getOrCreateFramePointerSaveIndex(MF);
// Get the size of our stack frame to be allocated ...
diff --git a/llvm/test/CodeGen/SystemZ/frame-25.ll
b/llvm/test/CodeGen/SystemZ/frame-25.ll
deleted file mode 100644
index 64c175bd4eca..
--- a/llvm/test/CodeGen/SystemZ/frame-25.ll
+++ /dev/null
@@ -1,24 +0,0 @@
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
-;
-; Test that space is allocated for the incoming back chain also in cases
-; where no GPRs are saved / restored.
-
-define void @fun0() #0 {
-; CHECK-LABEL: fun0:
-; CHECK: lgr %r1, %r15
-; CHECK-NEXT: aghi%r15, -24
-; CHECK-NEXT: stg %r1, 152(%r15)
-; CHECK-NEXT: #APP
-; CHECK-NEXT: stcke 160(%r15)
-; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: aghi%r15, 24
-; CHECK-NEXT: br %r14
-
-entry:
- %b = alloca [16 x i8], align 1
- %0 = getelementptr inbounds [16 x i8], [16 x i8]* %b, i64 0, i64 0
- call void asm "stcke $0", "=*Q"([16 x i8]* nonnull %b) #2
- ret void
-}
-
-attributes #0 = { nounwind "packed-stack" "backchain" "use-soft-float"="true" }
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[llvm-branch-commits] [llvm] 594f8e7 - [SystemZ] Bugfix for backchain with packed-stack
Author: Jonas Paulsson
Date: 2020-03-03T14:54:47+01:00
New Revision: 594f8e72700fb1ae244793e32ee328c8c8fc3d39
URL:
https://github.com/llvm/llvm-project/commit/594f8e72700fb1ae244793e32ee328c8c8fc3d39
DIFF:
https://github.com/llvm/llvm-project/commit/594f8e72700fb1ae244793e32ee328c8c8fc3d39.diff
LOG: [SystemZ] Bugfix for backchain with packed-stack
The incoming back chain slot was implicitly allocated whenever a GPR was
saved in SystemZFrameLowering::getRegSpillOffset(), but in cases where no
GPRs were saved/restored this did not take effect.
Review: Ulrich Weigand
Differential Revision: https://reviews.llvm.org/D75367
Added:
llvm/test/CodeGen/SystemZ/frame-25.ll
Modified:
llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
Removed:
diff --git a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
index 9eeccc25e1e6..0f43ccf63097 100644
--- a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
@@ -315,9 +315,10 @@ void SystemZFrameLowering::
processFunctionBeforeFrameFinalized(MachineFunction ,
RegScavenger *RS) const {
MachineFrameInfo = MF.getFrameInfo();
+ bool BackChain = MF.getFunction().hasFnAttribute("backchain");
- if (!usePackedStack(MF))
-// Always create the full incoming register save area.
+ if (!usePackedStack(MF) || BackChain)
+// Create the incoming register save area.
getOrCreateFramePointerSaveIndex(MF);
// Get the size of our stack frame to be allocated ...
diff --git a/llvm/test/CodeGen/SystemZ/frame-25.ll
b/llvm/test/CodeGen/SystemZ/frame-25.ll
new file mode 100644
index ..64c175bd4eca
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/frame-25.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+;
+; Test that space is allocated for the incoming back chain also in cases
+; where no GPRs are saved / restored.
+
+define void @fun0() #0 {
+; CHECK-LABEL: fun0:
+; CHECK: lgr %r1, %r15
+; CHECK-NEXT: aghi%r15, -24
+; CHECK-NEXT: stg %r1, 152(%r15)
+; CHECK-NEXT: #APP
+; CHECK-NEXT: stcke 160(%r15)
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: aghi%r15, 24
+; CHECK-NEXT: br %r14
+
+entry:
+ %b = alloca [16 x i8], align 1
+ %0 = getelementptr inbounds [16 x i8], [16 x i8]* %b, i64 0, i64 0
+ call void asm "stcke $0", "=*Q"([16 x i8]* nonnull %b) #2
+ ret void
+}
+
+attributes #0 = { nounwind "packed-stack" "backchain" "use-soft-float"="true" }
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[llvm-branch-commits] [llvm] ff2b340 - [SystemZ] Improve handling of huge PC relative immediate offsets.
Author: Jonas Paulsson
Date: 2019-11-04T10:35:21+01:00
New Revision: ff2b3401984b36f94a817995b0ee665c13d97264
URL:
https://github.com/llvm/llvm-project/commit/ff2b3401984b36f94a817995b0ee665c13d97264
DIFF:
https://github.com/llvm/llvm-project/commit/ff2b3401984b36f94a817995b0ee665c13d97264.diff
LOG: [SystemZ] Improve handling of huge PC relative immediate offsets.
Demand that an immediate offset to a PC relative address fits in 32 bits, or
else load it into a register and perform a separate add.
Verify in the assembler that such immediate offsets fit the bitwidth.
Even though the final address of a Load Address Relative Long may fit in 32
bits even with a >32 bit offset (depending on where the symbol lives relative
to PC), the GNU toolchain demands the offset by itself to be in range. This
patch adapts the same behavior for llvm.
Review: Ulrich Weigand
https://reviews.llvm.org/D69749
Added:
llvm/test/CodeGen/SystemZ/la-05.ll
Modified:
llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/test/MC/SystemZ/insn-bad.s
Removed:
diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
index 93c4ce4b5ccc..b58d20fc49ba 100644
--- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
@@ -1304,14 +1304,23 @@ SystemZAsmParser::parsePCRel(OperandVector ,
int64_t MinVal,
if (getParser().parseExpression(Expr))
return MatchOperand_NoMatch;
+ auto isOutOfRangeConstant = [&](const MCExpr *E) -> bool {
+if (auto *CE = dyn_cast(E)) {
+ int64_t Value = CE->getValue();
+ if ((Value & 1) || Value < MinVal || Value > MaxVal)
+return true;
+}
+return false;
+ };
+
// For consistency with the GNU assembler, treat immediates as offsets
// from ".".
if (auto *CE = dyn_cast(Expr)) {
-int64_t Value = CE->getValue();
-if ((Value & 1) || Value < MinVal || Value > MaxVal) {
+if (isOutOfRangeConstant(CE)) {
Error(StartLoc, "offset out of range");
return MatchOperand_ParseFail;
}
+int64_t Value = CE->getValue();
MCSymbol *Sym = Ctx.createTempSymbol();
Out.EmitLabel(Sym);
const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
@@ -1319,6 +1328,15 @@ SystemZAsmParser::parsePCRel(OperandVector ,
int64_t MinVal,
Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
}
+ // For consistency with the GNU assembler, conservatively assume that a
+ // constant offset must by itself be within the given size range.
+ if (const auto *BE = dyn_cast(Expr))
+if (isOutOfRangeConstant(BE->getLHS()) ||
+isOutOfRangeConstant(BE->getRHS())) {
+ Error(StartLoc, "offset out of range");
+ return MatchOperand_ParseFail;
+}
+
// Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
const MCExpr *Sym = nullptr;
if (AllowTLS && getLexer().is(AsmToken::Colon)) {
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index e0ca9da93561..8e71d8342562 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -2828,17 +2828,26 @@ SDValue
SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
SDValue Result;
if (Subtarget.isPC32DBLSymbol(GV, CM)) {
-// Assign anchors at 1<<12 byte boundaries.
-uint64_t Anchor = Offset & ~uint64_t(0xfff);
-Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor);
-Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
-
-// The offset can be folded into the address if it is aligned to a
halfword.
-Offset -= Anchor;
-if (Offset != 0 && (Offset & 1) == 0) {
- SDValue Full = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor +
Offset);
- Result = DAG.getNode(SystemZISD::PCREL_OFFSET, DL, PtrVT, Full, Result);
- Offset = 0;
+if (isInt<32>(Offset)) {
+ // Assign anchors at 1<<12 byte boundaries.
+ uint64_t Anchor = Offset & ~uint64_t(0xfff);
+ Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor);
+ Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
+
+ // The offset can be folded into the address if it is aligned to a
+ // halfword.
+ Offset -= Anchor;
+ if (Offset != 0 && (Offset & 1) == 0) {
+SDValue Full =
+ DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor + Offset);
+Result = DAG.getNode(SystemZISD::PCREL_OFFSET, DL, PtrVT, Full,
Result);
+Offset = 0;
+ }
+} else {
+ // Conservatively load a constant offset greater than 32 bits into a
+ // register below.
+ Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT);
+
