[llvm-branch-commits] [llvm] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

2024-06-06 Thread Luke Lau via llvm-branch-commits 

https://github.com/lukel97 approved this pull request.


https://github.com/llvm/llvm-project/pull/94313
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[llvm-branch-commits] [llvm] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

2024-06-06 Thread Luke Lau via llvm-branch-commits 


@@ -2211,6 +,16 @@ ParseStatus RISCVAsmParser::parseVTypeI(OperandVector 
) {
 
   if (getLexer().is(AsmToken::EndOfStatement) && State == VTypeState_Done) {
 RISCVII::VLMUL VLMUL = RISCVVType::encodeLMUL(Lmul, Fractional);
+if (Fractional) {
+  unsigned ELEN = STI->hasFeature(RISCV::FeatureStdExtZve64x) ? 64 : 32;
+  unsigned MaxSEW = ELEN / Lmul;
+  // If MaxSEW < 8, we should have printed warning about reserved LMUL.
+  if (MaxSEW >= 8 && Sew > MaxSEW)
+Warning(SEWLoc,
+"use of vtype encodings with SEW > " + Twine(MaxSEW) +
+" and LMUL == " + (Fractional ? "mf" : "m") + Twine(Lmul) +

lukel97 wrote:

Fractional is always true here right?

https://github.com/llvm/llvm-project/pull/94313
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[llvm-branch-commits] [llvm] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

2024-06-06 Thread Luke Lau via llvm-branch-commits 

https://github.com/lukel97 edited 
https://github.com/llvm/llvm-project/pull/94313
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[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

2024-06-04 Thread Luke Lau via llvm-branch-commits 


@@ -71,18 +73,21 @@ vsetvli a2, a0, e32, m8, ta, ma
 
 vsetvli a2, a0, e32, mf2, ta, ma
 # CHECK-INST: vsetvli a2, a0, e32, mf2, ta, ma
+# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 16 may not be compatible 
with all RVV implementations{{$}}
 # CHECK-ENCODING: [0x57,0x76,0x75,0x0d]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for 
Application Processors), 'Zve32x' (Vector Extensions for Embedded 
Processors){{$}}
 # CHECK-UNKNOWN: 0d757657 
 
 vsetvli a2, a0, e32, mf4, ta, ma
 # CHECK-INST: vsetvli a2, a0, e32, mf4, ta, ma
+# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 8 may not be compatible with 
all RVV implementations{{$}}

lukel97 wrote:

Ok, that seems reasonable. Should we maybe then reword the LMUL < SEWMIN/ELEN 
case to mention that the encoding is actually reserved, whereas for SEW > LMUL 
* ELEN it may just not be compatible

https://github.com/llvm/llvm-project/pull/94313
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[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

2024-06-04 Thread Luke Lau via llvm-branch-commits 


@@ -71,18 +73,21 @@ vsetvli a2, a0, e32, m8, ta, ma
 
 vsetvli a2, a0, e32, mf2, ta, ma
 # CHECK-INST: vsetvli a2, a0, e32, mf2, ta, ma
+# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 16 may not be compatible 
with all RVV implementations{{$}}
 # CHECK-ENCODING: [0x57,0x76,0x75,0x0d]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for 
Application Processors), 'Zve32x' (Vector Extensions for Embedded 
Processors){{$}}
 # CHECK-UNKNOWN: 0d757657 
 
 vsetvli a2, a0, e32, mf4, ta, ma
 # CHECK-INST: vsetvli a2, a0, e32, mf4, ta, ma
+# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 8 may not be compatible with 
all RVV implementations{{$}}

lukel97 wrote:

I see that the spec recommends that we warn when LMUL < SEWMIN/ELEN, but do we 
need to warn for SEW > LMUL * ELEN? IIUC this cause a warning on zve64x too 
since 32 > 1/4 * 64

https://github.com/llvm/llvm-project/pull/94313
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[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

2024-06-04 Thread Luke Lau via llvm-branch-commits 


@@ -1,5 +1,7 @@
 # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+v %s \
 # RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32x %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-WARNING

lukel97 wrote:

Nit, can we name the prefix something like CHECK-ZVE32X

https://github.com/llvm/llvm-project/pull/94313
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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

2024-05-17 Thread Luke Lau via llvm-branch-commits 

https://github.com/lukel97 approved this pull request.

Chiming in that this seems reasonable to me, given the performance impact of 
not having unaligned scalar accesses. And hopefully we can remove this one 
we're settled on a proper interface.

https://github.com/llvm/llvm-project/pull/92143
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[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

2024-04-29 Thread Luke Lau via llvm-branch-commits 


@@ -194,15 +194,12 @@ define void @vpmerge_vpload_store( 
%passthru, ptr %p, , i64 } @llvm.riscv.vleff.nxv2i32(, ptr, i64)
 define  @vpmerge_vleff( %passthru, ptr %p, 
 %m, i32 zeroext %vl) {
 ; CHECK-LABEL: vpmerge_vleff:
 ; CHECK:   # %bb.0:
-; CHECK-NEXT:vsetvli zero, a1, e32, m1, ta, ma
-; CHECK-NEXT:vle32ff.v v9, (a0)
-; CHECK-NEXT:vsetvli zero, a1, e32, m1, tu, ma
-; CHECK-NEXT:vmerge.vvm v8, v8, v9, v0
+; CHECK-NEXT:vsetvli zero, a1, e32, m1, tu, mu
+; CHECK-NEXT:vle32ff.v v8, (a0), v0.t

lukel97 wrote:

Looks correct to me.

https://github.com/llvm/llvm-project/pull/90049
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[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

2024-04-29 Thread Luke Lau via llvm-branch-commits 

https://github.com/lukel97 approved this pull request.


https://github.com/llvm/llvm-project/pull/90049
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[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

2024-04-29 Thread Luke Lau via llvm-branch-commits 

https://github.com/lukel97 edited 
https://github.com/llvm/llvm-project/pull/90049
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[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

2024-04-25 Thread Luke Lau via llvm-branch-commits 

https://github.com/lukel97 edited 
https://github.com/llvm/llvm-project/pull/90049
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[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

2024-04-25 Thread Luke Lau via llvm-branch-commits 

https://github.com/lukel97 commented:

Removing it from vleNff sense to me. As long as we have the implicit-def $vl on 
the pseudo to prevent it being moved between vsetvlis I think it should be ok. 

https://github.com/llvm/llvm-project/pull/90049
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[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

2024-04-05 Thread Luke Lau via llvm-branch-commits 

https://github.com/lukel97 approved this pull request.


https://github.com/llvm/llvm-project/pull/84455
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[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

2024-03-31 Thread Luke Lau via llvm-branch-commits 


@@ -302,102 +302,98 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock 
,
RISCVII::VLMUL LMul, unsigned NF) const 
{
   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
 
-  unsigned Opc;
-  unsigned SubRegIdx;
-  unsigned VVOpc, VIOpc;
-  switch (LMul) {
-  default:
-llvm_unreachable("Impossible LMUL for vector register copy.");
-  case RISCVII::LMUL_1:
-Opc = RISCV::VMV1R_V;
-SubRegIdx = RISCV::sub_vrm1_0;
-VVOpc = RISCV::PseudoVMV_V_V_M1;
-VIOpc = RISCV::PseudoVMV_V_I_M1;
-break;
-  case RISCVII::LMUL_2:
-Opc = RISCV::VMV2R_V;
-SubRegIdx = RISCV::sub_vrm2_0;
-VVOpc = RISCV::PseudoVMV_V_V_M2;
-VIOpc = RISCV::PseudoVMV_V_I_M2;
-break;
-  case RISCVII::LMUL_4:
-Opc = RISCV::VMV4R_V;
-SubRegIdx = RISCV::sub_vrm4_0;
-VVOpc = RISCV::PseudoVMV_V_V_M4;
-VIOpc = RISCV::PseudoVMV_V_I_M4;
-break;
-  case RISCVII::LMUL_8:
-assert(NF == 1);
-Opc = RISCV::VMV8R_V;
-SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0.
-VVOpc = RISCV::PseudoVMV_V_V_M8;
-VIOpc = RISCV::PseudoVMV_V_I_M8;
-break;
-  }
-
-  bool UseVMV_V_V = false;
-  bool UseVMV_V_I = false;
-  MachineBasicBlock::const_iterator DefMBBI;
-  if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
-UseVMV_V_V = true;
-Opc = VVOpc;
-
-if (DefMBBI->getOpcode() == VIOpc) {
-  UseVMV_V_I = true;
-  Opc = VIOpc;
-}
-  }
-
-  if (NF == 1) {
-auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg);
-if (UseVMV_V_V)
-  MIB.addReg(DstReg, RegState::Undef);
-if (UseVMV_V_I)
-  MIB = MIB.add(DefMBBI->getOperand(2));
-else
-  MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc));
-if (UseVMV_V_V) {
-  const MCInstrDesc  = DefMBBI->getDesc();
-  MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc)));  // AVL
-  MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
-  MIB.addImm(0);// tu, mu
-  MIB.addReg(RISCV::VL, RegState::Implicit);
-  MIB.addReg(RISCV::VTYPE, RegState::Implicit);
-}
-return;
-  }
-
-  int I = 0, End = NF, Incr = 1;
   unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
   unsigned DstEncoding = TRI->getEncodingValue(DstReg);
   unsigned LMulVal;
   bool Fractional;
   std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
   assert(!Fractional && "It is impossible be fractional lmul here.");
-  if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) {
-I = NF - 1;
-End = -1;
-Incr = -1;
-  }
+  unsigned NumRegs = NF * LMulVal;
+  bool ReversedCopy =
+  forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NumRegs);
+  if (ReversedCopy) {
+// If there exists overlapping, we should copy the registers reversely.
+SrcEncoding += NumRegs - LMulVal;
+DstEncoding += NumRegs - LMulVal;
+  }
+
+  unsigned I = 0;
+  auto GetCopyInfo = [&](uint16_t SrcEncoding, uint16_t DstEncoding)
+  -> std::tuple {
+// If source register encoding and destination register encoding are 
aligned
+// to 8, we can do a LMUL8 copying.
+if (SrcEncoding % 8 == 0 && DstEncoding % 8 == 0 && I + 8 <= NumRegs)
+  return {RISCVII::LMUL_8, RISCV::VRM8RegClass, RISCV::VMV8R_V,
+  RISCV::PseudoVMV_V_V_M8, RISCV::PseudoVMV_V_I_M8};
+// If source register encoding and destination register encoding are 
aligned
+// to 4, we can do a LMUL4 copying.
+if (SrcEncoding % 4 == 0 && DstEncoding % 4 == 0 && I + 4 <= NumRegs)
+  return {RISCVII::LMUL_4, RISCV::VRM4RegClass, RISCV::VMV4R_V,
+  RISCV::PseudoVMV_V_V_M4, RISCV::PseudoVMV_V_I_M4};
+// If source register encoding and destination register encoding are 
aligned
+// to 2, we can do a LMUL2 copying.
+if (SrcEncoding % 2 == 0 && DstEncoding % 2 == 0 && I + 2 <= NumRegs)
+  return {RISCVII::LMUL_2, RISCV::VRM2RegClass, RISCV::VMV2R_V,
+  RISCV::PseudoVMV_V_V_M2, RISCV::PseudoVMV_V_I_M2};
+// Or we should do LMUL1 copying.
+return {RISCVII::LMUL_1, RISCV::VRRegClass, RISCV::VMV1R_V,
+RISCV::PseudoVMV_V_V_M1, RISCV::PseudoVMV_V_I_M1};
+  };
+  auto FindRegWithEncoding = [](const TargetRegisterClass ,
+uint16_t Encoding) {
+ArrayRef Regs = RegClass.getRegisters();
+const auto *FoundReg = llvm::find_if(Regs, [&](MCPhysReg Reg) {
+  return TRI->getEncodingValue(Reg) == Encoding;
+});
+// We should be always able to find one valid register.
+assert(FoundReg != Regs.end());
+return *FoundReg;
+  };

lukel97 wrote:

Yeah, although I thought that `GetCopyInfo` was already checking that 
SrcReg/DstReg was aligned to the VRM8 reg class.

But I just checked and it looks like there's only subregisters on tuples for 
the same LMUL, e.g. V0_V1_V2_V3_V4_V5_V6_V7 from VRN8M1 only has the LMUL1 
subregisters, e.g. V0, V1,

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

2024-03-29 Thread Luke Lau via llvm-branch-commits 


@@ -302,102 +302,98 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock 
,
RISCVII::VLMUL LMul, unsigned NF) const 
{
   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
 
-  unsigned Opc;
-  unsigned SubRegIdx;
-  unsigned VVOpc, VIOpc;
-  switch (LMul) {
-  default:
-llvm_unreachable("Impossible LMUL for vector register copy.");
-  case RISCVII::LMUL_1:
-Opc = RISCV::VMV1R_V;
-SubRegIdx = RISCV::sub_vrm1_0;
-VVOpc = RISCV::PseudoVMV_V_V_M1;
-VIOpc = RISCV::PseudoVMV_V_I_M1;
-break;
-  case RISCVII::LMUL_2:
-Opc = RISCV::VMV2R_V;
-SubRegIdx = RISCV::sub_vrm2_0;
-VVOpc = RISCV::PseudoVMV_V_V_M2;
-VIOpc = RISCV::PseudoVMV_V_I_M2;
-break;
-  case RISCVII::LMUL_4:
-Opc = RISCV::VMV4R_V;
-SubRegIdx = RISCV::sub_vrm4_0;
-VVOpc = RISCV::PseudoVMV_V_V_M4;
-VIOpc = RISCV::PseudoVMV_V_I_M4;
-break;
-  case RISCVII::LMUL_8:
-assert(NF == 1);
-Opc = RISCV::VMV8R_V;
-SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0.
-VVOpc = RISCV::PseudoVMV_V_V_M8;
-VIOpc = RISCV::PseudoVMV_V_I_M8;
-break;
-  }
-
-  bool UseVMV_V_V = false;
-  bool UseVMV_V_I = false;
-  MachineBasicBlock::const_iterator DefMBBI;
-  if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
-UseVMV_V_V = true;
-Opc = VVOpc;
-
-if (DefMBBI->getOpcode() == VIOpc) {
-  UseVMV_V_I = true;
-  Opc = VIOpc;
-}
-  }
-
-  if (NF == 1) {
-auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg);
-if (UseVMV_V_V)
-  MIB.addReg(DstReg, RegState::Undef);
-if (UseVMV_V_I)
-  MIB = MIB.add(DefMBBI->getOperand(2));
-else
-  MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc));
-if (UseVMV_V_V) {
-  const MCInstrDesc  = DefMBBI->getDesc();
-  MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc)));  // AVL
-  MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
-  MIB.addImm(0);// tu, mu
-  MIB.addReg(RISCV::VL, RegState::Implicit);
-  MIB.addReg(RISCV::VTYPE, RegState::Implicit);
-}
-return;
-  }
-
-  int I = 0, End = NF, Incr = 1;
   unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
   unsigned DstEncoding = TRI->getEncodingValue(DstReg);
   unsigned LMulVal;
   bool Fractional;
   std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
   assert(!Fractional && "It is impossible be fractional lmul here.");
-  if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) {
-I = NF - 1;
-End = -1;
-Incr = -1;
-  }
+  unsigned NumRegs = NF * LMulVal;
+  bool ReversedCopy =
+  forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NumRegs);
+  if (ReversedCopy) {
+// If there exists overlapping, we should copy the registers reversely.
+SrcEncoding += NumRegs - LMulVal;
+DstEncoding += NumRegs - LMulVal;
+  }
+
+  unsigned I = 0;
+  auto GetCopyInfo = [&](uint16_t SrcEncoding, uint16_t DstEncoding)
+  -> std::tuple {
+// If source register encoding and destination register encoding are 
aligned
+// to 8, we can do a LMUL8 copying.
+if (SrcEncoding % 8 == 0 && DstEncoding % 8 == 0 && I + 8 <= NumRegs)
+  return {RISCVII::LMUL_8, RISCV::VRM8RegClass, RISCV::VMV8R_V,
+  RISCV::PseudoVMV_V_V_M8, RISCV::PseudoVMV_V_I_M8};
+// If source register encoding and destination register encoding are 
aligned
+// to 4, we can do a LMUL4 copying.
+if (SrcEncoding % 4 == 0 && DstEncoding % 4 == 0 && I + 4 <= NumRegs)
+  return {RISCVII::LMUL_4, RISCV::VRM4RegClass, RISCV::VMV4R_V,
+  RISCV::PseudoVMV_V_V_M4, RISCV::PseudoVMV_V_I_M4};
+// If source register encoding and destination register encoding are 
aligned
+// to 2, we can do a LMUL2 copying.
+if (SrcEncoding % 2 == 0 && DstEncoding % 2 == 0 && I + 2 <= NumRegs)
+  return {RISCVII::LMUL_2, RISCV::VRM2RegClass, RISCV::VMV2R_V,
+  RISCV::PseudoVMV_V_V_M2, RISCV::PseudoVMV_V_I_M2};
+// Or we should do LMUL1 copying.
+return {RISCVII::LMUL_1, RISCV::VRRegClass, RISCV::VMV1R_V,
+RISCV::PseudoVMV_V_V_M1, RISCV::PseudoVMV_V_I_M1};
+  };
+  auto FindRegWithEncoding = [](const TargetRegisterClass ,
+uint16_t Encoding) {
+ArrayRef Regs = RegClass.getRegisters();
+const auto *FoundReg = llvm::find_if(Regs, [&](MCPhysReg Reg) {
+  return TRI->getEncodingValue(Reg) == Encoding;
+});
+// We should be always able to find one valid register.
+assert(FoundReg != Regs.end());
+return *FoundReg;
+  };

lukel97 wrote:

I presume you don't need to use a subreg index if the register is a VRN8M1 and 
you're trying to do a VRM8 copy? Since the VRM8 reg class should be a subclass 
of VRN8M1 right? (Hope I'm getting the subreg/subclass terminology right btw)

https://github.com/llvm/llvm-project/pull/84455

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

2024-03-26 Thread Luke Lau via llvm-branch-commits 


@@ -212,19 +185,13 @@ body: |
 ; CHECK-NEXT: $v7 = VMV1R_V $v14
 ; CHECK-NEXT: $v8 = VMV1R_V $v15
 ; CHECK-NEXT: $v9 = VMV1R_V $v16
-; CHECK-NEXT: $v4 = VMV1R_V $v10
-; CHECK-NEXT: $v5 = VMV1R_V $v11
-; CHECK-NEXT: $v6 = VMV1R_V $v12
-; CHECK-NEXT: $v7 = VMV1R_V $v13
-; CHECK-NEXT: $v8 = VMV1R_V $v14
-; CHECK-NEXT: $v9 = VMV1R_V $v15
+; CHECK-NEXT: $v4m2 = VMV2R_V $v10m2
+; CHECK-NEXT: $v6m2 = VMV2R_V $v12m2
+; CHECK-NEXT: $v8m2 = VMV2R_V $v14m2
 ; CHECK-NEXT: $v10 = VMV1R_V $v16
-; CHECK-NEXT: $v22 = VMV1R_V $v16
-; CHECK-NEXT: $v21 = VMV1R_V $v15
-; CHECK-NEXT: $v20 = VMV1R_V $v14
-; CHECK-NEXT: $v19 = VMV1R_V $v13
-; CHECK-NEXT: $v18 = VMV1R_V $v12
-; CHECK-NEXT: $v17 = VMV1R_V $v11
+; CHECK-NEXT: $v22m2 = VMV2R_V $v16m2
+; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2
+; CHECK-NEXT: $v18m2 = VMV2R_V $v12m2
 ; CHECK-NEXT: $v16 = VMV1R_V $v10

lukel97 wrote:

Do we have a test for a copy like:

```
$v16_v17_v18_v19_v20_v21_v22 = COPY $v15_v16_v17_v18_v19_v20_v21
```

Because I think this will need to be all VMV1R_Vs. Does it already do this?

https://github.com/llvm/llvm-project/pull/84455
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[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

2024-03-26 Thread Luke Lau via llvm-branch-commits 


@@ -302,102 +302,98 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock 
,
RISCVII::VLMUL LMul, unsigned NF) const 
{
   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
 
-  unsigned Opc;
-  unsigned SubRegIdx;
-  unsigned VVOpc, VIOpc;
-  switch (LMul) {
-  default:
-llvm_unreachable("Impossible LMUL for vector register copy.");
-  case RISCVII::LMUL_1:
-Opc = RISCV::VMV1R_V;
-SubRegIdx = RISCV::sub_vrm1_0;
-VVOpc = RISCV::PseudoVMV_V_V_M1;
-VIOpc = RISCV::PseudoVMV_V_I_M1;
-break;
-  case RISCVII::LMUL_2:
-Opc = RISCV::VMV2R_V;
-SubRegIdx = RISCV::sub_vrm2_0;
-VVOpc = RISCV::PseudoVMV_V_V_M2;
-VIOpc = RISCV::PseudoVMV_V_I_M2;
-break;
-  case RISCVII::LMUL_4:
-Opc = RISCV::VMV4R_V;
-SubRegIdx = RISCV::sub_vrm4_0;
-VVOpc = RISCV::PseudoVMV_V_V_M4;
-VIOpc = RISCV::PseudoVMV_V_I_M4;
-break;
-  case RISCVII::LMUL_8:
-assert(NF == 1);
-Opc = RISCV::VMV8R_V;
-SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0.
-VVOpc = RISCV::PseudoVMV_V_V_M8;
-VIOpc = RISCV::PseudoVMV_V_I_M8;
-break;
-  }
-
-  bool UseVMV_V_V = false;
-  bool UseVMV_V_I = false;
-  MachineBasicBlock::const_iterator DefMBBI;
-  if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
-UseVMV_V_V = true;
-Opc = VVOpc;
-
-if (DefMBBI->getOpcode() == VIOpc) {
-  UseVMV_V_I = true;
-  Opc = VIOpc;
-}
-  }
-
-  if (NF == 1) {
-auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg);
-if (UseVMV_V_V)
-  MIB.addReg(DstReg, RegState::Undef);
-if (UseVMV_V_I)
-  MIB = MIB.add(DefMBBI->getOperand(2));
-else
-  MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc));
-if (UseVMV_V_V) {
-  const MCInstrDesc  = DefMBBI->getDesc();
-  MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc)));  // AVL
-  MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
-  MIB.addImm(0);// tu, mu
-  MIB.addReg(RISCV::VL, RegState::Implicit);
-  MIB.addReg(RISCV::VTYPE, RegState::Implicit);
-}
-return;
-  }
-
-  int I = 0, End = NF, Incr = 1;
   unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
   unsigned DstEncoding = TRI->getEncodingValue(DstReg);
   unsigned LMulVal;
   bool Fractional;
   std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
   assert(!Fractional && "It is impossible be fractional lmul here.");
-  if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) {
-I = NF - 1;
-End = -1;
-Incr = -1;
-  }
+  unsigned NumRegs = NF * LMulVal;
+  bool ReversedCopy =
+  forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NumRegs);
+  if (ReversedCopy) {
+// If there exists overlapping, we should copy the registers reversely.
+SrcEncoding += NumRegs - LMulVal;
+DstEncoding += NumRegs - LMulVal;
+  }
+
+  unsigned I = 0;
+  auto GetCopyInfo = [&](uint16_t SrcEncoding, uint16_t DstEncoding)
+  -> std::tuple {
+// If source register encoding and destination register encoding are 
aligned
+// to 8, we can do a LMUL8 copying.
+if (SrcEncoding % 8 == 0 && DstEncoding % 8 == 0 && I + 8 <= NumRegs)
+  return {RISCVII::LMUL_8, RISCV::VRM8RegClass, RISCV::VMV8R_V,
+  RISCV::PseudoVMV_V_V_M8, RISCV::PseudoVMV_V_I_M8};
+// If source register encoding and destination register encoding are 
aligned
+// to 4, we can do a LMUL4 copying.
+if (SrcEncoding % 4 == 0 && DstEncoding % 4 == 0 && I + 4 <= NumRegs)
+  return {RISCVII::LMUL_4, RISCV::VRM4RegClass, RISCV::VMV4R_V,
+  RISCV::PseudoVMV_V_V_M4, RISCV::PseudoVMV_V_I_M4};
+// If source register encoding and destination register encoding are 
aligned
+// to 2, we can do a LMUL2 copying.
+if (SrcEncoding % 2 == 0 && DstEncoding % 2 == 0 && I + 2 <= NumRegs)
+  return {RISCVII::LMUL_2, RISCV::VRM2RegClass, RISCV::VMV2R_V,
+  RISCV::PseudoVMV_V_V_M2, RISCV::PseudoVMV_V_I_M2};
+// Or we should do LMUL1 copying.
+return {RISCVII::LMUL_1, RISCV::VRRegClass, RISCV::VMV1R_V,
+RISCV::PseudoVMV_V_V_M1, RISCV::PseudoVMV_V_I_M1};
+  };
+  auto FindRegWithEncoding = [](const TargetRegisterClass ,
+uint16_t Encoding) {
+ArrayRef Regs = RegClass.getRegisters();
+const auto *FoundReg = llvm::find_if(Regs, [&](MCPhysReg Reg) {
+  return TRI->getEncodingValue(Reg) == Encoding;
+});
+// We should be always able to find one valid register.
+assert(FoundReg != Regs.end());
+return *FoundReg;
+  };

lukel97 wrote:

Would it be easier to get the register via `TRI->getSubReg`? I think you should 
be able to compute the subreg index based off the RegClass and `I`.

I don't think you'll need to compose any subreg indices like in 
`RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs`

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

2024-03-26 Thread Luke Lau via llvm-branch-commits 


@@ -302,102 +302,98 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock 
,
RISCVII::VLMUL LMul, unsigned NF) const 
{
   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
 
-  unsigned Opc;
-  unsigned SubRegIdx;
-  unsigned VVOpc, VIOpc;
-  switch (LMul) {
-  default:
-llvm_unreachable("Impossible LMUL for vector register copy.");
-  case RISCVII::LMUL_1:
-Opc = RISCV::VMV1R_V;
-SubRegIdx = RISCV::sub_vrm1_0;
-VVOpc = RISCV::PseudoVMV_V_V_M1;
-VIOpc = RISCV::PseudoVMV_V_I_M1;
-break;
-  case RISCVII::LMUL_2:
-Opc = RISCV::VMV2R_V;
-SubRegIdx = RISCV::sub_vrm2_0;
-VVOpc = RISCV::PseudoVMV_V_V_M2;
-VIOpc = RISCV::PseudoVMV_V_I_M2;
-break;
-  case RISCVII::LMUL_4:
-Opc = RISCV::VMV4R_V;
-SubRegIdx = RISCV::sub_vrm4_0;
-VVOpc = RISCV::PseudoVMV_V_V_M4;
-VIOpc = RISCV::PseudoVMV_V_I_M4;
-break;
-  case RISCVII::LMUL_8:
-assert(NF == 1);
-Opc = RISCV::VMV8R_V;
-SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0.
-VVOpc = RISCV::PseudoVMV_V_V_M8;
-VIOpc = RISCV::PseudoVMV_V_I_M8;
-break;
-  }
-
-  bool UseVMV_V_V = false;
-  bool UseVMV_V_I = false;
-  MachineBasicBlock::const_iterator DefMBBI;
-  if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
-UseVMV_V_V = true;
-Opc = VVOpc;
-
-if (DefMBBI->getOpcode() == VIOpc) {
-  UseVMV_V_I = true;
-  Opc = VIOpc;
-}
-  }
-
-  if (NF == 1) {
-auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg);
-if (UseVMV_V_V)
-  MIB.addReg(DstReg, RegState::Undef);
-if (UseVMV_V_I)
-  MIB = MIB.add(DefMBBI->getOperand(2));
-else
-  MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc));
-if (UseVMV_V_V) {
-  const MCInstrDesc  = DefMBBI->getDesc();
-  MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc)));  // AVL
-  MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
-  MIB.addImm(0);// tu, mu
-  MIB.addReg(RISCV::VL, RegState::Implicit);
-  MIB.addReg(RISCV::VTYPE, RegState::Implicit);
-}
-return;
-  }
-
-  int I = 0, End = NF, Incr = 1;
   unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
   unsigned DstEncoding = TRI->getEncodingValue(DstReg);
   unsigned LMulVal;
   bool Fractional;
   std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
   assert(!Fractional && "It is impossible be fractional lmul here.");
-  if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) {
-I = NF - 1;
-End = -1;
-Incr = -1;
-  }
+  unsigned NumRegs = NF * LMulVal;
+  bool ReversedCopy =
+  forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NumRegs);
+  if (ReversedCopy) {
+// If there exists overlapping, we should copy the registers reversely.

lukel97 wrote:

Nit, maybe clarify this happens when copying tuples?

```suggestion
// If the src and dest overlap when copying a tuple, we need to copy the 
registers in reverse.
```

https://github.com/llvm/llvm-project/pull/84455
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[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

2024-03-24 Thread Luke Lau via llvm-branch-commits 


@@ -146,16 +127,12 @@ body: |
 ; CHECK-NEXT: $v7 = VMV1R_V $v12
 ; CHECK-NEXT: $v8 = VMV1R_V $v13
 ; CHECK-NEXT: $v9 = VMV1R_V $v14
-; CHECK-NEXT: $v6 = VMV1R_V $v10
-; CHECK-NEXT: $v7 = VMV1R_V $v11
-; CHECK-NEXT: $v8 = VMV1R_V $v12
-; CHECK-NEXT: $v9 = VMV1R_V $v13
-; CHECK-NEXT: $v10 = VMV1R_V $v14
-; CHECK-NEXT: $v18 = VMV1R_V $v14
-; CHECK-NEXT: $v17 = VMV1R_V $v13
-; CHECK-NEXT: $v16 = VMV1R_V $v12
-; CHECK-NEXT: $v15 = VMV1R_V $v11
-; CHECK-NEXT: $v14 = VMV1R_V $v10
+; CHECK-NEXT: $v6m2 = VMV2R_V $v10m2
+; CHECK-NEXT: $v8m2 = VMV2R_V $v12m2
+; CHECK-NEXT: $v8 = VMV1R_V $v14
+; CHECK-NEXT: $v14m2 = VMV2R_V $v10m2
+; CHECK-NEXT: $v12m2 = VMV2R_V $v8m2
+; CHECK-NEXT: $v8 = VMV1R_V $v4

lukel97 wrote:

And this should be like?
```
$v18 = VMV1R_V $v14
$v16 = VMV2R_V $v12m2
$v14 = VMV2R_V $v10m2
```

https://github.com/llvm/llvm-project/pull/84455
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[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

2024-03-24 Thread Luke Lau via llvm-branch-commits 


@@ -146,16 +127,12 @@ body: |
 ; CHECK-NEXT: $v7 = VMV1R_V $v12
 ; CHECK-NEXT: $v8 = VMV1R_V $v13
 ; CHECK-NEXT: $v9 = VMV1R_V $v14
-; CHECK-NEXT: $v6 = VMV1R_V $v10
-; CHECK-NEXT: $v7 = VMV1R_V $v11
-; CHECK-NEXT: $v8 = VMV1R_V $v12
-; CHECK-NEXT: $v9 = VMV1R_V $v13
-; CHECK-NEXT: $v10 = VMV1R_V $v14
-; CHECK-NEXT: $v18 = VMV1R_V $v14
-; CHECK-NEXT: $v17 = VMV1R_V $v13
-; CHECK-NEXT: $v16 = VMV1R_V $v12
-; CHECK-NEXT: $v15 = VMV1R_V $v11
-; CHECK-NEXT: $v14 = VMV1R_V $v10
+; CHECK-NEXT: $v6m2 = VMV2R_V $v10m2
+; CHECK-NEXT: $v8m2 = VMV2R_V $v12m2
+; CHECK-NEXT: $v8 = VMV1R_V $v14

lukel97 wrote:

Shouldn't this be `$v10 = VMV1R_V $v14`?

https://github.com/llvm/llvm-project/pull/84455
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[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

2024-03-24 Thread Luke Lau via llvm-branch-commits 


@@ -302,102 +302,81 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock 
,
RISCVII::VLMUL LMul, unsigned NF) const 
{
   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
 
-  unsigned Opc;
-  unsigned SubRegIdx;
-  unsigned VVOpc, VIOpc;
-  switch (LMul) {
-  default:
-llvm_unreachable("Impossible LMUL for vector register copy.");
-  case RISCVII::LMUL_1:
-Opc = RISCV::VMV1R_V;
-SubRegIdx = RISCV::sub_vrm1_0;
-VVOpc = RISCV::PseudoVMV_V_V_M1;
-VIOpc = RISCV::PseudoVMV_V_I_M1;
-break;
-  case RISCVII::LMUL_2:
-Opc = RISCV::VMV2R_V;
-SubRegIdx = RISCV::sub_vrm2_0;
-VVOpc = RISCV::PseudoVMV_V_V_M2;
-VIOpc = RISCV::PseudoVMV_V_I_M2;
-break;
-  case RISCVII::LMUL_4:
-Opc = RISCV::VMV4R_V;
-SubRegIdx = RISCV::sub_vrm4_0;
-VVOpc = RISCV::PseudoVMV_V_V_M4;
-VIOpc = RISCV::PseudoVMV_V_I_M4;
-break;
-  case RISCVII::LMUL_8:
-assert(NF == 1);
-Opc = RISCV::VMV8R_V;
-SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0.
-VVOpc = RISCV::PseudoVMV_V_V_M8;
-VIOpc = RISCV::PseudoVMV_V_I_M8;
-break;
-  }
-
-  bool UseVMV_V_V = false;
-  bool UseVMV_V_I = false;
-  MachineBasicBlock::const_iterator DefMBBI;
-  if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
-UseVMV_V_V = true;
-Opc = VVOpc;
-
-if (DefMBBI->getOpcode() == VIOpc) {
-  UseVMV_V_I = true;
-  Opc = VIOpc;
-}
-  }
-
-  if (NF == 1) {
-auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg);
-if (UseVMV_V_V)
-  MIB.addReg(DstReg, RegState::Undef);
-if (UseVMV_V_I)
-  MIB = MIB.add(DefMBBI->getOperand(2));
-else
-  MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc));
-if (UseVMV_V_V) {
-  const MCInstrDesc  = DefMBBI->getDesc();
-  MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc)));  // AVL
-  MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
-  MIB.addImm(0);// tu, mu
-  MIB.addReg(RISCV::VL, RegState::Implicit);
-  MIB.addReg(RISCV::VTYPE, RegState::Implicit);
-}
-return;
-  }
-
-  int I = 0, End = NF, Incr = 1;
   unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
   unsigned DstEncoding = TRI->getEncodingValue(DstReg);
   unsigned LMulVal;
   bool Fractional;
   std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
   assert(!Fractional && "It is impossible be fractional lmul here.");
-  if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) {
-I = NF - 1;
-End = -1;
-Incr = -1;
-  }
+  unsigned NumRegs = NF * LMulVal;
+  bool ReversedCopy =
+  forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NumRegs);
+
+  unsigned I = 0;
+  auto GetCopyInfo = [&](MCRegister SrcReg, MCRegister DstReg)
+  -> std::tuple {
+unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
+unsigned DstEncoding = TRI->getEncodingValue(DstReg);
+if (!(SrcEncoding & 0b111) && !(DstEncoding & 0b111) && I + 8 <= NumRegs)

lukel97 wrote:

Ah ok, just wanted to check. I found it a bit hard to read but I'm not strongly 
opinionated

https://github.com/llvm/llvm-project/pull/84455
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[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

2024-03-24 Thread Luke Lau via llvm-branch-commits 


@@ -127,8 +127,21 @@ def XLenRI : RegInfoByHwMode<
   [RV32,  RV64],
   [RegInfo<32,32,32>, RegInfo<64,64,64>]>;
 
+class RISCVRegisterClass regTypes, int align, dag regList>
+: RegisterClass<"RISCV", regTypes, align, regList> {
+  bit IsVRegClass = 0;
+  int VLMul = 1;
+  int NF = 1;

lukel97 wrote:

Should these default to 0 since 0 is an invalid LMUL/NF?

https://github.com/llvm/llvm-project/pull/84894
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[llvm-branch-commits] [RISCV][NFC] Pass LMUL to copyPhysRegVector (PR #84448)

2024-03-24 Thread Luke Lau via llvm-branch-commits 

https://github.com/lukel97 approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/84448
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[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

2024-03-24 Thread Luke Lau via llvm-branch-commits 


@@ -302,102 +302,81 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock 
,
RISCVII::VLMUL LMul, unsigned NF) const 
{
   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
 
-  unsigned Opc;
-  unsigned SubRegIdx;
-  unsigned VVOpc, VIOpc;
-  switch (LMul) {
-  default:
-llvm_unreachable("Impossible LMUL for vector register copy.");
-  case RISCVII::LMUL_1:
-Opc = RISCV::VMV1R_V;
-SubRegIdx = RISCV::sub_vrm1_0;
-VVOpc = RISCV::PseudoVMV_V_V_M1;
-VIOpc = RISCV::PseudoVMV_V_I_M1;
-break;
-  case RISCVII::LMUL_2:
-Opc = RISCV::VMV2R_V;
-SubRegIdx = RISCV::sub_vrm2_0;
-VVOpc = RISCV::PseudoVMV_V_V_M2;
-VIOpc = RISCV::PseudoVMV_V_I_M2;
-break;
-  case RISCVII::LMUL_4:
-Opc = RISCV::VMV4R_V;
-SubRegIdx = RISCV::sub_vrm4_0;
-VVOpc = RISCV::PseudoVMV_V_V_M4;
-VIOpc = RISCV::PseudoVMV_V_I_M4;
-break;
-  case RISCVII::LMUL_8:
-assert(NF == 1);
-Opc = RISCV::VMV8R_V;
-SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0.
-VVOpc = RISCV::PseudoVMV_V_V_M8;
-VIOpc = RISCV::PseudoVMV_V_I_M8;
-break;
-  }
-
-  bool UseVMV_V_V = false;
-  bool UseVMV_V_I = false;
-  MachineBasicBlock::const_iterator DefMBBI;
-  if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
-UseVMV_V_V = true;
-Opc = VVOpc;
-
-if (DefMBBI->getOpcode() == VIOpc) {
-  UseVMV_V_I = true;
-  Opc = VIOpc;
-}
-  }
-
-  if (NF == 1) {
-auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg);
-if (UseVMV_V_V)
-  MIB.addReg(DstReg, RegState::Undef);
-if (UseVMV_V_I)
-  MIB = MIB.add(DefMBBI->getOperand(2));
-else
-  MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc));
-if (UseVMV_V_V) {
-  const MCInstrDesc  = DefMBBI->getDesc();
-  MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc)));  // AVL
-  MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
-  MIB.addImm(0);// tu, mu
-  MIB.addReg(RISCV::VL, RegState::Implicit);
-  MIB.addReg(RISCV::VTYPE, RegState::Implicit);
-}
-return;
-  }
-
-  int I = 0, End = NF, Incr = 1;
   unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
   unsigned DstEncoding = TRI->getEncodingValue(DstReg);
   unsigned LMulVal;
   bool Fractional;
   std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
   assert(!Fractional && "It is impossible be fractional lmul here.");
-  if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) {
-I = NF - 1;
-End = -1;
-Incr = -1;
-  }
+  unsigned NumRegs = NF * LMulVal;
+  bool ReversedCopy =
+  forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NumRegs);
+
+  unsigned I = 0;
+  auto GetCopyInfo = [&](MCRegister SrcReg, MCRegister DstReg)
+  -> std::tuple {
+unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
+unsigned DstEncoding = TRI->getEncodingValue(DstReg);
+if (!(SrcEncoding & 0b111) && !(DstEncoding & 0b111) && I + 8 <= NumRegs)

lukel97 wrote:

Is this the same as `SrcEncoding % 8 == 0 && DstEncoding % 8 == 0`?

https://github.com/llvm/llvm-project/pull/84455
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[llvm-branch-commits] [RISCV] Pass LMUL to copyPhysRegVector (PR #84448)

2024-03-08 Thread Luke Lau via llvm-branch-commits 

https://github.com/lukel97 commented:

Is this NFC?

https://github.com/llvm/llvm-project/pull/84448
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[llvm-branch-commits] [llvm] release/18.x: [SelectionDAG] Change computeAliasing signature from optional to LocationSize. (#83017) (PR #83848)

2024-03-04 Thread Luke Lau via llvm-branch-commits 

lukel97 wrote:

Superseded by #83856 

https://github.com/llvm/llvm-project/pull/83848
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[llvm-branch-commits] [llvm] release/18.x: [SelectionDAG] Change computeAliasing signature from optional to LocationSize. (#83017) (PR #83848)

2024-03-04 Thread Luke Lau via llvm-branch-commits 

https://github.com/lukel97 closed 
https://github.com/llvm/llvm-project/pull/83848
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[llvm-branch-commits] [llvm] release/18.x: [SelectionDAG] Change computeAliasing signature from optional to LocationSize. (#83017) (PR #83848)

2024-03-04 Thread Luke Lau via llvm-branch-commits 

lukel97 wrote:

> I think the "Requested by" comes from the git committer.

There's a PR open to fix this: #82680 

> @lukel97 i'm not sure if you have already or not, but it might be good to 
> include the recent test you added too.

Sure thing, I can't see a way of editing/pushing more commits to this PR's 
branch though. I'll close this and create another PR.

https://github.com/llvm/llvm-project/pull/83848
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[llvm-branch-commits] [llvm] Revert "[RISCV] Recurse on first operand of two operand shuffles (#79180)" (PR #80238)

2024-02-13 Thread Luke Lau via llvm-branch-commits 

https://github.com/lukel97 milestoned 
https://github.com/llvm/llvm-project/pull/80238
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[llvm-branch-commits] [llvm] [RISCV] Backport 5cf9f2cd9888feea23a624c1de3cc37ce8ce8112 to release/18.x (PR #79931)

2024-01-29 Thread Luke Lau via llvm-branch-commits 

https://github.com/lukel97 created 
https://github.com/llvm/llvm-project/pull/79931

This cherry picks a fix 5cf9f2cd9888feea23a624c1de3cc37ce8ce8112 for a 
miscompile (only with the -mrvv-vector-bits=zvl configuration or similar) 
introduced in bb8a8770e203ba027d141cd1200e93809ea66c8f, which is present in the 
18.x release branch. It also includes a commit that adds a test 
d407e6ca61a422f25841674d8f0b5ea0dbec85f8

>From 5b3331f29489446d7d723a33310b7fec37153976 Mon Sep 17 00:00:00 2001
From: Luke Lau 
Date: Fri, 26 Jan 2024 20:16:21 +0700
Subject: [PATCH 1/2] [RISCV] Add test to showcase miscompile from #79072

---
 .../rvv/fixed-vectors-shuffle-exact-vlen.ll| 18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll 
b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
index f53b51e05c572..c0b02f62444ef 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
@@ -138,8 +138,8 @@ define <4 x i64> @m2_splat_two_source(<4 x i64> %v1, <4 x 
i64> %v2) vscale_range
   ret <4 x i64> %res
 }
 
-define <4 x i64> @m2_splat_into_identity_two_source(<4 x i64> %v1, <4 x i64> 
%v2) vscale_range(2,2) {
-; CHECK-LABEL: m2_splat_into_identity_two_source:
+define <4 x i64> @m2_splat_into_identity_two_source_v2_hi(<4 x i64> %v1, <4 x 
i64> %v2) vscale_range(2,2) {
+; CHECK-LABEL: m2_splat_into_identity_two_source_v2_hi:
 ; CHECK:   # %bb.0:
 ; CHECK-NEXT:vsetivli zero, 2, e64, m1, ta, ma
 ; CHECK-NEXT:vrgather.vi v10, v8, 0
@@ -149,6 +149,20 @@ define <4 x i64> @m2_splat_into_identity_two_source(<4 x 
i64> %v1, <4 x i64> %v2
   ret <4 x i64> %res
 }
 
+; FIXME: This is a miscompile, we're clobbering the lower reg group of %v2
+; (v10), and the vmv1r.v is moving from the wrong reg group (should be v10)
+define <4 x i64> @m2_splat_into_slide_two_source_v2_lo(<4 x i64> %v1, <4 x 
i64> %v2) vscale_range(2,2) {
+; CHECK-LABEL: m2_splat_into_slide_two_source_v2_lo:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT:vrgather.vi v10, v8, 0
+; CHECK-NEXT:vmv1r.v v11, v8
+; CHECK-NEXT:vmv2r.v v8, v10
+; CHECK-NEXT:ret
+  %res = shufflevector <4 x i64> %v1, <4 x i64> %v2, <4 x i32> 
+  ret <4 x i64> %res
+}
+
 define <4 x i64> @m2_splat_into_slide_two_source(<4 x i64> %v1, <4 x i64> %v2) 
vscale_range(2,2) {
 ; CHECK-LABEL: m2_splat_into_slide_two_source:
 ; CHECK:   # %bb.0:

>From 60341586c8bd46b1094663749ac6467058b7efe8 Mon Sep 17 00:00:00 2001
From: Luke Lau 
Date: Fri, 26 Jan 2024 20:18:08 +0700
Subject: [PATCH 2/2] [RISCV] Fix M1 shuffle on wrong SrcVec in
 lowerShuffleViaVRegSplitting

This fixes a miscompile from #79072 where we were taking the wrong SrcVec to do
the M1 shuffle. E.g. if the SrcVecIdx was 2 and we had 2 VRegsPerSrc, we ended
up taking it from V1 instead of V2.
---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp   | 2 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll | 8 +++-
 2 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp 
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 47c6cd6e5487b..7895d74f06d12 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4718,7 +4718,7 @@ static SDValue 
lowerShuffleViaVRegSplitting(ShuffleVectorSDNode *SVN,
 if (SrcVecIdx == -1)
   continue;
 unsigned ExtractIdx = (SrcVecIdx % VRegsPerSrc) * NumOpElts;
-SDValue SrcVec = (unsigned)SrcVecIdx > VRegsPerSrc ? V2 : V1;
+SDValue SrcVec = (unsigned)SrcVecIdx >= VRegsPerSrc ? V2 : V1;
 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, SrcVec,
  DAG.getVectorIdxConstant(ExtractIdx, DL));
 SubVec = convertFromScalableVector(OneRegVT, SubVec, DAG, Subtarget);
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll 
b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
index c0b02f62444ef..3f0bdb9d5e316 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
@@ -149,15 +149,13 @@ define <4 x i64> 
@m2_splat_into_identity_two_source_v2_hi(<4 x i64> %v1, <4 x i6
   ret <4 x i64> %res
 }
 
-; FIXME: This is a miscompile, we're clobbering the lower reg group of %v2
-; (v10), and the vmv1r.v is moving from the wrong reg group (should be v10)
 define <4 x i64> @m2_splat_into_slide_two_source_v2_lo(<4 x i64> %v1, <4 x 
i64> %v2) vscale_range(2,2) {
 ; CHECK-LABEL: m2_splat_into_slide_two_source_v2_lo:
 ; CHECK:   # %bb.0:
 ; CHECK-NEXT:vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT:vrgather.vi v10, v8, 0
-; CHECK-NEXT:vmv1r.v v11, v8
-; CHECK-NEXT:vmv2r.v v8, v10
+; CHECK-NEXT:vrgather.vi v12, v8, 0
+; CHECK-NEXT:

[llvm-branch-commits] [llvm] [RISCV] Backport 5cf9f2cd9888feea23a624c1de3cc37ce8ce8112 to release/18.x (PR #79931)

2024-01-29 Thread Luke Lau via llvm-branch-commits 

https://github.com/lukel97 milestoned 
https://github.com/llvm/llvm-project/pull/79931
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[llvm-branch-commits] [llvm] c0b9269 - [RISCV] Add helper to copy the AVL of another VSETVLIInfo. NFC

2023-11-30 Thread Luke Lau via llvm-branch-commits 

Author: Luke Lau
Date: 2023-11-30T15:19:46+08:00
New Revision: c0b926939829d9d4bb6ac5825e62f30960b6ed22

URL: 
https://github.com/llvm/llvm-project/commit/c0b926939829d9d4bb6ac5825e62f30960b6ed22
DIFF: 
https://github.com/llvm/llvm-project/commit/c0b926939829d9d4bb6ac5825e62f30960b6ed22.diff

LOG: [RISCV] Add helper to copy the AVL of another VSETVLIInfo. NFC

Added: 


Modified: 
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Removed: 




diff  --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp 
b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 3bbc85d836c3f4a..3bb648359e39dd6 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -477,6 +477,18 @@ class VSETVLIInfo {
 return AVLImm;
   }
 
+  void setAVL(VSETVLIInfo Info) {
+assert(Info.isValid());
+if (Info.isUnknown())
+  setUnknown();
+else if (Info.hasAVLReg())
+  setAVLReg(Info.getAVLReg());
+else {
+  assert(Info.hasAVLImm());
+  setAVLImm(Info.getAVLImm());
+}
+  }
+
   unsigned getSEW() const { return SEW; }
   RISCVII::VLMUL getVLMUL() const { return VLMul; }
 
@@ -1054,10 +1066,7 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo 
,
   // TODO: We can probably relax this for immediates.
   if (Demanded.VLZeroness && !Demanded.VLAny && PrevInfo.isValid() &&
   PrevInfo.hasEquallyZeroAVL(Info, *MRI) && Info.hasSameVLMAX(PrevInfo)) {
-if (PrevInfo.hasAVLImm())
-  Info.setAVLImm(PrevInfo.getAVLImm());
-else
-  Info.setAVLReg(PrevInfo.getAVLReg());
+Info.setAVL(PrevInfo);
 return;
   }
 
@@ -1074,10 +1083,7 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo 
,
   VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
   if (DefInfo.hasSameVLMAX(Info) &&
   (DefInfo.hasAVLImm() || DefInfo.getAVLReg() == RISCV::X0)) {
-if (DefInfo.hasAVLImm())
-  Info.setAVLImm(DefInfo.getAVLImm());
-else
-  Info.setAVLReg(DefInfo.getAVLReg());
+Info.setAVL(DefInfo);
 return;
   }
 }



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