[llvm-branch-commits] [llvm] release/18.x: [InterleavedLoadCombine] Bail out on non-byte-sized vector element type (#90705) (PR #90805)

2024-05-09 Thread Tom Stellard via llvm-branch-commits 

tstellar wrote:

@nikic (or anyone else). If you would like to add a note about this fix in the 
release notes (completely optional). Please reply to this comment with a one or 
two sentence description of the fix.  When you are done, please add the 
release:note label to this PR.

https://github.com/llvm/llvm-project/pull/90805
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[llvm-branch-commits] [llvm] release/18.x: [InterleavedLoadCombine] Bail out on non-byte-sized vector element type (#90705) (PR #90805)

2024-05-09 Thread Tom Stellard via llvm-branch-commits 

https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/90805
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[llvm-branch-commits] [llvm] release/18.x: [InterleavedLoadCombine] Bail out on non-byte-sized vector element type (#90705) (PR #90805)

2024-05-09 Thread Tom Stellard via llvm-branch-commits 

https://github.com/tstellar updated 
https://github.com/llvm/llvm-project/pull/90805

>From d9a7e5179a89624f23d8d6993e7e9ec8887063fc Mon Sep 17 00:00:00 2001
From: Nikita Popov 
Date: Thu, 2 May 2024 09:38:09 +0900
Subject: [PATCH] [InterleavedLoadCombine] Bail out on non-byte-sized vector
 element type (#90705)

Vectors are always tightly packed, and elements of non-byte-sized
usually do not have a well-defined (byte) offset.

Fixes https://github.com/llvm/llvm-project/issues/90695.

(cherry picked from commit d484c4d3501a7ff3d00a6e0cfad026a3b01d320c)
---
 .../CodeGen/InterleavedLoadCombinePass.cpp|  3 +++
 .../interleaved-load-combine-pr90695.ll   | 19 +++
 2 files changed, 22 insertions(+)
 create mode 100644 
llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll

diff --git a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp 
b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
index f2d5c3c867c2d..bbb0b654dc67b 100644
--- a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
+++ b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
@@ -877,6 +877,9 @@ struct VectorInfo {
 if (LI->isAtomic())
   return false;
 
+if (!DL.typeSizeEqualsStoreSize(Result.VTy->getElementType()))
+  return false;
+
 // Get the base polynomial
 computePolynomialFromPointer(*LI->getPointerOperand(), Offset, BasePtr, 
DL);
 
diff --git a/llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll 
b/llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll
new file mode 100644
index 0..ee75b3a083f71
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 
UTC_ARGS: --version 4
+; RUN: opt -S -passes=interleaved-load-combine < %s | FileCheck %s
+
+target triple = "aarch64-unknown-windows-gnu"
+
+; Make sure we don't crash on loads of vectors of non-byte-sized types.
+define <4 x i1> @test(ptr %p) {
+; CHECK-LABEL: define <4 x i1> @test(
+; CHECK-SAME: ptr [[P:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:[[LOAD:%.*]] = load <2 x i1>, ptr [[P]], align 1
+; CHECK-NEXT:[[SHUF:%.*]] = shufflevector <2 x i1> [[LOAD]], <2 x i1> 
zeroinitializer, <4 x i32> 
+; CHECK-NEXT:ret <4 x i1> [[SHUF]]
+;
+entry:
+  %load = load <2 x i1>, ptr %p, align 1
+  %shuf = shufflevector <2 x i1> %load, <2 x i1> zeroinitializer, <4 x i32> 

+  ret <4 x i1> %shuf
+}

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[llvm-branch-commits] [llvm] release/18.x: [InterleavedLoadCombine] Bail out on non-byte-sized vector element type (#90705) (PR #90805)

2024-05-01 Thread Andrew Kelley via llvm-branch-commits 

andrewrk wrote:

Yes please

https://github.com/llvm/llvm-project/pull/90805
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[llvm-branch-commits] [llvm] release/18.x: [InterleavedLoadCombine] Bail out on non-byte-sized vector element type (#90705) (PR #90805)

2024-05-01 Thread via llvm-branch-commits 

llvmbot wrote:




@llvm/pr-subscribers-backend-aarch64

Author: None (llvmbot)


Changes

Backport d484c4d3501a7ff3d00a6e0cfad026a3b01d320c

Requested by: @nikic

---
Full diff: https://github.com/llvm/llvm-project/pull/90805.diff


2 Files Affected:

- (modified) llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp (+3) 
- (added) llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll (+19) 


``diff
diff --git a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp 
b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
index f2d5c3c867c2dd..bbb0b654dc67ba 100644
--- a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
+++ b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
@@ -877,6 +877,9 @@ struct VectorInfo {
 if (LI->isAtomic())
   return false;
 
+if (!DL.typeSizeEqualsStoreSize(Result.VTy->getElementType()))
+  return false;
+
 // Get the base polynomial
 computePolynomialFromPointer(*LI->getPointerOperand(), Offset, BasePtr, 
DL);
 
diff --git a/llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll 
b/llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll
new file mode 100644
index 00..ee75b3a083f713
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 
UTC_ARGS: --version 4
+; RUN: opt -S -passes=interleaved-load-combine < %s | FileCheck %s
+
+target triple = "aarch64-unknown-windows-gnu"
+
+; Make sure we don't crash on loads of vectors of non-byte-sized types.
+define <4 x i1> @test(ptr %p) {
+; CHECK-LABEL: define <4 x i1> @test(
+; CHECK-SAME: ptr [[P:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:[[LOAD:%.*]] = load <2 x i1>, ptr [[P]], align 1
+; CHECK-NEXT:[[SHUF:%.*]] = shufflevector <2 x i1> [[LOAD]], <2 x i1> 
zeroinitializer, <4 x i32> 
+; CHECK-NEXT:ret <4 x i1> [[SHUF]]
+;
+entry:
+  %load = load <2 x i1>, ptr %p, align 1
+  %shuf = shufflevector <2 x i1> %load, <2 x i1> zeroinitializer, <4 x i32> 

+  ret <4 x i1> %shuf
+}

``




https://github.com/llvm/llvm-project/pull/90805
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[llvm-branch-commits] [llvm] release/18.x: [InterleavedLoadCombine] Bail out on non-byte-sized vector element type (#90705) (PR #90805)

2024-05-01 Thread via llvm-branch-commits 

llvmbot wrote:

@andrewrk What do you think about merging this PR to the release branch?

https://github.com/llvm/llvm-project/pull/90805
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[llvm-branch-commits] [llvm] release/18.x: [InterleavedLoadCombine] Bail out on non-byte-sized vector element type (#90705) (PR #90805)

2024-05-01 Thread via llvm-branch-commits 

https://github.com/llvmbot milestoned 
https://github.com/llvm/llvm-project/pull/90805
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[llvm-branch-commits] [llvm] release/18.x: [InterleavedLoadCombine] Bail out on non-byte-sized vector element type (#90705) (PR #90805)

2024-05-01 Thread via llvm-branch-commits 

https://github.com/llvmbot created 
https://github.com/llvm/llvm-project/pull/90805

Backport d484c4d3501a7ff3d00a6e0cfad026a3b01d320c

Requested by: @nikic

>From 8bbe1d7601f2f805ff0b9d108c640b068033a01d Mon Sep 17 00:00:00 2001
From: Nikita Popov 
Date: Thu, 2 May 2024 09:38:09 +0900
Subject: [PATCH] [InterleavedLoadCombine] Bail out on non-byte-sized vector
 element type (#90705)

Vectors are always tightly packed, and elements of non-byte-sized
usually do not have a well-defined (byte) offset.

Fixes https://github.com/llvm/llvm-project/issues/90695.

(cherry picked from commit d484c4d3501a7ff3d00a6e0cfad026a3b01d320c)
---
 .../CodeGen/InterleavedLoadCombinePass.cpp|  3 +++
 .../interleaved-load-combine-pr90695.ll   | 19 +++
 2 files changed, 22 insertions(+)
 create mode 100644 
llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll

diff --git a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp 
b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
index f2d5c3c867c2dd..bbb0b654dc67ba 100644
--- a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
+++ b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
@@ -877,6 +877,9 @@ struct VectorInfo {
 if (LI->isAtomic())
   return false;
 
+if (!DL.typeSizeEqualsStoreSize(Result.VTy->getElementType()))
+  return false;
+
 // Get the base polynomial
 computePolynomialFromPointer(*LI->getPointerOperand(), Offset, BasePtr, 
DL);
 
diff --git a/llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll 
b/llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll
new file mode 100644
index 00..ee75b3a083f713
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 
UTC_ARGS: --version 4
+; RUN: opt -S -passes=interleaved-load-combine < %s | FileCheck %s
+
+target triple = "aarch64-unknown-windows-gnu"
+
+; Make sure we don't crash on loads of vectors of non-byte-sized types.
+define <4 x i1> @test(ptr %p) {
+; CHECK-LABEL: define <4 x i1> @test(
+; CHECK-SAME: ptr [[P:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:[[LOAD:%.*]] = load <2 x i1>, ptr [[P]], align 1
+; CHECK-NEXT:[[SHUF:%.*]] = shufflevector <2 x i1> [[LOAD]], <2 x i1> 
zeroinitializer, <4 x i32> 
+; CHECK-NEXT:ret <4 x i1> [[SHUF]]
+;
+entry:
+  %load = load <2 x i1>, ptr %p, align 1
+  %shuf = shufflevector <2 x i1> %load, <2 x i1> zeroinitializer, <4 x i32> 

+  ret <4 x i1> %shuf
+}

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