[llvm-commits] CVS: llvm/lib/CodeGen/IntrinsicLowering.cpp
Changes in directory llvm/lib/CodeGen:
IntrinsicLowering.cpp updated: 1.37 - 1.38
---
Log message:
Add BSWAP stuff to intrinsic lowering for CBE friends.
---
Diffs of the changes: (+106 -2)
IntrinsicLowering.cpp | 108 +-
1 files changed, 106 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/IntrinsicLowering.cpp
diff -u llvm/lib/CodeGen/IntrinsicLowering.cpp:1.37
llvm/lib/CodeGen/IntrinsicLowering.cpp:1.38
--- llvm/lib/CodeGen/IntrinsicLowering.cpp:1.37 Thu Jan 12 20:22:08 2006
+++ llvm/lib/CodeGen/IntrinsicLowering.cpp Mon Jan 16 01:57:00 2006
@@ -128,8 +128,102 @@
}
}
+/// LowerBSWAP - Emit the code to lower bswap of V before the specified
+/// instruction IP.
+static Value *LowerBSWAP(Value *V, Instruction *IP) {
+ assert(V-getType()-isInteger() Can't bswap a non-integer type!);
+
+ const Type *DestTy = V-getType();
+
+ // Force to unsigned so that the shift rights are logical.
+ if (DestTy-isSigned())
+V = new CastInst(V, DestTy-getUnsignedVersion(), V-getName(), IP);
+
+ unsigned BitSize = V-getType()-getPrimitiveSizeInBits();
+
+ switch(BitSize) {
+ default: assert(0 Unhandled type size of value to byteswap!);
+ case 16: {
+Value *Tmp1 = new ShiftInst(Instruction::Shl, V,
+
ConstantInt::get(Type::UByteTy,8),bswap.2,IP);
+Value *Tmp2 = new ShiftInst(Instruction::Shr, V,
+
ConstantInt::get(Type::UByteTy,8),bswap.1,IP);
+V = BinaryOperator::createOr(Tmp1, Tmp2, bswap.i16, IP);
+break;
+ }
+ case 32: {
+Value *Tmp4 = new ShiftInst(Instruction::Shl, V,
+ ConstantInt::get(Type::UByteTy,24),bswap.4,
IP);
+Value *Tmp3 = new ShiftInst(Instruction::Shl, V,
+
ConstantInt::get(Type::UByteTy,8),bswap.3,IP);
+Value *Tmp2 = new ShiftInst(Instruction::Shr, V,
+
ConstantInt::get(Type::UByteTy,8),bswap.2,IP);
+Value *Tmp1 = new ShiftInst(Instruction::Shr, V,
+ ConstantInt::get(Type::UByteTy,24),bswap.1,
IP);
+Tmp3 = BinaryOperator::createAnd(Tmp3,
+ ConstantUInt::get(Type::UIntTy, 0xFF),
+ bswap.and3, IP);
+Tmp2 = BinaryOperator::createAnd(Tmp2,
+ ConstantUInt::get(Type::UIntTy, 0xFF00),
+ bswap.and2, IP);
+Tmp4 = BinaryOperator::createOr(Tmp4, Tmp3, bswap.or1, IP);
+Tmp2 = BinaryOperator::createOr(Tmp2, Tmp1, bswap.or2, IP);
+V = BinaryOperator::createOr(Tmp4, Tmp3, bswap.i32, IP);
+break;
+ }
+ case 64: {
+Value *Tmp8 = new ShiftInst(Instruction::Shl, V,
+ ConstantInt::get(Type::UByteTy,56),bswap.8,
IP);
+Value *Tmp7 = new ShiftInst(Instruction::Shl, V,
+ ConstantInt::get(Type::UByteTy,40),bswap.7,
IP);
+Value *Tmp6 = new ShiftInst(Instruction::Shl, V,
+ ConstantInt::get(Type::UByteTy,24),bswap.6,
IP);
+Value *Tmp5 = new ShiftInst(Instruction::Shl, V,
+
ConstantInt::get(Type::UByteTy,8),bswap.5,IP);
+Value *Tmp4 = new ShiftInst(Instruction::Shr, V,
+
ConstantInt::get(Type::UByteTy,8),bswap.4,IP);
+Value *Tmp3 = new ShiftInst(Instruction::Shr, V,
+ ConstantInt::get(Type::UByteTy,24),bswap.3,
IP);
+Value *Tmp2 = new ShiftInst(Instruction::Shr, V,
+ ConstantInt::get(Type::UByteTy,40),bswap.2,
IP);
+Value *Tmp1 = new ShiftInst(Instruction::Shr, V,
+ ConstantInt::get(Type::UByteTy,56),bswap.1,
IP);
+Tmp7 = BinaryOperator::createAnd(Tmp7,
+ ConstantUInt::get(Type::ULongTy,
0xFFULL),
+ bswap.and7, IP);
+Tmp6 = BinaryOperator::createAnd(Tmp6,
+ConstantUInt::get(Type::ULongTy,
0xFF00ULL),
+bswap.and6, IP);
+Tmp5 = BinaryOperator::createAnd(Tmp5,
+ ConstantUInt::get(Type::ULongTy,
0xFFULL),
+ bswap.and5, IP);
+Tmp4 = BinaryOperator::createAnd(Tmp4,
+ConstantUInt::get(Type::ULongTy,
0xFF00ULL),
+bswap.and4, IP);
+Tmp3 = BinaryOperator::createAnd(Tmp3,
+ ConstantUInt::get(Type::ULongTy,
0xFFULL),
+ bswap.and3, IP);
+Tmp2 = BinaryOperator::createAnd(Tmp2,
+ConstantUInt::get(Type::ULongTy,
0xFF00ULL),
+bswap.and2, IP);
+Tmp8 = BinaryOperator::createOr(Tmp8, Tmp7, bswap.or1, IP);
+Tmp6 = BinaryOperator::createOr(Tmp6, Tmp5, bswap.or2, IP);
[llvm-commits] CVS: llvm/docs/ExtendingLLVM.html
Changes in directory llvm/docs: ExtendingLLVM.html updated: 1.20 - 1.21 --- Log message: Fix up 'adding an intrinsic' section a bit, first draft of 'adding a new sdnode' section. --- Diffs of the changes: (+116 -41) ExtendingLLVM.html | 157 +++-- 1 files changed, 116 insertions(+), 41 deletions(-) Index: llvm/docs/ExtendingLLVM.html diff -u llvm/docs/ExtendingLLVM.html:1.20 llvm/docs/ExtendingLLVM.html:1.21 --- llvm/docs/ExtendingLLVM.html:1.20 Fri Jan 13 19:27:10 2006 +++ llvm/docs/ExtendingLLVM.htmlMon Jan 16 01:54:23 2006 @@ -16,6 +16,7 @@ lia href=#introductionIntroduction and Warning/a/li lia href=#intrinsicAdding a new intrinsic function/a/li lia href=#instructionAdding a new instruction/a/li + lia href=#sdnodeAdding a new SelectionDAG node/a/li lia href=#typeAdding a new type/a ol lia href=#fund_typeAdding a new fundamental type/a/li @@ -105,9 +106,8 @@ effects, add it to the list of intrinsics in the ttisInstructionTriviallyDead/tt function./li -liTest your intrinsic/li - -littllvm/test/Regression/*/tt: add your test cases to the test suite/li +littllvm/test/Regression/*/tt: Add test cases for your test cases to the +test suite/li /ol pOnce the intrinsic has been added to the system, you must add code generator @@ -116,48 +116,123 @@ dl dtAdd support to the C backend in ttlib/Target/CBackend//tt/dt -ddDepending on the intrinsic, there are a few ways to implement this. First, -if it makes sense to lower the intrinsic to an expanded sequence of C code in -all cases, just emit the expansion in ttvisitCallInst/tt. Second, if the -intrinsic has some way to express it with GCC (or any other compiler) -extensions, it can be conditionally supported based on the compiler compiling -the CBE output (see llvm.prefetch for an example). Third, if the intrinsic -really has no way to be lowered, just have the code generator emit code that -prints an error message and calls abort if executed. +ddDepending on the intrinsic, there are a few ways to implement this. For +most intrinsics, it makes sense to add code to lower your intrinsic in +ttLowerIntrinsicCall/tt in ttlib/CodeGen/IntrinsicLowering.cpp/tt. +Second, if it makes sense to lower the intrinsic to an expanded sequence of C +code in all cases, just emit the expansion in ttvisitCallInst/tt in +ttWriter.cpp/tt. If the intrinsic has some way to express it with GCC +(or any other compiler) extensions, it can be conditionally supported based on +the compiler compiling the CBE output (see llvm.prefetch for an example). +Third, if the intrinsic really has no way to be lowered, just have the code +generator emit code that prints an error message and calls abort if executed. /dd -dtAdd a enum value for the SelectionDAG node in -ttinclude/llvm/CodeGen/SelectionDAGNodes.h/tt/dt +dl +dtAdd support to the SelectionDAG Instruction Selector in +ttlib/CodeGen/SelectionDAG//tt/dt + +ddSince most targets in LLVM use the SelectionDAG framework for generating +code, you will likely need to add support for your intrinsic there as well. +This is usually accomplished by adding a new node, and then teaching the +SelectionDAG code how to handle that node. To do this, follow the steps in +the next section, Adding a new SelectionDAG node./dd -ddAlso, add code to ttlib/CodeGen/SelectionDAG/SelectionDAG.cpp/tt (and -ttSelectionDAGPrinter.cpp/tt) to print the node./dd +dl +dtOnce you have added the new node, add code to +ttSelectionDAG/SelectionDAGISel.cpp/tt to recognize the intrinsic. In most +cases, the intrinsic will just be turned into the node you just added. For an +example of this, see how ttvisitIntrinsicCall/tt handles Intrinsic::ctpop +/dt -dtAdd code to ttSelectionDAG/SelectionDAGISel.cpp/tt to recognize the -intrinsic./dt +/div -ddPresumably the intrinsic should be recognized and turned into the node you -added above./dd - -dtAdd code to ttSelectionDAG/LegalizeDAG.cpp/tt to a -href=CodeGenerator.html#selectiondag_legalizelegalize, promote, and -expand/a the node as necessary./dt - -ddIf the intrinsic can be expanded to primitive operations, legalize can break -the node down into other elementary operations that are be supported./dd - -dtAdd target-specific support to specific code generators./dt - -ddExtend the code generators you are interested in to recognize and support -the node, emitting the code you want./dd -/dl - -p -Unfortunately, the process of extending the code generator to support a new node -is not extremely well documented. As such, it is often helpful to look at other -intrinsics (e.g. ttllvm.ctpop/tt) to see how they are recognized and turned -into a node by ttSelectionDAGISel.cpp/tt, legalized by -ttLegalizeDAG.cpp/tt, then finally emitted by the various code generators. -/p +!-- *** -- +div class=doc_section + a name=sdnodeAdding a new
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAG.cpp updated: 1.239 - 1.240
---
Log message:
Constant fold ctpop/ctlz/cttz, and a couple other small cleanups
---
Diffs of the changes: (+58 -2)
SelectionDAG.cpp | 60 +--
1 files changed, 58 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.239
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.240
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.239Sun Jan 15
02:39:35 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Jan 16 02:07:10 2006
@@ -32,6 +32,8 @@
switch (Opcode) {
case ISD::ADD:
case ISD::MUL:
+ case ISD::MULHU:
+ case ISD::MULHS:
case ISD::FADD:
case ISD::FMUL:
case ISD::AND:
@@ -828,6 +830,7 @@
SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
SDOperand Operand) {
+ unsigned Tmp1;
// Constant fold unary operations with an integer constant operand.
if (ConstantSDNode *C = dyn_castConstantSDNode(Operand.Val)) {
uint64_t Val = C-getValue();
@@ -848,6 +851,59 @@
return getConstantFP(BitsToDouble(Val), VT);
}
break;
+case ISD::BSWAP:
+ switch(VT) {
+ default: assert(0 Invalid bswap!); break;
+ case MVT::i16: return getConstant(ByteSwap_16((unsigned short)Val), VT);
+ case MVT::i32: return getConstant(ByteSwap_32((unsigned)Val), VT);
+ case MVT::i64: return getConstant(ByteSwap_64(Val), VT);
+ }
+ break;
+case ISD::CTPOP:
+ switch(VT) {
+ default: assert(0 Invalid ctpop!); break;
+ case MVT::i1: return getConstant(Val != 0, VT);
+ case MVT::i8:
+Tmp1 = (unsigned)Val 0xFF;
+return getConstant(CountPopulation_32(Tmp1), VT);
+ case MVT::i16:
+Tmp1 = (unsigned)Val 0x;
+return getConstant(CountPopulation_32(Tmp1), VT);
+ case MVT::i32:
+return getConstant(CountPopulation_32((unsigned)Val), VT);
+ case MVT::i64:
+return getConstant(CountPopulation_64(Val), VT);
+ }
+case ISD::CTLZ:
+ switch(VT) {
+ default: assert(0 Invalid ctlz!); break;
+ case MVT::i1: return getConstant(Val == 0, VT);
+ case MVT::i8:
+Tmp1 = (unsigned)Val 0xFF;
+return getConstant(CountLeadingZeros_32(Tmp1)-24, VT);
+ case MVT::i16:
+Tmp1 = (unsigned)Val 0x;
+return getConstant(CountLeadingZeros_32(Tmp1)-16, VT);
+ case MVT::i32:
+return getConstant(CountLeadingZeros_32((unsigned)Val), VT);
+ case MVT::i64:
+return getConstant(CountLeadingZeros_64(Val), VT);
+ }
+case ISD::CTTZ:
+ switch(VT) {
+ default: assert(0 Invalid cttz!); break;
+ case MVT::i1: return getConstant(Val == 0, VT);
+ case MVT::i8:
+Tmp1 = (unsigned)Val | 0x100;
+return getConstant(CountTrailingZeros_32(Tmp1), VT);
+ case MVT::i16:
+Tmp1 = (unsigned)Val | 0x1;
+return getConstant(CountTrailingZeros_32(Tmp1), VT);
+ case MVT::i32:
+return getConstant(CountTrailingZeros_32((unsigned)Val), VT);
+ case MVT::i64:
+return getConstant(CountTrailingZeros_64(Val), VT);
+ }
}
}
@@ -1926,7 +1982,6 @@
case ISD::SRL:return srl;
case ISD::ROTL: return rotl;
case ISD::ROTR: return rotr;
- case ISD::BSWAP: return bswap;
case ISD::FADD: return fadd;
case ISD::FSUB: return fsub;
case ISD::FMUL: return fmul;
@@ -1993,7 +2048,8 @@
case ISD::MEMCPY: return memcpy;
case ISD::MEMMOVE: return memmove;
- // Bit counting
+ // Bit manipulation
+ case ISD::BSWAP: return bswap;
case ISD::CTPOP: return ctpop;
case ISD::CTTZ:return cttz;
case ISD::CTLZ:return ctlz;
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.266 - 1.267
---
Log message:
Expand case for 64b Legalize, even though no one should end up using this
(itanium supports bswap natively, alpha should custom lower it using the
VAX floating point swapload, ha ha).
---
Diffs of the changes: (+43 -4)
LegalizeDAG.cpp | 47 +++
1 files changed, 43 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.266
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.267
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.266 Sun Jan 15 02:54:32 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Jan 16 01:59:13 2006
@@ -2179,12 +2179,12 @@
Tmp2 = LegalizeOp(Node-getOperand(1)); // RHS
switch (TLI.getOperationAction(Node-getOpcode(), Node-getValueType(0))) {
case TargetLowering::Custom: {
- Result = DAG.getNode(Node-getOpcode(), Node-getValueType(0), Tmp1,
Tmp2);
+ Result = DAG.getNode(Node-getOpcode(), Node-getValueType(0),
Tmp1,Tmp2);
SDOperand Tmp = TLI.LowerOperation(Result, DAG);
if (Tmp.Val) {
- Tmp = LegalizeOp(Tmp); // Relegalize input.
- AddLegalizedOperand(Op, Tmp);
- return Tmp;
+Tmp = LegalizeOp(Tmp); // Relegalize input.
+AddLegalizedOperand(Op, Tmp);
+return Tmp;
} //else it was considered legal and we fall through
}
case TargetLowering::Legal:
@@ -2276,6 +2276,45 @@
Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
Result = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
break;
+case MVT::i64: {
+ SDOperand Tmp5, Tmp6, Tmp7, Tmp8;
+ Tmp8 = DAG.getNode(ISD::SHL, VT, Tmp1,
+ DAG.getConstant(56, TLI.getShiftAmountTy()));
+ Tmp7 = DAG.getNode(ISD::SHL, VT, Tmp1,
+ DAG.getConstant(40, TLI.getShiftAmountTy()));
+ Tmp6 = DAG.getNode(ISD::SHL, VT, Tmp1,
+ DAG.getConstant(24, TLI.getShiftAmountTy()));
+ Tmp5 = DAG.getNode(ISD::SHL, VT, Tmp1,
+ DAG.getConstant(8, TLI.getShiftAmountTy()));
+ Tmp4 = DAG.getNode(ISD::SRL, VT, Tmp1,
+ DAG.getConstant(8, TLI.getShiftAmountTy()));
+ Tmp3 = DAG.getNode(ISD::SRL, VT, Tmp1,
+ DAG.getConstant(24, TLI.getShiftAmountTy()));
+ Tmp2 = DAG.getNode(ISD::SRL, VT, Tmp1,
+ DAG.getConstant(40, TLI.getShiftAmountTy()));
+ Tmp1 = DAG.getNode(ISD::SRL, VT, Tmp1,
+ DAG.getConstant(56, TLI.getShiftAmountTy()));
+ Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7,
+ DAG.getConstant(0x00FFULL, VT));
+ Tmp6 = DAG.getNode(ISD::AND, VT, Tmp7,
+ DAG.getConstant(0xFF00ULL, VT));
+ Tmp5 = DAG.getNode(ISD::AND, VT, Tmp7,
+ DAG.getConstant(0x00FFULL, VT));
+ Tmp4 = DAG.getNode(ISD::AND, VT, Tmp7,
+ DAG.getConstant(0xFF00ULL, VT));
+ Tmp3 = DAG.getNode(ISD::AND, VT, Tmp7,
+ DAG.getConstant(0x00FFULL, VT));
+ Tmp2 = DAG.getNode(ISD::AND, VT, Tmp7,
+ DAG.getConstant(0xFF00ULL, VT));
+ Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
+ Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
+ Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
+ Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
+ Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
+ Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
+ Result = DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
+ break;
+}
}
break;
}
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.22 - 1.23
---
Log message:
fixing divides: FP should now be 100%, and integers are fine too
unless you try to div/mod 0 by anything, in which case you will
get some cute number, and not 0, which is bad.
---
Diffs of the changes: (+24 -17)
IA64ISelDAGToDAG.cpp | 41 -
1 files changed, 24 insertions(+), 17 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.22
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.23
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.22 Mon Jan 16 00:33:38 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Mon Jan 16 08:33:04 2006
@@ -183,6 +183,10 @@
SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
SDOperand Result;
+
+// we'll need copies of F0 and F1
+SDOperand F0 = CurDAG-getRegister(IA64::F0, MVT::f64);
+SDOperand F1 = CurDAG-getRegister(IA64::F1, MVT::f64);
// OK, emit some code:
@@ -200,12 +204,10 @@
TmpF4 = CurDAG-getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2);
Chain = TmpF4.getValue(1);
} else { // is unsigned
-if(isModulus) { /* unsigned integer divides do not need any fcvt.x*f*
insns */
- TmpF3 = CurDAG-getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1);
- Chain = TmpF3.getValue(1);
- TmpF4 = CurDAG-getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2);
- Chain = TmpF4.getValue(1);
-}
+TmpF3 = CurDAG-getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1);
+Chain = TmpF3.getValue(1);
+TmpF4 = CurDAG-getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2);
+Chain = TmpF4.getValue(1);
}
} else { // this is an FP divide/remainder, so we 'leak' some temp
@@ -226,10 +228,6 @@
TmpPR = TmpF5.getValue(1);
Chain = TmpF5.getValue(2);
-// we'll need copies of F0 and F1
-SDOperand F0 = CurDAG-getRegister(IA64::F0, MVT::f64);
-SDOperand F1 = CurDAG-getRegister(IA64::F1, MVT::f64);
-
SDOperand minusB;
if(isModulus) { // for remainders, it'll be handy to have
// copies of -input_b
@@ -276,7 +274,7 @@
// we two-address hack it. See the comment for this to work... on
// page 48 of Intel application note #245415
Result = CurDAG-getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
-TmpY3, TmpR0, TmpQ0, TmpPR);
+TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR);
Chain = Result.getValue(1);
return Result; // XXX: early exit!
} else { // this is *not* an FP divide, so there's a bit left to do:
@@ -290,13 +288,22 @@
TmpF4, TmpQ2, TmpF3, TmpPR);
Chain = TmpR2.getValue(1);
-// we want TmpQ3 to have the same target register as the frcpa, so
-// we two-address hack it. See the comment for this to work... on
-// page 48 of Intel application note #245415
- TmpQ3 = CurDAG-getTargetNode(IA64::TCFMAS1, MVT::f64,
-TmpR2, TmpR2, TmpY2, TmpQ2, TmpPR);
+// we want TmpQ3 to have the same target register as the frcpa? maybe we
+// should two-address hack it. See the comment for this to work... on page
+// 48 of Intel application note #245415
+ TmpQ3 = CurDAG-getTargetNode(IA64::CFMAS1, MVT::f64,
+TmpR2, TmpY2, TmpQ2, TmpPR);
Chain = TmpQ3.getValue(1);
-
+
+ // FIXME: this is unfortunate :(
+ // the story is that the dest reg of the fnma above and the fma below it
+ // (and therefore the src of the fcvt.fx[u] below as well) cannot
+ // be the same register, or this code breaks if the first argument is
+ // zero. (e.g. without this hack, 0%8 yields -64, not 0.)
+/* XXX: these two lines do nothing */
+ SDOperand bogus = CurDAG-getTargetNode(IA64::IUSE, MVT::Other, TmpR2);
+ Chain = bogus.getValue(0);
+
if(isSigned)
TmpQ = CurDAG-getTargetNode(IA64::FCVTFXTRUNCS1, MVT::f64, TmpQ3);
else
___
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[llvm-commits] CVS: llvm/docs/ExtendingLLVM.html
Changes in directory llvm/docs: ExtendingLLVM.html updated: 1.21 - 1.22 --- Log message: Add a couple very minor tweaks --- Diffs of the changes: (+12 -8) ExtendingLLVM.html | 20 1 files changed, 12 insertions(+), 8 deletions(-) Index: llvm/docs/ExtendingLLVM.html diff -u llvm/docs/ExtendingLLVM.html:1.21 llvm/docs/ExtendingLLVM.html:1.22 --- llvm/docs/ExtendingLLVM.html:1.21 Mon Jan 16 01:54:23 2006 +++ llvm/docs/ExtendingLLVM.htmlMon Jan 16 10:31:40 2006 @@ -26,7 +26,8 @@ div class=doc_author pWritten by a href=http://misha.brukman.net;Misha Brukman/a, - Brad Jones, and a href=http://nondot.org/sabre;Chris Lattner/a/p + Brad Jones, Nate Begeman, + and a href=http://nondot.org/sabre;Chris Lattner/a/p /div !-- *** -- @@ -123,7 +124,8 @@ code in all cases, just emit the expansion in ttvisitCallInst/tt in ttWriter.cpp/tt. If the intrinsic has some way to express it with GCC (or any other compiler) extensions, it can be conditionally supported based on -the compiler compiling the CBE output (see llvm.prefetch for an example). +the compiler compiling the CBE output (see ttllvm.prefetch/tt for an +example). Third, if the intrinsic really has no way to be lowered, just have the code generator emit code that prints an error message and calls abort if executed. /dd @@ -136,13 +138,14 @@ code, you will likely need to add support for your intrinsic there as well. This is usually accomplished by adding a new node, and then teaching the SelectionDAG code how to handle that node. To do this, follow the steps in -the next section, Adding a new SelectionDAG node./dd +the a href=#sdnodeAdding a new SelectionDAG node/a section./dd dl dtOnce you have added the new node, add code to ttSelectionDAG/SelectionDAGISel.cpp/tt to recognize the intrinsic. In most cases, the intrinsic will just be turned into the node you just added. For an -example of this, see how ttvisitIntrinsicCall/tt handles Intrinsic::ctpop +example of this, see how ttvisitIntrinsicCall/tt handles +ttIntrinsic::ctpop_*/tt. /dt /div @@ -182,14 +185,15 @@ targets supported by the SelectionDAG framework will natively support the new node. In this case, you must also add code in your node's case statement in ttLegalizeOp/tt to Expand your node into simpler, legal -operations. The case for ISD::UREM for expanding a remainder into a -multiply and a subtract is a good example./li +operations. The case for ttISD::UREM/tt for expanding a remainder into +a divide, multiply, and a subtract is a good example./li littlib/CodeGen/SelectionDAG/LegalizeDAG.cpp/tt: If targets may support the new node being added only at certain sizes, you will also need to add code to your node's case statement in ttLegalizeOp/tt to Promote your node's operands to a larger size, and perform the correct operation. You will also need to add code to -ttPromoteOp/tt to do this as well. For a good example, see ISD::BSWAP, +ttPromoteOp/tt to do this as well. For a good example, see +ttISD::BSWAP/tt, which promotes its operand to a wider size, performs the byteswap, and then shifts the correct bytes right to emulate the narrower byteswap in the wider type./li @@ -401,7 +405,7 @@ a href=http://llvm.cs.uiuc.edu;The LLVM Compiler Infrastructure/a br - Last modified: $Date: 2006/01/16 07:54:23 $ + Last modified: $Date: 2006/01/16 16:31:40 $ /address /body ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/Alpha/not.ll rpcc.ll
Changes in directory llvm/test/Regression/CodeGen/Alpha: not.ll updated: 1.1 - 1.2 rpcc.ll updated: 1.1 - 1.2 --- Log message: Fix these testcases :( Apparently Andrew hasn't implemented ReadCycleCounter in the new isel and renamed ornot to eqv --- Diffs of the changes: (+2 -1) not.ll |2 +- rpcc.ll |1 + 2 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/Alpha/not.ll diff -u llvm/test/Regression/CodeGen/Alpha/not.ll:1.1 llvm/test/Regression/CodeGen/Alpha/not.ll:1.2 --- llvm/test/Regression/CodeGen/Alpha/not.ll:1.1 Fri Apr 8 11:46:44 2005 +++ llvm/test/Regression/CodeGen/Alpha/not.ll Mon Jan 16 10:34:39 2006 @@ -1,5 +1,5 @@ ; Make sure this testcase codegens to the ornot instruction -; RUN: llvm-as %s | llc -march=alpha | grep 'ornot' +; RUN: llvm-as %s | llc -march=alpha | grep 'eqv' implementation ; Functions: Index: llvm/test/Regression/CodeGen/Alpha/rpcc.ll diff -u llvm/test/Regression/CodeGen/Alpha/rpcc.ll:1.1 llvm/test/Regression/CodeGen/Alpha/rpcc.ll:1.2 --- llvm/test/Regression/CodeGen/Alpha/rpcc.ll:1.1 Fri Nov 11 10:47:31 2005 +++ llvm/test/Regression/CodeGen/Alpha/rpcc.ll Mon Jan 16 10:34:39 2006 @@ -1,4 +1,5 @@ ; RUN: llvm-as %s | llc -march=alpha | grep rpcc +; XFAIL: * declare ulong %llvm.readcyclecounter() ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/README.txt
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.22 - 1.23
---
Log message:
transfer some notes from my email to somewhere useful.
---
Diffs of the changes: (+45 -0)
README.txt | 45 +
1 files changed, 45 insertions(+)
Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.22 llvm/lib/Target/X86/README.txt:1.23
--- llvm/lib/Target/X86/README.txt:1.22 Thu Jan 12 19:20:42 2006
+++ llvm/lib/Target/X86/README.txt Mon Jan 16 11:52:31 2006
@@ -54,6 +54,10 @@
fucomi jl X
jg X
+Ideas:
+http://gcc.gnu.org/ml/gcc-patches/2004-11/msg02410.html
+
+
//===-===//
Improvements to the multiply - shift/add algorithm:
@@ -121,3 +125,44 @@
setg %al
testb %al, %al # unnecessary
jne .BB7
+
+//===-===//
+
+Count leading zeros and count trailing zeros:
+
+int clz(int X) { return __builtin_clz(X); }
+int ctz(int X) { return __builtin_ctz(X); }
+
+$ gcc t.c -S -o - -O3 -fomit-frame-pointer -masm=intel
+clz:
+bsr %eax, DWORD PTR [%esp+4]
+xor %eax, 31
+ret
+ctz:
+bsf %eax, DWORD PTR [%esp+4]
+ret
+
+however, check that these are defined for 0 and 32. Our intrinsics are, GCC's
+aren't.
+
+//===-===//
+
+Use push/pop instructions in prolog/epilog sequences instead of stores off
+ESP (certain code size win, perf win on some [which?] processors).
+
+//===-===//
+
+Only use inc/neg/not instructions on processors where they are faster than
+add/sub/xor. They are slower on the P4 due to only updating some processor
+flags.
+
+//===-===//
+
+Open code rint,floor,ceil,trunc:
+http://gcc.gnu.org/ml/gcc-patches/2004-08/msg02006.html
+http://gcc.gnu.org/ml/gcc-patches/2004-08/msg02011.html
+
+//===-===//
+
+Combine: a = sin(x), b = cos(x) into a,b = sincos(x).
+
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt
Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.44 - 1.45 --- Log message: add notes from my *other* email acct. --- Diffs of the changes: (+88 -0) README.txt | 88 + 1 files changed, 88 insertions(+) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.44 llvm/lib/Target/PowerPC/README.txt:1.45 --- llvm/lib/Target/PowerPC/README.txt:1.44 Mon Jan 16 11:53:00 2006 +++ llvm/lib/Target/PowerPC/README.txt Mon Jan 16 11:58:54 2006 @@ -251,3 +251,91 @@ instructions). SETCC nodes should be custom lowered in this case, not expanded by the isel. +===-=== + +Darwin Stub LICM optimization: + +Loops like this: + + for (...) bar(); + +Have to go through an indirect stub if bar is external or linkonce. It would +be better to compile it as: + + fp = bar; + for (...) fp(); + +which only computes the address of bar once (instead of each time through the +stub). This is Darwin specific and would have to be done in the code generator. +Probably not a win on x86. + +===-=== + +PowerPC i1/setcc stuff (depends on subreg stuff): + +Check out the PPC code we get for 'compare' in this testcase: +http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19672 + +oof. on top of not doing the logical crnand instead of (mfcr, mfcr, +invert, invert, or), we then have to compare it against zero instead of +using the value already in a CR! + +that should be something like +cmpw cr7, r8, r5 +cmpw cr0, r7, r3 +crnand cr0, cr0, cr7 +bne cr0, LBB_compare_4 + +instead of +cmpw cr7, r8, r5 +cmpw cr0, r7, r3 +mfcr r7, 1 +mcrf cr7, cr0 +mfcr r8, 1 +rlwinm r7, r7, 30, 31, 31 +rlwinm r8, r8, 30, 31, 31 +xori r7, r7, 1 +xori r8, r8, 1 +addi r2, r2, 1 +or r7, r8, r7 +cmpwi cr0, r7, 0 +bne cr0, LBB_compare_4 ; loopexit + +===-=== + +Simple IPO for argument passing, change: + void foo(int X, double Y, int Z) - void foo(int X, int Z, double Y) + +the Darwin ABI specifies that any integer arguments in the first 32 bytes worth +of arguments get assigned to r3 through r10. That is, if you have a function +foo(int, double, int) you get r3, f1, r6, since the 64 bit double ate up the +argument bytes for r4 and r5. The trick then would be to shuffle the argument +order for functions we can internalize so that the maximum number of +integers/pointers get passed in regs before you see any of the fp arguments. + +Instead of implementing this, it would actually probably be easier to just +implement a PPC fastcc, where we could do whatever we wanted to the CC, +including having this work sanely. + +===-=== + +Fix Darwin FP-In-Integer Registers ABI + +Darwin passes doubles in structures in integer registers, which is very very +bad. Add something like a BIT_CONVERT to LLVM, then do an i-p transformation +that percolates these things out of functions. + +Check out how horrible this is: +http://gcc.gnu.org/ml/gcc/2005-10/msg01036.html + +This is an extension of interprocedural CC unmunging that can't be done with +just fastcc. + +===-=== + +Code Gen IPO optimization: + +Squish small scalar globals together into a single global struct, allowing the +address of the struct to be CSE'd, avoiding PIC accesses (also reduces the size +of the GOT on targets with one). + ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.414 - 1.415 --- Log message: fix a crash due to missing parens --- Diffs of the changes: (+1 -1) InstructionCombining.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.414 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.415 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.414 Fri Jan 13 16:48:06 2006 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Mon Jan 16 13:47:21 2006 @@ -748,7 +748,7 @@ // This is a sign extend if the top bits are known zero. Constant *Mask = ConstantInt::getAllOnesValue(XorLHS-getType()); Mask = ConstantExpr::getShl(Mask, - ConstantInt::get(Type::UByteTy, 64-TySizeBits-Size)); + ConstantInt::get(Type::UByteTy, 64-(TySizeBits-Size))); if (!MaskedValueIsZero(XorLHS, castConstantInt(Mask))) Size = 0; // Not a sign ext, but can't be any others either. goto FoundSExt; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp AlphaISelLowering.h
Changes in directory llvm/lib/Target/Alpha:
AlphaISelLowering.cpp updated: 1.21 - 1.22
AlphaISelLowering.h updated: 1.8 - 1.9
---
Log message:
Friendly names
---
Diffs of the changes: (+19 -1)
AlphaISelLowering.cpp | 15 +++
AlphaISelLowering.h |5 -
2 files changed, 19 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.21
llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.22
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.21Fri Jan 13 21:14:10 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Mon Jan 16 13:53:25 2006
@@ -128,6 +128,21 @@
useITOF = TM.getSubtargetAlphaSubtarget().hasF2I();
}
+const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
+ switch (Opcode) {
+ default: return 0;
+ case AlphaISD::ITOFT_: return Alpha::ITOFT_;
+ case AlphaISD::FTOIT_: return Alpha::FTOIT_;
+ case AlphaISD::CVTQT_: return Alpha::CVTQT_;
+ case AlphaISD::CVTQS_: return Alpha::CVTQS_;
+ case AlphaISD::CVTTQ_: return Alpha::CVTTQ_;
+ case AlphaISD::GPRelHi: return Alpha::GPRelHi;
+ case AlphaISD::GPRelLo: return Alpha::GPRelLo;
+ case AlphaISD::RelLit: return Alpha::RelLit;
+ case AlphaISD::GlobalBaseReg: return Alpha::GlobalBaseReg;
+ case AlphaISD::DivCall: return Alpha::DivCall;
+ }
+}
//http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21
Index: llvm/lib/Target/Alpha/AlphaISelLowering.h
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.h:1.8
llvm/lib/Target/Alpha/AlphaISelLowering.h:1.9
--- llvm/lib/Target/Alpha/AlphaISelLowering.h:1.8 Sat Dec 24 19:34:27 2005
+++ llvm/lib/Target/Alpha/AlphaISelLowering.h Mon Jan 16 13:53:25 2006
@@ -56,7 +56,10 @@
/// LowerOperation - Provide custom lowering hooks for some operations.
///
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG DAG);
-
+
+//Friendly names for dumps
+const char *getTargetNodeName(unsigned Opcode) const;
+
/// LowerArguments - This hook must be implemented to indicate how we
should
/// lower the arguments for the specified function, into the specified DAG.
virtual std::vectorSDOperand
___
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[llvm-commits] CVS: llvm/lib/VMCore/AutoUpgrade.cpp
Changes in directory llvm/lib/VMCore:
AutoUpgrade.cpp added (r1.1)
---
Log message:
For PR411: http://llvm.cs.uiuc.edu/PR411 :
This file makes the helper functions for auto-upgrade of llvm assembly and
bytecode more accessible. This is part of de-overloading of intrinsic
functions to support the flat symbol table (no type planes).
---
Diffs of the changes: (+105 -0)
AutoUpgrade.cpp | 105
1 files changed, 105 insertions(+)
Index: llvm/lib/VMCore/AutoUpgrade.cpp
diff -c /dev/null llvm/lib/VMCore/AutoUpgrade.cpp:1.1
*** /dev/null Mon Jan 16 15:06:11 2006
--- llvm/lib/VMCore/AutoUpgrade.cpp Mon Jan 16 15:06:01 2006
***
*** 0
--- 1,105
+ //===-- AutoUpgrade.cpp - Implement auto-upgrade helper functions
-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Reid Spencer and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+
//===--===//
+ //
+ // This file implements the auto-upgrade helper functions
+ //
+
//===--===//
+
+ #include llvm/Assembly/AutoUpgrade.h
+ #include llvm/Function.h
+ #include llvm/Type.h
+ #include iostream
+
+ using namespace llvm;
+
+ // UpgradeIntrinsicFunction - Convert overloaded intrinsic function names to
+ // their non-overloaded variants by appending the appropriate suffix based on
+ // the argument types.
+ bool llvm::UpgradeIntrinsicFunction(Function* F) {
+
+ // Get the Function's name.
+ const std::string Name = F-getName();
+
+ // Quickly eliminate it, if it's not a candidate.
+ if (Name.length() = 5 || Name[0] != 'l' || Name[1] != 'l' || Name[2] !=
+ 'v' || Name[3] != 'm' || Name[4] != '.')
+ return false;
+
+ // See if its one of the name's we're interested in.
+ switch (Name[5]) {
+ case 'b':
+ if (Name == llvm.bswap) {
+ const Type* Ty = F-getReturnType();
+ std::string new_name = Name;
+ if (Ty == Type::UShortTy || Ty == Type::ShortTy)
+ new_name += .i16;
+ else if (Ty == Type::UIntTy || Ty == Type::IntTy)
+ new_name += .i32;
+ else if (Ty == Type::ULongTy || Ty == Type::LongTy)
+ new_name += .i64;
+ std::cerr WARNING: change Name to
+new_name \n;
+ F-setName(new_name);
+ return true;
+ }
+ break;
+ case 'c':
+ if (Name == llvm.ctpop || Name == llvm.ctlz ||
+ Name == llvm.cttz) {
+ const Type* Ty = F-getReturnType();
+ std::string new_name = Name;
+ if (Ty == Type::UByteTy || Ty == Type::SByteTy)
+ new_name += .i8;
+ else if (Ty == Type::UShortTy || Ty == Type::ShortTy)
+ new_name += .i16;
+ else if (Ty == Type::UIntTy || Ty == Type::IntTy)
+ new_name += .i32;
+ else if (Ty == Type::ULongTy || Ty == Type::LongTy)
+ new_name += .i64;
+ std::cerr WARNING: change Name to
+new_name \n;
+ F-setName(new_name);
+ return true;
+ }
+ break;
+ case 'i':
+ if (Name == llvm.isunordered) {
+ Function::const_arg_iterator ArgIt = F-arg_begin();
+ const Type* Ty = ArgIt-getType();
+ std::string new_name = Name;
+ if (Ty == Type::FloatTy)
+ new_name += .f32;
+ else if (Ty == Type::DoubleTy)
+ new_name += .f64;
+ std::cerr WARNING: change Name to
+new_name \n;
+ F-setName(new_name);
+ return true;
+ }
+ break;
+ case 's':
+ if (Name == llvm.sqrt) {
+ const Type* Ty = F-getReturnType();
+ std::string new_name = Name;
+ if (Ty == Type::FloatTy)
+ new_name += .f32;
+ else if (Ty == Type::DoubleTy) {
+ new_name += .f64;
+ }
+ std::cerr WARNING: change Name to
+new_name \n;
+ F-setName(new_name);
+ return true;
+ }
+ break;
+ default:
+ break;
+ }
+ return false;
+ }
___
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[llvm-commits] CVS: llvm/lib/Transforms/Utils/Local.cpp
Changes in directory llvm/lib/Transforms/Utils: Local.cpp updated: 1.49 - 1.50 --- Log message: For PR411: http://llvm.cs.uiuc.edu/PR411 : This patch is an incremental step towards supporting a flat symbol table. It de-overloads the intrinsic functions by providing type-specific intrinsics and arranging for automatically upgrading from the old overloaded name to the new non-overloaded name. Specifically: llvm.isunordered - llvm.isunordered.f32, llvm.isunordered.f64 llvm.sqrt - llvm.sqrt.f32, llvm.sqrt.f64 llvm.ctpop - llvm.ctpop.i8, llvm.ctpop.i16, llvm.ctpop.i32, llvm.ctpop.i64 llvm.ctlz - llvm.ctlz.i8, llvm.ctlz.i16, llvm.ctlz.i32, llvm.ctlz.i64 llvm.cttz - llvm.cttz.i8, llvm.cttz.i16, llvm.cttz.i32, llvm.cttz.i64 New code should not use the overloaded intrinsic names. Warnings will be emitted if they are used. --- Diffs of the changes: (+16 -5) Local.cpp | 21 - 1 files changed, 16 insertions(+), 5 deletions(-) Index: llvm/lib/Transforms/Utils/Local.cpp diff -u llvm/lib/Transforms/Utils/Local.cpp:1.49 llvm/lib/Transforms/Utils/Local.cpp:1.50 --- llvm/lib/Transforms/Utils/Local.cpp:1.49Fri Jan 13 19:25:24 2006 +++ llvm/lib/Transforms/Utils/Local.cpp Mon Jan 16 15:12:35 2006 @@ -297,14 +297,25 @@ case Intrinsic::returnaddress: case Intrinsic::frameaddress: case Intrinsic::stacksave: - case Intrinsic::isunordered: + case Intrinsic::isunordered_f32: + case Intrinsic::isunordered_f64: case Intrinsic::bswap_i16: case Intrinsic::bswap_i32: case Intrinsic::bswap_i64: - case Intrinsic::ctpop: - case Intrinsic::ctlz: - case Intrinsic::cttz: - case Intrinsic::sqrt: + case Intrinsic::ctpop_i8: + case Intrinsic::ctpop_i16: + case Intrinsic::ctpop_i32: + case Intrinsic::ctpop_i64: + case Intrinsic::ctlz_i8: + case Intrinsic::ctlz_i16: + case Intrinsic::ctlz_i32: + case Intrinsic::ctlz_i64: + case Intrinsic::cttz_i8: + case Intrinsic::cttz_i16: + case Intrinsic::cttz_i32: + case Intrinsic::cttz_i64: + case Intrinsic::sqrt_f32: + case Intrinsic::sqrt_f64: return true; // These intrinsics have no side effects. } return false; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Analysis/ConstantFolding.cpp
Changes in directory llvm/lib/Analysis:
ConstantFolding.cpp updated: 1.2 - 1.3
---
Log message:
For PR411: http://llvm.cs.uiuc.edu/PR411 :
This patch is an incremental step towards supporting a flat symbol table.
It de-overloads the intrinsic functions by providing type-specific intrinsics
and arranging for automatically upgrading from the old overloaded name to
the new non-overloaded name. Specifically:
llvm.isunordered - llvm.isunordered.f32, llvm.isunordered.f64
llvm.sqrt - llvm.sqrt.f32, llvm.sqrt.f64
llvm.ctpop - llvm.ctpop.i8, llvm.ctpop.i16, llvm.ctpop.i32, llvm.ctpop.i64
llvm.ctlz - llvm.ctlz.i8, llvm.ctlz.i16, llvm.ctlz.i32, llvm.ctlz.i64
llvm.cttz - llvm.cttz.i8, llvm.cttz.i16, llvm.cttz.i32, llvm.cttz.i64
New code should not use the overloaded intrinsic names. Warnings will be
emitted if they are used.
---
Diffs of the changes: (+18 -7)
ConstantFolding.cpp | 25 ++---
1 files changed, 18 insertions(+), 7 deletions(-)
Index: llvm/lib/Analysis/ConstantFolding.cpp
diff -u llvm/lib/Analysis/ConstantFolding.cpp:1.2
llvm/lib/Analysis/ConstantFolding.cpp:1.3
--- llvm/lib/Analysis/ConstantFolding.cpp:1.2 Fri Jan 13 19:25:24 2006
+++ llvm/lib/Analysis/ConstantFolding.cpp Mon Jan 16 15:12:35 2006
@@ -35,15 +35,26 @@
const std::string Name = F-getName();
switch (F-getIntrinsicID()) {
- case Intrinsic::isunordered:
- case Intrinsic::sqrt:
+ case Intrinsic::isunordered_f32:
+ case Intrinsic::isunordered_f64:
+ case Intrinsic::sqrt_f32:
+ case Intrinsic::sqrt_f64:
case Intrinsic::bswap_i16:
case Intrinsic::bswap_i32:
case Intrinsic::bswap_i64:
// FIXME: these should be constant folded as well
- //case Intrinsic::ctpop:
- //case Intrinsic::ctlz:
- //case Intrinsic::cttz:
+ //case Intrinsic::ctpop_i8:
+ //case Intrinsic::ctpop_i16:
+ //case Intrinsic::ctpop_i32:
+ //case Intrinsic::ctpop_i64:
+ //case Intrinsic::ctlz_i8:
+ //case Intrinsic::ctlz_i16:
+ //case Intrinsic::ctlz_i32:
+ //case Intrinsic::ctlz_i64:
+ //case Intrinsic::cttz_i8:
+ //case Intrinsic::cttz_i16:
+ //case Intrinsic::cttz_i32:
+ //case Intrinsic::cttz_i64:
return true;
default: break;
}
@@ -125,7 +136,7 @@
return ConstantFP::get(Ty, log(V));
else if (Name == log10 V 0)
return ConstantFoldFP(log10, V, Ty);
- else if (Name == llvm.sqrt) {
+ else if (Name == llvm.sqrt.f32 || Name == llvm.sqrt.f64) {
if (V = -0.0)
return ConstantFP::get(Ty, sqrt(V));
else // Undefined
@@ -164,7 +175,7 @@
if (ConstantFP *Op2 = dyn_castConstantFP(Operands[1])) {
double Op2V = Op2-getValue();
-if (Name == llvm.isunordered)
+if (Name == llvm.isunordered.f32 || Name == llvm.isunordered.f64)
return ConstantBool::get(IsNAN(Op1V) || IsNAN(Op2V));
else
if (Name == pow) {
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[llvm-commits] CVS: llvm/lib/Bytecode/Reader/Reader.cpp
Changes in directory llvm/lib/Bytecode/Reader: Reader.cpp updated: 1.176 - 1.177 --- Log message: For PR411: http://llvm.cs.uiuc.edu/PR411 : This patch is an incremental step towards supporting a flat symbol table. It de-overloads the intrinsic functions by providing type-specific intrinsics and arranging for automatically upgrading from the old overloaded name to the new non-overloaded name. Specifically: llvm.isunordered - llvm.isunordered.f32, llvm.isunordered.f64 llvm.sqrt - llvm.sqrt.f32, llvm.sqrt.f64 llvm.ctpop - llvm.ctpop.i8, llvm.ctpop.i16, llvm.ctpop.i32, llvm.ctpop.i64 llvm.ctlz - llvm.ctlz.i8, llvm.ctlz.i16, llvm.ctlz.i32, llvm.ctlz.i64 llvm.cttz - llvm.cttz.i8, llvm.cttz.i16, llvm.cttz.i32, llvm.cttz.i64 New code should not use the overloaded intrinsic names. Warnings will be emitted if they are used. --- Diffs of the changes: (+2 -0) Reader.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Bytecode/Reader/Reader.cpp diff -u llvm/lib/Bytecode/Reader/Reader.cpp:1.176 llvm/lib/Bytecode/Reader/Reader.cpp:1.177 --- llvm/lib/Bytecode/Reader/Reader.cpp:1.176 Tue Jan 10 13:04:39 2006 +++ llvm/lib/Bytecode/Reader/Reader.cpp Mon Jan 16 15:12:35 2006 @@ -17,6 +17,7 @@ //===--===// #include Reader.h +#include llvm/Assembly/AutoUpgrade.h #include llvm/Bytecode/BytecodeHandler.h #include llvm/BasicBlock.h #include llvm/CallingConv.h @@ -2002,6 +2003,7 @@ // Insert the place holder. Function *Func = new Function(FTy, GlobalValue::ExternalLinkage, , TheModule); +UpgradeIntrinsicFunction(Func); insertValue(Func, (FnSignature (~0U 1)) 5, ModuleValues); // Flags are not used yet. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.125 - 1.126 --- Log message: For PR411: http://llvm.cs.uiuc.edu/PR411 : This patch is an incremental step towards supporting a flat symbol table. It de-overloads the intrinsic functions by providing type-specific intrinsics and arranging for automatically upgrading from the old overloaded name to the new non-overloaded name. Specifically: llvm.isunordered - llvm.isunordered.f32, llvm.isunordered.f64 llvm.sqrt - llvm.sqrt.f32, llvm.sqrt.f64 llvm.ctpop - llvm.ctpop.i8, llvm.ctpop.i16, llvm.ctpop.i32, llvm.ctpop.i64 llvm.ctlz - llvm.ctlz.i8, llvm.ctlz.i16, llvm.ctlz.i32, llvm.ctlz.i64 llvm.cttz - llvm.cttz.i8, llvm.cttz.i16, llvm.cttz.i32, llvm.cttz.i64 New code should not use the overloaded intrinsic names. Warnings will be emitted if they are used. --- Diffs of the changes: (+16 -5) SelectionDAGISel.cpp | 21 - 1 files changed, 16 insertions(+), 5 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.125 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.126 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.125Fri Jan 13 21:18:27 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Jan 16 15:12:35 2006 @@ -963,12 +963,14 @@ setValue(I, DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType(; return 0; - case Intrinsic::isunordered: + case Intrinsic::isunordered_f32: + case Intrinsic::isunordered_f64: setValue(I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)), getValue(I.getOperand(2)), ISD::SETUO)); return 0; - case Intrinsic::sqrt: + case Intrinsic::sqrt_f32: + case Intrinsic::sqrt_f64: setValue(I, DAG.getNode(ISD::FSQRT, getValue(I.getOperand(1)).getValueType(), getValue(I.getOperand(1; @@ -996,17 +998,26 @@ getValue(I.getOperand(1)).getValueType(), getValue(I.getOperand(1; return 0; - case Intrinsic::cttz: + case Intrinsic::cttz_i8: + case Intrinsic::cttz_i16: + case Intrinsic::cttz_i32: + case Intrinsic::cttz_i64: setValue(I, DAG.getNode(ISD::CTTZ, getValue(I.getOperand(1)).getValueType(), getValue(I.getOperand(1; return 0; - case Intrinsic::ctlz: + case Intrinsic::ctlz_i8: + case Intrinsic::ctlz_i16: + case Intrinsic::ctlz_i32: + case Intrinsic::ctlz_i64: setValue(I, DAG.getNode(ISD::CTLZ, getValue(I.getOperand(1)).getValueType(), getValue(I.getOperand(1; return 0; - case Intrinsic::ctpop: + case Intrinsic::ctpop_i8: + case Intrinsic::ctpop_i16: + case Intrinsic::ctpop_i32: + case Intrinsic::ctpop_i64: setValue(I, DAG.getNode(ISD::CTPOP, getValue(I.getOperand(1)).getValueType(), getValue(I.getOperand(1; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Intrinsics.h
Changes in directory llvm/include/llvm: Intrinsics.h updated: 1.35 - 1.36 --- Log message: For PR411: http://llvm.cs.uiuc.edu/PR411 : This patch is an incremental step towards supporting a flat symbol table. It de-overloads the intrinsic functions by providing type-specific intrinsics and arranging for automatically upgrading from the old overloaded name to the new non-overloaded name. Specifically: llvm.isunordered - llvm.isunordered.f32, llvm.isunordered.f64 llvm.sqrt - llvm.sqrt.f32, llvm.sqrt.f64 llvm.ctpop - llvm.ctpop.i8, llvm.ctpop.i16, llvm.ctpop.i32, llvm.ctpop.i64 llvm.ctlz - llvm.ctlz.i8, llvm.ctlz.i16, llvm.ctlz.i32, llvm.ctlz.i64 llvm.cttz - llvm.cttz.i8, llvm.cttz.i16, llvm.cttz.i32, llvm.cttz.i64 New code should not use the overloaded intrinsic names. Warnings will be emitted if they are used. --- Diffs of the changes: (+16 -5) Intrinsics.h | 21 - 1 files changed, 16 insertions(+), 5 deletions(-) Index: llvm/include/llvm/Intrinsics.h diff -u llvm/include/llvm/Intrinsics.h:1.35 llvm/include/llvm/Intrinsics.h:1.36 --- llvm/include/llvm/Intrinsics.h:1.35 Fri Jan 13 19:25:24 2006 +++ llvm/include/llvm/Intrinsics.h Mon Jan 16 15:12:35 2006 @@ -62,16 +62,27 @@ memcpy, // Copy non-overlapping memory blocks memmove,// Copy potentially overlapping memory blocks memset, // Fill memory with a byte value -isunordered,// Return true if either argument is a NaN -sqrt, // Square root +isunordered_f32,// Return true if either float argument is a NaN +isunordered_f64,// Return true if either double argument is a NaN +sqrt_f32, // Square root of float +sqrt_f64, // Square root of double // Bit manipulation instrinsics. bswap_i16, // Byteswap 16 bits bswap_i32, // Byteswap 32 bits bswap_i64, // Byteswap 64 bits -ctpop, // Count population -ctlz, // Count leading zeros -cttz, // Count trailing zeros +ctpop_i8, // Count population of sbyte +ctpop_i16, // Count population of short +ctpop_i32, // Count population of int +ctpop_i64, // Count population of long +ctlz_i8,// Count leading zeros of sbyte +ctlz_i16, // Count leading zeros of short +ctlz_i32, // Count leading zeros of int +ctlz_i64, // Count leading zeros of long +cttz_i8,// Count trailing zeros of sbyte +cttz_i16, // Count trailing zeros of short +cttz_i32, // Count trailing zeros of int +cttz_i64, // Count trailing zeros of long // Input/Output intrinsics. readport, ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/docs/LangRef.html
Changes in directory llvm/docs: LangRef.html updated: 1.127 - 1.128 --- Log message: For PR411: http://llvm.cs.uiuc.edu/PR411 : This patch is an incremental step towards supporting a flat symbol table. It de-overloads the intrinsic functions by providing type-specific intrinsics and arranging for automatically upgrading from the old overloaded name to the new non-overloaded name. Specifically: llvm.isunordered - llvm.isunordered.f32, llvm.isunordered.f64 llvm.sqrt - llvm.sqrt.f32, llvm.sqrt.f64 llvm.ctpop - llvm.ctpop.i8, llvm.ctpop.i16, llvm.ctpop.i32, llvm.ctpop.i64 llvm.ctlz - llvm.ctlz.i8, llvm.ctlz.i16, llvm.ctlz.i32, llvm.ctlz.i64 llvm.cttz - llvm.cttz.i8, llvm.cttz.i16, llvm.cttz.i32, llvm.cttz.i64 New code should not use the overloaded intrinsic names. Warnings will be emitted if they are used. --- Diffs of the changes: (+28 -15) LangRef.html | 43 --- 1 files changed, 28 insertions(+), 15 deletions(-) Index: llvm/docs/LangRef.html diff -u llvm/docs/LangRef.html:1.127 llvm/docs/LangRef.html:1.128 --- llvm/docs/LangRef.html:1.127Sun Jan 15 14:48:27 2006 +++ llvm/docs/LangRef.html Mon Jan 16 15:12:35 2006 @@ -3394,20 +3394,21 @@ !-- ___ -- div class=doc_subsubsection - a name=i_isunordered'ttllvm.isunordered/tt' Intrinsic/a + a name=i_isunordered'ttllvm.isunordered.*/tt' Intrinsic/a /div div class=doc_text h5Syntax:/h5 pre - declare bool %llvm.isunordered(lt;float or doublegt; Val1, lt;float or doublegt; Val2) + declare bool %llvm.isunordered.f32(float Val1, float Val2) + declare bool %llvm.isunordered.f64(double Val1, double Val2) /pre h5Overview:/h5 p -The 'ttllvm.isunordered/tt' intrinsic returns true if either or both of the +The 'ttllvm.isunordered/tt' intrinsics return true if either or both of the specified floating point values is a NAN. /p @@ -3435,13 +3436,14 @@ h5Syntax:/h5 pre - declare lt;float or doublegt; %llvm.sqrt(lt;float or doublegt; Val) + declare double %llvm.sqrt.f32(float Val) + declare double %llvm.sqrt.f64(double Val) /pre h5Overview:/h5 p -The 'ttllvm.sqrt/tt' intrinsic returns the sqrt of the specified operand, +The 'ttllvm.sqrt/tt' intrinsics return the sqrt of the specified operand, returning the same value as the libm 'ttsqrt/tt' function would. Unlike ttsqrt/tt in libm, however, ttllvm.sqrt/tt has undefined behavior for negative numbers (which allows for better optimization). @@ -3483,6 +3485,7 @@ h5Syntax:/h5 pre + declare ushort %llvm.bswap.i8( ubyte lt;idgt; ) declare ushort %llvm.bswap.i16( ushort lt;idgt; ) declare uint %llvm.bswap.i32( uint lt;idgt; ) declare ulong %llvm.bswap.i64( ulong lt;idgt; ) @@ -3511,20 +3514,24 @@ !-- ___ -- div class=doc_subsubsection - a name=int_ctpop'ttllvm.ctpop/tt' Intrinsic/a + a name=int_ctpop'ttllvm.ctpop.*/tt' Intrinsic/a /div div class=doc_text h5Syntax:/h5 pre - declare int %llvm.ctpop(int lt;srcgt;) + declare sbyte %llvm.ctpop.i8(sbyte lt;srcgt;) + declare short %llvm.ctpop.i16(short lt;srcgt;) + declare int %llvm.ctpop.i32(int lt;srcgt;) + declare long %llvm.ctpop.i64(long lt;srcgt;) /pre h5Overview:/h5 p -The 'ttllvm.ctpop/tt' intrinsic counts the number of ones in a variable. +The 'ttllvm.ctpop/tt' family of intrinsics counts the number of ones in a +variable. /p h5Arguments:/h5 @@ -3550,15 +3557,17 @@ h5Syntax:/h5 pre - declare int %llvm.ctlz(int lt;srcgt;) - + declare sbyte %llvm.ctlz.i8(sbyte lt;srcgt;) + declare short %llvm.ctlz.i16(short lt;srcgt;) + declare int %llvm.ctlz.i32(int lt;srcgt;) + declare long %llvm.ctlz.i64(long lt;srcgt;) /pre h5Overview:/h5 p -The 'ttllvm.ctlz/tt' intrinsic counts the number of leading zeros in a -variable. +The 'ttllvm.ctlz/tt' family of intrinsic functions counts the number of +leading zeros in a variable. /p h5Arguments:/h5 @@ -3588,13 +3597,17 @@ h5Syntax:/h5 pre - declare int %llvm.cttz(int lt;srcgt;) + declare sbyte %llvm.cttz.i8(sbyte lt;srcgt;) + declare short %llvm.cttz.i16(short lt;srcgt;) + declare int %llvm.cttz.i32(int lt;srcgt;) + declare long %llvm.cttz.i64(long lt;srcgt;) /pre h5Overview:/h5 p -The 'ttllvm.cttz/tt' intrinsic counts the number of trailing zeros. +The 'ttllvm.cttz/tt' family of intrinsic functions counts the number of +trailing zeros. /p h5Arguments:/h5 @@ -3638,7 +3651,7 @@ a href=mailto:[EMAIL PROTECTED]Chris Lattner/abr a href=http://llvm.cs.uiuc.edu;The LLVM Compiler Infrastructure/abr - Last modified: $Date: 2006/01/15 20:48:27 $ + Last modified: $Date: 2006/01/16 21:12:35 $ /address /body /html ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp AlphaISelLowering.cpp AlphaInstrFormats.td
Changes in directory llvm/lib/Target/Alpha:
AlphaISelDAGToDAG.cpp updated: 1.27 - 1.28
AlphaISelLowering.cpp updated: 1.22 - 1.23
AlphaInstrFormats.td updated: 1.22 - 1.23
---
Log message:
stack and rpcc
---
Diffs of the changes: (+11 -35)
AlphaISelDAGToDAG.cpp | 36 +---
AlphaISelLowering.cpp |5 -
AlphaInstrFormats.td |5 ++---
3 files changed, 11 insertions(+), 35 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.27
llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.28
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.27Fri Jan 6 13:41:51 2006
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Mon Jan 16 15:22:38 2006
@@ -163,37 +163,6 @@
case ISD::TAILCALL:
case ISD::CALL: return SelectCALL(Op);
- case ISD::DYNAMIC_STACKALLOC: {
-if (!isaConstantSDNode(N-getOperand(2)) ||
-castConstantSDNode(N-getOperand(2))-getValue() != 0) {
- std::cerr Cannot allocate stack object with greater alignment than
- the stack alignment yet!;
- abort();
-}
-
-SDOperand Chain = Select(N-getOperand(0));
-SDOperand Amt = Select(N-getOperand(1));
-SDOperand Reg = CurDAG-getRegister(Alpha::R30, MVT::i64);
-SDOperand Val = CurDAG-getCopyFromReg(Chain, Alpha::R30, MVT::i64);
-Chain = Val.getValue(1);
-
-// Subtract the amount (guaranteed to be a multiple of the stack alignment)
-// from the stack pointer, giving us the result pointer.
-SDOperand Result = CurDAG-getTargetNode(Alpha::SUBQ, MVT::i64, Val, Amt);
-
-// Copy this result back into R30.
-Chain = CurDAG-getNode(ISD::CopyToReg, MVT::Other, Chain, Reg, Result);
-
-// Copy this result back out of R30 to make sure we're not using the stack
-// space without decrementing the stack pointer.
-Result = CurDAG-getCopyFromReg(Chain, Alpha::R30, MVT::i64);
-
-// Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
-CodeGenMap[Op.getValue(0)] = Result;
-CodeGenMap[Op.getValue(1)] = Result.getValue(1);
-return SDOperand(Result.Val, Op.ResNo);
- }
-
case ISD::FrameIndex: {
int FI = castFrameIndexSDNode(N)-getIndex();
return CurDAG-SelectNodeTo(N, Alpha::LDA, MVT::i64,
@@ -218,6 +187,11 @@
return CurDAG-SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
}
+ case ISD::READCYCLECOUNTER: {
+SDOperand Chain = Select(N-getOperand(0)); //Select chain
+return CurDAG-SelectNodeTo(N, Alpha::RPCC, MVT::i64, Chain);
+ }
+
case ISD::RET: {
SDOperand Chain = Select(N-getOperand(0)); // Token chain.
SDOperand InFlag;
Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.22
llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.23
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.22Mon Jan 16 13:53:25 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Mon Jan 16 15:22:38 2006
@@ -112,7 +112,8 @@
// Not implemented yet.
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
-
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
+
// We want to legalize GlobalAddress and ConstantPool and
// ExternalSymbols nodes into the appropriate instructions to
// materialize the address.
@@ -120,6 +121,8 @@
setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
+ setStackPointerRegisterToSaveRestore(Alpha::R30);
+
addLegalFPImmediate(+0.0); //F31
addLegalFPImmediate(-0.0); //-F31
Index: llvm/lib/Target/Alpha/AlphaInstrFormats.td
diff -u llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.22
llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.23
--- llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.22 Sun Jan 1 16:16:14 2006
+++ llvm/lib/Target/Alpha/AlphaInstrFormats.td Mon Jan 16 15:22:38 2006
@@ -65,12 +65,11 @@
let Inst{15-0} = disp;
}
class MfcFormbits6 opcode, bits16 fc, string asmstr
-: InstAlphaopcode, (ops GPRC:$RA, GPRC:$RB), asmstr {
+: InstAlphaopcode, (ops GPRC:$RA), asmstr {
bits5 Ra;
- bits5 Rb;
let Inst{25-21} = Ra;
- let Inst{20-16} = Rb;
+ let Inst{20-16} = 0;
let Inst{15-0} = fc;
}
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/Alpha/rpcc.ll
Changes in directory llvm/test/Regression/CodeGen/Alpha: rpcc.ll updated: 1.2 - 1.3 --- Log message: this is fixed --- Diffs of the changes: (+0 -1) rpcc.ll |1 - 1 files changed, 1 deletion(-) Index: llvm/test/Regression/CodeGen/Alpha/rpcc.ll diff -u llvm/test/Regression/CodeGen/Alpha/rpcc.ll:1.2 llvm/test/Regression/CodeGen/Alpha/rpcc.ll:1.3 --- llvm/test/Regression/CodeGen/Alpha/rpcc.ll:1.2 Mon Jan 16 10:34:39 2006 +++ llvm/test/Regression/CodeGen/Alpha/rpcc.ll Mon Jan 16 15:22:42 2006 @@ -1,5 +1,4 @@ ; RUN: llvm-as %s | llc -march=alpha | grep rpcc -; XFAIL: * declare ulong %llvm.readcyclecounter() ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Assembly/AutoUpgrade.h
Changes in directory llvm/include/llvm/Assembly:
AutoUpgrade.h added (r1.1)
---
Log message:
For PR411: http://llvm.cs.uiuc.edu/PR411 :
This file makes the helper functions for auto-upgrade of llvm assembly and
bytecode more accessible. This is part of de-overloading of intrinsic
functions to support the flat symbol table (no type planes).
---
Diffs of the changes: (+33 -0)
AutoUpgrade.h | 33 +
1 files changed, 33 insertions(+)
Index: llvm/include/llvm/Assembly/AutoUpgrade.h
diff -c /dev/null llvm/include/llvm/Assembly/AutoUpgrade.h:1.1
*** /dev/null Mon Jan 16 15:06:11 2006
--- llvm/include/llvm/Assembly/AutoUpgrade.hMon Jan 16 15:06:01 2006
***
*** 0
--- 1,33
+ //===-- llvm/Assembly/AutoUpgrade.h - AutoUpgrade Helpers *- C++
-*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Reid Spencer is distributed under the
University
+ // of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+
//===--===//
+ //
+ // These functions are implemented by the lib/VMCore/AutoUpgrade.cpp.
+ //
+
//===--===//
+
+ #ifndef LLVM_ASSEMBLY_AUTOUPGRADE_H
+ #define LLVM_ASSEMBLY_AUTOUPGRADE_H
+
+ namespace llvm {
+ class Function;
+
+ /// This function inspects the Function \p F to see if it is an old
overloaded
+ /// intrinsic. If it is, the Function's name is changed to add a suffix that
+ /// indicates the kind of arguments or result that it accepts. In LLVM
release
+ /// 1.7, the overloading of intrinsic functions was replaced with separate
+ /// functions for each of the various argument sizes. This function
implements
+ /// the auto-upgrade feature from the old overloaded names to the new
+ /// non-overloaded names.
+ /// @param F The Function to potentially auto-upgrade.
+ /// @brief Remove overloaded intrinsic function names.
+ bool UpgradeIntrinsicFunction(Function* F);
+
+ } // End llvm namespace
+
+ #endif
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.32 - 1.33
X86ISelLowering.cpp updated: 1.42 - 1.43
X86InstrInfo.td updated: 1.206 - 1.207
---
Log message:
Fix FP_TO_INT**_IN_MEM lowering.
---
Diffs of the changes: (+132 -103)
X86ISelDAGToDAG.cpp | 58
X86ISelLowering.cpp | 150 +---
X86InstrInfo.td | 27 -
3 files changed, 132 insertions(+), 103 deletions(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.32
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.33
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.32Sun Jan 15 03:00:21 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Jan 16 15:21:29 2006
@@ -642,64 +642,6 @@
return CodeGenMap[N] = CurDAG-getTargetNode(Opc, VT, Result);
break;
}
-
-case X86ISD::FP_TO_INT16_IN_MEM:
-case X86ISD::FP_TO_INT32_IN_MEM:
-case X86ISD::FP_TO_INT64_IN_MEM: {
- assert(N.getOperand(1).getValueType() == MVT::f64);
-
- // Change the floating point control register to use round towards zero
- // mode when truncating to an integer value.
- MachineFunction MF = CurDAG-getMachineFunction();
- int CWFI = MF.getFrameInfo()-CreateStackObject(2, 2);
- SDOperand CWSlot = CurDAG-getFrameIndex(CWFI, MVT::i32);
- SDOperand Base, Scale, Index, Disp;
- (void)SelectAddr(CWSlot, Base, Scale, Index, Disp);
- SDOperand Chain = N.getOperand(0);
-
- // Save the control word.
- Chain = CurDAG-getTargetNode(X86::FNSTCW16m, MVT::Other,
-Base, Scale, Index, Disp, Chain);
-
- // Load the old value of the high byte of the control word.
- SDOperand OldCW =
-CurDAG-getTargetNode(X86::MOV16rm, MVT::i16, MVT::Other,
- Base, Scale, Index, Disp, Chain);
- Chain = OldCW.getValue(1);
-
- // Set the high part to be round to zero...
- Chain = CurDAG-getTargetNode(X86::MOV16mi, MVT::Other,
-Base, Scale, Index, Disp,
-CurDAG-getConstant(0xC7F, MVT::i16),
-Chain);
-
- // Reload the modified control word now...
- Chain = CurDAG-getTargetNode(X86::FLDCW16m, MVT::Other,
-Base, Scale, Index, Disp, Chain);
-
- // Restore the memory image of control word to original value
- Chain = CurDAG-getTargetNode(X86::MOV16mr, MVT::Other,
-Base, Scale, Index, Disp, OldCW, Chain);
-
- switch (Opcode) {
- default: assert(0 Unknown FP_TO_INT*_IN_MEM);
- case X86ISD::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
- case X86ISD::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
- case X86ISD::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
- }
-
- SDOperand N1 = Select(N.getOperand(1));
- SDOperand Base2, Scale2, Index2, Disp2;
- (void)SelectAddr(N.getOperand(2), Base2, Scale2, Index2, Disp2);
- Chain = CurDAG-getTargetNode(Opc, MVT::Other,
-Base2, Scale2, Index2, Disp2, N1, Chain);
-
- // Reload the modified control word now...
- CodeGenMap[N] =
-Chain = CurDAG-getTargetNode(X86::FLDCW16m, MVT::Other,
- Base, Scale, Index, Disp, Chain);
- return Chain;
-}
}
return SelectCode(N);
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.42
llvm/lib/Target/X86/X86ISelLowering.cpp:1.43
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.42Sun Jan 15 03:00:21 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Jan 16 15:21:29 2006
@@ -13,6 +13,7 @@
//===--===//
#include X86.h
+#include X86InstrBuilder.h
#include X86ISelLowering.h
#include X86TargetMachine.h
#include llvm/CallingConv.h
@@ -1261,54 +1262,117 @@
MachineBasicBlock *
X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *BB) {
- assert((MI-getOpcode() == X86::CMOV_FR32 ||
- MI-getOpcode() == X86::CMOV_FR64)
- Unexpected instr type to insert);
-
- // To insert a SELECT_CC instruction, we actually have to insert the
diamond
- // control-flow pattern. The incoming instruction knows the destination vreg
- // to set, the condition code register to branch on, the true/false values to
- // select between, and a branch opcode to use.
- const BasicBlock *LLVM_BB = BB-getBasicBlock();
- ilistMachineBasicBlock::iterator It = BB;
- ++It;
+ switch (MI-getOpcode()) {
+ default: assert(false Unexpected instr type to insert);
+ case X86::CMOV_FR32:
+ case X86::CMOV_FR64: {
+// To insert a SELECT_CC instruction, we actually have to insert the
diamond
+
[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaInstrInfo.td
Changes in directory llvm/lib/Target/Alpha: AlphaInstrInfo.td updated: 1.101 - 1.102 --- Log message: fix short immediate loads --- Diffs of the changes: (+1 -1) AlphaInstrInfo.td |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.101 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.102 --- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.101 Tue Jan 10 21:33:06 2006 +++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Mon Jan 16 15:41:39 2006 @@ -826,7 +826,7 @@ def : Pat(i64 immSExt16int:$imm), (ZAPNOTi (LDA (SExt16 immSExt16int:$imm), R31), 15); def : Pat(i64 immConst2PartInt:$imm), - (ZAPNOTi (LDA (LL16 (SExt16 immConst2PartInt:$imm)), + (ZAPNOTi (LDA (LL16 (SExt32 immConst2PartInt:$imm)), (LDAH (LH16 (SExt32 immConst2PartInt:$imm)), R31)), 15); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-gcc/gcc/llvm-expand.c
Changes in directory llvm-gcc/gcc:
llvm-expand.c updated: 1.124 - 1.125
---
Log message:
For PR411: http://llvm.cs.uiuc.edu/PR411 :
Cause llvm-gcc to emit the non-overloaded form of the intrinsics for
ctpop, cttz, ctlz, isunordered, and sqrt.
---
Diffs of the changes: (+50 -7)
llvm-expand.c | 57 ++---
1 files changed, 50 insertions(+), 7 deletions(-)
Index: llvm-gcc/gcc/llvm-expand.c
diff -u llvm-gcc/gcc/llvm-expand.c:1.124 llvm-gcc/gcc/llvm-expand.c:1.125
--- llvm-gcc/gcc/llvm-expand.c:1.124Mon Jan 9 13:42:32 2006
+++ llvm-gcc/gcc/llvm-expand.c Mon Jan 16 16:21:14 2006
@@ -419,7 +419,7 @@
FnTy-Elements[2] = FloatTy;
FnTy = llvm_type_get_cannonical_function(FnTy);
llvm_isunordered_float_fn =
-G2V(CreateIntrinsicFnWithType(llvm.isunordered, FnTy));
+G2V(CreateIntrinsicFnWithType(llvm.isunordered.f32, FnTy));
}
I-Operands[0] = llvm_isunordered_float_fn;
@@ -431,7 +431,7 @@
FnTy-Elements[2] = DoubleTy;
FnTy = llvm_type_get_cannonical_function(FnTy);
llvm_isunordered_double_fn =
-G2V(CreateIntrinsicFnWithType(llvm.isunordered, FnTy));
+G2V(CreateIntrinsicFnWithType(llvm.isunordered.f64, FnTy));
}
I-Operands[0] = llvm_isunordered_double_fn;
@@ -4759,7 +4759,15 @@
case BUILT_IN_SQRTL:
/* If errno math has been disabled, expand these to llvm.sqrt calls. */
if (!flag_errno_math) {
- return llvm_expand_builtin_unaryop(Fn, DestTy, arglist, llvm.sqrt);
+ Op0 = llvm_expand_expr(Fn, TREE_VALUE(arglist), 0);
+ switch (Op0-Ty-ID) {
+ case FloatTyID:
+return llvm_expand_builtin_unaryop(Fn, DestTy,
arglist,llvm.sqrt.f32);
+ case DoubleTyID:
+return llvm_expand_builtin_unaryop(Fn, DestTy,
arglist,llvm.sqrt.f64);
+ default:
+abort(); /* shouldn't happen */
+ }
} else {
/* Otherwise, expand as a call to sqrt*. */
return llvm_expand_call (Fn, exp, DestLoc);
@@ -4941,16 +4949,51 @@
case BUILT_IN_CLZ:
case BUILT_IN_CLZL:
case BUILT_IN_CLZLL:
-return llvm_expand_builtin_unaryop(Fn, DestTy, arglist, llvm.ctlz);
+Op0 = llvm_expand_expr(Fn, TREE_VALUE(arglist), 0);
+switch (Op0-Ty-ID) {
+case UByteTyID: case SByteTyID: /* 8 bit types... */
+ return llvm_expand_builtin_unaryop(Fn, DestTy, arglist, llvm.ctlz.i8);
+case UShortTyID: case ShortTyID: /* 16 bit types... */
+ return llvm_expand_builtin_unaryop(Fn, DestTy, arglist, llvm.ctlz.i16);
+case UIntTyID: case IntTyID: /* 32 bit types... */
+ return llvm_expand_builtin_unaryop(Fn, DestTy, arglist, llvm.ctlz.i32);
+case ULongTyID: case LongTyID: /* 64 bit types... */
+ return llvm_expand_builtin_unaryop(Fn, DestTy, arglist, llvm.ctlz.i64);
+default:
+ abort(); /* this shouldn't happen? */
+}
case BUILT_IN_CTZ:
case BUILT_IN_CTZL:
case BUILT_IN_CTZLL:
-return llvm_expand_builtin_unaryop(Fn, DestTy, arglist, llvm.cttz);
-
+Op0 = llvm_expand_expr(Fn, TREE_VALUE(arglist), 0);
+switch (Op0-Ty-ID) {
+case UByteTyID: case SByteTyID: /* 8 bit types... */
+ return llvm_expand_builtin_unaryop(Fn, DestTy, arglist, llvm.cttz.i8);
+case UShortTyID: case ShortTyID: /* 16 bit types... */
+ return llvm_expand_builtin_unaryop(Fn, DestTy, arglist, llvm.cttz.i16);
+case UIntTyID: case IntTyID: /* 32 bit types... */
+ return llvm_expand_builtin_unaryop(Fn, DestTy, arglist, llvm.cttz.i32);
+case ULongTyID: case LongTyID: /* 64 bit types... */
+ return llvm_expand_builtin_unaryop(Fn, DestTy, arglist, llvm.cttz.i64);
+default:
+ abort(); /* this shouldn't happen? */
+}
case BUILT_IN_POPCOUNT:
case BUILT_IN_POPCOUNTL:
case BUILT_IN_POPCOUNTLL:
-return llvm_expand_builtin_unaryop(Fn, DestTy, arglist, llvm.ctpop);
+Op0 = llvm_expand_expr(Fn, TREE_VALUE(arglist), 0);
+switch (Op0-Ty-ID) {
+case UByteTyID: case SByteTyID: /* 8 bit types... */
+ return llvm_expand_builtin_unaryop(Fn, DestTy, arglist, llvm.ctpop.i8);
+case UShortTyID: case ShortTyID: /* 16 bit types... */
+ return llvm_expand_builtin_unaryop(Fn, DestTy, arglist,
llvm.ctpop.i16);
+case UIntTyID: case IntTyID: /* 32 bit types... */
+ return llvm_expand_builtin_unaryop(Fn, DestTy, arglist,
llvm.ctpop.i32);
+case ULongTyID: case LongTyID: /* 64 bit types... */
+ return llvm_expand_builtin_unaryop(Fn, DestTy, arglist,
llvm.ctpop.i64);
+default:
+ abort(); /* this shouldn't happen? */
+}
#if 0
case BUILT_IN_PARITY:
___
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[llvm-commits] CVS: llvm/docs/LangRef.html
Changes in directory llvm/docs: LangRef.html updated: 1.129 - 1.130 --- Log message: Consistency --- Diffs of the changes: (+6 -6) LangRef.html | 12 ++-- 1 files changed, 6 insertions(+), 6 deletions(-) Index: llvm/docs/LangRef.html diff -u llvm/docs/LangRef.html:1.129 llvm/docs/LangRef.html:1.130 --- llvm/docs/LangRef.html:1.129Mon Jan 16 15:14:01 2006 +++ llvm/docs/LangRef.html Mon Jan 16 16:34:14 2006 @@ -155,9 +155,9 @@ lia href=#int_manipBit Manipulation Intrinsics/a ol lia href=#i_bswap'ttllvm.bswap.*/tt' Intrinsics/a/li - lia href=#int_ctpop'ttllvm.ctpop/tt' Intrinsic /a/li - lia href=#int_ctlz'ttllvm.ctlz/tt' Intrinsic /a/li - lia href=#int_cttz'ttllvm.cttz/tt' Intrinsic /a/li + lia href=#int_ctpop'ttllvm.ctpop.*/tt' Intrinsic /a/li + lia href=#int_ctlz'ttllvm.ctlz.*/tt' Intrinsic /a/li + lia href=#int_cttz'ttllvm.cttz.*/tt' Intrinsic /a/li /ol /li lia href=#int_debuggerDebugger intrinsics/a/li @@ -3549,7 +3549,7 @@ !-- ___ -- div class=doc_subsubsection - a name=int_ctlz'ttllvm.ctlz/tt' Intrinsic/a + a name=int_ctlz'ttllvm.ctlz.*/tt' Intrinsic/a /div div class=doc_text @@ -3589,7 +3589,7 @@ !-- ___ -- div class=doc_subsubsection - a name=int_cttz'ttllvm.cttz/tt' Intrinsic/a + a name=int_cttz'ttllvm.cttz.*/tt' Intrinsic/a /div div class=doc_text @@ -3650,7 +3650,7 @@ a href=mailto:[EMAIL PROTECTED]Chris Lattner/abr a href=http://llvm.cs.uiuc.edu;The LLVM Compiler Infrastructure/abr - Last modified: $Date: 2006/01/16 21:14:01 $ + Last modified: $Date: 2006/01/16 22:34:14 $ /address /body /html ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/ADT/UniqueVector.h
Changes in directory llvm/include/llvm/ADT:
UniqueVector.h added (r1.1)
---
Log message:
UniqueVector template provides a means of enumerating objects uniquely.
---
Diffs of the changes: (+70 -0)
UniqueVector.h | 70 +
1 files changed, 70 insertions(+)
Index: llvm/include/llvm/ADT/UniqueVector.h
diff -c /dev/null llvm/include/llvm/ADT/UniqueVector.h:1.1
*** /dev/null Mon Jan 16 17:29:53 2006
--- llvm/include/llvm/ADT/UniqueVector.hMon Jan 16 17:29:43 2006
***
*** 0
--- 1,70
+
+ //===-- llvm/ADT/UniqueVector.h -*- C++
-*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by James M. Laskey and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for
details.
+ //
+
//===--===//
+
+ #ifndef LLVM_ADT_UNIQUEVECTOR_H
+ #define LLVM_ADT_UNIQUEVECTOR_H
+
+ #include map
+ #include vector
+
+ namespace llvm {
+
+
//===--===//
+ /// UniqueVector - This class produces a sequential ID number (base 1) for
each
+ /// unique entry that is added. This class also provides an ID ordered vector
+ /// of the entries (indexed by ID - 1.) T is the type of entries in the
vector.
+ /// This class should have an implementation of operator== and of operator.
+ templateclass T class UniqueVector {
+ private:
+ // Map - Used to handle the correspondence of entry to ID.
+ typename std::mapT, unsigned Map;
+
+ // Vector - ID ordered vector of entries. Entries can be indexed by ID - 1.
+ //
+ typename std::vectorT Vector;
+
+ public:
+ /// insert - Append entry to the vector if it doesn't already exist.
Returns
+ /// the entry's index + 1 to be used as a unique ID.
+ unsigned insert(const T Entry) {
+ // Check if the entry is already in the map.
+ typename std::mapT, unsigned::iterator MI = Map.lower_bound(Entry);
+
+ // See if entry exists, if so return prior ID.
+ if (MI != Map.end() MI-first == Entry) return MI-second;
+
+ // Compute ID for entry.
+ unsigned ID = Vector.size() + 1;
+
+ // Insert in map.
+ Map.insert(MI, std::make_pair(Entry, ID));
+
+ // Insert in vector.
+ Vector.push_back(Entry);
+
+ return ID;
+ }
+
+ /// operator[] - Returns a reference to the entry with the specified ID.
+ ///
+ const T operator[](unsigned ID) const { return Vector[ID - 1]; }
+
+ /// size - Returns the number of entries in the vector.
+ ///
+ size_t size() const { return Vector.size(); }
+
+ /// getVector - Return the ID ordered vector of entries.
+ ///
+ inline const typename std::vectorT getVector() const { return Vector; }
+ };
+
+ } // End of namespace llvm
+
+ #endif // LLVM_ADT_UNIQUEVECTOR_H
\ No newline at end of file
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.208 - 1.209
---
Log message:
More typo's
---
Diffs of the changes: (+2 -2)
X86InstrInfo.td |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.208
llvm/lib/Target/X86/X86InstrInfo.td:1.209
--- llvm/lib/Target/X86/X86InstrInfo.td:1.208 Mon Jan 16 16:48:46 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Mon Jan 16 17:26:53 2006
@@ -2797,9 +2797,9 @@
def FISUBR16m : FPI0xDE, MRM5m, (ops i16mem:$src), fisubr{s} $src;
def FISUBR32m : FPI0xDA, MRM5m, (ops i32mem:$src), fisubr{l} $src;
def FIDIV16m : FPI0xDE, MRM6m, (ops i16mem:$src), fidiv{s} $src;
-def FIDIV32m : FPI0xDA, MRM6m, (ops i32mem:$src), fidiv{s} $src;
+def FIDIV32m : FPI0xDA, MRM6m, (ops i32mem:$src), fidiv{l} $src;
def FIDIVR16m : FPI0xDE, MRM7m, (ops i16mem:$src), fidivr{s} $src;
-def FIDIVR32m : FPI0xDA, MRM7m, (ops i32mem:$src), fidivr{s} $src;
+def FIDIVR32m : FPI0xDA, MRM7m, (ops i32mem:$src), fidivr{l} $src;
// NOTE: GAS and apparently all other ATT style assemblers have a broken
notion
// of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
___
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[llvm-commits] CVS: llvm/include/llvm/ADT/UniqueVector.h
Changes in directory llvm/include/llvm/ADT:
UniqueVector.h updated: 1.1 - 1.2
---
Log message:
Redundant inline keyword.
---
Diffs of the changes: (+1 -1)
UniqueVector.h |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/include/llvm/ADT/UniqueVector.h
diff -u llvm/include/llvm/ADT/UniqueVector.h:1.1
llvm/include/llvm/ADT/UniqueVector.h:1.2
--- llvm/include/llvm/ADT/UniqueVector.h:1.1Mon Jan 16 17:29:43 2006
+++ llvm/include/llvm/ADT/UniqueVector.hMon Jan 16 17:44:03 2006
@@ -62,7 +62,7 @@
/// getVector - Return the ID ordered vector of entries.
///
- inline const typename std::vectorT getVector() const { return Vector; }
+ const typename std::vectorT getVector() const { return Vector; }
};
} // End of namespace llvm
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.43 - 1.44
X86InstrInfo.td updated: 1.209 - 1.210
---
Log message:
Bug fixes: fpGETRESULT should produces a flag result and X86ISD::FST should
read a flag.
---
Diffs of the changes: (+12 -10)
X86ISelLowering.cpp | 18 ++
X86InstrInfo.td |4 ++--
2 files changed, 12 insertions(+), 10 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.43
llvm/lib/Target/X86/X86ISelLowering.cpp:1.44
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.43Mon Jan 16 15:21:29 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Jan 16 18:19:47 2006
@@ -543,16 +543,17 @@
Chain = Hi.getValue(1);
break;
}
- case MVT::f32:
case MVT::f64: {
std::vectorMVT::ValueType Tys;
Tys.push_back(MVT::f64);
Tys.push_back(MVT::Other);
+Tys.push_back(MVT::Flag);
std::vectorSDOperand Ops;
Ops.push_back(Chain);
Ops.push_back(InFlag);
RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
-Chain = RetVal.getValue(1);
+Chain = RetVal.getValue(1);
+InFlag = RetVal.getValue(2);
if (X86ScalarSSE) {
unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
MachineFunction MF = DAG.getMachineFunction();
@@ -565,12 +566,12 @@
Ops.push_back(RetVal);
Ops.push_back(StackSlot);
Ops.push_back(DAG.getValueType(RetTyVT));
+ Ops.push_back(InFlag);
Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
DAG.getSrcValue(NULL));
Chain = RetVal.getValue(1);
-} else if (RetTyVT == MVT::f32)
- RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
+}
break;
}
}
@@ -1059,16 +1060,17 @@
Chain = Hi.getValue(1);
break;
}
- case MVT::f32:
case MVT::f64: {
std::vectorMVT::ValueType Tys;
Tys.push_back(MVT::f64);
Tys.push_back(MVT::Other);
+Tys.push_back(MVT::Flag);
std::vectorSDOperand Ops;
Ops.push_back(Chain);
Ops.push_back(InFlag);
RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
-Chain = RetVal.getValue(1);
+Chain = RetVal.getValue(1);
+InFlag = RetVal.getValue(2);
if (X86ScalarSSE) {
unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
MachineFunction MF = DAG.getMachineFunction();
@@ -1081,12 +1083,12 @@
Ops.push_back(RetVal);
Ops.push_back(StackSlot);
Ops.push_back(DAG.getValueType(RetTyVT));
+ Ops.push_back(InFlag);
Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
DAG.getSrcValue(NULL));
Chain = RetVal.getValue(1);
-} else if (RetTyVT == MVT::f32)
- RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
+}
break;
}
}
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.209
llvm/lib/Target/X86/X86InstrInfo.td:1.210
--- llvm/lib/Target/X86/X86InstrInfo.td:1.209 Mon Jan 16 17:26:53 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Mon Jan 16 18:19:47 2006
@@ -93,14 +93,14 @@
[SDNPHasChain, SDNPOutFlag, SDNPOptInFlag];
def X86fpget : SDNodeX86ISD::FP_GET_RESULT, SDTX86FpGet,
-[SDNPHasChain, SDNPInFlag];
+[SDNPHasChain, SDNPInFlag, SDNPOutFlag];
def X86fpset : SDNodeX86ISD::FP_SET_RESULT, SDTX86FpSet,
[SDNPHasChain, SDNPOutFlag];
def X86fld : SDNodeX86ISD::FLD, SDTX86Fld,
[SDNPHasChain];
def X86fst : SDNodeX86ISD::FST, SDTX86Fst,
-[SDNPHasChain];
+[SDNPHasChain, SDNPInFlag];
def X86fild: SDNodeX86ISD::FILD, SDTX86Fild,
[SDNPHasChain];
def X86fp_to_i16mem : SDNodeX86ISD::FP_TO_INT16_IN_MEM, SDTX86FpToIMem,
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[llvm-commits] CVS: llvm/lib/Support/CommandLine.cpp ToolRunner.cpp
Changes in directory llvm/lib/Support:
CommandLine.cpp updated: 1.65 - 1.66
ToolRunner.cpp updated: 1.46 - 1.47
---
Log message:
Add support for programs with a null argv[0]
---
Diffs of the changes: (+32 -10)
CommandLine.cpp | 34 --
ToolRunner.cpp |8
2 files changed, 32 insertions(+), 10 deletions(-)
Index: llvm/lib/Support/CommandLine.cpp
diff -u llvm/lib/Support/CommandLine.cpp:1.65
llvm/lib/Support/CommandLine.cpp:1.66
--- llvm/lib/Support/CommandLine.cpp:1.65 Sun Dec 25 22:56:16 2005
+++ llvm/lib/Support/CommandLine.cppMon Jan 16 18:32:28 2006
@@ -448,8 +448,11 @@
}
if (Handler == 0) {
- std::cerr ProgramName : Unknown command line argument '
argv[i]
- '. Try: ' argv[0] --help'\n;
+ if (ProgramName)
+std::cerr ProgramName : Unknown command line argument '
+ argv[i] '. Try: ' argv[0] --help'\n;
+ else
+std::cerr Unknown command line argument ' argv[i] '.\n;
ErrorParsing = true;
continue;
}
@@ -485,17 +488,28 @@
// Check and handle positional arguments now...
if (NumPositionalRequired PositionalVals.size()) {
-std::cerr ProgramName
- : Not enough positional command line arguments specified!\n
- Must specify at least NumPositionalRequired
-positional arguments: See: argv[0] --help\n;
+if (ProgramName)
+ std::cerr ProgramName
+ : Not enough positional command line arguments
specified!\n
+ Must specify at least NumPositionalRequired
+ positional arguments: See: argv[0] --help\n;
+else
+ std::cerr Not enough positional command line arguments specified!\n
+ Must specify at least NumPositionalRequired
+ positional arguments.;
+
ErrorParsing = true;
} else if (!HasUnlimitedPositionals
PositionalVals.size() PositionalOpts.size()) {
-std::cerr ProgramName
- : Too many positional arguments specified!\n
- Can specify at most PositionalOpts.size()
-positional arguments: See: argv[0] --help\n;
+if (ProgramName)
+ std::cerr ProgramName
+ : Too many positional arguments specified!\n
+ Can specify at most PositionalOpts.size()
+ positional arguments: See: argv[0] --help\n;
+else
+ std::cerr Too many positional arguments specified!\n
+ Can specify at most PositionalOpts.size()
+ positional arguments.\n;
ErrorParsing = true;
} else if (ConsumeAfterOpt == 0) {
Index: llvm/lib/Support/ToolRunner.cpp
diff -u llvm/lib/Support/ToolRunner.cpp:1.46
llvm/lib/Support/ToolRunner.cpp:1.47
--- llvm/lib/Support/ToolRunner.cpp:1.46Mon Aug 29 08:14:24 2005
+++ llvm/lib/Support/ToolRunner.cpp Mon Jan 16 18:32:28 2006
@@ -394,7 +394,15 @@
sys::Path OutputBinary (ProgramFile+.gcc.exe);
OutputBinary.makeUnique();
GCCArgs.push_back(OutputBinary.c_str()); // Output to the right file...
+ GCCArgs.push_back(-lz);
GCCArgs.push_back(-lm);// Hard-code the math library...
+ GCCArgs.push_back(-x);
+ GCCArgs.push_back(none);
+ GCCArgs.push_back(/usr/local/lib/NAGWare/quickfit.o);
+ GCCArgs.push_back(-Xlinker);
+ GCCArgs.push_back(-flat_namespace);
+ GCCArgs.push_back(/usr/local/lib/NAGWare/libf97.dylib);
+ GCCArgs.push_back(/usr/local/lib/NAGWare/libf96.a);
GCCArgs.push_back(-O2);// Optimize the program a bit...
#if defined (HAVE_LINK_R)
GCCArgs.push_back(-Wl,-R.);// Search this dir for .so files
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAG.h updated: 1.84 - 1.85
---
Log message:
Yet another getTargetNode() variant. I promise one of these days I'll fix
tblgen so this is unnecessary.
---
Diffs of the changes: (+12 -0)
SelectionDAG.h | 12
1 files changed, 12 insertions(+)
Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.84
llvm/include/llvm/CodeGen/SelectionDAG.h:1.85
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.84 Mon Jan 9 12:29:18 2006
+++ llvm/include/llvm/CodeGen/SelectionDAG.hMon Jan 16 18:32:38 2006
@@ -476,6 +476,18 @@
}
SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, MVT::ValueType VT3,
+ SDOperand Op1, SDOperand Op2) {
+std::vectorMVT::ValueType ResultTys;
+ResultTys.push_back(VT1);
+ResultTys.push_back(VT2);
+ResultTys.push_back(VT3);
+std::vectorSDOperand Ops;
+Ops.push_back(Op1);
+Ops.push_back(Op2);
+return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops);
+ }
+ SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT1,
+ MVT::ValueType VT2, MVT::ValueType VT3,
SDOperand Op1, SDOperand Op2,
SDOperand Op3, SDOperand Op4, SDOperand Op5,
SDOperand Op6) {
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[llvm-commits] CVS: llvm/lib/Support/ToolRunner.cpp
Changes in directory llvm/lib/Support: ToolRunner.cpp updated: 1.47 - 1.48 --- Log message: Revert this, I didn't mean to commit it --- Diffs of the changes: (+0 -8) ToolRunner.cpp |8 1 files changed, 8 deletions(-) Index: llvm/lib/Support/ToolRunner.cpp diff -u llvm/lib/Support/ToolRunner.cpp:1.47 llvm/lib/Support/ToolRunner.cpp:1.48 --- llvm/lib/Support/ToolRunner.cpp:1.47Mon Jan 16 18:32:28 2006 +++ llvm/lib/Support/ToolRunner.cpp Mon Jan 16 18:40:24 2006 @@ -394,15 +394,7 @@ sys::Path OutputBinary (ProgramFile+.gcc.exe); OutputBinary.makeUnique(); GCCArgs.push_back(OutputBinary.c_str()); // Output to the right file... - GCCArgs.push_back(-lz); GCCArgs.push_back(-lm);// Hard-code the math library... - GCCArgs.push_back(-x); - GCCArgs.push_back(none); - GCCArgs.push_back(/usr/local/lib/NAGWare/quickfit.o); - GCCArgs.push_back(-Xlinker); - GCCArgs.push_back(-flat_namespace); - GCCArgs.push_back(/usr/local/lib/NAGWare/libf97.dylib); - GCCArgs.push_back(/usr/local/lib/NAGWare/libf96.a); GCCArgs.push_back(-O2);// Optimize the program a bit... #if defined (HAVE_LINK_R) GCCArgs.push_back(-Wl,-R.);// Search this dir for .so files ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.23 - 1.24
---
Log message:
fixing divides
---
Diffs of the changes: (+9 -12)
IA64ISelDAGToDAG.cpp | 21 +
1 files changed, 9 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.23
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.24
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.23 Mon Jan 16 08:33:04 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Mon Jan 16 19:19:49 2006
@@ -228,6 +228,8 @@
TmpPR = TmpF5.getValue(1);
Chain = TmpF5.getValue(2);
+Chain = CurDAG-getCopyToReg(Chain, IA64::F8, TmpF5);
+
SDOperand minusB;
if(isModulus) { // for remainders, it'll be handy to have
// copies of -input_b
@@ -287,23 +289,18 @@
TmpR2 = CurDAG-getTargetNode(IA64::CFNMAS1, MVT::f64,
TmpF4, TmpQ2, TmpF3, TmpPR);
Chain = TmpR2.getValue(1);
-
+
// we want TmpQ3 to have the same target register as the frcpa? maybe we
// should two-address hack it. See the comment for this to work... on page
// 48 of Intel application note #245415
- TmpQ3 = CurDAG-getTargetNode(IA64::CFMAS1, MVT::f64,
-TmpR2, TmpY2, TmpQ2, TmpPR);
+ TmpQ3 = CurDAG-getTargetNode(IA64::TCFMAS1, MVT::f64,
+TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR);
Chain = TmpQ3.getValue(1);
- // FIXME: this is unfortunate :(
- // the story is that the dest reg of the fnma above and the fma below it
- // (and therefore the src of the fcvt.fx[u] below as well) cannot
- // be the same register, or this code breaks if the first argument is
- // zero. (e.g. without this hack, 0%8 yields -64, not 0.)
-/* XXX: these two lines do nothing */
- SDOperand bogus = CurDAG-getTargetNode(IA64::IUSE, MVT::Other, TmpR2);
- Chain = bogus.getValue(0);
-
+ // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
+ // the FPSWA won't be able to help out in the case of large/tiny
+ // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
+
if(isSigned)
TmpQ = CurDAG-getTargetNode(IA64::FCVTFXTRUNCS1, MVT::f64, TmpQ3);
else
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[llvm-commits] CVS: llvm-test/Makefile.tests
Changes in directory llvm-test: Makefile.tests updated: 1.5 - 1.6 --- Log message: Pass -emit-llvm to llvm-gcc. This flag is ignored by the old front-end, and tells the new front-end to emit a .ll (instead of a .s file) file like the old one does. --- Diffs of the changes: (+3 -3) Makefile.tests |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm-test/Makefile.tests diff -u llvm-test/Makefile.tests:1.5 llvm-test/Makefile.tests:1.6 --- llvm-test/Makefile.tests:1.5Tue Mar 8 16:58:33 2005 +++ llvm-test/Makefile.testsMon Jan 16 19:20:40 2006 @@ -50,15 +50,15 @@ # Compile from X.c to Output/X.ll Output/%.ll: %.c $(LCC1) Output/.dir $(INCLUDES) - -$(LLVMGCC) $(CPPFLAGS) $(LCCFLAGS) -S $ -o $@ + -$(LLVMGCC) $(CPPFLAGS) $(LCCFLAGS) -S $ -o $@ -emit-llvm # Compile from X.cpp to Output/X.ll Output/%.ll: %.cpp $(LCC1XX) Output/.dir $(INCLUDES) - -$(LLVMGXX) $(CPPFLAGS) $(LCXXFLAGS) -S $ -o $@ + -$(LLVMGXX) $(CPPFLAGS) $(LCXXFLAGS) -S $ -o $@ -emit-llvm # Compile from X.cc to Output/X.ll Output/%.ll: %.cc $(LCC1XX) Output/.dir $(INCLUDES) - -$(LLVMGXX) $(CPPFLAGS) $(LCXXFLAGS) -S $ -o $@ + -$(LLVMGXX) $(CPPFLAGS) $(LCXXFLAGS) -S $ -o $@ -emit-llvm # LLVM Assemble from Output/X.ll to Output/X.bc. Output/X.ll must have come # from GCC output, so use GCCAS. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td IA64RegisterInfo.cpp IA64RegisterInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64InstrInfo.td updated: 1.38 - 1.39
IA64RegisterInfo.cpp updated: 1.9 - 1.10
IA64RegisterInfo.td updated: 1.12 - 1.13
---
Log message:
use proper (82-bit) spills/fills when spilling FP regs, so that
divides don't get broken. this fixes obsequi, smg2000, and probably
a bunch of other stuff (tm)
---
Diffs of the changes: (+11 -3)
IA64InstrInfo.td |4
IA64RegisterInfo.cpp |4 ++--
IA64RegisterInfo.td |6 +-
3 files changed, 11 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.38
llvm/lib/Target/IA64/IA64InstrInfo.td:1.39
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.38 Mon Jan 16 00:33:38 2006
+++ llvm/lib/Target/IA64/IA64InstrInfo.td Mon Jan 16 20:04:52 2006
@@ -537,6 +537,8 @@
stfs [$dstPtr] = $value;;;
def STF8 : AForm0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
stfd [$dstPtr] = $value;;;
+ def STF_SPILL : AForm0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
+stf.spill [$dstPtr] = $value;;;
}
let isLoad = 1 in {
@@ -552,6 +554,8 @@
ldfs $dst = [$srcPtr];;;
def LDF8 : AForm0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
ldfd $dst = [$srcPtr];;;
+ def LDF_FILL : AForm0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
+ldf.fill $dst = [$srcPtr];;;
}
def POPCNT : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src),
Index: llvm/lib/Target/IA64/IA64RegisterInfo.cpp
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.9
llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.10
--- llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.9 Thu Oct 27 23:58:24 2005
+++ llvm/lib/Target/IA64/IA64RegisterInfo.cpp Mon Jan 16 20:04:52 2006
@@ -40,7 +40,7 @@
const TargetRegisterClass *RC)
const{
if (RC == IA64::FPRegisterClass) {
-BuildMI(MBB, MI, IA64::STF8, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
+BuildMI(MBB, MI, IA64::STF_SPILL,
2).addFrameIndex(FrameIdx).addReg(SrcReg);
} else if (RC == IA64::GRRegisterClass) {
BuildMI(MBB, MI, IA64::ST8, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
}
@@ -63,7 +63,7 @@
const TargetRegisterClass
*RC)const{
if (RC == IA64::FPRegisterClass) {
-BuildMI(MBB, MI, IA64::LDF8, 1, DestReg).addFrameIndex(FrameIdx);
+BuildMI(MBB, MI, IA64::LDF_FILL, 1, DestReg).addFrameIndex(FrameIdx);
} else if (RC == IA64::GRRegisterClass) {
BuildMI(MBB, MI, IA64::LD8, 1, DestReg).addFrameIndex(FrameIdx);
} else if (RC == IA64::PRRegisterClass) {
Index: llvm/lib/Target/IA64/IA64RegisterInfo.td
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.td:1.12
llvm/lib/Target/IA64/IA64RegisterInfo.td:1.13
--- llvm/lib/Target/IA64/IA64RegisterInfo.td:1.12 Wed Dec 21 21:56:03 2005
+++ llvm/lib/Target/IA64/IA64RegisterInfo.tdMon Jan 16 20:04:52 2006
@@ -282,7 +282,11 @@
// these are the scratch (+stacked) FP registers
-def FP : RegisterClassIA64, [f64], 64,
+
+// the 128 here is to make stf.spill/ldf.fill happy,
+// when storing full (82-bit) FP regs to stack slots
+// we need to 16-byte align
+def FP : RegisterClassIA64, [f64], 128,
[F6, F7,
F8, F9, F10, F11, F12, F13, F14, F15,
F32, F33, F34, F35, F36, F37, F38, F39,
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.45 - 1.46 --- Log message: SSE does not support i64 SINT_TO_FP (FP stack doesn't either, but we custom expand it), so ask legalizer to expand i32 UINT_TO_FP. --- Diffs of the changes: (+6 -1) X86ISelLowering.cpp |7 ++- 1 files changed, 6 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.45 llvm/lib/Target/X86/X86ISelLowering.cpp:1.46 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.45Mon Jan 16 18:37:42 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Jan 16 20:32:49 2006 @@ -52,7 +52,12 @@ setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); - setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); + + if (X86ScalarSSE) +// No SSE i64 SINT_TO_FP, so expand i32 UINT_TO_FP instead. +setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand); + else +setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have // this operation. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/win32/VMCore/VMCore.vcproj
Changes in directory llvm/win32/VMCore: VMCore.vcproj updated: 1.12 - 1.13 --- Log message: Visual Studio still has issues with being left out. --- Diffs of the changes: (+6 -0) VMCore.vcproj |6 ++ 1 files changed, 6 insertions(+) Index: llvm/win32/VMCore/VMCore.vcproj diff -u llvm/win32/VMCore/VMCore.vcproj:1.12 llvm/win32/VMCore/VMCore.vcproj:1.13 --- llvm/win32/VMCore/VMCore.vcproj:1.12Wed Jan 11 10:21:53 2006 +++ llvm/win32/VMCore/VMCore.vcproj Mon Jan 16 23:13:22 2006 @@ -112,6 +112,9 @@ RelativePath=..\..\lib\VMCore\AsmWriter.cpp /File File + RelativePath=..\..\lib\VMCore\AutoUpgrade.cpp + /File + File RelativePath=..\..\lib\VMCore\BasicBlock.cpp /File File @@ -186,6 +189,9 @@ RelativePath=..\..\include\llvm\Assembly\AsmAnnotationWriter.h /File File + RelativePath=..\..\include\llvm\Assembly\AutoUpgrade.h + /File + File RelativePath=..\..\include\llvm\BasicBlock.h /File File ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/win32/Transforms/Transforms.vcproj
Changes in directory llvm/win32/Transforms: Transforms.vcproj updated: 1.19 - 1.20 --- Log message: Visual Studio still has issues with being left out. --- Diffs of the changes: (+0 -3) Transforms.vcproj |3 --- 1 files changed, 3 deletions(-) Index: llvm/win32/Transforms/Transforms.vcproj diff -u llvm/win32/Transforms/Transforms.vcproj:1.19 llvm/win32/Transforms/Transforms.vcproj:1.20 --- llvm/win32/Transforms/Transforms.vcproj:1.19Fri Dec 16 18:14:47 2005 +++ llvm/win32/Transforms/Transforms.vcproj Mon Jan 16 23:13:21 2006 @@ -279,9 +279,6 @@ RelativePath=..\..\lib\Transforms\Scalar\Mem2Reg.cpp /File File - RelativePath=..\..\lib\Transforms\Scalar\PRE.cpp - /File - File RelativePath=..\..\lib\Transforms\Scalar\Reassociate.cpp /File File ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/win32/Support/Support.vcproj
Changes in directory llvm/win32/Support: Support.vcproj updated: 1.12 - 1.13 --- Log message: Visual Studio still has issues with being left out. --- Diffs of the changes: (+3 -15) Support.vcproj | 18 +++--- 1 files changed, 3 insertions(+), 15 deletions(-) Index: llvm/win32/Support/Support.vcproj diff -u llvm/win32/Support/Support.vcproj:1.12 llvm/win32/Support/Support.vcproj:1.13 --- llvm/win32/Support/Support.vcproj:1.12 Fri Dec 16 18:14:47 2005 +++ llvm/win32/Support/Support.vcproj Mon Jan 16 23:13:21 2006 @@ -129,16 +129,6 @@ /File File RelativePath=..\..\lib\Support\FileUtilities.cpp - FileConfiguration - Name=Debug|Win32 - Tool - Name=VCCLCompilerTool/ - /FileConfiguration - FileConfiguration - Name=Release|Win32 - Tool - Name=VCCLCompilerTool/ - /FileConfiguration /File File RelativePath=..\..\lib\Support\IsInf.cpp @@ -178,11 +168,6 @@ /File File RelativePath=..\..\lib\Support\ToolRunner.cpp - FileConfiguration - Name=Debug|Win32 - Tool - Name=VCCLCompilerTool/ - /FileConfiguration /File Filter Name=bzip2 @@ -381,6 +366,9 @@ RelativePath=..\..\include\llvm\Adt\Tree.h /File File + RelativePath=..\..\include\llvm\Adt\UniqueVector.h + /File + File RelativePath=..\..\include\llvm\Adt\VectorExtras.h /File /Filter ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-gcc/gcc/llvm-expand.c llvm-representation.h llvm-types.c
Changes in directory llvm-gcc/gcc:
llvm-expand.c updated: 1.125 - 1.126
llvm-representation.h updated: 1.22 - 1.23
llvm-types.c updated: 1.31 - 1.32
---
Log message:
Force bit count intrinsics to all have unsigned operands and unsigned results.
---
Diffs of the changes: (+70 -45)
llvm-expand.c | 101 --
llvm-representation.h |3 -
llvm-types.c | 11 +
3 files changed, 70 insertions(+), 45 deletions(-)
Index: llvm-gcc/gcc/llvm-expand.c
diff -u llvm-gcc/gcc/llvm-expand.c:1.125 llvm-gcc/gcc/llvm-expand.c:1.126
--- llvm-gcc/gcc/llvm-expand.c:1.125Mon Jan 16 16:21:14 2006
+++ llvm-gcc/gcc/llvm-expand.c Tue Jan 17 00:22:23 2006
@@ -3394,7 +3394,7 @@
/* Add a PHI node to merge together the two computed values */
- if (CondBr-NumOperands == 1 CondBr-Operands[0] != DoneBlock) {
+ if (CondBr-NumOperands == 1 CondBr-Operands[0] != D2V(DoneBlock)) {
/* The cond branch terminating FromBlock was folded to not go to the done
* block at all. This code is only reachable from the TestBlock.
*/
@@ -4585,19 +4585,23 @@
return BL-Fn = CreateIntrinsicFnWithType(Name, FnTy);
}
-static llvm_value *
-llvm_expand_builtin_unaryop(llvm_function *Fn, llvm_type *DestTy,
-tree arglist, const char *FnName) {
- llvm_value *arg;
- llvm_instruction *TheCall;
+/* llvm_expand_unaryop - Expand the specified operand list to a unary function,
+ * checking that it is actually a list with one element.
+ */
+static llvm_value *llvm_expand_unaryop(llvm_function *Fn, tree arglist) {
if (arglist == 0 || TREE_CHAIN(arglist) != 0) {
-error(Invalid argument list to `%s', FnName);
-return llvm_constant_get_null(DestTy);
+error(Invalid argument list to function);
+exit(1);
}
-
- arg = llvm_expand_expr(Fn, TREE_VALUE(arglist), 0);
- TheCall = llvm_instruction_new(arg-Ty, tmp, O_Call, 2);
+ return llvm_expand_expr(Fn, TREE_VALUE(arglist), 0);
+}
+
+static llvm_value *
+llvm_expand_builtin_unaryop(llvm_function *Fn, llvm_type *DestTy,
+llvm_value *arg, const char *FnName) {
+ llvm_instruction *TheCall =
+llvm_instruction_new(arg-Ty, tmp, O_Call, 2);
TheCall-Operands[0] = G2V(GetUnaryBuiltin(FnName, arg-Ty));
TheCall-Operands[1] = arg;
append_inst(Fn, TheCall);
@@ -4759,12 +4763,12 @@
case BUILT_IN_SQRTL:
/* If errno math has been disabled, expand these to llvm.sqrt calls. */
if (!flag_errno_math) {
- Op0 = llvm_expand_expr(Fn, TREE_VALUE(arglist), 0);
+ Op0 = llvm_expand_unaryop(Fn, arglist);
switch (Op0-Ty-ID) {
case FloatTyID:
-return llvm_expand_builtin_unaryop(Fn, DestTy,
arglist,llvm.sqrt.f32);
+return llvm_expand_builtin_unaryop(Fn, DestTy, Op0, llvm.sqrt.f32);
case DoubleTyID:
-return llvm_expand_builtin_unaryop(Fn, DestTy,
arglist,llvm.sqrt.f64);
+return llvm_expand_builtin_unaryop(Fn, DestTy, Op0, llvm.sqrt.f64);
default:
abort(); /* shouldn't happen */
}
@@ -4949,50 +4953,59 @@
case BUILT_IN_CLZ:
case BUILT_IN_CLZL:
case BUILT_IN_CLZLL:
-Op0 = llvm_expand_expr(Fn, TREE_VALUE(arglist), 0);
+Op0 = llvm_expand_unaryop(Fn, arglist);
+if (llvm_type_is_signed(Op0-Ty))
+ Op0 = cast_if_type_not_equal(Fn, Op0,
+ llvm_type_get_unsigned_version(Op0-Ty));
switch (Op0-Ty-ID) {
-case UByteTyID: case SByteTyID: /* 8 bit types... */
- return llvm_expand_builtin_unaryop(Fn, DestTy, arglist, llvm.ctlz.i8);
-case UShortTyID: case ShortTyID: /* 16 bit types... */
- return llvm_expand_builtin_unaryop(Fn, DestTy, arglist, llvm.ctlz.i16);
-case UIntTyID: case IntTyID: /* 32 bit types... */
- return llvm_expand_builtin_unaryop(Fn, DestTy, arglist, llvm.ctlz.i32);
-case ULongTyID: case LongTyID: /* 64 bit types... */
- return llvm_expand_builtin_unaryop(Fn, DestTy, arglist, llvm.ctlz.i64);
+case UByteTyID:
+ return llvm_expand_builtin_unaryop(Fn, DestTy, Op0, llvm.ctlz.i8);
+case UShortTyID:
+ return llvm_expand_builtin_unaryop(Fn, DestTy, Op0, llvm.ctlz.i16);
+case UIntTyID:
+ return llvm_expand_builtin_unaryop(Fn, DestTy, Op0, llvm.ctlz.i32);
+case ULongTyID:
+ return llvm_expand_builtin_unaryop(Fn, DestTy, Op0, llvm.ctlz.i64);
default:
- abort(); /* this shouldn't happen? */
+ abort(); /* this shouldn't happen */
}
case BUILT_IN_CTZ:
case BUILT_IN_CTZL:
case BUILT_IN_CTZLL:
-Op0 = llvm_expand_expr(Fn, TREE_VALUE(arglist), 0);
+Op0 = llvm_expand_unaryop(Fn, arglist);
+if (llvm_type_is_signed(Op0-Ty))
+ Op0 = cast_if_type_not_equal(Fn, Op0,
+ llvm_type_get_unsigned_version(Op0-Ty));
switch (Op0-Ty-ID) {
-case UByteTyID: case SByteTyID: /* 8 bit types... */
- return
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.210 - 1.211
---
Log message:
Zero extending load from i1 to i8.
---
Diffs of the changes: (+2 -0)
X86InstrInfo.td |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.210
llvm/lib/Target/X86/X86InstrInfo.td:1.211
--- llvm/lib/Target/X86/X86InstrInfo.td:1.210 Mon Jan 16 18:19:47 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Tue Jan 17 01:02:46 2006
@@ -343,6 +343,7 @@
def sextloadi32i8 : PatFrag(ops node:$ptr), (i32 (sextload node:$ptr, i8));
def sextloadi32i16 : PatFrag(ops node:$ptr), (i32 (sextload node:$ptr, i16));
+def zextloadi8i1 : PatFrag(ops node:$ptr), (i8 (zextload node:$ptr, i1));
def zextloadi16i1 : PatFrag(ops node:$ptr), (i16 (zextload node:$ptr, i1));
def zextloadi32i1 : PatFrag(ops node:$ptr), (i32 (zextload node:$ptr, i1));
def zextloadi16i8 : PatFrag(ops node:$ptr), (i16 (zextload node:$ptr, i8));
@@ -3029,6 +3030,7 @@
// {s|z}extload bool - {s|z}extload byte
def : Pat(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src);
def : Pat(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src);
+def : Pat(zextloadi8i1 addr:$src), (MOV8rm addr:$src);
def : Pat(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src);
def : Pat(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src);
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[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.134 - 1.135
---
Log message:
Emit a type matching check for ComplexPatterns.
---
Diffs of the changes: (+2 -0)
DAGISelEmitter.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.134
llvm/utils/TableGen/DAGISelEmitter.cpp:1.135
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.134Sun Jan 15 04:04:45 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp Tue Jan 17 01:36:41 2006
@@ -556,6 +556,8 @@
// Using a VTSDNode or CondCodeSDNode.
return Other;
} else if (R-isSubClassOf(ComplexPattern)) {
+if (NotRegisters)
+ return Unknown;
std::vectorunsigned char
ComplexPat(1, TP.getDAGISelEmitter().getComplexPattern(R).getValueType());
return ComplexPat;
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