[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCInstr64Bit.td
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.82 - 1.83
PPCInstr64Bit.td updated: 1.26 - 1.27
---
Log message:
Fix the PPC regressions last night
---
Diffs of the changes: (+7 -7)
PPCInstr64Bit.td|2 +-
PPCRegisterInfo.cpp | 12 ++--
2 files changed, 7 insertions(+), 7 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.82
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.83
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.82Tue Nov 14 12:44:47 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Wed Nov 15 11:40:51 2006
@@ -418,11 +418,11 @@
if (Old-getOpcode() == PPC::ADJCALLSTACKDOWN) {
if (!Subtarget.isPPC64()) {
BuildMI(MBB, I, PPC::LWZ, 2, PPC::R0).addImm(0).addReg(PPC::R31);
- BuildMI(MBB, I, PPC::STWU, 3)
+ BuildMI(MBB, I, PPC::STWU, 3, PPC::R1)
.addReg(PPC::R0).addImm(-Amount).addReg(PPC::R1);
} else {
BuildMI(MBB, I, PPC::LD, 2, PPC::X0).addImm(0).addReg(PPC::X31);
- BuildMI(MBB, I, PPC::STDU, 3)
+ BuildMI(MBB, I, PPC::STDU, 3, PPC::X1)
.addReg(PPC::X0).addImm(-Amount/4).addReg(PPC::X1);
}
} else {
@@ -684,8 +684,8 @@
BuildMI(MBB, MBBI, PPC::STWUX, 3)
.addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
} else if (NumBytes = 32768) {
- BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addImm(NegNumbytes)
-.addReg(PPC::R1);
+ BuildMI(MBB, MBBI, PPC::STWU, 3,
+ PPC::R1).addReg(PPC::R1).addImm(NegNumbytes).addReg(PPC::R1);
} else {
BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addImm(NegNumbytes 16);
BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
@@ -704,8 +704,8 @@
BuildMI(MBB, MBBI, PPC::STDUX, 3)
.addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0);
} else if (NumBytes = 32768*4) {
- BuildMI(MBB, MBBI, PPC::STDU, 3).addReg(PPC::X1).addImm(NegNumbytes/4)
- .addReg(PPC::X1);
+ BuildMI(MBB, MBBI, PPC::STDU, 3, PPC::X1)
+ .addReg(PPC::X1).addImm(NegNumbytes/4).addReg(PPC::X1);
} else {
BuildMI(MBB, MBBI, PPC::LIS8, 1, PPC::X0).addImm(NegNumbytes 16);
BuildMI(MBB, MBBI, PPC::ORI8, 2, PPC::X0).addReg(PPC::X0)
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.26
llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.27
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.26 Tue Nov 14 12:44:47 2006
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdWed Nov 15 11:40:51 2006
@@ -364,7 +364,7 @@
[(store G8RC:$rS, xaddr:$dst)], isPPC64,
PPC970_DGroup_Cracked;
-def STDU : DSForm_162, 1, (ops G8RC:$rS, memrix:$dst),
+def STDU : DSForm_162, 1, (ops G8RC:$ea_res, G8RC:$rS, memrix:$dst),
stdu $rS, $dst, LdStSTD,
[], isPPC64;
def STDUX : XForm_831, 181, (ops G8RC:$rS, memrr:$dst),
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.317 - 1.318 --- Log message: remove dead #include --- Diffs of the changes: (+0 -1) SelectionDAGISel.cpp |1 - 1 files changed, 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.317 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.318 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.317Thu Nov 9 22:41:34 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Nov 15 11:51:15 2006 @@ -24,7 +24,6 @@ #include llvm/Instructions.h #include llvm/Intrinsics.h #include llvm/IntrinsicInst.h -#include llvm/CodeGen/IntrinsicLowering.h #include llvm/CodeGen/MachineDebugInfo.h #include llvm/CodeGen/MachineFunction.h #include llvm/CodeGen/MachineFrameInfo.h ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/IntrinsicLowering.cpp
Changes in directory llvm/lib/CodeGen:
IntrinsicLowering.cpp updated: 1.45 - 1.46
---
Log message:
Simplify IntrinsicLowering and clarify that it is only for use by the
CBE and interpreter.
---
Diffs of the changes: (+3 -3)
IntrinsicLowering.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/IntrinsicLowering.cpp
diff -u llvm/lib/CodeGen/IntrinsicLowering.cpp:1.45
llvm/lib/CodeGen/IntrinsicLowering.cpp:1.46
--- llvm/lib/CodeGen/IntrinsicLowering.cpp:1.45 Wed Nov 8 00:47:33 2006
+++ llvm/lib/CodeGen/IntrinsicLowering.cpp Wed Nov 15 12:00:10 2006
@@ -7,7 +7,7 @@
//
//===--===//
//
-// This file implements the default intrinsic lowering implementation.
+// This file implements the IntrinsicLowering class.
//
//===--===//
@@ -82,7 +82,7 @@
return NewCI;
}
-void DefaultIntrinsicLowering::AddPrototypes(Module M) {
+void IntrinsicLowering::AddPrototypes(Module M) {
for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I)
if (I-isExternal() !I-use_empty())
switch (I-getIntrinsicID()) {
@@ -263,7 +263,7 @@
-void DefaultIntrinsicLowering::LowerIntrinsicCall(CallInst *CI) {
+void IntrinsicLowering::LowerIntrinsicCall(CallInst *CI) {
Function *Callee = CI-getCalledFunction();
assert(Callee Cannot lower an indirect call!);
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[llvm-commits] CVS: llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp
Changes in directory llvm/lib/ExecutionEngine/Interpreter:
Interpreter.cpp updated: 1.32 - 1.33
---
Log message:
Simplify IntrinsicLowering and clarify that it is only for use by the
CBE and interpreter.
---
Diffs of the changes: (+1 -1)
Interpreter.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp
diff -u llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp:1.32
llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp:1.33
--- llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp:1.32 Fri Jun 16
13:24:38 2006
+++ llvm/lib/ExecutionEngine/Interpreter/Interpreter.cppWed Nov 15
12:00:10 2006
@@ -67,7 +67,7 @@
initializeExternalFunctions();
emitGlobals();
- IL = new DefaultIntrinsicLowering();
+ IL = new IntrinsicLowering();
}
Interpreter::~Interpreter() {
___
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/IntrinsicLowering.h
Changes in directory llvm/include/llvm/CodeGen:
IntrinsicLowering.h updated: 1.10 - 1.11
---
Log message:
Simplify IntrinsicLowering and clarify that it is only for use by the
CBE and interpreter.
---
Diffs of the changes: (+3 -30)
IntrinsicLowering.h | 33 +++--
1 files changed, 3 insertions(+), 30 deletions(-)
Index: llvm/include/llvm/CodeGen/IntrinsicLowering.h
diff -u llvm/include/llvm/CodeGen/IntrinsicLowering.h:1.10
llvm/include/llvm/CodeGen/IntrinsicLowering.h:1.11
--- llvm/include/llvm/CodeGen/IntrinsicLowering.h:1.10 Fri Mar 10 16:49:05 2006
+++ llvm/include/llvm/CodeGen/IntrinsicLowering.h Wed Nov 15 12:00:10 2006
@@ -9,24 +9,7 @@
//
// This file defines the IntrinsicLowering interface. This interface allows
// addition of domain-specific or front-end specific intrinsics to LLVM without
-// having to modify all of the code generators to support the new intrinsic.
-// Later, as desired, targets can incrementally add support for particular
-// intrinsic functions, as desired, to generate better code.
-//
-// If a code generator cannot handle or does not know about an intrinsic
-// function, it will use the intrinsic lowering interface to change an
intrinsic
-// function name into a concrete function name which can be used to implement
-// the functionality of the intrinsic. For example, llvm.memcpy can be
-// implemented as a call to the math library 'memcpy' function if the target
-// doesn't have hardware support for the intrinsic, or if it has not yet been
-// implemented yet.
-//
-// Another use for this interface is the addition of domain-specific
intrinsics.
-// The default implementation of this interface would then lower the intrinsics
-// to noop calls, allowing the direct execution of programs with
instrumentation
-// or other hooks placed in them. When a specific tool or flag is used, a
-// different implementation of these interfaces may be used, which activates
the
-// intrinsics in some way.
+// having to modify all of the C backend or interpreter.
//
//===--===//
@@ -42,12 +25,11 @@
class IntrinsicLowering {
public:
IntrinsicLowering() {}
-virtual ~IntrinsicLowering() {}
/// AddPrototypes - This method, if called, causes all of the prototypes
/// that might be needed by an intrinsic lowering implementation to be
/// inserted into the module specified.
-virtual void AddPrototypes(Module M) = 0;
+void AddPrototypes(Module M);
/// LowerIntrinsicCall - This method returns the LLVM function which should
/// be used to implement the specified intrinsic function call. If an
@@ -59,16 +41,7 @@
/// _after_ the call instruction and the call is deleted. The caller must
/// be capable of handling this kind of change.
///
-virtual void LowerIntrinsicCall(CallInst *CI) = 0;
- };
-
- /// DefaultIntrinsicLower - This is the default intrinsic lowering pass which
- /// is used if no other one is specified. Custom intrinsic lowering
- /// implementations should pass any unhandled intrinsics to this
- /// implementation to allow for future extensibility.
- struct DefaultIntrinsicLowering : public IntrinsicLowering {
-virtual void AddPrototypes(Module M);
-virtual void LowerIntrinsicCall(CallInst *CI);
+void LowerIntrinsicCall(CallInst *CI);
};
}
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[llvm-commits] CVS: llvm/lib/Target/X86/X86.h X86JITInfo.h
Changes in directory llvm/lib/Target/X86:
X86.h updated: 1.48 - 1.49
X86JITInfo.h updated: 1.11 - 1.12
---
Log message:
Remove unneeded forward decls
---
Diffs of the changes: (+0 -2)
X86.h|1 -
X86JITInfo.h |1 -
2 files changed, 2 deletions(-)
Index: llvm/lib/Target/X86/X86.h
diff -u llvm/lib/Target/X86/X86.h:1.48 llvm/lib/Target/X86/X86.h:1.49
--- llvm/lib/Target/X86/X86.h:1.48 Sun Sep 3 23:14:57 2006
+++ llvm/lib/Target/X86/X86.h Wed Nov 15 11:53:13 2006
@@ -22,7 +22,6 @@
class X86TargetMachine;
class FunctionPassManager;
class FunctionPass;
-class IntrinsicLowering;
class MachineCodeEmitter;
/// createX86ISelDag - This pass converts a legalized DAG into a
Index: llvm/lib/Target/X86/X86JITInfo.h
diff -u llvm/lib/Target/X86/X86JITInfo.h:1.11
llvm/lib/Target/X86/X86JITInfo.h:1.12
--- llvm/lib/Target/X86/X86JITInfo.h:1.11 Sun Sep 3 23:14:57 2006
+++ llvm/lib/Target/X86/X86JITInfo.hWed Nov 15 11:53:13 2006
@@ -18,7 +18,6 @@
namespace llvm {
class X86TargetMachine;
- class IntrinsicLowering;
class X86JITInfo : public TargetJITInfo {
X86TargetMachine TM;
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[llvm-commits] CVS: llvm/lib/Target/CBackend/Writer.cpp
Changes in directory llvm/lib/Target/CBackend:
Writer.cpp updated: 1.281 - 1.282
---
Log message:
Simplify IntrinsicLowering and clarify that it is only for use by the
CBE and interpreter.
---
Diffs of the changes: (+1 -1)
Writer.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/CBackend/Writer.cpp
diff -u llvm/lib/Target/CBackend/Writer.cpp:1.281
llvm/lib/Target/CBackend/Writer.cpp:1.282
--- llvm/lib/Target/CBackend/Writer.cpp:1.281 Wed Nov 8 00:47:33 2006
+++ llvm/lib/Target/CBackend/Writer.cpp Wed Nov 15 12:00:10 2006
@@ -69,7 +69,7 @@
/// module to a C translation unit.
class CWriter : public FunctionPass, public InstVisitorCWriter {
std::ostream Out;
-DefaultIntrinsicLowering IL;
+IntrinsicLowering IL;
Mangler *Mang;
LoopInfo *LI;
const Module *TheModule;
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[llvm-commits] CVS: llvm/lib/VMCore/PassManager.cpp
Changes in directory llvm/lib/VMCore:
PassManager.cpp updated: 1.31 - 1.32
---
Log message:
Add run(Function F) support in FunctionPassManager_New
---
Diffs of the changes: (+41 -6)
PassManager.cpp | 47 +--
1 files changed, 41 insertions(+), 6 deletions(-)
Index: llvm/lib/VMCore/PassManager.cpp
diff -u llvm/lib/VMCore/PassManager.cpp:1.31
llvm/lib/VMCore/PassManager.cpp:1.32
--- llvm/lib/VMCore/PassManager.cpp:1.31Tue Nov 14 19:48:14 2006
+++ llvm/lib/VMCore/PassManager.cpp Wed Nov 15 13:39:54 2006
@@ -17,6 +17,7 @@
#include llvm/ModuleProvider.h
#include vector
#include map
+#include iostream
using namespace llvm;
@@ -158,6 +159,7 @@
/// track of whether any of the passes modifies the function, and if
/// so, return true.
bool runOnModule(Module M);
+ bool runOnFunction(Function F);
/// Return true IFF AnalysisID AID is currently available.
Pass *getAnalysisPassFromManager(AnalysisID AID);
@@ -423,19 +425,31 @@
/// PassManager_X is destroyed, the pass will be destroyed as well, so
/// there is no need to delete the pass. (TODO delete passes.)
/// This implies that all passes MUST be allocated with 'new'.
-void
-FunctionPassManager_New::add(Pass *P) {
+void FunctionPassManager_New::add(Pass *P) {
FPM-add(P);
}
/// Execute all of the passes scheduled for execution. Keep
/// track of whether any of the passes modifies the function, and if
/// so, return true.
-bool
-FunctionPassManager_New::runOnModule(Module M) {
+bool FunctionPassManager_New::runOnModule(Module M) {
return FPM-runOnModule(M);
}
+/// run - Execute all of the passes scheduled for execution. Keep
+/// track of whether any of the passes modifies the function, and if
+/// so, return true.
+///
+bool FunctionPassManager_New::run(Function F) {
+ std::string errstr;
+ if (MP-materializeFunction(F, errstr)) {
+std::cerr Error reading bytecode file: errstr \n;
+abort();
+ }
+ return FPM-runOnFunction(F);
+}
+
+
/// doInitialization - Run all of the initializers for the function passes.
///
bool FunctionPassManager_New::doInitialization() {
@@ -489,8 +503,7 @@
/// Execute all of the passes scheduled for execution by invoking
/// runOnFunction method. Keep track of whether any of the passes modifies
/// the function, and if so, return true.
-bool
-FunctionPassManagerImpl_New::runOnModule(Module M) {
+bool FunctionPassManagerImpl_New::runOnModule(Module M) {
bool Changed = false;
clearAnalysis();
@@ -509,6 +522,28 @@
return Changed;
}
+/// Execute all of the passes scheduled for execution by invoking
+/// runOnFunction method. Keep track of whether any of the passes modifies
+/// the function, and if so, return true.
+bool FunctionPassManagerImpl_New::runOnFunction(Function F) {
+
+ bool Changed = false;
+ clearAnalysis();
+
+ for (std::vectorPass *::iterator itr = passVectorBegin(),
+ e = passVectorEnd(); itr != e; ++itr) {
+Pass *P = *itr;
+
+noteDownAvailableAnalysis(P);
+FunctionPass *FP = dynamic_castFunctionPass*(P);
+Changed |= FP-runOnFunction(F);
+removeNotPreservedAnalysis(P);
+removeDeadPasses(P);
+ }
+ return Changed;
+}
+
+
/// Return true IFF AnalysisID AID is currently available.
Pass *FunctionPassManagerImpl_New::getAnalysisPassFromManager(AnalysisID AID) {
___
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[llvm-commits] CVS: llvm/include/llvm/PassManager.h
Changes in directory llvm/include/llvm: PassManager.h updated: 1.31 - 1.32 --- Log message: Add run(Function F) support in FunctionPassManager_New --- Diffs of the changes: (+6 -0) PassManager.h |6 ++ 1 files changed, 6 insertions(+) Index: llvm/include/llvm/PassManager.h diff -u llvm/include/llvm/PassManager.h:1.31 llvm/include/llvm/PassManager.h:1.32 --- llvm/include/llvm/PassManager.h:1.31Tue Nov 14 20:07:25 2006 +++ llvm/include/llvm/PassManager.h Wed Nov 15 13:39:54 2006 @@ -135,6 +135,12 @@ /// so, return true. bool runOnModule(Module M); + /// run - Execute all of the passes scheduled for execution. Keep + /// track of whether any of the passes modifies the function, and if + /// so, return true. + /// + bool run(Function F); + /// doInitialization - Run all of the initializers for the function passes. /// bool doInitialization(); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstr64Bit.td PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.219 - 1.220
PPCISelLowering.cpp updated: 1.226 - 1.227
PPCInstr64Bit.td updated: 1.27 - 1.28
PPCInstrInfo.td updated: 1.260 - 1.261
---
Log message:
fix ldu/stu jit encoding. Swith 64-bit preinc load instrs to use memri
addrmodes.
---
Diffs of the changes: (+58 -52)
PPCISelDAGToDAG.cpp | 55 ++--
PPCISelLowering.cpp | 25 ---
PPCInstr64Bit.td| 28 +++---
PPCInstrInfo.td |2 -
4 files changed, 58 insertions(+), 52 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.219
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.220
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.219 Tue Nov 14 12:43:11 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Wed Nov 15 13:55:13 2006
@@ -828,36 +828,37 @@
if (LD-getAddressingMode() != ISD::PRE_INC)
break;
-unsigned Opcode;
-bool isSExt = LD-getExtensionType() == ISD::SEXTLOAD;
-if (LD-getValueType(0) != MVT::i64) {
- // Handle PPC32 integer and normal FP loads.
- assert(!isSExt || LoadedVT == MVT::i16 Invalid sext update load);
- switch (LoadedVT) {
- default: assert(0 Invalid PPC load type!);
- case MVT::f64: Opcode = PPC::LFDU; break;
- case MVT::f32: Opcode = PPC::LFSU; break;
- case MVT::i32: Opcode = PPC::LWZU; break;
- case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
- case MVT::i1:
- case MVT::i8: Opcode = PPC::LBZU; break;
- }
-} else {
- assert(LD-getValueType(0) == MVT::i64 Unknown load result type!);
- assert(!isSExt || LoadedVT == MVT::i16 Invalid sext update load);
- switch (LoadedVT) {
- default: assert(0 Invalid PPC load type!);
- case MVT::i64: Opcode = PPC::LDU; break;
- case MVT::i32: Opcode = PPC::LWZU8; break;
- case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
- case MVT::i1:
- case MVT::i8: Opcode = PPC::LBZU8; break;
- }
-}
-
SDOperand Offset = LD-getOffset();
if (isaConstantSDNode(Offset) ||
Offset.getOpcode() == ISD::TargetGlobalAddress) {
+
+ unsigned Opcode;
+ bool isSExt = LD-getExtensionType() == ISD::SEXTLOAD;
+ if (LD-getValueType(0) != MVT::i64) {
+// Handle PPC32 integer and normal FP loads.
+assert(!isSExt || LoadedVT == MVT::i16 Invalid sext update load);
+switch (LoadedVT) {
+ default: assert(0 Invalid PPC load type!);
+ case MVT::f64: Opcode = PPC::LFDU; break;
+ case MVT::f32: Opcode = PPC::LFSU; break;
+ case MVT::i32: Opcode = PPC::LWZU; break;
+ case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
+ case MVT::i1:
+ case MVT::i8: Opcode = PPC::LBZU; break;
+}
+ } else {
+assert(LD-getValueType(0) == MVT::i64 Unknown load result type!);
+assert(!isSExt || LoadedVT == MVT::i16 Invalid sext update load);
+switch (LoadedVT) {
+ default: assert(0 Invalid PPC load type!);
+ case MVT::i64: Opcode = PPC::LDU; break;
+ case MVT::i32: Opcode = PPC::LWZU8; break;
+ case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
+ case MVT::i1:
+ case MVT::i8: Opcode = PPC::LBZU8; break;
+}
+ }
+
SDOperand Chain = LD-getChain();
SDOperand Base = LD-getBasePtr();
AddToISelQueue(Chain);
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.226
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.227
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.226 Mon Nov 13 23:28:08 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed Nov 15 13:55:13 2006
@@ -877,12 +877,12 @@
MVT::ValueType VT;
if (LoadSDNode *LD = dyn_castLoadSDNode(N)) {
Ptr = LD-getBasePtr();
-VT = LD-getValueType(0);
+VT = LD-getLoadedVT();
+
} else if (StoreSDNode *ST = dyn_castStoreSDNode(N)) {
ST = ST;
Ptr = ST-getBasePtr();
VT = ST-getStoredVT();
-return false; // TODO: Stores.
} else
return false;
@@ -890,18 +890,27 @@
if (MVT::isVector(VT))
return false;
- // TODO: Handle reg+reg.
- if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
-return false;
+ // TODO: Check reg+reg first.
+
+ // LDU/STU use reg+imm*4, others use reg+imm.
+ if (VT != MVT::i64) {
+// reg + imm
+if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
+ return false;
+ } else {
+// reg + imm * 4.
+if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
+ return false;
+ }
- // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
- // sext i32 to i64 when addr mode is r+i.
if (LoadSDNode *LD = dyn_castLoadSDNode(N)) {
+//
[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h
Changes in directory llvm/include/llvm/CodeGen:
MachineInstr.h updated: 1.196 - 1.197
---
Log message:
Add copyKillDeadInfo to copy kill / dead info; other minor updates.
---
Diffs of the changes: (+28 -8)
MachineInstr.h | 36
1 files changed, 28 insertions(+), 8 deletions(-)
Index: llvm/include/llvm/CodeGen/MachineInstr.h
diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.196
llvm/include/llvm/CodeGen/MachineInstr.h:1.197
--- llvm/include/llvm/CodeGen/MachineInstr.h:1.196 Mon Nov 13 17:30:45 2006
+++ llvm/include/llvm/CodeGen/MachineInstr.hWed Nov 15 14:48:17 2006
@@ -206,19 +206,19 @@
return IsDead;
}
void setIsKill() {
-assert(isRegister() Wrong MachineOperand accessor);
+assert(isRegister() !IsDef Wrong MachineOperand accessor);
IsKill = true;
}
void setIsDead() {
-assert(isRegister() Wrong MachineOperand accessor);
+assert(isRegister() IsDef Wrong MachineOperand accessor);
IsDead = true;
}
void unsetIsKill() {
-assert(isRegister() Wrong MachineOperand accessor);
+assert(isRegister() !IsDef Wrong MachineOperand accessor);
IsKill = false;
}
void unsetIsDead() {
-assert(isRegister() Wrong MachineOperand accessor);
+assert(isRegister() IsDef Wrong MachineOperand accessor);
IsDead = false;
}
@@ -261,7 +261,7 @@
}
/// isIdenticalTo - Return true if this operand is identical to the specified
- /// operand.
+ /// operand. Note: This method ignores isKill and isDead properties.
bool isIdenticalTo(const MachineOperand Other) const;
/// ChangeToImmediate - Replace this operand with a new immediate operand of
@@ -295,13 +295,13 @@
///
class MachineInstr {
short Opcode; // the opcode
+ short NumImplicitOps; // Number of implicit operands (which
+// are determined at construction
time).
+
std::vectorMachineOperand Operands; // the operands
MachineInstr* prev, *next;// links for our intrusive list
MachineBasicBlock* parent;// pointer to the owning basic block
- unsigned NumImplicitOps; // Number of implicit operands (which
-// are determined at construction
time).
-
// OperandComplete - Return true if it's illegal to add a new operand
bool OperandsComplete() const;
@@ -376,6 +376,26 @@
delete removeFromParent();
}
+ /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
+ ///
+ void copyKillDeadInfo(const MachineInstr *MI) {
+for (unsigned i = 0, e = MI-getNumOperands(); i != e; ++i) {
+ const MachineOperand MO = MI-getOperand(i);
+ if (MO.isReg() (MO.isKill() || MO.isDead())) {
+for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
+ MachineOperand MOp = getOperand(j);
+ if (MOp.isIdenticalTo(MO)) {
+if (MO.isKill())
+ MOp.setIsKill();
+else
+ MOp.setIsDead();
+break;
+ }
+}
+ }
+}
+ }
+
//
// Debugging support
//
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/LiveVariables.h
Changes in directory llvm/include/llvm/CodeGen:
LiveVariables.h updated: 1.30 - 1.31
---
Log message:
Do away with kill / dead maps. Move kill / dead info onto MI's.
---
Diffs of the changes: (+36 -95)
LiveVariables.h | 131 +++-
1 files changed, 36 insertions(+), 95 deletions(-)
Index: llvm/include/llvm/CodeGen/LiveVariables.h
diff -u llvm/include/llvm/CodeGen/LiveVariables.h:1.30
llvm/include/llvm/CodeGen/LiveVariables.h:1.31
--- llvm/include/llvm/CodeGen/LiveVariables.h:1.30 Tue Oct 3 02:20:20 2006
+++ llvm/include/llvm/CodeGen/LiveVariables.h Wed Nov 15 14:47:31 2006
@@ -107,23 +107,6 @@
///
std::vectorVarInfo VirtRegInfo;
- /// RegistersKilled - This map keeps track of all of the registers that
- /// are dead immediately after an instruction reads its operands. If an
- /// instruction does not have an entry in this map, it kills no registers.
- ///
- std::mapMachineInstr*, std::vectorunsigned RegistersKilled;
-
- /// RegistersDead - This map keeps track of all of the registers that are
- /// dead immediately after an instruction executes, which are not dead after
- /// the operands are evaluated. In practice, this only contains registers
- /// which are defined by an instruction, but never used.
- ///
- std::mapMachineInstr*, std::vectorunsigned RegistersDead;
-
- /// Dummy - An always empty vector used for instructions without dead or
- /// killed operands.
- std::vectorunsigned Dummy;
-
/// AllocatablePhysicalRegisters - This vector keeps track of which registers
/// are actually register allocatable by the target machine. We can not
track
/// liveness for values that are not in this set.
@@ -141,6 +124,15 @@
PHIVarInfoMap PHIVarInfo;
+
+ /// addRegisterKilled - We have determined MI kills a register. Look for the
+ /// operand that uses it and mark it as IsKill.
+ void addRegisterKilled(unsigned IncomingReg, MachineInstr *MI);
+
+ /// addRegisterDead - We have determined MI defined a register without a use.
+ /// Look for the operand that defines it and mark it as IsDead.
+ void addRegisterDead(unsigned IncomingReg, MachineInstr *MI);
+
void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
void HandlePhysRegDef(unsigned Reg, MachineInstr *MI);
@@ -153,55 +145,17 @@
virtual bool runOnMachineFunction(MachineFunction MF);
- /// killed_iterator - Iterate over registers killed by a machine instruction
- ///
- typedef std::vectorunsigned::iterator killed_iterator;
-
- std::vectorunsigned getKillsVector(MachineInstr *MI) {
-std::mapMachineInstr*, std::vectorunsigned ::iterator I =
- RegistersKilled.find(MI);
-return I != RegistersKilled.end() ? I-second : Dummy;
- }
- std::vectorunsigned getDeadDefsVector(MachineInstr *MI) {
-std::mapMachineInstr*, std::vectorunsigned ::iterator I =
- RegistersDead.find(MI);
-return I != RegistersDead.end() ? I-second : Dummy;
- }
-
-
- /// killed_begin/end - Get access to the range of registers killed by a
- /// machine instruction.
- killed_iterator killed_begin(MachineInstr *MI) {
-return getKillsVector(MI).begin();
- }
- killed_iterator killed_end(MachineInstr *MI) {
-return getKillsVector(MI).end();
- }
- std::pairkilled_iterator, killed_iterator
- killed_range(MachineInstr *MI) {
-std::vectorunsigned V = getKillsVector(MI);
-return std::make_pair(V.begin(), V.end());
- }
-
/// KillsRegister - Return true if the specified instruction kills the
/// specified register.
bool KillsRegister(MachineInstr *MI, unsigned Reg) const;
- killed_iterator dead_begin(MachineInstr *MI) {
-return getDeadDefsVector(MI).begin();
- }
- killed_iterator dead_end(MachineInstr *MI) {
-return getDeadDefsVector(MI).end();
- }
- std::pairkilled_iterator, killed_iterator
- dead_range(MachineInstr *MI) {
-std::vectorunsigned V = getDeadDefsVector(MI);
-return std::make_pair(V.begin(), V.end());
- }
-
/// RegisterDefIsDead - Return true if the specified instruction defines the
/// specified register, but that definition is dead.
bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
+
+ /// ModifiesRegister - Return true if the specified instruction modifies the
+ /// specified register.
+ bool ModifiesRegister(MachineInstr *MI, unsigned Reg) const;
//======//
// API to update live variable information
@@ -217,19 +171,9 @@
/// instruction.
///
void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI) {
-std::vectorunsigned V = RegistersKilled[MI];
-// Insert in a sorted order.
-if (V.empty() || IncomingReg V.back()) {
- V.push_back(IncomingReg);
-} else {
- std::vectorunsigned::iterator I = V.begin();
- for (; *I IncomingReg; ++I)
-/*empty*/;
- if (*I != IncomingReg) // Don't insert
[llvm-commits] CVS: llvm/lib/CodeGen/RegAllocLocal.cpp
Changes in directory llvm/lib/CodeGen:
RegAllocLocal.cpp updated: 1.94 - 1.95
---
Log message:
Match live variable changes.
---
Diffs of the changes: (+56 -10)
RegAllocLocal.cpp | 66 +-
1 files changed, 56 insertions(+), 10 deletions(-)
Index: llvm/lib/CodeGen/RegAllocLocal.cpp
diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.94
llvm/lib/CodeGen/RegAllocLocal.cpp:1.95
--- llvm/lib/CodeGen/RegAllocLocal.cpp:1.94 Fri Nov 10 02:38:19 2006
+++ llvm/lib/CodeGen/RegAllocLocal.cpp Wed Nov 15 14:55:15 2006
@@ -13,6 +13,7 @@
//===--===//
#define DEBUG_TYPE regalloc
+#include llvm/BasicBlock.h
#include llvm/CodeGen/Passes.h
#include llvm/CodeGen/MachineFunctionPass.h
#include llvm/CodeGen/MachineInstr.h
@@ -26,6 +27,7 @@
#include llvm/Support/Debug.h
#include llvm/Support/Compiler.h
#include llvm/ADT/DenseMap.h
+#include llvm/ADT/SmallVector.h
#include llvm/ADT/Statistic.h
#include algorithm
#include iostream
@@ -309,7 +311,18 @@
*AliasSet; ++AliasSet)
if (PhysRegsUsed[*AliasSet] != -1 // Spill aliased register.
PhysRegsUsed[*AliasSet] != -2) // If allocatable.
-if (PhysRegsUsed[*AliasSet] || !OnlyVirtRegs)
+if (PhysRegsUsed[*AliasSet] == 0) {
+ // This must have been a dead def due to something like this:
+ // %EAX :=
+ // := op %AL
+ // No more use of %EAX, %AH, etc.
+ // %EAX isn't dead upon definition, but %AH is. However %AH isn't
+ // an operand of definition MI so it's not marked as such.
+ DEBUG(std::cerrRegister RegInfo-getName(*AliasSet)
+ [%reg *AliasSet
+ ] is never used, removing it frame live list\n);
+ removePhysReg(*AliasSet);
+} else
spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
}
}
@@ -512,6 +525,9 @@
MachineBasicBlock::iterator MII = MBB.begin();
const TargetInstrInfo TII = *TM-getInstrInfo();
+ DEBUG(const BasicBlock *LBB = MBB.getBasicBlock();
+if (LBB) std::cerr \nStarting RegAlloc of BB: LBB-getName());
+
// If this is the first basic block in the machine function, add live-in
// registers as active.
if (MBB == *MF-begin()) {
@@ -552,6 +568,13 @@
MarkPhysRegRecentlyUsed(*ImplicitUses);
}
+SmallVectorunsigned, 8 Kills;
+for (unsigned i = 0, e = MI-getNumOperands(); i != e; ++i) {
+ MachineOperand MO = MI-getOperand(i);
+ if (MO.isRegister() MO.isKill())
+Kills.push_back(MO.getReg());
+}
+
// Get the used operands into registers. This has the potential to spill
// incoming values if we are out of registers. Note that we completely
// ignore physical register uses here. We assume that if an explicit
@@ -561,18 +584,17 @@
for (unsigned i = 0; i != MI-getNumOperands(); ++i) {
MachineOperand MO = MI-getOperand(i);
// here we are looking for only used operands (never defuse)
- if (MO.isRegister() !MO.isDef() !MO.isImplicit() MO.getReg()
+ if (MO.isRegister() !MO.isDef() MO.getReg() !MO.isImplicit()
MRegisterInfo::isVirtualRegister(MO.getReg()))
MI = reloadVirtReg(MBB, MI, i);
}
-// If this instruction is the last user of anything in registers, kill the
+// If this instruction is the last user of this register, kill the
// value, freeing the register being used, so it doesn't need to be
// spilled to memory.
//
-for (LiveVariables::killed_iterator KI = LV-killed_begin(MI),
- KE = LV-killed_end(MI); KI != KE; ++KI) {
- unsigned VirtReg = *KI;
+for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
+ unsigned VirtReg = Kills[i];
unsigned PhysReg = VirtReg;
if (MRegisterInfo::isVirtualRegister(VirtReg)) {
// If the virtual register was never materialized into a register, it
@@ -589,6 +611,15 @@
DEBUG(std::cerrLast use of RegInfo-getName(PhysReg)
[%reg VirtReg ], removing it from live set\n);
removePhysReg(PhysReg);
+for (const unsigned *AliasSet = RegInfo-getAliasSet(PhysReg);
+ *AliasSet; ++AliasSet) {
+ if (PhysRegsUsed[*AliasSet] != -2) {
+DEBUG(std::cerrLast use of
+ RegInfo-getName(*AliasSet)
+ [%reg VirtReg ], removing it from live set\n);
+removePhysReg(*AliasSet);
+ }
+}
}
}
@@ -602,7 +633,7 @@
if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
PhysRegsEverUsed[Reg] = true;
-spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in the
reg
+spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
PhysRegsUsed[Reg] = 0;// It is free and reserved now
[llvm-commits] CVS: llvm/lib/CodeGen/MachineInstr.cpp
Changes in directory llvm/lib/CodeGen:
MachineInstr.cpp updated: 1.130 - 1.131
---
Log message:
Minor updates.
---
Diffs of the changes: (+4 -4)
MachineInstr.cpp |8
1 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/MachineInstr.cpp
diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.130
llvm/lib/CodeGen/MachineInstr.cpp:1.131
--- llvm/lib/CodeGen/MachineInstr.cpp:1.130 Mon Nov 13 17:34:06 2006
+++ llvm/lib/CodeGen/MachineInstr.cpp Wed Nov 15 14:54:29 2006
@@ -38,7 +38,7 @@
/// Eventually, the resizing ctors will be phased out.
///
MachineInstr::MachineInstr(short opcode, unsigned numOperands)
- : Opcode(opcode), parent(0), NumImplicitOps(0) {
+ : Opcode(opcode), NumImplicitOps(0), parent(0) {
Operands.reserve(numOperands);
// Make sure that we get added to a machine basicblock
LeakDetector::addGarbageObject(this);
@@ -75,7 +75,7 @@
/// implicit operands. It reserves space for numOperand operands.
MachineInstr::MachineInstr(const TargetInstrInfo TII, short opcode,
unsigned numOperands)
- : Opcode(opcode), parent(0), NumImplicitOps(0) {
+ : Opcode(opcode), NumImplicitOps(0), parent(0) {
const TargetInstrDescriptor TID = TII.get(opcode);
if (TID.ImplicitDefs)
for (const unsigned *ImpDefs = TID.ImplicitDefs; *ImpDefs; ++ImpDefs)
@@ -94,7 +94,7 @@
///
MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
unsigned numOperands)
- : Opcode(opcode), parent(0), NumImplicitOps(0) {
+ : Opcode(opcode), NumImplicitOps(0), parent(0) {
assert(MBB Cannot use inserting ctor with null basic block!);
const TargetInstrDescriptor TID = MBB-getParent()-getTarget().
getInstrInfo()-get(opcode);
@@ -115,9 +115,9 @@
///
MachineInstr::MachineInstr(const MachineInstr MI) {
Opcode = MI.getOpcode();
+ NumImplicitOps = MI.NumImplicitOps;
Operands.reserve(MI.getNumOperands());
- NumImplicitOps = MI.NumImplicitOps;
// Add operands
for (unsigned i = 0; i != MI.getNumOperands(); ++i)
Operands.push_back(MI.getOperand(i));
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.cpp updated: 1.30 - 1.31
PPCRegisterInfo.cpp updated: 1.83 - 1.84
---
Log message:
Properly transfer kill / dead info.
---
Diffs of the changes: (+27 -13)
PPCInstrInfo.cpp| 10 ++
PPCRegisterInfo.cpp | 30 +-
2 files changed, 27 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.30
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.31
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.30 Mon Nov 13 17:36:35 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cppWed Nov 15 14:58:11 2006
@@ -147,8 +147,18 @@
// Swap op1/op2
unsigned Reg1 = MI-getOperand(1).getReg();
unsigned Reg2 = MI-getOperand(2).getReg();
+ bool Reg1IsKill = MI-getOperand(1).isKill();
+ bool Reg2IsKill = MI-getOperand(2).isKill();
MI-getOperand(2).setReg(Reg1);
MI-getOperand(1).setReg(Reg2);
+ if (Reg1IsKill)
+MI-getOperand(2).setIsKill();
+ else
+MI-getOperand(2).unsetIsKill();
+ if (Reg2IsKill)
+MI-getOperand(1).setIsKill();
+ else
+MI-getOperand(1).unsetIsKill();
// Swap the mask around.
unsigned MB = MI-getOperand(4).getImmedValue();
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.83
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.84
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.83Wed Nov 15 11:40:51 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Wed Nov 15 14:58:11 2006
@@ -337,47 +337,51 @@
// Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
// it takes more than one instruction to store it.
unsigned Opc = MI-getOpcode();
-
+
+ MachineInstr *NewMI = NULL;
if ((Opc == PPC::OR
MI-getOperand(1).getReg() == MI-getOperand(2).getReg())) {
if (OpNum == 0) { // move - store
unsigned InReg = MI-getOperand(1).getReg();
- return addFrameReference(BuildMI(TII, PPC::STW,
- 3).addReg(InReg), FrameIndex);
+ NewMI = addFrameReference(BuildMI(TII, PPC::STW,
+3).addReg(InReg), FrameIndex);
} else { // move - load
unsigned OutReg = MI-getOperand(0).getReg();
- return addFrameReference(BuildMI(TII, PPC::LWZ, 2, OutReg), FrameIndex);
+ NewMI = addFrameReference(BuildMI(TII, PPC::LWZ, 2, OutReg), FrameIndex);
}
} else if ((Opc == PPC::OR8
MI-getOperand(1).getReg() == MI-getOperand(2).getReg())) {
if (OpNum == 0) { // move - store
unsigned InReg = MI-getOperand(1).getReg();
- return addFrameReference(BuildMI(TII, PPC::STD,
- 3).addReg(InReg), FrameIndex);
+ NewMI = addFrameReference(BuildMI(TII, PPC::STD,
+3).addReg(InReg), FrameIndex);
} else { // move - load
unsigned OutReg = MI-getOperand(0).getReg();
- return addFrameReference(BuildMI(TII, PPC::LD, 2, OutReg), FrameIndex);
+ NewMI = addFrameReference(BuildMI(TII, PPC::LD, 2, OutReg), FrameIndex);
}
} else if (Opc == PPC::FMRD) {
if (OpNum == 0) { // move - store
unsigned InReg = MI-getOperand(1).getReg();
- return addFrameReference(BuildMI(TII, PPC::STFD,
- 3).addReg(InReg), FrameIndex);
+ NewMI = addFrameReference(BuildMI(TII, PPC::STFD,
+3).addReg(InReg), FrameIndex);
} else { // move - load
unsigned OutReg = MI-getOperand(0).getReg();
- return addFrameReference(BuildMI(TII, PPC::LFD, 2, OutReg), FrameIndex);
+ NewMI = addFrameReference(BuildMI(TII, PPC::LFD, 2, OutReg), FrameIndex);
}
} else if (Opc == PPC::FMRS) {
if (OpNum == 0) { // move - store
unsigned InReg = MI-getOperand(1).getReg();
- return addFrameReference(BuildMI(TII, PPC::STFS,
+ NewMI = addFrameReference(BuildMI(TII, PPC::STFS,
3).addReg(InReg), FrameIndex);
} else { // move - load
unsigned OutReg = MI-getOperand(0).getReg();
- return addFrameReference(BuildMI(TII, PPC::LFS, 2, OutReg), FrameIndex);
+ NewMI = addFrameReference(BuildMI(TII, PPC::LFS, 2, OutReg), FrameIndex);
}
}
- return 0;
+
+ if (NewMI)
+NewMI-copyKillDeadInfo(MI);
+ return NewMI;
}
//===--===//
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[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
Changes in directory llvm/lib/Target/Alpha:
AlphaRegisterInfo.cpp updated: 1.51 - 1.52
---
Log message:
Properly transfer kill / dead info.
---
Diffs of the changes: (+5 -2)
AlphaRegisterInfo.cpp |7 +--
1 files changed, 5 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.51
llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.52
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.51Mon Nov 13 17:36:35 2006
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Wed Nov 15 14:58:11 2006
@@ -104,6 +104,7 @@
// Make sure this is a reg-reg copy.
unsigned Opc = MI-getOpcode();
+ MachineInstr *NewMI = NULL;
switch(Opc) {
default:
break;
@@ -115,18 +116,20 @@
unsigned InReg = MI-getOperand(1).getReg();
Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
-return BuildMI(TII, Opc, 3).addReg(InReg).addFrameIndex(FrameIndex)
+NewMI = BuildMI(TII, Opc, 3).addReg(InReg).addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
} else { // load - move
unsigned OutReg = MI-getOperand(0).getReg();
Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
-return BuildMI(TII, Opc, 2, OutReg).addFrameIndex(FrameIndex)
+NewMI = BuildMI(TII, Opc, 2, OutReg).addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
}
}
break;
}
+ if (NewMI)
+NewMI-copyKillDeadInfo(MI);
return 0;
}
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[llvm-commits] CVS: llvm/lib/Target/TargetInstrInfo.cpp
Changes in directory llvm/lib/Target: TargetInstrInfo.cpp updated: 1.21 - 1.22 --- Log message: commuteInstruction should propagate kill / dead info. --- Diffs of the changes: (+10 -0) TargetInstrInfo.cpp | 10 ++ 1 files changed, 10 insertions(+) Index: llvm/lib/Target/TargetInstrInfo.cpp diff -u llvm/lib/Target/TargetInstrInfo.cpp:1.21 llvm/lib/Target/TargetInstrInfo.cpp:1.22 --- llvm/lib/Target/TargetInstrInfo.cpp:1.21Wed Nov 1 17:14:15 2006 +++ llvm/lib/Target/TargetInstrInfo.cpp Wed Nov 15 14:56:03 2006 @@ -60,7 +60,17 @@ This only knows how to commute register operands so far); unsigned Reg1 = MI-getOperand(1).getReg(); unsigned Reg2 = MI-getOperand(2).getReg(); + bool Reg1IsKill = MI-getOperand(1).isKill(); + bool Reg2IsKill = MI-getOperand(2).isKill(); MI-getOperand(2).setReg(Reg1); MI-getOperand(1).setReg(Reg2); + if (Reg1IsKill) +MI-getOperand(2).setIsKill(); + else +MI-getOperand(2).unsetIsKill(); + if (Reg2IsKill) +MI-getOperand(1).setIsKill(); + else +MI-getOperand(1).unsetIsKill(); return MI; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
Changes in directory llvm/lib/Target/Sparc:
SparcRegisterInfo.cpp updated: 1.46 - 1.47
---
Log message:
Properly transfer kill / dead info.
---
Diffs of the changes: (+9 -5)
SparcRegisterInfo.cpp | 14 +-
1 files changed, 9 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.46
llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.47
--- llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.46Mon Nov 13 17:36:35 2006
+++ llvm/lib/Target/Sparc/SparcRegisterInfo.cpp Wed Nov 15 14:58:11 2006
@@ -77,15 +77,16 @@
unsigned OpNum,
int FI) const {
bool isFloat = false;
+ MachineInstr *NewMI = NULL;
switch (MI-getOpcode()) {
case SP::ORrr:
if (MI-getOperand(1).isRegister() MI-getOperand(1).getReg() ==
SP::G0
MI-getOperand(0).isRegister() MI-getOperand(2).isRegister()) {
if (OpNum == 0)// COPY - STORE
-return BuildMI(TII, SP::STri, 3).addFrameIndex(FI).addImm(0)
+NewMI = BuildMI(TII, SP::STri, 3).addFrameIndex(FI).addImm(0)
.addReg(MI-getOperand(2).getReg());
else // COPY - LOAD
-return BuildMI(TII, SP::LDri, 2, MI-getOperand(0).getReg())
+NewMI = BuildMI(TII, SP::LDri, 2, MI-getOperand(0).getReg())
.addFrameIndex(FI).addImm(0);
}
break;
@@ -94,14 +95,17 @@
// FALLTHROUGH
case SP::FMOVD:
if (OpNum == 0) // COPY - STORE
- return BuildMI(TII, isFloat ? SP::STFri : SP::STDFri, 3)
+ NewMI = BuildMI(TII, isFloat ? SP::STFri : SP::STDFri, 3)
.addFrameIndex(FI).addImm(0).addReg(MI-getOperand(1).getReg());
else // COPY - LOAD
- return BuildMI(TII, isFloat ? SP::LDFri : SP::LDDFri, 2,
+ NewMI = BuildMI(TII, isFloat ? SP::LDFri : SP::LDDFri, 2,
MI-getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
break;
}
- return 0;
+
+ if (NewMI)
+NewMI-copyKillDeadInfo(MI);
+ return NewMI;
}
const unsigned* SparcRegisterInfo::getCalleeSaveRegs() const {
___
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[llvm-commits] CVS: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
Changes in directory llvm/lib/CodeGen:
LiveIntervalAnalysis.cpp updated: 1.194 - 1.195
---
Log message:
A register def can be partially dead when the whole register has use(s) but a
subreg does not.
---
Diffs of the changes: (+8 -1)
LiveIntervalAnalysis.cpp |9 -
1 files changed, 8 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
diff -u llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.194
llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.195
--- llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.194 Fri Nov 10 02:38:19 2006
+++ llvm/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Nov 15 14:54:11 2006
@@ -575,7 +575,6 @@
// A physical register cannot be live across basic block, so its
// lifetime must end somewhere in its defining basic block.
DEBUG(std::cerr \t\tregister: ; printRegName(interval.reg));
- typedef LiveVariables::killed_iterator KillIter;
unsigned baseIndex = MIIdx;
unsigned start = getDefIndex(baseIndex);
@@ -599,6 +598,14 @@
DEBUG(std::cerr killed);
end = getUseIndex(baseIndex) + 1;
goto exit;
+} else if (lv_-ModifiesRegister(mi, interval.reg)) {
+ // Another instruction redefines the register before it is ever read.
+ // Then the register is essentially dead at the instruction that defines
+ // it. Hence its interval is:
+ // [defSlot(def), defSlot(def)+1)
+ DEBUG(std::cerr dead);
+ end = getDefIndex(start) + 1;
+ goto exit;
}
}
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[llvm-commits] CVS: llvm/lib/CodeGen/LiveVariables.cpp
Changes in directory llvm/lib/CodeGen:
LiveVariables.cpp updated: 1.62 - 1.63
---
Log message:
Do away with kill / dead maps. Move kill / dead info onto MI's.
---
Diffs of the changes: (+107 -81)
LiveVariables.cpp | 188 ++
1 files changed, 107 insertions(+), 81 deletions(-)
Index: llvm/lib/CodeGen/LiveVariables.cpp
diff -u llvm/lib/CodeGen/LiveVariables.cpp:1.62
llvm/lib/CodeGen/LiveVariables.cpp:1.63
--- llvm/lib/CodeGen/LiveVariables.cpp:1.62 Fri Nov 10 02:38:19 2006
+++ llvm/lib/CodeGen/LiveVariables.cpp Wed Nov 15 14:51:59 2006
@@ -72,24 +72,56 @@
return VirtRegInfo[RegIdx];
}
+/// registerOverlap - Returns true if register 1 is equal to register 2
+/// or if register 1 is equal to any of alias of register 2.
+static bool registerOverlap(unsigned Reg1, unsigned Reg2,
+ const MRegisterInfo *RegInfo) {
+ bool isVirt1 = MRegisterInfo::isVirtualRegister(Reg1);
+ bool isVirt2 = MRegisterInfo::isVirtualRegister(Reg2);
+ if (isVirt1 != isVirt2)
+return false;
+ if (Reg1 == Reg2)
+return true;
+ else if (isVirt1)
+return false;
+ for (const unsigned *AliasSet = RegInfo-getAliasSet(Reg2);
+ unsigned Alias = *AliasSet; ++AliasSet) {
+if (Reg1 == Alias)
+ return true;
+ }
+ return false;
+}
+
bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
- std::mapMachineInstr*, std::vectorunsigned ::const_iterator I =
- RegistersKilled.find(MI);
- if (I == RegistersKilled.end()) return false;
-
- // Do a binary search, as these lists can grow pretty big, particularly for
- // call instructions on targets with lots of call-clobbered registers.
- return std::binary_search(I-second.begin(), I-second.end(), Reg);
+ for (unsigned i = 0, e = MI-getNumOperands(); i != e; ++i) {
+MachineOperand MO = MI-getOperand(i);
+if (MO.isReg() MO.isKill()) {
+ if (registerOverlap(Reg, MO.getReg(), RegInfo))
+return true;
+}
+ }
+ return false;
}
bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
- std::mapMachineInstr*, std::vectorunsigned ::const_iterator I =
- RegistersDead.find(MI);
- if (I == RegistersDead.end()) return false;
-
- // Do a binary search, as these lists can grow pretty big, particularly for
- // call instructions on targets with lots of call-clobbered registers.
- return std::binary_search(I-second.begin(), I-second.end(), Reg);
+ for (unsigned i = 0, e = MI-getNumOperands(); i != e; ++i) {
+MachineOperand MO = MI-getOperand(i);
+if (MO.isReg() MO.isDead())
+ if (registerOverlap(Reg, MO.getReg(), RegInfo))
+return true;
+ }
+ return false;
+}
+
+bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
+ for (unsigned i = 0, e = MI-getNumOperands(); i != e; ++i) {
+MachineOperand MO = MI-getOperand(i);
+if (MO.isReg() MO.isDef()) {
+ if (registerOverlap(Reg, MO.getReg(), RegInfo))
+return true;
+}
+ }
+ return false;
}
void LiveVariables::MarkVirtRegAliveInBlock(VarInfo VRInfo,
@@ -149,6 +181,26 @@
MarkVirtRegAliveInBlock(VRInfo, *PI);
}
+void LiveVariables::addRegisterKilled(unsigned IncomingReg, MachineInstr *MI) {
+ for (unsigned i = 0, e = MI-getNumOperands(); i != e; ++i) {
+MachineOperand MO = MI-getOperand(i);
+if (MO.isReg() MO.isUse() MO.getReg() == IncomingReg) {
+ MO.setIsKill();
+ break;
+}
+ }
+}
+
+void LiveVariables::addRegisterDead(unsigned IncomingReg, MachineInstr *MI) {
+ for (unsigned i = 0, e = MI-getNumOperands(); i != e; ++i) {
+MachineOperand MO = MI-getOperand(i);
+if (MO.isReg() MO.isDef() MO.getReg() == IncomingReg) {
+ MO.setIsDead();
+ break;
+}
+ }
+}
+
void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
PhysRegInfo[Reg] = MI;
PhysRegUsed[Reg] = true;
@@ -164,9 +216,9 @@
// Does this kill a previous version of this register?
if (MachineInstr *LastUse = PhysRegInfo[Reg]) {
if (PhysRegUsed[Reg])
- RegistersKilled[LastUse].push_back(Reg);
+ addRegisterKilled(Reg, LastUse);
else
- RegistersDead[LastUse].push_back(Reg);
+ addRegisterDead(Reg, LastUse);
}
PhysRegInfo[Reg] = MI;
PhysRegUsed[Reg] = false;
@@ -175,9 +227,9 @@
unsigned Alias = *AliasSet; ++AliasSet) {
if (MachineInstr *LastUse = PhysRegInfo[Alias]) {
if (PhysRegUsed[Alias])
-RegistersKilled[LastUse].push_back(Alias);
+addRegisterKilled(Alias, LastUse);
else
-RegistersDead[LastUse].push_back(Alias);
+addRegisterDead(Alias, LastUse);
}
PhysRegInfo[Alias] = MI;
PhysRegUsed[Alias] = false;
@@ -286,7 +338,7 @@
}
}
-// Finally, if the last block in the function is a return, make sure to
mark
+// Finally, if the last instruction in the block is a return, make sure to
mark
// it as using all of the
[llvm-commits] CVS: llvm/Makefile.rules
Changes in directory llvm: Makefile.rules updated: 1.409 - 1.410 --- Log message: Fix typo pointed out by Bryan Adams --- Diffs of the changes: (+1 -1) Makefile.rules |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.409 llvm/Makefile.rules:1.410 --- llvm/Makefile.rules:1.409 Fri Nov 10 18:00:31 2006 +++ llvm/Makefile.rules Wed Nov 15 15:04:15 2006 @@ -747,7 +747,7 @@ ifdef LINK_LIBS_IN_SHARED ifdef LOADABLE_MODULE -SharedLibKindMessage := Lodable Module +SharedLibKindMessage := Loadable Module else SharedLibKindMessage := Shared Library endif ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp
Changes in directory llvm/lib/Target/X86:
X86FloatingPoint.cpp updated: 1.59 - 1.60
---
Log message:
Kill / dead info has been moved to MI's.
---
Diffs of the changes: (+11 -18)
X86FloatingPoint.cpp | 29 +++--
1 files changed, 11 insertions(+), 18 deletions(-)
Index: llvm/lib/Target/X86/X86FloatingPoint.cpp
diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.59
llvm/lib/Target/X86/X86FloatingPoint.cpp:1.60
--- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.59 Tue Nov 14 13:20:33 2006
+++ llvm/lib/Target/X86/X86FloatingPoint.cppWed Nov 15 14:56:39 2006
@@ -40,6 +40,7 @@
#include llvm/Support/Debug.h
#include llvm/Support/Compiler.h
#include llvm/ADT/DepthFirstIterator.h
+#include llvm/ADT/SmallVector.h
#include llvm/ADT/Statistic.h
#include llvm/ADT/STLExtras.h
#include algorithm
@@ -213,20 +214,12 @@
// Get dead variables list now because the MI pointer may be deleted as
part
// of processing!
-LiveVariables::killed_iterator IB, IE;
-tie(IB, IE) = LV-dead_range(MI);
-
-DEBUG(
- const MRegisterInfo *MRI = MF.getTarget().getRegisterInfo();
- LiveVariables::killed_iterator I = LV-killed_begin(MI);
- LiveVariables::killed_iterator E = LV-killed_end(MI);
- if (I != E) {
-std::cerr Killed Operands:;
-for (; I != E; ++I)
- std::cerr % MRI-getName(*I);
-std::cerr \n;
- }
-);
+SmallVectorunsigned, 8 DeadRegs;
+for (unsigned i = 0, e = MI-getNumOperands(); i != e; ++i) {
+ const MachineOperand MO = MI-getOperand(i);
+ if (MO.isReg() MO.isDead())
+DeadRegs.push_back(MO.getReg());
+}
switch (Flags X86II::FPTypeMask) {
case X86II::ZeroArgFP: handleZeroArgFP(I); break;
@@ -241,8 +234,8 @@
// Check to see if any of the values defined by this instruction are dead
// after definition. If so, pop them.
-for (; IB != IE; ++IB) {
- unsigned Reg = *IB;
+for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
+ unsigned Reg = DeadRegs[i];
if (Reg = X86::FP0 Reg = X86::FP6) {
DEBUG(std::cerr Register FP# Reg-X86::FP0 is dead!\n);
freeStackSlotAfter(I, Reg-X86::FP0);
@@ -762,6 +755,7 @@
unsigned Op0 = getFPReg(MI-getOperand(0));
unsigned Op1 = getFPReg(MI-getOperand(2));
+ bool KillsOp1 = LV-KillsRegister(MI, X86::FP0+Op1);
// The first operand *must* be on the top of the stack.
moveToTop(Op0, I);
@@ -773,9 +767,8 @@
MI-getOperand(0).setReg(getSTReg(Op1));
MI-setOpcode(getConcreteOpcode(MI-getOpcode()));
-
// If we kill the second operand, make sure to pop it from the stack.
- if (Op0 != Op1 LV-KillsRegister(MI, X86::FP0+Op1)) {
+ if (Op0 != Op1 KillsOp1) {
// Get this value off of the register stack.
freeStackSlotAfter(I, Op1);
}
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.cpp updated: 1.72 - 1.73
X86RegisterInfo.cpp updated: 1.177 - 1.178
---
Log message:
Properly transfer kill / dead info.
---
Diffs of the changes: (+41 -21)
X86InstrInfo.cpp| 41 +++--
X86RegisterInfo.cpp | 21 ++---
2 files changed, 41 insertions(+), 21 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.72
llvm/lib/Target/X86/X86InstrInfo.cpp:1.73
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.72 Mon Nov 13 17:36:35 2006
+++ llvm/lib/Target/X86/X86InstrInfo.cppWed Nov 15 14:58:11 2006
@@ -130,6 +130,7 @@
unsigned Dest = MI-getOperand(0).getReg();
unsigned Src = MI-getOperand(1).getReg();
+ MachineInstr *NewMI = NULL;
switch (MI-getOpcode()) {
default: break;
case X86::SHUFPSrri: {
@@ -140,7 +141,9 @@
unsigned C = MI-getOperand(2).getReg();
unsigned M = MI-getOperand(3).getImmedValue();
if (!Subtarget-hasSSE2() || B != C) return 0;
-return BuildMI(*this, X86::PSHUFDri, 2, A).addReg(B).addImm(M);
+NewMI = BuildMI(*this, X86::PSHUFDri, 2, A).addReg(B).addImm(M);
+NewMI-copyKillDeadInfo(MI);
+return NewMI;
}
}
@@ -157,46 +160,51 @@
case X86::INC32r:
case X86::INC64_32r:
assert(MI-getNumOperands() == 2 Unknown inc instruction!);
-return addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, 1);
+NewMI = addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, 1);
+break;
case X86::INC16r:
case X86::INC64_16r:
if (DisableLEA16) return 0;
assert(MI-getNumOperands() == 2 Unknown inc instruction!);
-return addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, 1);
+NewMI = addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, 1);
+break;
case X86::DEC32r:
case X86::DEC64_32r:
assert(MI-getNumOperands() == 2 Unknown dec instruction!);
-return addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, -1);
+NewMI = addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, -1);
+break;
case X86::DEC16r:
case X86::DEC64_16r:
if (DisableLEA16) return 0;
assert(MI-getNumOperands() == 2 Unknown dec instruction!);
-return addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, -1);
+NewMI = addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, -1);
+break;
case X86::ADD32rr:
assert(MI-getNumOperands() == 3 Unknown add instruction!);
-return addRegReg(BuildMI(*this, X86::LEA32r, 5, Dest), Src,
+NewMI = addRegReg(BuildMI(*this, X86::LEA32r, 5, Dest), Src,
MI-getOperand(2).getReg());
+break;
case X86::ADD16rr:
if (DisableLEA16) return 0;
assert(MI-getNumOperands() == 3 Unknown add instruction!);
-return addRegReg(BuildMI(*this, X86::LEA16r, 5, Dest), Src,
+NewMI = addRegReg(BuildMI(*this, X86::LEA16r, 5, Dest), Src,
MI-getOperand(2).getReg());
+break;
case X86::ADD32ri:
case X86::ADD32ri8:
assert(MI-getNumOperands() == 3 Unknown add instruction!);
if (MI-getOperand(2).isImmediate())
- return addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src,
+ NewMI = addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src,
MI-getOperand(2).getImmedValue());
-return 0;
+break;
case X86::ADD16ri:
case X86::ADD16ri8:
if (DisableLEA16) return 0;
assert(MI-getNumOperands() == 3 Unknown add instruction!);
if (MI-getOperand(2).isImmediate())
- return addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src,
+ NewMI = addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src,
MI-getOperand(2).getImmedValue());
break;
-
case X86::SHL16ri:
if (DisableLEA16) return 0;
case X86::SHL32ri:
@@ -208,12 +216,14 @@
AM.Scale = 1 ShAmt;
AM.IndexReg = Src;
unsigned Opc = MI-getOpcode() == X86::SHL32ri ? X86::LEA32r
:X86::LEA16r;
- return addFullAddress(BuildMI(*this, Opc, 5, Dest), AM);
+ NewMI = addFullAddress(BuildMI(*this, Opc, 5, Dest), AM);
}
break;
}
- return 0;
+ if (NewMI)
+NewMI-copyKillDeadInfo(MI);
+ return NewMI;
}
/// commuteInstruction - We have a few instructions that must be hacked on to
@@ -239,7 +249,10 @@
unsigned A = MI-getOperand(0).getReg();
unsigned B = MI-getOperand(1).getReg();
unsigned C = MI-getOperand(2).getReg();
-return BuildMI(*this, Opc, 3, A).addReg(C).addReg(B).addImm(Size-Amt);
+bool BisKill = MI-getOperand(1).isKill();
+bool CisKill = MI-getOperand(2).isKill();
+return BuildMI(*this, Opc, 3, A).addReg(C, false, false, CisKill)
+ .addReg(B, false, false, BisKill).addImm(Size-Amt);
}
default:
return TargetInstrInfo::commuteInstruction(MI);
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.177
[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/SignlessTypes/cast2.cpp
Changes in directory llvm-test/SingleSource/UnitTests/SignlessTypes:
cast2.cpp added (r1.1)
---
Log message:
A test case, derived from MultiSource/Applications/hbd involving the
incorrect ZEXT of a cast involved in a setcc.
---
Diffs of the changes: (+15 -0)
cast2.cpp | 15 +++
1 files changed, 15 insertions(+)
Index: llvm-test/SingleSource/UnitTests/SignlessTypes/cast2.cpp
diff -c /dev/null llvm-test/SingleSource/UnitTests/SignlessTypes/cast2.cpp:1.1
*** /dev/null Wed Nov 15 15:41:26 2006
--- llvm-test/SingleSource/UnitTests/SignlessTypes/cast2.cppWed Nov 15
15:41:16 2006
***
*** 0
--- 1,15
+ #include stdio.h
+ int bug(unsigned char inbuff)
+ {
+ int incnum = (signed char)(inbuff);
+ if ((incnum!=1)(incnum!=-1)) {
+ return (incnum 1) ? 42 : 23 ;
+ } else {
+ return 17;
+ }
+ }
+
+ int main(int argc, char** argv)
+ {
+ printf(%d\n, bug(-1));
+ }
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[llvm-commits] CVS: llvm/lib/Target/Target.td
Changes in directory llvm/lib/Target: Target.td updated: 1.89 - 1.90 --- Log message: add a new field needed by the code emitter generator. --- Diffs of the changes: (+4 -0) Target.td |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/Target.td diff -u llvm/lib/Target/Target.td:1.89 llvm/lib/Target/Target.td:1.90 --- llvm/lib/Target/Target.td:1.89 Fri Nov 3 17:52:18 2006 +++ llvm/lib/Target/Target.td Wed Nov 15 16:55:04 2006 @@ -173,6 +173,10 @@ InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. string Constraints = ; + + /// DisableEncoding - List of operand names (e.g. $op1,$op2) that should not + /// be encoded into the output machineinstr. + string DisableEncoding = ; } /// Imp - Helper class for specifying the implicit uses/defs set for an ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h
Changes in directory llvm/include/llvm/CodeGen:
MachineInstr.h updated: 1.197 - 1.198
---
Log message:
ChangeToRegister should clear IsImp bit.
---
Diffs of the changes: (+4 -4)
MachineInstr.h |8
1 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/include/llvm/CodeGen/MachineInstr.h
diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.197
llvm/include/llvm/CodeGen/MachineInstr.h:1.198
--- llvm/include/llvm/CodeGen/MachineInstr.h:1.197 Wed Nov 15 14:48:17 2006
+++ llvm/include/llvm/CodeGen/MachineInstr.hWed Nov 15 17:55:03 2006
@@ -275,13 +275,13 @@
/// ChangeToRegister - Replace this operand with a new register operand of
/// the specified value. If an operand is known to be an register already,
/// the setReg method should be used.
- void ChangeToRegister(unsigned Reg, bool isDef,
-bool isKill = false, bool isDead = false) {
+ void ChangeToRegister(unsigned Reg, bool isDef) {
opType = MO_Register;
contents.RegNo = Reg;
IsDef = isDef;
-IsKill = isKill;
-IsDead = isDead;
+IsImp = false;
+IsKill = false;
+IsDead = false;
}
friend std::ostream operator(std::ostream os, const MachineOperand mop);
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.252 - 1.253
SelectionDAG.cpp updated: 1.373 - 1.374
---
Log message:
Fix an incorrectly inverted condition.
---
Diffs of the changes: (+1 -2)
DAGCombiner.cpp |2 +-
SelectionDAG.cpp |1 -
2 files changed, 1 insertion(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.252
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.253
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.252 Fri Nov 10 19:00:15 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Nov 15 18:08:20 2006
@@ -2856,7 +2856,7 @@
} else
return false;
- if (!Ptr.Val-hasOneUse())
+ if (Ptr.Val-hasOneUse())
return false;
for (SDNode::use_iterator I = Ptr.Val-use_begin(),
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.373
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.374
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.373Sat Nov 11
14:07:59 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Nov 15 18:08:20 2006
@@ -1481,7 +1481,6 @@
// Perform various simplifications.
ConstantSDNode *N1C = dyn_castConstantSDNode(N1.Val);
ConstantSDNode *N2C = dyn_castConstantSDNode(N2.Val);
- //ConstantSDNode *N3C = dyn_castConstantSDNode(N3.Val);
switch (Opcode) {
case ISD::SETCC: {
// Use FoldSetCC to simplify SETCC's.
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.td updated: 1.262 - 1.263
---
Log message:
switch these back to the 'bad old way'
---
Diffs of the changes: (+20 -20)
PPCInstrInfo.td | 40
1 files changed, 20 insertions(+), 20 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.262
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.263
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.262 Wed Nov 15 17:24:18 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Wed Nov 15 18:33:34 2006
@@ -528,33 +528,33 @@
// Unindexed (r+i) Stores with Update (preinc).
let isStore = 1, PPC970_Unit = 2 in {
-def STBU : DForm_139, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
-stbu $rS, $addr, LdStGeneral,
+def STBU : DForm_139, (ops ptr_rc:$ea_res, GPRC:$rS,
+ symbolLo:$ptroff, ptr_rc:$ptrreg),
+stbu $rS, $ptroff($ptrreg), LdStGeneral,
[/*(set ptr_rc:$ea_res,
(pre_truncsti8 GPRC:$rS, iaddr:$addr))*/],
-RegConstraint$addr.reg = $ea_res,
-NoEncode$ea_res;
-def STHU : DForm_137, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
-sthu $rS, $addr, LdStGeneral,
+RegConstraint$ptrreg = $ea_res, NoEncode$ea_res;
+def STHU : DForm_137, (ops ptr_rc:$ea_res, GPRC:$rS,
+ symbolLo:$ptroff, ptr_rc:$ptrreg),
+sthu $rS, $ptroff($ptrreg), LdStGeneral,
[/*(set ptr_rc:$ea_res,
(pre_truncsti16 GPRC:$rS, iaddr:$addr))*/],
-RegConstraint$addr.reg = $ea_res,
-NoEncode$ea_res;
-def STWU : DForm_137, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
-stwu $rS, $addr, LdStGeneral,
+RegConstraint$ptrreg = $ea_res, NoEncode$ea_res;
+def STWU : DForm_137, (ops ptr_rc:$ea_res, GPRC:$rS,
+ symbolLo:$ptroff, ptr_rc:$ptrreg),
+stwu $rS, $ptroff($ptrreg), LdStGeneral,
[/*(set ptr_rc:$ea_res, (pre_store GPRC:$rS,
iaddr:$addr))*/],
-RegConstraint$addr.reg = $ea_res,
-NoEncode$ea_res;
-def STFSU : DForm_137, (ops ptr_rc:$ea_res, F4RC:$rS, memri:$addr),
-stfsu $rS, $addr, LdStGeneral,
+RegConstraint$ptrreg = $ea_res, NoEncode$ea_res;
+def STFSU : DForm_137, (ops ptr_rc:$ea_res, F4RC:$rS,
+ symbolLo:$ptroff, ptr_rc:$ptrreg),
+stfsu $rS, $ptroff($ptrreg), LdStGeneral,
[/*(set ptr_rc:$ea_res, (pre_store F4RC:$rS,
iaddr:$addr))*/],
-RegConstraint$addr.reg = $ea_res,
-NoEncode$ea_res;
-def STFDU : DForm_137, (ops ptr_rc:$ea_res, F8RC:$rS, memri:$addr),
-stfdu $rS, $addr, LdStGeneral,
+RegConstraint$ptrreg = $ea_res, NoEncode$ea_res;
+def STFDU : DForm_137, (ops ptr_rc:$ea_res, F8RC:$rS,
+ symbolLo:$ptroff, ptr_rc:$ptrreg),
+stfdu $rS, $ptroff($ptrreg), LdStGeneral,
[/*(set ptr_rc:$ea_res, (pre_store F8RC:$rS,
iaddr:$addr))*/],
-RegConstraint$addr.reg = $ea_res,
-NoEncode$ea_res;
+RegConstraint$ptrreg = $ea_res, NoEncode$ea_res;
}
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.220 - 1.221
PPCInstrInfo.td updated: 1.263 - 1.264
---
Log message:
add patterns for ppc32 preinc stores. ppc64 next.
---
Diffs of the changes: (+22 -7)
PPCISelDAGToDAG.cpp |8
PPCInstrInfo.td | 21 ++---
2 files changed, 22 insertions(+), 7 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.220
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.221
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.220 Wed Nov 15 13:55:13 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Wed Nov 15 18:41:37 2006
@@ -108,6 +108,14 @@
SDOperand Base) {
return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
}
+
+/// SelectAddrImmOffs - Return true if the operand is valid for a preinc
+/// immediate field. Because preinc imms have already been validated, just
+/// accept it.
+bool SelectAddrImmOffs(SDOperand Op, SDOperand N, SDOperand Out) const {
+ Out = N;
+ return true;
+}
/// SelectAddrIdx - Given the specified addressed, check to see if it can
be
/// represented as an indexed [r+r] operation. Returns false if it can
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.263
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.264
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.263 Wed Nov 15 18:33:34 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Wed Nov 15 18:41:37 2006
@@ -273,6 +273,8 @@
def xoaddr : ComplexPatterniPTR, 2, SelectAddrIdxOnly,[], [];
def ixaddr : ComplexPatterniPTR, 2, SelectAddrImmShift, [], []; // std
+/// This is just the offset part of iaddr, used for preinc.
+def iaddroff : ComplexPatterniPTR, 1, SelectAddrImmOffs, [], [];
//===--===//
// PowerPC Instruction Predicate Definitions.
@@ -531,29 +533,34 @@
def STBU : DForm_139, (ops ptr_rc:$ea_res, GPRC:$rS,
symbolLo:$ptroff, ptr_rc:$ptrreg),
stbu $rS, $ptroff($ptrreg), LdStGeneral,
-[/*(set ptr_rc:$ea_res,
- (pre_truncsti8 GPRC:$rS, iaddr:$addr))*/],
+[(set ptr_rc:$ea_res,
+ (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
+ iaddroff:$ptroff))],
RegConstraint$ptrreg = $ea_res, NoEncode$ea_res;
def STHU : DForm_137, (ops ptr_rc:$ea_res, GPRC:$rS,
symbolLo:$ptroff, ptr_rc:$ptrreg),
sthu $rS, $ptroff($ptrreg), LdStGeneral,
-[/*(set ptr_rc:$ea_res,
- (pre_truncsti16 GPRC:$rS, iaddr:$addr))*/],
+[(set ptr_rc:$ea_res,
+(pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
+iaddroff:$ptroff))],
RegConstraint$ptrreg = $ea_res, NoEncode$ea_res;
def STWU : DForm_137, (ops ptr_rc:$ea_res, GPRC:$rS,
symbolLo:$ptroff, ptr_rc:$ptrreg),
stwu $rS, $ptroff($ptrreg), LdStGeneral,
-[/*(set ptr_rc:$ea_res, (pre_store GPRC:$rS,
iaddr:$addr))*/],
+[(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
+ iaddroff:$ptroff))],
RegConstraint$ptrreg = $ea_res, NoEncode$ea_res;
def STFSU : DForm_137, (ops ptr_rc:$ea_res, F4RC:$rS,
symbolLo:$ptroff, ptr_rc:$ptrreg),
stfsu $rS, $ptroff($ptrreg), LdStGeneral,
-[/*(set ptr_rc:$ea_res, (pre_store F4RC:$rS,
iaddr:$addr))*/],
+[(set ptr_rc:$ea_res, (pre_store F4RC:$rS,
ptr_rc:$ptrreg,
+ iaddroff:$ptroff))],
RegConstraint$ptrreg = $ea_res, NoEncode$ea_res;
def STFDU : DForm_137, (ops ptr_rc:$ea_res, F8RC:$rS,
symbolLo:$ptroff, ptr_rc:$ptrreg),
stfdu $rS, $ptroff($ptrreg), LdStGeneral,
-[/*(set ptr_rc:$ea_res, (pre_store F8RC:$rS,
iaddr:$addr))*/],
+[(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
+ iaddroff:$ptroff))],
RegConstraint$ptrreg = $ea_res, NoEncode$ea_res;
}
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp PPCInstr64Bit.td
Changes in directory llvm/lib/Target/PowerPC:
PPCHazardRecognizers.cpp updated: 1.16 - 1.17
PPCInstr64Bit.td updated: 1.29 - 1.30
---
Log message:
add ppc64 r+i stores with update.
---
Diffs of the changes: (+72 -40)
PPCHazardRecognizers.cpp | 27 +++---
PPCInstr64Bit.td | 85 ---
2 files changed, 72 insertions(+), 40 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
diff -u llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.16
llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.17
--- llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.16 Tue Nov 14
20:43:19 2006
+++ llvm/lib/Target/PowerPC/PPCHazardRecognizers.cppWed Nov 15 18:57:19 2006
@@ -234,28 +234,26 @@
unsigned ThisStoreSize;
switch (Opcode) {
default: assert(0 Unknown store instruction!);
-case PPC::STB: case PPC::STBU:
-case PPC::STBX:
-case PPC::STB8:
-case PPC::STBX8:
+case PPC::STB:case PPC::STB8:
+case PPC::STBU: case PPC::STBU8:
+case PPC::STBX: case PPC::STBX8:
case PPC::STVEBX:
ThisStoreSize = 1;
break;
-case PPC::STH: case PPC::STHU:
-case PPC::STHX:
-case PPC::STH8:
-case PPC::STHX8:
+case PPC::STH:case PPC::STH8:
+case PPC::STHU: case PPC::STHU8:
+case PPC::STHX: case PPC::STHX8:
case PPC::STVEHX:
case PPC::STHBRX:
ThisStoreSize = 2;
break;
-case PPC::STFS: case PPC::STFSU:
+case PPC::STFS:
+case PPC::STFSU:
case PPC::STFSX:
-case PPC::STWX:
+case PPC::STWX: case PPC::STWX8:
case PPC::STWUX:
-case PPC::STW:case PPC::STWU:
-case PPC::STW8:
-case PPC::STWX8:
+case PPC::STW:case PPC::STW8:
+case PPC::STWU: case PPC::STWU8:
case PPC::STVEWX:
case PPC::STFIWX:
case PPC::STWBRX:
@@ -263,7 +261,8 @@
break;
case PPC::STD_32:
case PPC::STDX_32:
-case PPC::STD: case PPC::STDU:
+case PPC::STD:
+case PPC::STDU:
case PPC::STFD:
case PPC::STFDX:
case PPC::STDX:
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.29
llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.30
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.29 Wed Nov 15 17:24:18 2006
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.tdWed Nov 15 18:57:19 2006
@@ -356,32 +356,6 @@
}
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
-// Normal stores.
-def STD : DSForm_162, 0, (ops G8RC:$rS, memrix:$dst),
-std $rS, $dst, LdStSTD,
-[(store G8RC:$rS, ixaddr:$dst)], isPPC64;
-def STDX : XForm_831, 149, (ops G8RC:$rS, memrr:$dst),
- stdx $rS, $dst, LdStSTD,
- [(store G8RC:$rS, xaddr:$dst)], isPPC64,
- PPC970_DGroup_Cracked;
-
-def STDU : DSForm_162, 1, (ops G8RC:$ea_res, G8RC:$rS, memrix:$dst),
-stdu $rS, $dst, LdStSTD,
-[], isPPC64;
-def STDUX : XForm_831, 181, (ops G8RC:$rS, memrr:$dst),
- stdux $rS, $dst, LdStSTD,
- [], isPPC64;
-
-// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
-def STD_32 : DSForm_162, 0, (ops GPRC:$rT, memrix:$dst),
- std $rT, $dst, LdStSTD,
- [(PPCstd_32 GPRC:$rT, ixaddr:$dst)], isPPC64;
-def STDX_32 : XForm_831, 149, (ops GPRC:$rT, memrr:$dst),
- stdx $rT, $dst, LdStSTD,
- [(PPCstd_32 GPRC:$rT, xaddr:$dst)], isPPC64,
- PPC970_DGroup_Cracked;
-
-
// Truncating stores.
def STB8 : DForm_138, (ops G8RC:$rS, memri:$src),
stb $rS, $src, LdStGeneral,
@@ -404,6 +378,65 @@
stwx $rS, $dst, LdStGeneral,
[(truncstorei32 G8RC:$rS, xaddr:$dst)],
PPC970_DGroup_Cracked;
+// Normal 8-byte stores.
+def STD : DSForm_162, 0, (ops G8RC:$rS, memrix:$dst),
+std $rS, $dst, LdStSTD,
+[(store G8RC:$rS, ixaddr:$dst)], isPPC64;
+def STDX : XForm_831, 149, (ops G8RC:$rS, memrr:$dst),
+ stdx $rS, $dst, LdStSTD,
+ [(store G8RC:$rS, xaddr:$dst)], isPPC64,
+ PPC970_DGroup_Cracked;
+}
+
+let isStore = 1, PPC970_Unit = 2 in {
+
+def STBU8 : DForm_138, (ops ptr_rc:$ea_res, G8RC:$rS,
+ symbolLo:$ptroff, ptr_rc:$ptrreg),
+stbu $rS, $ptroff($ptrreg), LdStGeneral,
+[(set ptr_rc:$ea_res,
+ (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg,
+ iaddroff:$ptroff))],
+RegConstraint$ptrreg = $ea_res, NoEncode$ea_res;
+def STHU8 : DForm_145, (ops ptr_rc:$ea_res, G8RC:$rS,
+ symbolLo:$ptroff, ptr_rc:$ptrreg),
+
[llvm-commits] CVS: llvm/lib/CodeGen/LLVMTargetMachine.cpp
Changes in directory llvm/lib/CodeGen: LLVMTargetMachine.cpp updated: 1.5 - 1.6 --- Log message: enable the branch folding pass for the JIT. --- Diffs of the changes: (+3 -0) LLVMTargetMachine.cpp |3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/CodeGen/LLVMTargetMachine.cpp diff -u llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.5 llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.6 --- llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.5 Tue Nov 7 13:33:46 2006 +++ llvm/lib/CodeGen/LLVMTargetMachine.cpp Wed Nov 15 19:00:07 2006 @@ -147,6 +147,9 @@ if (PrintMachineCode) // Print the register-allocated code PM.add(createMachineFunctionPrinterPass(std::cerr)); + // Branch folding must be run after regalloc and prolog/epilog insertion. + if (!Fast) +PM.add(createBranchFoldingPass()); if (addPreEmitPass(PM, Fast) PrintMachineCode) PM.add(createMachineFunctionPrinterPass(std::cerr)); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] Priority-Based Coloring Approach to Register Allocation
Hi all,
This is meant for a code review and NOT for submission (just yet).
This is my implementation of Chow Hennesey's Priority-Based Coloring
Approach to Register Allocation. It's still in the experimental stages
(though it compiles the tests). I'd like people to look at it and let
me know what you think. The patch included is needed for compilation.
You'd place the RegAllocGraphColoring.cpp file in the llvm/lib/
CodeGen directory. You can use the graph coloring with the commandline:
llc -regalloc=graphcoloring foo.bc
All comments are welcome!
-bw
RegAllocGraphColoring.cpp
Description: Binary data
Index: include/llvm/CodeGen/LinkAllCodegenComponents.h
===
RCS file: /var/cvs/llvm/llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h,v
retrieving revision 1.3
diff -a -u -r1.3 LinkAllCodegenComponents.h
--- include/llvm/CodeGen/LinkAllCodegenComponents.h 1 Aug 2006 19:14:14
- 1.3
+++ include/llvm/CodeGen/LinkAllCodegenComponents.h 16 Nov 2006 00:54:23
-
@@ -31,6 +31,7 @@
(void) llvm::createSimpleRegisterAllocator();
(void) llvm::createLocalRegisterAllocator();
(void) llvm::createLinearScanRegisterAllocator();
+ (void) llvm::createGraphColoringRegisterAllocator();
(void) llvm::createBFS_DAGScheduler(NULL, NULL, NULL);
(void) llvm::createSimpleDAGScheduler(NULL, NULL, NULL);
Index: include/llvm/CodeGen/LiveInterval.h
===
RCS file: /var/cvs/llvm/llvm/include/llvm/CodeGen/LiveInterval.h,v
retrieving revision 1.25
diff -a -u -r1.25 LiveInterval.h
--- include/llvm/CodeGen/LiveInterval.h 2 Sep 2006 05:37:53 - 1.25
+++ include/llvm/CodeGen/LiveInterval.h 16 Nov 2006 00:54:23 -
@@ -244,6 +244,10 @@
/// the range must already be in this interval in its entirety.
void removeRange(unsigned Start, unsigned End);
+void removeRange(LiveRange LR) {
+ removeRange(LR.start, LR.end);
+}
+
bool operator(const LiveInterval other) const {
return beginNumber() other.beginNumber();
}
Index: include/llvm/CodeGen/LiveIntervalAnalysis.h
===
RCS file: /var/cvs/llvm/llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h,v
retrieving revision 1.64
diff -a -u -r1.64 LiveIntervalAnalysis.h
--- include/llvm/CodeGen/LiveIntervalAnalysis.h 15 Sep 2006 03:57:23 -
1.64
+++ include/llvm/CodeGen/LiveIntervalAnalysis.h 16 Nov 2006 00:54:23 -
@@ -148,6 +148,11 @@
VirtRegMap vrm,
int slot);
+/// CreateNewLiveInterval - Create a new live interval with the given live
+/// ranges.
+LiveInterval CreateNewLiveInterval(const LiveInterval* LI,
+std::vectorLiveRange LRs);
+
virtual void getAnalysisUsage(AnalysisUsage AU) const;
virtual void releaseMemory();
Index: include/llvm/CodeGen/Passes.h
===
RCS file: /var/cvs/llvm/llvm/include/llvm/CodeGen/Passes.h,v
retrieving revision 1.22
diff -a -u -r1.22 Passes.h
--- include/llvm/CodeGen/Passes.h 7 Nov 2006 19:33:46 - 1.22
+++ include/llvm/CodeGen/Passes.h 16 Nov 2006 00:54:23 -
@@ -70,6 +70,12 @@
///
FunctionPass *createLinearScanRegisterAllocator();
+ /// GraphColoringRegisterAllocator Pass - This pass implements the
+ /// priority-based coloring approach to register allocation, a global
register
+ /// allocator.
+ ///
+ FunctionPass *createGraphColoringRegisterAllocator();
+
/// PrologEpilogCodeInserter Pass - This pass inserts prolog and epilog code,
/// and eliminates abstract frame references.
///
Index: lib/CodeGen/LiveIntervalAnalysis.cpp
===
RCS file: /var/cvs/llvm/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp,v
retrieving revision 1.195
diff -a -u -r1.195 LiveIntervalAnalysis.cpp
--- lib/CodeGen/LiveIntervalAnalysis.cpp15 Nov 2006 20:54:11 -
1.195
+++ lib/CodeGen/LiveIntervalAnalysis.cpp16 Nov 2006 00:54:24 -
@@ -251,6 +251,67 @@
}
}
+/// CreateNewLiveInterval - Create a new live interval with the given live
+/// ranges.
+LiveInterval
+LiveIntervals::CreateNewLiveInterval(const LiveInterval* LI,
+ std::vectorLiveRange LRs) {
+ lv_ = getAnalysisToUpdateLiveVariables();
+ const TargetRegisterClass* RC = mf_-getSSARegMap()-getRegClass(LI-reg);
+
+ // Create a new virtual register for the spill interval.
+ unsigned NewVReg = mf_-getSSARegMap()-createVirtualRegister(RC);
+
+ // Replace the old virtual registers in the machine operands with the shiny
+ // new one.
+ for (std::vectorLiveRange::iterator
+ I = LRs.begin(), E =
[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/mem_update.ll
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
mem_update.ll updated: 1.3 - 1.4
---
Log message:
make this harder
---
Diffs of the changes: (+26 -0)
mem_update.ll | 26 ++
1 files changed, 26 insertions(+)
Index: llvm/test/Regression/CodeGen/PowerPC/mem_update.ll
diff -u llvm/test/Regression/CodeGen/PowerPC/mem_update.ll:1.3
llvm/test/Regression/CodeGen/PowerPC/mem_update.ll:1.4
--- llvm/test/Regression/CodeGen/PowerPC/mem_update.ll:1.3 Fri Nov 10
18:13:07 2006
+++ llvm/test/Regression/CodeGen/PowerPC/mem_update.ll Wed Nov 15 19:22:52 2006
@@ -2,6 +2,7 @@
; RUN: llvm-as %s | llc -march=ppc32 -enable-ppc-preinc | not grep addi
; RUN: llvm-as %s | llc -march=ppc64 -enable-ppc-preinc
; RUN: llvm-as %s | llc -march=ppc64 -enable-ppc-preinc | not grep addi
+%Glob = global ulong 4
int *%test0(int *%X, int *%dest) {
%Y = getelementptr int* %X, int 4
@@ -33,6 +34,13 @@
ret ushort* %Y
}
+short *%test3a(short *%X, long *%dest) {
+ %Y = getelementptr short* %X, int 4
+ %A = load short* %Y
+ %B = cast short %A to long
+ store long %B, long* %dest
+ ret short* %Y
+}
long *%test4(long *%X, long *%dest) {
%Y = getelementptr long* %X, int 4
@@ -40,3 +48,21 @@
store long %A, long* %dest
ret long* %Y
}
+
+ushort *%test5(ushort *%X) {
+ %Y = getelementptr ushort* %X, int 4
+ store ushort 7, ushort* %Y
+ ret ushort* %Y
+}
+
+ulong *%test6(ulong *%X, ulong %A) {
+ %Y = getelementptr ulong* %X, int 4
+ store ulong %A, ulong* %Y
+ ret ulong* %Y
+}
+
+ulong *%test7(ulong *%X, ulong %A) {
+ store ulong %A, ulong* %Glob
+ ret ulong *%Glob
+}
+
___
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Re: [llvm-commits] Priority-Based
On Nov 15, 2006, at 5:03 PM, Bill Wendling wrote:
Hi all,
This is meant for a code review and NOT for submission (just yet).
This is my implementation of Chow Hennesey's Priority-Based
Coloring Approach to Register Allocation. It's still in the
experimental stages (though it compiles the tests). I'd like people
to look at it and let me know what you think. The patch included is
needed for compilation. You'd place the RegAllocGraphColoring.cpp
file in the llvm/lib/CodeGen directory. You can use the graph
coloring with the commandline:
Cool.
I'll review the patch. Evan, can you take a first look at the new file?
The patch looks good, but please:
1. Change CreateNewLiveInterval to take LRs by const reference. This
will require changing the iterators to be const_iterator instead of
just iterator's.
2. Please change int* X to int *X to fit with the rest of the code.
3. Why do this?
+ lv_ = getAnalysisToUpdateLiveVariables();
Isn't lv_ already valid when the method is called?
4. I don't think this is sufficient:
+MachineOperand MOp = MI-getOperand(J);
+if (MOp.isRegister() MOp.getReg() == LI-reg) {
In particular, consider if you have two vregs (R1025 and R1027)
that get coallesced before RA. When this happens I believe that live
intervals just marks the two vregs as having the same interval, and
that interval only has one reg (say R1027). When this happens, the
actual machine instrs are not updated. This means that you can have
a reference to R1025, even though the interval says it is R1027.
To fix this, try using:
+MachineOperand MOp = MI-getOperand(J);
+if (MOp.isRegister() rep(MOp.getReg()) == LI-reg) {
which should handle this case.
5. It is unclear to me why you have this loop:
+ for (unsigned K = J + 1; K != MI-getNumOperands(); ++K)
+if (MI-getOperand(K).isReg()
+MI-getOperand(K).getReg() == LI-reg)
+ MI-getOperand(K).setReg(NewVReg);
If not needed, just remove it.
6. I don't think this is right:
+ // Update live variables if it is available
+ if (lv_)
+lv_-addVirtualRegisterKilled(NewVReg, MI);
With Evan's recent change, kill/dead markers are now stored on the
instruction. If MOp.setReg doesn't modify these markers, you
probably don't need to do anything to update live vars.
7. The comment:
+/// CreateNewLiveInterval - Create a new live interval with the
given live
+/// ranges.
Should mention that the created interval has an infinite spill weight.
If you make these changes, go ahead and commit the
LiveIntervalAnalysis.cpp, LiveIntervalAnalysis.h, and LiveInterval.h
changes, even before the rest is reviewed.
Thanks Bill!
-Chris
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Re: [llvm-commits] Priority-Based
On Nov 15, 2006, at 6:04 PM, Chris Lattner wrote:
The patch looks good, but please:
1. Change CreateNewLiveInterval to take LRs by const reference.
This will require changing the iterators to be const_iterator
instead of just iterator's.
Will do.
2. Please change int* X to int *X to fit with the rest of the
code.
ARRRGH!! ;-) But okay. Consistency is a good thing :-)
3. Why do this?
+ lv_ = getAnalysisToUpdateLiveVariables();
Isn't lv_ already valid when the method is called?
I was kind of copying the code from addIntervalsForSpills. It has this
comment:
// since this is called after the analysis is done we don't know if
// LiveVariables is available
I'm not sure if this is also valid for this method...I'll try it
without this in it.
4. I don't think this is sufficient:
+MachineOperand MOp = MI-getOperand(J);
+if (MOp.isRegister() MOp.getReg() == LI-reg) {
In particular, consider if you have two vregs (R1025 and R1027)
that get coallesced before RA. When this happens I believe that
live intervals just marks the two vregs as having the same interval,
and that interval only has one reg (say R1027). When this happens,
the actual machine instrs are not updated. This means that you can
have a reference to R1025, even though the interval says it is R1027.
To fix this, try using:
+MachineOperand MOp = MI-getOperand(J);
+if (MOp.isRegister() rep(MOp.getReg()) == LI-reg) {
which should handle this case.
Ah! Okay. That's a good point. If this isn't documented, it might be a
good idea to throw it in a webpage somewhere.
5. It is unclear to me why you have this loop:
+ for (unsigned K = J + 1; K != MI-getNumOperands(); ++K)
+if (MI-getOperand(K).isReg()
+MI-getOperand(K).getReg() == LI-reg)
+ MI-getOperand(K).setReg(NewVReg);
If not needed, just remove it.
Hmm...you're right. It looks superfluous. I probably wrote it at 2AM
or something.
6. I don't think this is right:
+ // Update live variables if it is available
+ if (lv_)
+lv_-addVirtualRegisterKilled(NewVReg, MI);
With Evan's recent change, kill/dead markers are now stored on the
instruction. If MOp.setReg doesn't modify these markers, you
probably don't need to do anything to update live vars.
Alrighty.
7. The comment:
+/// CreateNewLiveInterval - Create a new live interval with the
given live
+/// ranges.
Should mention that the created interval has an infinite spill weight.
Okay.
If you make these changes, go ahead and commit the
LiveIntervalAnalysis.cpp, LiveIntervalAnalysis.h, and LiveInterval.h
changes, even before the rest is reviewed.
Cool. Thanks!
-bw
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[llvm-commits] CVS: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
Changes in directory llvm/lib/CodeGen:
LiveIntervalAnalysis.cpp updated: 1.195 - 1.196
---
Log message:
Added a new method CreateNewLiveInterval which, given a list of
LiveRanges, creates a new LiveInterval from them. The LiveRanges should
have existed already in another LiveInterval, but removed.
---
Diffs of the changes: (+49 -0)
LiveIntervalAnalysis.cpp | 49 +++
1 files changed, 49 insertions(+)
Index: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
diff -u llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.195
llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.196
--- llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.195 Wed Nov 15 14:54:11 2006
+++ llvm/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Nov 15 20:41:50 2006
@@ -251,6 +251,55 @@
}
}
+/// CreateNewLiveInterval - Create a new live interval with the given live
+/// ranges. The new live interval will have an infinite spill weight.
+LiveInterval
+LiveIntervals::CreateNewLiveInterval(const LiveInterval *LI,
+ const std::vectorLiveRange LRs) {
+ const TargetRegisterClass *RC = mf_-getSSARegMap()-getRegClass(LI-reg);
+
+ // Create a new virtual register for the spill interval.
+ unsigned NewVReg = mf_-getSSARegMap()-createVirtualRegister(RC);
+
+ // Replace the old virtual registers in the machine operands with the shiny
+ // new one.
+ for (std::vectorLiveRange::const_iterator
+ I = LRs.begin(), E = LRs.end(); I != E; ++I) {
+unsigned Index = getBaseIndex(I-start);
+unsigned End = getBaseIndex(I-end - 1) + InstrSlots::NUM;
+
+for (; Index != End; Index += InstrSlots::NUM) {
+ // Skip deleted instructions
+ while (Index != End !getInstructionFromIndex(Index))
+Index += InstrSlots::NUM;
+
+ if (Index == End) break;
+
+ MachineInstr *MI = getInstructionFromIndex(Index);
+
+ for (unsigned J = 0; J != MI-getNumOperands(); ++J) {
+MachineOperand MOp = MI-getOperand(J);
+if (MOp.isRegister() rep(MOp.getReg()) == LI-reg)
+ MOp.setReg(NewVReg);
+ }
+}
+ }
+
+ LiveInterval NewLI = getOrCreateInterval(NewVReg);
+
+ // The spill weight is now infinity as it cannot be spilled again
+ NewLI.weight = float(HUGE_VAL);
+
+ for (std::vectorLiveRange::const_iterator
+ I = LRs.begin(), E = LRs.end(); I != E; ++I) {
+DEBUG(std::cerrAdding live range *I to new interval\n);
+NewLI.addRange(*I);
+ }
+
+ DEBUG(std::cerr Created new live interval NewLI \n);
+ return NewLI;
+}
+
std::vectorLiveInterval* LiveIntervals::
addIntervalsForSpills(const LiveInterval li, VirtRegMap vrm, int slot) {
// since this is called after the analysis is done we don't know if
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h
Changes in directory llvm/include/llvm/CodeGen: LiveIntervalAnalysis.h updated: 1.64 - 1.65 --- Log message: Added a new method CreateNewLiveInterval which, given a list of LiveRanges, creates a new LiveInterval from them. The LiveRanges should have existed already in another LiveInterval, but removed. --- Diffs of the changes: (+5 -0) LiveIntervalAnalysis.h |5 + 1 files changed, 5 insertions(+) Index: llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h diff -u llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h:1.64 llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h:1.65 --- llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h:1.64 Thu Sep 14 22:57:23 2006 +++ llvm/include/llvm/CodeGen/LiveIntervalAnalysis.hWed Nov 15 20:41:50 2006 @@ -148,6 +148,11 @@ VirtRegMap vrm, int slot); +/// CreateNewLiveInterval - Create a new live interval with the given live +/// ranges. The new live interval will have an infinite spill weight. +LiveInterval CreateNewLiveInterval(const LiveInterval *LI, +const std::vectorLiveRange LRs); + virtual void getAnalysisUsage(AnalysisUsage AU) const; virtual void releaseMemory(); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/CodeGen/LiveInterval.h
Changes in directory llvm/include/llvm/CodeGen:
LiveInterval.h updated: 1.25 - 1.26
---
Log message:
Added removeRange, which takes and removes an entire LiveRange.
---
Diffs of the changes: (+4 -0)
LiveInterval.h |4
1 files changed, 4 insertions(+)
Index: llvm/include/llvm/CodeGen/LiveInterval.h
diff -u llvm/include/llvm/CodeGen/LiveInterval.h:1.25
llvm/include/llvm/CodeGen/LiveInterval.h:1.26
--- llvm/include/llvm/CodeGen/LiveInterval.h:1.25 Sat Sep 2 00:37:53 2006
+++ llvm/include/llvm/CodeGen/LiveInterval.hWed Nov 15 20:43:32 2006
@@ -244,6 +244,10 @@
/// the range must already be in this interval in its entirety.
void removeRange(unsigned Start, unsigned End);
+void removeRange(LiveRange LR) {
+ removeRange(LR.start, LR.end);
+}
+
bool operator(const LiveInterval other) const {
return beginNumber() other.beginNumber();
}
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[llvm-commits] CVS: llvm-test/Makefile.programs
Changes in directory llvm-test: Makefile.programs updated: 1.238 - 1.239 --- Log message: Add a facility for using the -disable-loop-extraction option with bugpoint. --- Diffs of the changes: (+4 -0) Makefile.programs |4 1 files changed, 4 insertions(+) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.238 llvm-test/Makefile.programs:1.239 --- llvm-test/Makefile.programs:1.238 Thu Nov 9 20:08:26 2006 +++ llvm-test/Makefile.programs Wed Nov 15 21:49:51 2006 @@ -391,6 +391,10 @@ BUGPOINT_OPTIONS += -abs-tolerance $(FP_ABSTOLERANCE) endif +ifdef DISABLE_LOOP_EXTRACT +BUGPOINT_OPTIONS += -disable-loop-extraction +endif + # Give bugpoint information about LDFLAGS to pass down to the actual link stage # of the program. BUGPOINT_OPTIONS += $(LDFLAGS:%=-Xlinker=%) $(EXTRA_OPTIONS:%=-Xlinker=%) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
