[llvm-commits] CVS: llvm/lib/Target/ARM/ARMConstantIslandPass.cpp ARMISelDAGToDAG.cpp ARMInstrThumb.td
Changes in directory llvm/lib/Target/ARM:
ARMConstantIslandPass.cpp updated: 1.1 - 1.2
ARMISelDAGToDAG.cpp updated: 1.102 - 1.103
ARMInstrThumb.td updated: 1.2 - 1.3
---
Log message:
Use PC relative ldr to load from a constantpool in Thumb mode.
---
Diffs of the changes: (+25 -9)
ARMConstantIslandPass.cpp |3 +++
ARMISelDAGToDAG.cpp | 25 +
ARMInstrThumb.td |6 +-
3 files changed, 25 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
diff -u llvm/lib/Target/ARM/ARMConstantIslandPass.cpp:1.1
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp:1.2
--- llvm/lib/Target/ARM/ARMConstantIslandPass.cpp:1.1 Fri Jan 19 01:51:42 2007
+++ llvm/lib/Target/ARM/ARMConstantIslandPass.cpp Wed Jan 24 02:53:17 2007
@@ -245,6 +245,9 @@
case ARMII::AddrModeT4:
MaxOffs = 1 (5+2);
break;
+ case ARMII::AddrModeTs:
+MaxOffs = 1 (8+2);
+break;
}
// Remember that this is a user of a CP entry.
Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.102
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.103
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.102 Tue Jan 23 20:45:25 2007
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Wed Jan 24 02:53:17 2007
@@ -380,6 +380,9 @@
SDOperand TmpBase, TmpOffImm;
if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
return false; // We want to select tLDRspi / tSTRspi instead.
+if (N.getOpcode() == ARMISD::Wrapper
+N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
+ return false; // We want to select tLDRpci instead.
}
if (N.getOpcode() != ISD::ADD) {
@@ -505,14 +508,20 @@
SDOperand CPIdx =
CurDAG-getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
TLI.getPointerTy());
- SDOperand Ops[] = {
-CPIdx,
-CurDAG-getRegister(0, MVT::i32),
-CurDAG-getTargetConstant(0, MVT::i32),
-CurDAG-getEntryNode()
- };
- SDNode *ResNode =
-CurDAG-getTargetNode(ARM::LDR, MVT::i32, MVT::Other, Ops, 4);
+
+ SDNode *ResNode;
+ if (Subtarget-isThumb())
+ResNode = CurDAG-getTargetNode(ARM::tLDRpci, MVT::i32, MVT::Other,
+CPIdx, CurDAG-getEntryNode());
+ else {
+SDOperand Ops[] = {
+ CPIdx,
+ CurDAG-getRegister(0, MVT::i32),
+ CurDAG-getTargetConstant(0, MVT::i32),
+ CurDAG-getEntryNode()
+};
+ResNode = CurDAG-getTargetNode(ARM::LDR, MVT::i32, MVT::Other, Ops,
4);
+ }
ReplaceUses(Op, SDOperand(ResNode, 0));
return NULL;
}
Index: llvm/lib/Target/ARM/ARMInstrThumb.td
diff -u llvm/lib/Target/ARM/ARMInstrThumb.td:1.2
llvm/lib/Target/ARM/ARMInstrThumb.td:1.3
--- llvm/lib/Target/ARM/ARMInstrThumb.td:1.2Tue Jan 23 16:59:13 2007
+++ llvm/lib/Target/ARM/ARMInstrThumb.tdWed Jan 24 02:53:17 2007
@@ -220,10 +220,14 @@
ldrsh $dst, $addr,
[(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))];
-// def tLDRpci
def tLDRspi : TIs(ops GPR:$dst, t_addrmode_sp:$addr),
ldr $dst, $addr,
[(set GPR:$dst, (load t_addrmode_sp:$addr))];
+
+// Load tconstpool
+def tLDRpci : TIs(ops GPR:$dst, i32imm:$addr),
+ ldr $dst, $addr,
+ [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))];
} // isLoad
let isStore = 1 in {
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[llvm-commits] CVS: llvm/lib/CodeGen/DwarfWriter.cpp
Changes in directory llvm/lib/CodeGen:
DwarfWriter.cpp updated: 1.111 - 1.112
---
Log message:
Use asm printer to emit alignment
---
Diffs of the changes: (+2 -8)
DwarfWriter.cpp | 10 ++
1 files changed, 2 insertions(+), 8 deletions(-)
Index: llvm/lib/CodeGen/DwarfWriter.cpp
diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.111
llvm/lib/CodeGen/DwarfWriter.cpp:1.112
--- llvm/lib/CodeGen/DwarfWriter.cpp:1.111 Mon Jan 8 16:15:18 2007
+++ llvm/lib/CodeGen/DwarfWriter.cppWed Jan 24 07:12:32 2007
@@ -945,12 +945,6 @@
O \n;
}
- /// EmitAlign - Print a align directive.
- ///
- void EmitAlign(unsigned Alignment) const {
-O TAI-getAlignDirective() Alignment \n;
- }
-
/// EmitULEB128Bytes - Emit an assembler byte data directive to compose an
/// unsigned leb128 value.
void EmitULEB128Bytes(unsigned Value) const {
@@ -2444,7 +2438,7 @@
EmitFrameMoves(NULL, 0, Moves);
for (unsigned i = 0, N = Moves.size(); i N; ++i) delete Moves[i];
-EmitAlign(2);
+Asm-EmitAlignment(2);
EmitLabel(frame_common_end, 0);
O \n;
@@ -2477,7 +2471,7 @@
EmitFrameMoves(func_begin, SubprogramCount, Moves);
-EmitAlign(2);
+Asm-EmitAlignment(2);
EmitLabel(frame_end, SubprogramCount);
O \n;
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.297 - 1.298
---
Log message:
Fix a misencoding of CBW and CWD. This fixes PR1030: http://llvm.org/PR1030 .
---
Diffs of the changes: (+2 -2)
X86InstrInfo.td |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.297
llvm/lib/Target/X86/X86InstrInfo.td:1.298
--- llvm/lib/Target/X86/X86InstrInfo.td:1.297 Tue Dec 5 13:50:18 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Wed Jan 24 12:31:00 2007
@@ -2394,12 +2394,12 @@
[(set GR32:$dst, (zextloadi32i16 addr:$src))], TB;
def CBW : I0x98, RawFrm, (ops),
-{cbtw|cbw}, [], Imp[AL],[AX]; // AX = signext(AL)
+{cbtw|cbw}, [], Imp[AL],[AX], OpSize; // AX = signext(AL)
def CWDE : I0x98, RawFrm, (ops),
{cwtl|cwde}, [], Imp[AX],[EAX]; // EAX = signext(AX)
def CWD : I0x99, RawFrm, (ops),
-{cwtd|cwd}, [], Imp[AX],[AX,DX]; // DX:AX = signext(AX)
+{cwtd|cwd}, [], Imp[AX],[AX,DX], OpSize; // DX:AX =
signext(AX)
def CDQ : I0x99, RawFrm, (ops),
{cltd|cdq}, [], Imp[EAX],[EAX,EDX]; // EDX:EAX = signext(EAX)
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[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/Alpha:
AlphaISelDAGToDAG.cpp updated: 1.66 - 1.67
---
Log message:
Fix unordered fp on alpha
---
Diffs of the changes: (+35 -15)
AlphaISelDAGToDAG.cpp | 50 +++---
1 files changed, 35 insertions(+), 15 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.66
llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.67
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.66Fri Jan 19 15:13:56 2007
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Wed Jan 24 12:43:14 2007
@@ -350,30 +350,50 @@
case ISD::SETCC:
if (MVT::isFloatingPoint(N-getOperand(0).Val-getValueType(0))) {
- unsigned Opc = Alpha::WTF;
ISD::CondCode CC = castCondCodeSDNode(N-getOperand(2))-get();
+
+ unsigned Opc = Alpha::WTF;
bool rev = false;
- bool isNE = false;
+ bool inv = false;
switch(CC) {
default: DEBUG(N-dump()); assert(0 Unknown FP comparison!);
- case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ: Opc =
Alpha::CMPTEQ; break;
- case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT: Opc =
Alpha::CMPTLT; break;
- case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE: Opc =
Alpha::CMPTLE; break;
- case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT: Opc =
Alpha::CMPTLT; rev = true; break;
- case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE: Opc =
Alpha::CMPTLE; rev = true; break;
- case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE: Opc =
Alpha::CMPTEQ; isNE = true; break;
+ case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
+ Opc = Alpha::CMPTEQ; break;
+ case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT:
+ Opc = Alpha::CMPTLT; break;
+ case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE:
+ Opc = Alpha::CMPTLE; break;
+ case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT:
+ Opc = Alpha::CMPTLT; rev = true; break;
+ case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE:
+ Opc = Alpha::CMPTLE; rev = true; break;
+ case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE:
+ Opc = Alpha::CMPTEQ; inv = true; break;
+ case ISD::SETO:
+ Opc = Alpha::CMPTUN; inv = true; break;
+ case ISD::SETUO:
+ Opc = Alpha::CMPTUN; break;
};
- SDOperand tmp1 = N-getOperand(0);
- SDOperand tmp2 = N-getOperand(1);
+ SDOperand tmp1 = N-getOperand(rev?1:0);
+ SDOperand tmp2 = N-getOperand(rev?0:1);
AddToISelQueue(tmp1);
AddToISelQueue(tmp2);
- SDNode *cmp = CurDAG-getTargetNode(Opc, MVT::f64,
- rev?tmp2:tmp1,
- rev?tmp1:tmp2);
- if (isNE)
+ SDNode *cmp = CurDAG-getTargetNode(Opc, MVT::f64, tmp1, tmp2);
+ if (inv)
cmp = CurDAG-getTargetNode(Alpha::CMPTEQ, MVT::f64, SDOperand(cmp,
0),
CurDAG-getRegister(Alpha::F31, MVT::f64));
-
+ switch(CC) {
+ case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
+ case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE:
+ {
+ SDNode* cmp2 = CurDAG-getTargetNode(Alpha::CMPTUN, MVT::f64, tmp1,
tmp2);
+ cmp = CurDAG-getTargetNode(Alpha::ADDT, MVT::f64,
+ SDOperand(cmp2, 0), SDOperand(cmp, 0));
+ break;
+ }
+ default: break;
+ }
+
SDOperand LD;
if (AlphaLowering.hasITOF()) {
LD = CurDAG-getNode(AlphaISD::FTOIT_, MVT::i64, SDOperand(cmp, 0));
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target: MRegisterInfo.h updated: 1.87 - 1.88 --- Log message: Repair debug frames as a prelude to eh_frames. Switched to using MachineMoves by value so that clean up is less confusing (these vectors tend to be small.) --- Diffs of the changes: (+1 -1) MRegisterInfo.h |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/Target/MRegisterInfo.h diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.87 llvm/include/llvm/Target/MRegisterInfo.h:1.88 --- llvm/include/llvm/Target/MRegisterInfo.h:1.87 Mon Jan 22 18:51:23 2007 +++ llvm/include/llvm/Target/MRegisterInfo.hWed Jan 24 12:45:12 2007 @@ -456,7 +456,7 @@ /// getInitialFrameState - Returns a list of machine moves that are assumed /// on entry to all functions. Note that LabelID is ignored (assumed to be /// the beginning of the function.) - virtual void getInitialFrameState(std::vectorMachineMove * Moves) const; + virtual void getInitialFrameState(std::vectorMachineMove Moves) const; }; // This is useful when building DenseMaps keyed on virtual registers ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineDebugInfo.h MachineLocation.h
Changes in directory llvm/include/llvm/CodeGen:
MachineDebugInfo.h updated: 1.47 - 1.48
MachineLocation.h updated: 1.2 - 1.3
---
Log message:
Repair debug frames as a prelude to eh_frames. Switched to using MachineMoves
by value so that clean up is less confusing (these vectors tend to be small.)
---
Diffs of the changes: (+10 -4)
MachineDebugInfo.h |4 ++--
MachineLocation.h | 10 --
2 files changed, 10 insertions(+), 4 deletions(-)
Index: llvm/include/llvm/CodeGen/MachineDebugInfo.h
diff -u llvm/include/llvm/CodeGen/MachineDebugInfo.h:1.47
llvm/include/llvm/CodeGen/MachineDebugInfo.h:1.48
--- llvm/include/llvm/CodeGen/MachineDebugInfo.h:1.47 Thu Nov 30 08:35:45 2006
+++ llvm/include/llvm/CodeGen/MachineDebugInfo.hWed Jan 24 12:45:12 2007
@@ -985,7 +985,7 @@
// FrameMoves - List of moves done by a function's prolog. Used to construct
// frame maps by debug consumers.
- std::vectorMachineMove * FrameMoves;
+ std::vectorMachineMove FrameMoves;
public:
MachineDebugInfo();
@@ -1145,7 +1145,7 @@
/// getFrameMoves - Returns a reference to a list of moves done in the
current
/// function's prologue. Used to construct frame maps for debug comsumers.
- std::vectorMachineMove * getFrameMoves() { return FrameMoves; }
+ std::vectorMachineMove getFrameMoves() { return FrameMoves; }
}; // End class MachineDebugInfo
Index: llvm/include/llvm/CodeGen/MachineLocation.h
diff -u llvm/include/llvm/CodeGen/MachineLocation.h:1.2
llvm/include/llvm/CodeGen/MachineLocation.h:1.3
--- llvm/include/llvm/CodeGen/MachineLocation.h:1.2 Fri Apr 7 11:34:45 2006
+++ llvm/include/llvm/CodeGen/MachineLocation.h Wed Jan 24 12:45:12 2007
@@ -79,10 +79,16 @@
unsigned LabelID; // Label ID number for post-instruction
// address when result of move takes
// effect.
- const MachineLocation Destination;// Move to location.
- const MachineLocation Source; // Move from location.
+ MachineLocation Destination; // Move to location.
+ MachineLocation Source; // Move from location.
public:
+ MachineMove()
+ : LabelID(0)
+ , Destination()
+ , Source()
+ {}
+
MachineMove(unsigned ID, MachineLocation D, MachineLocation S)
: LabelID(ID)
, Destination(D)
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[llvm-commits] CVS: llvm/lib/Target/MRegisterInfo.cpp
Changes in directory llvm/lib/Target:
MRegisterInfo.cpp updated: 1.17 - 1.18
---
Log message:
Repair debug frames as a prelude to eh_frames. Switched to using MachineMoves
by value so that clean up is less confusing (these vectors tend to be small.)
---
Diffs of the changes: (+1 -1)
MRegisterInfo.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/MRegisterInfo.cpp
diff -u llvm/lib/Target/MRegisterInfo.cpp:1.17
llvm/lib/Target/MRegisterInfo.cpp:1.18
--- llvm/lib/Target/MRegisterInfo.cpp:1.17 Fri Nov 17 15:19:15 2006
+++ llvm/lib/Target/MRegisterInfo.cpp Wed Jan 24 12:45:13 2007
@@ -64,7 +64,7 @@
/// getInitialFrameState - Returns a list of machine moves that are assumed
/// on entry to a function.
void
-MRegisterInfo::getInitialFrameState(std::vectorMachineMove * Moves) const {
+MRegisterInfo::getInitialFrameState(std::vectorMachineMove Moves) const {
// Default is to do nothing.
}
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[llvm-commits] CVS: llvm/lib/CodeGen/DwarfWriter.cpp MachineDebugInfo.cpp
Changes in directory llvm/lib/CodeGen:
DwarfWriter.cpp updated: 1.112 - 1.113
MachineDebugInfo.cpp updated: 1.69 - 1.70
---
Log message:
Repair debug frames as a prelude to eh_frames. Switched to using MachineMoves
by value so that clean up is less confusing (these vectors tend to be small.)
---
Diffs of the changes: (+28 -16)
DwarfWriter.cpp | 43 ---
MachineDebugInfo.cpp |1 -
2 files changed, 28 insertions(+), 16 deletions(-)
Index: llvm/lib/CodeGen/DwarfWriter.cpp
diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.112
llvm/lib/CodeGen/DwarfWriter.cpp:1.113
--- llvm/lib/CodeGen/DwarfWriter.cpp:1.112 Wed Jan 24 07:12:32 2007
+++ llvm/lib/CodeGen/DwarfWriter.cppWed Jan 24 12:45:13 2007
@@ -2112,16 +2112,25 @@
/// EmitFrameMoves - Emit frame instructions to describe the layout of the
/// frame.
void EmitFrameMoves(const char *BaseLabel, unsigned BaseLabelID,
- std::vectorMachineMove * Moves) {
+ std::vectorMachineMove Moves) {
+int stackGrowth =
+Asm-TM.getFrameInfo()-getStackGrowthDirection() ==
+ TargetFrameInfo::StackGrowsUp ?
+TAI-getAddressSize() : -TAI-getAddressSize();
+
for (unsigned i = 0, N = Moves.size(); i N; ++i) {
- MachineMove *Move = Moves[i];
- unsigned LabelID = DebugInfo-MappedLabel(Move-getLabelID());
+ MachineMove Move = Moves[i];
+ unsigned LabelID = Move.getLabelID();
- // Throw out move if the label is invalid.
- if (!LabelID) continue;
+ if (LabelID) {
+LabelID = DebugInfo-MappedLabel(LabelID);
- const MachineLocation Dst = Move-getDestination();
- const MachineLocation Src = Move-getSource();
+// Throw out move if the label is invalid.
+if (!LabelID) continue;
+ }
+
+ const MachineLocation Dst = Move.getDestination();
+ const MachineLocation Src = Move.getSource();
// Advance row if new location.
if (BaseLabel LabelID BaseLabelID != LabelID) {
@@ -2134,11 +2143,6 @@
BaseLabel = loc;
}
- int stackGrowth =
- Asm-TM.getFrameInfo()-getStackGrowthDirection() ==
-TargetFrameInfo::StackGrowsUp ?
- TAI-getAddressSize() : -TAI-getAddressSize();
-
// If advancing cfa.
if (Dst.isRegister() Dst.getRegister() == MachineLocation::VirtualFP)
{
if (!Src.isRegister()) {
@@ -2159,6 +2163,16 @@
} else {
assert(0 Machine move no supported yet.);
}
+ } else if (Src.isRegister()
+Src.getRegister() == MachineLocation::VirtualFP) {
+if (Dst.isRegister()) {
+ EmitInt8(DW_CFA_def_cfa_register);
+ EOL(DW_CFA_def_cfa_register);
+ EmitULEB128Bytes(RI-getDwarfRegNum(Dst.getRegister()));
+ EOL(Register);
+} else {
+ assert(0 Machine move no supported yet.);
+}
} else {
unsigned Reg = RI-getDwarfRegNum(Src.getRegister());
int Offset = Dst.getOffset() / stackGrowth;
@@ -2433,10 +2447,9 @@
EmitSLEB128Bytes(stackGrowth); EOL(CIE Data Alignment Factor);
EmitInt8(RI-getDwarfRegNum(RI-getRARegister())); EOL(CIE RA Column);
-std::vectorMachineMove * Moves;
+std::vectorMachineMove Moves;
RI-getInitialFrameState(Moves);
EmitFrameMoves(NULL, 0, Moves);
-for (unsigned i = 0, N = Moves.size(); i N; ++i) delete Moves[i];
Asm-EmitAlignment(2);
EmitLabel(frame_common_end, 0);
@@ -2467,7 +2480,7 @@
func_begin, SubprogramCount);
EOL(FDE address range);
-std::vectorMachineMove * Moves = DebugInfo-getFrameMoves();
+std::vectorMachineMove Moves = DebugInfo-getFrameMoves();
EmitFrameMoves(func_begin, SubprogramCount, Moves);
Index: llvm/lib/CodeGen/MachineDebugInfo.cpp
diff -u llvm/lib/CodeGen/MachineDebugInfo.cpp:1.69
llvm/lib/CodeGen/MachineDebugInfo.cpp:1.70
--- llvm/lib/CodeGen/MachineDebugInfo.cpp:1.69 Thu Jan 11 22:24:45 2007
+++ llvm/lib/CodeGen/MachineDebugInfo.cpp Wed Jan 24 12:45:13 2007
@@ -1505,7 +1505,6 @@
}
// Clean up frame info.
- for (unsigned i = 0, N = FrameMoves.size(); i N; ++i) delete FrameMoves[i];
FrameMoves.clear();
}
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.96 - 1.97
PPCRegisterInfo.h updated: 1.22 - 1.23
---
Log message:
Repair debug frames as a prelude to eh_frames. Switched to using MachineMoves
by value so that clean up is less confusing (these vectors tend to be small.)
---
Diffs of the changes: (+44 -16)
PPCRegisterInfo.cpp | 58 ++--
PPCRegisterInfo.h |2 -
2 files changed, 44 insertions(+), 16 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.96
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.97
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.96Mon Jan 22 18:55:21 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Wed Jan 24 12:45:13 2007
@@ -762,6 +762,10 @@
MachineFrameInfo *MFI = MF.getFrameInfo();
MachineDebugInfo *DebugInfo = MFI-getMachineDebugInfo();
+ // Prepare for debug frame info.
+ bool hasInfo = DebugInfo DebugInfo-hasInfo();
+ unsigned FrameLabelId = 0;
+
// Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
// process it.
for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
@@ -821,6 +825,12 @@
unsigned TargetAlign = MF.getTarget().getFrameInfo()-getStackAlignment();
unsigned MaxAlign = MFI-getMaxAlignment();
+ if (hasInfo) {
+// Mark effective beginning of when frame pointer becomes valid.
+FrameLabelId = DebugInfo-NextLabelID();
+BuildMI(MBB, MBBI, TII.get(PPC::DWARF_LABEL)).addImm(FrameLabelId);
+ }
+
// Adjust stack pointer: r1 += NegFrameSize.
// If there is a preferred stack alignment, align R1 now
if (!IsPPC64) {
@@ -866,26 +876,44 @@
}
}
- if (DebugInfo DebugInfo-hasInfo()) {
-std::vectorMachineMove * Moves = DebugInfo-getFrameMoves();
-unsigned LabelID = DebugInfo-NextLabelID();
+ if (hasInfo) {
+std::vectorMachineMove Moves = DebugInfo-getFrameMoves();
-// Mark effective beginning of when frame pointer becomes valid.
-BuildMI(MBB, MBBI, TII.get(PPC::DWARF_LABEL)).addImm(LabelID);
+if (NegFrameSize) {
+ // Show update of SP.
+ MachineLocation SPDst(MachineLocation::VirtualFP);
+ MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
+ Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
+} else {
+ MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
+ Moves.push_back(MachineMove(FrameLabelId, SP, SP));
+}
-// Show update of SP.
-MachineLocation SPDst(MachineLocation::VirtualFP);
-MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
-Moves.push_back(new MachineMove(LabelID, SPDst, SPSrc));
+if (HasFP) {
+ MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
+ MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
+ Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
+}
// Add callee saved registers to move list.
const std::vectorCalleeSavedInfo CSI = MFI-getCalleeSavedInfo();
for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
- MachineLocation CSDst(MachineLocation::VirtualFP,
-MFI-getObjectOffset(CSI[I].getFrameIdx()));
- MachineLocation CSSrc(CSI[I].getReg());
- Moves.push_back(new MachineMove(LabelID, CSDst, CSSrc));
+ int Offset = MFI-getObjectOffset(CSI[I].getFrameIdx());
+ unsigned Reg = CSI[I].getReg();
+ if (Reg == PPC::LR || Reg == PPC::LR8) continue;
+ MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
+ MachineLocation CSSrc(Reg);
+ Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
}
+
+// Mark effective beginning of when frame pointer is ready.
+unsigned ReadyLabelId = DebugInfo-NextLabelID();
+BuildMI(MBB, MBBI, TII.get(PPC::DWARF_LABEL)).addImm(ReadyLabelId);
+
+MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
+ (IsPPC64 ? PPC::X1 : PPC::R1));
+MachineLocation FPSrc(MachineLocation::VirtualFP);
+Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
}
// If there is a frame pointer, copy R1 into R31
@@ -983,12 +1011,12 @@
return hasFP(MF) ? PPC::X31 : PPC::X1;
}
-void PPCRegisterInfo::getInitialFrameState(std::vectorMachineMove * Moves)
+void PPCRegisterInfo::getInitialFrameState(std::vectorMachineMove Moves)
const
{
// Initial state of the frame pointer is R1.
MachineLocation Dst(MachineLocation::VirtualFP);
MachineLocation Src(PPC::R1, 0);
- Moves.push_back(new MachineMove(0, Dst, Src));
+ Moves.push_back(MachineMove(0, Dst, Src));
}
#include PPCGenRegisterInfo.inc
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.22
llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.23
---
[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.cpp updated: 1.194 - 1.195
---
Log message:
80 columns
---
Diffs of the changes: (+8 -4)
X86RegisterInfo.cpp | 12
1 files changed, 8 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.194
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.195
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.194 Tue Jan 23 03:38:11 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Wed Jan 24 12:50:57 2007
@@ -926,7 +926,8 @@
unsigned Opc = (Amount 128) ?
(Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
(Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
- New = BuildMI(TII.get(Opc),
StackPtr).addReg(StackPtr).addImm(Amount);
+ New = BuildMI(TII.get(Opc), StackPtr)
+.addReg(StackPtr).addImm(Amount);
}
}
@@ -1044,7 +1045,8 @@
// If it's main() on Cygwin\Mingw32 we should align stack as well
if (Fn-hasExternalLinkage() Fn-getName() == main
Subtarget-isTargetCygMing()) {
-MI= BuildMI(TII.get(X86::AND32ri),
X86::ESP).addReg(X86::ESP).addImm(-Align);
+MI= BuildMI(TII.get(X86::AND32ri), X86::ESP)
+.addReg(X86::ESP).addImm(-Align);
MBB.insert(MBBI, MI);
// Probe the stack
@@ -1104,12 +1106,14 @@
unsigned Opc = (NumBytes 128) ?
(Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
(Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
-BuildMI(MBB, MBBI, TII.get(Opc),
StackPtr).addReg(StackPtr).addImm(NumBytes);
+BuildMI(MBB, MBBI, TII.get(Opc), StackPtr)
+.addReg(StackPtr).addImm(NumBytes);
} else if ((int)NumBytes 0) {
unsigned Opc = (-NumBytes 128) ?
(Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
-BuildMI(MBB, MBBI, TII.get(Opc),
StackPtr).addReg(StackPtr).addImm(-NumBytes);
+BuildMI(MBB, MBBI, TII.get(Opc), StackPtr)
+.addReg(StackPtr).addImm(-NumBytes);
}
}
}
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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.h X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.h updated: 1.44 - 1.45
X86RegisterInfo.cpp updated: 1.195 - 1.196
---
Log message:
Call frames for intel.
---
Diffs of the changes: (+52 -0)
X86RegisterInfo.cpp | 51 +++
X86RegisterInfo.h |1 +
2 files changed, 52 insertions(+)
Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.44
llvm/lib/Target/X86/X86RegisterInfo.h:1.45
--- llvm/lib/Target/X86/X86RegisterInfo.h:1.44 Mon Jan 22 18:57:47 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.h Wed Jan 24 13:15:24 2007
@@ -94,6 +94,7 @@
// Debug information queries.
unsigned getRARegister() const;
unsigned getFrameRegister(MachineFunction MF) const;
+ void getInitialFrameState(std::vectorMachineMove Moves) const;
};
// getX86SubSuperRegister - X86 utility function. It returns the sub or super
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.195
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.196
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.195 Wed Jan 24 12:50:57 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Wed Jan 24 13:15:24 2007
@@ -995,6 +995,11 @@
const Function* Fn = MF.getFunction();
const X86Subtarget* Subtarget = MF.getTarget().getSubtargetX86Subtarget();
MachineInstr *MI;
+ MachineDebugInfo *DebugInfo = MFI-getMachineDebugInfo();
+
+ // Prepare for debug frame info.
+ bool hasInfo = DebugInfo DebugInfo-hasInfo();
+ unsigned FrameLabelId = 0;
// Get the number of bytes to allocate from the FrameInfo
unsigned NumBytes = MFI-getStackSize();
@@ -1018,6 +1023,12 @@
}
}
+ if (hasInfo) {
+// Mark effective beginning of when frame pointer becomes valid.
+FrameLabelId = DebugInfo-NextLabelID();
+BuildMI(MBB, MBBI, TII.get(X86::DWARF_LABEL)).addImm(FrameLabelId);
+ }
+
if (hasFP(MF)) {
// Get the offset of the stack slot for the EBP register... which is
// guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
@@ -1042,6 +1053,38 @@
MBB.insert(MBBI, MI);
}
+ if (hasInfo) {
+std::vectorMachineMove Moves = DebugInfo-getFrameMoves();
+
+if (NumBytes) {
+ // Show update of SP.
+ MachineLocation SPDst(MachineLocation::VirtualFP);
+ MachineLocation SPSrc(MachineLocation::VirtualFP, -NumBytes);
+ Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
+} else {
+ MachineLocation SP(StackPtr);
+ Moves.push_back(MachineMove(FrameLabelId, SP, SP));
+}
+
+// Add callee saved registers to move list.
+const std::vectorCalleeSavedInfo CSI = MFI-getCalleeSavedInfo();
+for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
+ int Offset = MFI-getObjectOffset(CSI[I].getFrameIdx());
+ unsigned Reg = CSI[I].getReg();
+ MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
+ MachineLocation CSSrc(Reg);
+ Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
+}
+
+// Mark effective beginning of when frame pointer is ready.
+unsigned ReadyLabelId = DebugInfo-NextLabelID();
+BuildMI(MBB, MBBI, TII.get(X86::DWARF_LABEL)).addImm(ReadyLabelId);
+
+MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
+MachineLocation FPSrc(MachineLocation::VirtualFP);
+Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
+ }
+
// If it's main() on Cygwin\Mingw32 we should align stack as well
if (Fn-hasExternalLinkage() Fn-getName() == main
Subtarget-isTargetCygMing()) {
@@ -1127,6 +1170,14 @@
return hasFP(MF) ? FramePtr : StackPtr;
}
+void X86RegisterInfo::getInitialFrameState(std::vectorMachineMove Moves)
+ const
{
+ // Initial state of the frame pointer is esp.
+ MachineLocation Dst(MachineLocation::VirtualFP);
+ MachineLocation Src(StackPtr, 0);
+ Moves.push_back(MachineMove(0, Dst, Src));
+}
+
namespace llvm {
unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
switch (VT) {
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Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.h X86RegisterInfo.cpp
Evan and Reid - feel free to tweak this. It shouldn't introduce
problems.
On 24-Jan-07, at 03:15 PM, Jim Laskey wrote:
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.h updated: 1.44 - 1.45
X86RegisterInfo.cpp updated: 1.195 - 1.196
---
Log message:
Call frames for intel.
---
Diffs of the changes: (+52 -0)
X86RegisterInfo.cpp | 51
+++
X86RegisterInfo.h |1 +
2 files changed, 52 insertions(+)
Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.44 llvm/lib/Target/
X86/X86RegisterInfo.h:1.45
--- llvm/lib/Target/X86/X86RegisterInfo.h:1.44 Mon Jan 22 18:57:47
2007
+++ llvm/lib/Target/X86/X86RegisterInfo.h Wed Jan 24 13:15:24 2007
@@ -94,6 +94,7 @@
// Debug information queries.
unsigned getRARegister() const;
unsigned getFrameRegister(MachineFunction MF) const;
+ void getInitialFrameState(std::vectorMachineMove Moves) const;
};
// getX86SubSuperRegister - X86 utility function. It returns the
sub or super
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.195 llvm/lib/
Target/X86/X86RegisterInfo.cpp:1.196
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.195 Wed Jan 24
12:50:57 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Wed Jan 24 13:15:24 2007
@@ -995,6 +995,11 @@
const Function* Fn = MF.getFunction();
const X86Subtarget* Subtarget = MF.getTarget
().getSubtargetX86Subtarget();
MachineInstr *MI;
+ MachineDebugInfo *DebugInfo = MFI-getMachineDebugInfo();
+
+ // Prepare for debug frame info.
+ bool hasInfo = DebugInfo DebugInfo-hasInfo();
+ unsigned FrameLabelId = 0;
// Get the number of bytes to allocate from the FrameInfo
unsigned NumBytes = MFI-getStackSize();
@@ -1018,6 +1023,12 @@
}
}
+ if (hasInfo) {
+// Mark effective beginning of when frame pointer becomes valid.
+FrameLabelId = DebugInfo-NextLabelID();
+BuildMI(MBB, MBBI, TII.get(X86::DWARF_LABEL)).addImm
(FrameLabelId);
+ }
+
if (hasFP(MF)) {
// Get the offset of the stack slot for the EBP register...
which is
// guaranteed to be the last slot by
processFunctionBeforeFrameFinalized.
@@ -1042,6 +1053,38 @@
MBB.insert(MBBI, MI);
}
+ if (hasInfo) {
+std::vectorMachineMove Moves = DebugInfo-getFrameMoves();
+
+if (NumBytes) {
+ // Show update of SP.
+ MachineLocation SPDst(MachineLocation::VirtualFP);
+ MachineLocation SPSrc(MachineLocation::VirtualFP, -NumBytes);
+ Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
+} else {
+ MachineLocation SP(StackPtr);
+ Moves.push_back(MachineMove(FrameLabelId, SP, SP));
+}
+
+// Add callee saved registers to move list.
+const std::vectorCalleeSavedInfo CSI = MFI-
getCalleeSavedInfo();
+for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
+ int Offset = MFI-getObjectOffset(CSI[I].getFrameIdx());
+ unsigned Reg = CSI[I].getReg();
+ MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
+ MachineLocation CSSrc(Reg);
+ Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
+}
+
+// Mark effective beginning of when frame pointer is ready.
+unsigned ReadyLabelId = DebugInfo-NextLabelID();
+BuildMI(MBB, MBBI, TII.get(X86::DWARF_LABEL)).addImm
(ReadyLabelId);
+
+MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
+MachineLocation FPSrc(MachineLocation::VirtualFP);
+Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
+ }
+
// If it's main() on Cygwin\Mingw32 we should align stack as well
if (Fn-hasExternalLinkage() Fn-getName() == main
Subtarget-isTargetCygMing()) {
@@ -1127,6 +1170,14 @@
return hasFP(MF) ? FramePtr : StackPtr;
}
+void X86RegisterInfo::getInitialFrameState
(std::vectorMachineMove Moves)
+
const {
+ // Initial state of the frame pointer is esp.
+ MachineLocation Dst(MachineLocation::VirtualFP);
+ MachineLocation Src(StackPtr, 0);
+ Moves.push_back(MachineMove(0, Dst, Src));
+}
+
namespace llvm {
unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT,
bool High) {
switch (VT) {
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[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Integer/arith.c field.c offset.reference_output union-struct.c union2.c union2.reference_output
Changes in directory llvm-test/SingleSource/UnitTests/Integer:
arith.c updated: 1.6 - 1.7
field.c updated: 1.5 - 1.6
offset.reference_output updated: 1.1 - 1.2
union-struct.c updated: 1.6 - 1.7
union2.c updated: 1.5 - 1.6
union2.reference_output updated: 1.1 - 1.2
---
Log message:
We changed the outputs and reference outputs for these programs. This is mainly
because the memory layout for bit-accurate types. For a n bit int type, it will
occupy m bits where m is the nearest large number of power of 2.
---
Diffs of the changes: (+39 -19)
arith.c |2 +-
field.c | 28 ++--
offset.reference_output |2 +-
union-struct.c |2 +-
union2.c| 21 +++--
union2.reference_output |3 +++
6 files changed, 39 insertions(+), 19 deletions(-)
Index: llvm-test/SingleSource/UnitTests/Integer/arith.c
diff -u llvm-test/SingleSource/UnitTests/Integer/arith.c:1.6
llvm-test/SingleSource/UnitTests/Integer/arith.c:1.7
--- llvm-test/SingleSource/UnitTests/Integer/arith.c:1.6Mon Jan 22
18:17:21 2007
+++ llvm-test/SingleSource/UnitTests/Integer/arith.cWed Jan 24 14:39:44 2007
@@ -43,7 +43,7 @@
l = j / k;
temp = l;
printf( temp = %hd\n, temp);
- j *= (-176);
+ j *= (-176); // after truncation, the value should be -384
l = j / k;
temp = l;
printf( temp = %hd\n, temp);
Index: llvm-test/SingleSource/UnitTests/Integer/field.c
diff -u llvm-test/SingleSource/UnitTests/Integer/field.c:1.5
llvm-test/SingleSource/UnitTests/Integer/field.c:1.6
--- llvm-test/SingleSource/UnitTests/Integer/field.c:1.5Mon Jan 22
18:17:21 2007
+++ llvm-test/SingleSource/UnitTests/Integer/field.cWed Jan 24 14:39:44 2007
@@ -9,6 +9,8 @@
// data layout of the field should be the same as the corresponding
// struct using bit accurate types.
//
+// Note: we assume that sizeof(x-bit int) = round up x to the most
+// nearest 2^n.
//===--===//
@@ -24,9 +26,9 @@
typedef char __attribute__ ((bitwidth(7))) char7;
typedef short __attribute__ ((bitwidth(17))) short17;
-typedef struct myStruct{int i; unsigned char c:7; int s:17; char c2;} myStruct;
+typedef struct myStruct{int i; char c:7; int s:17; char c2;} myStruct;
-typedef struct myStruct2{int32 i; int7 c; int17 s; int8 c2;} myStruct2;
+typedef struct myStruct2{int32 i; int17 s; int7 c; int8 c2;} myStruct2;
int main()
{
@@ -36,20 +38,26 @@
void* ptr, *ptr1, *ptr2, *ptr3;
unsigned int offset, offset1;
- ptr = (x.i);
- ptr1 = (x.c2);
+ // ptr = (x.i);
+ // ptr1 = (x.c2);
ptr2 = (y.i);
ptr3 = (y.c2);
- offset = ptr1 - ptr;
+ //offset = ptr1 - ptr;
offset1 = ptr3 - ptr2;
- if(offset != offset1)
-printf(error: offset=%x, offset1=%x\n, offset, offset1);
- if(sizeof(myStruct) != sizeof(myStruct2))
-printf(error2: sizeof myStruct = %d, sizeof myStruct2 = %d\n,
- sizeof(myStruct), sizeof(myStruct2));
+ if(offset1 != 2*sizeof(int) + sizeof(char))
+printf(error: offset1=%x\n, offset1);
+
+ x.c = -1;
+ y.c = -1;
+ if(x.c != y.c)
+printf(error: x.c = %x, y.c = %x\n, x.c, y.c);
+
+ //if(sizeof(myStruct) != sizeof(myStruct2))
+ // printf(error2: sizeof myStruct = %d, sizeof myStruct2 = %d\n,
+ // sizeof(myStruct), sizeof(myStruct2));
return 0;
}
Index: llvm-test/SingleSource/UnitTests/Integer/offset.reference_output
diff -u llvm-test/SingleSource/UnitTests/Integer/offset.reference_output:1.1
llvm-test/SingleSource/UnitTests/Integer/offset.reference_output:1.2
--- llvm-test/SingleSource/UnitTests/Integer/offset.reference_output:1.1
Thu Jan 18 20:22:46 2007
+++ llvm-test/SingleSource/UnitTests/Integer/offset.reference_outputWed Jan
24 14:39:44 2007
@@ -1,2 +1,2 @@
-5
+8
exit 0
Index: llvm-test/SingleSource/UnitTests/Integer/union-struct.c
diff -u llvm-test/SingleSource/UnitTests/Integer/union-struct.c:1.6
llvm-test/SingleSource/UnitTests/Integer/union-struct.c:1.7
--- llvm-test/SingleSource/UnitTests/Integer/union-struct.c:1.6 Mon Jan 22
18:17:21 2007
+++ llvm-test/SingleSource/UnitTests/Integer/union-struct.c Wed Jan 24
14:39:44 2007
@@ -27,7 +27,7 @@
int main()
{
- if( sizeof(struct Blend_Map_Entry) == 5 * sizeof(int) )
+ if( sizeof(struct Blend_Map_Entry) != 5 * sizeof(int) )
printf(error: %d\n, sizeof(struct Blend_Map_Entry));
return 0;
}
Index: llvm-test/SingleSource/UnitTests/Integer/union2.c
diff -u llvm-test/SingleSource/UnitTests/Integer/union2.c:1.5
llvm-test/SingleSource/UnitTests/Integer/union2.c:1.6
--- llvm-test/SingleSource/UnitTests/Integer/union2.c:1.5 Mon Jan 22
18:17:21 2007
+++ llvm-test/SingleSource/UnitTests/Integer/union2.c Wed Jan 24 14:39:44 2007
@@ -8,6 +8,10 @@
// This is a test for union type. By assigning values to different
// fields, we can check whether the assignment is correctly performed.
//
+// Note:
[llvm-commits] CVS: llvm/lib/Target/Alpha/Alpha.td AlphaAsmPrinter.cpp AlphaISelDAGToDAG.cpp AlphaISelLowering.cpp AlphaISelLowering.h AlphaInstrInfo.td AlphaSubtarget.cpp AlphaSubtarget.h
Changes in directory llvm/lib/Target/Alpha:
Alpha.td updated: 1.11 - 1.12
AlphaAsmPrinter.cpp updated: 1.61 - 1.62
AlphaISelDAGToDAG.cpp updated: 1.67 - 1.68
AlphaISelLowering.cpp updated: 1.76 - 1.77
AlphaISelLowering.h updated: 1.23 - 1.24
AlphaInstrInfo.td updated: 1.136 - 1.137
AlphaSubtarget.cpp updated: 1.7 - 1.8
AlphaSubtarget.h updated: 1.5 - 1.6
---
Log message:
FTOIT and ITOFT are bit converts, and if we drop 21264s, are always available
---
Diffs of the changes: (+17 -73)
Alpha.td |8 ++--
AlphaAsmPrinter.cpp |7 +++
AlphaISelDAGToDAG.cpp | 35 ---
AlphaISelLowering.cpp | 27 ---
AlphaISelLowering.h |2 +-
AlphaInstrInfo.td |6 ++
AlphaSubtarget.cpp|2 +-
AlphaSubtarget.h |3 ---
8 files changed, 17 insertions(+), 73 deletions(-)
Index: llvm/lib/Target/Alpha/Alpha.td
diff -u llvm/lib/Target/Alpha/Alpha.td:1.11 llvm/lib/Target/Alpha/Alpha.td:1.12
--- llvm/lib/Target/Alpha/Alpha.td:1.11 Wed May 17 19:11:53 2006
+++ llvm/lib/Target/Alpha/Alpha.td Wed Jan 24 15:09:16 2007
@@ -22,8 +22,6 @@
def FeatureCIX : SubtargetFeatureCIX, HasCT, true,
Enable CIX extentions;
-def FeatureFIX : SubtargetFeatureFIX, HasF2I, true,
- Enable FIX extentions;
//===--===//
// Register File Description
@@ -54,10 +52,8 @@
//===--===//
def : Processorgeneric, Alpha21264Itineraries, [];
-def : Processorpca56 , Alpha21264Itineraries, [];
-def : Processorev56 , Alpha21264Itineraries, [];
-def : Processorev6, Alpha21264Itineraries, [FeatureFIX];
-def : Processorev67 , Alpha21264Itineraries, [FeatureFIX, FeatureCIX];
+def : Processorev6, Alpha21264Itineraries, [];
+def : Processorev67 , Alpha21264Itineraries, [FeatureCIX];
//===--===//
// The Alpha Target
Index: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
diff -u llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.61
llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.62
--- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.61 Wed Jan 24 01:03:39 2007
+++ llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp Wed Jan 24 15:09:16 2007
@@ -190,11 +190,10 @@
bool AlphaAsmPrinter::doInitialization(Module M)
{
AsmPrinter::doInitialization(M);
- if(TM.getSubtargetAlphaSubtarget().hasF2I()
- || TM.getSubtargetAlphaSubtarget().hasCT())
-O \t.arch ev6\n;
+ if(TM.getSubtargetAlphaSubtarget().hasCT())
+O \t.arch ev6\n; //This might need to be ev67, so leave this test here
else
-O \t.arch ev56\n;
+O \t.arch ev6\n;
O \t.set noat\n;
return false;
}
Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.67
llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.68
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.67Wed Jan 24 12:43:14 2007
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Wed Jan 24 15:09:16 2007
@@ -394,24 +394,10 @@
default: break;
}
- SDOperand LD;
- if (AlphaLowering.hasITOF()) {
-LD = CurDAG-getNode(AlphaISD::FTOIT_, MVT::i64, SDOperand(cmp, 0));
- } else {
-int FrameIdx =
- CurDAG-getMachineFunction().getFrameInfo()-CreateStackObject(8, 8);
-SDOperand FI = CurDAG-getFrameIndex(FrameIdx, MVT::i64);
-SDOperand ST =
- SDOperand(CurDAG-getTargetNode(Alpha::STT, MVT::Other,
- SDOperand(cmp, 0), FI,
- CurDAG-getRegister(Alpha::R31,
MVT::i64)), 0);
-LD = SDOperand(CurDAG-getTargetNode(Alpha::LDQ, MVT::i64, FI,
- CurDAG-getRegister(Alpha::R31,
MVT::i64),
- ST), 0);
- }
+ SDNode* LD = CurDAG-getTargetNode(Alpha::FTOIT, MVT::i64,
SDOperand(cmp, 0));
return CurDAG-getTargetNode(Alpha::CMPULT, MVT::i64,
CurDAG-getRegister(Alpha::R31, MVT::i64),
- LD);
+ SDOperand(LD,0));
}
break;
@@ -424,7 +410,6 @@
// so that things like this can be caught in fall though code
//move int to fp
bool isDouble = N-getValueType(0) == MVT::f64;
- SDOperand LD;
SDOperand cond = N-getOperand(0);
SDOperand TV = N-getOperand(1);
SDOperand FV = N-getOperand(2);
@@ -432,21 +417,9 @@
AddToISelQueue(TV);
AddToISelQueue(FV);
- if (AlphaLowering.hasITOF()) {
- LD = CurDAG-getNode(AlphaISD::ITOFT_, MVT::f64, cond);
- } else {
- int FrameIdx =
- CurDAG-getMachineFunction().getFrameInfo()-CreateStackObject(8, 8);
- SDOperand
Re: [llvm-commits] CVS: llvm/lib/Target/Alpha/Alpha.td AlphaAsmPrinter.cpp AlphaISelDAGToDAG.cpp AlphaISelLowering.cpp AlphaISelLowering.h AlphaInstrInfo.td AlphaSubtarget.cpp AlphaSubtarget.h
Err, um, I meant 21164. dropping 21264 would be bad...
On 1/24/07, Andrew Lenharth [EMAIL PROTECTED] wrote:
Changes in directory llvm/lib/Target/Alpha:
Alpha.td updated: 1.11 - 1.12
AlphaAsmPrinter.cpp updated: 1.61 - 1.62
AlphaISelDAGToDAG.cpp updated: 1.67 - 1.68
AlphaISelLowering.cpp updated: 1.76 - 1.77
AlphaISelLowering.h updated: 1.23 - 1.24
AlphaInstrInfo.td updated: 1.136 - 1.137
AlphaSubtarget.cpp updated: 1.7 - 1.8
AlphaSubtarget.h updated: 1.5 - 1.6
---
Log message:
FTOIT and ITOFT are bit converts, and if we drop 21264s, are always available
---
Diffs of the changes: (+17 -73)
Alpha.td |8 ++--
AlphaAsmPrinter.cpp |7 +++
AlphaISelDAGToDAG.cpp | 35 ---
AlphaISelLowering.cpp | 27 ---
AlphaISelLowering.h |2 +-
AlphaInstrInfo.td |6 ++
AlphaSubtarget.cpp|2 +-
AlphaSubtarget.h |3 ---
8 files changed, 17 insertions(+), 73 deletions(-)
Index: llvm/lib/Target/Alpha/Alpha.td
diff -u llvm/lib/Target/Alpha/Alpha.td:1.11
llvm/lib/Target/Alpha/Alpha.td:1.12
--- llvm/lib/Target/Alpha/Alpha.td:1.11 Wed May 17 19:11:53 2006
+++ llvm/lib/Target/Alpha/Alpha.td Wed Jan 24 15:09:16 2007
@@ -22,8 +22,6 @@
def FeatureCIX : SubtargetFeatureCIX, HasCT, true,
Enable CIX extentions;
-def FeatureFIX : SubtargetFeatureFIX, HasF2I, true,
- Enable FIX extentions;
//===--===//
// Register File Description
@@ -54,10 +52,8 @@
//===--===//
def : Processorgeneric, Alpha21264Itineraries, [];
-def : Processorpca56 , Alpha21264Itineraries, [];
-def : Processorev56 , Alpha21264Itineraries, [];
-def : Processorev6, Alpha21264Itineraries, [FeatureFIX];
-def : Processorev67 , Alpha21264Itineraries, [FeatureFIX, FeatureCIX];
+def : Processorev6, Alpha21264Itineraries, [];
+def : Processorev67 , Alpha21264Itineraries, [FeatureCIX];
//===--===//
// The Alpha Target
Index: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
diff -u llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.61
llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.62
--- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.61 Wed Jan 24 01:03:39
2007
+++ llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp Wed Jan 24 15:09:16 2007
@@ -190,11 +190,10 @@
bool AlphaAsmPrinter::doInitialization(Module M)
{
AsmPrinter::doInitialization(M);
- if(TM.getSubtargetAlphaSubtarget().hasF2I()
- || TM.getSubtargetAlphaSubtarget().hasCT())
-O \t.arch ev6\n;
+ if(TM.getSubtargetAlphaSubtarget().hasCT())
+O \t.arch ev6\n; //This might need to be ev67, so leave this test
here
else
-O \t.arch ev56\n;
+O \t.arch ev6\n;
O \t.set noat\n;
return false;
}
Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.67
llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.68
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.67Wed Jan 24 12:43:14
2007
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Wed Jan 24 15:09:16 2007
@@ -394,24 +394,10 @@
default: break;
}
- SDOperand LD;
- if (AlphaLowering.hasITOF()) {
-LD = CurDAG-getNode(AlphaISD::FTOIT_, MVT::i64, SDOperand(cmp, 0));
- } else {
-int FrameIdx =
- CurDAG-getMachineFunction().getFrameInfo()-CreateStackObject(8,
8);
-SDOperand FI = CurDAG-getFrameIndex(FrameIdx, MVT::i64);
-SDOperand ST =
- SDOperand(CurDAG-getTargetNode(Alpha::STT, MVT::Other,
- SDOperand(cmp, 0), FI,
- CurDAG-getRegister(Alpha::R31,
MVT::i64)), 0);
-LD = SDOperand(CurDAG-getTargetNode(Alpha::LDQ, MVT::i64, FI,
- CurDAG-getRegister(Alpha::R31,
MVT::i64),
- ST), 0);
- }
+ SDNode* LD = CurDAG-getTargetNode(Alpha::FTOIT, MVT::i64,
SDOperand(cmp, 0));
return CurDAG-getTargetNode(Alpha::CMPULT, MVT::i64,
CurDAG-getRegister(Alpha::R31, MVT::i64),
- LD);
+ SDOperand(LD,0));
}
break;
@@ -424,7 +410,6 @@
// so that things like this can be caught in fall though code
//move int to fp
bool isDouble = N-getValueType(0) == MVT::f64;
- SDOperand LD;
SDOperand cond = N-getOperand(0);
SDOperand TV = N-getOperand(1);
SDOperand FV = N-getOperand(2);
@@ -432,21 +417,9 @@
AddToISelQueue(TV);
AddToISelQueue(FV);
- if
[llvm-commits] CVS: llvm/test/CFrontend/2007-01-24-InlineAsmCModifier.c
Changes in directory llvm/test/CFrontend:
2007-01-24-InlineAsmCModifier.c added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+9 -0)
2007-01-24-InlineAsmCModifier.c |9 +
1 files changed, 9 insertions(+)
Index: llvm/test/CFrontend/2007-01-24-InlineAsmCModifier.c
diff -c /dev/null llvm/test/CFrontend/2007-01-24-InlineAsmCModifier.c:1.1
*** /dev/null Wed Jan 24 20:52:43 2007
--- llvm/test/CFrontend/2007-01-24-InlineAsmCModifier.c Wed Jan 24 20:52:33 2007
***
*** 0
--- 1,9
+ // Verify that the %c modifier works and strips off any prefixes from
immediates.
+ // RUN: %llvmgcc -S %s -o - | llvm-as | llc | grep 'pickANumber: 789514'
+
+ void foo() {
+ __asm__ volatile(/* pickANumber : %c0 */::i(0xC0C0A));
+
+ // Check that non-c modifiers work also (not greped for above).
+__asm__ volatile(/* pickANumber2 : %0 */::i(123));
+ }
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCAsmPrinter.cpp updated: 1.228 - 1.229
---
Log message:
Fix test/CFrontend/2007-01-24-InlineAsmCModifier.c on PPC
---
Diffs of the changes: (+4 -0)
PPCAsmPrinter.cpp |4
1 files changed, 4 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.228
llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.229
--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.228 Sun Jan 14 00:37:54 2007
+++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Wed Jan 24 20:52:50 2007
@@ -412,6 +412,10 @@
switch (ExtraCode[0]) {
default: return true; // Unknown modifier.
+case 'c': // Don't print $ before a global var name or constant.
+ // PPC never has a prefix.
+ printOperand(MI, OpNo);
+ return false;
case 'L': // Write second word of DImode reference.
// Verify that this operand has two consecutive registers.
if (!MI-getOperand(OpNo).isRegister() ||
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
Changes in directory llvm/lib/Target/X86:
X86ATTAsmPrinter.cpp updated: 1.93 - 1.94
---
Log message:
Fix test/CFrontend/2007-01-24-InlineAsmCModifier.c on X86. The %c modifier
says that no $ prefix should be emitted on X86.
---
Diffs of the changes: (+3 -2)
X86ATTAsmPrinter.cpp |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.93
llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.94
--- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.93 Thu Jan 18 16:27:12 2007
+++ llvm/lib/Target/X86/X86ATTAsmPrinter.cppWed Jan 24 20:53:24 2007
@@ -219,7 +219,8 @@
}
case MachineOperand::MO_Immediate:
-if (!Modifier || strcmp(Modifier, debug) != 0)
+if (!Modifier ||
+(strcmp(Modifier, debug) strcmp(Modifier, mem)))
O '$';
O MO.getImmedValue();
return;
@@ -491,7 +492,7 @@
switch (ExtraCode[0]) {
default: return true; // Unknown modifier.
-case 'c': // Don't print $ before a global var name.
+case 'c': // Don't print $ before a global var name or constant.
printOperand(MI, OpNo, mem);
return false;
case 'b': // Print QImode register
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMAsmPrinter.cpp ARMMachineFunctionInfo.h ARMRegisterInfo.h
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.46 - 1.47
ARMMachineFunctionInfo.h updated: 1.2 - 1.3
ARMRegisterInfo.h updated: 1.6 - 1.7
---
Log message:
Getting rid uses of evil std::set
---
Diffs of the changes: (+39 -23)
ARMAsmPrinter.cpp|1
ARMMachineFunctionInfo.h | 60 ++-
ARMRegisterInfo.h|1
3 files changed, 39 insertions(+), 23 deletions(-)
Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
diff -u llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.46
llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.47
--- llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.46 Tue Jan 23 16:59:13 2007
+++ llvm/lib/Target/ARM/ARMAsmPrinter.cpp Wed Jan 24 21:07:27 2007
@@ -37,7 +37,6 @@
#include llvm/Support/MathExtras.h
#include cctype
#include iostream
-#include set
using namespace llvm;
STATISTIC(EmittedInsts, Number of machine instrs printed);
Index: llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
diff -u llvm/lib/Target/ARM/ARMMachineFunctionInfo.h:1.2
llvm/lib/Target/ARM/ARMMachineFunctionInfo.h:1.3
--- llvm/lib/Target/ARM/ARMMachineFunctionInfo.h:1.2Fri Jan 19 20:09:25 2007
+++ llvm/lib/Target/ARM/ARMMachineFunctionInfo.hWed Jan 24 21:07:27 2007
@@ -60,9 +60,9 @@
/// GPRCS1Frames, GPRCS2Frames, DPRCSFrames - Keeps track of frame indices
/// which belong to these spill areas.
- std::setint GPRCS1Frames;
- std::setint GPRCS2Frames;
- std::setint DPRCSFrames;
+ std::vectorbool GPRCS1Frames;
+ std::vectorbool GPRCS2Frames;
+ std::vectorbool DPRCSFrames;
/// JumpTableUId - Unique id for jumptables.
///
@@ -107,24 +107,42 @@
void setGPRCalleeSavedArea2Size(unsigned s) { GPRCS2Size = s; }
void setDPRCalleeSavedAreaSize(unsigned s) { DPRCSSize = s; }
- bool isGPRCalleeSavedArea1Frame(unsigned fi) const {
-return GPRCS1Frames.count(fi);
- }
- bool isGPRCalleeSavedArea2Frame(unsigned fi) const {
-return GPRCS2Frames.count(fi);
- }
- bool isDPRCalleeSavedAreaFrame(unsigned fi) const {
-return DPRCSFrames.count(fi);
- }
-
- void addGPRCalleeSavedArea1Frame(unsigned fi) {
-GPRCS1Frames.insert(fi);
- }
- void addGPRCalleeSavedArea2Frame(unsigned fi) {
-GPRCS2Frames.insert(fi);
- }
- void addDPRCalleeSavedAreaFrame(unsigned fi) {
-DPRCSFrames.insert(fi);
+ bool isGPRCalleeSavedArea1Frame(int fi) const {
+if (fi 0 || fi = (int)GPRCS1Frames.size())
+ return false;
+return GPRCS1Frames[fi];
+ }
+ bool isGPRCalleeSavedArea2Frame(int fi) const {
+if (fi 0 || fi = (int)GPRCS2Frames.size())
+ return false;
+return GPRCS2Frames[fi];
+ }
+ bool isDPRCalleeSavedAreaFrame(int fi) const {
+if (fi 0 || fi = (int)DPRCSFrames.size())
+ return false;
+return DPRCSFrames[fi];
+ }
+
+ void addGPRCalleeSavedArea1Frame(int fi) {
+if (fi = 0) {
+ if (fi = (int)GPRCS1Frames.size())
+GPRCS1Frames.resize(fi+1);
+ GPRCS1Frames[fi] = true;
+}
+ }
+ void addGPRCalleeSavedArea2Frame(int fi) {
+if (fi = 0) {
+ if (fi = (int)GPRCS2Frames.size())
+GPRCS2Frames.resize(fi+1);
+ GPRCS2Frames[fi] = true;
+}
+ }
+ void addDPRCalleeSavedAreaFrame(int fi) {
+if (fi = 0) {
+ if (fi = (int)DPRCSFrames.size())
+DPRCSFrames.resize(fi+1);
+ DPRCSFrames[fi] = true;
+}
}
unsigned createJumpTableUId() {
Index: llvm/lib/Target/ARM/ARMRegisterInfo.h
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.h:1.6
llvm/lib/Target/ARM/ARMRegisterInfo.h:1.7
--- llvm/lib/Target/ARM/ARMRegisterInfo.h:1.6 Mon Jan 22 18:52:44 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.h Wed Jan 24 21:07:27 2007
@@ -17,7 +17,6 @@
#include llvm/Target/MRegisterInfo.h
#include ARMGenRegisterInfo.h.inc
-#include set
namespace llvm {
class TargetInstrInfo;
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
Changes in directory llvm/lib/Target/ARM:
ARMConstantIslandPass.cpp updated: 1.2 - 1.3
---
Log message:
Added (preliminary) branch shortening capability to constantpool island pass.
---
Diffs of the changes: (+130 -7)
ARMConstantIslandPass.cpp | 137 +++---
1 files changed, 130 insertions(+), 7 deletions(-)
Index: llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
diff -u llvm/lib/Target/ARM/ARMConstantIslandPass.cpp:1.2
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp:1.3
--- llvm/lib/Target/ARM/ARMConstantIslandPass.cpp:1.2 Wed Jan 24 02:53:17 2007
+++ llvm/lib/Target/ARM/ARMConstantIslandPass.cpp Wed Jan 24 21:12:46 2007
@@ -15,6 +15,7 @@
#define DEBUG_TYPE arm-cp-islands
#include ARM.h
+#include ARMMachineFunctionInfo.h
#include ARMInstrInfo.h
#include llvm/CodeGen/MachineConstantPool.h
#include llvm/CodeGen/MachineFunctionPass.h
@@ -72,13 +73,30 @@
/// constant pools and their max displacement.
std::vectorCPUser CPUsers;
+/// ImmBranch - One per immediate branch, keeping the machine instruction
+/// pointer, conditional or unconditional, the max displacement,
+/// and (if isCond is true) the corresponding unconditional branch
+/// opcode.
+struct ImmBranch {
+ MachineInstr *MI;
+ bool isCond;
+ int UncondBr;
+ unsigned MaxDisp;
+ ImmBranch(MachineInstr *mi, bool cond, int ubr, unsigned maxdisp)
+: MI(mi), isCond(cond), UncondBr(ubr), MaxDisp(maxdisp) {}
+};
+
+/// Branches - Keep track of all the immediate branche instructions.
+///
+std::vectorImmBranch ImmBranches;
+
const TargetInstrInfo *TII;
const TargetAsmInfo *TAI;
public:
virtual bool runOnMachineFunction(MachineFunction Fn);
virtual const char *getPassName() const {
- return ARM constant island placement pass;
+ return ARM constant island placement and branch shortening pass;
}
private:
@@ -87,16 +105,18 @@
void InitialFunctionScan(MachineFunction Fn,
const std::vectorMachineInstr* CPEMIs);
void SplitBlockBeforeInstr(MachineInstr *MI);
-bool HandleConstantPoolUser(MachineFunction Fn, CPUser U);
void UpdateForInsertedWaterBlock(MachineBasicBlock *NewBB);
+bool HandleConstantPoolUser(MachineFunction Fn, CPUser U);
+bool ShortenImmediateBranch(MachineFunction Fn, ImmBranch Br);
unsigned GetInstSize(MachineInstr *MI) const;
unsigned GetOffsetOf(MachineInstr *MI) const;
+unsigned GetOffsetOf(MachineBasicBlock *MBB) const;
};
}
-/// createARMLoadStoreOptimizationPass - returns an instance of the load /
store
-/// optimization pass.
+/// createARMConstantIslandPass - returns an instance of the constpool
+/// island pass.
FunctionPass *llvm::createARMConstantIslandPass() {
return new ARMConstantIslands();
}
@@ -133,11 +153,14 @@
MadeChange = false;
for (unsigned i = 0, e = CPUsers.size(); i != e; ++i)
MadeChange |= HandleConstantPoolUser(Fn, CPUsers[i]);
+for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i)
+ MadeChange |= ShortenImmediateBranch(Fn, ImmBranches[i]);
} while (MadeChange);
BBSizes.clear();
WaterList.clear();
CPUsers.clear();
+ ImmBranches.clear();
return true;
}
@@ -208,6 +231,37 @@
// Add instruction size to MBBSize.
MBBSize += GetInstSize(I);
+ int Opc = I-getOpcode();
+ if (TII-isBranch(Opc)) {
+bool isCond = false;
+unsigned Bits = 0;
+unsigned Scale = 1;
+int UOpc = Opc;
+switch (Opc) {
+default: break; // Ignore JT branches
+case ARM::Bcc:
+ isCond = true;
+ UOpc = ARM::B;
+ // Fallthrough
+case ARM::B:
+ Bits = 24;
+ Scale = 4;
+ break;
+case ARM::tBcc:
+ isCond = true;
+ UOpc = ARM::tB;
+ Bits = 8;
+ Scale = 2;
+ break;
+case ARM::tB:
+ Bits = 11;
+ Scale = 2;
+ break;
+}
+unsigned MaxDisp = (1 (Bits-1)) * Scale;
+ImmBranches.push_back(ImmBranch(I, isCond, UOpc, MaxDisp));
+ }
+
// Scan the instructions for constant pool operands.
for (unsigned op = 0, e = I-getNumOperands(); op != e; ++op)
if (I-getOperand(op).isConstantPoolIndex()) {
@@ -336,6 +390,18 @@
}
}
+/// GetOffsetOf - Return the current offset of the specified machine BB
+/// from the start of the function. This offset changes as stuff is moved
+/// around inside the function.
+unsigned ARMConstantIslands::GetOffsetOf(MachineBasicBlock *MBB) const {
+ // Sum block sizes before MBB.
+ unsigned Offset = 0;
+ for (unsigned BB = 0, e = MBB-getNumber(); BB != e; ++BB)
+Offset += BBSizes[BB];
+
+ return Offset;
+}
+
/// CompareMBBNumbers - Little predicate function to sort the WaterList by MBB
/// ID.
static bool CompareMBBNumbers(const
