[llvm-commits] CVS: llvm/lib/Analysis/LoopPass.cpp
Changes in directory llvm/lib/Analysis:
LoopPass.cpp added (r1.1)
---
Log message:
Add Loop Pass Manager.
---
Diffs of the changes: (+69 -0)
LoopPass.cpp | 69 +++
1 files changed, 69 insertions(+)
Index: llvm/lib/Analysis/LoopPass.cpp
diff -c /dev/null llvm/lib/Analysis/LoopPass.cpp:1.1
*** /dev/null Thu Feb 22 02:56:27 2007
--- llvm/lib/Analysis/LoopPass.cpp Thu Feb 22 02:56:17 2007
***
*** 0
--- 1,69
+ //===- LoopPass.cpp - Loop Pass and Loop Pass Manager
-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Devang Patel and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for
details.
+ //
+
//===--===//
+ //
+ // This file implements LoopPass and LPPassManager. All loop optimization
+ // and transformation passes are derived from LoopPass. LPPassManager is
+ // responsible for managing LoopPasses.
+ //
+
//===--===//
+
+ #include "llvm/Analysis/LoopPass.h"
+ using namespace llvm;
+
+
//===--===//
+ // LPPassManager
+ //
+ /// LPPassManager manages FPPassManagers and CalLGraphSCCPasses.
+
+ /// run - Execute all of the passes scheduled for execution. Keep track of
+ /// whether any of the passes modifies the function, and if so, return true.
+ bool LPPassManager::runOnFunction(Function &F) {
+ LoopInfo &LI = getAnalysis();
+ bool Changed = false;
+
+ std::string Msg1 = "Executing Pass '";
+ std::string Msg3 = "' Made Modification '";
+
+ // Walk Loops
+ for (LoopInfo::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
+
+ Loop *L = *I;
+ // Run all passes on current SCC
+ for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) {
+
+ Pass *P = getContainedPass(Index);
+ AnalysisUsage AnUsage;
+ P->getAnalysisUsage(AnUsage);
+
+ std::string Msg2 = "' on Loop ...\n'";
+ dumpPassInfo(P, Msg1, Msg2);
+ dumpAnalysisSetInfo("Required", P, AnUsage.getRequiredSet());
+
+ initializeAnalysisImpl(P);
+
+ StartPassTimer(P);
+ LoopPass *LP = dynamic_cast(P);
+ assert (LP && "Invalid LPPassManager member");
+ LP->runOnLoop(*L, *this);
+ StopPassTimer(P);
+
+ if (Changed)
+ dumpPassInfo(P, Msg3, Msg2);
+ dumpAnalysisSetInfo("Preserved", P, AnUsage.getPreservedSet());
+
+ removeNotPreservedAnalysis(P);
+ recordAvailableAnalysis(P);
+ removeDeadPasses(P, Msg2);
+ }
+ }
+
+ return Changed;
+ }
+
+
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[llvm-commits] CVS: llvm/include/llvm/Analysis/LoopPass.h
Changes in directory llvm/include/llvm/Analysis:
LoopPass.h added (r1.1)
---
Log message:
Add Loop Pass Manager.
---
Diffs of the changes: (+86 -0)
LoopPass.h | 86 +
1 files changed, 86 insertions(+)
Index: llvm/include/llvm/Analysis/LoopPass.h
diff -c /dev/null llvm/include/llvm/Analysis/LoopPass.h:1.1
*** /dev/null Thu Feb 22 02:56:27 2007
--- llvm/include/llvm/Analysis/LoopPass.h Thu Feb 22 02:56:17 2007
***
*** 0
--- 1,86
+ //===- LoopPass.h - LoopPass class
===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Devang Patel and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for
details.
+ //
+
//===--===//
+ //
+ // This file defines LoopPass class. All loop optimization
+ // and transformation passes are derived from LoopPass.
+ //
+
//===--===//
+
+ #ifndef LLVM_LOOP_PASS_H
+ #define LLVM_LOOP_PASS_H
+
+ #include "llvm/Analysis/LoopInfo.h"
+ #include "llvm/Pass.h"
+ #include "llvm/PassManagers.h"
+ #include "llvm/Function.h"
+
+ namespace llvm {
+
+ class LPPassManager;
+ class Loop;
+ class Function;
+
+ class LoopPass : public Pass {
+
+ public:
+ // runOnLoop - THis method should be implemented by the subclass to perform
+ // whatever action is necessary for the specfied Loop.
+ virtual bool runOnLoop (Loop &L, LPPassManager &LPM) = 0;
+ virtual bool runOnFunctionBody (Function &F, LPPassManager &LPM) {
+ return false;
+ }
+
+ };
+
+ class LPPassManager : public FunctionPass, public PMDataManager {
+
+ public:
+ LPPassManager(int Depth) : PMDataManager(Depth) { }
+
+ /// run - Execute all of the passes scheduled for execution. Keep track of
+ /// whether any of the passes modifies the module, and if so, return true.
+ bool runOnFunction(Function &F);
+
+ /// Pass Manager itself does not invalidate any analysis info.
+ void getAnalysisUsage(AnalysisUsage &Info) const {
+ // LPPassManager needs LoopInfo. In the long term LoopInfo class will
+ // be consumed by LPPassManager.
+ Info.addRequired();
+ Info.setPreservesAll();
+ }
+
+ virtual const char *getPassName() const {
+ return "Loop Pass Manager";
+ }
+
+ // Print passes managed by this manager
+ void dumpPassStructure(unsigned Offset) {
+ llvm::cerr << std::string(Offset*2, ' ') << "Loop Pass Manager\n";
+ for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) {
+ Pass *P = getContainedPass(Index);
+ P->dumpPassStructure(Offset + 1);
+ dumpLastUses(P, Offset+1);
+ }
+ }
+
+ Pass *getContainedPass(unsigned N) {
+ assert ( N < PassVector.size() && "Pass number out of range!");
+ Pass *FP = static_cast(PassVector[N]);
+ return FP;
+ }
+
+ virtual PassManagerType getPassManagerType() {
+ return PMT_LoopPassManager;
+ }
+
+ };
+
+ } // End llvm namespace
+
+ #endif
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Re: [llvm-commits] CVS: llvm/docs/DeveloperPolicy.html
> + the GPL). This is not a problem for the main LLVM >distribution (which is already licensed under a more liberal license), but > may >be a problem if you intend to base commercial development on llvm-gcc > without >redistributing your source code. Maybe you should make explicit that there is no problem using llvm-gcc to compile proprietary code - there is only a problem if parts of llvm-gcc are included in the proprietary program. You do say that more or less a few lines before, but this last sentence could great doubt in peoples minds. Maybe you could offload the problem onto gcc, and say that compiling a program with llvm-gcc is like compiling it with gcc, and give a link to http://www.gnu.org/licenses/gpl-faq.html which discusses these issues. Ciao, Duncan. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/Sparc: SparcISelDAGToDAG.cpp updated: 1.120 -> 1.121 --- Log message: Simplify lowering and selection of exception ops. --- Diffs of the changes: (+0 -3) SparcISelDAGToDAG.cpp |3 --- 1 files changed, 3 deletions(-) Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.120 llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.121 --- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.120 Wed Feb 21 16:54:50 2007 +++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Thu Feb 22 08:56:36 2007 @@ -871,9 +871,6 @@ // Frame & Return address. Currently unimplemented case ISD::RETURNADDR: break; case ISD::FRAMEADDR: break; - // Exception address and exception selector. Currently unimplemented. - case ISD::EXCEPTIONADDR: break; - case ISD::EHSELECTION: break; } return SDOperand(); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.15 -> 1.16 --- Log message: Simplify lowering and selection of exception ops. --- Diffs of the changes: (+0 -3) ARMISelLowering.cpp |3 --- 1 files changed, 3 deletions(-) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.15 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.16 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.15Wed Feb 21 16:54:50 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Thu Feb 22 08:56:36 2007 @@ -1190,9 +1190,6 @@ return LowerFORMAL_ARGUMENTS(Op, DAG); case ISD::RETURNADDR:break; case ISD::FRAMEADDR: break; - // Exception address and exception selector. Currently unimplemented. - case ISD::EXCEPTIONADDR: break; - case ISD::EHSELECTION: break; } return SDOperand(); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.252 -> 1.253
---
Log message:
Simplify lowering and selection of exception ops.
---
Diffs of the changes: (+15 -34)
PPCISelLowering.cpp | 49 +++--
1 files changed, 15 insertions(+), 34 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.252
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.253
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.252 Wed Feb 21 16:54:50 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Feb 22 08:56:36 2007
@@ -140,14 +140,18 @@
// We cannot sextinreg(i1). Expand to shifts.
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
-
-
+
// Support label based line numbers.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
- // FIXME - use subtarget debug flags
- if (!TM.getSubtarget().isDarwin())
+ if (!TM.getSubtarget().isDarwin()) {
setOperationAction(ISD::LABEL, MVT::Other, Expand);
+ } else {
+setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
+setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
+setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
+setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
+ }
// We want to legalize GlobalAddress and ConstantPool nodes into the
// appropriate instructions to materialize the address.
@@ -283,10 +287,15 @@
setShiftAmountType(MVT::i32);
setSetCCResultContents(ZeroOrOneSetCCResult);
- if (TM.getSubtarget().isPPC64())
+ if (TM.getSubtarget().isPPC64()) {
setStackPointerRegisterToSaveRestore(PPC::X1);
- else
+setExceptionPointerRegister(PPC::X3);
+setExceptionSelectorRegister(PPC::X4);
+ } else {
setStackPointerRegisterToSaveRestore(PPC::R1);
+setExceptionPointerRegister(PPC::R3);
+setExceptionSelectorRegister(PPC::R4);
+ }
// We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine(ISD::SINT_TO_FP);
@@ -2610,30 +2619,6 @@
}
}
-/// LowerEXCEPTIONADDR - Replace EXCEPTIONADDR with a copy from the exception
-/// register. The register was made live in the ISel.
-static SDOperand LowerEXCEPTIONADDR(SDOperand Op, SelectionDAG &DAG) {
- const MRegisterInfo *MRI = DAG.getTargetLoweringInfo().
- getTargetMachine().
- getRegisterInfo();
- MVT::ValueType VT = Op.Val->getValueType(0);
- unsigned Reg = MRI->getEHExceptionRegister();
- SDOperand Result = DAG.getCopyFromReg(Op.getOperand(0), Reg, VT);
- return Result.getValue(Op.ResNo);
-}
-
-/// LowerEXCEPTIONADDR - Replace EHSELECTION with a copy from the exception
-/// selection register. The register was made live in the ISel.
-static SDOperand LowerEHSELECTION(SDOperand Op, SelectionDAG &DAG) {
- const MRegisterInfo *MRI = DAG.getTargetLoweringInfo().
- getTargetMachine().
- getRegisterInfo();
- MVT::ValueType VT = Op.Val->getValueType(0);
- unsigned Reg = MRI->getEHHandlerRegister();
- SDOperand Result = DAG.getCopyFromReg(Op.getOperand(1), Reg, VT);
- return Result.getValue(Op.ResNo);
-}
-
/// LowerOperation - Provide custom lowering hooks for some operations.
///
SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
@@ -2671,10 +2656,6 @@
// Frame & Return address. Currently unimplemented
case ISD::RETURNADDR: break;
case ISD::FRAMEADDR: break;
-
- // Exception address and exception selector.
- case ISD::EXCEPTIONADDR: return LowerEXCEPTIONADDR(Op, DAG);
- case ISD::EHSELECTION:return LowerEHSELECTION(Op, DAG);
}
return SDOperand();
}
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64: IA64ISelLowering.cpp updated: 1.54 -> 1.55 --- Log message: Simplify lowering and selection of exception ops. --- Diffs of the changes: (+0 -3) IA64ISelLowering.cpp |3 --- 1 files changed, 3 deletions(-) Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.54 llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.55 --- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.54 Wed Feb 21 16:54:50 2007 +++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Thu Feb 22 08:56:36 2007 @@ -590,9 +590,6 @@ // Frame & Return address. Currently unimplemented case ISD::RETURNADDR: break; case ISD::FRAMEADDR: break; - // Exception address and exception selector. Currently unimplemented. - case ISD::EXCEPTIONADDR: break; - case ISD::EHSELECTION: break; } return SDOperand(); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.322 -> 1.323 --- Log message: Simplify lowering and selection of exception ops. --- Diffs of the changes: (+0 -3) X86ISelLowering.cpp |3 --- 1 files changed, 3 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.322 llvm/lib/Target/X86/X86ISelLowering.cpp:1.323 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.322 Wed Feb 21 16:54:50 2007 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Feb 22 08:56:36 2007 @@ -4675,9 +4675,6 @@ case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); - // Exception address and exception selector. Currently unimplemented. - case ISD::EXCEPTIONADDR: break; - case ISD::EHSELECTION: break; } return SDOperand(); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target: MRegisterInfo.h updated: 1.95 -> 1.96 --- Log message: Simplify lowering and selection of exception ops. --- Diffs of the changes: (+0 -8) MRegisterInfo.h |8 1 files changed, 8 deletions(-) Index: llvm/include/llvm/Target/MRegisterInfo.h diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.95 llvm/include/llvm/Target/MRegisterInfo.h:1.96 --- llvm/include/llvm/Target/MRegisterInfo.h:1.95 Wed Feb 21 16:54:50 2007 +++ llvm/include/llvm/Target/MRegisterInfo.hThu Feb 22 08:56:35 2007 @@ -470,14 +470,6 @@ /// address can be found. virtual unsigned getRARegister() const = 0; - /// getEHExceptionRegister - This method should return the register containing - /// the address of the exception info on entry to a landing pad. - virtual unsigned getEHExceptionRegister() const = 0; - - /// getEHHandlerRegister - This method should return the register containing - /// the switch table selection on entry to an landing pad. - virtual unsigned getEHHandlerRegister() const = 0; - /// getLocation - This method should return the actual location of a frame /// variable given the frame index. The location is returned in ML. /// Subclasses should override this method for special handling of frame ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
Changes in directory llvm/lib/Target/Alpha: AlphaISelLowering.cpp updated: 1.82 -> 1.83 --- Log message: Simplify lowering and selection of exception ops. --- Diffs of the changes: (+0 -3) AlphaISelLowering.cpp |3 --- 1 files changed, 3 deletions(-) Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.82 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.83 --- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.82Wed Feb 21 16:54:50 2007 +++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Thu Feb 22 08:56:36 2007 @@ -548,9 +548,6 @@ return DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64); //FIXME: implement case ISD::FRAMEADDR: break; - // Exception address and exception selector. Currently unimplemented. - case ISD::EXCEPTIONADDR: break; - case ISD::EHSELECTION: break; } return SDOperand(); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [see] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.536.2.1 -> 1.536.2.1.2.1
---
Log message:
catch a missed * to int conversion
---
Diffs of the changes: (+15 -0)
InstructionCombining.cpp | 15 +++
1 files changed, 15 insertions(+)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.536.2.1
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.536.2.1.2.1
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.536.2.1 Wed Feb
7 16:32:03 2007
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Thu Feb 22 09:11:27 2007
@@ -4837,6 +4837,21 @@
return BinaryOperator::create(I.getOpcode(), Op0, Op1);
}
+//Handle special case of setcc (cast T* to uint) (cast T* to uint)
+//Generalize to seteq (cast T to >= T') (cast T to >= T')
+//restrict to ints and pointers (so casts are sext or zext, no reinterpret)
+if (CastInst* CI1 = dyn_cast(Op1)) {
+ Value* CastOp1 = CI1->getOperand(0);
+ if (I.isEquality() && CastOp0->getType() == CastOp1->getType() &&
+ TD->getTypeSize(Op1->getType()) >=
TD->getTypeSize(CastOp1->getType()) &&
+ (CastOp1->getType()->isInteger() ||
isa(CastOp1->getType())) &&
+ (Op1->getType()->isInteger() || isa(Op1->getType()))
+ ) {
+std::cerr << "Triggered\n";
+return BinaryOperator::create(I.getOpcode(), CastOp0, CastOp1);
+ }
+}
+
// Handle the special case of: setcc (cast bool to X),
// This comes up when you have code like
// int X = A < B;
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[llvm-commits] CVS: llvm/test/Transforms/InstCombine/cast_ptr.ll
Changes in directory llvm/test/Transforms/InstCombine:
cast_ptr.ll updated: 1.3 -> 1.4
---
Log message:
missed cast elimination
---
Diffs of the changes: (+7 -1)
cast_ptr.ll |8 +++-
1 files changed, 7 insertions(+), 1 deletion(-)
Index: llvm/test/Transforms/InstCombine/cast_ptr.ll
diff -u llvm/test/Transforms/InstCombine/cast_ptr.ll:1.3
llvm/test/Transforms/InstCombine/cast_ptr.ll:1.4
--- llvm/test/Transforms/InstCombine/cast_ptr.ll:1.3Fri Dec 1 22:23:09 2006
+++ llvm/test/Transforms/InstCombine/cast_ptr.llThu Feb 22 09:17:45 2007
@@ -1,6 +1,6 @@
; Tests to make sure elimination of casts is working correctly
; RUN: llvm-upgrade < %s | llvm-as | opt -instcombine -disable-output &&
-; RUN: llvm-upgrade < %s | llvm-as | opt -instcombine | llvm-dis | not grep
'\([sz]ext\)\|\(trunc\)'
+; RUN: llvm-upgrade < %s | llvm-as | opt -instcombine | llvm-dis | not grep
'\([sz]ext\)\|\(trunc\)|\(ptrtoint\)'
target pointersize = 32
@@ -13,3 +13,9 @@
ret sbyte* %tv
}
+bool %test2(sbyte* %a, sbyte* %b) {
+%tmpa = cast sbyte* %a to uint
+%tmpb = cast sbyte* %b to uint
+%r = seteq uint %tmpa, %tmpb
+ret bool %r
+}
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.477 -> 1.478
---
Log message:
Simplify lowering and selection of exception ops.
---
Diffs of the changes: (+26 -2)
LegalizeDAG.cpp | 28 ++--
1 files changed, 26 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.477
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.478
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.477 Wed Feb 21 16:53:45 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Feb 22 09:37:19 2007
@@ -668,8 +668,6 @@
break;
case ISD::FRAMEADDR:
case ISD::RETURNADDR:
- case ISD::EXCEPTIONADDR:
- case ISD::EHSELECTION:
// The only option for these nodes is to custom lower them. If the target
// does not custom lower them, then return zero.
Tmp1 = TLI.LowerOperation(Op, DAG);
@@ -678,6 +676,32 @@
else
Result = DAG.getConstant(0, TLI.getPointerTy());
break;
+ case ISD::EHSELECTION:
+LegalizeOp(Node->getOperand(1));
+// Fall Thru
+ case ISD::EXCEPTIONADDR: {
+Tmp1 = LegalizeOp(Node->getOperand(0));
+MVT::ValueType VT = Node->getValueType(0);
+switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
+default: assert(0 && "This action is not supported yet!");
+case TargetLowering::Expand: {
+unsigned Reg = Node->getOpcode() == ISD::EXCEPTIONADDR ?
+ TLI.getExceptionAddressRegister() :
+ TLI.getExceptionSelectorRegister();
+Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo);
+ }
+ break;
+case TargetLowering::Custom:
+ Result = TLI.LowerOperation(Op, DAG);
+ if (Result.Val) break;
+ // Fall Thru
+case TargetLowering::Legal:
+ Result = DAG.getNode(ISD::MERGE_VALUES, VT, DAG.getConstant(0, VT),
Tmp1).
+ getValue(Op.ResNo);
+ break;
+}
+}
+break;
case ISD::AssertSext:
case ISD::AssertZext:
Tmp1 = LegalizeOp(Node->getOperand(0));
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[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.109 -> 1.110
---
Log message:
Simplify lowering and selection of exception ops.
---
Diffs of the changes: (+38 -0)
TargetLowering.h | 38 ++
1 files changed, 38 insertions(+)
Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.109
llvm/include/llvm/Target/TargetLowering.h:1.110
--- llvm/include/llvm/Target/TargetLowering.h:1.109 Wed Feb 14 21:39:17 2007
+++ llvm/include/llvm/Target/TargetLowering.h Thu Feb 22 09:37:19 2007
@@ -403,6 +403,20 @@
return StackPointerRegisterToSaveRestore;
}
+ /// getExceptionAddressRegister - If a physical register, this returns
+ /// the register that receives the exception address on entry to a landing
+ /// pad.
+ unsigned getExceptionAddressRegister() const {
+return ExceptionPointerRegister;
+ }
+
+ /// getExceptionSelectorRegister - If a physical register, this returns
+ /// the register that receives the exception typeid on entry to a landing
+ /// pad.
+ unsigned getExceptionSelectorRegister() const {
+return ExceptionSelectorRegister;
+ }
+
/// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
/// set, the default is 200)
unsigned getJumpBufSize() const {
@@ -604,6 +618,20 @@
StackPointerRegisterToSaveRestore = R;
}
+ /// setExceptionPointerRegister - If set to a physical register, this sets
+ /// the register that receives the exception address on entry to a landing
+ /// pad.
+ void setExceptionPointerRegister(unsigned R) {
+ExceptionPointerRegister = R;
+ }
+
+ /// setExceptionSelectorRegister - If set to a physical register, this sets
+ /// the register that receives the exception typeid on entry to a landing
+ /// pad.
+ void setExceptionSelectorRegister(unsigned R) {
+ExceptionSelectorRegister = R;
+ }
+
/// SelectIsExpensive - Tells the code generator not to expand operations
/// into sequences that use the select operations if possible.
void setSelectIsExpensive() { SelectIsExpensive = true; }
@@ -956,6 +984,16 @@
/// and restore.
unsigned StackPointerRegisterToSaveRestore;
+ /// ExceptionPointerRegister - If set to a physical register, this specifies
+ /// the register that receives the exception address on entry to a landing
+ /// pad.
+ unsigned ExceptionPointerRegister;
+
+ /// ExceptionSelectorRegister - If set to a physical register, this specifies
+ /// the register that receives the exception typeid on entry to a landing
+ /// pad.
+ unsigned ExceptionSelectorRegister;
+
/// RegClassForVT - This indicates the default register class to use for
/// each ValueType the target supports natively.
TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.370 -> 1.371
---
Log message:
Handle lowering invoke to call correctly.
---
Diffs of the changes: (+97 -95)
SelectionDAGISel.cpp | 192 +--
1 files changed, 97 insertions(+), 95 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.370
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.371
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.370Wed Feb 21
16:53:45 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Feb 22 09:38:06 2007
@@ -484,7 +484,8 @@
unsigned Opc);
bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
void ExportFromCurrentBlock(Value *V);
-
+ void LowerCallTo(CallInst &I, SDOperand Callee, unsigned OpIdx);
+
// Terminator instructions.
void visitRet(ReturnInst &I);
void visitBr(BranchInst &I);
@@ -1117,17 +1118,7 @@
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
DAG.getConstant(BeginLabel, MVT::i32)));
- // Insert a normal call instruction.
- std::vector Args;
- for (InvokeInst::op_iterator OI = I.op_begin() + 3, E = I.op_end();
- OI != E; ++OI) {
-Args.push_back(*OI);
- }
- CallInst *NewCall = new CallInst(I.getCalledValue(), &Args[0], Args.size(),
- I.getName(), &I);
- NewCall->setCallingConv(I.getCallingConv());
- I.replaceAllUsesWith(NewCall);
- visitCall(*NewCall);
+ LowerCallTo((CallInst&)I, getValue(I.getOperand(0)), 3);
// Insert a label before the invoke call to mark the try range.
// This can be used to detect deletion of the invoke via the
@@ -2086,84 +2077,87 @@
case Intrinsic::eh_exception: {
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
-// Add a label to mark the beginning of the landing pad. Deletion of the
-// landing pad can thus be detected via the MachineModuleInfo.
-unsigned LabelID = MMI->addLandingPad(CurMBB);
-DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
-DAG.getConstant(LabelID, MVT::i32)));
-
-// Mark exception register as live in.
-const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
-unsigned Reg = MRI->getEHExceptionRegister();
-if (Reg) CurMBB->addLiveIn(Reg);
-
-// Insert the EXCEPTIONADDR instruction.
-SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
-SDOperand Ops[1];
-Ops[0] = DAG.getRoot();
-SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
-setValue(&I, Op);
-DAG.setRoot(Op.getValue(1));
-
+if (MMI) {
+ // Add a label to mark the beginning of the landing pad. Deletion of the
+ // landing pad can thus be detected via the MachineModuleInfo.
+ unsigned LabelID = MMI->addLandingPad(CurMBB);
+ DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
+ DAG.getConstant(LabelID, MVT::i32)));
+
+ // Mark exception register as live in.
+ unsigned Reg = TLI.getExceptionAddressRegister();
+ if (Reg) CurMBB->addLiveIn(Reg);
+
+ // Insert the EXCEPTIONADDR instruction.
+ SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
+ SDOperand Ops[1];
+ Ops[0] = DAG.getRoot();
+ SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
+ setValue(&I, Op);
+ DAG.setRoot(Op.getValue(1));
+}
return 0;
}
case Intrinsic::eh_handlers: {
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
-// Inform the MachineModuleInfo of the personality for this landing pad.
-if (ConstantExpr *CE = dyn_cast(I.getOperand(2))) {
- if (CE->getOpcode() == Instruction::BitCast) {
- MMI->addPersonality(CurMBB,
- cast(CE->getOperand(0)));
- }
-}
-
-// Gather all the type infos for this landing pad and pass them along to
-// MachineModuleInfo.
-std::vector TyInfo;
-for (unsigned i = 3, N = I.getNumOperands(); i < N; ++i) {
- if (ConstantExpr *CE = dyn_cast(I.getOperand(i))) {
+if (MMI) {
+ // Inform the MachineModuleInfo of the personality for this landing pad.
+ if (ConstantExpr *CE = dyn_cast(I.getOperand(2))) {
if (CE->getOpcode() == Instruction::BitCast) {
- TyInfo.push_back(cast(CE->getOperand(0)));
- continue;
+MMI->addPersonality(CurMBB,
+cast(CE->getOperand(0)));
}
}
- TyInfo.push_back(NULL);
+ // Gather all the type infos for this landing pad and pass them along to
+ // MachineModuleInfo.
+ std::vector TyInfo;
+ for (unsigned i = 3, N = I.getNumOperands(); i < N; ++i) {
+if (ConstantExpr *
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.371 -> 1.372
---
Log message:
Tighten up error checking of args.
---
Diffs of the changes: (+23 -17)
SelectionDAGISel.cpp | 40 +++-
1 files changed, 23 insertions(+), 17 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.371
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.372
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.371Thu Feb 22
09:38:06 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Feb 22 10:10:05 2007
@@ -2104,25 +2104,26 @@
if (MMI) {
// Inform the MachineModuleInfo of the personality for this landing pad.
- if (ConstantExpr *CE = dyn_cast(I.getOperand(2))) {
-if (CE->getOpcode() == Instruction::BitCast) {
-MMI->addPersonality(CurMBB,
-cast(CE->getOperand(0)));
-}
- }
+ ConstantExpr *CE = dyn_cast(I.getOperand(2));
+ assert(CE && CE->getOpcode() == Instruction::BitCast &&
+ isa(CE->getOperand(0)) &&
+ "Personality should be a function");
+ MMI->addPersonality(CurMBB, cast(CE->getOperand(0)));
// Gather all the type infos for this landing pad and pass them along to
// MachineModuleInfo.
std::vector TyInfo;
for (unsigned i = 3, N = I.getNumOperands(); i < N; ++i) {
-if (ConstantExpr *CE = dyn_cast(I.getOperand(i))) {
- if (CE->getOpcode() == Instruction::BitCast) {
-TyInfo.push_back(cast(CE->getOperand(0)));
-continue;
- }
+ConstantExpr *CE = dyn_cast(I.getOperand(i));
+if (CE && CE->getOpcode() == Instruction::BitCast &&
+isa(CE->getOperand(0))) {
+ TyInfo.push_back(cast(CE->getOperand(0)));
+} else {
+ ConstantInt *CI = dyn_cast(I.getOperand(i));
+ assert(CI && CI->getZExtValue() == 0 &&
+"TypeInfo must be a global variable typeinfo or NULL");
+ TyInfo.push_back(NULL);
}
-
-TyInfo.push_back(NULL);
}
MMI->addCatchTypeInfo(CurMBB, TyInfo);
@@ -2149,10 +2150,15 @@
if (MMI) {
// Find the type id for the given typeinfo.
GlobalVariable *GV = NULL;
- if (ConstantExpr *CE = dyn_cast(I.getOperand(1))) {
-if (CE->getOpcode() == Instruction::BitCast) {
- GV = cast(CE->getOperand(0));
-}
+ ConstantExpr *CE = dyn_cast(I.getOperand(1));
+ if (CE && CE->getOpcode() == Instruction::BitCast &&
+ isa(CE->getOperand(0))) {
+GV = cast(CE->getOperand(0));
+ } else {
+ConstantInt *CI = dyn_cast(I.getOperand(1));
+assert(CI && CI->getZExtValue() == 0 &&
+ "TypeInfo must be a global variable typeinfo or NULL");
+GV = NULL;
}
unsigned TypeID = MMI->getTypeIDFor(GV);
___
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[llvm-commits] CVS: llvm/lib/CodeGen/IntrinsicLowering.cpp
Changes in directory llvm/lib/CodeGen:
IntrinsicLowering.cpp updated: 1.68 -> 1.69
---
Log message:
Remove assertion.
---
Diffs of the changes: (+1 -4)
IntrinsicLowering.cpp |5 +
1 files changed, 1 insertion(+), 4 deletions(-)
Index: llvm/lib/CodeGen/IntrinsicLowering.cpp
diff -u llvm/lib/CodeGen/IntrinsicLowering.cpp:1.68
llvm/lib/CodeGen/IntrinsicLowering.cpp:1.69
--- llvm/lib/CodeGen/IntrinsicLowering.cpp:1.68 Wed Feb 21 16:53:45 2007
+++ llvm/lib/CodeGen/IntrinsicLowering.cpp Thu Feb 22 10:12:17 2007
@@ -356,12 +356,9 @@
case Intrinsic::dbg_region_end:
case Intrinsic::dbg_func_start:
case Intrinsic::dbg_declare:
-break;// Simply strip out debugging intrinsics
-
case Intrinsic::eh_exception:
case Intrinsic::eh_handlers:
-assert(0 && "Should not have leaked through");
-break;
+break;// Simply strip out debugging intrinsics
case Intrinsic::memcpy_i32:
case Intrinsic::memcpy_i64: {
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[llvm-commits] CVS: llvm/lib/Transforms/Utils/LowerInvoke.cpp
Changes in directory llvm/lib/Transforms/Utils:
LowerInvoke.cpp updated: 1.56 -> 1.57
---
Log message:
Revert changes for a simplier solution.
---
Diffs of the changes: (+36 -50)
LowerInvoke.cpp | 86 +++-
1 files changed, 36 insertions(+), 50 deletions(-)
Index: llvm/lib/Transforms/Utils/LowerInvoke.cpp
diff -u llvm/lib/Transforms/Utils/LowerInvoke.cpp:1.56
llvm/lib/Transforms/Utils/LowerInvoke.cpp:1.57
--- llvm/lib/Transforms/Utils/LowerInvoke.cpp:1.56 Wed Feb 21 16:49:50 2007
+++ llvm/lib/Transforms/Utils/LowerInvoke.cpp Thu Feb 22 10:21:18 2007
@@ -57,9 +57,6 @@
static cl::opt ExpensiveEHSupport("enable-correct-eh-support",
cl::desc("Make the -lowerinvoke pass insert expensive, but correct, EH
code"));
-
-static cl::opt ItaniumEHSupport("enable-real-eh-support",
- cl::desc("Make the -lowerinvoke pass insert itanium ABI EH code"));
namespace {
class VISIBILITY_HIDDEN LowerInvoke : public FunctionPass {
@@ -97,7 +94,6 @@
void splitLiveRangesLiveAcrossInvokes(std::vector &Invokes);
void rewriteExpensiveInvoke(InvokeInst *II, unsigned InvokeNo,
AllocaInst *InvokeNum, SwitchInst
*CatchSwitch);
-bool insertItaniumEHSupport(Function &F);
bool insertExpensiveEHSupport(Function &F);
};
@@ -115,50 +111,46 @@
// doInitialization - Make sure that there is a prototype for abort in the
// current module.
bool LowerInvoke::doInitialization(Module &M) {
- if (ItaniumEHSupport) {
-// Let Invoke pass through for ItaniumEHSupport support.
- } else {
-const Type *VoidPtrTy = PointerType::get(Type::Int8Ty);
-AbortMessage = 0;
-if (ExpensiveEHSupport) {
- // Insert a type for the linked list of jump buffers.
- unsigned JBSize = TLI ? TLI->getJumpBufSize() : 0;
- JBSize = JBSize ? JBSize : 200;
- const Type *JmpBufTy = ArrayType::get(VoidPtrTy, JBSize);
-
- { // The type is recursive, so use a type holder.
-std::vector Elements;
-Elements.push_back(JmpBufTy);
-OpaqueType *OT = OpaqueType::get();
-Elements.push_back(PointerType::get(OT));
-PATypeHolder JBLType(StructType::get(Elements));
-OT->refineAbstractTypeTo(JBLType.get()); // Complete the cycle.
-JBLinkTy = JBLType.get();
-M.addTypeName("llvm.sjljeh.jmpbufty", JBLinkTy);
- }
+ const Type *VoidPtrTy = PointerType::get(Type::Int8Ty);
+ AbortMessage = 0;
+ if (ExpensiveEHSupport) {
+// Insert a type for the linked list of jump buffers.
+unsigned JBSize = TLI ? TLI->getJumpBufSize() : 0;
+JBSize = JBSize ? JBSize : 200;
+const Type *JmpBufTy = ArrayType::get(VoidPtrTy, JBSize);
+
+{ // The type is recursive, so use a type holder.
+ std::vector Elements;
+ Elements.push_back(JmpBufTy);
+ OpaqueType *OT = OpaqueType::get();
+ Elements.push_back(PointerType::get(OT));
+ PATypeHolder JBLType(StructType::get(Elements));
+ OT->refineAbstractTypeTo(JBLType.get()); // Complete the cycle.
+ JBLinkTy = JBLType.get();
+ M.addTypeName("llvm.sjljeh.jmpbufty", JBLinkTy);
+}
- const Type *PtrJBList = PointerType::get(JBLinkTy);
+const Type *PtrJBList = PointerType::get(JBLinkTy);
- // Now that we've done that, insert the jmpbuf list head global, unless
it
- // already exists.
- if (!(JBListHead = M.getGlobalVariable("llvm.sjljeh.jblist",
PtrJBList))){
-JBListHead = new GlobalVariable(PtrJBList, false,
-GlobalValue::LinkOnceLinkage,
-Constant::getNullValue(PtrJBList),
-"llvm.sjljeh.jblist", &M);
- }
- SetJmpFn = M.getOrInsertFunction("llvm.setjmp", Type::Int32Ty,
- PointerType::get(JmpBufTy), (Type *)0);
- LongJmpFn = M.getOrInsertFunction("llvm.longjmp", Type::VoidTy,
-PointerType::get(JmpBufTy),
-Type::Int32Ty, (Type *)0);
+// Now that we've done that, insert the jmpbuf list head global, unless it
+// already exists.
+if (!(JBListHead = M.getGlobalVariable("llvm.sjljeh.jblist", PtrJBList))) {
+ JBListHead = new GlobalVariable(PtrJBList, false,
+ GlobalValue::LinkOnceLinkage,
+ Constant::getNullValue(PtrJBList),
+ "llvm.sjljeh.jblist", &M);
}
-
-// We need the 'write' and 'abort' functions for both models.
-AbortFn = M.getOrInsertFunction("abort", Type::VoidTy, (Type *)0);
-WriteFn = M.getOrInsertFunction("write", Type::VoidTy, Type::Int32Ty,
-VoidPtrTy, Type::Int32Ty, (Type *)0);
+SetJmpFn = M.getOrInsertFunction("llvm.setjmp", Type::Int32Ty,
+ PointerType::get(Jmp
[llvm-commits] CVS: llvm/lib/CodeGen/LLVMTargetMachine.cpp
Changes in directory llvm/lib/CodeGen: LLVMTargetMachine.cpp updated: 1.8 -> 1.9 --- Log message: Use exception flag. --- Diffs of the changes: (+2 -1) LLVMTargetMachine.cpp |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/LLVMTargetMachine.cpp diff -u llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.8 llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.9 --- llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.8 Wed Feb 7 19:36:53 2007 +++ llvm/lib/CodeGen/LLVMTargetMachine.cpp Thu Feb 22 10:22:15 2007 @@ -33,7 +33,8 @@ PM.add(createLowerGCPass()); // FIXME: Implement the invoke/unwind instructions! - PM.add(createLowerInvokePass(getTargetLowering())); + if (!ExceptionHandling) +PM.add(createLowerInvokePass(getTargetLowering())); // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/test/Transforms/InstCombine/cast_ptr.ll
I won't get a chance to fix this before the nightly testers start. Should I
x-fail this until it is handled?
Andrew
On 2/22/07, Andrew Lenharth <[EMAIL PROTECTED]> wrote:
Changes in directory llvm/test/Transforms/InstCombine:
cast_ptr.ll updated: 1.3 -> 1.4
---
Log message:
missed cast elimination
---
Diffs of the changes: (+7 -1)
cast_ptr.ll |8 +++-
1 files changed, 7 insertions(+), 1 deletion(-)
Index: llvm/test/Transforms/InstCombine/cast_ptr.ll
diff -u
llvm/test/Transforms/InstCombine/cast_ptr.ll:1.3llvm/test/Transforms/InstCombine/cast_ptr.ll:
1.4
--- llvm/test/Transforms/InstCombine/cast_ptr.ll:1.3Fri Dec 1
22:23:09 2006
+++ llvm/test/Transforms/InstCombine/cast_ptr.llThu Feb 22
09:17:45 2007
@@ -1,6 +1,6 @@
; Tests to make sure elimination of casts is working correctly
; RUN: llvm-upgrade < %s | llvm-as | opt -instcombine -disable-output &&
-; RUN: llvm-upgrade < %s | llvm-as | opt -instcombine | llvm-dis | not
grep '\([sz]ext\)\|\(trunc\)'
+; RUN: llvm-upgrade < %s | llvm-as | opt -instcombine | llvm-dis | not
grep '\([sz]ext\)\|\(trunc\)|\(ptrtoint\)'
target pointersize = 32
@@ -13,3 +13,9 @@
ret sbyte* %tv
}
+bool %test2(sbyte* %a, sbyte* %b) {
+%tmpa = cast sbyte* %a to uint
+%tmpb = cast sbyte* %b to uint
+%r = seteq uint %tmpa, %tmpb
+ret bool %r
+}
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[llvm-commits] CVS: llvm/lib/CodeGen/BranchFolding.cpp
Changes in directory llvm/lib/CodeGen:
BranchFolding.cpp updated: 1.43 -> 1.44
---
Log message:
Remove isAccessable.
---
Diffs of the changes: (+4 -4)
BranchFolding.cpp |8
1 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/BranchFolding.cpp
diff -u llvm/lib/CodeGen/BranchFolding.cpp:1.43
llvm/lib/CodeGen/BranchFolding.cpp:1.44
--- llvm/lib/CodeGen/BranchFolding.cpp:1.43 Wed Feb 21 16:42:20 2007
+++ llvm/lib/CodeGen/BranchFolding.cpp Thu Feb 22 10:39:03 2007
@@ -67,7 +67,7 @@
/// RemoveDeadBlock - Remove the specified dead machine basic block from the
/// function, updating the CFG.
void BranchFolder::RemoveDeadBlock(MachineBasicBlock *MBB) {
- assert(!MBB->isAccessable() && "MBB must be dead!");
+ assert(MBB->pred_empty() && "MBB must be dead!");
DOUT << "\nRemoving MBB: " << *MBB;
MachineFunction *MF = MBB->getParent();
@@ -440,7 +440,7 @@
OptimizeBlock(MBB);
// If it is dead, remove it.
-if (!MBB->isAccessable()) {
+if (MBB->pred_empty()) {
RemoveDeadBlock(MBB);
MadeChange = true;
++NumDeadBlocks;
@@ -618,14 +618,14 @@
// explicitly.
if (MBB->empty()) {
// Dead block? Leave for cleanup later.
-if (!MBB->isAccessable()) return;
+if (MBB->pred_empty()) return;
if (FallThrough == MBB->getParent()->end()) {
// TODO: Simplify preds to not branch here if possible!
} else {
// Rewrite all predecessors of the old block to go to the fallthrough
// instead.
- while (MBB->isAccessable()) {
+ while (!MBB->pred_empty()) {
MachineBasicBlock *Pred = *(MBB->pred_end()-1);
ReplaceUsesOfBlockWith(Pred, MBB, FallThrough, TII);
}
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineBasicBlock.h
Changes in directory llvm/include/llvm/CodeGen:
MachineBasicBlock.h updated: 1.59 -> 1.60
---
Log message:
Remove isAccessable.
---
Diffs of the changes: (+0 -4)
MachineBasicBlock.h |4
1 files changed, 4 deletions(-)
Index: llvm/include/llvm/CodeGen/MachineBasicBlock.h
diff -u llvm/include/llvm/CodeGen/MachineBasicBlock.h:1.59
llvm/include/llvm/CodeGen/MachineBasicBlock.h:1.60
--- llvm/include/llvm/CodeGen/MachineBasicBlock.h:1.59 Wed Feb 21 16:39:52 2007
+++ llvm/include/llvm/CodeGen/MachineBasicBlock.h Thu Feb 22 10:39:03 2007
@@ -165,10 +165,6 @@
/// this basic block is entered via an exception handler.
void setIsLandingPad() { IsLandingPad = true; }
- /// isAccessable - Returns true if the block is alive. That is, if it has
- /// predecessors or is an eh landing pad.
- bool isAccessable() const { return !pred_empty() || isLandingPad(); }
-
// Code Layout methods.
/// moveBefore/moveAfter - move 'this' block before or after the specified
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineModuleInfo.h
Changes in directory llvm/include/llvm/CodeGen: MachineModuleInfo.h updated: 1.5 -> 1.6 --- Log message: Typo. --- Diffs of the changes: (+1 -1) MachineModuleInfo.h |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/CodeGen/MachineModuleInfo.h diff -u llvm/include/llvm/CodeGen/MachineModuleInfo.h:1.5 llvm/include/llvm/CodeGen/MachineModuleInfo.h:1.6 --- llvm/include/llvm/CodeGen/MachineModuleInfo.h:1.5 Wed Feb 21 16:38:31 2007 +++ llvm/include/llvm/CodeGen/MachineModuleInfo.h Thu Feb 22 10:40:10 2007 @@ -1014,7 +1014,7 @@ // in the current function. std::vector LandingPads; - // TypeInfos - List of C++ TypeInfo used in the currect function. + // TypeInfos - List of C++ TypeInfo used in the current function. // std::vector TypeInfos; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: TargetLowering.cpp updated: 1.92 -> 1.93 --- Log message: Need to init. --- Diffs of the changes: (+2 -0) TargetLowering.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp diff -u llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.92 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.93 --- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.92 Sat Feb 17 00:00:35 2007 +++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cppThu Feb 22 12:04:49 2007 @@ -151,6 +151,8 @@ IntDivIsCheap = false; Pow2DivIsCheap = false; StackPointerRegisterToSaveRestore = 0; + ExceptionPointerRegister = 0; + ExceptionSelectorRegister = 0; SchedPreferenceInfo = SchedulingForLatency; JumpBufSize = 0; JumpBufAlignment = 0; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/DwarfWriter.cpp
Changes in directory llvm/lib/CodeGen:
DwarfWriter.cpp updated: 1.126 -> 1.127
---
Log message:
Missing end of abbreviations.
---
Diffs of the changes: (+3 -0)
DwarfWriter.cpp |3 +++
1 files changed, 3 insertions(+)
Index: llvm/lib/CodeGen/DwarfWriter.cpp
diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.126
llvm/lib/CodeGen/DwarfWriter.cpp:1.127
--- llvm/lib/CodeGen/DwarfWriter.cpp:1.126 Wed Feb 21 16:48:45 2007
+++ llvm/lib/CodeGen/DwarfWriter.cppThu Feb 22 12:22:42 2007
@@ -2104,6 +2104,9 @@
Asm->EOL();
}
+ // Mark end of abbreviations.
+ DD.getAsm()->EmitULEB128Bytes(0); DD.getAsm()->EOL("EOM(3)");
+
EmitLabel("abbrev_end", 0);
Asm->EOL();
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[llvm-commits] CVS: llvm/lib/CodeGen/DwarfWriter.cpp
Changes in directory llvm/lib/CodeGen:
DwarfWriter.cpp updated: 1.127 -> 1.128
---
Log message:
Missing end of abbreviations - correction
---
Diffs of the changes: (+1 -1)
DwarfWriter.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/DwarfWriter.cpp
diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.127
llvm/lib/CodeGen/DwarfWriter.cpp:1.128
--- llvm/lib/CodeGen/DwarfWriter.cpp:1.127 Thu Feb 22 12:22:42 2007
+++ llvm/lib/CodeGen/DwarfWriter.cppThu Feb 22 12:48:52 2007
@@ -2105,7 +2105,7 @@
}
// Mark end of abbreviations.
- DD.getAsm()->EmitULEB128Bytes(0); DD.getAsm()->EOL("EOM(3)");
+ Asm->EmitULEB128Bytes(0); Asm->EOL("EOM(3)");
EmitLabel("abbrev_end", 0);
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[llvm-commits] CVS: llvm/lib/CodeGen/IntrinsicLowering.cpp
Changes in directory llvm/lib/CodeGen:
IntrinsicLowering.cpp updated: 1.69 -> 1.70
---
Log message:
Update comment.
---
Diffs of the changes: (+1 -1)
IntrinsicLowering.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/IntrinsicLowering.cpp
diff -u llvm/lib/CodeGen/IntrinsicLowering.cpp:1.69
llvm/lib/CodeGen/IntrinsicLowering.cpp:1.70
--- llvm/lib/CodeGen/IntrinsicLowering.cpp:1.69 Thu Feb 22 10:12:17 2007
+++ llvm/lib/CodeGen/IntrinsicLowering.cpp Thu Feb 22 12:51:19 2007
@@ -358,7 +358,7 @@
case Intrinsic::dbg_declare:
case Intrinsic::eh_exception:
case Intrinsic::eh_handlers:
-break;// Simply strip out debugging intrinsics
+break;// Simply strip out debugging and eh intrinsics
case Intrinsic::memcpy_i32:
case Intrinsic::memcpy_i64: {
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[llvm-commits] [124197] Add a "LLVM_MINOR_VERSION" macro to Version.h.
Revision: 124197
Author: bwendlin
Date: 2007-02-22 13:25:13 -0800 (Thu, 22 Feb 2007)
Log Message:
---
Add a "LLVM_MINOR_VERSION" macro to Version.h.
Modified Paths:
--
apple-local/branches/llvm/build_gcc
Modified: apple-local/branches/llvm/build_gcc
===
--- apple-local/branches/llvm/build_gcc 2007-02-22 12:30:12 UTC (rev 124196)
+++ apple-local/branches/llvm/build_gcc 2007-02-22 21:25:13 UTC (rev 124197)
@@ -565,7 +565,25 @@
make $MAKEFLAGS ENABLE_OPTIMIZED=1 UNIVERSAL=1 OPTIMIZE_OPTION='-O2' install
## Install Version.h
+ if [ "x$LLVM_SUBMIT_SUBVERSION" = "x00" -o "x$LLVM_SUBMIT_SUBVERSION" = "x0"
]; then
+ RC_ProjectSourceSubversion=0
+ else
+ case "$LLVM_SUBMIT_SUBVERSION" in
+ 01) RC_ProjectSourceSubversion=1 ;;
+ 02) RC_ProjectSourceSubversion=2 ;;
+ 03) RC_ProjectSourceSubversion=3 ;;
+ 04) RC_ProjectSourceSubversion=4 ;;
+ 05) RC_ProjectSourceSubversion=5 ;;
+ 06) RC_ProjectSourceSubversion=6 ;;
+ 07) RC_ProjectSourceSubversion=7 ;;
+ 08) RC_ProjectSourceSubversion=8 ;;
+ 09) RC_ProjectSourceSubversion=9 ;;
+ *) RC_ProjectSourceSubversion=$LLVM_SUBMIT_SUBVERSION ;;
+ esac
+ fi
+
echo "#define LLVM_VERSION ${RC_ProjectSourceVersion}" >
$DEST_DIR$LLVM_INSTALL_PREFIX/include/llvm/Version.h
+ echo "#define LLVM_MINOR_VERSION ${RC_ProjectSourceSubversion}" >>
$DEST_DIR$LLVM_INSTALL_PREFIX/include/llvm/Version.h
## Strip local symbols from llvm libraries.
strip -S $DEST_DIR$LLVM_INSTALL_PREFIX/lib/*.[oa]
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h
Changes in directory llvm/include/llvm/CodeGen:
LiveIntervalAnalysis.h updated: 1.72 -> 1.73
---
Log message:
Remove unnecessary isKill properties if a live range has been lengthened due to
coalescing.
---
Diffs of the changes: (+11 -0)
LiveIntervalAnalysis.h | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h
diff -u llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h:1.72
llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h:1.73
--- llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h:1.72 Wed Feb 21
16:41:17 2007
+++ llvm/include/llvm/CodeGen/LiveIntervalAnalysis.hThu Feb 22 17:03:39 2007
@@ -172,6 +172,13 @@
}
private:
+/// isRemoved - returns true if the specified machine instr has been
+/// removed.
+bool isRemoved(MachineInstr* instr) const {
+ Mi2IndexMap::const_iterator it = mi2iMap_.find(instr);
+ return it == mi2iMap_.end();
+}
+
/// RemoveMachineInstrFromMaps - This marks the specified machine instr as
/// deleted.
void RemoveMachineInstrFromMaps(MachineInstr *MI) {
@@ -256,6 +263,10 @@
/// reg between indexes Start and End.
bool hasRegisterUse(unsigned Reg, unsigned Start, unsigned End);
+/// unsetRegisterKill - Unset IsKill property of all uses of specific
+/// register of the specific instruction.
+void unsetRegisterKill(MachineInstr *MI, unsigned Reg);
+
static LiveInterval createInterval(unsigned Reg);
void removeInterval(unsigned Reg) {
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[llvm-commits] CVS: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
Changes in directory llvm/lib/CodeGen:
LiveIntervalAnalysis.cpp updated: 1.211 -> 1.212
---
Log message:
Remove unnecessary isKill properties if a live range has been lengthened due to
coalescing.
---
Diffs of the changes: (+24 -1)
LiveIntervalAnalysis.cpp | 25 -
1 files changed, 24 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
diff -u llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.211
llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.212
--- llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.211 Wed Feb 21 16:41:17 2007
+++ llvm/lib/CodeGen/LiveIntervalAnalysis.cpp Thu Feb 22 17:03:39 2007
@@ -959,10 +959,22 @@
DOUT << "\n\t\tJoined. Result = "; DestInt.print(DOUT, mri_);
DOUT << "\n";
-
+
// If the intervals were swapped by Join, swap them back so that the register
// mapping (in the r2i map) is correct.
if (Swapped) SrcInt.swap(DestInt);
+
+ // Live range has been lengthened due to colaescing, eliminate the
+ // unnecessary kills at the end of the source live ranges.
+ LiveVariables::VarInfo& vi = lv_->getVarInfo(repSrcReg);
+ for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
+MachineInstr *Kill = vi.Kills[i];
+if (Kill == CopyMI || isRemoved(Kill))
+ continue;
+if (DestInt.liveAt(getInstructionIndex(Kill) + InstrSlots::NUM))
+ unsetRegisterKill(Kill, repSrcReg);
+ }
+
removeInterval(repSrcReg);
r2rMap_[repSrcReg] = repDstReg;
@@ -1471,6 +1483,17 @@
return false;
}
+/// unsetRegisterKill - Unset IsKill property of all uses of specific register
+/// of the specific instruction.
+void LiveIntervals::unsetRegisterKill(MachineInstr *MI, unsigned Reg) {
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+MachineOperand &MO = MI->getOperand(i);
+if (MO.isReg() && MO.isUse() && MO.isKill() && MO.getReg() &&
+mri_->regsOverlap(rep(MO.getReg()), Reg))
+ MO.unsetIsKill();
+ }
+}
+
LiveInterval LiveIntervals::createInterval(unsigned reg) {
float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
HUGE_VALF : 0.0F;
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[llvm-commits] CVS: llvm/lib/Analysis/LoopPass.cpp
Changes in directory llvm/lib/Analysis:
LoopPass.cpp updated: 1.1 -> 1.2
---
Log message:
Add LoopQueue. This is used by loop pass manager to manage loop nest.
---
Diffs of the changes: (+36 -0)
LoopPass.cpp | 36
1 files changed, 36 insertions(+)
Index: llvm/lib/Analysis/LoopPass.cpp
diff -u llvm/lib/Analysis/LoopPass.cpp:1.1 llvm/lib/Analysis/LoopPass.cpp:1.2
--- llvm/lib/Analysis/LoopPass.cpp:1.1 Thu Feb 22 02:56:17 2007
+++ llvm/lib/Analysis/LoopPass.cpp Thu Feb 22 17:30:07 2007
@@ -14,13 +14,49 @@
//===--===//
#include "llvm/Analysis/LoopPass.h"
+#include
using namespace llvm;
//===--===//
+// LoopQueue
+
+namespace llvm {
+
+// Compare Two loops based on their depth in loop nest.
+class LoopCompare {
+public:
+ bool operator()( Loop *L1, Loop *L2) const {
+return L1->getLoopDepth() > L2->getLoopDepth();
+ }
+};
+
+// Loop queue used by Loop Pass Manager. This is a wrapper class
+// that hides implemenation detail (use of priority_queue) inside .cpp file.
+class LoopQueue {
+
+ inline void push(Loop *L) { LPQ.push(L); }
+ inline void pop() { LPQ.pop(); }
+ inline Loop *top() { return LPQ.top(); }
+
+private:
+ std::priority_queue, LoopCompare> LPQ;
+};
+
+} // End of LLVM namespace
+
+//===--===//
// LPPassManager
//
/// LPPassManager manages FPPassManagers and CalLGraphSCCPasses.
+LPPassManager::LPPassManager(int Depth) : PMDataManager(Depth) {
+ LQ = new LoopQueue();
+}
+
+LPPassManager::~LPPassManager() {
+ delete LQ;
+}
+
/// run - Execute all of the passes scheduled for execution. Keep track of
/// whether any of the passes modifies the function, and if so, return true.
bool LPPassManager::runOnFunction(Function &F) {
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[llvm-commits] CVS: llvm/include/llvm/Analysis/LoopPass.h
Changes in directory llvm/include/llvm/Analysis:
LoopPass.h updated: 1.1 -> 1.2
---
Log message:
Add LoopQueue. This is used by loop pass manager to manage loop nest.
---
Diffs of the changes: (+6 -1)
LoopPass.h |7 ++-
1 files changed, 6 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/Analysis/LoopPass.h
diff -u llvm/include/llvm/Analysis/LoopPass.h:1.1
llvm/include/llvm/Analysis/LoopPass.h:1.2
--- llvm/include/llvm/Analysis/LoopPass.h:1.1 Thu Feb 22 02:56:17 2007
+++ llvm/include/llvm/Analysis/LoopPass.h Thu Feb 22 17:30:07 2007
@@ -25,6 +25,7 @@
class LPPassManager;
class Loop;
class Function;
+class LoopQueue;
class LoopPass : public Pass {
@@ -41,7 +42,8 @@
class LPPassManager : public FunctionPass, public PMDataManager {
public:
- LPPassManager(int Depth) : PMDataManager(Depth) { }
+ LPPassManager(int Depth);
+ ~LPPassManager();
/// run - Execute all of the passes scheduled for execution. Keep track of
/// whether any of the passes modifies the module, and if so, return true.
@@ -79,6 +81,9 @@
return PMT_LoopPassManager;
}
+ private:
+ LoopQueue *LQ;
+
};
} // End llvm namespace
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[llvm-commits] CVS: llvm/lib/Analysis/LoopPass.cpp
Changes in directory llvm/lib/Analysis:
LoopPass.cpp updated: 1.2 -> 1.3
---
Log message:
Populate and walk loop queue.
---
Diffs of the changes: (+20 -6)
LoopPass.cpp | 26 --
1 files changed, 20 insertions(+), 6 deletions(-)
Index: llvm/lib/Analysis/LoopPass.cpp
diff -u llvm/lib/Analysis/LoopPass.cpp:1.2 llvm/lib/Analysis/LoopPass.cpp:1.3
--- llvm/lib/Analysis/LoopPass.cpp:1.2 Thu Feb 22 17:30:07 2007
+++ llvm/lib/Analysis/LoopPass.cpp Thu Feb 22 17:45:15 2007
@@ -33,11 +33,11 @@
// Loop queue used by Loop Pass Manager. This is a wrapper class
// that hides implemenation detail (use of priority_queue) inside .cpp file.
class LoopQueue {
-
+public:
inline void push(Loop *L) { LPQ.push(L); }
inline void pop() { LPQ.pop(); }
inline Loop *top() { return LPQ.top(); }
-
+ inline bool empty() { return LPQ.empty(); }
private:
std::priority_queue, LoopCompare> LPQ;
};
@@ -57,22 +57,33 @@
delete LQ;
}
+// Recurse through all subloops and all loops into LQ.
+static void addLoopIntoQueue(Loop *L, LoopQueue *LQ) {
+ for (Loop::iterator I = L->begin(), E = L->end(); I != E; ++I)
+addLoopIntoQueue(*I, LQ);
+ LQ->push(L);
+}
+
/// run - Execute all of the passes scheduled for execution. Keep track of
/// whether any of the passes modifies the function, and if so, return true.
bool LPPassManager::runOnFunction(Function &F) {
LoopInfo &LI = getAnalysis();
bool Changed = false;
+ // Populate Loop Queue
+ for (LoopInfo::iterator I = LI.begin(), E = LI.end(); I != E; ++I)
+addLoopIntoQueue(*I, LQ);
+
std::string Msg1 = "Executing Pass '";
std::string Msg3 = "' Made Modification '";
// Walk Loops
- for (LoopInfo::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
-
-Loop *L = *I;
+ while (!LQ->empty()) {
+
+Loop *L = LQ->top();
// Run all passes on current SCC
for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) {
-
+
Pass *P = getContainedPass(Index);
AnalysisUsage AnUsage;
P->getAnalysisUsage(AnUsage);
@@ -97,6 +108,9 @@
recordAvailableAnalysis(P);
removeDeadPasses(P, Msg2);
}
+
+// Pop the loop from queue after running all passes.
+LQ->pop();
}
return Changed;
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/LICENSE.TXT
Changes in directory llvm/lib/Target/PowerPC: LICENSE.TXT (r1.2) removed --- Log message: remove obsolete file --- Diffs of the changes: (+0 -0) 0 files changed ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h
Changes in directory llvm/include/llvm/CodeGen:
LiveIntervalAnalysis.h updated: 1.73 -> 1.74
---
Log message:
Copy and paste silliness.
---
Diffs of the changes: (+1 -2)
LiveIntervalAnalysis.h |3 +--
1 files changed, 1 insertion(+), 2 deletions(-)
Index: llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h
diff -u llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h:1.73
llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h:1.74
--- llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h:1.73 Thu Feb 22
17:03:39 2007
+++ llvm/include/llvm/CodeGen/LiveIntervalAnalysis.hThu Feb 22 17:52:23 2007
@@ -175,8 +175,7 @@
/// isRemoved - returns true if the specified machine instr has been
/// removed.
bool isRemoved(MachineInstr* instr) const {
- Mi2IndexMap::const_iterator it = mi2iMap_.find(instr);
- return it == mi2iMap_.end();
+ return !mi2iMap_.count(instr);
}
/// RemoveMachineInstrFromMaps - This marks the specified machine instr as
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[llvm-commits] CVS: llvm/include/llvm/Analysis/LoopPass.h
Changes in directory llvm/include/llvm/Analysis: LoopPass.h updated: 1.2 -> 1.3 --- Log message: Add LPPassManager interface that LoopPass can use to skip rest of the passes in the queue for a loop. --- Diffs of the changes: (+6 -1) LoopPass.h |7 ++- 1 files changed, 6 insertions(+), 1 deletion(-) Index: llvm/include/llvm/Analysis/LoopPass.h diff -u llvm/include/llvm/Analysis/LoopPass.h:1.2 llvm/include/llvm/Analysis/LoopPass.h:1.3 --- llvm/include/llvm/Analysis/LoopPass.h:1.2 Thu Feb 22 17:30:07 2007 +++ llvm/include/llvm/Analysis/LoopPass.h Thu Feb 22 18:10:16 2007 @@ -81,8 +81,13 @@ return PMT_LoopPassManager; } - private: +public: + // Delete loop from the loop queue. This is used by Loop pass to inform + // Loop Pass Manager that it should skip rest of the passes for this loop. + void deleteLoopFromQueue(Loop *L); +private: LoopQueue *LQ; + bool skipThisLoop; }; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Analysis/LoopPass.cpp
Changes in directory llvm/lib/Analysis:
LoopPass.cpp updated: 1.3 -> 1.4
---
Log message:
Add LPPassManager interface that LoopPass can use to skip
rest of the passes in the queue for a loop.
---
Diffs of the changes: (+13 -0)
LoopPass.cpp | 13 +
1 files changed, 13 insertions(+)
Index: llvm/lib/Analysis/LoopPass.cpp
diff -u llvm/lib/Analysis/LoopPass.cpp:1.3 llvm/lib/Analysis/LoopPass.cpp:1.4
--- llvm/lib/Analysis/LoopPass.cpp:1.3 Thu Feb 22 17:45:15 2007
+++ llvm/lib/Analysis/LoopPass.cpp Thu Feb 22 18:10:16 2007
@@ -57,6 +57,13 @@
delete LQ;
}
+/// Delete loop from the loop queue. This is used by Loop pass to inform
+/// Loop Pass Manager that it should skip rest of the passes for this loop.
+void LPPassManager::deleteLoopFromQueue(Loop *L) {
+ // Do not pop loop from LQ here. It will be done by runOnFunction while loop.
+ skipThisLoop = true;
+}
+
// Recurse through all subloops and all loops into LQ.
static void addLoopIntoQueue(Loop *L, LoopQueue *LQ) {
for (Loop::iterator I = L->begin(), E = L->end(); I != E; ++I)
@@ -81,6 +88,8 @@
while (!LQ->empty()) {
Loop *L = LQ->top();
+skipThisLoop = false;
+
// Run all passes on current SCC
for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) {
@@ -107,6 +116,10 @@
removeNotPreservedAnalysis(P);
recordAvailableAnalysis(P);
removeDeadPasses(P, Msg2);
+
+ if (skipThisLoop)
+// Do not run other passes on this loop.
+break;
}
// Pop the loop from queue after running all passes.
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[llvm-commits] CVS: llvm/include/llvm/Analysis/LoopPass.h
Changes in directory llvm/include/llvm/Analysis: LoopPass.h updated: 1.3 -> 1.4 --- Log message: Add facility that allows LoopPass to re-insert a loop into Loop Pass Manager's queue. --- Diffs of the changes: (+6 -1) LoopPass.h |7 ++- 1 files changed, 6 insertions(+), 1 deletion(-) Index: llvm/include/llvm/Analysis/LoopPass.h diff -u llvm/include/llvm/Analysis/LoopPass.h:1.3 llvm/include/llvm/Analysis/LoopPass.h:1.4 --- llvm/include/llvm/Analysis/LoopPass.h:1.3 Thu Feb 22 18:10:16 2007 +++ llvm/include/llvm/Analysis/LoopPass.h Thu Feb 22 18:16:44 2007 @@ -85,10 +85,15 @@ // Delete loop from the loop queue. This is used by Loop pass to inform // Loop Pass Manager that it should skip rest of the passes for this loop. void deleteLoopFromQueue(Loop *L); + + // Reoptimize this loop. LPPassManager will re-insert this loop into the + // queue. This allows LoopPass to change loop nest for the loop. This + // utility may send LPPassManager into infinite loops so use caution. + void redoLoop(Loop *L); private: LoopQueue *LQ; bool skipThisLoop; - + bool redoThisLoop; }; } // End llvm namespace ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Analysis/LoopPass.cpp
Changes in directory llvm/lib/Analysis:
LoopPass.cpp updated: 1.4 -> 1.5
---
Log message:
Add facility that allows LoopPass to re-insert a loop into
Loop Pass Manager's queue.
---
Diffs of the changes: (+13 -0)
LoopPass.cpp | 13 +
1 files changed, 13 insertions(+)
Index: llvm/lib/Analysis/LoopPass.cpp
diff -u llvm/lib/Analysis/LoopPass.cpp:1.4 llvm/lib/Analysis/LoopPass.cpp:1.5
--- llvm/lib/Analysis/LoopPass.cpp:1.4 Thu Feb 22 18:10:16 2007
+++ llvm/lib/Analysis/LoopPass.cpp Thu Feb 22 18:16:44 2007
@@ -50,6 +50,8 @@
/// LPPassManager manages FPPassManagers and CalLGraphSCCPasses.
LPPassManager::LPPassManager(int Depth) : PMDataManager(Depth) {
+ skipThisLoop = false;
+ redoThisLoop = false;
LQ = new LoopQueue();
}
@@ -64,6 +66,13 @@
skipThisLoop = true;
}
+// Reoptimize this loop. LPPassManager will re-insert this loop into the
+// queue. This allows LoopPass to change loop nest for the loop. This
+// utility may send LPPassManager into infinite loops so use caution.
+void LPPassManager::redoLoop(Loop *L) {
+ redoThisLoop = true;
+}
+
// Recurse through all subloops and all loops into LQ.
static void addLoopIntoQueue(Loop *L, LoopQueue *LQ) {
for (Loop::iterator I = L->begin(), E = L->end(); I != E; ++I)
@@ -89,6 +98,7 @@
Loop *L = LQ->top();
skipThisLoop = false;
+redoThisLoop = false;
// Run all passes on current SCC
for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) {
@@ -124,6 +134,9 @@
// Pop the loop from queue after running all passes.
LQ->pop();
+
+if (redoThisLoop)
+ LQ->push(L);
}
return Changed;
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[llvm-commits] CVS: llvm/lib/Analysis/LoopPass.cpp
Changes in directory llvm/lib/Analysis:
LoopPass.cpp updated: 1.5 -> 1.6
---
Log message:
Teach LoopPass to assign itself one Loop Pass Manager.
---
Diffs of the changes: (+41 -0)
LoopPass.cpp | 41 +
1 files changed, 41 insertions(+)
Index: llvm/lib/Analysis/LoopPass.cpp
diff -u llvm/lib/Analysis/LoopPass.cpp:1.5 llvm/lib/Analysis/LoopPass.cpp:1.6
--- llvm/lib/Analysis/LoopPass.cpp:1.5 Thu Feb 22 18:16:44 2007
+++ llvm/lib/Analysis/LoopPass.cpp Thu Feb 22 18:36:57 2007
@@ -143,3 +143,44 @@
}
+//===--===//
+// LoopPass
+
+/// Assign pass manager to manage this pass.
+void LoopPass::assignPassManager(PMStack &PMS,
+ PassManagerType PreferredType) {
+ // Find LPPassManager
+ while (!PMS.empty()) {
+if (PMS.top()->getPassManagerType() > PMT_LoopPassManager)
+ PMS.pop();
+else;
+break;
+ }
+
+ LPPassManager *LPPM = dynamic_cast(PMS.top());
+
+ // Create new Loop Pass Manager if it does not exist.
+ if (!LPPM) {
+
+assert (!PMS.empty() && "Unable to create Loop Pass Manager");
+PMDataManager *PMD = PMS.top();
+
+// [1] Create new Call Graph Pass Manager
+LPPM = new LPPassManager(PMD->getDepth() + 1);
+
+// [2] Set up new manager's top level manager
+PMTopLevelManager *TPM = PMD->getTopLevelManager();
+TPM->addIndirectPassManager(LPPM);
+
+// [3] Assign manager to manage this new manager. This may create
+// and push new managers into PMS
+Pass *P = dynamic_cast(LPPM);
+P->assignPassManager(PMS);
+
+// [4] Push new manager into PMS
+PMS.push(LPPM);
+ }
+
+ LPPM->add(this);
+}
+
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[llvm-commits] CVS: llvm/include/llvm/Analysis/LoopPass.h
Changes in directory llvm/include/llvm/Analysis:
LoopPass.h updated: 1.4 -> 1.5
---
Log message:
Teach LoopPass to assign itself one Loop Pass Manager.
---
Diffs of the changes: (+4 -0)
LoopPass.h |4
1 files changed, 4 insertions(+)
Index: llvm/include/llvm/Analysis/LoopPass.h
diff -u llvm/include/llvm/Analysis/LoopPass.h:1.4
llvm/include/llvm/Analysis/LoopPass.h:1.5
--- llvm/include/llvm/Analysis/LoopPass.h:1.4 Thu Feb 22 18:16:44 2007
+++ llvm/include/llvm/Analysis/LoopPass.h Thu Feb 22 18:36:57 2007
@@ -37,6 +37,10 @@
return false;
}
+ /// Assign pass manager to manager this pass
+ virtual void assignPassManager(PMStack &PMS,
+PassManagerType PMT = PMT_LoopPassManager);
+
};
class LPPassManager : public FunctionPass, public PMDataManager {
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/RegisterScavenging.h
Changes in directory llvm/include/llvm/CodeGen:
RegisterScavenging.h added (r1.1)
---
Log message:
Initial check in of register scavenger. Its only current functionality is
tracking live registers per MBB.
---
Diffs of the changes: (+75 -0)
RegisterScavenging.h | 75 +++
1 files changed, 75 insertions(+)
Index: llvm/include/llvm/CodeGen/RegisterScavenging.h
diff -c /dev/null llvm/include/llvm/CodeGen/RegisterScavenging.h:1.1
*** /dev/null Thu Feb 22 19:01:29 2007
--- llvm/include/llvm/CodeGen/RegisterScavenging.h Thu Feb 22 19:01:19 2007
***
*** 0
--- 1,75
+ //===-- RegisterScavenging.h - Machine register scavenging --*- C++
-*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the Evan Cheng and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+
//===--===//
+ //
+ // This file declares the machine register scavenger class. It can provide
+ // information such as unused register at any point in a machine basic block.
+ // It also provides a mechanism to make registers availbale by evicting them
+ // to spill slots.
+ //
+
//===--===//
+
+ #ifndef LLVM_CODEGEN_REGISTER_SCAVENGING_H
+ #define LLVM_CODEGEN_REGISTER_SCAVENGING_H
+
+ #include "llvm/CodeGen/MachineBasicBlock.h"
+ #include "llvm/ADT/BitVector.h"
+
+ namespace llvm {
+
+ class TargetRegisterClass;
+
+ class RegScavenger {
+ MachineBasicBlock *MBB;
+ MachineBasicBlock::iterator MBBI;
+ unsigned NumPhysRegs;
+
+ /// RegStates - The current state of all the physical registers immediately
+ /// before MBBI. One bit per physical register. If bit is set that means
it's
+ /// available, unset means the register is currently being used.
+ BitVector RegStates;
+
+ public:
+ RegScavenger(MachineBasicBlock *mbb);
+
+ /// forward / backward - Move the internal MBB iterator and update register
+ /// states.
+ void forward();
+ void backward();
+
+ /// isReserved - Returns true if a register is reserved. It is never
"unused".
+ bool isReserved(unsigned Reg) const { return ReservedRegs[Reg]; }
+
+ /// isUsed / isUsed - Test if a register is currently being used.
+ ///
+ bool isUsed(unsigned Reg) const { return !RegStates[Reg]; }
+ bool isUnused(unsigned Reg) const { return RegStates[Reg]; }
+
+ /// setUsed / setUnused - Mark the state of one or a number of registers.
+ ///
+ void setUsed(unsigned Reg) { RegStates.reset(Reg); }
+ void setUsed(BitVector Regs) { RegStates &= ~Regs; }
+ void setUnused(unsigned Reg) { RegStates.set(Reg); }
+ void setUnused(BitVector Regs) { RegStates |= Regs; }
+
+ /// FindUnusedReg - Find a unused register of the specified register class.
+ /// Exclude callee saved registers if directed. It return 0 is none is
found.
+ unsigned FindUnusedReg(const TargetRegisterClass *RegClass,
+ bool ExCalleeSaved = false) const;
+
+ private:
+ /// CalleeSavedrRegs - A bitvector of callee saved registers for the target.
+ BitVector CalleeSavedRegs;
+
+ /// ReservedRegs - A bitvector of reserved registers.
+ BitVector ReservedRegs;
+ };
+
+ } // End llvm namespace
+
+ #endif
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[llvm-commits] CVS: llvm/lib/CodeGen/RegisterScavenging.cpp
Changes in directory llvm/lib/CodeGen:
RegisterScavenging.cpp added (r1.1)
---
Log message:
Initial check in of register scavenger. Its only current functionality is
tracking live registers per MBB.
---
Diffs of the changes: (+140 -0)
RegisterScavenging.cpp | 140 +
1 files changed, 140 insertions(+)
Index: llvm/lib/CodeGen/RegisterScavenging.cpp
diff -c /dev/null llvm/lib/CodeGen/RegisterScavenging.cpp:1.1
*** /dev/null Thu Feb 22 19:01:29 2007
--- llvm/lib/CodeGen/RegisterScavenging.cpp Thu Feb 22 19:01:19 2007
***
*** 0
--- 1,140
+ //===-- RegisterScavenging.cpp - Machine register scavenging
--===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the Evan Cheng and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+
//===--===//
+ //
+ // This file implements the machine register scavenger. It can provide
+ // information such as unused register at any point in a machine basic block.
+ // It also provides a mechanism to make registers availbale by evicting them
+ // to spill slots.
+ //
+
//===--===//
+
+ #define DEBUG_TYPE "reg-scavenging"
+ #include "llvm/CodeGen/RegisterScavenging.h"
+ #include "llvm/CodeGen/MachineFunction.h"
+ #include "llvm/CodeGen/MachineBasicBlock.h"
+ #include "llvm/CodeGen/MachineInstr.h"
+ #include "llvm/Target/MRegisterInfo.h"
+ #include "llvm/Target/TargetInstrInfo.h"
+ #include "llvm/Target/TargetMachine.h"
+ using namespace llvm;
+
+ RegScavenger::RegScavenger(MachineBasicBlock *mbb)
+ : MBB(mbb), MBBI(mbb->begin()) {
+ const MachineFunction &MF = *MBB->getParent();
+ const TargetMachine &TM = MF.getTarget();
+ const MRegisterInfo *RegInfo = TM.getRegisterInfo();
+
+ NumPhysRegs = RegInfo->getNumRegs();
+ RegStates.resize(NumPhysRegs, true);
+
+ // Create reserved registers bitvector.
+ ReservedRegs = RegInfo->getReservedRegs(MF);
+ RegStates ^= ReservedRegs;
+
+ // Create callee-saved registers bitvector.
+ CalleeSavedRegs.resize(NumPhysRegs);
+ const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
+ if (CSRegs != NULL)
+ for (unsigned i = 0; CSRegs[i]; ++i)
+ CalleeSavedRegs.set(CSRegs[i]);
+ }
+
+ void RegScavenger::forward() {
+ MachineInstr *MI = MBBI;
+ // Process uses first.
+ BitVector ChangedRegs(NumPhysRegs);
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI->getOperand(i);
+ if (!MO.isReg() || !MO.isUse())
+ continue;
+ unsigned Reg = MO.getReg();
+ if (Reg == 0)
+ continue;
+ assert(isUsed(Reg));
+ if (MO.isKill() && !isReserved(Reg))
+ ChangedRegs.set(Reg);
+ }
+ // Change states of all registers after all the uses are processed to guard
+ // against multiple uses.
+ setUnused(ChangedRegs);
+
+ // Process defs.
+ const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI->getOperand(i);
+ if (!MO.isReg() || !MO.isDef())
+ continue;
+ // Skip two-address destination operand.
+ if (TID->findTiedToSrcOperand(i) != -1)
+ continue;
+ unsigned Reg = MO.getReg();
+ assert(isUnused(Reg) || isReserved(Reg));
+ if (!MO.isDead())
+ setUsed(Reg);
+ }
+
+ ++MBBI;
+ }
+
+ void RegScavenger::backward() {
+ MachineInstr *MI = --MBBI;
+ // Process defs first.
+ const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI->getOperand(i);
+ if (!MO.isReg() || !MO.isDef())
+ continue;
+ // Skip two-address destination operand.
+ if (TID->findTiedToSrcOperand(i) != -1)
+ continue;
+ unsigned Reg = MO.getReg();
+ assert(isUsed(Reg));
+ if (!isReserved(Reg))
+ setUnused(Reg);
+ }
+
+ // Process uses.
+ BitVector ChangedRegs(NumPhysRegs);
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI->getOperand(i);
+ if (!MO.isReg() || !MO.isUse())
+ continue;
+ unsigned Reg = MO.getReg();
+ if (Reg == 0)
+ continue;
+ assert(isUnused(Reg) || isReserved(Reg));
+ ChangedRegs.set(Reg);
+ }
+ setUsed(ChangedRegs);
+ }
+
+ /// CreateRegClassMask - Set the bits that represent the registers in the
+ /// TargetRegisterClass.
+ static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector
&Mask) {
+ for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E;
+++I)
+ Mask.set(*I);
+ }
+
+ unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
+
[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h
Changes in directory llvm/include/llvm/CodeGen: MachineInstr.h updated: 1.212 -> 1.213 --- Log message: Use findRegisterUseOperand to find a kill of particular register. --- Diffs of the changes: (+3 -2) MachineInstr.h |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.212 llvm/include/llvm/CodeGen/MachineInstr.h:1.213 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.212 Mon Feb 19 15:49:53 2007 +++ llvm/include/llvm/CodeGen/MachineInstr.hThu Feb 22 19:03:39 2007 @@ -390,8 +390,9 @@ } /// findRegisterUseOperand() - Returns the MachineOperand that is a use of - /// the specific register or NULL if it is not found. - MachineOperand *findRegisterUseOperand(unsigned Reg); + /// the specific register or NULL if it is not found. It further tightening + /// the search criteria to a use that kills the register if isKill is true. + MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false); /// findRegisterDefOperand() - Returns the MachineOperand that is a def of /// the specific register or NULL if it is not found. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/MachineInstr.cpp
Changes in directory llvm/lib/CodeGen:
MachineInstr.cpp updated: 1.144 -> 1.145
---
Log message:
Use findRegisterUseOperand to find a kill of particular register.
---
Diffs of the changes: (+5 -3)
MachineInstr.cpp |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/MachineInstr.cpp
diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.144
llvm/lib/CodeGen/MachineInstr.cpp:1.145
--- llvm/lib/CodeGen/MachineInstr.cpp:1.144 Mon Feb 19 15:49:53 2007
+++ llvm/lib/CodeGen/MachineInstr.cpp Thu Feb 22 19:04:26 2007
@@ -170,12 +170,14 @@
}
/// findRegisterUseOperand() - Returns the MachineOperand that is a use of
-/// the specific register or NULL if it is not found.
-MachineOperand *MachineInstr::findRegisterUseOperand(unsigned Reg) {
+/// the specific register or NULL if it is not found. It further tightening
+/// the search criteria to a use that kills the register if isKill is true.
+MachineOperand *MachineInstr::findRegisterUseOperand(unsigned Reg, bool
isKill){
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
MachineOperand &MO = getOperand(i);
if (MO.isReg() && MO.isUse() && MO.getReg() == Reg)
- return &MO;
+ if (!isKill || MO.isKill())
+return &MO;
}
return NULL;
}
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[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.96 -> 1.97
---
Log message:
Temporay hook to enable register scavening for specific targets only.
---
Diffs of the changes: (+6 -0)
MRegisterInfo.h |6 ++
1 files changed, 6 insertions(+)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.96
llvm/include/llvm/Target/MRegisterInfo.h:1.97
--- llvm/include/llvm/Target/MRegisterInfo.h:1.96 Thu Feb 22 08:56:35 2007
+++ llvm/include/llvm/Target/MRegisterInfo.hThu Feb 22 19:07:04 2007
@@ -391,6 +391,12 @@
return false;
}
+ /// requiresRegisterScavenging - returns true if the target requires (and
+ /// can make use of) the register scavenger.
+ virtual bool requiresRegisterScavenging() const {
+return false;
+ }
+
/// hasFP - Return true if the specified function should have a dedicated
frame
/// pointer register. For most targets this is true only if the function has
/// variable sized allocas or if frame pointer elimination is disabled.
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp ARMRegisterInfo.h
Changes in directory llvm/lib/Target/ARM:
ARMRegisterInfo.cpp updated: 1.70 -> 1.71
ARMRegisterInfo.h updated: 1.11 -> 1.12
---
Log message:
Add option to turn on register scavenger; By default, spills kills the register
being stored.
---
Diffs of the changes: (+20 -6)
ARMRegisterInfo.cpp | 24 ++--
ARMRegisterInfo.h |2 ++
2 files changed, 20 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.70
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.71
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.70Wed Feb 21 16:54:50 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Thu Feb 22 19:09:11 2007
@@ -31,9 +31,13 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/Support/CommandLine.h"
#include
using namespace llvm;
+static cl::opt EnableScavenging("enable-arm-reg-scavenging", cl::Hidden,
+ cl::desc("Enable register scavenging on
ARM"));
+
unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
using namespace ARM;
switch (RegEnum) {
@@ -91,8 +95,12 @@
return false;
MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH));
- for (unsigned i = CSI.size(); i != 0; --i)
-MIB.addReg(CSI[i-1].getReg());
+ for (unsigned i = CSI.size(); i != 0; --i) {
+unsigned Reg = CSI[i-1].getReg();
+// Add the callee-saved register as live-in. It's killed at the spill.
+MBB.addLiveIn(Reg);
+MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
+ }
return true;
}
@@ -130,17 +138,17 @@
MachineFunction &MF = *MBB.getParent();
ARMFunctionInfo *AFI = MF.getInfo();
if (AFI->isThumbFunction())
- BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg)
+ BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg, false, false, true)
.addFrameIndex(FI).addImm(0);
else
- BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg)
+ BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg, false, false, true)
.addFrameIndex(FI).addReg(0).addImm(0);
} else if (RC == ARM::DPRRegisterClass) {
-BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg)
+BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg, false, false, true)
.addFrameIndex(FI).addImm(0);
} else {
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
-BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg)
+BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg, false, false, true)
.addFrameIndex(FI).addImm(0);
}
}
@@ -320,6 +328,10 @@
return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
}
+bool ARMRegisterInfo::requiresRegisterScavenging() const {
+ return EnableScavenging;
+}
+
/// emitARMRegPlusImmediate - Emits a series of instructions to materialize
/// a destreg = basereg + immediate in ARM code.
static
Index: llvm/lib/Target/ARM/ARMRegisterInfo.h
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.h:1.11
llvm/lib/Target/ARM/ARMRegisterInfo.h:1.12
--- llvm/lib/Target/ARM/ARMRegisterInfo.h:1.11 Wed Feb 21 16:54:50 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.h Thu Feb 22 19:09:11 2007
@@ -69,6 +69,8 @@
BitVector getReservedRegs(const MachineFunction &MF) const;
+ bool requiresRegisterScavenging() const;
+
bool hasFP(const MachineFunction &MF) const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
Changes in directory llvm/lib/Target/Sparc: SparcRegisterInfo.cpp updated: 1.55 -> 1.56 --- Log message: By default, spills kills the register being stored. --- Diffs of the changes: (+3 -3) SparcRegisterInfo.cpp |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.55 llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.56 --- llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.55Wed Feb 21 16:54:50 2007 +++ llvm/lib/Target/Sparc/SparcRegisterInfo.cpp Thu Feb 22 19:10:04 2007 @@ -37,13 +37,13 @@ // On the order of operands here: think "[FrameIdx + 0] = SrcReg". if (RC == SP::IntRegsRegisterClass) BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0) - .addReg(SrcReg); + .addReg(SrcReg, false, false, true); else if (RC == SP::FPRegsRegisterClass) BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0) - .addReg(SrcReg); + .addReg(SrcReg, false, false, true); else if (RC == SP::DFPRegsRegisterClass) BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0) - .addReg(SrcReg); + .addReg(SrcReg, false, false, true); else assert(0 && "Can't store this register to stack slot"); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64RegisterInfo.cpp
Changes in directory llvm/lib/Target/IA64:
IA64RegisterInfo.cpp updated: 1.32 -> 1.33
---
Log message:
By default, spills kills the register being stored.
---
Diffs of the changes: (+6 -5)
IA64RegisterInfo.cpp | 11 ++-
1 files changed, 6 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/IA64/IA64RegisterInfo.cpp
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.32
llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.33
--- llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.32 Wed Feb 21 16:54:50 2007
+++ llvm/lib/Target/IA64/IA64RegisterInfo.cpp Thu Feb 22 19:10:03 2007
@@ -42,17 +42,18 @@
const TargetRegisterClass *RC)
const{
if (RC == IA64::FPRegisterClass) {
-BuildMI(MBB, MI,
TII.get(IA64::STF_SPILL)).addFrameIndex(FrameIdx).addReg(SrcReg);
+BuildMI(MBB, MI, TII.get(IA64::STF_SPILL)).addFrameIndex(FrameIdx)
+ .addReg(SrcReg, false, false, true);
} else if (RC == IA64::GRRegisterClass) {
-BuildMI(MBB, MI,
TII.get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(SrcReg);
- }
- else if (RC == IA64::PRRegisterClass) {
+BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx)
+ .addReg(SrcReg, false, false, true);
+ } else if (RC == IA64::PRRegisterClass) {
/* we use IA64::r2 as a temporary register for doing this hackery. */
// first we load 0:
BuildMI(MBB, MI, TII.get(IA64::MOV), IA64::r2).addReg(IA64::r0);
// then conditionally add 1:
BuildMI(MBB, MI, TII.get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
- .addImm(1).addReg(SrcReg);
+ .addImm(1).addReg(SrcReg, false, false, true);
// and then store it to the stack
BuildMI(MBB, MI,
TII.get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2);
} else assert(0 &&
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.109 -> 1.110
---
Log message:
By default, spills kills the register being stored.
---
Diffs of the changes: (+15 -15)
PPCRegisterInfo.cpp | 30 +++---
1 files changed, 15 insertions(+), 15 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.109
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.110
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.109 Wed Feb 21 16:54:50 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Feb 22 19:10:03 2007
@@ -104,34 +104,34 @@
const TargetRegisterClass *RC) const {
if (RC == PPC::GPRCRegisterClass) {
if (SrcReg != PPC::LR) {
- addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(SrcReg),
-FrameIdx);
+ addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW))
+.addReg(SrcReg, false, false, true), FrameIdx);
} else {
// FIXME: this spills LR immediately to memory in one step. To do this,
// we use R11, which we know cannot be used in the prolog/epilog. This
is
// a hack.
BuildMI(MBB, MI, TII.get(PPC::MFLR), PPC::R11);
- addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R11),
-FrameIdx);
+ addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW))
+.addReg(PPC::R11, false, false, true), FrameIdx);
}
} else if (RC == PPC::G8RCRegisterClass) {
if (SrcReg != PPC::LR8) {
- addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(SrcReg),
-FrameIdx);
+ addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD))
+.addReg(SrcReg, false, false, true), FrameIdx);
} else {
// FIXME: this spills LR immediately to memory in one step. To do this,
// we use R11, which we know cannot be used in the prolog/epilog. This
is
// a hack.
BuildMI(MBB, MI, TII.get(PPC::MFLR8), PPC::X11);
- addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(PPC::X11),
-FrameIdx);
+ addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD))
+.addReg(PPC::X11, false, false, true), FrameIdx);
}
} else if (RC == PPC::F8RCRegisterClass) {
-addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD)).addReg(SrcReg),
- FrameIdx);
+addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD))
+ .addReg(SrcReg, false, false, true), FrameIdx);
} else if (RC == PPC::F4RCRegisterClass) {
-addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS)).addReg(SrcReg),
- FrameIdx);
+addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS))
+ .addReg(SrcReg, false, false, true), FrameIdx);
} else if (RC == PPC::CRRCRegisterClass) {
// FIXME: We use R0 here, because it isn't available for RA.
// We need to store the CR in the low 4-bits of the saved value. First,
@@ -147,8 +147,8 @@
.addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31);
}
-addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R0),
- FrameIdx);
+addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW))
+ .addReg(PPC::R0, false, false, true), FrameIdx);
} else if (RC == PPC::VRRCRegisterClass) {
// We don't have indexed addressing for vector loads. Emit:
// R11 = ADDI FI#
@@ -158,7 +158,7 @@
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
FrameIdx, 0, 0);
BuildMI(MBB, MI, TII.get(PPC::STVX))
- .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
+ .addReg(SrcReg, false, false, true).addReg(PPC::R0).addReg(PPC::R0);
} else {
assert(0 && "Unknown regclass!");
abort();
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[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
Changes in directory llvm/lib/Target/Alpha: AlphaRegisterInfo.cpp updated: 1.61 -> 1.62 --- Log message: By default, spills kills the register being stored. --- Diffs of the changes: (+6 -3) AlphaRegisterInfo.cpp |9 ++--- 1 files changed, 6 insertions(+), 3 deletions(-) Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.61 llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.62 --- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.61Wed Feb 21 16:54:50 2007 +++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Thu Feb 22 19:10:03 2007 @@ -68,13 +68,16 @@ //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg); if (RC == Alpha::F4RCRegisterClass) BuildMI(MBB, MI, TII.get(Alpha::STS)) - .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); + .addReg(SrcReg, false, false, true) + .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::F8RCRegisterClass) BuildMI(MBB, MI, TII.get(Alpha::STT)) - .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); + .addReg(SrcReg, false, false, true) + .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::GPRCRegisterClass) BuildMI(MBB, MI, TII.get(Alpha::STQ)) - .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); + .addReg(SrcReg, false, false, true) + .addFrameIndex(FrameIdx).addReg(Alpha::F31); else abort(); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86: X86RegisterInfo.cpp updated: 1.204 -> 1.205 --- Log message: By default, spills kills the register being stored. --- Diffs of the changes: (+2 -1) X86RegisterInfo.cpp |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.204 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.205 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.204 Wed Feb 21 16:54:50 2007 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Feb 22 19:10:04 2007 @@ -93,7 +93,8 @@ assert(0 && "Unknown regclass"); abort(); } - addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx).addReg(SrcReg); + addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx) +.addReg(SrcReg, false, false, true); } void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/PrologEpilogInserter.cpp
Changes in directory llvm/lib/CodeGen:
PrologEpilogInserter.cpp updated: 1.68 -> 1.69
---
Log message:
First potential client of register scavenger.
---
Diffs of the changes: (+13 -4)
PrologEpilogInserter.cpp | 17 +
1 files changed, 13 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp
diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.68
llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.69
--- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.68 Fri Jan 26 15:22:28 2007
+++ llvm/lib/CodeGen/PrologEpilogInserter.cpp Thu Feb 22 19:11:26 2007
@@ -20,6 +20,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
@@ -231,10 +232,12 @@
MachineBasicBlock::iterator I = MBB->begin();
if (!RegInfo->spillCalleeSavedRegisters(*MBB, I, CSI)) {
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
+ // Add the callee-saved register as live-in. It's killed at the spill.
+ MBB->addLiveIn(CSI[i].getReg());
+
// Insert the spill to the stack frame.
RegInfo->storeRegToStackSlot(*MBB, I, CSI[i].getReg(),
- CSI[i].getFrameIdx(),
- CSI[i].getRegClass());
+ CSI[i].getFrameIdx(), CSI[i].getRegClass());
}
}
@@ -440,8 +443,9 @@
assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!");
const MRegisterInfo &MRI = *TM.getRegisterInfo();
- for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB)
-for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ++I)
+ for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB)
{
+RegScavenger RS(BB);
+for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ++I) {
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
if (I->getOperand(i).isFrameIndex()) {
// If this instruction has a FrameIndex operand, we need to use that
@@ -449,4 +453,9 @@
MRI.eliminateFrameIndex(I);
break;
}
+ // Update register states.
+ if (MRI.requiresRegisterScavenging())
+RS.forward();
+}
+ }
}
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[llvm-commits] CVS: llvm/lib/CodeGen/VirtRegMap.cpp
Changes in directory llvm/lib/CodeGen:
VirtRegMap.cpp updated: 1.97 -> 1.98
---
Log message:
A spill kills the register being stored. But it is later being reused by
spiller, its live range has to be extended.
---
Diffs of the changes: (+39 -25)
VirtRegMap.cpp | 64 ++---
1 files changed, 39 insertions(+), 25 deletions(-)
Index: llvm/lib/CodeGen/VirtRegMap.cpp
diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.97
llvm/lib/CodeGen/VirtRegMap.cpp:1.98
--- llvm/lib/CodeGen/VirtRegMap.cpp:1.97Tue Feb 20 20:22:03 2007
+++ llvm/lib/CodeGen/VirtRegMap.cpp Thu Feb 22 19:13:26 2007
@@ -255,7 +255,8 @@
// SpillSlotsAvailable - This map keeps track of all of the spilled virtual
// register values that are still available, due to being loaded or stored
to,
// but not invalidated yet.
- std::map SpillSlotsAvailable;
+ typedef std::pair SSInfo;
+ std::map SpillSlotsAvailable;
// PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating
// which stack slot values are currently held by a physreg. This is used to
@@ -270,27 +271,33 @@
: MRI(mri), TII(tii) {
}
+ const MRegisterInfo *getRegInfo() const { return MRI; }
+
/// getSpillSlotPhysReg - If the specified stack slot is available in a
- /// physical register, return that PhysReg, otherwise return 0.
- unsigned getSpillSlotPhysReg(int Slot) const {
-std::map::const_iterator I = SpillSlotsAvailable.find(Slot);
-if (I != SpillSlotsAvailable.end())
- return I->second >> 1; // Remove the CanClobber bit.
+ /// physical register, return that PhysReg, otherwise return 0. It also
+ /// returns by reference the instruction that either defines or last uses
+ /// the register.
+ unsigned getSpillSlotPhysReg(int Slot, MachineInstr *&SSMI) const {
+std::map::const_iterator I = SpillSlotsAvailable.find(Slot);
+if (I != SpillSlotsAvailable.end()) {
+ SSMI = I->second.second;
+ return I->second.first >> 1; // Remove the CanClobber bit.
+}
return 0;
}
- const MRegisterInfo *getRegInfo() const { return MRI; }
-
/// addAvailable - Mark that the specified stack slot is available in the
/// specified physreg. If CanClobber is true, the physreg can be modified at
/// any time without changing the semantics of the program.
- void addAvailable(int Slot, unsigned Reg, bool CanClobber = true) {
+ void addAvailable(int Slot, MachineInstr *MI, unsigned Reg,
+bool CanClobber = true) {
// If this stack slot is thought to be available in some other physreg,
// remove its record.
ModifyStackSlot(Slot);
PhysRegsAvailable.insert(std::make_pair(Reg, Slot));
-SpillSlotsAvailable[Slot] = (Reg << 1) | (unsigned)CanClobber;
+SpillSlotsAvailable[Slot] =
+ std::make_pair((Reg << 1) | (unsigned)CanClobber, MI);
DOUT << "Remembering SS#" << Slot << " in physreg "
<< MRI->getName(Reg) << "\n";
@@ -301,7 +308,7 @@
/// stack slot must be available in a physreg for this query to make sense.
bool canClobberPhysReg(int Slot) const {
assert(SpillSlotsAvailable.count(Slot) && "Slot not available!");
-return SpillSlotsAvailable.find(Slot)->second & 1;
+return SpillSlotsAvailable.find(Slot)->second.first & 1;
}
/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
@@ -330,9 +337,9 @@
while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
int Slot = I->second;
I++;
-assert((SpillSlotsAvailable[Slot] >> 1) == PhysReg &&
+assert((SpillSlotsAvailable[Slot].first >> 1) == PhysReg &&
"Bidirectional map mismatch!");
-SpillSlotsAvailable[Slot] &= ~1;
+SpillSlotsAvailable[Slot].first &= ~1;
DOUT << "PhysReg " << MRI->getName(PhysReg)
<< " copied, it is available for use but can no longer be modified\n";
}
@@ -355,7 +362,7 @@
while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
int Slot = I->second;
PhysRegsAvailable.erase(I++);
-assert((SpillSlotsAvailable[Slot] >> 1) == PhysReg &&
+assert((SpillSlotsAvailable[Slot].first >> 1) == PhysReg &&
"Bidirectional map mismatch!");
SpillSlotsAvailable.erase(Slot);
DOUT << "PhysReg " << MRI->getName(PhysReg)
@@ -376,9 +383,9 @@
/// changes. This removes information about which register the previous value
/// for this slot lives in (as the previous value is dead now).
void AvailableSpills::ModifyStackSlot(int Slot) {
- std::map::iterator It = SpillSlotsAvailable.find(Slot);
+ std::map::iterator It = SpillSlotsAvailable.find(Slot);
if (It == SpillSlotsAvailable.end()) return;
- unsigned Reg = It->second >> 1;
+ unsigned Reg = It->second.first >> 1;
SpillSlotsAvailable.erase(It);
// This register may hold the value of multiple stack slots, only remove this
@@ -514,7 +521,7 @@
MI->getOperand(NewOp.Operand).setReg(Ne
[llvm-commits] CVS: llvm/lib/Support/APInt.cpp
Changes in directory llvm/lib/Support:
APInt.cpp updated: 1.31 -> 1.32
---
Log message:
1. Fix a carry out problem in add if destination and x point to the same
memory (as done in fromString).
2. Implement Knuth divide more closely to what is recommended in his book.
3. Fix computation of the remainder for Knuth Divide (bad shifting).
4. Remove some cruft from the file
---
Diffs of the changes: (+43 -92)
APInt.cpp | 135 +++---
1 files changed, 43 insertions(+), 92 deletions(-)
Index: llvm/lib/Support/APInt.cpp
diff -u llvm/lib/Support/APInt.cpp:1.31 llvm/lib/Support/APInt.cpp:1.32
--- llvm/lib/Support/APInt.cpp:1.31 Wed Feb 21 18:58:45 2007
+++ llvm/lib/Support/APInt.cpp Thu Feb 22 19:57:13 2007
@@ -190,10 +190,10 @@
/// add - This function adds the integer array x[] by integer array
/// y[] and returns the carry.
static uint64_t add(uint64_t dest[], uint64_t x[], uint64_t y[], uint32_t len)
{
- uint64_t carry = 0;
+ bool carry = 0;
for (uint32_t i = 0; i< len; ++i) {
+uint64_t limit = std::min(x[i],y[i]); // must come first in case dest == x
dest[i] = x[i] + y[i] + carry;
-uint64_t limit = std::min(x[i],y[i]);
carry = dest[i] < limit || (carry && dest[i] == limit);
}
return carry;
@@ -979,65 +979,6 @@
return API;
}
-#if 0
-/// subMul - This function substracts x[len-1:0] * y from
-/// dest[offset+len-1:offset], and returns the most significant
-/// word of the product, minus the borrow-out from the subtraction.
-static uint32_t subMul(uint32_t dest[], uint32_t offset,
-uint32_t x[], uint32_t len, uint32_t y) {
- uint64_t yl = (uint64_t) y & 0xL;
- uint32_t carry = 0;
- uint32_t j = 0;
- do {
-uint64_t prod = ((uint64_t) x[j] & 0xUL) * yl;
-uint32_t prod_low = (uint32_t) prod;
-uint32_t prod_high = (uint32_t) (prod >> 32);
-prod_low += carry;
-carry = (prod_low < carry ? 1 : 0) + prod_high;
-uint32_t x_j = dest[offset+j];
-prod_low = x_j - prod_low;
-if (prod_low > x_j) ++carry;
-dest[offset+j] = prod_low;
- } while (++j < len);
- return carry;
-}
-
-/// unitDiv - This function divides N by D,
-/// and returns (remainder << 32) | quotient.
-/// Assumes (N >> 32) < D.
-static uint64_t unitDiv(uint64_t N, uint32_t D) {
- uint64_t q, r; // q: quotient, r: remainder.
- uint64_t a1 = N >> 32; // a1: high 32-bit part of N.
- uint64_t a0 = N & 0xL; // a0: low 32-bit part of N
- if (a1 < ((D - a1 - (a0 >> 31)) & 0xL)) {
- q = N / D;
- r = N % D;
- }
- else {
-// Compute c1*2^32 + c0 = a1*2^32 + a0 - 2^31*d
-uint64_t c = N - ((uint64_t) D << 31);
-// Divide (c1*2^32 + c0) by d
-q = c / D;
-r = c % D;
-// Add 2^31 to quotient
-q += 1 << 31;
- }
-
- return (r << 32) | (q & 0xl);
-}
-
-#endif
-
-/// div - This is basically Knuth's formulation of the classical algorithm.
-/// Correspondance with Knuth's notation:
-/// Knuth's u[0:m+n] == zds[nx:0].
-/// Knuth's v[1:n] == y[ny-1:0]
-/// Knuth's n == ny.
-/// Knuth's m == nx-ny.
-/// Our nx == Knuth's m+n.
-/// Could be re-implemented using gmp's mpn_divrem:
-/// zds[nx] = mpn_divrem (&zds[ny], 0, zds, nx, y, ny).
-
/// Implementation of Knuth's Algorithm D (Division of nonnegative integers)
/// from "Art of Computer Programming, Volume 2", section 4.3.1, p. 272. The
/// variables here have the same names as in the algorithm. Comments explain
@@ -1089,32 +1030,42 @@
// on v[n-2] determines at high speed most of the cases in which the trial
// value qp is one too large, and it eliminates all cases where qp is two
// too large.
-uint64_t qp = ((uint64_t(u[j+n]) << 32) | uint64_t(u[j+n-1])) / v[n-1];
-uint64_t rp = ((uint64_t(u[j+n]) << 32) | uint64_t(u[j+n-1])) % v[n-1];
+uint64_t dividend = ((uint64_t(u[j+n]) << 32) + u[j+n-1]);
+uint64_t qp = dividend / v[n-1];
+uint64_t rp = dividend % v[n-1];
if (qp == b || qp*v[n-2] > b*rp + u[j+n-2]) {
qp--;
rp += v[n-1];
-}
-if (rp < b)
- if (qp == b || qp*v[n-2] > b*rp + u[j+n-2]) {
-qp--;
-rp += v[n-1];
+ if (rp < b) {
+if (qp == b || qp*v[n-2] > b*rp + u[j+n-2]) {
+ qp--;
+ rp += v[n-1];
+}
}
+}
-// D4. [Multiply and subtract.] Replace u with u - q*v (for each word).
-uint32_t borrow = 0;
-for (uint32_t i = 0; i < n; i++) {
- uint32_t save = u[j+i];
- u[j+i] = uint64_t(u[j+i]) - (qp * v[i]) - borrow;
- if (u[j+i] > save) {
-borrow = 1;
-u[j+i+1] += b;
- } else {
-borrow = 0;
- }
+// D4. [Multiply and subtract.] Replace (u[j+n]u[j+n-1]...u[j]) with
+// (u[j+n]u[j+n-1]..u[j]) - qp * (v[n-1]...v[1]v[0]). This computation
+// consists of a simple multiplication by a one-place number, combined with
+// a subtraction. The di
[llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp X86TargetAsmInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86ATTAsmPrinter.cpp updated: 1.96 -> 1.97
X86TargetAsmInfo.cpp updated: 1.31 -> 1.32
---
Log message:
External weak linkage is supported by recent binutils on mingw32.
---
Diffs of the changes: (+2 -1)
X86ATTAsmPrinter.cpp |2 +-
X86TargetAsmInfo.cpp |1 +
2 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.96
llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.97
--- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.96 Tue Jan 30 14:08:38 2007
+++ llvm/lib/Target/X86/X86ATTAsmPrinter.cppThu Feb 22 19:58:50 2007
@@ -117,8 +117,8 @@
O << "\t.weak_definition\t" << CurrentFnName << "\n";
} else if (Subtarget->isTargetCygMing()) {
EmitAlignment(4, F); // FIXME: This should be parameterized
somewhere.
- O << "\t.linkonce discard\n";
O << "\t.globl " << CurrentFnName << "\n";
+ O << "\t.linkonce discard\n";
} else {
EmitAlignment(4, F); // FIXME: This should be parameterized
somewhere.
O << "\t.weak " << CurrentFnName << "\n";
Index: llvm/lib/Target/X86/X86TargetAsmInfo.cpp
diff -u llvm/lib/Target/X86/X86TargetAsmInfo.cpp:1.31
llvm/lib/Target/X86/X86TargetAsmInfo.cpp:1.32
--- llvm/lib/Target/X86/X86TargetAsmInfo.cpp:1.31 Tue Jan 30 02:04:53 2007
+++ llvm/lib/Target/X86/X86TargetAsmInfo.cppThu Feb 22 19:58:50 2007
@@ -131,6 +131,7 @@
// Set up DWARF directives
HasLEB128 = true; // Target asm supports leb128 directives (little-endian)
PrivateGlobalPrefix = "L"; // Prefix for private global symbols
+WeakRefDirective = "\t.weak\t";
DwarfRequiresFrameSection = false;
DwarfAbbrevSection = "\t.section\t.debug_abbrev,\"dr\"";
DwarfInfoSection ="\t.section\t.debug_info,\"dr\"";
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[llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.cpp
Changes in directory llvm/lib/Target/X86:
X86TargetMachine.cpp updated: 1.142 -> 1.143
---
Log message:
80 col. violation.
---
Diffs of the changes: (+2 -1)
X86TargetMachine.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86TargetMachine.cpp
diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.142
llvm/lib/Target/X86/X86TargetMachine.cpp:1.143
--- llvm/lib/Target/X86/X86TargetMachine.cpp:1.142 Tue Feb 13 23:52:17 2007
+++ llvm/lib/Target/X86/X86TargetMachine.cppThu Feb 22 21:03:16 2007
@@ -106,7 +106,8 @@
/// X86TargetMachine ctor - Create an ILP32 architecture model
///
-X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS,
bool is64Bit)
+X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS,
+ bool is64Bit)
: Subtarget(M, FS, is64Bit),
DataLayout(Subtarget.is64Bit() ?
std::string("e-p:64:64-f64:32:64-i64:32:64") :
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMSubtarget.cpp ARMSubtarget.h ARMTargetMachine.cpp ARMTargetMachine.h
Changes in directory llvm/lib/Target/ARM:
ARMSubtarget.cpp updated: 1.3 -> 1.4
ARMSubtarget.h updated: 1.3 -> 1.4
ARMTargetMachine.cpp updated: 1.24 -> 1.25
ARMTargetMachine.h updated: 1.7 -> 1.8
---
Log message:
Added -march=thumb; removed -enable-thumb.
---
Diffs of the changes: (+36 -20)
ARMSubtarget.cpp | 10 ++
ARMSubtarget.h |2 +-
ARMTargetMachine.cpp | 33 +++--
ARMTargetMachine.h | 11 ++-
4 files changed, 36 insertions(+), 20 deletions(-)
Index: llvm/lib/Target/ARM/ARMSubtarget.cpp
diff -u llvm/lib/Target/ARM/ARMSubtarget.cpp:1.3
llvm/lib/Target/ARM/ARMSubtarget.cpp:1.4
--- llvm/lib/Target/ARM/ARMSubtarget.cpp:1.3Tue Feb 13 13:52:28 2007
+++ llvm/lib/Target/ARM/ARMSubtarget.cppThu Feb 22 21:14:31 2007
@@ -14,16 +14,12 @@
#include "ARMSubtarget.h"
#include "ARMGenSubtarget.inc"
#include "llvm/Module.h"
-#include "llvm/Support/CommandLine.h"
using namespace llvm;
-// FIXME: this is temporary.
-static cl::opt Thumb("enable-thumb",
- cl::desc("Switch to thumb mode in ARM backend"));
-
-ARMSubtarget::ARMSubtarget(const Module &M, const std::string &FS)
+ARMSubtarget::ARMSubtarget(const Module &M, const std::string &FS, bool thumb)
: ARMArchVersion(V4T)
, HasVFP2(false)
+ , IsThumb(thumb)
, UseThumbBacktraces(false)
, IsR9Reserved(false)
, stackAlignment(4)
@@ -36,8 +32,6 @@
// Parse features string.
ParseSubtargetFeatures(FS, CPU);
- IsThumb = Thumb;
-
// Set the boolean corresponding to the current target triple, or the default
// if one cannot be determined, to true.
const std::string& TT = M.getTargetTriple();
Index: llvm/lib/Target/ARM/ARMSubtarget.h
diff -u llvm/lib/Target/ARM/ARMSubtarget.h:1.3
llvm/lib/Target/ARM/ARMSubtarget.h:1.4
--- llvm/lib/Target/ARM/ARMSubtarget.h:1.3 Tue Feb 13 13:52:28 2007
+++ llvm/lib/Target/ARM/ARMSubtarget.h Thu Feb 22 21:14:31 2007
@@ -60,7 +60,7 @@
/// This constructor initializes the data members to match that
/// of the specified module.
///
- ARMSubtarget(const Module &M, const std::string &FS);
+ ARMSubtarget(const Module &M, const std::string &FS, bool thumb);
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
Index: llvm/lib/Target/ARM/ARMTargetMachine.cpp
diff -u llvm/lib/Target/ARM/ARMTargetMachine.cpp:1.24
llvm/lib/Target/ARM/ARMTargetMachine.cpp:1.25
--- llvm/lib/Target/ARM/ARMTargetMachine.cpp:1.24 Tue Feb 13 23:52:17 2007
+++ llvm/lib/Target/ARM/ARMTargetMachine.cppThu Feb 22 21:14:31 2007
@@ -27,21 +27,37 @@
namespace {
// Register the target.
- RegisterTarget X("arm", " ARM");
+ RegisterTarget X("arm", " ARM");
+ RegisterTarget Y("thumb", " Thumb");
}
-/// TargetMachine ctor - Create an ILP32 architecture model
+/// ThumbTargetMachine - Create an Thumb architecture model.
///
-ARMTargetMachine::ARMTargetMachine(const Module &M, const std::string &FS)
- : Subtarget(M, FS),
+unsigned ThumbTargetMachine::getModuleMatchQuality(const Module &M) {
+ std::string TT = M.getTargetTriple();
+ if (TT.size() >= 6 && std::string(TT.begin(), TT.begin()+6) == "thumb-")
+return 20;
+
+ return M.getPointerSize() == Module::Pointer32;
+}
+
+ThumbTargetMachine::ThumbTargetMachine(const Module &M, const std::string &FS)
+ : ARMTargetMachine(M, FS, true) {
+}
+
+/// TargetMachine ctor - Create an ARM architecture model.
+///
+ARMTargetMachine::ARMTargetMachine(const Module &M, const std::string &FS,
+ bool isThumb)
+ : Subtarget(M, FS, isThumb),
DataLayout(Subtarget.isAPCS_ABI() ?
// APCS ABI
- (Subtarget.isThumb() ?
+ (isThumb ?
std::string("e-p:32:32-f64:32:32-i64:32:32-"
"i16:16:32-i8:8:32-i1:8:32-a:0:32") :
std::string("e-p:32:32-f64:32:32-i64:32:32")) :
// AAPCS ABI
- (Subtarget.isThumb() ?
+ (isThumb ?
std::string("e-p:32:32-f64:64:64-i64:64:64-"
"i16:16:32-i8:8:32-i1:8:32-a:0:32") :
std::string("e-p:32:32-f64:64:64-i64:64:64"))),
@@ -53,10 +69,7 @@
if (TT.size() >= 4 && std::string(TT.begin(), TT.begin()+4) == "arm-")
return 20;
- if (M.getPointerSize() == Module::Pointer32)
-return 1;
- else
-return 0;
+ return M.getPointerSize() == Module::Pointer32;
}
Index: llvm/lib/Target/ARM/ARMTargetMachine.h
diff -u llvm/lib/Target/ARM/ARMTargetMachine.h:1.7
llvm/lib/Target/ARM/ARMTargetMachine.h:1.8
--- llvm/lib/Target/ARM/ARMTargetMachine.h:1.7 Fri Jan 19 01:51:42 2007
+++ llvm/lib/Target/ARM/ARMTargetMachine.h Thu Feb 22 21:14:31 2007
@@ -32,7 +32,7 @@
ARMInstrInfo InstrInfo;
ARMFrameInfo FrameInfo;
public:
- ARMTargetMachine(const Module &M, const std::string &FS);
+ ARMTargetMachine(const Module &
[llvm-commits] CVS: llvm/test/CodeGen/ARM/2007-01-31-RegInfoAssert.ll 2007-02-02-JoinIntervalsCrash.ll dyn-stackalloc.ll large-stack.ll ldr_ext.ll ldr_frame.ll long-setcc.ll long.ll long_shift.ll mul.
Changes in directory llvm/test/CodeGen/ARM:
2007-01-31-RegInfoAssert.ll updated: 1.2 -> 1.3
2007-02-02-JoinIntervalsCrash.ll updated: 1.1 -> 1.2
dyn-stackalloc.ll updated: 1.2 -> 1.3
large-stack.ll updated: 1.5 -> 1.6
ldr_ext.ll updated: 1.3 -> 1.4
ldr_frame.ll updated: 1.2 -> 1.3
long-setcc.ll updated: 1.1 -> 1.2
long.ll updated: 1.12 -> 1.13
long_shift.ll updated: 1.3 -> 1.4
mul.ll updated: 1.5 -> 1.6
select.ll updated: 1.12 -> 1.13
stack-frame.ll updated: 1.1 -> 1.2
thumb-imm.ll updated: 1.2 -> 1.3
unord.ll updated: 1.2 -> 1.3
vargs2.ll updated: 1.6 -> 1.7
---
Log message:
-march=arm -enable-thumb => -march=thumb
---
Diffs of the changes: (+40 -40)
2007-01-31-RegInfoAssert.ll |2 +-
2007-02-02-JoinIntervalsCrash.ll |2 +-
dyn-stackalloc.ll|8
large-stack.ll |4 ++--
ldr_ext.ll |8
ldr_frame.ll |4 ++--
long-setcc.ll|4 ++--
long.ll | 10 +-
long_shift.ll|2 +-
mul.ll |4 ++--
select.ll| 14 +++---
stack-frame.ll |4 ++--
thumb-imm.ll |4 ++--
unord.ll |6 +++---
vargs2.ll|4 ++--
15 files changed, 40 insertions(+), 40 deletions(-)
Index: llvm/test/CodeGen/ARM/2007-01-31-RegInfoAssert.ll
diff -u llvm/test/CodeGen/ARM/2007-01-31-RegInfoAssert.ll:1.2
llvm/test/CodeGen/ARM/2007-01-31-RegInfoAssert.ll:1.3
--- llvm/test/CodeGen/ARM/2007-01-31-RegInfoAssert.ll:1.2 Thu Feb 1
20:16:22 2007
+++ llvm/test/CodeGen/ARM/2007-01-31-RegInfoAssert.ll Thu Feb 22 21:15:39 2007
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -enable-thumb
+; RUN: llvm-as < %s | llc -mtriple=thumb-apple-darwin
%struct.rtx_def = type { i8 }
@str = external global [7 x i8]
Index: llvm/test/CodeGen/ARM/2007-02-02-JoinIntervalsCrash.ll
diff -u llvm/test/CodeGen/ARM/2007-02-02-JoinIntervalsCrash.ll:1.1
llvm/test/CodeGen/ARM/2007-02-02-JoinIntervalsCrash.ll:1.2
--- llvm/test/CodeGen/ARM/2007-02-02-JoinIntervalsCrash.ll:1.1 Sat Feb 3
03:14:10 2007
+++ llvm/test/CodeGen/ARM/2007-02-02-JoinIntervalsCrash.ll Thu Feb 22
21:15:39 2007
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -enable-thumb
+; RUN: llvm-as < %s | llc -mtriple=thumb-apple-darwin
%struct.color_sample = type { i32 }
%struct.ref = type { %struct.color_sample, i16, i16 }
Index: llvm/test/CodeGen/ARM/dyn-stackalloc.ll
diff -u llvm/test/CodeGen/ARM/dyn-stackalloc.ll:1.2
llvm/test/CodeGen/ARM/dyn-stackalloc.ll:1.3
--- llvm/test/CodeGen/ARM/dyn-stackalloc.ll:1.2 Wed Feb 7 03:24:03 2007
+++ llvm/test/CodeGen/ARM/dyn-stackalloc.ll Thu Feb 22 21:15:39 2007
@@ -1,8 +1,8 @@
; RUN: llvm-as < %s | llc -march=arm &&
-; RUN: llvm-as < %s | llc -march=arm -enable-thumb &&
-; RUN: llvm-as < %s | llc -march=arm -enable-thumb | not grep "ldr sp" &&
-; RUN: llvm-as < %s | llc -march=arm -mtriple=arm-apple-darwin -enable-thumb |
not grep "sub.*r7" &&
-; RUN: llvm-as < %s | llc -march=arm -enable-thumb | grep 4294967280
+; RUN: llvm-as < %s | llc -march=thumb &&
+; RUN: llvm-as < %s | llc -march=thumb | not grep "ldr sp" &&
+; RUN: llvm-as < %s | llc -mtriple=thumb-apple-darwin | not grep "sub.*r7" &&
+; RUN: llvm-as < %s | llc -march=thumb | grep 4294967280
%struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32,
i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* }
%struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }
Index: llvm/test/CodeGen/ARM/large-stack.ll
diff -u llvm/test/CodeGen/ARM/large-stack.ll:1.5
llvm/test/CodeGen/ARM/large-stack.ll:1.6
--- llvm/test/CodeGen/ARM/large-stack.ll:1.5Thu Feb 1 16:26:42 2007
+++ llvm/test/CodeGen/ARM/large-stack.llThu Feb 22 21:15:39 2007
@@ -1,6 +1,6 @@
; RUN: llvm-as < %s | llc -march=arm &&
-; RUN: llvm-as < %s | llc -march=arm -enable-thumb &&
-; RUN: llvm-as < %s | llc -march=arm -enable-thumb | \
+; RUN: llvm-as < %s | llc -march=thumb &&
+; RUN: llvm-as < %s | llc -march=thumb | \
; RUN:grep 'ldr.*LCP' | wc -l | grep 5
define void @test1() {
Index: llvm/test/CodeGen/ARM/ldr_ext.ll
diff -u llvm/test/CodeGen/ARM/ldr_ext.ll:1.3
llvm/test/CodeGen/ARM/ldr_ext.ll:1.4
--- llvm/test/CodeGen/ARM/ldr_ext.ll:1.3Fri Jan 26 02:25:05 2007
+++ llvm/test/CodeGen/ARM/ldr_ext.llThu Feb 22 21:15:39 2007
@@ -3,10 +3,10 @@
; RUN: llvm-as < %s | llc -march=arm | grep "ldrh" | wc -l | grep 1 &&
; RUN: llvm-as < %s | llc -march=arm | grep "ldrsb" | wc -l | grep 1 &&
; RUN: llvm-as < %s | llc -march=arm | grep "ldrsh" | wc -l | grep 1 &&
-; RUN: llvm-as < %s | llc -march=arm -enable-thumb | grep "ldrb" | wc -l |
grep 1 &&
-; RUN: llvm-as < %s | llc -march=arm -enable-thumb | grep "ldrh" | wc -l |
grep 1 &&
-; RUN:
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMConstantIslandPass.cpp README.txt
Changes in directory llvm/lib/Target/ARM:
ARMConstantIslandPass.cpp updated: 1.26 -> 1.27
README.txt updated: 1.11 -> 1.12
---
Log message:
rewrite of constant islands
---
Diffs of the changes: (+275 -86)
ARMConstantIslandPass.cpp | 335 +++---
README.txt| 26 +--
2 files changed, 275 insertions(+), 86 deletions(-)
Index: llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
diff -u llvm/lib/Target/ARM/ARMConstantIslandPass.cpp:1.26
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp:1.27
--- llvm/lib/Target/ARM/ARMConstantIslandPass.cpp:1.26 Fri Feb 9 17:59:14 2007
+++ llvm/lib/Target/ARM/ARMConstantIslandPass.cpp Thu Feb 22 23:02:36 2007
@@ -35,10 +35,10 @@
STATISTIC(NumUBrFixed, "Number of uncond branches fixed");
namespace {
- /// ARMConstantIslands - Due to limited pc-relative displacements, ARM
+ /// ARMConstantIslands - Due to limited PC-relative displacements, ARM
/// requires constant pool entries to be scattered among the instructions
/// inside a function. To do this, it completely ignores the normal LLVM
- /// constant pool, instead, it places constants where-ever it feels like with
+ /// constant pool; instead, it places constants wherever it feels like with
/// special instructions.
///
/// The terminology used in this pass includes:
@@ -59,6 +59,11 @@
/// to a return, unreachable, or unconditional branch).
std::vector WaterList;
+// WaterListOffsets - the offset of the beginning of each WaterList block.
+// This is computed as needed in HandleConstantPoolUser; not necessarily
+// valid at arbitrary times.
+std::vector WaterListOffsets;
+
/// CPUser - One user of a constant pool, keeping the machine instruction
/// pointer, the constant pool being referenced, and the max displacement
/// allowed from the instruction to the CP.
@@ -86,7 +91,10 @@
};
/// CPEntries - Keep track of all of the constant pool entry machine
-/// instructions. For each constpool index, it keeps a vector of entries.
+/// instructions. For each original constpool index (i.e. those that
+/// existed upon entry to this pass), it keeps a vector of entries.
+/// Original elements are cloned as we go along; the clones are
+/// put in the vector of the original element, but have distinct CPIs.
std::vector > CPEntries;
/// ImmBranch - One per immediate branch, keeping the machine instruction
@@ -131,8 +139,16 @@
const std::vector &CPEMIs);
MachineBasicBlock *SplitBlockBeforeInstr(MachineInstr *MI);
void UpdateForInsertedWaterBlock(MachineBasicBlock *NewBB);
+bool DecrementOldEntry(unsigned CPI, MachineInstr* CPEMI, unsigned Size);
+void ComputeWaterListOffsets(MachineFunction &Fn);
+int LookForExistingCPEntry(CPUser& U, unsigned UserOffset);
bool HandleConstantPoolUser(MachineFunction &Fn, CPUser &U);
-bool CPEIsInRange(MachineInstr *MI, MachineInstr *CPEMI, unsigned Disp);
+bool CPEIsInRange(MachineInstr *MI, unsigned UserOffset,
+ MachineInstr *CPEMI, unsigned Disp,
+ bool DoDump);
+bool WaterIsInRange(unsigned UserOffset,
+std::vector::iterator IP,
+unsigned Disp);
bool BBIsInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp);
bool FixUpImmediateBr(MachineFunction &Fn, ImmBranch &Br);
bool FixUpConditionalBr(MachineFunction &Fn, ImmBranch &Br);
@@ -240,7 +256,7 @@
}
}
-/// BBHasFallthrough - Return true of the specified basic block can fallthrough
+/// BBHasFallthrough - Return true if the specified basic block can fallthrough
/// into the block immediately after it.
static bool BBHasFallthrough(MachineBasicBlock *MBB) {
// Get the next machine basic block in the function.
@@ -394,8 +410,9 @@
}
}
-// In thumb mode, if this block is a constpool island, pessmisticly assume
-// it needs to be padded by two byte so it's aligned on 4 byte boundary.
+// In thumb mode, if this block is a constpool island, pessimistically
+// assume it needs to be padded by two byte so it's aligned on 4 byte
+// boundary.
if (AFI->isThumbFunction() &&
!MBB.empty() &&
MBB.begin()->getOpcode() == ARM::CONSTPOOL_ENTRY)
@@ -503,8 +520,27 @@
OrigBB->addSuccessor(NewBB);
// Update internal data structures to account for the newly inserted MBB.
- UpdateForInsertedWaterBlock(NewBB);
+ // This is almost the same as UpdateForInsertedWaterBlock, except that
+ // the Water goes after OrigBB, not NewBB.
+ NewBB->getParent()->RenumberBlocks(NewBB);
+ // Insert a size into BBSizes to align it properly with the (newly
+ // renumbered) block numbers.
+ BBSizes.insert(BBSizes.begin()+NewBB->getNumber(), 0);
+
+ // Next, update WaterList. Specifically, we need to add OrigMBB as having
+ // available water afte
[llvm-commits] CVS: llvm/docs/DeveloperPolicy.html
Changes in directory llvm/docs: DeveloperPolicy.html updated: 1.35 -> 1.36 --- Log message: clarify. --- Diffs of the changes: (+5 -5) DeveloperPolicy.html | 10 +- 1 files changed, 5 insertions(+), 5 deletions(-) Index: llvm/docs/DeveloperPolicy.html diff -u llvm/docs/DeveloperPolicy.html:1.35 llvm/docs/DeveloperPolicy.html:1.36 --- llvm/docs/DeveloperPolicy.html:1.35 Thu Feb 22 00:33:23 2007 +++ llvm/docs/DeveloperPolicy.html Fri Feb 23 00:53:06 2007 @@ -447,10 +447,10 @@ with the GPL, and must be releasable under the terms of the GPL. This implies that any code linked into llvm-gcc and distributed to others may be subject to the viral aspects of the GPL (for example, a proprietary code generator - linked into llvm-gcc must be made available under - the GPL). This is not a problem for the main LLVM - distribution (which is already licensed under a more liberal license), but may - be a problem if you intend to base commercial development on llvm-gcc without + linked into llvm-gcc must be made available under the GPL). This is not a + problem for code already distributed under a more liberal license (like the + UIUC license), and does not affect code generated by llvm-gcc. It may be a + problem if you intend to base commercial development on llvm-gcc without redistributing your source code. We have no plans to change the license of LLVM. If you have questions @@ -499,7 +499,7 @@ Written by the mailto:[EMAIL PROTECTED]">LLVM Oversight Group http://llvm.org";>The LLVM Compiler Infrastructure - Last modified: $Date: 2007/02/22 06:33:23 $ + Last modified: $Date: 2007/02/23 06:53:06 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/docs/DeveloperPolicy.html
On Feb 22, 2007, at 2:25 AM, Duncan Sands wrote: >> + the GPL). This is not a problem for the main LLVM >>distribution (which is already licensed under a more liberal >> license), but may >>be a problem if you intend to base commercial development on >> llvm-gcc without >>redistributing your source code. > > Maybe you should make explicit that there is no problem using llvm- > gcc to compile > proprietary code - there is only a problem if parts of llvm-gcc are > included in > the proprietary program. You do say that more or less a few lines > before, but this > last sentence could great doubt in peoples minds. Maybe you could > offload the > problem onto gcc, and say that compiling a program with llvm-gcc is > like compiling > it with gcc, and give a link to http://www.gnu.org/licenses/gpl- > faq.html which > discusses these issues. Done, thanks! -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
