[llvm-commits] [llvm] r37828 - /llvm/trunk/CREDITS.TXT
Author: duraid Date: Sat Jun 30 10:47:36 2007 New Revision: 37828 URL: http://llvm.org/viewvc/llvm-project?rev=37828view=rev Log: take blame for bigblock RA (test SVN commit) Modified: llvm/trunk/CREDITS.TXT Modified: llvm/trunk/CREDITS.TXT URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CREDITS.TXT?rev=37828r1=37827r2=37828view=diff == --- llvm/trunk/CREDITS.TXT (original) +++ llvm/trunk/CREDITS.TXT Sat Jun 30 10:47:36 2007 @@ -171,7 +171,7 @@ N: Duraid Madina E: [EMAIL PROTECTED] W: http://kinoko.c.u-tokyo.ac.jp/~duraid/ -D: IA64 backend +D: IA64 backend, BigBlock register allocator N: Michael McCracken E: [EMAIL PROTECTED] ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/RegAllocBigBlock.cpp
Changes in directory llvm/lib/CodeGen:
RegAllocBigBlock.cpp updated: 1.3 - 1.4
---
Log message:
pull evan's fixes - should help the nightly tester (but there are still
some issues)
---
Diffs of the changes: (+63 -48)
RegAllocBigBlock.cpp | 111 ---
1 files changed, 63 insertions(+), 48 deletions(-)
Index: llvm/lib/CodeGen/RegAllocBigBlock.cpp
diff -u llvm/lib/CodeGen/RegAllocBigBlock.cpp:1.3
llvm/lib/CodeGen/RegAllocBigBlock.cpp:1.4
--- llvm/lib/CodeGen/RegAllocBigBlock.cpp:1.3 Mon Jun 25 19:21:58 2007
+++ llvm/lib/CodeGen/RegAllocBigBlock.cpp Wed Jun 27 02:07:13 2007
@@ -47,6 +47,7 @@
#include llvm/ADT/SmallPtrSet.h
#include llvm/ADT/Statistic.h
#include algorithm
+#include iostream
using namespace llvm;
STATISTIC(NumStores, Number of stores added);
@@ -243,13 +244,6 @@
///
void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg);
-/// liberatePhysReg - Make sure the specified physical register is
available
-/// for use. If there is currently a value in it, it is either moved out
of
-/// the way or spilled to memory.
-///
-void liberatePhysReg(MachineBasicBlock MBB, MachineBasicBlock::iterator
I,
- unsigned PhysReg);
-
/// isPhysRegAvailable - Return true if the specified physical register is
/// free and available for use. This also includes checking to see if
/// aliased registers are all free...
@@ -364,18 +358,7 @@
*AliasSet; ++AliasSet)
if (PhysRegsUsed[*AliasSet] != -1 // Spill aliased register.
PhysRegsUsed[*AliasSet] != -2) // If allocatable.
-if (PhysRegsUsed[*AliasSet] == 0) {
- // This must have been a dead def due to something like this:
- // %EAX :=
- // := op %AL
- // No more use of %EAX, %AH, etc.
- // %EAX isn't dead upon definition, but %AH is. However %AH isn't
- // an operand of definition MI so it's not marked as such.
- DOUTRegister RegInfo-getName(*AliasSet)
- [%reg *AliasSet
-] is never used, removing it frame live list\n;
- removePhysReg(*AliasSet);
-} else
+if (PhysRegsUsed[*AliasSet])
spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
}
}
@@ -429,16 +412,6 @@
}
-/// liberatePhysReg - Make sure the specified physical register is available
for
-/// use. If there is currently a value in it, it is either moved out of the
way
-/// or spilled to memory.
-///
-void RABigBlock::liberatePhysReg(MachineBasicBlock MBB,
- MachineBasicBlock::iterator I,
- unsigned PhysReg) {
- spillPhysReg(MBB, I, PhysReg);
-}
-
/// chooseReg - Pick a physical register to hold the specified
/// virtual register by choosing the one whose value will be read
/// furthest in the future.
@@ -487,8 +460,8 @@
}
}
}
-
-assert(PhysReg couldn't grab a register from the table?);
+
+assert(PhysReg couldn't assign a physical register :( );
// TODO: assert that RC-contains(PhysReg) / handle aliased registers
// since we needed to look in the table we need to spill this register.
@@ -599,6 +572,29 @@
}
}
+/// isReadModWriteImplicitKill - True if this is an implicit kill for a
+/// read/mod/write register, i.e. update partial register.
+static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
+ for (unsigned i = 0, e = MI-getNumOperands(); i != e; ++i) {
+MachineOperand MO = MI-getOperand(i);
+if (MO.isRegister() MO.getReg() == Reg MO.isImplicit()
+MO.isDef() !MO.isDead())
+ return true;
+ }
+ return false;
+}
+
+/// isReadModWriteImplicitDef - True if this is an implicit def for a
+/// read/mod/write register, i.e. update partial register.
+static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
+ for (unsigned i = 0, e = MI-getNumOperands(); i != e; ++i) {
+MachineOperand MO = MI-getOperand(i);
+if (MO.isRegister() MO.getReg() == Reg MO.isImplicit()
+!MO.isDef() MO.isKill())
+ return true;
+ }
+ return false;
+}
void RABigBlock::AllocateBasicBlock(MachineBasicBlock MBB) {
// loop over each instruction
@@ -616,7 +612,7 @@
unsigned Reg = I-first;
MF-setPhysRegUsed(Reg);
PhysRegsUsed[Reg] = 0;// It is free and reserved now
- for (const unsigned *AliasSet = RegInfo-getAliasSet(Reg);
+ for (const unsigned *AliasSet = RegInfo-getSubRegisters(Reg);
*AliasSet; ++AliasSet) {
if (PhysRegsUsed[*AliasSet] != -2) {
PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
@@ -627,12 +623,10 @@
}
// Otherwise, sequentially allocate each instruction in the MBB.
- MBBCurTime = -1;
while (MII != MBB.end()) {
MachineInstr *MI = MII++;
-MBBCurTime++;
const
[llvm-commits] CVS: llvm/lib/CodeGen/RegAllocBigBlock.cpp
Changes in directory llvm/lib/CodeGen:
RegAllocBigBlock.cpp updated: 1.4 - 1.5
---
Log message:
revert evan's fixes (and my doofusness) since they had a huge code
quality hit. will look at this soon.
---
Diffs of the changes: (+31 -63)
RegAllocBigBlock.cpp | 94 ---
1 files changed, 31 insertions(+), 63 deletions(-)
Index: llvm/lib/CodeGen/RegAllocBigBlock.cpp
diff -u llvm/lib/CodeGen/RegAllocBigBlock.cpp:1.4
llvm/lib/CodeGen/RegAllocBigBlock.cpp:1.5
--- llvm/lib/CodeGen/RegAllocBigBlock.cpp:1.4 Wed Jun 27 02:07:13 2007
+++ llvm/lib/CodeGen/RegAllocBigBlock.cpp Wed Jun 27 03:11:59 2007
@@ -47,7 +47,6 @@
#include llvm/ADT/SmallPtrSet.h
#include llvm/ADT/Statistic.h
#include algorithm
-#include iostream
using namespace llvm;
STATISTIC(NumStores, Number of stores added);
@@ -358,7 +357,18 @@
*AliasSet; ++AliasSet)
if (PhysRegsUsed[*AliasSet] != -1 // Spill aliased register.
PhysRegsUsed[*AliasSet] != -2) // If allocatable.
-if (PhysRegsUsed[*AliasSet])
+if (PhysRegsUsed[*AliasSet] == 0) {
+ // This must have been a dead def due to something like this:
+ // %EAX :=
+ // := op %AL
+ // No more use of %EAX, %AH, etc.
+ // %EAX isn't dead upon definition, but %AH is. However %AH isn't
+ // an operand of definition MI so it's not marked as such.
+ DOUTRegister RegInfo-getName(*AliasSet)
+ [%reg *AliasSet
+] is never used, removing it frame live list\n;
+ removePhysReg(*AliasSet);
+} else
spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
}
}
@@ -460,8 +470,8 @@
}
}
}
-
-assert(PhysReg couldn't assign a physical register :( );
+
+assert(PhysReg couldn't grab a register from the table?);
// TODO: assert that RC-contains(PhysReg) / handle aliased registers
// since we needed to look in the table we need to spill this register.
@@ -572,29 +582,6 @@
}
}
-/// isReadModWriteImplicitKill - True if this is an implicit kill for a
-/// read/mod/write register, i.e. update partial register.
-static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
- for (unsigned i = 0, e = MI-getNumOperands(); i != e; ++i) {
-MachineOperand MO = MI-getOperand(i);
-if (MO.isRegister() MO.getReg() == Reg MO.isImplicit()
-MO.isDef() !MO.isDead())
- return true;
- }
- return false;
-}
-
-/// isReadModWriteImplicitDef - True if this is an implicit def for a
-/// read/mod/write register, i.e. update partial register.
-static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
- for (unsigned i = 0, e = MI-getNumOperands(); i != e; ++i) {
-MachineOperand MO = MI-getOperand(i);
-if (MO.isRegister() MO.getReg() == Reg MO.isImplicit()
-!MO.isDef() MO.isKill())
- return true;
- }
- return false;
-}
void RABigBlock::AllocateBasicBlock(MachineBasicBlock MBB) {
// loop over each instruction
@@ -612,7 +599,7 @@
unsigned Reg = I-first;
MF-setPhysRegUsed(Reg);
PhysRegsUsed[Reg] = 0;// It is free and reserved now
- for (const unsigned *AliasSet = RegInfo-getSubRegisters(Reg);
+ for (const unsigned *AliasSet = RegInfo-getAliasSet(Reg);
*AliasSet; ++AliasSet) {
if (PhysRegsUsed[*AliasSet] != -2) {
PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
@@ -623,10 +610,12 @@
}
// Otherwise, sequentially allocate each instruction in the MBB.
+ MBBCurTime = -1;
while (MII != MBB.end()) {
MachineInstr *MI = MII++;
+MBBCurTime++;
const TargetInstrDescriptor TID = TII.get(MI-getOpcode());
-DEBUG(DOUT \nStarting RegAlloc of: *MI;
+DEBUG(DOUT \nTime= MBBCurTime Starting RegAlloc of: *MI;
DOUTRegs have values: ;
for (unsigned i = 0; i != RegInfo-getNumRegs(); ++i)
if (PhysRegsUsed[i] != -1 PhysRegsUsed[i] != -2)
@@ -634,28 +623,11 @@
,%reg PhysRegsUsed[i] ] ;
DOUT \n);
-/* XXX :
-// Loop over the implicit uses, making sure that they are at the head of
the
-// use order list, so they don't get reallocated.
-if (TID.ImplicitUses) {
- for (const unsigned *ImplicitUses = TID.ImplicitUses;
- *ImplicitUses; ++ImplicitUses)
-MarkPhysRegRecentlyUsed(*ImplicitUses);
-}
- XXX */
-
SmallVectorunsigned, 8 Kills;
for (unsigned i = 0, e = MI-getNumOperands(); i != e; ++i) {
MachineOperand MO = MI-getOperand(i);
- if (MO.isRegister() MO.isKill()) {
-if (!MO.isImplicit())
- Kills.push_back(MO.getReg());
-else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
- // These are extra physical register kills when a sub-register
- // is defined (def of a sub-register is a
[llvm-commits] CVS: llvm/lib/CodeGen/RegAllocBigBlock.cpp
Changes in directory llvm/lib/CodeGen:
RegAllocBigBlock.cpp updated: 1.5 - 1.6
---
Log message:
ok, this much doesn't seem to bork anything
---
Diffs of the changes: (+48 -25)
RegAllocBigBlock.cpp | 73 +--
1 files changed, 48 insertions(+), 25 deletions(-)
Index: llvm/lib/CodeGen/RegAllocBigBlock.cpp
diff -u llvm/lib/CodeGen/RegAllocBigBlock.cpp:1.5
llvm/lib/CodeGen/RegAllocBigBlock.cpp:1.6
--- llvm/lib/CodeGen/RegAllocBigBlock.cpp:1.5 Wed Jun 27 03:11:59 2007
+++ llvm/lib/CodeGen/RegAllocBigBlock.cpp Wed Jun 27 03:31:07 2007
@@ -357,18 +357,7 @@
*AliasSet; ++AliasSet)
if (PhysRegsUsed[*AliasSet] != -1 // Spill aliased register.
PhysRegsUsed[*AliasSet] != -2) // If allocatable.
-if (PhysRegsUsed[*AliasSet] == 0) {
- // This must have been a dead def due to something like this:
- // %EAX :=
- // := op %AL
- // No more use of %EAX, %AH, etc.
- // %EAX isn't dead upon definition, but %AH is. However %AH isn't
- // an operand of definition MI so it's not marked as such.
- DOUTRegister RegInfo-getName(*AliasSet)
- [%reg *AliasSet
-] is never used, removing it frame live list\n;
- removePhysReg(*AliasSet);
-} else
+if (PhysRegsUsed[*AliasSet])
spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
}
}
@@ -582,6 +571,30 @@
}
}
+/// isReadModWriteImplicitKill - True if this is an implicit kill for a
+/// read/mod/write register, i.e. update partial register.
+static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
+ for (unsigned i = 0, e = MI-getNumOperands(); i != e; ++i) {
+MachineOperand MO = MI-getOperand(i);
+if (MO.isRegister() MO.getReg() == Reg MO.isImplicit()
+MO.isDef() !MO.isDead())
+ return true;
+ }
+ return false;
+}
+
+/// isReadModWriteImplicitDef - True if this is an implicit def for a
+/// read/mod/write register, i.e. update partial register.
+static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
+ for (unsigned i = 0, e = MI-getNumOperands(); i != e; ++i) {
+MachineOperand MO = MI-getOperand(i);
+if (MO.isRegister() MO.getReg() == Reg MO.isImplicit()
+!MO.isDef() MO.isKill())
+ return true;
+ }
+ return false;
+}
+
void RABigBlock::AllocateBasicBlock(MachineBasicBlock MBB) {
// loop over each instruction
@@ -599,7 +612,7 @@
unsigned Reg = I-first;
MF-setPhysRegUsed(Reg);
PhysRegsUsed[Reg] = 0;// It is free and reserved now
- for (const unsigned *AliasSet = RegInfo-getAliasSet(Reg);
+ for (const unsigned *AliasSet = RegInfo-getSubRegisters(Reg);
*AliasSet; ++AliasSet) {
if (PhysRegsUsed[*AliasSet] != -2) {
PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
@@ -626,8 +639,15 @@
SmallVectorunsigned, 8 Kills;
for (unsigned i = 0, e = MI-getNumOperands(); i != e; ++i) {
MachineOperand MO = MI-getOperand(i);
- if (MO.isRegister() MO.isKill())
-Kills.push_back(MO.getReg());
+ if (MO.isRegister() MO.isKill()) {
+if (!MO.isImplicit())
+ Kills.push_back(MO.getReg());
+else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
+ // These are extra physical register kills when a sub-register
+ // is defined (def of a sub-register is a read/mod/write of the
+ // larger registers). Ignore.
+ Kills.push_back(MO.getReg());
+ }
}
// Get the used operands into registers. This has the potential to spill
@@ -660,13 +680,16 @@
} else if (PhysRegsUsed[PhysReg] == -2) {
// Unallocatable register dead, ignore.
continue;
+ } else {
+assert(!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1
+ Silently clearing a virtual register?);
}
if (PhysReg) {
DOUTLast use of RegInfo-getName(PhysReg)
[%reg VirtReg ], removing it from live set\n;
removePhysReg(PhysReg);
-for (const unsigned *AliasSet = RegInfo-getAliasSet(PhysReg);
+for (const unsigned *AliasSet = RegInfo-getSubRegisters(PhysReg);
*AliasSet; ++AliasSet) {
if (PhysRegsUsed[*AliasSet] != -2) {
DOUT Last use of
@@ -686,11 +709,15 @@
MRegisterInfo::isPhysicalRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
-
+// These are extra physical register defs when a sub-register
+// is defined (def of a sub-register is a read/mod/write of the
+// larger registers). Ignore.
+if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
+
MF-setPhysRegUsed(Reg);
spillPhysReg(MBB, MI, Reg, true); //
[llvm-commits] CVS: llvm/lib/CodeGen/RegAllocBigBlock.cpp
Changes in directory llvm/lib/CodeGen:
RegAllocBigBlock.cpp updated: 1.6 - 1.7
---
Log message:
ok, this is something of a dirty hack, but it seems to work. (fixes e.g.
the SPASS miscompilation)
---
Diffs of the changes: (+16 -2)
RegAllocBigBlock.cpp | 18 --
1 files changed, 16 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/RegAllocBigBlock.cpp
diff -u llvm/lib/CodeGen/RegAllocBigBlock.cpp:1.6
llvm/lib/CodeGen/RegAllocBigBlock.cpp:1.7
--- llvm/lib/CodeGen/RegAllocBigBlock.cpp:1.6 Wed Jun 27 03:31:07 2007
+++ llvm/lib/CodeGen/RegAllocBigBlock.cpp Wed Jun 27 04:01:14 2007
@@ -459,9 +459,23 @@
}
}
}
+
+if(PhysReg == 0) { // ok, now we're desperate. We couldn't choose
+ // a register to spill by looking through the
+ // read timetable, so now we just spill the
+ // first allocatable register we find.
+
+ // for all physical regs in the RC,
+ for(TargetRegisterClass::iterator pReg = RC-begin();
+pReg != RC-end(); ++pReg) {
+// if we find a register we can spill
+if(PhysRegsUsed[*pReg]=-1)
+ PhysReg = *pReg; // choose it to be spilled
+ }
+}
-assert(PhysReg couldn't grab a register from the table?);
-// TODO: assert that RC-contains(PhysReg) / handle aliased registers
+assert(PhysReg couldn't choose a register to spill :( );
+// TODO: assert that RC-contains(PhysReg) / handle aliased registers?
// since we needed to look in the table we need to spill this register.
spillPhysReg(MBB, I, PhysReg);
___
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[llvm-commits] CVS: llvm-test/Makefile.programs
Changes in directory llvm-test: Makefile.programs updated: 1.271 - 1.272 --- Log message: spass+oggenc work, therefore everything works(tm) ;) --- Diffs of the changes: (+1 -1) Makefile.programs |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.271 llvm-test/Makefile.programs:1.272 --- llvm-test/Makefile.programs:1.271 Tue Jun 26 11:12:31 2007 +++ llvm-test/Makefile.programs Wed Jun 27 09:10:36 2007 @@ -235,7 +235,7 @@ LLCBETAOPTION := -sched=simple endif ifeq ($(ARCH),x86) -LLCBETAOPTION := -regalloc=local -fast +LLCBETAOPTION := -regalloc=bigblock -fast endif ifeq ($(ARCH),Sparc) LLCBETAOPTION := -enable-sparc-v9-insts ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/RegAllocBigBlock.cpp
Changes in directory llvm/lib/CodeGen:
RegAllocBigBlock.cpp updated: 1.1 - 1.2
---
Log message:
A bunch of fixes to the BigBlock allocator improve compile-time by ~20%
and code quality by ~2% on my tests.
A big thank you to Roman Levenstein for this patch! See
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070618/050717.html
for more details.
---
Diffs of the changes: (+65 -72)
RegAllocBigBlock.cpp | 137 ---
1 files changed, 65 insertions(+), 72 deletions(-)
Index: llvm/lib/CodeGen/RegAllocBigBlock.cpp
diff -u llvm/lib/CodeGen/RegAllocBigBlock.cpp:1.1
llvm/lib/CodeGen/RegAllocBigBlock.cpp:1.2
--- llvm/lib/CodeGen/RegAllocBigBlock.cpp:1.1 Fri Jun 22 03:27:12 2007
+++ llvm/lib/CodeGen/RegAllocBigBlock.cpp Mon Jun 25 18:46:54 2007
@@ -40,6 +40,7 @@
#include llvm/ADT/IndexedMap.h
#include llvm/ADT/DenseMap.h
#include llvm/ADT/SmallVector.h
+#include llvm/ADT/SmallPtrSet.h
#include llvm/ADT/Statistic.h
#include algorithm
using namespace llvm;
@@ -69,15 +70,17 @@
const MRegisterInfo *RegInfo;
LiveVariables *LV;
-// InsnTimes - maps machine instructions to their execute times
-std::mapMachineInstr *, unsigned InsnTimes;
-
// VRegReadTable - maps VRegs in a BB to the set of times they are read
-DenseMapunsigned, SmallVectorunsigned, 2*, VRegKeyInfo VRegReadTable;
+// This is a sorted list
+typedef SmallVectorunsigned, 2 VRegTimes;
+
+DenseMapunsigned, VRegTimes*, VRegKeyInfo VRegReadTable;
+DenseMapunsigned, unsigned , VRegKeyInfo VRegReadIdx;
// StackSlotForVirtReg - Maps virtual regs to the frame index where these
// values are spilled.
-std::mapunsigned, int StackSlotForVirtReg;
+//DenseMapunsigned, int, VRegKeyInf StackSlotForVirtReg;
+IndexedMapunsigned, VirtReg2IndexFunctor StackSlotForVirtReg;
// Virt2PhysRegMap - This map contains entries for each virtual register
// that is currently available in a physical register.
@@ -87,6 +90,11 @@
return Virt2PhysRegMap[VirtReg];
}
+unsigned getVirt2StackSlot(unsigned VirtReg) {
+ return StackSlotForVirtReg[VirtReg];
+}
+
+
// PhysRegsUsed - This array is effectively a map, containing entries for
// each physical register that currently has a value (ie, it is in
// Virt2PhysRegMap). The value mapped to is the virtual register
@@ -98,22 +106,19 @@
//
std::vectorint PhysRegsUsed;
-// PhysRegsUseOrder - This contains a list of the physical registers that
-// currently have a virtual register value in them. This list provides an
-// ordering of registers, imposing a reallocation order. This list is only
-// used if all registers are allocated and we have to spill one, in which
-// case we spill the least recently used register. Entries at the front of
-// the list are the least recently used registers, entries at the back are
-// the most recently used.
-//
-std::vectorunsigned PhysRegsUseOrder;
// VirtRegModified - This bitset contains information about which virtual
// registers need to be spilled back to memory when their registers are
// scavenged. If a virtual register has simply been rematerialized, there
// is no reason to spill it to memory when we need the register back.
//
-std::vectorbool VirtRegModified;
+std::vectorint VirtRegModified;
+
+// MBBLastInsnTime - the number of the the last instruction in MBB
+int MBBLastInsnTime;
+
+// MBBCurTime - the number of the the instruction being currently processed
+int MBBCurTime;
void markVirtRegModified(unsigned Reg, bool Val = true) {
assert(MRegisterInfo::isVirtualRegister(Reg) Illegal VirtReg!);
@@ -129,21 +134,6 @@
return VirtRegModified[Reg - MRegisterInfo::FirstVirtualRegister];
}
-void MarkPhysRegRecentlyUsed(unsigned Reg) {
- if (PhysRegsUseOrder.empty() ||
- PhysRegsUseOrder.back() == Reg) return; // Already most recently
used
-
- for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i)
-if (areRegsEqual(Reg, PhysRegsUseOrder[i-1])) {
- unsigned RegMatch = PhysRegsUseOrder[i-1]; // remove from
middle
- PhysRegsUseOrder.erase(PhysRegsUseOrder.begin()+i-1);
- // Add it to the end of the list
- PhysRegsUseOrder.push_back(RegMatch);
- if (RegMatch == Reg)
-return;// Found an exact match, exit early
-}
-}
-
public:
virtual const char *getPassName() const {
return BigBlock Register Allocator;
@@ -256,17 +246,17 @@
/// to be held on the stack.
int RABigBlock::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass
*RC) {
// Find the location Reg would belong...
- std::mapunsigned, int::iterator I
=StackSlotForVirtReg.lower_bound(VirtReg);
+ int FrameIdx = getVirt2StackSlot(VirtReg);
- if (I != StackSlotForVirtReg.end()
[llvm-commits] CVS: llvm/lib/CodeGen/RegAllocBigBlock.cpp
Changes in directory llvm/lib/CodeGen:
RegAllocBigBlock.cpp updated: 1.2 - 1.3
---
Log message:
tidy this file up a bit
---
Diffs of the changes: (+82 -54)
RegAllocBigBlock.cpp | 136 ++-
1 files changed, 82 insertions(+), 54 deletions(-)
Index: llvm/lib/CodeGen/RegAllocBigBlock.cpp
diff -u llvm/lib/CodeGen/RegAllocBigBlock.cpp:1.2
llvm/lib/CodeGen/RegAllocBigBlock.cpp:1.3
--- llvm/lib/CodeGen/RegAllocBigBlock.cpp:1.2 Mon Jun 25 18:46:54 2007
+++ llvm/lib/CodeGen/RegAllocBigBlock.cpp Mon Jun 25 19:21:58 2007
@@ -2,11 +2,15 @@
//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file was developed by Duraid Madina and is distributed under the
+// University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===--===//
//
+// This file implements the RABigBlock class
+//
+//===--===//
+
// This register allocator is derived from RegAllocLocal.cpp. Like it, this
// allocator works on one basic block at a time, oblivious to others.
// However, the algorithm used here is suited for long blocks of
@@ -54,79 +58,112 @@
bigBlockRegAlloc(bigblock, Big-block register allocator,
createBigBlockRegisterAllocator);
+/// VRegKeyInfo - Defines magic values required to use VirtRegs as DenseMap
+/// keys.
struct VRegKeyInfo {
static inline unsigned getEmptyKey() { return -1U; }
static inline unsigned getTombstoneKey() { return -2U; }
static unsigned getHashValue(const unsigned Key) { return Key; }
};
+
+/// This register allocator is derived from RegAllocLocal.cpp. Like it, this
+/// allocator works on one basic block at a time, oblivious to others.
+/// However, the algorithm used here is suited for long blocks of
+/// instructions - registers are spilled by greedily choosing those holding
+/// values that will not be needed for the longest amount of time. This works
+/// particularly well for blocks with 10 or more times as many instructions
+/// as machine registers, but can be used for general code.
+///
+/// TODO: - automagically invoke linearscan for (groups of) small BBs?
+/// - break ties when picking regs? (probably not worth it in a
+/// JIT context)
+///
class VISIBILITY_HIDDEN RABigBlock : public MachineFunctionPass {
public:
static char ID;
RABigBlock() : MachineFunctionPass((intptr_t)ID) {}
private:
+/// TM - For getting at TargetMachine info
+///
const TargetMachine *TM;
+
+/// MF - Our generic MachineFunction pointer
+///
MachineFunction *MF;
+
+/// RegInfo - For dealing with machine register info (aliases, folds
+/// etc)
const MRegisterInfo *RegInfo;
+
+/// LV - Our generic LiveVariables pointer
+///
LiveVariables *LV;
-// VRegReadTable - maps VRegs in a BB to the set of times they are read
-// This is a sorted list
typedef SmallVectorunsigned, 2 VRegTimes;
+/// VRegReadTable - maps VRegs in a BB to the set of times they are read
+///
DenseMapunsigned, VRegTimes*, VRegKeyInfo VRegReadTable;
+
+/// VRegReadIdx - keeps track of the current time in terms of
+/// positions in VRegReadTable
DenseMapunsigned, unsigned , VRegKeyInfo VRegReadIdx;
-// StackSlotForVirtReg - Maps virtual regs to the frame index where these
-// values are spilled.
-//DenseMapunsigned, int, VRegKeyInf StackSlotForVirtReg;
+/// StackSlotForVirtReg - Maps virtual regs to the frame index where these
+/// values are spilled.
IndexedMapunsigned, VirtReg2IndexFunctor StackSlotForVirtReg;
-// Virt2PhysRegMap - This map contains entries for each virtual register
-// that is currently available in a physical register.
+/// Virt2PhysRegMap - This map contains entries for each virtual register
+/// that is currently available in a physical register.
IndexedMapunsigned, VirtReg2IndexFunctor Virt2PhysRegMap;
-unsigned getVirt2PhysRegMapSlot(unsigned VirtReg) {
- return Virt2PhysRegMap[VirtReg];
-}
-
-unsigned getVirt2StackSlot(unsigned VirtReg) {
- return StackSlotForVirtReg[VirtReg];
-}
-
-
-// PhysRegsUsed - This array is effectively a map, containing entries for
-// each physical register that currently has a value (ie, it is in
-// Virt2PhysRegMap). The value mapped to is the virtual register
-// corresponding to the physical register (the inverse of the
-// Virt2PhysRegMap), or 0. The value is set to 0 if this register is
pinned
-// because it is used by a future instruction, and to -2 if it is not
-// allocatable. If the entry for a physical
[llvm-commits] CVS: llvm-test/Makefile.programs
Changes in directory llvm-test: Makefile.programs updated: 1.269 - 1.270 --- Log message: give the bigblock allocator a workout --- Diffs of the changes: (+1 -1) Makefile.programs |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.269 llvm-test/Makefile.programs:1.270 --- llvm-test/Makefile.programs:1.269 Wed Jun 20 18:48:01 2007 +++ llvm-test/Makefile.programs Mon Jun 25 22:22:13 2007 @@ -235,7 +235,7 @@ LLCBETAOPTION := -sched=simple endif ifeq ($(ARCH),x86) -LLCBETAOPTION := -regalloc=local -fast +LLCBETAOPTION := -regalloc=bigblock -fast endif ifeq ($(ARCH),Sparc) LLCBETAOPTION := -enable-sparc-v9-insts ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/CodeGen/Passes.h LinkAllCodegenComponents.h
Changes in directory llvm/include/llvm/CodeGen: Passes.h updated: 1.27 - 1.28 LinkAllCodegenComponents.h updated: 1.5 - 1.6 --- Log message: check in the BigBlock local register allocator --- Diffs of the changes: (+10 -0) LinkAllCodegenComponents.h |1 + Passes.h |9 + 2 files changed, 10 insertions(+) Index: llvm/include/llvm/CodeGen/Passes.h diff -u llvm/include/llvm/CodeGen/Passes.h:1.27 llvm/include/llvm/CodeGen/Passes.h:1.28 --- llvm/include/llvm/CodeGen/Passes.h:1.27 Fri Jun 8 12:18:56 2007 +++ llvm/include/llvm/CodeGen/Passes.h Fri Jun 22 03:27:12 2007 @@ -70,6 +70,15 @@ /// FunctionPass *createLocalRegisterAllocator(); + /// BigBlockRegisterAllocation Pass - The BigBlock register allocator + /// munches single basic blocks at a time, like the local register + /// allocator. While the BigBlock allocator is a little slower, and uses + /// somewhat more memory than the local register allocator, it tends to + /// yield the best allocations (of any of the allocators) for blocks that + /// have hundreds or thousands of instructions in sequence. + /// + FunctionPass *createBigBlockRegisterAllocator(); + /// LinearScanRegisterAllocation Pass - This pass implements the linear scan /// register allocation algorithm, a global register allocator. /// Index: llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h diff -u llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h:1.5 llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h:1.6 --- llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h:1.5Sun Dec 17 05:13:13 2006 +++ llvm/include/llvm/CodeGen/LinkAllCodegenComponents.hFri Jun 22 03:27:12 2007 @@ -30,6 +30,7 @@ (void) llvm::createSimpleRegisterAllocator(); (void) llvm::createLocalRegisterAllocator(); + (void) llvm::createBigBlockRegisterAllocator(); (void) llvm::createLinearScanRegisterAllocator(); (void) llvm::createBFS_DAGScheduler(NULL, NULL, NULL); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/RegAllocBigBlock.cpp
Changes in directory llvm/lib/CodeGen:
RegAllocBigBlock.cpp added (r1.1)
---
Log message:
check in the BigBlock local register allocator
---
Diffs of the changes: (+852 -0)
RegAllocBigBlock.cpp | 852 +++
1 files changed, 852 insertions(+)
Index: llvm/lib/CodeGen/RegAllocBigBlock.cpp
diff -c /dev/null llvm/lib/CodeGen/RegAllocBigBlock.cpp:1.1
*** /dev/null Fri Jun 22 03:27:22 2007
--- llvm/lib/CodeGen/RegAllocBigBlock.cpp Fri Jun 22 03:27:12 2007
***
*** 0
--- 1,852
+ //===- RegAllocBigBlock.cpp - A register allocator for large basic blocks
-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for
details.
+ //
+
//===--===//
+ //
+ // This register allocator is derived from RegAllocLocal.cpp. Like it, this
+ // allocator works on one basic block at a time, oblivious to others.
+ // However, the algorithm used here is suited for long blocks of
+ // instructions - registers are spilled by greedily choosing those holding
+ // values that will not be needed for the longest amount of time. This works
+ // particularly well for blocks with 10 or more times as many instructions
+ // as machine registers, but can be used for general code.
+ //
+
//===--===//
+ //
+ // TODO: - automagically invoke linearscan for (groups of) small BBs?
+ // - break ties when picking regs? (probably not worth it in a
+ // JIT context)
+ //
+
//===--===//
+
+ #define DEBUG_TYPE regalloc
+ #include llvm/BasicBlock.h
+ #include llvm/CodeGen/Passes.h
+ #include llvm/CodeGen/MachineFunctionPass.h
+ #include llvm/CodeGen/MachineInstr.h
+ #include llvm/CodeGen/SSARegMap.h
+ #include llvm/CodeGen/MachineFrameInfo.h
+ #include llvm/CodeGen/LiveVariables.h
+ #include llvm/CodeGen/RegAllocRegistry.h
+ #include llvm/Target/TargetInstrInfo.h
+ #include llvm/Target/TargetMachine.h
+ #include llvm/Support/CommandLine.h
+ #include llvm/Support/Debug.h
+ #include llvm/Support/Compiler.h
+ #include llvm/ADT/IndexedMap.h
+ #include llvm/ADT/DenseMap.h
+ #include llvm/ADT/SmallVector.h
+ #include llvm/ADT/Statistic.h
+ #include algorithm
+ using namespace llvm;
+
+ STATISTIC(NumStores, Number of stores added);
+ STATISTIC(NumLoads , Number of loads added);
+ STATISTIC(NumFolded, Number of loads/stores folded into instructions);
+
+ namespace {
+ static RegisterRegAlloc
+ bigBlockRegAlloc(bigblock, Big-block register allocator,
+ createBigBlockRegisterAllocator);
+
+ struct VRegKeyInfo {
+ static inline unsigned getEmptyKey() { return -1U; }
+ static inline unsigned getTombstoneKey() { return -2U; }
+ static unsigned getHashValue(const unsigned Key) { return Key; }
+ };
+
+ class VISIBILITY_HIDDEN RABigBlock : public MachineFunctionPass {
+ public:
+ static char ID;
+ RABigBlock() : MachineFunctionPass((intptr_t)ID) {}
+ private:
+ const TargetMachine *TM;
+ MachineFunction *MF;
+ const MRegisterInfo *RegInfo;
+ LiveVariables *LV;
+
+ // InsnTimes - maps machine instructions to their execute times
+ std::mapMachineInstr *, unsigned InsnTimes;
+
+ // VRegReadTable - maps VRegs in a BB to the set of times they are read
+ DenseMapunsigned, SmallVectorunsigned, 2*, VRegKeyInfo VRegReadTable;
+
+ // StackSlotForVirtReg - Maps virtual regs to the frame index where these
+ // values are spilled.
+ std::mapunsigned, int StackSlotForVirtReg;
+
+ // Virt2PhysRegMap - This map contains entries for each virtual register
+ // that is currently available in a physical register.
+ IndexedMapunsigned, VirtReg2IndexFunctor Virt2PhysRegMap;
+
+ unsigned getVirt2PhysRegMapSlot(unsigned VirtReg) {
+ return Virt2PhysRegMap[VirtReg];
+ }
+
+ // PhysRegsUsed - This array is effectively a map, containing entries for
+ // each physical register that currently has a value (ie, it is in
+ // Virt2PhysRegMap). The value mapped to is the virtual register
+ // corresponding to the physical register (the inverse of the
+ // Virt2PhysRegMap), or 0. The value is set to 0 if this register is
pinned
+ // because it is used by a future instruction, and to -2 if it is not
+ // allocatable. If the entry for a physical register is -1, then the
+ // physical register is not in the map.
+ //
+ std::vectorint PhysRegsUsed;
+
+ // PhysRegsUseOrder - This contains a list of the physical registers that
+ // currently have a virtual register value in them. This list provides an
+ // ordering of registers, imposing a
[llvm-commits] New BigBlock local register allocator
Hi all,
Attached is a new local register allocator tuned for big basic
blocks. It is fast and doesn't use much memory, but it is *slightly* slower
and does use more memory than the existing local allocator. Having said
that, it quickly gets close-to-optimal allocations on very large basic
blocks, and it doesn't give *terrible* results on complex functions, so it
might make sense to use this allocator by default in a JIT context. I
haven't yet been able to narrow down a case where the existing local
allocator produces better code than this one.
Anyway, to play with it, just drop it into lib/Codegen, but you'll
also need to declare it in:
include/CodeGen/Passes.h
include/CodeGen/LinkAllCodegenComponents.h
and for testing, you might want to edit lib/Codegen/Passes.cpp to make it
the default allocator. I've built llvm-gcc in this way, and the results are
pretty reasonable. The allocator hasn't choked on anything so far.
As you'll quickly notice, the file is basically a copy of
RegAllocLocal.cpp. The only bits changed are the bits implementing the new
algorithm, which is very simple. It's just:
At every instruction, if you have to spill a register, greedily spill the
one whose value isn't going to be read again for the longest amount of
time.
To do this, two passes over each basic block are performed. The
first pass builds a table which lists the times that each virtual register
is read. The second pass does the allocation proper, spilling registers
according to the won't be needed longest rule.
The only thing I am not happy about is the InsnTimes map, which
just maps all (unallocated) instructions in the basic-block to the integers
0,1,2... Surely there is some way I can do without this map? (I guess I just
need to thread a currentTime value through to chooseReg() and
reloadVirtReg()?) I tried this but messed it up, I probably just need more
coffee. ;) Seriously though, if anyone can find any problems or suggest any
improvements, I'd be really happy to hear them.
Well, the only other question I have is: can I check this in as a
seperate allocator, or should we upgrade the existing local allocator to
this one? This allocator will never be as fast, or use as little memory as
the simple local allocator, and for those reasons alone I'm thinking we
may as well keep the existing local allocator. However, compared to
linearscan, or almost any other imaginable heavy duty allocator, any
difference in the efficiency is probably going to be imperceptible. (On my
own JIT workload, BigBlock is 30% slower than Local, but even so, it is
still 1% of the total codegen time.)
OK, enough rambling: please take a look - flames welcome!!
Duraid
//===- RegAllocBigBlock.cpp - A register allocator for large basic blocks -===//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===--===//
//
// This register allocator is derived from RegAllocLocal.cpp. Like it, this
// allocator works on one basic block at a time, oblivious to others.
// However, the algorithm used here is suited for long blocks of
// instructions - registers are spilled by greedily choosing those holding
// values that will not be needed for the longest amount of time. This works
// particularly well for blocks with 10 or more times as many instructions
// as machine registers, but can be used for general code.
//
//===--===//
//
// TODO: - automagically invoke linearscan for (groups of) small BBs?
// - break ties when picking regs? (probably not worth it in a
// JIT context)
//
//===--===//
#define DEBUG_TYPE regalloc
#include llvm/BasicBlock.h
#include llvm/CodeGen/Passes.h
#include llvm/CodeGen/MachineFunctionPass.h
#include llvm/CodeGen/MachineInstr.h
#include llvm/CodeGen/SSARegMap.h
#include llvm/CodeGen/MachineFrameInfo.h
#include llvm/CodeGen/LiveVariables.h
#include llvm/CodeGen/RegAllocRegistry.h
#include llvm/Target/TargetInstrInfo.h
#include llvm/Target/TargetMachine.h
#include llvm/Support/CommandLine.h
#include llvm/Support/Debug.h
#include llvm/Support/Compiler.h
#include llvm/ADT/IndexedMap.h
#include llvm/ADT/DenseMap.h
#include llvm/ADT/SmallVector.h
#include llvm/ADT/Statistic.h
#include algorithm
using namespace llvm;
STATISTIC(NumStores, Number of stores added);
STATISTIC(NumLoads , Number of loads added);
STATISTIC(NumFolded, Number of loads/stores folded into instructions);
namespace {
static RegisterRegAlloc
bigBlockRegAlloc(bigblock, Big-block register allocator,
createBigBlockRegisterAllocator);
struct VRegKeyInfo {
static inline unsigned
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64: IA64ISelDAGToDAG.cpp updated: 1.60 - 1.61 IA64InstrInfo.td updated: 1.48 - 1.49 --- Log message: fix storing bools to mem and unordered FP ops --- Diffs of the changes: (+5 -5) IA64ISelDAGToDAG.cpp |2 +- IA64InstrInfo.td |8 2 files changed, 5 insertions(+), 5 deletions(-) Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.60 llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.61 --- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.60 Thu Nov 2 14:25:49 2006 +++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sat Nov 25 22:34:26 2006 @@ -515,7 +515,7 @@ SDOperand Tmp = ST-getValue(); AddToISelQueue(Tmp); Tmp = SDOperand(CurDAG-getTargetNode(IA64::TPCADDS, MVT::i64, Initial, - CurDAG-getConstant(1, MVT::i64), + CurDAG-getTargetConstant(1, MVT::i64), Tmp), 0); return CurDAG-SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain); } Index: llvm/lib/Target/IA64/IA64InstrInfo.td diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.48 llvm/lib/Target/IA64/IA64InstrInfo.td:1.49 --- llvm/lib/Target/IA64/IA64InstrInfo.td:1.48 Mon Jul 31 13:43:10 2006 +++ llvm/lib/Target/IA64/IA64InstrInfo.td Sat Nov 25 22:34:26 2006 @@ -307,16 +307,16 @@ fcmp.neq $dst, p0 = $src1, $src2, [(set PR:$dst, (setne FP:$src1, FP:$src2))], isF; def FCMPLTU: AForm_DAG0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2), - fcmp.ltu $dst, p0 = $src1, $src2, + fcmp.lt $dst, p0 = $src1, $src2, [(set PR:$dst, (setult FP:$src1, FP:$src2))], isF; def FCMPGTU: AForm_DAG0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2), - fcmp.gtu $dst, p0 = $src1, $src2, + fcmp.gt $dst, p0 = $src1, $src2, [(set PR:$dst, (setugt FP:$src1, FP:$src2))], isF; def FCMPLEU: AForm_DAG0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2), - fcmp.leu $dst, p0 = $src1, $src2, + fcmp.le $dst, p0 = $src1, $src2, [(set PR:$dst, (setule FP:$src1, FP:$src2))], isF; def FCMPGEU: AForm_DAG0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2), - fcmp.geu $dst, p0 = $src1, $src2, + fcmp.ge $dst, p0 = $src1, $src2, [(set PR:$dst, (setuge FP:$src1, FP:$src2))], isF; def PCMPEQUNCR0R0 : AForm0x03, 0x0b, (ops PR:$dst, PR:$qp), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Utils/LowerInvoke.cpp
Changes in directory llvm/lib/Transforms/Utils:
LowerInvoke.cpp updated: 1.39 - 1.40
---
Log message:
add setJumpBufSize() and setJumpBufAlignment() to target-lowering.
Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example
---
Diffs of the changes: (+10 -10)
LowerInvoke.cpp | 20 ++--
1 files changed, 10 insertions(+), 10 deletions(-)
Index: llvm/lib/Transforms/Utils/LowerInvoke.cpp
diff -u llvm/lib/Transforms/Utils/LowerInvoke.cpp:1.39
llvm/lib/Transforms/Utils/LowerInvoke.cpp:1.40
--- llvm/lib/Transforms/Utils/LowerInvoke.cpp:1.39 Sun Aug 27 17:42:52 2006
+++ llvm/lib/Transforms/Utils/LowerInvoke.cpp Mon Sep 4 01:21:35 2006
@@ -45,6 +45,7 @@
#include llvm/ADT/Statistic.h
#include llvm/Support/CommandLine.h
#include llvm/Support/Compiler.h
+#include llvm/Target/TargetLowering.h
#include csetjmp
using namespace llvm;
@@ -67,9 +68,12 @@
const Type *JBLinkTy;
GlobalVariable *JBListHead;
Function *SetJmpFn, *LongJmpFn;
+
+// We peek in TLI to grab the target's jmp_buf size and alignment
+const TargetLowering *TLI;
+
public:
-LowerInvoke(unsigned Size = 200, unsigned Align = 0) : JumpBufSize(Size),
- JumpBufAlign(Align) {}
+LowerInvoke(const TargetLowering *tli = NULL) : TLI(tli) { }
bool doInitialization(Module M);
bool runOnFunction(Function F);
@@ -89,9 +93,6 @@
void rewriteExpensiveInvoke(InvokeInst *II, unsigned InvokeNo,
AllocaInst *InvokeNum, SwitchInst
*CatchSwitch);
bool insertExpensiveEHSupport(Function F);
-
-unsigned JumpBufSize;
-unsigned JumpBufAlign;
};
RegisterPassLowerInvoke
@@ -101,9 +102,8 @@
const PassInfo *llvm::LowerInvokePassID = X.getPassInfo();
// Public Interface To the LowerInvoke pass.
-FunctionPass *llvm::createLowerInvokePass(unsigned JumpBufSize,
- unsigned JumpBufAlign) {
- return new LowerInvoke(JumpBufSize, JumpBufAlign);
+FunctionPass *llvm::createLowerInvokePass(const TargetLowering *TLI) {
+ return new LowerInvoke(TLI);
}
// doInitialization - Make sure that there is a prototype for abort in the
@@ -113,7 +113,7 @@
AbortMessage = 0;
if (ExpensiveEHSupport) {
// Insert a type for the linked list of jump buffers.
-const Type *JmpBufTy = ArrayType::get(VoidPtrTy, JumpBufSize);
+const Type *JmpBufTy = ArrayType::get(VoidPtrTy, TLI-getJumpBufSize());
{ // The type is recursive, so use a type holder.
std::vectorconst Type* Elements;
@@ -453,7 +453,7 @@
// that needs to be restored on all exits from the function. This is an
// alloca because the value needs to be live across invokes.
AllocaInst *JmpBuf =
- new AllocaInst(JBLinkTy, 0, JumpBufAlign, jblink, F.begin()-begin());
+ new AllocaInst(JBLinkTy, 0, TLI-getJumpBufAlignment(), jblink,
F.begin()-begin());
std::vectorValue* Idx;
Idx.push_back(Constant::getNullValue(Type::IntTy));
___
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llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Transforms/Scalar.h
Changes in directory llvm/include/llvm/Transforms: Scalar.h updated: 1.67 - 1.68 --- Log message: add setJumpBufSize() and setJumpBufAlignment() to target-lowering. Call these from your backend to enjoy setjmp/longjmp goodness, see lib/Target/IA64/IA64ISelLowering.cpp for an example --- Diffs of the changes: (+1 -2) Scalar.h |3 +-- 1 files changed, 1 insertion(+), 2 deletions(-) Index: llvm/include/llvm/Transforms/Scalar.h diff -u llvm/include/llvm/Transforms/Scalar.h:1.67 llvm/include/llvm/Transforms/Scalar.h:1.68 --- llvm/include/llvm/Transforms/Scalar.h:1.67 Mon Aug 28 17:44:55 2006 +++ llvm/include/llvm/Transforms/Scalar.h Mon Sep 4 01:21:35 2006 @@ -286,8 +286,7 @@ // my LLVM-to-LLVM pass doesn't support the invoke instruction yet lowering // pass. // -FunctionPass *createLowerInvokePass(unsigned JumBufSize = 200, -unsigned JumpBufAlign = 0); +FunctionPass *createLowerInvokePass(const TargetLowering *TLI = NULL); extern const PassInfo *LowerInvokePassID; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/LLVMTargetMachine.cpp
Changes in directory llvm/lib/CodeGen: LLVMTargetMachine.cpp updated: 1.1 - 1.2 --- Log message: add setJumpBufSize() and setJumpBufAlignment() to target-lowering. Call these from your backend to enjoy setjmp/longjmp goodness, see lib/Target/IA64/IA64ISelLowering.cpp for an example --- Diffs of the changes: (+2 -2) LLVMTargetMachine.cpp |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/LLVMTargetMachine.cpp diff -u llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.1 llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.2 --- llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.1 Sun Sep 3 23:16:09 2006 +++ llvm/lib/CodeGen/LLVMTargetMachine.cpp Mon Sep 4 01:21:35 2006 @@ -33,7 +33,7 @@ PM.add(createLowerGCPass()); // FIXME: Implement the invoke/unwind instructions! - PM.add(createLowerInvokePass()); + PM.add(createLowerInvokePass(getTargetLowering())); // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); @@ -107,7 +107,7 @@ PM.add(createLowerGCPass()); // FIXME: Implement the invoke/unwind instructions! - PM.add(createLowerInvokePass()); + PM.add(createLowerInvokePass(getTargetLowering())); // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.77 - 1.78
---
Log message:
add setJumpBufSize() and setJumpBufAlignment() to target-lowering.
Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example
---
Diffs of the changes: (+31 -0)
TargetLowering.h | 31 +++
1 files changed, 31 insertions(+)
Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.77
llvm/include/llvm/Target/TargetLowering.h:1.78
--- llvm/include/llvm/Target/TargetLowering.h:1.77 Mon Jun 12 11:06:08 2006
+++ llvm/include/llvm/Target/TargetLowering.h Mon Sep 4 01:21:35 2006
@@ -327,6 +327,18 @@
return StackPointerRegisterToSaveRestore;
}
+ /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
+ /// set, the default is 200)
+ unsigned getJumpBufSize() const {
+return JumpBufSize;
+ }
+
+ /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
+ /// (if never set, the default is 0)
+ unsigned getJumpBufAlignment() const {
+return JumpBufAlignment;
+ }
+
//======//
// TargetLowering Optimization Methods
//
@@ -537,6 +549,18 @@
TargetDAGCombineArray[NT 3] |= 1 (NT7);
}
+ /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
+ /// bytes); default is 200
+ void setJumpBufSize(unsigned Size) {
+JumpBufSize = Size;
+ }
+
+ /// setJumpBufAlignment - Set the target's required jmp_buf buffer
+ /// alignment (in bytes); default is 0
+ void setJumpBufAlignment(unsigned Align) {
+JumpBufAlignment = Align;
+ }
+
public:
//======//
@@ -718,6 +742,13 @@
/// _longjmp to implement llvm.setjmp/llvm.longjmp. Defaults to false.
bool UseUnderscoreSetJmpLongJmp;
+ /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
+ unsigned JumpBufSize;
+
+ /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
+ /// buffers
+ unsigned JumpBufAlignment;
+
/// StackPointerRegisterToSaveRestore - If set to a physical register, this
/// specifies the register that llvm.savestack/llvm.restorestack should save
/// and restore.
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64InstrInfo.td updated: 1.46 - 1.47
---
Log message:
doo de doo
---
Diffs of the changes: (+158 -148)
IA64InstrInfo.td | 306 ---
1 files changed, 158 insertions(+), 148 deletions(-)
Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.46
llvm/lib/Target/IA64/IA64InstrInfo.td:1.47
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.46 Sat Feb 11 01:32:15 2006
+++ llvm/lib/Target/IA64/IA64InstrInfo.td Wed Mar 8 00:18:46 2006
@@ -26,6 +26,16 @@
[SDNPHasChain, SDNPOptInFlag];
//===-
+// Instruction types
+
+class isA { bit A=1; } // I or M unit
+class isM { bit M=1; } // M unit
+class isI { bit I=1; } // I unit
+class isB { bit B=1; } // B unit
+class isF { bit F=1; } // F unit
+class isLX { bit LX=1; } // I/B
+
+//===-
def u2imm : Operandi8;
def u6imm : Operandi8;
@@ -105,48 +115,48 @@
def ADD : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
add $dst = $src1, $src2,
- [(set GR:$dst, (add GR:$src1, GR:$src2))];
+ [(set GR:$dst, (add GR:$src1, GR:$src2))], isA;
def ADD1 : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
add $dst = $src1, $src2, 1,
- [(set GR:$dst, (add (add GR:$src1, GR:$src2), 1))];
+ [(set GR:$dst, (add (add GR:$src1, GR:$src2), 1))], isA;
def ADDS : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
adds $dst = $imm, $src1,
- [(set GR:$dst, (add GR:$src1, immSExt14:$imm))];
+ [(set GR:$dst, (add GR:$src1, immSExt14:$imm))], isA;
def MOVL : AForm_DAG0x03, 0x0b, (ops GR:$dst, s64imm:$imm),
movl $dst = $imm,
- [(set GR:$dst, imm64:$imm)];
+ [(set GR:$dst, imm64:$imm)], isLX;
def ADDL_GA : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1,
globaladdress:$imm),
addl $dst = $imm, $src1,
- [];
+ [], isA;
// hmm
def ADDL_EA : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, calltarget:$imm),
addl $dst = $imm, $src1,
- [];
+ [], isA;
def SUB : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
sub $dst = $src1, $src2,
- [(set GR:$dst, (sub GR:$src1, GR:$src2))];
+ [(set GR:$dst, (sub GR:$src1, GR:$src2))], isA;
def SUB1 : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
sub $dst = $src1, $src2, 1,
- [(set GR:$dst, (add (sub GR: $src1, GR:$src2), -1))];
+ [(set GR:$dst, (add (sub GR: $src1, GR:$src2), -1))], isA;
let isTwoAddress = 1 in {
def TPCADDIMM22 : AForm0x03, 0x0b,
(ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
-($qp) add $dst = $imm, $dst;
+($qp) add $dst = $imm, $dst, isA;
def TPCADDS : AForm_DAG0x03, 0x0b,
(ops GR:$dst, GR:$src1, s14imm:$imm, PR:$qp),
($qp) adds $dst = $imm, $dst,
-[];
+[], isA;
def TPCMPIMM8NE : AForm0x03, 0x0b,
(ops PR:$dst, PR:$src1, s22imm:$imm, GR:$src2, PR:$qp),
-($qp) cmp.ne $dst , p0 = $imm, $src2;
+($qp) cmp.ne $dst , p0 = $imm, $src2, isA;
}
// zero extend a bool (predicate reg) into an integer reg
@@ -155,66 +165,66 @@
// normal sign/zero-extends
def SXT1 : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src), sxt1 $dst = $src,
- [(set GR:$dst, (sext_inreg GR:$src, i8))];
+ [(set GR:$dst, (sext_inreg GR:$src, i8))], isI;
def ZXT1 : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src), zxt1 $dst = $src,
- [(set GR:$dst, (and GR:$src, 255))];
+ [(set GR:$dst, (and GR:$src, 255))], isI;
def SXT2 : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src), sxt2 $dst = $src,
- [(set GR:$dst, (sext_inreg GR:$src, i16))];
+ [(set GR:$dst, (sext_inreg GR:$src, i16))], isI;
def ZXT2 : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src), zxt2 $dst = $src,
- [(set GR:$dst, (and GR:$src, 65535))];
+ [(set GR:$dst, (and GR:$src, 65535))], isI;
def SXT4 : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src), sxt4 $dst = $src,
- [(set GR:$dst, (sext_inreg GR:$src, i32))];
+ [(set GR:$dst, (sext_inreg GR:$src, i32))], isI;
def ZXT4 : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src), zxt4 $dst = $src,
- [(set GR:$dst, (and GR:$src, is32ones))];
+ [(set GR:$dst, (and GR:$src, is32ones))], isI;
// fixme: shrs vs shru?
def MIX1L : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
mix1.l $dst = $src1, $src2,
[(set GR:$dst, (or (and GR:$src1, isMIX1Lable),
-(and (srl GR:$src2, (i64 8)), isMIX1Lable)))];
+(and (srl GR:$src2, (i64 8)), isMIX1Lable)))],
isI;
def MIX2L : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
mix2.l $dst = $src1, $src2,
[(set GR:$dst, (or (and GR:$src1, isMIX2Lable),
-(and (srl GR:$src2, (i64 16)),
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64AsmPrinter.cpp
Changes in directory llvm/lib/Target/IA64:
IA64AsmPrinter.cpp updated: 1.22 - 1.23
---
Log message:
distinguish between objects and register names, now we can have stuff
with names like f84, in6 etc etc.
this should fix one or two tests
---
Diffs of the changes: (+12 -6)
IA64AsmPrinter.cpp | 18 --
1 files changed, 12 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/IA64/IA64AsmPrinter.cpp
diff -u llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.22
llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.23
--- llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.22Sun Jan 22 17:37:17 2006
+++ llvm/lib/Target/IA64/IA64AsmPrinter.cpp Thu Feb 16 07:12:57 2006
@@ -235,10 +235,16 @@
if (Needfptr)
O @fptr(;
O Mang-getValueName(MO.getGlobal());
-if (Needfptr)
- O ); // close fptr(
-if (!isBRCALLinsn)
- O ); // close ltoff(
+
+if (Needfptr !isBRCALLinsn)
+ O #)); // close both fptr( and ltoff(
+else {
+ if (Needfptr)
+O #); // close only fptr(
+ if (!isBRCALLinsn)
+O #); // close only ltoff(
+}
+
int Offset = MO.getOffset();
if (Offset 0)
O + Offset;
@@ -293,11 +299,11 @@
I-hasWeakLinkage() /* FIXME: Verify correct */)) {
SwitchSection(.data, I);
if (I-hasInternalLinkage()) {
- O \t.lcomm name , TD.getTypeSize(C-getType())
+ O \t.lcomm name #, TD.getTypeSize(C-getType())
, (1 Align);
O \t\t// ;
} else {
- O \t.common name , TD.getTypeSize(C-getType())
+ O \t.common name #, TD.getTypeSize(C-getType())
, (1 Align);
O \t\t// ;
}
___
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[llvm-commits] CVS: llvm/autoconf/configure.ac
Changes in directory llvm/autoconf: configure.ac updated: 1.207 - 1.208 --- Log message: previously, configure would die if GCC or ICC was not found. Now it'll go through, but we do want to know if we're using GCC/ICC since they share certain funky command line options (for dependency generation stuff) --- Diffs of the changes: (+0 -11) configure.ac | 11 --- 1 files changed, 11 deletions(-) Index: llvm/autoconf/configure.ac diff -u llvm/autoconf/configure.ac:1.207 llvm/autoconf/configure.ac:1.208 --- llvm/autoconf/configure.ac:1.207Sat Feb 4 23:56:51 2006 +++ llvm/autoconf/configure.ac Tue Feb 14 21:15:55 2006 @@ -412,17 +412,6 @@ ;; esac -if test $GCC != yes test $ICC != yes -then - AC_MSG_ERROR([gcc|icc required but not found]) -fi - -dnl Ensure that compilation tools are GCC; we use GCC specific extensions -if test $GXX != yes test $IXX != yes -then - AC_MSG_ERROR([g++|icc required but not found]) -fi - dnl Verify that GCC is version 3.0 or higher if test $GCC = yes then ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/configure
Changes in directory llvm:
configure updated: 1.209 - 1.210
---
Log message:
zap
---
Diffs of the changes: (+0 -14)
configure | 14 --
1 files changed, 14 deletions(-)
Index: llvm/configure
diff -u llvm/configure:1.209 llvm/configure:1.210
--- llvm/configure:1.209Sun Feb 5 00:26:43 2006
+++ llvm/configure Tue Feb 14 21:16:52 2006
@@ -24870,20 +24870,6 @@
;;
esac
-if test $GCC != yes test $ICC != yes
-then
- { { echo $as_me:$LINENO: error: gcc|icc required but not found 5
-echo $as_me: error: gcc|icc required but not found 2;}
- { (exit 1); exit 1; }; }
-fi
-
-if test $GXX != yes test $IXX != yes
-then
- { { echo $as_me:$LINENO: error: g++|icc required but not found 5
-echo $as_me: error: g++|icc required but not found 2;}
- { (exit 1); exit 1; }; }
-fi
-
if test $GCC = yes
then
gccmajor=`$CC --version | head -n 1 | sed 's/[^0-9]*\([0-9.]\).*/\1/'`
___
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[llvm-commits] CVS: llvm/Makefile.rules
Changes in directory llvm: Makefile.rules updated: 1.342 - 1.343 --- Log message: oops, I meant this --- Diffs of the changes: (+1 -1) Makefile.rules |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.342 llvm/Makefile.rules:1.343 --- llvm/Makefile.rules:1.342 Mon Feb 13 23:12:00 2006 +++ llvm/Makefile.rules Tue Feb 14 21:20:16 2006 @@ -347,7 +347,7 @@ CompileCommonOpts := -Wall -W -Wwrite-strings -Wno-unused ifeq ($(OS),HP-UX) - CompileCommonOpts += -D_REENTRANT -D_HPUX_SOURCE + CompileCommonOpts := -D_REENTRANT -D_HPUX_SOURCE endif LD.Flags += -L$(LibDir) -L$(LLVMLibDir) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/Makefile.rules
Changes in directory llvm: Makefile.rules updated: 1.343 - 1.344 --- Log message: HP aCC (and a bunch of other compilers, no doubt) don't share GCC's syntax for auto-dependency generation stuff. This should be changed to be disabling dependency stuff unless GCC/ICC is found. --- Diffs of the changes: (+5 -0) Makefile.rules |5 + 1 files changed, 5 insertions(+) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.343 llvm/Makefile.rules:1.344 --- llvm/Makefile.rules:1.343 Tue Feb 14 21:20:16 2006 +++ llvm/Makefile.rules Tue Feb 14 21:23:26 2006 @@ -951,6 +951,11 @@ # Object Build Rules: Build object files based on sources ### +# FIXME: This should be checking for if not GCC or ICC, not for if HP-UX +ifeq ($(OS),HP-UX) + DISABLE_AUTO_DEPENDENCIES=1 +endif + # Provide rule sets for when dependency generation is enabled ifndef DISABLE_AUTO_DEPENDENCIES ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/configure
Changes in directory llvm:
configure updated: 1.210 - 1.211
---
Log message:
reverting previous change, will add support for other compilers later
---
Diffs of the changes: (+14 -0)
configure | 14 ++
1 files changed, 14 insertions(+)
Index: llvm/configure
diff -u llvm/configure:1.210 llvm/configure:1.211
--- llvm/configure:1.210Tue Feb 14 21:16:52 2006
+++ llvm/configure Wed Feb 15 01:56:38 2006
@@ -24870,6 +24870,20 @@
;;
esac
+if test $GCC != yes test $ICC != yes
+then
+ { { echo $as_me:$LINENO: error: gcc|icc required but not found 5
+echo $as_me: error: gcc|icc required but not found 2;}
+ { (exit 1); exit 1; }; }
+fi
+
+if test $GXX != yes test $IXX != yes
+then
+ { { echo $as_me:$LINENO: error: g++|icc required but not found 5
+echo $as_me: error: g++|icc required but not found 2;}
+ { (exit 1); exit 1; }; }
+fi
+
if test $GCC = yes
then
gccmajor=`$CC --version | head -n 1 | sed 's/[^0-9]*\([0-9.]\).*/\1/'`
___
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[llvm-commits] CVS: llvm/autoconf/configure.ac
Changes in directory llvm/autoconf: configure.ac updated: 1.208 - 1.209 --- Log message: reverting previous change, will add support for other compilers later --- Diffs of the changes: (+11 -0) configure.ac | 11 +++ 1 files changed, 11 insertions(+) Index: llvm/autoconf/configure.ac diff -u llvm/autoconf/configure.ac:1.208 llvm/autoconf/configure.ac:1.209 --- llvm/autoconf/configure.ac:1.208Tue Feb 14 21:15:55 2006 +++ llvm/autoconf/configure.ac Wed Feb 15 01:57:42 2006 @@ -412,6 +412,17 @@ ;; esac +if test $GCC != yes test $ICC != yes +then + AC_MSG_ERROR([gcc|icc required but not found]) +fi + +dnl Ensure that compilation tools are GCC; we use GCC specific extensions +if test $GXX != yes test $IXX != yes +then + AC_MSG_ERROR([g++|icc required but not found]) +fi + dnl Verify that GCC is version 3.0 or higher if test $GCC = yes then ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64InstrInfo.td updated: 1.45 - 1.46
---
Log message:
now short immediates will get matched (previously constants were all
triggering movl 64bit imm fat instructions)
---
Diffs of the changes: (+3 -5)
IA64InstrInfo.td |8 +++-
1 files changed, 3 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.45
llvm/lib/Target/IA64/IA64InstrInfo.td:1.46
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.45 Thu Jan 26 19:46:15 2006
+++ llvm/lib/Target/IA64/IA64InstrInfo.td Sat Feb 11 01:32:15 2006
@@ -99,11 +99,9 @@
return (v = 8191 v = -8192);
}];
-def imm64 : PatLeaf(i64 imm), [{
- // imm64 predicate - True if the immediate fits in a 64-bit
- // field - i.e., true. used to keep movl happy
- return true;
-}];
+// imm64 predicate - True if the immediate fits in a 64-bit
+// field - i.e., true. used to keep movl happy
+def imm64 : PatLeaf(i64 imm);
def ADD : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
add $dst = $src1, $src2,
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64: IA64ISelDAGToDAG.cpp updated: 1.36 - 1.37 --- Log message: fix storing booleans (grawp missed this one) --- Diffs of the changes: (+3 -3) IA64ISelDAGToDAG.cpp |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.36 llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.37 --- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.36 Thu Feb 9 01:17:49 2006 +++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sat Feb 11 01:33:17 2006 @@ -556,9 +556,9 @@ // then load 1 into the same reg iff the predicate to store is 1 SDOperand Tmp; Select(Tmp, N-getOperand(1)); -CurDAG-getTargetNode(IA64::TPCADDS, MVT::i64, Initial, - CurDAG-getConstant(1, MVT::i64), - Tmp); +Tmp = SDOperand(CurDAG-getTargetNode(IA64::TPCADDS, MVT::i64, Initial, + CurDAG-getConstant(1, MVT::i64), + Tmp), 0); Result = CurDAG-SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain); return; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64Bundling.cpp IA64InstrInfo.td IA64RegisterInfo.cpp
Changes in directory llvm/lib/Target/IA64:
IA64Bundling.cpp updated: 1.1 - 1.2
IA64InstrInfo.td updated: 1.43 - 1.44
IA64RegisterInfo.cpp updated: 1.12 - 1.13
---
Log message:
some hoovering
---
Diffs of the changes: (+13 -9)
IA64Bundling.cpp |7 ---
IA64InstrInfo.td |7 +--
IA64RegisterInfo.cpp |8
3 files changed, 13 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/IA64/IA64Bundling.cpp
diff -u llvm/lib/Target/IA64/IA64Bundling.cpp:1.1
llvm/lib/Target/IA64/IA64Bundling.cpp:1.2
--- llvm/lib/Target/IA64/IA64Bundling.cpp:1.1 Tue Jan 24 20:23:38 2006
+++ llvm/lib/Target/IA64/IA64Bundling.cpp Thu Jan 26 03:08:31 2006
@@ -2,8 +2,8 @@
//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file was developed by Duraid Madina and is distributed under the
+// University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===--===//
//
@@ -56,7 +56,8 @@
std::setunsigned PendingRegWrites; // XXX: ugly global, but
// pending writes can cross basic blocks. Note that
- // taken branches end instruction groups.
+ // taken branches end instruction groups. So we
+// only need to worry about 'fallthrough' code
};
} // end of anonymous namespace
Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.43
llvm/lib/Target/IA64/IA64InstrInfo.td:1.44
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.43 Tue Jan 24 20:23:38 2006
+++ llvm/lib/Target/IA64/IA64InstrInfo.td Thu Jan 26 03:08:31 2006
@@ -501,10 +501,13 @@
def SHRSI : AForm0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
shr $dst = $src1, $imm;
-def EXTRU : AForm0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1,
u6imm:$imm2),
+def EXTRU : AForm0x03, 0x0b,
+ (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
extr.u $dst = $src1, $imm1, $imm2;
-def DEPZ : AForm0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1,
u6imm:$imm2), dep.z $dst = $src1, $imm1, $imm2;
+def DEPZ : AForm0x03, 0x0b,
+ (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
+ dep.z $dst = $src1, $imm1, $imm2;
def PCMPEQOR : AForm0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
($qp) cmp.eq.or $dst, p0 = $src1, $src2;
Index: llvm/lib/Target/IA64/IA64RegisterInfo.cpp
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.12
llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.13
--- llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.12 Tue Jan 24 20:23:38 2006
+++ llvm/lib/Target/IA64/IA64RegisterInfo.cpp Thu Jan 26 03:08:31 2006
@@ -168,8 +168,8 @@
if ( Offset = 8191 Offset = -8192) { // smallish offset
//fix up the old:
MI.SetMachineOperandReg(i, IA64::r22);
-MachineOperand MO = MI.getOperand(i);
-MO.setUse(); // mark r22 as being used (the bundler wants to know this)
+MI.getOperand(i).setUse(); // mark r22 as being used
+ // (the bundler wants to know this)
//insert the new
MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22)
.addReg(BaseRegister).addSImm(Offset);
@@ -177,8 +177,8 @@
} else { // it's big
//fix up the old:
MI.SetMachineOperandReg(i, IA64::r22);
-MachineOperand MO = MI.getOperand(i);
-MO.setUse(); // mark r22 as being used (the bundler wants to know this)
+MI.getOperand(i).setUse(); // mark r22 as being used
+ // (the bundler wants to know this)
MachineInstr* nMI;
nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(Offset);
MBB.insert(II, nMI);
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64RegisterInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64RegisterInfo.td updated: 1.14 - 1.15
---
Log message:
fix stack corruption! Previously, 16-byte whole-FP-register stores were
being treated as needing only 8 bytes (though they were 16 byte aligned.)
This should fix a bunch of tests - anyone have any comments, though?
- in Target.td , SpillSize and SpillAlignment seem dead - is this what
Size and Alignment do now?
- in CodeGenRegisters.h/CodeGenTarget.cpp , DeclaredSpillSize and
DeclaredSpillAlignment seem dead.
- there are a bunch of comments here and there that don't clearly
distinguish between 'size' and 'spillsize' etc. hmm.
---
Diffs of the changes: (+7 -4)
IA64RegisterInfo.td | 11 +++
1 files changed, 7 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/IA64/IA64RegisterInfo.td
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.td:1.14
llvm/lib/Target/IA64/IA64RegisterInfo.td:1.15
--- llvm/lib/Target/IA64/IA64RegisterInfo.td:1.14 Mon Jan 23 00:08:46 2006
+++ llvm/lib/Target/IA64/IA64RegisterInfo.tdThu Jan 26 03:45:03 2006
@@ -283,10 +283,7 @@
// these are the scratch (+stacked) FP registers
-// the 128 here is to make stf.spill/ldf.fill happy,
-// when storing full (82-bit) FP regs to stack slots
-// we need to 16-byte align
-def FP : RegisterClassIA64, [f64], 128,
+def FP : RegisterClassIA64, [f64], 64,
[F6, F7,
F8, F9, F10, F11, F12, F13, F14, F15,
F32, F33, F34, F35, F36, F37, F38, F39,
@@ -303,6 +300,12 @@
F120, F121, F122, F123, F124, F125, F126, F127,
F0, F1] // these last two are hidden
{
+// the 128s here are to make stf.spill/ldf.fill happy,
+// when storing full (82-bit) FP regs to stack slots
+// we need to 16-byte align
+let Size=128;
+let Alignment=128;
+
let MethodProtos = [{
iterator allocation_order_begin(MachineFunction MF) const;
iterator allocation_order_end(MachineFunction MF) const;
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64Bundling.cpp IA64.h IA64InstrInfo.cpp IA64InstrInfo.td IA64RegisterInfo.cpp IA64TargetMachine.cpp
Changes in directory llvm/lib/Target/IA64:
IA64Bundling.cpp added (r1.1)
IA64.h updated: 1.3 - 1.4
IA64InstrInfo.cpp updated: 1.3 - 1.4
IA64InstrInfo.td updated: 1.42 - 1.43
IA64RegisterInfo.cpp updated: 1.11 - 1.12
IA64TargetMachine.cpp updated: 1.10 - 1.11
---
Log message:
add bundling! well not really, for now it's just stop-insertion.
---
Diffs of the changes: (+277 -154)
IA64.h|6
IA64Bundling.cpp | 111 ++
IA64InstrInfo.cpp |1
IA64InstrInfo.td | 302 +-
IA64RegisterInfo.cpp |6
IA64TargetMachine.cpp |5
6 files changed, 277 insertions(+), 154 deletions(-)
Index: llvm/lib/Target/IA64/IA64Bundling.cpp
diff -c /dev/null llvm/lib/Target/IA64/IA64Bundling.cpp:1.1
*** /dev/null Tue Jan 24 20:23:48 2006
--- llvm/lib/Target/IA64/IA64Bundling.cpp Tue Jan 24 20:23:38 2006
***
*** 0
--- 1,111
+ //===-- IA64Bundling.cpp - IA-64 instruction bundling pass.
--===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for
details.
+ //
+
//===--===//
+ //
+ // Add stops where required to prevent read-after-write and write-after-write
+ // dependencies, for both registers and memory addresses. There are
exceptions:
+ //
+ //- Compare instructions (cmp*, tbit, tnat, fcmp, frcpa) are OK with
+ // WAW dependencies so long as they all target p0, or are of parallel
+ // type (.and*/.or*)
+ //
+ // FIXME: bundling, for now, is left to the assembler.
+ // FIXME: this might be an appropriate place to translate between different
+ //instructions that do the same thing, if this helps bundling.
+ //
+
//===--===//
+
+ #include IA64.h
+ #include llvm/CodeGen/MachineFunctionPass.h
+ #include llvm/CodeGen/MachineInstrBuilder.h
+ #include llvm/ADT/SetOperations.h
+ #include llvm/ADT/Statistic.h
+ #include llvm/Support/Debug.h
+ #include set
+ #include iostream
+ using namespace llvm;
+
+ namespace {
+ Statistic StopBitsAdded(ia64-codegen, Number of stop bits added);
+
+ struct IA64BundlingPass : public MachineFunctionPass {
+ /// Target machine description which we query for reg. names, data
+ /// layout, etc.
+ ///
+ TargetMachine TM;
+
+ IA64BundlingPass(TargetMachine tm) : TM(tm) { }
+
+ virtual const char *getPassName() const {
+ return IA64 (Itanium) Bundling Pass;
+ }
+
+ bool runOnMachineBasicBlock(MachineBasicBlock MBB);
+ bool runOnMachineFunction(MachineFunction F) {
+ bool Changed = false;
+ for (MachineFunction::iterator FI = F.begin(), FE = F.end();
+FI != FE; ++FI)
+ Changed |= runOnMachineBasicBlock(*FI);
+ return Changed;
+ }
+
+ std::setunsigned PendingRegWrites; // XXX: ugly global, but
+ // pending writes can cross basic blocks. Note that
+ // taken branches end instruction groups.
+ };
+ } // end of anonymous namespace
+
+ /// createIA64BundlingPass - Returns a pass that adds STOP (;;) instructions
+ /// and arranges the result into bundles.
+ ///
+ FunctionPass *llvm::createIA64BundlingPass(TargetMachine tm) {
+ return new IA64BundlingPass(tm);
+ }
+
+ /// runOnMachineBasicBlock - add stops and bundle this MBB.
+ ///
+ bool IA64BundlingPass::runOnMachineBasicBlock(MachineBasicBlock MBB) {
+ bool Changed = false;
+
+ for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
+ MachineInstr *CurrentInsn = I++;
+ std::setunsigned CurrentReads, CurrentWrites, OrigWrites;
+
+ for(unsigned i=0; i CurrentInsn-getNumOperands(); i++) {
+ MachineOperand MO=CurrentInsn-getOperand(i);
+ if(MO.isRegister()) {
+ if(MO.isUse()) { // TODO: exclude p0
+ CurrentReads.insert(MO.getReg());
+ }
+ if(MO.isDef()) { // TODO: exclude p0
+ CurrentWrites.insert(MO.getReg());
+ OrigWrites.insert(MO.getReg()); // FIXME: use a nondestructive
+ // set_intersect instead?
+ }
+ }
+ }
+
+ // CurrentReads/CurrentWrites contain info for the current instruction.
+ // Does it read or write any registers that are pending a write?
+ // (i.e. not separated by a stop)
+ set_intersect(CurrentReads, PendingRegWrites);
+ set_intersect(CurrentWrites, PendingRegWrites);
+
+ if(! (CurrentReads.empty() CurrentWrites.empty()) ) {
+ // there is a conflict, insert a stop and reset PendingRegWrites
+ CurrentInsn = BuildMI(MBB, CurrentInsn, IA64::STOP, 0);
+ PendingRegWrites=OrigWrites; // carry over current
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64.td
Changes in directory llvm/lib/Target/IA64: IA64.td updated: 1.5 - 1.6 --- Log message: die, die!! r15, you are not callee-saved --- Diffs of the changes: (+0 -1) IA64.td |1 - 1 files changed, 1 deletion(-) Index: llvm/lib/Target/IA64/IA64.td diff -u llvm/lib/Target/IA64/IA64.td:1.5 llvm/lib/Target/IA64/IA64.td:1.6 --- llvm/lib/Target/IA64/IA64.td:1.5Mon Jan 23 00:08:46 2006 +++ llvm/lib/Target/IA64/IA64.tdMon Jan 23 00:11:45 2006 @@ -51,7 +51,6 @@ // r12, // memory stack pointer (SP)- XXX NOT callee saved, we do it ourselves // rp, // return branch register (rp/b0) - we do this ourselves // r13 (thread pointer) we do not touch, ever. it's not here. // - //r15, //'stacked' GRs the RSE takes care of, we don't worry about /* We don't want PEI::calculateCallerSavedRegisters to worry about them, ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/MultiSource/Applications/Makefile
Changes in directory llvm-test/MultiSource/Applications: Makefile updated: 1.22 - 1.23 --- Log message: adding the ogg vorbis encoder --- Diffs of the changes: (+1 -1) Makefile |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/MultiSource/Applications/Makefile diff -u llvm-test/MultiSource/Applications/Makefile:1.22 llvm-test/MultiSource/Applications/Makefile:1.23 --- llvm-test/MultiSource/Applications/Makefile:1.22Tue Nov 8 15:11:32 2005 +++ llvm-test/MultiSource/Applications/Makefile Sat Jan 21 08:49:08 2006 @@ -4,7 +4,7 @@ include $(LEVEL)/Makefile.config -PARALLEL_DIRS = Burg aha sgefa siod lambda-0.1.3 d spiff hbd treecc SPASS hexxagon +PARALLEL_DIRS = Burg aha sgefa siod lambda-0.1.3 d spiff hbd treecc SPASS hexxagon oggenc # Obsequi uses Linux-only features; need to fix that ifeq ($(OS),Linux) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/LICENSE.TXT
Changes in directory llvm-test: LICENSE.TXT updated: 1.9 - 1.10 --- Log message: oggenc is Free --- Diffs of the changes: (+1 -0) LICENSE.TXT |1 + 1 files changed, 1 insertion(+) Index: llvm-test/LICENSE.TXT diff -u llvm-test/LICENSE.TXT:1.9 llvm-test/LICENSE.TXT:1.10 --- llvm-test/LICENSE.TXT:1.9 Wed May 18 14:43:33 2005 +++ llvm-test/LICENSE.TXT Sat Jan 21 08:56:27 2006 @@ -75,6 +75,7 @@ obsequi:llvm-test/MultiSource/Applications/obsequi Hexxagon: llvm-test/MultiSource/Applications/hexxagon SPASS: llvm-test/MultiSource/Applications/SPASS +oggenc: llvm-test/MultiSource/Applications/oggenc smg2000:llvm-test/MultiSource/Benchmarks/ASCI_Purple/SMG2000 Fhourstones:llvm-test/MultiSource/Benchmarks/Fhourstones McCat: llvm-test/MultiSource/Benchmarks/McCat ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-test/MultiSource/Applications/oggenc/COPYING LICENSE.TXT
Changes in directory llvm-test/MultiSource/Applications/oggenc: COPYING added (r1.1) LICENSE.TXT added (r1.1) --- Log message: license stuff --- Diffs of the changes: (+341 -0) COPYING | 340 LICENSE.TXT |1 2 files changed, 341 insertions(+) Index: llvm-test/MultiSource/Applications/oggenc/COPYING diff -c /dev/null llvm-test/MultiSource/Applications/oggenc/COPYING:1.1 *** /dev/null Sat Jan 21 08:58:47 2006 --- llvm-test/MultiSource/Applications/oggenc/COPYING Sat Jan 21 08:58:37 2006 *** *** 0 --- 1,340 + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your + freedom to share and change it. By contrast, the GNU General Public + License is intended to guarantee your freedom to share and change free + software--to make sure the software is free for all its users. This + General Public License applies to most of the Free Software + Foundation's software and to any other program whose authors commit to + using it. (Some other Free Software Foundation software is covered by + the GNU Library General Public License instead.) You can apply it to + your programs, too. + + When we speak of free software, we are referring to freedom, not + price. Our General Public Licenses are designed to make sure that you + have the freedom to distribute copies of free software (and charge for + this service if you wish), that you receive source code or can get it + if you want it, that you can change the software or use pieces of it + in new free programs; and that you know you can do these things. + + To protect your rights, we need to make restrictions that forbid + anyone to deny you these rights or to ask you to surrender the rights. + These restrictions translate to certain responsibilities for you if you + distribute copies of the software, or if you modify it. + + For example, if you distribute copies of such a program, whether + gratis or for a fee, you must give the recipients all the rights that + you have. You must make sure that they, too, receive or can get the + source code. And you must show them these terms so they know their + rights. + + We protect your rights with two steps: (1) copyright the software, and + (2) offer you this license which gives you legal permission to copy, + distribute and/or modify the software. + + Also, for each author's protection and ours, we want to make certain + that everyone understands that there is no warranty for this free + software. If the software is modified by someone else and passed on, we + want its recipients to know that what they have is not the original, so + that any problems introduced by others will not reflect on the original + authors' reputations. + + Finally, any free program is threatened constantly by software + patents. We wish to avoid the danger that redistributors of a free + program will individually obtain patent licenses, in effect making the + program proprietary. To prevent this, we have made it clear that any + patent must be licensed for everyone's free use or not licensed at all. + + The precise terms and conditions for copying, distribution and + modification follow. + + GNU GENERAL PUBLIC LICENSE +TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + 0. This License applies to any program or other work which contains + a notice placed by the copyright holder saying it may be distributed + under the terms of this General Public License. The Program, below, + refers to any such program or work, and a work based on the Program + means either the Program or any derivative work under copyright law: + that is to say, a work containing the Program or a portion of it, + either verbatim or with modifications and/or translated into another + language. (Hereinafter, translation is included without limitation in + the term modification.) Each licensee is addressed as you. + + Activities other than copying, distribution and modification are not + covered by this License; they are outside its scope. The act of + running the Program is not restricted, and the output from the Program + is covered only if its contents constitute a work based on the + Program (independent of having been made by running the Program). + Whether that is true depends on what the Program does. + + 1. You may copy and distribute verbatim copies of the Program's + source code as you receive it, in any medium, provided that you + conspicuously and appropriately publish on each copy an appropriate + copyright
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.26 - 1.27
IA64ISelLowering.cpp updated: 1.23 - 1.24
---
Log message:
fix sext breakage: now we correctly deal with functions that return
int vs uint
---
Diffs of the changes: (+5 -1)
IA64ISelDAGToDAG.cpp |2 +-
IA64ISelLowering.cpp |4
2 files changed, 5 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.26
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.27
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.26 Thu Jan 19 21:40:25 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Fri Jan 20 10:10:05 2006
@@ -494,7 +494,7 @@
*/
case ISD::LOAD:
- case ISD::EXTLOAD:
+ case ISD::EXTLOAD: // FIXME: load -1, not 1, for bools?
case ISD::ZEXTLOAD: {
SDOperand Chain = Select(N-getOperand(0));
SDOperand Address = Select(N-getOperand(1));
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.23
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.24
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.23 Thu Jan 19 02:31:51 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Fri Jan 20 10:10:05 2006
@@ -475,6 +475,8 @@
switch (RetTyVT) {
default: assert(0 Unknown value type to return!);
case MVT::i1: { // bools are just like other integers (returned in r8)
+ // we *could* fall through to the truncate below, but this saves a
+ // few redundant predicate ops
SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64,
InFlag);
InFlag = boolInR8.getValue(2);
Chain = boolInR8.getValue(1);
@@ -492,8 +494,10 @@
Chain = RetVal.getValue(1);
// keep track of whether it is sign or zero extended (todo: bools?)
+/* XXX
RetVal = DAG.getNode(RetTy-isSigned() ? ISD::AssertSext
:ISD::AssertZext,
MVT::i64, RetVal, DAG.getValueType(RetTyVT));
+*/
RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
break;
case MVT::i64:
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64ISelLowering.cpp IA64ISelLowering.h IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.27 - 1.28
IA64ISelLowering.cpp updated: 1.24 - 1.25
IA64ISelLowering.h updated: 1.4 - 1.5
IA64InstrInfo.td updated: 1.41 - 1.42
---
Log message:
remove RET hack, add proper support for rets (watching out for ret voids)
---
Diffs of the changes: (+89 -56)
IA64ISelDAGToDAG.cpp | 51 ---
IA64ISelLowering.cpp | 66 +++
IA64ISelLowering.h | 16 ++--
IA64InstrInfo.td | 12 ++---
4 files changed, 89 insertions(+), 56 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.27
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.28
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.27 Fri Jan 20 10:10:05 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Fri Jan 20 14:24:31 2006
@@ -585,57 +585,6 @@
getI64Imm(Amt), Select(N-getOperand(0)));
}
- case ISD::RET: {
-SDOperand Chain = Select(N-getOperand(0)); // Token chain.
-SDOperand InFlag;
-
-switch (N-getNumOperands()) {
-default:
- assert(0 Unknown return instruction!);
-case 2: {
- SDOperand RetVal = Select(N-getOperand(1));
- switch (RetVal.getValueType()) {
- default: assert(0 I don't know how to return this type! (promote?));
- // FIXME: do I need to add support for bools here?
- // (return '0' or '1' in r8, basically...)
- //
- // FIXME: need to round floats - 80 bits is bad, the tester
- // told me so
- case MVT::i64:
-// we mark r8 as live on exit up above in LowerArguments()
-// BuildMI(BB, IA64::MOV, 1, IA64::r8).addReg(Tmp1);
-Chain = CurDAG-getCopyToReg(Chain, IA64::r8, RetVal);
- InFlag = Chain.getValue(1);
- break;
- case MVT::f64:
-// we mark F8 as live on exit up above in LowerArguments()
-// BuildMI(BB, IA64::FMOV, 1, IA64::F8).addReg(Tmp1);
-Chain = CurDAG-getCopyToReg(Chain, IA64::F8, RetVal);
- InFlag = Chain.getValue(1);
-break;
- }
- break;
- }
-case 1:
- break;
-}
-
-// we need to copy VirtGPR (the vreg (to become a real reg)) that holds
-// the output of this function's alloc instruction back into ar.pfs
-// before we return. this copy must not float up above the last
-// outgoing call in this function!!!
-SDOperand AR_PFSVal = CurDAG-getCopyFromReg(Chain, IA64Lowering.VirtGPR,
- MVT::i64);
-Chain = AR_PFSVal.getValue(1);
-Chain = CurDAG-getCopyToReg(Chain, IA64::AR_PFS, AR_PFSVal);
-
-// and then just emit a 'ret' instruction
-// before returning, restore the ar.pfs register (set by the 'alloc' up
top)
-// BuildMI(BB, IA64::MOV,
1).addReg(IA64::AR_PFS).addReg(IA64Lowering.VirtGPR);
-//
-return CurDAG-SelectNodeTo(N, IA64::RET, MVT::Other, Chain);
- }
-
case ISD::BR:
// FIXME: we don't need long branches all the time!
return CurDAG-SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.24
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.25
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.24 Fri Jan 20 10:10:05 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Fri Jan 20 14:24:31 2006
@@ -39,6 +39,11 @@
setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
+ // We need to handle ISD::RET for void functions ourselves,
+ // so we get a chance to restore ar.pfs before adding a
+ // br.ret insn
+ setOperationAction(ISD::RET, MVT::Other, Custom);
+
setSetCCResultType(MVT::i1);
setShiftAmountType(MVT::i64);
@@ -101,6 +106,7 @@
default: return 0;
case IA64ISD::GETFD: return IA64ISD::GETFD;
case IA64ISD::BRCALL: return IA64ISD::BRCALL;
+ case IA64ISD::RET_FLAG: return IA64ISD::RET_FLAG;
}
}
@@ -524,6 +530,44 @@
return std::make_pair(RetVal, Chain);
}
+SDOperand IA64TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
+ SelectionDAG DAG) {
+ SDOperand Copy, InFlag;
+ SDOperand AR_PFSVal = DAG.getCopyFromReg(Chain, this-VirtGPR,
+ MVT::i64);
+ Chain = AR_PFSVal.getValue(1);
+
+ switch (Op.getValueType()) {
+ default: assert(0 Unknown type to return! (promote?));
+ case MVT::i64:
+Copy = DAG.getCopyToReg(Chain, IA64::r8, Op, InFlag);
+break;
+ case MVT::f64:
+Copy = DAG.getCopyToReg(Chain, IA64::F8, Op, InFlag);
+break;
+ }
+
+ Chain = Copy.getValue(0);
+ InFlag = Copy.getValue(1);
+ // we need to copy VirtGPR (the vreg (to become a real reg))
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelLowering.cpp updated: 1.22 - 1.23
---
Log message:
fix calls that return f32
---
Diffs of the changes: (+7 -2)
IA64ISelLowering.cpp |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.22
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.23
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.22 Sun Jan 15 03:45:23 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Thu Jan 19 02:31:51 2006
@@ -473,7 +473,7 @@
SDOperand RetVal;
if (RetTyVT != MVT::isVoid) {
switch (RetTyVT) {
-default: // assert(0 Unknown value type to return!);
+default: assert(0 Unknown value type to return!);
case MVT::i1: { // bools are just like other integers (returned in r8)
SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64,
InFlag);
InFlag = boolInR8.getValue(2);
@@ -491,7 +491,7 @@
RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
Chain = RetVal.getValue(1);
- // Add a note to keep track of whether it is sign or zero extended -
TODO: bools
+ // keep track of whether it is sign or zero extended (todo: bools?)
RetVal = DAG.getNode(RetTy-isSigned() ? ISD::AssertSext
:ISD::AssertZext,
MVT::i64, RetVal, DAG.getValueType(RetTyVT));
RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
@@ -501,6 +501,11 @@
Chain = RetVal.getValue(1);
InFlag = RetVal.getValue(2); // XXX dead
break;
+case MVT::f32:
+ RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
+ Chain = RetVal.getValue(1);
+ RetVal = DAG.getNode(ISD::TRUNCATE, MVT::f32, RetVal);
+ break;
case MVT::f64:
RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
Chain = RetVal.getValue(1);
___
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[llvm-commits] CVS: llvm-test/Makefile.programs
Changes in directory llvm-test: Makefile.programs updated: 1.184 - 1.185 --- Log message: look at those cute little opcodes running around!! --- Diffs of the changes: (+1 -1) Makefile.programs |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.184 llvm-test/Makefile.programs:1.185 --- llvm-test/Makefile.programs:1.184 Mon Jan 16 20:35:29 2006 +++ llvm-test/Makefile.programs Thu Jan 19 08:17:29 2006 @@ -194,7 +194,7 @@ # -enable-alpha-FTOI -enable-alpha-intfpdiv endif ifeq ($(ARCH),IA64) -LLCBETAOPTION := -enable-ia64-dag-isel +LLCBETAOPTION := -sched=simple endif ifeq ($(ARCH),x86) LLCBETAOPTION := -enable-x86-dag-isel ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64TargetMachine.cpp
Changes in directory llvm/lib/Target/IA64: IA64TargetMachine.cpp updated: 1.8 - 1.9 --- Log message: click click --- Diffs of the changes: (+3 -5) IA64TargetMachine.cpp |8 +++- 1 files changed, 3 insertions(+), 5 deletions(-) Index: llvm/lib/Target/IA64/IA64TargetMachine.cpp diff -u llvm/lib/Target/IA64/IA64TargetMachine.cpp:1.8 llvm/lib/Target/IA64/IA64TargetMachine.cpp:1.9 --- llvm/lib/Target/IA64/IA64TargetMachine.cpp:1.8 Mon Nov 7 20:11:51 2005 +++ llvm/lib/Target/IA64/IA64TargetMachine.cpp Thu Jan 19 08:13:11 2006 @@ -103,11 +103,9 @@ PM.add(createUnreachableBlockEliminationPass()); // Add an instruction selector - if(EnableDAGIsel) -PM.add(createIA64DAGToDAGInstructionSelector(*this)); - else -PM.add(createIA64PatternInstructionSelector(*this)); - +// FIXME: reap this option one day: if(EnableDAGIsel) + PM.add(createIA64DAGToDAGInstructionSelector(*this)); + /* XXX not yet. ;) // Run optional SSA-based machine code optimizations next... if (!NoSSAPeephole) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.39 - 1.40 --- Log message: fix boolean XOR (which fixes up comparisons..) --- Diffs of the changes: (+4 -1) IA64InstrInfo.td |5 - 1 files changed, 4 insertions(+), 1 deletion(-) Index: llvm/lib/Target/IA64/IA64InstrInfo.td diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.39 llvm/lib/Target/IA64/IA64InstrInfo.td:1.40 --- llvm/lib/Target/IA64/IA64InstrInfo.td:1.39 Mon Jan 16 20:04:52 2006 +++ llvm/lib/Target/IA64/IA64InstrInfo.td Thu Jan 19 09:18:56 2006 @@ -142,6 +142,9 @@ def TPCADDIMM22 : AForm0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp), ($qp) add $dst = $imm, $dst;;; +def TPCADDS : AForm0x03, 0x0b, + (ops GR:$dst, GR:$src1, s14imm:$imm, PR:$qp), +($qp) adds $dst = $imm, $dst;;; def TPCMPIMM8NE : AForm0x03, 0x0b, (ops PR:$dst, PR:$src1, s22imm:$imm, GR:$src2, PR:$qp), ($qp) cmp.ne $dst , p0 = $imm, $src2;;; @@ -377,7 +380,7 @@ def bXOR : Pat(xor PR:$src1, PR:$src2), (TPCMPIMM8NE (PCMPEQUNCR0R0 PR:$src2), 1, - (PADDS r0, 1, PR:$src2), + (TPCADDS (ADDS r0, 0), 1, PR:$src2), PR:$src1); def XOR : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64: IA64ISelDAGToDAG.cpp updated: 1.25 - 1.26 IA64InstrInfo.td updated: 1.40 - 1.41 --- Log message: fix storing bools! eek! --- Diffs of the changes: (+5 -8) IA64ISelDAGToDAG.cpp |4 ++-- IA64InstrInfo.td |9 +++-- 2 files changed, 5 insertions(+), 8 deletions(-) Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.25 llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.26 --- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.25 Mon Jan 16 21:09:48 2006 +++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Thu Jan 19 21:40:25 2006 @@ -542,9 +542,9 @@ // first load zero! SDOperand Initial = CurDAG-getCopyFromReg(Chain, IA64::r0, MVT::i64); Chain = Initial.getValue(1); - // then load 1 iff the predicate to store is 1 + // then load 1 into the same reg iff the predicate to store is 1 SDOperand Tmp = - CurDAG-getTargetNode(IA64::PADDS, MVT::i64, Initial, + CurDAG-getTargetNode(IA64::TPCADDS, MVT::i64, Initial, CurDAG-getConstant(1, MVT::i64), Select(N-getOperand(1))); return CurDAG-SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain); Index: llvm/lib/Target/IA64/IA64InstrInfo.td diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.40 llvm/lib/Target/IA64/IA64InstrInfo.td:1.41 --- llvm/lib/Target/IA64/IA64InstrInfo.td:1.40 Thu Jan 19 09:18:56 2006 +++ llvm/lib/Target/IA64/IA64InstrInfo.td Thu Jan 19 21:40:25 2006 @@ -113,10 +113,6 @@ adds $dst = $imm, $src1;;, [(set GR:$dst, (add GR:$src1, immSExt14:$imm))]; -def PADDS: AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm, PR:$qp), - ($qp) adds $dst = $imm, $src1;;, - []; - def MOVL : AForm_DAG0x03, 0x0b, (ops GR:$dst, s64imm:$imm), movl $dst = $imm;;, [(set GR:$dst, imm64:$imm)]; @@ -142,9 +138,10 @@ def TPCADDIMM22 : AForm0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp), ($qp) add $dst = $imm, $dst;;; -def TPCADDS : AForm0x03, 0x0b, +def TPCADDS : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm, PR:$qp), -($qp) adds $dst = $imm, $dst;;; +($qp) adds $dst = $imm, $dst;;, +[]; def TPCMPIMM8NE : AForm0x03, 0x0b, (ops PR:$dst, PR:$src1, s22imm:$imm, GR:$src2, PR:$qp), ($qp) cmp.ne $dst , p0 = $imm, $src2;;; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.22 - 1.23
---
Log message:
fixing divides: FP should now be 100%, and integers are fine too
unless you try to div/mod 0 by anything, in which case you will
get some cute number, and not 0, which is bad.
---
Diffs of the changes: (+24 -17)
IA64ISelDAGToDAG.cpp | 41 -
1 files changed, 24 insertions(+), 17 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.22
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.23
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.22 Mon Jan 16 00:33:38 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Mon Jan 16 08:33:04 2006
@@ -183,6 +183,10 @@
SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
SDOperand Result;
+
+// we'll need copies of F0 and F1
+SDOperand F0 = CurDAG-getRegister(IA64::F0, MVT::f64);
+SDOperand F1 = CurDAG-getRegister(IA64::F1, MVT::f64);
// OK, emit some code:
@@ -200,12 +204,10 @@
TmpF4 = CurDAG-getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2);
Chain = TmpF4.getValue(1);
} else { // is unsigned
-if(isModulus) { /* unsigned integer divides do not need any fcvt.x*f*
insns */
- TmpF3 = CurDAG-getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1);
- Chain = TmpF3.getValue(1);
- TmpF4 = CurDAG-getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2);
- Chain = TmpF4.getValue(1);
-}
+TmpF3 = CurDAG-getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1);
+Chain = TmpF3.getValue(1);
+TmpF4 = CurDAG-getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2);
+Chain = TmpF4.getValue(1);
}
} else { // this is an FP divide/remainder, so we 'leak' some temp
@@ -226,10 +228,6 @@
TmpPR = TmpF5.getValue(1);
Chain = TmpF5.getValue(2);
-// we'll need copies of F0 and F1
-SDOperand F0 = CurDAG-getRegister(IA64::F0, MVT::f64);
-SDOperand F1 = CurDAG-getRegister(IA64::F1, MVT::f64);
-
SDOperand minusB;
if(isModulus) { // for remainders, it'll be handy to have
// copies of -input_b
@@ -276,7 +274,7 @@
// we two-address hack it. See the comment for this to work... on
// page 48 of Intel application note #245415
Result = CurDAG-getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
-TmpY3, TmpR0, TmpQ0, TmpPR);
+TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR);
Chain = Result.getValue(1);
return Result; // XXX: early exit!
} else { // this is *not* an FP divide, so there's a bit left to do:
@@ -290,13 +288,22 @@
TmpF4, TmpQ2, TmpF3, TmpPR);
Chain = TmpR2.getValue(1);
-// we want TmpQ3 to have the same target register as the frcpa, so
-// we two-address hack it. See the comment for this to work... on
-// page 48 of Intel application note #245415
- TmpQ3 = CurDAG-getTargetNode(IA64::TCFMAS1, MVT::f64,
-TmpR2, TmpR2, TmpY2, TmpQ2, TmpPR);
+// we want TmpQ3 to have the same target register as the frcpa? maybe we
+// should two-address hack it. See the comment for this to work... on page
+// 48 of Intel application note #245415
+ TmpQ3 = CurDAG-getTargetNode(IA64::CFMAS1, MVT::f64,
+TmpR2, TmpY2, TmpQ2, TmpPR);
Chain = TmpQ3.getValue(1);
-
+
+ // FIXME: this is unfortunate :(
+ // the story is that the dest reg of the fnma above and the fma below it
+ // (and therefore the src of the fcvt.fx[u] below as well) cannot
+ // be the same register, or this code breaks if the first argument is
+ // zero. (e.g. without this hack, 0%8 yields -64, not 0.)
+/* XXX: these two lines do nothing */
+ SDOperand bogus = CurDAG-getTargetNode(IA64::IUSE, MVT::Other, TmpR2);
+ Chain = bogus.getValue(0);
+
if(isSigned)
TmpQ = CurDAG-getTargetNode(IA64::FCVTFXTRUNCS1, MVT::f64, TmpQ3);
else
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.23 - 1.24
---
Log message:
fixing divides
---
Diffs of the changes: (+9 -12)
IA64ISelDAGToDAG.cpp | 21 +
1 files changed, 9 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.23
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.24
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.23 Mon Jan 16 08:33:04 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Mon Jan 16 19:19:49 2006
@@ -228,6 +228,8 @@
TmpPR = TmpF5.getValue(1);
Chain = TmpF5.getValue(2);
+Chain = CurDAG-getCopyToReg(Chain, IA64::F8, TmpF5);
+
SDOperand minusB;
if(isModulus) { // for remainders, it'll be handy to have
// copies of -input_b
@@ -287,23 +289,18 @@
TmpR2 = CurDAG-getTargetNode(IA64::CFNMAS1, MVT::f64,
TmpF4, TmpQ2, TmpF3, TmpPR);
Chain = TmpR2.getValue(1);
-
+
// we want TmpQ3 to have the same target register as the frcpa? maybe we
// should two-address hack it. See the comment for this to work... on page
// 48 of Intel application note #245415
- TmpQ3 = CurDAG-getTargetNode(IA64::CFMAS1, MVT::f64,
-TmpR2, TmpY2, TmpQ2, TmpPR);
+ TmpQ3 = CurDAG-getTargetNode(IA64::TCFMAS1, MVT::f64,
+TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR);
Chain = TmpQ3.getValue(1);
- // FIXME: this is unfortunate :(
- // the story is that the dest reg of the fnma above and the fma below it
- // (and therefore the src of the fcvt.fx[u] below as well) cannot
- // be the same register, or this code breaks if the first argument is
- // zero. (e.g. without this hack, 0%8 yields -64, not 0.)
-/* XXX: these two lines do nothing */
- SDOperand bogus = CurDAG-getTargetNode(IA64::IUSE, MVT::Other, TmpR2);
- Chain = bogus.getValue(0);
-
+ // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
+ // the FPSWA won't be able to help out in the case of large/tiny
+ // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
+
if(isSigned)
TmpQ = CurDAG-getTargetNode(IA64::FCVTFXTRUNCS1, MVT::f64, TmpQ3);
else
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td IA64RegisterInfo.cpp IA64RegisterInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64InstrInfo.td updated: 1.38 - 1.39
IA64RegisterInfo.cpp updated: 1.9 - 1.10
IA64RegisterInfo.td updated: 1.12 - 1.13
---
Log message:
use proper (82-bit) spills/fills when spilling FP regs, so that
divides don't get broken. this fixes obsequi, smg2000, and probably
a bunch of other stuff (tm)
---
Diffs of the changes: (+11 -3)
IA64InstrInfo.td |4
IA64RegisterInfo.cpp |4 ++--
IA64RegisterInfo.td |6 +-
3 files changed, 11 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.38
llvm/lib/Target/IA64/IA64InstrInfo.td:1.39
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.38 Mon Jan 16 00:33:38 2006
+++ llvm/lib/Target/IA64/IA64InstrInfo.td Mon Jan 16 20:04:52 2006
@@ -537,6 +537,8 @@
stfs [$dstPtr] = $value;;;
def STF8 : AForm0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
stfd [$dstPtr] = $value;;;
+ def STF_SPILL : AForm0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
+stf.spill [$dstPtr] = $value;;;
}
let isLoad = 1 in {
@@ -552,6 +554,8 @@
ldfs $dst = [$srcPtr];;;
def LDF8 : AForm0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
ldfd $dst = [$srcPtr];;;
+ def LDF_FILL : AForm0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
+ldf.fill $dst = [$srcPtr];;;
}
def POPCNT : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src),
Index: llvm/lib/Target/IA64/IA64RegisterInfo.cpp
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.9
llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.10
--- llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.9 Thu Oct 27 23:58:24 2005
+++ llvm/lib/Target/IA64/IA64RegisterInfo.cpp Mon Jan 16 20:04:52 2006
@@ -40,7 +40,7 @@
const TargetRegisterClass *RC)
const{
if (RC == IA64::FPRegisterClass) {
-BuildMI(MBB, MI, IA64::STF8, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
+BuildMI(MBB, MI, IA64::STF_SPILL,
2).addFrameIndex(FrameIdx).addReg(SrcReg);
} else if (RC == IA64::GRRegisterClass) {
BuildMI(MBB, MI, IA64::ST8, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
}
@@ -63,7 +63,7 @@
const TargetRegisterClass
*RC)const{
if (RC == IA64::FPRegisterClass) {
-BuildMI(MBB, MI, IA64::LDF8, 1, DestReg).addFrameIndex(FrameIdx);
+BuildMI(MBB, MI, IA64::LDF_FILL, 1, DestReg).addFrameIndex(FrameIdx);
} else if (RC == IA64::GRRegisterClass) {
BuildMI(MBB, MI, IA64::LD8, 1, DestReg).addFrameIndex(FrameIdx);
} else if (RC == IA64::PRRegisterClass) {
Index: llvm/lib/Target/IA64/IA64RegisterInfo.td
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.td:1.12
llvm/lib/Target/IA64/IA64RegisterInfo.td:1.13
--- llvm/lib/Target/IA64/IA64RegisterInfo.td:1.12 Wed Dec 21 21:56:03 2005
+++ llvm/lib/Target/IA64/IA64RegisterInfo.tdMon Jan 16 20:04:52 2006
@@ -282,7 +282,11 @@
// these are the scratch (+stacked) FP registers
-def FP : RegisterClassIA64, [f64], 64,
+
+// the 128 here is to make stf.spill/ldf.fill happy,
+// when storing full (82-bit) FP regs to stack slots
+// we need to 16-byte align
+def FP : RegisterClassIA64, [f64], 128,
[F6, F7,
F8, F9, F10, F11, F12, F13, F14, F15,
F32, F33, F34, F35, F36, F37, F38, F39,
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.20 - 1.21
IA64ISelLowering.cpp updated: 1.21 - 1.22
---
Log message:
explain that r12 is the stack pointer reg
---
Diffs of the changes: (+5 -33)
IA64ISelDAGToDAG.cpp | 34 ++
IA64ISelLowering.cpp |4 +++-
2 files changed, 5 insertions(+), 33 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.20
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.21
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.20 Fri Jan 13 04:28:25 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sun Jan 15 03:45:22 2006
@@ -450,37 +450,6 @@
case ISD::SREM:
case ISD::UREM: return SelectDIV(Op);
- case ISD::DYNAMIC_STACKALLOC: {
-if (!isaConstantSDNode(N-getOperand(2)) ||
-castConstantSDNode(N-getOperand(2))-getValue() != 0) {
- std::cerr Cannot allocate stack object with greater alignment than
- the stack alignment yet!;
- abort();
-}
-
-SDOperand Chain = Select(N-getOperand(0));
-SDOperand Amt = Select(N-getOperand(1));
-SDOperand Reg = CurDAG-getRegister(IA64::r12, MVT::i64);
-SDOperand Val = CurDAG-getCopyFromReg(Chain, IA64::r12, MVT::i64);
-Chain = Val.getValue(1);
-
-// Subtract the amount (guaranteed to be a multiple of the stack alignment)
-// from the stack pointer, giving us the result pointer.
-SDOperand Result = Select(CurDAG-getNode(ISD::SUB, MVT::i64, Val, Amt));
-
-// Copy this result back into r12.
-Chain = CurDAG-getNode(ISD::CopyToReg, MVT::Other, Chain, Reg, Result);
-
-// Copy this result back out of r12 to make sure we're not using the stack
-// space without decrementing the stack pointer.
-Result = CurDAG-getCopyFromReg(Chain, IA64::r12, MVT::i64);
-
-// Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
-CodeGenMap[Op.getValue(0)] = Result;
-CodeGenMap[Op.getValue(1)] = Result.getValue(1);
-return SDOperand(Result.Val, Op.ResNo);
- }
-
case ISD::ConstantFP: {
SDOperand Chain = CurDAG-getEntryNode(); // this is a constant, so..
@@ -501,7 +470,8 @@
CurDAG-getTargetFrameIndex(FI, MVT::i64));
}
- case ISD::ConstantPool: {
+ case ISD::ConstantPool: { // TODO: nuke the constant pool
+ // (ia64 doesn't need one)
Constant *C = castConstantPoolSDNode(N)-get();
SDOperand CPI = CurDAG-getTargetConstantPool(C, MVT::i64);
return CurDAG-getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.21
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.22
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.21 Sat Jan 14 16:27:21 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Sun Jan 15 03:45:23 2006
@@ -84,9 +84,11 @@
setOperationAction(ISD::ROTR , MVT::i64 , Expand);
setOperationAction(ISD::BSWAP, MVT::i64 , Expand); // mux @rev
- // Not implemented yet.
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
+
+ setStackPointerRegisterToSaveRestore(IA64::r12);
computeRegisterProperties();
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.19 - 1.20
---
Log message:
don't be a doofus - this fixes storing bools
---
Diffs of the changes: (+5 -2)
IA64ISelDAGToDAG.cpp |7 +--
1 files changed, 5 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.19
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.20
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.19 Wed Jan 11 13:53:22 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Fri Jan 13 04:28:25 2006
@@ -571,9 +571,12 @@
default: assert(0 unknown type in store);
case MVT::i1: { // this is a bool
Opc = IA64::ST1; // we store either 0 or 1 as a byte
+ // first load zero!
+ SDOperand Initial = CurDAG-getCopyFromReg(Chain, IA64::r0, MVT::i64);
+ Chain = Initial.getValue(1);
+ // then load 1 iff the predicate to store is 1
SDOperand Tmp =
- CurDAG-getTargetNode(IA64::PADDS, MVT::i64,
-CurDAG-getRegister(IA64::r0, MVT::i64),
+ CurDAG-getTargetNode(IA64::PADDS, MVT::i64, Initial,
CurDAG-getConstant(1, MVT::i64),
Select(N-getOperand(1)));
return CurDAG-SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelLowering.cpp updated: 1.17 - 1.18
---
Log message:
sabre's (correct) fix means these guys need to be flagged as well (else
the scheduler will complain)
---
Diffs of the changes: (+7 -2)
IA64ISelLowering.cpp |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.17
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.18
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.17 Wed Jan 11 19:33:08 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Wed Jan 11 21:28:40 2006
@@ -392,11 +392,12 @@
// know this is required (i.e. for varardic or external (unknown) functions)
// first to the FP-(integer representation) conversions, these are
- // free-floating
+ // flagged for now, but shouldn't have to be (TODO)
unsigned seenConverts = 0;
for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
if(MVT::isFloatingPoint(RegValuesToPass[i].getValueType())) {
- Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Converts[seenConverts++]);
+ Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Converts[seenConverts++],
InFlag);
+ InFlag = Chain.getValue(1);
}
}
@@ -428,6 +429,8 @@
// emit the call itself
if (InFlag.Val)
CallOperands.push_back(InFlag);
+ else
+assert(0 this should never happen!\n);
/* out with the old...
Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0);
@@ -480,10 +483,12 @@
case MVT::i64:
RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
Chain = RetVal.getValue(1);
+ InFlag = RetVal.getValue(2); // XXX dead
break;
case MVT::f64:
RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
Chain = RetVal.getValue(1);
+ InFlag = RetVal.getValue(2); // XXX dead
break;
}
}
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.35 - 1.36 --- Log message: add support for selecting bools FIXME: this is commented out because it makes tblgen go a bit fruity --- Diffs of the changes: (+5 -1) IA64InstrInfo.td |6 +- 1 files changed, 5 insertions(+), 1 deletion(-) Index: llvm/lib/Target/IA64/IA64InstrInfo.td diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.35 llvm/lib/Target/IA64/IA64InstrInfo.td:1.36 --- llvm/lib/Target/IA64/IA64InstrInfo.td:1.35 Mon Dec 26 03:11:45 2005 +++ llvm/lib/Target/IA64/IA64InstrInfo.td Tue Jan 10 19:21:12 2006 @@ -424,11 +424,15 @@ ($qp) mov $dst = $src;;; } -// TODO: select bools def SELECTINT : Pat(select PR:$which, GR:$src1, GR:$src2), (CMOV (MOV GR:$src2), GR:$src1, PR:$which); // note order! def SELECTFP : Pat(select PR:$which, FP:$src1, FP:$src2), (CFMOV (FMOV FP:$src2), FP:$src1, PR:$which); // note order! +// TODO: can do this faster, w/o using any integer regs (see pattern isel) +// FIXME: this makes tblgen cough and splutter: +// Assertion Unknown node in result pattern!' +//def SELECTBOOL : Pat(select PR:$which, PR:$src1, PR:$src2), // note order! +// (trunc (CMOV (MOV (zext PR:$src2)), (zext PR:$src1), PR:$which)); // load constants of various sizes // FIXME: prettyprint -ve constants def : Pat(i64 immSExt14:$imm), (ADDS r0, immSExt14:$imm); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.17 - 1.18
---
Log message:
cleanup GETFD
---
Diffs of the changes: (+3 -4)
IA64ISelDAGToDAG.cpp |7 +++
1 files changed, 3 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.17
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.18
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.17 Sun Dec 25 08:09:08 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Tue Jan 10 21:50:40 2006
@@ -411,10 +411,9 @@
case IA64ISD::GETFD: {
SDOperand Input = Select(N-getOperand(0));
-SDOperand Result = CurDAG-getTargetNode(IA64::GETFD, MVT::i64, MVT::Flag,
Input);
-CodeGenMap[Op.getValue(0)] = Result;
-CodeGenMap[Op.getValue(1)] = Result.getValue(1);
-return Result.getValue(Op.ResNo);
+SDOperand Result = CurDAG-getTargetNode(IA64::GETFD, MVT::i64, Input);
+CodeGenMap[Op] = Result;
+return Result;
}
case ISD::CALL:
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelLowering.cpp updated: 1.12 - 1.13
---
Log message:
support functions that return bool (this should work but doesn't,
*maybe* due to a legalizer bug.)
---
Diffs of the changes: (+10 -10)
IA64ISelLowering.cpp | 20 ++--
1 files changed, 10 insertions(+), 10 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.12
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.13
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.12 Fri Jan 6 11:56:38 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Mon Jan 9 23:08:25 2006
@@ -452,18 +452,18 @@
SDOperand RetVal;
if (RetTyVT != MVT::isVoid) {
switch (RetTyVT) {
-default: assert(0 Unknown value type to return!);
-case MVT::i1:/* { // bools are just like other integers (returned in r8)
+default: // assert(0 Unknown value type to return!);
+case MVT::i1: { // bools are just like other integers (returned in r8)
SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64,
InFlag);
- RetVal = DAG.getTargetNode(IA64::CMPNE, MVT::i1, // FIXME: is this
flagged correctly?
-DAG.getRegister(IA64::r0, MVT::i64), boolInR8, Chain, InFlag);
- Chain = RetVal.getValue(1);
- // Add a note to keep track of whether it is sign or zero extended -
TODO: bools
- RetVal = DAG.getNode(RetTy-isSigned() ? ISD::AssertSext
:ISD::AssertZext,
- MVT::i64, RetVal, DAG.getValueType(RetTyVT));
- RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
+ InFlag = boolInR8.getValue(2);
+ Chain = boolInR8.getValue(1);
+ SDOperand zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64,
InFlag);
+ InFlag = zeroReg.getValue(2);
+ Chain = zeroReg.getValue(1);
+
+ RetVal = DAG.getNode(ISD::SETNE, MVT::i1, boolInR8, zeroReg);
break;
-}*/
+}
case MVT::i8:
case MVT::i16:
case MVT::i32:
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelLowering.cpp updated: 1.8 - 1.9
---
Log message:
nasty paste-o, calls passing more than 8 arguments along were having
args 8 put into the wrong place
---
Diffs of the changes: (+2 -2)
IA64ISelLowering.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.8
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.9
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.8 Thu Dec 22 07:29:14 2005
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Tue Dec 27 04:17:03 2005
@@ -347,12 +347,12 @@
PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff);
Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
ValToStore, PtrOff, NullSV));
+ArgOffset += ObjSize;
}
if(ValToConvert.Val) {
Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64,
ValToConvert));
}
- ArgOffset += ObjSize;
}
// Emit all stores, make sure they occur before any copies into physregs.
@@ -397,7 +397,7 @@
}
}
- // next copy args into the usual places
+ // next copy args into the usual places, these are flagged
unsigned usedFPArgs = 0;
for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
Chain = DAG.getCopyToReg(Chain,
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[llvm-commits] CVS: llvm/lib/Target/CBackend/Writer.cpp
Changes in directory llvm/lib/Target/CBackend: Writer.cpp updated: 1.249 - 1.250 --- Log message: yet more C++ standards-compliance stuff. --- Diffs of the changes: (+1 -0) Writer.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/CBackend/Writer.cpp diff -u llvm/lib/Target/CBackend/Writer.cpp:1.249 llvm/lib/Target/CBackend/Writer.cpp:1.250 --- llvm/lib/Target/CBackend/Writer.cpp:1.249 Thu Nov 10 15:39:29 2005 +++ llvm/lib/Target/CBackend/Writer.cpp Tue Dec 27 04:40:34 2005 @@ -39,6 +39,7 @@ #include llvm/Config/config.h #include algorithm #include iostream +#include ios #include sstream using namespace llvm; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/MachineCodeEmitter.cpp
Changes in directory llvm/lib/CodeGen: MachineCodeEmitter.cpp updated: 1.24 - 1.25 --- Log message: mixed-STL programs are big and nasty :( --- Diffs of the changes: (+1 -0) MachineCodeEmitter.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/CodeGen/MachineCodeEmitter.cpp diff -u llvm/lib/CodeGen/MachineCodeEmitter.cpp:1.24 llvm/lib/CodeGen/MachineCodeEmitter.cpp:1.25 --- llvm/lib/CodeGen/MachineCodeEmitter.cpp:1.24Thu Jul 28 13:13:59 2005 +++ llvm/lib/CodeGen/MachineCodeEmitter.cpp Tue Dec 27 20:44:35 2005 @@ -16,6 +16,7 @@ #include llvm/Function.h #include fstream #include iostream +#include ios using namespace llvm; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/RegAllocLinearScan.cpp
Changes in directory llvm/lib/CodeGen:
RegAllocLinearScan.cpp updated: 1.116 - 1.117
---
Log message:
HB is *the* code janitor.
---
Diffs of the changes: (+1 -0)
RegAllocLinearScan.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/CodeGen/RegAllocLinearScan.cpp
diff -u llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.116
llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.117
--- llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.116 Mon Nov 21 08:09:40 2005
+++ llvm/lib/CodeGen/RegAllocLinearScan.cpp Tue Dec 27 22:55:42 2005
@@ -30,6 +30,7 @@
#include cmath
#include set
#include queue
+#include memory
using namespace llvm;
namespace {
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[llvm-commits] CVS: llvm/tools/llc/llc.cpp
Changes in directory llvm/tools/llc:
llc.cpp updated: 1.119 - 1.120
---
Log message:
WAKEY WAKEY
---
Diffs of the changes: (+1 -1)
llc.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/tools/llc/llc.cpp
diff -u llvm/tools/llc/llc.cpp:1.119 llvm/tools/llc/llc.cpp:1.120
--- llvm/tools/llc/llc.cpp:1.119Thu Dec 15 23:19:55 2005
+++ llvm/tools/llc/llc.cpp Tue Dec 27 23:48:55 2005
@@ -243,7 +243,7 @@
' does not support generation of this file type!\n;
if (Out != std::cout) delete Out;
// And the Out file is empty and useless, so remove it now.
- std::remove(OutputFilename.c_str());
+ remove(OutputFilename.c_str());
return 1;
} else {
// Run our queue of passes all at once now, efficiently.
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineConstantPool.h
Changes in directory llvm/include/llvm/CodeGen:
MachineConstantPool.h updated: 1.7 - 1.8
---
Log message:
undo yuletide naughtyness(tm)
---
Diffs of the changes: (+0 -1)
MachineConstantPool.h |1 -
1 files changed, 1 deletion(-)
Index: llvm/include/llvm/CodeGen/MachineConstantPool.h
diff -u llvm/include/llvm/CodeGen/MachineConstantPool.h:1.7
llvm/include/llvm/CodeGen/MachineConstantPool.h:1.8
--- llvm/include/llvm/CodeGen/MachineConstantPool.h:1.7 Mon Dec 26 04:34:38 2005
+++ llvm/include/llvm/CodeGen/MachineConstantPool.h Wed Dec 28 00:29:38 2005
@@ -22,7 +22,6 @@
#ifndef LLVM_CODEGEN_MACHINECONSTANTPOOL_H
#define LLVM_CODEGEN_MACHINECONSTANTPOOL_H
-#include iostream
#include vector
namespace llvm {
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineConstantPool.h
Changes in directory llvm/include/llvm/CodeGen:
MachineConstantPool.h updated: 1.8 - 1.9
---
Log message:
be more polite in public headers
---
Diffs of the changes: (+1 -0)
MachineConstantPool.h |1 +
1 files changed, 1 insertion(+)
Index: llvm/include/llvm/CodeGen/MachineConstantPool.h
diff -u llvm/include/llvm/CodeGen/MachineConstantPool.h:1.8
llvm/include/llvm/CodeGen/MachineConstantPool.h:1.9
--- llvm/include/llvm/CodeGen/MachineConstantPool.h:1.8 Wed Dec 28 00:29:38 2005
+++ llvm/include/llvm/CodeGen/MachineConstantPool.h Wed Dec 28 00:47:33 2005
@@ -23,6 +23,7 @@
#define LLVM_CODEGEN_MACHINECONSTANTPOOL_H
#include vector
+#include iosfwd
namespace llvm {
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[llvm-commits] CVS: llvm/lib/VMCore/Dominators.cpp
Changes in directory llvm/lib/VMCore: Dominators.cpp updated: 1.64 - 1.65 --- Log message: more HP-UX cleanliness --- Diffs of the changes: (+1 -0) Dominators.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/VMCore/Dominators.cpp diff -u llvm/lib/VMCore/Dominators.cpp:1.64 llvm/lib/VMCore/Dominators.cpp:1.65 --- llvm/lib/VMCore/Dominators.cpp:1.64 Fri Nov 18 01:27:53 2005 +++ llvm/lib/VMCore/Dominators.cpp Mon Dec 26 02:35:06 2005 @@ -20,6 +20,7 @@ #include llvm/ADT/DepthFirstIterator.h #include llvm/ADT/SetOperations.h #include algorithm +#include iostream using namespace llvm; //===--===// ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Linker.h
Changes in directory llvm/include/llvm:
Linker.h updated: 1.16 - 1.17
---
Log message:
more standards compliance (damn, I can't wait for unordered_set (tee hee)
and unordered_map to make it into the standard)
Hurry up, JTC1 SC22 WG21 Library Working Group!
---
Diffs of the changes: (+1 -0)
Linker.h |1 +
1 files changed, 1 insertion(+)
Index: llvm/include/llvm/Linker.h
diff -u llvm/include/llvm/Linker.h:1.16 llvm/include/llvm/Linker.h:1.17
--- llvm/include/llvm/Linker.h:1.16 Tue Dec 13 14:00:37 2005
+++ llvm/include/llvm/Linker.h Mon Dec 26 07:34:00 2005
@@ -16,6 +16,7 @@
#include llvm/System/Path.h
#include vector
+#include memory
namespace llvm {
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/LowerPacked.cpp
Changes in directory llvm/lib/Transforms/Scalar: LowerPacked.cpp updated: 1.5 - 1.6 --- Log message: getting there... --- Diffs of the changes: (+1 -0) LowerPacked.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Transforms/Scalar/LowerPacked.cpp diff -u llvm/lib/Transforms/Scalar/LowerPacked.cpp:1.5 llvm/lib/Transforms/Scalar/LowerPacked.cpp:1.6 --- llvm/lib/Transforms/Scalar/LowerPacked.cpp:1.5 Thu Apr 21 18:45:12 2005 +++ llvm/lib/Transforms/Scalar/LowerPacked.cpp Mon Dec 26 07:48:44 2005 @@ -24,6 +24,7 @@ #include algorithm #include map #include iostream +#include functional using namespace llvm; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Bytecode/Reader/Analyzer.cpp ReaderWrappers.cpp
Changes in directory llvm/lib/Bytecode/Reader: Analyzer.cpp updated: 1.20 - 1.21 ReaderWrappers.cpp updated: 1.52 - 1.53 --- Log message: I bet pinski knows why g++ accepts this stuff --- Diffs of the changes: (+3 -0) Analyzer.cpp |1 + ReaderWrappers.cpp |2 ++ 2 files changed, 3 insertions(+) Index: llvm/lib/Bytecode/Reader/Analyzer.cpp diff -u llvm/lib/Bytecode/Reader/Analyzer.cpp:1.20 llvm/lib/Bytecode/Reader/Analyzer.cpp:1.21 --- llvm/lib/Bytecode/Reader/Analyzer.cpp:1.20 Thu May 5 17:32:13 2005 +++ llvm/lib/Bytecode/Reader/Analyzer.cpp Mon Dec 26 08:23:22 2005 @@ -25,6 +25,7 @@ #include llvm/Assembly/Writer.h #include iomanip #include sstream +#include ios using namespace llvm; Index: llvm/lib/Bytecode/Reader/ReaderWrappers.cpp diff -u llvm/lib/Bytecode/Reader/ReaderWrappers.cpp:1.52 llvm/lib/Bytecode/Reader/ReaderWrappers.cpp:1.53 --- llvm/lib/Bytecode/Reader/ReaderWrappers.cpp:1.52Sat Oct 22 23:37:20 2005 +++ llvm/lib/Bytecode/Reader/ReaderWrappers.cpp Mon Dec 26 08:23:22 2005 @@ -21,6 +21,8 @@ #include llvm/System/MappedFile.h #include cerrno #include iostream +#include memory + using namespace llvm; //===--===// ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Bytecode/Archive/ArchiveReader.cpp
Changes in directory llvm/lib/Bytecode/Archive: ArchiveReader.cpp updated: 1.42 - 1.43 --- Log message: more C++ daintiness --- Diffs of the changes: (+1 -0) ArchiveReader.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Bytecode/Archive/ArchiveReader.cpp diff -u llvm/lib/Bytecode/Archive/ArchiveReader.cpp:1.42 llvm/lib/Bytecode/Archive/ArchiveReader.cpp:1.43 --- llvm/lib/Bytecode/Archive/ArchiveReader.cpp:1.42Fri Sep 23 01:22:58 2005 +++ llvm/lib/Bytecode/Archive/ArchiveReader.cpp Mon Dec 26 08:31:26 2005 @@ -13,6 +13,7 @@ #include ArchiveInternals.h #include llvm/Bytecode/Reader.h +#include memory using namespace llvm; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64: IA64ISelDAGToDAG.cpp updated: 1.16 - 1.17 --- Log message: unbreak calls, a few more tests should run. Tomorrow: bugpoint! --- Diffs of the changes: (+1 -2) IA64ISelDAGToDAG.cpp |3 +-- 1 files changed, 1 insertion(+), 2 deletions(-) Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.16 llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.17 --- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.16 Thu Dec 22 07:29:14 2005 +++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sun Dec 25 08:09:08 2005 @@ -352,7 +352,6 @@ unsigned CallOpcode; SDOperand CallOperand; -std::vectorMVT::ValueType TypeOperands; // if we can call directly, do so if (GlobalAddressSDNode *GASD = @@ -395,7 +394,7 @@ // Finally, once everything is setup, emit the call itself if(InFlag.Val) - Chain = CurDAG-getTargetNode(CallOpcode, MVT::Other, MVT::Flag, CallOperand, Chain, InFlag); + Chain = CurDAG-getTargetNode(CallOpcode, MVT::Other, MVT::Flag, CallOperand, InFlag); else // there might be no arguments Chain = CurDAG-getTargetNode(CallOpcode, MVT::Other, MVT::Flag, CallOperand, Chain); InFlag = Chain.getValue(1); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Support/CommandLine.cpp
Changes in directory llvm/lib/Support: CommandLine.cpp updated: 1.64 - 1.65 --- Log message: MERRY CHRISTMAS EVERYONE!!! (what better way to spend christmas than to try building LLVM on HP-UX! (the Right Way seems to be to tear out the ancient STL that HP ship and use http://incubator.apache.org/stdcxx/ ) --- Diffs of the changes: (+1 -0) CommandLine.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Support/CommandLine.cpp diff -u llvm/lib/Support/CommandLine.cpp:1.64 llvm/lib/Support/CommandLine.cpp:1.65 --- llvm/lib/Support/CommandLine.cpp:1.64 Wed Nov 16 00:36:47 2005 +++ llvm/lib/Support/CommandLine.cppSun Dec 25 22:56:16 2005 @@ -19,6 +19,7 @@ #include llvm/Config/config.h #include llvm/Support/CommandLine.h #include algorithm +#include functional #include map #include set #include iostream ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Support/bzip2/Makefile
Changes in directory llvm/lib/Support/bzip2: Makefile updated: 1.3 - 1.4 --- Log message: HP aCC chokes on this, but it's not required anyway: according to the bzip2 homepage, only ancient (gcc 2.7.x ?) versions of GCC require this? It certainly isn't needed for the current bzip2 sources. --- Diffs of the changes: (+0 -2) Makefile |2 -- 1 files changed, 2 deletions(-) Index: llvm/lib/Support/bzip2/Makefile diff -u llvm/lib/Support/bzip2/Makefile:1.3 llvm/lib/Support/bzip2/Makefile:1.4 --- llvm/lib/Support/bzip2/Makefile:1.3 Sat Dec 4 16:34:21 2004 +++ llvm/lib/Support/bzip2/Makefile Sun Dec 25 23:00:25 2005 @@ -13,6 +13,4 @@ EXTRA_DIST = bzlib.h bzlib_private.h CHANGES LICENSE README \ README.COMPILATION.PROBLEMS Y2K_INFO -CFLAGS=-fno-strength-reduce - include $(LEVEL)/Makefile.common ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/utils/TableGen/TableGen.cpp Record.cpp
Changes in directory llvm/utils/TableGen:
TableGen.cpp updated: 1.41 - 1.42
Record.cpp updated: 1.48 - 1.49
---
Log message:
more standards-compliance stuff
---
Diffs of the changes: (+3 -0)
Record.cpp |2 ++
TableGen.cpp |1 +
2 files changed, 3 insertions(+)
Index: llvm/utils/TableGen/TableGen.cpp
diff -u llvm/utils/TableGen/TableGen.cpp:1.41
llvm/utils/TableGen/TableGen.cpp:1.42
--- llvm/utils/TableGen/TableGen.cpp:1.41 Sun Oct 23 00:47:52 2005
+++ llvm/utils/TableGen/TableGen.cppSun Dec 25 23:08:55 2005
@@ -28,6 +28,7 @@
#include algorithm
#include cstdio
#include fstream
+#include ios
using namespace llvm;
enum ActionType {
Index: llvm/utils/TableGen/Record.cpp
diff -u llvm/utils/TableGen/Record.cpp:1.48 llvm/utils/TableGen/Record.cpp:1.49
--- llvm/utils/TableGen/Record.cpp:1.48 Wed Nov 30 12:37:14 2005
+++ llvm/utils/TableGen/Record.cpp Sun Dec 25 23:08:55 2005
@@ -12,6 +12,8 @@
#include Record.h
#include llvm/Support/DataTypes.h
+#include ios
+
using namespace llvm;
//===--===//
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64.td IA64InstrInfo.td IA64RegisterInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64.td updated: 1.3 - 1.4
IA64InstrInfo.td updated: 1.30 - 1.31
IA64RegisterInfo.td updated: 1.11 - 1.12
---
Log message:
update tablegen files - nothing to see here
---
Diffs of the changes: (+18 -6)
IA64.td |1 +
IA64InstrInfo.td| 19 +++
IA64RegisterInfo.td |4 ++--
3 files changed, 18 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/IA64/IA64.td
diff -u llvm/lib/Target/IA64/IA64.td:1.3 llvm/lib/Target/IA64/IA64.td:1.4
--- llvm/lib/Target/IA64/IA64.td:1.3Fri Sep 30 01:42:24 2005
+++ llvm/lib/Target/IA64/IA64.tdWed Dec 21 21:56:03 2005
@@ -47,6 +47,7 @@
// r1, // global data pointer (GP) - XXX NOT callee saved, we do it ourselves
// r12, // memory stack pointer (SP)- XXX NOT callee saved, we do it ourselves
+// rp, // return branch register (rp/b0) - we do this ourselves
// r13 (thread pointer) we do not touch, ever. it's not here. //
//r15, // our frame pointer (FP)
Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.30
llvm/lib/Target/IA64/IA64InstrInfo.td:1.31
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.30 Sun Dec 4 20:34:29 2005
+++ llvm/lib/Target/IA64/IA64InstrInfo.td Wed Dec 21 21:56:03 2005
@@ -23,7 +23,7 @@
def s14imm : Operandi64 {
let PrintMethod = printS14ImmOperand;
}
-def s22imm : Operandi32 {
+def s22imm : Operandi64 {
let PrintMethod = printS22ImmOperand;
}
def u64imm : Operandi64 {
@@ -116,7 +116,12 @@
def ADDL_GA : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1,
globaladdress:$imm),
addl $dst = $imm, $src1;;,
[];
-
+
+// hmm
+def ADDL_EA : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, calltarget:$imm),
+ addl $dst = $imm, $src1;;,
+ [];
+
def SUB : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
sub $dst = $src1, $src2;;,
[(set GR:$dst, (sub GR:$src1, GR:$src2))];
@@ -639,7 +644,7 @@
($qp) br.cond.sptk $dst;;;
}
-let isCall = 1, isTerminator = 1, isBranch = 1,
+let isCall = 1, /* isTerminator = 1, isBranch = 1, */
Uses = [out0,out1,out2,out3,out4,out5,out6,out7],
// all calls clobber non-callee-saved registers, and for now, they are these:
Defs = [r2,r3,r8,r9,r10,r11,r14,r15,r16,r17,r18,r19,r20,r21,r22,r23,r24,
@@ -659,8 +664,14 @@
def BRCALL: RawForm0x03, 0xb0, (ops calltarget:$dst),
br.call.sptk rp = $dst;;; // FIXME: teach llvm about branch regs?
// new daggy stuff!
- def BRCALL_IPREL : RawForm0x03, 0xb0, (ops calltarget:$dst, variable_ops),
+
+// calls a globaladdress
+ def BRCALL_IPREL_GA : RawForm0x03, 0xb0, (ops calltarget:$dst,
variable_ops),
+ br.call.sptk rp = $dst;;; // FIXME: teach llvm about branch regs?
+// calls an externalsymbol
+ def BRCALL_IPREL_ES : RawForm0x03, 0xb0, (ops calltarget:$dst,
variable_ops),
br.call.sptk rp = $dst;;; // FIXME: teach llvm about branch regs?
+// calls through a function descriptor
def BRCALL_INDIRECT : RawForm0x03, 0xb0, (ops GR:$branchreg, variable_ops),
br.call.sptk rp = $branchreg;;; // FIXME: teach llvm about branch regs?
def BRLCOND_CALL : RawForm0x03, 0xb0, (ops PR:$qp, i64imm:$dst),
Index: llvm/lib/Target/IA64/IA64RegisterInfo.td
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.td:1.11
llvm/lib/Target/IA64/IA64RegisterInfo.td:1.12
--- llvm/lib/Target/IA64/IA64RegisterInfo.td:1.11 Wed Nov 30 22:51:06 2005
+++ llvm/lib/Target/IA64/IA64RegisterInfo.tdWed Dec 21 21:56:03 2005
@@ -235,8 +235,8 @@
def GR : RegisterClassIA64, [i64], 64,
[
-//FIXME!: for readability, we don't want the out registers to be the first
-//ones allocated
+//FIXME!: for both readability and performance, we don't want the out
+//registers to be the first ones allocated
out7, out6, out5, out4, out3, out2, out1, out0,
r3, r8, r9, r10, r11, r14,
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.13 - 1.14
---
Log message:
kill SelectCALL() in the DAG isel, we handle this in lowering now, like
SPARCv8. (we copy sparcv8's workaround for tablegen not being nice about
ISD::CALL/TAILCALL)
---
Diffs of the changes: (+47 -189)
IA64ISelDAGToDAG.cpp | 236 ++-
1 files changed, 47 insertions(+), 189 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.13
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.14
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.13 Wed Nov 30 17:02:08 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Wed Dec 21 21:58:17 2005
@@ -94,7 +94,6 @@
private:
SDOperand SelectDIV(SDOperand Op);
-SDOperand SelectCALL(SDOperand Op);
};
}
@@ -327,191 +326,6 @@
return Result;
}
-
-SDOperand IA64DAGToDAGISel::SelectCALL(SDOperand Op) {
- SDNode *N = Op.Val;
- SDOperand Chain = Select(N-getOperand(0));
-
- unsigned CallOpcode;
- std::vectorSDOperand CallOperands;
-
- // save the current GP, SP and RP : FIXME: do we need to do all 3 always?
- SDOperand GPBeforeCall = CurDAG-getCopyFromReg(Chain, IA64::r1, MVT::i64);
- Chain = GPBeforeCall.getValue(1);
- SDOperand SPBeforeCall = CurDAG-getCopyFromReg(Chain, IA64::r12, MVT::i64);
- Chain = SPBeforeCall.getValue(1);
- SDOperand RPBeforeCall = CurDAG-getCopyFromReg(Chain, IA64::rp, MVT::i64);
- Chain = RPBeforeCall.getValue(1);
-
- // if we can call directly, do so
- if (GlobalAddressSDNode *GASD =
- dyn_castGlobalAddressSDNode(N-getOperand(1))) {
-CallOpcode = IA64::BRCALL_IPREL;
-CallOperands.push_back(CurDAG-getTargetGlobalAddress(GASD-getGlobal(),
- MVT::i64));
- } else if (ExternalSymbolSDNode *ESSDN = // FIXME: we currently NEED this
-// case for correctness, to avoid
-// non-pic code with imm reloc.n
-// against dynamic symbol errors
- dyn_castExternalSymbolSDNode(N-getOperand(1))) {
-CallOpcode = IA64::BRCALL_IPREL;
-CallOperands.push_back(N-getOperand(1));
- } else {
-// otherwise we need to load the function descriptor,
-// load the branch target (function)'s entry point and GP,
-// branch (call) then restore the GP
-
-SDOperand FnDescriptor = Select(N-getOperand(1));
-
-// load the branch target's entry point [mem] and
-// GP value [mem+8]
-SDOperand targetEntryPoint=CurDAG-getTargetNode(IA64::LD8, MVT::i64,
- FnDescriptor);
-Chain = targetEntryPoint.getValue(1);
-SDOperand targetGPAddr=CurDAG-getTargetNode(IA64::ADDS, MVT::i64,
- FnDescriptor, CurDAG-getConstant(8, MVT::i64));
-Chain = targetGPAddr.getValue(1);
-SDOperand targetGP=CurDAG-getTargetNode(IA64::LD8, MVT::i64,
- targetGPAddr);
-Chain = targetGP.getValue(1);
-
-/* FIXME? (methcall still fails)
-SDOperand targetEntryPoint=CurDAG-getLoad(MVT::i64, Chain, FnDescriptor,
- CurDAG-getSrcValue(0));
-SDOperand targetGPAddr=CurDAG-getNode(ISD::ADD, MVT::i64, FnDescriptor,
- CurDAG-getConstant(8, MVT::i64));
-SDOperand targetGP=CurDAG-getLoad(MVT::i64, Chain, targetGPAddr,
- CurDAG-getSrcValue(0));
-*/
-
-/* this is just the long way of writing the two lines below?
-// Copy the callee GP into r1
-SDOperand r1 = CurDAG-getRegister(IA64::r1, MVT::i64);
-Chain = CurDAG-getNode(ISD::CopyToReg, MVT::i64, Chain, r1,
-targetGP);
-
-
-// Copy the callee address into the b6 branch register
-SDOperand B6 = CurDAG-getRegister(IA64::B6, MVT::i64);
-Chain = CurDAG-getNode(ISD::CopyToReg, MVT::i64, Chain, B6,
-targetEntryPoint);
-*/
-
-Chain = CurDAG-getCopyToReg(Chain, IA64::r1, targetGP);
-Chain = CurDAG-getCopyToReg(Chain, IA64::B6, targetEntryPoint);
-
-CallOperands.push_back(CurDAG-getRegister(IA64::B6, MVT::i64));
-CallOpcode = IA64::BRCALL_INDIRECT;
- }
-
- // see section 8.5.8 of Itanium Software Conventions and
- // Runtime Architecture Guide to see some examples of what's going
- // on here. (in short: int args get mapped 1:1 'slot-wise' to out0-out7,
- // while FP args get mapped to F8-F15 as needed)
-
- // TODO: support in-memory arguments
-
- unsigned used_FPArgs=0; // how many FP args have been used so far?
-
- unsigned intArgs[] = {IA64::out0, IA64::out1, IA64::out2, IA64::out3,
-IA64::out4, IA64::out5, IA64::out6, IA64::out7 };
- unsigned FPArgs[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
- IA64::F12, IA64::F13, IA64::F14, IA64::F15 };
-
- SDOperand InFlag; //
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelLowering.cpp updated: 1.5 - 1.6
---
Log message:
I shoulda done this a *long* time ago (tm): implement calls properly,
i.e. r1/r12/rp are saved/restored regardless of scheduling/luck
TODO: calls to external symbols, indirect (function descriptor) calls,
performance (we're being paranoid right now)
BUG: the code for handling calls to vararg functions breaks if FP
args are passed (this will make printf() go haywire so a bunch of
tests will fail)
BUG: this seems to trigger some legalize nastiness
---
Diffs of the changes: (+158 -16)
IA64ISelLowering.cpp | 174 ++-
1 files changed, 158 insertions(+), 16 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.5
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.6
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.5 Wed Dec 21 14:51:36 2005
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Wed Dec 21 22:07:40 2005
@@ -282,13 +282,25 @@
MF.getInfoIA64FunctionInfo()-outRegsUsed=
std::max(outRegsUsed, MF.getInfoIA64FunctionInfo()-outRegsUsed);
+ // keep stack frame 16-byte aligned
+ //assert(NumBytes==((NumBytes+15) ~15) stack frame not 16-byte
aligned!);
+ NumBytes = (NumBytes+15) ~15;
+
Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
DAG.getConstant(NumBytes, getPointerTy()));
- std::vectorSDOperand args_to_use;
+ SDOperand StackPtr, NullSV;
+ std::vectorSDOperand Stores;
+ std::vectorSDOperand RegValuesToPass;
+ unsigned ArgOffset = 16;
+
for (unsigned i = 0, e = Args.size(); i != e; ++i)
{
- switch (getValueType(Args[i].second)) {
+ SDOperand Val = Args[i].first;
+ MVT::ValueType ObjectVT = Val.getValueType();
+ SDOperand ValToStore;
+ unsigned ObjSize=8;
+ switch (ObjectVT) {
default: assert(0 unexpected argument type!);
case MVT::i1:
case MVT::i8:
@@ -297,34 +309,164 @@
//promote to 64-bits, sign/zero extending based on type
//of the argument
if(Args[i].second-isSigned())
- Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64,
- Args[i].first);
+ Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Val);
else
- Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64,
- Args[i].first);
+ Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Val);
+// XXX: fall through
+ case MVT::i64:
+//ObjSize = 8;
+if(RegValuesToPass.size() = 8) {
+ ValToStore = Val;
+} else {
+ RegValuesToPass.push_back(Val);
+}
break;
case MVT::f32:
//promote to 64-bits
-Args[i].first = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Args[i].first);
+Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
+// XXX: fall through
case MVT::f64:
- case MVT::i64:
+if(RegValuesToPass.size() = 8) {
+ ValToStore = Val;
+} else {
+ RegValuesToPass.push_back(Val);
+}
break;
}
- args_to_use.push_back(Args[i].first);
+
+ if(ValToStore.Val) {
+if(!StackPtr.Val) {
+ StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
+ NullSV = DAG.getSrcValue(NULL);
+}
+SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
+PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff);
+Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
+ ValToStore, PtrOff, NullSV));
+ }
+ ArgOffset += ObjSize;
}
+ // Emit all stores, make sure they occur before any copies into physregs.
+ if (!Stores.empty())
+Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
+
+ static const unsigned IntArgRegs[] = {
+IA64::out0, IA64::out1, IA64::out2, IA64::out3,
+IA64::out4, IA64::out5, IA64::out6, IA64::out7
+ };
+
+ static const unsigned FPArgRegs[] = {
+IA64::F8, IA64::F9, IA64::F10, IA64::F11,
+IA64::F12, IA64::F13, IA64::F14, IA64::F15
+ };
+
+ SDOperand InFlag;
+
+ // save the current GP, SP and RP : FIXME: do we need to do all 3 always?
+ SDOperand GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64,
InFlag);
+ Chain = GPBeforeCall;
+ InFlag = Chain.getValue(1);
+ SDOperand SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64,
InFlag);
+ Chain = SPBeforeCall;
+ InFlag = Chain.getValue(1);
+ SDOperand RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64,
InFlag);
+ Chain = RPBeforeCall;
+ InFlag = Chain.getValue(1);
+
+ // Build a sequence of copy-to-reg nodes chained together with token chain
+ // and flag operands which copy the outgoing integer args into regs out[0-7]
+ // mapped 1:1 and the FP args into regs F8-F15 lazily
+ // TODO: for performance, we should only copy FP args
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64InstrInfo.td updated: 1.31 - 1.32
---
Log message:
we need to emit the getf.d instruction in lowering, so add it
to IA64ISD
---
Diffs of the changes: (+11 -2)
IA64InstrInfo.td | 13 +++--
1 files changed, 11 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.31
llvm/lib/Target/IA64/IA64InstrInfo.td:1.32
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.31 Wed Dec 21 21:56:03 2005
+++ llvm/lib/Target/IA64/IA64InstrInfo.td Thu Dec 22 00:38:38 2005
@@ -15,6 +15,14 @@
include IA64InstrFormats.td
+//===--===//
+// IA-64 specific DAG Nodes.
+//
+
+def IA64getfd : SDNodeIA64ISD::GETFD, SDTFPToIntOp, [];
+
+//===-
+
def u2imm : Operandi8;
def u6imm : Operandi8;
def s8imm : Operandi8 {
@@ -614,8 +622,9 @@
def FNORMD : AForm0x03, 0x0b, (ops FP:$dst, FP:$src),
fnorm.d $dst = $src;;;
-def GETFD : AForm0x03, 0x0b, (ops GR:$dst, FP:$src),
- getf.d $dst = $src;;;
+def GETFD : AForm_DAG0x03, 0x0b, (ops GR:$dst, FP:$src),
+ getf.d $dst = $src;;,
+ [(set GR:$dst, (IA64getfd FP:$src))];
def SETFD : AForm0x03, 0x0b, (ops FP:$dst, GR:$src),
setf.d $dst = $src;;;
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelLowering.cpp updated: 1.6 - 1.7
---
Log message:
this should take care of calls to varadic functions, but it doesn.,t
BUG: calling printf(string, float) will load the float into the wrong
register, completely forget about loading the string, etce
---
Diffs of the changes: (+14 -7)
IA64ISelLowering.cpp | 21 ++---
1 files changed, 14 insertions(+), 7 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.6
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.7
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.6 Wed Dec 21 22:07:40 2005
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Thu Dec 22 00:39:57 2005
@@ -388,16 +388,22 @@
InFlag = Chain.getValue(1);
//FIXME: for performance, only do the following when required
-
+
// if we have just copied an FP arg, copy its in-memory representation
// to the appropriate integer register
-/*if(MVT::isFloatingPoint(RegValuesToPass[i].getValueType())) {
- Chain = DAG.getTargetNode(IA64::GETFD, MVT::i64, RegValuesToPass[i],
Chain, InFlag);
- InFlag = Chain.getValue(0); // XXX
- Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Chain, InFlag); //
...thrice!
+if(MVT::isFloatingPoint(RegValuesToPass[i].getValueType())) {
+ std::vectorMVT::ValueType GETFDRetTypes;
+ std::vectorSDOperand GETFDOperands;
+ GETFDRetTypes.push_back(MVT::i64);
+ GETFDRetTypes.push_back(MVT::Flag);
+ GETFDOperands.push_back(RegValuesToPass[i]);
+ GETFDOperands.push_back(Chain);
+ GETFDOperands.push_back(InFlag);
+
+ Chain = DAG.getNode(IA64ISD::GETFD, GETFDRetTypes, GETFDOperands);
+ Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Chain.getValue(0),
Chain.getValue(1)); // ...thrice!
InFlag = Chain.getValue(1);
-} */
-
+}
}
std::vectorMVT::ValueType RetVals;
@@ -452,6 +458,7 @@
RetVal = DAG.getNode(RetTy-isSigned() ? ISD::AssertSext
:ISD::AssertZext,
MVT::i64, RetVal, DAG.getValueType(RetTyVT));
RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
+ break;
case MVT::i64:
RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
Chain = RetVal.getValue(1);
___
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAG.h updated: 1.80 - 1.81
---
Log message:
i need to do this to take over the earth
when I take over the earth, sabre will be happy because i'll stop asking
him silly questions!!
---
Diffs of the changes: (+9 -0)
SelectionDAG.h |9 +
1 files changed, 9 insertions(+)
Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.80
llvm/include/llvm/CodeGen/SelectionDAG.h:1.81
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.80 Sun Dec 18 15:00:53 2005
+++ llvm/include/llvm/CodeGen/SelectionDAG.hThu Dec 22 01:02:51 2005
@@ -364,6 +364,15 @@
return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops);
}
SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT1,
+ MVT::ValueType VT2, SDOperand Op1) {
+std::vectorMVT::ValueType ResultTys;
+ResultTys.push_back(VT1);
+ResultTys.push_back(VT2);
+std::vectorSDOperand Ops;
+Ops.push_back(Op1);
+return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops);
+ }
+ SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, SDOperand Op1, SDOperand Op2) {
std::vectorMVT::ValueType ResultTys;
ResultTys.push_back(VT1);
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.32 - 1.33 --- Log message: oops, back this out --- Diffs of the changes: (+2 -3) IA64InstrInfo.td |5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) Index: llvm/lib/Target/IA64/IA64InstrInfo.td diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.32 llvm/lib/Target/IA64/IA64InstrInfo.td:1.33 --- llvm/lib/Target/IA64/IA64InstrInfo.td:1.32 Thu Dec 22 00:38:38 2005 +++ llvm/lib/Target/IA64/IA64InstrInfo.td Thu Dec 22 01:13:51 2005 @@ -622,9 +622,8 @@ def FNORMD : AForm0x03, 0x0b, (ops FP:$dst, FP:$src), fnorm.d $dst = $src;;; -def GETFD : AForm_DAG0x03, 0x0b, (ops GR:$dst, FP:$src), - getf.d $dst = $src;;, - [(set GR:$dst, (IA64getfd FP:$src))]; +def GETFD : AForm0x03, 0x0b, (ops GR:$dst, FP:$src), + getf.d $dst = $src;;; def SETFD : AForm0x03, 0x0b, (ops FP:$dst, GR:$src), setf.d $dst = $src;;; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.10 - 1.11
---
Log message:
add support for div/rem to the dag-dag isel. yay.
---
Diffs of the changes: (+180 -0)
IA64ISelDAGToDAG.cpp | 180 +++
1 files changed, 180 insertions(+)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.10
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.11
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.10 Sun Nov 6 21:11:03 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Mon Nov 21 08:14:54 2005
@@ -93,6 +93,7 @@
#include IA64GenDAGISel.inc
private:
+SDOperand SelectDIV(SDOperand Op);
SDOperand SelectCALL(SDOperand Op);
};
}
@@ -153,6 +154,179 @@
ScheduleAndEmitDAG(DAG);
}
+SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
+ SDNode *N = Op.Val;
+ SDOperand Chain = Select(N-getOperand(0));
+
+ SDOperand Tmp1 = Select(N-getOperand(0));
+ SDOperand Tmp2 = Select(N-getOperand(1));
+
+ bool isFP=false;
+
+ if(MVT::isFloatingPoint(Tmp1.getValueType()))
+isFP=true;
+
+ bool isModulus=false; // is it a division or a modulus?
+ bool isSigned=false;
+
+ switch(N-getOpcode()) {
+case ISD::FDIV:
+case ISD::SDIV: isModulus=false; isSigned=true; break;
+case ISD::UDIV: isModulus=false; isSigned=false; break;
+case ISD::FREM:
+case ISD::SREM: isModulus=true; isSigned=true; break;
+case ISD::UREM: isModulus=true; isSigned=false; break;
+ }
+
+ // TODO: check for integer divides by powers of 2 (or other simple patterns?)
+
+SDOperand TmpPR, TmpPR2;
+SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
+SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
+SDOperand Result;
+
+// OK, emit some code:
+
+if(!isFP) {
+ // first, load the inputs into FP regs.
+ TmpF1 = CurDAG-getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1);
+ Chain = TmpF1.getValue(1);
+ TmpF2 = CurDAG-getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2);
+ Chain = TmpF2.getValue(1);
+
+ // next, convert the inputs to FP
+ if(isSigned) {
+TmpF3 = CurDAG-getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1);
+Chain = TmpF3.getValue(1);
+TmpF4 = CurDAG-getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2);
+Chain = TmpF4.getValue(1);
+ } else {
+TmpF3 = CurDAG-getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1);
+Chain = TmpF3.getValue(1);
+TmpF4 = CurDAG-getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2);
+Chain = TmpF4.getValue(1);
+ }
+
+} else { // this is an FP divide/remainder, so we 'leak' some temp
+ // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
+ TmpF3=Tmp1;
+ TmpF4=Tmp2;
+}
+
+// we start by computing an approximate reciprocal (good to 9 bits?)
+// note, this instruction writes _both_ TmpF5 (answer) and TmpPR
(predicate)
+TmpF5 = CurDAG-getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
+ TmpF3, TmpF4);
+TmpPR = TmpF5.getValue(1);
+Chain = TmpF5.getValue(2);
+
+if(!isModulus) { // if this is a divide, we worry about div-by-zero
+SDOperand bogusPR = CurDAG-getTargetNode(IA64::CMPEQ, MVT::i1,
+ CurDAG-getRegister(IA64::r0, MVT::i64),
+ CurDAG-getRegister(IA64::r0, MVT::i64));
+Chain = bogusPR.getValue(1);
+TmpPR2 = CurDAG-getTargetNode(IA64::TPCMPNE, MVT::i1, bogusPR,
+ CurDAG-getRegister(IA64::r0, MVT::i64),
+ CurDAG-getRegister(IA64::r0, MVT::i64), TmpPR);
+Chain = TmpPR2.getValue(1);
+}
+
+SDOperand F0 = CurDAG-getRegister(IA64::F0, MVT::f64);
+SDOperand F1 = CurDAG-getRegister(IA64::F1, MVT::f64);
+
+// now we apply newton's method, thrice! (FIXME: this is ~72 bits of
+// precision, don't need this much for f32/i32)
+TmpF6 = CurDAG-getTargetNode(IA64::CFNMAS1, MVT::f64,
+ TmpF4, TmpF5, F1, TmpPR);
+Chain = TmpF6.getValue(1);
+TmpF7 = CurDAG-getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpF3, TmpF5, F0, TmpPR);
+Chain = TmpF7.getValue(1);
+TmpF8 = CurDAG-getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpF6, TmpF6, F0, TmpPR);
+Chain = TmpF8.getValue(1);
+TmpF9 = CurDAG-getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpF6, TmpF7, TmpF7, TmpPR);
+Chain = TmpF9.getValue(1);
+TmpF10 = CurDAG-getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpF6, TmpF5, TmpF5, TmpPR);
+Chain = TmpF10.getValue(1);
+TmpF11 = CurDAG-getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpF8, TmpF9, TmpF9, TmpPR);
+Chain = TmpF11.getValue(1);
+TmpF12 = CurDAG-getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpF8, TmpF10, TmpF10, TmpPR);
+Chain = TmpF12.getValue(1);
+TmpF13 = CurDAG-getTargetNode(IA64::CFNMAS1, MVT::f64,
+ TmpF4, TmpF11, TmpF3, TmpPR);
+Chain = TmpF13.getValue(1);
+
+ // FIXME: this is unfortunate :(
+
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.6 - 1.7
---
Log message:
add support for loading bools
---
Diffs of the changes: (+7 -1)
IA64ISelDAGToDAG.cpp |8 +++-
1 files changed, 7 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.6
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.7
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.6 Wed Nov 2 01:32:59 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Fri Nov 4 03:59:06 2005
@@ -369,7 +369,13 @@
unsigned Opc;
switch (TypeBeingLoaded) {
default: N-dump(); assert(0 Cannot load this type!);
-// FIXME: bools? case MVT::i1:
+case MVT::i1: { // this is a bool
+ Opc = IA64::LD1; // first we load a byte, then compare for != 0
+ CurDAG-SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
+ CurDAG-getTargetNode(Opc, MVT::i64, Address),
+ CurDAG-getRegister(IA64::r0, MVT::i64), Chain);
+ return SDOperand(N, Op.ResNo); // XXX: early exit
+ }
case MVT::i8: Opc = IA64::LD1; break;
case MVT::i16: Opc = IA64::LD2; break;
case MVT::i32: Opc = IA64::LD4; break;
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64: IA64ISelLowering.cpp updated: 1.2 - 1.3 --- Log message: kill redundant SP/GP/RP save/restores across calls --- Diffs of the changes: (+3 -2) IA64ISelLowering.cpp |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.2 llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.3 --- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.2 Tue Nov 1 20:35:04 2005 +++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Fri Nov 4 04:01:11 2005 @@ -192,20 +192,21 @@ VirtGPR = MF.getSSARegMap()-createVirtualRegister(getRegClassFor(MVT::i64)); BuildMI(BB, IA64::PSEUDO_ALLOC, 0, VirtGPR); // we create a PSEUDO_ALLOC (pseudo)instruction for now - +/* BuildMI(BB, IA64::IDEF, 0, IA64::r1); // hmm: BuildMI(BB, IA64::IDEF, 0, IA64::r12); BuildMI(BB, IA64::IDEF, 0, IA64::rp); // ..hmm. - + BuildMI(BB, IA64::MOV, 1, GP).addReg(IA64::r1); // hmm: BuildMI(BB, IA64::MOV, 1, SP).addReg(IA64::r12); BuildMI(BB, IA64::MOV, 1, RP).addReg(IA64::rp); // ..hmm. +*/ unsigned tempOffset=0; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.7 - 1.8
---
Log message:
oops, forgot to load GP for indirect calls, though the old code now commented
out failed (e.g. methcall) - now the code compiles, though it's not quite
right just yet (tm) ;)
would fix this but it's 3am! :O
---
Diffs of the changes: (+21 -4)
IA64ISelDAGToDAG.cpp | 25 +
1 files changed, 21 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.7
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.8
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.7 Fri Nov 4 03:59:06 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Fri Nov 4 11:55:53 2005
@@ -185,23 +185,40 @@
} else {
// otherwise we need to load the function descriptor,
// load the branch target (function)'s entry point and GP,
-// branch (call) then restore the
-// GP
+// branch (call) then restore the GP
SDOperand FnDescriptor = Select(N-getOperand(1));
// load the branch target's entry point [mem] and
// GP value [mem+8]
+SDOperand targetEntryPoint=CurDAG-getTargetNode(IA64::LD8, MVT::i64,
+ FnDescriptor);
+Chain = targetEntryPoint.getValue(1);
+SDOperand targetGPAddr=CurDAG-getTargetNode(IA64::ADDS, MVT::i64,
+ FnDescriptor, CurDAG-getConstant(8, MVT::i64));
+Chain = targetGPAddr.getValue(1);
+SDOperand targetGP=CurDAG-getTargetNode(IA64::LD8, MVT::i64,
+ targetGPAddr);
+Chain = targetGP.getValue(1);
+
+/* FIXME! (methcall still fails)
SDOperand targetEntryPoint=CurDAG-getLoad(MVT::i64, Chain, FnDescriptor,
CurDAG-getSrcValue(0));
SDOperand targetGPAddr=CurDAG-getNode(ISD::ADD, MVT::i64, FnDescriptor,
CurDAG-getConstant(8, MVT::i64));
SDOperand targetGP=CurDAG-getLoad(MVT::i64, Chain, targetGPAddr,
- CurDAG-getSrcValue(0));
+ CurDAG-getSrcValue(0));
+*/
+
+// Copy the callee GP into r1
+SDOperand r1 = CurDAG-getRegister(IA64::r1, MVT::i64);
+Chain = CurDAG-getNode(ISD::CopyToReg, MVT::i64, Chain, r1,
+targetGP);
+
// Copy the callee address into the b6 branch register
SDOperand B6 = CurDAG-getRegister(IA64::B6, MVT::i64);
-Chain = CurDAG-getNode(ISD::CopyToReg, MVT::Other, Chain, B6,
+Chain = CurDAG-getNode(ISD::CopyToReg, MVT::i64, Chain, B6,
targetEntryPoint);
CallOperands.push_back(B6);
___
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[llvm-commits] CVS: llvm-test/Makefile.programs
Changes in directory llvm-test: Makefile.programs updated: 1.176 - 1.177 --- Log message: fun with scheduling on ia64 --- Diffs of the changes: (+1 -1) Makefile.programs |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.176 llvm-test/Makefile.programs:1.177 --- llvm-test/Makefile.programs:1.176 Mon Oct 31 15:18:30 2005 +++ llvm-test/Makefile.programs Thu Nov 3 16:00:16 2005 @@ -194,7 +194,7 @@ #-enable-alpha-intfpdiv -enable-alpha-FTOI endif ifeq ($(ARCH),IA64) -LLCBETAOPTION := -enable-ia64-dag-isel +LLCBETAOPTION := -enable-ia64-dag-isel -sched=simple endif ifeq ($(ARCH),x86) LLCBETAOPTION := -enable-x86-fastcc ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64InstrInfo.td updated: 1.27 - 1.28
---
Log message:
fun with predicates! (add TRUNC i64-i1, AND i1 i1, fix XOR i1 i1)
---
Diffs of the changes: (+97 -41)
IA64InstrInfo.td | 137 ++-
1 files changed, 97 insertions(+), 40 deletions(-)
Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.27
llvm/lib/Target/IA64/IA64InstrInfo.td:1.28
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.27 Thu Nov 3 04:09:32 2005
+++ llvm/lib/Target/IA64/IA64InstrInfo.td Thu Nov 3 18:57:56 2005
@@ -105,6 +105,10 @@
adds $dst = $imm, $src1;;,
[(set GR:$dst, (add GR:$src1, immSExt14:$imm))];
+def PADDS: AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm, PR:$qp),
+ ($qp) adds $dst = $imm, $src1;;,
+ [];
+
def MOVL : AForm_DAG0x03, 0x0b, (ops GR:$dst, s64imm:$imm),
movl $dst = $imm;;,
[(set GR:$dst, imm64:$imm)];
@@ -225,47 +229,6 @@
def pOR : AForm0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2, PR:$qp),
($qp) or $dst = $src1, $src2;;;
-def PCMPEQUNCR0R0 : AForm0x03, 0x0b, (ops PR:$dst, PR:$qp),
-($qp) cmp.eq.unc $dst, p0 = r0, r0;;;
-
-let isTwoAddress=1 in
-def TPCMPEQR0R0 : AForm0x03, 0x0b, (ops PR:$dst, PR:$bogus, PR:$qp),
- ($qp) cmp.eq $dst, p0 = r0, r0;;;
-
-/* our pseudocode for OR on predicates is:
-pC = pA OR pB
--
-(pA) cmp.eq.unc pC,p0 = r0,r0 // pC = pA
- ;;
-(pB) cmp.eq pC,p0 = r0,r0 // if (pB) pC = 1 */
-
-def bOR : Pat(or PR:$src1, PR:$src2),
- (TPCMPEQR0R0 (PCMPEQUNCR0R0 PR:$src1), PR:$src2);
-
-// FIXME: these are bogus
-def bXOR : Pat(xor PR:$src1, PR:$src2),
- (PCMPEQUNCR0R0 PR:$src1);
-
-def XOR : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
- xor $dst = $src1, $src2;;,
- [(set GR:$dst, (xor GR:$src1, GR:$src2))];
-
-def SHLADD: AForm_DAG0x03, 0x0b, (ops GR:$dst,GR:$src1,s64imm:$imm,GR:$src2),
- shladd $dst = $src1, $imm, $src2;;,
- [(set GR:$dst, (add GR:$src2, (shl GR:$src1, isSHLADDimm:$imm)))];
-
-def SHL : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
- shl $dst = $src1, $src2;;,
- [(set GR:$dst, (shl GR:$src1, GR:$src2))];
-
-def SHRU : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
- shr.u $dst = $src1, $src2;;,
- [(set GR:$dst, (srl GR:$src1, GR:$src2))];
-
-def SHRS : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
- shr $dst = $src1, $src2;;,
- [(set GR:$dst, (sra GR:$src1, GR:$src2))];
-
// the following are all a bit unfortunate: we throw away the complement
// of the compare!
def CMPEQ : AForm_DAG0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
@@ -331,6 +294,99 @@
fcmp.geu $dst, p0 = $src1, $src2;;,
[(set PR:$dst, (setuge FP:$src1, FP:$src2))];
+def PCMPEQUNCR0R0 : AForm0x03, 0x0b, (ops PR:$dst, PR:$qp),
+($qp) cmp.eq.unc $dst, p0 = r0, r0;;;
+
+def : Pat(trunc GR:$src), // truncate i64 to i1
+ (CMPNE GR:$src, r0); // $src!=0? If so, PR:$dst=true
+
+let isTwoAddress=1 in {
+ def TPCMPEQR0R0 : AForm0x03, 0x0b, (ops PR:$dst, PR:$bogus, PR:$qp),
+($qp) cmp.eq $dst, p0 = r0, r0;;;
+ def TPCMPNER0R0 : AForm0x03, 0x0b, (ops PR:$dst, PR:$bogus, PR:$qp),
+($qp) cmp.ne $dst, p0 = r0, r0;;;
+}
+
+/* our pseudocode for OR on predicates is:
+pC = pA OR pB
+-
+(pA) cmp.eq.unc pC,p0 = r0,r0 // pC = pA
+ ;;
+(pB) cmp.eq pC,p0 = r0,r0 // if (pB) pC = 1 */
+
+def bOR : Pat(or PR:$src1, PR:$src2),
+ (TPCMPEQR0R0 (PCMPEQUNCR0R0 PR:$src1), PR:$src2);
+
+/* our pseudocode for AND on predicates is:
+ *
+(pA) cmp.eq.unc pC,p0 = r0,r0 // pC = pA
+ cmp.eq pTemp,p0 = r0,r0// pTemp = NOT pB
+ ;;
+(pB) cmp.ne pTemp,p0 = r0,r0
+ ;;
+(pTemp)cmp.ne pC,p0 = r0,r0// if (NOT pB) pC = 0 */
+
+def bAND : Pat(and PR:$src1, PR:$src2),
+ ( TPCMPNER0R0 (PCMPEQUNCR0R0 PR:$src1),
+ (TPCMPNER0R0 (CMPEQ r0, r0), PR:$src2) );
+
+/* one possible routine for XOR on predicates is:
+
+ // Compute px = py ^ pz
+// using sum of products: px = (py !pz) | (pz !py)
+// Uses 5 instructions in 3 cycles.
+// cycle 1
+(pz)cmp.eq.unc px = r0, r0 // px = pz
+(py)cmp.eq.unc pt = r0, r0 // pt = py
+;;
+// cycle 2
+(pt)cmp.ne.and px = r0, r0 // px = px !pt (px = pz !pt)
+(pz)cmp.ne.and pt = r0, r0 // pt = pt !pz
+;;
+} { .mmi
+// cycle 3
+(pt)cmp.eq.or px = r0, r0 // px = px | pt
+
+*** Another, which we use here, requires one scratch GR. it is:
+
+mov rt = 0 // initialize rt off critical path
+;;
+
+// cycle 1
+(pz)cmp.eq.unc px = r0, r0 // px = pz
+(pz)mov rt = 1 // rt = pz
+;;
+// cycle 2
+(py)
[llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrItineraries.h
Changes in directory llvm/include/llvm/Target:
TargetInstrItineraries.h updated: 1.4 - 1.5
---
Log message:
change NULL to 0, unbreaks the ppc target when building on ia64
---
Diffs of the changes: (+2 -2)
TargetInstrItineraries.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/include/llvm/Target/TargetInstrItineraries.h
diff -u llvm/include/llvm/Target/TargetInstrItineraries.h:1.4
llvm/include/llvm/Target/TargetInstrItineraries.h:1.5
--- llvm/include/llvm/Target/TargetInstrItineraries.h:1.4 Thu Nov 3
16:47:42 2005
+++ llvm/include/llvm/Target/TargetInstrItineraries.h Thu Nov 3 19:45:04 2005
@@ -55,13 +55,13 @@
//
// Ctors.
//
- InstrItineraryData() : Stages(NULL), Itineratries(NULL) {}
+ InstrItineraryData() : Stages(0), Itineratries(0) {}
InstrItineraryData(InstrStage *S, InstrItinerary *I) : Stages(S),
Itineratries(I) {}
//
// isEmpty - Returns true if there are no itineraries.
//
- inline bool isEmpty() const { return Itineratries == NULL; }
+ inline bool isEmpty() const { return Itineratries == 0; }
//
// begin - Return the first stage of the itinerary.
___
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[llvm-commits] CVS: llvm-test/Makefile.programs
Changes in directory llvm-test: Makefile.programs updated: 1.177 - 1.178 --- Log message: chicken out: sched=simple breaks quite a bit of the testsuite currently. will look at this again later :) --- Diffs of the changes: (+1 -1) Makefile.programs |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.177 llvm-test/Makefile.programs:1.178 --- llvm-test/Makefile.programs:1.177 Thu Nov 3 16:00:16 2005 +++ llvm-test/Makefile.programs Thu Nov 3 23:29:38 2005 @@ -194,7 +194,7 @@ #-enable-alpha-intfpdiv -enable-alpha-FTOI endif ifeq ($(ARCH),IA64) -LLCBETAOPTION := -enable-ia64-dag-isel -sched=simple +LLCBETAOPTION := -enable-ia64-dag-isel endif ifeq ($(ARCH),x86) LLCBETAOPTION := -enable-x86-fastcc ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.4 - 1.5
IA64ISelLowering.cpp updated: 1.1 - 1.2
---
Log message:
add support for loading FP constants +0.0 and +1.0 to the dag isel,
stop pretending -0.0 and -1.0 are machine constants
---
Diffs of the changes: (+8 -3)
IA64ISelDAGToDAG.cpp |8
IA64ISelLowering.cpp |3 ---
2 files changed, 8 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.4
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.5
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.4 Mon Oct 31 23:46:16 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Tue Nov 1 20:35:04 2005
@@ -321,6 +321,14 @@
/* todo:
* case ISD::DYNAMIC_STACKALLOC:
*/
+ case ISD::ConstantFP: {
+if (castConstantFPSDNode(N)-isExactlyValue(+0.0))
+ return CurDAG-getRegister(IA64::F0, MVT::f64); // load 0.0
+else if (castConstantFPSDNode(N)-isExactlyValue(+1.0))
+ return CurDAG-getRegister(IA64::F1, MVT::f64); // load 1.0
+else
+ assert(0 Unexpected FP constant!);
+ }
case ISD::FrameIndex: { // TODO: reduce creepyness
int FI = castFrameIndexSDNode(N)-getIndex();
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.1
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.2
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.1 Fri Oct 28 12:46:36 2005
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Tue Nov 1 20:35:04 2005
@@ -80,9 +80,6 @@
addLegalFPImmediate(+0.0);
addLegalFPImmediate(+1.0);
- addLegalFPImmediate(-0.0);
- addLegalFPImmediate(-1.0);
-
}
/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
___
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.8 - 1.9 --- Log message: add support for SELECT to TargetSelectionDAG.td, add support for selecting ints to IA64, and a few other ia64 bits and pieces --- Diffs of the changes: (+5 -0) TargetSelectionDAG.td |5 + 1 files changed, 5 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.8 llvm/lib/Target/TargetSelectionDAG.td:1.9 --- llvm/lib/Target/TargetSelectionDAG.td:1.8 Mon Oct 31 21:07:25 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Tue Nov 1 20:37:18 2005 @@ -109,6 +109,10 @@ SDTCisInt0, SDTCisSameAs1, 2, SDTCisVT3, OtherVT ]; +def SDTSelect : SDTypeProfile1, 3, [ // select + SDTCisInt1, SDTCisSameAs0, 2, SDTCisSameAs2, 3 +]; + //===--===// // Selection DAG Node Properties. // @@ -184,6 +188,7 @@ def fp_to_uint : SDNodeISD::FP_TO_UINT , SDTFPToIntOp; def setcc : SDNodeISD::SETCC , SDTSetCC; +def select : SDNodeISD::SELECT , SDTSelect; //===--===// // Selection DAG Condition Codes ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64InstrInfo.td updated: 1.23 - 1.24
---
Log message:
add support for SELECT to TargetSelectionDAG.td, add support for
selecting ints to IA64, and a few other ia64 bits and pieces
---
Diffs of the changes: (+38 -31)
IA64InstrInfo.td | 69 ++-
1 files changed, 38 insertions(+), 31 deletions(-)
Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.23
llvm/lib/Target/IA64/IA64InstrInfo.td:1.24
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.23 Mon Oct 31 21:32:15 2005
+++ llvm/lib/Target/IA64/IA64InstrInfo.td Tue Nov 1 20:37:18 2005
@@ -211,11 +211,6 @@
// def ADDS : AForm0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
// adds $dst = $imm, $src1;;;
-// load constants of various sizes // FIXME: prettyprint -ve constants
-def : Pat(i64 immSExt14:$imm), (ADDS r0, immSExt14:$imm);
-def : Pat(i64 imm64:$imm), (MOVL imm64:$imm);
-// TODO: def : Pat(i1 1), (stuff);
-
def AND : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
and $dst = $src1, $src2;;,
[(set GR:$dst, (and GR:$src1, GR:$src2))];
@@ -336,6 +331,38 @@
fcmp.geu $dst, p0 = $src1, $src2;;,
[(set PR:$dst, (setuge FP:$src1, FP:$src2))];
+def MOV : AForm0x03, 0x0b, (ops GR:$dst, GR:$src), mov $dst = $src;;;
+def PMOV : AForm0x03, 0x0b, (ops GR:$dst, GR:$src, PR:$qp),
+ ($qp) mov $dst = $src;;;
+
+def SPILL_ALL_PREDICATES_TO_GR : AForm0x03, 0x0b, (ops GR:$dst),
+ mov $dst = pr;;;
+def FILL_ALL_PREDICATES_FROM_GR : AForm0x03, 0x0b, (ops GR:$src),
+ mov pr = $src;;;
+
+let isTwoAddress = 1 in {
+ def CMOV : AForm0x03, 0x0b, (ops GR:$dst, GR:$src2, GR:$src, PR:$qp),
+($qp) mov $dst = $src;;;
+}
+
+def PFMOV : AForm0x03, 0x0b, (ops FP:$dst, FP:$src, PR:$qp),
+ ($qp) mov $dst = $src;;;
+
+let isTwoAddress = 1 in {
+ def CFMOV : AForm0x03, 0x0b, (ops FP:$dst, FP:$src2, FP:$src, PR:$qp),
+($qp) mov $dst = $src;;;
+}
+
+// TODO: select FPs, bools
+def SELECTINT : Pat(select PR:$which, GR:$src1, GR:$src2),
+ (CMOV (MOV GR:$src2), GR:$src1, PR:$which); // note order!
+
+// load constants of various sizes // FIXME: prettyprint -ve constants
+def : Pat(i64 immSExt14:$imm), (ADDS r0, immSExt14:$imm);
+def : Pat(i64 imm64:$imm), (MOVL imm64:$imm);
+//FIXME: tablegen coughs on this next one:
+//def : Pat(i1 1), (CMPEQ r0, r0); // TODO: this should just be a ref to p0
+
// TODO: support postincrement (reg, imm9) loads+stores - this needs more
// tablegen support
@@ -360,28 +387,6 @@
(ops GR:$dst, i8imm:$inputs, i8imm:$locals, i8imm:$outputs, i8imm:$rotating),
alloc $dst = ar.pfs,$inputs,$locals,$outputs,$rotating;;;
-def MOV : AForm0x03, 0x0b, (ops GR:$dst, GR:$src), mov $dst = $src;;;
-def PMOV : AForm0x03, 0x0b, (ops GR:$dst, GR:$src, PR:$qp),
- ($qp) mov $dst = $src;;;
-
-def SPILL_ALL_PREDICATES_TO_GR : AForm0x03, 0x0b, (ops GR:$dst),
- mov $dst = pr;;;
-def FILL_ALL_PREDICATES_FROM_GR : AForm0x03, 0x0b, (ops GR:$src),
- mov pr = $src;;;
-
-let isTwoAddress = 1 in {
- def CMOV : AForm0x03, 0x0b, (ops GR:$dst, GR:$src2, GR:$src, PR:$qp),
-($qp) mov $dst = $src;;;
-}
-
-def PFMOV : AForm0x03, 0x0b, (ops FP:$dst, FP:$src, PR:$qp),
- ($qp) mov $dst = $src;;;
-
-let isTwoAddress = 1 in {
- def CFMOV : AForm0x03, 0x0b, (ops FP:$dst, FP:$src2, FP:$src, PR:$qp),
-($qp) mov $dst = $src;;;
-}
-
let isTwoAddress = 1 in {
def TCMPNE : AForm0x03, 0x0b,
(ops PR:$dst, PR:$src2, GR:$src3, GR:$src4),
@@ -498,13 +503,15 @@
def FNMA : AForm_DAG0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
fnma $dst = $src1, $src2, $src3;;,
[(set FP:$dst, (fneg (fadd (fmul FP:$src1, FP:$src2), FP:$src3)))];
-def FABS : AForm0x03, 0x0b, (ops FP:$dst, FP:$src),
- fabs $dst = $src;;;
+def FABS : AForm_DAG0x03, 0x0b, (ops FP:$dst, FP:$src),
+ fabs $dst = $src;;,
+ [(set FP:$dst, (fabs FP:$src))];
def FNEG : AForm_DAG0x03, 0x0b, (ops FP:$dst, FP:$src),
fneg $dst = $src;;,
[(set FP:$dst, (fneg FP:$src))];
-def FNEGABS : AForm0x03, 0x0b, (ops FP:$dst, FP:$src),
- fnegabs $dst = $src;;;
+def FNEGABS : AForm_DAG0x03, 0x0b, (ops FP:$dst, FP:$src),
+ fnegabs $dst = $src;;,
+ [(set FP:$dst, (fneg (fabs FP:$src)))];
def CFMAS1 : AForm0x03, 0x0b,
(ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64RegisterInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64RegisterInfo.td updated: 1.9 - 1.10
---
Log message:
add F0 and F1 to the FP register class
---
Diffs of the changes: (+19 -3)
IA64RegisterInfo.td | 22 +++---
1 files changed, 19 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/IA64/IA64RegisterInfo.td
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.td:1.9
llvm/lib/Target/IA64/IA64RegisterInfo.td:1.10
--- llvm/lib/Target/IA64/IA64RegisterInfo.td:1.9Fri Oct 28 12:46:36 2005
+++ llvm/lib/Target/IA64/IA64RegisterInfo.tdWed Nov 2 01:30:39 2005
@@ -226,7 +226,6 @@
//
// these are the scratch (+stacked) general registers
-// ZERO (r0), GP (r1), SP (r12), ThreadP (r13) are not here...
// FIXME/XXX we also reserve a frame pointer (r15)
// FIXME/XXX we also reserve r2 for spilling/filling predicates
// in IA64RegisterInfo.cpp
@@ -283,7 +282,6 @@
// these are the scratch (+stacked) FP registers
-// ZERO (F0) and ONE (F1) are not here
def FP : RegisterClassIA64, f64, 64,
[F6, F7,
F8, F9, F10, F11, F12, F13, F14, F15,
@@ -298,7 +296,25 @@
F96, F97, F98, F99, F100, F101, F102, F103,
F104, F105, F106, F107, F108, F109, F110, F111,
F112, F113, F114, F115, F116, F117, F118, F119,
- F120, F121, F122, F123, F124, F125, F126, F127];
+ F120, F121, F122, F123, F124, F125, F126, F127,
+ F0, F1] // these last two are hidden
+ {
+let MethodProtos = [{
+iterator allocation_order_begin(MachineFunction MF) const;
+iterator allocation_order_end(MachineFunction MF) const;
+ }];
+ let MethodBodies = [{
+FPClass::iterator
+FPClass::allocation_order_begin(MachineFunction MF) const {
+ return begin(); // we don't hide any FP regs from the start
+ }
+
+ FPClass::iterator
+ FPClass::allocation_order_end(MachineFunction MF) const {
+ return end()-2; // we hide regs F0, F1 from the end
+ }
+ }];
+}
// these are the predicate registers, p0 (1/TRUE) is not here
def PR : RegisterClassIA64, i1, 64,
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.5 - 1.6
---
Log message:
fix support for FP constants (this code asserts in the scheduler,
though)
---
Diffs of the changes: (+4 -2)
IA64ISelDAGToDAG.cpp |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.5
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.6
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.5 Tue Nov 1 20:35:04 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Wed Nov 2 01:32:59 2005
@@ -322,10 +322,12 @@
* case ISD::DYNAMIC_STACKALLOC:
*/
case ISD::ConstantFP: {
+SDOperand Chain = CurDAG-getEntryNode(); // this is a constant, so..
+
if (castConstantFPSDNode(N)-isExactlyValue(+0.0))
- return CurDAG-getRegister(IA64::F0, MVT::f64); // load 0.0
+ return CurDAG-getCopyFromReg(Chain, IA64::F0, MVT::f64);
else if (castConstantFPSDNode(N)-isExactlyValue(+1.0))
- return CurDAG-getRegister(IA64::F1, MVT::f64); // load 1.0
+ return CurDAG-getCopyFromReg(Chain, IA64::F1, MVT::f64);
else
assert(0 Unexpected FP constant!);
}
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64InstrInfo.td updated: 1.20 - 1.21
---
Log message:
add zeroextend predicate-integer
---
Diffs of the changes: (+42 -37)
IA64InstrInfo.td | 79 +--
1 files changed, 42 insertions(+), 37 deletions(-)
Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.20
llvm/lib/Target/IA64/IA64InstrInfo.td:1.21
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.20 Sun Oct 30 19:42:11 2005
+++ llvm/lib/Target/IA64/IA64InstrInfo.td Mon Oct 31 19:29:55 2005
@@ -93,6 +93,48 @@
return true;
}];
+def ADD : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+ add $dst = $src1, $src2;;,
+ [(set GR:$dst, (add GR:$src1, GR:$src2))];
+
+def ADD1 : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+ add $dst = $src1, $src2, 1;;,
+ [(set GR:$dst, (add (add GR:$src1, GR:$src2), 1))];
+
+def ADDS : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
+ adds $dst = $imm, $src1;;,
+ [(set GR:$dst, (add GR:$src1, immSExt14:$imm))];
+
+def MOVL : AForm_DAG0x03, 0x0b, (ops GR:$dst, s64imm:$imm),
+ movl $dst = $imm;;,
+ [(set GR:$dst, imm64:$imm)];
+
+def ADDL_GA : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1,
globaladdress:$imm),
+ addl $dst = $imm, $src1;;,
+ [];
+
+def SUB : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+ sub $dst = $src1, $src2;;,
+ [(set GR:$dst, (sub GR:$src1, GR:$src2))];
+
+def SUB1 : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+ sub $dst = $src1, $src2, 1;;,
+ [(set GR:$dst, (add (sub GR: $src1, GR:$src2), -1))];
+
+let isTwoAddress = 1 in {
+def TPCADDIMM22 : AForm0x03, 0x0b,
+ (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
+($qp) add $dst = $imm, $dst;;;
+def TPCMPIMM8NE : AForm0x03, 0x0b,
+ (ops PR:$dst, PR:$src1, s22imm:$imm, GR:$src2, PR:$qp),
+($qp) cmp.ne $dst , p0 = $imm, $src2;;;
+}
+
+// zero extend a bool (predicate reg) into an integer reg
+def ZXTb : Pat(zext PR:$src),
+ (TPCADDIMM22 (ADDS r0, 0), 1, PR:$src);
+
+// normal sign/zero-extends
def SXT1 : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src), sxt1 $dst = $src;;,
[(set GR:$dst, (sext_inreg GR:$src, i8))];
def ZXT1 : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src), zxt1 $dst = $src;;,
@@ -137,34 +179,6 @@
[(set GR:$dst, (or (and (shl GR:$src1, 32), isMIX4Rable),
(and GR:$src2, isMIX4Rable)))];
-def ADD : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
- add $dst = $src1, $src2;;,
- [(set GR:$dst, (add GR:$src1, GR:$src2))];
-
-def ADD1 : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
- add $dst = $src1, $src2, 1;;,
- [(set GR:$dst, (add (add GR:$src1, GR:$src2), 1))];
-
-def ADDS : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
- adds $dst = $imm, $src1;;,
- [(set GR:$dst, (add GR:$src1, immSExt14:$imm))];
-
-def MOVL : AForm_DAG0x03, 0x0b, (ops GR:$dst, s64imm:$imm),
- movl $dst = $imm;;,
- [(set GR:$dst, imm64:$imm)];
-
-def ADDL_GA : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1,
globaladdress:$imm),
- addl $dst = $imm, $src1;;,
- [];
-
-def SUB : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
- sub $dst = $src1, $src2;;,
- [(set GR:$dst, (sub GR:$src1, GR:$src2))];
-
-def SUB1 : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
- sub $dst = $src1, $src2, 1;;,
- [(set GR:$dst, (add (sub GR: $src1, GR:$src2), -1))];
-
def GETFSIGD : AForm_DAG0x03, 0x0b, (ops GR:$dst, FP:$src),
getf.sig $dst = $src;;,
[];
@@ -424,15 +438,6 @@
def CADDIMM22 : AForm0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
($qp) add $dst = $imm, $src1;;;
-let isTwoAddress = 1 in {
-def TPCADDIMM22 : AForm0x03, 0x0b,
- (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
-($qp) add $dst = $imm, $dst;;;
-def TPCMPIMM8NE : AForm0x03, 0x0b,
- (ops PR:$dst, PR:$src1, s22imm:$imm, GR:$src2, PR:$qp),
-($qp) cmp.ne $dst , p0 = $imm, $src2;;;
-}
-
def SUBIMM8 : AForm0x03, 0x0b, (ops GR:$dst, s8imm:$imm, GR:$src2),
sub $dst = $imm, $src2;;;
___
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.7 - 1.8 --- Log message: add support for int-FP and FP-int ops, and add ia64 patterns for these --- Diffs of the changes: (+11 -0) TargetSelectionDAG.td | 11 +++ 1 files changed, 11 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.7 llvm/lib/Target/TargetSelectionDAG.td:1.8 --- llvm/lib/Target/TargetSelectionDAG.td:1.7 Wed Oct 26 12:00:25 2005 +++ llvm/lib/Target/TargetSelectionDAG.td Mon Oct 31 21:07:25 2005 @@ -94,6 +94,12 @@ def SDTFPExtendOp : SDTypeProfile1, 1, [ // fextend SDTCisFP0, SDTCisFP1, SDTCisOpSmallerThanOp1, 0 ]; +def SDTIntToFPOp : SDTypeProfile1, 1, [ // [su]int_to_fp + SDTCisFP0, SDTCisInt1 +]; +def SDTFPToIntOp : SDTypeProfile1, 1, [ // fp_to_[su]int + SDTCisInt0, SDTCisFP1 +]; def SDTExtInreg : SDTypeProfile1, 2, [ // sext_inreg SDTCisSameAs0, 1, SDTCisInt0, SDTCisVT2, OtherVT, SDTCisVTSmallerThanOp2, 1 @@ -172,6 +178,11 @@ def fround : SDNodeISD::FP_ROUND , SDTFPRoundOp; def fextend: SDNodeISD::FP_EXTEND , SDTFPExtendOp; +def sint_to_fp : SDNodeISD::SINT_TO_FP , SDTIntToFPOp; +def uint_to_fp : SDNodeISD::UINT_TO_FP , SDTIntToFPOp; +def fp_to_sint : SDNodeISD::FP_TO_SINT , SDTFPToIntOp; +def fp_to_uint : SDNodeISD::FP_TO_UINT , SDTFPToIntOp; + def setcc : SDNodeISD::SETCC , SDTSetCC; //===--===// ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64InstrInfo.td updated: 1.21 - 1.22
---
Log message:
add support for int-FP and FP-int ops, and add ia64 patterns for these
---
Diffs of the changes: (+12 -0)
IA64InstrInfo.td | 12
1 files changed, 12 insertions(+)
Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.21
llvm/lib/Target/IA64/IA64InstrInfo.td:1.22
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.21 Mon Oct 31 19:29:55 2005
+++ llvm/lib/Target/IA64/IA64InstrInfo.td Mon Oct 31 21:07:25 2005
@@ -553,6 +553,18 @@
def SETFSIG : AForm0x03, 0x0b, (ops FP:$dst, GR:$src),
setf.sig $dst = $src;;;
+// these four FP-int conversion patterns need checking/cleaning
+def SINT_TO_FP : Pat(sint_to_fp GR:$src),
+ (FNORMD (FCVTXF (SETFSIG GR:$src)));
+def UINT_TO_FP : Pat(uint_to_fp GR:$src),
+ (FNORMD (FCVTXUF (SETFSIG GR:$src)));
+/* FIXME: tablegen coughs on these
+def FP_TO_SINT : Pat(fp_to_sint FP:$src),
+ (GETFSIG (FCVTFXTRUNC FP:$src));
+def FP_TO_UINT : Pat(fp_to_uint FP:$src),
+ (GETFSIG (FCVTFXUTRUNC FP:$src));
+*/
+
let isTerminator = 1, isBranch = 1 in {
def BRL_NOTCALL : RawForm0x03, 0xb0, (ops i64imm:$dst),
(p0) brl.cond.sptk $dst;;;
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.3 - 1.4
---
Log message:
FORTRAN!!! :( and other similarly unfortunate things mean that on ia64
one sometimes needs to pass FP args in both FP *and* integer registers.
---
Diffs of the changes: (+20 -0)
IA64ISelDAGToDAG.cpp | 20
1 files changed, 20 insertions(+)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.3
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.4
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.3 Sat Oct 29 11:08:30 2005
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Mon Oct 31 23:46:16 2005
@@ -208,7 +208,13 @@
CallOpcode = IA64::BRCALL_INDIRECT;
}
+ // see section 8.5.8 of Itanium Software Conventions and
+ // Runtime Architecture Guide to see some examples of what's going
+ // on here. (in short: int args get mapped 1:1 'slot-wise' to out0-out7,
+ // while FP args get mapped to F8-F15 as needed)
+
// TODO: support in-memory arguments
+
unsigned used_FPArgs=0; // how many FP args have been used so far?
unsigned intArgs[] = {IA64::out0, IA64::out1, IA64::out2, IA64::out3,
@@ -236,6 +242,20 @@
Chain = CurDAG-getCopyToReg(Chain, DestReg, Val, InFlag);
InFlag = Chain.getValue(1);
CallOperands.push_back(CurDAG-getRegister(DestReg, RegTy));
+ // some functions (e.g. printf) want floating point arguments
+ // *also* passed as in-memory representations in integer registers
+ // this is FORTRAN legacy junk which we don't _always_ need
+ // to do, but to be on the safe side, we do.
+ if(MVT::isFloatingPoint(N-getOperand(i).getValueType())) {
+assert((i-2) 8 FP args alone would fit, but no int regs left);
+ DestReg = intArgs[i-2]; // this FP arg goes in an int reg
+// GETFD takes an FP reg and writes a GP reg
+ Chain = CurDAG-getTargetNode(IA64::GETFD, MVT::i64, Val, InFlag);
+// FIXME: this next line is a bit unfortunate
+ Chain = CurDAG-getCopyToReg(Chain, DestReg, Chain, InFlag);
+InFlag = Chain.getValue(1);
+CallOperands.push_back(CurDAG-getRegister(DestReg, MVT::i64));
+ }
}
}
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrFormats.td IA64InstrInfo.td
Changes in directory llvm/lib/Target/IA64:
IA64InstrFormats.td updated: 1.2 - 1.3
IA64InstrInfo.td updated: 1.19 - 1.20
---
Log message:
add FP compares and implicit register defs to the dag isel
---
Diffs of the changes: (+45 -23)
IA64InstrFormats.td |4 +++
IA64InstrInfo.td| 64 +---
2 files changed, 45 insertions(+), 23 deletions(-)
Index: llvm/lib/Target/IA64/IA64InstrFormats.td
diff -u llvm/lib/Target/IA64/IA64InstrFormats.td:1.2
llvm/lib/Target/IA64/IA64InstrFormats.td:1.3
--- llvm/lib/Target/IA64/IA64InstrFormats.td:1.2Fri Oct 28 12:46:36 2005
+++ llvm/lib/Target/IA64/IA64InstrFormats.tdSun Oct 30 19:42:11 2005
@@ -72,4 +72,8 @@
class PseudoInstIA64dag OL, string nm : InstIA640, OL, nm {
}
+class PseudoInstIA64_DAGdag OL, string nm, listdag pattern
+ : InstIA640, OL, nm {
+ let Pattern = pattern;
+}
Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.19
llvm/lib/Target/IA64/IA64InstrInfo.td:1.20
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.19 Sun Oct 30 04:14:19 2005
+++ llvm/lib/Target/IA64/IA64InstrInfo.td Sun Oct 30 19:42:11 2005
@@ -200,7 +200,7 @@
// load constants of various sizes // FIXME: prettyprint -ve constants
def : Pat(i64 immSExt14:$imm), (ADDS r0, immSExt14:$imm);
def : Pat(i64 imm64:$imm), (MOVL imm64:$imm);
-// TODO: def : Pat(i1 1), (MOV p0);
+// TODO: def : Pat(i1 1), (stuff);
def AND : AForm_DAG0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
and $dst = $src1, $src2;;,
@@ -290,11 +290,51 @@
cmp.geu $dst, p0 = $src1, $src2;;,
[(set PR:$dst, (setuge GR:$src1, GR:$src2))];
+// and we do the whole thing again for FP compares!
+def FCMPEQ : AForm_DAG0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+ fcmp.eq $dst, p0 = $src1, $src2;;,
+ [(set PR:$dst, (seteq FP:$src1, FP:$src2))];
+def FCMPGT : AForm_DAG0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+ fcmp.gt $dst, p0 = $src1, $src2;;,
+ [(set PR:$dst, (setgt FP:$src1, FP:$src2))];
+def FCMPGE : AForm_DAG0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+ fcmp.ge $dst, p0 = $src1, $src2;;,
+ [(set PR:$dst, (setge FP:$src1, FP:$src2))];
+def FCMPLT : AForm_DAG0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+ fcmp.lt $dst, p0 = $src1, $src2;;,
+ [(set PR:$dst, (setlt FP:$src1, FP:$src2))];
+def FCMPLE : AForm_DAG0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+ fcmp.le $dst, p0 = $src1, $src2;;,
+ [(set PR:$dst, (setle FP:$src1, FP:$src2))];
+def FCMPNE : AForm_DAG0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+ fcmp.neq $dst, p0 = $src1, $src2;;,
+ [(set PR:$dst, (setne FP:$src1, FP:$src2))];
+def FCMPLTU: AForm_DAG0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+ fcmp.ltu $dst, p0 = $src1, $src2;;,
+ [(set PR:$dst, (setult FP:$src1, FP:$src2))];
+def FCMPGTU: AForm_DAG0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+ fcmp.gtu $dst, p0 = $src1, $src2;;,
+ [(set PR:$dst, (setugt FP:$src1, FP:$src2))];
+def FCMPLEU: AForm_DAG0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+ fcmp.leu $dst, p0 = $src1, $src2;;,
+ [(set PR:$dst, (setule FP:$src1, FP:$src2))];
+def FCMPGEU: AForm_DAG0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+ fcmp.geu $dst, p0 = $src1, $src2;;,
+ [(set PR:$dst, (setuge FP:$src1, FP:$src2))];
+
// TODO: support postincrement (reg, imm9) loads+stores - this needs more
// tablegen support
def PHI : PseudoInstIA64(ops variable_ops), PHI;
def IDEF : PseudoInstIA64(ops variable_ops), // IDEF;
+
+def IDEF_GR_D : PseudoInstIA64_DAG(ops GR:$reg), // $reg = IDEF,
+[(set GR:$reg, (undef))];
+def IDEF_FP_D : PseudoInstIA64_DAG(ops FP:$reg), // $reg = IDEF,
+[(set FP:$reg, (undef))];
+def IDEF_PR_D : PseudoInstIA64_DAG(ops PR:$reg), // $reg = IDEF,
+[(set PR:$reg, (undef))];
+
def IUSE : PseudoInstIA64(ops variable_ops), // IUSE;
def ADJUSTCALLSTACKUP : PseudoInstIA64(ops variable_ops),
// ADJUSTCALLSTACKUP;
@@ -365,28 +405,6 @@
def DEPZ : AForm0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1,
u6imm:$imm2), dep.z $dst = $src1, $imm1, $imm2;;;
-// and we do the whole thing again for FP compares!
-def FCMPEQ : AForm0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
- fcmp.eq $dst, p0 = $src1, $src2;;;
-def FCMPGT : AForm0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
- fcmp.gt $dst, p0 = $src1, $src2;;;
-def FCMPGE : AForm0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
- fcmp.ge $dst, p0 = $src1, $src2;;;
-def FCMPLT : AForm0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
- fcmp.lt $dst, p0 = $src1, $src2;;;
-def FCMPLE : AForm0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
- fcmp.le $dst, p0 = $src1, $src2;;;
-def FCMPNE : AForm0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
- fcmp.neq $dst, p0 = $src1, $src2;;;
-def FCMPLTU :
