[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.2 -> 1.3 --- Log message: Use bl to call Thumb fuctions directly. --- Diffs of the changes: (+1 -1) ARMISelLowering.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.2 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.3 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.2 Fri Jan 19 13:28:01 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Mon Jan 22 13:40:10 2007 @@ -483,7 +483,7 @@ getTargetMachine().getRelocationModel() != Reloc::Static; isARMFunc = !Subtarget->isThumb() || isStub; // Wrap it since tBX takes a register source operand. -if (!Subtarget->hasV5TOps() && Subtarget->isThumb()) +if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) Callee = DAG.getNode(ARMISD::WrapperCall, MVT::i32, Callee); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.4 -> 1.5 --- Log message: Propagate changes from my local tree. This patch includes: 1. New parameter attribute called 'inreg'. It has meaning "place this parameter in registers, if possible". This is some generalization of gcc's regparm(n) attribute. It's currently used only in X86-32 backend. 2. Completely rewritten CC handling/lowering code inside X86 backend. Merged stdcall + c CCs and fastcall + fast CC. 3. Dropped CSRET CC. We cannot add struct return variant for each target-specific CC (e.g. stdcall + csretcc and so on). 4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in on first attribute has meaning 'This is hidden pointer to structure return. Handle it gently'. 5. Fixed small bug in llvm-extract + add new feature to FunctionExtraction pass, which relinks all internal-linkaged callees from deleted function to external linkage. This will allow further linking everything together. NOTEs: 1. Documentation will be updated soon. 2. llvm-upgrade should be improved to translate csret => sret. Before this, there will be some unexpected test fails. --- Diffs of the changes: (+0 -1) ARMISelLowering.cpp |1 - 1 files changed, 1 deletion(-) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.4 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.5 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.4 Fri Jan 26 08:34:51 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Sun Jan 28 07:31:35 2007 @@ -352,7 +352,6 @@ SDOperand Chain= Op.getOperand(0); unsigned CallConv = cast(Op.getOperand(1))->getValue(); assert((CallConv == CallingConv::C || - CallConv == CallingConv::CSRet || CallConv == CallingConv::Fast) && "unknown calling convention"); SDOperand Callee = Op.getOperand(4); unsigned NumOps= (Op.getNumOperands() - 5) / 2; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.5 -> 1.6 --- Log message: Finish off bug 680: http://llvm.org/PR680 , allowing targets to custom lower frame and return address nodes. --- Diffs of the changes: (+3 -0) ARMISelLowering.cpp |3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.5 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.6 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.5 Sun Jan 28 07:31:35 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Mon Jan 29 16:58:52 2007 @@ -1130,7 +1130,10 @@ case ISD::SRA: return LowerSRx(Op, DAG, Subtarget); case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); + case ISD::RETURNADDR:break; + case ISD::FRAMEADDR: break; } + return SDOperand(); } //===--===// ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.8 -> 1.9
---
Log message:
Observe -soft-float.
---
Diffs of the changes: (+4 -3)
ARMISelLowering.cpp |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.8
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.9
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.8 Tue Jan 30 14:37:08 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Wed Jan 31 02:40:13 2007
@@ -28,6 +28,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/VectorExtras.h"
using namespace llvm;
@@ -36,7 +37,7 @@
Subtarget = &TM.getSubtarget();
// Uses VFP for Thumb libfuncs if available.
- if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
+ if (!UseSoftFloat && Subtarget->isThumb() && Subtarget->hasVFP2()) {
// Single-precision floating-point arithmetic.
setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
@@ -91,7 +92,7 @@
}
addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
- if (Subtarget->hasVFP2() && !Subtarget->isThumb()) {
+ if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
}
@@ -173,7 +174,7 @@
}
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
- if (Subtarget->hasVFP2() && !Subtarget->isThumb())
+ if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
// Turn f64->i64 into FMRRD iff target supports vfp2.
setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.9 -> 1.10 --- Log message: Specify the right CC for comparison libcalls. --- Diffs of the changes: (+20 -0) ARMISelLowering.cpp | 20 1 files changed, 20 insertions(+) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.9 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.10 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.9 Wed Jan 31 02:40:13 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Wed Jan 31 03:30:58 2007 @@ -58,6 +58,16 @@ setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); +setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); + +setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); +setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); +setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); +setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); +setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); +setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); +setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); +setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); // Double-precision comparisons. setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); @@ -67,6 +77,16 @@ setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); +setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); + +setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); +setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); +setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); +setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); +setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); +setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); +setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); +setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); // Floating-point to integer conversions. // i64 conversions are done via library routines even when generating VFP ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.10 -> 1.11 --- Log message: Thumb does not have clz. --- Diffs of the changes: (+1 -1) ARMISelLowering.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.10 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.11 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.10Wed Jan 31 03:30:58 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Thu Feb 1 17:34:03 2007 @@ -154,7 +154,7 @@ setOperationAction(ISD::ROTL, MVT::i32, Expand); setOperationAction(ISD::CTTZ , MVT::i32, Expand); setOperationAction(ISD::CTPOP, MVT::i32, Expand); - if (!Subtarget->hasV5TOps()) + if (!Subtarget->hasV5TOps() || Subtarget->isThumb()) setOperationAction(ISD::CTLZ, MVT::i32, Expand); // These are expanded into libcalls. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.11 -> 1.12
---
Log message:
Fix a bug in getARMCMP (which translate CondCode to ARM specific CC) when the
RHS is a constant.
---
Diffs of the changes: (+18 -20)
ARMISelLowering.cpp | 38 ++
1 files changed, 18 insertions(+), 20 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.11
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.12
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.11Thu Feb 1 17:34:03 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Thu Feb 1 19:53:26 2007
@@ -859,7 +859,7 @@
return false;
}
-static bool isLegalCmpImmediate(int C, bool isThumb) {
+static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
return ( isThumb && (C & ~255U) == 0) ||
(!isThumb && ARM_AM::getSOImmVal(C) != -1);
}
@@ -869,38 +869,36 @@
static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC,
SDOperand &ARMCC, SelectionDAG &DAG, bool isThumb) {
if (ConstantSDNode *RHSC = dyn_cast(RHS.Val)) {
-int C = (int)RHSC->getValue();
+unsigned C = RHSC->getValue();
if (!isLegalCmpImmediate(C, isThumb)) {
// Constant does not fit, try adjusting it by one?
switch (CC) {
default: break;
case ISD::SETLT:
- case ISD::SETULT:
case ISD::SETGE:
- case ISD::SETUGE:
if (isLegalCmpImmediate(C-1, isThumb)) {
- switch (CC) {
- default: break;
- case ISD::SETLT: CC = ISD::SETLE; break;
- case ISD::SETULT: CC = ISD::SETULE; break;
- case ISD::SETGE: CC = ISD::SETGT; break;
- case ISD::SETUGE: CC = ISD::SETUGT; break;
- }
+ CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
+ RHS = DAG.getConstant(C-1, MVT::i32);
+}
+break;
+ case ISD::SETULT:
+ case ISD::SETUGE:
+if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) {
+ CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
RHS = DAG.getConstant(C-1, MVT::i32);
}
break;
case ISD::SETLE:
- case ISD::SETULE:
case ISD::SETGT:
- case ISD::SETUGT:
if (isLegalCmpImmediate(C+1, isThumb)) {
- switch (CC) {
- default: break;
- case ISD::SETLE: CC = ISD::SETLT; break;
- case ISD::SETULE: CC = ISD::SETULT; break;
- case ISD::SETGT: CC = ISD::SETGE; break;
- case ISD::SETUGT: CC = ISD::SETUGE; break;
- }
+ CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
+ RHS = DAG.getConstant(C+1, MVT::i32);
+}
+break;
+ case ISD::SETULE:
+ case ISD::SETUGT:
+if (C < 0x && isLegalCmpImmediate(C+1, isThumb)) {
+ CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
RHS = DAG.getConstant(C+1, MVT::i32);
}
break;
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.12 -> 1.13
---
Log message:
Fix comments.
---
Diffs of the changes: (+3 -3)
ARMISelLowering.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.12
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.13
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.12Thu Feb 1 19:53:26 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Sat Feb 3 02:53:01 2007
@@ -364,9 +364,9 @@
}
}
-// This transforms a ISD::CALL node into a
-// callseq_star <- ARMISD:CALL <- callseq_end
-// chain
+/// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
+/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
+/// nodes.
SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
MVT::ValueType RetVT= Op.Val->getValueType(0);
SDOperand Chain= Op.getOperand(0);
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.15 -> 1.16 --- Log message: Simplify lowering and selection of exception ops. --- Diffs of the changes: (+0 -3) ARMISelLowering.cpp |3 --- 1 files changed, 3 deletions(-) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.15 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.16 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.15Wed Feb 21 16:54:50 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Thu Feb 22 08:56:36 2007 @@ -1190,9 +1190,6 @@ return LowerFORMAL_ARGUMENTS(Op, DAG); case ISD::RETURNADDR:break; case ISD::FRAMEADDR: break; - // Exception address and exception selector. Currently unimplemented. - case ISD::EXCEPTIONADDR: break; - case ISD::EHSELECTION: break; } return SDOperand(); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.16 -> 1.17
---
Log message:
Fix stack alignment in functions with varargs.
---
Diffs of the changes: (+5 -2)
ARMISelLowering.cpp |7 +--
1 files changed, 5 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.16
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.17
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.16Thu Feb 22 08:56:36 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Fri Feb 23 14:32:57 2007
@@ -831,13 +831,16 @@
SSARegMap *RegMap = MF.getSSARegMap();
MachineFrameInfo *MFI = MF.getFrameInfo();
ARMFunctionInfo *AFI = MF.getInfo();
-unsigned VARegSaveSize = (4 - NumGPRs) * 4;
+unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
+unsigned VARegSize = (4 - NumGPRs) * 4;
+unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
if (VARegSaveSize) {
// If this function is vararg, store any remaining integer argument regs
// to their spots on the stack so that they may be loaded by deferencing
// the result of va_next.
AFI->setVarArgsRegSaveSize(VARegSaveSize);
- VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset);
+ VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
+ VARegSaveSize - VARegSize);
SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
SmallVector MemOps;
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.17 -> 1.18 --- Log message: Use new SDIselParamAttr enumeration. This removes "magick" constants from formal attributes' flags processing. --- Diffs of the changes: (+2 -1) ARMISelLowering.cpp |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.17 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.18 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.17Fri Feb 23 14:32:57 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Tue Mar 6 02:12:33 2007 @@ -27,6 +27,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/SelectionDAG.h" +#include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/VectorExtras.h" @@ -346,7 +347,7 @@ NeededGPRs = 0; StackPad = 0; GPRPad = 0; - unsigned align = (Flags >> 27); + unsigned align = (Flags >> SDISelParamFlags::OrigAlignmentOffs); GPRPad = NumGPRs % ((align + 3)/4); StackPad = StackOffset % align; unsigned firstGPR = NumGPRs + GPRPad; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.18 -> 1.19 --- Log message: Refactoring of formal parameter flags. Enable properly use of zext/sext/aext stuff. --- Diffs of the changes: (+1 -2) ARMISelLowering.cpp |3 +-- 1 files changed, 1 insertion(+), 2 deletions(-) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.18 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.19 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.18Tue Mar 6 02:12:33 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Wed Mar 7 10:25:08 2007 @@ -27,7 +27,6 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/VectorExtras.h" @@ -347,7 +346,7 @@ NeededGPRs = 0; StackPad = 0; GPRPad = 0; - unsigned align = (Flags >> SDISelParamFlags::OrigAlignmentOffs); + unsigned align = (Flags >> ISD::ParamFlags::OrigAlignmentOffs); GPRPad = NumGPRs % ((align + 3)/4); StackPad = StackOffset % align; unsigned firstGPR = NumGPRs + GPRPad; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.19 -> 1.20 --- Log message: Fix a typo. --- Diffs of the changes: (+1 -1) ARMISelLowering.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.19 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.20 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.19Wed Mar 7 10:25:08 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Thu Mar 8 15:59:30 2007 @@ -167,7 +167,7 @@ setOperationAction(ISD::LOCATION, MVT::Other, Expand); setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); // FIXME - use subtarget debug flags - if (Subtarget->isTargetDarwin()) + if (!Subtarget->isTargetDarwin()) setOperationAction(ISD::LABEL, MVT::Other, Expand); setOperationAction(ISD::RET, MVT::Other, Custom); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.21 -> 1.22
---
Log message:
Zero is always a legal AM immediate.
---
Diffs of the changes: (+3 -0)
ARMISelLowering.cpp |3 +++
1 files changed, 3 insertions(+)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.21
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.22
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.21Mon Mar 12 18:30:29 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Tue Mar 13 15:37:59 2007
@@ -1273,6 +1273,9 @@
/// as the offset of the target addressing mode for load / store of the
/// given type.
bool ARMTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty)
const{
+ if (V == 0)
+return true;
+
MVT::ValueType VT = getValueType(Ty);
if (Subtarget->isThumb()) {
if (V < 0)
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.23 -> 1.24 --- Log message: Only ARMv6 has BSWAP. Fix MultiSource/Applications/aha test. --- Diffs of the changes: (+4 -0) ARMISelLowering.cpp |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.23 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.24 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.23Fri Mar 16 03:43:56 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Fri Mar 16 17:54:16 2007 @@ -159,6 +159,10 @@ if (!Subtarget->hasV5TOps() || Subtarget->isThumb()) setOperationAction(ISD::CTLZ, MVT::i32, Expand); + // Only ARMv6 has BSWAP. + if (!Subtarget->hasV6Ops()) + setOperationAction(ISD::BSWAP, MVT::i32, Expand); + // These are expanded into libcalls. setOperationAction(ISD::SDIV, MVT::i32, Expand); setOperationAction(ISD::UDIV, MVT::i32, Expand); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.25 -> 1.26 --- Log message: fix indentation --- Diffs of the changes: (+1 -1) ARMISelLowering.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.25 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.26 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.25Mon Mar 19 02:48:02 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Mon Mar 19 21:25:53 2007 @@ -161,7 +161,7 @@ // Only ARMv6 has BSWAP. if (!Subtarget->hasV6Ops()) - setOperationAction(ISD::BSWAP, MVT::i32, Expand); +setOperationAction(ISD::BSWAP, MVT::i32, Expand); // These are expanded into libcalls. setOperationAction(ISD::SDIV, MVT::i32, Expand); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.31 -> 1.32
---
Log message:
Remove isLegalAddressImmediate.
---
Diffs of the changes: (+0 -14)
ARMISelLowering.cpp | 14 --
1 files changed, 14 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.31
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.32
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.31Tue Mar 27 11:19:21 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Tue Mar 27 20:53:55 2007
@@ -1281,20 +1281,6 @@
// ARM Optimization Hooks
//===--===//
-/// isLegalAddressExpression - Return true if the binary expression made up of
-/// specified opcode, operands, and type can be folded into target addressing
-/// mode for load / store of the given type.
-bool ARMTargetLowering::isLegalAddressExpression(unsigned Opc, Value *Op0,
- Value *Op1, const Type *Ty) const
{
- if (ConstantInt *Op1C = dyn_cast(Op1)) {
-if (Opc == Instruction::Add)
- return isLegalAddressImmediate(Op1C->getSExtValue(), Ty);
-if (Opc == Instruction::Sub)
- return isLegalAddressImmediate(-Op1C->getSExtValue(), Ty);
- }
- return false;
-}
-
/// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode for load / store of the
/// given type.
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.33 -> 1.34
---
Log message:
Add i16 address mode.
---
Diffs of the changes: (+7 -2)
ARMISelLowering.cpp |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.33
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.34
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.33Fri Mar 30 18:15:24 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Sun Apr 1 03:06:46 2007
@@ -1300,19 +1300,24 @@
return false;
default:
-// FIXME: verify.
switch (getValueType(Ty)) {
default: return false;
case MVT::i1:
case MVT::i8:
-// TODO: i16? i64 should be i32, no?
case MVT::i32:
+case MVT::i64:
+ // This assumes i64 is legalized to a pair of i32. If not (i.e.
+ // ldrd / strd are used, then its address mode is same as i16.
// r + r
if (AM.Scale == 2)
return true;
// r + r << imm
if (!isPowerOf2_32(AM.Scale & ~1))
return false;
+case MVT::i16:
+ // r + r
+ if (((unsigned)AM.HasBaseReg + AM.Scale) <= 2)
+return true;
}
break;
}
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.35 -> 1.36
---
Log message:
add support for the 'w' inline asm register class.
---
Diffs of the changes: (+28 -6)
ARMISelLowering.cpp | 34 --
1 files changed, 28 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.35
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.36
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.35Sun Apr 1 20:30:03 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Mon Apr 2 12:24:08 2007
@@ -1598,6 +1598,7 @@
switch (Constraint[0]) {
default: break;
case 'l': return C_RegisterClass;
+case 'w': return C_RegisterClass;
}
}
return TargetLowering::getConstraintType(Constraint);
@@ -1609,12 +1610,17 @@
if (Constraint.size() == 1) {
// GCC RS6000 Constraint Letters
switch (Constraint[0]) {
- case 'l':
- // FIXME: in thumb mode, 'l' is only low-regs.
- // FALL THROUGH.
- case 'r':
-return std::make_pair(0U, ARM::GPRRegisterClass);
-break;
+case 'l':
+// FIXME: in thumb mode, 'l' is only low-regs.
+// FALL THROUGH.
+case 'r':
+ return std::make_pair(0U, ARM::GPRRegisterClass);
+case 'w':
+ if (VT == MVT::f32)
+return std::make_pair(0U, ARM::SPRRegisterClass);
+ if (VT == MVT::f32)
+return std::make_pair(0U, ARM::DPRRegisterClass);
+ break;
}
}
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
@@ -1634,6 +1640,22 @@
ARM::R4, ARM::R5, ARM::R6, ARM::R7,
ARM::R8, ARM::R9, ARM::R10, ARM::R11,
ARM::R12, ARM::LR, 0);
+ case 'w':
+if (VT == MVT::f32)
+ return make_vector(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
+ ARM::S4, ARM::S5, ARM::S6, ARM::S7,
+ ARM::S8, ARM::S9, ARM::S10, ARM::S11,
+ ARM::S12,ARM::S13,ARM::S14,ARM::S15,
+ ARM::S16,ARM::S17,ARM::S18,ARM::S19,
+ ARM::S20,ARM::S21,ARM::S22,ARM::S23,
+ ARM::S24,ARM::S25,ARM::S26,ARM::S27,
+ ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
+if (VT == MVT::f64)
+ return make_vector(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
+ ARM::D4, ARM::D5, ARM::D6, ARM::D7,
+ ARM::D8, ARM::D9, ARM::D10,ARM::D11,
+ ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
+ break;
}
return std::vector();
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.36 -> 1.37 --- Log message: fix the CodeGen/ARM/2007-03-13-InstrSched.ll regression: allow IV's with scales to be folded into non-store instructions. --- Diffs of the changes: (+20 -4) ARMISelLowering.cpp | 24 1 files changed, 20 insertions(+), 4 deletions(-) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.36 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.37 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.36Mon Apr 2 12:24:08 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Mon Apr 2 13:51:18 2007 @@ -1332,6 +1332,15 @@ // r + r if (((unsigned)AM.HasBaseReg + AM.Scale) <= 2) return true; + +case MVT::isVoid: + // Note, we allow "void" uses (basically, uses that aren't loads or + // stores), because arm allows folding a scale into many arithmetic + // operations. This should be made more precise and revisited later. + + // Allow r << imm, but the imm has to be a multiple of two. + if (AM.Scale & 1) return false; + return isPowerOf2_32(AM.Scale); } break; } @@ -1413,12 +1422,19 @@ case MVT::i1: case MVT::i8: case MVT::i32: -// r + r -if (S == 2) - return true; -// r + r << imm +// Allow: r + r +// Allow: r << imm +// Allow: r + r << imm S &= ~1; return isPowerOf2_32(S); + case MVT::isVoid: +// Note, we allow "void" uses (basically, uses that aren't loads or +// stores), because arm allows folding a scale into many arithmetic +// operations. This should be made more precise and revisited later. + +// Allow r << imm, but the imm has to be a multiple of two. +if (S & 1) return false; +return isPowerOf2_32(S); } } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.37 -> 1.38 --- Log message: Arm supports negative strides as well, add them. This lets us compile: CodeGen/ARM/arm-negative-stride.ll to: LBB1_2: @bb str r1, [r3, -r0, lsl #2] add r0, r0, #1 cmp r0, r2 bne LBB1_2 @bb --- Diffs of the changes: (+6 -3) ARMISelLowering.cpp |9 ++--- 1 files changed, 6 insertions(+), 3 deletions(-) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.37 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.38 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.37Mon Apr 2 13:51:18 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Mon Apr 2 19:13:57 2007 @@ -1323,7 +1323,7 @@ // This assumes i64 is legalized to a pair of i32. If not (i.e. // ldrd / strd are used, then its address mode is same as i16. // r + r - if (AM.Scale == 2) + if (AM.Scale == 1) return true; // r + r << imm if (!isPowerOf2_32(AM.Scale & ~1)) @@ -1422,7 +1422,9 @@ case MVT::i1: case MVT::i8: case MVT::i32: -// Allow: r + r +if (S < 0) S = -S; +if (S == 1) return true; // Allow: r + r + // Allow: r << imm // Allow: r + r << imm S &= ~1; @@ -1431,7 +1433,8 @@ // Note, we allow "void" uses (basically, uses that aren't loads or // stores), because arm allows folding a scale into many arithmetic // operations. This should be made more precise and revisited later. - +if (S == 1) return true; // Allow: r + r + // Allow r << imm, but the imm has to be a multiple of two. if (S & 1) return false; return isPowerOf2_32(S); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.38 -> 1.39 --- Log message: Typo. --- Diffs of the changes: (+1 -1) ARMISelLowering.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.38 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.39 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.38Mon Apr 2 19:13:57 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Tue Apr 3 19:06:07 2007 @@ -1637,7 +1637,7 @@ case 'w': if (VT == MVT::f32) return std::make_pair(0U, ARM::SPRRegisterClass); - if (VT == MVT::f32) + if (VT == MVT::f64) return std::make_pair(0U, ARM::DPRRegisterClass); break; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.41 -> 1.42
---
Log message:
restore support for negative strides
---
Diffs of the changes: (+5 -3)
ARMISelLowering.cpp |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.41
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.42
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.41Mon Apr 9 18:33:39 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Mon Apr 9 22:48:29 2007
@@ -1372,6 +1372,7 @@
return false;
default:
+int Scale = AM.Scale;
switch (getValueType(Ty)) {
default: return false;
case MVT::i1:
@@ -1381,14 +1382,15 @@
// This assumes i64 is legalized to a pair of i32. If not (i.e.
// ldrd / strd are used, then its address mode is same as i16.
// r + r
- if (AM.Scale == 1)
+ if (Scale < 0) Scale = -Scale;
+ if (Scale == 1)
return true;
// r + r << imm
- if (!isPowerOf2_32(AM.Scale & ~1))
+ if (!isPowerOf2_32(Scale & ~1))
return false;
case MVT::i16:
// r + r
- if (((unsigned)AM.HasBaseReg + AM.Scale) <= 2)
+ if (((unsigned)AM.HasBaseReg + Scale) <= 2)
return true;
case MVT::isVoid:
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.42 -> 1.43 --- Log message: Fix incorrect fall-throughs in addr mode code. This fixes CodeGen/ARM/arm-negative-stride.ll --- Diffs of the changes: (+3 -3) ARMISelLowering.cpp |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.42 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.43 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.42Mon Apr 9 22:48:29 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Wed Apr 11 11:17:12 2007 @@ -1386,13 +1386,13 @@ if (Scale == 1) return true; // r + r << imm - if (!isPowerOf2_32(Scale & ~1)) -return false; + return isPowerOf2_32(Scale & ~1); case MVT::i16: // r + r if (((unsigned)AM.HasBaseReg + Scale) <= 2) return true; - + return false; + case MVT::isVoid: // Note, we allow "void" uses (basically, uses that aren't loads or // stores), because arm allows folding a scale into many arithmetic ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.43 -> 1.44
---
Log message:
arm has r+r*s and r+i addr modes, but no r+i+r*s addr modes.
---
Diffs of the changes: (+5 -1)
ARMISelLowering.cpp |6 +-
1 files changed, 5 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.43
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.44
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.43Wed Apr 11 11:17:12 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Fri Apr 13 01:50:55 2007
@@ -1370,8 +1370,12 @@
case 1:
if (Subtarget->isThumb())
return false;
-
+// FALL THROUGH.
default:
+// ARM doesn't support any R+R*scale+imm addr modes.
+if (AM.BaseOffs)
+ return false;
+
int Scale = AM.Scale;
switch (getValueType(Ty)) {
default: return false;
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.45 -> 1.46
---
Log message:
Darwin runtime library does not have these.
---
Diffs of the changes: (+79 -73)
ARMISelLowering.cpp | 152 +++-
1 files changed, 79 insertions(+), 73 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.45
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.46
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.45Sat Apr 21 19:04:12 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Fri Apr 27 03:15:43 2007
@@ -38,79 +38,85 @@
: TargetLowering(TM), ARMPCLabelIndex(0) {
Subtarget = &TM.getSubtarget();
- // Uses VFP for Thumb libfuncs if available.
- if (!UseSoftFloat && Subtarget->isThumb() && Subtarget->hasVFP2()) {
-// Single-precision floating-point arithmetic.
-setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
-setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
-setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
-setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
-
-// Double-precision floating-point arithmetic.
-setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
-setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
-setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
-setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
-
-// Single-precision comparisons.
-setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
-setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
-setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
-setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
-setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
-setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
-setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
-setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
-
-setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
-setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
-setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
-setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
-setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
-setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
-setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
-setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
-
-// Double-precision comparisons.
-setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
-setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
-setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
-setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
-setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
-setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
-setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
-setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
-
-setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
-setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
-setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
-setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
-setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
-setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
-setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
-setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
-
-// Floating-point to integer conversions.
-// i64 conversions are done via library routines even when generating VFP
-// instructions, so use the same ones.
-setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
-setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
-setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
-setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
-
-// Conversions between floating types.
-setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
-setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
-
-// Integer to floating-point conversions.
-// i64 conversions are done via library routines even when generating VFP
-// instructions, so use the same ones.
-// FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g.
-// __floatunsidf vs. __floatunssidfvfp.
-setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
-setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
-setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
-setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
+ if (Subtarget->isTargetDarwin()) {
+// Don't have these.
+setLibcallName(RTLIB::UINTTOFP_I64_F32, NULL);
+setLibcallName(RTLIB::UINTTOFP_I64_F64, NULL);
+
+// Uses VFP for Thumb libfuncs if available.
+if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
+ // Single-precision floating-point arithmetic.
+ setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
+ setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
+ setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
+ setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
+
+ // Double-precision floating-point arithmetic.
+ setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
+ setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
+ setLibcallName(RTLIB::MUL_F64, "__muld
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.47 -> 1.48 --- Log message: Typo. It's checking if V is multiple of 4, not multiple of 3. :-) --- Diffs of the changes: (+1 -1) ARMISelLowering.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.47 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.48 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.47Fri Apr 27 08:54:47 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Wed May 2 21:00:18 2007 @@ -1486,7 +1486,7 @@ case MVT::f64: if (!Subtarget->hasVFP2()) return false; -if ((V % 3) != 0) +if ((V & 3) != 0) return false; V >>= 2; return V == V & ((1LL << 8) - 1); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.49 -> 1.50
---
Log message:
On Mac OS X, GV requires an extra load only when relocation-model is non-static.
---
Diffs of the changes: (+6 -5)
ARMISelLowering.cpp | 11 ++-
1 files changed, 6 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.49
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.50
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.49Thu May 3 15:28:35 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Thu May 3 19:26:58 2007
@@ -812,10 +812,11 @@
}
/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
-/// even in dynamic-no-pic mode.
-static bool GVIsIndirectSymbol(GlobalValue *GV) {
- return (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
- (GV->isDeclaration() && !GV->hasNotBeenReadFromBytecode()));
+/// even in non-static mode.
+static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
+ return RelocM != Reloc::Static &&
+(GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
+ (GV->isDeclaration() && !GV->hasNotBeenReadFromBytecode()));
}
SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op,
@@ -823,7 +824,7 @@
MVT::ValueType PtrVT = getPointerTy();
GlobalValue *GV = cast(Op)->getGlobal();
Reloc::Model RelocM = getTargetMachine().getRelocationModel();
- bool IsIndirect = GVIsIndirectSymbol(GV);
+ bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
SDOperand CPAddr;
if (RelocM == Reloc::Static)
CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.50 -> 1.51
---
Log message:
Optimize PIC implementation. GOTOFF can be used when the symbol is defined
and used in the same module.
---
Diffs of the changes: (+1 -1)
ARMISelLowering.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.50
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.51
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.50Thu May 3 19:26:58 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Mon May 14 13:46:23 2007
@@ -792,7 +792,7 @@
GlobalValue *GV = cast(Op)->getGlobal();
Reloc::Model RelocM = getTargetMachine().getRelocationModel();
if (RelocM == Reloc::PIC_) {
-bool UseGOTOFF = GV->hasInternalLinkage();
+bool UseGOTOFF = !GV->isDeclaration();
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.51 -> 1.52
---
Log message:
Fix previous patch. GOTOFF can be used only when the symbol has internal
linkage or hidden visibility.
---
Diffs of the changes: (+1 -1)
ARMISelLowering.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.51
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.52
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.51Mon May 14 13:46:23 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Mon May 14 18:20:21 2007
@@ -792,7 +792,7 @@
GlobalValue *GV = cast(Op)->getGlobal();
Reloc::Model RelocM = getTargetMachine().getRelocationModel();
if (RelocM == Reloc::PIC_) {
-bool UseGOTOFF = !GV->isDeclaration();
+bool UseGOTOFF = GV->hasInternalLinkage() || GV->hasHiddenVisibility();
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.53 -> 1.54 --- Log message: Set ARM if-conversion block size threshold to 10 instructions for now. --- Diffs of the changes: (+2 -2) ARMISelLowering.cpp |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.53 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.54 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.53Thu May 17 16:31:21 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Thu May 17 19:19:34 2007 @@ -124,6 +124,7 @@ addRegisterClass(MVT::f32, ARM::SPRRegisterClass); addRegisterClass(MVT::f64, ARM::DPRRegisterClass); } + computeRegisterProperties(); // ARM does not have f32 extending load. setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); @@ -252,9 +253,8 @@ setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); setStackPointerRegisterToSaveRestore(ARM::SP); - setSchedulingPreference(SchedulingForRegPressure); - computeRegisterProperties(); + setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10); maxStoresPerMemcpy = 1; temporary - rewrite interface to use type } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.54 -> 1.55
---
Log message:
Silence some compilation warnings.
---
Diffs of the changes: (+2 -2)
ARMISelLowering.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.54
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.55
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.54Thu May 17 19:19:34 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Thu May 17 20:19:57 2007
@@ -1369,7 +1369,7 @@
unsigned SrcOff = 0, DstOff = 0;
MVT::ValueType VT = MVT::i32;
unsigned VTSize = 4;
- const int MAX_LOADS_IN_LDM = 6;
+ const unsigned MAX_LOADS_IN_LDM = 6;
SDOperand LoadChains[MAX_LOADS_IN_LDM];
SDOperand Loads[MAX_LOADS_IN_LDM];
@@ -1377,7 +1377,7 @@
// number of stores. The loads and stores will get combined into
// ldm/stm later on.
while(EmittedNumMemOps < NumMemOps) {
-unsigned int i;
+unsigned i;
for (i=0; ihttp://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.55 -> 1.56 --- Log message: Set ARM ifcvt duplication limit to 3 for now. --- Diffs of the changes: (+1 -0) ARMISelLowering.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.55 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.56 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.55Thu May 17 20:19:57 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Fri Jun 1 03:28:59 2007 @@ -255,6 +255,7 @@ setStackPointerRegisterToSaveRestore(ARM::SP); setSchedulingPreference(SchedulingForRegPressure); setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10); + setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 3); maxStoresPerMemcpy = 1; temporary - rewrite interface to use type } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.57 -> 1.58 --- Log message: Be more conservative of duplicating blocks. --- Diffs of the changes: (+1 -1) ARMISelLowering.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.57 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.58 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.57Tue Jun 19 16:05:09 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Tue Jun 19 18:55:02 2007 @@ -255,7 +255,7 @@ setStackPointerRegisterToSaveRestore(ARM::SP); setSchedulingPreference(SchedulingForRegPressure); setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10); - setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 3); + setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2); maxStoresPerMemcpy = 1; temporary - rewrite interface to use type } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.59 -> 1.60 --- Log message: Silence a warning. --- Diffs of the changes: (+2 -1) ARMISelLowering.cpp |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.59 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.60 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.59Fri Jun 22 09:59:07 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Tue Jun 26 13:31:22 2007 @@ -1195,7 +1195,8 @@ Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy)); SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; - Addr = DAG.getLoad(isPIC ? MVT::i32 : PTy, Chain, Addr, NULL, 0); + Addr = DAG.getLoad(isPIC ? (MVT::ValueType)MVT::i32 : PTy, + Chain, Addr, NULL, 0); Chain = Addr.getValue(1); if (isPIC) Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMTargetMachine.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.13 -> 1.14
ARMTargetMachine.cpp updated: 1.20 -> 1.21
---
Log message:
According to ARM EABI, 8-bytes function arguments must be 8-bytes aligned.
---
Diffs of the changes: (+53 -30)
ARMISelLowering.cpp | 79 ---
ARMTargetMachine.cpp |4 +-
2 files changed, 53 insertions(+), 30 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.13
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.14
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.13Sat Feb 3 02:53:01 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Tue Feb 13 08:07:13 2007
@@ -338,29 +338,36 @@
}
static void
-HowToPassArgument(MVT::ValueType ObjectVT,
- unsigned NumGPRs, unsigned &ObjSize, unsigned &ObjGPRs) {
- ObjSize = 0;
- ObjGPRs = 0;
-
+HowToPassArgument(MVT::ValueType ObjectVT, unsigned NumGPRs,
+ unsigned StackOffset, unsigned &NeededGPRs,
+ unsigned &NeededStackSize, unsigned &GPRPad,
+ unsigned &StackPad, unsigned Flags) {
+ NeededStackSize = 0;
+ NeededGPRs = 0;
+ StackPad = 0;
+ GPRPad = 0;
+ unsigned align = (Flags >> 27);
+ GPRPad = NumGPRs % ((align + 3)/4);
+ StackPad = StackOffset % align;
+ unsigned firstGPR = NumGPRs + GPRPad;
switch (ObjectVT) {
default: assert(0 && "Unhandled argument type!");
case MVT::i32:
case MVT::f32:
-if (NumGPRs < 4)
- ObjGPRs = 1;
+if (firstGPR < 4)
+ NeededGPRs = 1;
else
- ObjSize = 4;
+ NeededStackSize = 4;
break;
case MVT::i64:
case MVT::f64:
-if (NumGPRs < 3)
- ObjGPRs = 2;
-else if (NumGPRs == 3) {
- ObjGPRs = 1;
- ObjSize = 4;
+if (firstGPR < 3)
+ NeededGPRs = 2;
+else if (firstGPR == 3) {
+ NeededGPRs = 1;
+ NeededStackSize = 4;
} else
- ObjSize = 8;
+ NeededStackSize = 8;
}
}
@@ -383,12 +390,16 @@
// Add up all the space actually used.
for (unsigned i = 0; i < NumOps; ++i) {
-unsigned ObjSize = 0;
-unsigned ObjGPRs = 0;
+unsigned ObjSize;
+unsigned ObjGPRs;
+unsigned StackPad;
+unsigned GPRPad;
MVT::ValueType ObjectVT = Op.getOperand(5+2*i).getValueType();
-HowToPassArgument(ObjectVT, NumGPRs, ObjSize, ObjGPRs);
-NumBytes += ObjSize;
-NumGPRs += ObjGPRs;
+unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
+HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize,
+ GPRPad, StackPad, Flags);
+NumBytes += ObjSize + StackPad;
+NumGPRs += ObjGPRs + GPRPad;
}
// Adjust the stack pointer for the new arguments...
@@ -407,18 +418,24 @@
std::vector MemOpChains;
for (unsigned i = 0; i != NumOps; ++i) {
SDOperand Arg = Op.getOperand(5+2*i);
+unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
MVT::ValueType ArgVT = Arg.getValueType();
-unsigned ObjSize = 0;
-unsigned ObjGPRs = 0;
-HowToPassArgument(ArgVT, NumGPRs, ObjSize, ObjGPRs);
+unsigned ObjSize;
+unsigned ObjGPRs;
+unsigned GPRPad;
+unsigned StackPad;
+HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs,
+ ObjSize, GPRPad, StackPad, Flags);
+NumGPRs += GPRPad;
+ArgOffset += StackPad;
if (ObjGPRs > 0) {
switch (ArgVT) {
default: assert(0 && "Unexpected ValueType for argument!");
case MVT::i32:
RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg));
break;
- case MVT::f32:
+ case MVT::f32:
RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs],
DAG.getNode(ISD::BIT_CONVERT, MVT::i32,
Arg)));
break;
@@ -436,7 +453,7 @@
MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0));
}
break;
- }
+ }
case MVT::f64: {
SDOperand Cvt = DAG.getNode(ARMISD::FMRRD,
DAG.getVTList(MVT::i32, MVT::i32),
@@ -715,7 +732,7 @@
}
static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
- unsigned *vRegs, unsigned ArgNo,
+ unsigned *vRegs, unsigned ArgNo,
unsigned &NumGPRs, unsigned &ArgOffset) {
MachineFunction &MF = DAG.getMachineFunction();
MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
@@ -727,9 +744,15 @@
ARM::R0, ARM::R1, ARM::R2, ARM::R3
};
- unsigned ObjSize = 0;
- unsigned ObjGPRs = 0;
- HowToPassArgument(ObjectVT, NumGPRs, ObjSize, ObjGPRs);
+ unsigned ObjSize;
+ unsigned ObjGPRs;
+ unsigned GPRPad;
+ unsigned StackPad;
+ unsigned Flags = Op.getConstantOperandVal(ArgNo + 3);
+ HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs,
+ObjSize, GPRPad, StackPad, Flags);
+ NumGPRs += GPRPad;
+ Arg
Re: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
> @@ -27,6 +27,7 @@ > #include "llvm/CodeGen/MachineFunction.h" > #include "llvm/CodeGen/MachineInstrBuilder.h" > #include "llvm/CodeGen/SelectionDAG.h" > +#include "llvm/CodeGen/SelectionDAGISel.h" Please put the enum into SelectionDAGNodes.h so that SDISel.h doesn't need to be pulled into other code like this. Thanks, -Chris > #include "llvm/CodeGen/SSARegMap.h" > #include "llvm/Target/TargetOptions.h" > #include "llvm/ADT/VectorExtras.h" > @@ -346,7 +347,7 @@ >NeededGPRs = 0; >StackPad = 0; >GPRPad = 0; > - unsigned align = (Flags >> 27); > + unsigned align = (Flags >> SDISelParamFlags::OrigAlignmentOffs); >GPRPad = NumGPRs % ((align + 3)/4); >StackPad = StackOffset % align; >unsigned firstGPR = NumGPRs + GPRPad; > > > > ___ > llvm-commits mailing list > llvm-commits@cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMISelLowering.h
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.20 -> 1.21
ARMISelLowering.h updated: 1.2 -> 1.3
---
Log message:
Updated TargetLowering LSR addressing mode hooks for ARM and Thumb.
---
Diffs of the changes: (+88 -8)
ARMISelLowering.cpp | 81
ARMISelLowering.h | 15 +++--
2 files changed, 88 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.20
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.21
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.20Thu Mar 8 15:59:30 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Mon Mar 12 18:30:29 2007
@@ -30,6 +30,7 @@
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/VectorExtras.h"
+#include "llvm/Support/MathExtras.h"
using namespace llvm;
ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
@@ -1268,17 +1269,87 @@
// ARM Optimization Hooks
//===--===//
-/// isLegalAddressImmediate - Return true if the integer value or
-/// GlobalValue can be used as the offset of the target addressing mode.
-bool ARMTargetLowering::isLegalAddressImmediate(int64_t V) const {
- // ARM allows a 12-bit immediate field.
- return V == V & ((1LL << 12) - 1);
+/// isLegalAddressImmediate - Return true if the integer value can be used
+/// as the offset of the target addressing mode for load / store of the
+/// given type.
+bool ARMTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty)
const{
+ MVT::ValueType VT = getValueType(Ty);
+ if (Subtarget->isThumb()) {
+if (V < 0)
+ return false;
+
+unsigned Scale = 1;
+switch (VT) {
+default: return false;
+case MVT::i1:
+case MVT::i8:
+ // Scale == 1;
+ break;
+case MVT::i16:
+ // Scale == 2;
+ Scale = 2;
+ break;
+case MVT::i32:
+ // Scale == 4;
+ Scale = 4;
+ break;
+}
+
+if ((V & (Scale - 1)) != 0)
+ return false;
+V /= Scale;
+return V == V & ((1LL << 5) - 1);
+ }
+
+ if (V < 0)
+V = - V;
+ switch (VT) {
+ default: return false;
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i32:
+// +- imm12
+return V == V & ((1LL << 12) - 1);
+ case MVT::i16:
+// +- imm8
+return V == V & ((1LL << 8) - 1);
+ case MVT::f32:
+ case MVT::f64:
+if (!Subtarget->hasVFP2())
+ return false;
+if ((V % 3) != 0)
+ return false;
+V >>= 2;
+return V == V & ((1LL << 8) - 1);
+ }
}
bool ARMTargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
return false;
}
+/// isLegalAddressScale - Return true if the integer value can be used as
+/// the scale of the target addressing mode for load / store of the given
+/// type.
+bool ARMTargetLowering::isLegalAddressScale(int64_t S, const Type *Ty) const {
+ if (Subtarget->isThumb())
+return false;
+
+ MVT::ValueType VT = getValueType(Ty);
+ switch (VT) {
+ default: return false;
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i32:
+// r + r
+if (S == 2)
+ return true;
+// r + r << imm
+S &= ~1;
+return isPowerOf2_32(S);
+ }
+}
+
static bool getIndexedAddressParts(SDNode *Ptr, MVT::ValueType VT,
bool isSEXTLoad, SDOperand &Base,
SDOperand &Offset, bool &isInc,
Index: llvm/lib/Target/ARM/ARMISelLowering.h
diff -u llvm/lib/Target/ARM/ARMISelLowering.h:1.2
llvm/lib/Target/ARM/ARMISelLowering.h:1.3
--- llvm/lib/Target/ARM/ARMISelLowering.h:1.2 Tue Jan 30 14:37:08 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.h Mon Mar 12 18:30:29 2007
@@ -80,11 +80,20 @@
virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *MBB);
-/// isLegalAddressImmediate - Return true if the integer value or
-/// GlobalValue can be used as the offset of the target addressing mode.
-virtual bool isLegalAddressImmediate(int64_t V) const;
+/// isLegalAddressImmediate - Return true if the integer value can be used
+/// as the offset of the target addressing mode for load / store of the
+/// given type.
+virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
+
+/// isLegalAddressImmediate - Return true if the GlobalValue can be used as
+/// the offset of the target addressing mode.
virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
+/// isLegalAddressScale - Return true if the integer value can be used as
+/// the scale of the target addressing mode for load / store of the given
+/// type.
+virtual bool isLegalAddressScale(int64_t S, const Type *Ty) const;
+
/// getPreIndexedAddressParts - returns true by value, base pointer and
/// offset pointer and addressing
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMISelLowering.h
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.22 -> 1.23
ARMISelLowering.h updated: 1.3 -> 1.4
---
Log message:
Added isLegalAddressExpression(). Only allows X +/- C for now.
---
Diffs of the changes: (+21 -0)
ARMISelLowering.cpp | 15 +++
ARMISelLowering.h |6 ++
2 files changed, 21 insertions(+)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.22
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.23
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.22Tue Mar 13 15:37:59 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Fri Mar 16 03:43:56 2007
@@ -22,6 +22,7 @@
#include "ARMTargetMachine.h"
#include "llvm/CallingConv.h"
#include "llvm/Constants.h"
+#include "llvm/Instruction.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
@@ -1269,6 +1270,20 @@
// ARM Optimization Hooks
//===--===//
+/// isLegalAddressExpression - Return true if the binary expression made up of
+/// specified opcode, operands, and type can be folded into target addressing
+/// mode for load / store of the given type.
+bool ARMTargetLowering::isLegalAddressExpression(unsigned Opc, Value *Op0,
+ Value *Op1, const Type *Ty) const
{
+ if (ConstantInt *Op1C = dyn_cast(Op1)) {
+if (Opc == Instruction::Add)
+ return isLegalAddressImmediate(Op1C->getSExtValue(), Ty);
+if (Opc == Instruction::Sub)
+ return isLegalAddressImmediate(-Op1C->getSExtValue(), Ty);
+ }
+ return false;
+}
+
/// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode for load / store of the
/// given type.
Index: llvm/lib/Target/ARM/ARMISelLowering.h
diff -u llvm/lib/Target/ARM/ARMISelLowering.h:1.3
llvm/lib/Target/ARM/ARMISelLowering.h:1.4
--- llvm/lib/Target/ARM/ARMISelLowering.h:1.3 Mon Mar 12 18:30:29 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.h Fri Mar 16 03:43:56 2007
@@ -80,6 +80,12 @@
virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *MBB);
+/// isLegalAddressExpression - Return true if the binary expression made up
+/// of specified opcode, operands, and type can be folded into target
+/// addressing mode for load / store of the given type.
+virtual bool isLegalAddressExpression(unsigned Opc, Value *Op0, Value *Op1,
+ const Type *Ty) const;
+
/// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode for load / store of the
/// given type.
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMISelLowering.h
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.29 -> 1.30
ARMISelLowering.h updated: 1.7 -> 1.8
---
Log message:
switch TargetLowering::getConstraintType to take the entire constraint,
not just the first letter. No functionality change.
---
Diffs of the changes: (+8 -6)
ARMISelLowering.cpp | 12 +++-
ARMISelLowering.h |2 +-
2 files changed, 8 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.29
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.30
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.29Wed Mar 21 16:51:52 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Sat Mar 24 21:14:49 2007
@@ -1550,12 +1550,14 @@
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
ARMTargetLowering::ConstraintType
-ARMTargetLowering::getConstraintType(char ConstraintLetter) const {
- switch (ConstraintLetter) {
-case 'l':
- return C_RegisterClass;
-default: return TargetLowering::getConstraintType(ConstraintLetter);
+ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
+ if (Constraint.size() == 1) {
+switch (Constraint[0]) {
+default: break;
+case 'l': return C_RegisterClass;
+}
}
+ return TargetLowering::getConstraintType(Constraint);
}
std::pair
Index: llvm/lib/Target/ARM/ARMISelLowering.h
diff -u llvm/lib/Target/ARM/ARMISelLowering.h:1.7
llvm/lib/Target/ARM/ARMISelLowering.h:1.8
--- llvm/lib/Target/ARM/ARMISelLowering.h:1.7 Wed Mar 21 16:51:52 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.h Sat Mar 24 21:14:49 2007
@@ -133,7 +133,7 @@
uint64_t &KnownZero,
uint64_t &KnownOne,
unsigned Depth) const;
-ConstraintType getConstraintType(char ConstraintLetter) const;
+ConstraintType getConstraintType(const std::string &Constraint) const;
std::pair
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMISelLowering.h
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.32 -> 1.33
ARMISelLowering.h updated: 1.9 -> 1.10
---
Log message:
implement the new addressing mode description hook.
---
Diffs of the changes: (+42 -0)
ARMISelLowering.cpp | 38 ++
ARMISelLowering.h |4
2 files changed, 42 insertions(+)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.32
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.33
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.32Tue Mar 27 20:53:55 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Fri Mar 30 18:15:24 2007
@@ -1281,6 +1281,44 @@
// ARM Optimization Hooks
//===--===//
+/// isLegalAddressingMode - Return true if the addressing mode represented
+/// by AM is legal for this target, for a load/store of the specified type.
+bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
+ const Type *Ty) const {
+ if (!isLegalAddressImmediate(AM.BaseOffs, Ty))
+return false;
+
+ // Can never fold addr of global into load/store.
+ if (AM.BaseGV)
+return false;
+
+ switch (AM.Scale) {
+ case 0: // no scale reg, must be "r+i" or "r", or "i".
+break;
+ case 1:
+if (Subtarget->isThumb())
+ return false;
+
+ default:
+// FIXME: verify.
+switch (getValueType(Ty)) {
+default: return false;
+case MVT::i1:
+case MVT::i8:
+// TODO: i16? i64 should be i32, no?
+case MVT::i32:
+ // r + r
+ if (AM.Scale == 2)
+return true;
+ // r + r << imm
+ if (!isPowerOf2_32(AM.Scale & ~1))
+return false;
+}
+break;
+ }
+ return true;
+}
+
/// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode for load / store of the
/// given type.
Index: llvm/lib/Target/ARM/ARMISelLowering.h
diff -u llvm/lib/Target/ARM/ARMISelLowering.h:1.9
llvm/lib/Target/ARM/ARMISelLowering.h:1.10
--- llvm/lib/Target/ARM/ARMISelLowering.h:1.9 Tue Mar 27 20:52:29 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.h Fri Mar 30 18:15:24 2007
@@ -80,6 +80,10 @@
virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *MBB);
+/// isLegalAddressingMode - Return true if the addressing mode represented
+/// by AM is legal for this target, for a load/store of the specified type.
+virtual bool isLegalAddressingMode(const AddrMode &AM, const Type
*Ty)const;
+
/// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode for load / store of the
/// given type.
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMISelLowering.h
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.39 -> 1.40
ARMISelLowering.h updated: 1.11 -> 1.12
---
Log message:
remove some dead target hooks, subsumed by isLegalAddressingMode
---
Diffs of the changes: (+0 -30)
ARMISelLowering.cpp | 18 --
ARMISelLowering.h | 12
2 files changed, 30 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.39
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.40
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.39Tue Apr 3 19:06:07 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Mon Apr 9 17:25:41 2007
@@ -1441,24 +1441,6 @@
}
}
-/// isLegalAddressScaleAndImm - Return true if S works for IsLegalAddressScale
-/// and V works for isLegalAddressImmediate _and_ both can be applied
-/// simultaneously to the same instruction.
-bool ARMTargetLowering::isLegalAddressScaleAndImm(int64_t S, int64_t V,
- const Type* Ty) const {
- if (V == 0)
-return isLegalAddressScale(S, Ty);
- return false;
-}
-
-/// isLegalAddressScaleAndImm - Return true if S works for IsLegalAddressScale
-/// and GV works for isLegalAddressImmediate _and_ both can be applied
-/// simultaneously to the same instruction.
-bool ARMTargetLowering::isLegalAddressScaleAndImm(int64_t S, GlobalValue *GV,
- const Type* Ty) const {
- return false;
-}
-
static bool getIndexedAddressParts(SDNode *Ptr, MVT::ValueType VT,
bool isSEXTLoad, SDOperand &Base,
SDOperand &Offset, bool &isInc,
Index: llvm/lib/Target/ARM/ARMISelLowering.h
diff -u llvm/lib/Target/ARM/ARMISelLowering.h:1.11
llvm/lib/Target/ARM/ARMISelLowering.h:1.12
--- llvm/lib/Target/ARM/ARMISelLowering.h:1.11 Sun Apr 1 20:30:03 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.h Mon Apr 9 17:25:41 2007
@@ -99,18 +99,6 @@
/// type.
virtual bool isLegalAddressScale(int64_t S, const Type *Ty) const;
-/// isLegalAddressScaleAndImm - Return true if S works for
-/// IsLegalAddressScale and V works for isLegalAddressImmediate _and_
-/// both can be applied simultaneously to the same instruction.
-virtual bool isLegalAddressScaleAndImm(int64_t S, int64_t V,
- const Type *Ty) const;
-
-/// isLegalAddressScaleAndImm - Return true if S works for
-/// IsLegalAddressScale and GV works for isLegalAddressImmediate _and_
-/// both can be applied simultaneously to the same instruction.
-virtual bool isLegalAddressScaleAndImm(int64_t S, GlobalValue *GV,
- const Type *Ty) const;
-
/// getPreIndexedAddressParts - returns true by value, base pointer and
/// offset pointer and addressing mode by reference if the node's address
/// can be legally represented as pre-indexed load / store address.
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMISelLowering.h
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.40 -> 1.41
ARMISelLowering.h updated: 1.12 -> 1.13
---
Log message:
remove dead target hooks
---
Diffs of the changes: (+49 -98)
ARMISelLowering.cpp | 133 +++-
ARMISelLowering.h | 14 -
2 files changed, 49 insertions(+), 98 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.40
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.41
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.40Mon Apr 9 17:25:41 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Mon Apr 9 18:33:39 2007
@@ -1295,66 +1295,14 @@
// ARM Optimization Hooks
//===--===//
-/// isLegalAddressingMode - Return true if the addressing mode represented
-/// by AM is legal for this target, for a load/store of the specified type.
-bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
- const Type *Ty) const {
- if (!isLegalAddressImmediate(AM.BaseOffs, Ty))
-return false;
-
- // Can never fold addr of global into load/store.
- if (AM.BaseGV)
-return false;
-
- switch (AM.Scale) {
- case 0: // no scale reg, must be "r+i" or "r", or "i".
-break;
- case 1:
-if (Subtarget->isThumb())
- return false;
-
- default:
-switch (getValueType(Ty)) {
-default: return false;
-case MVT::i1:
-case MVT::i8:
-case MVT::i32:
-case MVT::i64:
- // This assumes i64 is legalized to a pair of i32. If not (i.e.
- // ldrd / strd are used, then its address mode is same as i16.
- // r + r
- if (AM.Scale == 1)
-return true;
- // r + r << imm
- if (!isPowerOf2_32(AM.Scale & ~1))
-return false;
-case MVT::i16:
- // r + r
- if (((unsigned)AM.HasBaseReg + AM.Scale) <= 2)
-return true;
-
-case MVT::isVoid:
- // Note, we allow "void" uses (basically, uses that aren't loads or
- // stores), because arm allows folding a scale into many arithmetic
- // operations. This should be made more precise and revisited later.
-
- // Allow r << imm, but the imm has to be a multiple of two.
- if (AM.Scale & 1) return false;
- return isPowerOf2_32(AM.Scale);
-}
-break;
- }
- return true;
-}
-
/// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode for load / store of the
/// given type.
-bool ARMTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty)
const{
+static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT,
+const ARMSubtarget *Subtarget) {
if (V == 0)
return true;
- MVT::ValueType VT = getValueType(Ty);
if (Subtarget->isThumb()) {
if (V < 0)
return false;
@@ -1405,42 +1353,59 @@
}
}
-bool ARMTargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
- return false;
-}
-
-/// isLegalAddressScale - Return true if the integer value can be used as
-/// the scale of the target addressing mode for load / store of the given
-/// type.
-bool ARMTargetLowering::isLegalAddressScale(int64_t S, const Type *Ty) const {
- if (Subtarget->isThumb())
+/// isLegalAddressingMode - Return true if the addressing mode represented
+/// by AM is legal for this target, for a load/store of the specified type.
+bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
+ const Type *Ty) const {
+ if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty), Subtarget))
+return false;
+
+ // Can never fold addr of global into load/store.
+ if (AM.BaseGV)
return false;
+
+ switch (AM.Scale) {
+ case 0: // no scale reg, must be "r+i" or "r", or "i".
+break;
+ case 1:
+if (Subtarget->isThumb())
+ return false;
- MVT::ValueType VT = getValueType(Ty);
- switch (VT) {
- default: return false;
- case MVT::i1:
- case MVT::i8:
- case MVT::i32:
-if (S < 0) S = -S;
-if (S == 1) return true; // Allow: r + r
+ default:
+switch (getValueType(Ty)) {
+default: return false;
+case MVT::i1:
+case MVT::i8:
+case MVT::i32:
+case MVT::i64:
+ // This assumes i64 is legalized to a pair of i32. If not (i.e.
+ // ldrd / strd are used, then its address mode is same as i16.
+ // r + r
+ if (AM.Scale == 1)
+return true;
+ // r + r << imm
+ if (!isPowerOf2_32(AM.Scale & ~1))
+return false;
+case MVT::i16:
+ // r + r
+ if (((unsigned)AM.HasBaseReg + AM.Scale) <= 2)
+return true;
+
+case MVT::isVoid:
+ // Note, we allow "void" uses (basically, uses that aren't loads or
+ // stores), because arm allows folding a scale into many arithmetic
+ // operations
Re: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
On May 3, 2007, at 5:27 PM, Evan Cheng wrote:
>
>
> Changes in directory llvm/lib/Target/ARM:
>
> ARMISelLowering.cpp updated: 1.49 -> 1.50
> ---
> Log message:
>
> On Mac OS X, GV requires an extra load only when relocation-model
> is non-static.
Does ELF do something similar? If not, this should probably be
method on ARMSubTarget, like the X86 backend does.
-Chris
> ---
> Diffs of the changes: (+6 -5)
>
> ARMISelLowering.cpp | 11 ++-
> 1 files changed, 6 insertions(+), 5 deletions(-)
>
>
> Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
> diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.49 llvm/lib/
> Target/ARM/ARMISelLowering.cpp:1.50
> --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.49 Thu May 3
> 15:28:35 2007
> +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Thu May 3 19:26:58 2007
> @@ -812,10 +812,11 @@
> }
>
> /// GVIsIndirectSymbol - true if the GV will be accessed via an
> indirect symbol
> -/// even in dynamic-no-pic mode.
> -static bool GVIsIndirectSymbol(GlobalValue *GV) {
> - return (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
> - (GV->isDeclaration() && !GV->hasNotBeenReadFromBytecode
> ()));
> +/// even in non-static mode.
> +static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model
> RelocM) {
> + return RelocM != Reloc::Static &&
> +(GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
> + (GV->isDeclaration() && !GV->hasNotBeenReadFromBytecode()));
> }
>
> SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op,
> @@ -823,7 +824,7 @@
>MVT::ValueType PtrVT = getPointerTy();
>GlobalValue *GV = cast(Op)->getGlobal();
>Reloc::Model RelocM = getTargetMachine().getRelocationModel();
> - bool IsIndirect = GVIsIndirectSymbol(GV);
> + bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
>SDOperand CPAddr;
>if (RelocM == Reloc::Static)
> CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
>
>
>
> ___
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Re: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
No idea. Lauro?
Evan
On May 3, 2007, at 5:33 PM, Chris Lattner wrote:
>
> On May 3, 2007, at 5:27 PM, Evan Cheng wrote:
>
>>
>>
>> Changes in directory llvm/lib/Target/ARM:
>>
>> ARMISelLowering.cpp updated: 1.49 -> 1.50
>> ---
>> Log message:
>>
>> On Mac OS X, GV requires an extra load only when relocation-model
>> is non-static.
>
> Does ELF do something similar? If not, this should probably be
> method on ARMSubTarget, like the X86 backend does.
>
> -Chris
>
>> ---
>> Diffs of the changes: (+6 -5)
>>
>> ARMISelLowering.cpp | 11 ++-
>> 1 files changed, 6 insertions(+), 5 deletions(-)
>>
>>
>> Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
>> diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.49 llvm/lib/
>> Target/ARM/ARMISelLowering.cpp:1.50
>> --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.49 Thu May 3
>> 15:28:35 2007
>> +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Thu May 3 19:26:58 2007
>> @@ -812,10 +812,11 @@
>> }
>>
>> /// GVIsIndirectSymbol - true if the GV will be accessed via an
>> indirect symbol
>> -/// even in dynamic-no-pic mode.
>> -static bool GVIsIndirectSymbol(GlobalValue *GV) {
>> - return (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
>> - (GV->isDeclaration() && !GV->hasNotBeenReadFromBytecode
>> ()));
>> +/// even in non-static mode.
>> +static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model
>> RelocM) {
>> + return RelocM != Reloc::Static &&
>> +(GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
>> + (GV->isDeclaration() && !GV->hasNotBeenReadFromBytecode()));
>> }
>>
>> SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op,
>> @@ -823,7 +824,7 @@
>>MVT::ValueType PtrVT = getPointerTy();
>>GlobalValue *GV = cast(Op)->getGlobal();
>>Reloc::Model RelocM = getTargetMachine().getRelocationModel();
>> - bool IsIndirect = GVIsIndirectSymbol(GV);
>> + bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
>>SDOperand CPAddr;
>>if (RelocM == Reloc::Static)
>> CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
>>
>>
>>
>> ___
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>
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Re: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Nowadays we have two functions for the GV lowering: one for ELF and one for
Darwin. So, the ELF and Darwin GV lowering implementations are completely
different and ELF doesn't use the auxiliary function GVIsIndirectSymbol.
Lauro
2007/5/3, Evan Cheng <[EMAIL PROTECTED]>:
No idea. Lauro?
Evan
On May 3, 2007, at 5:33 PM, Chris Lattner wrote:
>
> On May 3, 2007, at 5:27 PM, Evan Cheng wrote:
>
>>
>>
>> Changes in directory llvm/lib/Target/ARM:
>>
>> ARMISelLowering.cpp updated: 1.49 -> 1.50
>> ---
>> Log message:
>>
>> On Mac OS X, GV requires an extra load only when relocation-model
>> is non-static.
>
> Does ELF do something similar? If not, this should probably be
> method on ARMSubTarget, like the X86 backend does.
>
> -Chris
>
>> ---
>> Diffs of the changes: (+6 -5)
>>
>> ARMISelLowering.cpp | 11 ++-
>> 1 files changed, 6 insertions(+), 5 deletions(-)
>>
>>
>> Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
>> diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.49 llvm/lib/
>> Target/ARM/ARMISelLowering.cpp:1.50
>> --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.49 Thu May 3
>> 15:28:35 2007
>> +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Thu May 3 19:26:58 2007
>> @@ -812,10 +812,11 @@
>> }
>>
>> /// GVIsIndirectSymbol - true if the GV will be accessed via an
>> indirect symbol
>> -/// even in dynamic-no-pic mode.
>> -static bool GVIsIndirectSymbol(GlobalValue *GV) {
>> - return (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
>> - (GV->isDeclaration() && !GV->hasNotBeenReadFromBytecode
>> ()));
>> +/// even in non-static mode.
>> +static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model
>> RelocM) {
>> + return RelocM != Reloc::Static &&
>> +(GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
>> + (GV->isDeclaration() && !GV->hasNotBeenReadFromBytecode()));
>> }
>>
>> SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op,
>> @@ -823,7 +824,7 @@
>>MVT::ValueType PtrVT = getPointerTy();
>>GlobalValue *GV = cast(Op)->getGlobal();
>>Reloc::Model RelocM = getTargetMachine().getRelocationModel();
>> - bool IsIndirect = GVIsIndirectSymbol(GV);
>> + bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
>>SDOperand CPAddr;
>>if (RelocM == Reloc::Static)
>> CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
>>
>>
>>
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>
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Re: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
On May 4, 2007, at 3:08 PM, Lauro Ramos Venancio wrote: > Nowadays we have two functions for the GV lowering: one for ELF and > one for Darwin. So, the ELF and Darwin GV lowering implementations > are completely different and ELF doesn't use the auxiliary function > GVIsIndirectSymbol. Great point. Thanks Lauro, -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
> Optimize PIC implementation. GOTOFF can be used when the symbol is
> defined
> and used in the same module.
Does this work for weak symbols?
-Chris
>
> ---
> Diffs of the changes: (+1 -1)
>
> ARMISelLowering.cpp |2 +-
> 1 files changed, 1 insertion(+), 1 deletion(-)
>
>
> Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
> diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.50 llvm/lib/
> Target/ARM/ARMISelLowering.cpp:1.51
> --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.50 Thu May 3
> 19:26:58 2007
> +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Mon May 14 13:46:23 2007
> @@ -792,7 +792,7 @@
>GlobalValue *GV = cast(Op)->getGlobal();
>Reloc::Model RelocM = getTargetMachine().getRelocationModel();
>if (RelocM == Reloc::PIC_) {
> -bool UseGOTOFF = GV->hasInternalLinkage();
> +bool UseGOTOFF = !GV->isDeclaration();
> ARMConstantPoolValue *CPV =
>new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ?
> "GOTOFF":"GOT");
> SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
>
>
>
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMISelLowering.h
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.58 -> 1.59
ARMISelLowering.h updated: 1.17 -> 1.18
---
Log message:
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
---
Diffs of the changes: (+9 -8)
ARMISelLowering.cpp | 16
ARMISelLowering.h |1 +
2 files changed, 9 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.58
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.59
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.58Tue Jun 19 18:55:02 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Fri Jun 22 09:59:07 2007
@@ -1254,9 +1254,8 @@
SDOperand RL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(1),
DAG.getConstant(0, MVT::i32));
- const TargetLowering &TL = DAG.getTargetLoweringInfo();
- unsigned LHSSB = TL.ComputeNumSignBits(Op.getOperand(0));
- unsigned RHSSB = TL.ComputeNumSignBits(Op.getOperand(1));
+ unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
+ unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
SDOperand Lo, Hi;
// Figure out how to lower this multiply.
@@ -1265,8 +1264,8 @@
Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL);
Hi = DAG.getNode(ISD::MULHS, MVT::i32, LL, RL);
} else if (LHSSB == 32 && RHSSB == 32 &&
- TL.MaskedValueIsZero(Op.getOperand(0), 0xULL) &&
- TL.MaskedValueIsZero(Op.getOperand(1), 0xULL)) {
+ DAG.MaskedValueIsZero(Op.getOperand(0), 0xULL) &&
+ DAG.MaskedValueIsZero(Op.getOperand(1), 0xULL)) {
// If the inputs are zero extended, use mulhu.
Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL);
Hi = DAG.getNode(ISD::MULHU, MVT::i32, LL, RL);
@@ -1757,6 +1756,7 @@
uint64_t Mask,
uint64_t &KnownZero,
uint64_t &KnownOne,
+ const SelectionDAG &DAG,
unsigned Depth) const {
KnownZero = 0;
KnownOne = 0;
@@ -1764,12 +1764,12 @@
default: break;
case ARMISD::CMOV: {
// Bits are known zero/one if known on the LHS and RHS.
-ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
+DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne,
Depth+1);
if (KnownZero == 0 && KnownOne == 0) return;
uint64_t KnownZeroRHS, KnownOneRHS;
-ComputeMaskedBits(Op.getOperand(1), Mask,
- KnownZeroRHS, KnownOneRHS, Depth+1);
+DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
+ KnownZeroRHS, KnownOneRHS, Depth+1);
KnownZero &= KnownZeroRHS;
KnownOne &= KnownOneRHS;
return;
Index: llvm/lib/Target/ARM/ARMISelLowering.h
diff -u llvm/lib/Target/ARM/ARMISelLowering.h:1.17
llvm/lib/Target/ARM/ARMISelLowering.h:1.18
--- llvm/lib/Target/ARM/ARMISelLowering.h:1.17 Tue Jun 19 16:05:09 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.h Fri Jun 22 09:59:07 2007
@@ -108,6 +108,7 @@
uint64_t Mask,
uint64_t &KnownZero,
uint64_t &KnownOne,
+const SelectionDAG &DAG,
unsigned Depth) const;
ConstraintType getConstraintType(const std::string &Constraint) const;
std::pair
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMRegisterInfo.cpp ARMTargetMachine.cpp
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.1 -> 1.2
ARMRegisterInfo.cpp updated: 1.34 -> 1.35
ARMTargetMachine.cpp updated: 1.14 -> 1.15
---
Log message:
isDarwin -> isTargetDarwin
---
Diffs of the changes: (+8 -8)
ARMISelLowering.cpp |8
ARMRegisterInfo.cpp |6 +++---
ARMTargetMachine.cpp |2 +-
3 files changed, 8 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.1
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.2
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.1 Fri Jan 19 01:51:42 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Fri Jan 19 13:28:01 2007
@@ -146,7 +146,7 @@
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
// FIXME - use subtarget debug flags
- if (Subtarget->isDarwin())
+ if (Subtarget->isTargetDarwin())
setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
setOperationAction(ISD::RET, MVT::Other, Custom);
@@ -470,7 +470,7 @@
isDirect = true;
bool isExt = (GV->isExternal() || GV->hasWeakLinkage() ||
GV->hasLinkOnceLinkage());
-bool isStub = (isExt && Subtarget->isDarwin()) &&
+bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
getTargetMachine().getRelocationModel() != Reloc::Static;
isARMFunc = !Subtarget->isThumb() || isStub;
// Wrap it since tBX takes a register source operand.
@@ -479,7 +479,7 @@
} else if (ExternalSymbolSDNode *S = dyn_cast(Callee))
{
Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
isDirect = true;
-bool isStub = Subtarget->isDarwin() &&
+bool isStub = Subtarget->isTargetDarwin() &&
getTargetMachine().getRelocationModel() != Reloc::Static;
isARMFunc = !Subtarget->isThumb() || isStub;
// Wrap it since tBX takes a register source operand.
@@ -641,7 +641,7 @@
MVT::ValueType PtrVT = getPointerTy();
GlobalValue *GV = cast(Op)->getGlobal();
Reloc::Model RelocM = getTargetMachine().getRelocationModel();
- bool IsIndirect = Subtarget->isDarwin() && GVIsIndirectSymbol(GV);
+ bool IsIndirect = Subtarget->isTargetDarwin() && GVIsIndirectSymbol(GV);
SDOperand CPAddr;
if (RelocM == Reloc::Static)
CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.34
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.35
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.34Fri Jan 19 01:51:42 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Fri Jan 19 13:28:01 2007
@@ -256,7 +256,7 @@
ARM::D11, ARM::D10, ARM::D9, ARM::D8,
0
};
- return STI.isDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
+ return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
}
const TargetRegisterClass* const *
@@ -807,7 +807,7 @@
case ARM::R9:
case ARM::R10:
case ARM::R11:
-Category = STI.isDarwin() ? 2 : 1;
+Category = STI.isTargetDarwin() ? 2 : 1;
break;
case ARM::D8:
case ARM::D9:
@@ -870,7 +870,7 @@
case ARM::R11:
if (Reg == FramePtr)
FramePtrSpillFI = FI;
-if (STI.isDarwin()) {
+if (STI.isTargetDarwin()) {
AFI->addGPRCalleeSavedArea2Frame(FI);
GPRCS2Size += 4;
} else {
Index: llvm/lib/Target/ARM/ARMTargetMachine.cpp
diff -u llvm/lib/Target/ARM/ARMTargetMachine.cpp:1.14
llvm/lib/Target/ARM/ARMTargetMachine.cpp:1.15
--- llvm/lib/Target/ARM/ARMTargetMachine.cpp:1.14 Fri Jan 19 01:51:42 2007
+++ llvm/lib/Target/ARM/ARMTargetMachine.cppFri Jan 19 13:28:01 2007
@@ -35,7 +35,7 @@
ARMTargetMachine::ARMTargetMachine(const Module &M, const std::string &FS)
: Subtarget(M, FS), DataLayout("e-p:32:32-d:32"), InstrInfo(Subtarget),
FrameInfo(Subtarget) {
- if (Subtarget.isDarwin())
+ if (Subtarget.isTargetDarwin())
NoFramePointerElim = true;
}
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Re: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMTargetMachine.cpp
Hi Lauro,
This is wrong for Mac OS X. Please back out the patch until it is
fixed. Make sure you conditionalize base on the ABI of choice
Please add an ABI enum ABIType to ARMSubtarget.h and the
corresponding methods. Looking at llvm-gcc/gcc/config/arm/arm.h, I
see there are 5 ARM abi's:
ARM_ABI_APCS,
ARM_ABI_ATPCS,
ARM_ABI_AAPCS,
ARM_ABI_IWMMXT,
ARM_ABI_AAPCS_LINUX
The default is ARM_ABI_APCS, I suppose ARM EABI is ARM_ABI_AAPCS_LINUX?
Thanks,
Evan
On Feb 13, 2007, at 6:07 AM, Lauro Ramos Venancio wrote:
>
>
> Changes in directory llvm/lib/Target/ARM:
>
> ARMISelLowering.cpp updated: 1.13 -> 1.14
> ARMTargetMachine.cpp updated: 1.20 -> 1.21
> ---
> Log message:
>
> According to ARM EABI, 8-bytes function arguments must be 8-bytes
> aligned.
>
>
> ---
> Diffs of the changes: (+53 -30)
>
> ARMISelLowering.cpp | 79 +++
> +---
> ARMTargetMachine.cpp |4 +-
> 2 files changed, 53 insertions(+), 30 deletions(-)
>
>
> Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
> diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.13 llvm/lib/
> Target/ARM/ARMISelLowering.cpp:1.14
> --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.13 Sat Feb 3
> 02:53:01 2007
> +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Tue Feb 13 08:07:13 2007
> @@ -338,29 +338,36 @@
> }
>
> static void
> -HowToPassArgument(MVT::ValueType ObjectVT,
> - unsigned NumGPRs, unsigned &ObjSize, unsigned
> &ObjGPRs) {
> - ObjSize = 0;
> - ObjGPRs = 0;
> -
> +HowToPassArgument(MVT::ValueType ObjectVT, unsigned NumGPRs,
> + unsigned StackOffset, unsigned &NeededGPRs,
> + unsigned &NeededStackSize, unsigned &GPRPad,
> + unsigned &StackPad, unsigned Flags) {
> + NeededStackSize = 0;
> + NeededGPRs = 0;
> + StackPad = 0;
> + GPRPad = 0;
> + unsigned align = (Flags >> 27);
> + GPRPad = NumGPRs % ((align + 3)/4);
> + StackPad = StackOffset % align;
> + unsigned firstGPR = NumGPRs + GPRPad;
>switch (ObjectVT) {
>default: assert(0 && "Unhandled argument type!");
>case MVT::i32:
>case MVT::f32:
> -if (NumGPRs < 4)
> - ObjGPRs = 1;
> +if (firstGPR < 4)
> + NeededGPRs = 1;
> else
> - ObjSize = 4;
> + NeededStackSize = 4;
> break;
>case MVT::i64:
>case MVT::f64:
> -if (NumGPRs < 3)
> - ObjGPRs = 2;
> -else if (NumGPRs == 3) {
> - ObjGPRs = 1;
> - ObjSize = 4;
> +if (firstGPR < 3)
> + NeededGPRs = 2;
> +else if (firstGPR == 3) {
> + NeededGPRs = 1;
> + NeededStackSize = 4;
> } else
> - ObjSize = 8;
> + NeededStackSize = 8;
>}
> }
>
> @@ -383,12 +390,16 @@
>
>// Add up all the space actually used.
>for (unsigned i = 0; i < NumOps; ++i) {
> -unsigned ObjSize = 0;
> -unsigned ObjGPRs = 0;
> +unsigned ObjSize;
> +unsigned ObjGPRs;
> +unsigned StackPad;
> +unsigned GPRPad;
> MVT::ValueType ObjectVT = Op.getOperand(5+2*i).getValueType();
> -HowToPassArgument(ObjectVT, NumGPRs, ObjSize, ObjGPRs);
> -NumBytes += ObjSize;
> -NumGPRs += ObjGPRs;
> +unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
> +HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize,
> + GPRPad, StackPad, Flags);
> +NumBytes += ObjSize + StackPad;
> +NumGPRs += ObjGPRs + GPRPad;
>}
>
>// Adjust the stack pointer for the new arguments...
> @@ -407,18 +418,24 @@
>std::vector MemOpChains;
>for (unsigned i = 0; i != NumOps; ++i) {
> SDOperand Arg = Op.getOperand(5+2*i);
> +unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
> MVT::ValueType ArgVT = Arg.getValueType();
>
> -unsigned ObjSize = 0;
> -unsigned ObjGPRs = 0;
> -HowToPassArgument(ArgVT, NumGPRs, ObjSize, ObjGPRs);
> +unsigned ObjSize;
> +unsigned ObjGPRs;
> +unsigned GPRPad;
> +unsigned StackPad;
> +HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs,
> + ObjSize, GPRPad, StackPad, Flags);
> +NumGPRs += GPRPad;
> +ArgOffset += StackPad;
> if (ObjGPRs > 0) {
>switch (ArgVT) {
>default: assert(0 && "Unexpected ValueType for argument!");
>case MVT::i32:
> RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs],
> Arg));
> break;
> - case MVT::f32:
> + case MVT::f32:
> RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs],
> DAG.getNode(ISD::BIT_CONVERT,
> MVT::i32, Arg)));
> break;
> @@ -436,7 +453,7 @@
>MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff,
> NULL, 0));
> }
> break;
> - }
> + }
>case MVT::f64: {
> SDOperand Cvt = DAG.getNode(ARMISD::FMRRD,
> DAG.getVTList(MVT::i32,
> MVT::i32),
> @@ -715,7 +732,7 @@
> }
>
> static SDOperand LowerFORMAL_ARGUMENT(SDOperand
Re: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMTargetMachine.cpp
Hi Evan,
I change function arguments alignment only for ELF. The code generated
for mtriple=arm-apple-darwin remains the same. For now, I am
implementing only ARM EABI. I don't have testing environment for
others ABIs. Did you found any miscompilation caused by this patch?
Lauro
2007/2/13, Evan Cheng <[EMAIL PROTECTED]>:
> Hi Lauro,
>
> This is wrong for Mac OS X. Please back out the patch until it is
> fixed. Make sure you conditionalize base on the ABI of choice
>
> Please add an ABI enum ABIType to ARMSubtarget.h and the
> corresponding methods. Looking at llvm-gcc/gcc/config/arm/arm.h, I
> see there are 5 ARM abi's:
>
>ARM_ABI_APCS,
>ARM_ABI_ATPCS,
>ARM_ABI_AAPCS,
>ARM_ABI_IWMMXT,
>ARM_ABI_AAPCS_LINUX
>
> The default is ARM_ABI_APCS, I suppose ARM EABI is ARM_ABI_AAPCS_LINUX?
>
> Thanks,
>
> Evan
>
> On Feb 13, 2007, at 6:07 AM, Lauro Ramos Venancio wrote:
>
> >
> >
> > Changes in directory llvm/lib/Target/ARM:
> >
> > ARMISelLowering.cpp updated: 1.13 -> 1.14
> > ARMTargetMachine.cpp updated: 1.20 -> 1.21
> > ---
> > Log message:
> >
> > According to ARM EABI, 8-bytes function arguments must be 8-bytes
> > aligned.
> >
> >
> > ---
> > Diffs of the changes: (+53 -30)
> >
> > ARMISelLowering.cpp | 79 +++
> > +---
> > ARMTargetMachine.cpp |4 +-
> > 2 files changed, 53 insertions(+), 30 deletions(-)
> >
> >
> > Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
> > diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.13 llvm/lib/
> > Target/ARM/ARMISelLowering.cpp:1.14
> > --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.13 Sat Feb 3
> > 02:53:01 2007
> > +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Tue Feb 13 08:07:13 2007
> > @@ -338,29 +338,36 @@
> > }
> >
> > static void
> > -HowToPassArgument(MVT::ValueType ObjectVT,
> > - unsigned NumGPRs, unsigned &ObjSize, unsigned
> > &ObjGPRs) {
> > - ObjSize = 0;
> > - ObjGPRs = 0;
> > -
> > +HowToPassArgument(MVT::ValueType ObjectVT, unsigned NumGPRs,
> > + unsigned StackOffset, unsigned &NeededGPRs,
> > + unsigned &NeededStackSize, unsigned &GPRPad,
> > + unsigned &StackPad, unsigned Flags) {
> > + NeededStackSize = 0;
> > + NeededGPRs = 0;
> > + StackPad = 0;
> > + GPRPad = 0;
> > + unsigned align = (Flags >> 27);
> > + GPRPad = NumGPRs % ((align + 3)/4);
> > + StackPad = StackOffset % align;
> > + unsigned firstGPR = NumGPRs + GPRPad;
> >switch (ObjectVT) {
> >default: assert(0 && "Unhandled argument type!");
> >case MVT::i32:
> >case MVT::f32:
> > -if (NumGPRs < 4)
> > - ObjGPRs = 1;
> > +if (firstGPR < 4)
> > + NeededGPRs = 1;
> > else
> > - ObjSize = 4;
> > + NeededStackSize = 4;
> > break;
> >case MVT::i64:
> >case MVT::f64:
> > -if (NumGPRs < 3)
> > - ObjGPRs = 2;
> > -else if (NumGPRs == 3) {
> > - ObjGPRs = 1;
> > - ObjSize = 4;
> > +if (firstGPR < 3)
> > + NeededGPRs = 2;
> > +else if (firstGPR == 3) {
> > + NeededGPRs = 1;
> > + NeededStackSize = 4;
> > } else
> > - ObjSize = 8;
> > + NeededStackSize = 8;
> >}
> > }
> >
> > @@ -383,12 +390,16 @@
> >
> >// Add up all the space actually used.
> >for (unsigned i = 0; i < NumOps; ++i) {
> > -unsigned ObjSize = 0;
> > -unsigned ObjGPRs = 0;
> > +unsigned ObjSize;
> > +unsigned ObjGPRs;
> > +unsigned StackPad;
> > +unsigned GPRPad;
> > MVT::ValueType ObjectVT = Op.getOperand(5+2*i).getValueType();
> > -HowToPassArgument(ObjectVT, NumGPRs, ObjSize, ObjGPRs);
> > -NumBytes += ObjSize;
> > -NumGPRs += ObjGPRs;
> > +unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
> > +HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize,
> > + GPRPad, StackPad, Flags);
> > +NumBytes += ObjSize + StackPad;
> > +NumGPRs += ObjGPRs + GPRPad;
> >}
> >
> >// Adjust the stack pointer for the new arguments...
> > @@ -407,18 +418,24 @@
> >std::vector MemOpChains;
> >for (unsigned i = 0; i != NumOps; ++i) {
> > SDOperand Arg = Op.getOperand(5+2*i);
> > +unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
> > MVT::ValueType ArgVT = Arg.getValueType();
> >
> > -unsigned ObjSize = 0;
> > -unsigned ObjGPRs = 0;
> > -HowToPassArgument(ArgVT, NumGPRs, ObjSize, ObjGPRs);
> > +unsigned ObjSize;
> > +unsigned ObjGPRs;
> > +unsigned GPRPad;
> > +unsigned StackPad;
> > +HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs,
> > + ObjSize, GPRPad, StackPad, Flags);
> > +NumGPRs += GPRPad;
> > +ArgOffset += StackPad;
> > if (ObjGPRs > 0) {
> >switch (ArgVT) {
> >default: assert(0 && "Unexpected ValueType for argument!");
> >case MVT::i32:
> > RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs],
> > Arg));
> > break;
> > - case
Re: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMTargetMachine.cpp
Ah, I see you have only changed long alignment when target isn't
Darwin. My mistake, this will not break Mac OS X / APCS support.
What is the default ABI for Linux? Can you experiment with gcc -mabi=
to see if this might break other ABI's?
Thanks,
Evan
On Feb 13, 2007, at 9:33 AM, Lauro Ramos Venancio wrote:
> Hi Evan,
>
> I change function arguments alignment only for ELF. The code generated
> for mtriple=arm-apple-darwin remains the same. For now, I am
> implementing only ARM EABI. I don't have testing environment for
> others ABIs. Did you found any miscompilation caused by this patch?
>
> Lauro
>
> 2007/2/13, Evan Cheng <[EMAIL PROTECTED]>:
>> Hi Lauro,
>>
>> This is wrong for Mac OS X. Please back out the patch until it is
>> fixed. Make sure you conditionalize base on the ABI of choice
>>
>> Please add an ABI enum ABIType to ARMSubtarget.h and the
>> corresponding methods. Looking at llvm-gcc/gcc/config/arm/arm.h, I
>> see there are 5 ARM abi's:
>>
>>ARM_ABI_APCS,
>>ARM_ABI_ATPCS,
>>ARM_ABI_AAPCS,
>>ARM_ABI_IWMMXT,
>>ARM_ABI_AAPCS_LINUX
>>
>> The default is ARM_ABI_APCS, I suppose ARM EABI is
>> ARM_ABI_AAPCS_LINUX?
>>
>> Thanks,
>>
>> Evan
>>
>> On Feb 13, 2007, at 6:07 AM, Lauro Ramos Venancio wrote:
>>
>> >
>> >
>> > Changes in directory llvm/lib/Target/ARM:
>> >
>> > ARMISelLowering.cpp updated: 1.13 -> 1.14
>> > ARMTargetMachine.cpp updated: 1.20 -> 1.21
>> > ---
>> > Log message:
>> >
>> > According to ARM EABI, 8-bytes function arguments must be 8-bytes
>> > aligned.
>> >
>> >
>> > ---
>> > Diffs of the changes: (+53 -30)
>> >
>> > ARMISelLowering.cpp | 79 +++
>> > +---
>> > ARMTargetMachine.cpp |4 +-
>> > 2 files changed, 53 insertions(+), 30 deletions(-)
>> >
>> >
>> > Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
>> > diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.13 llvm/lib/
>> > Target/ARM/ARMISelLowering.cpp:1.14
>> > --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.13 Sat Feb 3
>> > 02:53:01 2007
>> > +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Tue Feb 13
>> 08:07:13 2007
>> > @@ -338,29 +338,36 @@
>> > }
>> >
>> > static void
>> > -HowToPassArgument(MVT::ValueType ObjectVT,
>> > - unsigned NumGPRs, unsigned &ObjSize, unsigned
>> > &ObjGPRs) {
>> > - ObjSize = 0;
>> > - ObjGPRs = 0;
>> > -
>> > +HowToPassArgument(MVT::ValueType ObjectVT, unsigned NumGPRs,
>> > + unsigned StackOffset, unsigned &NeededGPRs,
>> > + unsigned &NeededStackSize, unsigned &GPRPad,
>> > + unsigned &StackPad, unsigned Flags) {
>> > + NeededStackSize = 0;
>> > + NeededGPRs = 0;
>> > + StackPad = 0;
>> > + GPRPad = 0;
>> > + unsigned align = (Flags >> 27);
>> > + GPRPad = NumGPRs % ((align + 3)/4);
>> > + StackPad = StackOffset % align;
>> > + unsigned firstGPR = NumGPRs + GPRPad;
>> >switch (ObjectVT) {
>> >default: assert(0 && "Unhandled argument type!");
>> >case MVT::i32:
>> >case MVT::f32:
>> > -if (NumGPRs < 4)
>> > - ObjGPRs = 1;
>> > +if (firstGPR < 4)
>> > + NeededGPRs = 1;
>> > else
>> > - ObjSize = 4;
>> > + NeededStackSize = 4;
>> > break;
>> >case MVT::i64:
>> >case MVT::f64:
>> > -if (NumGPRs < 3)
>> > - ObjGPRs = 2;
>> > -else if (NumGPRs == 3) {
>> > - ObjGPRs = 1;
>> > - ObjSize = 4;
>> > +if (firstGPR < 3)
>> > + NeededGPRs = 2;
>> > +else if (firstGPR == 3) {
>> > + NeededGPRs = 1;
>> > + NeededStackSize = 4;
>> > } else
>> > - ObjSize = 8;
>> > + NeededStackSize = 8;
>> >}
>> > }
>> >
>> > @@ -383,12 +390,16 @@
>> >
>> >// Add up all the space actually used.
>> >for (unsigned i = 0; i < NumOps; ++i) {
>> > -unsigned ObjSize = 0;
>> > -unsigned ObjGPRs = 0;
>> > +unsigned ObjSize;
>> > +unsigned ObjGPRs;
>> > +unsigned StackPad;
>> > +unsigned GPRPad;
>> > MVT::ValueType ObjectVT = Op.getOperand(5+2*i).getValueType();
>> > -HowToPassArgument(ObjectVT, NumGPRs, ObjSize, ObjGPRs);
>> > -NumBytes += ObjSize;
>> > -NumGPRs += ObjGPRs;
>> > +unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
>> > +HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs,
>> ObjSize,
>> > + GPRPad, StackPad, Flags);
>> > +NumBytes += ObjSize + StackPad;
>> > +NumGPRs += ObjGPRs + GPRPad;
>> >}
>> >
>> >// Adjust the stack pointer for the new arguments...
>> > @@ -407,18 +418,24 @@
>> >std::vector MemOpChains;
>> >for (unsigned i = 0; i != NumOps; ++i) {
>> > SDOperand Arg = Op.getOperand(5+2*i);
>> > +unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
>> > MVT::ValueType ArgVT = Arg.getValueType();
>> >
>> > -unsigned ObjSize = 0;
>> > -unsigned ObjGPRs = 0;
>> > -HowToPassArgument(ArgVT, NumGPRs, ObjSize, ObjGPRs);
>> > +unsigned ObjSize;
>> > +unsigned ObjGPRs;
>> > +unsigned G
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMRegisterInfo.cpp ARMRegisterInfo.h
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.14 -> 1.15
ARMRegisterInfo.cpp updated: 1.69 -> 1.70
ARMRegisterInfo.h updated: 1.10 -> 1.11
---
Log message:
Support to provide exception and selector registers.
---
Diffs of the changes: (+17 -0)
ARMISelLowering.cpp |3 +++
ARMRegisterInfo.cpp | 10 ++
ARMRegisterInfo.h |4
3 files changed, 17 insertions(+)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.14
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.15
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.14Tue Feb 13 08:07:13 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Wed Feb 21 16:54:50 2007
@@ -1190,6 +1190,9 @@
return LowerFORMAL_ARGUMENTS(Op, DAG);
case ISD::RETURNADDR:break;
case ISD::FRAMEADDR: break;
+ // Exception address and exception selector. Currently unimplemented.
+ case ISD::EXCEPTIONADDR: break;
+ case ISD::EHSELECTION: break;
}
return SDOperand();
}
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.69
llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.70
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.69Mon Feb 19 15:49:53 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Wed Feb 21 16:54:50 2007
@@ -1287,5 +1287,15 @@
return STI.useThumbBacktraces() ? ARM::R7 : ARM::R11;
}
+unsigned ARMRegisterInfo::getEHExceptionRegister() const {
+ assert(0 && "What is the exception register");
+ return 0;
+}
+
+unsigned ARMRegisterInfo::getEHHandlerRegister() const {
+ assert(0 && "What is the exception handler register");
+ return 0;
+}
+
#include "ARMGenRegisterInfo.inc"
Index: llvm/lib/Target/ARM/ARMRegisterInfo.h
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.h:1.10
llvm/lib/Target/ARM/ARMRegisterInfo.h:1.11
--- llvm/lib/Target/ARM/ARMRegisterInfo.h:1.10 Mon Feb 19 15:49:53 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.h Wed Feb 21 16:54:50 2007
@@ -85,6 +85,10 @@
// Debug information queries.
unsigned getRARegister() const;
unsigned getFrameRegister(MachineFunction &MF) const;
+
+ // Exception handling queries.
+ unsigned getEHExceptionRegister() const;
+ unsigned getEHHandlerRegister() const;
};
} // end namespace llvm
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMInstrInfo.td ARMInstrThumb.td
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.26 -> 1.27
ARMInstrInfo.td updated: 1.92 -> 1.93
ARMInstrThumb.td updated: 1.17 -> 1.18
---
Log message:
bugfix: When the source register of CALL_NOLINK was LR, the following code was
emitted:
mov lr, pc
bx lr
So, the function was not called.
---
Diffs of the changes: (+28 -19)
ARMISelLowering.cpp | 29 ++---
ARMInstrInfo.td | 10 +-
ARMInstrThumb.td|8 +---
3 files changed, 28 insertions(+), 19 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.26
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.27
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.26Mon Mar 19 21:25:53 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Tue Mar 20 12:57:23 2007
@@ -544,6 +544,24 @@
Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
}
+ // FIXME: handle tail calls differently.
+ unsigned CallOpc;
+ if (Subtarget->isThumb()) {
+if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
+ CallOpc = ARMISD::CALL_NOLINK;
+else
+ CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
+ } else {
+CallOpc = (isDirect || Subtarget->hasV5TOps())
+ ? ARMISD::CALL : ARMISD::CALL_NOLINK;
+ }
+ if (CallOpc == ARMISD::CALL_NOLINK) {
+// On CALL_NOLINK we must move PC to LR
+Chain = DAG.getCopyToReg(Chain, ARM::LR,
+ DAG.getRegister(ARM::PC, MVT::i32), InFlag);
+InFlag = Chain.getValue(1);
+ }
+
std::vector NodeTys;
NodeTys.push_back(MVT::Other); // Returns a chain
NodeTys.push_back(MVT::Flag);// Returns a flag for retval copy to use.
@@ -558,17 +576,6 @@
Ops.push_back(DAG.getRegister(RegsToPass[i].first,
RegsToPass[i].second.getValueType()));
- // FIXME: handle tail calls differently.
- unsigned CallOpc;
- if (Subtarget->isThumb()) {
-if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
- CallOpc = ARMISD::CALL_NOLINK;
-else
- CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
- } else {
-CallOpc = (isDirect || Subtarget->hasV5TOps())
- ? ARMISD::CALL : ARMISD::CALL_NOLINK;
- }
if (InFlag.Val)
Ops.push_back(InFlag);
Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.92
llvm/lib/Target/ARM/ARMInstrInfo.td:1.93
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.92Tue Mar 20 03:11:30 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.td Tue Mar 20 12:57:23 2007
@@ -370,8 +370,6 @@
: I;
class AI4 pattern>
: I;
-class AIx2 pattern>
- : I;
class AI1x2 pattern>
: I;
@@ -546,10 +544,12 @@
def BLX : AI<(ops GPR:$dst, variable_ops),
"blx $dst",
[(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>;
- // ARMv4T
- def BX : AIx2<(ops GPR:$dst, variable_ops),
-"mov lr, pc\n\tbx $dst",
+ let Uses = [LR] in {
+// ARMv4T
+def BX : AI<(ops GPR:$dst, variable_ops),
+"bx $dst",
[(ARMcall_nolink GPR:$dst)]>;
+ }
}
let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
Index: llvm/lib/Target/ARM/ARMInstrThumb.td
diff -u llvm/lib/Target/ARM/ARMInstrThumb.td:1.17
llvm/lib/Target/ARM/ARMInstrThumb.td:1.18
--- llvm/lib/Target/ARM/ARMInstrThumb.td:1.17 Mon Mar 19 02:48:02 2007
+++ llvm/lib/Target/ARM/ARMInstrThumb.tdTue Mar 20 12:57:23 2007
@@ -189,10 +189,12 @@
def tBLXr : TI<(ops GPR:$dst, variable_ops),
"blx $dst",
[(ARMtcall GPR:$dst)]>, Requires<[HasV5T]>;
- // ARMv4T
- def tBX : TIx2<(ops GPR:$dst, variable_ops),
- "cpy lr, pc\n\tbx $dst",
+ let Uses = [LR] in {
+// ARMv4T
+def tBX : TI<(ops GPR:$dst, variable_ops),
+ "bx $dst",
[(ARMcall_nolink GPR:$dst)]>;
+ }
}
let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMInstrInfo.td ARMInstrThumb.td
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.30 -> 1.31
ARMInstrInfo.td updated: 1.93 -> 1.94
ARMInstrThumb.td updated: 1.18 -> 1.19
---
Log message:
bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of
a CALL_NOLINK.
---
Diffs of the changes: (+11 -11)
ARMISelLowering.cpp |6 +++---
ARMInstrInfo.td |8 +---
ARMInstrThumb.td|8 +++-
3 files changed, 11 insertions(+), 11 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.30
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.31
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.30Sat Mar 24 21:14:49 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Tue Mar 27 11:19:21 2007
@@ -555,10 +555,10 @@
CallOpc = (isDirect || Subtarget->hasV5TOps())
? ARMISD::CALL : ARMISD::CALL_NOLINK;
}
- if (CallOpc == ARMISD::CALL_NOLINK) {
-// On CALL_NOLINK we must move PC to LR
+ if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
+// implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
Chain = DAG.getCopyToReg(Chain, ARM::LR,
- DAG.getRegister(ARM::PC, MVT::i32), InFlag);
+ DAG.getNode(ISD::UNDEF, MVT::i32), InFlag);
InFlag = Chain.getValue(1);
}
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.93
llvm/lib/Target/ARM/ARMInstrInfo.td:1.94
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.93Tue Mar 20 12:57:23 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.td Tue Mar 27 11:19:21 2007
@@ -370,6 +370,8 @@
: I;
class AI4 pattern>
: I;
+class AIx2 pattern>
+ : I;
class AI1x2 pattern>
: I;
@@ -546,9 +548,9 @@
[(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>;
let Uses = [LR] in {
// ARMv4T
-def BX : AI<(ops GPR:$dst, variable_ops),
-"bx $dst",
-[(ARMcall_nolink GPR:$dst)]>;
+def BX : AIx2<(ops GPR:$dst, variable_ops),
+ "mov lr, pc\n\tbx $dst",
+ [(ARMcall_nolink GPR:$dst)]>;
}
}
Index: llvm/lib/Target/ARM/ARMInstrThumb.td
diff -u llvm/lib/Target/ARM/ARMInstrThumb.td:1.18
llvm/lib/Target/ARM/ARMInstrThumb.td:1.19
--- llvm/lib/Target/ARM/ARMInstrThumb.td:1.18 Tue Mar 20 12:57:23 2007
+++ llvm/lib/Target/ARM/ARMInstrThumb.tdTue Mar 27 11:19:21 2007
@@ -189,12 +189,10 @@
def tBLXr : TI<(ops GPR:$dst, variable_ops),
"blx $dst",
[(ARMtcall GPR:$dst)]>, Requires<[HasV5T]>;
- let Uses = [LR] in {
-// ARMv4T
-def tBX : TI<(ops GPR:$dst, variable_ops),
- "bx $dst",
+ // ARMv4T
+ def tBX : TIx2<(ops GPR:$dst, variable_ops),
+ "cpy lr, pc\n\tbx $dst",
[(ARMcall_nolink GPR:$dst)]>;
- }
}
let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMISelLowering.h ARMInstrInfo.td
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.56 -> 1.57
ARMISelLowering.h updated: 1.16 -> 1.17
ARMInstrInfo.td updated: 1.112 -> 1.113
---
Log message:
Allow predicated immediate ARM to ARM calls.
---
Diffs of the changes: (+14 -1)
ARMISelLowering.cpp |7 ++-
ARMISelLowering.h |1 +
ARMInstrInfo.td |7 +++
3 files changed, 14 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.56
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.57
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.56Fri Jun 1 03:28:59 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Tue Jun 19 16:05:09 2007
@@ -267,6 +267,7 @@
case ARMISD::Wrapper: return "ARMISD::Wrapper";
case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
case ARMISD::CALL: return "ARMISD::CALL";
+ case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
case ARMISD::tCALL: return "ARMISD::tCALL";
case ARMISD::BRCOND:return "ARMISD::BRCOND";
@@ -517,6 +518,7 @@
// node so that legalize doesn't hack it.
bool isDirect = false;
bool isARMFunc = false;
+ bool isLocalARMFunc = false;
if (GlobalAddressSDNode *G = dyn_cast(Callee)) {
GlobalValue *GV = G->getGlobal();
isDirect = true;
@@ -525,6 +527,8 @@
bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
getTargetMachine().getRelocationModel() != Reloc::Static;
isARMFunc = !Subtarget->isThumb() || isStub;
+// ARM call to a local ARM function is predicable.
+isLocalARMFunc = !Subtarget->isThumb() && !isExt;
// tBX takes a register source operand.
if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
@@ -564,7 +568,8 @@
CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
} else {
CallOpc = (isDirect || Subtarget->hasV5TOps())
- ? ARMISD::CALL : ARMISD::CALL_NOLINK;
+ ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
+ : ARMISD::CALL_NOLINK;
}
if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
// implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
Index: llvm/lib/Target/ARM/ARMISelLowering.h
diff -u llvm/lib/Target/ARM/ARMISelLowering.h:1.16
llvm/lib/Target/ARM/ARMISelLowering.h:1.17
--- llvm/lib/Target/ARM/ARMISelLowering.h:1.16 Thu May 17 16:31:21 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.h Tue Jun 19 16:05:09 2007
@@ -34,6 +34,7 @@
WrapperJT,// WrapperJT - A wrapper node for TargetJumpTable
CALL, // Function call.
+ CALL_PRED,// Function call that's predicable.
CALL_NOLINK, // Function call with branch not branch-and-link.
tCALL,// Thumb function call.
BRCOND, // Conditional branch.
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.112
llvm/lib/Target/ARM/ARMInstrInfo.td:1.113
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.112 Mon Jun 18 20:48:04 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.td Tue Jun 19 16:05:09 2007
@@ -52,6 +52,8 @@
def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
+def ARMcall_pred: SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
+ [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
@@ -621,6 +623,11 @@
def BL : AXI<(ops i32imm:$func, variable_ops),
"bl ${func:call}",
[(ARMcall tglobaladdr:$func)]>;
+
+ def BL_pred : AI<(ops i32imm:$func, variable_ops),
+"bl", " ${func:call}",
+[(ARMcall_pred tglobaladdr:$func)]>;
+
// ARMv5T and above
def BLX : AXI<(ops GPR:$dst, variable_ops),
"blx $dst",
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMISelLowering.h ARMInstrInfo.td ARMInstrThumb.td
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.34 -> 1.35
ARMISelLowering.h updated: 1.10 -> 1.11
ARMInstrInfo.td updated: 1.94 -> 1.95
ARMInstrThumb.td updated: 1.20 -> 1.21
---
Log message:
- Divides the comparisons in two types: comparisons that only use N and Z
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).
---
Diffs of the changes: (+45 -7)
ARMISelLowering.cpp | 16 +++-
ARMISelLowering.h |1 +
ARMInstrInfo.td | 16
ARMInstrThumb.td| 19 +--
4 files changed, 45 insertions(+), 7 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.34
llvm/lib/Target/ARM/ARMISelLowering.cpp:1.35
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.34Sun Apr 1 03:06:46 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Sun Apr 1 20:30:03 2007
@@ -266,6 +266,7 @@
case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
case ARMISD::CMP: return "ARMISD::CMP";
+ case ARMISD::CMPNZ: return "ARMISD::CMPNZ";
case ARMISD::CMPFP: return "ARMISD::CMPFP";
case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
case ARMISD::FMSTAT:return "ARMISD::FMSTAT";
@@ -946,8 +947,21 @@
}
ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
+ ARMISD::NodeType CompareType;
+ switch (CondCode) {
+ default:
+CompareType = ARMISD::CMP;
+break;
+ case ARMCC::EQ:
+ case ARMCC::NE:
+ case ARMCC::MI:
+ case ARMCC::PL:
+// Uses only N and Z Flags
+CompareType = ARMISD::CMPNZ;
+break;
+ }
ARMCC = DAG.getConstant(CondCode, MVT::i32);
- return DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
+ return DAG.getNode(CompareType, MVT::Flag, LHS, RHS);
}
/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
Index: llvm/lib/Target/ARM/ARMISelLowering.h
diff -u llvm/lib/Target/ARM/ARMISelLowering.h:1.10
llvm/lib/Target/ARM/ARMISelLowering.h:1.11
--- llvm/lib/Target/ARM/ARMISelLowering.h:1.10 Fri Mar 30 18:15:24 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.h Sun Apr 1 20:30:03 2007
@@ -43,6 +43,7 @@
PIC_ADD, // Add with a PC operand and a PIC label.
CMP, // ARM compare instructions.
+ CMPNZ,// ARM compare that uses only N or Z flags.
CMPFP,// ARM VFP compare instruction, sets FPSCR.
CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
FMSTAT, // ARM fmstat instruction.
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.94
llvm/lib/Target/ARM/ARMInstrInfo.td:1.95
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.94Tue Mar 27 11:19:21 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.td Sun Apr 1 20:30:03 2007
@@ -70,6 +70,9 @@
def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
[SDNPOutFlag]>;
+def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp,
+ [SDNPOutFlag]>;
+
def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp,
[SDNPOutFlag]>;
@@ -1023,10 +1026,15 @@
(CMNri GPR:$src, so_imm_neg:$imm)>;
// Note that TST/TEQ don't set all the same flags that CMP does!
-def TSTrr : AI1<(ops GPR:$a, so_reg:$b), "tst $a, $b", []>;
-def TSTri : AI1<(ops GPR:$a, so_imm:$b), "tst $a, $b", []>;
-def TEQrr : AI1<(ops GPR:$a, so_reg:$b), "teq $a, $b", []>;
-def TEQri : AI1<(ops GPR:$a, so_imm:$b), "teq $a, $b", []>;
+defm TST : AI1_bin0_irs<"tst", BinOpFrag<(ARMcmpNZ (and node:$LHS,
node:$RHS), 0)>>;
+defm TEQ : AI1_bin0_irs<"teq", BinOpFrag<(ARMcmpNZ (xor node:$LHS,
node:$RHS), 0)>>;
+
+defm CMPnz : AI1_bin0_irs<"cmp", BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
+defm CMNnz : AI1_bin0_irs<"cmn", BinOpFrag<(ARMcmpNZ node:$LHS,(ineg
node:$RHS))>>;
+
+def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
+ (CMNri GPR:$src, so_imm_neg:$imm)>;
+
// Conditional moves
def MOVCCr : AI<(ops GPR:$dst, GPR:$false, GPR:$true, CCOp:$cc),
Index: llvm/lib/Target/ARM/ARMInstrThumb.td
diff -u llvm/lib/Target/ARM/ARMInstrThumb.td:1.20
llvm/lib/Target/ARM/ARMInstrThumb.td:1.21
--- llvm/lib/Target/ARM/ARMInstrThumb.td:1.20 Thu Mar 29 16:38:31 2007
+++ llvm/lib/Target/ARM/ARMInstrThumb.tdSun Apr 1 20:30:03 2007
@@ -356,7 +356,23 @@
def tCMPr : TI<(ops GPR:$lhs, GPR:$rhs),
"cmp $lhs, $rhs",
[(ARMcmp GPR:$lhs, GPR:$rhs)]>;
-
+
+def tTST : TI<(ops GPR:$lhs, GPR:$rhs),
+ "tst $lhs, $rhs",
+ [(ARMcmpNZ (and GPR:$lhs, GPR:$rhs), 0)]>;
+
+def tCMNNZ : TI<(ops GPR:$lhs, GPR:$rhs),
+"cmn $lhs, $rhs",
+[(ARMcmpNZ GPR:$lhs, (ineg GPR:$rhs))]>;
+
+def tCMPNZi8 : TI<
