[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Reid Spencer]

Changes in directory llvm/lib/Target:

TargetLowering.cpp added (r1.1)
---
Log message:

Add a new home for TargetLowering member functions.


---
Diffs of the changes:  (+40 -0)

 TargetLowering.cpp |   40 
 1 files changed, 40 insertions(+)


Index: llvm/lib/Target/TargetLowering.cpp
diff -c /dev/null llvm/lib/Target/TargetLowering.cpp:1.1
*** /dev/null   Fri Jan 12 17:18:28 2007
--- llvm/lib/Target/TargetLowering.cpp  Fri Jan 12 17:18:18 2007
***
*** 0 
--- 1,40 
+ //===-- TargetLowering.cpp - Asm Info 
--==//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Reid Spencer  and is distributed under the 
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ 
//===--===//
+ //
+ // This file implements methods of the TargetLowering class.
+ //
+ 
//===--===//
+ //
+ 
+ #include llvm/Target/TargetLowering.h
+ #include llvm/DerivedTypes.h
+ #include llvm/CodeGen/ValueTypes.h
+ 
+ using namespace llvm;
+ 
+ MVT::ValueType TargetLowering::getValueType(const Type *Ty) const {
+   switch (Ty-getTypeID()) {
+   default: assert(0  Unknown type!);
+   case Type::VoidTyID:return MVT::isVoid;
+   case Type::IntegerTyID:
+ switch (castIntegerType(Ty)-getBitWidth()) {
+   default: assert(0  Invalid width for value type);
+   case 1:return MVT::i1;
+   case 8:return MVT::i8;
+   case 16:   return MVT::i16;
+   case 32:   return MVT::i32;
+   case 64:   return MVT::i64;
+ }
+ break;
+   case Type::FloatTyID:   return MVT::f32;
+   case Type::DoubleTyID:  return MVT::f64;
+   case Type::PointerTyID: return PointerTy;
+   case Type::PackedTyID:  return MVT::Vector;
+   }
+ }



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[LLVM]

Changes in directory llvm/lib/Target:

TargetLowering.cpp (r1.1) removed
---
Log message:

Remove this file. It was inadvertently added because I could not find
TargetLowering.cpp in CodeGen/SelectionDAG (location makes no sense to me)


---
Diffs of the changes:  (+0 -0)

 0 files changed



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.69 - 1.70
---
Log message:

Fix a typo that causes 2006-07-07-ComputeMaskedBits.ll to fail.

---
Diffs of the changes:  (+1 -1)

 TargetLowering.cpp |2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.69 
llvm/lib/Target/TargetLowering.cpp:1.70
--- llvm/lib/Target/TargetLowering.cpp:1.69 Tue Jun 13 11:52:37 2006
+++ llvm/lib/Target/TargetLowering.cpp  Fri Jul  7 16:37:21 2006
@@ -988,7 +988,7 @@
 KnownZero = ~((1ULL  (64-NLZ2))-1)  Mask;  // Top bits known zero.
 KnownOne = 0;   // No one bits known.
   } else {
-KnownOne = KnownOne = 0;  // Otherwise, nothing known.
+KnownZero = KnownOne = 0;  // Otherwise, nothing known.
   }
 }
 return;



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Jim Laskey]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.67 - 1.68
---
Log message:

TargetLowering::ComputeMaskedBits was not clearing reciprocal bits on shifts.





---
Diffs of the changes:  (+11 -6)

 TargetLowering.cpp |   17 +++--
 1 files changed, 11 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.67 
llvm/lib/Target/TargetLowering.cpp:1.68
--- llvm/lib/Target/TargetLowering.cpp:1.67 Mon Jun 12 11:07:18 2006
+++ llvm/lib/Target/TargetLowering.cpp  Tue Jun 13 08:08:58 2006
@@ -780,12 +780,14 @@
   case ISD::SHL:
 // (shl X, C1)  C2 == 0   iff   (X  C2 u C1) == 0
 if (ConstantSDNode *SA = dyn_castConstantSDNode(Op.getOperand(1))) {
+  uint64_t LowBits = (1ULL  SA-getValue())-1;
   Mask = SA-getValue();
   ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
   assert((KnownZero  KnownOne) == 0  Bits known to be one AND zero?); 
   KnownZero = SA-getValue();
   KnownOne  = SA-getValue();
-  KnownZero |= (1ULL  SA-getValue())-1;  // low bits known zero.
+  KnownZero |= LowBits;  // low bits known zero
+  KnownOne = ~LowBits;  // and known not to be one.
 }
 return;
   case ISD::SRL:
@@ -798,7 +800,8 @@
   assert((KnownZero  KnownOne) == 0  Bits known to be one AND zero?); 
   KnownZero = SA-getValue();
   KnownOne  = SA-getValue();
-  KnownZero |= HighBits;  // high bits known zero.
+  KnownZero |= HighBits;  // high bits known zero
+  KnownOne  = ~HighBits; // and known not to be one.
 }
 return;
   case ISD::SRA:
@@ -815,10 +818,12 @@
   uint64_t SignBit = 1ULL  (MVT::getSizeInBits(Op.getValueType())-1);
   SignBit = SA-getValue();  // Adjust to where it is now in the mask.
   
-  if (KnownZero  SignBit) {   // New bits are known zero.
-KnownZero |= HighBits;
-  } else if (KnownOne  SignBit) { // New bits are known one.
-KnownOne |= HighBits;
+  if (KnownZero  SignBit) {   
+KnownZero |= HighBits;  // New bits are known zero
+KnownOne  = ~HighBits; // and known not to be one.
+  } else if (KnownOne  SignBit) {
+KnownOne  |= HighBits;  // New bits are known one
+KnownZero = ~HighBits; // and known not to be zero.
   }
 }
 return;



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.68 - 1.69
---
Log message:

Port some bugfixes in shift handling from SimplifyDemandedBits over to 
ComputeMaskedBits.  DemandedMasks and KnownZero/One masks should never have
bits set out of the range of the base datatype.


---
Diffs of the changes:  (+51 -35)

 TargetLowering.cpp |   86 +++--
 1 files changed, 51 insertions(+), 35 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.68 
llvm/lib/Target/TargetLowering.cpp:1.69
--- llvm/lib/Target/TargetLowering.cpp:1.68 Tue Jun 13 08:08:58 2006
+++ llvm/lib/Target/TargetLowering.cpp  Tue Jun 13 11:52:37 2006
@@ -442,10 +442,7 @@
   unsigned ShAmt = SA-getValue();
   
   // Compute the new bits that are at the top now.
-  uint64_t HighBits = (1ULL  ShAmt)-1;
-  HighBits = MVT::getSizeInBits(VT) - ShAmt;
   uint64_t TypeMask = MVT::getIntVTBitMask(VT);
-  
   if (SimplifyDemandedBits(Op.getOperand(0), 
(DemandedMask  ShAmt)  TypeMask,
KnownZero, KnownOne, TLO, Depth+1))
@@ -455,7 +452,10 @@
   KnownOne  = TypeMask;
   KnownZero = ShAmt;
   KnownOne  = ShAmt;
-  KnownZero |= HighBits;  // high bits known zero.
+
+  uint64_t HighBits = (1ULL  ShAmt)-1;
+  HighBits = MVT::getSizeInBits(VT) - ShAmt;
+  KnownZero |= HighBits;  // High bits known zero.
 }
 break;
   case ISD::SRA:
@@ -464,14 +464,14 @@
   unsigned ShAmt = SA-getValue();
   
   // Compute the new bits that are at the top now.
-  uint64_t HighBits = (1ULL  ShAmt)-1;
-  HighBits = MVT::getSizeInBits(VT) - ShAmt;
   uint64_t TypeMask = MVT::getIntVTBitMask(VT);
   
   uint64_t InDemandedMask = (DemandedMask  ShAmt)  TypeMask;
 
   // If any of the demanded bits are produced by the sign extension, we 
also
   // demand the input sign bit.
+  uint64_t HighBits = (1ULL  ShAmt)-1;
+  HighBits = MVT::getSizeInBits(VT) - ShAmt;
   if (HighBits  DemandedMask)
 InDemandedMask |= MVT::getIntVTSignBit(VT);
   
@@ -481,12 +481,12 @@
   assert((KnownZero  KnownOne) == 0  Bits known to be one AND zero?); 
   KnownZero = TypeMask;
   KnownOne  = TypeMask;
-  KnownZero = SA-getValue();
-  KnownOne  = SA-getValue();
+  KnownZero = ShAmt;
+  KnownOne  = ShAmt;
   
   // Handle the sign bits.
   uint64_t SignBit = MVT::getIntVTSignBit(VT);
-  SignBit = SA-getValue();  // Adjust to where it is now in the mask.
+  SignBit = ShAmt;  // Adjust to where it is now in the mask.
   
   // If the input sign bit is known to be zero, or if none of the top bits
   // are demanded, turn this into an unsigned shift right.
@@ -780,50 +780,66 @@
   case ISD::SHL:
 // (shl X, C1)  C2 == 0   iff   (X  C2 u C1) == 0
 if (ConstantSDNode *SA = dyn_castConstantSDNode(Op.getOperand(1))) {
-  uint64_t LowBits = (1ULL  SA-getValue())-1;
-  Mask = SA-getValue();
-  ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
+  ComputeMaskedBits(Op.getOperand(0), Mask  SA-getValue(),
+KnownZero, KnownOne, Depth+1);
   assert((KnownZero  KnownOne) == 0  Bits known to be one AND zero?); 
   KnownZero = SA-getValue();
   KnownOne  = SA-getValue();
-  KnownZero |= LowBits;  // low bits known zero
-  KnownOne = ~LowBits;  // and known not to be one.
+  KnownZero |= (1ULL  SA-getValue())-1;  // low bits known zero.
 }
 return;
   case ISD::SRL:
 // (ushr X, C1)  C2 == 0   iff  (-1  C1)  C2 == 0
 if (ConstantSDNode *SA = dyn_castConstantSDNode(Op.getOperand(1))) {
-  uint64_t HighBits = (1ULL  SA-getValue())-1;
-  HighBits = MVT::getSizeInBits(Op.getValueType())-SA-getValue();
-  Mask = SA-getValue();
-  ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
+  MVT::ValueType VT = Op.getValueType();
+  unsigned ShAmt = SA-getValue();
+
+  uint64_t TypeMask = MVT::getIntVTBitMask(VT);
+  ComputeMaskedBits(Op.getOperand(0), (Mask  ShAmt)  TypeMask,
+KnownZero, KnownOne, Depth+1);
   assert((KnownZero  KnownOne) == 0  Bits known to be one AND zero?); 
-  KnownZero = SA-getValue();
-  KnownOne  = SA-getValue();
-  KnownZero |= HighBits;  // high bits known zero
-  KnownOne  = ~HighBits; // and known not to be one.
+  KnownZero = TypeMask;
+  KnownOne  = TypeMask;
+  KnownZero = ShAmt;
+  KnownOne  = ShAmt;
+
+  uint64_t HighBits = (1ULL  ShAmt)-1;
+  HighBits = MVT::getSizeInBits(VT)-ShAmt;
+  KnownZero |= HighBits;  // High bits known zero.
 }
 return;
   case ISD::SRA:
 if (ConstantSDNode *SA = dyn_castConstantSDNode(Op.getOperand(1))) {
-  uint64_t HighBits = (1ULL  SA-getValue())-1;
-  

[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Andrew Lenharth]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.66 - 1.67
---
Log message:

Start on my todo list

---
Diffs of the changes:  (+2 -2)

 TargetLowering.cpp |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.66 
llvm/lib/Target/TargetLowering.cpp:1.67
--- llvm/lib/Target/TargetLowering.cpp:1.66 Wed May 17 13:22:14 2006
+++ llvm/lib/Target/TargetLowering.cpp  Mon Jun 12 11:07:18 2006
@@ -1511,7 +1511,7 @@
 /// multiplying by a magic number.  See:
 /// http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html
 SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG DAG, 
-   std::listSDNode** Created) const {
+   std::vectorSDNode** Created) const {
   MVT::ValueType VT = N-getValueType(0);
   
   // Check to see if we can do this.
@@ -1559,7 +1559,7 @@
 /// multiplying by a magic number.  See:
 /// http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html
 SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG DAG,
-   std::listSDNode** Created) const {
+   std::vectorSDNode** Created) const {
   MVT::ValueType VT = N-getValueType(0);
   
   // Check to see if we can do this.



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.64 - 1.65
---
Log message:

Fix an obvious bug in getPackedTypeBreakdown. Return 1 if type is legal.

---
Diffs of the changes:  (+2 -2)

 TargetLowering.cpp |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.64 
llvm/lib/Target/TargetLowering.cpp:1.65
--- llvm/lib/Target/TargetLowering.cpp:1.64 Tue May 16 12:45:23 2006
+++ llvm/lib/Target/TargetLowering.cpp  Wed May 17 13:10:06 2006
@@ -144,7 +144,7 @@
 }
 
 /// getPackedTypeBreakdown - Packed types are broken down into some number of
-/// legal scalar types.  For example, 8 x float maps to 2 MVT::v2f32 values
+/// legal first class types. For example, 8 x float maps to 2 MVT::v2f32
 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
 ///
 /// This method returns the number and type of the resultant breakdown.
@@ -184,7 +184,7 @@
 return NumVectorRegs;
   }
   
-  return DestVT;
+  return 1;
 }
 
 
//===--===//



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.65 - 1.66
---
Log message:

Another typo. Pointed out by Nate Begeman.

---
Diffs of the changes:  (+1 -1)

 TargetLowering.cpp |2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.65 
llvm/lib/Target/TargetLowering.cpp:1.66
--- llvm/lib/Target/TargetLowering.cpp:1.65 Wed May 17 13:10:06 2006
+++ llvm/lib/Target/TargetLowering.cpp  Wed May 17 13:22:14 2006
@@ -144,7 +144,7 @@
 }
 
 /// getPackedTypeBreakdown - Packed types are broken down into some number of
-/// legal first class types. For example, 8 x float maps to 2 MVT::v2f32
+/// legal first class types. For example, 8 x float maps to 2 MVT::v4f32
 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
 ///
 /// This method returns the number and type of the resultant breakdown.



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Andrew Lenharth]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.62 - 1.63
---
Log message:

Move this code to a common place

---
Diffs of the changes:  (+265 -0)

 TargetLowering.cpp |  265 +
 1 files changed, 265 insertions(+)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.62 
llvm/lib/Target/TargetLowering.cpp:1.63
--- llvm/lib/Target/TargetLowering.cpp:1.62 Fri May 12 01:33:48 2006
+++ llvm/lib/Target/TargetLowering.cpp  Tue May 16 12:42:15 2006
@@ -1330,3 +1330,268 @@
 bool TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
   return false;
 }
+
+
+// Magic for divide replacement
+
+struct ms {
+  int64_t m;  // magic number
+  int64_t s;  // shift amount
+};
+
+struct mu {
+  uint64_t m; // magic number
+  int64_t a;  // add indicator
+  int64_t s;  // shift amount
+};
+
+/// magic - calculate the magic numbers required to codegen an integer sdiv as
+/// a sequence of multiply and shifts.  Requires that the divisor not be 0, 1,
+/// or -1.
+static ms magic32(int32_t d) {
+  int32_t p;
+  uint32_t ad, anc, delta, q1, r1, q2, r2, t;
+  const uint32_t two31 = 0x8000U;
+  struct ms mag;
+  
+  ad = abs(d);
+  t = two31 + ((uint32_t)d  31);
+  anc = t - 1 - t%ad;   // absolute value of nc
+  p = 31;   // initialize p
+  q1 = two31/anc;   // initialize q1 = 2p/abs(nc)
+  r1 = two31 - q1*anc;  // initialize r1 = rem(2p,abs(nc))
+  q2 = two31/ad;// initialize q2 = 2p/abs(d)
+  r2 = two31 - q2*ad;   // initialize r2 = rem(2p,abs(d))
+  do {
+p = p + 1;
+q1 = 2*q1;// update q1 = 2p/abs(nc)
+r1 = 2*r1;// update r1 = rem(2p/abs(nc))
+if (r1 = anc) {  // must be unsigned comparison
+  q1 = q1 + 1;
+  r1 = r1 - anc;
+}
+q2 = 2*q2;// update q2 = 2p/abs(d)
+r2 = 2*r2;// update r2 = rem(2p/abs(d))
+if (r2 = ad) {   // must be unsigned comparison
+  q2 = q2 + 1;
+  r2 = r2 - ad;
+}
+delta = ad - r2;
+  } while (q1  delta || (q1 == delta  r1 == 0));
+  
+  mag.m = (int32_t)(q2 + 1); // make sure to sign extend
+  if (d  0) mag.m = -mag.m; // resulting magic number
+  mag.s = p - 32;// resulting shift
+  return mag;
+}
+
+/// magicu - calculate the magic numbers required to codegen an integer udiv as
+/// a sequence of multiply, add and shifts.  Requires that the divisor not be 
0.
+static mu magicu32(uint32_t d) {
+  int32_t p;
+  uint32_t nc, delta, q1, r1, q2, r2;
+  struct mu magu;
+  magu.a = 0;   // initialize add indicator
+  nc = - 1 - (-d)%d;
+  p = 31;   // initialize p
+  q1 = 0x8000/nc;   // initialize q1 = 2p/nc
+  r1 = 0x8000 - q1*nc;  // initialize r1 = rem(2p,nc)
+  q2 = 0x7FFF/d;// initialize q2 = (2p-1)/d
+  r2 = 0x7FFF - q2*d;   // initialize r2 = rem((2p-1),d)
+  do {
+p = p + 1;
+if (r1 = nc - r1 ) {
+  q1 = 2*q1 + 1;  // update q1
+  r1 = 2*r1 - nc; // update r1
+}
+else {
+  q1 = 2*q1; // update q1
+  r1 = 2*r1; // update r1
+}
+if (r2 + 1 = d - r2) {
+  if (q2 = 0x7FFF) magu.a = 1;
+  q2 = 2*q2 + 1; // update q2
+  r2 = 2*r2 + 1 - d; // update r2
+}
+else {
+  if (q2 = 0x8000) magu.a = 1;
+  q2 = 2*q2; // update q2
+  r2 = 2*r2 + 1; // update r2
+}
+delta = d - 1 - r2;
+  } while (p  64  (q1  delta || (q1 == delta  r1 == 0)));
+  magu.m = q2 + 1; // resulting magic number
+  magu.s = p - 32;  // resulting shift
+  return magu;
+}
+
+/// magic - calculate the magic numbers required to codegen an integer sdiv as
+/// a sequence of multiply and shifts.  Requires that the divisor not be 0, 1,
+/// or -1.
+static ms magic64(int64_t d) {
+  int64_t p;
+  uint64_t ad, anc, delta, q1, r1, q2, r2, t;
+  const uint64_t two63 = 9223372036854775808ULL; // 2^63
+  struct ms mag;
+  
+  ad = d = 0 ? d : -d;
+  t = two63 + ((uint64_t)d  63);
+  anc = t - 1 - t%ad;   // absolute value of nc
+  p = 63;   // initialize p
+  q1 = two63/anc;   // initialize q1 = 2p/abs(nc)
+  r1 = two63 - q1*anc;  // initialize r1 = rem(2p,abs(nc))
+  q2 = two63/ad;// initialize q2 = 2p/abs(d)
+  r2 = two63 - q2*ad;   // initialize r2 = rem(2p,abs(d))
+  do {
+p = p + 1;
+q1 = 2*q1;// update q1 = 2p/abs(nc)
+r1 = 2*r1;// update r1 = rem(2p/abs(nc))
+if (r1 = anc) {  // must be unsigned comparison
+  q1 = q1 + 1;
+  r1 = r1 - anc;
+}
+q2 = 2*q2;// update q2 = 2p/abs(d)
+r2 = 2*r2;// update r2 = rem(2p/abs(d))
+if (r2 = ad) {   // must be unsigned comparison
+  q2 = q2 + 1;
+  r2 = r2 - ad;
+}
+delta = ad - r2;
+  } while (q1  delta || (q1 == delta  r1 == 0));
+  
+  mag.m = q2 + 1;
+  if (d  0) mag.m = -mag.m; // resulting magic number
+  mag.s = p - 64;// resulting shift
+  return mag;
+}
+
+/// magicu - calculate the 

[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Andrew Lenharth]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.63 - 1.64
---
Log message:

this should be 128 I think

---
Diffs of the changes:  (+1 -1)

 TargetLowering.cpp |2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.63 
llvm/lib/Target/TargetLowering.cpp:1.64
--- llvm/lib/Target/TargetLowering.cpp:1.63 Tue May 16 12:42:15 2006
+++ llvm/lib/Target/TargetLowering.cpp  Tue May 16 12:45:23 2006
@@ -1500,7 +1500,7 @@
   r2 = 2*r2 + 1; // update r2
 }
 delta = d - 1 - r2;
-  } while (p  64  (q1  delta || (q1 == delta  r1 == 0)));
+  } while (p  128  (q1  delta || (q1 == delta  r1 == 0)));
   magu.m = q2 + 1; // resulting magic number
   magu.s = p - 64;  // resulting shift
   return magu;



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Owen Anderson]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.61 - 1.62
---
Log message:

Refactor a bunch of includes so that TargetMachine.h doesn't have to include
TargetData.h.  This should make recompiles a bit faster with my current
TargetData tinkering.


---
Diffs of the changes:  (+1 -0)

 TargetLowering.cpp |1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.61 
llvm/lib/Target/TargetLowering.cpp:1.62
--- llvm/lib/Target/TargetLowering.cpp:1.61 Mon May  8 12:22:53 2006
+++ llvm/lib/Target/TargetLowering.cpp  Fri May 12 01:33:48 2006
@@ -12,6 +12,7 @@
 
//===--===//
 
 #include llvm/Target/TargetLowering.h
+#include llvm/Target/TargetData.h
 #include llvm/Target/TargetMachine.h
 #include llvm/Target/MRegisterInfo.h
 #include llvm/DerivedTypes.h



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.60 - 1.61
---
Log message:

When tracking demanded bits, if any bits from the sext of an SRA are demanded,
then so is the input sign bit.  This fixes mediabench/g721 on X86.


---
Diffs of the changes:  (+8 -2)

 TargetLowering.cpp |   10 --
 1 files changed, 8 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.60 
llvm/lib/Target/TargetLowering.cpp:1.61
--- llvm/lib/Target/TargetLowering.cpp:1.60 Sat May  6 18:48:13 2006
+++ llvm/lib/Target/TargetLowering.cpp  Mon May  8 12:22:53 2006
@@ -467,8 +467,14 @@
   HighBits = MVT::getSizeInBits(VT) - ShAmt;
   uint64_t TypeMask = MVT::getIntVTBitMask(VT);
   
-  if (SimplifyDemandedBits(Op.getOperand(0),
-   (DemandedMask  ShAmt)  TypeMask,
+  uint64_t InDemandedMask = (DemandedMask  ShAmt)  TypeMask;
+
+  // If any of the demanded bits are produced by the sign extension, we 
also
+  // demand the input sign bit.
+  if (HighBits  DemandedMask)
+InDemandedMask |= MVT::getIntVTSignBit(VT);
+  
+  if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
KnownZero, KnownOne, TLO, Depth+1))
 return true;
   assert((KnownZero  KnownOne) == 0  Bits known to be one AND zero?); 



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.56 - 1.57
---
Log message:

Add some really really simple code for computing sign-bit propagation.

This will certainly be enhanced in the future.


---
Diffs of the changes:  (+95 -0)

 TargetLowering.cpp |   95 +
 1 files changed, 95 insertions(+)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.56 
llvm/lib/Target/TargetLowering.cpp:1.57
--- llvm/lib/Target/TargetLowering.cpp:1.56 Fri May  5 19:11:52 2006
+++ llvm/lib/Target/TargetLowering.cpp  Sat May  6 04:27:13 2006
@@ -995,6 +995,101 @@
   KnownOne = 0;
 }
 
+/// ComputeNumSignBits - Return the number of times the sign bit of the
+/// register is replicated into the other bits.  We know that at least 1 bit
+/// is always equal to the sign bit (itself), but other cases can give us
+/// information.  For example, immediately after an SRA X, 2, we know that
+/// the top 3 bits are all equal to each other, so we return 3.
+unsigned TargetLowering::ComputeNumSignBits(SDOperand Op, unsigned Depth) 
const{
+  MVT::ValueType VT = Op.getValueType();
+  assert(MVT::isInteger(VT)  Invalid VT!);
+  unsigned VTBits = MVT::getSizeInBits(VT);
+  unsigned Tmp, Tmp2;
+  
+  if (Depth == 6)
+return 1;  // Limit search depth.
+
+  switch (Op.getOpcode()) {
+  default: 
+// Allow the target to implement this method for its nodes.
+if (Op.getOpcode() = ISD::BUILTIN_OP_END) {
+  case ISD::INTRINSIC_WO_CHAIN:
+  case ISD::INTRINSIC_W_CHAIN:
+  case ISD::INTRINSIC_VOID:
+  unsigned NumBits = ComputeNumSignBitsForTargetNode(Op, Depth);
+  if (NumBits  1) return NumBits;
+}
+
+// FIXME: Should use computemaskedbits to look at the top bits.
+return 1;
+
+  case ISD::AssertSext:
+Tmp = MVT::getSizeInBits(castVTSDNode(Op.getOperand(1))-getVT());
+return VTBits-Tmp+1;
+  case ISD::AssertZext:
+Tmp = MVT::getSizeInBits(castVTSDNode(Op.getOperand(1))-getVT());
+return VTBits-Tmp;
+
+  case ISD::SIGN_EXTEND_INREG:
+// Max of the input and what this extends.
+Tmp = MVT::getSizeInBits(castVTSDNode(Op.getOperand(1))-getVT());
+Tmp = VTBits-Tmp+1;
+
+Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1);
+return std::max(Tmp, Tmp2);
+
+  case ISD::SRA:
+Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
+// SRA X, C   - adds C sign bits.
+if (ConstantSDNode *C = dyn_castConstantSDNode(Op.getOperand(1))) {
+  Tmp += C-getValue();
+  if (Tmp  VTBits) Tmp = VTBits;
+}
+return Tmp;
+
+  case ISD::ADD:
+  case ISD::SUB:
+// Add and sub can have at most one carry bit.  Thus we know that the 
output
+// is, at worst, one more bit than the inputs.
+Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
+if (Tmp == 1) return 1;
+Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
+if (Tmp2 == 1) return 1;
+return std::min(Tmp, Tmp2)-1;
+
+  //case ISD::ZEXTLOAD:   // 16 bits known
+  //case ISD::SEXTLOAD:   // 17 bits known
+  //case ISD::Constant:
+  //case ISD::SIGN_EXTEND:
+  //
+  }
+  
+#if 0
+  // fold (sext_in_reg (setcc x)) - setcc x iff (setcc x) == 0 or -1
+  if (N0.getOpcode() == ISD::SETCC 
+  TLI.getSetCCResultContents() == 
+  TargetLowering::ZeroOrNegativeOneSetCCResult)
+return N0;
+#endif
+}
+
+
+
+/// ComputeNumSignBitsForTargetNode - This method can be implemented by
+/// targets that want to expose additional information about sign bits to the
+/// DAG Combiner.
+unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op,
+ unsigned Depth) const 
{
+  assert((Op.getOpcode() = ISD::BUILTIN_OP_END ||
+  Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
+  Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
+  Op.getOpcode() == ISD::INTRINSIC_VOID) 
+ Should use ComputeNumSignBits if you don't know whether Op
+  is a target node!);
+  return 1;
+}
+
+
 SDOperand TargetLowering::
 PerformDAGCombine(SDNode *N, DAGCombinerInfo DCI) const {
   // Default implementation: no optimization.



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.59 - 1.60
---
Log message:

Use ComputeMaskedBits to determine # sign bits as a fallback.  This allows us 
to handle all kinds of stuff, including silly things like:
sextinreg(setcc,i16) - setcc.


---
Diffs of the changes:  (+23 -2)

 TargetLowering.cpp |   25 +++--
 1 files changed, 23 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.59 
llvm/lib/Target/TargetLowering.cpp:1.60
--- llvm/lib/Target/TargetLowering.cpp:1.59 Sat May  6 18:40:29 2006
+++ llvm/lib/Target/TargetLowering.cpp  Sat May  6 18:48:13 2006
@@ -1176,8 +1176,29 @@
 if (NumBits  1) return NumBits;
   }
   
-  // FIXME: Should use computemaskedbits to look at the top bits.
-  return 1;
+  // Finally, if we can prove that the top bits of the result are 0's or 1's,
+  // use this information.
+  uint64_t KnownZero, KnownOne;
+  uint64_t Mask = MVT::getIntVTBitMask(VT);
+  ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
+  
+  uint64_t SignBit = MVT::getIntVTSignBit(VT);
+  if (KnownZero  SignBit) {// SignBit is 0
+Mask = KnownZero;
+  } else if (KnownOne  SignBit) {  // SignBit is 1;
+Mask = KnownOne;
+  } else {
+// Nothing known.
+return 1;
+  }
+  
+  // Okay, we know that the sign bit in Mask is set.  Use CLZ to determine
+  // the number of identical bits in the top of the input value.
+  Mask ^= ~0ULL;
+  Mask = 64-VTBits;
+  // Return # leading zeros.  We use 'min' here in case Val was zero before
+  // shifting.  We don't want to return '64' as for an i32 0.
+  return std::min(VTBits, CountLeadingZeros_64(Mask));
 }
 
 



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.54 - 1.55
---
Log message:

Implement ComputeMaskedBits/SimplifyDemandedBits for ISD::TRUNCATE


---
Diffs of the changes:  (+18 -0)

 TargetLowering.cpp |   18 ++
 1 files changed, 18 insertions(+)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.54 
llvm/lib/Target/TargetLowering.cpp:1.55
--- llvm/lib/Target/TargetLowering.cpp:1.54 Tue May  2 20:29:56 2006
+++ llvm/lib/Target/TargetLowering.cpp  Fri May  5 17:32:12 2006
@@ -607,6 +607,16 @@
 assert((KnownZero  KnownOne) == 0  Bits known to be one AND zero?); 
 break;
   }
+  case ISD::TRUNCATE: {
+if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask,
+ KnownZero, KnownOne, TLO, Depth+1))
+  return true;
+assert((KnownZero  KnownOne) == 0  Bits known to be one AND zero?); 
+uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
+KnownZero = OutMask;
+KnownOne = OutMask;
+break;
+  }
   case ISD::AssertZext: {
 MVT::ValueType VT = castVTSDNode(Op.getOperand(1))-getVT();
 uint64_t InMask = MVT::getIntVTBitMask(VT);
@@ -864,6 +874,14 @@
   KnownZero, KnownOne, Depth+1);
 return;
   }
+  case ISD::TRUNCATE: {
+ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
+assert((KnownZero  KnownOne) == 0  Bits known to be one AND zero?); 
+uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
+KnownZero = OutMask;
+KnownOne = OutMask;
+break;
+  }
   case ISD::AssertZext: {
 MVT::ValueType VT = castVTSDNode(Op.getOperand(1))-getVT();
 uint64_t InMask = MVT::getIntVTBitMask(VT);



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.55 - 1.56
---
Log message:

Fold (trunc (srl x, c)) - (srl (trunc x), c)


---
Diffs of the changes:  (+32 -0)

 TargetLowering.cpp |   32 
 1 files changed, 32 insertions(+)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.55 
llvm/lib/Target/TargetLowering.cpp:1.56
--- llvm/lib/Target/TargetLowering.cpp:1.55 Fri May  5 17:32:12 2006
+++ llvm/lib/Target/TargetLowering.cpp  Fri May  5 19:11:52 2006
@@ -608,9 +608,41 @@
 break;
   }
   case ISD::TRUNCATE: {
+// Simplify the input, using demanded bit information, and compute the 
known
+// zero/one bits live out.
 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask,
  KnownZero, KnownOne, TLO, Depth+1))
   return true;
+
+// If the input is only used by this truncate, see if we can shrink it 
based
+// on the known demanded bits.
+if (Op.getOperand(0).Val-hasOneUse()) {
+  SDOperand In = Op.getOperand(0);
+  switch (In.getOpcode()) {
+  default: break;
+  case ISD::SRL:
+// Shrink SRL by a constant if none of the high bits shifted in are
+// demanded.
+if (ConstantSDNode *ShAmt = 
dyn_castConstantSDNode(In.getOperand(1))){
+  uint64_t HighBits = MVT::getIntVTBitMask(In.getValueType());
+  HighBits = ~MVT::getIntVTBitMask(Op.getValueType());
+  HighBits = ShAmt-getValue();
+  
+  if (ShAmt-getValue()  MVT::getSizeInBits(Op.getValueType()) 
+  (DemandedMask  HighBits) == 0) {
+// None of the shifted in bits are needed.  Add a truncate of the
+// shift input, then shift it.
+SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, 
+ Op.getValueType(), 
+ In.getOperand(0));
+return TLO.CombineTo(Op, 
TLO.DAG.getNode(ISD::SRL,Op.getValueType(),
+   NewTrunc, 
In.getOperand(1)));
+  }
+}
+break;
+  }
+}
+
 assert((KnownZero  KnownOne) == 0  Bits known to be one AND zero?); 
 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
 KnownZero = OutMask;



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp TargetMachine.cpp

[Owen Anderson]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.53 - 1.54
TargetMachine.cpp updated: 1.43 - 1.44
---
Log message:

Refactor TargetMachine, pushing handling of TargetData into the target-specific 
subclasses.  This has one caller-visible change: getTargetData() now returns a 
pointer instead of a reference.

This fixes PR 759: http://llvm.cs.uiuc.edu/PR759 .



---
Diffs of the changes:  (+3 -17)

 TargetLowering.cpp |4 ++--
 TargetMachine.cpp  |   16 +---
 2 files changed, 3 insertions(+), 17 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.53 
llvm/lib/Target/TargetLowering.cpp:1.54
--- llvm/lib/Target/TargetLowering.cpp:1.53 Sun Apr  2 00:19:46 2006
+++ llvm/lib/Target/TargetLowering.cpp  Tue May  2 20:29:56 2006
@@ -27,8 +27,8 @@
   // All operations default to being supported.
   memset(OpActions, 0, sizeof(OpActions));
 
-  IsLittleEndian = TD.isLittleEndian();
-  ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD.getIntPtrType());
+  IsLittleEndian = TD-isLittleEndian();
+  ShiftAmountTy = SetCCResultTy = PointerTy = 
getValueType(TD-getIntPtrType());
   ShiftAmtHandling = Undefined;
   memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
   memset(TargetDAGCombineArray, 0, 


Index: llvm/lib/Target/TargetMachine.cpp
diff -u llvm/lib/Target/TargetMachine.cpp:1.43 
llvm/lib/Target/TargetMachine.cpp:1.44
--- llvm/lib/Target/TargetMachine.cpp:1.43  Wed Mar 22 23:43:15 2006
+++ llvm/lib/Target/TargetMachine.cpp   Tue May  2 20:29:56 2006
@@ -69,23 +69,9 @@
 //---
 // TargetMachine Class
 //
-TargetMachine::TargetMachine(const std::string name, bool LittleEndian,
- unsigned char PtrSize, unsigned char PtrAl,
- unsigned char DoubleAl, unsigned char FloatAl,
- unsigned char LongAl, unsigned char IntAl,
- unsigned char ShortAl, unsigned char ByteAl,
- unsigned char BoolAl)
-  : Name(name), DataLayout(name, LittleEndian,
-   PtrSize, PtrAl, DoubleAl, FloatAl, LongAl,
-   IntAl, ShortAl, ByteAl, BoolAl) {
-}
-
-TargetMachine::TargetMachine(const std::string name, const TargetData TD)
-  : Name(name), DataLayout(TD) {
-}
 
 TargetMachine::TargetMachine(const std::string name, const Module M)
-  : Name(name), DataLayout(name, M) {
+  : Name(name) {
 }
 
 TargetMachine::~TargetMachine() {



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.52 - 1.53
---
Log message:

relax assertion


---
Diffs of the changes:  (+4 -1)

 TargetLowering.cpp |5 -
 1 files changed, 4 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.52 
llvm/lib/Target/TargetLowering.cpp:1.53
--- llvm/lib/Target/TargetLowering.cpp:1.52 Sun Apr  2 00:15:09 2006
+++ llvm/lib/Target/TargetLowering.cpp  Sun Apr  2 00:19:46 2006
@@ -935,7 +935,10 @@
 uint64_t KnownZero, 
 uint64_t KnownOne,
 unsigned Depth) const {
-  assert(Op.getOpcode() = ISD::BUILTIN_OP_END 
+  assert((Op.getOpcode() = ISD::BUILTIN_OP_END ||
+  Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
+  Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
+  Op.getOpcode() == ISD::INTRINSIC_VOID) 
  Should use MaskedValueIsZero if you don't know whether Op
   is a target node!);
   KnownZero = 0;



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.48 - 1.49
---
Log message:

Implement TargetLowering::getPackedTypeBreakdown


---
Diffs of the changes:  (+41 -0)

 TargetLowering.cpp |   41 +
 1 files changed, 41 insertions(+)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.48 
llvm/lib/Target/TargetLowering.cpp:1.49
--- llvm/lib/Target/TargetLowering.cpp:1.48 Thu Mar 23 17:24:51 2006
+++ llvm/lib/Target/TargetLowering.cpp  Thu Mar 30 18:28:56 2006
@@ -14,6 +14,7 @@
 #include llvm/Target/TargetLowering.h
 #include llvm/Target/TargetMachine.h
 #include llvm/Target/MRegisterInfo.h
+#include llvm/DerivedTypes.h
 #include llvm/CodeGen/SelectionDAG.h
 #include llvm/ADT/StringExtras.h
 #include llvm/Support/MathExtras.h
@@ -141,6 +142,46 @@
   return NULL;
 }
 
+/// getPackedTypeBreakdown - Packed types are broken down into some number of
+/// legal scalar types.  For example, 8 x float maps to 2 MVT::v2f32 values
+/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
+///
+/// This method returns the number and type of the resultant breakdown.
+///
+MVT::ValueType TargetLowering::getPackedTypeBreakdown(const PackedType *PTy, 
+  unsigned NumVals) const 
{
+  // Figure out the right, legal destination reg to copy into.
+  unsigned NumElts = PTy-getNumElements();
+  MVT::ValueType EltTy = getValueType(PTy-getElementType());
+  
+  unsigned NumVectorRegs = 1;
+  
+  // Divide the input until we get to a supported size.  This will always
+  // end with a scalar if the target doesn't support vectors.
+  while (NumElts  1  !isTypeLegal(getVectorType(EltTy, NumElts))) {
+NumElts = 1;
+NumVectorRegs = 1;
+  }
+  
+  MVT::ValueType VT;
+  if (NumElts == 1)
+VT = EltTy;
+  else
+VT = getVectorType(EltTy, NumElts);
+
+  MVT::ValueType DestVT = getTypeToTransformTo(VT);
+  if (DestVT  VT) {
+// Value is expanded, e.g. i64 - i16.
+NumVals = 
NumVectorRegs*(MVT::getSizeInBits(VT)/MVT::getSizeInBits(DestVT));
+  } else {
+// Otherwise, promotion or legal types use the same number of registers as
+// the vector decimated to the appropriate level.
+NumVals = NumVectorRegs;
+  }
+  
+  return DestVT;
+}
+
 
//===--===//
 //  Optimization Methods
 
//===--===//



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.49 - 1.50
---
Log message:

Modify the TargetLowering::getPackedTypeBreakdown method to also return the
unpromoted element type.



---
Diffs of the changes:  (+7 -4)

 TargetLowering.cpp |   11 +++
 1 files changed, 7 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.49 
llvm/lib/Target/TargetLowering.cpp:1.50
--- llvm/lib/Target/TargetLowering.cpp:1.49 Thu Mar 30 18:28:56 2006
+++ llvm/lib/Target/TargetLowering.cpp  Thu Mar 30 18:46:36 2006
@@ -148,11 +148,13 @@
 ///
 /// This method returns the number and type of the resultant breakdown.
 ///
-MVT::ValueType TargetLowering::getPackedTypeBreakdown(const PackedType *PTy, 
-  unsigned NumVals) const 
{
+unsigned TargetLowering::getPackedTypeBreakdown(const PackedType *PTy, 
+MVT::ValueType PTyElementVT,
+  MVT::ValueType PTyLegalElementVT) const 
{
   // Figure out the right, legal destination reg to copy into.
   unsigned NumElts = PTy-getNumElements();
   MVT::ValueType EltTy = getValueType(PTy-getElementType());
+  PTyElementVT = EltTy;
   
   unsigned NumVectorRegs = 1;
   
@@ -170,13 +172,14 @@
 VT = getVectorType(EltTy, NumElts);
 
   MVT::ValueType DestVT = getTypeToTransformTo(VT);
+  PTyLegalElementVT = DestVT;
   if (DestVT  VT) {
 // Value is expanded, e.g. i64 - i16.
-NumVals = 
NumVectorRegs*(MVT::getSizeInBits(VT)/MVT::getSizeInBits(DestVT));
+return NumVectorRegs*(MVT::getSizeInBits(VT)/MVT::getSizeInBits(DestVT));
   } else {
 // Otherwise, promotion or legal types use the same number of registers as
 // the vector decimated to the appropriate level.
-NumVals = NumVectorRegs;
+return NumVectorRegs;
   }
   
   return DestVT;



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.50 - 1.51
---
Log message:

Was returning the wrong type.


---
Diffs of the changes:  (+5 -4)

 TargetLowering.cpp |9 +
 1 files changed, 5 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.50 
llvm/lib/Target/TargetLowering.cpp:1.51
--- llvm/lib/Target/TargetLowering.cpp:1.50 Thu Mar 30 18:46:36 2006
+++ llvm/lib/Target/TargetLowering.cpp  Thu Mar 30 19:50:09 2006
@@ -154,7 +154,6 @@
   // Figure out the right, legal destination reg to copy into.
   unsigned NumElts = PTy-getNumElements();
   MVT::ValueType EltTy = getValueType(PTy-getElementType());
-  PTyElementVT = EltTy;
   
   unsigned NumVectorRegs = 1;
   
@@ -166,10 +165,12 @@
   }
   
   MVT::ValueType VT;
-  if (NumElts == 1)
+  if (NumElts == 1) {
 VT = EltTy;
-  else
-VT = getVectorType(EltTy, NumElts);
+  } else {
+VT = getVectorType(EltTy, NumElts); 
+  }
+  PTyElementVT = VT;
 
   MVT::ValueType DestVT = getTypeToTransformTo(VT);
   PTyLegalElementVT = DestVT;



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.47 - 1.48
---
Log message:

Typo

---
Diffs of the changes:  (+1 -1)

 TargetLowering.cpp |2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.47 
llvm/lib/Target/TargetLowering.cpp:1.48
--- llvm/lib/Target/TargetLowering.cpp:1.47 Thu Mar 16 13:50:01 2006
+++ llvm/lib/Target/TargetLowering.cpp  Thu Mar 23 17:24:51 2006
@@ -128,7 +128,7 @@
   // Loop over all of the legal vector value types, specifying an identity type
   // transformation.
   for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
-   i != MVT::LAST_VECTOR_VALUETYPE; ++i) {
+   i = MVT::LAST_VECTOR_VALUETYPE; ++i) {
 if (isTypeLegal((MVT::ValueType)i))
   TransformToType[i] = (MVT::ValueType)i;
   }



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.46 - 1.47
---
Log message:

set TransformToType correctly for vector types.


---
Diffs of the changes:  (+8 -0)

 TargetLowering.cpp |8 
 1 files changed, 8 insertions(+)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.46 
llvm/lib/Target/TargetLowering.cpp:1.47
--- llvm/lib/Target/TargetLowering.cpp:1.46 Mon Mar 13 17:16:31 2006
+++ llvm/lib/Target/TargetLowering.cpp  Thu Mar 16 13:50:01 2006
@@ -124,6 +124,14 @@
   // Set MVT::Vector to always be Expanded
   SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType, 
  ValueTypeActions);
+  
+  // Loop over all of the legal vector value types, specifying an identity type
+  // transformation.
+  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
+   i != MVT::LAST_VECTOR_VALUETYPE; ++i) {
+if (isTypeLegal((MVT::ValueType)i))
+  TransformToType[i] = (MVT::ValueType)i;
+  }
 
   assert(isTypeLegal(MVT::f64)  Target does not support FP?);
   TransformToType[MVT::f64] = MVT::f64;



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.45 - 1.46
---
Log message:

Add LSR hooks.


---
Diffs of the changes:  (+13 -0)

 TargetLowering.cpp |   13 +
 1 files changed, 13 insertions(+)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.45 
llvm/lib/Target/TargetLowering.cpp:1.46
--- llvm/lib/Target/TargetLowering.cpp:1.45 Mon Mar 13 00:42:16 2006
+++ llvm/lib/Target/TargetLowering.cpp  Mon Mar 13 17:16:31 2006
@@ -976,3 +976,16 @@
   
   return std::pairunsigned, const TargetRegisterClass*(0, 0);
 }
+
+//===--===//
+//  Loop Strength Reduction hooks
+//===--===//
+
+/// isLegalAddressImmediate - Return true if the integer value or
+/// GlobalValue can be used as the offset of the target addressing mode.
+bool TargetLowering::isLegalAddressImmediate(int64_t V) const {
+  return false;
+}
+bool TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
+  return false;
+}



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.41 - 1.42
---
Log message:

Add interfaces for targets to provide target-specific dag combiner 
optimizations.


---
Diffs of the changes:  (+8 -0)

 TargetLowering.cpp |8 
 1 files changed, 8 insertions(+)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.41 
llvm/lib/Target/TargetLowering.cpp:1.42
--- llvm/lib/Target/TargetLowering.cpp:1.41 Sun Feb 26 19:00:42 2006
+++ llvm/lib/Target/TargetLowering.cpp  Tue Feb 28 22:52:55 2006
@@ -30,6 +30,8 @@
   ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD.getIntPtrType());
   ShiftAmtHandling = Undefined;
   memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
+  memset(TargetDAGCombineArray, 0, 
+ sizeof(TargetDAGCombineArray)/sizeof(TargetDAGCombineArray[0]));
   maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
   allowUnalignedMemoryAccesses = false;
   UseUnderscoreSetJmpLongJmp = false;
@@ -916,6 +918,12 @@
   KnownOne = 0;
 }
 
+SDOperand TargetLowering::
+PerformDAGCombine(SDNode *N, DAGCombinerInfo DCI) const {
+  // Default implementation: no optimization.
+  return SDOperand();
+}
+
 
//===--===//
 //  Inline Assembler Implementation Methods
 
//===--===//



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.38 - 1.39
---
Log message:

Just like we use the RHS of an AND to simplify the LHS, use the LHS to 
simplify the RHS.  This allows for the elimination of many thousands of 
ands from multisource, and compiles CodeGen/PowerPC/and-elim.ll:test2 
into this:

_test2:
srwi r2, r3, 1
xori r3, r2, 40961
blr

instead of this:

_test2:
rlwinm r2, r3, 31, 17, 31
xori r2, r2, 40961
rlwinm r3, r2, 0, 16, 31
blr



---
Diffs of the changes:  (+17 -0)

 TargetLowering.cpp |   17 +
 1 files changed, 17 insertions(+)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.38 
llvm/lib/Target/TargetLowering.cpp:1.39
--- llvm/lib/Target/TargetLowering.cpp:1.38 Sun Feb 26 17:36:02 2006
+++ llvm/lib/Target/TargetLowering.cpp  Sun Feb 26 18:22:28 2006
@@ -223,6 +223,23 @@
 // If the RHS is a constant, see if we can simplify it.
 if (TLO.ShrinkDemandedConstant(Op, DemandedMask  ~KnownZero2))
   return true;
+  
+// If the RHS is a constant, check to see if the LHS would be zero without
+// using the bits from the RHS.  Above, we used knowledge about the RHS to
+// simplify the LHS, here we're using information from the LHS to simplify
+// the RHS.
+if (ConstantSDNode *RHSC = dyn_castConstantSDNode(Op.getOperand(1))) {
+  uint64_t LHSZero, LHSOne;
+  ComputeMaskedBits(Op.getOperand(0), DemandedMask,
+LHSZero, LHSOne, Depth+1);
+  // If the LHS already has zeros where RHSC does, this and is dead.
+  if ((LHSZero  DemandedMask) == (~RHSC-getValue()  DemandedMask))
+return TLO.CombineTo(Op, Op.getOperand(0));
+  // If any of the set bits in the RHS are known zero on the LHS, shrink
+  // the constant.
+  if (TLO.ShrinkDemandedConstant(Op, ~LHSZero  DemandedMask))
+return true;
+}
 
 // Output known-1 bits are only known if set in both the LHS  RHS.
 KnownOne = KnownOne2;



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.39 - 1.40
---
Log message:

Check RHS simplification before LHS simplification to avoid infinitely looping
on PowerPC/small-arguments.ll


---
Diffs of the changes:  (+17 -18)

 TargetLowering.cpp |   35 +--
 1 files changed, 17 insertions(+), 18 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.39 
llvm/lib/Target/TargetLowering.cpp:1.40
--- llvm/lib/Target/TargetLowering.cpp:1.39 Sun Feb 26 18:22:28 2006
+++ llvm/lib/Target/TargetLowering.cpp  Sun Feb 26 18:36:27 2006
@@ -201,7 +201,23 @@
 KnownZero = ~KnownOne  DemandedMask;
 return false;   // Don't fall through, will infinitely loop.
   case ISD::AND:
-// If either the LHS or the RHS are Zero, the result is zero.
+// If the RHS is a constant, check to see if the LHS would be zero without
+// using the bits from the RHS.  Below, we use knowledge about the RHS to
+// simplify the LHS, here we're using information from the LHS to simplify
+// the RHS.
+if (ConstantSDNode *RHSC = dyn_castConstantSDNode(Op.getOperand(1))) {
+  uint64_t LHSZero, LHSOne;
+  ComputeMaskedBits(Op.getOperand(0), DemandedMask,
+LHSZero, LHSOne, Depth+1);
+  // If the LHS already has zeros where RHSC does, this and is dead.
+  if ((LHSZero  DemandedMask) == (~RHSC-getValue()  DemandedMask))
+return TLO.CombineTo(Op, Op.getOperand(0));
+  // If any of the set bits in the RHS are known zero on the LHS, shrink
+  // the constant.
+  if (TLO.ShrinkDemandedConstant(Op, ~LHSZero  DemandedMask))
+return true;
+}
+
 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
  KnownOne, TLO, Depth+1))
   return true;
@@ -224,23 +240,6 @@
 if (TLO.ShrinkDemandedConstant(Op, DemandedMask  ~KnownZero2))
   return true;
   
-// If the RHS is a constant, check to see if the LHS would be zero without
-// using the bits from the RHS.  Above, we used knowledge about the RHS to
-// simplify the LHS, here we're using information from the LHS to simplify
-// the RHS.
-if (ConstantSDNode *RHSC = dyn_castConstantSDNode(Op.getOperand(1))) {
-  uint64_t LHSZero, LHSOne;
-  ComputeMaskedBits(Op.getOperand(0), DemandedMask,
-LHSZero, LHSOne, Depth+1);
-  // If the LHS already has zeros where RHSC does, this and is dead.
-  if ((LHSZero  DemandedMask) == (~RHSC-getValue()  DemandedMask))
-return TLO.CombineTo(Op, Op.getOperand(0));
-  // If any of the set bits in the RHS are known zero on the LHS, shrink
-  // the constant.
-  if (TLO.ShrinkDemandedConstant(Op, ~LHSZero  DemandedMask))
-return true;
-}
-
 // Output known-1 bits are only known if set in both the LHS  RHS.
 KnownOne = KnownOne2;
 // Output known-0 are known to be clear if zero in either the LHS | RHS.



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.36 - 1.37
---
Log message:

Recognize memory operand codes


---
Diffs of the changes:  (+6 -1)

 TargetLowering.cpp |7 ++-
 1 files changed, 6 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.36 
llvm/lib/Target/TargetLowering.cpp:1.37
--- llvm/lib/Target/TargetLowering.cpp:1.36 Wed Feb 22 17:00:51 2006
+++ llvm/lib/Target/TargetLowering.cpp  Thu Feb 23 19:10:46 2006
@@ -718,6 +718,10 @@
   switch (ConstraintLetter) {
   default: return C_Unknown;
   case 'r': return C_RegisterClass;
+  case 'm':// memory
+  case 'o':// offsetable
+  case 'V':// not offsetable
+return C_Memory;
   case 'i':// Simple Integer or Relocatable Constant
   case 'n':// Simple Integer
   case 's':// Relocatable Constant
@@ -728,7 +732,8 @@
   case 'M':
   case 'N':
   case 'O':
-  case 'P':  return C_Other;
+  case 'P':
+return C_Other;
   }
 }
 



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.35 - 1.36
---
Log message:

Don't return registers from register classes that aren't legal.


---
Diffs of the changes:  (+15 -2)

 TargetLowering.cpp |   17 +++--
 1 files changed, 15 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.35 
llvm/lib/Target/TargetLowering.cpp:1.36
--- llvm/lib/Target/TargetLowering.cpp:1.35 Tue Feb 21 18:56:38 2006
+++ llvm/lib/Target/TargetLowering.cpp  Wed Feb 22 17:00:51 2006
@@ -766,11 +766,24 @@
   for (MRegisterInfo::regclass_iterator RCI = RI-regclass_begin(),
E = RI-regclass_end(); RCI != E; ++RCI) {
 const TargetRegisterClass *RC = *RCI;
+
+// If none of the the value types for this register class are valid, we 
+// can't use it.  For example, 64-bit reg classes on 32-bit targets.
+bool isLegal = false;
+for (TargetRegisterClass::vt_iterator I = RC-vt_begin(), E = RC-vt_end();
+ I != E; ++I) {
+  if (isTypeLegal(*I)) {
+isLegal = true;
+break;
+  }
+}
+
+if (!isLegal) continue;
+
 for (TargetRegisterClass::iterator I = RC-begin(), E = RC-end(); 
  I != E; ++I) {
-  if (StringsEqualNoCase(RegName, RI-get(*I).Name)) {
+  if (StringsEqualNoCase(RegName, RI-get(*I).Name))
 return std::make_pair(*I, RC);
-  }
 }
   }
   



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.33 - 1.34
---
Log message:

Updates to match change of getRegForInlineAsmConstraint prototype


---
Diffs of the changes:  (+2 -1)

 TargetLowering.cpp |3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.33 
llvm/lib/Target/TargetLowering.cpp:1.34
--- llvm/lib/Target/TargetLowering.cpp:1.33 Fri Feb 17 20:43:25 2006
+++ llvm/lib/Target/TargetLowering.cpp  Tue Feb 21 17:11:00 2006
@@ -745,7 +745,8 @@
 
 
 std::vectorunsigned TargetLowering::
-getRegForInlineAsmConstraint(const std::string Constraint) const {
+getRegForInlineAsmConstraint(const std::string Constraint,
+ MVT::ValueType VT) const {
   // Not a physreg, must not be a register reference or something.
   if (Constraint[0] != '{') return std::vectorunsigned();
   assert(*(Constraint.end()-1) == '}'  Not a brace enclosed constraint?);



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.34 - 1.35
---
Log message:

split register class handling from explicit physreg handling.


---
Diffs of the changes:  (+21 -11)

 TargetLowering.cpp |   32 +---
 1 files changed, 21 insertions(+), 11 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.34 
llvm/lib/Target/TargetLowering.cpp:1.35
--- llvm/lib/Target/TargetLowering.cpp:1.34 Tue Feb 21 17:11:00 2006
+++ llvm/lib/Target/TargetLowering.cpp  Tue Feb 21 18:56:38 2006
@@ -745,24 +745,34 @@
 
 
 std::vectorunsigned TargetLowering::
+getRegClassForInlineAsmConstraint(const std::string Constraint,
+  MVT::ValueType VT) const {
+  return std::vectorunsigned();
+}
+
+
+std::pairunsigned, const TargetRegisterClass* TargetLowering::
 getRegForInlineAsmConstraint(const std::string Constraint,
  MVT::ValueType VT) const {
-  // Not a physreg, must not be a register reference or something.
-  if (Constraint[0] != '{') return std::vectorunsigned();
+  if (Constraint[0] != '{')
+return std::pairunsigned, const TargetRegisterClass*(0, 0);
   assert(*(Constraint.end()-1) == '}'  Not a brace enclosed constraint?);
 
   // Remove the braces from around the name.
   std::string RegName(Constraint.begin()+1, Constraint.end()-1);
-  
-  // Scan to see if this constraint is a register name.
+
+  // Figure out which register class contains this reg.
   const MRegisterInfo *RI = TM.getRegisterInfo();
-  for (unsigned i = 1, e = RI-getNumRegs(); i != e; ++i) {
-if (const char *Name = RI-get(i).Name)
-  if (StringsEqualNoCase(RegName, Name))
-return std::vectorunsigned(1, i);
+  for (MRegisterInfo::regclass_iterator RCI = RI-regclass_begin(),
+   E = RI-regclass_end(); RCI != E; ++RCI) {
+const TargetRegisterClass *RC = *RCI;
+for (TargetRegisterClass::iterator I = RC-begin(), E = RC-end(); 
+ I != E; ++I) {
+  if (StringsEqualNoCase(RegName, RI-get(*I).Name)) {
+return std::make_pair(*I, RC);
+  }
+}
   }
   
-  // Unknown physreg.
-  return std::vectorunsigned();
+  return std::pairunsigned, const TargetRegisterClass*(0, 0);
 }
-



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Nate Begeman]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.32 - 1.33
---
Log message:

Add a fold for add that exchanges it with a constant shift if possible, so
that the shift may be more easily folded into other operations.


---
Diffs of the changes:  (+24 -6)

 TargetLowering.cpp |   30 --
 1 files changed, 24 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.32 
llvm/lib/Target/TargetLowering.cpp:1.33
--- llvm/lib/Target/TargetLowering.cpp:1.32 Thu Feb 16 20:12:18 2006
+++ llvm/lib/Target/TargetLowering.cpp  Fri Feb 17 20:43:25 2006
@@ -459,6 +459,24 @@
CountTrailingZeros_64(~KnownZero2));
   KnownZero = (1ULL  KnownZeroOut) - 1;
   KnownOne = 0;
+  
+  SDOperand SH = Op.getOperand(0);
+  // fold (add (shl x, c1), (shl c2, c1)) - (shl (add x, c2), c1)
+  if (KnownZero  SH.getOpcode() == ISD::SHL  SH.Val-hasOneUse() 
+  Op.Val-hasOneUse()) {
+if (ConstantSDNode *SA = dyn_castConstantSDNode(SH.getOperand(1))) {
+  MVT::ValueType VT = Op.getValueType();
+  unsigned ShiftAmt = SA-getValue();
+  uint64_t AddAmt = AA-getValue();
+  uint64_t AddShr = AddAmt  ShiftAmt;
+  if (AddAmt == (AddShr  ShiftAmt)) {
+SDOperand ADD = TLO.DAG.getNode(ISD::ADD, VT, SH.getOperand(0),
+TLO.DAG.getConstant(AddShr, VT));
+SDOperand SHL = TLO.DAG.getNode(ISD::SHL, VT, 
ADD,SH.getOperand(1));
+return TLO.CombineTo(Op, SHL);
+  }
+}
+  }
 }
 break;
   case ISD::CTTZ:
@@ -577,7 +595,7 @@
   KnownOne  = SA-getValue();
   KnownZero |= (1ULL  SA-getValue())-1;  // low bits known zero.
 }
-break;
+return;
   case ISD::SRL:
 // (ushr X, C1)  C2 == 0   iff  (-1  C1)  C2 == 0
 if (ConstantSDNode *SA = dyn_castConstantSDNode(Op.getOperand(1))) {
@@ -585,12 +603,12 @@
   HighBits = MVT::getSizeInBits(Op.getValueType())-SA-getValue();
   Mask = SA-getValue();
   ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
-  assert((KnownZero  KnownOne) == 0Bits known to be one AND zero?); 
+  assert((KnownZero  KnownOne) == 0  Bits known to be one AND zero?); 
   KnownZero = SA-getValue();
   KnownOne  = SA-getValue();
   KnownZero |= HighBits;  // high bits known zero.
 }
-break;
+return;
   case ISD::SRA:
 if (ConstantSDNode *SA = dyn_castConstantSDNode(Op.getOperand(1))) {
   uint64_t HighBits = (1ULL  SA-getValue())-1;
@@ -611,7 +629,7 @@
 KnownOne |= HighBits;
   }
 }
-break;
+return;
   case ISD::CTTZ:
   case ISD::CTLZ:
   case ISD::CTPOP: {
@@ -666,12 +684,12 @@
 // We know that the top bits of C-X are clear if X contains less bits
 // than C (i.e. no wrap-around can happen).  For example, 20-X is
 // positive if we can prove that X is = 0 and  16.
-break;
+return;
   default:
 // Allow the target to implement this method for its nodes.
 if (Op.getOpcode() = ISD::BUILTIN_OP_END)
   computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne);
-break;
+return;
   }
 }
 



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Nate Begeman]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.30 - 1.31
---
Log message:

Rework the SelectionDAG-based implementations of SimplifyDemandedBits
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.


---
Diffs of the changes:  (+506 -122)

 TargetLowering.cpp |  628 ++---
 1 files changed, 506 insertions(+), 122 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.30 
llvm/lib/Target/TargetLowering.cpp:1.31
--- llvm/lib/Target/TargetLowering.cpp:1.30 Tue Feb 14 02:38:30 2006
+++ llvm/lib/Target/TargetLowering.cpp  Thu Feb 16 15:11:51 2006
@@ -135,175 +135,559 @@
 //  Optimization Methods
 
//===--===//
 
-/// DemandedBitsAreZero - Return true if 'Op  Mask' demands no bits from a bit
-/// set operation such as a sign extend or or/xor with constant whose only
-/// use is Op.  If it returns true, the old node that sets bits which are
-/// not demanded is returned in Old, and its replacement node is returned in
-/// New, such that callers of DemandedBitsAreZero may call CombineTo on them if
-/// desired.
-bool TargetLowering::DemandedBitsAreZero(const SDOperand Op, uint64_t Mask, 
- SDOperand Old, SDOperand New,
- SelectionDAG DAG) const {
-  // If the operation has more than one use, we're not interested in it.
-  // Tracking down and checking all uses would be problematic and slow.
-  if (!Op.Val-hasOneUse())
+/// ShrinkDemandedConstant - Check to see if the specified operand of the 
+/// specified instruction is a constant integer.  If so, check to see if there
+/// are any bits set in the constant that are not demanded.  If so, shrink the
+/// constant and return true.
+bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op, 
+uint64_t Demanded) 
{
+  // FIXME: ISD::SELECT
+  switch(Op.getOpcode()) {
+  default: break;
+  case ISD::AND:
+  case ISD::OR:
+  case ISD::XOR:
+if (ConstantSDNode *C = dyn_castConstantSDNode(Op.getOperand(1)))
+  if ((~Demanded  C-getValue()) != 0) {
+MVT::ValueType VT = Op.getValueType();
+SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
+DAG.getConstant(Demanded  C-getValue(), 
+VT));
+return CombineTo(Op, New);
+  }
+break;
+  }
+  return false;
+}
+
+/// SimplifyDemandedBits - Look at Op.  At this point, we know that only the
+/// DemandedMask bits of the result of Op are ever used downstream.  If we can
+/// use this information to simplify Op, create a new simplified DAG node and
+/// return true, returning the original and new nodes in Old and New. 
Otherwise,
+/// analyze the expression and return a mask of KnownOne and KnownZero bits for
+/// the expression (used to simplify the caller).  The KnownZero/One bits may
+/// only be accurate for those bits in the DemandedMask.
+bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 
+  uint64_t KnownZero,
+  uint64_t KnownOne,
+  TargetLoweringOpt TLO,
+  unsigned Depth) const {
+  KnownZero = KnownOne = 0;   // Don't know anything.
+  // Other users may use these bits.
+  if (!Op.Val-hasOneUse()) { 
+if (Depth != 0) {
+  // If not at the root, Just compute the KnownZero/KnownOne bits to 
+  // simplify things downstream.
+  ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
+  return false;
+}
+// If this is the root being simplified, allow it to have multiple uses,
+// just set the DemandedMask to all bits.
+DemandedMask = MVT::getIntVTBitMask(Op.getValueType());
+  } else if (DemandedMask == 0) {   
+// Not demanding any bits from Op.
+if (Op.getOpcode() != ISD::UNDEF)
+  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType()));
 return false;
-  
+  } else if (Depth == 6) {// Limit search depth.
+return false;
+  }
+
+  uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
   switch (Op.getOpcode()) {
+  case ISD::Constant:
+// We know all of the bits for a constant!
+KnownOne = castConstantSDNode(Op)-getValue()  DemandedMask;
+KnownZero = ~KnownOne  DemandedMask;
+return false;
   case ISD::AND:
-// (X  C1)  C2 == 0   iff   C1  C2 == 0.
-if (ConstantSDNode *AndRHS = dyn_castConstantSDNode(Op.getOperand(1))) {
-  uint64_t NewVal = Mask  AndRHS-getValue();
-  return DemandedBitsAreZero(Op.getOperand(0), NewVal, Old, New, DAG);
+// If either the LHS 

[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Jeff Cohen]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.31 - 1.32
---
Log message:

Fix bug noticed by VC++.

---
Diffs of the changes:  (+2 -2)

 TargetLowering.cpp |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.31 
llvm/lib/Target/TargetLowering.cpp:1.32
--- llvm/lib/Target/TargetLowering.cpp:1.31 Thu Feb 16 15:11:51 2006
+++ llvm/lib/Target/TargetLowering.cpp  Thu Feb 16 20:12:18 2006
@@ -243,9 +243,9 @@
 
 // If all of the demanded bits are known zero on one side, return the 
other.
 // These bits cannot contribute to the result of the 'or'.
-if ((DemandedMask  ~KnownOne2  KnownZero) == DemandedMask  ~KnownOne2)
+if ((DemandedMask  ~KnownOne2  KnownZero) == (DemandedMask  ~KnownOne2))
   return TLO.CombineTo(Op, Op.getOperand(0));
-if ((DemandedMask  ~KnownOne  KnownZero2) == DemandedMask  ~KnownOne)
+if ((DemandedMask  ~KnownOne  KnownZero2) == (DemandedMask  ~KnownOne))
   return TLO.CombineTo(Op, Op.getOperand(1));
 // If all of the potentially set bits on one side are known to be set on
 // the other side, just use the 'other' side.



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.29 - 1.30
---
Log message:

Rename maxStoresPerMemSet to maxStoresPerMemset, etc.


---
Diffs of the changes:  (+1 -1)

 TargetLowering.cpp |2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.29 
llvm/lib/Target/TargetLowering.cpp:1.30
--- llvm/lib/Target/TargetLowering.cpp:1.29 Fri Feb  3 20:13:02 2006
+++ llvm/lib/Target/TargetLowering.cpp  Tue Feb 14 02:38:30 2006
@@ -30,7 +30,7 @@
   ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD.getIntPtrType());
   ShiftAmtHandling = Undefined;
   memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
-  maxStoresPerMemSet = maxStoresPerMemCpy = maxStoresPerMemMove = 8;
+  maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
   allowUnalignedMemoryAccesses = false;
   UseUnderscoreSetJmpLongJmp = false;
   IntDivIsCheap = false;



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Nate Begeman]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.27 - 1.28
---
Log message:

Implement some feedback from sabre


---
Diffs of the changes:  (+5 -5)

 TargetLowering.cpp |   10 +-
 1 files changed, 5 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.27 
llvm/lib/Target/TargetLowering.cpp:1.28
--- llvm/lib/Target/TargetLowering.cpp:1.27 Fri Feb  3 16:24:05 2006
+++ llvm/lib/Target/TargetLowering.cpp  Fri Feb  3 16:38:07 2006
@@ -135,14 +135,14 @@
 /// set operation such as a sign extend or or/xor with constant whose only
 /// use is Op.  If it returns true, the old node that sets bits which are
 /// not demanded is returned in Old, and its replacement node is returned in
-/// New, such that callers of SetBitsAreZero may call CombineTo on them if
+/// New, such that callers of DemandedBitsAreZero may call CombineTo on them if
 /// desired.
 bool TargetLowering::DemandedBitsAreZero(const SDOperand Op, uint64_t Mask, 
  SDOperand Old, SDOperand New,
  SelectionDAG DAG) {
   // If the operation has more than one use, we're not interested in it.
   // Tracking down and checking all uses would be problematic and slow.
-  if (!Op.hasOneUse())
+  if (!Op.Val-hasOneUse())
 return false;
   
   switch (Op.getOpcode()) {
@@ -164,11 +164,11 @@
 MVT::ValueType EVT = castVTSDNode(Op.getOperand(1))-getVT();
 unsigned ExtendBits = MVT::getSizeInBits(EVT);
 // If we're extending from something smaller than MVT::i64 and all of the
-// sign extension bits are masked, return true and set New to be a zero
-// extend inreg from the same type.
+// sign extension bits are masked, return true and set New to be the
+// first operand, since we no longer care what the high bits are.
 if (ExtendBits  64  ((Mask  (~0ULL  ExtendBits)) == 0)) {
   Old = Op;
-  New = DAG.getZeroExtendInReg(Op.getOperand(0), EVT);
+  New = Op.getOperand(0);
   return true;
 }
 break;



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.28 - 1.29
---
Log message:

implementation of some methods for inlineasm


---
Diffs of the changes:  (+41 -1)

 TargetLowering.cpp |   42 +-
 1 files changed, 41 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.28 
llvm/lib/Target/TargetLowering.cpp:1.29
--- llvm/lib/Target/TargetLowering.cpp:1.28 Fri Feb  3 16:38:07 2006
+++ llvm/lib/Target/TargetLowering.cpp  Fri Feb  3 20:13:02 2006
@@ -131,6 +131,10 @@
   return NULL;
 }
 
+//===--===//
+//  Optimization Methods
+//===--===//
+
 /// DemandedBitsAreZero - Return true if 'Op  Mask' demands no bits from a bit
 /// set operation such as a sign extend or or/xor with constant whose only
 /// use is Op.  If it returns true, the old node that sets bits which are
@@ -139,7 +143,7 @@
 /// desired.
 bool TargetLowering::DemandedBitsAreZero(const SDOperand Op, uint64_t Mask, 
  SDOperand Old, SDOperand New,
- SelectionDAG DAG) {
+ SelectionDAG DAG) const {
   // If the operation has more than one use, we're not interested in it.
   // Tracking down and checking all uses would be problematic and slow.
   if (!Op.Val-hasOneUse())
@@ -302,6 +306,42 @@
   return false;
 }
 
+//===--===//
+//  Inline Assembler Implementation Methods
+//===--===//
+
+TargetLowering::ConstraintType
+TargetLowering::getConstraintType(char ConstraintLetter) const {
+  // FIXME: lots more standard ones to handle.
+  switch (ConstraintLetter) {
+  default: return C_Unknown;
+  case 'r': return C_RegisterClass;
+  case 'i':// Simple Integer or Relocatable Constant
+  case 'n':// Simple Integer
+  case 's':// Relocatable Constant
+  case 'I':// Target registers.
+  case 'J':
+  case 'K':
+  case 'L':
+  case 'M':
+  case 'N':
+  case 'O':
+  case 'P':  return C_Other;
+  }
+}
+
+bool TargetLowering::isOperandValidForConstraint(SDOperand Op, 
+ char ConstraintLetter) {
+  switch (ConstraintLetter) {
+  default: return false;
+  case 'i':// Simple Integer or Relocatable Constant
+  case 'n':// Simple Integer
+  case 's':// Relocatable Constant
+return true;   // FIXME: not right.
+  }
+}
+
+
 std::vectorunsigned TargetLowering::
 getRegForInlineAsmConstraint(const std::string Constraint) const {
   // Not a physreg, must not be a register reference or something.



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.25 - 1.26
---
Log message:

Implement MaskedValueIsZero for ANY_EXTEND nodes


---
Diffs of the changes:  (+5 -0)

 TargetLowering.cpp |5 +
 1 files changed, 5 insertions(+)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.25 
llvm/lib/Target/TargetLowering.cpp:1.26
--- llvm/lib/Target/TargetLowering.cpp:1.25 Tue Jan 31 19:29:22 2006
+++ llvm/lib/Target/TargetLowering.cpp  Thu Feb  2 00:43:15 2006
@@ -154,6 +154,11 @@
   case ISD::ZERO_EXTEND:
 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
 return MaskedValueIsZero(Op.getOperand(0),Mask  (~0ULL  (64-SrcBits)));
+  case ISD::ANY_EXTEND:
+// If the mask only includes bits in the low part, recurse.
+SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
+if (Mask  SrcBits) return false;  // Use of unknown top bits.
+return MaskedValueIsZero(Op.getOperand(0), Mask);
   case ISD::AssertZext:
 SrcBits = MVT::getSizeInBits(castVTSDNode(Op.getOperand(1))-getVT());
 return (Mask  ((1ULL  SrcBits)-1)) == 0; // Returning only the zext 
bits.



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.24 - 1.25
---
Log message:

Beef up the interface to inline asm constraint parsing, making it more general, 
useful, and easier to use.



---
Diffs of the changes:  (+10 -3)

 TargetLowering.cpp |   13 ++---
 1 files changed, 10 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.24 
llvm/lib/Target/TargetLowering.cpp:1.25
--- llvm/lib/Target/TargetLowering.cpp:1.24 Sun Jan 29 22:09:04 2006
+++ llvm/lib/Target/TargetLowering.cpp  Tue Jan 31 19:29:22 2006
@@ -243,15 +243,22 @@
 
 std::vectorunsigned TargetLowering::
 getRegForInlineAsmConstraint(const std::string Constraint) const {
+  // Not a physreg, must not be a register reference or something.
+  if (Constraint[0] != '{') return std::vectorunsigned();
+  assert(*(Constraint.end()-1) == '}'  Not a brace enclosed constraint?);
+
+  // Remove the braces from around the name.
+  std::string RegName(Constraint.begin()+1, Constraint.end()-1);
+  
   // Scan to see if this constraint is a register name.
   const MRegisterInfo *RI = TM.getRegisterInfo();
   for (unsigned i = 1, e = RI-getNumRegs(); i != e; ++i) {
 if (const char *Name = RI-get(i).Name)
-  if (StringsEqualNoCase(Constraint, Name))
+  if (StringsEqualNoCase(RegName, Name))
 return std::vectorunsigned(1, i);
   }
-
-  // Not a physreg, must not be a register reference or something.
+  
+  // Unknown physreg.
   return std::vectorunsigned();
 }
 



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.21 - 1.22
---
Log message:

clean up interface to ValueTypeActions


---
Diffs of the changes:  (+3 -3)

 TargetLowering.cpp |6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.21 
llvm/lib/Target/TargetLowering.cpp:1.22
--- llvm/lib/Target/TargetLowering.cpp:1.21 Thu Jan 26 14:37:03 2006
+++ llvm/lib/Target/TargetLowering.cpp  Sun Jan 29 02:41:12 2006
@@ -19,7 +19,7 @@
 using namespace llvm;
 
 TargetLowering::TargetLowering(TargetMachine tm)
-  : TM(tm), TD(TM.getTargetData()), ValueTypeActions(0) {
+  : TM(tm), TD(TM.getTargetData()) {
   assert(ISD::BUILTIN_OP_END = 128 
  Fixed size array in TargetLowering is not large enough!);
   // All operations default to being supported.
@@ -46,8 +46,8 @@
TargetLowering::LegalizeAction Action,
TargetLowering TLI,
MVT::ValueType *TransformToType,
-   unsigned long long ValueTypeActions) {
-  ValueTypeActions |= (unsigned long long)Action  (VT*2);
+TargetLowering::ValueTypeActionImpl ValueTypeActions) 
{
+  ValueTypeActions.setTypeAction(VT, Action);
   if (Action == TargetLowering::Promote) {
 MVT::ValueType PromoteTo;
 if (VT == MVT::f32)



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.22 - 1.23
---
Log message:

adjust prototype


---
Diffs of the changes:  (+2 -1)

 TargetLowering.cpp |3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.22 
llvm/lib/Target/TargetLowering.cpp:1.23
--- llvm/lib/Target/TargetLowering.cpp:1.22 Sun Jan 29 02:41:12 2006
+++ llvm/lib/Target/TargetLowering.cpp  Sun Jan 29 21:49:07 2006
@@ -131,7 +131,8 @@
 }
 
 bool TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand Op,
-uint64_t Mask) const {
+uint64_t Mask,
+ MVIZFnPtr MVIZ) const {
   return false;
 }
 



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.23 - 1.24
---
Log message:

Move MaskedValueIsZero from the DAGCombiner to the TargetLowering 
interface,making isMaskedValueZeroForTargetNode simpler, and useable from other 
partsof the compiler.



---
Diffs of the changes:  (+107 -2)

 TargetLowering.cpp |  109 -
 1 files changed, 107 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.23 
llvm/lib/Target/TargetLowering.cpp:1.24
--- llvm/lib/Target/TargetLowering.cpp:1.23 Sun Jan 29 21:49:07 2006
+++ llvm/lib/Target/TargetLowering.cpp  Sun Jan 29 22:09:04 2006
@@ -16,6 +16,7 @@
 #include llvm/Target/MRegisterInfo.h
 #include llvm/CodeGen/SelectionDAG.h
 #include llvm/ADT/StringExtras.h
+#include llvm/Support/MathExtras.h
 using namespace llvm;
 
 TargetLowering::TargetLowering(TargetMachine tm)
@@ -130,9 +131,113 @@
   return NULL;
 }
 
+
+
+/// MaskedValueIsZero - Return true if 'Op  Mask' is known to be zero.  We use
+/// this predicate to simplify operations downstream.  Op and Mask are known to
+/// be the same type.
+bool TargetLowering::MaskedValueIsZero(const SDOperand Op,
+   uint64_t Mask) const {
+  unsigned SrcBits;
+  if (Mask == 0) return true;
+  
+  // If we know the result of a setcc has the top bits zero, use this info.
+  switch (Op.getOpcode()) {
+  case ISD::Constant:
+return (castConstantSDNode(Op)-getValue()  Mask) == 0;
+  case ISD::SETCC:
+return ((Mask  1) == 0) 
+  getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
+  case ISD::ZEXTLOAD:
+SrcBits = MVT::getSizeInBits(castVTSDNode(Op.getOperand(3))-getVT());
+return (Mask  ((1ULL  SrcBits)-1)) == 0; // Returning only the zext 
bits.
+  case ISD::ZERO_EXTEND:
+SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
+return MaskedValueIsZero(Op.getOperand(0),Mask  (~0ULL  (64-SrcBits)));
+  case ISD::AssertZext:
+SrcBits = MVT::getSizeInBits(castVTSDNode(Op.getOperand(1))-getVT());
+return (Mask  ((1ULL  SrcBits)-1)) == 0; // Returning only the zext 
bits.
+  case ISD::AND:
+// If either of the operands has zero bits, the result will too.
+if (MaskedValueIsZero(Op.getOperand(1), Mask) ||
+MaskedValueIsZero(Op.getOperand(0), Mask))
+  return true;
+// (X  C1)  C2 == 0   iff   C1  C2 == 0.
+if (ConstantSDNode *AndRHS = dyn_castConstantSDNode(Op.getOperand(1)))
+  return MaskedValueIsZero(Op.getOperand(0),AndRHS-getValue()  Mask);
+return false;
+  case ISD::OR:
+  case ISD::XOR:
+return MaskedValueIsZero(Op.getOperand(0), Mask) 
+   MaskedValueIsZero(Op.getOperand(1), Mask);
+  case ISD::SELECT:
+return MaskedValueIsZero(Op.getOperand(1), Mask) 
+   MaskedValueIsZero(Op.getOperand(2), Mask);
+  case ISD::SELECT_CC:
+return MaskedValueIsZero(Op.getOperand(2), Mask) 
+   MaskedValueIsZero(Op.getOperand(3), Mask);
+  case ISD::SRL:
+// (ushr X, C1)  C2 == 0   iff  X  (C2  C1) == 0
+if (ConstantSDNode *ShAmt = dyn_castConstantSDNode(Op.getOperand(1))) {
+  uint64_t NewVal = Mask  ShAmt-getValue();
+  SrcBits = MVT::getSizeInBits(Op.getValueType());
+  if (SrcBits != 64) NewVal = (1ULL  SrcBits)-1;
+  return MaskedValueIsZero(Op.getOperand(0), NewVal);
+}
+return false;
+  case ISD::SHL:
+// (ushl X, C1)  C2 == 0   iff  X  (C2  C1) == 0
+if (ConstantSDNode *ShAmt = dyn_castConstantSDNode(Op.getOperand(1))) {
+  uint64_t NewVal = Mask  ShAmt-getValue();
+  return MaskedValueIsZero(Op.getOperand(0), NewVal);
+}
+return false;
+  case ISD::ADD:
+// (add X, Y)  C == 0 iff (XC)|(YC) == 0 and all bits are low bits.
+if ((Mask(Mask+1)) == 0) {  // All low bits
+  if (MaskedValueIsZero(Op.getOperand(0), Mask) 
+  MaskedValueIsZero(Op.getOperand(1), Mask))
+return true;
+}
+break;
+  case ISD::SUB:
+if (ConstantSDNode *CLHS = dyn_castConstantSDNode(Op.getOperand(0))) {
+  // We know that the top bits of C-X are clear if X contains less bits
+  // than C (i.e. no wrap-around can happen).  For example, 20-X is
+  // positive if we can prove that X is = 0 and  16.
+  unsigned Bits = MVT::getSizeInBits(CLHS-getValueType(0));
+  if ((CLHS-getValue()  (1  (Bits-1))) == 0) {  // sign bit clear
+unsigned NLZ = CountLeadingZeros_64(CLHS-getValue()+1);
+uint64_t MaskV = (1ULL  (63-NLZ))-1;
+if (MaskedValueIsZero(Op.getOperand(1), ~MaskV)) {
+  // High bits are clear this value is known to be = C.
+  unsigned NLZ2 = CountLeadingZeros_64(CLHS-getValue());
+  if ((Mask  ((1ULL  (64-NLZ2))-1)) == 0)
+return true;
+}
+  }
+}
+break;
+  case ISD::CTTZ:
+  case ISD::CTLZ:
+  case ISD::CTPOP:
+// Bit counting instructions can not set the high bits of the result
+ 

[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.20 - 1.21
---
Log message:

Implement a method for inline asm support


---
Diffs of the changes:  (+17 -0)

 TargetLowering.cpp |   17 +
 1 files changed, 17 insertions(+)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.20 
llvm/lib/Target/TargetLowering.cpp:1.21
--- llvm/lib/Target/TargetLowering.cpp:1.20 Wed Jan 25 12:57:15 2006
+++ llvm/lib/Target/TargetLowering.cpp  Thu Jan 26 14:37:03 2006
@@ -13,7 +13,9 @@
 
 #include llvm/Target/TargetLowering.h
 #include llvm/Target/TargetMachine.h
+#include llvm/Target/MRegisterInfo.h
 #include llvm/CodeGen/SelectionDAG.h
+#include llvm/ADT/StringExtras.h
 using namespace llvm;
 
 TargetLowering::TargetLowering(TargetMachine tm)
@@ -132,3 +134,18 @@
 uint64_t Mask) const {
   return false;
 }
+
+std::vectorunsigned TargetLowering::
+getRegForInlineAsmConstraint(const std::string Constraint) const {
+  // Scan to see if this constraint is a register name.
+  const MRegisterInfo *RI = TM.getRegisterInfo();
+  for (unsigned i = 1, e = RI-getNumRegs(); i != e; ++i) {
+if (const char *Name = RI-get(i).Name)
+  if (StringsEqualNoCase(Constraint, Name))
+return std::vectorunsigned(1, i);
+  }
+
+  // Not a physreg, must not be a register reference or something.
+  return std::vectorunsigned();
+}
+



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.18 - 1.19
---
Log message:

Set SchedulingForLatency to be the default scheduling preference for all.


---
Diffs of the changes:  (+1 -0)

 TargetLowering.cpp |1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.18 
llvm/lib/Target/TargetLowering.cpp:1.19
--- llvm/lib/Target/TargetLowering.cpp:1.18 Wed Dec 21 17:14:54 2005
+++ llvm/lib/Target/TargetLowering.cpp  Wed Jan 25 12:52:42 2006
@@ -32,6 +32,7 @@
   UseUnderscoreSetJmpLongJmp = false;
   IntDivIsCheap = false;
   Pow2DivIsCheap = false;
+  SchedPreferenceInfo = SchedulingForLatency;
 }
 
 TargetLowering::~TargetLowering() {}



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.19 - 1.20
---
Log message:

initialize an instance var, apparently I forgot to commit this long ago



---
Diffs of the changes:  (+1 -0)

 TargetLowering.cpp |1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.19 
llvm/lib/Target/TargetLowering.cpp:1.20
--- llvm/lib/Target/TargetLowering.cpp:1.19 Wed Jan 25 12:52:42 2006
+++ llvm/lib/Target/TargetLowering.cpp  Wed Jan 25 12:57:15 2006
@@ -32,6 +32,7 @@
   UseUnderscoreSetJmpLongJmp = false;
   IntDivIsCheap = false;
   Pow2DivIsCheap = false;
+  StackPointerRegisterToSaveRestore = 0;
   SchedPreferenceInfo = SchedulingForLatency;
 }
 



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.15 - 1.16
---
Log message:

Added a hook to print out names of target specific DAG nodes.


---
Diffs of the changes:  (+3 -0)

 TargetLowering.cpp |3 +++
 1 files changed, 3 insertions(+)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.15 
llvm/lib/Target/TargetLowering.cpp:1.16
--- llvm/lib/Target/TargetLowering.cpp:1.15 Mon Nov 28 23:45:29 2005
+++ llvm/lib/Target/TargetLowering.cpp  Tue Dec 20 00:22:03 2005
@@ -122,3 +122,6 @@
   TransformToType[MVT::f64] = MVT::f64;
 }
 
+const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
+  return NULL;
+}



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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Nate Begeman]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.13 - 1.14
---
Log message:

Rather than attempting to legalize 1 x float, make sure the SD ISel never
generates it.  Make MVT::Vector expand-only, and remove the code in
Legalize that attempts to legalize it.

The plan for supporting N x Type is to continually epxand it in ExpandOp
until it gets down to 2 x Type, where it will be scalarized into a pair of
scalars.


---
Diffs of the changes:  (+5 -1)

 TargetLowering.cpp |6 +-
 1 files changed, 5 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.13 
llvm/lib/Target/TargetLowering.cpp:1.14
--- llvm/lib/Target/TargetLowering.cpp:1.13 Thu Oct 20 19:02:42 2005
+++ llvm/lib/Target/TargetLowering.cpp  Mon Nov 21 19:29:36 2005
@@ -64,7 +64,7 @@
 assert(VT  PromoteTo  Must promote to a larger type!);
 TransformToType[VT] = PromoteTo;
   } else if (Action == TargetLowering::Expand) {
-assert(MVT::isInteger(VT)  VT  MVT::i8 
+assert((VT == MVT::Vector || MVT::isInteger(VT))  VT  MVT::i8 
Cannot expand this type: target must support SOME integer reg!);
 // Expand to the next smaller integer type!
 TransformToType[VT] = (MVT::ValueType)(VT-1);
@@ -113,6 +113,10 @@
TransformToType, ValueTypeActions);
   else
 TransformToType[MVT::f32] = MVT::f32;
+  
+  // Set MVT::Vector to always be Expanded
+  SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType, 
+ ValueTypeActions);
 
   assert(isTypeLegal(MVT::f64)  Target does not support FP?);
   TransformToType[MVT::f64] = MVT::f64;



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