Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Awesome, thanks Evan. As an improvement, can't vector fneg be implemented with a xor of a constant vector? -Chris On Jun 28, 2007, at 5:18 PM, Evan Cheng wrote: > > > Changes in directory llvm/lib/Target/X86: > > X86ISelLowering.cpp updated: 1.416 -> 1.417 > --- > Log message: > > No vector fneg. > > --- > Diffs of the changes: (+1 -0) > > X86ISelLowering.cpp |1 + > 1 files changed, 1 insertion(+) > > > Index: llvm/lib/Target/X86/X86ISelLowering.cpp > diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.416 llvm/lib/ > Target/X86/X86ISelLowering.cpp:1.417 > --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.416 Thu Jun 28 > 19:01:20 2007 > +++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Jun 28 19:18:15 2007 > @@ -314,6 +314,7 @@ > setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand); > setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand); > setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand); > +setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand); > setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand); > setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); > setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand); > > > > ___ > llvm-commits mailing list > llvm-commits@cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.416 -> 1.417 --- Log message: No vector fneg. --- Diffs of the changes: (+1 -0) X86ISelLowering.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.416 llvm/lib/Target/X86/X86ISelLowering.cpp:1.417 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.416 Thu Jun 28 19:01:20 2007 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Jun 28 19:18:15 2007 @@ -314,6 +314,7 @@ setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand); setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand); setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand); +setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand); setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand); setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.415 -> 1.416
---
Log message:
Type of vector extract / insert index operand should be iPTR.
---
Diffs of the changes: (+1 -1)
X86ISelLowering.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.415
llvm/lib/Target/X86/X86ISelLowering.cpp:1.416
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.415 Mon Jun 25 11:23:39 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Jun 28 19:01:20 2007
@@ -2959,7 +2959,7 @@
if (N1.getValueType() != MVT::i32)
N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
if (N2.getValueType() != MVT::i32)
- N2 = DAG.getConstant(cast(N2)->getValue(), MVT::i32);
+ N2 =
DAG.getConstant(cast(N2)->getValue(),getPointerTy());
return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
} else if (MVT::getSizeInBits(BaseVT) == 32) {
unsigned Idx = cast(N2)->getValue();
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.414 -> 1.415
---
Log message:
Generalize MVT::ValueType and associated functions to be able to represent
extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.
This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.
---
Diffs of the changes: (+8 -4)
X86ISelLowering.cpp | 12
1 files changed, 8 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.414
llvm/lib/Target/X86/X86ISelLowering.cpp:1.415
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.414 Fri Jun 22 09:59:07 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Jun 25 11:23:39 2007
@@ -2493,9 +2493,14 @@
}
}
- if (NumNonZero == 0)
-// Must be a mix of zero and undef. Return a zero vector.
-return getZeroVector(VT, DAG);
+ if (NumNonZero == 0) {
+if (NumZero == 0)
+ // All undef vector. Return an UNDEF.
+ return DAG.getNode(ISD::UNDEF, VT);
+else
+ // A mix of zero and undef. Return a zero vector.
+ return getZeroVector(VT, DAG);
+ }
// Splat is obviously ok. Let legalizer expand it to a shuffle.
if (Values.size() == 1)
@@ -4919,7 +4924,6 @@
case MVT::i64:
return std::make_pair(0U, X86::FR64RegisterClass);
// Vector types.
- case MVT::Vector:
case MVT::v16i8:
case MVT::v8i16:
case MVT::v4i32:
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.411 -> 1.412
---
Log message:
Look for VECTOR_SHUFFLE that's identity operation on either LHS or RHS. This
can happen before DAGCombiner catches it.
---
Diffs of the changes: (+19 -2)
X86ISelLowering.cpp | 21 +++--
1 files changed, 19 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.411
llvm/lib/Target/X86/X86ISelLowering.cpp:1.412
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.411 Sat Jun 16 18:57:15 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Jun 18 19:02:56 2007
@@ -1954,6 +1954,16 @@
return HasHi;
}
+/// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
+/// specifies a identity operation on the LHS or RHS.
+static bool isIdentityMask(SDNode *N, bool RHS = false) {
+ unsigned NumElems = N->getNumOperands();
+ for (unsigned i = 0; i < NumElems; ++i)
+if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
+ return false;
+ return true;
+}
+
/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
/// a splat of a single element.
static bool isSplatMask(SDNode *N) {
@@ -2630,6 +2640,11 @@
if (isZeroShuffle(Op.Val))
return getZeroVector(VT, DAG);
+ if (isIdentityMask(PermMask.Val))
+return V1;
+ else if (isIdentityMask(PermMask.Val, true))
+return V2;
+
if (isSplatMask(PermMask.Val)) {
if (NumElems <= 4) return Op;
// Promote it to a v4i32 splat.
@@ -4316,12 +4331,14 @@
// Only do shuffles on 128-bit vector types for now.
if (MVT::getSizeInBits(VT) == 64) return false;
return (Mask.Val->getNumOperands() <= 4 ||
+ isIdentityMask(Mask.Val) ||
+ isIdentityMask(Mask.Val, true) ||
isSplatMask(Mask.Val) ||
isPSHUFHW_PSHUFLWMask(Mask.Val) ||
X86::isUNPCKLMask(Mask.Val) ||
+ X86::isUNPCKHMask(Mask.Val) ||
X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
- X86::isUNPCKH_v_undef_Mask(Mask.Val) ||
- X86::isUNPCKHMask(Mask.Val));
+ X86::isUNPCKH_v_undef_Mask(Mask.Val));
}
bool X86TargetLowering::isVectorClearMaskLegal(std::vector &BVOps,
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Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
On Jun 16, 2007, at 4:57 PM, Bill Wendling wrote:
> Revert patch. It regresses:
>
> define double @test2(i64 %A) {
>%B = bitcast i64 %A to double
>ret double %B
> }
Thanks Bill,
-Chris
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Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Doh! Reverting. Sorry about that.
-bw
On Jun 16, 2007, at 12:35 PM, Chris Lattner wrote:
> On Jun 15, 2007, at 11:17 PM, Bill Wendling wrote:
>> Fix a failure to bit_convert from integer GPR to MMX register.
>
> Bill, this causes a regression on this testcase:
>
> define double @test2(i64 %A) {
>%B = bitcast i64 %A to double
>ret double %B
> }
>
> $ llvm-as < t.ll | llc -march=x86-64
>
> before:
>
> .align 4
> .globl _test2
> _test2:
> movd %rdi, %xmm0
> ret
>
> after:
>
> _test2:
> subq $8, %rsp
> movq %rdi, (%rsp)
> movsd (%rsp), %xmm0
> addq $8, %rsp
> ret
>
> Please fix or revert your patch until you can,
>
> -Chris
>
>>
>> ---
>> Diffs of the changes: (+2 -0)
>>
>> X86ISelLowering.cpp |2 ++
>> 1 files changed, 2 insertions(+)
>>
>>
>> Index: llvm/lib/Target/X86/X86ISelLowering.cpp
>> diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.409 llvm/lib/
>> Target/X86/X86ISelLowering.cpp:1.410
>> --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.409Thu Jun 14
>> 17:58:02 2007
>> +++ llvm/lib/Target/X86/X86ISelLowering.cpp Sat Jun 16 01:17:31 2007
>> @@ -394,6 +394,8 @@
>> setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
>> setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Custom);
>> setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
>> +
>> +setOperationAction(ISD::BIT_CONVERT,MVT::i64, Expand);
>>}
>>
>>if (Subtarget->hasSSE1()) {
>>
>>
>>
>> ___
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>
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.410 -> 1.411
---
Log message:
Revert patch. It regresses:
define double @test2(i64 %A) {
%B = bitcast i64 %A to double
ret double %B
}
$ llvm-as < t.ll | llc -march=x86-64
before:
.align 4
.globl _test2
_test2:
movd %rdi, %xmm0
ret
after:
_test2:
subq $8, %rsp
movq %rdi, (%rsp)
movsd (%rsp), %xmm0
addq $8, %rsp
ret
---
Diffs of the changes: (+0 -2)
X86ISelLowering.cpp |2 --
1 files changed, 2 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.410
llvm/lib/Target/X86/X86ISelLowering.cpp:1.411
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.410 Sat Jun 16 01:17:31 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sat Jun 16 18:57:15 2007
@@ -394,8 +394,6 @@
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
-
-setOperationAction(ISD::BIT_CONVERT,MVT::i64, Expand);
}
if (Subtarget->hasSSE1()) {
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Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
On Jun 15, 2007, at 11:17 PM, Bill Wendling wrote:
> Fix a failure to bit_convert from integer GPR to MMX register.
Bill, this causes a regression on this testcase:
define double @test2(i64 %A) {
%B = bitcast i64 %A to double
ret double %B
}
$ llvm-as < t.ll | llc -march=x86-64
before:
.align 4
.globl _test2
_test2:
movd %rdi, %xmm0
ret
after:
_test2:
subq $8, %rsp
movq %rdi, (%rsp)
movsd (%rsp), %xmm0
addq $8, %rsp
ret
Please fix or revert your patch until you can,
-Chris
>
> ---
> Diffs of the changes: (+2 -0)
>
> X86ISelLowering.cpp |2 ++
> 1 files changed, 2 insertions(+)
>
>
> Index: llvm/lib/Target/X86/X86ISelLowering.cpp
> diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.409 llvm/lib/
> Target/X86/X86ISelLowering.cpp:1.410
> --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.409 Thu Jun 14
> 17:58:02 2007
> +++ llvm/lib/Target/X86/X86ISelLowering.cpp Sat Jun 16 01:17:31 2007
> @@ -394,6 +394,8 @@
> setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
> setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Custom);
> setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
> +
> +setOperationAction(ISD::BIT_CONVERT,MVT::i64, Expand);
>}
>
>if (Subtarget->hasSSE1()) {
>
>
>
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.409 -> 1.410
---
Log message:
Fix a failure to bit_convert from integer GPR to MMX register.
---
Diffs of the changes: (+2 -0)
X86ISelLowering.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.409
llvm/lib/Target/X86/X86ISelLowering.cpp:1.410
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.409 Thu Jun 14 17:58:02 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sat Jun 16 01:17:31 2007
@@ -394,6 +394,8 @@
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
+
+setOperationAction(ISD::BIT_CONVERT,MVT::i64, Expand);
}
if (Subtarget->hasSSE1()) {
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.408 -> 1.409
---
Log message:
Rename MVT::getVectorBaseType to MVT::getVectorElementType.
---
Diffs of the changes: (+22 -22)
X86ISelLowering.cpp | 44 ++--
1 files changed, 22 insertions(+), 22 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.408
llvm/lib/Target/X86/X86ISelLowering.cpp:1.409
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.408 Sat Jun 9 00:08:10 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Jun 14 17:58:02 2007
@@ -2106,7 +2106,7 @@
SelectionDAG &DAG) {
MVT::ValueType VT = Op.getValueType();
MVT::ValueType MaskVT = Mask.getValueType();
- MVT::ValueType EltVT = MVT::getVectorBaseType(MaskVT);
+ MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
unsigned NumElems = Mask.getNumOperands();
SmallVector MaskVec;
@@ -2265,7 +2265,7 @@
static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
assert(MVT::isVector(VT) && "Expected a vector type");
unsigned NumElems = MVT::getVectorNumElements(VT);
- MVT::ValueType EVT = MVT::getVectorBaseType(VT);
+ MVT::ValueType EVT = MVT::getVectorElementType(VT);
bool isFP = MVT::isFloatingPoint(EVT);
SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0,
EVT);
SmallVector ZeroVec(NumElems, Zero);
@@ -2302,7 +2302,7 @@
/// operation of specified width.
static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
- MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
+ MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
SmallVector MaskVec;
MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
@@ -2315,7 +2315,7 @@
/// of specified width.
static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
- MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
+ MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
SmallVector MaskVec;
for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
MaskVec.push_back(DAG.getConstant(i,BaseVT));
@@ -2328,7 +2328,7 @@
/// of specified width.
static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
- MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
+ MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
unsigned Half = NumElems/2;
SmallVector MaskVec;
for (unsigned i = 0; i != Half; ++i) {
@@ -2366,7 +2366,7 @@
bool isZero, SelectionDAG &DAG) {
SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
- MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
+ MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
SDOperand Zero = DAG.getConstant(0, EVT);
SmallVector MaskVec(NumElems, Zero);
MaskVec[Idx] = DAG.getConstant(NumElems, EVT);
@@ -2458,7 +2458,7 @@
return Op;
MVT::ValueType VT = Op.getValueType();
- MVT::ValueType EVT = MVT::getVectorBaseType(VT);
+ MVT::ValueType EVT = MVT::getVectorElementType(VT);
unsigned EVTBits = MVT::getSizeInBits(EVT);
unsigned NumElems = Op.getNumOperands();
@@ -2502,7 +2502,7 @@
Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0,
DAG);
MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
- MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
+ MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
SmallVector MaskVec;
for (unsigned i = 0; i < NumElems; i++)
MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
@@ -2571,7 +2571,7 @@
if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
return V[0];
MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
-MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
+MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
SmallVector MaskVec;
bool Reverse = (NonZeros & 0x3) == 2;
for (unsigned i = 0; i < 2; ++i)
@@ -2728,7 +2728,7 @@
// Handle v8i16 shuffle high / low shuffle node pair.
if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) {
MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
- MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
+ MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
SmallVector MaskVec;
for (unsigned i = 0; i != 4; ++i)
MaskVec.push_back(PermMask.getOperand(i));
@@ -2763,7 +2763,7 @@
// Don't do this for MMX.
MVT::getSizeInBits(VT) != 64
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.407 -> 1.408
---
Log message:
fix x86-64 mmx calling convention for real, which passes in integer gprs.
---
Diffs of the changes: (+9 -3)
X86ISelLowering.cpp | 12 +---
1 files changed, 9 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.407
llvm/lib/Target/X86/X86ISelLowering.cpp:1.408
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.407 Sat Jun 9 00:01:50 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sat Jun 9 00:08:10 2007
@@ -1183,9 +1183,10 @@
RC = X86::FR64RegisterClass;
else {
assert(MVT::isVector(RegVT));
-if (MVT::getSizeInBits(RegVT) == 64)
- RC = X86::VR64RegisterClass;
-else
+if (MVT::getSizeInBits(RegVT) == 64) {
+ RC = X86::GR64RegisterClass; // MMX values are passed in GPRs.
+ RegVT = MVT::i64;
+} else
RC = X86::VR128RegisterClass;
}
@@ -1205,6 +1206,11 @@
if (VA.getLocInfo() != CCValAssign::Full)
ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
+ // Handle MMX values passed in GPRs.
+ if (RegVT != VA.getLocVT() && RC == X86::GR64RegisterClass &&
+ MVT::getSizeInBits(RegVT) == 64)
+ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
+
ArgValues.push_back(ArgValue);
} else {
assert(VA.isMemLoc());
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.406 -> 1.407
---
Log message:
fix mmx handling bug
---
Diffs of the changes: (+4 -1)
X86ISelLowering.cpp |5 -
1 files changed, 4 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.406
llvm/lib/Target/X86/X86ISelLowering.cpp:1.407
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.406 Thu May 24 09:33:05 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sat Jun 9 00:01:50 2007
@@ -1183,7 +1183,10 @@
RC = X86::FR64RegisterClass;
else {
assert(MVT::isVector(RegVT));
-RC = X86::VR128RegisterClass;
+if (MVT::getSizeInBits(RegVT) == 64)
+ RC = X86::VR64RegisterClass;
+else
+ RC = X86::VR128RegisterClass;
}
unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.405 -> 1.406
---
Log message:
Add explicit qualification for namespace MVT members.
---
Diffs of the changes: (+1 -1)
X86ISelLowering.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.405
llvm/lib/Target/X86/X86ISelLowering.cpp:1.406
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.405 Fri May 18 13:44:07 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu May 24 09:33:05 2007
@@ -2255,7 +2255,7 @@
///
static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
assert(MVT::isVector(VT) && "Expected a vector type");
- unsigned NumElems = getVectorNumElements(VT);
+ unsigned NumElems = MVT::getVectorNumElements(VT);
MVT::ValueType EVT = MVT::getVectorBaseType(VT);
bool isFP = MVT::isFloatingPoint(EVT);
SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0,
EVT);
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.404 -> 1.405
---
Log message:
Use MVT::FIRST_VECTOR_VALUETYPE and MVT::LAST_VECTOR_VALUETYPE.
---
Diffs of the changes: (+2 -2)
X86ISelLowering.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.404
llvm/lib/Target/X86/X86ISelLowering.cpp:1.405
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.404 Thu May 17 13:45:50 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri May 18 13:44:07 2007
@@ -309,8 +309,8 @@
// First set operation action for all vector types to expand. Then we
// will selectively turn on ones that can be effectively codegen'd.
- for (unsigned VT = (unsigned)MVT::Vector + 1;
- VT != (unsigned)MVT::LAST_VALUETYPE; VT++) {
+ for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
+ VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand);
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.403 -> 1.404
---
Log message:
Fix a bogus check that prevented folding VECTOR_SHUFFLE to UNDEF; add an
optimization to fold VECTOR_SHUFFLE to a zero vector.
---
Diffs of the changes: (+61 -24)
X86ISelLowering.cpp | 85 +---
1 files changed, 61 insertions(+), 24 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.403
llvm/lib/Target/X86/X86ISelLowering.cpp:1.404
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.403 Thu May 17 12:13:13 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu May 17 13:45:50 2007
@@ -1630,7 +1630,7 @@
return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
}
-/// isCommutedSHUFP - Returns true if the shuffle mask is except
+/// isCommutedSHUFP - Returns true if the shuffle mask is exactly
/// the reverse of what x86 shuffles want. x86 shuffles requires the lower
/// half elements to come from vector 1 (which would equal the dest.) and
/// the upper half to come from vector 2.
@@ -2188,7 +2188,7 @@
/// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
/// to an undef.
static bool isUndefShuffle(SDNode *N) {
- if (N->getOpcode() != ISD::BUILD_VECTOR)
+ if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
return false;
SDOperand V1 = N->getOperand(0);
@@ -2208,6 +2208,61 @@
return true;
}
+/// isZeroNode - Returns true if Elt is a constant zero or a floating point
+/// constant +0.0.
+static inline bool isZeroNode(SDOperand Elt) {
+ return ((isa(Elt) &&
+ cast(Elt)->getValue() == 0) ||
+ (isa(Elt) &&
+ cast(Elt)->isExactlyValue(0.0)));
+}
+
+/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
+/// to an zero vector.
+static bool isZeroShuffle(SDNode *N) {
+ if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
+return false;
+
+ SDOperand V1 = N->getOperand(0);
+ SDOperand V2 = N->getOperand(1);
+ SDOperand Mask = N->getOperand(2);
+ unsigned NumElems = Mask.getNumOperands();
+ for (unsigned i = 0; i != NumElems; ++i) {
+SDOperand Arg = Mask.getOperand(i);
+if (Arg.getOpcode() != ISD::UNDEF) {
+ unsigned Idx = cast(Arg)->getValue();
+ if (Idx < NumElems) {
+unsigned Opc = V1.Val->getOpcode();
+if (Opc == ISD::UNDEF)
+ continue;
+if (Opc != ISD::BUILD_VECTOR ||
+!isZeroNode(V1.Val->getOperand(Idx)))
+ return false;
+ } else if (Idx >= NumElems) {
+unsigned Opc = V2.Val->getOpcode();
+if (Opc == ISD::UNDEF)
+ continue;
+if (Opc != ISD::BUILD_VECTOR ||
+!isZeroNode(V2.Val->getOperand(Idx - NumElems)))
+ return false;
+ }
+}
+ }
+ return true;
+}
+
+/// getZeroVector - Returns a vector of specified type with all zero elements.
+///
+static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
+ assert(MVT::isVector(VT) && "Expected a vector type");
+ unsigned NumElems = getVectorNumElements(VT);
+ MVT::ValueType EVT = MVT::getVectorBaseType(VT);
+ bool isFP = MVT::isFloatingPoint(EVT);
+ SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0,
EVT);
+ SmallVector ZeroVec(NumElems, Zero);
+ return DAG.getNode(ISD::BUILD_VECTOR, VT, &ZeroVec[0], ZeroVec.size());
+}
+
/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
/// that point to V2 points to its first element.
static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
@@ -2274,18 +2329,6 @@
return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
}
-/// getZeroVector - Returns a vector of specified type with all zero elements.
-///
-static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
- assert(MVT::isVector(VT) && "Expected a vector type");
- unsigned NumElems = getVectorNumElements(VT);
- MVT::ValueType EVT = MVT::getVectorBaseType(VT);
- bool isFP = MVT::isFloatingPoint(EVT);
- SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0,
EVT);
- SmallVector ZeroVec(NumElems, Zero);
- return DAG.getNode(ISD::BUILD_VECTOR, VT, &ZeroVec[0], ZeroVec.size());
-}
-
/// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
///
static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
@@ -2307,17 +2350,8 @@
return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
}
-/// isZeroNode - Returns true if Elt is a constant zero or a floating point
-/// constant +0.0.
-static inline bool isZeroNode(SDOperand Elt) {
- return ((isa(Elt) &&
- cast(Elt)->getValue() == 0) ||
- (isa(Elt) &&
- cast(Elt)->isExactlyValue(0.0)));
-}
-
/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
-/// vector and zero or undef vector.
+/// vector of zero or undef vector.
static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2,
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.402 -> 1.403
---
Log message:
This is the correct fix for PR1427: http://llvm.org/PR1427 . This fixes
mmx-shuffle.ll and doesn't
cause other regressions.
---
Diffs of the changes: (+5 -2)
X86ISelLowering.cpp |7 +--
1 files changed, 5 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.402
llvm/lib/Target/X86/X86ISelLowering.cpp:1.403
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.402 Thu May 17 02:50:14 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu May 17 12:13:13 2007
@@ -2675,7 +2675,8 @@
return Op;
}
-if (X86::isSHUFPMask(PermMask.Val))
+if (X86::isSHUFPMask(PermMask.Val) &&
+MVT::getSizeInBits(VT) != 64)// Don't do this for MMX.
return Op;
// Handle v8i16 shuffle high / low shuffle node pair.
@@ -2712,7 +2713,9 @@
}
}
- if (NumElems == 4) {
+ if (NumElems == 4 &&
+ // Don't do this for MMX.
+ MVT::getSizeInBits(VT) != 64) {
MVT::ValueType MaskVT = PermMask.getValueType();
MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
SmallVector, 8> Locs;
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.401 -> 1.402
---
Log message:
Revert patch for PR1427: http://llvm.org/PR1427 . It breaks almost all vector
tests.
---
Diffs of the changes: (+1 -10)
X86ISelLowering.cpp | 11 +--
1 files changed, 1 insertion(+), 10 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.401
llvm/lib/Target/X86/X86ISelLowering.cpp:1.402
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.401 Wed May 16 22:29:42 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu May 17 02:50:14 2007
@@ -1614,13 +1614,6 @@
static bool isSHUFPMask(const SDOperand *Elems, unsigned NumElems) {
if (NumElems != 2 && NumElems != 4) return false;
- // Ensure this is not an mmx shuffle.
- if (NumElems == 4 && Elems[0].getValueType() == MVT::i16)
-return false;
- if (NumElems == 2 && Elems[0].getValueType() == MVT::i32)
-return false;
-
-
unsigned Half = NumElems / 2;
for (unsigned i = 0; i < Half; ++i)
if (!isUndefOrInRange(Elems[i], 0, NumElems))
@@ -2719,9 +2712,7 @@
}
}
- if (NumElems == 4 &&
- // Don't do this for MMX.
- MVT::getSizeInBits(VT) != 64) {
+ if (NumElems == 4) {
MVT::ValueType MaskVT = PermMask.getValueType();
MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
SmallVector, 8> Locs;
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.400 -> 1.401
---
Log message:
Fix PR1427: http://llvm.org/PR1427 and test/CodeGen/X86/mmx-shuffle.ll
---
Diffs of the changes: (+10 -1)
X86ISelLowering.cpp | 11 ++-
1 files changed, 10 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.400
llvm/lib/Target/X86/X86ISelLowering.cpp:1.401
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.400 Mon May 14 20:28:08 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed May 16 22:29:42 2007
@@ -1614,6 +1614,13 @@
static bool isSHUFPMask(const SDOperand *Elems, unsigned NumElems) {
if (NumElems != 2 && NumElems != 4) return false;
+ // Ensure this is not an mmx shuffle.
+ if (NumElems == 4 && Elems[0].getValueType() == MVT::i16)
+return false;
+ if (NumElems == 2 && Elems[0].getValueType() == MVT::i32)
+return false;
+
+
unsigned Half = NumElems / 2;
for (unsigned i = 0; i < Half; ++i)
if (!isUndefOrInRange(Elems[i], 0, NumElems))
@@ -2712,7 +2719,9 @@
}
}
- if (NumElems == 4) {
+ if (NumElems == 4 &&
+ // Don't do this for MMX.
+ MVT::getSizeInBits(VT) != 64) {
MVT::ValueType MaskVT = PermMask.getValueType();
MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
SmallVector, 8> Locs;
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.399 -> 1.400
---
Log message:
fix subtle bugs in inline asm operand selection
---
Diffs of the changes: (+4 -3)
X86ISelLowering.cpp |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.399
llvm/lib/Target/X86/X86ISelLowering.cpp:1.400
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.399 Thu May 3 11:52:29 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon May 14 20:28:08 2007
@@ -4725,18 +4725,19 @@
case 'I':
if (ConstantSDNode *C = dyn_cast(Op)) {
if (C->getValue() <= 31)
-return Op;
+return DAG.getTargetConstant(C->getValue(), Op.getValueType());
}
return SDOperand(0,0);
case 'N':
if (ConstantSDNode *C = dyn_cast(Op)) {
if (C->getValue() <= 255)
-return Op;
+return DAG.getTargetConstant(C->getValue(), Op.getValueType());
}
return SDOperand(0,0);
case 'i': {
// Literal immediates are always ok.
-if (isa(Op)) return Op;
+if (ConstantSDNode *CST = dyn_cast(Op))
+ return DAG.getTargetConstant(CST->getValue(), Op.getValueType());
// If we are in non-pic codegen mode, we allow the address of a global
(with
// an optional displacement) to be used with 'i'.
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.398 -> 1.399
---
Log message:
Fix two classes of bugs:
1. x86 backend rejected (&gv+c) for the 'i' constraint when in static mode.
2. the matcher didn't correctly reject and accept some global addresses.
the right predicate is GVRequiresExtraLoad, not "relomodel = pic".
---
Diffs of the changes: (+32 -8)
X86ISelLowering.cpp | 40
1 files changed, 32 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.398
llvm/lib/Target/X86/X86ISelLowering.cpp:1.399
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.398 Wed May 2 14:53:33 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu May 3 11:52:29 2007
@@ -4734,25 +4734,49 @@
return Op;
}
return SDOperand(0,0);
- case 'i':
+ case 'i': {
// Literal immediates are always ok.
if (isa(Op)) return Op;
-// If we are in non-pic codegen mode, we allow the address of a global to
-// be used with 'i'.
-if (GlobalAddressSDNode *GA = dyn_cast(Op)) {
- if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
+// If we are in non-pic codegen mode, we allow the address of a global
(with
+// an optional displacement) to be used with 'i'.
+GlobalAddressSDNode *GA = dyn_cast(Op);
+int64_t Offset = 0;
+
+// Match either (GA) or (GA+C)
+if (GA) {
+ Offset = GA->getOffset();
+} else if (Op.getOpcode() == ISD::ADD) {
+ ConstantSDNode *C = dyn_cast(Op.getOperand(1));
+ GA = dyn_cast(Op.getOperand(0));
+ if (C && GA) {
+Offset = GA->getOffset()+C->getValue();
+ } else {
+C = dyn_cast(Op.getOperand(1));
+GA = dyn_cast(Op.getOperand(0));
+if (C && GA)
+ Offset = GA->getOffset()+C->getValue();
+else
+ C = 0, GA = 0;
+ }
+}
+
+if (GA) {
+ // If addressing this global requires a load (e.g. in PIC mode), we can't
+ // match.
+ if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
+ false))
return SDOperand(0, 0);
- if (GA->getOpcode() != ISD::TargetGlobalAddress)
-Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
-GA->getOffset());
+ Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
+ Offset);
return Op;
}
// Otherwise, not valid for this mode.
return SDOperand(0, 0);
}
+ }
return TargetLowering::isOperandValidForConstraint(Op, Constraint, DAG);
}
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.397 -> 1.398
X86RegisterInfo.cpp updated: 1.218 -> 1.219
---
Log message:
Emit correct register move information in eh frames for X86. This allows
Shootout-C++/except to pass on x86/linux
with non-llvm-compiled (e.g. "native") unwind runtime.
---
Diffs of the changes: (+56 -8)
X86ISelLowering.cpp | 13 +
X86RegisterInfo.cpp | 51 +++
2 files changed, 56 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.397
llvm/lib/Target/X86/X86ISelLowering.cpp:1.398
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.397 Tue Apr 24 16:16:55 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed May 2 14:53:33 2007
@@ -226,6 +226,19 @@
!Subtarget->isTargetCygMing())
setOperationAction(ISD::LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
+ setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
+ setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
+ setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
+ if (Subtarget->is64Bit()) {
+// FIXME: Verify
+setExceptionPointerRegister(X86::RAX);
+setExceptionSelectorRegister(X86::RDX);
+ } else {
+setExceptionPointerRegister(X86::EAX);
+setExceptionSelectorRegister(X86::EDX);
+ }
+
// VASTART needs to be custom lowered to use the VarArgsFrameIndex
setOperationAction(ISD::VASTART , MVT::Other, Custom);
setOperationAction(ISD::VAARG , MVT::Other, Expand);
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.218
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.219
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.218 Wed May 2 03:46:03 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Wed May 2 14:53:33 2007
@@ -26,6 +26,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineLocation.h"
+#include "llvm/Target/TargetAsmInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
@@ -1060,11 +1061,17 @@
MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
// Prepare for frame info.
- unsigned FrameLabelId = 0;
+ unsigned FrameLabelId = 0, StartLabelId = 0;
// Get the number of bytes to allocate from the FrameInfo
uint64_t NumBytes = MFI->getStackSize();
+ if (MMI && MMI->needsFrameInfo()) {
+// Mark function start
+StartLabelId = MMI->NextLabelID();
+BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(StartLabelId);
+ }
+
if (NumBytes) { // adjust stack pointer: ESP -= numbytes
if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
// Check, whether EAX is livein for this function
@@ -1138,17 +1145,38 @@
if (MMI && MMI->needsFrameInfo()) {
std::vector &Moves = MMI->getFrameMoves();
-
+const TargetAsmInfo *TAI = MF.getTarget().getTargetAsmInfo();
+
+// Calculate amount of bytes used for return address storing
+int stackGrowth =
+ (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
+ TargetFrameInfo::StackGrowsUp ?
+ TAI->getAddressSize() : -TAI->getAddressSize());
+
+// Add return address to move list
+MachineLocation CSDst(StackPtr, stackGrowth);
+MachineLocation CSSrc(getRARegister());
+Moves.push_back(MachineMove(StartLabelId, CSDst, CSSrc));
+
if (NumBytes) {
// Show update of SP.
- MachineLocation SPDst(MachineLocation::VirtualFP);
- MachineLocation SPSrc(MachineLocation::VirtualFP, -NumBytes);
- Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
+ if (hasFP(MF)) {
+// Adjust SP
+MachineLocation SPDst(MachineLocation::VirtualFP);
+MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
+Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
+ } else {
+MachineLocation SPDst(MachineLocation::VirtualFP);
+MachineLocation SPSrc(MachineLocation::VirtualFP,
-NumBytes+stackGrowth);
+Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
+ }
} else {
- MachineLocation SP(StackPtr);
- Moves.push_back(MachineMove(FrameLabelId, SP, SP));
+ //FIXME: Verify & implement for FP
+ MachineLocation SPDst(StackPtr);
+ MachineLocation SPSrc(StackPtr, stackGrowth);
+ Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
}
-
+
// Add callee saved registers to move list.
const std::vector &CSI = MFI->getCalleeSavedInfo();
for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
@@ -1162,6 +1190,13 @@
// Mark effective beginning of when frame pointer is ready.
unsigned ReadyLabelId = MMI->NextLabelID();
BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(Read
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.396 -> 1.397
X86ISelLowering.h updated: 1.99 -> 1.100
---
Log message:
Support for the special case of a vector with the canonical form:
vector_shuffle v1, v2, <2, 6, 3, 7>
I.e.
vector_shuffle v, undef, <2, 2, 3, 3>
MMX only has a shuffle for v4i16 vectors. It needs to use the unpackh for
this type of operation.
---
Diffs of the changes: (+35 -2)
X86ISelLowering.cpp | 32 ++--
X86ISelLowering.h |5 +
2 files changed, 35 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.396
llvm/lib/Target/X86/X86ISelLowering.cpp:1.397
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.396 Sun Apr 22 17:50:52 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Apr 24 16:16:55 2007
@@ -379,6 +379,8 @@
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
+setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Custom);
+setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
}
if (Subtarget->hasSSE1()) {
@@ -1776,7 +1778,7 @@
assert(N->getOpcode() == ISD::BUILD_VECTOR);
unsigned NumElems = N->getNumOperands();
- if (NumElems != 4 && NumElems != 8 && NumElems != 16)
+ if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
return false;
for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
@@ -1792,6 +1794,29 @@
return true;
}
+/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
+/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
+/// <2, 2, 3, 3>
+bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
+ assert(N->getOpcode() == ISD::BUILD_VECTOR);
+
+ unsigned NumElems = N->getNumOperands();
+ if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
+return false;
+
+ for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
+SDOperand BitI = N->getOperand(i);
+SDOperand BitI1 = N->getOperand(i + 1);
+
+if (!isUndefOrEqual(BitI, j))
+ return false;
+if (!isUndefOrEqual(BitI1, j))
+ return false;
+ }
+
+ return true;
+}
+
/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
/// specifies a shuffle of elements that is suitable for input to MOVSS,
/// MOVSD, and MOVD, i.e. setting the lowest element.
@@ -2432,7 +2457,7 @@
}
}
- // Let legalizer expand 2-wide build_vector's.
+ // Let legalizer expand 2-wide build_vectors.
if (EVTBits == 64)
return SDOperand();
@@ -2591,6 +2616,7 @@
}
if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
+ X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
X86::isUNPCKLMask(PermMask.Val) ||
X86::isUNPCKHMask(PermMask.Val))
return Op;
@@ -2619,6 +2645,7 @@
// Commute is back and try unpck* again.
Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
+X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
X86::isUNPCKLMask(PermMask.Val) ||
X86::isUNPCKHMask(PermMask.Val))
return Op;
@@ -4231,6 +4258,7 @@
isPSHUFHW_PSHUFLWMask(Mask.Val) ||
X86::isUNPCKLMask(Mask.Val) ||
X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
+ X86::isUNPCKH_v_undef_Mask(Mask.Val) ||
X86::isUNPCKHMask(Mask.Val));
}
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.99
llvm/lib/Target/X86/X86ISelLowering.h:1.100
--- llvm/lib/Target/X86/X86ISelLowering.h:1.99 Fri Apr 20 16:38:10 2007
+++ llvm/lib/Target/X86/X86ISelLowering.h Tue Apr 24 16:16:55 2007
@@ -231,6 +231,11 @@
/// <0, 0, 1, 1>
bool isUNPCKL_v_undef_Mask(SDNode *N);
+ /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
+ /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
+ /// <2, 2, 3, 3>
+ bool isUNPCKH_v_undef_Mask(SDNode *N);
+
/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
/// specifies a shuffle of elements that is suitable for input to MOVSS,
/// MOVSD, and MOVD, i.e. setting the lowest element.
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.394 -> 1.395
---
Log message:
X86 TLS: Implement review feedback.
---
Diffs of the changes: (+3 -2)
X86ISelLowering.cpp |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.394
llvm/lib/Target/X86/X86ISelLowering.cpp:1.395
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.394 Fri Apr 20 16:38:10 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sat Apr 21 15:56:26 2007
@@ -3004,8 +3004,9 @@
SDOperand
X86TargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
// TODO: implement the "local dynamic" model
- // TODO: implement the "initial exec"model for pic executables
- assert(!Subtarget->is64Bit() && "TLS not implemented for X86_64");
+ // TODO: implement the "initial exec"model for pic executables
+ assert(!Subtarget->is64Bit() && Subtarget->isTargetELF() &&
+ "TLS not implemented for non-ELF and 64-bit targets");
GlobalAddressSDNode *GA = cast(Op);
// If the relocation model is PIC, use the "General Dynamic" TLS Model,
// otherwise use the "Local Exec"TLS Model
___
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Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Thanks Anton!
On Apr 17, 2007, at 12:34 PM, Anton Korobeynikov wrote:
>
>
> Changes in directory llvm/lib/Target/X86:
>
> X86ISelLowering.cpp updated: 1.392 -> 1.393
> ---
> Log message:
>
> Add comment
>
>
> ---
> Diffs of the changes: (+9 -0)
>
> X86ISelLowering.cpp |9 +
> 1 files changed, 9 insertions(+)
>
>
> Index: llvm/lib/Target/X86/X86ISelLowering.cpp
> diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.392 llvm/lib/
> Target/X86/X86ISelLowering.cpp:1.393
> --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.392 Tue Apr 17
> 12:21:52 2007
> +++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Apr 17 14:34:00 2007
> @@ -3406,8 +3406,17 @@
> }
> }
>
> +
> +// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw
> targets.
> +// Calls to _alloca is needed to probe the stack when allocating
> more than 4k
> +// bytes in one go. Touching the stack at 4K increments is
> necessary to ensure
> +// that the guard pages used by the OS virtual memory manager are
> allocated in
> +// correct sequence.
> SDOperand X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
> SelectionDAG
> &DAG) {
> + assert(Subtarget->isTargetCygMing() &&
> + "This should be used only on Cygwin/Mingw targets");
> +
>// Get the inputs.
>SDOperand Chain = Op.getOperand(0);
>SDOperand Size = Op.getOperand(1);
>
>
>
> ___
> llvm-commits mailing list
> llvm-commits@cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.392 -> 1.393
---
Log message:
Add comment
---
Diffs of the changes: (+9 -0)
X86ISelLowering.cpp |9 +
1 files changed, 9 insertions(+)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.392
llvm/lib/Target/X86/X86ISelLowering.cpp:1.393
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.392 Tue Apr 17 12:21:52 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Apr 17 14:34:00 2007
@@ -3406,8 +3406,17 @@
}
}
+
+// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
+// Calls to _alloca is needed to probe the stack when allocating more than 4k
+// bytes in one go. Touching the stack at 4K increments is necessary to ensure
+// that the guard pages used by the OS virtual memory manager are allocated in
+// correct sequence.
SDOperand X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
SelectionDAG &DAG) {
+ assert(Subtarget->isTargetCygMing() &&
+ "This should be used only on Cygwin/Mingw targets");
+
// Get the inputs.
SDOperand Chain = Op.getOperand(0);
SDOperand Size = Op.getOperand(1);
___
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Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrInfo.td X86RegisterInfo.cpp
>
> Implemented correct stack probing on mingw/cygwin for dynamic
> alloca's.
> Also, fixed static case in presence of eax livin. This fixes PR331:
> http://llvm.org/PR331
Cool :)
>
> +SDOperand X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
> + SelectionDAG
> &DAG) {
Please add a comment above this that explains why this lowering is
needed. Also, please assert that the subtarget isCygMing() on entry,
to make it obvious to the reader that this is cygwin-specific
lowering code.
Thanks Anton!
-Chris
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrInfo.td X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.390 -> 1.391
X86ISelLowering.h updated: 1.97 -> 1.98
X86InstrInfo.td updated: 1.301 -> 1.302
X86RegisterInfo.cpp updated: 1.209 -> 1.210
---
Log message:
Implemented correct stack probing on mingw/cygwin for dynamic alloca's.
Also, fixed static case in presence of eax livin. This fixes PR331:
http://llvm.org/PR331
PS: Why don't we still have push/pop instructions? :)
---
Diffs of the changes: (+68 -5)
X86ISelLowering.cpp | 36 +++-
X86ISelLowering.h |1 +
X86InstrInfo.td |3 +++
X86RegisterInfo.cpp | 33 +
4 files changed, 68 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.390
llvm/lib/Target/X86/X86ISelLowering.cpp:1.391
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.390 Mon Apr 16 13:10:23 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Apr 17 04:20:00 2007
@@ -237,7 +237,10 @@
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
if (Subtarget->is64Bit())
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
+ if (Subtarget->isTargetCygMing())
+setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
+ else
+setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
if (X86ScalarSSE) {
// Set up the FP register classes.
@@ -3401,6 +3404,36 @@
}
}
+SDOperand X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
+ SelectionDAG &DAG) {
+ // Get the inputs.
+ SDOperand Chain = Op.getOperand(0);
+ SDOperand Size = Op.getOperand(1);
+ // FIXME: Ensure alignment here
+
+ TargetLowering::ArgListTy Args;
+ TargetLowering::ArgListEntry Entry;
+ MVT::ValueType IntPtr = getPointerTy();
+ MVT::ValueType SPTy = (Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
+ const Type *IntPtrTy = getTargetData()->getIntPtrType();
+
+ Entry.Node= Size;
+ Entry.Ty = IntPtrTy;
+ Entry.isInReg = true; // Should pass in EAX
+ Args.push_back(Entry);
+ std::pair CallResult =
+LowerCallTo(Chain, IntPtrTy, false, false, CallingConv::C, false,
+DAG.getExternalSymbol("_alloca", IntPtr), Args, DAG);
+
+ SDOperand SP = DAG.getCopyFromReg(CallResult.second, X86StackPtr, SPTy);
+
+ std::vector Tys;
+ Tys.push_back(SPTy);
+ Tys.push_back(MVT::Other);
+ SDOperand Ops[2] = { SP, CallResult.second };
+ return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
+}
+
SDOperand
X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
MachineFunction &MF = DAG.getMachineFunction();
@@ -4002,6 +4035,7 @@
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
+ case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
}
return SDOperand();
}
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.97
llvm/lib/Target/X86/X86ISelLowering.h:1.98
--- llvm/lib/Target/X86/X86ISelLowering.h:1.97 Mon Apr 9 18:31:19 2007
+++ llvm/lib/Target/X86/X86ISelLowering.h Tue Apr 17 04:20:00 2007
@@ -401,6 +401,7 @@
SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
+SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG);
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.301
llvm/lib/Target/X86/X86InstrInfo.td:1.302
--- llvm/lib/Target/X86/X86InstrInfo.td:1.301 Tue Apr 10 17:10:25 2007
+++ llvm/lib/Target/X86/X86InstrInfo.td Tue Apr 17 04:20:00 2007
@@ -477,6 +477,9 @@
def POP32r : I<0x58, AddRegFrm,
(ops GR32:$reg), "pop{l} $reg", []>, Imp<[ESP],[ESP]>;
+def PUSH32r : I<0x50, AddRegFrm,
+ (ops GR32:$reg), "push{l} $reg", []>, Imp<[ESP],[ESP]>;
+
def MovePCtoStack : I<0, Pseudo, (ops piclabel:$label),
"call $label", []>;
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.209
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.210
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.209 Tue Apr 3 01:18:31 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Apr 17 04:20:00 2007
@@ -1039,14 +1039,39 @@
if (NumBytes) { // adjust stack pointer: ESP -= numbytes
if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
+ // Check, whether EA
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.388 -> 1.389
---
Log message:
Fix mmx paddq, add support for the 'y' register class, though it isn't tested.
---
Diffs of the changes: (+5 -1)
X86ISelLowering.cpp |6 +-
1 files changed, 5 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.388
llvm/lib/Target/X86/X86ISelLowering.cpp:1.389
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.388 Mon Apr 9 18:31:19 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Apr 11 23:14:49 2007
@@ -321,6 +321,7 @@
setOperationAction(ISD::ADD,MVT::v8i8, Legal);
setOperationAction(ISD::ADD,MVT::v4i16, Legal);
setOperationAction(ISD::ADD,MVT::v2i32, Legal);
+setOperationAction(ISD::ADD,MVT::v1i64, Legal);
setOperationAction(ISD::SUB,MVT::v8i8, Legal);
setOperationAction(ISD::SUB,MVT::v4i16, Legal);
@@ -4636,7 +4637,10 @@
else if (VT == MVT::i8)
return std::make_pair(0U, X86::GR8RegisterClass);
break;
-// FIXME: not handling MMX registers yet ('y' constraint).
+case 'y': // MMX_REGS if MMX allowed.
+ if (!Subtarget->hasMMX()) break;
+ return std::make_pair(0U, X86::VR64RegisterClass);
+ break;
case 'Y': // SSE_REGS if SSE2 allowed
if (!Subtarget->hasSSE2()) break;
// FALL THROUGH.
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.387 -> 1.388
X86ISelLowering.h updated: 1.96 -> 1.97
---
Log message:
remove some dead hooks
---
Diffs of the changes: (+0 -49)
X86ISelLowering.cpp | 35 ---
X86ISelLowering.h | 14 --
2 files changed, 49 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.387
llvm/lib/Target/X86/X86ISelLowering.cpp:1.388
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.387 Mon Apr 9 17:26:30 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Apr 9 18:31:19 2007
@@ -4092,41 +4092,6 @@
}
-/// isLegalAddressImmediate - Return true if the integer value can be used
-/// as the offset of the target addressing mode for load / store of the
-/// given type.
-bool X86TargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty)
const{
- // X86 allows a sign-extended 32-bit immediate field.
- return (V > -(1LL << 32) && V < (1LL << 32)-1);
-}
-
-/// isLegalAddressImmediate - Return true if the GlobalValue can be used as
-/// the offset of the target addressing mode.
-bool X86TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
- // In 64-bit mode, GV is 64-bit so it won't fit in the 32-bit displacement
- // field unless we are in small code model.
- if (Subtarget->is64Bit() &&
- getTargetMachine().getCodeModel() != CodeModel::Small)
-return false;
-
- return (!Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false));
-}
-
-/// isLegalAddressScale - Return true if the integer value can be used as the
-/// scale of the target addressing mode for load / store of the given type.
-bool X86TargetLowering::isLegalAddressScale(int64_t S, const Type *Ty) const {
- switch (S) {
- default:
-return false;
- case 2: case 4: case 8:
-return true;
- // FIXME: These require both scale + index last and thus more expensive.
- // How to tell LSR to try for 2, 4, 8 first?
- case 3: case 5: case 9:
-return true;
- }
-}
-
/// isShuffleMaskLegal - Targets can use this to indicate that they only
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.96
llvm/lib/Target/X86/X86ISelLowering.h:1.97
--- llvm/lib/Target/X86/X86ISelLowering.h:1.96 Mon Apr 9 17:26:30 2007
+++ llvm/lib/Target/X86/X86ISelLowering.h Mon Apr 9 18:31:19 2007
@@ -339,20 +339,6 @@
/// by AM is legal for this target, for a load/store of the specified type.
virtual bool isLegalAddressingMode(const AddrMode &AM, const Type
*Ty)const;
-/// isLegalAddressImmediate - Return true if the integer value can be used
-/// as the offset of the target addressing mode for load / store of the
-/// given type.
-virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
-
-/// isLegalAddressImmediate - Return true if the GlobalValue can be used as
-/// the offset of the target addressing mode.
-virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
-
-/// isLegalAddressScale - Return true if the integer value can be used as
-/// the scale of the target addressing mode for load / store of the given
-/// type.
-virtual bool isLegalAddressScale(int64_t S, const Type *Ty) const;
-
/// isShuffleMaskLegal - Targets can use this to indicate that they only
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.386 -> 1.387
X86ISelLowering.h updated: 1.95 -> 1.96
---
Log message:
remove some dead target hooks, subsumed by isLegalAddressingMode
---
Diffs of the changes: (+0 -28)
X86ISelLowering.cpp | 16
X86ISelLowering.h | 12
2 files changed, 28 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.386
llvm/lib/Target/X86/X86ISelLowering.cpp:1.387
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.386 Mon Apr 9 00:49:22 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Apr 9 17:26:30 2007
@@ -4127,22 +4127,6 @@
}
}
-/// isLegalAddressScaleAndImm - Return true if S works for IsLegalAddressScale
-/// and V works for isLegalAddressImmediate _and_ both can be applied
-/// simultaneously to the same instruction.
-bool X86TargetLowering::isLegalAddressScaleAndImm(int64_t S, int64_t V,
- const Type* Ty) const {
- return isLegalAddressScale(S, Ty) && isLegalAddressImmediate(V, Ty);
-}
-
-/// isLegalAddressScaleAndImm - Return true if S works for IsLegalAddressScale
-/// and GV works for isLegalAddressImmediate _and_ both can be applied
-/// simultaneously to the same instruction.
-bool X86TargetLowering::isLegalAddressScaleAndImm(int64_t S, GlobalValue *GV,
- const Type* Ty) const {
- return isLegalAddressScale(S, Ty) && isLegalAddressImmediate(GV);
-}
-
/// isShuffleMaskLegal - Targets can use this to indicate that they only
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.95
llvm/lib/Target/X86/X86ISelLowering.h:1.96
--- llvm/lib/Target/X86/X86ISelLowering.h:1.95 Fri Mar 30 18:15:24 2007
+++ llvm/lib/Target/X86/X86ISelLowering.h Mon Apr 9 17:26:30 2007
@@ -353,18 +353,6 @@
/// type.
virtual bool isLegalAddressScale(int64_t S, const Type *Ty) const;
-/// isLegalAddressScaleAndImm - Return true if S works for
-/// IsLegalAddressScale and V works for isLegalAddressImmediate _and_
-/// both can be applied simultaneously to the same instruction.
-virtual bool isLegalAddressScaleAndImm(int64_t S, int64_t V,
- const Type *Ty) const;
-
-/// isLegalAddressScaleAndImm - Return true if S works for
-/// IsLegalAddressScale and GV works for isLegalAddressImmediate _and_
-/// both can be applied simultaneously to the same instruction.
-virtual bool isLegalAddressScaleAndImm(int64_t S, GlobalValue *GV,
- const Type *Ty) const;
-
/// isShuffleMaskLegal - Targets can use this to indicate that they only
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.385 -> 1.386
---
Log message:
move a bunch of register constraints from being handled by
getRegClassForInlineAsmConstraint to being handled by
getRegForInlineAsmConstraint. This allows us to let the llvm register allocator
allocate, which gives us better code. For example,
X86/2007-01-29-InlineAsm-ir.ll
used to compile to:
_run_init_process:
subl $4, %esp
movl %ebx, (%esp)
xorl %ebx, %ebx
movl $11, %eax
movl %ebx, %ecx
movl %ebx, %edx
# InlineAsm Start
push %ebx ; movl %ebx,%ebx ; int $0x80 ; pop %ebx
# InlineAsm End
Now we get:
_run_init_process:
xorl %ecx, %ecx
movl $11, %eax
movl %ecx, %edx
# InlineAsm Start
push %ebx ; movl %ecx,%ebx ; int $0x80 ; pop %ebx
# InlineAsm End
---
Diffs of the changes: (+36 -42)
X86ISelLowering.cpp | 78
1 files changed, 36 insertions(+), 42 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.385
llvm/lib/Target/X86/X86ISelLowering.cpp:1.386
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.385 Mon Apr 9 00:31:48 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Apr 9 00:49:22 2007
@@ -4645,39 +4645,12 @@
MVT::ValueType VT) const {
if (Constraint.size() == 1) {
// FIXME: not handling fp-stack yet!
-// FIXME: not handling MMX registers yet ('y' constraint).
switch (Constraint[0]) { // GCC X86 Constraint Letters
default: break; // Unknown constraint letter
case 'A': // EAX/EDX
if (VT == MVT::i32 || VT == MVT::i64)
return make_vector(X86::EAX, X86::EDX, 0);
break;
-case 'r': // GENERAL_REGS
-case 'R': // LEGACY_REGS
- if (VT == MVT::i64 && Subtarget->is64Bit())
-return make_vector(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
- X86::RSI, X86::RDI, X86::RBP, X86::RSP,
- X86::R8, X86::R9, X86::R10, X86::R11,
- X86::R12, X86::R13, X86::R14, X86::R15,
0);
- if (VT == MVT::i32)
-return make_vector(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
- X86::ESI, X86::EDI, X86::EBP, X86::ESP,
0);
- else if (VT == MVT::i16)
-return make_vector(X86::AX, X86::DX, X86::CX, X86::BX,
- X86::SI, X86::DI, X86::BP, X86::SP, 0);
- else if (VT == MVT::i8)
-return make_vector(X86::AL, X86::DL, X86::CL, X86::BL, 0);
- break;
-case 'l': // INDEX_REGS
- if (VT == MVT::i32)
-return make_vector(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
- X86::ESI, X86::EDI, X86::EBP, 0);
- else if (VT == MVT::i16)
-return make_vector(X86::AX, X86::DX, X86::CX, X86::BX,
- X86::SI, X86::DI, X86::BP, 0);
- else if (VT == MVT::i8)
-return make_vector(X86::AL, X86::DL, X86::CL, X86::DL, 0);
- break;
case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
case 'Q': // Q_REGS
if (VT == MVT::i32)
@@ -4687,18 +4660,6 @@
else if (VT == MVT::i8)
return make_vector(X86::AL, X86::DL, X86::CL, X86::DL, 0);
break;
-case 'x': // SSE_REGS if SSE1 allowed
- if (Subtarget->hasSSE1())
-return make_vector(X86::XMM0, X86::XMM1, X86::XMM2,
X86::XMM3,
- X86::XMM4, X86::XMM5, X86::XMM6,
X86::XMM7,
- 0);
- return std::vector();
-case 'Y': // SSE_REGS if SSE2 allowed
- if (Subtarget->hasSSE2())
-return make_vector(X86::XMM0, X86::XMM1, X86::XMM2,
X86::XMM3,
- X86::XMM4, X86::XMM5, X86::XMM6,
X86::XMM7,
- 0);
- return std::vector();
}
}
@@ -4714,11 +4675,44 @@
// GCC Constraint Letters
switch (Constraint[0]) {
default: break;
-case 'x':
- if (VT == MVT::f32 || VT == MVT::i32)
+case 'r': // GENERAL_REGS
+case 'R': // LEGACY_REGS
+case 'l': // INDEX_REGS
+ if (VT == MVT::i64 && Subtarget->is64Bit())
+return std::make_pair(0U, X86::GR64RegisterClass);
+ if (VT == MVT::i32)
+return std::make_pair(0U, X86::GR32RegisterClass);
+ else if (VT == MVT::i16)
+return std::make_pair(0U, X86::GR16RegisterClass);
+ else if (VT == MVT::i8)
+return std::make_pair(0U, X86::GR8RegisterClass);
+ break;
+// FIXME: not handling MMX registers yet ('y' constraint).
+case 'Y': // SSE_REGS if SSE2 allowed
+ if (!Subtarget->hasSSE2()) break;
+ // FALL THROUGH.
+case 'x': // SSE_REGS if SSE1 allowed
+ if (!Subtarget->hasSSE1()) break
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.384 -> 1.385
---
Log message:
implement support for CodeGen/X86/inline-asm-x-scalar.ll:test3 - i32/i64 values
used with x constraints.
---
Diffs of the changes: (+2 -2)
X86ISelLowering.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.384
llvm/lib/Target/X86/X86ISelLowering.cpp:1.385
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.384 Mon Apr 9 00:11:28 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Apr 9 00:31:48 2007
@@ -4715,9 +4715,9 @@
switch (Constraint[0]) {
default: break;
case 'x':
- if (VT == MVT::f32)
+ if (VT == MVT::f32 || VT == MVT::i32)
return std::make_pair(0U, X86::FR32RegisterClass);
- if (VT == MVT::f64)
+ if (VT == MVT::f64 || VT == MVT::i64)
return std::make_pair(0U, X86::FR64RegisterClass);
break;
}
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.383 -> 1.384
---
Log message:
implement CodeGen/X86/inline-asm-x-scalar.ll
---
Diffs of the changes: (+15 -1)
X86ISelLowering.cpp | 16 +++-
1 files changed, 15 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.383
llvm/lib/Target/X86/X86ISelLowering.cpp:1.384
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.383 Fri Mar 30 18:15:24 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Apr 9 00:11:28 2007
@@ -4640,7 +4640,6 @@
return TargetLowering::isOperandValidForConstraint(Op, Constraint, DAG);
}
-
std::vector X86TargetLowering::
getRegClassForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const {
@@ -4709,6 +4708,21 @@
std::pair
X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const {
+ // First, see if this is a constraint that directly corresponds to an LLVM
+ // register class.
+ if (Constraint.size() == 1) {
+// GCC Constraint Letters
+switch (Constraint[0]) {
+default: break;
+case 'x':
+ if (VT == MVT::f32)
+return std::make_pair(0U, X86::FR32RegisterClass);
+ if (VT == MVT::f64)
+return std::make_pair(0U, X86::FR64RegisterClass);
+ break;
+}
+ }
+
// Use the default implementation in TargetLowering to convert the register
// constraint into a member of a register class.
std::pair Res;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.382 -> 1.383
X86ISelLowering.h updated: 1.94 -> 1.95
---
Log message:
implement the new addressing mode description hook.
---
Diffs of the changes: (+49 -0)
X86ISelLowering.cpp | 45 +
X86ISelLowering.h |4
2 files changed, 49 insertions(+)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.382
llvm/lib/Target/X86/X86ISelLowering.cpp:1.383
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.382 Tue Mar 27 20:02:54 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Mar 30 18:15:24 2007
@@ -4047,6 +4047,51 @@
}
}
+// isLegalAddressingMode - Return true if the addressing mode represented
+// by AM is legal for this target, for a load/store of the specified type.
+bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
+ const Type *Ty) const {
+ // X86 supports extremely general addressing modes.
+
+ // X86 allows a sign-extended 32-bit immediate field as a displacement.
+ if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
+return false;
+
+ if (AM.BaseGV) {
+// X86-64 only supports addr of globals in small code model.
+if (Subtarget->is64Bit() &&
+getTargetMachine().getCodeModel() != CodeModel::Small)
+ return false;
+
+// We can only fold this if we don't need a load either.
+if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
+ return false;
+ }
+
+ switch (AM.Scale) {
+ case 0:
+ case 1:
+ case 2:
+ case 4:
+ case 8:
+// These scales always work.
+break;
+ case 3:
+ case 5:
+ case 9:
+// These scales are formed with basereg+scalereg. Only accept if there is
+// no basereg yet.
+if (AM.HasBaseReg)
+ return false;
+break;
+ default: // Other stuff never works.
+return false;
+ }
+
+ return true;
+}
+
+
/// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode for load / store of the
/// given type.
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.94
llvm/lib/Target/X86/X86ISelLowering.h:1.95
--- llvm/lib/Target/X86/X86ISelLowering.h:1.94 Sat Mar 24 21:14:49 2007
+++ llvm/lib/Target/X86/X86ISelLowering.h Fri Mar 30 18:15:24 2007
@@ -335,6 +335,10 @@
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
+/// isLegalAddressingMode - Return true if the addressing mode represented
+/// by AM is legal for this target, for a load/store of the specified type.
+virtual bool isLegalAddressingMode(const AddrMode &AM, const Type
*Ty)const;
+
/// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode for load / store of the
/// given type.
___
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Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrMMX.td
On 3/27/07, Chris Lattner <[EMAIL PROTECTED]> wrote: > > On Mar 27, 2007, at 5:57 PM, Bill Wendling wrote: > > > -// This file was developed by the Evan Cheng and is distributed > > under the > > +// This file was developed by Evan Cheng and is distributed under the > > Why are you dissing on the evan? > Because he's too busy to notice. :-) -bw ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.381 -> 1.382
---
Log message:
Remove cruft I put in there...
---
Diffs of the changes: (+0 -72)
X86ISelLowering.cpp | 72
1 files changed, 72 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.381
llvm/lib/Target/X86/X86ISelLowering.cpp:1.382
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.381 Tue Mar 27 19:57:11 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Mar 27 20:02:54 2007
@@ -2286,78 +2286,6 @@
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
}
-/// LowerBuildVectorv8i8 - Custom lower build_vector of v8i8.
-///
-static SDOperand LowerBuildVectorv8i8(SDOperand Op, unsigned NonZeros,
- unsigned NumNonZero, unsigned NumZero,
- SelectionDAG &DAG, TargetLowering &TLI) {
- if (NumNonZero > 8)
-return SDOperand();
-
- SDOperand V(0, 0);
- bool First = true;
- for (unsigned i = 0; i < 8; ++i) {
-bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
-if (ThisIsNonZero && First) {
- if (NumZero)
-V = getZeroVector(MVT::v4i16, DAG);
- else
-V = DAG.getNode(ISD::UNDEF, MVT::v4i16);
- First = false;
-}
-
-if ((i & 1) != 0) {
- SDOperand ThisElt(0, 0), LastElt(0, 0);
- bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
- if (LastIsNonZero) {
-LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
- }
- if (ThisIsNonZero) {
-ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
-ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
- ThisElt, DAG.getConstant(8, MVT::i8));
-if (LastIsNonZero)
- ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
- } else
-ThisElt = LastElt;
-
- if (ThisElt.Val)
-V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v4i16, V, ThisElt,
-DAG.getConstant(i/2, TLI.getPointerTy()));
-}
- }
-
- return DAG.getNode(ISD::BIT_CONVERT, MVT::v8i8, V);
-}
-
-/// LowerBuildVectorv4i16 - Custom lower build_vector of v4i16.
-///
-static SDOperand LowerBuildVectorv4i16(SDOperand Op, unsigned NonZeros,
- unsigned NumNonZero, unsigned NumZero,
- SelectionDAG &DAG, TargetLowering &TLI)
{
- if (NumNonZero > 4)
-return SDOperand();
-
- SDOperand V(0, 0);
- bool First = true;
- for (unsigned i = 0; i < 4; ++i) {
-bool isNonZero = (NonZeros & (1 << i)) != 0;
-if (isNonZero) {
- if (First) {
-if (NumZero)
- V = getZeroVector(MVT::v4i16, DAG);
-else
- V = DAG.getNode(ISD::UNDEF, MVT::v4i16);
-First = false;
- }
- V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v4i16, V, Op.getOperand(i),
- DAG.getConstant(i, TLI.getPointerTy()));
-}
- }
-
- return V;
-}
-
/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
///
static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
___
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Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrMMX.td
On Mar 27, 2007, at 5:57 PM, Bill Wendling wrote: > -// This file was developed by the Evan Cheng and is distributed > under the > +// This file was developed by Evan Cheng and is distributed under the Why are you dissing on the evan? -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrMMX.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.380 -> 1.381
X86InstrMMX.td updated: 1.27 -> 1.28
---
Log message:
Unbreak mmx arithmetic. It was barfing trying to do v8i8 arithmetic.
---
Diffs of the changes: (+78 -3)
X86ISelLowering.cpp | 79 ++--
X86InstrMMX.td |2 -
2 files changed, 78 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.380
llvm/lib/Target/X86/X86ISelLowering.cpp:1.381
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.380 Tue Mar 27 15:22:40 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Mar 27 19:57:11 2007
@@ -370,6 +370,9 @@
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
+
+setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
+setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
}
if (Subtarget->hasSSE1()) {
@@ -2283,6 +2286,78 @@
return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
}
+/// LowerBuildVectorv8i8 - Custom lower build_vector of v8i8.
+///
+static SDOperand LowerBuildVectorv8i8(SDOperand Op, unsigned NonZeros,
+ unsigned NumNonZero, unsigned NumZero,
+ SelectionDAG &DAG, TargetLowering &TLI) {
+ if (NumNonZero > 8)
+return SDOperand();
+
+ SDOperand V(0, 0);
+ bool First = true;
+ for (unsigned i = 0; i < 8; ++i) {
+bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
+if (ThisIsNonZero && First) {
+ if (NumZero)
+V = getZeroVector(MVT::v4i16, DAG);
+ else
+V = DAG.getNode(ISD::UNDEF, MVT::v4i16);
+ First = false;
+}
+
+if ((i & 1) != 0) {
+ SDOperand ThisElt(0, 0), LastElt(0, 0);
+ bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
+ if (LastIsNonZero) {
+LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
+ }
+ if (ThisIsNonZero) {
+ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
+ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
+ ThisElt, DAG.getConstant(8, MVT::i8));
+if (LastIsNonZero)
+ ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
+ } else
+ThisElt = LastElt;
+
+ if (ThisElt.Val)
+V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v4i16, V, ThisElt,
+DAG.getConstant(i/2, TLI.getPointerTy()));
+}
+ }
+
+ return DAG.getNode(ISD::BIT_CONVERT, MVT::v8i8, V);
+}
+
+/// LowerBuildVectorv4i16 - Custom lower build_vector of v4i16.
+///
+static SDOperand LowerBuildVectorv4i16(SDOperand Op, unsigned NonZeros,
+ unsigned NumNonZero, unsigned NumZero,
+ SelectionDAG &DAG, TargetLowering &TLI)
{
+ if (NumNonZero > 4)
+return SDOperand();
+
+ SDOperand V(0, 0);
+ bool First = true;
+ for (unsigned i = 0; i < 4; ++i) {
+bool isNonZero = (NonZeros & (1 << i)) != 0;
+if (isNonZero) {
+ if (First) {
+if (NumZero)
+ V = getZeroVector(MVT::v4i16, DAG);
+else
+ V = DAG.getNode(ISD::UNDEF, MVT::v4i16);
+First = false;
+ }
+ V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v4i16, V, Op.getOperand(i),
+ DAG.getConstant(i, TLI.getPointerTy()));
+}
+ }
+
+ return V;
+}
+
/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
///
static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
@@ -2426,13 +2501,13 @@
return SDOperand();
// If element VT is < 32 bits, convert it to inserts into a zero vector.
- if (EVTBits == 8) {
+ if (EVTBits == 8 && NumElems == 16) {
SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
*this);
if (V.Val) return V;
}
- if (EVTBits == 16) {
+ if (EVTBits == 16 && NumElems == 8) {
SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
*this);
if (V.Val) return V;
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.27
llvm/lib/Target/X86/X86InstrMMX.td:1.28
--- llvm/lib/Target/X86/X86InstrMMX.td:1.27 Tue Mar 27 16:20:36 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Tue Mar 27 19:57:11 2007
@@ -2,7 +2,7 @@
//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the Evan Cheng and is distributed under the
+// This file was developed by Evan Cheng and is distributed under the
// University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===--
Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrMMX.td
On Mar 27, 2007, at 1:22 PM, Bill Wendling wrote: > +// Some special case pandn patterns. > +def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 > immAllOnesV))), > + VR64:$src2)), > + (MMX_PANDNrr VR64:$src1, VR64:$src2)>; > +def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 > immAllOnesV))), > + VR64:$src2)), > + (MMX_PANDNrr VR64:$src1, VR64:$src2)>; > +def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 > immAllOnesV))), > + VR64:$src2)), > + (MMX_PANDNrr VR64:$src1, VR64:$src2)>; > + > +def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 > immAllOnesV))), > + (load addr:$src2))), > + (MMX_PANDNrm VR64:$src1, addr:$src2)>; > +def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 > immAllOnesV))), > + (load addr:$src2))), > + (MMX_PANDNrm VR64:$src1, addr:$src2)>; > +def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 > immAllOnesV))), > + (load addr:$src2))), > + (MMX_PANDNrm VR64:$src1, addr:$src2)>; These shouldn't be needed. Please get legalize to promote "build_vector" to a single vector type like it does for loads. This would eliminate the need for these patterns. -chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrMMX.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.379 -> 1.380
X86InstrMMX.td updated: 1.25 -> 1.26
---
Log message:
Fix so that pandn is emitted instead of an xor/and combo. Add integer
comparison operators.
---
Diffs of the changes: (+55 -13)
X86ISelLowering.cpp |8 --
X86InstrMMX.td | 60 +++-
2 files changed, 55 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.379
llvm/lib/Target/X86/X86ISelLowering.cpp:1.380
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.379 Mon Mar 26 03:03:33 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Mar 27 15:22:40 2007
@@ -361,13 +361,15 @@
AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
-setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
-setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
-setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
+setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
}
if (Subtarget->hasSSE1()) {
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.25
llvm/lib/Target/X86/X86InstrMMX.td:1.26
--- llvm/lib/Target/X86/X86InstrMMX.td:1.25 Mon Mar 26 02:53:08 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Tue Mar 27 15:22:40 2007
@@ -43,11 +43,12 @@
// MMX Pattern Fragments
//===--===//
-def loadv1i64 : PatFrag<(ops node:$ptr), (v1i64 (load node:$ptr))>;
+def load_mmx : PatFrag<(ops node:$ptr), (v1i64 (load node:$ptr))>;
def bc_v8i8 : PatFrag<(ops node:$in), (v8i8 (bitconvert node:$in))>;
def bc_v4i16 : PatFrag<(ops node:$in), (v4i16 (bitconvert node:$in))>;
def bc_v2i32 : PatFrag<(ops node:$in), (v2i32 (bitconvert node:$in))>;
+def bc_v1i64 : PatFrag<(ops node:$in), (v1i64 (bitconvert node:$in))>;
//===--===//
// MMX Multiclasses
@@ -66,7 +67,7 @@
!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (OpVT (OpNode VR64:$src1,
(bitconvert
- (loadv1i64 addr:$src2)]>;
+ (load_mmx addr:$src2)]>;
}
multiclass MMXI_binop_rm_int opc, string OpcodeStr, Intrinsic IntId,
@@ -79,7 +80,7 @@
def rm : MMXI;
+ (bitconvert (load_mmx addr:$src2]>;
}
// MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
@@ -97,7 +98,7 @@
def rm : MMXI;
+(OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
}
multiclass MMXI_binop_rmi_int opc, bits<8> opc2, Format ImmForm,
@@ -108,7 +109,7 @@
def rm : MMXI;
+(bitconvert (load_mmx addr:$src2]>;
def ri : MMXIi8;
def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
(ops VR64:$dst, VR64:$src1, VR64:$src2),
@@ -191,7 +192,7 @@
"punpckhwd {$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v4i16 (vector_shuffle VR64:$src1,
- (bc_v4i16 (loadv1i64 addr:$src2)),
+ (bc_v4i16 (load_mmx addr:$src2)),
MMX_UNPCKH_shuffle_mask)))]>;
def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
(ops VR64:$dst, VR64:$src1, VR64:$src2),
@@ -204,7 +205,7 @@
"punpckhdq {$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v1i64 (vector_shuffle VR64:$src1,
- (loadv1i64 addr:$src2),
+ (load_mmx addr:$src2),
MMX_UNPCKH_shuffle_mask)))]>;
}
@@ -251,6 +252,15 @@
defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
+// Integer comparison
+defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
+defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.378 -> 1.379 --- Log message: Promote to v1i64 type... --- Diffs of the changes: (+15 -9) X86ISelLowering.cpp | 24 +++- 1 files changed, 15 insertions(+), 9 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.378 llvm/lib/Target/X86/X86ISelLowering.cpp:1.379 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.378 Mon Mar 26 02:53:08 2007 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Mar 26 03:03:33 2007 @@ -330,22 +330,28 @@ setOperationAction(ISD::MUL,MVT::v4i16, Legal); setOperationAction(ISD::AND,MVT::v8i8, Promote); -AddPromotedToType (ISD::AND,MVT::v8i8, MVT::v2i32); +AddPromotedToType (ISD::AND,MVT::v8i8, MVT::v1i64); setOperationAction(ISD::AND,MVT::v4i16, Promote); -AddPromotedToType (ISD::AND,MVT::v4i16, MVT::v2i32); -setOperationAction(ISD::AND,MVT::v2i32, Legal); +AddPromotedToType (ISD::AND,MVT::v4i16, MVT::v1i64); +setOperationAction(ISD::AND,MVT::v2i32, Promote); +AddPromotedToType (ISD::AND,MVT::v2i32, MVT::v1i64); +setOperationAction(ISD::AND,MVT::v1i64, Legal); setOperationAction(ISD::OR, MVT::v8i8, Promote); -AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v2i32); +AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64); setOperationAction(ISD::OR, MVT::v4i16, Promote); -AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v2i32); -setOperationAction(ISD::OR, MVT::v2i32, Legal); +AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64); +setOperationAction(ISD::OR, MVT::v2i32, Promote); +AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64); +setOperationAction(ISD::OR, MVT::v1i64, Legal); setOperationAction(ISD::XOR,MVT::v8i8, Promote); -AddPromotedToType (ISD::XOR,MVT::v8i8, MVT::v2i32); +AddPromotedToType (ISD::XOR,MVT::v8i8, MVT::v1i64); setOperationAction(ISD::XOR,MVT::v4i16, Promote); -AddPromotedToType (ISD::XOR,MVT::v4i16, MVT::v2i32); -setOperationAction(ISD::XOR,MVT::v2i32, Legal); +AddPromotedToType (ISD::XOR,MVT::v4i16, MVT::v1i64); +setOperationAction(ISD::XOR,MVT::v2i32, Promote); +AddPromotedToType (ISD::XOR,MVT::v2i32, MVT::v1i64); +setOperationAction(ISD::XOR,MVT::v1i64, Legal); setOperationAction(ISD::LOAD, MVT::v8i8, Promote); AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrMMX.td X86RegisterInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.377 -> 1.378
X86InstrMMX.td updated: 1.24 -> 1.25
X86RegisterInfo.td updated: 1.40 -> 1.41
---
Log message:
Add support for the v1i64 type. This makes better code for this:
#include
extern __m64 C;
void baz(__v2si *A, __v2si *B)
{
*A = C;
_mm_empty();
}
We get this:
_baz:
call "L1$pb"
"L1$pb":
popl %eax
movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
movq (%eax), %mm0
movl 4(%esp), %eax
movq %mm0, (%eax)
emms
ret
GCC gives us this:
_baz:
pushl %ebx
callL3
"L001$pb":
L3:
popl%ebx
subl$8, %esp
movlL_C$non_lazy_ptr-"L001$pb"(%ebx), %eax
movl(%eax), %edx
movl4(%eax), %ecx
movl16(%esp), %eax
movl%edx, (%eax)
movl%ecx, 4(%eax)
emms
addl$8, %esp
popl%ebx
ret
---
Diffs of the changes: (+58 -28)
X86ISelLowering.cpp |9 --
X86InstrMMX.td | 75 +++-
X86RegisterInfo.td |2 -
3 files changed, 58 insertions(+), 28 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.377
llvm/lib/Target/X86/X86ISelLowering.cpp:1.378
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.377 Sat Mar 24 21:14:49 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Mar 26 02:53:08 2007
@@ -314,6 +314,7 @@
addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
+addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
// FIXME: add MMX packed arithmetics
@@ -347,10 +348,12 @@
setOperationAction(ISD::XOR,MVT::v2i32, Legal);
setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
-AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32);
+AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
-AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v2i32);
-setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
+AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
+setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
+AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
+setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.24
llvm/lib/Target/X86/X86InstrMMX.td:1.25
--- llvm/lib/Target/X86/X86InstrMMX.td:1.24 Fri Mar 23 17:35:46 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Mon Mar 26 02:53:08 2007
@@ -37,12 +37,13 @@
def : Pat<(v8i8 (undef)), (IMPLICIT_DEF_VR64)>;
def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>;
def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>;
+def : Pat<(v1i64 (undef)), (IMPLICIT_DEF_VR64)>;
//===--===//
// MMX Pattern Fragments
//===--===//
-def loadv2i32 : PatFrag<(ops node:$ptr), (v2i32 (load node:$ptr))>;
+def loadv1i64 : PatFrag<(ops node:$ptr), (v1i64 (load node:$ptr))>;
def bc_v8i8 : PatFrag<(ops node:$in), (v8i8 (bitconvert node:$in))>;
def bc_v4i16 : PatFrag<(ops node:$in), (v4i16 (bitconvert node:$in))>;
@@ -65,7 +66,7 @@
!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (OpVT (OpNode VR64:$src1,
(bitconvert
- (loadv2i32 addr:$src2)]>;
+ (loadv1i64 addr:$src2)]>;
}
multiclass MMXI_binop_rm_int opc, string OpcodeStr, Intrinsic IntId,
@@ -78,25 +79,25 @@
def rm : MMXI;
+ (bitconvert (loadv1i64 addr:$src2]>;
}
- // MMXI_binop_rm_v2i32 - Simple MMX binary operator whose type is v2i32.
+ // MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
//
// FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen
knew
// to collapse (bitconvert VT to VT) into its operand.
//
- multiclass MMXI_binop_rm_v2i32 opc, string OpcodeStr, SDNode OpNode,
+ multiclass MMXI_binop_rm_v1i64 opc, string OpcodeStr, SDNode OpNode,
bit Commutable = 0> {
def rr : MMXI {
+ [(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
let isCommutable = Commutable;
}
def rm : MMXI;
+
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.376 -> 1.377
X86ISelLowering.h updated: 1.93 -> 1.94
---
Log message:
switch TargetLowering::getConstraintType to take the entire constraint,
not just the first letter. No functionality change.
---
Diffs of the changes: (+17 -13)
X86ISelLowering.cpp | 28
X86ISelLowering.h |2 +-
2 files changed, 17 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.376
llvm/lib/Target/X86/X86ISelLowering.cpp:1.377
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.376 Sat Mar 24 20:57:35 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sat Mar 24 21:14:49 2007
@@ -4521,19 +4521,23 @@
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
X86TargetLowering::ConstraintType
-X86TargetLowering::getConstraintType(char ConstraintLetter) const {
- switch (ConstraintLetter) {
- case 'A':
- case 'r':
- case 'R':
- case 'l':
- case 'q':
- case 'Q':
- case 'x':
- case 'Y':
-return C_RegisterClass;
- default: return TargetLowering::getConstraintType(ConstraintLetter);
+X86TargetLowering::getConstraintType(const std::string &Constraint) const {
+ if (Constraint.size() == 1) {
+switch (Constraint[0]) {
+case 'A':
+case 'r':
+case 'R':
+case 'l':
+case 'q':
+case 'Q':
+case 'x':
+case 'Y':
+ return C_RegisterClass;
+default:
+ break;
+}
}
+ return TargetLowering::getConstraintType(Constraint);
}
/// isOperandValidForConstraint - Return the specified operand (possibly
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.93
llvm/lib/Target/X86/X86ISelLowering.h:1.94
--- llvm/lib/Target/X86/X86ISelLowering.h:1.93 Wed Mar 21 16:51:52 2007
+++ llvm/lib/Target/X86/X86ISelLowering.h Sat Mar 24 21:14:49 2007
@@ -316,7 +316,7 @@
SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
-ConstraintType getConstraintType(char ConstraintLetter) const;
+ConstraintType getConstraintType(const std::string &Constraint) const;
std::vector
getRegClassForInlineAsmConstraint(const std::string &Constraint,
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.375 -> 1.376
---
Log message:
enforce the proper range for the i386 N constraint.
---
Diffs of the changes: (+9 -8)
X86ISelLowering.cpp | 17 +
1 files changed, 9 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.375
llvm/lib/Target/X86/X86ISelLowering.cpp:1.376
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.375 Thu Mar 22 13:42:45 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sat Mar 24 20:57:35 2007
@@ -4544,16 +4544,17 @@
switch (Constraint) {
default: break;
case 'I':
-if (isa(Op)) {
- unsigned Value = cast(Op)->getValue();
- if (Value <= 31)
+if (ConstantSDNode *C = dyn_cast(Op)) {
+ if (C->getValue() <= 31)
return Op;
- else
-return SDOperand(0,0);
-} else {
-return SDOperand(0,0);
}
-break;
+return SDOperand(0,0);
+ case 'N':
+if (ConstantSDNode *C = dyn_cast(Op)) {
+ if (C->getValue() <= 255)
+return Op;
+}
+return SDOperand(0,0);
case 'i':
// Literal immediates are always ok.
if (isa(Op)) return Op;
___
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llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.372 -> 1.373
---
Log message:
fix a warning
---
Diffs of the changes: (+1 -1)
X86ISelLowering.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.372
llvm/lib/Target/X86/X86ISelLowering.cpp:1.373
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.372 Fri Mar 16 19:13:28 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sun Mar 18 19:39:32 2007
@@ -4526,7 +4526,7 @@
case 'I':
if (isa(Op)) {
unsigned Value = cast(Op)->getValue();
- if (Value >= 0 && Value <= 31)
+ if (Value <= 31)
return Op;
else
return SDOperand(0,0);
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.371 -> 1.372
---
Log message:
Support 'I' inline asm constraint.
---
Diffs of the changes: (+11 -0)
X86ISelLowering.cpp | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.371
llvm/lib/Target/X86/X86ISelLowering.cpp:1.372
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.371 Fri Mar 16 04:44:46 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Mar 16 19:13:28 2007
@@ -4523,6 +4523,17 @@
isOperandValidForConstraint(SDOperand Op, char Constraint, SelectionDAG &DAG) {
switch (Constraint) {
default: break;
+ case 'I':
+if (isa(Op)) {
+ unsigned Value = cast(Op)->getValue();
+ if (Value >= 0 && Value <= 31)
+return Op;
+ else
+return SDOperand(0,0);
+} else {
+return SDOperand(0,0);
+}
+break;
case 'i':
// Literal immediates are always ok.
if (isa(Op)) return Op;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrMMX.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.370 -> 1.371
X86InstrMMX.td updated: 1.20 -> 1.21
---
Log message:
And now support for MMX logical operations.
---
Diffs of the changes: (+54 -2)
X86ISelLowering.cpp | 18 ++
X86InstrMMX.td | 38 --
2 files changed, 54 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.370
llvm/lib/Target/X86/X86ISelLowering.cpp:1.371
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.370 Thu Mar 15 16:24:36 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Mar 16 04:44:46 2007
@@ -328,6 +328,24 @@
setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
setOperationAction(ISD::MUL,MVT::v4i16, Legal);
+setOperationAction(ISD::AND,MVT::v8i8, Promote);
+AddPromotedToType (ISD::AND,MVT::v8i8, MVT::v2i32);
+setOperationAction(ISD::AND,MVT::v4i16, Promote);
+AddPromotedToType (ISD::AND,MVT::v4i16, MVT::v2i32);
+setOperationAction(ISD::AND,MVT::v2i32, Legal);
+
+setOperationAction(ISD::OR, MVT::v8i8, Promote);
+AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v2i32);
+setOperationAction(ISD::OR, MVT::v4i16, Promote);
+AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v2i32);
+setOperationAction(ISD::OR, MVT::v2i32, Legal);
+
+setOperationAction(ISD::XOR,MVT::v8i8, Promote);
+AddPromotedToType (ISD::XOR,MVT::v8i8, MVT::v2i32);
+setOperationAction(ISD::XOR,MVT::v4i16, Promote);
+AddPromotedToType (ISD::XOR,MVT::v4i16, MVT::v2i32);
+setOperationAction(ISD::XOR,MVT::v2i32, Legal);
+
setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32);
setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.20
llvm/lib/Target/X86/X86InstrMMX.td:1.21
--- llvm/lib/Target/X86/X86InstrMMX.td:1.20 Thu Mar 15 16:24:36 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Fri Mar 16 04:44:46 2007
@@ -63,9 +63,7 @@
(bitconvert
(loadv2i32 addr:$src2)]>;
}
-}
-let isTwoAddress = 1 in {
multiclass MMXI_binop_rm_int opc, string OpcodeStr, Intrinsic IntId,
bit Commutable = 0> {
def rr : MMXI;
}
+
+ // MMXI_binop_rm_v2i32 - Simple MMX binary operator whose type is v2i32.
+ //
+ // FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen
knew
+ // to collapse (bitconvert VT to VT) into its operand.
+ //
+ multiclass MMXI_binop_rm_v2i32 opc, string OpcodeStr, SDNode OpNode,
+ bit Commutable = 0> {
+def rr : MMXI {
+ let isCommutable = Commutable;
+}
+def rm : MMXI;
+ }
}
//===--===//
@@ -116,6 +132,24 @@
defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw" , int_x86_mmx_pmulh_w , 1>;
defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
+// Logical Instructions
+defm MMX_PAND : MMXI_binop_rm_v2i32<0xDB, "pand", and, 1>;
+defm MMX_POR : MMXI_binop_rm_v2i32<0xEB, "por" , or, 1>;
+defm MMX_PXOR : MMXI_binop_rm_v2i32<0xEF, "pxor", xor, 1>;
+
+let isTwoAddress = 1 in {
+ def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
+ (ops VR64:$dst, VR64:$src1, VR64:$src2),
+ "pandn {$src2, $dst|$dst, $src2}",
+ [(set VR64:$dst, (v2i32 (and (vnot VR64:$src1),
+ VR64:$src2)))]>;
+ def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
+ (ops VR64:$dst, VR64:$src1, i64mem:$src2),
+ "pandn {$src2, $dst|$dst, $src2}",
+ [(set VR64:$dst, (v2i32 (and (vnot VR64:$src1),
+ (load addr:$src2]>;
+}
+
// Move Instructions
def MOVD64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
"movd {$src, $dst|$dst, $src}", []>;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrMMX.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.369 -> 1.370
X86InstrMMX.td updated: 1.19 -> 1.20
---
Log message:
Multiplication support for MMX.
---
Diffs of the changes: (+9 -1)
X86ISelLowering.cpp |3 +++
X86InstrMMX.td |7 ++-
2 files changed, 9 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.369
llvm/lib/Target/X86/X86ISelLowering.cpp:1.370
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.369 Wed Mar 14 17:11:11 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Mar 15 16:24:36 2007
@@ -325,6 +325,9 @@
setOperationAction(ISD::SUB,MVT::v4i16, Legal);
setOperationAction(ISD::SUB,MVT::v2i32, Legal);
+setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
+setOperationAction(ISD::MUL,MVT::v4i16, Legal);
+
setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32);
setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.19
llvm/lib/Target/X86/X86InstrMMX.td:1.20
--- llvm/lib/Target/X86/X86InstrMMX.td:1.19 Sat Mar 10 03:57:05 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Thu Mar 15 16:24:36 2007
@@ -111,6 +111,11 @@
defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
+defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>;
+
+defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw" , int_x86_mmx_pmulh_w , 1>;
+defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
+
// Move Instructions
def MOVD64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
"movd {$src, $dst|$dst, $src}", []>;
@@ -139,7 +144,7 @@
"cvtpi2pd {$src, $dst|$dst, $src}", []>;
def CVTTPS2PIrr: I<0x2C, MRMSrcReg, (ops VR64:$dst, VR128:$src),
"cvttps2pi {$src, $dst|$dst, $src}", []>, TB,
- Requires<[HasSSE2]>;
+ Requires<[HasMMX]>;
def CVTTPS2PIrm: I<0x2C, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
"cvttps2pi {$src, $dst|$dst, $src}", []>, TB,
Requires<[HasMMX]>;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.368 -> 1.369
---
Log message:
Under X86-64 large code model, do not emit 32-bit pc relative calls.
---
Diffs of the changes: (+5 -3)
X86ISelLowering.cpp |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.368
llvm/lib/Target/X86/X86ISelLowering.cpp:1.369
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.368 Mon Mar 12 18:28:50 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Mar 14 17:11:11 2007
@@ -1304,11 +1304,13 @@
if (GlobalAddressSDNode *G = dyn_cast(Callee)) {
// We should use extra load for direct calls to dllimported functions in
// non-JIT mode.
-if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
-getTargetMachine(), true))
+if (getTargetMachine().getCodeModel() != CodeModel::Large
+ && !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
+ getTargetMachine(), true))
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
} else if (ExternalSymbolSDNode *S = dyn_cast(Callee))
-Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
+if (getTargetMachine().getCodeModel() != CodeModel::Large)
+ Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
// Returns a chain & a flag for retval copy to use.
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.367 -> 1.368
X86ISelLowering.h updated: 1.91 -> 1.92
---
Log message:
More flexible TargetLowering LSR hooks for testing whether an immediate is
a legal target address immediate or scale.
---
Diffs of the changes: (+33 -16)
X86ISelLowering.cpp | 34 +-
X86ISelLowering.h | 15 ---
2 files changed, 33 insertions(+), 16 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.367
llvm/lib/Target/X86/X86ISelLowering.cpp:1.368
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.367 Mon Mar 12 17:58:52 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Mar 12 18:28:50 2007
@@ -64,16 +64,6 @@
setUseUnderscoreLongJmp(true);
}
- // Add legal addressing mode scale values.
- addLegalAddressScale(8);
- addLegalAddressScale(4);
- addLegalAddressScale(2);
- // Enter the ones which require both scale + index last. These are more
- // expensive.
- addLegalAddressScale(9);
- addLegalAddressScale(5);
- addLegalAddressScale(3);
-
// Set up the register classes.
addRegisterClass(MVT::i8, X86::GR8RegisterClass);
addRegisterClass(MVT::i16, X86::GR16RegisterClass);
@@ -4016,13 +4006,16 @@
}
}
-/// isLegalAddressImmediate - Return true if the integer value or
-/// GlobalValue can be used as the offset of the target addressing mode.
-bool X86TargetLowering::isLegalAddressImmediate(int64_t V) const {
+/// isLegalAddressImmediate - Return true if the integer value can be used
+/// as the offset of the target addressing mode for load / store of the
+/// given type.
+bool X86TargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty)
const{
// X86 allows a sign-extended 32-bit immediate field.
return (V > -(1LL << 32) && V < (1LL << 32)-1);
}
+/// isLegalAddressImmediate - Return true if the GlobalValue can be used as
+/// the offset of the target addressing mode.
bool X86TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
// In 64-bit mode, GV is 64-bit so it won't fit in the 32-bit displacement
// field unless we are in small code model.
@@ -4033,6 +4026,21 @@
return (!Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false));
}
+/// isLegalAddressScale - Return true if the integer value can be used as the
+/// scale of the target addressing mode for load / store of the given type.
+bool X86TargetLowering::isLegalAddressScale(int64_t S, const Type *Ty) const {
+ switch (S) {
+ default:
+return false;
+ case 2: case 4: case 8:
+return true;
+ // FIXME: These require both scale + index last and thus more expensive.
+ // How to tell LSR to try for 2, 4, 8 first?
+ case 3: case 5: case 9:
+return true;
+ }
+}
+
/// isShuffleMaskLegal - Targets can use this to indicate that they only
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.91
llvm/lib/Target/X86/X86ISelLowering.h:1.92
--- llvm/lib/Target/X86/X86ISelLowering.h:1.91 Fri Mar 2 17:16:35 2007
+++ llvm/lib/Target/X86/X86ISelLowering.h Mon Mar 12 18:28:50 2007
@@ -335,11 +335,20 @@
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
-/// isLegalAddressImmediate - Return true if the integer value or
-/// GlobalValue can be used as the offset of the target addressing mode.
-virtual bool isLegalAddressImmediate(int64_t V) const;
+/// isLegalAddressImmediate - Return true if the integer value can be used
+/// as the offset of the target addressing mode for load / store of the
+/// given type.
+virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
+
+/// isLegalAddressImmediate - Return true if the GlobalValue can be used as
+/// the offset of the target addressing mode.
virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
+/// isLegalAddressScale - Return true if the integer value can be used as
+/// the scale of the target addressing mode for load / store of the given
+/// type.
+virtual bool isLegalAddressScale(int64_t S, const Type *Ty) const;
+
/// isShuffleMaskLegal - Targets can use this to indicate that they only
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.366 -> 1.367 --- Log message: Stupid bug: SSE2 supports v2i64 add / sub. --- Diffs of the changes: (+2 -0) X86ISelLowering.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.366 llvm/lib/Target/X86/X86ISelLowering.cpp:1.367 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.366 Sat Mar 10 03:57:05 2007 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Mar 12 17:58:52 2007 @@ -370,9 +370,11 @@ setOperationAction(ISD::ADD,MVT::v16i8, Legal); setOperationAction(ISD::ADD,MVT::v8i16, Legal); setOperationAction(ISD::ADD,MVT::v4i32, Legal); +setOperationAction(ISD::ADD,MVT::v2i64, Legal); setOperationAction(ISD::SUB,MVT::v16i8, Legal); setOperationAction(ISD::SUB,MVT::v8i16, Legal); setOperationAction(ISD::SUB,MVT::v4i32, Legal); +setOperationAction(ISD::SUB,MVT::v2i64, Legal); setOperationAction(ISD::MUL,MVT::v8i16, Legal); setOperationAction(ISD::FADD, MVT::v2f64, Legal); setOperationAction(ISD::FSUB, MVT::v2f64, Legal); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrMMX.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.365 -> 1.366
X86InstrMMX.td updated: 1.18 -> 1.19
---
Log message:
Adding more arithmetic operators to MMX. This is an almost exact copy of
the addition. Please let me know if you have suggestions.
---
Diffs of the changes: (+14 -0)
X86ISelLowering.cpp |4
X86InstrMMX.td | 10 ++
2 files changed, 14 insertions(+)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.365
llvm/lib/Target/X86/X86ISelLowering.cpp:1.366
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.365 Thu Mar 8 16:09:11 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sat Mar 10 03:57:05 2007
@@ -331,6 +331,10 @@
setOperationAction(ISD::ADD,MVT::v4i16, Legal);
setOperationAction(ISD::ADD,MVT::v2i32, Legal);
+setOperationAction(ISD::SUB,MVT::v8i8, Legal);
+setOperationAction(ISD::SUB,MVT::v4i16, Legal);
+setOperationAction(ISD::SUB,MVT::v2i32, Legal);
+
setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32);
setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.18
llvm/lib/Target/X86/X86InstrMMX.td:1.19
--- llvm/lib/Target/X86/X86InstrMMX.td:1.18 Thu Mar 8 16:09:11 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Sat Mar 10 03:57:05 2007
@@ -101,6 +101,16 @@
defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
+defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>;
+defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>;
+defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>;
+
+defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
+defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
+
+defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
+defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
+
// Move Instructions
def MOVD64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
"movd {$src, $dst|$dst, $src}", []>;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrInfo.cpp X86InstrMMX.td X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.364 -> 1.365
X86InstrInfo.cpp updated: 1.77 -> 1.78
X86InstrMMX.td updated: 1.17 -> 1.18
X86RegisterInfo.cpp updated: 1.206 -> 1.207
---
Log message:
Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that
moves, loads, etc. are recognized.
---
Diffs of the changes: (+73 -10)
X86ISelLowering.cpp | 23 ++-
X86InstrInfo.cpp|7 ++-
X86InstrMMX.td | 47 +++
X86RegisterInfo.cpp |6 ++
4 files changed, 73 insertions(+), 10 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.364
llvm/lib/Target/X86/X86ISelLowering.cpp:1.365
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.364 Wed Mar 7 10:25:09 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Mar 8 16:09:11 2007
@@ -326,15 +326,20 @@
addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
// FIXME: add MMX packed arithmetics
-setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
-AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32);
-setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
-AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v2i32);
-setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
-
-setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
-setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
-setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
+
+setOperationAction(ISD::ADD,MVT::v8i8, Legal);
+setOperationAction(ISD::ADD,MVT::v4i16, Legal);
+setOperationAction(ISD::ADD,MVT::v2i32, Legal);
+
+setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
+AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32);
+setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
+AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v2i32);
+setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
+
+setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
+setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
}
if (Subtarget->hasSSE1()) {
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.77
llvm/lib/Target/X86/X86InstrInfo.cpp:1.78
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.77 Fri Jan 26 08:34:51 2007
+++ llvm/lib/Target/X86/X86InstrInfo.cppThu Mar 8 16:09:11 2007
@@ -37,7 +37,8 @@
oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
- oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr) {
+ oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
+ oc == X86::MOVD64rr || oc == X86::MOVQ64rr) {
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
@@ -64,6 +65,8 @@
case X86::MOVSDrm:
case X86::MOVAPSrm:
case X86::MOVAPDrm:
+ case X86::MOVD64rm:
+ case X86::MOVQ64rm:
if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
MI->getOperand(2).getImmedValue() == 1 &&
@@ -92,6 +95,8 @@
case X86::MOVSDmr:
case X86::MOVAPSmr:
case X86::MOVAPDmr:
+ case X86::MOVD64mr:
+ case X86::MOVQ64mr:
if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
MI->getOperand(1).getImmedValue() == 1 &&
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.17
llvm/lib/Target/X86/X86InstrMMX.td:1.18
--- llvm/lib/Target/X86/X86InstrMMX.td:1.17 Wed Mar 7 12:23:09 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Thu Mar 8 16:09:11 2007
@@ -45,6 +45,42 @@
def loadv2i32 : PatFrag<(ops node:$ptr), (v2i32 (load node:$ptr))>;
//===--===//
+// MMX Multiclasses
+//===--===//
+
+let isTwoAddress = 1 in {
+ // MMXI_binop_rm - Simple MMX binary operator.
+ multiclass MMXI_binop_rm opc, string OpcodeStr, SDNode OpNode,
+ ValueType OpVT, bit Commutable = 0> {
+def rr : MMXI {
+ let isCommutable = Commutable;
+}
+def rm : MMXI;
+ }
+}
+
+let isTwoAddress = 1 in {
+ multiclass MMXI_binop_rm_int opc, string OpcodeStr, Intrinsic IntId,
+ bit Commutable = 0> {
+def rr : MMXI {
+ let isCommutable = Commutable;
+}
+def rm : MMXI;
+ }
+}
+
+//===--
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.363 -> 1.364 --- Log message: Refactoring of formal parameter flags. Enable properly use of zext/sext/aext stuff. --- Diffs of the changes: (+2 -12) X86ISelLowering.cpp | 14 ++ 1 files changed, 2 insertions(+), 12 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.363 llvm/lib/Target/X86/X86ISelLowering.cpp:1.364 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.363 Tue Mar 6 23:43:18 2007 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Mar 7 10:25:09 2007 @@ -29,7 +29,6 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/CodeGen/SSARegMap.h" #include "llvm/Support/MathExtras.h" #include "llvm/Target/TargetOptions.h" @@ -677,7 +676,7 @@ // If this is an sret function, the return should pop the hidden pointer. if (NumArgs && (cast(Op.getOperand(3))->getValue() & - SDISelParamFlags::StructReturn)) + ISD::ParamFlags::StructReturn)) BytesToPopOnReturn = 4; BytesCallerReserves = StackSize; @@ -751,7 +750,7 @@ // If the first argument is an sret pointer, remember it. bool isSRet = NumOps && (cast(Op.getOperand(6))->getValue() & - SDISelParamFlags::StructReturn); + ISD::ParamFlags::StructReturn); if (!MemOpChains.empty()) Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, @@ -3408,16 +3407,10 @@ TargetLowering::ArgListEntry Entry; Entry.Node = Op.getOperand(1); Entry.Ty = IntPtrTy; -Entry.isSigned = false; -Entry.isInReg = false; -Entry.isSRet = false; Args.push_back(Entry); // Extend the unsigned i8 argument to be an int value for the call. Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2)); Entry.Ty = IntPtrTy; -Entry.isSigned = false; -Entry.isInReg = false; -Entry.isSRet = false; Args.push_back(Entry); Entry.Node = Op.getOperand(3); Args.push_back(Entry); @@ -3568,9 +3561,6 @@ TargetLowering::ArgListTy Args; TargetLowering::ArgListEntry Entry; Entry.Ty = getTargetData()->getIntPtrType(); -Entry.isSigned = false; -Entry.isInReg = false; -Entry.isSRet = false; Entry.Node = Op.getOperand(1); Args.push_back(Entry); Entry.Node = Op.getOperand(2); Args.push_back(Entry); Entry.Node = Op.getOperand(3); Args.push_back(Entry); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrMMX.td
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.362 -> 1.363 X86InstrMMX.td updated: 1.15 -> 1.16 --- Log message: Properly support v8i8 and v4i16 types. It now converts them to v2i32 for load and stores. --- Diffs of the changes: (+20 -6) X86ISelLowering.cpp |7 +-- X86InstrMMX.td | 19 +++ 2 files changed, 20 insertions(+), 6 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.362 llvm/lib/Target/X86/X86ISelLowering.cpp:1.363 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.362 Tue Mar 6 12:53:42 2007 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Mar 6 23:43:18 2007 @@ -327,9 +327,12 @@ addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); // FIXME: add MMX packed arithmetics -setOperationAction(ISD::LOAD, MVT::v8i8, Legal); -setOperationAction(ISD::LOAD, MVT::v4i16, Legal); +setOperationAction(ISD::LOAD, MVT::v8i8, Promote); +AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32); +setOperationAction(ISD::LOAD, MVT::v4i16, Promote); +AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v2i32); setOperationAction(ISD::LOAD, MVT::v2i32, Legal); + setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand); Index: llvm/lib/Target/X86/X86InstrMMX.td diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.15 llvm/lib/Target/X86/X86InstrMMX.td:1.16 --- llvm/lib/Target/X86/X86InstrMMX.td:1.15 Tue Mar 6 12:53:42 2007 +++ llvm/lib/Target/X86/X86InstrMMX.td Tue Mar 6 23:43:18 2007 @@ -1,4 +1,4 @@ -//- X86InstrMMX.td - Describe the X86 Instruction Set ---*- C++ -*-===// +//- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===// // // The LLVM Compiler Infrastructure // @@ -33,14 +33,17 @@ [(set VR64:$dst, (v8i8 (undef)))]>, Requires<[HasMMX]>; -def : Pat<(v8i8 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>; -def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>; -def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>; +// 64-bit vector undef's. +def : Pat<(v8i8 (undef)), (IMPLICIT_DEF_VR64)>; +def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>; +def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>; //===--===// // MMX Pattern Fragments //===--===// +def loadv8i8 : PatFrag<(ops node:$ptr), (v8i8 (load node:$ptr))>; +def loadv4i16 : PatFrag<(ops node:$ptr), (v4i16 (load node:$ptr))>; def loadv2i32 : PatFrag<(ops node:$ptr), (v2i32 (load node:$ptr))>; //===--===// @@ -120,3 +123,11 @@ (MOVQ64mr addr:$dst, VR64:$src)>; def : Pat<(store (v4i16 VR64:$src), addr:$dst), (MOVQ64mr addr:$dst, VR64:$src)>; + +// Bit convert. +def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>; +def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>; +def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>; +def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>; +def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>; +def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrMMX.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.361 -> 1.362
X86InstrMMX.td updated: 1.14 -> 1.15
---
Log message:
Add LOAD/STORE support for MMX.
---
Diffs of the changes: (+47 -22)
X86ISelLowering.cpp |3 ++
X86InstrMMX.td | 66 ++--
2 files changed, 47 insertions(+), 22 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.361
llvm/lib/Target/X86/X86ISelLowering.cpp:1.362
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.361 Tue Mar 6 02:12:33 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Mar 6 12:53:42 2007
@@ -327,6 +327,9 @@
addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
// FIXME: add MMX packed arithmetics
+setOperationAction(ISD::LOAD, MVT::v8i8, Legal);
+setOperationAction(ISD::LOAD, MVT::v4i16, Legal);
+setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.14
llvm/lib/Target/X86/X86InstrMMX.td:1.15
--- llvm/lib/Target/X86/X86InstrMMX.td:1.14 Mon Mar 5 17:09:45 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Tue Mar 6 12:53:42 2007
@@ -13,7 +13,10 @@
//
//===--===//
+//===--===//
// Instruction templates
+//===--===//
+
// MMXI - MMX instructions with TB prefix.
// MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
@@ -30,33 +33,42 @@
[(set VR64:$dst, (v8i8 (undef)))]>,
Requires<[HasMMX]>;
+def : Pat<(v8i8 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>;
def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>;
def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>;
-// EMMS
-def EMMS : I<0x77, RawFrm, (ops), "emms", [(int_x86_mmx_emms)]>, TB,
- Requires<[HasMMX]>;
+//===--===//
+// MMX Pattern Fragments
+//===--===//
-// Move Instructions
-def MOVD64rr : I<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
- "movd {$src, $dst|$dst, $src}", []>, TB,
- Requires<[HasMMX]>;
-def MOVD64rm : I<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
- "movd {$src, $dst|$dst, $src}", []>, TB,
- Requires<[HasMMX]>;
-def MOVD64mr : I<0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
- "movd {$src, $dst|$dst, $src}", []>, TB,
- Requires<[HasMMX]>;
+def loadv2i32 : PatFrag<(ops node:$ptr), (v2i32 (load node:$ptr))>;
-def MOVQ64rr : I<0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src),
- "movq {$src, $dst|$dst, $src}", []>, TB,
- Requires<[HasMMX]>;
-def MOVQ64rm : I<0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
- "movq {$src, $dst|$dst, $src}", []>, TB,
- Requires<[HasMMX]>;
-def MOVQ64mr : I<0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
- "movq {$src, $dst|$dst, $src}", []>, TB,
- Requires<[HasMMX]>;
+//===--===//
+// MMX EMMS Instruction
+//===--===//
+
+def EMMS : MMXI<0x77, RawFrm, (ops), "emms", [(int_x86_mmx_emms)]>;
+
+//===--===//
+// MMX Scalar Instructions
+//===--===//
+
+// Move Instructions
+def MOVD64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
+"movd {$src, $dst|$dst, $src}", []>;
+def MOVD64rm : MMXI<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
+"movd {$src, $dst|$dst, $src}", []>;
+def MOVD64mr : MMXI<0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
+"movd {$src, $dst|$dst, $src}", []>;
+
+def MOVQ64rr : MMXI<0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src),
+"movq {$src, $dst|$dst, $src}", []>;
+def MOVQ64rm : MMXI<0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
+"movq {$src, $dst|$dst, $src}",
+[(set VR64:$dst, (loadv2i32 addr:$src))]>;
+def MOVQ64mr : MMXI<0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
+"movq {$src, $dst|$dst, $src}",
+[(store (v2i32 VR64:$src), addr:$
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.360 -> 1.361
---
Log message:
Use new SDIselParamAttr enumeration. This removes "magick" constants
from formal attributes' flags processing.
---
Diffs of the changes: (+8 -3)
X86ISelLowering.cpp | 11 ---
1 files changed, 8 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.360
llvm/lib/Target/X86/X86ISelLowering.cpp:1.361
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.360 Fri Mar 2 17:16:35 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Mar 6 02:12:33 2007
@@ -29,6 +29,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetOptions.h"
@@ -665,10 +666,12 @@
BytesToPopOnReturn = StackSize;// Callee pops everything..
BytesCallerReserves = 0;
} else {
-BytesToPopOnReturn = 0; // Callee pops hidden struct pointer.
+BytesToPopOnReturn = 0; // Callee pops nothing.
// If this is an sret function, the return should pop the hidden pointer.
-if (NumArgs && (cast(Op.getOperand(3))->getValue() & 4))
+if (NumArgs &&
+(cast(Op.getOperand(3))->getValue() &
+ SDISelParamFlags::StructReturn))
BytesToPopOnReturn = 4;
BytesCallerReserves = StackSize;
@@ -740,7 +743,9 @@
}
// If the first argument is an sret pointer, remember it.
- bool isSRet = NumOps
&&(cast(Op.getOperand(6))->getValue()&4);
+ bool isSRet = NumOps &&
+(cast(Op.getOperand(6))->getValue() &
+ SDISelParamFlags::StructReturn);
if (!MemOpChains.empty())
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.359 -> 1.360
X86ISelLowering.h updated: 1.90 -> 1.91
---
Log message:
X86-64 VACOPY needs custom expansion. va_list is a struct { i32, i32, i8*, i8*
}.
---
Diffs of the changes: (+34 -3)
X86ISelLowering.cpp | 36 +---
X86ISelLowering.h |1 +
2 files changed, 34 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.359
llvm/lib/Target/X86/X86ISelLowering.cpp:1.360
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.359 Fri Mar 2 15:50:27 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Mar 2 17:16:35 2007
@@ -236,11 +236,13 @@
// VASTART needs to be custom lowered to use the VarArgsFrameIndex
setOperationAction(ISD::VASTART , MVT::Other, Custom);
-
- // Use the default implementation.
setOperationAction(ISD::VAARG , MVT::Other, Expand);
- setOperationAction(ISD::VACOPY, MVT::Other, Expand);
setOperationAction(ISD::VAEND , MVT::Other, Expand);
+ if (Subtarget->is64Bit())
+setOperationAction(ISD::VACOPY , MVT::Other, Custom);
+ else
+setOperationAction(ISD::VACOPY , MVT::Other, Expand);
+
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
if (Subtarget->is64Bit())
@@ -3761,6 +3763,33 @@
return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
}
+SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) {
+ // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
+ SDOperand Chain = Op.getOperand(0);
+ SDOperand DstPtr = Op.getOperand(1);
+ SDOperand SrcPtr = Op.getOperand(2);
+ SrcValueSDNode *DstSV = cast(Op.getOperand(3));
+ SrcValueSDNode *SrcSV = cast(Op.getOperand(4));
+
+ SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr,
+ SrcSV->getValue(), SrcSV->getOffset());
+ Chain = SrcPtr.getValue(1);
+ for (unsigned i = 0; i < 3; ++i) {
+SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr,
+SrcSV->getValue(), SrcSV->getOffset());
+Chain = Val.getValue(1);
+Chain = DAG.getStore(Chain, Val, DstPtr,
+ DstSV->getValue(), DstSV->getOffset());
+if (i == 2)
+ break;
+SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr,
+ DAG.getConstant(8, getPointerTy()));
+DstPtr = DAG.getNode(ISD::ADD, getPointerTy(), DstPtr,
+ DAG.getConstant(8, getPointerTy()));
+ }
+ return Chain;
+}
+
SDOperand
X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
unsigned IntNo = cast(Op.getOperand(0))->getValue();
@@ -3925,6 +3954,7 @@
case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
case ISD::READCYCLECOUNTER: return LowerREADCYCLCECOUNTER(Op, DAG);
case ISD::VASTART:return LowerVASTART(Op, DAG);
+ case ISD::VACOPY: return LowerVACOPY(Op, DAG);
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.90
llvm/lib/Target/X86/X86ISelLowering.h:1.91
--- llvm/lib/Target/X86/X86ISelLowering.h:1.90 Wed Feb 28 00:05:16 2007
+++ llvm/lib/Target/X86/X86ISelLowering.h Fri Mar 2 17:16:35 2007
@@ -405,6 +405,7 @@
SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG);
+SDOperand LowerVACOPY(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG);
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.358 -> 1.359
---
Log message:
Simplify things
---
Diffs of the changes: (+2 -8)
X86ISelLowering.cpp | 10 ++
1 files changed, 2 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.358
llvm/lib/Target/X86/X86ISelLowering.cpp:1.359
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.358 Thu Mar 1 23:12:29 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Mar 2 15:50:27 2007
@@ -30,16 +30,11 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SSARegMap.h"
-#include "llvm/Support/CommandLine.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/StringExtras.h"
using namespace llvm;
-static cl::opt FastCallAlignStack("x86-fastcc-align-stack", cl::Hidden,
- cl::desc("Align stack to 8-byte boundary for fastcall function"),
-cl::init(false));
-
X86TargetLowering::X86TargetLowering(TargetMachine &TM)
: TargetLowering(TM) {
Subtarget = &TM.getSubtarget();
@@ -909,7 +904,7 @@
unsigned StackSize = CCInfo.getNextStackOffset();
- if (FastCallAlignStack) {
+ if (!Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows()) {
// Make sure the instruction takes 8n+4 bytes to make sure the start of the
// arguments and the arguments after the retaddr has been pushed are
aligned.
if ((StackSize & 7) == 0)
@@ -943,7 +938,7 @@
// Get a count of how many bytes are to be pushed on the stack.
unsigned NumBytes = CCInfo.getNextStackOffset();
- if (FastCallAlignStack) {
+ if (!Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows()) {
// Make sure the instruction takes 8n+4 bytes to make sure the start of the
// arguments and the arguments after the retaddr has been pushed are
aligned.
if ((NumBytes & 7) == 0)
@@ -951,7 +946,6 @@
}
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
getPointerTy()));
-
SmallVector, 8> RegsToPass;
SmallVector MemOpChains;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.357 -> 1.358 --- Log message: argument lowering should copy from the vreg shadows of live-in arguments passed in registers, not directly from the pregs themselves. --- Diffs of the changes: (+7 -7) X86ISelLowering.cpp | 14 +++--- 1 files changed, 7 insertions(+), 7 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.357 llvm/lib/Target/X86/X86ISelLowering.cpp:1.358 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.357 Thu Mar 1 10:29:22 2007 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Mar 1 23:12:29 2007 @@ -627,8 +627,8 @@ RC = X86::VR128RegisterClass; } - SDOperand ArgValue = DAG.getCopyFromReg(Root, VA.getLocReg(), RegVT); - AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); + unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); + SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); // If this is an 8 or 16-bit value, it is really passed promoted to 32 // bits. Insert an assert[sz]ext to capture this, then truncate to the @@ -877,8 +877,8 @@ RC = X86::VR128RegisterClass; } - SDOperand ArgValue = DAG.getCopyFromReg(Root, VA.getLocReg(), RegVT); - AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); + unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); + SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); // If this is an 8 or 16-bit value, it is really passed promoted to 32 // bits. Insert an assert[sz]ext to capture this, then truncate to the @@ -1116,9 +1116,9 @@ assert(MVT::isVector(RegVT)); RC = X86::VR128RegisterClass; } - - SDOperand ArgValue = DAG.getCopyFromReg(Root, VA.getLocReg(), RegVT); - AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); + + unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); + SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); // If this is an 8 or 16-bit value, it is really passed promoted to 32 // bits. Insert an assert[sz]ext to capture this, then truncate to the ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.355 -> 1.356
---
Log message:
remove dead option
---
Diffs of the changes: (+0 -4)
X86ISelLowering.cpp |4
1 files changed, 4 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.355
llvm/lib/Target/X86/X86ISelLowering.cpp:1.356
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.355 Wed Feb 28 01:09:55 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Feb 28 12:39:53 2007
@@ -32,13 +32,9 @@
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Support/CommandLine.h"
#include "llvm/ADT/StringExtras.h"
using namespace llvm;
-// FIXME: temporary.
-static cl::opt EnableFastCC("enable-x86-fastcc", cl::Hidden,
- cl::desc("Enable fastcc on X86"));
X86TargetLowering::X86TargetLowering(TargetMachine &TM)
: TargetLowering(TM) {
Subtarget = &TM.getSubtarget();
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.353 -> 1.354
---
Log message:
make use of helper functions in CCState for analyzing formals and calls.
---
Diffs of the changes: (+15 -49)
X86ISelLowering.cpp | 64
1 files changed, 15 insertions(+), 49 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.353
llvm/lib/Target/X86/X86ISelLowering.cpp:1.354
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.353 Wed Feb 28 00:26:33 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Feb 28 01:00:42 2007
@@ -609,17 +609,12 @@
SDOperand Root = Op.getOperand(0);
bool isVarArg = cast(Op.getOperand(2))->getValue() != 0;
+ // Assign locations to all of the incoming arguments.
SmallVector ArgLocs;
CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
ArgLocs);
-
- for (unsigned i = 0; i != NumArgs; ++i) {
-MVT::ValueType ArgVT = Op.getValue(i).getValueType();
-unsigned ArgFlags = cast(Op.getOperand(3+i))->getValue();
-if (CC_X86_32_C(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo))
- assert(0 && "Unhandled argument type!");
- }
-
+ CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_32_C);
+
SmallVector ArgValues;
unsigned LastVal = ~0U;
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
@@ -708,15 +703,10 @@
SDOperand Callee= Op.getOperand(4);
unsigned NumOps = (Op.getNumOperands() - 5) / 2;
+ // Analyze operands of the call, assigning locations to each operand.
SmallVector ArgLocs;
CCState CCInfo(CC, getTargetMachine(), ArgLocs);
-
- for (unsigned i = 0; i != NumOps; ++i) {
-MVT::ValueType ArgVT = Op.getOperand(5+2*i).getValueType();
-unsigned ArgFlags
=cast(Op.getOperand(5+2*i+1))->getValue();
-if (CC_X86_32_C(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo))
- assert(0 && "Unhandled argument type!");
- }
+ CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_32_C);
// Get a count of how many bytes are to be pushed on the stack.
unsigned NumBytes = CCInfo.getNextStackOffset();
@@ -865,21 +855,15 @@
// reasons.
SDOperand
X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
- unsigned NumArgs = Op.Val->getNumValues()-1;
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
SDOperand Root = Op.getOperand(0);
+ // Assign locations to all of the incoming arguments.
SmallVector ArgLocs;
CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
ArgLocs);
-
- for (unsigned i = 0; i != NumArgs; ++i) {
-MVT::ValueType ArgVT = Op.getValue(i).getValueType();
-unsigned ArgFlags = cast(Op.getOperand(3+i))->getValue();
-if (CC_X86_32_FastCall(i, ArgVT, ArgVT, CCValAssign::Full,
ArgFlags,CCInfo))
- assert(0 && "Unhandled argument type!");
- }
+ CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_32_FastCall);
SmallVector ArgValues;
unsigned LastVal = ~0U;
@@ -956,18 +940,11 @@
SDOperand Chain = Op.getOperand(0);
bool isTailCall = cast(Op.getOperand(3))->getValue() !=
0;
SDOperand Callee= Op.getOperand(4);
- unsigned NumOps = (Op.getNumOperands() - 5) / 2;
-
+ // Analyze operands of the call, assigning locations to each operand.
SmallVector ArgLocs;
CCState CCInfo(CC, getTargetMachine(), ArgLocs);
-
- for (unsigned i = 0; i != NumOps; ++i) {
-MVT::ValueType ArgVT = Op.getOperand(5+2*i).getValueType();
-unsigned ArgFlags
=cast(Op.getOperand(5+2*i+1))->getValue();
-if (CC_X86_32_C(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo))
- assert(0 && "Unhandled argument type!");
- }
+ CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_32_FastCall);
// Get a count of how many bytes are to be pushed on the stack.
unsigned NumBytes = CCInfo.getNextStackOffset();
@@ -1098,7 +1075,6 @@
SDOperand
X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
- unsigned NumArgs = Op.Val->getNumValues() - 1;
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
SDOperand Root = Op.getOperand(0);
@@ -1112,16 +1088,12 @@
X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
};
+
+ // Assign locations to all of the incoming arguments.
SmallVector ArgLocs;
CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
ArgLocs);
-
- for (unsigned i = 0; i != NumArgs; ++i) {
-MVT::ValueType ArgVT = Op.getValue(i).getValueType();
-unsigned ArgFlags = cast(Op.getOperand(3+i))->getValue();
-if (CC_X86_64_C(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo))
- assert(0 && "Unhandled argument type!");
- }
+ CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_64_C);
SmallVector ArgValues;
unsigned LastVal = ~0U;
@@ -1243,17 +1215,11 @@
bo
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.354 -> 1.355
---
Log message:
use high-level functions in CCState
---
Diffs of the changes: (+6 -15)
X86ISelLowering.cpp | 21 ++---
1 files changed, 6 insertions(+), 15 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.354
llvm/lib/Target/X86/X86ISelLowering.cpp:1.355
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.354 Wed Feb 28 01:00:42 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Feb 28 01:09:55 2007
@@ -438,15 +438,8 @@
SmallVector RVLocs;
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
CCState CCInfo(CC, getTargetMachine(), RVLocs);
+ CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
- // Determine which register each value should be copied into.
- for (unsigned i = 0; i != Op.getNumOperands() / 2; ++i) {
-MVT::ValueType VT = Op.getOperand(i*2+1).getValueType();
-if (RetCC_X86(i, VT, VT, CCValAssign::Full,
- cast(Op.getOperand(i*2+2))->getValue(),
- CCInfo))
- assert(0 && "Unhandled result type!");
- }
// If this is the first return lowered for this function, add the regs to the
// liveout set for the function.
@@ -521,16 +514,14 @@
SDNode *X86TargetLowering::
LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
unsigned CallingConv, SelectionDAG &DAG) {
- SmallVector ResultVals;
-
+
+ // Assign locations to each value returned by this call.
SmallVector RVLocs;
CCState CCInfo(CallingConv, getTargetMachine(), RVLocs);
+ CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
+
- for (unsigned i = 0, e = TheCall->getNumValues() - 1; i != e; ++i) {
-MVT::ValueType VT = TheCall->getValueType(i);
-if (RetCC_X86(i, VT, VT, CCValAssign::Full, 0, CCInfo))
- assert(0 && "Unhandled result type!");
- }
+ SmallVector ResultVals;
// Copy all of the result registers out of their specified physreg.
if (RVLocs.size() != 1 || RVLocs[0].getLocReg() != X86::ST0) {
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.352 -> 1.353
---
Log message:
switch LowerFastCCCallTo over to using the new fastcall description.
---
Diffs of the changes: (+40 -97)
X86ISelLowering.cpp | 137 +++-
1 files changed, 40 insertions(+), 97 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.352
llvm/lib/Target/X86/X86ISelLowering.cpp:1.353
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.352 Wed Feb 28 00:21:19 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Feb 28 00:26:33 2007
@@ -958,58 +958,19 @@
SDOperand Callee= Op.getOperand(4);
unsigned NumOps = (Op.getNumOperands() - 5) / 2;
- // Count how many bytes are to be pushed on the stack.
- unsigned NumBytes = 0;
-
- // Keep track of the number of integer regs passed so far. This can be
either
- // 0 (neither EAX/ECX or EDX used), 1 (EAX/ECX is used) or 2 (EAX/ECX and EDX
- // are both used).
- unsigned NumIntRegs = 0;
- unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
-
- static const unsigned GPRArgRegs[][2] = {
-{ X86::CL, X86::DL },
-{ X86::CX, X86::DX },
-{ X86::ECX, X86::EDX }
- };
- static const unsigned XMMArgRegs[] = {
-X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
- };
-
+
+ SmallVector ArgLocs;
+ CCState CCInfo(CC, getTargetMachine(), ArgLocs);
+
for (unsigned i = 0; i != NumOps; ++i) {
-SDOperand Arg = Op.getOperand(5+2*i);
-
-switch (Arg.getValueType()) {
-default: assert(0 && "Unknown value type!");
-case MVT::i8:
-case MVT::i16:
-case MVT::i32:
- if (NumIntRegs < 2) {
- ++NumIntRegs;
- break;
- } // Fall through
-case MVT::f32:
- NumBytes += 4;
- break;
-case MVT::f64:
- NumBytes += 8;
- break;
-case MVT::v16i8:
-case MVT::v8i16:
-case MVT::v4i32:
-case MVT::v2i64:
-case MVT::v4f32:
-case MVT::v2f64:
- if (NumXMMRegs < 4)
-NumXMMRegs++;
- else {
-// XMM arguments have to be aligned on 16-byte boundary.
-NumBytes = ((NumBytes + 15) / 16) * 16;
-NumBytes += 16;
- }
- break;
-}
+MVT::ValueType ArgVT = Op.getOperand(5+2*i).getValueType();
+unsigned ArgFlags
=cast(Op.getOperand(5+2*i+1))->getValue();
+if (CC_X86_32_C(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo))
+ assert(0 && "Unhandled argument type!");
}
+
+ // Get a count of how many bytes are to be pushed on the stack.
+ unsigned NumBytes = CCInfo.getNextStackOffset();
// Make sure the instruction takes 8n+4 bytes to make sure the start of the
// arguments and the arguments after the retaddr has been pushed are aligned.
@@ -1018,59 +979,41 @@
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
getPointerTy()));
- // Arguments go on the stack in reverse order, as specified by the ABI.
- unsigned ArgOffset = 0;
- NumIntRegs = 0;
+
SmallVector, 8> RegsToPass;
SmallVector MemOpChains;
- SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy());
- for (unsigned i = 0; i != NumOps; ++i) {
-SDOperand Arg = Op.getOperand(5+2*i);
-
-switch (Arg.getValueType()) {
-default: assert(0 && "Unexpected ValueType for argument!");
-case MVT::i8:
-case MVT::i16:
-case MVT::i32:
- if (NumIntRegs < 2) {
-unsigned RegToUse =
- GPRArgRegs[Arg.getValueType()-MVT::i8][NumIntRegs];
-RegsToPass.push_back(std::make_pair(RegToUse, Arg));
-++NumIntRegs;
+
+ SDOperand StackPtr;
+
+ // Walk the register/memloc assignments, inserting copies/loads.
+ for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
+CCValAssign &VA = ArgLocs[i];
+SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
+
+// Promote the value if needed.
+switch (VA.getLocInfo()) {
+ default: assert(0 && "Unknown loc info!");
+ case CCValAssign::Full: break;
+ case CCValAssign::SExt:
+Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
+break;
+ case CCValAssign::ZExt:
+Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
+break;
+ case CCValAssign::AExt:
+Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
break;
- } // Fall through
-case MVT::f32: {
- SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
- PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
- MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
- ArgOffset += 4;
- break;
}
-case MVT::f64: {
- SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
+
+if (VA.isRegLoc()) {
+ RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
+} else {
+ assert(VA.isMemLoc());
+ if (StackPtr.Val == 0)
+StackPtr = DAG.getRegister(getStackPtrRe
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.351 -> 1.352
---
Log message:
switch LowerFastCCArguments over to using the autogenerated Fastcall
description.
---
Diffs of the changes: (+59 -174)
X86ISelLowering.cpp | 233 +---
1 files changed, 59 insertions(+), 174 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.351
llvm/lib/Target/X86/X86ISelLowering.cpp:1.352
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.351 Wed Feb 28 00:10:12 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Feb 28 00:21:19 2007
@@ -601,66 +601,6 @@
return VReg;
}
-/// HowToPassArgument - Returns how an formal argument of the specified type
-/// should be passed. If it is through stack, returns the size of the stack
-/// slot; if it is through integer or XMM register, returns the number of
-/// integer or XMM registers are needed.
-static void
-HowToPassCallArgument(MVT::ValueType ObjectVT,
- bool ArgInReg,
- unsigned NumIntRegs, unsigned NumXMMRegs,
- unsigned MaxNumIntRegs,
- unsigned &ObjSize, unsigned &ObjIntRegs,
- unsigned &ObjXMMRegs) {
- ObjSize = 0;
- ObjIntRegs = 0;
- ObjXMMRegs = 0;
-
- if (MaxNumIntRegs>3) {
-// We don't have too much registers on ia32! :)
-MaxNumIntRegs = 3;
- }
-
- switch (ObjectVT) {
- default: assert(0 && "Unhandled argument type!");
- case MVT::i8:
- if (ArgInReg && (NumIntRegs < MaxNumIntRegs))
- ObjIntRegs = 1;
- else
- ObjSize = 1;
- break;
- case MVT::i16:
- if (ArgInReg && (NumIntRegs < MaxNumIntRegs))
- ObjIntRegs = 1;
- else
- ObjSize = 2;
- break;
- case MVT::i32:
- if (ArgInReg && (NumIntRegs < MaxNumIntRegs))
- ObjIntRegs = 1;
- else
- ObjSize = 4;
- break;
- case MVT::f32:
-ObjSize = 4;
-break;
- case MVT::f64:
-ObjSize = 8;
-break;
- case MVT::v16i8:
- case MVT::v8i16:
- case MVT::v4i32:
- case MVT::v2i64:
- case MVT::v4f32:
- case MVT::v2f64:
-if (NumXMMRegs < 4)
- ObjXMMRegs = 1;
-else
- ObjSize = 16;
-break;
- }
-}
-
SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG,
bool isStdCall) {
unsigned NumArgs = Op.Val->getNumValues() - 1;
@@ -929,138 +869,83 @@
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
SDOperand Root = Op.getOperand(0);
- SmallVector ArgValues;
-
- // Add DAG nodes to load the arguments... On entry to a function the stack
- // frame looks like this:
- //
- // [ESP] -- return address
- // [ESP + 4] -- first nonreg argument (leftmost lexically)
- // [ESP + 8] -- second nonreg argument, if 1st argument is <= 4 bytes in size
- //...
- unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
-
- // Keep track of the number of integer regs passed so far. This can be
either
- // 0 (neither EAX/ECX or EDX used), 1 (EAX/ECX is used) or 2 (EAX/ECX and EDX
- // are both used).
- unsigned NumIntRegs = 0;
- unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
-
- static const unsigned XMMArgRegs[] = {
-X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
- };
-
- static const unsigned GPRArgRegs[][2] = {
-{ X86::CL, X86::DL },
-{ X86::CX, X86::DX },
-{ X86::ECX, X86::EDX }
- };
- static const TargetRegisterClass* GPRClasses[3] = {
-X86::GR8RegisterClass, X86::GR16RegisterClass, X86::GR32RegisterClass
- };
-
- for (unsigned i = 0; i < NumArgs; ++i) {
-MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
-unsigned ArgIncrement = 4;
-unsigned ObjSize = 0;
-unsigned ObjXMMRegs = 0;
-unsigned ObjIntRegs = 0;
-unsigned Reg = 0;
-SDOperand ArgValue;
-
-HowToPassCallArgument(ObjectVT,
- true, // Use as much registers as possible
- NumIntRegs, NumXMMRegs, 2,
- ObjSize, ObjIntRegs, ObjXMMRegs);
+ SmallVector ArgLocs;
+ CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
+ ArgLocs);
+
+ for (unsigned i = 0; i != NumArgs; ++i) {
+MVT::ValueType ArgVT = Op.getValue(i).getValueType();
+unsigned ArgFlags = cast(Op.getOperand(3+i))->getValue();
+if (CC_X86_32_FastCall(i, ArgVT, ArgVT, CCValAssign::Full,
ArgFlags,CCInfo))
+ assert(0 && "Unhandled argument type!");
+ }
+
+ SmallVector ArgValues;
+ unsigned LastVal = ~0U;
+ for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
+CCValAssign &VA = ArgLocs[i];
+// TODO: If an arg is passed in two places (e.g. reg and stack), skip later
+// places.
+assert(VA.getValNo() != LastVal &&
+ "Don't support value assigned to multiple locs yet");
+LastVal = VA.getValNo();
-if (Obj
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.350 -> 1.351
---
Log message:
rearrange code
---
Diffs of the changes: (+441 -449)
X86ISelLowering.cpp | 890 +---
1 files changed, 441 insertions(+), 449 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.350
llvm/lib/Target/X86/X86ISelLowering.cpp:1.351
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.350 Wed Feb 28 00:05:16 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Feb 28 00:10:12 2007
@@ -912,211 +912,283 @@
//===--===//
-// X86-64 C Calling Convention implementation
+// FastCall Calling Convention implementation
//===--===//
-
-
-
+//
+// The X86 'fastcall' calling convention passes up to two integer arguments in
+// registers (an appropriate portion of ECX/EDX), passes arguments in C order,
+// and requires that the callee pop its arguments off the stack (allowing
proper
+// tail calls), and has the same return value conventions as C calling convs.
+//
+// This calling convention always arranges for the callee pop value to be 8n+4
+// bytes, which is needed for tail recursion elimination and stack alignment
+// reasons.
SDOperand
-X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
- unsigned NumArgs = Op.Val->getNumValues() - 1;
+X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
+ unsigned NumArgs = Op.Val->getNumValues()-1;
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
SDOperand Root = Op.getOperand(0);
- bool isVarArg = cast(Op.getOperand(2))->getValue() != 0;
+ SmallVector ArgValues;
+
+ // Add DAG nodes to load the arguments... On entry to a function the stack
+ // frame looks like this:
+ //
+ // [ESP] -- return address
+ // [ESP + 4] -- first nonreg argument (leftmost lexically)
+ // [ESP + 8] -- second nonreg argument, if 1st argument is <= 4 bytes in size
+ //...
+ unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
+
+ // Keep track of the number of integer regs passed so far. This can be
either
+ // 0 (neither EAX/ECX or EDX used), 1 (EAX/ECX is used) or 2 (EAX/ECX and EDX
+ // are both used).
+ unsigned NumIntRegs = 0;
+ unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
- static const unsigned GPR64ArgRegs[] = {
-X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
- };
static const unsigned XMMArgRegs[] = {
-X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
-X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
+X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
};
- SmallVector ArgLocs;
- CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
- ArgLocs);
-
- for (unsigned i = 0; i != NumArgs; ++i) {
-MVT::ValueType ArgVT = Op.getValue(i).getValueType();
-unsigned ArgFlags = cast(Op.getOperand(3+i))->getValue();
-if (CC_X86_64_C(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo))
- assert(0 && "Unhandled argument type!");
- }
-
- SmallVector ArgValues;
- unsigned LastVal = ~0U;
- for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
-CCValAssign &VA = ArgLocs[i];
-// TODO: If an arg is passed in two places (e.g. reg and stack), skip later
-// places.
-assert(VA.getValNo() != LastVal &&
- "Don't support value assigned to multiple locs yet");
-LastVal = VA.getValNo();
+ static const unsigned GPRArgRegs[][2] = {
+{ X86::CL, X86::DL },
+{ X86::CX, X86::DX },
+{ X86::ECX, X86::EDX }
+ };
+
+ static const TargetRegisterClass* GPRClasses[3] = {
+X86::GR8RegisterClass, X86::GR16RegisterClass, X86::GR32RegisterClass
+ };
+
+ for (unsigned i = 0; i < NumArgs; ++i) {
+MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
+unsigned ArgIncrement = 4;
+unsigned ObjSize = 0;
+unsigned ObjXMMRegs = 0;
+unsigned ObjIntRegs = 0;
+unsigned Reg = 0;
+SDOperand ArgValue;
+
+HowToPassCallArgument(ObjectVT,
+ true, // Use as much registers as possible
+ NumIntRegs, NumXMMRegs, 2,
+ ObjSize, ObjIntRegs, ObjXMMRegs);
-if (VA.isRegLoc()) {
- MVT::ValueType RegVT = VA.getLocVT();
- TargetRegisterClass *RC;
- if (RegVT == MVT::i32)
-RC = X86::GR32RegisterClass;
- else if (RegVT == MVT::i64)
-RC = X86::GR64RegisterClass;
- else if (RegVT == MVT::f32)
-RC = X86::FR32RegisterClass;
- else if (RegVT == MVT::f64)
-RC = X86::FR64RegisterClass;
- else {
-assert(MVT::isVector(RegVT));
-RC = X86::VR128RegisterClass;
+if (ObjSize > 4)
+ ArgIncrement
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.349 -> 1.350
X86ISelLowering.h updated: 1.89 -> 1.90
---
Log message:
remove fastcc (not fastcall) support
---
Diffs of the changes: (+26 -58)
X86ISelLowering.cpp | 65
X86ISelLowering.h | 19 ---
2 files changed, 26 insertions(+), 58 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.349
llvm/lib/Target/X86/X86ISelLowering.cpp:1.350
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.349 Tue Feb 27 23:46:49 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Feb 28 00:05:16 2007
@@ -1223,8 +1223,7 @@
// bytes, which is needed for tail recursion elimination and stack alignment
// reasons.
SDOperand
-X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG,
-bool isFastCall) {
+X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
unsigned NumArgs = Op.Val->getNumValues()-1;
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
@@ -1250,17 +1249,16 @@
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
};
- static const unsigned GPRArgRegs[][2][2] = {
-{{ X86::AL, X86::DL }, { X86::CL, X86::DL }},
-{{ X86::AX, X86::DX }, { X86::CX, X86::DX }},
-{{ X86::EAX, X86::EDX }, { X86::ECX, X86::EDX }}
+ static const unsigned GPRArgRegs[][2] = {
+{ X86::CL, X86::DL },
+{ X86::CX, X86::DX },
+{ X86::ECX, X86::EDX }
};
static const TargetRegisterClass* GPRClasses[3] = {
X86::GR8RegisterClass, X86::GR16RegisterClass, X86::GR32RegisterClass
};
- unsigned GPRInd = (isFastCall ? 1 : 0);
for (unsigned i = 0; i < NumArgs; ++i) {
MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
unsigned ArgIncrement = 4;
@@ -1272,8 +1270,7 @@
HowToPassCallArgument(ObjectVT,
true, // Use as much registers as possible
- NumIntRegs, NumXMMRegs,
- (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS),
+ NumIntRegs, NumXMMRegs, 2,
ObjSize, ObjIntRegs, ObjXMMRegs);
if (ObjSize > 4)
@@ -1285,7 +1282,7 @@
case MVT::i8:
case MVT::i16:
case MVT::i32: {
-unsigned RegToUse = GPRArgRegs[ObjectVT-MVT::i8][GPRInd][NumIntRegs];
+unsigned RegToUse = GPRArgRegs[ObjectVT-MVT::i8][NumIntRegs];
Reg = AddLiveIn(MF, RegToUse, GPRClasses[ObjectVT-MVT::i8]);
ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
break;
@@ -1296,7 +1293,6 @@
case MVT::v2i64:
case MVT::v4f32:
case MVT::v2f64: {
-assert(!isFastCall && "Unhandled argument type!");
Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass);
ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
break;
@@ -1360,7 +1356,6 @@
case MVT::v2i64:
case MVT::v4f32:
case MVT::v2f64:
-assert(!isFastCall && "Unknown result type");
MF.addLiveOut(X86::XMM0);
break;
}
@@ -1386,17 +1381,15 @@
unsigned NumIntRegs = 0;
unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
- static const unsigned GPRArgRegs[][2][2] = {
-{{ X86::AL, X86::DL }, { X86::CL, X86::DL }},
-{{ X86::AX, X86::DX }, { X86::CX, X86::DX }},
-{{ X86::EAX, X86::EDX }, { X86::ECX, X86::EDX }}
+ static const unsigned GPRArgRegs[][2] = {
+{ X86::CL, X86::DL },
+{ X86::CX, X86::DX },
+{ X86::ECX, X86::EDX }
};
static const unsigned XMMArgRegs[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
};
- bool isFastCall = CC == CallingConv::X86_FastCall;
- unsigned GPRInd = isFastCall ? 1 : 0;
for (unsigned i = 0; i != NumOps; ++i) {
SDOperand Arg = Op.getOperand(5+2*i);
@@ -1404,12 +1397,10 @@
default: assert(0 && "Unknown value type!");
case MVT::i8:
case MVT::i16:
-case MVT::i32: {
- unsigned MaxNumIntRegs = (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS);
- if (NumIntRegs < MaxNumIntRegs) {
+case MVT::i32:
+ if (NumIntRegs < 2) {
++NumIntRegs;
break;
- }
} // Fall through
case MVT::f32:
NumBytes += 4;
@@ -1423,7 +1414,6 @@
case MVT::v2i64:
case MVT::v4f32:
case MVT::v2f64:
- assert(!isFastCall && "Unknown value type!");
if (NumXMMRegs < 4)
NumXMMRegs++;
else {
@@ -1455,16 +1445,14 @@
default: assert(0 && "Unexpected ValueType for argument!");
case MVT::i8:
case MVT::i16:
-case MVT::i32: {
- unsigned MaxNumIntRegs = (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS);
- if (NumIntRegs < MaxNumIntRegs) {
- unsigned RegToUse =
- GPRArgRegs[Arg.getValueType()-MVT::i8][GPRInd][NumIntRegs];
- RegsToPass.push_back(std::make_pair(RegToUse,
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.348 -> 1.349
---
Log message:
switch LowerCCCArguments over to using autogenerated CC.
---
Diffs of the changes: (+62 -94)
X86ISelLowering.cpp | 156
1 files changed, 62 insertions(+), 94 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.348
llvm/lib/Target/X86/X86ISelLowering.cpp:1.349
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.348 Tue Feb 27 23:39:26 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Feb 27 23:46:49 2007
@@ -667,124 +667,92 @@
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
SDOperand Root = Op.getOperand(0);
- SmallVector ArgValues;
bool isVarArg = cast(Op.getOperand(2))->getValue() != 0;
- // Add DAG nodes to load the arguments... On entry to a function on the X86,
- // the stack frame looks like this:
- //
- // [ESP] -- return address
- // [ESP + 4] -- first argument (leftmost lexically)
- // [ESP + 8] -- second argument, if first argument is <= 4 bytes in size
- //...
- //
- unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
- unsigned NumSRetBytes= 0; // How much bytes on stack used for struct return
- unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
- unsigned NumIntRegs = 0; // Integer regs used for parameter passing
-
- static const unsigned XMMArgRegs[] = {
-X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
- };
- static const unsigned GPRArgRegs[][3] = {
-{ X86::AL, X86::DL, X86::CL },
-{ X86::AX, X86::DX, X86::CX },
-{ X86::EAX, X86::EDX, X86::ECX }
- };
- static const TargetRegisterClass* GPRClasses[3] = {
-X86::GR8RegisterClass, X86::GR16RegisterClass, X86::GR32RegisterClass
- };
+ SmallVector ArgLocs;
+ CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
+ ArgLocs);
- // Handle regparm attribute
- SmallVector ArgInRegs(NumArgs, false);
- SmallVector SRetArgs(NumArgs, false);
- if (!isVarArg) {
-for (unsigned i = 0; i(Op.getOperand(3+i))->getValue();
- ArgInRegs[i] = (Flags >> 1) & 1;
- SRetArgs[i]= (Flags >> 2) & 1;
-}
+ for (unsigned i = 0; i != NumArgs; ++i) {
+MVT::ValueType ArgVT = Op.getValue(i).getValueType();
+unsigned ArgFlags = cast(Op.getOperand(3+i))->getValue();
+if (CC_X86_32_C(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo))
+ assert(0 && "Unhandled argument type!");
}
- for (unsigned i = 0; i < NumArgs; ++i) {
-MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
-unsigned ArgIncrement = 4;
-unsigned ObjSize = 0;
-unsigned ObjXMMRegs = 0;
-unsigned ObjIntRegs = 0;
-unsigned Reg = 0;
-SDOperand ArgValue;
-
-HowToPassCallArgument(ObjectVT,
- ArgInRegs[i],
- NumIntRegs, NumXMMRegs, 3,
- ObjSize, ObjIntRegs, ObjXMMRegs);
-
-if (ObjSize > 4)
- ArgIncrement = ObjSize;
-
-if (ObjIntRegs || ObjXMMRegs) {
- switch (ObjectVT) {
- default: assert(0 && "Unhandled argument type!");
- case MVT::i8:
- case MVT::i16:
- case MVT::i32: {
- unsigned RegToUse = GPRArgRegs[ObjectVT-MVT::i8][NumIntRegs];
- Reg = AddLiveIn(MF, RegToUse, GPRClasses[ObjectVT-MVT::i8]);
- ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
- break;
- }
- case MVT::v16i8:
- case MVT::v8i16:
- case MVT::v4i32:
- case MVT::v2i64:
- case MVT::v4f32:
- case MVT::v2f64:
- assert(!isStdCall && "Unhandled argument type!");
- Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass);
- ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
- break;
+ SmallVector ArgValues;
+ unsigned LastVal = ~0U;
+ for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
+CCValAssign &VA = ArgLocs[i];
+// TODO: If an arg is passed in two places (e.g. reg and stack), skip later
+// places.
+assert(VA.getValNo() != LastVal &&
+ "Don't support value assigned to multiple locs yet");
+LastVal = VA.getValNo();
+
+if (VA.isRegLoc()) {
+ MVT::ValueType RegVT = VA.getLocVT();
+ TargetRegisterClass *RC;
+ if (RegVT == MVT::i32)
+RC = X86::GR32RegisterClass;
+ else {
+assert(MVT::isVector(RegVT));
+RC = X86::VR128RegisterClass;
}
- NumIntRegs += ObjIntRegs;
- NumXMMRegs += ObjXMMRegs;
-}
-if (ObjSize) {
- // XMM arguments have to be aligned on 16-byte boundary.
- if (ObjSize == 16)
-ArgOffset = ((ArgOffset + 15) / 16) * 16;
- // Create the SelectionDAG nodes corresponding to a load from this
- // parameter.
- int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
- SDOperand FIN = DAG.getFrameInde
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.347 -> 1.348
---
Log message:
simplify sret handling
---
Diffs of the changes: (+5 -13)
X86ISelLowering.cpp | 18 +-
1 files changed, 5 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.347
llvm/lib/Target/X86/X86ISelLowering.cpp:1.348
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.347 Tue Feb 27 23:31:48 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Feb 27 23:39:26 2007
@@ -819,7 +819,6 @@
SmallVector MemOpChains;
SDOperand StackPtr;
- unsigned NumSRetBytes = 0;
// Walk the register/memloc assignments, inserting copies/loads.
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
@@ -850,19 +849,12 @@
SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
-
- // FIXME: What is this doing?
- unsigned Flags =
-cast(Op.getOperand(5+2*VA.getValNo()+1))->getValue();
- if ((Flags >> 2) & 1)
-NumSRetBytes += 4;
}
}
- // Sanity check: we haven't seen NumSRetBytes > 4
- assert((NumSRetBytes<=4) &&
- "Too much space for struct-return pointer requested");
-
+ // If the first argument is an sret pointer, remember it.
+ bool isSRet = NumOps
&&(cast(Op.getOperand(6))->getValue()&4);
+
if (!MemOpChains.empty())
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
&MemOpChains[0], MemOpChains.size());
@@ -926,14 +918,14 @@
if (CC == CallingConv::X86_StdCall) {
if (isVarArg)
- NumBytesForCalleeToPush = NumSRetBytes;
+ NumBytesForCalleeToPush = isSRet ? 4 : 0;
else
NumBytesForCalleeToPush = NumBytes;
} else {
// If this is is a call to a struct-return function, the callee
// pops the hidden struct pointer, so we have to push it back.
// This is common for Darwin/X86, Linux & Mingw32 targets.
-NumBytesForCalleeToPush = NumSRetBytes;
+NumBytesForCalleeToPush = isSRet ? 4 : 0;
}
NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.345 -> 1.346
---
Log message:
switch return value passing and the x86-64 calling convention information
over to being autogenerated from the X86CallingConv.td file.
---
Diffs of the changes: (+9 -137)
X86ISelLowering.cpp | 146 +++-
1 files changed, 9 insertions(+), 137 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.345
llvm/lib/Target/X86/X86ISelLowering.cpp:1.346
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.345 Mon Feb 26 23:28:59 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Feb 27 22:55:35 2007
@@ -429,67 +429,7 @@
// Return Value Calling Convention Implementation
//===--===//
-/// X86_RetCC_Assign - Implement the X86 return value conventions. This
returns
-/// true if the value wasn't handled by this CC.
-static bool X86_RetCC_Assign(unsigned ValNo, MVT::ValueType ValVT,
- unsigned ArgFlags, CCState &State) {
- MVT::ValueType LocVT = ValVT;
- CCValAssign::LocInfo LocInfo = CCValAssign::Full;
-
- // If this is a 32-bit value, assign to a 32-bit register if any are
- // available.
- if (LocVT == MVT::i8) {
-static const unsigned GPR8ArgRegs[] = { X86::AL, X86::DL };
-if (unsigned Reg = State.AllocateReg(GPR8ArgRegs, 2)) {
- State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
- return false;
-}
- }
- if (LocVT == MVT::i16) {
-static const unsigned GPR16ArgRegs[] = { X86::AX, X86::DX };
-if (unsigned Reg = State.AllocateReg(GPR16ArgRegs, 2)) {
- State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
- return false;
-}
- }
- if (LocVT == MVT::i32) {
-static const unsigned GPR32ArgRegs[] = { X86::EAX, X86::EDX };
-if (unsigned Reg = State.AllocateReg(GPR32ArgRegs, 2)) {
- State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
- return false;
-}
- }
- if (LocVT == MVT::i64) {
-static const unsigned GPR64ArgRegs[] = { X86::RAX, X86::RDX };
-if (unsigned Reg = State.AllocateReg(GPR64ArgRegs, 2)) {
- State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
- return false;
-}
- }
- if (MVT::isVector(LocVT)) {
-if (unsigned Reg = State.AllocateReg(X86::XMM0)) {
- State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
- return false;
-}
- }
- if (LocVT == MVT::f32 || LocVT == MVT::f64) {
-unsigned Reg;
-if (State.getTarget().getSubtarget().is64Bit())
- Reg = X86::XMM0; // FP values in X86-64 go in XMM0.
-else if (State.getCallingConv() == CallingConv::Fast &&
- State.getTarget().getSubtarget().hasSSE2())
- Reg = X86::XMM0; // FP values in X86-32 with fastcc go in XMM0.
-else
- Reg = X86::ST0; // FP values in X86-32 go in ST0.
-
-if ((Reg = State.AllocateReg(Reg))) {
- State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
- return false;
-}
- }
-
- return true;
-}
+#include "X86GenCallingConv.inc"
/// LowerRET - Lower an ISD::RET node.
SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
@@ -501,9 +441,10 @@
// Determine which register each value should be copied into.
for (unsigned i = 0; i != Op.getNumOperands() / 2; ++i) {
-if (X86_RetCC_Assign(i, Op.getOperand(i*2+1).getValueType(),
-
cast(Op.getOperand(i*2+2))->getValue(),
- CCInfo))
+MVT::ValueType VT = Op.getOperand(i*2+1).getValueType();
+if (RetCC_X86(i, VT, VT, CCValAssign::Full,
+ cast(Op.getOperand(i*2+2))->getValue(),
+ CCInfo))
assert(0 && "Unhandled result type!");
}
@@ -586,7 +527,8 @@
CCState CCInfo(CallingConv, getTargetMachine(), RVLocs);
for (unsigned i = 0, e = TheCall->getNumValues() - 1; i != e; ++i) {
-if (X86_RetCC_Assign(i, TheCall->getValueType(i), 0, CCInfo))
+MVT::ValueType VT = TheCall->getValueType(i);
+if (RetCC_X86(i, VT, VT, CCValAssign::Full, 0, CCInfo))
assert(0 && "Unhandled result type!");
}
@@ -1081,76 +1023,6 @@
//===--===//
-/// X86_64_CCC_AssignArgument - Implement the X86-64 C Calling Convention.
This
-/// returns true if the value was not handled by this calling convention.
-static bool X86_64_CCC_AssignArgument(unsigned ValNo,
- MVT::ValueType ArgVT, unsigned ArgFlags,
- CCState &State) {
- MVT::ValueType LocVT = ArgVT;
- CCValAssign::LocInfo LocInfo = CCValAssign::Full;
-
- // Promote the integer to 32 bits. If the input type is signed use a
- // sign exten
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.344 -> 1.345
---
Log message:
switch x86-64 return value lowering over to using same mechanism as argument
lowering uses.
---
Diffs of the changes: (+88 -68)
X86ISelLowering.cpp | 156 +---
1 files changed, 88 insertions(+), 68 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.344
llvm/lib/Target/X86/X86ISelLowering.cpp:1.345
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.344 Mon Feb 26 23:13:54 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Feb 26 23:28:59 2007
@@ -429,79 +429,103 @@
// Return Value Calling Convention Implementation
//===--===//
-
-/// GetRetValueLocs - If we are returning a set of values with the specified
-/// value types, determine the set of registers each one will land in. This
-/// sets one element of the ResultRegs array for each element in the VTs array.
-static void GetRetValueLocs(const MVT::ValueType *VTs, unsigned NumVTs,
-unsigned *ResultRegs,
-const X86Subtarget *Subtarget,
-unsigned CC) {
- if (NumVTs == 0) return;
+/// X86_RetCC_Assign - Implement the X86 return value conventions. This
returns
+/// true if the value wasn't handled by this CC.
+static bool X86_RetCC_Assign(unsigned ValNo, MVT::ValueType ValVT,
+ unsigned ArgFlags, CCState &State) {
+ MVT::ValueType LocVT = ValVT;
+ CCValAssign::LocInfo LocInfo = CCValAssign::Full;
- if (NumVTs == 2) {
-ResultRegs[0] = VTs[0] == MVT::i64 ? X86::RAX : X86::EAX;
-ResultRegs[1] = VTs[1] == MVT::i64 ? X86::RDX : X86::EDX;
-return;
+ // If this is a 32-bit value, assign to a 32-bit register if any are
+ // available.
+ if (LocVT == MVT::i8) {
+static const unsigned GPR8ArgRegs[] = { X86::AL, X86::DL };
+if (unsigned Reg = State.AllocateReg(GPR8ArgRegs, 2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+}
}
-
- // Otherwise, NumVTs is 1.
- MVT::ValueType ArgVT = VTs[0];
-
- unsigned Reg;
- switch (ArgVT) {
- case MVT::i8: Reg = X86::AL; break;
- case MVT::i16: Reg = X86::AX; break;
- case MVT::i32: Reg = X86::EAX; break;
- case MVT::i64: Reg = X86::RAX; break;
- case MVT::f32:
- case MVT::f64:
-if (Subtarget->is64Bit())
+ if (LocVT == MVT::i16) {
+static const unsigned GPR16ArgRegs[] = { X86::AX, X86::DX };
+if (unsigned Reg = State.AllocateReg(GPR16ArgRegs, 2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+}
+ }
+ if (LocVT == MVT::i32) {
+static const unsigned GPR32ArgRegs[] = { X86::EAX, X86::EDX };
+if (unsigned Reg = State.AllocateReg(GPR32ArgRegs, 2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+}
+ }
+ if (LocVT == MVT::i64) {
+static const unsigned GPR64ArgRegs[] = { X86::RAX, X86::RDX };
+if (unsigned Reg = State.AllocateReg(GPR64ArgRegs, 2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+}
+ }
+ if (MVT::isVector(LocVT)) {
+if (unsigned Reg = State.AllocateReg(X86::XMM0)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+}
+ }
+ if (LocVT == MVT::f32 || LocVT == MVT::f64) {
+unsigned Reg;
+if (State.getTarget().getSubtarget().is64Bit())
Reg = X86::XMM0; // FP values in X86-64 go in XMM0.
-else if (CC == CallingConv::Fast && Subtarget->hasSSE2())
+else if (State.getCallingConv() == CallingConv::Fast &&
+ State.getTarget().getSubtarget().hasSSE2())
Reg = X86::XMM0; // FP values in X86-32 with fastcc go in XMM0.
else
Reg = X86::ST0; // FP values in X86-32 go in ST0.
-break;
- default:
-assert(MVT::isVector(ArgVT) && "Unknown return value type!");
-Reg = X86::XMM0; // Int/FP vector result -> XMM0.
-break;
+
+if ((Reg = State.AllocateReg(Reg))) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+}
}
- ResultRegs[0] = Reg;
+
+ return true;
}
-
+
/// LowerRET - Lower an ISD::RET node.
SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
- // Support up returning up to two registers.
- MVT::ValueType VTs[2];
- unsigned DestRegs[2];
- unsigned NumRegs = Op.getNumOperands() / 2;
- assert(NumRegs <= 2 && "Can only return up to two regs!");
-
- for (unsigned i = 0; i != NumRegs; ++i)
-VTs[i] = Op.getOperand(i*2+1).getValueType();
+ SmallVector RVLocs;
+ unsigned CC = DAG.g
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.343 -> 1.344
---
Log message:
Minor refactoring of CC Lowering interfaces
---
Diffs of the changes: (+24 -22)
X86ISelLowering.cpp | 46 --
1 files changed, 24 insertions(+), 22 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.343
llvm/lib/Target/X86/X86ISelLowering.cpp:1.344
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.343 Mon Feb 26 22:43:02 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Feb 26 23:13:54 2007
@@ -429,6 +429,7 @@
// Return Value Calling Convention Implementation
//===--===//
+
/// GetRetValueLocs - If we are returning a set of values with the specified
/// value types, determine the set of registers each one will land in. This
/// sets one element of the ResultRegs array for each element in the VTs array.
@@ -1060,11 +1061,11 @@
//===--===//
-/// X86_64_CCC_AssignArgument - Implement the X86-64 C Calling Convention.
-static void X86_64_CCC_AssignArgument(unsigned ValNo,
+/// X86_64_CCC_AssignArgument - Implement the X86-64 C Calling Convention.
This
+/// returns true if the value was not handled by this calling convention.
+static bool X86_64_CCC_AssignArgument(unsigned ValNo,
MVT::ValueType ArgVT, unsigned ArgFlags,
- CCState &State,
- SmallVector &Locs) {
+ CCState &State) {
MVT::ValueType LocVT = ArgVT;
CCValAssign::LocInfo LocInfo = CCValAssign::Full;
@@ -1082,8 +1083,8 @@
X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
};
if (unsigned Reg = State.AllocateReg(GPR32ArgRegs, 6)) {
- Locs.push_back(CCValAssign::getReg(ValNo, ArgVT, Reg, LocVT, LocInfo));
- return;
+ State.addLoc(CCValAssign::getReg(ValNo, ArgVT, Reg, LocVT, LocInfo));
+ return false;
}
}
@@ -1094,8 +1095,8 @@
X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
};
if (unsigned Reg = State.AllocateReg(GPR64ArgRegs, 6)) {
- Locs.push_back(CCValAssign::getReg(ValNo, ArgVT, Reg, LocVT, LocInfo));
- return;
+ State.addLoc(CCValAssign::getReg(ValNo, ArgVT, Reg, LocVT, LocInfo));
+ return false;
}
}
@@ -1107,8 +1108,8 @@
X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
};
if (unsigned Reg = State.AllocateReg(XMMArgRegs, 8)) {
- Locs.push_back(CCValAssign::getReg(ValNo, ArgVT, Reg, LocVT, LocInfo));
- return;
+ State.addLoc(CCValAssign::getReg(ValNo, ArgVT, Reg, LocVT, LocInfo));
+ return false;
}
}
@@ -1117,17 +1118,17 @@
if (LocVT == MVT::i32 || LocVT == MVT::i64 ||
LocVT == MVT::f32 || LocVT == MVT::f64) {
unsigned Offset = State.AllocateStack(8, 8);
-Locs.push_back(CCValAssign::getMem(ValNo, ArgVT, Offset, LocVT, LocInfo));
-return;
+State.addLoc(CCValAssign::getMem(ValNo, ArgVT, Offset, LocVT, LocInfo));
+return false;
}
// Vectors get 16-byte stack slots that are 16-byte aligned.
if (MVT::isVector(LocVT)) {
unsigned Offset = State.AllocateStack(16, 16);
-Locs.push_back(CCValAssign::getMem(ValNo, ArgVT, Offset, LocVT, LocInfo));
-return;
+State.addLoc(CCValAssign::getMem(ValNo, ArgVT, Offset, LocVT, LocInfo));
+return false;
}
- assert(0 && "Unknown argument type!");
+ return true;
}
@@ -1147,18 +1148,18 @@
X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
};
- SmallVector ArgValues;
-
-
- CCState CCInfo(*getTargetMachine().getRegisterInfo());
SmallVector ArgLocs;
+ CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
+ ArgLocs);
for (unsigned i = 0; i != NumArgs; ++i) {
MVT::ValueType ArgVT = Op.getValue(i).getValueType();
unsigned ArgFlags = cast(Op.getOperand(3+i))->getValue();
-X86_64_CCC_AssignArgument(i, ArgVT, ArgFlags, CCInfo, ArgLocs);
+if (X86_64_CCC_AssignArgument(i, ArgVT, ArgFlags, CCInfo))
+ assert(0 && "Unhandled argument type!");
}
+ SmallVector ArgValues;
unsigned LastVal = ~0U;
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
@@ -1280,13 +1281,14 @@
SDOperand Callee= Op.getOperand(4);
unsigned NumOps = (Op.getNumOperands() - 5) / 2;
- CCState CCInfo(*getTargetMachine().getRegisterInfo());
SmallVector ArgLocs;
+ CCState CCInfo(CC, getTargetMachine(), ArgLocs);
for (unsigned i = 0; i != NumOps; ++i) {
MVT::ValueType ArgVT = Op.getOperand(5+2*i).getValueType();
unsigned ArgFlags
=cast(Op.getOperand(5+2*i+1))->getValue();
-X86_64_CCC_AssignArgument(i, ArgVT, ArgFlags, CCInfo, ArgLocs);
+
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.342 -> 1.343
---
Log message:
move CC Lowering stuff to its own public interface
---
Diffs of the changes: (+17 -146)
X86ISelLowering.cpp | 163 +---
1 files changed, 17 insertions(+), 146 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.342
llvm/lib/Target/X86/X86ISelLowering.cpp:1.343
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.342 Mon Feb 26 22:18:15 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Feb 26 22:43:02 2007
@@ -24,6 +24,7 @@
#include "llvm/Intrinsics.h"
#include "llvm/ADT/VectorExtras.h"
#include "llvm/Analysis/ScalarEvolutionExpressions.h"
+#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -1058,140 +1059,11 @@
// X86-64 C Calling Convention implementation
//===--===//
-class CallingConvState {
- unsigned StackOffset;
- const MRegisterInfo &MRI;
- SmallVector UsedRegs;
-public:
- CallingConvState(const MRegisterInfo &mri) : MRI(mri) {
-// No stack is used.
-StackOffset = 0;
-
-UsedRegs.resize(MRI.getNumRegs());
- }
-
- unsigned getNextStackOffset() const { return StackOffset; }
-
- /// isAllocated - Return true if the specified register (or an alias) is
- /// allocated.
- bool isAllocated(unsigned Reg) const {
-return UsedRegs[Reg/32] & (1 << (Reg&31));
- }
-
- /// getFirstUnallocated - Return the first unallocated register in the set,
or
- /// NumRegs if they are all allocated.
- unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const {
-for (unsigned i = 0; i != NumRegs; ++i)
- if (!isAllocated(Regs[i]))
-return i;
-return NumRegs;
- }
-
- /// AllocateReg - Attempt to allocate one of the specified registers. If
none
- /// are available, return zero. Otherwise, return the first one available,
- /// marking it and any aliases as allocated.
- unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) {
-unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
-if (FirstUnalloc == NumRegs)
- return 0;// Didn't find the reg.
-
-// Mark the register and any aliases as allocated.
-unsigned Reg = Regs[FirstUnalloc];
-MarkAllocated(Reg);
-if (const unsigned *RegAliases = MRI.getAliasSet(Reg))
- for (; *RegAliases; ++RegAliases)
-MarkAllocated(*RegAliases);
-return Reg;
- }
-
- /// AllocateStack - Allocate a chunk of stack space with the specified size
- /// and alignment.
- unsigned AllocateStack(unsigned Size, unsigned Align) {
-assert(Align && ((Align-1) & Align) == 0); // Align is power of 2.
-StackOffset = ((StackOffset + Align-1) & ~(Align-1));
-unsigned Result = StackOffset;
-StackOffset += Size;
-return Result;
- }
-private:
- void MarkAllocated(unsigned Reg) {
-UsedRegs[Reg/32] |= 1 << (Reg&31);
- }
-};
-
-/// CCValAssign - Represent assignment of one arg/retval to a location.
-class CCValAssign {
-public:
- enum LocInfo {
-Full, // The value fills the full location.
-SExt, // The value is sign extended in the location.
-ZExt, // The value is zero extended in the location.
-AExt// The value is extended with undefined upper bits.
-// TODO: a subset of the value is in the location.
- };
-private:
- /// ValNo - This is the value number begin assigned (e.g. an argument
number).
- unsigned ValNo;
-
- /// Loc is either a stack offset or a register number.
- unsigned Loc;
-
- /// isMem - True if this is a memory loc, false if it is a register loc.
- bool isMem : 1;
-
- /// Information about how the value is assigned.
- LocInfo HTP : 7;
-
- /// ValVT - The type of the value being assigned.
- MVT::ValueType ValVT : 8;
-
- /// LocVT - The type of the location being assigned to.
- MVT::ValueType LocVT : 8;
-public:
-
- static CCValAssign getReg(unsigned ValNo, MVT::ValueType ValVT,
-unsigned RegNo, MVT::ValueType LocVT,
-LocInfo HTP) {
-CCValAssign Ret;
-Ret.ValNo = ValNo;
-Ret.Loc = RegNo;
-Ret.isMem = false;
-Ret.HTP = HTP;
-Ret.ValVT = ValVT;
-Ret.LocVT = LocVT;
-return Ret;
- }
- static CCValAssign getMem(unsigned ValNo, MVT::ValueType ValVT,
-unsigned Offset, MVT::ValueType LocVT,
-LocInfo HTP) {
-CCValAssign Ret;
-Ret.ValNo = ValNo;
-Ret.Loc = Offset;
-Ret.isMem = true;
-Ret.HTP = HTP;
-Ret.ValVT = ValVT;
-Ret.LocVT = LocVT;
-return Ret;
- }
-
- unsigned getValNo() const { return ValNo; }
- MVT::ValueType getValVT() const { return ValVT; }
-
- bool isRegLoc
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.341 -> 1.342
---
Log message:
refactor x86-64 argument lowering yet again, this time eliminating templates,
'clients', etc, and adding CCValAssign instead.
---
Diffs of the changes: (+179 -166)
X86ISelLowering.cpp | 345 ++--
1 files changed, 179 insertions(+), 166 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.341
llvm/lib/Target/X86/X86ISelLowering.cpp:1.342
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.341 Mon Feb 26 01:59:53 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Feb 26 22:18:15 2007
@@ -1061,7 +1061,7 @@
class CallingConvState {
unsigned StackOffset;
const MRegisterInfo &MRI;
- SmallVector UsedRegs;
+ SmallVector UsedRegs;
public:
CallingConvState(const MRegisterInfo &mri) : MRI(mri) {
// No stack is used.
@@ -1119,19 +1119,88 @@
}
};
+/// CCValAssign - Represent assignment of one arg/retval to a location.
+class CCValAssign {
+public:
+ enum LocInfo {
+Full, // The value fills the full location.
+SExt, // The value is sign extended in the location.
+ZExt, // The value is zero extended in the location.
+AExt// The value is extended with undefined upper bits.
+// TODO: a subset of the value is in the location.
+ };
+private:
+ /// ValNo - This is the value number begin assigned (e.g. an argument
number).
+ unsigned ValNo;
+
+ /// Loc is either a stack offset or a register number.
+ unsigned Loc;
+
+ /// isMem - True if this is a memory loc, false if it is a register loc.
+ bool isMem : 1;
+
+ /// Information about how the value is assigned.
+ LocInfo HTP : 7;
+
+ /// ValVT - The type of the value being assigned.
+ MVT::ValueType ValVT : 8;
+
+ /// LocVT - The type of the location being assigned to.
+ MVT::ValueType LocVT : 8;
+public:
+
+ static CCValAssign getReg(unsigned ValNo, MVT::ValueType ValVT,
+unsigned RegNo, MVT::ValueType LocVT,
+LocInfo HTP) {
+CCValAssign Ret;
+Ret.ValNo = ValNo;
+Ret.Loc = RegNo;
+Ret.isMem = false;
+Ret.HTP = HTP;
+Ret.ValVT = ValVT;
+Ret.LocVT = LocVT;
+return Ret;
+ }
+ static CCValAssign getMem(unsigned ValNo, MVT::ValueType ValVT,
+unsigned Offset, MVT::ValueType LocVT,
+LocInfo HTP) {
+CCValAssign Ret;
+Ret.ValNo = ValNo;
+Ret.Loc = Offset;
+Ret.isMem = true;
+Ret.HTP = HTP;
+Ret.ValVT = ValVT;
+Ret.LocVT = LocVT;
+return Ret;
+ }
+
+ unsigned getValNo() const { return ValNo; }
+ MVT::ValueType getValVT() const { return ValVT; }
+
+ bool isRegLoc() const { return !isMem; }
+ bool isMemLoc() const { return isMem; }
+
+ unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
+ unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; }
+ MVT::ValueType getLocVT() const { return LocVT; }
+
+ LocInfo getLocInfo() const { return HTP; }
+};
+
+
/// X86_64_CCC_AssignArgument - Implement the X86-64 C Calling Convention.
-template
-static void X86_64_CCC_AssignArgument(Client &C, CallingConvState &State,
+static void X86_64_CCC_AssignArgument(unsigned ValNo,
MVT::ValueType ArgVT, unsigned ArgFlags,
- DataTy Data) {
+ CallingConvState &State,
+ SmallVector &Locs) {
MVT::ValueType LocVT = ArgVT;
- unsigned ExtendType = ISD::ANY_EXTEND;
+ CCValAssign::LocInfo LocInfo = CCValAssign::Full;
// Promote the integer to 32 bits. If the input type is signed use a
// sign extend, otherwise use a zero extend.
if (ArgVT == MVT::i8 || ArgVT == MVT::i16) {
LocVT = MVT::i32;
-ExtendType = (ArgFlags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
+LocInfo = (ArgFlags & 1) ? CCValAssign::SExt : CCValAssign::ZExt;
}
// If this is a 32-bit value, assign to a 32-bit register if any are
@@ -1141,7 +1210,7 @@
X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
};
if (unsigned Reg = State.AllocateReg(GPR32ArgRegs, 6)) {
- C.AssignToReg(Data, Reg, ArgVT, LocVT, ExtendType);
+ Locs.push_back(CCValAssign::getReg(ValNo, ArgVT, Reg, LocVT, LocInfo));
return;
}
}
@@ -1153,7 +1222,7 @@
X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
};
if (unsigned Reg = State.AllocateReg(GPR64ArgRegs, 6)) {
- C.AssignToReg(Data, Reg, ArgVT, LocVT, ExtendType);
+ Locs.push_back(CCValAssign::getReg(ValNo, ArgVT, Reg, LocVT, LocInfo));
return;
}
}
@@ -1166,7 +1235,7 @@
X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
};
if (unsigned Reg = State.AllocateReg(XMMArgRegs, 8)) {
- C.AssignToReg(Data, Reg, ArgVT, LocVT, ExtendTy
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.340 -> 1.341
---
Log message:
switch to smallvector
---
Diffs of the changes: (+1 -3)
X86ISelLowering.cpp |4 +---
1 files changed, 1 insertion(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.340
llvm/lib/Target/X86/X86ISelLowering.cpp:1.341
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.340 Mon Feb 26 01:50:02 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Feb 26 01:59:53 2007
@@ -1059,17 +1059,15 @@
//===--===//
class CallingConvState {
- uint32_t UsedRegs[(X86::NUM_TARGET_REGS+31)/32];
unsigned StackOffset;
const MRegisterInfo &MRI;
+ SmallVector UsedRegs;
public:
CallingConvState(const MRegisterInfo &mri) : MRI(mri) {
// No stack is used.
StackOffset = 0;
UsedRegs.resize(MRI.getNumRegs());
-// No registers are used.
-memset(UsedRegs, 0, sizeof(UsedRegs));
}
unsigned getNextStackOffset() const { return StackOffset; }
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.339 -> 1.340
---
Log message:
initial hack at splitting the x86-64 calling convention info out from the
mechanics that process it. I'm still not happy with this, but it's a step
in the right direction.
---
Diffs of the changes: (+300 -272)
X86ISelLowering.cpp | 572 +++-
1 files changed, 300 insertions(+), 272 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.339
llvm/lib/Target/X86/X86ISelLowering.cpp:1.340
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.339 Sun Feb 25 23:21:05 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Feb 26 01:50:02 2007
@@ -833,7 +833,7 @@
// Return the new list of results.
return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
- &ArgValues[0], ArgValues.size());
+ &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
}
SDOperand X86TargetLowering::LowerallTo(SDOperand Op, SelectionDAG &DAG,
@@ -1058,63 +1058,264 @@
// X86-64 C Calling Convention implementation
//===--===//
-/// HowToPassX86_64CCCArgument - Returns how an formal argument of the
specified
-/// type should be passed. If it is through stack, returns the size of the
stack
-/// slot; if it is through integer or XMM register, returns the number of
-/// integer or XMM registers are needed.
-static void
-HowToPassX86_64CCCArgument(MVT::ValueType ObjectVT,
- unsigned NumIntRegs, unsigned NumXMMRegs,
- unsigned &ObjSize, unsigned &ObjIntRegs,
- unsigned &ObjXMMRegs) {
- ObjSize = 0;
- ObjIntRegs = 0;
- ObjXMMRegs = 0;
+class CallingConvState {
+ uint32_t UsedRegs[(X86::NUM_TARGET_REGS+31)/32];
+ unsigned StackOffset;
+ const MRegisterInfo &MRI;
+public:
+ CallingConvState(const MRegisterInfo &mri) : MRI(mri) {
+// No stack is used.
+StackOffset = 0;
+
+UsedRegs.resize(MRI.getNumRegs());
+// No registers are used.
+memset(UsedRegs, 0, sizeof(UsedRegs));
+ }
+
+ unsigned getNextStackOffset() const { return StackOffset; }
- switch (ObjectVT) {
- default: assert(0 && "Unhandled argument type!");
- case MVT::i8:
- case MVT::i16:
- case MVT::i32:
- case MVT::i64:
-if (NumIntRegs < 6)
- ObjIntRegs = 1;
-else {
- switch (ObjectVT) {
- default: break;
- case MVT::i8: ObjSize = 1; break;
- case MVT::i16: ObjSize = 2; break;
- case MVT::i32: ObjSize = 4; break;
- case MVT::i64: ObjSize = 8; break;
- }
+ /// isAllocated - Return true if the specified register (or an alias) is
+ /// allocated.
+ bool isAllocated(unsigned Reg) const {
+return UsedRegs[Reg/32] & (1 << (Reg&31));
+ }
+
+ /// getFirstUnallocated - Return the first unallocated register in the set,
or
+ /// NumRegs if they are all allocated.
+ unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const {
+for (unsigned i = 0; i != NumRegs; ++i)
+ if (!isAllocated(Regs[i]))
+return i;
+return NumRegs;
+ }
+
+ /// AllocateReg - Attempt to allocate one of the specified registers. If
none
+ /// are available, return zero. Otherwise, return the first one available,
+ /// marking it and any aliases as allocated.
+ unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) {
+unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
+if (FirstUnalloc == NumRegs)
+ return 0;// Didn't find the reg.
+
+// Mark the register and any aliases as allocated.
+unsigned Reg = Regs[FirstUnalloc];
+MarkAllocated(Reg);
+if (const unsigned *RegAliases = MRI.getAliasSet(Reg))
+ for (; *RegAliases; ++RegAliases)
+MarkAllocated(*RegAliases);
+return Reg;
+ }
+
+ /// AllocateStack - Allocate a chunk of stack space with the specified size
+ /// and alignment.
+ unsigned AllocateStack(unsigned Size, unsigned Align) {
+assert(Align && ((Align-1) & Align) == 0); // Align is power of 2.
+StackOffset = ((StackOffset + Align-1) & ~(Align-1));
+unsigned Result = StackOffset;
+StackOffset += Size;
+return Result;
+ }
+private:
+ void MarkAllocated(unsigned Reg) {
+UsedRegs[Reg/32] |= 1 << (Reg&31);
+ }
+};
+
+/// X86_64_CCC_AssignArgument - Implement the X86-64 C Calling Convention.
+template
+static void X86_64_CCC_AssignArgument(Client &C, CallingConvState &State,
+ MVT::ValueType ArgVT, unsigned ArgFlags,
+ DataTy Data) {
+ MVT::ValueType LocVT = ArgVT;
+ unsigned ExtendType = ISD::ANY_EXTEND;
+
+ // Promote the integer to 32 bits. If the input type is signed use a
+ // sign extend, otherwise use a zero extend.
+ if (ArgVT == MVT::i8 || ArgVT == MVT::i16) {
+
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.338 -> 1.339 --- Log message: the truncate must always be done, it's only the assert that is conditional. --- Diffs of the changes: (+1 -1) X86ISelLowering.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.338 llvm/lib/Target/X86/X86ISelLowering.cpp:1.339 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.338 Sun Feb 25 21:18:56 2007 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Sun Feb 25 23:21:05 2007 @@ -1200,8 +1200,8 @@ unsigned ExtOpc = (ArgFlags & 1) ? ISD::AssertSext :ISD::AssertZext; ArgValue = DAG.getNode(ExtOpc, MVT::i32, ArgValue, DAG.getValueType(ObjectVT)); -ArgValue = DAG.getNode(ISD::TRUNCATE, ObjectVT, ArgValue); } + ArgValue = DAG.getNode(ISD::TRUNCATE, ObjectVT, ArgValue); } break; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.337 -> 1.338
---
Log message:
in X86-64 CCC, i8/i16 arguments are already properly zext/sext'd on input.
Capture this so that downstream zext/sext's are optimized out. This
compiles:
int test(short X) { return (int)X; }
to:
_test:
movl %edi, %eax
ret
instead of:
_test:
movswl %di, %eax
ret
GCC produces this bizarre code:
_test:
movw%di, -12(%rsp)
movswl -12(%rsp),%eax
ret
---
Diffs of the changes: (+19 -14)
X86ISelLowering.cpp | 33 +++--
1 files changed, 19 insertions(+), 14 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.337
llvm/lib/Target/X86/X86ISelLowering.cpp:1.338
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.337 Sun Feb 25 17:10:46 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sun Feb 25 21:18:56 2007
@@ -1137,12 +1137,6 @@
unsigned NumIntRegs = 0; // Int regs used for parameter passing.
unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
- static const unsigned GPR8ArgRegs[] = {
-X86::DIL, X86::SIL, X86::DL, X86::CL, X86::R8B, X86::R9B
- };
- static const unsigned GPR16ArgRegs[] = {
-X86::DI, X86::SI, X86::DX, X86::CX, X86::R8W, X86::R9W
- };
static const unsigned GPR32ArgRegs[] = {
X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
};
@@ -1156,6 +1150,7 @@
for (unsigned i = 0; i < NumArgs; ++i) {
MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
+unsigned ArgFlags = cast(Op.getOperand(3+i))->getValue();
unsigned ArgIncrement = 8;
unsigned ObjSize = 0;
unsigned ObjIntRegs = 0;
@@ -1178,26 +1173,36 @@
case MVT::i64: {
TargetRegisterClass *RC = NULL;
switch (ObjectVT) {
-default: break;
+default: assert(0 && "Unknown integer VT!");
case MVT::i8:
- RC = X86::GR8RegisterClass;
- Reg = GPR8ArgRegs[NumIntRegs];
- break;
case MVT::i16:
- RC = X86::GR16RegisterClass;
- Reg = GPR16ArgRegs[NumIntRegs];
- break;
case MVT::i32:
RC = X86::GR32RegisterClass;
Reg = GPR32ArgRegs[NumIntRegs];
+ ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i32);
break;
case MVT::i64:
RC = X86::GR64RegisterClass;
Reg = GPR64ArgRegs[NumIntRegs];
+ ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i64);
break;
}
Reg = AddLiveIn(MF, Reg, RC);
-ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
+
+// If this is an 8 or 16-bit value, it is really passed promoted to 32
+// bits. Insert an assert[sz]ext to capture this, then truncate to the
+// right size.
+if (ObjectVT == MVT::i8 || ObjectVT == MVT::i16) {
+ // FIXME: FORMAL_ARGUMENTS can't currently distinguish between an
+ // argument with undefined high bits, so we can't insert a assertzext
+ // yet.
+ if (ArgFlags & 1) {
+unsigned ExtOpc = (ArgFlags & 1) ? ISD::AssertSext
:ISD::AssertZext;
+ArgValue = DAG.getNode(ExtOpc, MVT::i32, ArgValue,
+ DAG.getValueType(ObjectVT));
+ArgValue = DAG.getNode(ISD::TRUNCATE, ObjectVT, ArgValue);
+ }
+}
break;
}
case MVT::f32:
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.336 -> 1.337
---
Log message:
Fix an X86-64 abi bug. We now compile:
void foo(short);
void bar(unsigned short A) {
foo(A);
}
into:
_bar:
subq $8, %rsp
movswl %di, %edi
call _foo
addq $8, %rsp
ret
instead of:
_bar:
subq $8, %rsp
call _foo
addq $8, %rsp
ret
Testcase here: test/CodeGen/X86/x86-64-shortint.ll
---
Diffs of the changes: (+13 -10)
X86ISelLowering.cpp | 23 +--
1 files changed, 13 insertions(+), 10 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.336
llvm/lib/Target/X86/X86ISelLowering.cpp:1.337
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.336 Sun Feb 25 16:23:46 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sun Feb 25 17:10:46 2007
@@ -1301,12 +1301,6 @@
unsigned NumIntRegs = 0; // Int regs used for parameter passing.
unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
- static const unsigned GPR8ArgRegs[] = {
-X86::DIL, X86::SIL, X86::DL, X86::CL, X86::R8B, X86::R9B
- };
- static const unsigned GPR16ArgRegs[] = {
-X86::DI, X86::SI, X86::DX, X86::CX, X86::R8W, X86::R9W
- };
static const unsigned GPR32ArgRegs[] = {
X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
};
@@ -1366,7 +1360,16 @@
for (unsigned i = 0; i != NumOps; ++i) {
SDOperand Arg = Op.getOperand(5+2*i);
MVT::ValueType ArgVT = Arg.getValueType();
+unsigned ArgFlags
=cast(Op.getOperand(5+2*i+1))->getValue();
+if (MVT::isInteger(ArgVT) && ArgVT < MVT::i32) {
+ // Promote the integer to 32 bits. If the input type is signed use a
+ // sign extend, otherwise use a zero extend.
+ unsigned ExtOpc = (ArgFlags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
+ Arg = DAG.getNode(ExtOpc, MVT::i32, Arg);
+ ArgVT = MVT::i32;
+}
+
switch (ArgVT) {
default: assert(0 && "Unexpected ValueType for argument!");
case MVT::i8:
@@ -1376,10 +1379,10 @@
if (NumIntRegs < 6) {
unsigned Reg = 0;
switch (ArgVT) {
-default: break;
-case MVT::i8: Reg = GPR8ArgRegs[NumIntRegs]; break;
-case MVT::i16: Reg = GPR16ArgRegs[NumIntRegs]; break;
-case MVT::i32: Reg = GPR32ArgRegs[NumIntRegs]; break;
+default: assert(0 && "Unknown integer size!");
+case MVT::i32:
+ Reg = GPR32ArgRegs[NumIntRegs];
+ break;
case MVT::i64: Reg = GPR64ArgRegs[NumIntRegs]; break;
}
RegsToPass.push_back(std::make_pair(Reg, Arg));
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.335 -> 1.336 --- Log message: fix CodeGen/X86/2007-02-25-FastCCStack.ll, a regression from my patch last night: fastcc returns should only go in XMM0 if we have SSE2 or above. --- Diffs of the changes: (+1 -1) X86ISelLowering.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.335 llvm/lib/Target/X86/X86ISelLowering.cpp:1.336 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.335 Sun Feb 25 03:31:16 2007 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Sun Feb 25 16:23:46 2007 @@ -456,7 +456,7 @@ case MVT::f64: if (Subtarget->is64Bit()) Reg = X86::XMM0; // FP values in X86-64 go in XMM0. -else if (CC == CallingConv::Fast) +else if (CC == CallingConv::Fast && Subtarget->hasSSE2()) Reg = X86::XMM0; // FP values in X86-32 with fastcc go in XMM0. else Reg = X86::ST0; // FP values in X86-32 go in ST0. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.334 -> 1.335
---
Log message:
fastcc functions that return double values now return them in xmm0 on x86-32.
This implements CodeGen/X86/fp-stack-ret.ll:test[23]
---
Diffs of the changes: (+3 -1)
X86ISelLowering.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.334
llvm/lib/Target/X86/X86ISelLowering.cpp:1.335
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.334 Sun Feb 25 03:14:25 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sun Feb 25 03:31:16 2007
@@ -434,7 +434,7 @@
static void GetRetValueLocs(const MVT::ValueType *VTs, unsigned NumVTs,
unsigned *ResultRegs,
const X86Subtarget *Subtarget,
-unsigned CallingConv) {
+unsigned CC) {
if (NumVTs == 0) return;
if (NumVTs == 2) {
@@ -456,6 +456,8 @@
case MVT::f64:
if (Subtarget->is64Bit())
Reg = X86::XMM0; // FP values in X86-64 go in XMM0.
+else if (CC == CallingConv::Fast)
+ Reg = X86::XMM0; // FP values in X86-32 with fastcc go in XMM0.
else
Reg = X86::ST0; // FP values in X86-32 go in ST0.
break;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.333 -> 1.334
---
Log message:
allow vectors to be passed to stdcall/fastcall functions
---
Diffs of the changes: (+10 -18)
X86ISelLowering.cpp | 28 ++--
1 files changed, 10 insertions(+), 18 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.333
llvm/lib/Target/X86/X86ISelLowering.cpp:1.334
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.333 Sun Feb 25 03:12:39 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sun Feb 25 03:14:25 2007
@@ -645,8 +645,7 @@
unsigned NumIntRegs, unsigned NumXMMRegs,
unsigned MaxNumIntRegs,
unsigned &ObjSize, unsigned &ObjIntRegs,
- unsigned &ObjXMMRegs,
- bool AllowVectors = true) {
+ unsigned &ObjXMMRegs) {
ObjSize = 0;
ObjIntRegs = 0;
ObjXMMRegs = 0;
@@ -696,14 +695,11 @@
case MVT::v2i64:
case MVT::v4f32:
case MVT::v2f64:
- if (AllowVectors) {
- if (NumXMMRegs < 4)
- ObjXMMRegs = 1;
- else
- ObjSize = 16;
- break;
- } else
- assert(0 && "Unhandled argument type [vector]!");
+if (NumXMMRegs < 4)
+ ObjXMMRegs = 1;
+else
+ ObjSize = 16;
+break;
}
}
@@ -764,8 +760,7 @@
HowToPassCallArgument(ObjectVT,
ArgInRegs[i],
NumIntRegs, NumXMMRegs, 3,
- ObjSize, ObjIntRegs, ObjXMMRegs,
- !isStdCall);
+ ObjSize, ObjIntRegs, ObjXMMRegs);
if (ObjSize > 4)
ArgIncrement = ObjSize;
@@ -884,8 +879,7 @@
HowToPassCallArgument(Arg.getValueType(),
ArgInRegs[i],
NumIntRegs, NumXMMRegs, 3,
- ObjSize, ObjIntRegs, ObjXMMRegs,
- CC != CallingConv::X86_StdCall);
+ ObjSize, ObjIntRegs, ObjXMMRegs);
if (ObjSize > 4)
ArgIncrement = ObjSize;
@@ -918,8 +912,7 @@
HowToPassCallArgument(Arg.getValueType(),
ArgInRegs[i],
NumIntRegs, NumXMMRegs, 3,
- ObjSize, ObjIntRegs, ObjXMMRegs,
- CC != CallingConv::X86_StdCall);
+ ObjSize, ObjIntRegs, ObjXMMRegs);
if (ObjSize > 4)
ArgIncrement = ObjSize;
@@ -1574,8 +1567,7 @@
true, // Use as much registers as possible
NumIntRegs, NumXMMRegs,
(isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS),
- ObjSize, ObjIntRegs, ObjXMMRegs,
- !isFastCall);
+ ObjSize, ObjIntRegs, ObjXMMRegs);
if (ObjSize > 4)
ArgIncrement = ObjSize;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.332 -> 1.333
---
Log message:
move LowerRET into the 'Return Value Calling Convention Implementation'
section of the file.
---
Diffs of the changes: (+77 -75)
X86ISelLowering.cpp | 152 ++--
1 files changed, 77 insertions(+), 75 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.332
llvm/lib/Target/X86/X86ISelLowering.cpp:1.333
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.332 Sun Feb 25 03:10:05 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sun Feb 25 03:12:39 2007
@@ -467,6 +467,83 @@
ResultRegs[0] = Reg;
}
+/// LowerRET - Lower an ISD::RET node.
+SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
+ assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
+
+ // Support up returning up to two registers.
+ MVT::ValueType VTs[2];
+ unsigned DestRegs[2];
+ unsigned NumRegs = Op.getNumOperands() / 2;
+ assert(NumRegs <= 2 && "Can only return up to two regs!");
+
+ for (unsigned i = 0; i != NumRegs; ++i)
+VTs[i] = Op.getOperand(i*2+1).getValueType();
+
+ // Determine which register each value should be copied into.
+ GetRetValueLocs(VTs, NumRegs, DestRegs, Subtarget,
+ DAG.getMachineFunction().getFunction()->getCallingConv());
+
+ // If this is the first return lowered for this function, add the regs to the
+ // liveout set for the function.
+ if (DAG.getMachineFunction().liveout_empty()) {
+for (unsigned i = 0; i != NumRegs; ++i)
+ DAG.getMachineFunction().addLiveOut(DestRegs[i]);
+ }
+
+ SDOperand Chain = Op.getOperand(0);
+ SDOperand Flag;
+
+ // Copy the result values into the output registers.
+ if (NumRegs != 1 || DestRegs[0] != X86::ST0) {
+for (unsigned i = 0; i != NumRegs; ++i) {
+ Chain = DAG.getCopyToReg(Chain, DestRegs[i], Op.getOperand(i*2+1), Flag);
+ Flag = Chain.getValue(1);
+}
+ } else {
+// We need to handle a destination of ST0 specially, because it isn't
really
+// a register.
+SDOperand Value = Op.getOperand(1);
+
+// If this is an FP return with ScalarSSE, we need to move the value from
+// an XMM register onto the fp-stack.
+if (X86ScalarSSE) {
+ SDOperand MemLoc;
+
+ // If this is a load into a scalarsse value, don't store the loaded value
+ // back to the stack, only to reload it: just replace the scalar-sse
load.
+ if (ISD::isNON_EXTLoad(Value.Val) &&
+ (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
+Chain = Value.getOperand(0);
+MemLoc = Value.getOperand(1);
+ } else {
+// Spill the value to memory and reload it into top of stack.
+unsigned Size = MVT::getSizeInBits(VTs[0])/8;
+MachineFunction &MF = DAG.getMachineFunction();
+int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
+MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
+Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc, NULL, 0);
+ }
+ SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other);
+ SDOperand Ops[] = { Chain, MemLoc, DAG.getValueType(VTs[0]) };
+ Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
+ Chain = Value.getValue(1);
+}
+
+SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
+SDOperand Ops[] = { Chain, Value };
+Chain = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2);
+Flag = Chain.getValue(1);
+ }
+
+ SDOperand BytesToPop = DAG.getConstant(getBytesToPopOnReturn(), MVT::i16);
+ if (Flag.Val)
+return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop, Flag);
+ else
+return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop);
+}
+
+
/// LowerCallResult - Lower the result values of an ISD::CALL into the
/// appropriate copies out of appropriate physical registers. This assumes
that
/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
@@ -3808,81 +3885,6 @@
}
}
-SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
- assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
-
- // Support up returning up to two registers.
- MVT::ValueType VTs[2];
- unsigned DestRegs[2];
- unsigned NumRegs = Op.getNumOperands() / 2;
- assert(NumRegs <= 2 && "Can only return up to two regs!");
-
- for (unsigned i = 0; i != NumRegs; ++i)
-VTs[i] = Op.getOperand(i*2+1).getValueType();
-
- // Determine which register each value should be copied into.
- GetRetValueLocs(VTs, NumRegs, DestRegs, Subtarget,
- DAG.getMachineFunction().getFunction()->getCallingConv());
-
- // If this is the first return lowered for this function, add the regs to the
- // liveout set for the function.
- if (DAG.getMachineFunction().liveout_empty()) {
-for (unsigned i = 0; i !=
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.331 -> 1.332
---
Log message:
make all Lower*CallTo implementations use LowerCallResult to handle their
result value stuff. This eliminates a bunch of duplicated code and now
GetRetValueLocs is the sole place that decides where a value is returned.
---
Diffs of the changes: (+10 -153)
X86ISelLowering.cpp | 163 +++-
1 files changed, 10 insertions(+), 153 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.331
llvm/lib/Target/X86/X86ISelLowering.cpp:1.332
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.331 Sun Feb 25 03:06:15 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sun Feb 25 03:10:05 2007
@@ -1217,12 +1217,11 @@
SDOperand
X86TargetLowering::LowerX86_64allTo(SDOperand Op, SelectionDAG &DAG,
-unsigned CallingConv) {
+unsigned CC) {
SDOperand Chain = Op.getOperand(0);
bool isVarArg = cast(Op.getOperand(2))->getValue() !=
0;
bool isTailCall = cast(Op.getOperand(3))->getValue() !=
0;
SDOperand Callee= Op.getOperand(4);
- MVT::ValueType RetVT= Op.Val->getValueType(0);
unsigned NumOps = (Op.getNumOperands() - 5) / 2;
// Count how many bytes are to be pushed on the stack.
@@ -1412,65 +1411,11 @@
Ops.push_back(DAG.getConstant(0, getPointerTy()));
Ops.push_back(InFlag);
Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
- if (RetVT != MVT::Other)
-InFlag = Chain.getValue(1);
-
- SmallVector ResultVals;
- switch (RetVT) {
- default: assert(0 && "Unknown value type to return!");
- case MVT::Other:
-NodeTys = DAG.getVTList(MVT::Other);
-break;
- case MVT::i8:
-Chain = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag).getValue(1);
-ResultVals.push_back(Chain.getValue(0));
-NodeTys = DAG.getVTList(MVT::i8, MVT::Other);
-break;
- case MVT::i16:
-Chain = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag).getValue(1);
-ResultVals.push_back(Chain.getValue(0));
-NodeTys = DAG.getVTList(MVT::i16, MVT::Other);
-break;
- case MVT::i32:
-Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1);
-ResultVals.push_back(Chain.getValue(0));
-NodeTys = DAG.getVTList(MVT::i32, MVT::Other);
-break;
- case MVT::i64:
-if (Op.Val->getValueType(1) == MVT::i64) {
- // FIXME: __int128 support?
- Chain = DAG.getCopyFromReg(Chain, X86::RAX, MVT::i64,
InFlag).getValue(1);
- ResultVals.push_back(Chain.getValue(0));
- Chain = DAG.getCopyFromReg(Chain, X86::RDX, MVT::i64,
- Chain.getValue(2)).getValue(1);
- ResultVals.push_back(Chain.getValue(0));
- NodeTys = DAG.getVTList(MVT::i64, MVT::i64, MVT::Other);
-} else {
- Chain = DAG.getCopyFromReg(Chain, X86::RAX, MVT::i64,
InFlag).getValue(1);
- ResultVals.push_back(Chain.getValue(0));
- NodeTys = DAG.getVTList(MVT::i64, MVT::Other);
-}
-break;
- case MVT::f32:
- case MVT::f64:
- case MVT::v16i8:
- case MVT::v8i16:
- case MVT::v4i32:
- case MVT::v2i64:
- case MVT::v4f32:
- case MVT::v2f64:
-// FIXME: long double support?
-Chain = DAG.getCopyFromReg(Chain, X86::XMM0, RetVT, InFlag).getValue(1);
-ResultVals.push_back(Chain.getValue(0));
-NodeTys = DAG.getVTList(RetVT, MVT::Other);
-break;
- }
-
- // Merge everything together with a MERGE_VALUES node.
- ResultVals.push_back(Chain);
- SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
- &ResultVals[0], ResultVals.size());
- return Res.getValue(Op.ResNo);
+ InFlag = Chain.getValue(1);
+
+ // Handle result values, copying them out of physregs into vregs that we
+ // return.
+ return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
}
//===--===//
@@ -1654,7 +1599,6 @@
SDOperand Chain = Op.getOperand(0);
bool isTailCall = cast(Op.getOperand(3))->getValue() !=
0;
SDOperand Callee= Op.getOperand(4);
- MVT::ValueType RetVT= Op.Val->getValueType(0);
unsigned NumOps = (Op.getNumOperands() - 5) / 2;
// Count how many bytes are to be pushed on the stack.
@@ -1848,98 +1792,11 @@
Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
Ops.push_back(InFlag);
Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
- if (RetVT != MVT::Other)
-InFlag = Chain.getValue(1);
-
- SmallVector ResultVals;
- switch (RetVT) {
- default: assert(0 && "Unknown value type to return!");
- case MVT::Other:
-NodeTys = DAG.getVTList(MVT::Other);
-break;
- case MVT::i8:
-Chain = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag).getValue(1);
-ResultVals.push_back(Chain.getValue(0));
-NodeTys =
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.330 -> 1.331
X86ISelLowering.h updated: 1.87 -> 1.88
---
Log message:
pass the calling convention into Lower*CallTo, instead of using ad-hoc flags.
---
Diffs of the changes: (+19 -23)
X86ISelLowering.cpp | 34 --
X86ISelLowering.h |8 +++-
2 files changed, 19 insertions(+), 23 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.330
llvm/lib/Target/X86/X86ISelLowering.cpp:1.331
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.330 Sun Feb 25 02:59:22 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sun Feb 25 03:06:15 2007
@@ -763,7 +763,7 @@
}
SDOperand X86TargetLowering::LowerallTo(SDOperand Op, SelectionDAG &DAG,
-bool isStdCall) {
+unsigned CC) {
SDOperand Chain = Op.getOperand(0);
bool isVarArg = cast(Op.getOperand(2))->getValue() !=
0;
bool isTailCall = cast(Op.getOperand(3))->getValue() !=
0;
@@ -808,7 +808,7 @@
ArgInRegs[i],
NumIntRegs, NumXMMRegs, 3,
ObjSize, ObjIntRegs, ObjXMMRegs,
- !isStdCall);
+ CC != CallingConv::X86_StdCall);
if (ObjSize > 4)
ArgIncrement = ObjSize;
@@ -842,7 +842,7 @@
ArgInRegs[i],
NumIntRegs, NumXMMRegs, 3,
ObjSize, ObjIntRegs, ObjXMMRegs,
- !isStdCall);
+ CC != CallingConv::X86_StdCall);
if (ObjSize > 4)
ArgIncrement = ObjSize;
@@ -868,7 +868,6 @@
case MVT::v2i64:
case MVT::v4f32:
case MVT::v2f64:
- assert(!isStdCall && "Unhandled argument type!");
RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg));
break;
}
@@ -956,12 +955,11 @@
// Create the CALLSEQ_END node.
unsigned NumBytesForCalleeToPush = 0;
- if (isStdCall) {
-if (isVarArg) {
+ if (CC == CallingConv::X86_StdCall) {
+if (isVarArg)
NumBytesForCalleeToPush = NumSRetBytes;
-} else {
+else
NumBytesForCalleeToPush = NumBytes;
-}
} else {
// If this is is a call to a struct-return function, the callee
// pops the hidden struct pointer, so we have to push it back.
@@ -980,8 +978,7 @@
// Handle result values, copying them out of physregs into vregs that we
// return.
- return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CallingConv::C, DAG),
- Op.ResNo);
+ return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
}
@@ -1219,7 +1216,8 @@
}
SDOperand
-X86TargetLowering::LowerX86_64allTo(SDOperand Op, SelectionDAG &DAG) {
+X86TargetLowering::LowerX86_64allTo(SDOperand Op, SelectionDAG &DAG,
+unsigned CallingConv) {
SDOperand Chain = Op.getOperand(0);
bool isVarArg = cast(Op.getOperand(2))->getValue() !=
0;
bool isTailCall = cast(Op.getOperand(3))->getValue() !=
0;
@@ -1652,7 +1650,7 @@
}
SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
- bool isFastCall) {
+ unsigned CC) {
SDOperand Chain = Op.getOperand(0);
bool isTailCall = cast(Op.getOperand(3))->getValue() !=
0;
SDOperand Callee= Op.getOperand(4);
@@ -1677,7 +1675,8 @@
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
};
- unsigned GPRInd = (isFastCall ? 1 : 0);
+ bool isFastCall = CC == CallingConv::X86_FastCall;
+ unsigned GPRInd = isFastCall ? 1 : 0;
for (unsigned i = 0; i != NumOps; ++i) {
SDOperand Arg = Op.getOperand(5+2*i);
@@ -3935,21 +3934,20 @@
unsigned CallingConv= cast(Op.getOperand(1))->getValue();
if (Subtarget->is64Bit())
-return LowerX86_64allTo(Op, DAG);
+return LowerX86_64allTo(Op, DAG, CallingConv);
else
switch (CallingConv) {
default:
assert(0 && "Unsupported calling convention");
case CallingConv::Fast:
if (EnableFastCC)
-return LowerFastCCCallTo(Op, DAG);
+return LowerFastCCCallTo(Op, DAG, CallingConv);
// Falls through
case CallingConv::C:
- return LowerallTo(Op, DAG);
case CallingConv::X86_StdCall:
- return LowerallTo(Op, DAG, true);
+ return LowerallTo(Op, DAG, CallingConv);
case CallingConv::X86_FastCall:
- return LowerFastCCCallTo(Op, DAG, true);
+ return LowerFastCCCallTo(Op, DAG, CallingConv);
}
}
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.87
llvm/lib/Target/X86/X86ISelLowering.h:1.88
--- llvm/lib/Target/X86/X86ISelLowering.h:1.87 Sun Feb 25 02:
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.329 -> 1.330
X86ISelLowering.h updated: 1.86 -> 1.87
---
Log message:
factor a bunch of code out of LowerallTo into a new LowerCallResult
function. This function now uses GetRetValueLocs to determine *where*
the result values are located and concerns itself with *how* to pull the
values out.
---
Diffs of the changes: (+97 -100)
X86ISelLowering.cpp | 194 +---
X86ISelLowering.h |3
2 files changed, 97 insertions(+), 100 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.329
llvm/lib/Target/X86/X86ISelLowering.cpp:1.330
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.329 Sun Feb 25 02:29:00 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sun Feb 25 02:59:22 2007
@@ -446,24 +446,96 @@
// Otherwise, NumVTs is 1.
MVT::ValueType ArgVT = VTs[0];
- if (MVT::isVector(ArgVT))// Integer or FP vector result -> XMM0.
-ResultRegs[0] = X86::XMM0;
- else if (MVT::isFloatingPoint(ArgVT) && Subtarget->is64Bit())
-// FP values in X86-64 go in XMM0.
-ResultRegs[0] = X86::XMM0;
- else if (MVT::isFloatingPoint(ArgVT))
-// FP values in X86-32 go in ST0.
-ResultRegs[0] = X86::ST0;
- else {
-assert(MVT::isInteger(ArgVT) && "Unknown return value type!");
+ unsigned Reg;
+ switch (ArgVT) {
+ case MVT::i8: Reg = X86::AL; break;
+ case MVT::i16: Reg = X86::AX; break;
+ case MVT::i32: Reg = X86::EAX; break;
+ case MVT::i64: Reg = X86::RAX; break;
+ case MVT::f32:
+ case MVT::f64:
+if (Subtarget->is64Bit())
+ Reg = X86::XMM0; // FP values in X86-64 go in XMM0.
+else
+ Reg = X86::ST0; // FP values in X86-32 go in ST0.
+break;
+ default:
+assert(MVT::isVector(ArgVT) && "Unknown return value type!");
+Reg = X86::XMM0; // Int/FP vector result -> XMM0.
+break;
+ }
+ ResultRegs[0] = Reg;
+}
+
+/// LowerCallResult - Lower the result values of an ISD::CALL into the
+/// appropriate copies out of appropriate physical registers. This assumes
that
+/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
+/// being lowered. The returns a SDNode with the same number of values as the
+/// ISD::CALL.
+SDNode *X86TargetLowering::
+LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
+unsigned CallingConv, SelectionDAG &DAG) {
+ SmallVector ResultVals;
+
+ // We support returning up to two registers.
+ MVT::ValueType VTs[2];
+ unsigned DestRegs[2];
+ unsigned NumRegs = TheCall->getNumValues() - 1;
+ assert(NumRegs <= 2 && "Can only return up to two regs!");
+
+ for (unsigned i = 0; i != NumRegs; ++i)
+VTs[i] = TheCall->getValueType(i);
+
+ // Determine which register each value should be copied into.
+ GetRetValueLocs(VTs, NumRegs, DestRegs, Subtarget, CallingConv);
+
+ // Copy all of the result registers out of their specified physreg.
+ if (NumRegs != 1 || DestRegs[0] != X86::ST0) {
+for (unsigned i = 0; i != NumRegs; ++i) {
+ Chain = DAG.getCopyFromReg(Chain, DestRegs[i], VTs[i],
+ InFlag).getValue(1);
+ InFlag = Chain.getValue(2);
+ ResultVals.push_back(Chain.getValue(0));
+}
+ } else {
+// Copies from the FP stack are special, as ST0 isn't a valid register
+// before the fp stackifier runs.
-// Integer result -> EAX / RAX.
-// The C calling convention guarantees the return value has been
-// promoted to at least MVT::i32. The X86-64 ABI doesn't require the
-// value to be promoted MVT::i64. So we don't have to extend it to
-// 64-bit.
-ResultRegs[0] = (ArgVT == MVT::i64) ? X86::RAX : X86::EAX;
+// Copy ST0 into an RFP register with FP_GET_RESULT.
+SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
+SDOperand GROps[] = { Chain, InFlag };
+SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, GROps, 2);
+Chain = RetVal.getValue(1);
+InFlag = RetVal.getValue(2);
+
+// If we are using ScalarSSE, store ST(0) to the stack and reload it into
+// an XMM register.
+if (X86ScalarSSE) {
+ // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
+ // shouldn't be necessary except that RFP cannot be live across
+ // multiple blocks. When stackifier is fixed, they can be uncoupled.
+ MachineFunction &MF = DAG.getMachineFunction();
+ int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
+ SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
+ SDOperand Ops[] = {
+Chain, RetVal, StackSlot, DAG.getValueType(VTs[0]), InFlag
+ };
+ Chain = DAG.getNode(X86ISD::FST, MVT::Other, Ops, 5);
+ RetVal = DAG.getLoad(VTs[0], Chain, StackSlot, NULL, 0);
+ Chain = RetVal.getValue(1);
+}
+
+if (VTs[0] == MVT::f32 && !X86ScalarSSE)
+ // FI
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.328 -> 1.329
---
Log message:
move some code around, pass in calling conv, even though it is unused
---
Diffs of the changes: (+46 -39)
X86ISelLowering.cpp | 85
1 files changed, 46 insertions(+), 39 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.328
llvm/lib/Target/X86/X86ISelLowering.cpp:1.329
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.328 Sun Feb 25 02:15:11 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sun Feb 25 02:29:00 2007
@@ -423,6 +423,50 @@
allowUnalignedMemoryAccesses = true; // x86 supports it!
}
+
+//===--===//
+// Return Value Calling Convention Implementation
+//===--===//
+
+/// GetRetValueLocs - If we are returning a set of values with the specified
+/// value types, determine the set of registers each one will land in. This
+/// sets one element of the ResultRegs array for each element in the VTs array.
+static void GetRetValueLocs(const MVT::ValueType *VTs, unsigned NumVTs,
+unsigned *ResultRegs,
+const X86Subtarget *Subtarget,
+unsigned CallingConv) {
+ if (NumVTs == 0) return;
+
+ if (NumVTs == 2) {
+ResultRegs[0] = VTs[0] == MVT::i64 ? X86::RAX : X86::EAX;
+ResultRegs[1] = VTs[1] == MVT::i64 ? X86::RDX : X86::EDX;
+return;
+ }
+
+ // Otherwise, NumVTs is 1.
+ MVT::ValueType ArgVT = VTs[0];
+
+ if (MVT::isVector(ArgVT))// Integer or FP vector result -> XMM0.
+ResultRegs[0] = X86::XMM0;
+ else if (MVT::isFloatingPoint(ArgVT) && Subtarget->is64Bit())
+// FP values in X86-64 go in XMM0.
+ResultRegs[0] = X86::XMM0;
+ else if (MVT::isFloatingPoint(ArgVT))
+// FP values in X86-32 go in ST0.
+ResultRegs[0] = X86::ST0;
+ else {
+assert(MVT::isInteger(ArgVT) && "Unknown return value type!");
+
+// Integer result -> EAX / RAX.
+// The C calling convention guarantees the return value has been
+// promoted to at least MVT::i32. The X86-64 ABI doesn't require the
+// value to be promoted MVT::i64. So we don't have to extend it to
+// 64-bit.
+ResultRegs[0] = (ArgVT == MVT::i64) ? X86::RAX : X86::EAX;
+ }
+}
+
+
//===--===//
//C & StdCall Calling Convention implementation
//===--===//
@@ -3915,44 +3959,6 @@
}
}
-/// GetRetValueLocs - If we are returning a set of values with the specified
-/// value types, determine the set of registers each one will land in. This
-/// sets one element of the ResultRegs array for each element in the VTs array.
-static void GetRetValueLocs(const MVT::ValueType *VTs, unsigned NumVTs,
-unsigned *ResultRegs,
-const X86Subtarget *Subtarget) {
- if (NumVTs == 0) return;
-
- if (NumVTs == 2) {
-ResultRegs[0] = VTs[0] == MVT::i64 ? X86::RAX : X86::EAX;
-ResultRegs[1] = VTs[1] == MVT::i64 ? X86::RDX : X86::EDX;
-return;
- }
-
- // Otherwise, NumVTs is 1.
- MVT::ValueType ArgVT = VTs[0];
-
- if (MVT::isVector(ArgVT))// Integer or FP vector result -> XMM0.
-ResultRegs[0] = X86::XMM0;
- else if (MVT::isFloatingPoint(ArgVT) && Subtarget->is64Bit())
-// FP values in X86-64 go in XMM0.
-ResultRegs[0] = X86::XMM0;
- else if (MVT::isFloatingPoint(ArgVT))
-// FP values in X86-32 go in ST0.
-ResultRegs[0] = X86::ST0;
- else {
-assert(MVT::isInteger(ArgVT) && "Unknown return value type!");
-
-// Integer result -> EAX / RAX.
-// The C calling convention guarantees the return value has been
-// promoted to at least MVT::i32. The X86-64 ABI doesn't require the
-// value to be promoted MVT::i64. So we don't have to extend it to
-// 64-bit.
-ResultRegs[0] = (ArgVT == MVT::i64) ? X86::RAX : X86::EAX;
- }
-}
-
-
SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
@@ -3966,7 +3972,8 @@
VTs[i] = Op.getOperand(i*2+1).getValueType();
// Determine which register each value should be copied into.
- GetRetValueLocs(VTs, NumRegs, DestRegs, Subtarget);
+ GetRetValueLocs(VTs, NumRegs, DestRegs, Subtarget,
+ DAG.getMachineFunction().getFunction()->getCallingConv());
// If this is the first return lowered for this function, add the regs to the
// liveout set for the function.
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.327 -> 1.328
X86ISelLowering.h updated: 1.85 -> 1.86
---
Log message:
simplify result value lowering by splitting the selection of *where* to return
registers out from the logic of *how* to return them.
This changes X86-64 to mark EAX live out when returning a 32-bit value,
where before it marked RAX liveout.
---
Diffs of the changes: (+111 -91)
X86ISelLowering.cpp | 190
X86ISelLowering.h | 12 +--
2 files changed, 111 insertions(+), 91 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.327
llvm/lib/Target/X86/X86ISelLowering.cpp:1.328
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.327 Sun Feb 25 01:18:38 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sun Feb 25 02:15:11 2007
@@ -3915,96 +3915,116 @@
}
}
-SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
- SDOperand Copy;
+/// GetRetValueLocs - If we are returning a set of values with the specified
+/// value types, determine the set of registers each one will land in. This
+/// sets one element of the ResultRegs array for each element in the VTs array.
+static void GetRetValueLocs(const MVT::ValueType *VTs, unsigned NumVTs,
+unsigned *ResultRegs,
+const X86Subtarget *Subtarget) {
+ if (NumVTs == 0) return;
+
+ if (NumVTs == 2) {
+ResultRegs[0] = VTs[0] == MVT::i64 ? X86::RAX : X86::EAX;
+ResultRegs[1] = VTs[1] == MVT::i64 ? X86::RDX : X86::EDX;
+return;
+ }
+
+ // Otherwise, NumVTs is 1.
+ MVT::ValueType ArgVT = VTs[0];
+
+ if (MVT::isVector(ArgVT))// Integer or FP vector result -> XMM0.
+ResultRegs[0] = X86::XMM0;
+ else if (MVT::isFloatingPoint(ArgVT) && Subtarget->is64Bit())
+// FP values in X86-64 go in XMM0.
+ResultRegs[0] = X86::XMM0;
+ else if (MVT::isFloatingPoint(ArgVT))
+// FP values in X86-32 go in ST0.
+ResultRegs[0] = X86::ST0;
+ else {
+assert(MVT::isInteger(ArgVT) && "Unknown return value type!");
+
+// Integer result -> EAX / RAX.
+// The C calling convention guarantees the return value has been
+// promoted to at least MVT::i32. The X86-64 ABI doesn't require the
+// value to be promoted MVT::i64. So we don't have to extend it to
+// 64-bit.
+ResultRegs[0] = (ArgVT == MVT::i64) ? X86::RAX : X86::EAX;
+ }
+}
- switch(Op.getNumOperands()) {
-default:
- assert(0 && "Do not know how to return this many arguments!");
- abort();
-case 1:// ret void.
- return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0),
-DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
-case 3: {
- MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
-
- if (MVT::isVector(ArgVT) ||
- (Subtarget->is64Bit() && MVT::isFloatingPoint(ArgVT))) {
-// Integer or FP vector result -> XMM0.
-if (DAG.getMachineFunction().liveout_empty())
- DAG.getMachineFunction().addLiveOut(X86::XMM0);
-Copy = DAG.getCopyToReg(Op.getOperand(0), X86::XMM0, Op.getOperand(1),
-SDOperand());
- } else if (MVT::isInteger(ArgVT)) {
-// Integer result -> EAX / RAX.
-// The C calling convention guarantees the return value has been
-// promoted to at least MVT::i32. The X86-64 ABI doesn't require the
-// value to be promoted MVT::i64. So we don't have to extend it to
-// 64-bit. Return the value in EAX, but mark RAX as liveout.
-unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
-if (DAG.getMachineFunction().liveout_empty())
- DAG.getMachineFunction().addLiveOut(Reg);
-
-Reg = (ArgVT == MVT::i64) ? X86::RAX : X86::EAX;
-Copy = DAG.getCopyToReg(Op.getOperand(0), Reg, Op.getOperand(1),
-SDOperand());
- } else if (!X86ScalarSSE) {
-// FP return with fp-stack value.
-if (DAG.getMachineFunction().liveout_empty())
- DAG.getMachineFunction().addLiveOut(X86::ST0);
-
-SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
-SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) };
-Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2);
- } else {
-// FP return with ScalarSSE (return on fp-stack).
-if (DAG.getMachineFunction().liveout_empty())
- DAG.getMachineFunction().addLiveOut(X86::ST0);
-
-SDOperand MemLoc;
-SDOperand Chain = Op.getOperand(0);
-SDOperand Value = Op.getOperand(1);
-
-if (ISD::isNON_EXTLoad(Value.Val) &&
-(Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
- Chain = Value.getOperand(0);
- MemLoc = Value.getOperand(1);
-} else {
- // Spill the value to memory and relo
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.326 -> 1.327
---
Log message:
make void-return not a special case
---
Diffs of the changes: (+17 -33)
X86ISelLowering.cpp | 50 +-
1 files changed, 17 insertions(+), 33 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.326
llvm/lib/Target/X86/X86ISelLowering.cpp:1.327
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.326 Sun Feb 25 01:10:00 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sun Feb 25 01:18:38 2007
@@ -854,10 +854,7 @@
NumBytesForCalleeToPush = NumSRetBytes;
}
- if (RetVT != MVT::Other)
-NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
- else
-NodeTys = DAG.getVTList(MVT::Other);
+ NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
Ops.clear();
Ops.push_back(Chain);
Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
@@ -870,7 +867,9 @@
SmallVector ResultVals;
switch (RetVT) {
default: assert(0 && "Unknown value type to return!");
- case MVT::Other: break;
+ case MVT::Other:
+NodeTys = DAG.getVTList(MVT::Other);
+break;
case MVT::i8:
Chain = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag).getValue(1);
ResultVals.push_back(Chain.getValue(0));
@@ -939,11 +938,7 @@
}
}
- // If the function returns void, just return the chain.
- if (ResultVals.empty())
-return Chain;
-
- // Otherwise, merge everything together with a MERGE_VALUES node.
+ // Merge everything together with a MERGE_VALUES node.
ResultVals.push_back(Chain);
SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
&ResultVals[0], ResultVals.size());
@@ -1372,11 +1367,8 @@
NodeTys, &Ops[0], Ops.size());
InFlag = Chain.getValue(1);
- if (RetVT != MVT::Other)
-// Returns a flag for retval copy to use.
-NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
- else
-NodeTys = DAG.getVTList(MVT::Other);
+ // Returns a flag for retval copy to use.
+ NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
Ops.clear();
Ops.push_back(Chain);
Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
@@ -1389,7 +1381,9 @@
SmallVector ResultVals;
switch (RetVT) {
default: assert(0 && "Unknown value type to return!");
- case MVT::Other: break;
+ case MVT::Other:
+NodeTys = DAG.getVTList(MVT::Other);
+break;
case MVT::i8:
Chain = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag).getValue(1);
ResultVals.push_back(Chain.getValue(0));
@@ -1435,11 +1429,7 @@
break;
}
- // If the function returns void, just return the chain.
- if (ResultVals.empty())
-return Chain;
-
- // Otherwise, merge everything together with a MERGE_VALUES node.
+ // Merge everything together with a MERGE_VALUES node.
ResultVals.push_back(Chain);
SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
&ResultVals[0], ResultVals.size());
@@ -1812,11 +1802,8 @@
NodeTys, &Ops[0], Ops.size());
InFlag = Chain.getValue(1);
- if (RetVT != MVT::Other)
-// Returns a flag for retval copy to use.
-NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
- else
-NodeTys = DAG.getVTList(MVT::Other);
+ // Returns a flag for retval copy to use.
+ NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
Ops.clear();
Ops.push_back(Chain);
Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
@@ -1829,7 +1816,9 @@
SmallVector ResultVals;
switch (RetVT) {
default: assert(0 && "Unknown value type to return!");
- case MVT::Other: break;
+ case MVT::Other:
+NodeTys = DAG.getVTList(MVT::Other);
+break;
case MVT::i8:
Chain = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag).getValue(1);
ResultVals.push_back(Chain.getValue(0));
@@ -1908,12 +1897,7 @@
}
}
-
- // If the function returns void, just return the chain.
- if (ResultVals.empty())
-return Chain;
-
- // Otherwise, merge everything together with a MERGE_VALUES node.
+ // Merge everything together with a MERGE_VALUES node.
ResultVals.push_back(Chain);
SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
&ResultVals[0], ResultVals.size());
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.325 -> 1.326
---
Log message:
eliminate a bunch more temporary vectors from X86 lowering.
---
Diffs of the changes: (+141 -176)
X86ISelLowering.cpp | 317 +++-
1 files changed, 141 insertions(+), 176 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.325
llvm/lib/Target/X86/X86ISelLowering.cpp:1.326
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.325 Sun Feb 25 00:40:16 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sun Feb 25 01:10:00 2007
@@ -520,7 +520,7 @@
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
SDOperand Root = Op.getOperand(0);
- std::vector ArgValues;
+ SmallVector ArgValues;
bool isVarArg = cast(Op.getOperand(2))->getValue() != 0;
// Add DAG nodes to load the arguments... On entry to a function on the X86,
@@ -549,8 +549,8 @@
};
// Handle regparm attribute
- std::vector ArgInRegs(NumArgs, false);
- std::vector SRetArgs(NumArgs, false);
+ SmallVector ArgInRegs(NumArgs, false);
+ SmallVector SRetArgs(NumArgs, false);
if (!isVarArg) {
for (unsigned i = 0; i(Op.getOperand(3+i))->getValue();
@@ -642,9 +642,8 @@
MF.getInfo()->setBytesToPopOnReturn(BytesToPopOnReturn);
// Return the new list of results.
- std::vector RetVTs(Op.Val->value_begin(),
- Op.Val->value_end());
- return DAG.getNode(ISD::MERGE_VALUES, RetVTs,
&ArgValues[0],ArgValues.size());
+ return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
+ &ArgValues[0], ArgValues.size());
}
SDOperand X86TargetLowering::LowerallTo(SDOperand Op, SelectionDAG &DAG,
@@ -673,8 +672,8 @@
unsigned NumSRetBytes= 0;
// Handle regparm attribute
- std::vector ArgInRegs(NumOps, false);
- std::vector SRetArgs(NumOps, false);
+ SmallVector ArgInRegs(NumOps, false);
+ SmallVector SRetArgs(NumOps, false);
for (unsigned i = 0; i(Op.getOperand(5+2*i+1))->getValue();
@@ -714,8 +713,8 @@
unsigned ArgOffset = 0;
NumXMMRegs = 0;
NumIntRegs = 0;
- std::vector > RegsToPass;
- std::vector MemOpChains;
+ SmallVector, 8> RegsToPass;
+ SmallVector MemOpChains;
SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy());
for (unsigned i = 0; i != NumOps; ++i) {
SDOperand Arg = Op.getOperand(5+2*i);
@@ -817,7 +816,7 @@
// Returns a chain & a flag for retval copy to use.
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
- std::vector Ops;
+ SmallVector Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
@@ -868,7 +867,7 @@
if (RetVT != MVT::Other)
InFlag = Chain.getValue(1);
- std::vector ResultVals;
+ SmallVector ResultVals;
switch (RetVT) {
default: assert(0 && "Unknown value type to return!");
case MVT::Other: break;
@@ -909,15 +908,9 @@
break;
case MVT::f32:
case MVT::f64: {
-std::vector Tys;
-Tys.push_back(MVT::f64);
-Tys.push_back(MVT::Other);
-Tys.push_back(MVT::Flag);
-std::vector Ops;
-Ops.push_back(Chain);
-Ops.push_back(InFlag);
-SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys,
- &Ops[0], Ops.size());
+SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
+SDOperand GROps[] = { Chain, InFlag };
+SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, GROps, 2);
Chain = RetVal.getValue(1);
InFlag = RetVal.getValue(2);
if (X86ScalarSSE) {
@@ -927,15 +920,11 @@
MachineFunction &MF = DAG.getMachineFunction();
int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
- Tys.clear();
- Tys.push_back(MVT::Other);
- Ops.clear();
- Ops.push_back(Chain);
- Ops.push_back(RetVal);
- Ops.push_back(StackSlot);
- Ops.push_back(DAG.getValueType(RetVT));
- Ops.push_back(InFlag);
- Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
+ Tys = DAG.getVTList(MVT::Other);
+ SDOperand Ops[] = {
+Chain, RetVal, StackSlot, DAG.getValueType(RetVT), InFlag
+ };
+ Chain = DAG.getNode(X86ISD::FST, Tys, Ops, 5);
RetVal = DAG.getLoad(RetVT, Chain, StackSlot, NULL, 0);
Chain = RetVal.getValue(1);
}
@@ -1031,7 +1020,7 @@
MachineFrameInfo *MFI = MF.getFrameInfo();
SDOperand Root = Op.getOperand(0);
bool isVarArg = cast(Op.getOperand(2))->getValue() != 0;
- std::vector ArgValues;
+ SmallVector ArgValues;
// Add DAG nodes to load the arguments... On entry to a function on the X86,
// the stack frame looks like this:
@@ -1153,7 +1142,7 @@
RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
// Store the integer parameter registers.
-std::vector MemOps;
+SmallVector MemOps;
SDOperand RSFIN = DAG.ge
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.324 -> 1.325
---
Log message:
eliminate temporary vectors created during X86 lowering.
---
Diffs of the changes: (+47 -70)
X86ISelLowering.cpp | 117
1 files changed, 47 insertions(+), 70 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.324
llvm/lib/Target/X86/X86ISelLowering.cpp:1.325
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.324 Sun Feb 25 00:21:57 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sun Feb 25 00:40:16 2007
@@ -815,9 +815,8 @@
} else if (ExternalSymbolSDNode *S = dyn_cast(Callee))
Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
- std::vector NodeTys;
- NodeTys.push_back(MVT::Other); // Returns a chain
- NodeTys.push_back(MVT::Flag);// Returns a flag for retval copy to use.
+ // Returns a chain & a flag for retval copy to use.
+ SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
std::vector Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
@@ -856,10 +855,10 @@
NumBytesForCalleeToPush = NumSRetBytes;
}
- NodeTys.clear();
- NodeTys.push_back(MVT::Other); // Returns a chain
if (RetVT != MVT::Other)
-NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
+NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
+ else
+NodeTys = DAG.getVTList(MVT::Other);
Ops.clear();
Ops.push_back(Chain);
Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
@@ -870,19 +869,18 @@
InFlag = Chain.getValue(1);
std::vector ResultVals;
- NodeTys.clear();
switch (RetVT) {
default: assert(0 && "Unknown value type to return!");
case MVT::Other: break;
case MVT::i8:
Chain = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag).getValue(1);
ResultVals.push_back(Chain.getValue(0));
-NodeTys.push_back(MVT::i8);
+NodeTys = DAG.getVTList(MVT::i8, MVT::Other);
break;
case MVT::i16:
Chain = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag).getValue(1);
ResultVals.push_back(Chain.getValue(0));
-NodeTys.push_back(MVT::i16);
+NodeTys = DAG.getVTList(MVT::i16, MVT::Other);
break;
case MVT::i32:
if (Op.Val->getValueType(1) == MVT::i32) {
@@ -891,12 +889,12 @@
Chain = DAG.getCopyFromReg(Chain, X86::EDX, MVT::i32,
Chain.getValue(2)).getValue(1);
ResultVals.push_back(Chain.getValue(0));
- NodeTys.push_back(MVT::i32);
+ NodeTys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
} else {
Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32,
InFlag).getValue(1);
ResultVals.push_back(Chain.getValue(0));
+ NodeTys = DAG.getVTList(MVT::i32, MVT::Other);
}
-NodeTys.push_back(MVT::i32);
break;
case MVT::v16i8:
case MVT::v8i16:
@@ -907,7 +905,7 @@
assert(!isStdCall && "Unknown value type to return!");
Chain = DAG.getCopyFromReg(Chain, X86::XMM0, RetVT, InFlag).getValue(1);
ResultVals.push_back(Chain.getValue(0));
-NodeTys.push_back(RetVT);
+NodeTys = DAG.getVTList(RetVT, MVT::Other);
break;
case MVT::f32:
case MVT::f64: {
@@ -947,7 +945,7 @@
// operation is okay to eliminate if we allow excess FP precision.
RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
ResultVals.push_back(RetVal);
-NodeTys.push_back(RetVT);
+NodeTys = DAG.getVTList(RetVT, MVT::Other);
break;
}
}
@@ -957,7 +955,6 @@
return Chain;
// Otherwise, merge everything together with a MERGE_VALUES node.
- NodeTys.push_back(MVT::Other);
ResultVals.push_back(Chain);
SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
&ResultVals[0], ResultVals.size());
@@ -1367,9 +1364,8 @@
} else if (ExternalSymbolSDNode *S = dyn_cast(Callee))
Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
- std::vector NodeTys;
- NodeTys.push_back(MVT::Other); // Returns a chain
- NodeTys.push_back(MVT::Flag);// Returns a flag for retval copy to use.
+ // Returns a chain & a flag for retval copy to use.
+ SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
std::vector Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
@@ -1388,10 +1384,11 @@
NodeTys, &Ops[0], Ops.size());
InFlag = Chain.getValue(1);
- NodeTys.clear();
- NodeTys.push_back(MVT::Other); // Returns a chain
if (RetVT != MVT::Other)
-NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
+// Returns a flag for retval copy to use.
+NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
+ else
+NodeTys = DAG.getVTList(MVT::Other);
Ops.clear();
Ops.push_back(Chain);
Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
@@ -1402,24 +1399,23 @@
InFlag = Chain.getValue(1);
std::vector ResultVal
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.323 -> 1.324
---
Log message:
remove std::vector's in RET lowering.
---
Diffs of the changes: (+11 -22)
X86ISelLowering.cpp | 33 +++--
1 files changed, 11 insertions(+), 22 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.323
llvm/lib/Target/X86/X86ISelLowering.cpp:1.324
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.323 Thu Feb 22 08:56:36 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sun Feb 25 00:21:57 2007
@@ -4014,13 +4014,9 @@
if (DAG.getMachineFunction().liveout_empty())
DAG.getMachineFunction().addLiveOut(X86::ST0);
-std::vector Tys;
-Tys.push_back(MVT::Other);
-Tys.push_back(MVT::Flag);
-std::vector Ops;
-Ops.push_back(Op.getOperand(0));
-Ops.push_back(Op.getOperand(1));
-Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, &Ops[0], Ops.size());
+SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
+SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) };
+Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2);
} else {
// FP return with ScalarSSE (return on fp-stack).
if (DAG.getMachineFunction().liveout_empty())
@@ -4042,21 +4038,14 @@
MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc, NULL, 0);
}
-std::vector Tys;
-Tys.push_back(MVT::f64);
-Tys.push_back(MVT::Other);
-std::vector Ops;
-Ops.push_back(Chain);
-Ops.push_back(MemLoc);
-Ops.push_back(DAG.getValueType(ArgVT));
-Copy = DAG.getNode(X86ISD::FLD, Tys, &Ops[0], Ops.size());
-Tys.clear();
-Tys.push_back(MVT::Other);
-Tys.push_back(MVT::Flag);
-Ops.clear();
-Ops.push_back(Copy.getValue(1));
-Ops.push_back(Copy);
-Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, &Ops[0], Ops.size());
+SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other);
+SDOperand Ops[] = { Chain, MemLoc, DAG.getValueType(ArgVT) };
+Copy = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
+
+Tys = DAG.getVTList(MVT::Other, MVT::Flag);
+Ops[0] = Copy.getValue(1);
+Ops[1] = Copy;
+Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2);
}
break;
}
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.322 -> 1.323 --- Log message: Simplify lowering and selection of exception ops. --- Diffs of the changes: (+0 -3) X86ISelLowering.cpp |3 --- 1 files changed, 3 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.322 llvm/lib/Target/X86/X86ISelLowering.cpp:1.323 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.322 Wed Feb 21 16:54:50 2007 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Feb 22 08:56:36 2007 @@ -4675,9 +4675,6 @@ case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); - // Exception address and exception selector. Currently unimplemented. - case ISD::EXCEPTIONADDR: break; - case ISD::EHSELECTION: break; } return SDOperand(); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86RegisterInfo.cpp X86RegisterInfo.h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.321 -> 1.322
X86RegisterInfo.cpp updated: 1.203 -> 1.204
X86RegisterInfo.h updated: 1.48 -> 1.49
---
Log message:
Support to provide exception and selector registers.
---
Diffs of the changes: (+18 -0)
X86ISelLowering.cpp |4
X86RegisterInfo.cpp | 10 ++
X86RegisterInfo.h |4
3 files changed, 18 insertions(+)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.321
llvm/lib/Target/X86/X86ISelLowering.cpp:1.322
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.321 Wed Feb 21 15:18:14 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Feb 21 16:54:50 2007
@@ -4675,7 +4675,11 @@
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
+ // Exception address and exception selector. Currently unimplemented.
+ case ISD::EXCEPTIONADDR: break;
+ case ISD::EHSELECTION: break;
}
+ return SDOperand();
}
const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.203
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.204
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.203 Mon Feb 19 15:49:54 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Wed Feb 21 16:54:50 2007
@@ -1193,6 +1193,16 @@
Moves.push_back(MachineMove(0, Dst, Src));
}
+unsigned X86RegisterInfo::getEHExceptionRegister() const {
+ assert(0 && "What is the exception register");
+ return 0;
+}
+
+unsigned X86RegisterInfo::getEHHandlerRegister() const {
+ assert(0 && "What is the exception handler register");
+ return 0;
+}
+
namespace llvm {
unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
switch (VT) {
Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.48
llvm/lib/Target/X86/X86RegisterInfo.h:1.49
--- llvm/lib/Target/X86/X86RegisterInfo.h:1.48 Mon Feb 19 15:49:54 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.h Wed Feb 21 16:54:50 2007
@@ -101,6 +101,10 @@
unsigned getRARegister() const;
unsigned getFrameRegister(MachineFunction &MF) const;
void getInitialFrameState(std::vector &Moves) const;
+
+ // Exception handling queries.
+ unsigned getEHExceptionRegister() const;
+ unsigned getEHHandlerRegister() const;
};
// getX86SubSuperRegister - X86 utility function. It returns the sub or super
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.320 -> 1.321
---
Log message:
ELF / PIC requires GOT be in the EBX register during calls via PLT GOT pointer.
Add implicit uses of EBX to calls to ensure liveintervalanalysis does not treat
the GOT in EBX move as dead upon definition.
This should fix PR1207: http://llvm.org/PR1207 .
---
Diffs of the changes: (+14 -0)
X86ISelLowering.cpp | 14 ++
1 files changed, 14 insertions(+)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.320
llvm/lib/Target/X86/X86ISelLowering.cpp:1.321
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.320 Thu Feb 1 02:39:52 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Feb 21 15:18:14 2007
@@ -794,6 +794,8 @@
InFlag = Chain.getValue(1);
}
+ // ELF / PIC requires GOT in the EBX register before function calls via PLT
+ // GOT pointer.
if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
Subtarget->isPICStyleGOT()) {
Chain = DAG.getCopyToReg(Chain, X86::EBX,
@@ -825,6 +827,11 @@
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
Ops.push_back(DAG.getRegister(RegsToPass[i].first,
RegsToPass[i].second.getValueType()));
+
+ // Add an implicit use GOT pointer in EBX.
+ if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
+ Subtarget->isPICStyleGOT())
+Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
if (InFlag.Val)
Ops.push_back(InFlag);
@@ -1788,6 +1795,8 @@
} else if (ExternalSymbolSDNode *S = dyn_cast(Callee))
Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
+ // ELF / PIC requires GOT in the EBX register before function calls via PLT
+ // GOT pointer.
if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
Subtarget->isPICStyleGOT()) {
Chain = DAG.getCopyToReg(Chain, X86::EBX,
@@ -1809,6 +1818,11 @@
Ops.push_back(DAG.getRegister(RegsToPass[i].first,
RegsToPass[i].second.getValueType()));
+ // Add an implicit use GOT pointer in EBX.
+ if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
+ Subtarget->isPICStyleGOT())
+Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
+
if (InFlag.Val)
Ops.push_back(InFlag);
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.319 -> 1.320 --- Log message: Fixed uninitialized stuff inside LegalizeDAG. Fortunately, the only affected part is codegen of "memove" inside x86 backend. This fixes PR1144: http://llvm.org/PR1144 --- Diffs of the changes: (+4 -0) X86ISelLowering.cpp |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.319 llvm/lib/Target/X86/X86ISelLowering.cpp:1.320 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.319 Mon Jan 29 16:58:52 2007 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Feb 1 02:39:52 2007 @@ -777,6 +777,10 @@ } } + // Sanity check: we haven't seen NumSRetBytes > 4 + assert((NumSRetBytes<=4) && + "Too much space for struct-return pointer requested"); + if (!MemOpChains.empty()) Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOpChains[0], MemOpChains.size()); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.318 -> 1.319
X86ISelLowering.h updated: 1.84 -> 1.85
---
Log message:
Finish off bug 680: http://llvm.org/PR680 , allowing targets to custom lower
frame and return
address nodes.
---
Diffs of the changes: (+24 -23)
X86ISelLowering.cpp | 41 ++---
X86ISelLowering.h |6 ++
2 files changed, 24 insertions(+), 23 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.318
llvm/lib/Target/X86/X86ISelLowering.cpp:1.319
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.318 Sun Jan 28 09:39:16 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Jan 29 16:58:52 2007
@@ -1940,25 +1940,6 @@
-std::pair X86TargetLowering::
-LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
-SelectionDAG &DAG) {
- SDOperand Result;
- if (Depth)// Depths > 0 not supported yet!
-Result = DAG.getConstant(0, getPointerTy());
- else {
-SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
-if (!isFrameAddress)
- // Just load the return address
- Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI,
- NULL, 0);
-else
- Result = DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
- DAG.getConstant(4, getPointerTy()));
- }
- return std::make_pair(Result, Chain);
-}
-
/// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
/// specific condition code. It returns a false if it cannot do a direct
/// translation. X86CC is the translated CondCode. LHS/RHS are modified as
@@ -4621,6 +4602,26 @@
}
}
+SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
+ // Depths > 0 not supported yet!
+ if (cast(Op.getOperand(0))->getValue() > 0)
+return SDOperand();
+
+ // Just load the return address
+ SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
+ return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
+}
+
+SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
+ // Depths > 0 not supported yet!
+ if (cast(Op.getOperand(0))->getValue() > 0)
+return SDOperand();
+
+ SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
+ return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
+ DAG.getConstant(4, getPointerTy()));
+}
+
/// LowerOperation - Provide custom lowering hooks for some operations.
///
SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
@@ -4654,6 +4655,8 @@
case ISD::READCYCLECOUNTER: return LowerREADCYCLCECOUNTER(Op, DAG);
case ISD::VASTART:return LowerVASTART(Op, DAG);
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
+ case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
+ case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
}
}
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.84
llvm/lib/Target/X86/X86ISelLowering.h:1.85
--- llvm/lib/Target/X86/X86ISelLowering.h:1.84 Sun Jan 28 07:31:35 2007
+++ llvm/lib/Target/X86/X86ISelLowering.h Mon Jan 29 16:58:52 2007
@@ -292,10 +292,6 @@
///
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
-virtual std::pair
-LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
-SelectionDAG &DAG);
-
virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
@@ -406,6 +402,8 @@
SDOperand LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG);
SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
+SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG);
+SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG);
};
}
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Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Hello, Nick. > Fix compile error "jump to case label crosses initialization". > What compiler are people using that accepts this code? Sorry for the breakage. It was just gcc 3.4.6 :( I know about this "feature" and double checked the code. However, I was wrong -- With best regards, Anton Korobeynikov. Faculty of Mathematics & Mechanics, Saint Petersburg State University. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.317 -> 1.318
---
Log message:
Fix compile error "jump to case label crosses initialization".
What compiler are people using that accepts this code?
---
Diffs of the changes: (+6 -5)
X86ISelLowering.cpp | 11 ++-
1 files changed, 6 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.317
llvm/lib/Target/X86/X86ISelLowering.cpp:1.318
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.317 Sun Jan 28 07:31:35 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sun Jan 28 09:39:16 2007
@@ -1542,11 +1542,12 @@
default: assert(0 && "Unhandled argument type!");
case MVT::i8:
case MVT::i16:
- case MVT::i32:
- unsigned RegToUse = GPRArgRegs[ObjectVT-MVT::i8][GPRInd][NumIntRegs];
- Reg = AddLiveIn(MF, RegToUse, GPRClasses[ObjectVT-MVT::i8]);
- ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
- break;
+ case MVT::i32: {
+unsigned RegToUse = GPRArgRegs[ObjectVT-MVT::i8][GPRInd][NumIntRegs];
+Reg = AddLiveIn(MF, RegToUse, GPRClasses[ObjectVT-MVT::i8]);
+ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
+break;
+ }
case MVT::v16i8:
case MVT::v8i16:
case MVT::v4i32:
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