Re: SMP vs AMP: watch your cacheline sizes
Apparently this is considered a hardware bug by ARM for that SoC: https://lists.linaro.org/pipermail/linaro-toolchain/2016-September/005900.html On Wed, Jan 25, 2017 at 10:04 AM, Avi Kivity wrote: > On 01/25/2017 05:01 PM, Avi Kivity wrote: > >> On 01/25/2017 01:11 AM, Ross Bencina wrote: >> >>> On 25/01/2017 9:31 AM, Vitaly Davidovich wrote: >>> Interesting (not just) Mono bug: http://www.mono-project.com/news/2016/09/12/arm64-icache/ >>> >>> Scary. From the article's Summary section: >>> >>> """ >>> Some ARM big.LITTLE CPUs can have cores with different cache line sizes, >>> and pretty much no code out there is ready to deal with it as they assume >>> all cores to be symmetrical. >>> """ >>> >>> The article appears to deal with icache flushing. Could multiple cache >>> line sizes also cause issues for data access? Under what circumstances? >>> >>> >> If your data cache is not coherent. I don't know of any such >> implementations, they would be a nightmare for general-purpose computing. >> Incoherent instruction caches only affect kernels, module loaders, JITs, >> and malware authors. >> > > Some (most?) architectures have incoherent DMA. So if you flush your > dcache with the wrong cache line size, you end up with corrupted data on > disk or on the wire. > > > -- > You received this message because you are subscribed to the Google Groups > "mechanical-sympathy" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to mechanical-sympathy+unsubscr...@googlegroups.com. > For more options, visit https://groups.google.com/d/optout. > -- You received this message because you are subscribed to the Google Groups "mechanical-sympathy" group. To unsubscribe from this group and stop receiving emails from it, send an email to mechanical-sympathy+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: SMP vs AMP: watch your cacheline sizes
On 01/25/2017 05:01 PM, Avi Kivity wrote: On 01/25/2017 01:11 AM, Ross Bencina wrote: On 25/01/2017 9:31 AM, Vitaly Davidovich wrote: Interesting (not just) Mono bug: http://www.mono-project.com/news/2016/09/12/arm64-icache/ Scary. From the article's Summary section: """ Some ARM big.LITTLE CPUs can have cores with different cache line sizes, and pretty much no code out there is ready to deal with it as they assume all cores to be symmetrical. """ The article appears to deal with icache flushing. Could multiple cache line sizes also cause issues for data access? Under what circumstances? If your data cache is not coherent. I don't know of any such implementations, they would be a nightmare for general-purpose computing. Incoherent instruction caches only affect kernels, module loaders, JITs, and malware authors. Some (most?) architectures have incoherent DMA. So if you flush your dcache with the wrong cache line size, you end up with corrupted data on disk or on the wire. -- You received this message because you are subscribed to the Google Groups "mechanical-sympathy" group. To unsubscribe from this group and stop receiving emails from it, send an email to mechanical-sympathy+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: SMP vs AMP: watch your cacheline sizes
On 01/25/2017 01:11 AM, Ross Bencina wrote: On 25/01/2017 9:31 AM, Vitaly Davidovich wrote: Interesting (not just) Mono bug: http://www.mono-project.com/news/2016/09/12/arm64-icache/ Scary. From the article's Summary section: """ Some ARM big.LITTLE CPUs can have cores with different cache line sizes, and pretty much no code out there is ready to deal with it as they assume all cores to be symmetrical. """ The article appears to deal with icache flushing. Could multiple cache line sizes also cause issues for data access? Under what circumstances? If your data cache is not coherent. I don't know of any such implementations, they would be a nightmare for general-purpose computing. Incoherent instruction caches only affect kernels, module loaders, JITs, and malware authors. -- You received this message because you are subscribed to the Google Groups "mechanical-sympathy" group. To unsubscribe from this group and stop receiving emails from it, send an email to mechanical-sympathy+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: SMP vs AMP: watch your cacheline sizes
On 25/01/2017 9:31 AM, Vitaly Davidovich wrote: Interesting (not just) Mono bug: http://www.mono-project.com/news/2016/09/12/arm64-icache/ Scary. From the article's Summary section: """ Some ARM big.LITTLE CPUs can have cores with different cache line sizes, and pretty much no code out there is ready to deal with it as they assume all cores to be symmetrical. """ The article appears to deal with icache flushing. Could multiple cache line sizes also cause issues for data access? Under what circumstances? -- You received this message because you are subscribed to the Google Groups "mechanical-sympathy" group. To unsubscribe from this group and stop receiving emails from it, send an email to mechanical-sympathy+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
