Mersenne: Error rate
Hi all, The first results are in from version 17.0 535 results have been reported with 7 mismatched residues. Of those 7, 2 had errors reported during the version 17.0 run. Thus, very preliminary data indicates that if you get an error-free double-check run under version 17, then there is about 1 in 100 chance that you are doing a first-time check that could find a new Mersenne prime. Actually, the odds could be lower as I assumed the 5 mismatches were due to a bad initial run as opposed to a bad version 17 run. Unfortunately, my database is not well enough organized to know whether any errors were reported on the initial run of those 5 numbers. I'll post updated numbers at a later date. Best regards, George
Re: Mersenne: When triple checking fails
ftp://gimps:[EMAIL PROTECTED]/home/gimps/programs.txt works and that ftp://gimps:[EMAIL PROTECTED]/programs.txt dit not work with Internet Explorer on his computer. I would probably consider this a bug in Internet Explorer. From your description, it is a bug either in IE or in either the HTTP or FTP server on 209.45.246.79; the FTP protocol is quite clear as to the directory at login. But FTP itself (my Linux ftp client, e.g., rather than a web browser) is working correctly, so the FTP server appears to be working fine. Only the longer URL works for me, too. I'm using Netscape Communicator v4.05 on Windows 95 NT. Can we please have the URLs fixed so that as many people as possible can access the files without having to manually edit URLs. I believe the longer URL works with current versions of both Netscape and Microsoft IE. I'm not over concerned about what standards claim to be correct, just that it works. (This is known as "de-facto standardization". Regardless of your attitude on "browser wars", you have to accept that Netscape and IE between them have the vast majority of the market!) Regards Brian Beesley Regards Brian Beesley
Re: Mersenne: The Edge Conjecture
A bad mathematician's proof: (Sorry I will have to spell all this out, can't use proper math symbols without resorting to non-ascii messages!) Let S be the set of all statements. Let T be the set of all true statements. Let C be the complement of T in S. (Note that I am deliberately not using the word "false". C includes all statements which are indeterminate as well as false statements.) Consider: (1) Both this statement and statement (2) (below) are members of C. (2) There are an (in)finite number of primes. Now, (1) asserts that (1) is in C. Therefore (1) cannot possibly be in T. If (2) is also in C, then (1) and (2) are both in C, making (1) true. Contradiction. Therefore (2) is true. Clearly this is bunkum, since the wording of (2) could be changed to anything at all without affecting the proof. However, it does help make clear just how careful one needs to be with analytical proofs! Regards Brian Beesley Regards Brian Beesley
Mersenne: Re: The EDGE CONJECTURE
Hey Kevin, you are the next Einstein of Mathematics ! But have you ever thought about what you have said ? You are saying that theorems and axioms (which build everthing in maths) can change for big numbers. But why should that be so ? They have a general validity ! I agree with you that not all qualities of numbers are discovered. That knows everyone who has some knowledge in mathematics. But the problem of physics is that when you do a messure there are always some errors in it. And in the distrbution of such errors every exorbitant theory has a place in it. And if Newton or doesn`t matter which scientist would have precise instruments he/she would write another theories. But don`t forget: MATHEMATICS IS EXACT !!! If we would use the binary system for counting since our first day a child could count up to 1023 and then see much more of the world. I get angry when some people attack some 100% logic things like the maths isn`t absolut (e.g. 1+1=3 is in an other galaxy) or predicts from Nostradamus say that an asian mathematik expert (nothing agaings them) discoveres in 22xx that PI was calculated false. B...sh.. ! Your problem -and there you aren`t alone- is that they mix aequivalences = with implications - or think that implications can be tourned in the other way. It`s nice that you think about correctness of proofs, but be very careful with that what you say. I know that was hard. But life is also hard. greetings Bojan
Re: Mersenne: AMD K7 will
c:=a+b RISC: add a,b,c CISC: mov a,c (1) add b,c (2) When (2) depends on (1), there is no possibility for parallelization. Good, you can argue that instructions on 3 operators are better than the one on 2 instructions. I'm no expert, but isn't this an unfair characterization of CISC? Yes and no. I know that MIPS uses the "add a,b,c" format and Intel uses "add a,b", but Intel is just one CISC architecture. I don't see any reason why you couldn't build a CISC processor with a three-operand format. Me too. I wrote that it`s unfair to associate 2 op. intructions to CISC and 2 op. inst. to RISC. When RISC was introduced, this instruction format was inculed with it, but it has nothing to do with it. The idea of RISC was to have few but very fast commands. For that a lot of complexity (number of transitors) was wasted to reach this goal (I assume it is so, at least it makes sense). But some RISC machines (like Alpha) added some instructions which could be typical for CISC. The PEER command give the middle value of 8 byte - 1 instr. vs. 9 instr., this because of multimedia (MPEG). Intel would best be served if the would introduce 3 op. instructions at Katmai (maybe the do it ?). While in 32 bit code with 32 register 3 register each decoded by 5 bits have space, in an 64 bit architecture with 64 register up to 8 registers could be used for computation (8x6 bit=48 bit + 16 bit for decoding the instruction), or in IA-64 with 128 registers up to 7 registers (7x7 bit=49 bit+ 15 bit for instructions). My conjuncture is: there is no need for 128 bit instruction code, so 64 bit inst. code will be the final one. FPU register will stay to use 64 bit, and for the other one I can`t say nothing. The main part of speeding up processors will be done be using multiple processors. greetings Bojan
Re: Mersenne: The Edge Conjecture
OH NO! Not this thread again! --- William Stuart ([EMAIL PROTECTED]) "Don't rush me sonny. You rush a miracle man you get rotten miracles." --Miracle Max, "The Princess Bride" On Sat, 24 Oct 1998, Joao Paulo Sousa wrote: Date: Sat, 24 Oct 1998 19:58:01 +0100 From: Joao Paulo Sousa [EMAIL PROTECTED] To: [EMAIL PROTECTED] Subject: Re: Mersenne: The Edge Conjecture Polititians have an even better proof: 1 is prime 3 is prime 5 is prime 7 is prime 9 is prime 11 is prime 13 is prime . . . All odd numbers are prime! Regards, _ __ __ | / \ / \ Joao Paulo Sousa University of Porto - DEEC | |__/ \__ ____ __ Microprocessors Laboratory | | \ / \ | | /__ __\ Rua dos Bragas, 4099 PORTO Codex, Portugal \__/ |\__/ \__/ \__/ __/ \__/ Tel +351-2-2041846 Fax +351-2-2059280 [ http://www.fe.up.pt/~jpsousa ]-
Re: Mersenne: AMD K7 will
On Mon, 26 Oct 1998, Bojan Antonovic wrote: [...schnipp...] My conjuncture is: there is no need for 128 bit instruction code, so 64 bit inst. code will be the final one. FPU register will stay to use 64 bit, and for the other one I can`t say nothing. The main part of speeding up processors will be done be using multiple processors. Why do you believe there will be no 128bit processors? Isn't "more data at a time" always better? I agree with you that advances in multiprocessing are needed and will be beneficial, but in the race for a better desktop machine, SMP does little to help. Without more info on the technical reasons behind your conjecture, I am willing to bet that at least one of the non-intel chip manufacturers announces a 128bit chip, if only to gain some attention. --- William Stuart ([EMAIL PROTECTED]) "Don't rush me sonny. You rush a miracle man you get rotten miracles." --Miracle Max, "The Princess Bride"
Mersenne: FTP urls
Brian J Beesley wrote: Can we please have the URLs fixed? There's no disagreement on how ftp urls work for anonymous access, at least there's less. Who else reading this is in a position to host the ftp archive? I may be moving my data off of 209.45.246.79 because of a dispute with the system administrators of TNI, who shut down telnet several weeks ago and have not re-enabled it even after daily complaints. I think it would be a simple thing for a university to host the archive, if I was faculty at UMKC I would have it set up but as I am but staff I do not wish to add to our (receding, but still...) bandwidth problems. What kind of internet connection have they got there at ulst.ac.uk, Brian? __ David Nicol 816.235.1187 UMKC Network Operations [EMAIL PROTECTED] "No... I think I hit the group code."
Re: Mersenne: The EDGE CONJECTURE
I can even prove... Now *WHERE* is this going?? Several years ago I spent an afternoon reading alt.cascade. There was a thread of bragging about what an excellent engineer the poster was (not unlike this one.) The form was, I have serious CS feat running on minimal hardware. You know, like, I have X-windows running under linux on a 386-20 with 4 Megs of ram, that's nothing, I have a vt100 emulator running on a ZX81, I'm running BOVINE on the PLL-chip in my stereo, and so forth As I recall, the one that made me laugh so hard I fell off my chair was "I have concurrent parallel molecular models of the known universe running on a single paperclip" Hmm. I guess you had to have been there. __ David Nicol 816.235.1187 UMKC Network Operations [EMAIL PROTECTED] "No... I think I hit the group code."
Re: Mersenne: AMD K7 will
c:=a+b RISC: add a,b,c CISC: mov a,c (1) add b,c (2) When (2) depends on (1), there is no possibility for parallelization. Good, you can argue that instructions on 3 operators are better than the one on 2 instructions. I'm no expert, but isn't this an unfair characterization of CISC? Yes and no. All modern processors use a dynamic execution architecture that blends out-of-order and speculative execution with hardware register renaming and branch prediction. These processors feature an in-order issue pipeline, which breaks processor macroinstructions into simple, micro-operations, and an out-of-order, superscalar processor core, which executes the micro-ops. The out-of-order core of the processor contains several pipelines to which integer, branch, floating-point and memory execution units are attached. Many instructions contain few micro-operations then the processor is able to execute more than 1 instruction per cycle. Some instructions are complex and needs several cycles to be executed (div, sqrt, cos, ...) but they are not often used. Is that processor a RISC or a CISC ? Neither a RISC nor a CISC! And it is really faster than a RISC or a CISC. Yves
Re: Mersenne: AMD K7 will
I can offer a quick synopsis that 64bit will be the main stay for at least 8 years after intel introduces it's chip to the market. The first 32bit intel processor was introduced around '88 -89'. the 486. It wasn't really fully utilized for 5 years. (I know Unix used it correctly, and OS/2 too, I'm not a Mac person so no knowledge there (anyway different chip)) Legacy programming and OS's dictate the speed of use and embracing of new architecture. I think it mainly had to deal with the OS DOS was designed for 8bit originally and then extended through creative programming. I'm in the process of changing over into Oracle and GUI is still 16bit. Legacy code. With the introduction of the 64bit chip, you'll receive some increase in processing speed due to data throughput. The other area which right now looks a lot more promising in speed breakthroughs is in chip manufacturing. Mainly replacing AL with CU. Lower resistance, which produces less heat, which enables a higher density of transistors. Corporate America will not switch over unless it's economically viable for them to switch. Meaning that they do nothing until it becomes clear that if they don't switch they'll lose money or due to the sheer size of the company no wholesale conversion is possible only working units will be slowly converted. Meaning that backwards compatibility is a must. So that throws out any radical shift in OS design making full utilization of the chip architecture. I'm not ruling out 128bit chips. High end machines will always be out there and ahead of the marketplace. The Alpha has been out for awhile now, but how many alpha machines do you see sitting on desktops in your basic office. On Mon, 26 Oct 1998, Bojan Antonovic wrote: [...schnipp...] My conjuncture is: there is no need for 128 bit instruction code, so 64 bit inst. code will be the final one. FPU register will stay to use 64 bit, and for the other one I can`t say nothing. The main part of speeding up processors will be done be using multiple processors. Why do you believe there will be no 128bit processors? Isn't "more data at a time" always better? I agree with you that advances in multiprocessing are needed and will be beneficial, but in the race for a better desktop machine, SMP does little to help. Without more info on the technical reasons behind your conjecture, I am willing to bet that at least one of the non-intel chip manufacturers announces a 128bit chip, if only to gain some attention. --- William Stuart ([EMAIL PROTECTED]) "Don't rush me sonny. You rush a miracle man you get rotten miracles." --Miracle Max, "The Princess Bride"
Re: Mersenne: AMD K7 will
On Mon, 26 Oct 1998 16:13:33 EST "Foghorn Leghorn" wrote: Sony Playstation has got a MIPS. So what about GIMPS at Playstation ??? The Playstation doesn't do floating point. It would be a very slow platform for running GIMPS. :) Question: does Prime95 use floating point because the algorithm requires it, or because something about the Intel architecture makes it a good choice? I'm not clear about how Prime95 is able to use floating point to perform something that is theoretically an all-integer computation. Is there any platform on which an all-integer implementation would be superior to one that uses floating point? In a nutshell, most platforms have much faster floating-point operations than integer, especially in the case of FP multiply vs. integer multiply. Also a lot of machines have larger floating point registers - eg 64 bit FP vs. 32 bit integer. I guess if there was an architecture that had as fast integer as floating point, and the integer registers were the same size as the floating point registers, then you'd probably have a platform where integer only FFTs would be a win. Simon.
