Mesa (master): radv: remove some unused macros and functions
Module: Mesa
Branch: master
Commit: cb89d19dbbaac301534e7a543bb9bcd740b05008
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb89d19dbbaac301534e7a543bb9bcd740b05008
Author: Grazvydas Ignotas
Date: Wed Jan 11 03:31:24 2017 +0200
radv: remove some unused macros and functions
These seem unlikely to be used.
Also remove irrelevant comment about SKL.
v2: forgot to rebase on master
Signed-off-by: Grazvydas Ignotas
---
src/amd/vulkan/radv_private.h | 15 +--
src/amd/vulkan/radv_util.c| 19 ---
2 files changed, 1 insertion(+), 33 deletions(-)
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index ebda49d..fc3cbca 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -79,8 +79,7 @@ typedef uint32_t xcb_window_t;
#define MAX_SCISSORS16
#define MAX_PUSH_CONSTANTS_SIZE 128
#define MAX_DYNAMIC_BUFFERS 16
-#define MAX_IMAGES 8
-#define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
+#define MAX_SAMPLES_LOG2 4
#define NUM_META_FS_KEYS 11
#define NUM_DEPTH_CLEAR_PIPELINES 3
@@ -112,7 +111,6 @@ enum {
RADV_DEBUG_UNSAFE_MATH = 0x80,
};
-#define radv_noreturn __attribute__((__noreturn__))
#define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
static inline uint32_t
@@ -248,9 +246,6 @@ void radv_loge_v(const char *format, va_list va);
#define radv_assert(x)
#endif
-void radv_abortf(const char *format, ...) radv_noreturn radv_printflike(1, 2);
-void radv_abortfv(const char *format, va_list va) radv_noreturn;
-
#define stub_return(v) \
do {\
radv_finishme("stub %s", __func__); \
@@ -1328,12 +1323,4 @@ RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass,
VkRenderPass)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
-#define RADV_DEFINE_STRUCT_CASTS(__radv_type, __VkType)
\
- \
- static inline const __VkType * \
- __radv_type ## _to_ ## __VkType(const struct __radv_type *__radv_obj) \
- { \
- return (const __VkType *) __radv_obj; \
- }
-
#endif /* RADV_PRIVATE_H */
diff --git a/src/amd/vulkan/radv_util.c b/src/amd/vulkan/radv_util.c
index 8c7a948..c642bb7 100644
--- a/src/amd/vulkan/radv_util.c
+++ b/src/amd/vulkan/radv_util.c
@@ -65,25 +65,6 @@ void radv_printflike(3, 4)
fprintf(stderr, "%s:%d: FINISHME: %s\n", file, line, buffer);
}
-void radv_noreturn radv_printflike(1, 2)
- radv_abortf(const char *format, ...)
-{
- va_list va;
-
- va_start(va, format);
- radv_abortfv(format, va);
- va_end(va);
-}
-
-void radv_noreturn
-radv_abortfv(const char *format, va_list va)
-{
- fprintf(stderr, "vk: error: ");
- vfprintf(stderr, format, va);
- fprintf(stderr, "\n");
- abort();
-}
-
VkResult
__vk_errorf(VkResult error, const char *file, int line, const char *format,
...)
{
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Mesa (master): 21 new commits
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=64272d4f1bc8fe1b476ed26904d673f35b0f2c86 Author: Nanley Chery Date: Wed Dec 14 18:20:26 2016 -0800 anv: Avoid some resolves for samplable HiZ buffers v2: Simplify nested ifs (Jason Ekstrand) Signed-off-by: Nanley Chery Reviewed-by: Jason Ekstrand URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=71334f494acea9ef0372fd4b3cd6557765669421 Author: Nanley Chery Date: Wed Jan 11 08:12:48 2017 -0800 anv: Enable sampling from HiZ v2: Restrict ISL_AUX_USAGE_HIZ to depth aspects Signed-off-by: Nanley Chery Reviewed-by: Jason Ekstrand URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e0902cd2abf21df955be359e0903fc5b66905f5 Author: Nanley Chery Date: Thu Dec 15 09:57:48 2016 -0800 anv/blorp: Don't fast depth clear samplable HiZ buffers on BDW Avoid the resolves that would be required if fast depth clears were allowed for such buffers. Signed-off-by: Nanley Chery Reviewed-by: Jason Ekstrand URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ac01ad2ac2aedee7e2515365d13c71a024878fb Author: Nanley Chery Date: Mon Jan 9 19:24:44 2017 -0800 anv: Add a helper to determine sampling with HiZ Signed-off-by: Nanley Chery Reviewed-by: Jason Ekstrand URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bcf880a9c89622bc7ab48da652eae4549207e6e8 Author: Nanley Chery Date: Mon Dec 5 15:24:28 2016 -0800 isl/surface_state: Handle ISL_AUX_USAGE_HIZ v2: Remove redundant x/y offset asserts (Jason Ekstrand) Signed-off-by: Nanley Chery Reviewed-by: Jason Ekstrand URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=58af6156360a309578241acba949e540acf72cb1 Author: Nanley Chery Date: Mon Jan 2 01:06:15 2017 -0800 anv: Perform HiZ resolves only on layout transitions This is a better mapping to the Vulkan API and improves performance in all tested workloads. v2: Remove unnecessary image view aspect checks (Jason Ekstrand) Signed-off-by: Nanley Chery Reviewed-by: Jason Ekstrand URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2852efcda40274acf3272611c6a3b7731523a72d Author: Nanley Chery Date: Wed Jan 11 15:12:35 2017 -0800 anv: Disable HiZ for input attachments v2 (Jason Ekstrand): - Add spec citation - Drop conditional Signed-off-by: Nanley Chery Reviewed-by: Jason Ekstrand URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b62d8ad2aee2f67fb290332b285a0a5aa93e7724 Author: Nanley Chery Date: Tue Dec 6 09:08:09 2016 -0800 anv: Avoid resolves incurred by fast depth clears Signed-off-by: Nanley Chery Reviewed-by: Jason Ekstrand URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=968ffd6c868af7226e8f889573eef709888151cb Author: Nanley Chery Date: Mon Jan 9 10:44:36 2017 -0800 anv: Prepare for transitioning to the requested final layout Signed-off-by: Nanley Chery Reviewed-by: Jason Ekstrand URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=104ce1dbab44f8d11d5dcc90d3f1cc8c466893d8 Author: Nanley Chery Date: Mon Jan 2 00:44:08 2017 -0800 anv: Store depth stencil layouts Store the current and requested depth stencil layouts so that we can perform the appropriate HiZ resolves for a given transition while recording a render pass. Signed-off-by: Nanley Chery Reviewed-by: Jason Ekstrand URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e2cf78a5104b3e08fea039d1b2d20a137d6a371 Author: Nanley Chery Date: Wed Dec 14 17:58:41 2016 -0800 anv: Add helpers to handle depth buffer layout transitions Signed-off-by: Nanley Chery Reviewed-by: Jason Ekstrand URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ce8b37a8e51d6e7691dfcde52f318200a3f3f74 Author: Nanley Chery Date: Thu Jan 5 23:34:38 2017 -0800 anv: Delete anv's HiZ op emit function This is no longer used. Signed-off-by: Nanley Chery Reviewed-by: Jason Ekstrand URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=462a4c96487b3bf36119bdfaee2bdacb835e4100 Author: Nanley Chery Date: Wed Jan 11 13:05:13 2017 -0800 anv: Use the gen8 BLORP HiZ resolving function Signed-off-by: Nanley Chery Reviewed-by: Jason Ekstrand URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d16871d9580152c5a041e9d54165f54f366ebb45 Author: Nanley Chery Date: Thu Jan 5 23:32:07 2017 -0800 anv/blorp: Add a gen8 HiZ op resolve function Add an entry point for resolving using BLORP's gen8 HiZ op function. v2: Manually add the aux info Signed-off-by: Nanley Chery Reviewed-by: Jason Ekstrand URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b7106c18136a107bd0d396bf061b8c9f914b4b9 Author: Nanley Chery Date: Thu Jan 5 16:46:37 2017 -0800
Mesa (master): ac: automake: ensure that ./common is generated
Module: Mesa Branch: master Commit: 5abd0a7583708ec91ee25cf559a15fa33fa7 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5abd0a7583708ec91ee25cf559a15fa33fa7 Author: Emil Velikov Date: Thu Jan 12 22:13:21 2017 + ac: automake: ensure that ./common is generated Depending on the autoconf (or friends) version one may or may not have the ./common folder created. Thus in the latter case we'll fail to generate the file. Reviewed-by: Thierry Reding Tested-by: Darren Salt Reported-by: Darren Salt Signed-off-by: Emil Velikov --- src/amd/Makefile.common.am | 1 + 1 file changed, 1 insertion(+) diff --git a/src/amd/Makefile.common.am b/src/amd/Makefile.common.am index ab69fc3..832a943 100644 --- a/src/amd/Makefile.common.am +++ b/src/amd/Makefile.common.am @@ -66,6 +66,7 @@ endif endif common/sid_tables.h: $(srcdir)/common/sid_tables.py $(srcdir)/common/sid.h + $(AM_V_at)$(MKDIR_P) $(@D) $(AM_V_GEN) $(PYTHON2) $(srcdir)/common/sid_tables.py $(srcdir)/common/sid.h > $@ BUILT_SOURCES = $(AMD_GENERATED_FILES) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): get-typod-pick-list.sh: add new script
Module: Mesa Branch: master Commit: f0bdd13fdbc0bec1119b296d99820899183e26ab URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0bdd13fdbc0bec1119b296d99820899183e26ab Author: Emil Velikov Date: Fri Dec 16 15:08:30 2016 + get-typod-pick-list.sh: add new script Typos do happen as people nominate patches for stable. This script aims to catch most of those. Due to the subtle nature of things, one has to pay special attention to the output, similar to get-extra-pick-list.sh. At the moment only the following is handled: grep -i "CC:.*mesa-dev" Cc: 12.0 13.0 Signed-off-by: Emil Velikov --- bin/get-typod-pick-list.sh | 39 +++ 1 file changed, 39 insertions(+) diff --git a/bin/get-typod-pick-list.sh b/bin/get-typod-pick-list.sh new file mode 100755 index 000..2fe3d89 --- /dev/null +++ b/bin/get-typod-pick-list.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# Script for generating a list of candidates which have typos in the nomination line +# +# Usage examples: +# +# $ bin/get-typod-pick-list.sh +# $ bin/get-typod-pick-list.sh > picklist +# $ bin/get-typod-pick-list.sh | tee picklist + +# NB: +# This script intentionally _never_ checks for specific version tag +# Should we consider folding it with the original get-pick-list.sh + +# Grep for commits with "cherry picked from commit" in the commit message. +git log --reverse --grep="cherry picked from commit" origin/master..HEAD |\ + grep "cherry picked from commit" |\ + sed -e 's/^[[:space:]]*(cherry picked from commit[[:space:]]*//' -e 's/)//' > already_picked + +# Grep for commits that were marked as a candidate for the stable tree. +git log --reverse --pretty=%H -i --grep='^CC:.*mesa-dev' HEAD..origin/master |\ +while read sha +do + # Check to see whether the patch is on the ignore list. + if [ -f bin/.cherry-ignore ] ; then + if grep -q ^$sha bin/.cherry-ignore ; then + continue + fi + fi + + # Check to see if it has already been picked over. + if grep -q ^$sha already_picked ; then + continue + fi + + git log -n1 --pretty=oneline $sha | cat +done + +rm -f already_picked ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nvc0/ir: only try to check for zero LOD if we aren' t already forcing it
Module: Mesa
Branch: master
Commit: f897036978b42619ce27ea4f41886cc0002f33ef
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f897036978b42619ce27ea4f41886cc0002f33ef
Author: Ilia Mirkin
Date: Thu Jan 12 21:06:40 2017 -0500
nvc0/ir: only try to check for zero LOD if we aren't already forcing it
There's a levelZero flag which forces texturing to pick level zero (and
not consume an explicit LOD argument). This is set for MS targets, but
could also be set for any other incoming instruction. As that is what
determines whether a LOD argument is present, check that rather than the
more indirect isMS logic.
Signed-off-by: Ilia Mirkin
---
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index ff253af..95de87c 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -118,7 +118,7 @@ NVC0LegalizeSSA::handleFTZ(Instruction *i)
void
NVC0LegalizeSSA::handleTEXLOD(TexInstruction *i)
{
- if (i->tex.target.isMS())
+ if (i->tex.levelZero)
return;
ImmediateValue lod;
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Mesa (master): nouveau: take extra push space into account for pushbuf_space calls
Module: Mesa
Branch: master
Commit: eb60a89bc3ac2b43faf52d06e05670bbbca7292d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eb60a89bc3ac2b43faf52d06e05670bbbca7292d
Author: Ilia Mirkin
Date: Tue Jan 10 22:07:53 2017 -0500
nouveau: take extra push space into account for pushbuf_space calls
Ever since a long time ago when I messed around with fences, I ensure
that after a PUSH_SPACE call there is enough space to write a fence out
into the pushbuf.
However the PUSH_SPACE macro is not all-knowing, and so sometimes we
have to invoke nouveau_pushbuf_space manually with the relocs/pushes
args set. If we don't take the extra allocation from PUSH_SPACE into
account, then we will end up accidentally flushing when the code was not
expecting a flush. This can lead to various runtime and rendering
failures.
The amount of extra allocation isn't that important - it has to be at
least 8 based on the current nouveau_winsys.h setting, but even more
won't hurt. I just rounded up to powers of 2.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99354
Cc: "12.0 13.0"
Signed-off-by: Ilia Mirkin
Acked-by: Ben Skeggs
---
src/gallium/drivers/nouveau/nouveau_video.c | 2 +-
src/gallium/drivers/nouveau/nv30/nv30_clear.c | 2 +-
src/gallium/drivers/nouveau/nv30/nv30_transfer.c | 8
src/gallium/drivers/nouveau/nv50/nv50_surface.c | 6 +++---
src/gallium/drivers/nouveau/nv50/nv50_vbo.c | 2 +-
src/gallium/drivers/nouveau/nv50/nv98_video.c | 6 +++---
src/gallium/drivers/nouveau/nv50/nv98_video_bsp.c | 7 +--
src/gallium/drivers/nouveau/nv50/nv98_video_ppp.c | 7 +--
src/gallium/drivers/nouveau/nv50/nv98_video_vp.c | 9 ++---
src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c | 2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c | 2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_video.c | 6 +++---
src/gallium/drivers/nouveau/nvc0/nvc0_video_bsp.c | 7 +--
src/gallium/drivers/nouveau/nvc0/nvc0_video_ppp.c | 7 +--
src/gallium/drivers/nouveau/nvc0/nvc0_video_vp.c | 9 ++---
15 files changed, 26 insertions(+), 56 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nouveau_video.c
b/src/gallium/drivers/nouveau/nouveau_video.c
index bb3aad7..95d8866 100644
--- a/src/gallium/drivers/nouveau/nouveau_video.c
+++ b/src/gallium/drivers/nouveau/nouveau_video.c
@@ -73,7 +73,7 @@ nouveau_vpe_fini(struct nouveau_decoder *dec) {
if (!dec->cmds)
return;
- nouveau_pushbuf_space(push, 8, 2, 0);
+ nouveau_pushbuf_space(push, 16, 2, 0);
nouveau_bufctx_reset(dec->bufctx, NV31_VIDEO_BIND_CMD);
#define BCTX_ARGS dec->bufctx, NV31_VIDEO_BIND_CMD, NOUVEAU_BO_RD
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_clear.c
b/src/gallium/drivers/nouveau/nv30/nv30_clear.c
index 4217bca..4e6df1e 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_clear.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_clear.c
@@ -128,7 +128,7 @@ nv30_clear_render_target(struct pipe_context *pipe, struct
pipe_surface *ps,
refn.bo = mt->base.bo;
refn.flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_WR;
- if (nouveau_pushbuf_space(push, 16, 1, 0) ||
+ if (nouveau_pushbuf_space(push, 32, 1, 0) ||
nouveau_pushbuf_refn (push, &refn, 1))
return;
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_transfer.c
b/src/gallium/drivers/nouveau/nv30/nv30_transfer.c
index e4b9497..6f06ee6 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_transfer.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_transfer.c
@@ -431,7 +431,7 @@ nv30_transfer_rect_sifm(XFER_ARGS)
si_arg |= NV03_SIFM_FORMAT_FILTER_BILINEAR;
}
- if (nouveau_pushbuf_space(push, 32, 6, 0) ||
+ if (nouveau_pushbuf_space(push, 64, 6, 0) ||
nouveau_pushbuf_refn (push, refs, 2))
return;
@@ -516,7 +516,7 @@ nv30_transfer_rect_m2mf(XFER_ARGS)
while (h) {
unsigned lines = (h > 2047) ? 2047 : h;
- if (nouveau_pushbuf_space(push, 13, 2, 0) ||
+ if (nouveau_pushbuf_space(push, 32, 2, 0) ||
nouveau_pushbuf_refn (push, refs, 2))
return;
@@ -708,7 +708,7 @@ nv30_transfer_copy_data(struct nouveau_context *nv,
lines = (pages > 2047) ? 2047 : pages;
pages -= lines;
- if (nouveau_pushbuf_space(push, 13, 2, 0) ||
+ if (nouveau_pushbuf_space(push, 32, 2, 0) ||
nouveau_pushbuf_refn (push, refs, 2))
return;
@@ -732,7 +732,7 @@ nv30_transfer_copy_data(struct nouveau_context *nv,
}
if (size) {
- if (nouveau_pushbuf_space(push, 13, 2, 0) ||
+ if (nouveau_pushbuf_space(push, 32, 2, 0) ||
nouveau_pushbuf_refn (push, refs, 2))
return;
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_surface.c
b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
index a6c0bbc..f5fa9d6 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
@@ -295,7 +295,7 @@ nv50_clear_render_target(struct pipe_context *pipe,
PUSH_DATAf(p
Mesa (master): mapi: update the asm code to support x32
Module: Mesa
Branch: master
Commit: 89458366585c34879b70110758bb4fd3acb62ce0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=89458366585c34879b70110758bb4fd3acb62ce0
Author: Grazvydas Ignotas
Date: Sun Jan 8 19:38:09 2017 +0200
mapi: update the asm code to support x32
Fixes crashes when both glx-tls and asm are enabled on x32.
Cc: mesa-sta...@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94512
Bugzilla: https://bugs.gentoo.org/show_bug.cgi?id=575458
Signed-off-by: Grazvydas Ignotas
Reviewed-by: Ilia Mirkin
Reviewed-by: Edward O'Callaghan
---
src/mapi/entry_x86-64_tls.h | 31 ---
1 file changed, 28 insertions(+), 3 deletions(-)
diff --git a/src/mapi/entry_x86-64_tls.h b/src/mapi/entry_x86-64_tls.h
index 8f3fa91..1e29bde 100644
--- a/src/mapi/entry_x86-64_tls.h
+++ b/src/mapi/entry_x86-64_tls.h
@@ -41,11 +41,23 @@ __asm__(".text\n"
".balign 32\n"\
func ":"
+#ifndef __ILP32__
+
#define STUB_ASM_CODE(slot) \
"movq " ENTRY_CURRENT_TABLE "@GOTTPOFF(%rip), %rax\n\t" \
"movq %fs:(%rax), %r11\n\t" \
"jmp *(8 * " slot ")(%r11)"
+#else
+
+#define STUB_ASM_CODE(slot) \
+ "movq " ENTRY_CURRENT_TABLE "@GOTTPOFF(%rip), %rax\n\t" \
+ "movl %fs:(%rax), %r11d\n\t" \
+ "movl 4*" slot "(%r11d), %r11d\n\t" \
+ "jmp *%r11"
+
+#endif
+
#define MAPI_TMP_STUB_ASM_GCC
#include "mapi_tmp.h"
@@ -72,19 +84,32 @@ void
entry_patch(mapi_func entry, int slot)
{
char *code = (char *) entry;
- *((unsigned int *) (code + 12)) = slot * sizeof(mapi_func);
+ int offset = 12;
+#ifdef __ILP32__
+ offset = 13;
+#endif
+ *((unsigned int *) (code + offset)) = slot * sizeof(mapi_func);
}
mapi_func
entry_generate(int slot)
{
- const char code_templ[16] = {
+ const char code_templ[] = {
+#ifndef __ILP32__
/* movq %fs:0, %r11 */
0x64, 0x4c, 0x8b, 0x1c, 0x25, 0x00, 0x00, 0x00, 0x00,
/* jmp *0x1234(%r11) */
0x41, 0xff, 0xa3, 0x34, 0x12, 0x00, 0x00,
+#else
+ /* movl %fs:0, %r11d */
+ 0x64, 0x44, 0x8b, 0x1c, 0x25, 0x00, 0x00, 0x00, 0x00,
+ /* movl 0x1234(%r11d), %r11d */
+ 0x67, 0x45, 0x8b, 0x9b, 0x34, 0x12, 0x00, 0x00,
+ /* jmp *%r11 */
+ 0x41, 0xff, 0xe3,
+#endif
};
- unsigned long addr;
+ unsigned long long addr;
char *code;
mapi_func entry;
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Mesa (master): radeonsi: remove unused si_prepare_cube_coords
Module: Mesa
Branch: master
Commit: fccf29373d418ec41e29fe57f628d681ec67e92a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fccf29373d418ec41e29fe57f628d681ec67e92a
Author: Nicolai Hähnle
Date: Tue Jan 10 17:20:57 2017 +0100
radeonsi: remove unused si_prepare_cube_coords
Reviewed-by: Bas Nieuwenhuizen
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader_internal.h | 4 -
src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c | 196 --
2 files changed, 200 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h
b/src/gallium/drivers/radeonsi/si_shader_internal.h
index 6b3ac17..51d491e 100644
--- a/src/gallium/drivers/radeonsi/si_shader_internal.h
+++ b/src/gallium/drivers/radeonsi/si_shader_internal.h
@@ -215,9 +215,5 @@ void si_llvm_emit_store(struct lp_build_tgsi_context
*bld_base,
LLVMValueRef dst[4]);
void si_shader_context_init_alu(struct lp_build_tgsi_context *bld_base);
-void si_prepare_cube_coords(struct lp_build_tgsi_context *bld_base,
- struct lp_build_emit_data *emit_data,
- LLVMValueRef *coords_arg,
- LLVMValueRef *derivs_arg);
#endif
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
index 11bd45d..085fd5b 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
@@ -906,199 +906,3 @@ void si_shader_context_init_alu(struct
lp_build_tgsi_context *bld_base)
bld_base->op_actions[TGSI_OPCODE_U64DIV].emit = emit_udiv;
bld_base->op_actions[TGSI_OPCODE_I64DIV].emit = emit_idiv;
}
-
-/* Coordinates for cube map selection. sc, tc, and ma are as in Table 8.27
- * of the OpenGL 4.5 (Compatibility Profile) specification, except ma is
- * already multiplied by two. id is the cube face number.
- */
-struct cube_selection_coords {
- LLVMValueRef stc[2];
- LLVMValueRef ma;
- LLVMValueRef id;
-};
-
-static void build_cube_intrinsic(struct gallivm_state *gallivm,
-LLVMValueRef in[3],
-struct cube_selection_coords *out)
-{
- LLVMBuilderRef builder = gallivm->builder;
-
- if (HAVE_LLVM >= 0x0309) {
- LLVMTypeRef f32 = LLVMTypeOf(in[0]);
-
- out->stc[1] = lp_build_intrinsic(builder, "llvm.amdgcn.cubetc",
- f32, in, 3, LP_FUNC_ATTR_READNONE);
- out->stc[0] = lp_build_intrinsic(builder, "llvm.amdgcn.cubesc",
- f32, in, 3, LP_FUNC_ATTR_READNONE);
- out->ma = lp_build_intrinsic(builder, "llvm.amdgcn.cubema",
- f32, in, 3, LP_FUNC_ATTR_READNONE);
- out->id = lp_build_intrinsic(builder, "llvm.amdgcn.cubeid",
- f32, in, 3, LP_FUNC_ATTR_READNONE);
- } else {
- LLVMValueRef c[4] = {
- in[0],
- in[1],
- in[2],
- LLVMGetUndef(LLVMTypeOf(in[0]))
- };
- LLVMValueRef vec = lp_build_gather_values(gallivm, c, 4);
-
- LLVMValueRef tmp =
- lp_build_intrinsic(builder, "llvm.AMDGPU.cube",
- LLVMTypeOf(vec), &vec, 1,
- LP_FUNC_ATTR_READNONE);
-
- out->stc[1] = LLVMBuildExtractElement(builder, tmp,
- lp_build_const_int32(gallivm, 0), "");
- out->stc[0] = LLVMBuildExtractElement(builder, tmp,
- lp_build_const_int32(gallivm, 1), "");
- out->ma = LLVMBuildExtractElement(builder, tmp,
- lp_build_const_int32(gallivm, 2), "");
- out->id = LLVMBuildExtractElement(builder, tmp,
- lp_build_const_int32(gallivm, 3), "");
- }
-}
-
-/**
- * Build a manual selection sequence for cube face sc/tc coordinates and
- * major axis vector (multiplied by 2 for consistency) for the given
- * vec3 \p coords, for the face implied by \p selcoords.
- *
- * For the major axis, we always adjust the sign to be in the direction of
- * selcoords.ma; i.e., a positive out_ma means that coords is pointed towards
- * the selcoords major axis.
- */
-static void build_cube_select(LLVMBuilderRef builder,
- const struct cube_selection_coords *selcoords,
- const LLVMValueRef *coords,
- LLVMValueRef *out_st,
- LLVMValueRef *out_ma)
-{
- LLVMTypeRef f32 = LLVMTypeOf(coords[0]);
- LLVMValueRef is_ma_positive;
- LLVMValueRef sgn_ma;
- LLVMValueRef is_ma_z, is_not_ma_z;
-
Mesa (master): ac/nir: use ac_build_gather_values[_extended] throughout
Module: Mesa
Branch: master
Commit: 38c67f77ed35423bdba5ee1ffd5ab6e5b1765f90
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=38c67f77ed35423bdba5ee1ffd5ab6e5b1765f90
Author: Nicolai Hähnle
Date: Tue Jan 10 15:44:04 2017 +0100
ac/nir: use ac_build_gather_values[_extended] throughout
... and eliminate the non-ac copies. Mostly straight-forward
search & replace.
Reviewed-by: Bas Nieuwenhuizen
Reviewed-by: Marek Olšák
---
src/amd/common/ac_nir_to_llvm.c | 89 +++--
1 file changed, 24 insertions(+), 65 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 2a5f916..f650937 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -631,39 +631,6 @@ static LLVMValueRef trim_vector(struct nir_to_llvm_context
*ctx,
return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
}
-static LLVMValueRef
-build_gather_values_extended(struct nir_to_llvm_context *ctx,
-LLVMValueRef *values,
-unsigned value_count,
-unsigned value_stride,
-bool load)
-{
- LLVMBuilderRef builder = ctx->builder;
- LLVMValueRef vec;
- unsigned i;
-
-
- if (value_count == 1) {
- if (load)
- return LLVMBuildLoad(builder, values[0], "");
- return values[0];
- } else if (!value_count)
- unreachable("value_count is 0");
-
- for (i = 0; i < value_count; i++) {
- LLVMValueRef value = values[i * value_stride];
- if (load)
- value = LLVMBuildLoad(builder, value, "");
-
- if (!i)
- vec = LLVMGetUndef( LLVMVectorType(LLVMTypeOf(value),
value_count));
- LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
- vec = LLVMBuildInsertElement(builder, vec, value, index, "");
- }
- return vec;
-}
-
-
static void
build_store_values_extended(struct nir_to_llvm_context *ctx,
LLVMValueRef *values,
@@ -687,14 +654,6 @@ build_store_values_extended(struct nir_to_llvm_context
*ctx,
}
}
-static LLVMValueRef
-build_gather_values(struct nir_to_llvm_context *ctx,
- LLVMValueRef *values,
- unsigned value_count)
-{
- return build_gather_values_extended(ctx, values, value_count, 1, false);
-}
-
static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
nir_ssa_def *def)
{
@@ -751,7 +710,7 @@ static LLVMValueRef get_alu_src(struct nir_to_llvm_context
*ctx,
masks[0], "");
} else if (src_components == 1 && num_components > 1) {
LLVMValueRef values[] = {value, value, value, value};
- value = build_gather_values(ctx, values,
num_components);
+ value = ac_build_gather_values(&ctx->ac, values,
num_components);
} else {
LLVMValueRef swizzle = LLVMConstVector(masks,
num_components);
value = LLVMBuildShuffleVector(ctx->builder, value,
value,
@@ -1231,7 +1190,7 @@ static LLVMValueRef emit_ddxy_interp(
result[i] = emit_ddxy(ctx, nir_op_fddx, a);
result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
}
- return build_gather_values(ctx, result, 4);
+ return ac_build_gather_values(&ctx->ac, result, 4);
}
static LLVMValueRef emit_fdiv(struct nir_to_llvm_context *ctx,
@@ -1483,7 +1442,7 @@ static void visit_alu(struct nir_to_llvm_context *ctx,
nir_alu_instr *instr)
case nir_op_vec4:
for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs;
i++)
src[i] = to_integer(ctx, src[i]);
- result = build_gather_values(ctx, src, num_components);
+ result = ac_build_gather_values(&ctx->ac, src, num_components);
break;
case nir_op_f2i:
src[0] = to_float(ctx, src[0]);
@@ -2005,7 +1964,7 @@ static LLVMValueRef visit_load_ubo_buffer(struct
nir_to_llvm_context *ctx,
}
- ret = build_gather_values(ctx, results, instr->num_components);
+ ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
return LLVMBuildBitCast(ctx->builder, ret,
get_def_type(ctx, &instr->dest.ssa), "");
}
@@ -2079,8 +2038,8 @@ static LLVMValueRef visit_load_var(struct
nir_to_llvm_context *ctx,
unsigned count = glsl_count_attribute_slots(
instr->variables[0]->var->type,
ctx->stage ==
MESA_SHADER_VERTEX);
- LLVMValueRef tmp_vec =
Mesa (master): ac/nir: use ac_emit_fdiv throughout
Module: Mesa
Branch: master
Commit: 1007047ca1086eef89f65c87e7ea2371c4f80513
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1007047ca1086eef89f65c87e7ea2371c4f80513
Author: Nicolai Hähnle
Date: Tue Jan 10 15:46:17 2017 +0100
ac/nir: use ac_emit_fdiv throughout
... and eliminate emit_fdiv and nir_to_llvm_context::fpmath_md_*, which
are now unused.
Reviewed-by: Bas Nieuwenhuizen
Reviewed-by: Marek Olšák
---
src/amd/common/ac_nir_to_llvm.c | 28 ++--
1 file changed, 6 insertions(+), 22 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index f650937..d21dfef 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -113,10 +113,8 @@ struct nir_to_llvm_context {
unsigned range_md_kind;
unsigned uniform_md_kind;
- unsigned fpmath_md_kind;
unsigned invariant_load_md_kind;
LLVMValueRef empty_md;
- LLVMValueRef fpmath_md_2p5_ulp;
gl_shader_stage stage;
LLVMValueRef lds;
@@ -583,10 +581,7 @@ static void setup_types(struct nir_to_llvm_context *ctx)
LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
- ctx->fpmath_md_kind = LLVMGetMDKindIDInContext(ctx->context, "fpmath",
6);
-
args[0] = LLVMConstReal(ctx->f32, 2.5);
- ctx->fpmath_md_2p5_ulp = LLVMMDNodeInContext(ctx->context, args, 1);
}
static int get_llvm_num_components(LLVMValueRef value)
@@ -1193,17 +1188,6 @@ static LLVMValueRef emit_ddxy_interp(
return ac_build_gather_values(&ctx->ac, result, 4);
}
-static LLVMValueRef emit_fdiv(struct nir_to_llvm_context *ctx,
- LLVMValueRef num,
- LLVMValueRef den)
-{
- LLVMValueRef ret = LLVMBuildFDiv(ctx->builder, num, den, "");
-
- if (!LLVMIsConstant(ret))
- LLVMSetMetadata(ret, ctx->fpmath_md_kind,
ctx->fpmath_md_2p5_ulp);
- return ret;
-}
-
static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
{
LLVMValueRef src[4], result = NULL;
@@ -1273,7 +1257,7 @@ static void visit_alu(struct nir_to_llvm_context *ctx,
nir_alu_instr *instr)
case nir_op_fmod:
src[0] = to_float(ctx, src[0]);
src[1] = to_float(ctx, src[1]);
- result = emit_fdiv(ctx, src[0], src[1]);
+ result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
result = emit_intrin_1f_param(ctx, "llvm.floor.f32", result);
result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
result = LLVMBuildFSub(ctx->builder, src[0], result, "");
@@ -1297,11 +1281,11 @@ static void visit_alu(struct nir_to_llvm_context *ctx,
nir_alu_instr *instr)
case nir_op_fdiv:
src[0] = to_float(ctx, src[0]);
src[1] = to_float(ctx, src[1]);
- result = emit_fdiv(ctx, src[0], src[1]);
+ result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
break;
case nir_op_frcp:
src[0] = to_float(ctx, src[0]);
- result = emit_fdiv(ctx, ctx->f32one, src[0]);
+ result = ac_emit_fdiv(&ctx->ac, ctx->f32one, src[0]);
break;
case nir_op_iand:
result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
@@ -1408,7 +1392,7 @@ static void visit_alu(struct nir_to_llvm_context *ctx,
nir_alu_instr *instr)
break;
case nir_op_frsq:
result = emit_intrin_1f_param(ctx, "llvm.sqrt.f32", src[0]);
- result = emit_fdiv(ctx, ctx->f32one, result);
+ result = ac_emit_fdiv(&ctx->ac, ctx->f32one, result);
break;
case nir_op_fpow:
result = emit_intrin_2f_param(ctx, "llvm.pow.f32", src[0],
src[1]);
@@ -1637,7 +1621,7 @@ static LLVMValueRef radv_lower_gather4_integer(struct
nir_to_llvm_context *ctx,
half_texel[c] = LLVMBuildExtractElement(ctx->builder,
size,
LLVMConstInt(ctx->i32, c, false), "");
half_texel[c] = LLVMBuildUIToFP(ctx->builder,
half_texel[c], ctx->f32, "");
- half_texel[c] = emit_fdiv(ctx, ctx->f32one,
half_texel[c]);
+ half_texel[c] = ac_emit_fdiv(&ctx->ac, ctx->f32one,
half_texel[c]);
half_texel[c] = LLVMBuildFMul(ctx->builder,
half_texel[c],
LLVMConstReal(ctx->f32,
-0.5), "");
}
@@ -3837,7 +3821,7 @@ handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
for(int i = 0; i < 3; ++i)
inputs[i] = ctx->frag_pos[i];
- inputs[3] = emit_fdiv(ctx, ctx->f32one,
ctx->frag_pos[3]);
+
Mesa (master): ac/nir: use ac_emit_llvm_intrinsic throughout
Module: Mesa
Branch: master
Commit: 2c9d26a3564c215695758b4d6b44a838b7a286d4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c9d26a3564c215695758b4d6b44a838b7a286d4
Author: Nicolai Hähnle
Date: Tue Jan 10 15:39:56 2017 +0100
ac/nir: use ac_emit_llvm_intrinsic throughout
... by straight-forward search & replace, and eliminate
emit_llvm_intrinsic.
Reviewed-by: Bas Nieuwenhuizen
Reviewed-by: Marek Olšák
---
src/amd/common/ac_nir_to_llvm.c | 120 ++--
1 file changed, 41 insertions(+), 79 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index ae21be4..2a5f916 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -142,10 +142,6 @@ struct ac_tex_info {
bool has_offset;
};
-static LLVMValueRef
-emit_llvm_intrinsic(struct nir_to_llvm_context *ctx, const char *name,
-LLVMTypeRef return_type, LLVMValueRef *params,
-unsigned param_count, unsigned attr_mask);
static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
nir_deref_var *deref,
enum desc_type desc_type);
@@ -797,7 +793,7 @@ static LLVMValueRef emit_intrin_1f_param(struct
nir_to_llvm_context *ctx,
LLVMValueRef params[] = {
to_float(ctx, src0),
};
- return emit_llvm_intrinsic(ctx, intrin, ctx->f32, params, 1,
AC_FUNC_ATTR_READNONE);
+ return ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->f32, params, 1,
AC_FUNC_ATTR_READNONE);
}
static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
@@ -808,7 +804,7 @@ static LLVMValueRef emit_intrin_2f_param(struct
nir_to_llvm_context *ctx,
to_float(ctx, src0),
to_float(ctx, src1),
};
- return emit_llvm_intrinsic(ctx, intrin, ctx->f32, params, 2,
AC_FUNC_ATTR_READNONE);
+ return ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->f32, params, 2,
AC_FUNC_ATTR_READNONE);
}
static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
@@ -820,7 +816,7 @@ static LLVMValueRef emit_intrin_3f_param(struct
nir_to_llvm_context *ctx,
to_float(ctx, src1),
to_float(ctx, src2),
};
- return emit_llvm_intrinsic(ctx, intrin, ctx->f32, params, 3,
AC_FUNC_ATTR_READNONE);
+ return ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->f32, params, 3,
AC_FUNC_ATTR_READNONE);
}
static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
@@ -846,13 +842,13 @@ static LLVMValueRef emit_find_lsb(struct
nir_to_llvm_context *ctx,
*/
LLVMConstInt(ctx->i32, 1, false),
};
- return emit_llvm_intrinsic(ctx, "llvm.cttz.i32", ctx->i32, params, 2,
AC_FUNC_ATTR_READNONE);
+ return ac_emit_llvm_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32,
params, 2, AC_FUNC_ATTR_READNONE);
}
static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
LLVMValueRef src0)
{
- LLVMValueRef msb = emit_llvm_intrinsic(ctx, "llvm.AMDGPU.flbit.i32",
+ LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac,
"llvm.AMDGPU.flbit.i32",
ctx->i32, &src0, 1,
AC_FUNC_ATTR_READNONE);
@@ -878,7 +874,7 @@ static LLVMValueRef emit_ufind_msb(struct
nir_to_llvm_context *ctx,
src0,
ctx->i32one,
};
- LLVMValueRef msb = emit_llvm_intrinsic(ctx, "llvm.ctlz.i32",
+ LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctlz.i32",
ctx->i32, args, ARRAY_SIZE(args),
AC_FUNC_ATTR_READNONE);
@@ -942,7 +938,7 @@ static LLVMValueRef emit_ffract(struct nir_to_llvm_context
*ctx,
LLVMValueRef params[] = {
fsrc0,
};
- LLVMValueRef floor = emit_llvm_intrinsic(ctx, intr,
+ LLVMValueRef floor = ac_emit_llvm_intrinsic(&ctx->ac, intr,
ctx->f32, params, 1,
AC_FUNC_ATTR_READNONE);
return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
@@ -959,7 +955,7 @@ static LLVMValueRef emit_uint_carry(struct
nir_to_llvm_context *ctx,
ret_type = LLVMStructTypeInContext(ctx->context, types,
2, true);
- res = emit_llvm_intrinsic(ctx, intrin, ret_type,
+ res = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ret_type,
params, 2, AC_FUNC_ATTR_READNONE);
res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
@@ -1005,7 +1001,7 @@ static LLVMValueRef emit_bitfield_extract(struct
nir_to_llvm_context *ctx,
{
LLVMValueRef result;
LLVMValueRef icond = LLVMBuildICmp(ctx->build
Mesa (master): radeonsi: only touch first three coordinates in si_prepare_cube_coords
Module: Mesa
Branch: master
Commit: 0ee1ee5fbb93e76dd96c4ccbd45c82ba8382682c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ee1ee5fbb93e76dd96c4ccbd45c82ba8382682c
Author: Nicolai Hähnle
Date: Tue Jan 10 14:54:22 2017 +0100
radeonsi: only touch first three coordinates in si_prepare_cube_coords
Sourcing coords_arg[4] is actually never correct, since bias is handled
differently in tex_fetch_args anyway.
Reviewed-by: Bas Nieuwenhuizen
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
index c410a8b..11bd45d 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
@@ -1027,7 +1027,7 @@ void si_prepare_cube_coords(struct lp_build_tgsi_context
*bld_base,
LLVMBuilderRef builder = gallivm->builder;
LLVMTypeRef type = bld_base->base.elem_type;
struct cube_selection_coords selcoords;
- LLVMValueRef coords[4];
+ LLVMValueRef coords[3];
LLVMValueRef invma;
build_cube_intrinsic(gallivm, coords_arg, &selcoords);
@@ -1100,16 +1100,5 @@ void si_prepare_cube_coords(struct lp_build_tgsi_context
*bld_base,
coords_arg[3],
lp_build_const_float(gallivm, 8.0), coords[2]);
}
- /* Preserve compare/lod/bias. Put it in coords.w. */
- if (opcode == TGSI_OPCODE_TEX2 ||
- opcode == TGSI_OPCODE_TXB2 ||
- opcode == TGSI_OPCODE_TXL2) {
- coords[3] = coords_arg[4];
- } else if (opcode == TGSI_OPCODE_TXB ||
- opcode == TGSI_OPCODE_TXL ||
- target == TGSI_TEXTURE_SHADOWCUBE) {
- coords[3] = coords_arg[3];
- }
-
memcpy(coords_arg, coords, sizeof(coords));
}
___
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Mesa (master): amd/common: unify cube map coordinate handling between radeonsi and radv
Module: Mesa
Branch: master
Commit: a0ce09b4b2a3063e49a02de3d12096cf462d10a3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0ce09b4b2a3063e49a02de3d12096cf462d10a3
Author: Nicolai Hähnle
Date: Tue Jan 10 15:35:27 2017 +0100
amd/common: unify cube map coordinate handling between radeonsi and radv
Code is taken from a combination of radv (for the more basic functions,
to avoid gallivm dependencies) and radeonsi (for the new and improved
derivative calculations).
v2: add 0.5 offset to tex coords only after derivative calculation
v3:
- really only touch the first three coordinates
- rebase on the removal of the 1.5 --> 0.5 offset change
Reviewed-by: Bas Nieuwenhuizen (v2)
Reviewed-by: Marek Olšák
---
src/amd/common/ac_llvm_util.c | 364 +
src/amd/common/ac_llvm_util.h | 57
src/amd/common/ac_nir_to_llvm.c| 204 +---
src/gallium/drivers/radeonsi/si_shader.c | 6 +-
src/gallium/drivers/radeonsi/si_shader_internal.h | 2 +
.../drivers/radeonsi/si_shader_tgsi_setup.c| 4 +
6 files changed, 440 insertions(+), 197 deletions(-)
diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c
index a8408dd..770e3bd 100644
--- a/src/amd/common/ac_llvm_util.c
+++ b/src/amd/common/ac_llvm_util.c
@@ -32,6 +32,9 @@
#include
#include
+#include "util/bitscan.h"
+#include "util/macros.h"
+
static void ac_init_llvm_target()
{
#if HAVE_LLVM < 0x0307
@@ -140,3 +143,364 @@ LLVMTargetMachineRef ac_create_target_machine(enum
radeon_family family)
return tm;
}
+
+/* Initialize module-independent parts of the context.
+ *
+ * The caller is responsible for initializing ctx::module and ctx::builder.
+ */
+void
+ac_llvm_context_init(struct ac_llvm_context *ctx, LLVMContextRef context)
+{
+ LLVMValueRef args[1];
+
+ ctx->context = context;
+ ctx->module = NULL;
+ ctx->builder = NULL;
+
+ ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
+ ctx->f32 = LLVMFloatTypeInContext(ctx->context);
+
+ ctx->fpmath_md_kind = LLVMGetMDKindIDInContext(ctx->context, "fpmath",
6);
+
+ args[0] = LLVMConstReal(ctx->f32, 2.5);
+ ctx->fpmath_md_2p5_ulp = LLVMMDNodeInContext(ctx->context, args, 1);
+}
+
+#if HAVE_LLVM < 0x0400
+static LLVMAttribute ac_attr_to_llvm_attr(enum ac_func_attr attr)
+{
+ switch (attr) {
+ case AC_FUNC_ATTR_ALWAYSINLINE: return LLVMAlwaysInlineAttribute;
+ case AC_FUNC_ATTR_BYVAL: return LLVMByValAttribute;
+ case AC_FUNC_ATTR_INREG: return LLVMInRegAttribute;
+ case AC_FUNC_ATTR_NOALIAS: return LLVMNoAliasAttribute;
+ case AC_FUNC_ATTR_NOUNWIND: return LLVMNoUnwindAttribute;
+ case AC_FUNC_ATTR_READNONE: return LLVMReadNoneAttribute;
+ case AC_FUNC_ATTR_READONLY: return LLVMReadOnlyAttribute;
+ default:
+ fprintf(stderr, "Unhandled function attribute: %x\n", attr);
+ return 0;
+ }
+}
+
+#else
+
+static const char *attr_to_str(enum ac_func_attr attr)
+{
+ switch (attr) {
+ case AC_FUNC_ATTR_ALWAYSINLINE: return "alwaysinline";
+ case AC_FUNC_ATTR_BYVAL: return "byval";
+ case AC_FUNC_ATTR_INREG: return "inreg";
+ case AC_FUNC_ATTR_NOALIAS: return "noalias";
+ case AC_FUNC_ATTR_NOUNWIND: return "nounwind";
+ case AC_FUNC_ATTR_READNONE: return "readnone";
+ case AC_FUNC_ATTR_READONLY: return "readonly";
+ default:
+ fprintf(stderr, "Unhandled function attribute: %x\n", attr);
+ return 0;
+ }
+}
+
+#endif
+
+void
+ac_add_function_attr(LLVMValueRef function,
+ int attr_idx,
+ enum ac_func_attr attr)
+{
+
+#if HAVE_LLVM < 0x0400
+ LLVMAttribute llvm_attr = ac_attr_to_llvm_attr(attr);
+ if (attr_idx == -1) {
+ LLVMAddFunctionAttr(function, llvm_attr);
+ } else {
+ LLVMAddAttribute(LLVMGetParam(function, attr_idx - 1), llvm_attr);
+ }
+#else
+ LLVMContextRef context =
LLVMGetModuleContext(LLVMGetGlobalParent(function));
+ const char *attr_name = attr_to_str(attr);
+ unsigned kind_id = LLVMGetEnumAttributeKindForName(attr_name,
+ strlen(attr_name));
+ LLVMAttributeRef llvm_attr = LLVMCreateEnumAttribute(context, kind_id, 0);
+ LLVMAddAttributeAtIndex(function, attr_idx, llvm_attr);
+#endif
+}
+
+LLVMValueRef
+ac_emit_llvm_intrinsic(struct ac_llvm_context *ctx, const char *name,
+ LLVMTypeRef return_type, LLVMValueRef *params,
+ unsigned param_count, unsigned attrib_mask)
+{
+ LLVMValueRef function;
+
+ function = LLVMGetNamedFunction(ctx->module, name);
+ if (!function) {
+ LLVMTypeRef param_types[32], function_type;
+ unsigned i;
+
+ assert(param_count <= 32);
+
+ for (i = 0; i < param_count; ++i) {
+ assert(params[i]);
+ param_types[i] = LLVMTypeOf(params[i]
Mesa (master): radeonsi: communicate cube map coordinates more explicitly
Module: Mesa
Branch: master
Commit: e01deee42f1a7b939be15e96f9a037145d570c62
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e01deee42f1a7b939be15e96f9a037145d570c62
Author: Nicolai Hähnle
Date: Tue Jan 10 10:57:48 2017 +0100
radeonsi: communicate cube map coordinates more explicitly
v2: fix compile error that snuck in during rebase
Reviewed-by: Bas Nieuwenhuizen
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c | 76 +--
1 file changed, 43 insertions(+), 33 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
index 0a49bc2..1c37345 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
@@ -907,23 +907,33 @@ void si_shader_context_init_alu(struct
lp_build_tgsi_context *bld_base)
bld_base->op_actions[TGSI_OPCODE_I64DIV].emit = emit_idiv;
}
-static LLVMValueRef build_cube_intrinsic(struct gallivm_state *gallivm,
-LLVMValueRef in[3])
+/* Coordinates for cube map selection. sc, tc, and ma are as in Table 8.27
+ * of the OpenGL 4.5 (Compatibility Profile) specification, except ma is
+ * already multiplied by two. id is the cube face number.
+ */
+struct cube_selection_coords {
+ LLVMValueRef stc[2];
+ LLVMValueRef ma;
+ LLVMValueRef id;
+};
+
+static void build_cube_intrinsic(struct gallivm_state *gallivm,
+LLVMValueRef in[3],
+struct cube_selection_coords *out)
{
+ LLVMBuilderRef builder = gallivm->builder;
+
if (HAVE_LLVM >= 0x0309) {
LLVMTypeRef f32 = LLVMTypeOf(in[0]);
- LLVMValueRef out[4];
- out[0] = lp_build_intrinsic(gallivm->builder,
"llvm.amdgcn.cubetc",
+ out->stc[1] = lp_build_intrinsic(builder, "llvm.amdgcn.cubetc",
f32, in, 3, LP_FUNC_ATTR_READNONE);
- out[1] = lp_build_intrinsic(gallivm->builder,
"llvm.amdgcn.cubesc",
+ out->stc[0] = lp_build_intrinsic(builder, "llvm.amdgcn.cubesc",
f32, in, 3, LP_FUNC_ATTR_READNONE);
- out[2] = lp_build_intrinsic(gallivm->builder,
"llvm.amdgcn.cubema",
+ out->ma = lp_build_intrinsic(builder, "llvm.amdgcn.cubema",
f32, in, 3, LP_FUNC_ATTR_READNONE);
- out[3] = lp_build_intrinsic(gallivm->builder,
"llvm.amdgcn.cubeid",
+ out->id = lp_build_intrinsic(builder, "llvm.amdgcn.cubeid",
f32, in, 3, LP_FUNC_ATTR_READNONE);
-
- return lp_build_gather_values(gallivm, out, 4);
} else {
LLVMValueRef c[4] = {
in[0],
@@ -933,9 +943,19 @@ static LLVMValueRef build_cube_intrinsic(struct
gallivm_state *gallivm,
};
LLVMValueRef vec = lp_build_gather_values(gallivm, c, 4);
- return lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.cube",
+ LLVMValueRef tmp =
+ lp_build_intrinsic(builder, "llvm.AMDGPU.cube",
LLVMTypeOf(vec), &vec, 1,
LP_FUNC_ATTR_READNONE);
+
+ out->stc[1] = LLVMBuildExtractElement(builder, tmp,
+ lp_build_const_int32(gallivm, 0), "");
+ out->stc[0] = LLVMBuildExtractElement(builder, tmp,
+ lp_build_const_int32(gallivm, 1), "");
+ out->ma = LLVMBuildExtractElement(builder, tmp,
+ lp_build_const_int32(gallivm, 2), "");
+ out->id = LLVMBuildExtractElement(builder, tmp,
+ lp_build_const_int32(gallivm, 3), "");
}
}
@@ -945,36 +965,26 @@ static void si_llvm_cube_to_2d_coords(struct
lp_build_tgsi_context *bld_base,
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMBuilderRef builder = gallivm->builder;
LLVMTypeRef type = bld_base->base.elem_type;
- LLVMValueRef coords[4];
+ struct cube_selection_coords coords;
+ LLVMValueRef invma;
LLVMValueRef mad_args[3];
- LLVMValueRef v;
- unsigned i;
-
- v = build_cube_intrinsic(gallivm, in);
- for (i = 0; i < 4; ++i)
- coords[i] = LLVMBuildExtractElement(builder, v,
-
lp_build_const_int32(gallivm, i), "");
+ build_cube_intrinsic(gallivm, in, &coords);
- coords[2] = lp_build_intrinsic(builder, "llvm.fabs.f32",
- type, &coords[2], 1, LP_FUNC_ATTR_READNONE);
- coords[2] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_RCP,
coords[2]);
+ invma = lp_build_intr
Mesa (master): radeonsi: remove unused si_llvm_cube_to_2d_coords
Module: Mesa
Branch: master
Commit: 9f590ee9d9033d72cba70a774902ee2472b9414f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f590ee9d9033d72cba70a774902ee2472b9414f
Author: Nicolai Hähnle
Date: Tue Jan 10 13:16:11 2017 +0100
radeonsi: remove unused si_llvm_cube_to_2d_coords
Reviewed-by: Bas Nieuwenhuizen
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c | 28 ---
1 file changed, 28 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
index c0c92a8..c410a8b 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
@@ -1015,34 +1015,6 @@ static void build_cube_select(LLVMBuilderRef builder,
*out_ma = LLVMBuildFMul(builder, tmp, sgn, "");
}
-static void si_llvm_cube_to_2d_coords(struct lp_build_tgsi_context *bld_base,
- LLVMValueRef *in, LLVMValueRef *out)
-{
- struct gallivm_state *gallivm = bld_base->base.gallivm;
- LLVMBuilderRef builder = gallivm->builder;
- LLVMTypeRef type = bld_base->base.elem_type;
- struct cube_selection_coords coords;
- LLVMValueRef invma;
- LLVMValueRef mad_args[3];
-
- build_cube_intrinsic(gallivm, in, &coords);
-
- invma = lp_build_intrinsic(builder, "llvm.fabs.f32",
- type, &coords.ma, 1, LP_FUNC_ATTR_READNONE);
- invma = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_RCP, invma);
-
- mad_args[1] = invma;
- mad_args[2] = LLVMConstReal(type, 1.5);
-
- for (int i = 0; i < 2; ++i) {
- mad_args[0] = coords.stc[i];
- out[i] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
- mad_args[0], mad_args[1], mad_args[2]);
- }
-
- out[2] = coords.id;
-}
-
void si_prepare_cube_coords(struct lp_build_tgsi_context *bld_base,
struct lp_build_emit_data *emit_data,
LLVMValueRef *coords_arg,
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Mesa (master): radeonsi: restrict cube map derivative computations to the correct plane
Module: Mesa
Branch: master
Commit: 205ad5234af5a3a5dd6f584b0814cd5a9ce7f10c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=205ad5234af5a3a5dd6f584b0814cd5a9ce7f10c
Author: Nicolai Hähnle
Date: Tue Jan 10 11:47:22 2017 +0100
radeonsi: restrict cube map derivative computations to the correct plane
As remarked by the comment in the original code, the old algorithm fails when
(tc + deriv) points at a different cube face. Instead, simply project the
derivative directly to the plane of the selected cube face.
The new code is based on exactly differentiating (using the chain rule)
the projection onto a plane corresponding to a fixed cube map face (which
is still selected in the usual way based on the texture coordinate itself).
The computations end up fairly involved, but we do save two reciprocal
computations.
Fixes GL45-CTS.texture_cube_map_array.sampling.
v2: add 0.5 offset to tex coords only after derivative calculation
v3: go back to 1.5 offset
Reviewed-by: Bas Nieuwenhuizen (v2)
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c | 130 ++
1 file changed, 107 insertions(+), 23 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
index 1c37345..c0c92a8 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
@@ -959,6 +959,62 @@ static void build_cube_intrinsic(struct gallivm_state
*gallivm,
}
}
+/**
+ * Build a manual selection sequence for cube face sc/tc coordinates and
+ * major axis vector (multiplied by 2 for consistency) for the given
+ * vec3 \p coords, for the face implied by \p selcoords.
+ *
+ * For the major axis, we always adjust the sign to be in the direction of
+ * selcoords.ma; i.e., a positive out_ma means that coords is pointed towards
+ * the selcoords major axis.
+ */
+static void build_cube_select(LLVMBuilderRef builder,
+ const struct cube_selection_coords *selcoords,
+ const LLVMValueRef *coords,
+ LLVMValueRef *out_st,
+ LLVMValueRef *out_ma)
+{
+ LLVMTypeRef f32 = LLVMTypeOf(coords[0]);
+ LLVMValueRef is_ma_positive;
+ LLVMValueRef sgn_ma;
+ LLVMValueRef is_ma_z, is_not_ma_z;
+ LLVMValueRef is_ma_y;
+ LLVMValueRef is_ma_x;
+ LLVMValueRef sgn;
+ LLVMValueRef tmp;
+
+ is_ma_positive = LLVMBuildFCmp(builder, LLVMRealUGE,
+ selcoords->ma, LLVMConstReal(f32, 0.0), "");
+ sgn_ma = LLVMBuildSelect(builder, is_ma_positive,
+ LLVMConstReal(f32, 1.0), LLVMConstReal(f32, -1.0), "");
+
+ is_ma_z = LLVMBuildFCmp(builder, LLVMRealUGE, selcoords->id,
LLVMConstReal(f32, 4.0), "");
+ is_not_ma_z = LLVMBuildNot(builder, is_ma_z, "");
+ is_ma_y = LLVMBuildAnd(builder, is_not_ma_z,
+ LLVMBuildFCmp(builder, LLVMRealUGE, selcoords->id,
LLVMConstReal(f32, 2.0), ""), "");
+ is_ma_x = LLVMBuildAnd(builder, is_not_ma_z, LLVMBuildNot(builder,
is_ma_y, ""), "");
+
+ /* Select sc */
+ tmp = LLVMBuildSelect(builder, is_ma_z, coords[2], coords[0], "");
+ sgn = LLVMBuildSelect(builder, is_ma_y, LLVMConstReal(f32, 1.0),
+ LLVMBuildSelect(builder, is_ma_x, sgn_ma,
+ LLVMBuildFNeg(builder, sgn_ma, ""), ""), "");
+ out_st[0] = LLVMBuildFMul(builder, tmp, sgn, "");
+
+ /* Select tc */
+ tmp = LLVMBuildSelect(builder, is_ma_y, coords[2], coords[1], "");
+ sgn = LLVMBuildSelect(builder, is_ma_y, LLVMBuildFNeg(builder, sgn_ma,
""),
+ LLVMConstReal(f32, -1.0), "");
+ out_st[1] = LLVMBuildFMul(builder, tmp, sgn, "");
+
+ /* Select ma */
+ tmp = LLVMBuildSelect(builder, is_ma_z, coords[2],
+ LLVMBuildSelect(builder, is_ma_y, coords[1], coords[0], ""),
"");
+ sgn = LLVMBuildSelect(builder, is_ma_positive,
+ LLVMConstReal(f32, 2.0), LLVMConstReal(f32, -2.0), "");
+ *out_ma = LLVMBuildFMul(builder, tmp, sgn, "");
+}
+
static void si_llvm_cube_to_2d_coords(struct lp_build_tgsi_context *bld_base,
LLVMValueRef *in, LLVMValueRef *out)
{
@@ -997,10 +1053,21 @@ void si_prepare_cube_coords(struct lp_build_tgsi_context
*bld_base,
unsigned opcode = emit_data->inst->Instruction.Opcode;
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMBuilderRef builder = gallivm->builder;
+ LLVMTypeRef type = bld_base->base.elem_type;
+ struct cube_selection_coords selcoords;
LLVMValueRef coords[4];
- unsigned i;
+ LLVMValueRef invma;
- si_llvm_cube_to_2d_coords(bld_base, coords_arg, coords);
+ build_cube_intrinsic(gallivm, coords_arg, &selcoords);
+
+ invma = lp_build_intrinsic(builder, "llvm.fabs.f32",
+
Mesa (master): ac/debug: move .gitignore for sid_tables.h too
Module: Mesa
Branch: master
Commit: c728051131721d0121dc92376f2244f341bd74b4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c728051131721d0121dc92376f2244f341bd74b4
Author: Grazvydas Ignotas
Date: Thu Jan 12 01:58:59 2017 +0200
ac/debug: move .gitignore for sid_tables.h too
b838f642 "ac/debug: Move sid_tables.h generation to common code." moved
sid_tables.h but forgot the corresponding .gitignore.
Signed-off-by: Grazvydas Ignotas
Reviewed-by: Nicolai Hähnle
---
src/{gallium/drivers/radeonsi => amd/common}/.gitignore | 0
1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/.gitignore b/src/amd/common/.gitignore
similarity index 100%
rename from src/gallium/drivers/radeonsi/.gitignore
rename to src/amd/common/.gitignore
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Mesa (master): nir/gcm: Fix a typo in a comment
Module: Mesa Branch: master Commit: 08eced3cfd8cb3b5d7f7de1098dabcfdf7dd3650 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=08eced3cfd8cb3b5d7f7de1098dabcfdf7dd3650 Author: Jason Ekstrand Date: Thu Jan 12 14:09:30 2017 -0800 nir/gcm: Fix a typo in a comment Reported-by: Matt Turner --- src/compiler/nir/nir_opt_gcm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_opt_gcm.c b/src/compiler/nir/nir_opt_gcm.c index 9d7f59c..cff2315 100644 --- a/src/compiler/nir/nir_opt_gcm.c +++ b/src/compiler/nir/nir_opt_gcm.c @@ -320,7 +320,7 @@ gcm_schedule_late_def(nir_ssa_def *def, void *void_state) if (lca == NULL) return true; - /* We know have the LCA of all of the uses. If our invariants hold, + /* We now have the LCA of all of the uses. If our invariants hold, * this is dominated by the block that we chose when scheduling early. * We now walk up the dominance tree and pick the lowest block that is * as far outside loops as we can get. ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nir/gcm: Rework the schedule late loop
Module: Mesa
Branch: master
Commit: 087e172179be3b9be89955cd012a26ea770ee9eb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=087e172179be3b9be89955cd012a26ea770ee9eb
Author: Jason Ekstrand
Date: Thu Dec 1 13:51:03 2016 -0800
nir/gcm: Rework the schedule late loop
This fixes a bug in code motion that occurred when the best block is the
same as the schedule early block. In this case, because we're checking
(lca != def->parent_instr->block) at the top of the loop, we never get to
the check for loop depth so we wouldn't move it out of the loop. This
commit reworks the loop to be a simple for loop up the dominator chain and
we place the (lca != def->parent_instr->block) check at the end of the
loop.
Reviewed-by: Matt Turner
---
src/compiler/nir/nir_opt_gcm.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/src/compiler/nir/nir_opt_gcm.c b/src/compiler/nir/nir_opt_gcm.c
index 77eb8e6..9d7f59c 100644
--- a/src/compiler/nir/nir_opt_gcm.c
+++ b/src/compiler/nir/nir_opt_gcm.c
@@ -326,12 +326,13 @@ gcm_schedule_late_def(nir_ssa_def *def, void *void_state)
* as far outside loops as we can get.
*/
nir_block *best = lca;
- while (lca != def->parent_instr->block) {
- assert(lca);
- if (state->blocks[lca->index].loop_depth <
+ for (nir_block *block = lca; block != NULL; block = block->imm_dom) {
+ if (state->blocks[block->index].loop_depth <
state->blocks[best->index].loop_depth)
- best = lca;
- lca = lca->imm_dom;
+ best = block;
+
+ if (block == def->parent_instr->block)
+ break;
}
def->parent_instr->block = best;
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Mesa (master): ac, radeonsi: automake: add missing builddir include
Module: Mesa Branch: master Commit: c90f921273d4d9108f12bbea9f0c42f6ca12d770 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c90f921273d4d9108f12bbea9f0c42f6ca12d770 Author: Emil Velikov Date: Thu Jan 12 21:54:03 2017 + ac, radeonsi: automake: add missing builddir include The generated file is correctly stored in the builddir as of earlier commit. Yet the commit forgot to add the respective include flag thus the compiler would error out failing to find sid_tables.h Bugzila: https://bugs.freedesktop.org/show_bug.cgi?id=99389 Fixes: d1dc22eb466 "ac: automake: rework sid_tables.h generation" Signed-off-by: Emil Velikov --- src/amd/Makefile.common.am | 1 + src/gallium/drivers/radeonsi/Makefile.am | 1 + 2 files changed, 2 insertions(+) diff --git a/src/amd/Makefile.common.am b/src/amd/Makefile.common.am index b5fce2b..ab69fc3 100644 --- a/src/amd/Makefile.common.am +++ b/src/amd/Makefile.common.am @@ -30,6 +30,7 @@ common_libamd_common_la_CPPFLAGS = \ -I$(top_srcdir)/include \ -I$(top_builddir)/src \ -I$(top_srcdir)/src \ + -I$(top_builddir)/src/amd/common \ -I$(top_srcdir)/src/amd/common \ -I$(top_builddir)/src/compiler \ -I$(top_builddir)/src/compiler/nir \ diff --git a/src/gallium/drivers/radeonsi/Makefile.am b/src/gallium/drivers/radeonsi/Makefile.am index 00c8a32..2d5c1a3 100644 --- a/src/gallium/drivers/radeonsi/Makefile.am +++ b/src/gallium/drivers/radeonsi/Makefile.am @@ -25,6 +25,7 @@ include $(top_srcdir)/src/gallium/Automake.inc AM_CFLAGS = \ $(GALLIUM_DRIVER_CFLAGS) \ + -I$(top_builddir)/src/amd/common \ -I$(top_srcdir)/src/amd/common \ $(RADEON_CFLAGS) \ $(LLVM_CFLAGS) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glx: Add missing glproto dependency for gallium-xlib glx
Module: Mesa Branch: master Commit: e9a4ec4bd806107223b4e3f656071de3a08756a0 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9a4ec4bd806107223b4e3f656071de3a08756a0 Author: Chuck Atkins Date: Fri Jan 6 08:27:44 2017 -0500 glx: Add missing glproto dependency for gallium-xlib glx Cc: mesa-sta...@lists.freedesktop.org Cc: Bruce Cherniak Signed-of-by: Chuck Atkins Reviewed-by: Bruce Cherniak Reviewed-by: Emil Velikov --- configure.ac| 4 +++- src/gallium/state_trackers/glx/xlib/Makefile.am | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index 49c5e25..bc92fb5 100644 --- a/configure.ac +++ b/configure.ac @@ -1598,6 +1598,9 @@ AC_ARG_ENABLE([driglx-direct], dnl dnl libGL configuration per driver dnl +if test "x$enable_glx" != xno; then +PKG_CHECK_MODULES([GLPROTO], [glproto >= $GLPROTO_REQUIRED]) +fi case "x$enable_glx" in xxlib | xgallium-xlib) # Xlib-based GLX @@ -1611,7 +1614,6 @@ xxlib | xgallium-xlib) ;; xdri) # DRI-based GLX -PKG_CHECK_MODULES([GLPROTO], [glproto >= $GLPROTO_REQUIRED]) # find the DRI deps for libGL dri_modules="x11 xext xdamage xfixes x11-xcb xcb xcb-glx >= $XCBGLX_REQUIRED" diff --git a/src/gallium/state_trackers/glx/xlib/Makefile.am b/src/gallium/state_trackers/glx/xlib/Makefile.am index a7e6c0c..112030be 100644 --- a/src/gallium/state_trackers/glx/xlib/Makefile.am +++ b/src/gallium/state_trackers/glx/xlib/Makefile.am @@ -25,6 +25,7 @@ include $(top_srcdir)/src/gallium/Automake.inc AM_CFLAGS = \ $(GALLIUM_CFLAGS) \ + $(GLPROTO_CFLAGS) \ $(X11_INCLUDES) AM_CPPFLAGS = \ -I$(top_srcdir)/include \ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: Call nir_lower_constant_initializers.
Module: Mesa Branch: master Commit: 65cbb993d33976d9ee24eff01ade8ed9013617ca URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=65cbb993d33976d9ee24eff01ade8ed9013617ca Author: Bas Nieuwenhuizen Date: Sun Jan 8 23:17:38 2017 +0100 radv: Call nir_lower_constant_initializers. Port of c5d664f9dc2d281c74844cef36ecb9f5862a8f6a "anv/pipeline: Call nir_lower_constant_initializers" Signed-off-by: Bas Nieuwenhuizen Cc: Reviewed-by: Timothy Arceri --- src/amd/vulkan/radv_pipeline.c | 13 + 1 file changed, 13 insertions(+) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 03603f5..d818938 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -205,6 +205,13 @@ radv_shader_compile_to_nir(struct radv_device *device, free(spec_entries); + /* We have to lower away local constant initializers right before we +* inline functions. That way they get properly initialized at the top +* of the function and not at the top of its caller. +*/ + nir_lower_constant_initializers(nir, nir_var_local); + nir_validate_shader(nir); + nir_lower_returns(nir); nir_validate_shader(nir); @@ -224,6 +231,12 @@ radv_shader_compile_to_nir(struct radv_device *device, nir_var_system_value); nir_validate_shader(nir); + /* Now that we've deleted all but the main function, we can go ahead and +* lower the rest of the constant initializers. +*/ + nir_lower_constant_initializers(nir, ~0); + nir_validate_shader(nir); + nir_lower_system_values(nir); nir_validate_shader(nir); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: Call NIR passes using NIR_PASS_V.
Module: Mesa
Branch: master
Commit: 8aaca3820cfc98705215e31b751d818154437fe4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8aaca3820cfc98705215e31b751d818154437fe4
Author: Bas Nieuwenhuizen
Date: Sun Jan 8 23:23:52 2017 +0100
radv: Call NIR passes using NIR_PASS_V.
Port of faa1edeeb7bbe9321c79587e592dce812e8caa78
"anv/pipeline: Call NIR passes using NIR_PASS_V"
Signed-off-by: Bas Nieuwenhuizen
Reviewed-by: Timothy Arceri
---
src/amd/vulkan/radv_pipeline.c | 24 +++-
1 file changed, 7 insertions(+), 17 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index d818938..d1a3efe 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -209,14 +209,9 @@ radv_shader_compile_to_nir(struct radv_device *device,
* inline functions. That way they get properly initialized at
the top
* of the function and not at the top of its caller.
*/
- nir_lower_constant_initializers(nir, nir_var_local);
- nir_validate_shader(nir);
-
- nir_lower_returns(nir);
- nir_validate_shader(nir);
-
- nir_inline_functions(nir);
- nir_validate_shader(nir);
+ NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
+ NIR_PASS_V(nir, nir_lower_returns);
+ NIR_PASS_V(nir, nir_inline_functions);
/* Pick off the single entrypoint that we want */
foreach_list_typed_safe(nir_function, func, node,
&nir->functions) {
@@ -226,19 +221,14 @@ radv_shader_compile_to_nir(struct radv_device *device,
assert(exec_list_length(&nir->functions) == 1);
entry_point->name = ralloc_strdup(entry_point, "main");
- nir_remove_dead_variables(nir, nir_var_shader_in |
- nir_var_shader_out |
- nir_var_system_value);
- nir_validate_shader(nir);
+ NIR_PASS_V(nir, nir_remove_dead_variables,
+ nir_var_shader_in | nir_var_shader_out |
nir_var_system_value);
/* Now that we've deleted all but the main function, we can go
ahead and
* lower the rest of the constant initializers.
*/
- nir_lower_constant_initializers(nir, ~0);
- nir_validate_shader(nir);
-
- nir_lower_system_values(nir);
- nir_validate_shader(nir);
+ NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
+ NIR_PASS_V(nir, nir_lower_system_values);
}
/* Vulkan uses the separate-shader linking model */
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Mesa (master): radv: Only call remove_dead_variables once.
Module: Mesa Branch: master Commit: 18e70edd8c283463b2a5c8a22b6a5ea9a8d8fcd3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=18e70edd8c283463b2a5c8a22b6a5ea9a8d8fcd3 Author: Bas Nieuwenhuizen Date: Sun Jan 8 22:39:36 2017 +0100 radv: Only call remove_dead_variables once. Port of 43e0b0d4b255d910616c10e3e01bfec5db469e0e "anv/pipeline: Only call remove_dead_variables once" Signed-off-by: Bas Nieuwenhuizen Reviewed-by: Timothy Arceri --- src/amd/vulkan/radv_pipeline.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 61af01c..03603f5 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -219,9 +219,9 @@ radv_shader_compile_to_nir(struct radv_device *device, assert(exec_list_length(&nir->functions) == 1); entry_point->name = ralloc_strdup(entry_point, "main"); - nir_remove_dead_variables(nir, nir_var_shader_in); - nir_remove_dead_variables(nir, nir_var_shader_out); - nir_remove_dead_variables(nir, nir_var_system_value); + nir_remove_dead_variables(nir, nir_var_shader_in | + nir_var_shader_out | + nir_var_system_value); nir_validate_shader(nir); nir_lower_system_values(nir); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): st/nine: Don' t call u_box_union_* when dirty region is empty
Module: Mesa
Branch: master
Commit: 9b5f5de9e9efd6a0c0f53806c0f4b5890c84f98b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b5f5de9e9efd6a0c0f53806c0f4b5890c84f98b
Author: Masanori Kakura
Date: Wed Dec 28 22:21:02 2016 +0900
st/nine: Don't call u_box_union_* when dirty region is empty
When dirty region is empty, u_box_union_* incorrectly expands
the new region.
This fixes broken font rendering issue in WOLF RPG Editor v2.10 games.
Signed-off-by: Masanori Kakura
Reviewed-by: Axel Davy
---
src/gallium/state_trackers/nine/cubetexture9.c | 12
src/gallium/state_trackers/nine/texture9.c | 10 +++---
src/gallium/state_trackers/nine/volumetexture9.c | 10 +++---
3 files changed, 22 insertions(+), 10 deletions(-)
diff --git a/src/gallium/state_trackers/nine/cubetexture9.c
b/src/gallium/state_trackers/nine/cubetexture9.c
index 977a345..65251ad 100644
--- a/src/gallium/state_trackers/nine/cubetexture9.c
+++ b/src/gallium/state_trackers/nine/cubetexture9.c
@@ -285,10 +285,14 @@ NineCubeTexture9_AddDirtyRect( struct NineCubeTexture9
*This,
This->base.base.info.height0,
&This->dirty_rect[FaceType]);
} else {
-struct pipe_box box;
-rect_to_pipe_box_clamp(&box, pDirtyRect);
-u_box_union_2d(&This->dirty_rect[FaceType],
&This->dirty_rect[FaceType],
- &box);
+if (This->dirty_rect[FaceType].width == 0) {
+rect_to_pipe_box_clamp(&This->dirty_rect[FaceType], pDirtyRect);
+} else {
+struct pipe_box box;
+rect_to_pipe_box_clamp(&box, pDirtyRect);
+u_box_union_2d(&This->dirty_rect[FaceType],
&This->dirty_rect[FaceType],
+ &box);
+}
(void) u_box_clip_2d(&This->dirty_rect[FaceType],
&This->dirty_rect[FaceType],
This->base.base.info.width0,
diff --git a/src/gallium/state_trackers/nine/texture9.c
b/src/gallium/state_trackers/nine/texture9.c
index bf054cc..78ca4ad 100644
--- a/src/gallium/state_trackers/nine/texture9.c
+++ b/src/gallium/state_trackers/nine/texture9.c
@@ -330,9 +330,13 @@ NineTexture9_AddDirtyRect( struct NineTexture9 *This,
u_box_origin_2d(This->base.base.info.width0,
This->base.base.info.height0, &This->dirty_rect);
} else {
-struct pipe_box box;
-rect_to_pipe_box_clamp(&box, pDirtyRect);
-u_box_union_2d(&This->dirty_rect, &This->dirty_rect, &box);
+if (This->dirty_rect.width == 0) {
+rect_to_pipe_box_clamp(&This->dirty_rect, pDirtyRect);
+} else {
+struct pipe_box box;
+rect_to_pipe_box_clamp(&box, pDirtyRect);
+u_box_union_2d(&This->dirty_rect, &This->dirty_rect, &box);
+}
(void) u_box_clip_2d(&This->dirty_rect, &This->dirty_rect,
This->base.base.info.width0,
This->base.base.info.height0);
diff --git a/src/gallium/state_trackers/nine/volumetexture9.c
b/src/gallium/state_trackers/nine/volumetexture9.c
index 5c83fdb..c836dd2 100644
--- a/src/gallium/state_trackers/nine/volumetexture9.c
+++ b/src/gallium/state_trackers/nine/volumetexture9.c
@@ -222,9 +222,13 @@ NineVolumeTexture9_AddDirtyBox( struct NineVolumeTexture9
*This,
This->dirty_box.height = This->base.base.info.height0;
This->dirty_box.depth = This->base.base.info.depth0;
} else {
-struct pipe_box box;
-d3dbox_to_pipe_box(&box, pDirtyBox);
-u_box_union_3d(&This->dirty_box, &This->dirty_box, &box);
+if (This->dirty_box.width == 0) {
+d3dbox_to_pipe_box(&This->dirty_box, pDirtyBox);
+} else {
+struct pipe_box box;
+d3dbox_to_pipe_box(&box, pDirtyBox);
+u_box_union_3d(&This->dirty_box, &This->dirty_box, &box);
+}
This->dirty_box.x = MAX2(This->dirty_box.x, 0);
This->dirty_box.y = MAX2(This->dirty_box.y, 0);
This->dirty_box.z = MAX2(This->dirty_box.z, 0);
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Mesa (master): st/nine: Rework CreatePipeSurface
Module: Mesa
Branch: master
Commit: f895ab8e22dc520304141ba56c1b81d8d6657ccd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f895ab8e22dc520304141ba56c1b81d8d6657ccd
Author: Axel Davy
Date: Wed Dec 28 18:24:12 2016 +0100
st/nine: Rework CreatePipeSurface
Create both surfaces in one call.
Signed-off-by: Axel Davy
---
src/gallium/state_trackers/nine/surface9.c | 49 ++
src/gallium/state_trackers/nine/surface9.h | 3 --
2 files changed, 30 insertions(+), 22 deletions(-)
diff --git a/src/gallium/state_trackers/nine/surface9.c
b/src/gallium/state_trackers/nine/surface9.c
index a5c4a9e..4b8e213 100644
--- a/src/gallium/state_trackers/nine/surface9.c
+++ b/src/gallium/state_trackers/nine/surface9.c
@@ -44,6 +44,9 @@
#define DBG_CHANNEL DBG_SURFACE
+static void
+NineSurface9_CreatePipeSurfaces( struct NineSurface9 *This );
+
HRESULT
NineSurface9_ctor( struct NineSurface9 *This,
struct NineUnknownParams *pParams,
@@ -184,10 +187,8 @@ NineSurface9_ctor( struct NineSurface9 *This,
if (This->base.resource && (pDesc->Usage & D3DUSAGE_DYNAMIC))
This->base.resource->flags |= NINE_RESOURCE_FLAG_LOCKABLE;
-if (This->base.resource && (pDesc->Usage & (D3DUSAGE_RENDERTARGET |
D3DUSAGE_DEPTHSTENCIL))) {
-(void) NineSurface9_CreatePipeSurface(This, 0);
-(void) NineSurface9_CreatePipeSurface(This, 1);
-}
+if (This->base.resource && (pDesc->Usage & (D3DUSAGE_RENDERTARGET |
D3DUSAGE_DEPTHSTENCIL)))
+NineSurface9_CreatePipeSurfaces(This);
/* TODO: investigate what else exactly needs to be cleared */
if (This->base.resource && (pDesc->Usage & D3DUSAGE_RENDERTARGET))
@@ -220,8 +221,8 @@ NineSurface9_dtor( struct NineSurface9 *This )
NineResource9_dtor(&This->base);
}
-struct pipe_surface *
-NineSurface9_CreatePipeSurface( struct NineSurface9 *This, const int sRGB )
+static void
+NineSurface9_CreatePipeSurfaces( struct NineSurface9 *This )
{
struct pipe_context *pipe;
struct pipe_screen *screen = NineDevice9_GetScreen(This->base.base.device);
@@ -233,21 +234,33 @@ NineSurface9_CreatePipeSurface( struct NineSurface9
*This, const int sRGB )
assert(resource);
srgb_format = util_format_srgb(resource->format);
-if (sRGB && srgb_format != PIPE_FORMAT_NONE &&
-screen->is_format_supported(screen, srgb_format,
-resource->target, 0, resource->bind))
-templ.format = srgb_format;
-else
-templ.format = resource->format;
+if (srgb_format == PIPE_FORMAT_NONE ||
+!screen->is_format_supported(screen, srgb_format,
+ resource->target, 0, resource->bind))
+srgb_format = resource->format;
+
+memset(&templ, 0, sizeof(templ));
+templ.format = resource->format;
templ.u.tex.level = This->level;
templ.u.tex.first_layer = This->layer;
templ.u.tex.last_layer = This->layer;
pipe = nine_context_get_pipe_acquire(This->base.base.device);
-This->surface[sRGB] = pipe->create_surface(pipe, resource, &templ);
+
+This->surface[0] = pipe->create_surface(pipe, resource, &templ);
+
+memset(&templ, 0, sizeof(templ));
+templ.format = srgb_format;
+templ.u.tex.level = This->level;
+templ.u.tex.first_layer = This->layer;
+templ.u.tex.last_layer = This->layer;
+
+This->surface[1] = pipe->create_surface(pipe, resource, &templ);
+
nine_context_get_pipe_release(This->base.base.device);
-assert(This->surface[sRGB]);
-return This->surface[sRGB];
+
+assert(This->surface[0]); /* TODO: Handle failure */
+assert(This->surface[1]);
}
#ifdef DEBUG
@@ -762,10 +775,8 @@ NineSurface9_SetResourceResize( struct NineSurface9 *This,
pipe_surface_reference(&This->surface[0], NULL);
pipe_surface_reference(&This->surface[1], NULL);
-if (resource) {
-(void) NineSurface9_CreatePipeSurface(This, 0);
-(void) NineSurface9_CreatePipeSurface(This, 1);
-}
+if (resource)
+NineSurface9_CreatePipeSurfaces(This);
}
diff --git a/src/gallium/state_trackers/nine/surface9.h
b/src/gallium/state_trackers/nine/surface9.h
index 8263060..6f416f2 100644
--- a/src/gallium/state_trackers/nine/surface9.h
+++ b/src/gallium/state_trackers/nine/surface9.h
@@ -90,9 +90,6 @@ NineSurface9_dtor( struct NineSurface9 *This );
void
NineSurface9_MarkContainerDirty( struct NineSurface9 *This );
-struct pipe_surface *
-NineSurface9_CreatePipeSurface( struct NineSurface9 *This, const int sRGB );
-
static inline struct pipe_surface *
NineSurface9_GetSurface( struct NineSurface9 *This, int sRGB )
{
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Mesa (master): st/nine: Flush the queue at device dtor
Module: Mesa
Branch: master
Commit: 5f4359ea0ed54b06d443e0ba040eb73406fc3e34
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f4359ea0ed54b06d443e0ba040eb73406fc3e34
Author: Axel Davy
Date: Wed Dec 28 18:58:48 2016 +0100
st/nine: Flush the queue at device dtor
Flush the queue to get refcounts right, and properly
release the items, instead of throwing away all pending
commands.
Signed-off-by: Axel Davy
---
src/gallium/state_trackers/nine/device9.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/gallium/state_trackers/nine/device9.c
b/src/gallium/state_trackers/nine/device9.c
index b150faa..92bc72c 100644
--- a/src/gallium/state_trackers/nine/device9.c
+++ b/src/gallium/state_trackers/nine/device9.c
@@ -535,8 +535,13 @@ NineDevice9_dtor( struct NineDevice9 *This )
DBG("This=%p\n", This);
-/* Do not call nine_csmt_process here. The device is dead! */
+/* Flush all pending commands to get refcount right,
+ * and properly release bound objects. It is ok to still
+ * execute commands while we are in device dtor, because
+ * we haven't released anything yet. Note that no pending
+ * command can increase the device refcount. */
if (This->csmt_active && This->csmt_ctx) {
+nine_csmt_process(This);
nine_csmt_destroy(This, This->csmt_ctx);
This->csmt_active = FALSE;
This->csmt_ctx = NULL;
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Mesa (master): st/nine: Flush pending commands if needed for surface9 changes
Module: Mesa
Branch: master
Commit: 6b87a2a77a459d5c69f296b732d66daa9ff8e223
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b87a2a77a459d5c69f296b732d66daa9ff8e223
Author: Axel Davy
Date: Wed Dec 28 18:32:39 2016 +0100
st/nine: Flush pending commands if needed for surface9 changes
nine_context uses NineSurface9 fields, thus we need to flush
pending commands using the surface before changing the fields.
Signed-off-by: Axel Davy
---
src/gallium/state_trackers/nine/surface9.c | 28
src/gallium/state_trackers/nine/surface9.h | 17 -
2 files changed, 32 insertions(+), 13 deletions(-)
diff --git a/src/gallium/state_trackers/nine/surface9.c
b/src/gallium/state_trackers/nine/surface9.c
index 4b8e213..836369c 100644
--- a/src/gallium/state_trackers/nine/surface9.c
+++ b/src/gallium/state_trackers/nine/surface9.c
@@ -755,6 +755,33 @@ NineSurface9_UploadSelf( struct NineSurface9 *This,
return D3D_OK;
}
+/* Currently nine_context uses the NineSurface9
+ * fields when it is render target. Any modification requires
+ * pending commands with the surface to be executed. If the bind
+ * count is 0, there is no pending commands. */
+#define PROCESS_IF_BOUND(surf) \
+if (surf->base.base.bind) \
+nine_csmt_process(surf->base.base.device);
+
+void
+NineSurface9_SetResource( struct NineSurface9 *This,
+ struct pipe_resource *resource, unsigned level )
+{
+/* No need to call PROCESS_IF_BOUND, because SetResource is used only
+ * for MANAGED textures, and they are not render targets. */
+assert(This->base.pool == D3DPOOL_MANAGED);
+This->level = level;
+pipe_resource_reference(&This->base.resource, resource);
+}
+
+void
+NineSurface9_SetMultiSampleType( struct NineSurface9 *This,
+ D3DMULTISAMPLE_TYPE mst )
+{
+PROCESS_IF_BOUND(This);
+This->desc.MultiSampleType = mst;
+}
+
void
NineSurface9_SetResourceResize( struct NineSurface9 *This,
struct pipe_resource *resource )
@@ -764,6 +791,7 @@ NineSurface9_SetResourceResize( struct NineSurface9 *This,
assert(This->desc.Pool == D3DPOOL_DEFAULT);
assert(!This->texture);
+PROCESS_IF_BOUND(This);
pipe_resource_reference(&This->base.resource, resource);
This->desc.Width = This->base.info.width0 = resource->width0;
diff --git a/src/gallium/state_trackers/nine/surface9.h
b/src/gallium/state_trackers/nine/surface9.h
index 6f416f2..7badde4 100644
--- a/src/gallium/state_trackers/nine/surface9.h
+++ b/src/gallium/state_trackers/nine/surface9.h
@@ -103,22 +103,13 @@ NineSurface9_GetResource( struct NineSurface9 *This )
return This->base.resource;
}
-static inline void
+void
NineSurface9_SetResource( struct NineSurface9 *This,
- struct pipe_resource *resource, unsigned level )
-{
-This->level = level;
-pipe_resource_reference(&This->base.resource, resource);
-pipe_surface_reference(&This->surface[0], NULL);
-pipe_surface_reference(&This->surface[1], NULL);
-}
+ struct pipe_resource *resource, unsigned level );
-static inline void
+void
NineSurface9_SetMultiSampleType( struct NineSurface9 *This,
- D3DMULTISAMPLE_TYPE mst )
-{
-This->desc.MultiSampleType = mst;
-}
+ D3DMULTISAMPLE_TYPE mst );
void
NineSurface9_SetResourceResize( struct NineSurface9 *This,
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Mesa (master): st/nine: Protect dtors with mutex
Module: Mesa
Branch: master
Commit: 970556292b37fb9f7a64460a964e7a88503dcab6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=970556292b37fb9f7a64460a964e7a88503dcab6
Author: Axel Davy
Date: Thu Jan 5 23:04:09 2017 +0100
st/nine: Protect dtors with mutex
When the flag D3DCREATE_MULTITHREAD is set, a global mutex is used
to protect nine calls.
However for performance reasons, AddRef and Release didn't hold the mutex,
and instead used atomics.
Unfortunately at item release, the item can be destroyed, and that
destruction path should be protected by a mutex (at least for
some objects).
Without this patch, it is possible an app thread is in a dtor
while another thread is making gallium nine calls. It is possible
that two threads are using the same gallium pipe, which is forbiden.
The problem has been made worse with csmt, because it can cause hang,
since nine_csmt_process is not threadsafe.
Fixes Hitman hang, and possibly others.
Signed-off-by: Axel Davy
---
src/gallium/state_trackers/nine/iunknown.c | 26 +++
src/gallium/state_trackers/nine/iunknown.h | 3 ++
src/gallium/state_trackers/nine/nine_lock.c | 51 ++---
src/gallium/state_trackers/nine/nine_lock.h | 3 ++
4 files changed, 64 insertions(+), 19 deletions(-)
diff --git a/src/gallium/state_trackers/nine/iunknown.c
b/src/gallium/state_trackers/nine/iunknown.c
index eae4997..d76d644 100644
--- a/src/gallium/state_trackers/nine/iunknown.c
+++ b/src/gallium/state_trackers/nine/iunknown.c
@@ -26,6 +26,7 @@
#include "nine_helpers.h"
#include "nine_pdata.h"
+#include "nine_lock.h"
#define DBG_CHANNEL DBG_UNKNOWN
@@ -135,6 +136,31 @@ NineUnknown_Release( struct NineUnknown *This )
return r;
}
+/* No need to lock the mutex protecting nine (when D3DCREATE_MULTITHREADED)
+ * for AddRef and Release, except for dtor as some of the dtors require it. */
+ULONG NINE_WINAPI
+NineUnknown_ReleaseWithDtorLock( struct NineUnknown *This )
+{
+if (This->forward)
+return NineUnknown_ReleaseWithDtorLock(This->container);
+
+ULONG r = p_atomic_dec_return(&This->refs);
+
+if (r == 0) {
+if (This->device) {
+if (NineUnknown_ReleaseWithDtorLock(NineUnknown(This->device)) ==
0)
+return r; /* everything's gone */
+}
+/* Containers (here with !forward) take care of item destruction */
+if (!This->container && This->bind == 0) {
+NineLockGlobalMutex();
+This->dtor(This);
+NineUnlockGlobalMutex();
+}
+}
+return r;
+}
+
HRESULT NINE_WINAPI
NineUnknown_GetDevice( struct NineUnknown *This,
IDirect3DDevice9 **ppDevice )
diff --git a/src/gallium/state_trackers/nine/iunknown.h
b/src/gallium/state_trackers/nine/iunknown.h
index 4b9edaa..f9ce7b5 100644
--- a/src/gallium/state_trackers/nine/iunknown.h
+++ b/src/gallium/state_trackers/nine/iunknown.h
@@ -100,6 +100,9 @@ NineUnknown_AddRef( struct NineUnknown *This );
ULONG NINE_WINAPI
NineUnknown_Release( struct NineUnknown *This );
+ULONG NINE_WINAPI
+NineUnknown_ReleaseWithDtorLock( struct NineUnknown *This );
+
HRESULT NINE_WINAPI
NineUnknown_GetDevice( struct NineUnknown *This,
IDirect3DDevice9 **ppDevice );
diff --git a/src/gallium/state_trackers/nine/nine_lock.c
b/src/gallium/state_trackers/nine/nine_lock.c
index fb24400..1136dad 100644
--- a/src/gallium/state_trackers/nine/nine_lock.c
+++ b/src/gallium/state_trackers/nine/nine_lock.c
@@ -43,12 +43,25 @@
#include "volumetexture9.h"
#include "d3d9.h"
+#include "nine_lock.h"
#include "os/os_thread.h"
/* Global mutex as described by MSDN */
pipe_static_mutex(d3dlock_global);
+void
+NineLockGlobalMutex()
+{
+pipe_mutex_lock(d3dlock_global);
+}
+
+void
+NineUnlockGlobalMutex()
+{
+pipe_mutex_unlock(d3dlock_global);
+}
+
static HRESULT NINE_WINAPI
LockAuthenticatedChannel9_GetCertificateSize( struct NineAuthenticatedChannel9
*This,
UINT *pCertificateSize )
@@ -114,7 +127,7 @@ LockAuthenticatedChannel9_Configure( struct
NineAuthenticatedChannel9 *This,
IDirect3DAuthenticatedChannel9Vtbl LockAuthenticatedChannel9_vtable = {
(void *)NineUnknown_QueryInterface,
(void *)NineUnknown_AddRef,
-(void *)NineUnknown_Release,
+(void *)NineUnknown_ReleaseWithDtorLock,
(void *)LockAuthenticatedChannel9_GetCertificateSize,
(void *)LockAuthenticatedChannel9_GetCertificate,
(void *)LockAuthenticatedChannel9_NegotiateKeyExchange,
@@ -398,7 +411,7 @@ LockCryptoSession9_GetEncryptionBltKey( struct
NineCryptoSession9 *This,
IDirect3DCryptoSession9Vtbl LockCryptoSession9_vtable = {
(void *)NineUnknown_QueryInterface,
(void *)NineUnknown_AddRef,
-(void *)NineUnknown_Release,
+(void *)NineUnknown_ReleaseWithDtorLock,
(void *)LockCryptoSession9_GetCertificateSize,
(void *)LockCryptoSession9_GetCertificate,
(void *
Mesa (master): st/nine: Remove duplicated checks
Module: Mesa
Branch: master
Commit: d43bc05e8ba0f326273c21b10f714e4d2514adae
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d43bc05e8ba0f326273c21b10f714e4d2514adae
Author: Axel Davy
Date: Wed Dec 28 17:54:47 2016 +0100
st/nine: Remove duplicated checks
There is no need to check on csmt_active before
calling nine_csmt_process, because the function
checks already.
Signed-off-by: Axel Davy
---
src/gallium/state_trackers/nine/device9.c| 3 +--
src/gallium/state_trackers/nine/nine_state.c | 14 ++
2 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/src/gallium/state_trackers/nine/device9.c
b/src/gallium/state_trackers/nine/device9.c
index f095ff3..d76d506 100644
--- a/src/gallium/state_trackers/nine/device9.c
+++ b/src/gallium/state_trackers/nine/device9.c
@@ -522,8 +522,7 @@ NineDevice9_ctor( struct NineDevice9 *This,
nine_state_init_sw(This);
ID3DPresentGroup_Release(This->present);
-if (This->csmt_active)
-nine_csmt_process(This);
+nine_csmt_process(This);
return D3D_OK;
}
diff --git a/src/gallium/state_trackers/nine/nine_state.c
b/src/gallium/state_trackers/nine/nine_state.c
index afc309f..697e216 100644
--- a/src/gallium/state_trackers/nine/nine_state.c
+++ b/src/gallium/state_trackers/nine/nine_state.c
@@ -280,8 +280,7 @@ nine_csmt_resume( struct NineDevice9 *device )
struct pipe_context *
nine_context_get_pipe( struct NineDevice9 *device )
{
-if (device->csmt_active)
-nine_csmt_process(device);
+nine_csmt_process(device);
return device->context.pipe;
}
@@ -1908,8 +1907,8 @@ nine_context_light_enable_stateblock(struct NineDevice9
*device,
{
struct nine_context *context = &device->context;
-if (device->csmt_active) /* TODO: fix */
-nine_csmt_process(device);
+/* TODO: Use CSMT_* to avoid calling nine_csmt_process */
+nine_csmt_process(device);
memcpy(context->ff.active_light, active_light, NINE_MAX_LIGHTS_ACTIVE *
sizeof(context->ff.active_light[0]));
context->ff.num_lights_active = num_lights_active;
context->changed.group |= NINE_STATE_FF_LIGHTING;
@@ -2821,10 +2820,9 @@ nine_context_get_query_result(struct NineDevice9
*device, struct pipe_query *que
struct pipe_context *pipe;
boolean ret;
-if (wait) {
-if (device->csmt_active)
-nine_csmt_process(device);
-} else if (p_atomic_read(counter) > 0) {
+if (wait)
+nine_csmt_process(device);
+else if (p_atomic_read(counter) > 0) {
if (flush && device->csmt_active)
nine_queue_flush(device->csmt_ctx->pool);
DBG("Pending begin/end. Returning\n");
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Mesa (master): st/nine: Process pending commands on Reset
Module: Mesa
Branch: master
Commit: 4e922c81f616bba71565de8d7fd8f5f6955ce1cc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e922c81f616bba71565de8d7fd8f5f6955ce1cc
Author: Axel Davy
Date: Wed Dec 28 18:49:10 2016 +0100
st/nine: Process pending commands on Reset
Some nine_state_* and nine_context_* functions
used for Reset() require all pending commands are
flushed.
Signed-off-by: Axel Davy
---
src/gallium/state_trackers/nine/device9.c| 1 +
src/gallium/state_trackers/nine/device9ex.c | 1 +
src/gallium/state_trackers/nine/nine_state.c | 3 +++
3 files changed, 5 insertions(+)
diff --git a/src/gallium/state_trackers/nine/device9.c
b/src/gallium/state_trackers/nine/device9.c
index d76d506..b150faa 100644
--- a/src/gallium/state_trackers/nine/device9.c
+++ b/src/gallium/state_trackers/nine/device9.c
@@ -917,6 +917,7 @@ NineDevice9_Reset( struct NineDevice9 *This,
break;
}
+nine_csmt_process(This);
nine_state_clear(&This->state, TRUE);
nine_context_clear(This);
diff --git a/src/gallium/state_trackers/nine/device9ex.c
b/src/gallium/state_trackers/nine/device9ex.c
index 30c8c65..2853a81 100644
--- a/src/gallium/state_trackers/nine/device9ex.c
+++ b/src/gallium/state_trackers/nine/device9ex.c
@@ -257,6 +257,7 @@ NineDevice9Ex_Reset( struct NineDevice9Ex *This,
break;
}
+nine_csmt_process(&This->base);
nine_state_clear(&This->base.state, TRUE);
nine_context_clear(&This->base);
diff --git a/src/gallium/state_trackers/nine/nine_state.c
b/src/gallium/state_trackers/nine/nine_state.c
index 697e216..8909692 100644
--- a/src/gallium/state_trackers/nine/nine_state.c
+++ b/src/gallium/state_trackers/nine/nine_state.c
@@ -2995,6 +2995,9 @@ static const DWORD
nine_samp_state_defaults[NINED3DSAMP_LAST + 1] =
[NINED3DSAMP_CUBETEX] = 0
};
+/* Note: The following 4 functions assume there is no
+ * pending commands */
+
void nine_state_restore_non_cso(struct NineDevice9 *device)
{
struct nine_context *context = &device->context;
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Mesa (master): ac: automake: rework sid_tables.h generation
Module: Mesa Branch: master Commit: d1dc22eb4661dbb343920bb36a9c71accec334d5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1dc22eb4661dbb343920bb36a9c71accec334d5 Author: Emil Velikov Date: Thu Jan 12 17:34:15 2017 + ac: automake: rework sid_tables.h generation Drop $(srcdir)/ prefix analogous to before the file (and rule) movement and move it outside of the NEED_RADEON_LLVM conditional. Otherwise the build may fail as below. make[3]: *** No rule to make target 'common/sid_tables.h', needed by 'distdir'. Stop. Fixes: b838f642371 "ac/debug: Move sid_tables.h generation to common code." Signed-off-by: Emil Velikov --- src/amd/Makefile.am| 2 +- src/amd/Makefile.common.am | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/amd/Makefile.am b/src/amd/Makefile.am index 0a8456d..7d191af 100644 --- a/src/amd/Makefile.am +++ b/src/amd/Makefile.am @@ -23,6 +23,6 @@ include Makefile.sources noinst_LTLIBRARIES = -EXTRA_DIST = $(COMMON_HEADER_FILES) $(srcdir)/common/sid_tables.py +EXTRA_DIST = $(COMMON_HEADER_FILES) common/sid_tables.py include Makefile.addrlib.am include Makefile.common.am diff --git a/src/amd/Makefile.common.am b/src/amd/Makefile.common.am index 533ad17..b5fce2b 100644 --- a/src/amd/Makefile.common.am +++ b/src/amd/Makefile.common.am @@ -62,9 +62,9 @@ common_libamd_common_la_SOURCES = \ if HAVE_RADEON_VULKAN common_libamd_common_la_SOURCES += $(AMD_NIR_FILES) endif +endif -$(srcdir)/common/sid_tables.h: $(srcdir)/common/sid_tables.py $(srcdir)/common/sid.h +common/sid_tables.h: $(srcdir)/common/sid_tables.py $(srcdir)/common/sid.h $(AM_V_GEN) $(PYTHON2) $(srcdir)/common/sid_tables.py $(srcdir)/common/sid.h > $@ BUILT_SOURCES = $(AMD_GENERATED_FILES) -endif ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): automake: use shared llvm libs for make distcheck
Module: Mesa Branch: master Commit: 23dcce0c03db055c168696c9120637506b68b13d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=23dcce0c03db055c168696c9120637506b68b13d Author: Emil Velikov Date: Thu Jan 12 17:18:51 2017 + automake: use shared llvm libs for make distcheck Cc: "12.0 13.0" Signed-off-by: Emil Velikov --- Makefile.am | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.am b/Makefile.am index 71030f2..4f2e698 100644 --- a/Makefile.am +++ b/Makefile.am @@ -40,7 +40,7 @@ AM_DISTCHECK_CONFIGURE_FLAGS = \ --enable-vdpau \ --enable-xa \ --enable-xvmc \ - --disable-llvm-shared-libs \ + --enable-llvm-shared-libs \ --with-egl-platforms=x11,wayland,drm,surfaceless \ --with-dri-drivers=i915,i965,nouveau,radeon,r200,swrast \ --with-gallium-drivers=i915,ilo,nouveau,r300,r600,radeonsi,freedreno,svga,swrast,vc4,virgl,swr,etnaviv,imx \ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): automake: add the new drivers etnaviv and imx to make distcheck
Module: Mesa Branch: master Commit: 024b4c35bc095d421abbe1f850526254750cb3c4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=024b4c35bc095d421abbe1f850526254750cb3c4 Author: Emil Velikov Date: Thu Jan 12 17:17:35 2017 + automake: add the new drivers etnaviv and imx to make distcheck Signed-off-by: Emil Velikov --- Makefile.am | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.am b/Makefile.am index e6d1969..71030f2 100644 --- a/Makefile.am +++ b/Makefile.am @@ -43,7 +43,7 @@ AM_DISTCHECK_CONFIGURE_FLAGS = \ --disable-llvm-shared-libs \ --with-egl-platforms=x11,wayland,drm,surfaceless \ --with-dri-drivers=i915,i965,nouveau,radeon,r200,swrast \ - --with-gallium-drivers=i915,ilo,nouveau,r300,r600,radeonsi,freedreno,svga,swrast,vc4,virgl,swr \ + --with-gallium-drivers=i915,ilo,nouveau,r300,r600,radeonsi,freedreno,svga,swrast,vc4,virgl,swr,etnaviv,imx \ --with-vulkan-drivers=intel,radeon ACLOCAL_AMFLAGS = -I m4 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): imx: gallium driver for imx-drm scanout driver
Module: Mesa Branch: master Commit: e8626e3b317035352148a6af15a2b781eba6e707 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e8626e3b317035352148a6af15a2b781eba6e707 Author: Christian Gmeiner Date: Fri Dec 23 21:10:29 2016 +0100 imx: gallium driver for imx-drm scanout driver Changes from V1 -> V2: - updated Copyright - added $(top_srcdir)/src/gallium/winsys to include path (suggested by Emil) - adapted driver to new renderonly API Signed-off-by: Christian Gmeiner Acked-by: Emil Velikov --- configure.ac | 14 +- src/gallium/Makefile.am| 4 ++ .../auxiliary/pipe-loader/pipe_loader_drm.c| 5 +++ src/gallium/auxiliary/target-helpers/drm_helper.h | 24 +++ .../auxiliary/target-helpers/drm_helper_public.h | 3 ++ src/gallium/drivers/imx/Automake.inc | 9 src/gallium/drivers/imx/Makefile.am| 8 src/gallium/targets/dri/Makefile.am| 1 + src/gallium/targets/dri/target.c | 8 src/gallium/winsys/imx/drm/Makefile.am | 33 ++ src/gallium/winsys/imx/drm/Makefile.sources| 3 ++ src/gallium/winsys/imx/drm/imx_drm_public.h| 34 +++ src/gallium/winsys/imx/drm/imx_drm_winsys.c| 50 ++ 13 files changed, 195 insertions(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index efac67c..49c5e25 100644 --- a/configure.ac +++ b/configure.ac @@ -1234,7 +1234,7 @@ GALLIUM_DRIVERS_DEFAULT="r300,r600,svga,swrast" AC_ARG_WITH([gallium-drivers], [AS_HELP_STRING([--with-gallium-drivers@<:@=DIRS...@:>@], [comma delimited Gallium drivers list, e.g. - "i915,ilo,nouveau,r300,r600,radeonsi,freedreno,svga,swrast,vc4,virgl,etnaviv" + "i915,ilo,nouveau,r300,r600,radeonsi,freedreno,svga,swrast,vc4,virgl,etnaviv,imx" @<:@default=r300,r600,svga,swrast@:>@])], [with_gallium_drivers="$withval"], [with_gallium_drivers="$GALLIUM_DRIVERS_DEFAULT"]) @@ -2512,6 +2512,9 @@ if test -n "$with_gallium_drivers"; then PKG_CHECK_MODULES([ETNAVIV], [libdrm_etnaviv >= $LIBDRM_ETNAVIV_REQUIRED]) require_libdrm "etnaviv" ;; + ximx) +HAVE_GALLIUM_IMX=yes +;; xswrast) HAVE_GALLIUM_SOFTPIPE=yes if test "x$MESA_LLVM" = x1 && test "x$enable_gallium_llvm" == "xyes"; then @@ -2566,6 +2569,12 @@ if test "x$enable_gallium_llvm" == "xyes"; then llvm_add_default_components "gallium" fi +dnl We need to validate some needed dependencies for renderonly drivers. + +if test "x$HAVE_GALLIUM_ETNAVIV" != xyes -a "x$HAVE_GALLIUM_IMX" == xyes ; then +AC_ERROR([Building with imx requires etnaviv]) +fi + dnl Set LLVM_LIBS - This is done after the driver configuration so dnl that drivers can add additional components to LLVM_COMPONENTS. dnl Previously, gallium drivers were updating LLVM_LIBS directly @@ -2631,6 +2640,7 @@ AM_CONDITIONAL(HAVE_GALLIUM_RADEON_COMMON, test "x$HAVE_GALLIUM_R600" = xyes -o AM_CONDITIONAL(HAVE_GALLIUM_NOUVEAU, test "x$HAVE_GALLIUM_NOUVEAU" = xyes) AM_CONDITIONAL(HAVE_GALLIUM_FREEDRENO, test "x$HAVE_GALLIUM_FREEDRENO" = xyes) AM_CONDITIONAL(HAVE_GALLIUM_ETNAVIV, test "x$HAVE_GALLIUM_ETNAVIV" = xyes) +AM_CONDITIONAL(HAVE_GALLIUM_IMX, test "x$HAVE_GALLIUM_IMX" = xyes) AM_CONDITIONAL(HAVE_GALLIUM_SOFTPIPE, test "x$HAVE_GALLIUM_SOFTPIPE" = xyes) AM_CONDITIONAL(HAVE_GALLIUM_LLVMPIPE, test "x$HAVE_GALLIUM_LLVMPIPE" = xyes) AM_CONDITIONAL(HAVE_GALLIUM_SWR, test "x$HAVE_GALLIUM_SWR" = xyes) @@ -2785,6 +2795,7 @@ AC_CONFIG_FILES([Makefile src/gallium/drivers/swr/Makefile src/gallium/drivers/trace/Makefile src/gallium/drivers/etnaviv/Makefile + src/gallium/drivers/imx/Makefile src/gallium/drivers/vc4/Makefile src/gallium/drivers/virgl/Makefile src/gallium/state_trackers/clover/Makefile @@ -2815,6 +2826,7 @@ AC_CONFIG_FILES([Makefile src/gallium/tests/trivial/Makefile src/gallium/tests/unit/Makefile src/gallium/winsys/etnaviv/drm/Makefile + src/gallium/winsys/imx/drm/Makefile src/gallium/winsys/freedreno/drm/Makefile src/gallium/winsys/i915/drm/Makefile src/gallium/winsys/intel/drm/Makefile diff --git a/src/gallium/Makefile.am b/src/gallium/Makefile.am index 9e47e9f..f910f31 100644 --- a/src/gallium/Makefile.am +++ b/src/gallium/Makefile.am @@ -72,6 +72,10 @@ if HAVE_GALLIUM_ETNAVIV SUBDIRS += drivers/etnaviv winsys/etnaviv/drm endif +if HAVE_GALLIUM_IMX +SUBDIRS += drivers/imx winsys/imx/drm +endif + ## swrast/softpipe if HAVE_GALLIUM_SOFTPIPE SUBDIRS += drivers/softpipe diff --git a/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c b/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c i
Mesa (master): winsys/etnaviv: automake: introduce Makefile.sources
Module: Mesa Branch: master Commit: a5f0cdb36f9dd06866e62c7094939ccd62db7caa URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5f0cdb36f9dd06866e62c7094939ccd62db7caa Author: Emil Velikov Date: Thu Jan 12 18:49:41 2017 + winsys/etnaviv: automake: introduce Makefile.sources ... and list the public header within it. Signed-off-by: Emil Velikov --- src/gallium/winsys/etnaviv/drm/Makefile.am | 3 ++- src/gallium/winsys/etnaviv/drm/Makefile.sources | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/gallium/winsys/etnaviv/drm/Makefile.am b/src/gallium/winsys/etnaviv/drm/Makefile.am index 995b709..ed04d95 100644 --- a/src/gallium/winsys/etnaviv/drm/Makefile.am +++ b/src/gallium/winsys/etnaviv/drm/Makefile.am @@ -20,6 +20,7 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER # DEALINGS IN THE SOFTWARE. +include Makefile.sources include $(top_srcdir)/src/gallium/Automake.inc AM_CFLAGS = \ @@ -29,4 +30,4 @@ AM_CFLAGS = \ noinst_LTLIBRARIES = libetnavivdrm.la -libetnavivdrm_la_SOURCES = etnaviv_drm_winsys.c +libetnavivdrm_la_SOURCES = $(C_SOURCES) diff --git a/src/gallium/winsys/etnaviv/drm/Makefile.sources b/src/gallium/winsys/etnaviv/drm/Makefile.sources new file mode 100644 index 000..f338b08 --- /dev/null +++ b/src/gallium/winsys/etnaviv/drm/Makefile.sources @@ -0,0 +1,3 @@ +C_SOURCES := \ + etnaviv_drm_public.h \ + etnaviv_drm_winsys.c ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): etnaviv: gallium driver for Vivante GPUs
Module: Mesa Branch: master Commit: c9e8b49b885242d84ba031dacef5aa4a5ac1e5b6 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c9e8b49b885242d84ba031dacef5aa4a5ac1e5b6 Author: The etnaviv authors Date: Fri Dec 23 20:58:23 2016 +0100 etnaviv: gallium driver for Vivante GPUs This driver supports a wide range of Vivante IP cores like GC880, GC1000, GC2000 and GC3000. Changes from V1 -> V2: - added missing files to actually integrate the driver into build system. - adapted driver to new renderonly API Signed-off-by: Christian Gmeiner Signed-off-by: Lucas Stach Signed-off-by: Philipp Zabel Signed-off-by: Rob Herring Signed-off-by: Russell King Signed-off-by: Wladimir J. van der Laan Acked-by: Emil Velikov --- configure.ac | 11 +- src/gallium/Makefile.am|4 + .../auxiliary/pipe-loader/pipe_loader_drm.c|5 + src/gallium/auxiliary/target-helpers/drm_helper.h | 22 + .../auxiliary/target-helpers/drm_helper_public.h |3 + src/gallium/drivers/etnaviv/.gitignore |1 + src/gallium/drivers/etnaviv/Automake.inc | 11 + src/gallium/drivers/etnaviv/Makefile.am| 44 + src/gallium/drivers/etnaviv/Makefile.sources | 49 + src/gallium/drivers/etnaviv/README | 13 + src/gallium/drivers/etnaviv/etnaviv_asm.c | 107 + src/gallium/drivers/etnaviv/etnaviv_asm.h | 133 + src/gallium/drivers/etnaviv/etnaviv_blend.c| 109 + src/gallium/drivers/etnaviv/etnaviv_blend.h| 52 + src/gallium/drivers/etnaviv/etnaviv_clear_blit.c | 640 + src/gallium/drivers/etnaviv/etnaviv_clear_blit.h | 48 + src/gallium/drivers/etnaviv/etnaviv_compiler.c | 2532 src/gallium/drivers/etnaviv/etnaviv_compiler.h | 120 + .../drivers/etnaviv/etnaviv_compiler_cmdline.c | 146 ++ src/gallium/drivers/etnaviv/etnaviv_context.c | 323 +++ src/gallium/drivers/etnaviv/etnaviv_context.h | 194 ++ src/gallium/drivers/etnaviv/etnaviv_debug.h| 79 + src/gallium/drivers/etnaviv/etnaviv_disasm.c | 612 + src/gallium/drivers/etnaviv/etnaviv_disasm.h | 40 + src/gallium/drivers/etnaviv/etnaviv_emit.c | 770 ++ src/gallium/drivers/etnaviv/etnaviv_emit.h | 123 + src/gallium/drivers/etnaviv/etnaviv_fence.c| 87 + src/gallium/drivers/etnaviv/etnaviv_fence.h| 39 + src/gallium/drivers/etnaviv/etnaviv_format.c | 268 +++ src/gallium/drivers/etnaviv/etnaviv_format.h | 47 + src/gallium/drivers/etnaviv/etnaviv_internal.h | 259 ++ src/gallium/drivers/etnaviv/etnaviv_query.c| 120 + src/gallium/drivers/etnaviv/etnaviv_query.h| 64 + src/gallium/drivers/etnaviv/etnaviv_query_sw.c | 123 + src/gallium/drivers/etnaviv/etnaviv_query_sw.h | 47 + src/gallium/drivers/etnaviv/etnaviv_rasterizer.c | 81 + src/gallium/drivers/etnaviv/etnaviv_rasterizer.h | 57 + src/gallium/drivers/etnaviv/etnaviv_resource.c | 438 src/gallium/drivers/etnaviv/etnaviv_resource.h | 148 ++ src/gallium/drivers/etnaviv/etnaviv_rs.c | 127 + src/gallium/drivers/etnaviv/etnaviv_rs.h | 86 + src/gallium/drivers/etnaviv/etnaviv_screen.c | 813 +++ src/gallium/drivers/etnaviv/etnaviv_screen.h | 95 + src/gallium/drivers/etnaviv/etnaviv_shader.c | 285 +++ src/gallium/drivers/etnaviv/etnaviv_shader.h | 45 + src/gallium/drivers/etnaviv/etnaviv_state.c| 664 + src/gallium/drivers/etnaviv/etnaviv_state.h| 52 + src/gallium/drivers/etnaviv/etnaviv_surface.c | 152 ++ src/gallium/drivers/etnaviv/etnaviv_surface.h | 55 + src/gallium/drivers/etnaviv/etnaviv_texture.c | 338 +++ src/gallium/drivers/etnaviv/etnaviv_texture.h | 75 + src/gallium/drivers/etnaviv/etnaviv_tiling.c | 96 + src/gallium/drivers/etnaviv/etnaviv_tiling.h | 56 + src/gallium/drivers/etnaviv/etnaviv_transfer.c | 355 +++ src/gallium/drivers/etnaviv/etnaviv_transfer.h | 35 + src/gallium/drivers/etnaviv/etnaviv_translate.h| 516 src/gallium/drivers/etnaviv/etnaviv_uniforms.c | 118 + src/gallium/drivers/etnaviv/etnaviv_uniforms.h | 45 + src/gallium/drivers/etnaviv/etnaviv_util.h | 108 + src/gallium/drivers/etnaviv/etnaviv_zsa.c | 123 + src/gallium/drivers/etnaviv/etnaviv_zsa.h | 52 + src/gallium/drivers/etnaviv/hw/cmdstream.xml.h | 270 +++ src/gallium/drivers/etnaviv/hw/common.xml.h| 320 +++ src/gallium/drivers/etnaviv/hw/isa.xml.h | 239 ++ src/gallium/drivers/etnaviv/hw/state.xml.h | 397 +++ src/gallium/drivers/etnaviv/hw/state_3d.xml.h | 1231 ++ src/gallium/targets/dri/Makefile.am|2 + src/gallium/targets/dri/target.c | 11 + src/gallium/winsys/etnaviv/dr
Mesa (master): etnaviv: automake: include all files in the sources lists
Module: Mesa Branch: master Commit: 0467700536e332985a2f6fcc67163a088934b1b9 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0467700536e332985a2f6fcc67163a088934b1b9 Author: Emil Velikov Date: Thu Jan 12 17:54:34 2017 + etnaviv: automake: include all files in the sources lists Note: the currently mentioned etnaviv_utils.h is typo. Signed-off-by: Emil Velikov --- src/gallium/drivers/etnaviv/Makefile.sources | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/etnaviv/Makefile.sources b/src/gallium/drivers/etnaviv/Makefile.sources index ded3a31..60275c9 100644 --- a/src/gallium/drivers/etnaviv/Makefile.sources +++ b/src/gallium/drivers/etnaviv/Makefile.sources @@ -1,4 +1,10 @@ C_SOURCES := \ + hw/cmdstream.xml.h \ + hw/common.xml.h \ + hw/isa.xml.h \ + hw/state_3d.xml.h \ + hw/state.xml.h \ + \ etnaviv_asm.c \ etnaviv_asm.h \ etnaviv_blend.c \ @@ -18,6 +24,7 @@ C_SOURCES := \ etnaviv_fence.h \ etnaviv_format.c \ etnaviv_format.h \ + etnaviv_internal.h \ etnaviv_query.c \ etnaviv_query.h \ etnaviv_query_sw.c \ @@ -42,8 +49,9 @@ C_SOURCES := \ etnaviv_tiling.h \ etnaviv_transfer.c \ etnaviv_transfer.h \ + etnaviv_translate.h \ etnaviv_uniforms.c \ etnaviv_uniforms.h \ - etnaviv_utils.h \ + etnaviv_util.h \ etnaviv_zsa.c \ etnaviv_zsa.h ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): gallium: add renderonly library
Module: Mesa
Branch: master
Commit: 848b49b288fc2fa942418d12829db2e559ad4916
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=848b49b288fc2fa942418d12829db2e559ad4916
Author: Christian Gmeiner
Date: Fri Dec 23 20:33:10 2016 +0100
gallium: add renderonly library
This a very lightweight library to add basic support for renderonly
GPUs. A kms gallium driver must specify how a renderonly_scanout
objects gets created. Also it must provide file handles to the used
kms device and the used gpu device.
This could look like:
struct renderonly ro = {
.create_for_resource = renderonly_create_gpu_import_for_resource,
.kms_fd = fd,
.gpu_fd = open("/dev/dri/renderD128", O_RDWR | O_CLOEXEC)
};
The renderonly_scanout object exits for two reasons:
- Do any special treatment for a scanout resource like importing the
GPU resource into the scanout hw.
- Make it easier for a gallium driver to detect if anything special
needs to be done in flush_resource(..) like a resolve to linear.
A GPU gallium driver which gets used as renderonly GPU needs to be
aware of the renderonly library.
This library will likely break android support and hopefully will get
replaced with a better solution based on gbm2.
Changes from V1 -> V2:
- reworked the lifecycle of renderonly object (suggested by Nicolai Hähnle)
- killed the midlayer (suggested by Thierry Reding)
- made the API more explicit regarding gpu and kms fd's
- added some docs
Signed-off-by: Christian Gmeiner
Acked-by: Emil Velikov
Tested-by: Alexandre Courbot
---
src/gallium/Automake.inc | 5 +
src/gallium/auxiliary/Makefile.am | 10 ++
src/gallium/auxiliary/Makefile.sources| 4 +
src/gallium/auxiliary/renderonly/renderonly.c | 175 ++
src/gallium/auxiliary/renderonly/renderonly.h | 109
5 files changed, 303 insertions(+)
diff --git a/src/gallium/Automake.inc b/src/gallium/Automake.inc
index 6fe2e22..6aadcb9 100644
--- a/src/gallium/Automake.inc
+++ b/src/gallium/Automake.inc
@@ -50,6 +50,11 @@ GALLIUM_COMMON_LIB_DEPS = \
$(PTHREAD_LIBS) \
$(DLOPEN_LIBS)
+if HAVE_LIBDRM
+GALLIUM_COMMON_LIB_DEPS += \
+ $(LIBDRM_LIBS)
+endif
+
GALLIUM_WINSYS_CFLAGS = \
-I$(top_srcdir)/src \
-I$(top_srcdir)/include \
diff --git a/src/gallium/auxiliary/Makefile.am
b/src/gallium/auxiliary/Makefile.am
index 0d1aee6..1154c79 100644
--- a/src/gallium/auxiliary/Makefile.am
+++ b/src/gallium/auxiliary/Makefile.am
@@ -20,6 +20,16 @@ libgallium_la_SOURCES = \
$(NIR_SOURCES) \
$(GENERATED_SOURCES)
+if HAVE_LIBDRM
+
+AM_CFLAGS += \
+ $(LIBDRM_CFLAGS)
+
+libgallium_la_SOURCES += \
+ $(RENDERONLY_SOURCES)
+
+endif
+
if HAVE_GALLIUM_LLVM
AM_CFLAGS += \
diff --git a/src/gallium/auxiliary/Makefile.sources
b/src/gallium/auxiliary/Makefile.sources
index 5d4fe30..8d3e4a9 100644
--- a/src/gallium/auxiliary/Makefile.sources
+++ b/src/gallium/auxiliary/Makefile.sources
@@ -435,3 +435,7 @@ GALLIVM_SOURCES := \
draw/draw_llvm_sample.c \
draw/draw_pt_fetch_shade_pipeline_llvm.c \
draw/draw_vs_llvm.c
+
+RENDERONLY_SOURCES := \
+ renderonly/renderonly.c \
+ renderonly/renderonly.h
diff --git a/src/gallium/auxiliary/renderonly/renderonly.c
b/src/gallium/auxiliary/renderonly/renderonly.c
new file mode 100644
index 000..7e23769
--- /dev/null
+++ b/src/gallium/auxiliary/renderonly/renderonly.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (C) 2016 Christian Gmeiner
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *Christian Gmeiner
+ */
+
+#include "renderonly/renderonly.h"
+
+#include
+#include
+#include
+#include
+#include
+
+#include "state_tracker/drm_driver.h"
+#include "pipe/p_screen.h"
+#include "util/u_memory.h"
+
+struct renderonly *
+renderonly_dup(const struct renderonly *ro)
+{
+ struct rendero
Mesa (master): spirv: Handle patch decorations up-front
Module: Mesa
Branch: master
Commit: 27a1c7ffbdd7d7a8fd1240413446c1172752d93b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=27a1c7ffbdd7d7a8fd1240413446c1172752d93b
Author: Jason Ekstrand
Date: Wed Jan 11 18:04:57 2017 -0800
spirv: Handle patch decorations up-front
Once again, SPIR-V is insane... It allows you to place "patch"
decorations on structure members. Presumably, this is so that you can
do something such as
out struct S {
layout(location = 0) patch vec4 thing1;
layout(location = 0) vec4 thing2;
} str;
And have your I/O "nicely" organized. While this is a bit silly, it's
allowed and well-defined so whatever. Where it really gets interesting
is when you have an array of struct. SPIR-V says nothing about not
allowing you to have those qualifiers on the members of a struct that's
inside an array and GLSLang does this. Specifically, if you have
layout(location = 0) out patch struct S {
vec4 thing1;
vec4 thing2;
} str[2];
then GLSLang will place the "patch" decorations on the struct members.
This is ridiculous there is no way that having some of them be patch and
some not would be well-defined given that patch and non-patch outputs
are in effectively different storage classes. This commit moves around
the way we handle the "patch" decoration so that we can detect even the
crazy cases and handle them.
Fixes: dEQP-VK.tessellation.user_defined_io.per_patch_block_array.*
Reviewed-by: Kenneth Graunke
---
src/compiler/spirv/vtn_variables.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/src/compiler/spirv/vtn_variables.c
b/src/compiler/spirv/vtn_variables.c
index 1cc1402..61a3701 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1361,8 +1361,29 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp opcode,
case vtn_variable_mode_input:
case vtn_variable_mode_output: {
+ /* In order to know whether or not we're a per-vertex inout, we need
+ * the patch qualifier. This means walking the variable decorations
+ * early before we actually create any variables. Not a big deal.
+ *
+ * GLSLang really likes to place decorations in the most interior
+ * thing it possibly can. In particular, if you have a struct, it
+ * will place the patch decorations on the struct members. This
+ * should be handled by the variable splitting below just fine.
+ *
+ * If you have an array-of-struct, things get even more weird as it
+ * will place the patch decorations on the struct even though it's
+ * inside an array and some of the members being patch and others not
+ * makes no sense whatsoever. Since the only sensible thing is for
+ * it to be all or nothing, we'll call it patch if any of the members
+ * are declared patch.
+ */
var->patch = false;
vtn_foreach_decoration(b, val, var_is_patch_cb, &var->patch);
+ if (glsl_type_is_array(var->type->type) &&
+ glsl_type_is_struct(without_array->type)) {
+vtn_foreach_decoration(b, without_array->val,
+ var_is_patch_cb, &var->patch);
+ }
/* For inputs and outputs, we immediately split structures. This
* is for a couple of reasons. For one, builtins may all come in
@@ -1402,6 +1423,7 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp opcode,
var->members[i]->interface_type =
interface_type->members[i]->type;
var->members[i]->data.mode = nir_mode;
+ var->members[i]->data.patch = var->patch;
}
} else {
var->var = rzalloc(b->shader, nir_variable);
@@ -1409,6 +1431,7 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp opcode,
var->var->type = var->type->type;
var->var->interface_type = interface_type->type;
var->var->data.mode = nir_mode;
+var->var->data.patch = var->patch;
}
/* For inputs and outputs, we need to grab locations and builtin
___
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Mesa (master): vulkan: Update vk_icd.h to interface version 3
Module: Mesa
Branch: master
Commit: 98cf089849a2bae08a834d01f459b8f38c544918
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=98cf089849a2bae08a834d01f459b8f38c544918
Author: Chad Versace
Date: Tue Jan 10 12:40:55 2017 -0800
vulkan: Update vk_icd.h to interface version 3
Import from commit f2aeefec on branch 'master'
of https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers.
Reviewed-by: Emil Velikov
Cc: mesa-sta...@lists.freedesktop.org
---
include/vulkan/vk_icd.h | 110 ++--
1 file changed, 78 insertions(+), 32 deletions(-)
diff --git a/include/vulkan/vk_icd.h b/include/vulkan/vk_icd.h
index d664f2c..7b54fb5 100644
--- a/include/vulkan/vk_icd.h
+++ b/include/vulkan/vk_icd.h
@@ -1,28 +1,56 @@
+//
+// File: vk_icd.h
+//
+/*
+ * Copyright (c) 2015-2016 The Khronos Group Inc.
+ * Copyright (c) 2015-2016 Valve Corporation
+ * Copyright (c) 2015-2016 LunarG, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
#ifndef VKICD_H
#define VKICD_H
-#include "vk_platform.h"
+#include "vulkan.h"
/*
+ * Loader-ICD version negotiation API
+ */
+#define CURRENT_LOADER_ICD_INTERFACE_VERSION 3
+#define MIN_SUPPORTED_LOADER_ICD_INTERFACE_VERSION 0
+typedef VkResult (VKAPI_PTR
*PFN_vkNegotiateLoaderICDInterfaceVersion)(uint32_t *pVersion);
+/*
* The ICD must reserve space for a pointer for the loader's dispatch
* table, at the start of .
* The ICD must initialize this variable using the SET_LOADER_MAGIC_VALUE
macro.
*/
-#define ICD_LOADER_MAGIC 0x01CDC0DE
+#define ICD_LOADER_MAGIC 0x01CDC0DE
-typedef union _VK_LOADER_DATA {
- uintptr_t loaderMagic;
- void *loaderData;
+typedef union {
+uintptr_t loaderMagic;
+void *loaderData;
} VK_LOADER_DATA;
-static inline void set_loader_magic_value(void* pNewObject) {
-VK_LOADER_DATA *loader_info = (VK_LOADER_DATA *) pNewObject;
+static inline void set_loader_magic_value(void *pNewObject) {
+VK_LOADER_DATA *loader_info = (VK_LOADER_DATA *)pNewObject;
loader_info->loaderMagic = ICD_LOADER_MAGIC;
}
-static inline bool valid_loader_magic_value(void* pNewObject) {
-const VK_LOADER_DATA *loader_info = (VK_LOADER_DATA *) pNewObject;
+static inline bool valid_loader_magic_value(void *pNewObject) {
+const VK_LOADER_DATA *loader_info = (VK_LOADER_DATA *)pNewObject;
return (loader_info->loaderMagic & 0x) == ICD_LOADER_MAGIC;
}
@@ -30,56 +58,74 @@ static inline bool valid_loader_magic_value(void*
pNewObject) {
* Windows and Linux ICDs will treat VkSurfaceKHR as a pointer to a struct that
* contains the platform-specific connection and surface information.
*/
-typedef enum _VkIcdWsiPlatform {
+typedef enum {
VK_ICD_WSI_PLATFORM_MIR,
VK_ICD_WSI_PLATFORM_WAYLAND,
VK_ICD_WSI_PLATFORM_WIN32,
VK_ICD_WSI_PLATFORM_XCB,
VK_ICD_WSI_PLATFORM_XLIB,
+VK_ICD_WSI_PLATFORM_DISPLAY
} VkIcdWsiPlatform;
-typedef struct _VkIcdSurfaceBase {
-VkIcdWsiPlatform platform;
+typedef struct {
+VkIcdWsiPlatform platform;
} VkIcdSurfaceBase;
#ifdef VK_USE_PLATFORM_MIR_KHR
-typedef struct _VkIcdSurfaceMir {
-VkIcdSurfaceBase base;
-MirConnection* connection;
-MirSurface*mirSurface;
+typedef struct {
+VkIcdSurfaceBase base;
+MirConnection *connection;
+MirSurface *mirSurface;
} VkIcdSurfaceMir;
#endif // VK_USE_PLATFORM_MIR_KHR
#ifdef VK_USE_PLATFORM_WAYLAND_KHR
-typedef struct _VkIcdSurfaceWayland {
-VkIcdSurfaceBase base;
-struct wl_display* display;
-struct wl_surface* surface;
+typedef struct {
+VkIcdSurfaceBase base;
+struct wl_display *display;
+struct wl_surface *surface;
} VkIcdSurfaceWayland;
#endif // VK_USE_PLATFORM_WAYLAND_KHR
#ifdef VK_USE_PLATFORM_WIN32_KHR
-typedef struct _VkIcdSurfaceWin32 {
-VkIcdSurfaceBase base;
-HINSTANCE hinstance;
-HWND hwnd;
+typedef struct {
+VkIcdSurfaceBase base;
+HINSTANCE hinstance;
+HWND hwnd;
} VkIcdSurfaceWin32;
#endif // VK_USE_PLATFORM_WIN32_KHR
#ifdef VK_USE_PLATFORM_XCB_KHR
-typedef struct _VkIcdSurfaceXcb {
-VkIcdSurfaceBase base;
-xcb_connection_t* connection;
-xcb_window_t window;
+typedef struct {
+VkIcdSurfaceBase base;
+xcb_connection_t *connection;
+xcb_window_t window;
} VkIcdSurfaceXcb;
#endif // VK_USE_PLATFORM_XCB_KHR
#ifdef VK_USE_PLATFORM_XLIB_KHR
-typedef struct _VkIcdSurfaceXli
Mesa (master): vulkan: Add new cast macros for VkIcd types
Module: Mesa
Branch: master
Commit: c085bfcec9915879e97a33c5235cf21607c72318
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c085bfcec9915879e97a33c5235cf21607c72318
Author: Chad Versace
Date: Tue Jan 10 13:23:06 2017 -0800
vulkan: Add new cast macros for VkIcd types
We can't import the latest vk_icd.h because the new header breaks the
Mesa build. This patch defines new casting macros,
ICD_DEFINE_NONDISP_HANDLE_CASTS() and ICD_FROM_HANDLE(), which can
handle both the old and new vk_icd.h, and will prevent the build from
breaking when we update the header.
In the old vk_icd.h, types were defined as:
typedef struct _VkIcdFoo {
...
} VkIcdFoo;
Commit 6ebba1f6 in the Vulkan loader changed the above to
typedef {
...
} VkIcdFoo;
because the old definitions violated the C and C++ specs. According to
the specs, identifiers that begins with an underscore followed by an
uppercase letter are reserved. (It's pedantic, I know), See the Github
issue referenced below.
References:
https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/issues/7
References:
https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/commit/6ebba1f630015af7a78767a15c1e74ba9b23601c
Reviewed-by: Emil Velikov
Cc: mesa-sta...@lists.freedesktop.org
---
src/amd/vulkan/radv_wsi.c | 12 ++--
src/intel/vulkan/anv_wsi.c | 12 ++--
src/vulkan/wsi/wsi_common.h | 20 +++-
src/vulkan/wsi/wsi_common_wayland.c | 2 +-
src/vulkan/wsi/wsi_common_x11.c | 4 ++--
5 files changed, 34 insertions(+), 16 deletions(-)
diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index 2eb8e45..952f2c3 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -75,7 +75,7 @@ void radv_DestroySurfaceKHR(
const VkAllocationCallbacks* pAllocator)
{
RADV_FROM_HANDLE(radv_instance, instance, _instance);
- RADV_FROM_HANDLE(_VkIcdSurfaceBase, surface, _surface);
+ ICD_FROM_HANDLE(VkIcdSurfaceBase, surface, _surface);
vk_free2(&instance->alloc, pAllocator, surface);
}
@@ -87,7 +87,7 @@ VkResult radv_GetPhysicalDeviceSurfaceSupportKHR(
VkBool32* pSupported)
{
RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
- RADV_FROM_HANDLE(_VkIcdSurfaceBase, surface, _surface);
+ ICD_FROM_HANDLE(VkIcdSurfaceBase, surface, _surface);
struct wsi_interface *iface = device->wsi_device.wsi[surface->platform];
return iface->get_support(surface, &device->wsi_device,
@@ -101,7 +101,7 @@ VkResult radv_GetPhysicalDeviceSurfaceCapabilitiesKHR(
VkSurfaceCapabilitiesKHR* pSurfaceCapabilities)
{
RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
- RADV_FROM_HANDLE(_VkIcdSurfaceBase, surface, _surface);
+ ICD_FROM_HANDLE(VkIcdSurfaceBase, surface, _surface);
struct wsi_interface *iface = device->wsi_device.wsi[surface->platform];
return iface->get_capabilities(surface, pSurfaceCapabilities);
@@ -114,7 +114,7 @@ VkResult radv_GetPhysicalDeviceSurfaceFormatsKHR(
VkSurfaceFormatKHR* pSurfaceFormats)
{
RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
- RADV_FROM_HANDLE(_VkIcdSurfaceBase, surface, _surface);
+ ICD_FROM_HANDLE(VkIcdSurfaceBase, surface, _surface);
struct wsi_interface *iface = device->wsi_device.wsi[surface->platform];
return iface->get_formats(surface, &device->wsi_device,
pSurfaceFormatCount,
@@ -128,7 +128,7 @@ VkResult radv_GetPhysicalDeviceSurfacePresentModesKHR(
VkPresentModeKHR* pPresentModes)
{
RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
- RADV_FROM_HANDLE(_VkIcdSurfaceBase, surface, _surface);
+ ICD_FROM_HANDLE(VkIcdSurfaceBase, surface, _surface);
struct wsi_interface *iface = device->wsi_device.wsi[surface->platform];
return iface->get_present_modes(surface, pPresentModeCount,
@@ -249,7 +249,7 @@ VkResult radv_CreateSwapchainKHR(
VkSwapchainKHR* pSwapchain)
{
RADV_FROM_HANDLE(radv_device, device, _device);
- RADV_FROM_HANDLE(_VkIcdSurfaceBase, surface, pCreateInfo->surface);
+ ICD_FROM_HANDLE(VkIcdSurfaceBase, surface, pCreateInfo->surface);
struct wsi_interface *iface =
device->instance->physicalDevice.wsi_device.wsi[surface->platform];
struct wsi_swapchain *swapchain;
diff --git a/src/intel/vulkan/anv_wsi.c b/src/intel/vulkan/anv_wsi.c
index 669eacc..a01ef03 100644
--- a/src/intel/vulkan/anv_wsi.c
+++ b/src/intel/vulkan/anv_wsi.c
@@ -74,7 +74,7 @@ void anv_DestroySurfaceKHR(
const VkAllocationCallbacks* pAllocator)
{
ANV_FROM_HANDLE(anv_instance, instance, _instance);
- ANV_FROM_HANDLE(_VkIcdSurfaceBase, surface, _surfa
Mesa (master): anv: Support loader interface version 3 (patch v2)
Module: Mesa
Branch: master
Commit: 1e41d7f7b0855934744fe578ba4eae9209ee69f7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e41d7f7b0855934744fe578ba4eae9209ee69f7
Author: Chad Versace
Date: Tue Jan 10 17:29:08 2017 -0800
anv: Support loader interface version 3 (patch v2)
This patch implements vk_icdNegotiateLoaderICDInterfaceVersion(), which
brings us to loader interface v3.
v2:
- Drop the pragmas. [emil]
- Advertise v3 instead of v2. Anvil supported more than I
thought. [jason]
- s/Surface/SurfaceKHR/ in comments. [emil]
Reviewed-by: Emil Velikov
Cc: mesa-sta...@lists.freedesktop.org
Cc: Jason Ekstrand
---
src/intel/vulkan/anv_device.c | 44 +++
1 file changed, 44 insertions(+)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index f58d1ac..6349537 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -2034,3 +2034,47 @@ void anv_DestroyFramebuffer(
vk_free2(&device->alloc, pAllocator, fb);
}
+
+/* vk_icd.h does not declare this function, so we declare it here to
+ * suppress Wmissing-prototypes.
+ */
+PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
+vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t* pSupportedVersion);
+
+PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
+vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t* pSupportedVersion)
+{
+ /* For the full details on loader interface versioning, see
+*
.
+* What follows is a condensed summary, to help you navigate the large and
+* confusing official doc.
+*
+* - Loader interface v0 is incompatible with later versions. We don't
+* support it.
+*
+* - In loader interface v1:
+* - The first ICD entrypoint called by the loader is
+* vk_icdGetInstanceProcAddr(). The ICD must statically expose this
+* entrypoint.
+* - The ICD must statically expose no other Vulkan symbol unless it
is
+* linked with -Bsymbolic.
+* - Each dispatchable Vulkan handle created by the ICD must be
+* a pointer to a struct whose first member is VK_LOADER_DATA. The
+* ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
+* - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
+* vkDestroySurfaceKHR(). The ICD must be capable of working with
+* such loader-managed surfaces.
+*
+*- Loader interface v2 differs from v1 in:
+* - The first ICD entrypoint called by the loader is
+* vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
+* statically expose this entrypoint.
+*
+*- Loader interface v3 differs from v2 in:
+*- The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
+* vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
+* because the loader no longer does so.
+*/
+ *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
+ return VK_SUCCESS;
+}
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Mesa (master): Always defer memory free in swr_resource_destroy
Module: Mesa
Branch: master
Commit: a61528fa33f8d7f39167e62da6d9317ed84c43b8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a61528fa33f8d7f39167e62da6d9317ed84c43b8
Author: George Kyriazis
Date: Tue Jan 10 17:12:03 2017 -0600
Always defer memory free in swr_resource_destroy
Defer delete on regular resources. This ensures that any work being done
on the resource is completed before freeing up the resource's memory.
Reviewed-by: Bruce Cherniak
---
src/gallium/drivers/swr/swr_screen.cpp | 17 +
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/swr/swr_screen.cpp
b/src/gallium/drivers/swr/swr_screen.cpp
index cc8030e..5012388 100644
--- a/src/gallium/drivers/swr/swr_screen.cpp
+++ b/src/gallium/drivers/swr/swr_screen.cpp
@@ -880,18 +880,11 @@ swr_resource_destroy(struct pipe_screen *p_screen, struct
pipe_resource *pt)
winsys->displaytarget_destroy(winsys, spr->display_target);
} else {
- /* For regular resources, if the resource is being used, defer deletion
- * (use aligned-free) */
- if (pipe && spr->status) {
- swr_resource_unused(pt);
- swr_fence_work_free(screen->flush_fence,
- spr->swr.pBaseAddress, true);
- swr_fence_work_free(screen->flush_fence,
- spr->secondary.pBaseAddress, true);
- } else {
- AlignedFree(spr->swr.pBaseAddress);
- AlignedFree(spr->secondary.pBaseAddress);
- }
+ /* For regular resources, defer deletion */
+ swr_resource_unused(pt);
+ swr_fence_work_free(screen->flush_fence, spr->swr.pBaseAddress, true);
+ swr_fence_work_free(screen->flush_fence,
+ spr->secondary.pBaseAddress, true);
}
FREE(spr);
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Mesa (master): nir/i965: assert first is always less than 64
Module: Mesa
Branch: master
Commit: ce44501ea87ff66267c9cf280e4596065ffebd46
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ce44501ea87ff66267c9cf280e4596065ffebd46
Author: Juan A. Suarez Romero
Date: Thu Jan 12 10:31:34 2017 +0100
nir/i965: assert first is always less than 64
This fixes a defect detected by Coverity Scan.
Reviewed-by: Iago Toral Quiroga
---
src/mesa/drivers/dri/i965/brw_draw_upload.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index a865f27..04d7aa9 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -566,6 +566,7 @@ brw_prepare_vertices(struct brw_context *brw)
brw->vb.nr_enabled = 0;
while (vs_inputs) {
GLuint first = ffsll(vs_inputs) - 1;
+ assert (first < 64);
GLuint index =
first -
DIV_ROUND_UP(_mesa_bitcount_64(vs_prog_data->double_inputs_read &
BITFIELD64_MASK(first)), 2);
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Mesa (master): nv50/ir: use sched control codes for gm107 builtins
Module: Mesa Branch: master Commit: 90537d6a891df2cefa99b0fdcfec19dbeb8c5a78 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=90537d6a891df2cefa99b0fdcfec19dbeb8c5a78 Author: Samuel Pitoiset Date: Tue Dec 20 00:11:33 2016 +0100 nv50/ir: use sched control codes for gm107 builtins Yes, IMUL/IMAD require dependency barriers and we should definitely replace these instructions by XMAD but the different flags need to be figured out. Note that XMAD only supports 16-bits integers. Signed-off-by: Samuel Pitoiset Reviewed-by: Pierre Moreau --- src/gallium/drivers/nouveau/codegen/lib/gm107.asm | 40 +++--- .../drivers/nouveau/codegen/lib/gm107.asm.h| 40 +++--- 2 files changed, 40 insertions(+), 40 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/lib/gm107.asm b/src/gallium/drivers/nouveau/codegen/lib/gm107.asm index 67b98da..90741b6 100644 --- a/src/gallium/drivers/nouveau/codegen/lib/gm107.asm +++ b/src/gallium/drivers/nouveau/codegen/lib/gm107.asm @@ -11,39 +11,39 @@ // SIZE:22 / 14 * 8 bytes // gm107_div_u32: - sched (st 0x0) (st 0x0) (st 0x0) + sched (st 0xd wr 0x0 wt 0x3f) (st 0x1 wt 0x1) (st 0x6) flo u32 $r2 $r1 lop xor 1 $r2 $r2 0x1f mov $r3 0x1 0xf - sched (st 0x0) (st 0x0) (st 0x0) + sched (st 0x1) (st 0xf wr 0x0) (st 0x6 wr 0x0 wt 0x1) shl $r2 $r3 $r2 i2i u32 u32 $r1 neg $r1 imul u32 u32 $r3 $r1 $r2 - sched (st 0x0) (st 0x0) (st 0x0) + sched (st 0x6 wr 0x0 wt 0x1) (st 0x6 wr 0x0 wt 0x1) (st 0x6 wr 0x0 wt 0x1) imad u32 u32 hi $r2 $r2 $r3 $r2 imul u32 u32 $r3 $r1 $r2 imad u32 u32 hi $r2 $r2 $r3 $r2 - sched (st 0x0) (st 0x0) (st 0x0) + sched (st 0x6 wr 0x0 wt 0x1) (st 0x6 wr 0x0 wt 0x1) (st 0x6 wr 0x0 wt 0x1) imul u32 u32 $r3 $r1 $r2 imad u32 u32 hi $r2 $r2 $r3 $r2 imul u32 u32 $r3 $r1 $r2 - sched (st 0x0) (st 0x0) (st 0x0) + sched (st 0x6 wr 0x0 wt 0x1) (st 0x6 wr 0x0 wt 0x1) (st 0x6 wr 0x0 wt 0x1) imad u32 u32 hi $r2 $r2 $r3 $r2 imul u32 u32 $r3 $r1 $r2 imad u32 u32 hi $r2 $r2 $r3 $r2 - sched (st 0x0) (st 0x0) (st 0x0) + sched (st 0x6) (st 0x6 wr 0x0 rd 0x1 wt 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x2) mov $r3 $r0 0xf imul u32 u32 hi $r0 $r0 $r2 i2i u32 u32 $r2 neg $r1 - sched (st 0x0) (st 0x0) (st 0x0) + sched (st 0x6 wr 0x0 wt 0x3) (st 0xd wt 0x1) (st 0x1) imad u32 u32 $r1 $r1 $r0 $r3 isetp ge u32 and $p0 1 $r1 $r2 1 $p0 iadd $r1 $r1 neg $r2 - sched (st 0x0) (st 0x0) (st 0x0) + sched (st 0x5) (st 0xd) (st 0x1) $p0 iadd $r0 $r0 0x1 $p0 isetp ge u32 and $p0 1 $r1 $r2 1 $p0 iadd $r1 $r1 neg $r2 - sched (st 0x0) (st 0x0) (st 0x0) + sched (st 0x1) (st 0xf) (st 0xf) $p0 iadd $r0 $r0 0x1 ret nop 0 @@ -55,47 +55,47 @@ gm107_div_u32: // CLOBBER: $r2 - $r3, $p0 - $p3 // gm107_div_s32: - sched (st 0x0) (st 0x0) (st 0x0) + sched (st 0xd wt 0x3f) (st 0x1) (st 0x1 wr 0x0) isetp lt and $p2 0x1 $r0 0 1 isetp lt xor $p3 1 $r1 0 $p2 i2i s32 s32 $r0 abs $r0 - sched (st 0x0) (st 0x0) (st 0x0) + sched (st 0xf wr 0x1) (st 0xd wr 0x1 wt 0x2) (st 0x1 wt 0x2) i2i s32 s32 $r1 abs $r1 flo u32 $r2 $r1 lop xor 1 $r2 $r2 0x1f - sched (st 0x0) (st 0x0) (st 0x0) + sched (st 0x6) (st 0x1) (st 0xf wr 0x1) mov $r3 0x1 0xf shl $r2 $r3 $r2 i2i u32 u32 $r1 neg $r1 - sched (st 0x0) (st 0x0) (st 0x0) + sched (st 0x6 wr 0x1 wt 0x2) (st 0x6 wr 0x1 wt 0x2) (st 0x6 wr 0x1 wt 0x2) imul u32 u32 $r3 $r1 $r2 imad u32 u32 hi $r2 $r2 $r3 $r2 imul u32 u32 $r3 $r1 $r2 - sched (st 0x0) (st 0x0) (st 0x0) + sched (st 0x6 wr 0x1 wt 0x2) (st 0x6 wr 0x1 wt 0x2) (st 0x6 wr 0x1 wt 0x2) imad u32 u32 hi $r2 $r2 $r3 $r2 imul u32 u32 $r3 $r1 $r2 imad u32 u32 hi $r2 $r2 $r3 $r2 - sched (st 0x0) (st 0x0) (st 0x0) + sched (st 0x6 wr 0x1 wt 0x2) (st 0x6 wr 0x1 wt 0x2) (st 0x6 wr 0x1 wt 0x2) imul u32 u32 $r3 $r1 $r2 imad u32 u32 hi $r2 $r2 $r3 $r2 imul u32 u32 $r3 $r1 $r2 - sched (st 0x0) (st 0x0) (st 0x0) + sched (st 0x6 wr 0x1 rd 0x2 wt 0x2) (st 0x2 wt 0x5) (st 0x6 wr 0x0 rd 0x1 wt 0x2) imad u32 u32 hi $r2 $r2 $r3 $r2 mov $r3 $r0 0xf imul u32 u32 hi $r0 $r0 $r2 - sched (st 0x0) (st 0x0) (st 0x0) + sched (st 0xf wr 0x1 rd 0x2 wt 0x2) (st 0x6 wr 0x0 wt 0x5) (st 0xd wt 0x3) i2i u32 u32 $r2 neg $r1 imad u32 u32 $r1 $r1 $r0 $r3 isetp ge u32 and $p0 1 $r1 $r2 1 - sched (st 0x0) (st 0x0) (st 0x0) + sched (st 0x1) (st 0x5) (st 0xd) $p0 iadd $r1 $r1 neg $r2 $p0 iadd $r0 $r0 0x1 $p0 isetp ge u32 and $p0 1 $r1 $r2 1 - sched (st 0x0) (st 0x0) (st 0x0) + sched (st 0x1) (st 0x2) (st 0xf wr 0x0) $p0 iadd $r1 $r1 neg $r2 $p0 iadd $r0 $r0 0x1 $p3 i2i s32 s32 $r0 neg $r0 - sched (st 0x0) (st 0x0) (st 0x0) + sched (st 0xf wr 0x1) (st 0xf wt 0x3) (st 0xf) $p2 i2i s32 s32 $r1 neg $r1 ret nop 0 diff --git a/src/gallium/drivers/nouveau/codegen/lib/gm107.asm.h b/src/gallium/drivers/nouveau/codegen/lib
Mesa (master): nv50/ir: do not insert texture barriers on gm107
Module: Mesa
Branch: master
Commit: 1b3b4196f08bf825d031cdf6bfcbc7dd3ccf3172
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b3b4196f08bf825d031cdf6bfcbc7dd3ccf3172
Author: Samuel Pitoiset
Date: Fri Dec 16 14:22:16 2016 +0100
nv50/ir: do not insert texture barriers on gm107
It's actually useless to insert those texture barriers post RA
because the current control code (ie. st 0x0) will wait for all
dependencies before issuing a new instruction.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Ilia Mirkin
Reviewed-by: Pierre Moreau
---
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index fe18f47..ff253af 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -190,7 +190,8 @@ NVC0LegalizePostRA::NVC0LegalizePostRA(const Program *prog)
: rZero(NULL),
carry(NULL),
pOne(NULL),
- needTexBar(prog->getTarget()->getChipset() >= 0xe0)
+ needTexBar(prog->getTarget()->getChipset() >= 0xe0 &&
+prog->getTarget()->getChipset() < 0x110)
{
}
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Mesa (master): nvc0: use sched control codes for gm107 MP counters code
Module: Mesa
Branch: master
Commit: 38ff9980d792fc99e8e04898418dd6c9d198750e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=38ff9980d792fc99e8e04898418dd6c9d198750e
Author: Samuel Pitoiset
Date: Tue Dec 20 13:46:14 2016 +0100
nvc0: use sched control codes for gm107 MP counters code
Signed-off-by: Samuel Pitoiset
Reviewed-by: Pierre Moreau
---
.../drivers/nouveau/nvc0/nvc0_query_hw_sm.c| 88 +++---
1 file changed, 44 insertions(+), 44 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
index dae1721..df5723d 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
@@ -539,50 +539,50 @@ static const uint64_t nvf0_read_hw_sm_counters_code[] =
static const uint64_t gm107_read_hw_sm_counters_code[] =
{
- 0x001f8000fc0007e0ULL, /* sched (st 0x0) (st 0x0) (st 0x0) */
- 0xf0c802170008ULL, /* mov $r8 $tidx */
- 0xf0c80037000cULL, /* mov $r12 $virtid */
- 0xf0c80047ULL, /* mov $r0 $pm0 */
- 0x001f8000fc0007e0ULL, /* sched (st 0x0) (st 0x0) (st 0x0) */
- 0xf0c800570001ULL, /* mov $r1 $pm1 */
- 0xf0c800670002ULL, /* mov $r2 $pm2 */
- 0xf0c800770003ULL, /* mov $r3 $pm3 */
- 0x001f8000fc0007e0ULL, /* sched (st 0x0) (st 0x0) (st 0x0) */
- 0xf0c800870004ULL, /* mov $r4 $pm4 */
- 0xf0c800970005ULL, /* mov $r5 $pm5 */
- 0xf0c800a70006ULL, /* mov $r6 $pm6 */
- 0x001f8000fc0007e0ULL, /* sched (st 0x0) (st 0x0) (st 0x0) */
- 0xf0c800b70007ULL, /* mov $r7 $pm7 */
- 0x5b6403800087ff07ULL, /* isetp eq u32 and $p0 0x1 0x0 $r8 0x1 */
- 0x4c98079c1887000aULL, /* mov $r10 c7[0x620] 0xf */
- 0x001f8000fc0007e0ULL, /* sched (st 0x0) (st 0x0) (st 0x0) */
- 0x380091470c08ULL, /* bfe u32 $r8 $r12 0x914 */
- 0x4c98079c1897000bULL, /* mov $r11 c7[0x624] 0xf */
- 0x380020870c09ULL, /* bfe u32 $r9 $r12 0x208 */
- 0x001f8000fc0007e0ULL, /* sched (st 0x0) (st 0x0) (st 0x0) */
- 0xe308000fULL, /* not $p0 exit */
- 0x5b6403800097ff0fULL, /* isetp eq u32 and $p1 0x1 0x0 $r9 0x1 */
- 0x383806070808ULL, /* imul u32 u32 $r8 $r8 0x60 */
- 0x001f8000fc0007e0ULL, /* sched (st 0x0) (st 0x0) (st 0x0) */
- 0x38380107090cULL, /* imul u32 u32 $r12 $r9 0x10 */
- 0x38380047090dULL, /* imul u32 u32 $r13 $r9 0x4 */
- 0x5c1000d70809ULL, /* iadd $r9 $r8 $r13 */
- 0x001f8000fc0007e0ULL, /* sched (st 0x0) (st 0x0) (st 0x0) */
- 0x5c1000c70808ULL, /* iadd $r8 $r8 $r12 */
- 0x5c98078000a7000cULL, /* mov $r12 $r10 0xf */
- 0x5c1080870a0aULL, /* iadd cc $r10 $r10 $r8 */
- 0x001f8000fc0007e0ULL, /* sched (st 0x0) (st 0x0) (st 0x0) */
- 0x5c98078000b7000dULL, /* mov $r13 $r11 0xf */
- 0x5c1008000ff70b0bULL, /* iadd x $r11 $r11 0x0 */
- 0x5c1080970c0cULL, /* iadd cc $r12 $r12 $r9 */
- 0x001f8000fc0007e0ULL, /* sched (st 0x0) (st 0x0) (st 0x0) */
- 0x5c1008000ff70d0dULL, /* iadd x $r13 $r13 0x0 */
- 0xbfd70a00ULL, /* st e wt b128 g[$r10] $r0 0x1 */
- 0x4c98079c18a7ULL, /* mov $r0 c7[0x628] 0xf */
- 0x001f8000fc0007e0ULL, /* sched (st 0x0) (st 0x0) (st 0x0) */
- 0xbfd004010c04ULL, /* $p1 st e wt b128 g[$r12+0x40] $r4 0x1 */
- 0xbf9005070c00ULL, /* st e wt b32 g[$r12+0x50] $r0 0x1 */
- 0xe307000fULL, /* exit */
+ 0x001d0400e4200701ULL, /* sched (st 0x1 wr 0x0) (st 0x1 wr 0x1) (st 0x1 wr
0x2) */
+ 0xf0c802170008ULL, /* mov $r8 $tidx
*/
+ 0xf0c80037000cULL, /* mov $r12 $virtid
*/
+ 0xf0c80047ULL, /* mov $r0 $pm0
*/
+ 0x001e8400f0200761ULL, /* sched (st 0x1 wr 0x3) (st 0x1 wr 0x4) (st 0x1 wr
0x5) */
+ 0xf0c800570001ULL, /* mov $r1 $pm1
*/
+ 0xf0c800670002ULL, /* mov $r2 $pm2
*/
+ 0xf0c800770003ULL, /* mov $r3 $pm3
*/
+ 0x001e8400f42007a1ULL, /* sched (st 0x1 wr 0x5) (st 0x1 wr 0x5) (st 0x1 wr
0x5) */
+ 0xf0c800870004ULL, /* mov $r4 $pm4
Mesa (master): nvc0: enable GL 4.3 on gm107+
Module: Mesa
Branch: master
Commit: f0997e2aa8b5628a8cccbd5adf9b22a053c6be54
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0997e2aa8b5628a8cccbd5adf9b22a053c6be54
Author: Samuel Pitoiset
Date: Mon Aug 22 20:42:39 2016 +0200
nvc0: enable GL 4.3 on gm107+
Although, arb_shader_image_load_store-atomicity will most likely
hang your box, I think it's now quite reasonable to enable GL 4.3
on Maxwell/Pascal GPUs. I suspect that test to be wrong because
it doesn't even work on the NVIDIA blob.
I have tested a bunch of benchmarks (UE4 demos) and real games
like Shadow of Mordor and they all work fine.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 2531591..b6e4c6c 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -125,9 +125,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
return 128 * 1024 * 1024;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
- if (class_3d <= NVF0_3D_CLASS)
- return 430;
- return 410;
+ return 430;
case PIPE_CAP_MAX_RENDER_TARGETS:
return 8;
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
@@ -388,11 +386,10 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
unsigned shader,
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
- if (class_3d == NVE4_3D_CLASS || class_3d == NVF0_3D_CLASS)
+ if (class_3d >= NVE4_3D_CLASS)
+ return NVC0_MAX_IMAGES;
+ if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
return NVC0_MAX_IMAGES;
- if (class_3d < NVE4_3D_CLASS)
- if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
-return NVC0_MAX_IMAGES;
return 0;
default:
NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
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Mesa (master): nv50/ir: improve instruction pipelining on gm107
Module: Mesa
Branch: master
Commit: f519c47f7d47d88ecf3b5e8f28fdffaa12f684d3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f519c47f7d47d88ecf3b5e8f28fdffaa12f684d3
Author: Samuel Pitoiset
Date: Fri Dec 16 14:28:14 2016 +0100
nv50/ir: improve instruction pipelining on gm107
This makes use of scheduling control codes which are very useful
for improving the instruction pipelining.
This patch will increase performance on Maxwell GPUs by, at least,
x1.5 up to x3.5 for some benchmarks.
Although this has been fairly well tested, I would not be suprised
if someone hit a corner case somewhere. That way, the scheduler
is enabled by default but it can be deactivated by using
NV50_PROG_SCHED=0.
Thanks to Scott Gray for the reverse engineering work available from
https://github.com/NervanaSystems/maxas/wiki/Control-Codes.
Signed-off-by: Samuel Pitoiset
Acked-by: Pierre Moreau
Tested-by: Alexandre Courbot
Tested-by: Jan Vesely
---
.../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 771 -
.../nouveau/codegen/nv50_ir_target_gm107.cpp | 253 +++
.../drivers/nouveau/codegen/nv50_ir_target_gm107.h | 7 +
3 files changed, 1027 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index 5bd0fa0..f3ebd2b 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
@@ -24,6 +24,8 @@
#include "codegen/nv50_ir_target_gm107.h"
+//#define GM107_DEBUG_SCHED_DATA
+
namespace nv50_ir {
class CodeEmitterGM107 : public CodeEmitter
@@ -3374,20 +3376,781 @@ CodeEmitterGM107::getMinEncodingSize(const Instruction
*i) const
class SchedDataCalculatorGM107 : public Pass
{
public:
- SchedDataCalculatorGM107(const Target *targ) : targ(targ) {}
+ SchedDataCalculatorGM107(const TargetGM107 *targ) : targ(targ) {}
+
private:
- const Target *targ;
- bool visit(BasicBlock *bb);
+ struct RegScores
+ {
+ struct ScoreData {
+ int r[256];
+ int p[8];
+ int c;
+ } rd, wr;
+ int base;
+
+ void rebase(const int base)
+ {
+ const int delta = this->base - base;
+ if (!delta)
+return;
+ this->base = 0;
+
+ for (int i = 0; i < 256; ++i) {
+rd.r[i] += delta;
+wr.r[i] += delta;
+ }
+ for (int i = 0; i < 8; ++i) {
+rd.p[i] += delta;
+wr.p[i] += delta;
+ }
+ rd.c += delta;
+ wr.c += delta;
+ }
+ void wipe()
+ {
+ memset(&rd, 0, sizeof(rd));
+ memset(&wr, 0, sizeof(wr));
+ }
+ int getLatest(const ScoreData& d) const
+ {
+ int max = 0;
+ for (int i = 0; i < 256; ++i)
+if (d.r[i] > max)
+ max = d.r[i];
+ for (int i = 0; i < 8; ++i)
+if (d.p[i] > max)
+ max = d.p[i];
+ if (d.c > max)
+max = d.c;
+ return max;
+ }
+ inline int getLatestRd() const
+ {
+ return getLatest(rd);
+ }
+ inline int getLatestWr() const
+ {
+ return getLatest(wr);
+ }
+ inline int getLatest() const
+ {
+ return MAX2(getLatestRd(), getLatestWr());
+ }
+ void setMax(const RegScores *that)
+ {
+ for (int i = 0; i < 256; ++i) {
+rd.r[i] = MAX2(rd.r[i], that->rd.r[i]);
+wr.r[i] = MAX2(wr.r[i], that->wr.r[i]);
+ }
+ for (int i = 0; i < 8; ++i) {
+rd.p[i] = MAX2(rd.p[i], that->rd.p[i]);
+wr.p[i] = MAX2(wr.p[i], that->wr.p[i]);
+ }
+ rd.c = MAX2(rd.c, that->rd.c);
+ wr.c = MAX2(wr.c, that->wr.c);
+ }
+ void print(int cycle)
+ {
+ for (int i = 0; i < 256; ++i) {
+if (rd.r[i] > cycle)
+ INFO("rd $r%i @ %i\n", i, rd.r[i]);
+if (wr.r[i] > cycle)
+ INFO("wr $r%i @ %i\n", i, wr.r[i]);
+ }
+ for (int i = 0; i < 8; ++i) {
+if (rd.p[i] > cycle)
+ INFO("rd $p%i @ %i\n", i, rd.p[i]);
+if (wr.p[i] > cycle)
+ INFO("wr $p%i @ %i\n", i, wr.p[i]);
+ }
+ if (rd.c > cycle)
+INFO("rd $c @ %i\n", rd.c);
+ if (wr.c > cycle)
+INFO("wr $c @ %i\n", wr.c);
+ }
+ };
+
+ RegScores *score; // for current BB
+ std::vector scoreBoards;
+
+ const TargetGM107 *targ;
+ bool visit(Function *);
+ bool visit(BasicBlock *);
+
+ void commitInsn(const Instruction *, int);
+ int calcDelay(const Instruction *, int) const;
+ void setDelay(Instruction *, int, const Instruction *);
+ void recordWr(const Value *, int, int);
+ void checkRd(const Value *, int, int&) const;
+
+ inline void emitYield(Instruction *);
+ inline void emitStall(Instruction *, uint8_t);
Mesa (master): nvc0: use sched control codes for gm107 blitter shader
Module: Mesa
Branch: master
Commit: 75e6992379b239c618931925122a5d724d45e385
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=75e6992379b239c618931925122a5d724d45e385
Author: Samuel Pitoiset
Date: Sun Dec 11 23:17:10 2016 +0100
nvc0: use sched control codes for gm107 blitter shader
Signed-off-by: Samuel Pitoiset
Reviewed-by: Pierre Moreau
Acked-by: Ilia Mirkin
---
src/gallium/drivers/nouveau/nvc0/nvc0_surface.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
index 0d14058..d567d82 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
@@ -836,12 +836,20 @@ nvc0_blitter_make_vp(struct nvc0_blitter *blit)
};
static const uint32_t code_gm107[] =
{
- 0xfc0007e0, 0x001f8000, /* sched (st 0x0) (st 0x0) (st 0x0) */
- 0x0807ff04, 0xefd8ff80, /* ld b64 $r4 a[0x80] 0x0 */
- 0x0907ff00, 0xefd97f80, /* ld b96 $r0 a[0x90] 0x0 */
- 0x0707ff04, 0xeff0ff80, /* st b64 a[0x70] $r4 0x0 */
- 0xfc0007e0, 0x, /* sched (st 0x0) (st 0x0) (st 0x0) */
- 0x0807ff00, 0xeff17f80, /* st b96 a[0x80] $r0 0x0 */
+ 0xe4200701, 0x001d0400, /* sched (st 0x1 wr 0x0) (st 0x1 wr 0x1) (st 0x1
wr 0x2) */
+ 0x0807ff00, 0xefd87f80, /* ld b32 $r0 a[0x80] 0x0 */
+ 0x0847ff01, 0xefd87f80, /* ld b32 $r1 a[0x84] 0x0 */
+ 0x0907ff02, 0xefd87f80, /* ld b32 $r2 a[0x90] 0x0 */
+ 0xf0200761, 0x003f8400, /* sched (st 0x1 wr 0x3) (st 0x1 wr 0x4) (st 0x1
wt 0x1) */
+ 0x0947ff03, 0xefd87f80, /* ld b32 $r3 a[0x94] 0x0 */
+ 0x0987ff04, 0xefd87f80, /* ld b32 $r4 a[0x98] 0x0 */
+ 0x0707ff00, 0xeff07f80, /* st b32 a[0x70] $r0 0x0 */
+ 0xfc2017e1, 0x011f8404, /* sched (st 0x1 wt 0x2) (st 0x1 wt 0x4) (st 0x1
wt 0x8) */
+ 0x0747ff01, 0xeff07f80, /* st b32 a[0x74] $r1 0x0 */
+ 0x0807ff02, 0xeff07f80, /* st b32 a[0x80] $r2 0x0 */
+ 0x0847ff03, 0xeff07f80, /* st b32 a[0x84] $r3 0x0 */
+ 0xfde087e1, 0x001f8000, /* sched (st 0x1 wt 0x10) (st 0xf) (st 0x0) */
+ 0x0887ff04, 0xeff07f80, /* st b32 a[0x88] $r4 0x0 */
0x0007000f, 0xe300, /* exit */
};
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Mesa (master): i965: check for dual slot attributes on any gen
Module: Mesa Branch: master Commit: 6bb4255f8ebb8cc048afe498e11738985d134f8a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6bb4255f8ebb8cc048afe498e11738985d134f8a Author: Juan A. Suarez Romero Date: Wed Dec 14 17:12:24 2016 + i965: check for dual slot attributes on any gen Those not supporting 64 bit input vertex attributes will have the dual_slot value as false. Reviewed-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 9c36d05..a865f27 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -570,8 +570,7 @@ brw_prepare_vertices(struct brw_context *brw) first - DIV_ROUND_UP(_mesa_bitcount_64(vs_prog_data->double_inputs_read & BITFIELD64_MASK(first)), 2); struct brw_vertex_element *input = &brw->vb.inputs[index]; - input->is_dual_slot = brw->gen >= 8 && - (vs_prog_data->double_inputs_read & BITFIELD64_BIT(first)) != 0; + input->is_dual_slot = (vs_prog_data->double_inputs_read & BITFIELD64_BIT(first)) != 0; vs_inputs &= ~BITFIELD64_BIT(first); if (input->is_dual_slot) vs_inputs &= ~BITFIELD64_BIT(first + 1); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/vec4: emit correctly load_inputs for 64bit data
Module: Mesa
Branch: master
Commit: f51a5b51ab92ada4b9f3b1d603f9de60b66e46ce
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f51a5b51ab92ada4b9f3b1d603f9de60b66e46ce
Author: Juan A. Suarez Romero
Date: Wed Jul 6 12:40:49 2016 +0200
i965/vec4: emit correctly load_inputs for 64bit data
For dvec3 and dvec4 types, a single GRF do not have enough space to
allocate two inputs from two different vertices (SIMD4x2).
So the GRF only contains first two components for the two vertices, and
the next GRF has the remaining components.
We want to put all the components for the same vertex in the same
register. Thus, we do a shuffle to reorder the data.
Reviewed-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 21 +++--
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 98e023a..71156ec 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -417,15 +417,24 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr)
/* We set EmitNoIndirectInput for VS */
assert(const_offset);
+ dest = get_nir_dest(instr->dest);
+ dest.writemask = brw_writemask_for_size(instr->num_components);
+
src = src_reg(ATTR, instr->const_index[0] + const_offset->u32[0],
glsl_type::uvec4_type);
- /* Swizzle source based on component layout qualifier */
- src.swizzle = BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr));
-
- dest = get_nir_dest(instr->dest, src.type);
- dest.writemask = brw_writemask_for_size(instr->num_components);
+ src = retype(src, dest.type);
- emit(MOV(dest, src));
+ bool is_64bit = nir_dest_bit_size(instr->dest) == 64;
+ if (is_64bit) {
+ dst_reg tmp = dst_reg(this, glsl_type::dvec4_type);
+ src.swizzle = BRW_SWIZZLE_XYZW;
+ shuffle_64bit_data(tmp, src, false);
+ emit(MOV(dest, src_reg(tmp)));
+ } else {
+ /* Swizzle source based on component layout qualifier */
+ src.swizzle = BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr));
+ emit(MOV(dest, src));
+ }
break;
}
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Mesa (master): i965: enable ARB_shader_precision to HSW+
Module: Mesa
Branch: master
Commit: 77077986eb281f7537b77b91445778b7d75a81d7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=77077986eb281f7537b77b91445778b7d75a81d7
Author: Samuel Iglesias Gonsálvez
Date: Mon Oct 17 13:59:18 2016 +0200
i965: enable ARB_shader_precision to HSW+
v2: update docs (Jordan)
Signed-off-by: Samuel Iglesias Gonsálvez
Signed-off-by: Juan A. Suarez Romero
Reviewed-by: Jordan Justen
---
docs/features.txt| 2 +-
docs/relnotes/17.0.0.html| 1 +
src/mesa/drivers/dri/i965/intel_extensions.c | 2 +-
3 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/docs/features.txt b/docs/features.txt
index 37accac..efa780f 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -141,7 +141,7 @@ GL 4.1, GLSL 4.10 --- all DONE: i965/gen8+, nvc0, r600,
radeonsi
GL_ARB_ES2_compatibility DONE (i965, nv50,
llvmpipe, softpipe, swr)
GL_ARB_get_program_binary DONE (0 binary formats)
GL_ARB_separate_shader_objectsDONE (all drivers)
- GL_ARB_shader_precision DONE (all drivers that
support GLSL 4.10)
+ GL_ARB_shader_precision DONE (i965/hsw+, all
drivers that support GLSL 4.10)
GL_ARB_vertex_attrib_64bitDONE (i965/hsw+,
llvmpipe, softpipe)
GL_ARB_viewport_array DONE (i965, nv50,
llvmpipe, softpipe)
diff --git a/docs/relnotes/17.0.0.html b/docs/relnotes/17.0.0.html
index 3ca8305..bd397d2 100644
--- a/docs/relnotes/17.0.0.html
+++ b/docs/relnotes/17.0.0.html
@@ -49,6 +49,7 @@ Note: some of the new features are only available with
certain drivers.
GL_NV_image_formats on any driver supporting
GL_ARB_shader_image_load_store (i965, nvc0, radeonsi, softpipe)
GL_ARB_gpu_shader_fp64 in i965/haswell
GL_ARB_vertex_attrib_64bit in i965/haswell
+GL_ARB_shader_precision in i965/haswell
Intel Haswell now supports OpenGL 4.0
GL_OES_geometry_shader on i965/haswell
GL_OES_texture_cube_map_array on i965/haswell
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index afe5f8a..dc46772 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -238,6 +238,7 @@ intelInitExtensions(struct gl_context *ctx)
if (brw->gen >= 8 || brw->is_haswell) {
ctx->Extensions.ARB_gpu_shader_fp64 = true;
+ ctx->Extensions.ARB_shader_precision = true;
ctx->Extensions.ARB_stencil_texturing = true;
ctx->Extensions.ARB_texture_stencil8 = true;
ctx->Extensions.ARB_vertex_attrib_64bit = true;
@@ -263,7 +264,6 @@ intelInitExtensions(struct gl_context *ctx)
}
if (brw->gen >= 8) {
- ctx->Extensions.ARB_shader_precision = true;
ctx->Extensions.ARB_ES3_2_compatibility = true;
}
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Mesa (master): i965: downsize *64*PASSTHRU formats to equivalent *32*FLOAT formats on gen < 8
Module: Mesa
Branch: master
Commit: 329cbe363dcc465764719d91f8f31c8606769ba4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=329cbe363dcc465764719d91f8f31c8606769ba4
Author: Alejandro Piñeiro
Date: Mon Apr 11 10:05:24 2016 +0200
i965: downsize *64*PASSTHRU formats to equivalent *32*FLOAT formats on gen < 8
gen < 8 doesn't support *64*PASSTHRU formats when emitting
vertices. So in order to provide the equivalent functionality, we need
to downsize the format to equivalent *32*FLOAT, and in some cases
(R64G64B64 and R64G64B64A64) submit two 3DSTATE_VERTEX_ELEMENTS for
each vertex element.
Signed-off-by: Alejandro Piñeiro
Signed-off-by: Juan A. Suarez Romero
Reviewed-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_draw_upload.c | 169 +++-
1 file changed, 139 insertions(+), 30 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 79eb634..9c36d05 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -242,6 +242,86 @@ double_types(struct brw_context *brw,
: double_types_float[size]);
}
+static bool
+is_passthru_format(uint32_t format)
+{
+ switch (format) {
+ case BRW_SURFACEFORMAT_R64_PASSTHRU:
+ case BRW_SURFACEFORMAT_R64G64_PASSTHRU:
+ case BRW_SURFACEFORMAT_R64G64B64_PASSTHRU:
+ case BRW_SURFACEFORMAT_R64G64B64A64_PASSTHRU:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static int
+uploads_needed(uint32_t format)
+{
+ if (!is_passthru_format(format))
+ return 1;
+
+ switch (format) {
+ case BRW_SURFACEFORMAT_R64_PASSTHRU:
+ case BRW_SURFACEFORMAT_R64G64_PASSTHRU:
+ return 1;
+ case BRW_SURFACEFORMAT_R64G64B64_PASSTHRU:
+ case BRW_SURFACEFORMAT_R64G64B64A64_PASSTHRU:
+ return 2;
+ default:
+ unreachable("not reached");
+ }
+}
+
+/*
+ * Returns the number of componentes associated with a format that is used on
+ * a 64 to 32 format split. See downsize_format()
+ */
+static int
+upload_format_size(uint32_t upload_format)
+{
+ switch (upload_format) {
+ case BRW_SURFACEFORMAT_R32G32_FLOAT:
+ return 2;
+ case BRW_SURFACEFORMAT_R32G32B32A32_FLOAT:
+ return 4;
+ default:
+ unreachable("not reached");
+ }
+}
+
+/*
+ * Returns the format that we are finally going to use when upload a vertex
+ * element. It will only change if we are using *64*PASSTHRU formats, as for
+ * gen < 8 they need to be splitted on two *32*FLOAT formats.
+ *
+ * @upload points in which upload we are. Valid values are [0,1]
+ */
+static uint32_t
+downsize_format_if_needed(uint32_t format,
+ int upload)
+{
+ assert(upload == 0 || upload == 1);
+
+ if (!is_passthru_format(format))
+ return format;
+
+ switch (format) {
+ case BRW_SURFACEFORMAT_R64_PASSTHRU:
+ return BRW_SURFACEFORMAT_R32G32_FLOAT;
+ case BRW_SURFACEFORMAT_R64G64_PASSTHRU:
+ return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
+ case BRW_SURFACEFORMAT_R64G64B64_PASSTHRU:
+ return !upload ? BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
+ : BRW_SURFACEFORMAT_R32G32_FLOAT;
+ case BRW_SURFACEFORMAT_R64G64B64A64_PASSTHRU:
+ return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
+ default:
+ unreachable("not reached");
+ }
+}
+
/**
* Given vertex array type/size/format/normalized info, return
* the appopriate hardware surface type.
@@ -805,6 +885,18 @@ brw_emit_vertices(struct brw_context *brw)
if (vs_prog_data->uses_drawid)
nr_elements++;
+ /* If any of the formats of vb.enabled needs more that one upload, we need
+* to add it to nr_elements */
+ unsigned extra_uploads = 0;
+ for (unsigned i = 0; i < brw->vb.nr_enabled; i++) {
+ struct brw_vertex_element *input = brw->vb.enabled[i];
+ uint32_t format = brw_get_vertex_surface_type(brw, input->glarray);
+
+ if (uploads_needed(format) > 1)
+ extra_uploads++;
+ }
+ nr_elements += extra_uploads;
+
/* If the VS doesn't read any inputs (calculating vertex position from
* a state variable for some reason, for example), emit a single pad
* VERTEX_ELEMENT struct and bail.
@@ -908,6 +1000,10 @@ brw_emit_vertices(struct brw_context *brw)
uint32_t comp1 = BRW_VE1_COMPONENT_STORE_SRC;
uint32_t comp2 = BRW_VE1_COMPONENT_STORE_SRC;
uint32_t comp3 = BRW_VE1_COMPONENT_STORE_SRC;
+ unsigned num_uploads = 1;
+ unsigned c;
+
+ num_uploads = uploads_needed(format);
if (input == &brw->vb.inputs[VERT_ATTRIB_EDGEFLAG]) {
/* Gen6+ passes edgeflag as sideband along with the vertex, instead
@@ -920,38 +1016,51 @@ brw_emit_vertices(struct brw_context *brw)
}
}
- switch (input->glarray->Size) {
- case 0: comp0 = BRW_VE1_COMPONENT_STORE_0;
- case 1: comp1 = BRW_VE1_COMPONENT_STORE_0;
- case 2: comp2 = BRW_VE1_COMPONENT_STORE_0;
- case 3: comp3 = input->glarr
Mesa (master): i965/vec4: use attribute slots for first non payload GRF
Module: Mesa Branch: master Commit: f8310189f4a31c443657cd0c1aef35db02b86c95 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f8310189f4a31c443657cd0c1aef35db02b86c95 Author: Alejandro Piñeiro Date: Thu Apr 21 12:23:47 2016 +0200 i965/vec4: use attribute slots for first non payload GRF As part of the payload setup, setup_attributes is called with the first GRF that can be used for the attributes (first ones are used for uniforms for example) and returns the first GRF that is not part of the payload. Before this patch, it adds directly the number of attributes. But as with 64-bit attributes can consume more than one slot, that is not valid anymore. This patch change the addition to use the number of slots consumed. gen >= 8 would not be affected, as they use the scalar mode. For that case, the vs configuration is done at fs_visitor::assign_vs_urb_setup. v2: add explanation in commit log (Jordan) Reviewed-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 5ddbe58..f80162d 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -1757,7 +1757,7 @@ vec4_vs_visitor::setup_attributes(int payload_reg) lower_attributes_to_hw_regs(attribute_map, false /* interleaved */); - return payload_reg + vs_prog_data->nr_attributes; + return payload_reg + vs_prog_data->nr_attribute_slots; } int ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: unify the code to enable of ARB_gpu_shader_fp64 and ARB_vertex_attrib_64bit for HSW+
Module: Mesa
Branch: master
Commit: 1d1ddbaa562fb3a60c4c612e1b6a8d0e2e402d0a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1d1ddbaa562fb3a60c4c612e1b6a8d0e2e402d0a
Author: Samuel Iglesias Gonsálvez
Date: Mon Oct 17 13:58:27 2016 +0200
i965: unify the code to enable of ARB_gpu_shader_fp64 and
ARB_vertex_attrib_64bit for HSW+
Signed-off-by: Samuel Iglesias Gonsálvez
Signed-off-by: Juan A. Suarez Romero
Reviewed-by: Jordan Justen
---
src/mesa/drivers/dri/i965/intel_extensions.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index ac877cc..afe5f8a 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -218,11 +218,6 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.OES_primitive_bounding_box = true;
ctx->Extensions.OES_texture_buffer = true;
- if (brw->is_haswell) {
- ctx->Extensions.ARB_gpu_shader_fp64 = true;
- ctx->Extensions.ARB_vertex_attrib_64bit = true;
- }
-
if (can_do_pipelined_register_writes(brw->screen)) {
ctx->Extensions.ARB_draw_indirect = true;
ctx->Extensions.ARB_transform_feedback2 = true;
@@ -242,8 +237,10 @@ intelInitExtensions(struct gl_context *ctx)
}
if (brw->gen >= 8 || brw->is_haswell) {
+ ctx->Extensions.ARB_gpu_shader_fp64 = true;
ctx->Extensions.ARB_stencil_texturing = true;
ctx->Extensions.ARB_texture_stencil8 = true;
+ ctx->Extensions.ARB_vertex_attrib_64bit = true;
ctx->Extensions.OES_geometry_shader = true;
ctx->Extensions.OES_texture_cube_map_array = true;
ctx->Extensions.OES_viewport_array = true;
@@ -266,9 +263,7 @@ intelInitExtensions(struct gl_context *ctx)
}
if (brw->gen >= 8) {
- ctx->Extensions.ARB_gpu_shader_fp64 = true;
ctx->Extensions.ARB_shader_precision = true;
- ctx->Extensions.ARB_vertex_attrib_64bit = true;
ctx->Extensions.ARB_ES3_2_compatibility = true;
}
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Mesa (master): i965/vec4: take into account doubles when creating attribute mapping
Module: Mesa
Branch: master
Commit: 58fdb85f0f413d1a144d4beb6519da59bc52c974
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=58fdb85f0f413d1a144d4beb6519da59bc52c974
Author: Alejandro Piñeiro
Date: Thu Apr 21 14:16:18 2016 +0200
i965/vec4: take into account doubles when creating attribute mapping
Doubles needs more that one slot per attribute. So when filling the
attribute_map we check if it is a double in order to allocate one
extra register.
Signed-off-by: Alejandro Piñeiro
Signed-off-by: Juan A. Suarez Romero
Reviewed-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index f80162d..748a068 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1733,10 +1733,15 @@ vec4_vs_visitor::setup_attributes(int payload_reg)
memset(attribute_map, 0, sizeof(attribute_map));
nr_attributes = 0;
- for (int i = 0; i < VERT_ATTRIB_MAX; i++) {
- if (vs_prog_data->inputs_read & BITFIELD64_BIT(i)) {
-attribute_map[i] = payload_reg + nr_attributes;
-nr_attributes++;
+ GLbitfield64 vs_inputs = vs_prog_data->inputs_read;
+ while (vs_inputs) {
+ GLuint first = ffsll(vs_inputs) - 1;
+ int needed_slots =
+ (vs_prog_data->double_inputs_read & BITFIELD64_BIT(first)) ? 2 : 1;
+ for (int c = 0; c < needed_slots; c++) {
+ attribute_map[nr_attributes] = payload_reg + nr_attributes;
+ nr_attributes++;
+ vs_inputs &= ~BITFIELD64_BIT(first + c);
}
}
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Mesa (master): i965/vec4/nir: vec4 also needs to remap vs attributes
Module: Mesa
Branch: master
Commit: 57bab6708f2bbc1ab8a3d202e9a467963596d462
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=57bab6708f2bbc1ab8a3d202e9a467963596d462
Author: Alejandro Piñeiro
Date: Fri Apr 22 10:49:24 2016 +0200
i965/vec4/nir: vec4 also needs to remap vs attributes
Doubles need extra space, so we would need to do a remapping for vec4
too in order to take that into account. We reuse the already
existing remap_vs_attrs, but passing is_scalar, so they could
remap accordingly.
v2: code-format remap_vs_attrs_params initialization (Matt)
Signed-off-by: Alejandro Piñeiro
Signed-off-by: Juan A. Suarez Romero
Reviewed-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_nir.c | 32 ++--
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c
b/src/mesa/drivers/dri/i965/brw_nir.c
index 3c1bc51..b39e2b1 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -95,9 +95,19 @@ add_const_offset_to_base(nir_shader *nir, nir_variable_mode
mode)
}
}
+struct remap_vs_attrs_params {
+ shader_info *nir_info;
+ bool is_scalar;
+};
+
static bool
-remap_vs_attrs(nir_block *block, shader_info *nir_info)
+remap_vs_attrs(nir_block *block, void *closure)
{
+ struct remap_vs_attrs_params *params =
+ (struct remap_vs_attrs_params *) closure;
+ shader_info *nir_info = params->nir_info;
+ bool is_scalar = params->is_scalar;
+
nir_foreach_instr(instr, block) {
if (instr->type != nir_instr_type_intrinsic)
continue;
@@ -113,7 +123,7 @@ remap_vs_attrs(nir_block *block, shader_info *nir_info)
int attr = intrin->const_index[0];
int slot = _mesa_bitcount_64(nir_info->inputs_read &
BITFIELD64_MASK(attr));
- intrin->const_index[0] = 4 * slot;
+ intrin->const_index[0] = is_scalar ? 4 * slot : slot;
}
}
return true;
@@ -257,6 +267,11 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
bool use_legacy_snorm_formula,
const uint8_t *vs_attrib_wa_flags)
{
+ struct remap_vs_attrs_params params = {
+ .nir_info = nir->info,
+ .is_scalar = is_scalar
+ };
+
/* Start with the location of the variable's base. */
foreach_list_typed(nir_variable, var, node, &nir->inputs) {
var->data.driver_location = var->data.location;
@@ -276,14 +291,11 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
brw_nir_apply_attribute_workarounds(nir, use_legacy_snorm_formula,
vs_attrib_wa_flags);
- if (is_scalar) {
- /* Finally, translate VERT_ATTRIB_* values into the actual registers. */
-
- nir_foreach_function(function, nir) {
- if (function->impl) {
-nir_foreach_block(block, function->impl) {
- remap_vs_attrs(block, nir->info);
-}
+ /* Finally, translate VERT_ATTRIB_* values into the actual registers. */
+ nir_foreach_function(function, nir) {
+ if (function->impl) {
+ nir_foreach_block(block, function->impl) {
+remap_vs_attrs(block, ¶ms);
}
}
}
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Mesa (master): i965: Enable ARB_vertex_attrib_64bit for Haswell
Module: Mesa
Branch: master
Commit: 485955be9c59ce56af9de41eaf9898526ee24be8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=485955be9c59ce56af9de41eaf9898526ee24be8
Author: Alejandro Piñeiro
Date: Thu Jul 7 11:49:33 2016 +0200
i965: Enable ARB_vertex_attrib_64bit for Haswell
v2: update docs (Jordan)
Signed-off-by: Alejandro Piñeiro
Signed-off-by: Juan A. Suarez Romero
Reviewed-by: Jordan Justen
---
docs/features.txt| 2 +-
docs/relnotes/17.0.0.html| 1 +
src/mesa/drivers/dri/i965/intel_extensions.c | 4 +++-
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/docs/features.txt b/docs/features.txt
index 65ef8ee..37accac 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -142,7 +142,7 @@ GL 4.1, GLSL 4.10 --- all DONE: i965/gen8+, nvc0, r600,
radeonsi
GL_ARB_get_program_binary DONE (0 binary formats)
GL_ARB_separate_shader_objectsDONE (all drivers)
GL_ARB_shader_precision DONE (all drivers that
support GLSL 4.10)
- GL_ARB_vertex_attrib_64bitDONE (llvmpipe,
softpipe)
+ GL_ARB_vertex_attrib_64bitDONE (i965/hsw+,
llvmpipe, softpipe)
GL_ARB_viewport_array DONE (i965, nv50,
llvmpipe, softpipe)
diff --git a/docs/relnotes/17.0.0.html b/docs/relnotes/17.0.0.html
index 899d24c..3ca8305 100644
--- a/docs/relnotes/17.0.0.html
+++ b/docs/relnotes/17.0.0.html
@@ -48,6 +48,7 @@ Note: some of the new features are only available with
certain drivers.
GL_INTEL_conservative_rasterization on i965/gen9+
GL_NV_image_formats on any driver supporting
GL_ARB_shader_image_load_store (i965, nvc0, radeonsi, softpipe)
GL_ARB_gpu_shader_fp64 in i965/haswell
+GL_ARB_vertex_attrib_64bit in i965/haswell
Intel Haswell now supports OpenGL 4.0
GL_OES_geometry_shader on i965/haswell
GL_OES_texture_cube_map_array on i965/haswell
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 915797a..ac877cc 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -218,8 +218,10 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.OES_primitive_bounding_box = true;
ctx->Extensions.OES_texture_buffer = true;
- if (brw->is_haswell)
+ if (brw->is_haswell) {
ctx->Extensions.ARB_gpu_shader_fp64 = true;
+ ctx->Extensions.ARB_vertex_attrib_64bit = true;
+ }
if (can_do_pipelined_register_writes(brw->screen)) {
ctx->Extensions.ARB_draw_indirect = true;
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Mesa (master): i965/gen7: expose OpenGL 4.2 on Haswell when supported
Module: Mesa Branch: master Commit: 75968a668e44b3fd7c9b9277937c005366fca116 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=75968a668e44b3fd7c9b9277937c005366fca116 Author: Juan A. Suarez Romero Date: Tue Oct 11 15:05:36 2016 + i965/gen7: expose OpenGL 4.2 on Haswell when supported GL_ARB_vertex_attrib_64bit was the last piece missing. v2: update docs (Jordan) Signed-off-by: Juan A. Suarez Romero Reviewed-by: Jordan Justen --- docs/features.txt| 4 ++-- docs/relnotes/17.0.0.html| 2 +- src/mesa/drivers/dri/i965/intel_extensions.c | 2 +- src/mesa/drivers/dri/i965/intel_screen.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/docs/features.txt b/docs/features.txt index efa780f..dd40ac4 100644 --- a/docs/features.txt +++ b/docs/features.txt @@ -136,7 +136,7 @@ GL 4.0, GLSL 4.00 --- all DONE: i965/hsw+, nvc0, r600, radeonsi GL_ARB_transform_feedback3DONE (i965/gen7+, llvmpipe, softpipe, swr) -GL 4.1, GLSL 4.10 --- all DONE: i965/gen8+, nvc0, r600, radeonsi +GL 4.1, GLSL 4.10 --- all DONE: i965/hsw+, nvc0, r600, radeonsi GL_ARB_ES2_compatibility DONE (i965, nv50, llvmpipe, softpipe, swr) GL_ARB_get_program_binary DONE (0 binary formats) @@ -146,7 +146,7 @@ GL 4.1, GLSL 4.10 --- all DONE: i965/gen8+, nvc0, r600, radeonsi GL_ARB_viewport_array DONE (i965, nv50, llvmpipe, softpipe) -GL 4.2, GLSL 4.20 -- all DONE: i965/gen8+, nvc0, radeonsi +GL 4.2, GLSL 4.20 -- all DONE: i965/hsw+, nvc0, radeonsi GL_ARB_texture_compression_bptc DONE (i965, r600) GL_ARB_compressed_texture_pixel_storage DONE (all drivers) diff --git a/docs/relnotes/17.0.0.html b/docs/relnotes/17.0.0.html index bd397d2..b50f9e9 100644 --- a/docs/relnotes/17.0.0.html +++ b/docs/relnotes/17.0.0.html @@ -50,7 +50,7 @@ Note: some of the new features are only available with certain drivers. GL_ARB_gpu_shader_fp64 in i965/haswell GL_ARB_vertex_attrib_64bit in i965/haswell GL_ARB_shader_precision in i965/haswell -Intel Haswell now supports OpenGL 4.0 +Intel Haswell now supports OpenGL 4.2 GL_OES_geometry_shader on i965/haswell GL_OES_texture_cube_map_array on i965/haswell GL_OES_viewport_array on i965/haswell diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index dc46772..7a40eba 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -137,7 +137,7 @@ intelInitExtensions(struct gl_context *ctx) if (brw->gen >= 8) ctx->Const.GLSLVersion = 450; else if (brw->is_haswell && can_do_pipelined_register_writes(brw->screen)) - ctx->Const.GLSLVersion = 400; + ctx->Const.GLSLVersion = 420; else if (brw->gen >= 6) ctx->Const.GLSLVersion = 330; else diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 5fcb5c6..a8d401c 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -1539,7 +1539,7 @@ set_max_gl_versions(struct intel_screen *screen) break; case 7: dri_screen->max_gl_core_version = screen->devinfo.is_haswell && - can_do_pipelined_register_writes(screen) ? 40 : 33; + can_do_pipelined_register_writes(screen) ? 42 : 33; dri_screen->max_gl_compat_version = 30; dri_screen->max_gl_es1_version = 11; dri_screen->max_gl_es2_version = screen->devinfo.is_haswell ? 31 : 30; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: return PASSTHRU surface types also on gen7
Module: Mesa Branch: master Commit: 717f99b34a329d21d7b65e3193c6bf2162ad7964 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=717f99b34a329d21d7b65e3193c6bf2162ad7964 Author: Alejandro Piñeiro Date: Fri Apr 15 19:08:04 2016 +0200 i965: return PASSTHRU surface types also on gen7 Although gen7 doesn't include surface types as a valid conversion format, we return it, as it reflects what we want to achieve, even if we need to workaround it on gen < 8. Reviewed-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index b7527f2..79eb634 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -231,9 +231,13 @@ double_types(struct brw_context *brw, * 64-bit components are stored in the URB without any conversion." * Also included on BDW PRM, Volume 7, page 470, table "Source Element * Formats Supported in VF Unit" -* Previous PRMs don't include those references. +* +* Previous PRMs don't include those references, so for gen7 we can't use +* PASSTHRU formats directly. But in any case, we prefer to return passthru +* even in that case, because that reflects what we want to achieve, even +* if we would need to workaround on gen < 8. */ - return (brw->gen >= 8 && doubles + return (doubles ? double_types_passthru[size] : double_types_float[size]); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): main/buffers: update error handling on DrawBuffers for 4.5
Module: Mesa
Branch: master
Commit: d54bc7e01f3f2e3178adecf53ea243470a3d5d93
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d54bc7e01f3f2e3178adecf53ea243470a3d5d93
Author: Alejandro Piñeiro
Date: Tue Dec 13 08:58:59 2016 -0200
main/buffers: update error handling on DrawBuffers for 4.5
Before 4.5, GL_BACK was not allowed as a value of bufs. Since 4.5 it
is allowed under some circumstances:
From the OpenGL 4.5 specification, Section 17.4.1 "Selecting Buffers
for Writing", page 493 (page 515 of the PDF):
"An INVALID_ENUM error is generated if any value in bufs is FRONT,
LEFT, RIGHT, or FRONT_AND_BACK . This restriction applies to both
the de- fault framebuffer and framebuffer objects, and exists
because these constants may themselves refer to multiple buffers, as
shown in table 17.4."
And on page 492 (page 514 of the PDF):
"If the default framebuffer is affected, then each of the constants
must be one of the values listed in table 17.6 or the special value
BACK . When BACK is used, n must be 1 and color values are written
into the left buffer for single-buffered contexts, or into the back
left buffer for double-buffered contexts."
This patch keeps the same behaviour if OpenGL version is < 4. We
assume that for 4.x this is the intended behaviour, so a fix, but for
3.x the intended behaviour is the already in place.
Part of the fix for:
GL45-CTS.direct_state_access.framebuffers_draw_read_buffers_errors
v2: remove forgot printf
v3: remove spaces before commas on spec quote, split line too
long (Anuj)
Reviewed-by: Anuj Phogat
---
src/mesa/main/buffers.c | 46 +-
1 file changed, 33 insertions(+), 13 deletions(-)
diff --git a/src/mesa/main/buffers.c b/src/mesa/main/buffers.c
index 2b24e5a..bba5e7e 100644
--- a/src/mesa/main/buffers.c
+++ b/src/mesa/main/buffers.c
@@ -343,7 +343,9 @@ _mesa_NamedFramebufferDrawBuffer(GLuint framebuffer, GLenum
buf)
* \param n number of outputs
* \param buffers array [n] of renderbuffer names. Unlike glDrawBuffer, the
* names cannot specify more than one buffer. For example,
- * GL_FRONT_AND_BACK is illegal.
+ * GL_FRONT_AND_BACK is illegal. The only exception is GL_BACK
+ * that is considered special and allowed as far as n is one
+ * since 4.5.
*/
static void
draw_buffers(struct gl_context *ctx, struct gl_framebuffer *fb,
@@ -401,20 +403,38 @@ draw_buffers(struct gl_context *ctx, struct
gl_framebuffer *fb,
return;
}
- /* From the OpenGL 4.0 specification, page 256:
- * "For both the default framebuffer and framebuffer objects, the
- * constants FRONT, BACK, LEFT, RIGHT, and FRONT_AND_BACK are not
- * valid in the bufs array passed to DrawBuffers, and will result in
- * the error INVALID_ENUM. This restriction is because these
- * constants may themselves refer to multiple buffers, as shown in
- * table 4.4."
- * Previous versions of the OpenGL specification say INVALID_OPERATION,
- * but the Khronos conformance tests expect INVALID_ENUM.
+ /* From the OpenGL 4.5 specification, page 493 (page 515 of the PDF)
+ * "An INVALID_ENUM error is generated if any value in bufs is FRONT,
+ * LEFT, RIGHT, or FRONT_AND_BACK . This restriction applies to both
+ * the default framebuffer and framebuffer objects, and exists because
+ * these constants may themselves refer to multiple buffers, as shown
+ * in table 17.4."
+ *
+ * And on page 492 (page 514 of the PDF):
+ * "If the default framebuffer is affected, then each of the constants
+ * must be one of the values listed in table 17.6 or the special value
+ * BACK. When BACK is used, n must be 1 and color values are written
+ * into the left buffer for single-buffered contexts, or into the back
+ * left buffer for double-buffered contexts."
+ *
+ * Note "special value BACK". GL_BACK also refers to multiple buffers,
+ * but it is consider a special case here. This is a change on 4.5. For
+ * OpenGL 4.x we check that behaviour. For any previous version we keep
+ * considering it wrong (as INVALID_ENUM).
*/
if (_mesa_bitcount(destMask[output]) > 1) {
- _mesa_error(ctx, GL_INVALID_ENUM, "%s(invalid buffer %s)",
- caller, _mesa_enum_to_string(buffers[output]));
- return;
+ if (_mesa_is_winsys_fbo(fb) && ctx->Version >= 40 &&
+ buffers[output] == GL_BACK) {
+if (n != 1) {
+ _mesa_error(ctx, GL_INVALID_OPERATION, "%s(with GL_BACK n must
be 1)",
+ caller);
+ return;
+}
+ } else {
+_mesa_error(ctx, GL_INVALID_ENUM, "%s(invalid buffer %s)",
+caller, _mesa_enum_to_string(buffers[output]))
Mesa (master): main/buffers: take into account FRONT_AND_BACK on ReadBuffer
Module: Mesa Branch: master Commit: f354cd5c69b0b1fe7db87473240a51ecc7369c03 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f354cd5c69b0b1fe7db87473240a51ecc7369c03 Author: Alejandro Piñeiro Date: Wed Jan 11 18:11:55 2017 -0200 main/buffers: take into account FRONT_AND_BACK on ReadBuffer From OpenGL 3.1 spec, section 4.3.1 "Reading Pixels", page 190 (203 PDF) "When READ FRAMEBUFFER BINDING is zero, i.e. the default framebuffer, src must be one of the values listed in table 4.4, including NONE . FRONT_AND_BACK , FRONT , and LEFT refer to the front left buffer." There is an equivalent text on OpenGL 4.5 spec, section 18.2.1 "Selecting Buffers for Reading", page 502 (524 PDF), so the behaviour is still the same. Part of the fix for: GL45-CTS.direct_state_access.framebuffers_draw_read_buffers_errors Reviewed-by: Anuj Phogat --- src/mesa/main/buffers.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/main/buffers.c b/src/mesa/main/buffers.c index bba5e7e..7d17ae9 100644 --- a/src/mesa/main/buffers.c +++ b/src/mesa/main/buffers.c @@ -204,6 +204,8 @@ read_buffer_enum_to_index(const struct gl_context *ctx, GLenum buffer) return BUFFER_FRONT_LEFT; case GL_AUX0: return BUFFER_AUX0; + case GL_FRONT_AND_BACK: + return BUFFER_FRONT_LEFT; case GL_AUX1: case GL_AUX2: case GL_AUX3: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: num_records is in units of stride for swizzled buffers even on VI
Module: Mesa Branch: master Commit: e33910b0d977071dc715e8d0927ebb63c0b4647c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e33910b0d977071dc715e8d0927ebb63c0b4647c Author: Nicolai Hähnle Date: Thu Dec 15 16:11:54 2016 +0100 radeonsi: num_records is in units of stride for swizzled buffers even on VI The old setting didn't hurt, but this is cleaner. Reviewed-by: Marek Olšák --- src/gallium/drivers/radeonsi/si_shader.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 5dfbd66..6f0f414 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -5872,8 +5872,6 @@ static void preload_ring_buffers(struct si_shader_context *ctx) assert(stride < (1 << 14)); num_records = 64; - if (ctx->screen->b.chip_class >= VI) - num_records *= stride; ring = LLVMBuildBitCast(builder, base_ring, v2i64, ""); tmp = LLVMBuildExtractElement(builder, ring, uint->zero, ""); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): docs: document INTEL_PRECISE_TRIG envvar
Module: Mesa Branch: master Commit: 883ca597df0debbf27431c218b2acb72986c52e2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=883ca597df0debbf27431c218b2acb72986c52e2 Author: Juan A. Suarez Romero Date: Wed Jan 11 18:51:35 2017 +0100 docs: document INTEL_PRECISE_TRIG envvar v2: use more generic description (Jordan) Reviewed-by: Jordan Justen --- docs/envvars.html | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/envvars.html b/docs/envvars.html index 9eee8db..276cea3 100644 --- a/docs/envvars.html +++ b/docs/envvars.html @@ -187,6 +187,8 @@ See the Xlib software driver page for details. do32 - generate compute shader SIMD32 programs even if workgroup size doesn't exceed the SIMD16 limit norbc - disable single sampled render buffer compression +INTEL_PRECISE_TRIG - if set to 1, true or yes, then the driver prefers + accuracy over performance in trig functions. ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
