Mesa (master): i965: Fix compiler warning about write being undefined.
Module: Mesa
Branch: master
Commit: afa7b2f19975f45234637f47859fdd768551a080
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=afa7b2f19975f45234637f47859fdd768551a080
Author: Eric Anholt
Date: Sat Feb 10 11:19:00 2018 +
i965: Fix compiler warning about write being undefined.
This looks like it should be protected by the assume() about
nr_color_regions, but my compiler warns anyway.
Reviewed-by: Matt Turner
---
src/intel/compiler/brw_fs.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 6fb46e7374..bed632d21b 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -3070,7 +3070,7 @@ fs_visitor::emit_repclear_shader()
.MOV(vec4(brw_message_reg(color_mrf)), fs_reg(reg));
}
- fs_inst *write;
+ fs_inst *write = NULL;
if (key->nr_color_regions == 1) {
write = bld.emit(FS_OPCODE_REP_FB_WRITE);
write->saturate = key->clamp_fragment_color;
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Mesa (master): loader: Fix compiler warnings about truncating the PCI ID path.
Module: Mesa
Branch: master
Commit: 7075c084fc5699d76970d2f045c8c7c668dc53d8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7075c084fc5699d76970d2f045c8c7c668dc53d8
Author: Eric Anholt
Date: Sat Feb 10 10:45:18 2018 +
loader: Fix compiler warnings about truncating the PCI ID path.
My build was producing:
../src/loader/loader.c:121:67: warning: ‘%1u’ directive output may be truncated
writing between 1 and 3 bytes into a region of size 2 [-Wformat-truncation=]
and we can avoid this careful calculation by just using asprintf (as we do
elsewhere in the file).
Reviewed-by: Eric Engestrom
Reviewed-by: Emil Velikov
Reviewed-by: Ian Romanick
---
src/loader/loader.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/src/loader/loader.c b/src/loader/loader.c
index 913b3dcac0..92b4c5204b 100644
--- a/src/loader/loader.c
+++ b/src/loader/loader.c
@@ -110,17 +110,16 @@ static char *loader_get_dri_config_device_id(void)
static char *drm_construct_id_path_tag(drmDevicePtr device)
{
-#define PCI_ID_PATH_TAG_LENGTH sizeof("pci-_xx_xx_x")
char *tag = NULL;
if (device->bustype == DRM_BUS_PCI) {
-tag = calloc(PCI_ID_PATH_TAG_LENGTH, sizeof(char));
-if (tag == NULL)
-return NULL;
-
-snprintf(tag, PCI_ID_PATH_TAG_LENGTH, "pci-%04x_%02x_%02x_%1u",
- device->businfo.pci->domain, device->businfo.pci->bus,
- device->businfo.pci->dev, device->businfo.pci->func);
+ if (asprintf(&tag, "pci-%04x_%02x_%02x_%1u",
+ device->businfo.pci->domain,
+ device->businfo.pci->bus,
+ device->businfo.pci->dev,
+ device->businfo.pci->func) < 0) {
+ return NULL;
+ }
}
return tag;
}
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Mesa (master): glsl/tests: Fix a compiler warning about signed/unsigned loop comparison.
Module: Mesa
Branch: master
Commit: 4636ce362d4defc70a2b40cab1f52d1c890f5673
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4636ce362d4defc70a2b40cab1f52d1c890f5673
Author: Eric Anholt
Date: Sat Feb 10 11:03:38 2018 +
glsl/tests: Fix a compiler warning about signed/unsigned loop comparison.
Fixes: d32956935edf ("glsl: Walk a list of ir_dereference_array to mark array
elements as accessed")
Reviewed-by: Ian Romanick
---
src/compiler/glsl/tests/array_refcount_test.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/compiler/glsl/tests/array_refcount_test.cpp
b/src/compiler/glsl/tests/array_refcount_test.cpp
index ecd7f46900..0d8f4521ca 100644
--- a/src/compiler/glsl/tests/array_refcount_test.cpp
+++ b/src/compiler/glsl/tests/array_refcount_test.cpp
@@ -628,7 +628,7 @@ TEST_F(array_refcount_test, visit_array_indexing_an_array)
ir_array_refcount_entry *const entry_c = v.get_variable_entry(var_c);
- for (unsigned i = 0; i < var_c->type->array_size(); i++) {
+ for (int i = 0; i < var_c->type->array_size(); i++) {
EXPECT_EQ(true, entry_c->is_linearized_index_referenced(i)) <<
"array c, i = " << i;
}
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Mesa (master): glsl: Silence warnings in the uniform initializer test about 16-bit types
Module: Mesa
Branch: master
Commit: 1b313eedb5e5da3c7ee3f62a83b66a6e097fe0d3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b313eedb5e5da3c7ee3f62a83b66a6e097fe0d3
Author: Eric Anholt
Date: Sat Feb 10 10:41:07 2018 +
glsl: Silence warnings in the uniform initializer test about 16-bit types
They should probably get unit tests implemented, but this cleans up a
bunch of warnings in my build for now.
Fixes: 59f458cd8703 ("glsl: Add 16-bit types")
Cc: Eduardo Lima Mitev
Reviewed-by: Ian Romanick
---
src/compiler/glsl/tests/uniform_initializer_utils.cpp | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/compiler/glsl/tests/uniform_initializer_utils.cpp
b/src/compiler/glsl/tests/uniform_initializer_utils.cpp
index a1c68c8272..0d7fa26752 100644
--- a/src/compiler/glsl/tests/uniform_initializer_utils.cpp
+++ b/src/compiler/glsl/tests/uniform_initializer_utils.cpp
@@ -110,6 +110,9 @@ generate_data_element(void *mem_ctx, const glsl_type *type,
case GLSL_TYPE_INTERFACE:
case GLSL_TYPE_SUBROUTINE:
case GLSL_TYPE_FUNCTION:
+ case GLSL_TYPE_FLOAT16:
+ case GLSL_TYPE_UINT16:
+ case GLSL_TYPE_INT16:
ASSERT_TRUE(false);
break;
}
@@ -150,6 +153,9 @@ generate_data_element(void *mem_ctx, const glsl_type *type,
case GLSL_TYPE_INTERFACE:
case GLSL_TYPE_SUBROUTINE:
case GLSL_TYPE_FUNCTION:
+ case GLSL_TYPE_FLOAT16:
+ case GLSL_TYPE_UINT16:
+ case GLSL_TYPE_INT16:
ASSERT_TRUE(false);
break;
}
@@ -278,6 +284,9 @@ verify_data(gl_constant_value *storage, unsigned
storage_array_size,
case GLSL_TYPE_INTERFACE:
case GLSL_TYPE_SUBROUTINE:
case GLSL_TYPE_FUNCTION:
+ case GLSL_TYPE_FLOAT16:
+ case GLSL_TYPE_UINT16:
+ case GLSL_TYPE_INT16:
ASSERT_TRUE(false);
break;
}
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Mesa (master): i965: Enable disk shader cache by default
Module: Mesa
Branch: master
Commit: 96fe36f7acc62130c40a8881c02ad6b8155b5533
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=96fe36f7acc62130c40a8881c02ad6b8155b5533
Author: Jordan Justen
Date: Wed Nov 8 15:42:14 2017 -0800
i965: Enable disk shader cache by default
Signed-off-by: Jordan Justen
Reviewed-by: Timothy Arceri
Reviewed-by: Tapani Pälli
Acked-by: Kenneth Graunke
---
docs/relnotes/18.1.0.html | 1 +
src/mesa/drivers/dri/i965/brw_disk_cache.c | 3 ---
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/docs/relnotes/18.1.0.html b/docs/relnotes/18.1.0.html
index 93cf1f2b4f..0aca0aa1ab 100644
--- a/docs/relnotes/18.1.0.html
+++ b/docs/relnotes/18.1.0.html
@@ -47,6 +47,7 @@ Note: some of the new features are only available with
certain drivers.
GL_ARB_bindless_texture on nvc0/maxwell+
GL_EXT_semaphore on radeonsi
GL_EXT_semaphore_fd on radeonsi
+Disk shader cache support for i965 enabled by default
Bug fixes
diff --git a/src/mesa/drivers/dri/i965/brw_disk_cache.c
b/src/mesa/drivers/dri/i965/brw_disk_cache.c
index f989456bcd..41f742e858 100644
--- a/src/mesa/drivers/dri/i965/brw_disk_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_disk_cache.c
@@ -407,9 +407,6 @@ void
brw_disk_cache_init(struct intel_screen *screen)
{
#ifdef ENABLE_SHADER_CACHE
- if (env_var_as_boolean("MESA_GLSL_CACHE_DISABLE", true))
- return;
-
char renderer[10];
MAYBE_UNUSED int len = snprintf(renderer, sizeof(renderer), "i965_%04x",
screen->deviceID);
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Mesa (master): radv: don't send num_tcs_input_cp to sgprs.
Module: Mesa
Branch: master
Commit: baa0feb73d0c011f3a2b29626244d3936532361e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=baa0feb73d0c011f3a2b29626244d3936532361e
Author: Dave Airlie
Date: Mon Feb 19 04:59:53 2018 +
radv: don't send num_tcs_input_cp to sgprs.
We never use it in the shaders.
Reviewed-by: Samuel Pitoiset
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_pipeline.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index a2dec0e3bd..9990a3e863 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -68,7 +68,6 @@ struct radv_tessellation_state {
uint32_t offchip_layout;
unsigned num_patches;
unsigned lds_size;
- unsigned num_tcs_input_cp;
uint32_t tf_param;
};
@@ -1397,7 +1396,6 @@ calculate_tess_state(struct radv_pipeline *pipeline,
S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
tess.num_patches = num_patches;
- tess.num_tcs_input_cp = num_tcs_input_cp;
struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
unsigned type = 0, partitioning = 0, topology = 0, distribution_mode =
0;
@@ -2621,8 +2619,7 @@ radv_pipeline_generate_tess_shaders(struct
radeon_winsys_cs *cs,
radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 4);
radeon_emit(cs, tess->offchip_layout);
radeon_emit(cs, tess->tcs_out_offsets);
- radeon_emit(cs, tess->tcs_out_layout |
- tess->num_tcs_input_cp << 26);
+ radeon_emit(cs, tess->tcs_out_layout);
radeon_emit(cs, tess->tcs_in_layout);
}
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Mesa (master): ac/radv: remove total_vertices variable
Module: Mesa
Branch: master
Commit: 0e6f0d400b9078262844de6664f5f83f6566b567
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0e6f0d400b9078262844de6664f5f83f6566b567
Author: Dave Airlie
Date: Mon Feb 19 06:53:21 2018 +
ac/radv: remove total_vertices variable
This just removes an unneeded variable.
Reviewed-by: Samuel Pitoiset
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 1cea5486e4..88b1abd2ae 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2771,14 +2771,12 @@ static LLVMValueRef get_tcs_tes_buffer_address(struct
radv_shader_context *ctx,
LLVMValueRef vertex_index,
LLVMValueRef param_index)
{
- LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
+ LLVMValueRef base_addr, vertices_per_patch, num_patches;
LLVMValueRef param_stride, constant16;
LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9,
6);
num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
- total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
- num_patches, "");
constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
if (vertex_index) {
@@ -2788,7 +2786,8 @@ static LLVMValueRef get_tcs_tes_buffer_address(struct
radv_shader_context *ctx,
base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
vertex_index, "");
- param_stride = total_vertices;
+ param_stride = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
+ num_patches, "");
} else {
base_addr = rel_patch_id;
param_stride = num_patches;
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Mesa (master): ac/radv: don't mark tess inner as used if we don't use it.
Module: Mesa
Branch: master
Commit: e9b9fb36168cccdc6a1c14e86b4aec5321bd57e0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9b9fb36168cccdc6a1c14e86b4aec5321bd57e0
Author: Dave Airlie
Date: Mon Feb 19 20:33:17 2018 +
ac/radv: don't mark tess inner as used if we don't use it.
This just avoids marking it as a used output if we don't
actually use it.
Reviewed-by: Samuel Pitoiset
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 2185c53834..1cea5486e4 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -6360,8 +6360,8 @@ write_tess_factors(struct radv_shader_context *ctx)
struct ac_build_if_state if_ctx, inner_if_ctx;
LLVMValueRef invocation_id = unpack_param(&ctx->ac,
ctx->abi.tcs_rel_ids, 8, 5);
LLVMValueRef rel_patch_id = unpack_param(&ctx->ac,
ctx->abi.tcs_rel_ids, 0, 8);
- unsigned tess_inner_index, tess_outer_index;
- LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
+ unsigned tess_inner_index = 0, tess_outer_index;
+ LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
int i;
emit_barrier(&ctx->ac, ctx->stage);
@@ -6390,14 +6390,17 @@ write_tess_factors(struct radv_shader_context *ctx)
LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
invocation_id, ctx->ac.i32_0, ""));
- tess_inner_index =
shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
- tess_outer_index =
shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
+ lds_base = get_tcs_out_current_patch_data_offset(ctx);
+
+ if (inner_comps) {
+ tess_inner_index =
shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
+ mark_tess_output(ctx, true, tess_inner_index);
+ lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
+LLVMConstInt(ctx->ac.i32,
tess_inner_index * 4, false), "");
+ }
- mark_tess_output(ctx, true, tess_inner_index);
+ tess_outer_index =
shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
mark_tess_output(ctx, true, tess_outer_index);
- lds_base = get_tcs_out_current_patch_data_offset(ctx);
- lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
-LLVMConstInt(ctx->ac.i32, tess_inner_index *
4, false), "");
lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
LLVMConstInt(ctx->ac.i32, tess_outer_index *
4, false), "");
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Mesa (master): ac/radv: cleanup some tcs output values access
Module: Mesa
Branch: master
Commit: 77fd1b9187a3aec665257ced5e58fae6fc89290f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=77fd1b9187a3aec665257ced5e58fae6fc89290f
Author: Dave Airlie
Date: Mon Feb 19 06:19:07 2018 +
ac/radv: cleanup some tcs output values access
Just consolidates some code to make it easier to change.
Reviewed-by: Samuel Pitoiset
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 88b1abd2ae..ec4dd098ed 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -383,6 +383,12 @@ get_tcs_out_patch_stride(struct radv_shader_context *ctx)
}
static LLVMValueRef
+get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
+{
+ return unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
+}
+
+static LLVMValueRef
get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
{
return LLVMBuildMul(ctx->ac.builder,
@@ -2899,7 +2905,7 @@ load_tcs_varyings(struct ac_shader_abi *abi,
dw_addr = get_tcs_in_current_patch_offset(ctx);
} else {
if (!is_patch) {
- stride = unpack_param(&ctx->ac, ctx->tcs_out_layout,
13, 8);
+ stride = get_tcs_out_vertex_stride(ctx);
dw_addr = get_tcs_out_current_patch_offset(ctx);
} else {
dw_addr = get_tcs_out_current_patch_data_offset(ctx);
@@ -2955,7 +2961,7 @@ store_tcs_output(struct ac_shader_abi *abi,
}
if (!is_patch) {
- stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
+ stride = get_tcs_out_vertex_stride(ctx);
dw_addr = get_tcs_out_current_patch_offset(ctx);
} else {
dw_addr = get_tcs_out_current_patch_data_offset(ctx);
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Mesa (master): radv/tess: don't need to look in constant for vertices_per_patch
Module: Mesa
Branch: master
Commit: 95ddd423bce3b6e836f3ae305cbad0622e22
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=95ddd423bce3b6e836f3ae305cbad0622e22
Author: Dave Airlie
Date: Mon Feb 19 04:55:52 2018 +
radv/tess: don't need to look in constant for vertices_per_patch
This just avoids passing this value via user sgprs.
Reviewed-by: Samuel Pitoiset
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 5 -
src/amd/vulkan/radv_pipeline.c | 2 +-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index ec4dd098ed..351e6fa9ef 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -127,6 +127,7 @@ struct radv_shader_context {
uint32_t tcs_patch_outputs_read;
uint64_t tcs_outputs_read;
+ uint32_t tcs_vertices_per_patch;
};
static inline struct radv_shader_context *
@@ -2781,7 +2782,7 @@ static LLVMValueRef get_tcs_tes_buffer_address(struct
radv_shader_context *ctx,
LLVMValueRef param_stride, constant16;
LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
- vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9,
6);
+ vertices_per_patch = LLVMConstInt(ctx->ac.i32,
ctx->tcs_vertices_per_patch, false);
num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
@@ -6905,11 +6906,13 @@ LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
ctx.abi.load_tess_varyings = load_tcs_varyings;
ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
ctx.abi.store_tcs_outputs = store_tcs_output;
+ ctx.tcs_vertices_per_patch =
shaders[i]->info.tess.tcs_vertices_out;
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
ctx.tes_primitive_mode =
shaders[i]->info.tess.primitive_mode;
ctx.abi.load_tess_varyings = load_tes_input;
ctx.abi.load_tess_coord = load_tess_coord;
ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
+ ctx.tcs_vertices_per_patch =
shaders[i]->info.tess.tcs_vertices_out;
} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
if (shader_info->info.vs.needs_instance_id) {
if (ctx.options->key.vs.as_ls) {
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 88646fda2f..a2dec0e3bd 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1391,7 +1391,7 @@ calculate_tess_state(struct radv_pipeline *pipeline,
tess.tcs_out_offsets = (output_patch0_offset / 16) |
((perpatch_output_offset / 16) << 16);
tess.offchip_layout = (pervertex_output_patch_size * num_patches << 16)
|
- (num_tcs_output_cp << 9) | num_patches;
+ num_patches;
tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
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Mesa (master): ac/nir: to integer the args to bcsel.
Module: Mesa
Branch: master
Commit: d5b2d7ed670e6b6a2d7a96e588cb3de852d0b289
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5b2d7ed670e6b6a2d7a96e588cb3de852d0b289
Author: Dave Airlie
Date: Tue Feb 20 10:15:18 2018 +1000
ac/nir: to integer the args to bcsel.
dEQP-VK.tessellation.invariance.outer_edge_symmetry.triangles_equal_spacing_ccw
was hitting an llvm assert due to one value being an int and the
other a float.
This just casts both values to integer and fixes the test.
Fixes:
dEQP-VK.tessellation.invariance.outer_edge_symmetry.triangles_equal_spacing_ccw
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Bas Nieuwenhuizen
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 12f097e2b2..2185c53834 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1314,7 +1314,8 @@ static LLVMValueRef emit_bcsel(struct ac_llvm_context
*ctx,
{
LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
ctx->i32_0, "");
- return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
+ return LLVMBuildSelect(ctx->builder, v, ac_to_integer(ctx, src1),
+ ac_to_integer(ctx, src2), "");
}
static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
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Mesa (master): anv/cmd_buffer: Use layout_to_* helpers in compute_aux_usage
Module: Mesa
Branch: master
Commit: e10a62662bc5ea5e8bf17ab8c4944a3a131453f2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e10a62662bc5ea5e8bf17ab8c4944a3a131453f2
Author: Jason Ekstrand
Date: Thu Feb 1 19:36:22 2018 -0800
anv/cmd_buffer: Use layout_to_* helpers in compute_aux_usage
Reviewed-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/genX_cmd_buffer.c | 53 +-
1 file changed, 35 insertions(+), 18 deletions(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 5c36fc740d..8bd824b2a7 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -223,16 +223,27 @@ color_attachment_compute_aux_usage(struct anv_device *
device,
att_state->input_aux_usage = ISL_AUX_USAGE_NONE;
att_state->fast_clear = false;
return;
- } else if (iview->image->planes[0].aux_usage == ISL_AUX_USAGE_MCS) {
- att_state->aux_usage = ISL_AUX_USAGE_MCS;
+ }
+
+ att_state->aux_usage =
+ anv_layout_to_aux_usage(&device->info, iview->image,
+ VK_IMAGE_ASPECT_COLOR_BIT,
+ VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL);
+
+ /* If we don't have aux, then we should have returned early in the layer
+* check above. If we got here, we must have something.
+*/
+ assert(att_state->aux_usage != ISL_AUX_USAGE_NONE);
+
+ if (att_state->aux_usage == ISL_AUX_USAGE_MCS) {
att_state->input_aux_usage = ISL_AUX_USAGE_MCS;
att_state->fast_clear = false;
return;
- } else if (iview->image->planes[0].aux_usage == ISL_AUX_USAGE_CCS_E) {
- att_state->aux_usage = ISL_AUX_USAGE_CCS_E;
+ }
+
+ if (att_state->aux_usage == ISL_AUX_USAGE_CCS_E) {
att_state->input_aux_usage = ISL_AUX_USAGE_CCS_E;
} else {
- att_state->aux_usage = ISL_AUX_USAGE_CCS_D;
/* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
*
*"If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
@@ -286,8 +297,25 @@ color_attachment_compute_aux_usage(struct anv_device *
device,
isl_color_value_is_zero(clear_color, iview->planes[0].isl.format);
if (att_state->pending_clear_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
- /* Start off assuming fast clears are possible */
- att_state->fast_clear = true;
+ /* Start by getting the fast clear type. We use the first subpass
+ * layout here because we don't want to fast-clear if the first subpass
+ * to use the attachment can't handle fast-clears.
+ */
+ enum anv_fast_clear_type fast_clear_type =
+ anv_layout_to_fast_clear_type(&device->info, iview->image,
+ VK_IMAGE_ASPECT_COLOR_BIT,
+
cmd_state->pass->attachments[att].first_subpass_layout);
+ switch (fast_clear_type) {
+ case ANV_FAST_CLEAR_NONE:
+ att_state->fast_clear = false;
+ break;
+ case ANV_FAST_CLEAR_DEFAULT_VALUE:
+ att_state->fast_clear = att_state->clear_color_is_zero;
+ break;
+ case ANV_FAST_CLEAR_ANY:
+ att_state->fast_clear = true;
+ break;
+ }
/* Potentially, we could do partial fast-clears but doing so has crazy
* alignment restrictions. It's easier to just restrict to full size
@@ -303,17 +331,6 @@ color_attachment_compute_aux_usage(struct anv_device *
device,
if (GEN_GEN <= 8 && !att_state->clear_color_is_zero_one)
att_state->fast_clear = false;
- /* We only allow fast clears in the GENERAL layout if the auxiliary
- * buffer is always enabled and the fast-clear value is all 0's. See
- * add_aux_state_tracking_buffer() for more information.
- */
- if (cmd_state->pass->attachments[att].first_subpass_layout ==
- VK_IMAGE_LAYOUT_GENERAL &&
- (!att_state->clear_color_is_zero ||
- iview->image->planes[0].aux_usage == ISL_AUX_USAGE_NONE)) {
- att_state->fast_clear = false;
- }
-
/* We only allow fast clears to the first slice of an image (level 0,
* layer 0) and only for the entire slice. This guarantees us that, at
* any given time, there is only one clear color on any given image at
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Mesa (master): anv/cmd_buffer: Delete some assert-only variables
Module: Mesa
Branch: master
Commit: 0fa040e6f52080ee7446ed5509c1c70085ea285b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0fa040e6f52080ee7446ed5509c1c70085ea285b
Author: Jason Ekstrand
Date: Thu Feb 1 20:02:48 2018 -0800
anv/cmd_buffer: Delete some assert-only variables
Checking the sample count is almost as good as aux usage in this case.
Reviewed-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/genX_cmd_buffer.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 8bd824b2a7..939a795c2b 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -740,9 +740,6 @@ init_fast_clear_color(struct anv_cmd_buffer *cmd_buffer,
set_image_fast_clear_state(cmd_buffer, image, aspect,
ANV_FAST_CLEAR_NONE);
- uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
- enum isl_aux_usage aux_usage = image->planes[plane].aux_usage;
-
/* The fast clear value dword(s) will be copied into a surface state object.
* Ensure that the restrictions of the fields in the dword(s) are followed.
*
@@ -763,7 +760,7 @@ init_fast_clear_color(struct anv_cmd_buffer *cmd_buffer,
if (GEN_GEN >= 9) {
/* MCS buffers on SKL+ can only have 1/0 clear colors. */
-assert(aux_usage == ISL_AUX_USAGE_MCS);
+assert(image->samples > 1);
sdi.ImmediateData = 0;
} else if (GEN_VERSIONx10 >= 75) {
/* Pre-SKL, the dword containing the clear values also contains
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Mesa (master): anv/cmd_buffer: Simplify transition_depth_buffer
Module: Mesa
Branch: master
Commit: 7ea8131aa0830b2a834864edcd06354334ea2fd9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ea8131aa0830b2a834864edcd06354334ea2fd9
Author: Jason Ekstrand
Date: Thu Feb 1 19:13:12 2018 -0800
anv/cmd_buffer: Simplify transition_depth_buffer
If we don't have HiZ, then anv_layout_to_aux_usage will return NONE for
both layouts. If the two layouts are the same, they will get the aux
usage. In either case, the code below will give us ISL_AUX_OP_NONE and
we'll return without doing anything.
Reviewed-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/genX_cmd_buffer.c | 12
1 file changed, 12 deletions(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index d90dcb0e1d..5c36fc740d 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -432,18 +432,6 @@ transition_depth_buffer(struct anv_cmd_buffer *cmd_buffer,
VkImageLayout initial_layout,
VkImageLayout final_layout)
{
- assert(image);
-
- /* A transition is a no-op if HiZ is not enabled, or if the initial and
-* final layouts are equal.
-*
-* The undefined layout indicates that the user doesn't care about the data
-* that's currently in the buffer. Therefore, a data-preserving resolve
-* operation is not needed.
-*/
- if (image->planes[0].aux_usage != ISL_AUX_USAGE_HIZ || initial_layout ==
final_layout)
- return;
-
const bool hiz_enabled = ISL_AUX_USAGE_HIZ ==
anv_layout_to_aux_usage(&cmd_buffer->device->info, image,
VK_IMAGE_ASPECT_DEPTH_BIT, initial_layout);
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Mesa (master): anv/blorp: Use layout_to_aux_usage when a layout is provided
Module: Mesa
Branch: master
Commit: c66fb1211734fdee55062ccbeb5c546fce131dbc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c66fb1211734fdee55062ccbeb5c546fce131dbc
Author: Jason Ekstrand
Date: Fri Feb 2 14:51:56 2018 -0800
anv/blorp: Use layout_to_aux_usage when a layout is provided
Instead of having aux usage and ANV_AUX_USAGE_DEFAULT to mean "give me
something reasonable" we now use anv_layout_to_aux_usage whenever a
layout is available. If a layout is available, we ignore the aux_usage
parameter. For the cases where we have an explicit aux usage such as
clears and aux ops, we have a new ANV_IMAGE_LAYOUT_EXPLICIT_AUX layout.
Reviewed-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_blorp.c | 71
1 file changed, 46 insertions(+), 25 deletions(-)
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index a3551fee94..bee51e0cdf 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -176,7 +176,10 @@ get_blorp_surf_for_anv_buffer(struct anv_device *device,
assert(ok);
}
-#define ANV_AUX_USAGE_DEFAULT ((enum isl_aux_usage)0xff)
+/* Pick something high enough that it won't be used in core and low enough it
+ * will never map to an extension.
+ */
+#define ANV_IMAGE_LAYOUT_EXPLICIT_AUX (VkImageLayout)1000
static struct blorp_address
anv_to_blorp_address(struct anv_address addr)
@@ -191,18 +194,14 @@ static void
get_blorp_surf_for_anv_image(const struct anv_device *device,
const struct anv_image *image,
VkImageAspectFlags aspect,
+ VkImageLayout layout,
enum isl_aux_usage aux_usage,
struct blorp_surf *blorp_surf)
{
uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
- if (aux_usage == ANV_AUX_USAGE_DEFAULT) {
- aux_usage = image->planes[plane].aux_usage;
-
- /* Blorp copies and blits can't handle HiZ so disable it by default */
- if (aux_usage == ISL_AUX_USAGE_HIZ)
- aux_usage = ISL_AUX_USAGE_NONE;
- }
+ if (layout != ANV_IMAGE_LAYOUT_EXPLICIT_AUX)
+ aux_usage = anv_layout_to_aux_usage(&device->info, image, aspect,
layout);
const struct anv_surface *surface = &image->planes[plane].surface;
*blorp_surf = (struct blorp_surf) {
@@ -282,10 +281,12 @@ void anv_CmdCopyImage(
struct blorp_surf src_surf, dst_surf;
get_blorp_surf_for_anv_image(cmd_buffer->device,
src_image, 1UL << aspect_bit,
- ANV_AUX_USAGE_DEFAULT, &src_surf);
+ srcImageLayout, ISL_AUX_USAGE_NONE,
+ &src_surf);
get_blorp_surf_for_anv_image(cmd_buffer->device,
dst_image, 1UL << aspect_bit,
- ANV_AUX_USAGE_DEFAULT, &dst_surf);
+ dstImageLayout, ISL_AUX_USAGE_NONE,
+ &dst_surf);
anv_cmd_buffer_mark_image_written(cmd_buffer, dst_image,
1UL << aspect_bit,
dst_surf.aux_usage, dst_level,
@@ -302,9 +303,11 @@ void anv_CmdCopyImage(
} else {
struct blorp_surf src_surf, dst_surf;
get_blorp_surf_for_anv_image(cmd_buffer->device, src_image, src_mask,
- ANV_AUX_USAGE_DEFAULT, &src_surf);
+ srcImageLayout, ISL_AUX_USAGE_NONE,
+ &src_surf);
get_blorp_surf_for_anv_image(cmd_buffer->device, dst_image, dst_mask,
- ANV_AUX_USAGE_DEFAULT, &dst_surf);
+ dstImageLayout, ISL_AUX_USAGE_NONE,
+ &dst_surf);
anv_cmd_buffer_mark_image_written(cmd_buffer, dst_image, dst_mask,
dst_surf.aux_usage, dst_level,
dst_base_layer, layer_count);
@@ -326,6 +329,7 @@ static void
copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
struct anv_buffer *anv_buffer,
struct anv_image *anv_image,
+ VkImageLayout image_layout,
uint32_t regionCount,
const VkBufferImageCopy* pRegions,
bool buffer_to_image)
@@ -354,7 +358,8 @@ copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
const VkImageAspectFlags aspect =
pRegions[r].imageSubresource.aspectMask;
get_blorp_surf_for_anv_image(cmd_buffer->device, anv_image, aspect,
- ANV_AUX_USAGE_DEFAULT, &image.surf);
+
Mesa (master): anv/cmd_buffer: Apply subpass flushes before set_subpass
Module: Mesa Branch: master Commit: b5bd3fb4e43ce0e6edd453a3c502e9c8c5bdf4f1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5bd3fb4e43ce0e6edd453a3c502e9c8c5bdf4f1 Author: Jason Ekstrand Date: Tue Nov 21 12:27:43 2017 -0800 anv/cmd_buffer: Apply subpass flushes before set_subpass This seems slightly more correct because it means that the flushes happen before any clears or resolves implied by the subpass transition. Reviewed-by: Nanley Chery --- src/intel/vulkan/genX_cmd_buffer.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 9c50f91b44..ada05ccee6 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -3520,10 +3520,10 @@ void genX(CmdBeginRenderPass)( genX(flush_pipeline_select_3d)(cmd_buffer); - genX(cmd_buffer_set_subpass)(cmd_buffer, pass->subpasses); - cmd_buffer->state.pending_pipe_bits |= cmd_buffer->state.pass->subpass_flushes[0]; + + genX(cmd_buffer_set_subpass)(cmd_buffer, pass->subpasses); } void genX(CmdNextSubpass)( @@ -3543,11 +3543,11 @@ void genX(CmdNextSubpass)( */ cmd_buffer_subpass_transition_layouts(cmd_buffer, true); - genX(cmd_buffer_set_subpass)(cmd_buffer, cmd_buffer->state.subpass + 1); - uint32_t subpass_id = anv_get_subpass_id(&cmd_buffer->state); cmd_buffer->state.pending_pipe_bits |= cmd_buffer->state.pass->subpass_flushes[subpass_id]; + + genX(cmd_buffer_set_subpass)(cmd_buffer, cmd_buffer->state.subpass + 1); } void genX(CmdEndRenderPass)( ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv/cmd_buffer: Pass a subpass id into begin_subpass
Module: Mesa
Branch: master
Commit: 6fb9d6c6f5510a9fb594892228fabb831be1d34c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6fb9d6c6f5510a9fb594892228fabb831be1d34c
Author: Jason Ekstrand
Date: Tue Nov 21 12:42:45 2017 -0800
anv/cmd_buffer: Pass a subpass id into begin_subpass
This is a bit less awkward than passing in the subpass because it means
we don't have to extract the subpass id from the subpass.
Reviewed-by: Nanley Chery
---
src/intel/vulkan/genX_cmd_buffer.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 59945695fd..743662dff7 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -3448,13 +3448,11 @@ cmd_buffer_subpass_sync_fast_clear_values(struct
anv_cmd_buffer *cmd_buffer)
}
}
-
static void
cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
- struct anv_subpass *subpass)
+ uint32_t subpass_id)
{
- cmd_buffer->state.subpass = subpass;
- uint32_t subpass_id = anv_get_subpass_id(&cmd_buffer->state);
+ cmd_buffer->state.subpass = &cmd_buffer->state.pass->subpasses[subpass_id];
cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
@@ -3545,7 +3543,7 @@ void genX(CmdBeginRenderPass)(
genX(flush_pipeline_select_3d)(cmd_buffer);
- cmd_buffer_begin_subpass(cmd_buffer, pass->subpasses);
+ cmd_buffer_begin_subpass(cmd_buffer, 0);
}
void genX(CmdNextSubpass)(
@@ -3559,9 +3557,9 @@ void genX(CmdNextSubpass)(
assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
+ uint32_t prev_subpass = anv_get_subpass_id(&cmd_buffer->state);
cmd_buffer_end_subpass(cmd_buffer);
-
- cmd_buffer_begin_subpass(cmd_buffer, cmd_buffer->state.subpass + 1);
+ cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
}
void genX(CmdEndRenderPass)(
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Mesa (master): anv/cmd_buffer: Add a concept of pending load aspects
Module: Mesa
Branch: master
Commit: bd356e1bcf5f481775ef26b0f8ad29a48cf6f685
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd356e1bcf5f481775ef26b0f8ad29a48cf6f685
Author: Jason Ekstrand
Date: Tue Nov 21 20:29:36 2017 -0800
anv/cmd_buffer: Add a concept of pending load aspects
These are the same as pending clear aspects only for the "load"
operation.
Reviewed-by: Nanley Chery
---
src/intel/vulkan/anv_private.h | 1 +
src/intel/vulkan/genX_cmd_buffer.c | 22 --
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index d9c855b969..020f293f0f 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1689,6 +1689,7 @@ struct anv_attachment_state {
VkImageLayoutcurrent_layout;
VkImageAspectFlags pending_clear_aspects;
+ VkImageAspectFlags pending_load_aspects;
bool fast_clear;
VkClearValue clear_value;
bool clear_color_is_zero_one;
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index f21eaa4b3c..db93210d2a 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1132,26 +1132,36 @@ genX(cmd_buffer_setup_attachments)(struct
anv_cmd_buffer *cmd_buffer,
struct anv_render_pass_attachment *att = &pass->attachments[i];
VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
VkImageAspectFlags clear_aspects = 0;
+ VkImageAspectFlags load_aspects = 0;
if (att_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
/* color attachment */
if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
+} else if (att->load_op == VK_ATTACHMENT_LOAD_OP_LOAD) {
+ load_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
}
} else {
/* depthstencil attachment */
-if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
-att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
- clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
+if (att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
+ if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
+ clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
+ } else if (att->load_op == VK_ATTACHMENT_LOAD_OP_LOAD) {
+ load_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
+ }
}
-if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
-att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
- clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
+if (att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
+ if (att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
+ clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
+ } else if (att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_LOAD) {
+ load_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
+ }
}
}
state->attachments[i].current_layout = att->initial_layout;
state->attachments[i].pending_clear_aspects = clear_aspects;
+ state->attachments[i].pending_load_aspects = load_aspects;
if (clear_aspects)
state->attachments[i].clear_value = begin->pClearValues[i];
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Mesa (master): anv/cmd_buffer: Add begin/end_subpass helpers
Module: Mesa
Branch: master
Commit: 01223b8199127c265c6a75b70f75d042decc1169
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=01223b8199127c265c6a75b70f75d042decc1169
Author: Jason Ekstrand
Date: Tue Nov 21 12:41:01 2017 -0800
anv/cmd_buffer: Add begin/end_subpass helpers
Having begin/end_subpass is a bit nicer than the begin/next/end hooks
that Vulkan gives us.
Reviewed-by: Nanley Chery
---
src/intel/vulkan/genX_cmd_buffer.c | 55 +-
1 file changed, 31 insertions(+), 24 deletions(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index ada05ccee6..59945695fd 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -3450,10 +3450,11 @@ cmd_buffer_subpass_sync_fast_clear_values(struct
anv_cmd_buffer *cmd_buffer)
static void
-genX(cmd_buffer_set_subpass)(struct anv_cmd_buffer *cmd_buffer,
- struct anv_subpass *subpass)
+cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
+ struct anv_subpass *subpass)
{
cmd_buffer->state.subpass = subpass;
+ uint32_t subpass_id = anv_get_subpass_id(&cmd_buffer->state);
cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
@@ -3478,6 +3479,10 @@ genX(cmd_buffer_set_subpass)(struct anv_cmd_buffer
*cmd_buffer,
*/
cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;
+ /* Accumulate any subpass flushes that need to happen before the subpass */
+ cmd_buffer->state.pending_pipe_bits |=
+ cmd_buffer->state.pass->subpass_flushes[subpass_id];
+
/* Perform transitions to the subpass layout before any writes have
* occurred.
*/
@@ -3497,6 +3502,26 @@ genX(cmd_buffer_set_subpass)(struct anv_cmd_buffer
*cmd_buffer,
anv_cmd_buffer_clear_subpass(cmd_buffer);
}
+static void
+cmd_buffer_end_subpass(struct anv_cmd_buffer *cmd_buffer)
+{
+ uint32_t subpass_id = anv_get_subpass_id(&cmd_buffer->state);
+
+ anv_cmd_buffer_resolve_subpass(cmd_buffer);
+
+ /* Perform transitions to the final layout after all writes have occurred.
+*/
+ cmd_buffer_subpass_transition_layouts(cmd_buffer, true);
+
+ /* Accumulate any subpass flushes that need to happen after the subpass.
+* Yes, they do get accumulated twice in the NextSubpass case but since
+* genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
+* ORing the bits in twice so it's harmless.
+*/
+ cmd_buffer->state.pending_pipe_bits |=
+ cmd_buffer->state.pass->subpass_flushes[subpass_id + 1];
+}
+
void genX(CmdBeginRenderPass)(
VkCommandBuffer commandBuffer,
const VkRenderPassBeginInfo*pRenderPassBegin,
@@ -3520,10 +3545,7 @@ void genX(CmdBeginRenderPass)(
genX(flush_pipeline_select_3d)(cmd_buffer);
- cmd_buffer->state.pending_pipe_bits |=
- cmd_buffer->state.pass->subpass_flushes[0];
-
- genX(cmd_buffer_set_subpass)(cmd_buffer, pass->subpasses);
+ cmd_buffer_begin_subpass(cmd_buffer, pass->subpasses);
}
void genX(CmdNextSubpass)(
@@ -3537,17 +3559,9 @@ void genX(CmdNextSubpass)(
assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
- anv_cmd_buffer_resolve_subpass(cmd_buffer);
-
- /* Perform transitions to the final layout after all writes have occurred.
-*/
- cmd_buffer_subpass_transition_layouts(cmd_buffer, true);
-
- uint32_t subpass_id = anv_get_subpass_id(&cmd_buffer->state);
- cmd_buffer->state.pending_pipe_bits |=
- cmd_buffer->state.pass->subpass_flushes[subpass_id];
+ cmd_buffer_end_subpass(cmd_buffer);
- genX(cmd_buffer_set_subpass)(cmd_buffer, cmd_buffer->state.subpass + 1);
+ cmd_buffer_begin_subpass(cmd_buffer, cmd_buffer->state.subpass + 1);
}
void genX(CmdEndRenderPass)(
@@ -3558,14 +3572,7 @@ void genX(CmdEndRenderPass)(
if (anv_batch_has_error(&cmd_buffer->batch))
return;
- anv_cmd_buffer_resolve_subpass(cmd_buffer);
-
- /* Perform transitions to the final layout after all writes have occurred.
-*/
- cmd_buffer_subpass_transition_layouts(cmd_buffer, true);
-
- cmd_buffer->state.pending_pipe_bits |=
-
cmd_buffer->state.pass->subpass_flushes[cmd_buffer->state.pass->subpass_count];
+ cmd_buffer_end_subpass(cmd_buffer);
cmd_buffer->state.hiz_enabled = false;
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Mesa (master): anv/cmd_buffer: Iterate all subpass attachments when clearing
Module: Mesa
Branch: master
Commit: e526d49edd9fe7ccf37ae22fd698a6c24de66ac4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e526d49edd9fe7ccf37ae22fd698a6c24de66ac4
Author: Jason Ekstrand
Date: Mon Nov 27 10:43:03 2017 -0800
anv/cmd_buffer: Iterate all subpass attachments when clearing
This unifies things a bit because we now handle depth and stencil at the
same time.
Reviewed-by: Nanley Chery
---
src/intel/vulkan/genX_cmd_buffer.c | 78 --
1 file changed, 33 insertions(+), 45 deletions(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 5b41284258..f21eaa4b3c 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -3563,66 +3563,52 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer,
VkRect2D render_area = cmd_buffer->state.render_area;
struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
- for (uint32_t i = 0; i < subpass->color_count; ++i) {
- const uint32_t a = subpass->color_attachments[i].attachment;
+
+ for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
+ const uint32_t a = subpass->attachments[i].attachment;
if (a == VK_ATTACHMENT_UNUSED)
continue;
assert(a < cmd_state->pass->attachment_count);
struct anv_attachment_state *att_state = &cmd_state->attachments[a];
- if (!att_state->pending_clear_aspects)
- continue;
-
- assert(att_state->pending_clear_aspects == VK_IMAGE_ASPECT_COLOR_BIT);
-
struct anv_image_view *iview = fb->attachments[a];
const struct anv_image *image = iview->image;
- /* Multi-planar images are not supported as attachments */
- assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
- assert(image->n_planes == 1);
-
- uint32_t base_clear_layer = iview->planes[0].isl.base_array_layer;
- uint32_t clear_layer_count = fb->layers;
+ if (att_state->pending_clear_aspects & VK_IMAGE_ASPECT_COLOR_BIT) {
+ assert(att_state->pending_clear_aspects == VK_IMAGE_ASPECT_COLOR_BIT);
- if (att_state->fast_clear) {
- /* We only support fast-clears on the first layer */
- assert(iview->planes[0].isl.base_level == 0);
- assert(iview->planes[0].isl.base_array_layer == 0);
-
- anv_image_ccs_op(cmd_buffer, image, VK_IMAGE_ASPECT_COLOR_BIT,
- 0, 0, 1, ISL_AUX_OP_FAST_CLEAR, false);
- base_clear_layer++;
- clear_layer_count--;
- }
-
- if (clear_layer_count > 0) {
+ /* Multi-planar images are not supported as attachments */
+ assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
assert(image->n_planes == 1);
- anv_image_clear_color(cmd_buffer, image, VK_IMAGE_ASPECT_COLOR_BIT,
- att_state->aux_usage,
- iview->planes[0].isl.format,
- iview->planes[0].isl.swizzle,
- iview->planes[0].isl.base_level,
- base_clear_layer, clear_layer_count,
render_area,
- vk_to_isl_color(att_state->clear_value.color));
- }
-
- att_state->pending_clear_aspects = 0;
- }
- if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
- const uint32_t a = subpass->depth_stencil_attachment.attachment;
+ uint32_t base_clear_layer = iview->planes[0].isl.base_array_layer;
+ uint32_t clear_layer_count = fb->layers;
- assert(a < cmd_state->pass->attachment_count);
- struct anv_attachment_state *att_state = &cmd_state->attachments[a];
- struct anv_image_view *iview = fb->attachments[a];
- const struct anv_image *image = iview->image;
+ if (att_state->fast_clear) {
+/* We only support fast-clears on the first layer */
+assert(iview->planes[0].isl.base_level == 0);
+assert(iview->planes[0].isl.base_array_layer == 0);
- assert(image->aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
- VK_IMAGE_ASPECT_STENCIL_BIT));
+anv_image_ccs_op(cmd_buffer, image, VK_IMAGE_ASPECT_COLOR_BIT,
+ 0, 0, 1, ISL_AUX_OP_FAST_CLEAR, false);
+base_clear_layer++;
+clear_layer_count--;
+ }
- if (att_state->pending_clear_aspects) {
+ if (clear_layer_count > 0) {
+assert(image->n_planes == 1);
+anv_image_clear_color(cmd_buffer, image, VK_IMAGE_ASPECT_COLOR_BIT,
+ att_state->aux_usage,
+ iview->planes[0].isl.format,
+ iview->planes[0].isl.swizzle,
+ iview->planes[0].isl.base_level,
+ base_clear_layer, clear_layer_count,
+ render_area,
+
Mesa (master): anv: Be more careful about fast-clear colors
Module: Mesa
Branch: master
Commit: 85d0bec9616bc1ffa8e4ab5e7c5d12ff4e414872
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=85d0bec9616bc1ffa8e4ab5e7c5d12ff4e414872
Author: Jason Ekstrand
Date: Mon Feb 12 16:03:28 2018 -0800
anv: Be more careful about fast-clear colors
Previously, we just used all the channels regardless of the format.
This is less than ideal because some channels may have undefined values
and this should be ok from the client's perspective. Even though the
driver should do the correct thing regardless of what is in the
undefined value, it makes things less deterministic. In particular, the
driver may choose to fast-clear or not based on undefined values. This
level of nondeterminism is bad.
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Nanley Chery
---
src/intel/vulkan/genX_cmd_buffer.c | 46 --
1 file changed, 19 insertions(+), 27 deletions(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index fd1119c2e4..7aab116217 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -202,24 +202,6 @@ add_image_view_relocs(struct anv_cmd_buffer *cmd_buffer,
}
}
-static bool
-color_is_zero_one(VkClearColorValue value, enum isl_format format)
-{
- if (isl_format_has_int_channel(format)) {
- for (unsigned i = 0; i < 4; i++) {
- if (value.int32[i] != 0 && value.int32[i] != 1)
-return false;
- }
- } else {
- for (unsigned i = 0; i < 4; i++) {
- if (value.float32[i] != 0.0f && value.float32[i] != 1.0f)
-return false;
- }
- }
-
- return true;
-}
-
static void
color_attachment_compute_aux_usage(struct anv_device * device,
struct anv_cmd_state * cmd_state,
@@ -283,13 +265,25 @@ color_attachment_compute_aux_usage(struct anv_device *
device,
assert(iview->image->planes[0].aux_surface.isl.usage &
ISL_SURF_USAGE_CCS_BIT);
+ const struct isl_format_layout *view_fmtl =
+ isl_format_get_layout(iview->planes[0].isl.format);
+ union isl_color_value clear_color = {};
+
+#define COPY_CLEAR_COLOR_CHANNEL(c, i) \
+ if (view_fmtl->channels.c.bits) \
+ clear_color.u32[i] = att_state->clear_value.color.uint32[i]
+
+ COPY_CLEAR_COLOR_CHANNEL(r, 0);
+ COPY_CLEAR_COLOR_CHANNEL(g, 1);
+ COPY_CLEAR_COLOR_CHANNEL(b, 2);
+ COPY_CLEAR_COLOR_CHANNEL(a, 3);
+
+#undef COPY_CLEAR_COLOR_CHANNEL
+
att_state->clear_color_is_zero_one =
- color_is_zero_one(att_state->clear_value.color,
iview->planes[0].isl.format);
+ isl_color_value_is_zero_one(clear_color, iview->planes[0].isl.format);
att_state->clear_color_is_zero =
- att_state->clear_value.color.uint32[0] == 0 &&
- att_state->clear_value.color.uint32[1] == 0 &&
- att_state->clear_value.color.uint32[2] == 0 &&
- att_state->clear_value.color.uint32[3] == 0;
+ isl_color_value_is_zero(clear_color, iview->planes[0].isl.format);
if (att_state->pending_clear_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
/* Start off assuming fast clears are possible */
@@ -341,10 +335,8 @@ color_attachment_compute_aux_usage(struct anv_device *
device,
"LOAD_OP_CLEAR. Only fast-clearing the first slice");
}
- if (att_state->fast_clear) {
- memcpy(fast_clear_color->u32, att_state->clear_value.color.uint32,
-sizeof(fast_clear_color->u32));
- }
+ if (att_state->fast_clear)
+ *fast_clear_color = clear_color;
} else {
att_state->fast_clear = false;
}
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Mesa (master): intel/isl: Add an isl_color_value_is_zero helper
Module: Mesa
Branch: master
Commit: 4796025ba518baa0e8893337591a3f452a375d94
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4796025ba518baa0e8893337591a3f452a375d94
Author: Jason Ekstrand
Date: Mon Feb 12 15:50:12 2018 -0800
intel/isl: Add an isl_color_value_is_zero helper
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Nanley Chery
---
src/intel/isl/isl.c | 20
src/intel/isl/isl.h | 3 +++
2 files changed, 23 insertions(+)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 4dce0596d2..1a32c02818 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -269,6 +269,26 @@ isl_tiling_get_info(enum isl_tiling tiling,
}
bool
+isl_color_value_is_zero(union isl_color_value value,
+enum isl_format format)
+{
+ const struct isl_format_layout *fmtl = isl_format_get_layout(format);
+
+#define RETURN_FALSE_IF_NOT_0(c, i) \
+ if (fmtl->channels.c.bits && value.u32[i] != 0) \
+ return false
+
+ RETURN_FALSE_IF_NOT_0(r, 0);
+ RETURN_FALSE_IF_NOT_0(g, 1);
+ RETURN_FALSE_IF_NOT_0(b, 2);
+ RETURN_FALSE_IF_NOT_0(a, 3);
+
+#undef RETURN_FALSE_IF_NOT_0
+
+ return true;
+}
+
+bool
isl_color_value_is_zero_one(union isl_color_value value,
enum isl_format format)
{
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index fda2411510..209769a9a9 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1692,6 +1692,9 @@ isl_extent4d(uint32_t width, uint32_t height, uint32_t
depth,
return e;
}
+bool isl_color_value_is_zero(union isl_color_value value,
+ enum isl_format format);
+
bool isl_color_value_is_zero_one(union isl_color_value value,
enum isl_format format);
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Mesa (master): anv: Use framebuffer layers for implicit subpass transitions
Module: Mesa
Branch: master
Commit: 869448a8aba25bddcc1ae5e70a95cea9882c8882
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=869448a8aba25bddcc1ae5e70a95cea9882c8882
Author: Jason Ekstrand
Date: Thu Feb 8 16:44:56 2018 -0800
anv: Use framebuffer layers for implicit subpass transitions
Fixes: de3be618016 "anv/cmd_buffer: Rework aux tracking"
Reviewed-by: Nanley Chery
---
src/intel/vulkan/genX_cmd_buffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 7aab116217..9c50f91b44 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -3344,7 +3344,7 @@ cmd_buffer_subpass_transition_layouts(struct
anv_cmd_buffer * const cmd_buffer,
iview->planes[0].isl.base_level);
} else {
base_layer = iview->planes[0].isl.base_array_layer;
-layer_count = iview->planes[0].isl.array_len;
+layer_count = cmd_state->framebuffer->layers;
}
transition_color_buffer(cmd_buffer, image, VK_IMAGE_ASPECT_COLOR_BIT,
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Mesa (master): anv/cmd_buffer: Decide whether or not to HiZ clear up-front
Module: Mesa
Branch: master
Commit: 2cc3445eb24af469537911277f7bc4e73a6c5670
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2cc3445eb24af469537911277f7bc4e73a6c5670
Author: Jason Ekstrand
Date: Mon Nov 27 10:20:00 2017 -0800
anv/cmd_buffer: Decide whether or not to HiZ clear up-front
This moves the decision out of begin_subpass and into BeginRenderPass
like the decision for color clears. We use a similar name for the
function for depth/stencil as for color even though no aux usage is
really getting computed.
v2 (Jason Ekstrand):
- Don't always disable HiZ clears by accident
- Use the initial layout to decide whether to do fast clears
Reviewed-by: Nanley Chery
---
src/intel/vulkan/genX_cmd_buffer.c | 107 +
1 file changed, 72 insertions(+), 35 deletions(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index a1cbe2692b..5b41284258 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -342,6 +342,73 @@ color_attachment_compute_aux_usage(struct anv_device *
device,
}
}
+static void
+depth_stencil_attachment_compute_aux_usage(struct anv_device *device,
+ struct anv_cmd_state *cmd_state,
+ uint32_t att, VkRect2D render_area)
+{
+ struct anv_render_pass_attachment *pass_att =
+ &cmd_state->pass->attachments[att];
+ struct anv_attachment_state *att_state = &cmd_state->attachments[att];
+ struct anv_image_view *iview = cmd_state->framebuffer->attachments[att];
+
+ /* These will be initialized after the first subpass transition. */
+ att_state->aux_usage = ISL_AUX_USAGE_NONE;
+ att_state->input_aux_usage = ISL_AUX_USAGE_NONE;
+
+ if (GEN_GEN == 7) {
+ /* We don't do any HiZ or depth fast-clears on gen7 yet */
+ att_state->fast_clear = false;
+ return;
+ }
+
+ if (!(att_state->pending_clear_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
+ /* If we're just clearing stencil, we can always HiZ clear */
+ att_state->fast_clear = true;
+ return;
+ }
+
+ /* Default to false for now */
+ att_state->fast_clear = false;
+
+ /* We must have depth in order to have HiZ */
+ if (!(iview->image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
+ return;
+
+ const enum isl_aux_usage first_subpass_aux_usage =
+ anv_layout_to_aux_usage(&device->info, iview->image,
+ VK_IMAGE_ASPECT_DEPTH_BIT,
+ pass_att->first_subpass_layout);
+ if (first_subpass_aux_usage != ISL_AUX_USAGE_HIZ)
+ return;
+
+ if (!blorp_can_hiz_clear_depth(GEN_GEN,
+ iview->planes[0].isl.format,
+ iview->image->samples,
+ render_area.offset.x,
+ render_area.offset.y,
+ render_area.offset.x +
+ render_area.extent.width,
+ render_area.offset.y +
+ render_area.extent.height))
+ return;
+
+ if (att_state->clear_value.depthStencil.depth != ANV_HZ_FC_VAL)
+ return;
+
+ if (GEN_GEN == 8 && anv_can_sample_with_hiz(&device->info, iview->image)) {
+ /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
+ * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
+ * only supports returning 0.0f. Gens prior to gen8 do not support this
+ * feature at all.
+ */
+ return;
+ }
+
+ /* If we got here, then we can fast clear */
+ att_state->fast_clear = true;
+}
+
static bool
need_input_attachment_state(const struct anv_render_pass_attachment *att)
{
@@ -1113,12 +1180,9 @@ genX(cmd_buffer_setup_attachments)(struct anv_cmd_buffer
*cmd_buffer,
add_image_view_relocs(cmd_buffer, iview, 0,
state->attachments[i].color);
} else {
-/* This field will be initialized after the first subpass
- * transition.
- */
-state->attachments[i].aux_usage = ISL_AUX_USAGE_NONE;
-
-state->attachments[i].input_aux_usage = ISL_AUX_USAGE_NONE;
+depth_stencil_attachment_compute_aux_usage(cmd_buffer->device,
+ state, i,
+ begin->renderArea);
}
if (need_input_attachment_state(&pass->attachments[i])) {
@@ -3559,35 +3623,8 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer,
VK_IMAGE_ASPECT_STENCIL_BIT));
if (att_state->pending_clear_aspects) {
- bool clear_with_hiz = att_state->aux_usage == ISL_AUX_USAGE_HIZ;
- if (clear_with_hiz &&
- (att_state->pending_clear_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
Mesa (master): anv/gpu_memcpy: CS Stall before a MI memcpy on gen7
Module: Mesa
Branch: master
Commit: 116e818ef18f62cf810de98fd3909dcef9fe4e84
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=116e818ef18f62cf810de98fd3909dcef9fe4e84
Author: Jason Ekstrand
Date: Fri Feb 16 17:35:15 2018 -0800
anv/gpu_memcpy: CS Stall before a MI memcpy on gen7
This fixes a pile of hangs caused by the recent shuffling of resolves
and transitions. The particularly problematic case is when you have at
least three attachments with load ops of CLEAR, LOAD, CLEAR. In this
case, we execute the first CLEAR followed by a MI memcpy to copy the
clear values over for the LOAD followed by a second CLEAR. The MI
commands cause the first CLEAR to hang which causes us to get stuck on
the 3DSTATE_MULTISAMPLE in the second CLEAR.
We also add guards for BLORP to fix the same issue. These shouldn't
actually do anything right now because the only use of indirect clears
in BLORP today is for resolves which are already guarded by a render
cache flush and CS stall. However, this will guard us against potential
issues in the future.
Acked-by: Kenneth Graunke
Acked-by: Nanley Chery
---
src/intel/vulkan/genX_blorp_exec.c | 10 ++
src/intel/vulkan/genX_gpu_memcpy.c | 22 ++
2 files changed, 32 insertions(+)
diff --git a/src/intel/vulkan/genX_blorp_exec.c
b/src/intel/vulkan/genX_blorp_exec.c
index 04f76755de..f956715228 100644
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -200,6 +200,16 @@ genX(blorp_exec)(struct blorp_batch *batch,
genX(cmd_buffer_config_l3)(cmd_buffer, cfg);
}
+#if GEN_GEN == 7
+ /* The MI_LOAD/STORE_REGISTER_MEM commands which BLORP uses to implement
+* indirect fast-clear colors can cause GPU hangs if we don't stall first.
+* See genX(cmd_buffer_mi_memcpy) for more details.
+*/
+ assert(params->src.clear_color_addr.buffer == NULL);
+ if (params->dst.clear_color_addr.buffer)
+ cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
+#endif
+
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
genX(flush_pipeline_select_3d)(cmd_buffer);
diff --git a/src/intel/vulkan/genX_gpu_memcpy.c
b/src/intel/vulkan/genX_gpu_memcpy.c
index f3ada9..1d527fb154 100644
--- a/src/intel/vulkan/genX_gpu_memcpy.c
+++ b/src/intel/vulkan/genX_gpu_memcpy.c
@@ -62,6 +62,28 @@ genX(cmd_buffer_mi_memcpy)(struct anv_cmd_buffer *cmd_buffer,
assert(dst_offset % 4 == 0);
assert(src_offset % 4 == 0);
+#if GEN_GEN == 7
+ /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
+* and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
+* in-flight when they are issued even if the memory touched is not
+* currently active for rendering. The weird bit is that it is not the
+* MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
+* rendering hangs such that the next stalling command after the
+* MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
+*
+* It is unclear exactly why this hang occurs. Both MI commands come with
+* warnings about the 3D pipeline but that doesn't seem to fully explain
+* it. My (Jason's) best theory is that it has something to do with the
+* fact that we're using a GPU state register as our temporary and that
+* something with reading/writing it is causing problems.
+*
+* In order to work around this issue, we emit a PIPE_CONTROL with the
+* command streamer stall bit set.
+*/
+ cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
+ genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
+#endif
+
for (uint32_t i = 0; i < size; i += 4) {
const struct anv_address src_addr =
(struct anv_address) { src, src_offset + i};
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv/cmd_buffer: Sync clear values in begin_subpass
Module: Mesa
Branch: master
Commit: 8a3f086a42b643e33310ad8b9dbe63c57d6620b9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a3f086a42b643e33310ad8b9dbe63c57d6620b9
Author: Jason Ekstrand
Date: Tue Nov 21 15:16:40 2017 -0800
anv/cmd_buffer: Sync clear values in begin_subpass
This is quite a bit cleaner because we now sync the clear values at the
same time as we do the fast clear. For loading the clear values into
the surface state, we now do it once when we handle the LOAD_OP_LOAD
instead of every subpass.
Reviewed-by: Nanley Chery
---
src/intel/vulkan/genX_cmd_buffer.c | 148 -
1 file changed, 48 insertions(+), 100 deletions(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 5f770dd4f3..1b1bf56a6f 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -3431,97 +3431,6 @@ cmd_buffer_subpass_transition_layouts(struct
anv_cmd_buffer * const cmd_buffer,
}
}
-/* Update the clear value dword(s) in surface state objects or the fast clear
- * state buffer entry for the color attachments used in this subpass.
- */
-static void
-cmd_buffer_subpass_sync_fast_clear_values(struct anv_cmd_buffer *cmd_buffer)
-{
- assert(cmd_buffer && cmd_buffer->state.subpass);
-
- const struct anv_cmd_state *state = &cmd_buffer->state;
-
- /* Iterate through every color attachment used in this subpass. */
- for (uint32_t i = 0; i < state->subpass->color_count; ++i) {
-
- /* The attachment should be one of the attachments described in the
- * render pass and used in the subpass.
- */
- const uint32_t a = state->subpass->color_attachments[i].attachment;
- if (a == VK_ATTACHMENT_UNUSED)
- continue;
-
- assert(a < state->pass->attachment_count);
-
- /* Store some information regarding this attachment. */
- const struct anv_attachment_state *att_state = &state->attachments[a];
- const struct anv_image_view *iview = state->framebuffer->attachments[a];
- const struct anv_render_pass_attachment *rp_att =
- &state->pass->attachments[a];
-
- if (att_state->aux_usage == ISL_AUX_USAGE_NONE)
- continue;
-
- /* The fast clear state entry must be updated if a fast clear is going to
- * happen. The surface state must be updated if the clear value from a
- * prior fast clear may be needed.
- */
- if (att_state->pending_clear_aspects && att_state->fast_clear) {
- /* Update the fast clear state entry. */
- genX(copy_fast_clear_dwords)(cmd_buffer, att_state->color.state,
- iview->image,
- VK_IMAGE_ASPECT_COLOR_BIT,
- true /* copy from ss */);
-
- /* Fast-clears impact whether or not a resolve will be necessary. */
- if (att_state->clear_color_is_zero) {
-/* This image has the auxiliary buffer enabled. We can mark the
- * subresource as not needing a resolve because the clear color
- * will match what's in every RENDER_SURFACE_STATE object when
- * it's being used for sampling.
- */
-set_image_fast_clear_state(cmd_buffer, iview->image,
- VK_IMAGE_ASPECT_COLOR_BIT,
- ANV_FAST_CLEAR_DEFAULT_VALUE);
- } else {
-set_image_fast_clear_state(cmd_buffer, iview->image,
- VK_IMAGE_ASPECT_COLOR_BIT,
- ANV_FAST_CLEAR_ANY);
- }
- } else if (rp_att->load_op == VK_ATTACHMENT_LOAD_OP_LOAD &&
- iview->planes[0].isl.base_level == 0 &&
- iview->planes[0].isl.base_array_layer == 0) {
- /* The attachment may have been fast-cleared in a previous render
- * pass and the value is needed now. Update the surface state(s).
- *
- * TODO: Do this only once per render pass instead of every subpass.
- */
- genX(copy_fast_clear_dwords)(cmd_buffer, att_state->color.state,
- iview->image,
- VK_IMAGE_ASPECT_COLOR_BIT,
- false /* copy to ss */);
-
- if (need_input_attachment_state(rp_att) &&
- att_state->input_aux_usage != ISL_AUX_USAGE_NONE) {
-genX(copy_fast_clear_dwords)(cmd_buffer, att_state->input.state,
- iview->image,
- VK_IMAGE_ASPECT_COLOR_BIT,
- false /* copy to ss */);
- }
- }
-
- /* We assume that if we're starting a subpass, we're going to do some
- * rendering so we may end up with compressed data.
- */
- genX(cmd_buffer_mark_image_written)(cmd_buff
Mesa (master): anv/pass: Store usage in each subpass attachment
Module: Mesa
Branch: master
Commit: a4136b8c1a4533925af616d4920054c9734a265b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4136b8c1a4533925af616d4920054c9734a265b
Author: Jason Ekstrand
Date: Sat Jan 13 10:45:55 2018 -0800
anv/pass: Store usage in each subpass attachment
This requires us to ditch the VkAttachmentReference struct in favor of
an anv-specific struct. However, we can now easily identify from just
the subpass attachment what kind of an attachment it is. This will make
iteration over anv_subpass::attachments a little easier in some case.
Reviewed-by: Nanley Chery
---
src/intel/vulkan/anv_pass.c| 35 +++
src/intel/vulkan/anv_private.h | 16 +++-
src/intel/vulkan/genX_cmd_buffer.c | 2 +-
3 files changed, 39 insertions(+), 14 deletions(-)
diff --git a/src/intel/vulkan/anv_pass.c b/src/intel/vulkan/anv_pass.c
index a77e52b0c0..5b8b138ed9 100644
--- a/src/intel/vulkan/anv_pass.c
+++ b/src/intel/vulkan/anv_pass.c
@@ -65,7 +65,7 @@ VkResult anv_CreateRenderPass(
anv_multialloc_add(&ma, &attachments, pCreateInfo->attachmentCount);
anv_multialloc_add(&ma, &subpass_flushes, pCreateInfo->subpassCount + 1);
- VkAttachmentReference *subpass_attachments;
+ struct anv_subpass_attachment *subpass_attachments;
uint32_t subpass_attachment_count = 0;
for (uint32_t i = 0; i < pCreateInfo->subpassCount; i++) {
subpass_attachment_count +=
@@ -117,7 +117,11 @@ VkResult anv_CreateRenderPass(
for (uint32_t j = 0; j < desc->inputAttachmentCount; j++) {
uint32_t a = desc->pInputAttachments[j].attachment;
-subpass->input_attachments[j] = desc->pInputAttachments[j];
+subpass->input_attachments[j] = (struct anv_subpass_attachment) {
+ .usage = VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT,
+ .attachment = desc->pInputAttachments[j].attachment,
+ .layout = desc->pInputAttachments[j].layout,
+};
if (a != VK_ATTACHMENT_UNUSED) {
has_input = true;
pass->attachments[a].usage |=
VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT;
@@ -138,7 +142,11 @@ VkResult anv_CreateRenderPass(
for (uint32_t j = 0; j < desc->colorAttachmentCount; j++) {
uint32_t a = desc->pColorAttachments[j].attachment;
-subpass->color_attachments[j] = desc->pColorAttachments[j];
+subpass->color_attachments[j] = (struct anv_subpass_attachment) {
+ .usage = VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT,
+ .attachment = desc->pColorAttachments[j].attachment,
+ .layout = desc->pColorAttachments[j].layout,
+};
if (a != VK_ATTACHMENT_UNUSED) {
has_color = true;
pass->attachments[a].usage |=
VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
@@ -157,7 +165,11 @@ VkResult anv_CreateRenderPass(
for (uint32_t j = 0; j < desc->colorAttachmentCount; j++) {
uint32_t a = desc->pResolveAttachments[j].attachment;
-subpass->resolve_attachments[j] = desc->pResolveAttachments[j];
+subpass->resolve_attachments[j] = (struct anv_subpass_attachment) {
+ .usage = VK_IMAGE_USAGE_TRANSFER_DST_BIT,
+ .attachment = desc->pResolveAttachments[j].attachment,
+ .layout = desc->pResolveAttachments[j].layout,
+};
if (a != VK_ATTACHMENT_UNUSED) {
subpass->has_resolve = true;
uint32_t color_att = desc->pColorAttachments[j].attachment;
@@ -174,8 +186,12 @@ VkResult anv_CreateRenderPass(
if (desc->pDepthStencilAttachment) {
uint32_t a = desc->pDepthStencilAttachment->attachment;
- *subpass_attachments++ = subpass->depth_stencil_attachment =
-*desc->pDepthStencilAttachment;
+ subpass->depth_stencil_attachment = (struct anv_subpass_attachment) {
+.usage = VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT,
+.attachment = desc->pDepthStencilAttachment->attachment,
+.layout = desc->pDepthStencilAttachment->layout,
+ };
+ *subpass_attachments++ = subpass->depth_stencil_attachment;
if (a != VK_ATTACHMENT_UNUSED) {
has_depth = true;
pass->attachments[a].usage |=
@@ -186,8 +202,11 @@ VkResult anv_CreateRenderPass(
*desc->pDepthStencilAttachment);
}
} else {
- subpass->depth_stencil_attachment.attachment = VK_ATTACHMENT_UNUSED;
- subpass->depth_stencil_attachment.layout = VK_IMAGE_LAYOUT_UNDEFINED;
+ subpass->depth_stencil_attachment = (struct anv_subpass_attachment) {
+.usage = VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT,
+.attachment = VK_ATTACHMENT_UNUSED,
+.layout = VK_IMAGE_LAYOUT_UNDEFINED,
+ };
Mesa (master): anv/cmd_buffer: Move the rest of clear_subpass into begin_subpass
Module: Mesa
Branch: master
Commit: 6fc85556108794169657d8fdc6cf2377c0de08b3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6fc85556108794169657d8fdc6cf2377c0de08b3
Author: Jason Ekstrand
Date: Tue Nov 21 14:46:25 2017 -0800
anv/cmd_buffer: Move the rest of clear_subpass into begin_subpass
Reviewed-by: Nanley Chery
---
src/intel/vulkan/anv_blorp.c | 240 -
src/intel/vulkan/anv_private.h | 17 ++-
src/intel/vulkan/genX_cmd_buffer.c | 68 ++-
3 files changed, 185 insertions(+), 140 deletions(-)
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 8ef7b6de7b..a3551fee94 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1139,143 +1139,6 @@ enum subpass_stage {
SUBPASS_STAGE_RESOLVE,
};
-static bool
-subpass_needs_clear(const struct anv_cmd_buffer *cmd_buffer)
-{
- const struct anv_cmd_state *cmd_state = &cmd_buffer->state;
- uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
-
- if (ds != VK_ATTACHMENT_UNUSED) {
- assert(ds < cmd_state->pass->attachment_count);
- if (cmd_state->attachments[ds].pending_clear_aspects)
- return true;
- }
-
- return false;
-}
-
-void
-anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer)
-{
- const struct anv_cmd_state *cmd_state = &cmd_buffer->state;
- const VkRect2D render_area = cmd_buffer->state.render_area;
-
-
- if (!subpass_needs_clear(cmd_buffer))
- return;
-
- /* Because this gets called within a render pass, we tell blorp not to
-* trash our depth and stencil buffers.
-*/
- struct blorp_batch batch;
- blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer,
-BLORP_BATCH_NO_EMIT_DEPTH_STENCIL);
-
- VkClearRect clear_rect = {
- .rect = cmd_buffer->state.render_area,
- .baseArrayLayer = 0,
- .layerCount = cmd_buffer->state.framebuffer->layers,
- };
-
- struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
-
- const uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
- assert(ds == VK_ATTACHMENT_UNUSED || ds <
cmd_state->pass->attachment_count);
-
- if (ds != VK_ATTACHMENT_UNUSED &&
- cmd_state->attachments[ds].pending_clear_aspects) {
-
- VkClearAttachment clear_att = {
- .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
- .clearValue = cmd_state->attachments[ds].clear_value,
- };
-
-
- const uint8_t gen = cmd_buffer->device->info.gen;
- bool clear_with_hiz = gen >= 8 && cmd_state->attachments[ds].aux_usage ==
-ISL_AUX_USAGE_HIZ;
- const struct anv_image_view *iview = fb->attachments[ds];
-
- if (clear_with_hiz) {
- const bool clear_depth = clear_att.aspectMask &
- VK_IMAGE_ASPECT_DEPTH_BIT;
- const bool clear_stencil = clear_att.aspectMask &
-VK_IMAGE_ASPECT_STENCIL_BIT;
-
- /* Check against restrictions for depth buffer clearing. A great GPU
- * performance benefit isn't expected when using the HZ sequence for
- * stencil-only clears. Therefore, we don't emit a HZ op sequence for
- * a stencil clear in addition to using the BLORP-fallback for depth.
- */
- if (clear_depth) {
-if (!blorp_can_hiz_clear_depth(gen, iview->planes[0].isl.format,
- iview->image->samples,
- render_area.offset.x,
- render_area.offset.y,
- render_area.offset.x +
- render_area.extent.width,
- render_area.offset.y +
- render_area.extent.height)) {
- clear_with_hiz = false;
-} else if (clear_att.clearValue.depthStencil.depth !=
- ANV_HZ_FC_VAL) {
- /* Don't enable fast depth clears for any color not equal to
-* ANV_HZ_FC_VAL.
-*/
- clear_with_hiz = false;
-} else if (gen == 8 &&
- anv_can_sample_with_hiz(&cmd_buffer->device->info,
- iview->image)) {
- /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
-* fast-cleared portion of a HiZ buffer. Testing has revealed
-* that Gen8 only supports returning 0.0f. Gens prior to gen8 do
-* not support this feature at all.
-*/
- clear_with_hiz = false;
-}
- }
-
- if (clear_with_hiz) {
-blorp_gen8_hiz_clear_attachments(&batch, iview->image->samples,
- render_area.offse
Mesa (master): anv/cmd_buffer: Do subpass image transitions in begin/end_subpass
Module: Mesa
Branch: master
Commit: 87e86ee2e65eb73df397b3140cfa056216438098
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=87e86ee2e65eb73df397b3140cfa056216438098
Author: Jason Ekstrand
Date: Tue Nov 21 15:56:35 2017 -0800
anv/cmd_buffer: Do subpass image transitions in begin/end_subpass
Reviewed-by: Nanley Chery
---
src/intel/vulkan/genX_cmd_buffer.c | 220 +++--
1 file changed, 88 insertions(+), 132 deletions(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index d11eca6d71..d90dcb0e1d 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -3286,130 +3286,6 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer)
cmd_buffer->state.hiz_enabled = info.hiz_usage == ISL_AUX_USAGE_HIZ;
}
-
-/**
- * @brief Perform any layout transitions required at the beginning and/or end
- *of the current subpass for depth buffers.
- *
- * TODO: Consider preprocessing the attachment reference array at render pass
- * create time to determine if no layout transition is needed at the
- * beginning and/or end of each subpass.
- *
- * @param cmd_buffer The command buffer the transition is happening within.
- * @param subpass_end If true, marks that the transition is happening at the
- *end of the subpass.
- */
-static void
-cmd_buffer_subpass_transition_layouts(struct anv_cmd_buffer * const cmd_buffer,
- const bool subpass_end)
-{
- /* We need a non-NULL command buffer. */
- assert(cmd_buffer);
-
- const struct anv_cmd_state * const cmd_state = &cmd_buffer->state;
- const struct anv_subpass * const subpass = cmd_state->subpass;
-
- /* This function must be called within a subpass. */
- assert(subpass);
-
- /* If there are attachment references, the array shouldn't be NULL.
-*/
- if (subpass->attachment_count > 0)
- assert(subpass->attachments);
-
- /* Iterate over the array of attachment references. */
- for (const struct anv_subpass_attachment *att_ref = subpass->attachments;
-att_ref < subpass->attachments + subpass->attachment_count; att_ref++)
{
-
- /* If the attachment is unused, we can't perform a layout transition. */
- if (att_ref->attachment == VK_ATTACHMENT_UNUSED)
- continue;
-
- /* This attachment index shouldn't go out of bounds. */
- assert(att_ref->attachment < cmd_state->pass->attachment_count);
-
- const struct anv_render_pass_attachment * const att_desc =
- &cmd_state->pass->attachments[att_ref->attachment];
- struct anv_attachment_state * const att_state =
- &cmd_buffer->state.attachments[att_ref->attachment];
-
- /* The attachment should not be used in a subpass after its last. */
- assert(att_desc->last_subpass_idx >= anv_get_subpass_id(cmd_state));
-
- if (subpass_end && anv_get_subpass_id(cmd_state) <
- att_desc->last_subpass_idx) {
- /* We're calling this function on a buffer twice in one subpass and
- * this is not the last use of the buffer. The layout should not have
- * changed from the first call and no transition is necessary.
- */
- assert(att_state->current_layout == att_ref->layout ||
-att_state->current_layout ==
-VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL);
- continue;
- }
-
- /* The attachment index must be less than the number of attachments
- * within the framebuffer.
- */
- assert(att_ref->attachment < cmd_state->framebuffer->attachment_count);
-
- const struct anv_image_view * const iview =
- cmd_state->framebuffer->attachments[att_ref->attachment];
- const struct anv_image * const image = iview->image;
-
- /* Get the appropriate target layout for this attachment. */
- VkImageLayout target_layout;
-
- /* A resolve is necessary before use as an input attachment if the clear
- * color or auxiliary buffer usage isn't supported by the sampler.
- */
- const bool input_needs_resolve =
-(att_state->fast_clear && !att_state->clear_color_is_zero_one) ||
-att_state->input_aux_usage != att_state->aux_usage;
- if (subpass_end) {
- target_layout = att_desc->final_layout;
- } else if (iview->aspect_mask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV &&
- !input_needs_resolve) {
- /* Layout transitions before the final only help to enable sampling as
- * an input attachment. If the input attachment supports sampling
- * using the auxiliary surface, we can skip such transitions by making
- * the target layout one that is CCS-aware.
- */
- target_layout = VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
- } else {
- target_layout = att_ref->layout;
- }
-
- /* Perform the layout transition. */
-
Mesa (master): anv/cmd_buffer: Move the color portion of clear_subpass into begin_subpass
Module: Mesa
Branch: master
Commit: 1900dd76d049d99f9bf256cccb1dee3a5ec3cb3b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1900dd76d049d99f9bf256cccb1dee3a5ec3cb3b
Author: Jason Ekstrand
Date: Tue Nov 21 13:30:49 2017 -0800
anv/cmd_buffer: Move the color portion of clear_subpass into begin_subpass
This doesn't really change much now but it will give us more/better
control over clears in the future. The one interesting functional
change here is that we are now re-emitting 3DSTATE_DEPTH_BUFFERS and
friends for each clear. However, this only happens at begin_subpass
time so it shouldn't be substantially more expensive.
Reviewed-by: Nanley Chery
---
src/intel/vulkan/anv_blorp.c | 124 ++---
src/intel/vulkan/anv_private.h | 8 +++
src/intel/vulkan/genX_cmd_buffer.c | 54 +++-
3 files changed, 94 insertions(+), 92 deletions(-)
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index d98bf8364d..8ef7b6de7b 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1145,17 +1145,6 @@ subpass_needs_clear(const struct anv_cmd_buffer
*cmd_buffer)
const struct anv_cmd_state *cmd_state = &cmd_buffer->state;
uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
- for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
- uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
- if (a == VK_ATTACHMENT_UNUSED)
- continue;
-
- assert(a < cmd_state->pass->attachment_count);
- if (cmd_state->attachments[a].pending_clear_aspects) {
- return true;
- }
- }
-
if (ds != VK_ATTACHMENT_UNUSED) {
assert(ds < cmd_state->pass->attachment_count);
if (cmd_state->attachments[ds].pending_clear_aspects)
@@ -1189,86 +1178,6 @@ anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer
*cmd_buffer)
};
struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
- for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
- const uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
- if (a == VK_ATTACHMENT_UNUSED)
- continue;
-
- assert(a < cmd_state->pass->attachment_count);
- struct anv_attachment_state *att_state = &cmd_state->attachments[a];
-
- if (!att_state->pending_clear_aspects)
- continue;
-
- assert(att_state->pending_clear_aspects == VK_IMAGE_ASPECT_COLOR_BIT);
-
- struct anv_image_view *iview = fb->attachments[a];
- const struct anv_image *image = iview->image;
- struct blorp_surf surf;
- get_blorp_surf_for_anv_image(cmd_buffer->device,
- image, VK_IMAGE_ASPECT_COLOR_BIT,
- att_state->aux_usage, &surf);
-
- uint32_t base_layer = iview->planes[0].isl.base_array_layer;
- uint32_t layer_count = fb->layers;
-
- if (att_state->fast_clear) {
- surf.clear_color = vk_to_isl_color(att_state->clear_value.color);
-
- /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
- *
- *"After Render target fast clear, pipe-control with color cache
- *write-flush must be issued before sending any DRAW commands on
- *that render target."
- *
- * This comment is a bit cryptic and doesn't really tell you what's
- * going or what's really needed. It appears that fast clear ops are
- * not properly synchronized with other drawing. This means that we
- * cannot have a fast clear operation in the pipe at the same time as
- * other regular drawing operations. We need to use a PIPE_CONTROL
- * to ensure that the contents of the previous draw hit the render
- * target before we resolve and then use a second PIPE_CONTROL after
- * the resolve to ensure that it is completed before any additional
- * drawing occurs.
- */
- cmd_buffer->state.pending_pipe_bits |=
-ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
-
- /* We only support fast-clears on the first layer */
- assert(iview->planes[0].isl.base_level == 0);
- assert(iview->planes[0].isl.base_array_layer == 0);
-
- assert(image->n_planes == 1);
- blorp_fast_clear(&batch, &surf, iview->planes[0].isl.format, 0, 0, 1,
- render_area.offset.x, render_area.offset.y,
- render_area.offset.x + render_area.extent.width,
- render_area.offset.y + render_area.extent.height);
- base_layer++;
- layer_count--;
-
- cmd_buffer->state.pending_pipe_bits |=
-ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
- }
-
- if (layer_count > 0) {
- assert(image->n_planes == 1);
- anv_cmd_buffer_mark_image_written(cmd_buffer, image,
-
Mesa (master): intel/blorp: Add a blorp_hiz_clear_depth_stencil helper
Module: Mesa
Branch: master
Commit: 79918389739e178da117ec3195594eaeaa943284
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=79918389739e178da117ec3195594eaeaa943284
Author: Jason Ekstrand
Date: Tue Nov 21 14:00:44 2017 -0800
intel/blorp: Add a blorp_hiz_clear_depth_stencil helper
This is similar to blorp_gen8_hiz_clear_attachments except that it takes
actual images instead of trusting in the already set depth state.
Reviewed-by: Nanley Chery
---
src/intel/blorp/blorp.h | 11 +
src/intel/blorp/blorp_clear.c | 53 +++
2 files changed, 64 insertions(+)
diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
index ce3762c42f..4626f2f83c 100644
--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -170,6 +170,17 @@ blorp_can_hiz_clear_depth(uint8_t gen, enum isl_format
format,
uint32_t num_samples,
uint32_t x0, uint32_t y0,
uint32_t x1, uint32_t y1);
+void
+blorp_hiz_clear_depth_stencil(struct blorp_batch *batch,
+ const struct blorp_surf *depth,
+ const struct blorp_surf *stencil,
+ uint32_t level,
+ uint32_t start_layer, uint32_t num_layers,
+ uint32_t x0, uint32_t y0,
+ uint32_t x1, uint32_t y1,
+ bool clear_depth, float depth_value,
+ bool clear_stencil, uint8_t stencil_value);
+
void
blorp_gen8_hiz_clear_attachments(struct blorp_batch *batch,
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index 421a6c5d34..dde116fa26 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -612,6 +612,59 @@ blorp_can_hiz_clear_depth(uint8_t gen, enum isl_format
format,
return true;
}
+void
+blorp_hiz_clear_depth_stencil(struct blorp_batch *batch,
+ const struct blorp_surf *depth,
+ const struct blorp_surf *stencil,
+ uint32_t level,
+ uint32_t start_layer, uint32_t num_layers,
+ uint32_t x0, uint32_t y0,
+ uint32_t x1, uint32_t y1,
+ bool clear_depth, float depth_value,
+ bool clear_stencil, uint8_t stencil_value)
+{
+ struct blorp_params params;
+ blorp_params_init(¶ms);
+
+ /* This requires WM_HZ_OP which only exists on gen8+ */
+ assert(ISL_DEV_GEN(batch->blorp->isl_dev) >= 8);
+
+ params.hiz_op = ISL_AUX_OP_FAST_CLEAR;
+ params.num_layers = 1;
+
+ params.x0 = x0;
+ params.y0 = y0;
+ params.x1 = x1;
+ params.y1 = y1;
+
+ for (uint32_t l = 0; l < num_layers; l++) {
+ const uint32_t layer = start_layer + l;
+ if (clear_stencil) {
+ brw_blorp_surface_info_init(batch->blorp, ¶ms.stencil, stencil,
+ level, layer,
+ ISL_FORMAT_UNSUPPORTED, true);
+ params.stencil_mask = 0xff;
+ params.stencil_ref = stencil_value;
+ params.num_samples = params.stencil.surf.samples;
+ }
+
+ if (clear_depth) {
+ /* If we're clearing depth, we must have HiZ */
+ assert(depth && depth->aux_usage == ISL_AUX_USAGE_HIZ);
+
+ brw_blorp_surface_info_init(batch->blorp, ¶ms.depth, depth,
+ level, layer,
+ ISL_FORMAT_UNSUPPORTED, true);
+ params.depth.clear_color.f32[0] = depth_value;
+ params.depth_format =
+isl_format_get_depth_format(depth->surf->format, false);
+ params.num_samples = params.depth.surf.samples;
+ }
+
+ batch->blorp->exec(batch, ¶ms);
+ }
+}
+
/* Given a depth stencil attachment, this function performs a fast depth clear
* on a depth portion and a regular clear on the stencil portion. When
* performing a fast depth clear on the depth portion, the HiZ buffer is simply
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Mesa (master): anv/cmd_buffer: Mark depth/stencil surfaces written in begin_subpass
Module: Mesa
Branch: master
Commit: 7d5f6b6088e1fd46560b1e2fe6f1b1c05687540a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7d5f6b6088e1fd46560b1e2fe6f1b1c05687540a
Author: Jason Ekstrand
Date: Sat Jan 13 10:59:05 2018 -0800
anv/cmd_buffer: Mark depth/stencil surfaces written in begin_subpass
Reviewed-by: Nanley Chery
---
src/intel/vulkan/genX_cmd_buffer.c | 50 ++
1 file changed, 29 insertions(+), 21 deletions(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 1b1bf56a6f..d11eca6d71 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -3284,27 +3284,6 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer)
isl_emit_depth_stencil_hiz_s(&device->isl_dev, dw, &info);
cmd_buffer->state.hiz_enabled = info.hiz_usage == ISL_AUX_USAGE_HIZ;
-
- /* We may be writing depth or stencil so we need to mark the surface.
-* Unfortunately, there's no way to know at this point whether the depth or
-* stencil tests used will actually write to the surface.
-*/
- if (image && (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
- genX(cmd_buffer_mark_image_written)(cmd_buffer, image,
- VK_IMAGE_ASPECT_DEPTH_BIT,
- info.hiz_usage,
- info.view->base_level,
- info.view->base_array_layer,
- info.view->array_len);
- }
- if (image && (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT)) {
- genX(cmd_buffer_mark_image_written)(cmd_buffer, image,
- VK_IMAGE_ASPECT_STENCIL_BIT,
- ISL_AUX_USAGE_NONE,
- info.view->base_level,
- info.view->base_array_layer,
- info.view->array_len);
- }
}
@@ -3590,6 +3569,35 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer,
iview->planes[0].isl.base_level,
iview->planes[0].isl.base_array_layer,
fb->layers);
+ } else if (subpass->attachments[i].usage ==
+ VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT) {
+ /* We may be writing depth or stencil so we need to mark the surface.
+ * Unfortunately, there's no way to know at this point whether the
+ * depth or stencil tests used will actually write to the surface.
+ *
+ * Even though stencil may be plane 1, it always shares a base_level
+ * with depth.
+ */
+ const struct isl_view *ds_view = &iview->planes[0].isl;
+ if (iview->aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT) {
+genX(cmd_buffer_mark_image_written)(cmd_buffer, image,
+VK_IMAGE_ASPECT_DEPTH_BIT,
+att_state->aux_usage,
+ds_view->base_level,
+ds_view->base_array_layer,
+fb->layers);
+ }
+ if (iview->aspect_mask & VK_IMAGE_ASPECT_STENCIL_BIT) {
+/* Even though stencil may be plane 1, it always shares a
+ * base_level with depth.
+ */
+genX(cmd_buffer_mark_image_written)(cmd_buffer, image,
+VK_IMAGE_ASPECT_STENCIL_BIT,
+ISL_AUX_USAGE_NONE,
+ds_view->base_level,
+ds_view->base_array_layer,
+fb->layers);
+ }
}
att_state->pending_clear_aspects = 0;
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Mesa (master): st/mesa: Factorize duplicate code in st_update_framebuffer_state()
Module: Mesa
Branch: master
Commit: 56bfcd50f7f49d9c5119cd1297064b4d62a0d964
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=56bfcd50f7f49d9c5119cd1297064b4d62a0d964
Author: Guillaume Charifi
Date: Fri Jan 5 17:49:39 2018 +0100
st/mesa: Factorize duplicate code in st_update_framebuffer_state()
Signed-off-by: Guillaume Charifi
Reviewed-by: Marek Olšák
Signed-off-by: Marek Olšák
---
src/mesa/state_tracker/st_atom_framebuffer.c | 18 +-
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/src/mesa/state_tracker/st_atom_framebuffer.c
b/src/mesa/state_tracker/st_atom_framebuffer.c
index a29f5b35a8..3ef3ff34a9 100644
--- a/src/mesa/state_tracker/st_atom_framebuffer.c
+++ b/src/mesa/state_tracker/st_atom_framebuffer.c
@@ -172,6 +172,9 @@ st_update_framebuffer_state( struct st_context *st )
* Depth/Stencil renderbuffer/surface.
*/
strb = st_renderbuffer(fb->Attachment[BUFFER_DEPTH].Renderbuffer);
+ if (!strb)
+ strb = st_renderbuffer(fb->Attachment[BUFFER_STENCIL].Renderbuffer);
+
if (strb) {
if (strb->is_rtt) {
/* rendering to a GL texture, may have to update surface */
@@ -180,19 +183,8 @@ st_update_framebuffer_state( struct st_context *st )
framebuffer.zsbuf = strb->surface;
update_framebuffer_size(&framebuffer, strb->surface);
}
- else {
- strb = st_renderbuffer(fb->Attachment[BUFFER_STENCIL].Renderbuffer);
- if (strb) {
- if (strb->is_rtt) {
-/* rendering to a GL texture, may have to update surface */
-st_update_renderbuffer_surface(st, strb);
- }
- framebuffer.zsbuf = strb->surface;
- update_framebuffer_size(&framebuffer, strb->surface);
- }
- else
- framebuffer.zsbuf = NULL;
- }
+ else
+ framebuffer.zsbuf = NULL;
#ifdef DEBUG
/* Make sure the resource binding flags were set properly */
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Mesa (master): st/mesa: Factorize duplicate code for atomic buffer binding
Module: Mesa
Branch: master
Commit: a572ec2efe00981ea866baeb387cccaa62bbc9d8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a572ec2efe00981ea866baeb387cccaa62bbc9d8
Author: Guillaume Charifi
Date: Tue Feb 20 12:49:28 2018 +0100
st/mesa: Factorize duplicate code for atomic buffer binding
Signed-off-by: Guillaume Charifi
Signed-off-by: Marek Olšák
---
src/mesa/state_tracker/st_atom_atomicbuf.c | 67 +-
1 file changed, 29 insertions(+), 38 deletions(-)
diff --git a/src/mesa/state_tracker/st_atom_atomicbuf.c
b/src/mesa/state_tracker/st_atom_atomicbuf.c
index eda9e51b58..6907d0064d 100644
--- a/src/mesa/state_tracker/st_atom_atomicbuf.c
+++ b/src/mesa/state_tracker/st_atom_atomicbuf.c
@@ -41,6 +41,30 @@
#include "st_program.h"
static void
+st_binding_to_sb(struct gl_buffer_binding *binding,
+ struct pipe_shader_buffer *sb)
+{
+ struct st_buffer_object *st_obj =
+ st_buffer_object(binding->BufferObject);
+
+ if (st_obj && st_obj->buffer) {
+ sb->buffer = st_obj->buffer;
+ sb->buffer_offset = binding->Offset;
+ sb->buffer_size = st_obj->buffer->width0 - binding->Offset;
+
+ /* AutomaticSize is FALSE if the buffer was set with BindBufferRange.
+ * Take the minimum just to be sure.
+ */
+ if (!binding->AutomaticSize)
+ sb->buffer_size = MIN2(sb->buffer_size, (unsigned) binding->Size);
+ } else {
+ sb->buffer = NULL;
+ sb->buffer_offset = 0;
+ sb->buffer_size = 0;
+ }
+}
+
+static void
st_bind_atomics(struct st_context *st, struct gl_program *prog,
enum pipe_shader_type shader_type)
{
@@ -52,23 +76,9 @@ st_bind_atomics(struct st_context *st, struct gl_program
*prog,
for (i = 0; i < prog->sh.data->NumAtomicBuffers; i++) {
struct gl_active_atomic_buffer *atomic =
&prog->sh.data->AtomicBuffers[i];
- struct gl_buffer_binding *binding =
- &st->ctx->AtomicBufferBindings[atomic->Binding];
- struct st_buffer_object *st_obj =
- st_buffer_object(binding->BufferObject);
- struct pipe_shader_buffer sb = { 0 };
-
- if (st_obj && st_obj->buffer) {
- sb.buffer = st_obj->buffer;
- sb.buffer_offset = binding->Offset;
- sb.buffer_size = st_obj->buffer->width0 - binding->Offset;
-
- /* AutomaticSize is FALSE if the buffer was set with BindBufferRange.
- * Take the minimum just to be sure.
- */
- if (!binding->AutomaticSize)
-sb.buffer_size = MIN2(sb.buffer_size, (unsigned) binding->Size);
- }
+ struct pipe_shader_buffer sb;
+
+ st_binding_to_sb(&st->ctx->AtomicBufferBindings[atomic->Binding], &sb);
st->pipe->set_shader_buffers(st->pipe, shader_type,
atomic->Binding, 1, &sb);
@@ -142,27 +152,8 @@ st_bind_hw_atomic_buffers(struct st_context *st)
if (!st->has_hw_atomics)
return;
- for (i = 0; i < st->ctx->Const.MaxAtomicBufferBindings; i++) {
- struct gl_buffer_binding *binding = &st->ctx->AtomicBufferBindings[i];
- struct st_buffer_object *st_obj =
st_buffer_object(binding->BufferObject);
- struct pipe_shader_buffer *sb = &buffers[i];
-
- if (st_obj && st_obj->buffer) {
-sb->buffer = st_obj->buffer;
-sb->buffer_offset = binding->Offset;
-sb->buffer_size = st_obj->buffer->width0 - binding->Offset;
-
-/* AutomaticSize is FALSE if the buffer was set with BindBufferRange.
- * Take the minimum just to be sure.
- */
-if (!binding->AutomaticSize)
- sb->buffer_size = MIN2(sb->buffer_size, (unsigned) binding->Size);
- } else {
-sb->buffer = NULL;
-sb->buffer_offset = 0;
-sb->buffer_size = 0;
- }
- }
+ for (i = 0; i < st->ctx->Const.MaxAtomicBufferBindings; i++)
+ st_binding_to_sb(&st->ctx->AtomicBufferBindings[i], &buffers[i]);
st->pipe->set_hw_atomic_buffers(st->pipe, 0,
st->ctx->Const.MaxAtomicBufferBindings, buffers);
}
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Mesa (master): freedreno/ir3: fix use_count refcnt'ing issue
Module: Mesa Branch: master Commit: 4c4e6232ee2e6dd4c19f526c06df05b829174240 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4c4e6232ee2e6dd4c19f526c06df05b829174240 Author: Rob Clark Date: Tue Feb 20 13:40:46 2018 -0500 freedreno/ir3: fix use_count refcnt'ing issue Was hitting an assert with vs-varying-array-mat4-index-col-row-wr.shader_test When eliminating a copy, we were dropping the use_count of the mov that is skipped, but not increasing the use_count of it's src instruction. Fixes: 76440fcca91 freedreno/ir3: clean up dangling false-dep's Signed-off-by: Rob Clark --- src/gallium/drivers/freedreno/ir3/ir3_cp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cp.c b/src/gallium/drivers/freedreno/ir3/ir3_cp.c index 7713c645e0..391e94ca44 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_cp.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_cp.c @@ -361,6 +361,7 @@ reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr, instr->barrier_conflict |= src->barrier_conflict; unuse(src); + reg->instr->use_count++; } } else if (is_same_type_mov(src) && ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): docs: fix patent url
Module: Mesa Branch: master Commit: ac731531a1e43e4fa3e10099380a3bba68d65bfd URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac731531a1e43e4fa3e10099380a3bba68d65bfd Author: Eric Engestrom Date: Tue Feb 20 13:35:56 2018 + docs: fix patent url Reported-by: Pierre Moreau Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov --- docs/patents.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/patents.txt b/docs/patents.txt index b20a045d4b..91c5757d14 100644 --- a/docs/patents.txt +++ b/docs/patents.txt @@ -27,5 +27,5 @@ ARB_texture_float: enable this extension. -[1] https://www.google.com/patents/about?id=mIIOEBAJ&dq=6650327 +[1] https://patents.google.com/patent/US6650327B1 [2] https://www.opengl.org/registry/specs/ARB/texture_float.txt ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): svga: replaced 'unsigned' with proper enum types in shader code
Module: Mesa
Branch: master
Commit: e7d1a9372309161d4faa06bcc2b38de021c9e398
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e7d1a9372309161d4faa06bcc2b38de021c9e398
Author: Brian Paul
Date: Fri Feb 16 13:57:51 2018 -0700
svga: replaced 'unsigned' with proper enum types in shader code
Reviewed-by: Charmaine Lee
---
src/gallium/drivers/svga/svga_tgsi_vgpu10.c | 33 ++---
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
index 4d0834b3f6..6b8337ccfd 100644
--- a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
+++ b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
@@ -2053,11 +2053,15 @@ emit_decl_instruction(struct svga_shader_emitter_v10
*emit,
*/
static void
emit_input_declaration(struct svga_shader_emitter_v10 *emit,
- VGPU10_OPCODE_TYPE opcodeType, unsigned operandType,
- unsigned dim, unsigned index, unsigned size,
- unsigned name, unsigned numComp,
- unsigned selMode, unsigned usageMask,
- unsigned interpMode)
+ VGPU10_OPCODE_TYPE opcodeType,
+ VGPU10_OPERAND_TYPE operandType,
+ VGPU10_OPERAND_INDEX_DIMENSION dim,
+ unsigned index, unsigned size,
+ VGPU10_SYSTEM_NAME name,
+ VGPU10_OPERAND_NUM_COMPONENTS numComp,
+ VGPU10_OPERAND_4_COMPONENT_SELECTION_MODE selMode,
+ unsigned usageMask,
+ VGPU10_INTERPOLATION_MODE interpMode)
{
VGPU10OpcodeToken0 opcode0;
VGPU10OperandToken0 operand0;
@@ -2117,8 +2121,9 @@ emit_input_declaration(struct svga_shader_emitter_v10
*emit,
*/
static void
emit_output_declaration(struct svga_shader_emitter_v10 *emit,
-unsigned type, unsigned index,
-unsigned name, unsigned usageMask)
+VGPU10_OPCODE_TYPE type, unsigned index,
+VGPU10_SYSTEM_NAME name,
+unsigned usageMask)
{
VGPU10OpcodeToken0 opcode0;
VGPU10OperandToken0 operand0;
@@ -2352,7 +2357,9 @@ emit_input_declarations(struct svga_shader_emitter_v10
*emit)
enum tgsi_semantic semantic_name = emit->info.input_semantic_name[i];
unsigned usage_mask = emit->info.input_usage_mask[i];
unsigned index = emit->linkage.input_map[i];
- unsigned type, interpolationMode, name;
+ VGPU10_OPCODE_TYPE type;
+ VGPU10_INTERPOLATION_MODE interpolationMode;
+ VGPU10_SYSTEM_NAME name;
if (usage_mask == 0)
continue; /* register is not actually used */
@@ -2412,9 +2419,10 @@ emit_input_declarations(struct svga_shader_emitter_v10
*emit)
unsigned usage_mask = emit->info.input_usage_mask[i];
unsigned index = emit->linkage.input_map[i];
VGPU10_OPCODE_TYPE opcodeType, operandType;
- unsigned numComp, selMode;
- unsigned name;
- unsigned dim;
+ VGPU10_OPERAND_NUM_COMPONENTS numComp;
+ VGPU10_OPERAND_4_COMPONENT_SELECTION_MODE selMode;
+ VGPU10_SYSTEM_NAME name;
+ VGPU10_OPERAND_INDEX_DIMENSION dim;
if (usage_mask == 0)
continue; /* register is not actually used */
@@ -2548,7 +2556,8 @@ emit_output_declarations(struct svga_shader_emitter_v10
*emit)
}
else {
/* VS or GS */
- unsigned name, type;
+ VGPU10_COMPONENT_NAME name;
+ VGPU10_OPCODE_TYPE type;
unsigned writemask = VGPU10_OPERAND_4_COMPONENT_MASK_ALL;
switch (semantic_name) {
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Mesa (master): configure.ac: pthread-stubs not present on OpenBSD
Module: Mesa Branch: master Commit: 9401d90a537f0db62e726eeffe468a64189550f1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9401d90a537f0db62e726eeffe468a64189550f1 Author: Jonathan Gray Date: Tue Feb 20 17:38:00 2018 +1100 configure.ac: pthread-stubs not present on OpenBSD pthread-stubs is no longer required on OpenBSD and has been removed. libpthread parts involved moved to libc. Signed-off-by: Jonathan Gray Cc: 17.3 18.0 Reviewed-by: Eric Engestrom Reviewed-by: Emil Velikov --- configure.ac | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/configure.ac b/configure.ac index d37cb67a46..8a9172690a 100644 --- a/configure.ac +++ b/configure.ac @@ -939,10 +939,10 @@ dnl In practise that should be sufficient for all platforms, since any dnl platforms build with GCC and Clang support the flag. PTHREAD_LIBS="$PTHREAD_LIBS -pthread" -dnl pthread-stubs is mandatory on BSD platforms, due to the nature of the +dnl pthread-stubs is mandatory on some BSD platforms, due to the nature of the dnl project. Even then there's a notable issue as described in the project README case "$host_os" in -linux* | cygwin* | darwin* | solaris* | *-gnu* | gnu*) +linux* | cygwin* | darwin* | solaris* | *-gnu* | gnu* | openbsd*) pthread_stubs_possible="no" ;; * ) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): swr: bump minimum supported LLVM version to 4.0
Module: Mesa
Branch: master
Commit: 36ac485bd1c99412717d2b3023c490d26ca91f92
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=36ac485bd1c99412717d2b3023c490d26ca91f92
Author: Andres Gomez
Date: Wed Feb 14 00:42:57 2018 +0200
swr: bump minimum supported LLVM version to 4.0
Since radv and radeonsi removed support for LLVM 3.9 the distcheck
target got broken because SWR distribution needed 3.9.x.
After checking with George Kyriazis, SWR is OK with moving to LLVM 4.0
and above, which will solve this problem.
Fixes: 3bf1e036e8a ("amd: remove support for LLVM 3.9")
Cc: George Kyriazis
Cc: Tim Rowley
Cc: Emil Velikov
Cc: Dylan Baker
Cc: Eric Engestrom
Signed-off-by: Andres Gomez
Reviewed-by: Dylan Baker
Reviewed-by: George Kyriazis
---
.travis.yml | 15 ++-
configure.ac| 6 +++---
meson.build | 4 ++--
src/gallium/drivers/swr/Makefile.am | 2 +-
src/gallium/drivers/swr/SConscript | 4 ++--
5 files changed, 14 insertions(+), 17 deletions(-)
diff --git a/.travis.yml b/.travis.yml
index 3651d00169..0ec08e5bff 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -90,12 +90,10 @@ matrix:
- BUILD=make
- MAKEFLAGS="-j4"
- MAKE_CHECK_COMMAND="true"
-- LLVM_VERSION=3.9
+- LLVM_VERSION=4.0
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
- OVERRIDE_CC="gcc-4.8"
- OVERRIDE_CXX="g++-4.8"
-# New binutils linker is required for llvm-3.9
-- OVERRIDE_PATH=/usr/lib/binutils-2.26/bin
- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
- DRI_DRIVERS=""
- GALLIUM_ST="--enable-dri --disable-opencl --disable-xa
--disable-nine --disable-xvmc --disable-vdpau --disable-va
--disable-omx-bellagio --disable-gallium-osmesa"
@@ -105,13 +103,12 @@ matrix:
addons:
apt:
sources:
-- llvm-toolchain-trusty-3.9
+- llvm-toolchain-trusty-4.0
packages:
-- binutils-2.26
# LLVM packaging is broken and misses these dependencies
- libedit-dev
# From sources above
-- llvm-3.9-dev
+- llvm-4.0-dev
# Common
- xz-utils
- x11proto-xf86vidmode-dev
@@ -400,7 +397,7 @@ matrix:
- BUILD=scons
- SCONSFLAGS="-j4"
- SCONS_TARGET="swr=1"
-- LLVM_VERSION=3.9
+- LLVM_VERSION=4.0
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
# Keep it symmetrical to the make build. There's no actual SWR, yet.
- SCONS_CHECK_COMMAND="true"
@@ -409,13 +406,13 @@ matrix:
addons:
apt:
sources:
-- llvm-toolchain-trusty-3.9
+- llvm-toolchain-trusty-4.0
packages:
- scons
# LLVM packaging is broken and misses these dependencies
- libedit-dev
# From sources above
-- llvm-3.9-dev
+- llvm-4.0-dev
# Common
- xz-utils
- x11proto-xf86vidmode-dev
diff --git a/configure.ac b/configure.ac
index 994052d5c4..d37cb67a46 100644
--- a/configure.ac
+++ b/configure.ac
@@ -105,7 +105,7 @@ LLVM_REQUIRED_OPENCL=3.9.0
LLVM_REQUIRED_R600=3.9.0
LLVM_REQUIRED_RADEONSI=4.0.0
LLVM_REQUIRED_RADV=4.0.0
-LLVM_REQUIRED_SWR=3.9.0
+LLVM_REQUIRED_SWR=4.0.0
dnl Check for progs
AC_PROG_CPP
@@ -2695,8 +2695,8 @@ if test -n "$with_gallium_drivers"; then
fi
# XXX: Keep in sync with LLVM_REQUIRED_SWR
-AM_CONDITIONAL(SWR_INVALID_LLVM_VERSION, test "x$LLVM_VERSION" != x3.9.0 -a \
- "x$LLVM_VERSION" != x3.9.1)
+AM_CONDITIONAL(SWR_INVALID_LLVM_VERSION, test "x$LLVM_VERSION" != x4.0.0 -a \
+ "x$LLVM_VERSION" != x4.0.1)
if test "x$enable_llvm" = "xyes" -a "$with_gallium_drivers"; then
llvm_require_version $LLVM_REQUIRED_GALLIUM "gallium"
diff --git a/meson.build b/meson.build
index 6fc7ec7fc9..8cf67b8171 100644
--- a/meson.build
+++ b/meson.build
@@ -1011,9 +1011,9 @@ if with_gallium_opencl
# TODO: optional modules
endif
-if with_amd_vk or with_gallium_radeonsi
+if with_amd_vk or with_gallium_radeonsi or with_gallium_swr
_llvm_version = '>= 4.0.0'
-elif with_gallium_opencl or with_gallium_swr or with_gallium_r600
+elif with_gallium_opencl or with_gallium_r600
_llvm_version = '>= 3.9.0'
else
_llvm_version = '>= 3.3.0'
diff --git a/src/gallium/drivers/swr/Makefile.am
b/src/gallium/drivers/swr/Makefile.am
index 869eec16d8..2edaf666f1 100644
--- a/src/gallium/drivers/swr/Makefile.am
+++ b/src/gallium/drivers/swr/Makefile.am
@@ -356,7 +356,7 @@ include $(top_srcdir)/install-gallium-links.mk
dist-hook:
if SWR_INVALID_LLVM_VERSION
@echo "***"
- @echo "LLVM 3.9.0 or LLVM 3.9.1 required to create the tarball"
+ @echo "L
Mesa (master): travis: radeonsi and radv need LLVM 4.0
Module: Mesa
Branch: master
Commit: b39f6d5fc7cec07249cf3fa23ba6163546a9a73b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b39f6d5fc7cec07249cf3fa23ba6163546a9a73b
Author: Andres Gomez
Date: Tue Feb 6 17:42:42 2018 +0200
travis: radeonsi and radv need LLVM 4.0
Fixes: 3bf1e036e8a ("amd: remove support for LLVM 3.9")
Cc: Marek Olšák
Cc: Emil Velikov
Cc: Jan Vesely
Signed-off-by: Andres Gomez
Reviewed-by: Emil Velikov
---
.travis.yml | 46 --
1 file changed, 36 insertions(+), 10 deletions(-)
diff --git a/.travis.yml b/.travis.yml
index 0156eefb7a..3651d00169 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -37,12 +37,12 @@ matrix:
addons:
apt:
sources:
-- llvm-toolchain-trusty-3.9
+- llvm-toolchain-trusty-4.0
packages:
# LLVM packaging is broken and misses these dependencies
- libedit-dev
# From sources above
-- llvm-3.9-dev
+- llvm-4.0-dev
# Common
- xz-utils
- libexpat1-dev
@@ -120,6 +120,35 @@ matrix:
- libelf-dev
- libunwind8-dev
- env:
+- LABEL="make Gallium Drivers RadeonSI"
+- BUILD=make
+- MAKEFLAGS="-j4"
+- MAKE_CHECK_COMMAND="true"
+- LLVM_VERSION=4.0
+- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
+- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
+- DRI_DRIVERS=""
+- GALLIUM_ST="--enable-dri --disable-opencl --disable-xa
--disable-nine --disable-xvmc --disable-vdpau --disable-va
--disable-omx-bellagio --disable-gallium-osmesa"
+- GALLIUM_DRIVERS="radeonsi"
+- VULKAN_DRIVERS=""
+- LIBUNWIND_FLAGS="--enable-libunwind"
+ addons:
+apt:
+ sources:
+- llvm-toolchain-trusty-4.0
+ packages:
+# LLVM packaging is broken and misses these dependencies
+- libedit-dev
+# From sources above
+- llvm-4.0-dev
+# Common
+- xz-utils
+- x11proto-xf86vidmode-dev
+- libexpat1-dev
+- libx11-xcb-dev
+- libelf-dev
+- libunwind8-dev
+- env:
- LABEL="make Gallium Drivers Other"
- BUILD=make
- MAKEFLAGS="-j4"
@@ -131,7 +160,7 @@ matrix:
- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
- DRI_DRIVERS=""
- GALLIUM_ST="--enable-dri --disable-opencl --disable-xa
--disable-nine --disable-xvmc --disable-vdpau --disable-va
--disable-omx-bellagio --disable-gallium-osmesa"
--
GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,radeonsi,freedreno,svga,swrast,vc4,virgl,etnaviv,imx"
+-
GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,freedreno,svga,swrast,vc4,virgl,etnaviv,imx"
- VULKAN_DRIVERS=""
- LIBUNWIND_FLAGS="--enable-libunwind"
addons:
@@ -166,7 +195,7 @@ matrix:
- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
- DRI_DRIVERS=""
- GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd
--enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau
--disable-va --disable-omx-bellagio --disable-gallium-osmesa"
-- GALLIUM_DRIVERS="r600,radeonsi"
+- GALLIUM_DRIVERS="r600"
- VULKAN_DRIVERS=""
- LIBUNWIND_FLAGS="--enable-libunwind"
addons:
@@ -303,10 +332,8 @@ matrix:
- BUILD=make
- MAKEFLAGS="-j4"
- MAKE_CHECK_COMMAND="make -C src/gtest check && make -C src/intel
check"
-- LLVM_VERSION=3.9
+- LLVM_VERSION=4.0
- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
-# New binutils linker is required for llvm-3.9
-- OVERRIDE_PATH=/usr/lib/binutils-2.26/bin
- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl
--with-platforms=x11,wayland"
- DRI_DRIVERS=""
- GALLIUM_ST="--enable-dri --enable-dri3 --disable-opencl --disable-xa
--disable-nine --disable-xvmc --disable-vdpau --disable-va
--disable-omx-bellagio --disable-gallium-osmesa"
@@ -316,13 +343,12 @@ matrix:
addons:
apt:
sources:
-- llvm-toolchain-trusty-3.9
+- llvm-toolchain-trusty-4.0
packages:
-- binutils-2.26
# LLVM packaging is broken and misses these dependencies
- libedit-dev
# From sources above
-- llvm-3.9-dev
+- llvm-4.0-dev
# Common
- xz-utils
- x11proto-xf86vidmode-dev
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Mesa (master): ac/nir: move ac_declare_lds_as_pointer() outside of the switch
Module: Mesa
Branch: master
Commit: 1ac741d690bea8e9a3d2dbc2f8e34deadc2ec072
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1ac741d690bea8e9a3d2dbc2f8e34deadc2ec072
Author: Samuel Pitoiset
Date: Fri Feb 16 10:33:10 2018 +0100
ac/nir: move ac_declare_lds_as_pointer() outside of the switch
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/common/ac_nir_to_llvm.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index dc471de977..12f097e2b2 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1068,8 +1068,6 @@ static void create_function(struct radv_shader_context
*ctx,
set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
&user_sgpr_idx, 1);
}
- if (ctx->options->key.vs.as_ls)
- ac_declare_lds_as_pointer(&ctx->ac);
break;
case MESA_SHADER_TESS_CTRL:
set_vs_specific_input_locs(ctx, stage, has_previous_stage,
@@ -1080,7 +1078,6 @@ static void create_function(struct radv_shader_context
*ctx,
set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx,
4);
if (ctx->abi.view_index)
set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx,
1);
- ac_declare_lds_as_pointer(&ctx->ac);
break;
case MESA_SHADER_TESS_EVAL:
set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx,
1);
@@ -1102,8 +1099,6 @@ static void create_function(struct radv_shader_context
*ctx,
&user_sgpr_idx, 2);
if (ctx->abi.view_index)
set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx,
1);
- if (has_previous_stage)
- ac_declare_lds_as_pointer(&ctx->ac);
break;
case MESA_SHADER_FRAGMENT:
if (ctx->shader_info->info.ps.needs_sample_positions) {
@@ -1115,6 +1110,13 @@ static void create_function(struct radv_shader_context
*ctx,
unreachable("Shader stage not implemented");
}
+ if (stage == MESA_SHADER_TESS_CTRL ||
+ (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
+ /* GFX9 has the ESGS ring buffer in LDS. */
+ (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
+ ac_declare_lds_as_pointer(&ctx->ac);
+ }
+
ctx->shader_info->num_user_sgprs = user_sgpr_idx;
}
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Mesa (master): radv: allow to force family using RADV_FORCE_FAMILY
Module: Mesa
Branch: master
Commit: b5d111ae763b672c141266760db55e83716d77f9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5d111ae763b672c141266760db55e83716d77f9
Author: Samuel Pitoiset
Date: Fri Feb 16 11:00:14 2018 +0100
radv: allow to force family using RADV_FORCE_FAMILY
Useful for pipeline-db.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Dave Airlie
---
src/amd/vulkan/radv_device.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 09bb382eeb..98cfd9b58a 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -183,6 +183,37 @@ radv_physical_device_init_mem_types(struct
radv_physical_device *device)
device->memory_properties.memoryTypeCount = type_count;
}
+static void
+radv_handle_env_var_force_family(struct radv_physical_device *device)
+{
+ const char *family = getenv("RADV_FORCE_FAMILY");
+ unsigned i;
+
+ if (!family)
+ return;
+
+ for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
+ if (!strcmp(family, ac_get_llvm_processor_name(i))) {
+ /* Override family and chip_class. */
+ device->rad_info.family = i;
+
+ if (i >= CHIP_VEGA10)
+ device->rad_info.chip_class = GFX9;
+ else if (i >= CHIP_TONGA)
+ device->rad_info.chip_class = VI;
+ else if (i >= CHIP_BONAIRE)
+ device->rad_info.chip_class = CIK;
+ else
+ device->rad_info.chip_class = SI;
+
+ return;
+ }
+ }
+
+ fprintf(stderr, "radv: Unknown family: %s\n", family);
+ exit(1);
+}
+
static VkResult
radv_physical_device_init(struct radv_physical_device *device,
struct radv_instance *instance,
@@ -226,6 +257,8 @@ radv_physical_device_init(struct radv_physical_device
*device,
device->local_fd = fd;
device->ws->query_info(device->ws, &device->rad_info);
+ radv_handle_env_var_force_family(device);
+
radv_get_device_name(device->rad_info.family, device->name,
sizeof(device->name));
if (radv_device_get_cache_uuid(device->rad_info.family,
device->cache_uuid)) {
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Mesa (master): loader_dri3/glx/egl: Reinstate the loader_dri3_vtable get_dri_screen callback
Module: Mesa
Branch: master
Commit: f386776ea55f86d0288c955cf4cf877a1b4a027d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f386776ea55f86d0288c955cf4cf877a1b4a027d
Author: Thomas Hellstrom
Date: Fri Feb 9 09:37:19 2018 +0100
loader_dri3/glx/egl: Reinstate the loader_dri3_vtable get_dri_screen callback
Removing this callback caused rendering corruption in some multi-screen cases,
so it is reinstated but without the drawable argument which was never used
by implementations and was confusing since the drawable could have been
created with another screen.
Cc: "17.3 18.0" mesa-sta...@lists.freedesktop.org
Fixes: 5198e48a0d (loader_dri3/glx/egl: Remove the loader_dri3_vtable
get_dri_screen callback)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105013
Reported-by: Daniel van Vugt
Tested-by: Timo Aaltonen
Signed-off-by: Thomas Hellstrom
Reviewed-by: Brian Paul
---
src/egl/drivers/dri2/platform_x11_dri3.c | 12
src/glx/dri3_glx.c | 11 +++
src/loader/loader_dri3_helper.c | 12 +++-
src/loader/loader_dri3_helper.h | 1 +
4 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/src/egl/drivers/dri2/platform_x11_dri3.c
b/src/egl/drivers/dri2/platform_x11_dri3.c
index 6ead4d0a22..2073c592dc 100644
--- a/src/egl/drivers/dri2/platform_x11_dri3.c
+++ b/src/egl/drivers/dri2/platform_x11_dri3.c
@@ -75,6 +75,17 @@ egl_dri3_get_dri_context(struct loader_dri3_drawable *draw)
return dri2_ctx->dri_context;
}
+static __DRIscreen *
+egl_dri3_get_dri_screen(void)
+{
+ _EGLContext *ctx = _eglGetCurrentContext();
+ struct dri2_egl_context *dri2_ctx;
+ if (!ctx)
+ return NULL;
+ dri2_ctx = dri2_egl_context(ctx);
+ return dri2_egl_display(dri2_ctx->base.Resource.Display)->dri_screen;
+}
+
static void
egl_dri3_flush_drawable(struct loader_dri3_drawable *draw, unsigned flags)
{
@@ -88,6 +99,7 @@ static const struct loader_dri3_vtable egl_dri3_vtable = {
.set_drawable_size = egl_dri3_set_drawable_size,
.in_current_context = egl_dri3_in_current_context,
.get_dri_context = egl_dri3_get_dri_context,
+ .get_dri_screen = egl_dri3_get_dri_screen,
.flush_drawable = egl_dri3_flush_drawable,
.show_fps = NULL,
};
diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c
index f280a8cef7..016f91b196 100644
--- a/src/glx/dri3_glx.c
+++ b/src/glx/dri3_glx.c
@@ -116,6 +116,16 @@ glx_dri3_get_dri_context(struct loader_dri3_drawable *draw)
return (gc != &dummyContext) ? dri3Ctx->driContext : NULL;
}
+static __DRIscreen *
+glx_dri3_get_dri_screen(void)
+{
+ struct glx_context *gc = __glXGetCurrentContext();
+ struct dri3_context *pcp = (struct dri3_context *) gc;
+ struct dri3_screen *psc = (struct dri3_screen *) pcp->base.psc;
+
+ return (gc != &dummyContext && psc) ? psc->driScreen : NULL;
+}
+
static void
glx_dri3_flush_drawable(struct loader_dri3_drawable *draw, unsigned flags)
{
@@ -150,6 +160,7 @@ static const struct loader_dri3_vtable glx_dri3_vtable = {
.set_drawable_size = glx_dri3_set_drawable_size,
.in_current_context = glx_dri3_in_current_context,
.get_dri_context = glx_dri3_get_dri_context,
+ .get_dri_screen = glx_dri3_get_dri_screen,
.flush_drawable = glx_dri3_flush_drawable,
.show_fps = glx_dri3_show_fps,
};
diff --git a/src/loader/loader_dri3_helper.c b/src/loader/loader_dri3_helper.c
index 0cd0dffa69..30ea133f7e 100644
--- a/src/loader/loader_dri3_helper.c
+++ b/src/loader/loader_dri3_helper.c
@@ -1318,6 +1318,7 @@ dri3_get_pixmap_buffer(__DRIdrawable *driDrawable,
unsigned int format,
xcb_sync_fence_t sync_fence;
struct xshmfence *shm_fence;
int fence_fd;
+ __DRIscreen *cur_screen;
if (buffer)
return buffer;
@@ -1348,8 +1349,17 @@ dri3_get_pixmap_buffer(__DRIdrawable *driDrawable,
unsigned int format,
if (!bp_reply)
goto no_image;
+ /* Get the currently-bound screen or revert to using the drawable's screen
if
+* no contexts are currently bound. The latter case is at least necessary
for
+* obs-studio, when using Window Capture (Xcomposite) as a Source.
+*/
+ cur_screen = draw->vtable->get_dri_screen();
+ if (!cur_screen) {
+ cur_screen = draw->dri_screen;
+ }
+
buffer->image = loader_dri3_create_image(draw->conn, bp_reply, format,
-draw->dri_screen, draw->ext->image,
+cur_screen, draw->ext->image,
buffer);
if (!buffer->image)
goto no_image;
diff --git a/src/loader/loader_dri3_helper.h b/src/loader/loader_dri3_helper.h
index 4ce98b8c59..839cba30df 100644
--- a/src/loader/loader_dri3_helper.h
+++ b/src/loader/loader_dri3_helper.h
@@ -99,6 +99,7 @@ struct loader_dri3_vtable {
void (*set_drawable_size)(struct loader_dri3_drawable *,
Mesa (master): svga: Fix a leftover debug hack
Module: Mesa Branch: master Commit: 80c31f7837cd319910d94d780f5048de6cce0adb URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=80c31f7837cd319910d94d780f5048de6cce0adb Author: Thomas Hellstrom Date: Mon Jan 15 12:51:27 2018 +0100 svga: Fix a leftover debug hack Fix what appears to be a leftover debug hack. The hack would force the driver to take a different blit path; possibly, although unverified, reverting to software blits. Tested using piglit tests/quick. No related regressions. Cc: "17.2 17.3 18.0" Fixes: 9d81ab7376 (svga: Relax the format checks for copy_region_vgpu10 somewhat) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104625 Reported-by: Grazvydas Ignotas Signed-off-by: Thomas Hellstrom Reviewed-by: Brian Paul --- src/gallium/drivers/svga/svga_pipe_blit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/svga/svga_pipe_blit.c b/src/gallium/drivers/svga/svga_pipe_blit.c index e98113c385..4b65a69a9e 100644 --- a/src/gallium/drivers/svga/svga_pipe_blit.c +++ b/src/gallium/drivers/svga/svga_pipe_blit.c @@ -351,8 +351,8 @@ can_blit_via_surface_copy(struct svga_context *svga, if (blit_info->src.resource->format != blit_info->src.format || blit_info->dst.resource->format != blit_info->dst.format || - !util_is_format_compatible(src_desc, dst_desc)); - return FALSE; + !util_is_format_compatible(src_desc, dst_desc)) + return false; } if (svga->render_condition && blit_info->render_condition_enable) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
