Mesa (master): egl: remove wayland-egl now that we're using libwayland-egl

[Matt Turner]

Module: Mesa
Branch: master
Commit: b9361c9df051be632ef7b6481afe5b6c3c5efe4f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9361c9df051be632ef7b6481afe5b6c3c5efe4f

Author: Eric Engestrom 
Date:   Tue May 29 15:41:29 2018 +0100

egl: remove wayland-egl now that we're using libwayland-egl

Cc: Emil Velikov 
Cc: Daniel Stone 
Reviewed-by: Matt Turner 
Signed-off-by: Eric Engestrom 

---

 src/egl/wayland/wayland-egl/Makefile.am|  24 ---
 src/egl/wayland/wayland-egl/meson.build|  50 -
 .../wayland/wayland-egl/wayland-egl-abi-check.c| 235 -
 src/egl/wayland/wayland-egl/wayland-egl-backend.h  |  63 --
 .../wayland/wayland-egl/wayland-egl-symbols-check  |  24 ---
 src/egl/wayland/wayland-egl/wayland-egl.c  | 109 --
 src/egl/wayland/wayland-egl/wayland-egl.pc.in  |  11 -
 7 files changed, 516 deletions(-)

diff --git a/src/egl/wayland/wayland-egl/Makefile.am 
b/src/egl/wayland/wayland-egl/Makefile.am
deleted file mode 100644
index 31dcca9e10..00
--- a/src/egl/wayland/wayland-egl/Makefile.am
+++ /dev/null
@@ -1,24 +0,0 @@
-pkgconfigdir = $(libdir)/pkgconfig
-pkgconfig_DATA = wayland-egl.pc
-
-AM_CFLAGS = $(DEFINES) \
-   $(VISIBILITY_CFLAGS) \
-   $(WAYLAND_CLIENT_CFLAGS)
-
-lib_LTLIBRARIES = libwayland-egl.la
-noinst_HEADERS = wayland-egl-backend.h
-libwayland_egl_la_SOURCES = wayland-egl.c
-libwayland_egl_la_LDFLAGS = \
-   -no-undefined \
-   -version-info 1 \
-   $(GC_SECTIONS) \
-   $(LD_NO_UNDEFINED)
-
-TESTS = wayland-egl-symbols-check \
-wayland-egl-abi-check
-
-EXTRA_DIST = wayland-egl-symbols-check meson.build
-
-check_PROGRAMS = wayland-egl-abi-check
-
-include $(top_srcdir)/install-lib-links.mk
diff --git a/src/egl/wayland/wayland-egl/meson.build 
b/src/egl/wayland/wayland-egl/meson.build
deleted file mode 100644
index d0a7521da9..00
--- a/src/egl/wayland/wayland-egl/meson.build
+++ /dev/null
@@ -1,50 +0,0 @@
-# Copyright © 2017 Intel Corporation
-
-# Permission is hereby granted, free of charge, to any person obtaining a copy
-# of this software and associated documentation files (the "Software"), to deal
-# in the Software without restriction, including without limitation the rights
-# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-# copies of the Software, and to permit persons to whom the Software is
-# furnished to do so, subject to the following conditions:
-
-# The above copyright notice and this permission notice shall be included in
-# all copies or substantial portions of the Software.
-
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-# SOFTWARE.
-
-
-libwayland_egl = shared_library(
-  'wayland-egl',
-  'wayland-egl.c',
-  c_args : [c_vis_args],
-  link_args : ld_args_gc_sections,
-  dependencies : dep_wayland_client,
-  version : '1.0.0',
-  install : true,
-)
-
-pkg.generate(
-  name : 'wayland-egl',
-  description : 'Mesa wayland-egl library',
-  libraries : libwayland_egl,
-  version : meson.project_version(),
-  requires : 'wayland-client',
-)
-
-if with_tests
-  test('wayland-egl-symbols-check',
-find_program('wayland-egl-symbols-check'),
-env : env_test,
-args : libwayland_egl
-  )
-  test(
-'wayland-egl-abi-check',
-executable('wayland-egl-abi-check', 'wayland-egl-abi-check.c')
-  )
-endif
diff --git a/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c 
b/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c
deleted file mode 100644
index 62c51a2260..00
--- a/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
- * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SH

Mesa (master): egl: rewire the build systems to use libwayland-egl

[Matt Turner]

Module: Mesa
Branch: master
Commit: 1db4ec05462914096b1f243e9b2af7e71cf38622
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1db4ec05462914096b1f243e9b2af7e71cf38622

Author: Eric Engestrom 
Date:   Tue May 29 15:41:28 2018 +0100

egl: rewire the build systems to use libwayland-egl

Cc: Emil Velikov 
Cc: Daniel Stone 
Reviewed-by: Matt Turner 
Signed-off-by: Eric Engestrom 

---

 configure.ac   |  6 --
 meson.build|  3 +++
 src/Makefile.am|  5 -
 src/egl/Makefile.am|  3 ++-
 src/egl/drivers/dri2/platform_wayland.c|  7 +++
 src/egl/meson.build| 10 ++
 src/gallium/state_trackers/omx/tizonia/Makefile.am |  2 +-
 7 files changed, 15 insertions(+), 21 deletions(-)

diff --git a/configure.ac b/configure.ac
index 600127af8f..875c47fcd4 100644
--- a/configure.ac
+++ b/configure.ac
@@ -90,6 +90,7 @@ LIBOMXIL_TIZONIA_REQUIRED=0.10.0
 LIBVA_REQUIRED=0.39.0
 VDPAU_REQUIRED=1.1
 WAYLAND_REQUIRED=1.11
+WAYLAND_EGL_REQUIRED=1.15
 WAYLAND_PROTOCOLS_REQUIRED=1.8
 XCB_REQUIRED=1.9.3
 XCBDRI2_REQUIRED=1.8
@@ -1808,6 +1809,9 @@ for plat in $platforms; do
 PKG_CHECK_MODULES([WAYLAND_CLIENT], [wayland-client >= 
$WAYLAND_REQUIRED])
 PKG_CHECK_MODULES([WAYLAND_SERVER], [wayland-server >= 
$WAYLAND_REQUIRED])
 PKG_CHECK_MODULES([WAYLAND_PROTOCOLS], [wayland-protocols >= 
$WAYLAND_PROTOCOLS_REQUIRED])
+if test "x$enable_egl" = xyes; then
+  PKG_CHECK_MODULES([WAYLAND_EGL], [wayland-egl >= 
$WAYLAND_EGL_REQUIRED])
+fi
 WAYLAND_PROTOCOLS_DATADIR=`$PKG_CONFIG --variable=pkgdatadir 
wayland-protocols`
 
 PKG_CHECK_MODULES([WAYLAND_SCANNER], [wayland-scanner],
@@ -3022,8 +3026,6 @@ AC_CONFIG_FILES([Makefile
  src/egl/Makefile
  src/egl/main/egl.pc
  src/egl/wayland/wayland-drm/Makefile
- src/egl/wayland/wayland-egl/Makefile
- src/egl/wayland/wayland-egl/wayland-egl.pc
  src/gallium/Makefile
  src/gallium/auxiliary/Makefile
  src/gallium/auxiliary/pipe-loader/Makefile
diff --git a/meson.build b/meson.build
index 1d1b2a979b..4d4ca5d557 100644
--- a/meson.build
+++ b/meson.build
@@ -1201,6 +1201,9 @@ if with_platform_wayland
   dep_wl_protocols = dependency('wayland-protocols', version : '>= 1.8')
   dep_wayland_client = dependency('wayland-client', version : '>=1.11')
   dep_wayland_server = dependency('wayland-server', version : '>=1.11')
+  if with_egl
+dep_wayland_egl = dependency('wayland-egl', version : '>=1.15')
+  endif
   wayland_dmabuf_xml = join_paths(
 dep_wl_protocols.get_pkgconfig_variable('pkgdatadir'), 'unstable',
 'linux-dmabuf', 'linux-dmabuf-unstable-v1.xml'
diff --git a/src/Makefile.am b/src/Makefile.am
index fd5ae44550..9bb3bce3c0 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -95,11 +95,6 @@ if HAVE_GBM
 SUBDIRS += gbm
 endif
 
-## Optionally required by EGL
-if HAVE_PLATFORM_WAYLAND
-SUBDIRS += egl/wayland/wayland-egl
-endif
-
 if HAVE_EGL
 SUBDIRS += egl
 endif
diff --git a/src/egl/Makefile.am b/src/egl/Makefile.am
index 086a4a1e63..be3547d968 100644
--- a/src/egl/Makefile.am
+++ b/src/egl/Makefile.am
@@ -84,6 +84,8 @@ drivers/dri2/egl_dri2.lo: 
drivers/dri2/linux-dmabuf-unstable-v1-client-protocol.
 AM_CFLAGS += $(WAYLAND_CLIENT_CFLAGS)
 libEGL_common_la_LIBADD += $(WAYLAND_CLIENT_LIBS)
 libEGL_common_la_LIBADD += $(LIBDRM_LIBS)
+AM_CFLAGS += $(WAYLAND_EGL_CFLAGS)
+libEGL_common_la_LIBADD += $(WAYLAND_EGL_LIBS)
 AM_CFLAGS += $(WAYLAND_SERVER_CFLAGS)
 libEGL_common_la_LIBADD += 
$(top_builddir)/src/egl/wayland/wayland-drm/libwayland-drm.la
 libEGL_common_la_LIBADD += $(WAYLAND_SERVER_LIBS)
@@ -114,7 +116,6 @@ AM_CFLAGS += \
-I$(top_builddir)/src/egl/drivers/dri2 \
-I$(top_srcdir)/src/egl/drivers/dri2 \
-I$(top_srcdir)/src/gbm/backends/dri \
-   -I$(top_srcdir)/src/egl/wayland/wayland-egl \
-I$(top_builddir)/src/egl/wayland/wayland-drm \
-I$(top_srcdir)/src/egl/wayland/wayland-drm \
-DDEFAULT_DRIVER_DIR=\"$(DRI_DRIVER_SEARCH_DIR)\" \
diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index 63da21cdf5..11026f9fbf 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -45,12 +45,11 @@
 #include "util/u_vector.h"
 #include "eglglobals.h"
 
+#include 
 #include 
 #include "wayland-drm-client-protocol.h"
 #include "linux-dmabuf-unstable-v1-client-protocol.h"
 
-#include "wayland/wayland-egl/wayland-egl-backend.h"
-
 #ifndef DRM_FORMAT_MOD_INVALID
 #define DRM_FORMAT_MOD_INVALID ((1ULL << 56) - 1)
 #endif
@@ -298,7 +297,7 @@ dri2_wl_create_window_surface(_EGLD

Mesa (master): docs: add note about moving to libwayland-egl in 18.2.0

[Matt Turner]

Module: Mesa
Branch: master
Commit: 735b104707382b6f14f5d49b456c80f5852240af
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=735b104707382b6f14f5d49b456c80f5852240af

Author: Eric Engestrom 
Date:   Tue May 29 15:41:30 2018 +0100

docs: add note about moving to libwayland-egl in 18.2.0

Cc: Emil Velikov 
Cc: Daniel Stone 
Cc: Andres Gomez 
Cc: Dylan Baker 
Reviewed-by: Matt Turner 
Signed-off-by: Eric Engestrom 

---

 docs/relnotes/18.2.0.html | 8 
 1 file changed, 8 insertions(+)

diff --git a/docs/relnotes/18.2.0.html b/docs/relnotes/18.2.0.html
index a3f44a29dc..0db37b620d 100644
--- a/docs/relnotes/18.2.0.html
+++ b/docs/relnotes/18.2.0.html
@@ -30,6 +30,13 @@ Some drivers don't support all the features required in 
OpenGL 4.5.  OpenGL
 Compatibility contexts may report a lower version depending on each driver.
 
 
+
+libwayland-egl is now distributed by libwayland (since 1.15,
+https://lists.freedesktop.org/archives/wayland-devel/2018-April/037767.html;>see
 announcement),
+and has been removed from Mesa in this release. Make sure you're using
+an up-to-date version of libwayland to keep the functionality.
+
+
 
 SHA256 checksums
 
@@ -57,6 +64,7 @@ Note: some of the new features are only available with 
certain drivers.
 
 
 Removed GL_EXT_polygon_offset applications should use glPolygonOffset 
instead.
+Removed libwayland-egl, now part of Wayland
 
 
 

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Mesa (master): configure.ac: rework -latomic check

[Matt Turner]

Module: Mesa
Branch: master
Commit: 54bbe600ec2654bcf43c3378e84d972e0a7ce4b6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=54bbe600ec2654bcf43c3378e84d972e0a7ce4b6

Author: Thomas Petazzoni <thomas.petazz...@bootlin.com>
Date:   Mon May  7 13:34:11 2018 +0200

configure.ac: rework -latomic check

The configure.ac logic added in commit
2ef7f23820a67e958c2252bd81eb0458903ebf33 ("configure: check if
-latomic is needed for __atomic_*") makes the assumption that if a
64-bit atomic intrinsic test program fails to link without -latomic,
it is because we must use -latomic.

Unfortunately, this is not completely correct: libatomic only appeared
in gcc 4.8, and therefore gcc versions before that will not have
libatomic, and therefore don't provide atomic intrinsics for all
architectures. This issue was for example encountered on PowerPC with
a gcc 4.7 toolchain, where the build fails with:

powerpc-ctng_e500v2-linux-gnuspe/bin/ld: cannot find -latomic

This commit aims at fixing that, by not assuming -latomic is
available. The commit re-organizes the atomic intrinsics detection as
follows:

 (1) Test if a program using 64-bit atomic intrinsics links properly,
 without -latomic. If this is the case, we have atomic intrinsics,
 and we're good to go.

 (2) If (1) has failed, then test to link the same program, but this
 time with -latomic in LDFLAGS. If this is the case, then we have
 atomic intrinsics, provided we link with -latomic.

This has been tested in three situations:

 - On x86-64, where atomic instrinsics are all built-in, with no need
   for libatomic. In this case, config.log contains:

   GCC_ATOMIC_BUILTINS_SUPPORTED_FALSE='#'
   GCC_ATOMIC_BUILTINS_SUPPORTED_TRUE=''
   LIBATOMIC_LIBS=''

   This means: atomic intrinsics are available, and we don't need to
   link with libatomic.

 - On NIOS2, where atomic intrinsics are available, but some of them
   (64-bit ones) require using libatomic. In this case, config.log
   contains:

   GCC_ATOMIC_BUILTINS_SUPPORTED_FALSE='#'
   GCC_ATOMIC_BUILTINS_SUPPORTED_TRUE=''
   LIBATOMIC_LIBS='-latomic'

   This means: atomic intrinsics are available, and we need to link
   with libatomic.

 - On PowerPC with an old gcc 4.7 toolchain, where 32-bit atomic
   instrinsics are available, but not 64-bit atomic instrinsics, and
   there is no libatomic. In this case, config.log contains:

   GCC_ATOMIC_BUILTINS_SUPPORTED_FALSE=''
   GCC_ATOMIC_BUILTINS_SUPPORTED_TRUE='#'

   With means that atomic intrinsics are not usable.

Reviewed-by: Matt Turner <matts...@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazz...@bootlin.com>

---

 configure.ac | 44 +++-
 1 file changed, 27 insertions(+), 17 deletions(-)

diff --git a/configure.ac b/configure.ac
index 4bb89607e2..35ade986d1 100644
--- a/configure.ac
+++ b/configure.ac
@@ -434,28 +434,38 @@ fi
 AM_CONDITIONAL([SSE41_SUPPORTED], [test x$SSE41_SUPPORTED = x1])
 AC_SUBST([SSE41_CFLAGS], $SSE41_CFLAGS)
 
-dnl Check for new-style atomic builtins
-AC_COMPILE_IFELSE([AC_LANG_SOURCE([[
+dnl Check for new-style atomic builtins. We first check without linking to
+dnl -latomic.
+AC_MSG_CHECKING(whether __atomic_load_n is supported)
+AC_LINK_IFELSE([AC_LANG_SOURCE([[
+#include 
 int main() {
-int n;
-return __atomic_load_n(, __ATOMIC_ACQUIRE);
-}]])], GCC_ATOMIC_BUILTINS_SUPPORTED=1)
-if test "x$GCC_ATOMIC_BUILTINS_SUPPORTED" = x1; then
-DEFINES="$DEFINES -DUSE_GCC_ATOMIC_BUILTINS"
-dnl On some platforms, new-style atomics need a helper library
-AC_MSG_CHECKING(whether -latomic is needed)
-AC_LINK_IFELSE([AC_LANG_SOURCE([[
-#include 
 struct {
 uint64_t *v;
 } x;
-int main() {
+return (int)__atomic_load_n(x.v, __ATOMIC_ACQUIRE);
+}]])], GCC_ATOMIC_BUILTINS_SUPPORTED=yes, GCC_ATOMIC_BUILTINS_SUPPORTED=no)
+
+dnl If that didn't work, we try linking with -latomic, which is needed on some
+dnl platforms.
+if test "x$GCC_ATOMIC_BUILTINS_SUPPORTED" != xyes; then
+   save_LDFLAGS=$LDFLAGS
+   LDFLAGS="$LDFLAGS -latomic"
+   AC_LINK_IFELSE([AC_LANG_SOURCE([[
+   #include 
+   int main() {
+struct {
+uint64_t *v;
+} x;
 return (int)__atomic_load_n(x.v, __ATOMIC_ACQUIRE);
-}]])], GCC_ATOMIC_BUILTINS_NEED_LIBATOMIC=no, 
GCC_ATOMIC_BUILTINS_NEED_LIBATOMIC=yes)
-AC_MSG_RESULT($GCC_ATOMIC_BUILTINS_NEED_LIBATOMIC)
-if test "x$GCC_ATOMIC_BUILTINS_NEED_LIBATOMIC" = xyes; then
-LIBATOMIC_LIBS="-latomic"
-fi
+   }]])], GCC_ATOMIC_BUILTINS_SUPPORTED=yes LIBATOMIC_LIBS="-latomic",
+  GCC_ATOMIC_BUILTINS_SUPPORTED=no)
+   LDFLAGS=$save_LDFLAGS
+fi
+AC_MSG_RESULT($GCC_ATOMIC_BUILTINS_SUPPORTED)
+
+if test "x$GCC_ATOMIC_BUILTINS_SUPPORTED" = xyes; then
+DEFINES="$DEFINES -DUSE_GCC_ATOMIC_BUILTINS"
 fi
 AC_SUBST([LIBATOMIC_LIBS

Mesa (master): configure.ac: Check for grep with AC_PROG_GREP

[Matt Turner]

Module: Mesa
Branch: master
Commit: 00979402230e659fff57dec612f60987665157fa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=00979402230e659fff57dec612f60987665157fa

Author: Matt Turner <matts...@gmail.com>
Date:   Wed May  9 16:32:12 2018 -0700

configure.ac: Check for grep with AC_PROG_GREP

Perhaps with a new version of autoconf, I began seeing:

| checking the name lister (/usr/bin/nm -B) interface... ./configure: line 
6973: External.*some_variable: command not found
| BSD nm

This is because AC_PROG_NM expands to

...
if $GREP 'External.*some_variable' conftest.out > /dev/null; then
lt_cv_nm_interface="MS dumpbin"
fi
...

I'm not sure if it's a bug in AC_PROG_NM that it doesn't call
AC_PROG_GREP, but it's easy enough for us to do it.

---

 configure.ac | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configure.ac b/configure.ac
index c0fbfe9413..4bb89607e2 100644
--- a/configure.ac
+++ b/configure.ac
@@ -119,6 +119,7 @@ dnl other CC/CXX flags related help
 AC_ARG_VAR([CXX11_CXXFLAGS], [Compiler flag to enable C++11 support (only 
needed if not
   enabled by default and different  from 
-std=c++11)])
 AM_PROG_CC_C_O
+AC_PROG_GREP
 AC_PROG_NM
 AM_PROG_AS
 AX_CHECK_GNU_MAKE

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Mesa (master): gallium/tests: Fix assignment of EXTRA_DIST

[Matt Turner]

Module: Mesa
Branch: master
Commit: 0f959215c340150cb6075f5c2d3ccfc5d109558f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0f959215c340150cb6075f5c2d3ccfc5d109558f

Author: Matt Turner <matts...@gmail.com>
Date:   Wed May  9 16:36:58 2018 -0700

gallium/tests: Fix assignment of EXTRA_DIST

Fixes: 6754c2e83d79 ("autotools: Include new meson files")

---

 src/gallium/tests/unit/Makefile.am | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/gallium/tests/unit/Makefile.am 
b/src/gallium/tests/unit/Makefile.am
index f1192af17a..74d125fe44 100644
--- a/src/gallium/tests/unit/Makefile.am
+++ b/src/gallium/tests/unit/Makefile.am
@@ -2,7 +2,7 @@
 
 include $(top_srcdir)/src/gallium/Automake.inc
 
-EXTRA_DIST = SConscript
+EXTRA_DIST = SConscript meson.build
 
 AM_CFLAGS = \
$(GALLIUM_CFLAGS)
@@ -32,5 +32,3 @@ u_format_test_SOURCES = u_format_test.c
 u_format_compatible_test_SOURCES = u_format_compatible_test.c
 
 translate_test_SOURCES = translate_test.c
-
-EXTRA_DIST = meson.build

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Mesa (master): src/intel/Makefile.vulkan.am: add missing MKDIR_GEN

[Matt Turner]

Module: Mesa
Branch: master
Commit: 1755654d9f533240dc19954b0dbccaf74e645265
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1755654d9f533240dc19954b0dbccaf74e645265

Author: Ross Burton <ross.bur...@intel.com>
Date:   Wed May  9 21:48:43 2018 +0100

src/intel/Makefile.vulkan.am: add missing MKDIR_GEN

Out of tree builds can try to write into a directory that doesn't exist yet:

| Traceback (most recent call last):
|   File "../../../mesa-18.0.2/src/intel/vulkan/anv_icd.py", line 46, in 

| with open(args.out, 'w') as f:
| IOError: [Errno 2] No such file or directory: 'vulkan/intel_icd.x86_64.json'
| Makefile:4882: recipe for target 'vulkan/intel_icd.x86_64.json' failed

Add missing MKDIR_GEN calls to solve this.

Cc: <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Matt Turner <matts...@gmail.com>

---

 src/intel/Makefile.vulkan.am | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/intel/Makefile.vulkan.am b/src/intel/Makefile.vulkan.am
index 0bcbf0419c..4125cb205a 100644
--- a/src/intel/Makefile.vulkan.am
+++ b/src/intel/Makefile.vulkan.am
@@ -64,10 +64,12 @@ EXTRA_DIST += \
vulkan/TODO
 
 vulkan/dev_icd.json : vulkan/anv_extensions.py vulkan/anv_icd.py
+   $(MKDIR_GEN)
$(AM_V_GEN)$(PYTHON2) $(srcdir)/vulkan/anv_icd.py \
--lib-path="${abs_top_builddir}/${LIB_DIR}" --out $@
 
 vulkan/intel_icd.@host_cpu@.json : vulkan/anv_extensions.py vulkan/anv_icd.py
+   $(MKDIR_GEN)
$(AM_V_GEN)$(PYTHON2) $(srcdir)/vulkan/anv_icd.py \
--lib-path="${libdir}" --out $@
 

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Mesa (master): nir: Transform discard_if(true) into discard

[Matt Turner]

Module: Mesa
Branch: master
Commit: ed5af9437344f932f8cbebfa776f873d16a8aae1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed5af9437344f932f8cbebfa776f873d16a8aae1

Author: Matt Turner <matts...@gmail.com>
Date:   Thu Apr 26 21:25:42 2018 -0700

nir: Transform discard_if(true) into discard

Noticed while reviewing Tim Arceri's NIR inlining series.

Without his series:

instructions in affected programs: 16 -> 14 (-12.50%)
helped: 2

With his series:

instructions in affected programs: 196 -> 174 (-11.22%)
helped: 22

Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>

---

 src/compiler/nir/nir_opt_constant_folding.c | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/src/compiler/nir/nir_opt_constant_folding.c 
b/src/compiler/nir/nir_opt_constant_folding.c
index a848b14587..fe34f4ade8 100644
--- a/src/compiler/nir/nir_opt_constant_folding.c
+++ b/src/compiler/nir/nir_opt_constant_folding.c
@@ -167,7 +167,22 @@ constant_fold_intrinsic_instr(nir_intrinsic_instr *instr)
 
if (instr->intrinsic == nir_intrinsic_discard_if) {
   nir_const_value *src_val = nir_src_as_const_value(instr->src[0]);
-  if (src_val && src_val->u32[0] == 0) {
+  if (src_val && src_val->u32[0] == NIR_FALSE) {
+ nir_instr_remove(>instr);
+ progress = true;
+  } else if (src_val && src_val->u32[0] == NIR_TRUE) {
+ /* This method of getting a nir_shader * from a nir_instr is
+  * admittedly gross, but given the rarity of hitting this case I think
+  * it's preferable to plumbing an otherwise unused nir_shader *
+  * parameter through four functions to get here.
+  */
+ nir_cf_node *cf_node = >instr.block->cf_node;
+ nir_function_impl *impl = nir_cf_node_get_function(cf_node);
+ nir_shader *shader = impl->function->shader;
+
+ nir_intrinsic_instr *discard =
+nir_intrinsic_instr_create(shader, nir_intrinsic_discard);
+ nir_instr_insert_before(>instr, >instr);
  nir_instr_remove(>instr);
  progress = true;
   }

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Mesa (master): configure.ac/meson.build: Fix -latomic test

[Matt Turner]

Module: Mesa
Branch: master
Commit: 54ba73ef102f7b9085922686bb31719539e0dc3c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=54ba73ef102f7b9085922686bb31719539e0dc3c

Author: Nicolas Boichat <drink...@chromium.org>
Date:   Thu Apr  5 09:33:09 2018 +0800

configure.ac/meson.build: Fix -latomic test

When compiling with LLVM 6.0 on x86 (32-bit) for Android, the test
fails to detect that -latomic is actually required, as the atomic
call is inlined.

In the code itself (src/util/disk_cache.c), we see this pattern:
p_atomic_add(cache->size, - (uint64_t)size);
where cache->size is an uint64_t *, and results in the following
link time error without -latomic:
src/util/disk_cache.c:628: error: undefined reference to '__atomic_fetch_add_8'

Fix the configure/meson test to replicate this pattern, which then
correctly realizes the need for -latomic.

Reviewed-by: Matt Turner <matts...@gmail.com>
Signed-off-by: Nicolas Boichat <drink...@chromium.org>

---

 configure.ac | 6 --
 meson.build  | 6 --
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/configure.ac b/configure.ac
index f1fbdcc6c7..c0fbfe9413 100644
--- a/configure.ac
+++ b/configure.ac
@@ -445,9 +445,11 @@ if test "x$GCC_ATOMIC_BUILTINS_SUPPORTED" = x1; then
 AC_MSG_CHECKING(whether -latomic is needed)
 AC_LINK_IFELSE([AC_LANG_SOURCE([[
 #include 
-uint64_t v;
+struct {
+uint64_t *v;
+} x;
 int main() {
-return (int)__atomic_load_n(, __ATOMIC_ACQUIRE);
+return (int)__atomic_load_n(x.v, __ATOMIC_ACQUIRE);
 }]])], GCC_ATOMIC_BUILTINS_NEED_LIBATOMIC=no, 
GCC_ATOMIC_BUILTINS_NEED_LIBATOMIC=yes)
 AC_MSG_RESULT($GCC_ATOMIC_BUILTINS_NEED_LIBATOMIC)
 if test "x$GCC_ATOMIC_BUILTINS_NEED_LIBATOMIC" = xyes; then
diff --git a/meson.build b/meson.build
index 6e61766809..e52b4a5109 100644
--- a/meson.build
+++ b/meson.build
@@ -849,8 +849,10 @@ if cc.compiles('int main() { int n; return 
__atomic_load_n(, __ATOMIC_ACQUIRE)
   # as ARM.
   if not cc.links('''#include 
  int main() {
-   uint64_t n;
-   return (int)__atomic_load_n(, __ATOMIC_ACQUIRE);
+   struct {
+ uint64_t *v;
+   } x;
+   return (int)__atomic_load_n(x.v, __ATOMIC_ACQUIRE);
  }''',
   name : 'GCC atomic builtins required -latomic')
 dep_atomic = cc.find_library('atomic')

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Mesa (master): build: Fix up nir_intrinsics.Plo

[Matt Turner]

Module: Mesa
Branch: master
Commit: 3e6326deb978a26169481df15f5ba99c2754fa50
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e6326deb978a26169481df15f5ba99c2754fa50

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Mar 28 11:07:36 2018 -0700

build: Fix up nir_intrinsics.Plo

nir_intrinsics.c existed as a static file until commit 76dfed8ae2d5 began
generating it as part of the build process. autotools is incapable of
coping, and so a build-tree from before this commit would then fail with
it:

[4]: *** No rule to make target 
'../../../mesa/src/compiler/nir/nir_intrinsics.c', needed by 
'nir/nir_intrinsics.lo'.  Stop.

Add a few lines to configure.ac to update the broken build files.

Fixes: 76dfed8ae2d5 ("nir: mako all the intrinsics")

---

 configure.ac | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/configure.ac b/configure.ac
index 99805e0f2b..e874f8ebfb 100644
--- a/configure.ac
+++ b/configure.ac
@@ -3127,6 +3127,9 @@ $SED -i -e 's/brw_blorp.cpp/brw_blorp.c/' 
src/mesa/drivers/dri/i965/.deps/brw_bl
 rm -f src/compiler/spirv/spirv_info.lo
 echo "# dummy" > src/compiler/spirv/.deps/spirv_info.Plo
 
+rm -f src/compiler/nir/.deps/nir_intrinsics.Plo
+echo "# dummy" > src/compiler/nir/.deps/nir_intrinsics.Plo
+
 dnl
 dnl Output some configuration info for the user
 dnl

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Mesa (master): intel/common/icl: Disable hiz surface sampling

[Matt Turner]

Module: Mesa
Branch: master
Commit: f05e0d9c2a5f5a26e0678b40fff17086098dc405
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f05e0d9c2a5f5a26e0678b40fff17086098dc405

Author: Anuj Phogat 
Date:   Fri Feb 16 13:44:10 2018 -0800

intel/common/icl: Disable hiz surface sampling

On gen11+ AUX_HIZ is not a supported value for surfaces being
sampled by the 3D sampler.

Reviewed-by: Rafael Antognolli 
Reviewed-by: Kenneth Graunke 

---

 src/intel/dev/gen_device_info.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
index 3365bdd4dd..9e684b78a0 100644
--- a/src/intel/dev/gen_device_info.c
+++ b/src/intel/dev/gen_device_info.c
@@ -823,6 +823,7 @@ static const struct gen_device_info gen_device_info_cnl_5x8 
= {
GEN11_HW_INFO, \
.has_64bit_types = false,  \
.has_integer_dword_mul = false,\
+   .has_sample_with_hiz = false,  \
.gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
.num_subslices = _subslices
 

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Mesa (master): intel: Disable fast color clear on icl

[Matt Turner]

Module: Mesa
Branch: master
Commit: 1065acfb692fa8c62459ba258191eefec445ac8c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1065acfb692fa8c62459ba258191eefec445ac8c

Author: Anuj Phogat <anuj.pho...@gmail.com>
Date:   Tue Nov 21 13:46:25 2017 -0800

intel: Disable fast color clear on icl

Disabling fast color clear makes fbo-clearmipmap test render correct
texture in base miplevel. Fast color clear is anyways disabled for
non-base miplevels.

Acked-by: Matt Turner <matts...@gmail.com>
Acked-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/mesa/drivers/dri/i965/brw_blorp.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 72578b6ea5..a9c6dc4d50 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1228,6 +1228,11 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
   }
}
 
+   /* FINISHME: Debug and enable fast clears */
+   const struct gen_device_info *devinfo = >screen->devinfo;
+   if (devinfo->gen >= 11)
+  can_fast_clear = false;
+
if (can_fast_clear) {
   const enum isl_aux_state aux_state =
  intel_miptree_get_aux_state(irb->mt, irb->mt_level, irb->mt_layer);

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Mesa (master): intel: Add a Ice Lake PCI IDs

[Matt Turner]

Module: Mesa
Branch: master
Commit: ad7ed86bf7831d03c1c6115c37e11a47745e5a5a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad7ed86bf7831d03c1c6115c37e11a47745e5a5a

Author: Anuj Phogat 
Date:   Tue Mar 14 14:43:34 2017 -0700

intel: Add a Ice Lake PCI IDs

Reviewed-by: Rafael Antognolli 

---

 include/pci_ids/i965_pci_ids.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index feb9c582b1..8716d758f0 100644
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -196,3 +196,11 @@ CHIPSET(0x5A50, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 
5x8 GT2)")
 CHIPSET(0x5A51, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
 CHIPSET(0x5A52, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
 CHIPSET(0x5A54, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
+CHIPSET(0x8A50, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
+CHIPSET(0x8A51, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
+CHIPSET(0x8A52, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
+CHIPSET(0x8A5A, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
+CHIPSET(0x8A5B, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
+CHIPSET(0x8A5C, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
+CHIPSET(0x8A5D, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
+CHIPSET(0x8A71, icl_1x8, "Intel(R) HD Graphics (Ice Lake 1x8 GT0.5)")

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Mesa (master): intel/tools/aubinator: Drop platform list from print_help()

[Matt Turner]

Module: Mesa
Branch: master
Commit: f56693af4b2039ff389d74c181e107e48950b893
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f56693af4b2039ff389d74c181e107e48950b893

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Mar 21 14:05:09 2018 -0700

intel/tools/aubinator: Drop platform list from print_help()

We all know the platform names, and I don't want to update this list
continually.

Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/tools/aubinator.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index 8029dc1215..2a72efa8a2 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -548,7 +548,7 @@ print_help(const char *progname, FILE *file)
"Decode aub file contents from either FILE or the standard 
input.\n\n"
"A valid --gen option must be provided.\n\n"
"  --help  display this help and exit\n"
-   "  --gen=platform  decode for given platform (ivb, byt, hsw, 
bdw, chv, skl, kbl, bxt or cnl)\n"
+   "  --gen=platform  decode for given platform (3 letter platform 
name)\n"
"  --headers   decode only command headers\n"
"  --color[=WHEN]  colorize the output; WHEN can be 'auto' 
(default\n"
"if omitted), 'always', or 'never'\n"

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Mesa (master): intel/compiler/icl: Clear "null render target" bit in extended message descriptor

[Matt Turner]

Module: Mesa
Branch: master
Commit: d2eecf0b0b24d203d0f171807681dffd830d54de
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2eecf0b0b24d203d0f171807681dffd830d54de

Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date:   Mon Dec 18 11:29:14 2017 -0800

intel/compiler/icl: Clear "null render target" bit in extended message 
descriptor

Otherwise all our render target writes go no where.

Reviewed-by: Matt Turner <matts...@gmail.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/brw_eu_emit.c | 3 +++
 src/intel/compiler/brw_inst.h| 3 +++
 2 files changed, 6 insertions(+)

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index f039af56d0..ee5a048bca 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -536,6 +536,9 @@ brw_set_dp_write_message(struct brw_codegen *p,
if (devinfo->gen < 7) {
   brw_inst_set_dp_write_commit(devinfo, insn, send_commit_msg);
}
+
+   if (devinfo->gen >= 11)
+  brw_inst_set_null_rt(devinfo, insn, false);
 }
 
 void
diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h
index e6998973b6..8663c1b7f5 100644
--- a/src/intel/compiler/brw_inst.h
+++ b/src/intel/compiler/brw_inst.h
@@ -505,6 +505,9 @@ FF(sfid,
/* 6:   */  27,  24,
/* 7:   */  27,  24,
/* 8:   */  27,  24)
+FF(null_rt,
+   /* 4-7: */ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+   /* 8:   */ 80, 80) /* actually only Gen11+ */
 FC(base_mrf,   27,  24, devinfo->gen < 6);
 /** @} */
 

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Mesa (master): intel/common/icl: Add L3 config

[Matt Turner]

Module: Mesa
Branch: master
Commit: 370af9dcc0c192d2592d22cd6a901c9ee6643b8c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=370af9dcc0c192d2592d22cd6a901c9ee6643b8c

Author: Anuj Phogat 
Date:   Thu Jul 20 16:23:24 2017 -0700

intel/common/icl: Add L3 config

ICL uses the same L3 configs as CNL, just leaving the SLM configs out.

Reviewed-by: Kenneth Graunke 

---

 src/intel/common/gen_l3_config.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index 7d58ad8d7c..b977c6ab13 100644
--- a/src/intel/common/gen_l3_config.c
+++ b/src/intel/common/gen_l3_config.c
@@ -133,6 +133,21 @@ static const struct gen_l3_config cnl_l3_configs[] = {
 };
 
 /**
+ * ICL validated L3 configurations.  \sa icl_l3_configs.
+ */
+static const struct gen_l3_config icl_l3_configs[] = {
+   /* SLM URB ALL DC  RO  IS   C   T */
+   {{  0, 64, 64,  0,  0,  0,  0,  0 }},
+   {{  0, 64,  0, 16, 48,  0,  0,  0 }},
+   {{  0, 48,  0, 16, 64,  0,  0,  0 }},
+   {{  0, 32,  0,  0, 96,  0,  0,  0 }},
+   {{  0, 32, 96,  0,  0,  0,  0,  0 }},
+   {{  0, 32,  0, 16, 80,  0,  0,  0 }},
+   {{  0 }}
+};
+
+
+/**
  * Return a zero-terminated array of validated L3 configurations for the
  * specified device.
  */
@@ -154,6 +169,9 @@ get_l3_configs(const struct gen_device_info *devinfo)
case 10:
   return cnl_l3_configs;
 
+   case 11:
+  return icl_l3_configs;
+
default:
   unreachable("Not implemented");
}

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Mesa (master): intel/compiler/icl: Update the assert in brw_stage_has_packed_dispatch()

[Matt Turner]

Module: Mesa
Branch: master
Commit: 1484876ef78219e8014278c2c43b8d90e6260b11
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1484876ef78219e8014278c2c43b8d90e6260b11

Author: Anuj Phogat <anuj.pho...@gmail.com>
Date:   Thu Jul 20 16:20:33 2017 -0700

intel/compiler/icl: Update the assert in brw_stage_has_packed_dispatch()

Rafael ran piglit with the test code enabled and saw no additional GPU
hangs.

Reviewed-by: Matt Turner <matts...@gmail.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/brw_compiler.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_compiler.h 
b/src/intel/compiler/brw_compiler.h
index 0e27c89820..d3ae6499b9 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -1294,7 +1294,7 @@ brw_stage_has_packed_dispatch(MAYBE_UNUSED const struct 
gen_device_info *devinfo
 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
 * the NIR front-end before changing this assertion.
 */
-   assert(devinfo->gen <= 10);
+   assert(devinfo->gen <= 11);
 
switch (stage) {
case MESA_SHADER_FRAGMENT: {

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Mesa (master): intel/compiler: Readd ICL to test_eu_validate.cpp

[Matt Turner]

Module: Mesa
Branch: master
Commit: 724586a2665d2109a581913822f60aa768573e39
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=724586a2665d2109a581913822f60aa768573e39

Author: Matt Turner <matts...@gmail.com>
Date:   Fri Mar 16 11:00:50 2018 -0700

intel/compiler: Readd ICL to test_eu_validate.cpp

Now that the PCI IDs are upstream, this can be readded.

---

 src/intel/compiler/test_eu_validate.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/compiler/test_eu_validate.cpp 
b/src/intel/compiler/test_eu_validate.cpp
index 303773d6d7..b132b87a1a 100644
--- a/src/intel/compiler/test_eu_validate.cpp
+++ b/src/intel/compiler/test_eu_validate.cpp
@@ -43,6 +43,7 @@ static const struct gen_info {
{ "glk", },
{ "cfl", },
{ "cnl", },
+   { "icl", },
 };
 
 class validation_test: public ::testing::TestWithParam {

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Mesa (master): intel/compiler: Skip 64-bit type tests when types not available

[Matt Turner]

Module: Mesa
Branch: master
Commit: 65b060d9cbe932d6749c472b754aa7971b4129e8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=65b060d9cbe932d6749c472b754aa7971b4129e8

Author: Matt Turner <matts...@gmail.com>
Date:   Fri Mar 16 11:15:26 2018 -0700

intel/compiler: Skip 64-bit type tests when types not available

Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/test_eu_validate.cpp | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/src/intel/compiler/test_eu_validate.cpp 
b/src/intel/compiler/test_eu_validate.cpp
index 161db994b2..303773d6d7 100644
--- a/src/intel/compiler/test_eu_validate.cpp
+++ b/src/intel/compiler/test_eu_validate.cpp
@@ -1066,6 +1066,10 @@ TEST_P(validation_test, 
qword_low_power_align1_regioning_restrictions)
   return;
 
for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
+  if (!devinfo.has_64bit_types &&
+  (type_sz(inst[i].dst_type) == 8 || type_sz(inst[i].src_type) == 8))
+ continue;
+
   if (inst[i].opcode == BRW_OPCODE_MOV) {
  brw_MOV(p, retype(g0, inst[i].dst_type),
 retype(g0, inst[i].src_type));
@@ -1186,6 +1190,10 @@ TEST_P(validation_test, 
qword_low_power_no_indirect_addressing)
   return;
 
for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
+  if (!devinfo.has_64bit_types &&
+  (type_sz(inst[i].dst_type) == 8 || type_sz(inst[i].src_type) == 8))
+ continue;
+
   if (inst[i].opcode == BRW_OPCODE_MOV) {
  brw_MOV(p, retype(g0, inst[i].dst_type),
 retype(g0, inst[i].src_type));
@@ -1322,6 +1330,10 @@ TEST_P(validation_test, qword_low_power_no_64bit_arf)
   return;
 
for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
+  if (!devinfo.has_64bit_types &&
+  (type_sz(inst[i].dst_type) == 8 || type_sz(inst[i].src_type) == 8))
+ continue;
+
   if (inst[i].opcode == BRW_OPCODE_MOV) {
  brw_MOV(p, retype(inst[i].dst, inst[i].dst_type),
 retype(inst[i].src, inst[i].src_type));
@@ -1350,6 +1362,9 @@ TEST_P(validation_test, qword_low_power_no_64bit_arf)
   clear_instructions(p);
}
 
+   if (!devinfo.has_64bit_types)
+  return;
+
/* MAC implicitly reads the accumulator */
brw_MAC(p, retype(g0, BRW_REGISTER_TYPE_DF),
   retype(stride(g0, 4, 4, 1), BRW_REGISTER_TYPE_DF),
@@ -1520,6 +1535,10 @@ TEST_P(validation_test, qword_low_power_no_depctrl)
   return;
 
for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {
+  if (!devinfo.has_64bit_types &&
+  (type_sz(inst[i].dst_type) == 8 || type_sz(inst[i].src_type) == 8))
+ continue;
+
   if (inst[i].opcode == BRW_OPCODE_MOV) {
  brw_MOV(p, retype(g0, inst[i].dst_type),
 retype(g0, inst[i].src_type));

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Mesa (master): intel: Add cfl to gen_device_name_to_pci_device_id()

[Matt Turner]

Module: Mesa
Branch: master
Commit: 54db78b196d883a878301651af3313fd50c39fd5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=54db78b196d883a878301651af3313fd50c39fd5

Author: Matt Turner <matts...@gmail.com>
Date:   Fri Mar 16 10:50:51 2018 -0700

intel: Add cfl to gen_device_name_to_pci_device_id()

Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>

---

 src/intel/dev/gen_device_info.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
index 1773009d33..3365bdd4dd 100644
--- a/src/intel/dev/gen_device_info.c
+++ b/src/intel/dev/gen_device_info.c
@@ -55,6 +55,7 @@ gen_device_name_to_pci_device_id(const char *name)
   { "bxt", 0x5A85 },
   { "kbl", 0x5912 },
   { "glk", 0x3185 },
+  { "cfl", 0x3E9B },
   { "cnl", 0x5a52 },
   { "icl", 0x8a52 },
};

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Mesa (master): intel/compiler: Use gen_get_device_info() in test_eu_validate

[Matt Turner]

Module: Mesa
Branch: master
Commit: f3833f1ca79960a944760914b8a208c4e6bc12e7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f3833f1ca79960a944760914b8a208c4e6bc12e7

Author: Matt Turner <matts...@gmail.com>
Date:   Fri Mar 16 10:52:55 2018 -0700

intel/compiler: Use gen_get_device_info() in test_eu_validate

Previously the unit test filled out a minimal devinfo struct. A previous
patch caused the test to begin assert failing because the devinfo was
not complete. Avoid this by using the real mechanism to create devinfo.

Note that we have to drop icl from the table, since we now rely on the
name -> PCI ID translation done by gen_device_name_to_pci_device_id(),
and ICL's PCI IDs are not upstream yet.

Fixes: f89e735719a6 ("intel/compiler: Check for unsupported register sizes.")
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>

---

 src/intel/Makefile.compiler.am  |  1 +
 src/intel/compiler/meson.build  |  2 +-
 src/intel/compiler/test_eu_validate.cpp | 55 ++---
 3 files changed, 19 insertions(+), 39 deletions(-)

diff --git a/src/intel/Makefile.compiler.am b/src/intel/Makefile.compiler.am
index 45e7a6ccce..af30a58a1d 100644
--- a/src/intel/Makefile.compiler.am
+++ b/src/intel/Makefile.compiler.am
@@ -48,6 +48,7 @@ TEST_LIBS = \
$(top_builddir)/src/gtest/libgtest.la \
compiler/libintel_compiler.la \
common/libintel_common.la \
+   dev/libintel_dev.la \
$(top_builddir)/src/compiler/nir/libnir.la \
$(top_builddir)/src/util/libmesautil.la \
$(top_builddir)/src/intel/isl/libisl.la \
diff --git a/src/intel/compiler/meson.build b/src/intel/compiler/meson.build
index 602206c725..72b7a6796c 100644
--- a/src/intel/compiler/meson.build
+++ b/src/intel/compiler/meson.build
@@ -152,7 +152,7 @@ if with_tests
 'test_@0@.cpp'.format(t),
 include_directories : [inc_common, inc_intel],
 link_with : [
-  libintel_compiler, libintel_common, libmesa_util, libisl,
+  libintel_compiler, libintel_common, libintel_dev, libmesa_util, 
libisl,
 ],
 dependencies : [dep_thread, dep_dl, idep_gtest, idep_nir],
   )
diff --git a/src/intel/compiler/test_eu_validate.cpp 
b/src/intel/compiler/test_eu_validate.cpp
index d987311ef8..161db994b2 100644
--- a/src/intel/compiler/test_eu_validate.cpp
+++ b/src/intel/compiler/test_eu_validate.cpp
@@ -25,38 +25,24 @@
 #include "brw_eu.h"
 #include "util/ralloc.h"
 
-enum subgen {
-   IS_G45 = 1,
-   IS_BYT,
-   IS_HSW,
-   IS_CHV,
-   IS_BXT,
-   IS_KBL,
-   IS_GLK,
-   IS_CFL,
-};
-
 static const struct gen_info {
const char *name;
-   int gen;
-   enum subgen subgen;
 } gens[] = {
-   { "brw", 4 },
-   { "g45", 4, IS_G45 },
-   { "ilk", 5 },
-   { "snb", 6 },
-   { "ivb", 7 },
-   { "byt", 7, IS_BYT },
-   { "hsw", 7, IS_HSW },
-   { "bdw", 8 },
-   { "chv", 8, IS_CHV },
-   { "skl", 9 },
-   { "bxt", 9, IS_BXT },
-   { "kbl", 9, IS_KBL },
-   { "glk", 9, IS_GLK },
-   { "cfl", 9, IS_CFL },
-   { "cnl", 10 },
-   { "icl", 11 },
+   { "brw", },
+   { "g4x", },
+   { "ilk", },
+   { "snb", },
+   { "ivb", },
+   { "byt", },
+   { "hsw", },
+   { "bdw", },
+   { "chv", },
+   { "skl", },
+   { "bxt", },
+   { "kbl", },
+   { "glk", },
+   { "cfl", },
+   { "cnl", },
 };
 
 class validation_test: public ::testing::TestWithParam {
@@ -84,16 +70,9 @@ validation_test::~validation_test()
 void validation_test::SetUp()
 {
struct gen_info info = GetParam();
+   int devid = gen_device_name_to_pci_device_id(info.name);
 
-   devinfo.gen   = info.gen;
-   devinfo.is_g4x= info.subgen == IS_G45;
-   devinfo.is_baytrail   = info.subgen == IS_BYT;
-   devinfo.is_haswell= info.subgen == IS_HSW;
-   devinfo.is_cherryview = info.subgen == IS_CHV;
-   devinfo.is_broxton= info.subgen == IS_BXT;
-   devinfo.is_kabylake   = info.subgen == IS_KBL;
-   devinfo.is_geminilake = info.subgen == IS_GLK;
-   devinfo.is_coffeelake = info.subgen == IS_CFL;
+   gen_get_device_info(devid, );
 
brw_init_codegen(, p, p);
 }

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Mesa (master): intel/compiler: Re-add .vs_inputs_dual_locations = true

[Matt Turner]

Module: Mesa
Branch: master
Commit: debaa822ef12bc9006dcf95ab76ac8e3432bd9a7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=debaa822ef12bc9006dcf95ab76ac8e3432bd9a7

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Feb 28 13:25:21 2018 -0800

intel/compiler: Re-add .vs_inputs_dual_locations = true

Looks like a rebase mistake.

Fixes: 89fe5190a256 ("intel/compiler: Lower flrp32 on Gen11+")

---

 src/intel/compiler/brw_compiler.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/compiler/brw_compiler.c 
b/src/intel/compiler/brw_compiler.c
index 34be3b705f..9340317492 100644
--- a/src/intel/compiler/brw_compiler.c
+++ b/src/intel/compiler/brw_compiler.c
@@ -57,6 +57,7 @@
.lower_unpack_snorm_4x8 = true,\
.lower_unpack_unorm_2x16 = true,   \
.lower_unpack_unorm_4x8 = true,\
+   .vs_inputs_dual_locations = true,  \
.max_unroll_iterations = 32
 
 static const struct nir_shader_compiler_options scalar_nir_options = {

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Mesa (master): intel/compiler: Add ICL to test_eu_validate.cpp

[Matt Turner]

Module: Mesa
Branch: master
Commit: 6f00bf519d6f13eb58e7495a41b8f8b055782832
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f00bf519d6f13eb58e7495a41b8f8b055782832

Author: Matt Turner <matts...@gmail.com>
Date:   Mon Jan 29 15:52:39 2018 -0800

intel/compiler: Add ICL to test_eu_validate.cpp

With the Align16 tests now disabled, we can run the rest of the tests in
ICL mode (and see them pass!)

Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/test_eu_validate.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/compiler/test_eu_validate.cpp 
b/src/intel/compiler/test_eu_validate.cpp
index f6c2b35625..d987311ef8 100644
--- a/src/intel/compiler/test_eu_validate.cpp
+++ b/src/intel/compiler/test_eu_validate.cpp
@@ -56,6 +56,7 @@ static const struct gen_info {
{ "glk", 9, IS_GLK },
{ "cfl", 9, IS_CFL },
{ "cnl", 10 },
+   { "icl", 11 },
 };
 
 class validation_test: public ::testing::TestWithParam {

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Mesa (master): i965: Warn about preliminary support for Gen11

[Matt Turner]

Module: Mesa
Branch: master
Commit: 35bfe2099564b6655563d920a21d13392b78c43e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=35bfe2099564b6655563d920a21d13392b78c43e

Author: Matt Turner <matts...@gmail.com>
Date:   Mon Feb 26 14:25:17 2018 -0800

i965: Warn about preliminary support for Gen11

Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/mesa/drivers/dri/i965/brw_context.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index b9c3fa27bf..8ab9063d21 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1011,6 +1011,13 @@ brwCreateContext(gl_api api,
   return false;
}
 
+   if (devinfo->gen == 11) {
+  fprintf(stderr,
+  "WARNING: i965 does not fully support Gen11 yet.\n"
+  "Instability or lower performance might occur.\n");
+
+   }
+
brw_init_state(brw);
 
intelInitExtensions(ctx);

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Mesa (master): intel/compiler/fs: Implement ddy without using align16 for Gen11+

[Matt Turner]

Module: Mesa
Branch: master
Commit: 2134ea380033d5d1f3c5760b8bdb1da7aadd9842
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2134ea380033d5d1f3c5760b8bdb1da7aadd9842

Author: Matt Turner <matts...@gmail.com>
Date:   Thu Jun 15 17:29:16 2017 -0700

intel/compiler/fs: Implement ddy without using align16 for Gen11+

Align16 is no more. We previously generated an align16 ADD instruction
to calculate DDY:

   add(16) g25<1>F  -g23<4>.xyxyF   g23<4>.zwzwF   { align16 1H };

Without align16, we now implement it as:

   add(4) g25<1>F   -g23<0,2,1>Fg23.2<0,2,1>F  { align1 1N };
   add(4) g25.4<1>F -g23.4<0,2,1>F  g23.6<0,2,1>F  { align1 1N };
   add(4) g26<1>F   -g24<0,2,1>Fg24.2<0,2,1>F  { align1 1N };
   add(4) g26.4<1>F -g24.4<0,2,1>F  g24.6<0,2,1>F  { align1 1N };

where only the first two instructions are needed in SIMD8 mode.

Note: an earlier version of the patch implemented this in two
instructions in SIMD16:

   add(8) g25<2>F   -g23<4,2,0>Fg23.2<4,2,0>F  { align1 1N };
   add(8) g25.1<2>F -g23.1<4,2,0>F  g23.3<4,2,0>F  { align1 1N };

but I realized that the channel enable bits will not be correct. If we
knew we were under uniform control flow, we could emit only those two
instructions however.

Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/brw_fs_generator.cpp | 46 +++--
 1 file changed, 38 insertions(+), 8 deletions(-)

diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index e6fb7c92d4..0dc0a695e4 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1187,15 +1187,45 @@ fs_generator::generate_ddy(const fs_inst *inst,
 {
if (inst->opcode == FS_OPCODE_DDY_FINE) {
   /* produce accurate derivatives */
-  struct brw_reg src0 = stride(src, 4, 4, 1);
-  struct brw_reg src1 = stride(src, 4, 4, 1);
-  src0.swizzle = BRW_SWIZZLE_XYXY;
-  src1.swizzle = BRW_SWIZZLE_ZWZW;
+  if (devinfo->gen >= 11) {
+ src = stride(src, 0, 2, 1);
+ struct brw_reg src_0  = byte_offset(src,  0 * sizeof(float));
+ struct brw_reg src_2  = byte_offset(src,  2 * sizeof(float));
+ struct brw_reg src_4  = byte_offset(src,  4 * sizeof(float));
+ struct brw_reg src_6  = byte_offset(src,  6 * sizeof(float));
+ struct brw_reg src_8  = byte_offset(src,  8 * sizeof(float));
+ struct brw_reg src_10 = byte_offset(src, 10 * sizeof(float));
+ struct brw_reg src_12 = byte_offset(src, 12 * sizeof(float));
+ struct brw_reg src_14 = byte_offset(src, 14 * sizeof(float));
+
+ struct brw_reg dst_0  = byte_offset(dst,  0 * sizeof(float));
+ struct brw_reg dst_4  = byte_offset(dst,  4 * sizeof(float));
+ struct brw_reg dst_8  = byte_offset(dst,  8 * sizeof(float));
+ struct brw_reg dst_12 = byte_offset(dst, 12 * sizeof(float));
 
-  brw_push_insn_state(p);
-  brw_set_default_access_mode(p, BRW_ALIGN_16);
-  brw_ADD(p, dst, negate(src0), src1);
-  brw_pop_insn_state(p);
+ brw_push_insn_state(p);
+ brw_set_default_exec_size(p, BRW_EXECUTE_4);
+
+ brw_ADD(p, dst_0, negate(src_0), src_2);
+ brw_ADD(p, dst_4, negate(src_4), src_6);
+
+ if (inst->exec_size == 16) {
+brw_ADD(p, dst_8,  negate(src_8),  src_10);
+brw_ADD(p, dst_12, negate(src_12), src_14);
+ }
+
+ brw_pop_insn_state(p);
+  } else {
+ struct brw_reg src0 = stride(src, 4, 4, 1);
+ struct brw_reg src1 = stride(src, 4, 4, 1);
+ src0.swizzle = BRW_SWIZZLE_XYXY;
+ src1.swizzle = BRW_SWIZZLE_ZWZW;
+
+ brw_push_insn_state(p);
+ brw_set_default_access_mode(p, BRW_ALIGN_16);
+ brw_ADD(p, dst, negate(src0), src1);
+ brw_pop_insn_state(p);
+  }
} else {
   /* replicate the derivative at the top-left pixel to other pixels */
   struct brw_reg src0 = stride(src, 4, 4, 0);

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Mesa (master): intel: Disable 64-bit extensions on platforms without 64-bit types

[Matt Turner]

Module: Mesa
Branch: master
Commit: bb428454a9d70e5f5984269e6c4a7f5d6e2871d9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb428454a9d70e5f5984269e6c4a7f5d6e2871d9

Author: Matt Turner <matts...@gmail.com>
Date:   Mon Dec 11 13:59:13 2017 -0800

intel: Disable 64-bit extensions on platforms without 64-bit types

Gen11 does not support DF, Q, UQ types in hardware. As a result, we have
to disable some GL extensions until they can be reimplemented.

Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Iago Toral Quiroga <ito...@igalia.com>

---

 src/intel/common/gen_device_info.c   | 3 +++
 src/intel/common/gen_device_info.h   | 1 +
 src/mesa/drivers/dri/i965/intel_extensions.c | 9 +
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/intel/common/gen_device_info.c 
b/src/intel/common/gen_device_info.c
index 11a4480ebf..7bed806b36 100644
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -197,6 +197,7 @@ static const struct gen_device_info gen_device_info_snb_gt2 
= {
.must_use_separate_stencil = true,   \
.has_llc = true, \
.has_pln = true, \
+   .has_64bit_types = true, \
.has_surface_tile_offset = true, \
.timestamp_frequency = 1250
 
@@ -381,6 +382,7 @@ static const struct gen_device_info gen_device_info_hsw_gt3 
= {
.has_llc = true, \
.has_sample_with_hiz = false,\
.has_pln = true, \
+   .has_64bit_types = true, \
.supports_simd16_3src = true,\
.has_surface_tile_offset = true, \
.max_vs_threads = 504,   \
@@ -815,6 +817,7 @@ static const struct gen_device_info gen_device_info_cnl_5x8 
= {
 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
GEN8_FEATURES, \
GEN11_HW_INFO, \
+   .has_64bit_types = false,  \
.gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
.num_subslices = _subslices
 
diff --git a/src/intel/common/gen_device_info.h 
b/src/intel/common/gen_device_info.h
index 3e9c087f58..9b635ff178 100644
--- a/src/intel/common/gen_device_info.h
+++ b/src/intel/common/gen_device_info.h
@@ -59,6 +59,7 @@ struct gen_device_info
bool has_llc;
 
bool has_pln;
+   bool has_64bit_types;
bool has_compr4;
bool has_surface_tile_offset;
bool supports_simd16_3src;
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 127371c5b8..73a6c73f53 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -218,7 +218,7 @@ intelInitExtensions(struct gl_context *ctx)
   ctx->Extensions.ARB_derivative_control = true;
   ctx->Extensions.ARB_framebuffer_no_attachments = true;
   ctx->Extensions.ARB_gpu_shader5 = true;
-  ctx->Extensions.ARB_gpu_shader_fp64 = true;
+  ctx->Extensions.ARB_gpu_shader_fp64 = devinfo->has_64bit_types;
   ctx->Extensions.ARB_shader_atomic_counters = true;
   ctx->Extensions.ARB_shader_atomic_counter_ops = true;
   ctx->Extensions.ARB_shader_clock = true;
@@ -230,7 +230,7 @@ intelInitExtensions(struct gl_context *ctx)
   ctx->Extensions.ARB_texture_compression_bptc = true;
   ctx->Extensions.ARB_texture_view = true;
   ctx->Extensions.ARB_shader_storage_buffer_object = true;
-  ctx->Extensions.ARB_vertex_attrib_64bit = true;
+  ctx->Extensions.ARB_vertex_attrib_64bit = devinfo->has_64bit_types;
   ctx->Extensions.EXT_shader_samples_identical = true;
   ctx->Extensions.OES_primitive_bounding_box = true;
   ctx->Extensions.OES_texture_buffer = true;
@@ -280,8 +280,9 @@ intelInitExtensions(struct gl_context *ctx)
}
 
if (devinfo->gen >= 8) {
-  ctx->Extensions.ARB_gpu_shader_int64 = true;
-  ctx->Extensions.ARB_shader_ballot = true; /* requires 
ARB_gpu_shader_int64 */
+  ctx->Extensions.ARB_gpu_shader_int64 = devinfo->has_64bit_types;
+  /* requires ARB_gpu_shader_int64 */
+  ctx->Extensions.ARB_shader_ballot = devinfo->has_64bit_types;
   ctx->Extensions.ARB_ES3_2_compatibility = true;
}
 

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Mesa (master): intel/compiler: Disable Align16 tests on Gen11+

[Matt Turner]

Module: Mesa
Branch: master
Commit: ff4b41dd1dffe81f70572c9183062cd36b0074dc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff4b41dd1dffe81f70572c9183062cd36b0074dc

Author: Matt Turner <matts...@gmail.com>
Date:   Thu Feb  8 10:23:11 2018 -0800

intel/compiler: Disable Align16 tests on Gen11+

Align16 is no more.

Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/test_eu_validate.cpp | 16 
 1 file changed, 16 insertions(+)

diff --git a/src/intel/compiler/test_eu_validate.cpp 
b/src/intel/compiler/test_eu_validate.cpp
index cb2fcd3d40..f6c2b35625 100644
--- a/src/intel/compiler/test_eu_validate.cpp
+++ b/src/intel/compiler/test_eu_validate.cpp
@@ -374,6 +374,10 @@ TEST_P(validation_test, dst_horizontal_stride_0)
 
clear_instructions(p);
 
+   /* Align16 does not exist on Gen11+ */
+   if (devinfo.gen >= 11)
+  return;
+
brw_set_default_access_mode(p, BRW_ALIGN_16);
 
brw_ADD(p, g0, g0, g0);
@@ -421,6 +425,10 @@ TEST_P(validation_test, 
must_not_cross_grf_boundary_in_a_width)
 /* Destination Horizontal must be 1 in Align16 */
 TEST_P(validation_test, dst_hstride_on_align16_must_be_1)
 {
+   /* Align16 does not exist on Gen11+ */
+   if (devinfo.gen >= 11)
+  return;
+
brw_set_default_access_mode(p, BRW_ALIGN_16);
 
brw_ADD(p, g0, g0, g0);
@@ -439,6 +447,10 @@ TEST_P(validation_test, dst_hstride_on_align16_must_be_1)
 /* VertStride must be 0 or 4 in Align16 */
 TEST_P(validation_test, vstride_on_align16_must_be_0_or_4)
 {
+   /* Align16 does not exist on Gen11+ */
+   if (devinfo.gen >= 11)
+  return;
+
const struct {
   enum brw_vertical_stride vstride;
   bool expected_result;
@@ -1419,6 +1431,10 @@ TEST_P(validation_test, align16_64_bit_integer)
if (devinfo.gen < 8)
   return;
 
+   /* Align16 does not exist on Gen11+ */
+   if (devinfo.gen >= 11)
+  return;
+
brw_set_default_access_mode(p, BRW_ALIGN_16);
 
for (unsigned i = 0; i < sizeof(inst) / sizeof(inst[0]); i++) {

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Mesa (master): intel/compiler/fs: Simplify ddx/ddy code generation

[Matt Turner]

Module: Mesa
Branch: master
Commit: 62cfd4c6563dfcd950b703c4159faff21f36a19e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=62cfd4c6563dfcd950b703c4159faff21f36a19e

Author: Matt Turner <matts...@gmail.com>
Date:   Thu Jun 15 17:20:29 2017 -0700

intel/compiler/fs: Simplify ddx/ddy code generation

The brw_reg() constructor just obfuscates things here, in my opinion.

Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/brw_fs_generator.cpp | 63 +++--
 1 file changed, 21 insertions(+), 42 deletions(-)

diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index c49af89f2f..e6fb7c92d4 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1163,20 +1163,17 @@ fs_generator::generate_ddx(const fs_inst *inst,
   width = BRW_WIDTH_4;
}
 
-   struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
- src.negate, src.abs,
-BRW_REGISTER_TYPE_F,
-vstride,
-width,
-BRW_HORIZONTAL_STRIDE_0,
-BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
-   struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
- src.negate, src.abs,
-BRW_REGISTER_TYPE_F,
-vstride,
-width,
-BRW_HORIZONTAL_STRIDE_0,
-BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
+   struct brw_reg src0 = src;
+   struct brw_reg src1 = src;
+
+   src0.subnr   = sizeof(float);
+   src0.vstride = vstride;
+   src0.width   = width;
+   src0.hstride = BRW_HORIZONTAL_STRIDE_0;
+   src1.vstride = vstride;
+   src1.width   = width;
+   src1.hstride = BRW_HORIZONTAL_STRIDE_0;
+
brw_ADD(p, dst, src0, negate(src1));
 }
 
@@ -1190,40 +1187,22 @@ fs_generator::generate_ddy(const fs_inst *inst,
 {
if (inst->opcode == FS_OPCODE_DDY_FINE) {
   /* produce accurate derivatives */
-  struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
-src.negate, src.abs,
-BRW_REGISTER_TYPE_F,
-BRW_VERTICAL_STRIDE_4,
-BRW_WIDTH_4,
-BRW_HORIZONTAL_STRIDE_1,
-BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
-  struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
-src.negate, src.abs,
-BRW_REGISTER_TYPE_F,
-BRW_VERTICAL_STRIDE_4,
-BRW_WIDTH_4,
-BRW_HORIZONTAL_STRIDE_1,
-BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
+  struct brw_reg src0 = stride(src, 4, 4, 1);
+  struct brw_reg src1 = stride(src, 4, 4, 1);
+  src0.swizzle = BRW_SWIZZLE_XYXY;
+  src1.swizzle = BRW_SWIZZLE_ZWZW;
+
   brw_push_insn_state(p);
   brw_set_default_access_mode(p, BRW_ALIGN_16);
   brw_ADD(p, dst, negate(src0), src1);
   brw_pop_insn_state(p);
} else {
   /* replicate the derivative at the top-left pixel to other pixels */
-  struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
-src.negate, src.abs,
-BRW_REGISTER_TYPE_F,
-BRW_VERTICAL_STRIDE_4,
-BRW_WIDTH_4,
-BRW_HORIZONTAL_STRIDE_0,
-BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
-  struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
-src.negate, src.abs,
-BRW_REGISTER_TYPE_F,
-BRW_VERTICAL_STRIDE_4,
-BRW_WIDTH_4,
-BRW_HORIZONTAL_STRIDE_0,
-BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
+  struct brw_reg src0 = stride(src, 4, 4, 0);
+  struct brw_reg src1 = stride(src, 4, 4, 0);
+  src0.subnr = 0 * sizeof(float);
+  src1.subnr = 2 * sizeof(float);
+
   brw_ADD(p, dst, negate(src0), src1);
}
 }

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Mesa (master): intel/compiler: Add Gen11+ native float type

[Matt Turner]

Module: Mesa
Branch: master
Commit: 2cff3242109078999c57d5e6772418c09e835826
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2cff3242109078999c57d5e6772418c09e835826

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Jun 14 11:03:19 2017 -0700

intel/compiler: Add Gen11+ native float type

This new type exposes the additional precision offered by the
accumulator register and will be used in the next patch to implement the
functionality of the PLN instruction using a pair of MAD instructions.

One weird thing to note: align1 ternary instructions may only have an
accumulator in the dst or src1 normally, but when src0's type is :NF
the accumulator is read.

Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/brw_disasm.c  |  7 +++
 src/intel/compiler/brw_eu_emit.c | 10 --
 src/intel/compiler/brw_eu_validate.c |  1 +
 src/intel/compiler/brw_reg_type.c|  8 
 src/intel/compiler/brw_reg_type.h|  2 ++
 src/intel/compiler/brw_shader.cpp|  6 ++
 6 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index 429ed78140..a9a108f8ac 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -1035,6 +1035,12 @@ src0_3src(FILE *file, const struct gen_device_info 
*devinfo, const brw_inst *ins
  reg_nr = brw_inst_3src_src0_reg_nr(devinfo, inst);
  subreg_nr = brw_inst_3src_a1_src0_subreg_nr(devinfo, inst);
  type = brw_inst_3src_a1_src0_type(devinfo, inst);
+  } else if (brw_inst_3src_a1_src0_type(devinfo, inst) ==
+ BRW_REGISTER_TYPE_NF) {
+ _file = BRW_ARCHITECTURE_REGISTER_FILE;
+ reg_nr = brw_inst_3src_src0_reg_nr(devinfo, inst);
+ subreg_nr = brw_inst_3src_a1_src0_subreg_nr(devinfo, inst);
+ type = brw_inst_3src_a1_src0_type(devinfo, inst);
   } else {
  _file = BRW_IMMEDIATE_VALUE;
  uint16_t imm_val = brw_inst_3src_a1_src0_imm(devinfo, inst);
@@ -1288,6 +1294,7 @@ imm(FILE *file, const struct gen_device_info *devinfo, 
enum brw_reg_type type,
case BRW_REGISTER_TYPE_HF:
   string(file, "Half Float IMM");
   break;
+   case BRW_REGISTER_TYPE_NF:
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
   format(file, "*** invalid immediate type %d ", type);
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index c25d8d6eda..ec871e5aa7 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -771,7 +771,11 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct 
brw_reg dest,
 to_3src_align1_hstride(src2.hstride));
 
   brw_inst_set_3src_a1_src0_subreg_nr(devinfo, inst, src0.subnr);
-  brw_inst_set_3src_src0_reg_nr(devinfo, inst, src0.nr);
+  if (src0.type == BRW_REGISTER_TYPE_NF) {
+ brw_inst_set_3src_src0_reg_nr(devinfo, inst, BRW_ARF_ACCUMULATOR);
+  } else {
+ brw_inst_set_3src_src0_reg_nr(devinfo, inst, src0.nr);
+  }
   brw_inst_set_3src_src0_abs(devinfo, inst, src0.abs);
   brw_inst_set_3src_src0_negate(devinfo, inst, src0.negate);
 
@@ -790,7 +794,9 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct 
brw_reg dest,
   brw_inst_set_3src_src2_negate(devinfo, inst, src2.negate);
 
   assert(src0.file == BRW_GENERAL_REGISTER_FILE ||
- src0.file == BRW_IMMEDIATE_VALUE);
+ src0.file == BRW_IMMEDIATE_VALUE ||
+ (src0.file == BRW_ARCHITECTURE_REGISTER_FILE &&
+  src0.type == BRW_REGISTER_TYPE_NF));
   assert(src1.file == BRW_GENERAL_REGISTER_FILE ||
  src1.file == BRW_ARCHITECTURE_REGISTER_FILE);
   assert(src2.file == BRW_GENERAL_REGISTER_FILE ||
diff --git a/src/intel/compiler/brw_eu_validate.c 
b/src/intel/compiler/brw_eu_validate.c
index 6ee6b4ffbe..d3189d1ef5 100644
--- a/src/intel/compiler/brw_eu_validate.c
+++ b/src/intel/compiler/brw_eu_validate.c
@@ -277,6 +277,7 @@ static enum brw_reg_type
 execution_type_for_type(enum brw_reg_type type)
 {
switch (type) {
+   case BRW_REGISTER_TYPE_NF:
case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_F:
case BRW_REGISTER_TYPE_HF:
diff --git a/src/intel/compiler/brw_reg_type.c 
b/src/intel/compiler/brw_reg_type.c
index c4f8eedeb4..3c82eb0a76 100644
--- a/src/intel/compiler/brw_reg_type.c
+++ b/src/intel/compiler/brw_reg_type.c
@@ -52,6 +52,7 @@ enum hw_reg_type {
GEN11_HW_REG_TYPE_HF = 8,
GEN11_HW_REG_TYPE_F  = 9,
GEN11_HW_REG_TYPE_DF = 10,
+   GEN11_HW_REG_TYPE_NF = 11,
 };
 
 enum hw_imm_type {
@@ -87,6 +88,8 @@ static const struct hw_type {
enum hw_reg_type reg_type;
enum hw_imm_type imm_type;
 } gen4_hw_type[] = {
+   [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID },
+
[BRW_REGISTER_TYPE_DF] = { GEN7_HW_REG_TYPE_DF, GEN8_HW_IMM_TYPE_DF },
[BRW

Mesa (master): intel/compiler: Mark line, pln, and lrp as removed on Gen11+

[Matt Turner]

Module: Mesa
Branch: master
Commit: d5bf093cf9da323ce3ebb69c07834870441e0e38
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5bf093cf9da323ce3ebb69c07834870441e0e38

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Jun 14 16:14:11 2017 -0700

intel/compiler: Mark line, pln, and lrp as removed on Gen11+

Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/brw_eu.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c
index bc297a21b3..3646076a8e 100644
--- a/src/intel/compiler/brw_eu.c
+++ b/src/intel/compiler/brw_eu.c
@@ -384,7 +384,8 @@ enum gen {
GEN75 = (1 << 5),
GEN8  = (1 << 6),
GEN9  = (1 << 7),
-   GEN10  = (1 << 8),
+   GEN10 = (1 << 8),
+   GEN11 = (1 << 9),
GEN_ALL = ~0
 };
 
@@ -628,16 +629,16 @@ static const struct opcode_desc opcode_descs[128] = {
},
/* Reserved 88 */
[BRW_OPCODE_LINE] = {
-  .name = "line",.nsrc = 2, .ndst = 1, .gens = GEN_ALL,
+  .name = "line",.nsrc = 2, .ndst = 1, .gens = GEN_LE(GEN10),
},
[BRW_OPCODE_PLN] = {
-  .name = "pln", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN45),
+  .name = "pln", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN45) & 
GEN_LE(GEN10),
},
[BRW_OPCODE_MAD] = {
   .name = "mad", .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN6),
},
[BRW_OPCODE_LRP] = {
-  .name = "lrp", .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN6),
+  .name = "lrp", .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN6) & 
GEN_LE(GEN10),
},
[93] = {
   .name = "madm",.nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN8),
@@ -662,6 +663,7 @@ gen_from_devinfo(const struct gen_device_info *devinfo)
case 8: return GEN8;
case 9: return GEN9;
case 10: return GEN10;
+   case 11: return GEN11;
default:
   unreachable("not reached");
}

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Mesa (master): intel/compiler/fs: Implement FS_OPCODE_LINTERP with MADs on Gen11+

[Matt Turner]

Module: Mesa
Branch: master
Commit: 432674ce93ceee2abd7e0cc4171bc36a499d4c1f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=432674ce93ceee2abd7e0cc4171bc36a499d4c1f

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Jun 14 14:47:19 2017 -0700

intel/compiler/fs: Implement FS_OPCODE_LINTERP with MADs on Gen11+

The PLN instruction is no more. Its functionality is now implemented
using two MAD instructions with the new native-float type. Instead of

   pln(16) r20.0<1>:F r10.4<0;1,0>:F r4.0<8;8,1>:F

we now have

   mad(8) acc0<1>:NF r10.7<0;1,0>:F r4.0<8;8,1>:F r10.4<0;1,0>:F
   mad(8) r20.0<1>:F acc0<8;8,1>:NF r5.0<8;8,1>:F r10.5<0;1,0>:F
   mad(8) acc0<1>:NF r10.7<0;1,0>:F r6.0<8;8,1>:F r10.4<0;1,0>:F
   mad(8) r21.0<1>:F acc0<8;8,1>:NF r7.0<8;8,1>:F r10.5<0;1,0>:F

... and in the case of SIMD8 only the first pair of MAD instructions is
used.

Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/brw_eu_emit.c|  2 +-
 src/intel/compiler/brw_fs_generator.cpp | 48 ++---
 2 files changed, 46 insertions(+), 4 deletions(-)

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index ec871e5aa7..a96fe43556 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -968,7 +968,7 @@ ALU2(DP4)
 ALU2(DPH)
 ALU2(DP3)
 ALU2(DP2)
-ALU3F(MAD)
+ALU3(MAD)
 ALU3F(LRP)
 ALU1(BFREV)
 ALU3(BFE)
diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index 3abd7cf538..736b3b5fba 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -673,10 +673,52 @@ fs_generator::generate_linterp(fs_inst *inst,
struct brw_reg delta_x = src[0];
struct brw_reg delta_y = offset(src[0], inst->exec_size / 8);
struct brw_reg interp = src[1];
-   brw_inst *i[2];
+   brw_inst *i[4];
 
-   if (devinfo->has_pln &&
-   (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
+   if (devinfo->gen >= 11) {
+  struct brw_reg acc = retype(brw_acc_reg(8), BRW_REGISTER_TYPE_NF);
+  struct brw_reg dwP = suboffset(interp, 0);
+  struct brw_reg dwQ = suboffset(interp, 1);
+  struct brw_reg dwR = suboffset(interp, 3);
+
+  brw_set_default_exec_size(p, BRW_EXECUTE_8);
+
+  if (inst->exec_size == 8) {
+ i[0] = brw_MAD(p,acc, dwR, offset(delta_x, 0), dwP);
+ i[1] = brw_MAD(p, offset(dst, 0), acc, offset(delta_y, 0), dwQ);
+
+ brw_inst_set_cond_modifier(p->devinfo, i[1], inst->conditional_mod);
+
+ /* brw_set_default_saturate() is called before emitting instructions,
+  * so the saturate bit is set in each instruction, so we need to unset
+  * it on the first instruction of each pair.
+  */
+ brw_inst_set_saturate(p->devinfo, i[0], false);
+  } else {
+ brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
+ i[0] = brw_MAD(p,acc, dwR, offset(delta_x, 0), dwP);
+ i[1] = brw_MAD(p, offset(dst, 0), acc, offset(delta_x, 1), dwQ);
+
+ brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
+ i[2] = brw_MAD(p,acc, dwR, offset(delta_y, 0), dwP);
+ i[3] = brw_MAD(p, offset(dst, 1), acc, offset(delta_y, 1), dwQ);
+
+ brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
+
+ brw_inst_set_cond_modifier(p->devinfo, i[1], inst->conditional_mod);
+ brw_inst_set_cond_modifier(p->devinfo, i[3], inst->conditional_mod);
+
+ /* brw_set_default_saturate() is called before emitting instructions,
+  * so the saturate bit is set in each instruction, so we need to unset
+  * it on the first instruction of each pair.
+  */
+ brw_inst_set_saturate(p->devinfo, i[0], false);
+ brw_inst_set_saturate(p->devinfo, i[2], false);
+  }
+
+  return true;
+   } else if (devinfo->has_pln &&
+  (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
   brw_PLN(p, dst, interp, delta_x);
 
   return false;

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Mesa (master): intel/compiler: Add Gen11 register types

[Matt Turner]

Module: Mesa
Branch: master
Commit: 58611ff913df74e7f790b0c572b983a992e25a17
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=58611ff913df74e7f790b0c572b983a992e25a17

Author: Matt Turner <matts...@gmail.com>
Date:   Fri Aug 25 09:50:29 2017 -0700

intel/compiler: Add Gen11 register types

The hardware register types' encodings have changed on Gen11. Good thing
we have that superfluous looking brw_reg_type abstraction lying around!

Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/brw_reg_type.c | 73 ++-
 1 file changed, 65 insertions(+), 8 deletions(-)

diff --git a/src/intel/compiler/brw_reg_type.c 
b/src/intel/compiler/brw_reg_type.c
index b7fff0867f..c4f8eedeb4 100644
--- a/src/intel/compiler/brw_reg_type.c
+++ b/src/intel/compiler/brw_reg_type.c
@@ -40,6 +40,18 @@ enum hw_reg_type {
BRW_HW_REG_TYPE_B   = 5,
GEN7_HW_REG_TYPE_DF = 6,
GEN8_HW_REG_TYPE_HF = 10,
+
+   GEN11_HW_REG_TYPE_UD = 0,
+   GEN11_HW_REG_TYPE_D  = 1,
+   GEN11_HW_REG_TYPE_UW = 2,
+   GEN11_HW_REG_TYPE_W  = 3,
+   GEN11_HW_REG_TYPE_UB = 4,
+   GEN11_HW_REG_TYPE_B  = 5,
+   GEN11_HW_REG_TYPE_UQ = 6,
+   GEN11_HW_REG_TYPE_Q  = 7,
+   GEN11_HW_REG_TYPE_HF = 8,
+   GEN11_HW_REG_TYPE_F  = 9,
+   GEN11_HW_REG_TYPE_DF = 10,
 };
 
 enum hw_imm_type {
@@ -56,9 +68,22 @@ enum hw_imm_type {
BRW_HW_IMM_TYPE_V   = 6,
GEN8_HW_IMM_TYPE_DF = 10,
GEN8_HW_IMM_TYPE_HF = 11,
+
+   GEN11_HW_IMM_TYPE_UD = 0,
+   GEN11_HW_IMM_TYPE_D  = 1,
+   GEN11_HW_IMM_TYPE_UW = 2,
+   GEN11_HW_IMM_TYPE_W  = 3,
+   GEN11_HW_IMM_TYPE_UV = 4,
+   GEN11_HW_IMM_TYPE_V  = 5,
+   GEN11_HW_IMM_TYPE_UQ = 6,
+   GEN11_HW_IMM_TYPE_Q  = 7,
+   GEN11_HW_IMM_TYPE_HF = 8,
+   GEN11_HW_IMM_TYPE_F  = 9,
+   GEN11_HW_IMM_TYPE_DF = 10,
+   GEN11_HW_IMM_TYPE_VF = 11,
 };
 
-static const struct {
+static const struct hw_type {
enum hw_reg_type reg_type;
enum hw_imm_type imm_type;
 } gen4_hw_type[] = {
@@ -77,6 +102,22 @@ static const struct {
[BRW_REGISTER_TYPE_UB] = { BRW_HW_REG_TYPE_UB,  INVALID },
[BRW_REGISTER_TYPE_V]  = { INVALID, BRW_HW_IMM_TYPE_V   },
[BRW_REGISTER_TYPE_UV] = { INVALID, BRW_HW_IMM_TYPE_UV  },
+}, gen11_hw_type[] = {
+   [BRW_REGISTER_TYPE_DF] = { GEN11_HW_REG_TYPE_DF, GEN11_HW_IMM_TYPE_DF },
+   [BRW_REGISTER_TYPE_F]  = { GEN11_HW_REG_TYPE_F,  GEN11_HW_IMM_TYPE_F  },
+   [BRW_REGISTER_TYPE_HF] = { GEN11_HW_REG_TYPE_HF, GEN11_HW_IMM_TYPE_HF },
+   [BRW_REGISTER_TYPE_VF] = { INVALID,  GEN11_HW_IMM_TYPE_VF },
+
+   [BRW_REGISTER_TYPE_Q]  = { GEN11_HW_REG_TYPE_Q,  GEN11_HW_IMM_TYPE_Q  },
+   [BRW_REGISTER_TYPE_UQ] = { GEN11_HW_REG_TYPE_UQ, GEN11_HW_IMM_TYPE_UQ },
+   [BRW_REGISTER_TYPE_D]  = { GEN11_HW_REG_TYPE_D,  GEN11_HW_IMM_TYPE_D  },
+   [BRW_REGISTER_TYPE_UD] = { GEN11_HW_REG_TYPE_UD, GEN11_HW_IMM_TYPE_UD },
+   [BRW_REGISTER_TYPE_W]  = { GEN11_HW_REG_TYPE_W,  GEN11_HW_IMM_TYPE_W  },
+   [BRW_REGISTER_TYPE_UW] = { GEN11_HW_REG_TYPE_UW, GEN11_HW_IMM_TYPE_UW },
+   [BRW_REGISTER_TYPE_B]  = { GEN11_HW_REG_TYPE_B,  INVALID  },
+   [BRW_REGISTER_TYPE_UB] = { GEN11_HW_REG_TYPE_UB, INVALID  },
+   [BRW_REGISTER_TYPE_V]  = { INVALID,  GEN11_HW_IMM_TYPE_V  },
+   [BRW_REGISTER_TYPE_UV] = { INVALID,  GEN11_HW_IMM_TYPE_UV },
 };
 
 /* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so
@@ -147,14 +188,22 @@ brw_reg_type_to_hw_type(const struct gen_device_info 
*devinfo,
 enum brw_reg_file file,
 enum brw_reg_type type)
 {
-   assert(type < ARRAY_SIZE(gen4_hw_type));
+   const struct hw_type *table;
+
+   if (devinfo->gen >= 11) {
+  assert(type < ARRAY_SIZE(gen11_hw_type));
+  table = gen11_hw_type;
+   } else {
+  assert(type < ARRAY_SIZE(gen4_hw_type));
+  table = gen4_hw_type;
+   }
 
if (file == BRW_IMMEDIATE_VALUE) {
-  assert(gen4_hw_type[type].imm_type != (enum hw_imm_type)INVALID);
-  return gen4_hw_type[type].imm_type;
+  assert(table[type].imm_type != (enum hw_imm_type)INVALID);
+  return table[type].imm_type;
} else {
-  assert(gen4_hw_type[type].reg_type != (enum hw_reg_type)INVALID);
-  return gen4_hw_type[type].reg_type;
+  assert(table[type].reg_type != (enum hw_reg_type)INVALID);
+  return table[type].reg_type;
}
 }
 
@@ -167,15 +216,23 @@ enum brw_reg_type
 brw_hw_type_to_reg_type(const struct gen_device_info *devinfo,
 enum brw_reg_file file, unsigned hw_type)
 {
+   const struct hw_type *table;
+
+   if (devinfo->gen >= 11) {
+  table = gen11_hw_type;
+   } else {
+  table = gen4_hw_type;
+   }
+
if (file == BRW_IMMEDIATE_VALUE) {
   for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) {
- if (gen4_hw_type[i].imm_type == (enum hw_imm_type)hw_type) {
+ if (table[i].imm_type == (enum hw_imm_t

Mesa (master): intel/compiler/fs: Return multiple_instructions_emitted from generate_linterp

[Matt Turner]

Module: Mesa
Branch: master
Commit: b5d8781e19559a8f9850f1a900ef93ffa3617faa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5d8781e19559a8f9850f1a900ef93ffa3617faa

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Jun 14 11:06:45 2017 -0700

intel/compiler/fs: Return multiple_instructions_emitted from generate_linterp

If multiple instructions are emitted, special handling of things like
conditional mod and NoDDClr/NoDDChk need to be performed.

Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/brw_fs.h |  2 +-
 src/intel/compiler/brw_fs_generator.cpp | 10 +++---
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index 63373580ee..37106ccb28 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -409,7 +409,7 @@ private:
void generate_urb_write(fs_inst *inst, struct brw_reg payload);
void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
void generate_barrier(fs_inst *inst, struct brw_reg src);
-   void generate_linterp(fs_inst *inst, struct brw_reg dst,
+   bool generate_linterp(fs_inst *inst, struct brw_reg dst,
 struct brw_reg *src);
void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
  struct brw_reg surface_index,
diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index bba917d755..3abd7cf538 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -646,9 +646,9 @@ fs_generator::generate_barrier(fs_inst *inst, struct 
brw_reg src)
brw_WAIT(p);
 }
 
-void
+bool
 fs_generator::generate_linterp(fs_inst *inst,
-struct brw_reg dst, struct brw_reg *src)
+   struct brw_reg dst, struct brw_reg *src)
 {
/* PLN reads:
 *  /   in SIMD16   \
@@ -678,6 +678,8 @@ fs_generator::generate_linterp(fs_inst *inst,
if (devinfo->has_pln &&
(devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
   brw_PLN(p, dst, interp, delta_x);
+
+  return false;
} else {
   i[0] = brw_LINE(p, brw_null_reg(), interp, delta_x);
   i[1] = brw_MAC(p, dst, suboffset(interp, 1), delta_y);
@@ -689,6 +691,8 @@ fs_generator::generate_linterp(fs_inst *inst,
* the first instruction.
*/
   brw_inst_set_saturate(p->devinfo, i[0], false);
+
+  return true;
}
 }
 
@@ -1963,7 +1967,7 @@ fs_generator::generate_code(const cfg_t *cfg, int 
dispatch_width)
 brw_MOV(p, dst, src[0]);
 break;
   case FS_OPCODE_LINTERP:
-generate_linterp(inst, dst, src);
+multiple_instructions_emitted = generate_linterp(inst, dst, src);
 break;
   case FS_OPCODE_PIXEL_X:
  assert(src[0].type == BRW_REGISTER_TYPE_UW);

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Mesa (master): intel/compiler/fs: Don't generate integer DWord multiply on Gen11

[Matt Turner]

Module: Mesa
Branch: master
Commit: 3a584a15c0b1dd6c31a6520a0f749306f48d5782
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3a584a15c0b1dd6c31a6520a0f749306f48d5782

Author: Matt Turner <matts...@gmail.com>
Date:   Mon Oct 23 10:44:39 2017 -0700

intel/compiler/fs: Don't generate integer DWord multiply on Gen11

Like CHV et al., Gen11 does not support 32x32 -> 32/64-bit integer
multiplies.

Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/common/gen_device_info.c | 4 
 src/intel/common/gen_device_info.h | 1 +
 src/intel/compiler/brw_fs.cpp  | 6 +-
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/intel/common/gen_device_info.c 
b/src/intel/common/gen_device_info.c
index 7bed806b36..1773009d33 100644
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -382,6 +382,7 @@ static const struct gen_device_info gen_device_info_hsw_gt3 
= {
.has_llc = true, \
.has_sample_with_hiz = false,\
.has_pln = true, \
+   .has_integer_dword_mul = true,   \
.has_64bit_types = true, \
.supports_simd16_3src = true,\
.has_surface_tile_offset = true, \
@@ -464,6 +465,7 @@ static const struct gen_device_info gen_device_info_bdw_gt3 
= {
 static const struct gen_device_info gen_device_info_chv = {
GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
.has_llc = false,
+   .has_integer_dword_mul = false,
.num_slices = 1,
.num_subslices = { 2, },
.num_thread_per_eu = 7,
@@ -514,6 +516,7 @@ static const struct gen_device_info gen_device_info_chv = {
 #define GEN9_LP_FEATURES   \
GEN8_FEATURES,  \
GEN9_HW_INFO,   \
+   .has_integer_dword_mul = false, \
.gt = 1,\
.has_llc = false,   \
.has_sample_with_hiz = true,\
@@ -818,6 +821,7 @@ static const struct gen_device_info gen_device_info_cnl_5x8 
= {
GEN8_FEATURES, \
GEN11_HW_INFO, \
.has_64bit_types = false,  \
+   .has_integer_dword_mul = false,\
.gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
.num_subslices = _subslices
 
diff --git a/src/intel/common/gen_device_info.h 
b/src/intel/common/gen_device_info.h
index 9b635ff178..b8044d0003 100644
--- a/src/intel/common/gen_device_info.h
+++ b/src/intel/common/gen_device_info.h
@@ -60,6 +60,7 @@ struct gen_device_info
 
bool has_pln;
bool has_64bit_types;
+   bool has_integer_dword_mul;
bool has_compr4;
bool has_surface_tile_offset;
bool supports_simd16_3src;
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index bed632d21b..113f62c46c 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -3549,11 +3549,7 @@ fs_visitor::lower_integer_multiplication()
   inst->dst.type != BRW_REGISTER_TYPE_UD))
 continue;
 
- /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
-  * operation directly, but CHV/BXT cannot.
-  */
- if (devinfo->gen >= 8 &&
- !devinfo->is_cherryview && !gen_device_info_is_9lp(devinfo))
+ if (devinfo->has_integer_dword_mul)
 continue;
 
  if (inst->src[1].file == IMM &&

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Mesa (master): intel: Add a preliminary device for Ice Lake

[Matt Turner]

Module: Mesa
Branch: master
Commit: 5ac804bd9accac58a176ae102dd0de52aaec6eb2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ac804bd9accac58a176ae102dd0de52aaec6eb2

Author: Anuj Phogat 
Date:   Tue Mar 14 14:43:34 2017 -0700

intel: Add a preliminary device for Ice Lake

Reviewed-by: Kenneth Graunke 
Signed-off-by: Anuj Phogat 

---

 src/intel/common/gen_device_info.c | 57 +-
 1 file changed, 56 insertions(+), 1 deletion(-)

diff --git a/src/intel/common/gen_device_info.c 
b/src/intel/common/gen_device_info.c
index ef0ae4ce8c..b17d22e5f8 100644
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -789,6 +789,50 @@ static const struct gen_device_info 
gen_device_info_cnl_5x8 = {
.is_cannonlake = true,
 };
 
+#define GEN11_HW_INFO   \
+   .gen = 11,   \
+   .has_pln = false,\
+   .max_vs_threads = 364,   \
+   .max_gs_threads = 224,   \
+   .max_tcs_threads = 224,  \
+   .max_tes_threads = 364,  \
+   .max_cs_threads = 56,\
+   .urb = { \
+  .size = 1024, \
+  .min_entries = {  \
+ [MESA_SHADER_VERTEX]= 64,  \
+ [MESA_SHADER_TESS_EVAL] = 34,  \
+  },\
+  .max_entries = {  \
+ [MESA_SHADER_VERTEX]= 2384,\
+ [MESA_SHADER_TESS_CTRL] = 1032,\
+ [MESA_SHADER_TESS_EVAL] = 2384,\
+ [MESA_SHADER_GEOMETRY]  = 1032,\
+  },\
+   }
+
+#define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
+   GEN8_FEATURES, \
+   GEN11_HW_INFO, \
+   .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
+   .num_subslices = _subslices
+
+static const struct gen_device_info gen_device_info_icl_8x8 = {
+   GEN11_FEATURES(2, 1, subslices(8), 8),
+};
+
+static const struct gen_device_info gen_device_info_icl_6x8 = {
+   GEN11_FEATURES(1, 1, subslices(6), 6),
+};
+
+static const struct gen_device_info gen_device_info_icl_4x8 = {
+   GEN11_FEATURES(1, 1, subslices(4), 6),
+};
+
+static const struct gen_device_info gen_device_info_icl_1x8 = {
+   GEN11_FEATURES(1, 1, subslices(1), 6),
+};
+
 bool
 gen_get_device_info(int devid, struct gen_device_info *devinfo)
 {
@@ -815,10 +859,21 @@ gen_get_device_info(int devid, struct gen_device_info 
*devinfo)
 * Extra padding can be necessary depending how the thread IDs are
 * calculated for a particular shader stage.
 */
-   if (devinfo->gen >= 9) {
+
+   switch(devinfo->gen) {
+   case 9:
+   case 10:
   devinfo->max_wm_threads = 64 /* threads-per-PSD */
   * devinfo->num_slices
   * 4; /* effective subslices per slice */
+  break;
+   case 11:
+  devinfo->max_wm_threads = 128 /* threads-per-PSD */
+  * devinfo->num_slices
+  * 8; /* subslices per slice */
+  break;
+   default:
+  break;
}
 
assert(devinfo->num_slices <= ARRAY_SIZE(devinfo->num_subslices));

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Mesa (master): intel/compiler: Lower flrp32 on Gen11+

[Matt Turner]

Module: Mesa
Branch: master
Commit: 89fe5190a256ee0939061c4c264e9156256d16e8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=89fe5190a256ee0939061c4c264e9156256d16e8

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Jun 14 16:20:41 2017 -0700

intel/compiler: Lower flrp32 on Gen11+

The LRP instruction is no more.

Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/brw_compiler.c   | 35 +
 src/intel/compiler/brw_fs_builder.h |  2 +-
 src/intel/compiler/brw_fs_generator.cpp |  2 +-
 src/intel/compiler/brw_vec4_builder.h   |  2 +-
 src/intel/compiler/brw_vec4_visitor.cpp |  2 +-
 5 files changed, 26 insertions(+), 17 deletions(-)

diff --git a/src/intel/compiler/brw_compiler.c 
b/src/intel/compiler/brw_compiler.c
index bb9df5e701..34be3b705f 100644
--- a/src/intel/compiler/brw_compiler.c
+++ b/src/intel/compiler/brw_compiler.c
@@ -46,20 +46,28 @@
.use_interpolated_input_intrinsics = true, \
.vertex_id_zero_based = true
 
+#define COMMON_SCALAR_OPTIONS \
+   .lower_pack_half_2x16 = true,  \
+   .lower_pack_snorm_2x16 = true, \
+   .lower_pack_snorm_4x8 = true,  \
+   .lower_pack_unorm_2x16 = true, \
+   .lower_pack_unorm_4x8 = true,  \
+   .lower_unpack_half_2x16 = true,\
+   .lower_unpack_snorm_2x16 = true,   \
+   .lower_unpack_snorm_4x8 = true,\
+   .lower_unpack_unorm_2x16 = true,   \
+   .lower_unpack_unorm_4x8 = true,\
+   .max_unroll_iterations = 32
+
 static const struct nir_shader_compiler_options scalar_nir_options = {
COMMON_OPTIONS,
-   .lower_pack_half_2x16 = true,
-   .lower_pack_snorm_2x16 = true,
-   .lower_pack_snorm_4x8 = true,
-   .lower_pack_unorm_2x16 = true,
-   .lower_pack_unorm_4x8 = true,
-   .lower_unpack_half_2x16 = true,
-   .lower_unpack_snorm_2x16 = true,
-   .lower_unpack_snorm_4x8 = true,
-   .lower_unpack_unorm_2x16 = true,
-   .lower_unpack_unorm_4x8 = true,
-   .vs_inputs_dual_locations = true,
-   .max_unroll_iterations = 32,
+   COMMON_SCALAR_OPTIONS,
+};
+
+static const struct nir_shader_compiler_options scalar_nir_options_gen11 = {
+   COMMON_OPTIONS,
+   COMMON_SCALAR_OPTIONS,
+   .lower_flrp32 = true,
 };
 
 static const struct nir_shader_compiler_options vector_nir_options = {
@@ -149,7 +157,8 @@ brw_compiler_create(void *mem_ctx, const struct 
gen_device_info *devinfo)
   compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 
   if (is_scalar) {
- compiler->glsl_compiler_options[i].NirOptions = _nir_options;
+ compiler->glsl_compiler_options[i].NirOptions =
+devinfo->gen < 11 ? _nir_options : 
_nir_options_gen11;
   } else {
  compiler->glsl_compiler_options[i].NirOptions =
 devinfo->gen < 6 ? _nir_options : _nir_options_gen6;
diff --git a/src/intel/compiler/brw_fs_builder.h 
b/src/intel/compiler/brw_fs_builder.h
index 87394bc17b..874272b7af 100644
--- a/src/intel/compiler/brw_fs_builder.h
+++ b/src/intel/compiler/brw_fs_builder.h
@@ -540,7 +540,7 @@ namespace brw {
   LRP(const dst_reg , const src_reg , const src_reg ,
   const src_reg ) const
   {
- if (shader->devinfo->gen >= 6) {
+ if (shader->devinfo->gen >= 6 && shader->devinfo->gen <= 10) {
 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), 
so
  * we need to reorder the operands.
  */
diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index 0dc0a695e4..b59c09f46e 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1826,7 +1826,7 @@ fs_generator::generate_code(const cfg_t *cfg, int 
dispatch_width)
 break;
 
   case BRW_OPCODE_LRP:
- assert(devinfo->gen >= 6);
+ assert(devinfo->gen >= 6 && devinfo->gen <= 10);
  if (devinfo->gen < 10)
 brw_set_default_access_mode(p, BRW_ALIGN_16);
  brw_LRP(p, dst, src[0], src[1], src[2]);
diff --git a/src/intel/compiler/brw_vec4_builder.h 
b/src/intel/compiler/brw_vec4_builder.h
index 4c3efe8457..5c880c19f5 100644
--- a/src/intel/compiler/brw_vec4_builder.h
+++ b/src/intel/compiler/brw_vec4_builder.h
@@ -501,7 +501,7 @@ namespace brw {
   LRP(const dst_reg , const src_reg , const src_reg ,
   const src_reg ) const
   {
- if (shader->devinfo->

Mesa (master): intel: Add icl pci id for INTEL_DEVID_OVERRIDE

[Matt Turner]

Module: Mesa
Branch: master
Commit: 5e42103f3be5cfaaa374442e009c101403c143bd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e42103f3be5cfaaa374442e009c101403c143bd

Author: Anuj Phogat <anuj.pho...@gmail.com>
Date:   Wed May 10 15:26:51 2017 -0700

intel: Add icl pci id for INTEL_DEVID_OVERRIDE

Reviewed-by: Matt Turner <matts...@gmail.com>
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>

---

 src/intel/common/gen_device_info.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/common/gen_device_info.c 
b/src/intel/common/gen_device_info.c
index b17d22e5f8..11a4480ebf 100644
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -56,6 +56,7 @@ gen_device_name_to_pci_device_id(const char *name)
   { "kbl", 0x5912 },
   { "glk", 0x3185 },
   { "cnl", 0x5a52 },
+  { "icl", 0x8a52 },
};
 
for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {

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Mesa (master): intel/compiler/fs: Pass fs_inst to generate_ddx/ddy instead of opcode

[Matt Turner]

Module: Mesa
Branch: master
Commit: bed0267ff64d923feff01ab9144a8f8283700d63
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bed0267ff64d923feff01ab9144a8f8283700d63

Author: Matt Turner <matts...@gmail.com>
Date:   Thu Jun 15 15:41:40 2017 -0700

intel/compiler/fs: Pass fs_inst to generate_ddx/ddy instead of opcode

In a future patch, generate_ddy will want to inspect inst->exec_size.
Change generate_ddx as well for consistency.

Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/brw_fs.h |  6 --
 src/intel/compiler/brw_fs_generator.cpp | 12 ++--
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index 37106ccb28..76ad76e08b 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -417,8 +417,10 @@ private:
void generate_get_buffer_size(fs_inst *inst, struct brw_reg dst,
  struct brw_reg src,
  struct brw_reg surf_index);
-   void generate_ddx(enum opcode op, struct brw_reg dst, struct brw_reg src);
-   void generate_ddy(enum opcode op, struct brw_reg dst, struct brw_reg src);
+   void generate_ddx(const fs_inst *inst,
+ struct brw_reg dst, struct brw_reg src);
+   void generate_ddy(const fs_inst *inst,
+ struct brw_reg dst, struct brw_reg src);
void generate_scratch_write(fs_inst *inst, struct brw_reg src);
void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index 736b3b5fba..c49af89f2f 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1148,12 +1148,12 @@ fs_generator::generate_tex(fs_inst *inst, struct 
brw_reg dst, struct brw_reg src
  * appropriate swizzling.
  */
 void
-fs_generator::generate_ddx(enum opcode opcode,
+fs_generator::generate_ddx(const fs_inst *inst,
struct brw_reg dst, struct brw_reg src)
 {
unsigned vstride, width;
 
-   if (opcode == FS_OPCODE_DDX_FINE) {
+   if (inst->opcode == FS_OPCODE_DDX_FINE) {
   /* produce accurate derivatives */
   vstride = BRW_VERTICAL_STRIDE_2;
   width = BRW_WIDTH_2;
@@ -1185,10 +1185,10 @@ fs_generator::generate_ddx(enum opcode opcode,
  * left.
  */
 void
-fs_generator::generate_ddy(enum opcode opcode,
+fs_generator::generate_ddy(const fs_inst *inst,
struct brw_reg dst, struct brw_reg src)
 {
-   if (opcode == FS_OPCODE_DDY_FINE) {
+   if (inst->opcode == FS_OPCODE_DDY_FINE) {
   /* produce accurate derivatives */
   struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
 src.negate, src.abs,
@@ -2044,11 +2044,11 @@ fs_generator::generate_code(const cfg_t *cfg, int 
dispatch_width)
 break;
   case FS_OPCODE_DDX_COARSE:
   case FS_OPCODE_DDX_FINE:
- generate_ddx(inst->opcode, dst, src[0]);
+ generate_ddx(inst, dst, src[0]);
  break;
   case FS_OPCODE_DDY_COARSE:
   case FS_OPCODE_DDY_FINE:
- generate_ddy(inst->opcode, dst, src[0]);
+ generate_ddy(inst, dst, src[0]);
 break;
 
   case SHADER_OPCODE_GEN4_SCRATCH_WRITE:

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Mesa (master): intel/compiler/fs: Fix application of cmod and saturate to LINE/MAC pair

[Matt Turner]

Module: Mesa
Branch: master
Commit: b1afdf9fc121df7e2e757fb9cf0d2c1f37a408ba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b1afdf9fc121df7e2e757fb9cf0d2c1f37a408ba

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Jun 14 14:47:19 2017 -0700

intel/compiler/fs: Fix application of cmod and saturate to LINE/MAC pair

This isn't technically broken, but the next patch will make this
function report whether it generated multiple instructions, and that
information will be used to disable the application of conditional mod
by the generic code.

Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/brw_fs_generator.cpp | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index cd5be054f6..bba917d755 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -673,13 +673,22 @@ fs_generator::generate_linterp(fs_inst *inst,
struct brw_reg delta_x = src[0];
struct brw_reg delta_y = offset(src[0], inst->exec_size / 8);
struct brw_reg interp = src[1];
+   brw_inst *i[2];
 
if (devinfo->has_pln &&
(devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
   brw_PLN(p, dst, interp, delta_x);
} else {
-  brw_LINE(p, brw_null_reg(), interp, delta_x);
-  brw_MAC(p, dst, suboffset(interp, 1), delta_y);
+  i[0] = brw_LINE(p, brw_null_reg(), interp, delta_x);
+  i[1] = brw_MAC(p, dst, suboffset(interp, 1), delta_y);
+
+  brw_inst_set_cond_modifier(p->devinfo, i[1], inst->conditional_mod);
+
+  /* brw_set_default_saturate() is called before emitting instructions, so
+   * the saturate bit is set in each instruction, so we need to unset it on
+   * the first instruction.
+   */
+  brw_inst_set_saturate(p->devinfo, i[0], false);
}
 }
 

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Mesa (master): intel/compiler: Add instruction compaction support on Gen11

[Matt Turner]

Module: Mesa
Branch: master
Commit: c31d77ac22c10f23704a98fe955ce22e0839cfe2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c31d77ac22c10f23704a98fe955ce22e0839cfe2

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Jun 14 16:43:05 2017 -0700

intel/compiler: Add instruction compaction support on Gen11

Gen11 only differs from SKL+ in that it uses a new datatype index table.

Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/brw_eu_compact.c | 42 +
 1 file changed, 42 insertions(+)

diff --git a/src/intel/compiler/brw_eu_compact.c 
b/src/intel/compiler/brw_eu_compact.c
index 8d33e2adff..ae14ef10ec 100644
--- a/src/intel/compiler/brw_eu_compact.c
+++ b/src/intel/compiler/brw_eu_compact.c
@@ -637,6 +637,41 @@ static const uint16_t gen8_src_index_table[32] = {
0b010110001000
 };
 
+static const uint32_t gen11_datatype_table[32] = {
+   0b00101,
+   0b001000100,
+   0b001000101,
+   0b001001101,
+   0b0010101100101,
+   0b0010010100101,
+   0b0010010010101,
+   0b00100100101000101,
+   0b00100100101100101,
+   0b001010101,
+   0b001110100,
+   0b001110101,
+   0b001000101000101000101,
+   0b001000111000101000100,
+   0b001000111000101000101,
+   0b001100100100101100101,
+   0b001100101100100100101,
+   0b001100101100101100100,
+   0b001100101100101100101,
+   0b00110000101100100,
+   0b001001100,
+   0b0010001100101,
+   0b0010101000101,
+   0b001010100,
+   0b001000101000101000100,
+   0b00100011100010100,
+   0b00100100100101001,
+   0b00110100101100101,
+   0b00110000101100101,
+   0b00100001101001100,
+   0b001001001001001001000,
+   0b001001011001001001000,
+};
+
 /* This is actually the control index table for Cherryview (26 bits), but the
  * only difference from Broadwell (24 bits) is that it has two extra 0-bits at
  * the start.
@@ -1450,8 +1485,15 @@ brw_init_compaction_tables(const struct gen_device_info 
*devinfo)
assert(gen8_datatype_table[ARRAY_SIZE(gen8_datatype_table) - 1] != 0);
assert(gen8_subreg_table[ARRAY_SIZE(gen8_subreg_table) - 1] != 0);
assert(gen8_src_index_table[ARRAY_SIZE(gen8_src_index_table) - 1] != 0);
+   assert(gen11_datatype_table[ARRAY_SIZE(gen11_datatype_table) - 1] != 0);
 
switch (devinfo->gen) {
+   case 11:
+  control_index_table = gen8_control_index_table;
+  datatype_table = gen11_datatype_table;
+  subreg_table = gen8_subreg_table;
+  src_index_table = gen8_src_index_table;
+  break;
case 10:
case 9:
case 8:

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Mesa (master): i965: Move mistakenly placed line

[Matt Turner]

Module: Mesa
Branch: master
Commit: e2b31e9acf034407cc020d8956b06bd0995fe809
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2b31e9acf034407cc020d8956b06bd0995fe809

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Jan 31 11:09:36 2018 -0800

i965: Move mistakenly placed line

Ken called this out in review, but it seems I forgot to make the change.
I noticed that the control flow annotations in the fragment shader
disassembly of tests/shaders/glsl-fs-loop-continue.shader_test were not
correct, and moving this line to the correct place fixes it.

---

 src/intel/compiler/brw_disasm_info.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_disasm_info.c 
b/src/intel/compiler/brw_disasm_info.c
index 3db79ede70..f8f4c02e76 100644
--- a/src/intel/compiler/brw_disasm_info.c
+++ b/src/intel/compiler/brw_disasm_info.c
@@ -123,8 +123,8 @@ disasm_annotate(struct disasm_info *disasm,
struct inst_group *group;
if (!disasm->use_tail) {
   group = disasm_new_inst_group(disasm, offset);
-  disasm->use_tail = false;
} else {
+  disasm->use_tail = false;
   group = exec_node_data(struct inst_group,
  exec_list_get_tail_raw(>group_list), 
link);
}

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Mesa (master): Revert "Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+""

[Matt Turner]

Module: Mesa
Branch: master
Commit: c0ef14f5b1a59d016369a0d3322b9e783009b308
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0ef14f5b1a59d016369a0d3322b9e783009b308

Author: Matt Turner <matts...@gmail.com>
Date:   Fri Jan  5 09:46:11 2018 -0800

Revert "Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+""

This reverts commit 2d0457203871c843ebfc90fb895b65a9b14cd9bb.

Acked-by: Scott D Phillips <scott.d.phill...@intel.com>

---

 src/intel/compiler/brw_fs_generator.cpp | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index 37b8f07769..91bf064308 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1758,13 +1758,15 @@ fs_generator::generate_code(const cfg_t *cfg, int 
dispatch_width)
 
   case BRW_OPCODE_MAD:
  assert(devinfo->gen >= 6);
-brw_set_default_access_mode(p, BRW_ALIGN_16);
+ if (devinfo->gen < 10)
+brw_set_default_access_mode(p, BRW_ALIGN_16);
  brw_MAD(p, dst, src[0], src[1], src[2]);
 break;
 
   case BRW_OPCODE_LRP:
  assert(devinfo->gen >= 6);
-brw_set_default_access_mode(p, BRW_ALIGN_16);
+ if (devinfo->gen < 10)
+brw_set_default_access_mode(p, BRW_ALIGN_16);
  brw_LRP(p, dst, src[0], src[1], src[2]);
 break;
 
@@ -1862,7 +1864,8 @@ fs_generator::generate_code(const cfg_t *cfg, int 
dispatch_width)
 
   case BRW_OPCODE_BFE:
  assert(devinfo->gen >= 7);
- brw_set_default_access_mode(p, BRW_ALIGN_16);
+ if (devinfo->gen < 10)
+brw_set_default_access_mode(p, BRW_ALIGN_16);
  brw_BFE(p, dst, src[0], src[1], src[2]);
  break;
 
@@ -1872,7 +1875,8 @@ fs_generator::generate_code(const cfg_t *cfg, int 
dispatch_width)
  break;
   case BRW_OPCODE_BFI2:
  assert(devinfo->gen >= 7);
- brw_set_default_access_mode(p, BRW_ALIGN_16);
+ if (devinfo->gen < 10)
+brw_set_default_access_mode(p, BRW_ALIGN_16);
  brw_BFI2(p, dst, src[0], src[1], src[2]);
  break;
 

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Mesa (master): i965/fs: Add/use functions to convert to 3src_align1 vstride/hstride

[Matt Turner]

Module: Mesa
Branch: master
Commit: 01ebfbb67ac82d5257dfc619a81fd841aed576b5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=01ebfbb67ac82d5257dfc619a81fd841aed576b5

Author: Matt Turner <matts...@gmail.com>
Date:   Mon Dec 11 11:44:48 2017 -0800

i965/fs: Add/use functions to convert to 3src_align1 vstride/hstride

Some cases weren't handled, such as stride 4 which is needed for 64-bit
operations. Presumably fixes the assertion failure mentioned in commit
2d0457203871 (Revert "i965/fs: Use align1 mode on ternary instructions
on Gen10+") but who can really say since the commit neglected to list
any of them!

Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>

---

 src/intel/compiler/brw_eu_emit.c | 69 
 1 file changed, 41 insertions(+), 28 deletions(-)

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 85bb6a4cdd..c25d8d6eda 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -673,6 +673,42 @@ get_3src_subreg_nr(struct brw_reg reg)
return reg.subnr / 4;
 }
 
+static enum gen10_align1_3src_vertical_stride
+to_3src_align1_vstride(enum brw_vertical_stride vstride)
+{
+   switch (vstride) {
+   case BRW_VERTICAL_STRIDE_0:
+  return BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0;
+   case BRW_VERTICAL_STRIDE_2:
+  return BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2;
+   case BRW_VERTICAL_STRIDE_4:
+  return BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4;
+   case BRW_VERTICAL_STRIDE_8:
+   case BRW_VERTICAL_STRIDE_16:
+  return BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8;
+   default:
+  unreachable("invalid vstride");
+   }
+}
+
+
+static enum gen10_align1_3src_src_horizontal_stride
+to_3src_align1_hstride(enum brw_horizontal_stride hstride)
+{
+   switch (hstride) {
+   case BRW_HORIZONTAL_STRIDE_0:
+  return BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0;
+   case BRW_HORIZONTAL_STRIDE_1:
+  return BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1;
+   case BRW_HORIZONTAL_STRIDE_2:
+  return BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2;
+   case BRW_HORIZONTAL_STRIDE_4:
+  return BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4;
+   default:
+  unreachable("invalid hstride");
+   }
+}
+
 static brw_inst *
 brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
  struct brw_reg src0, struct brw_reg src1, struct brw_reg src2)
@@ -721,41 +757,18 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct 
brw_reg dest,
   brw_inst_set_3src_a1_src1_type(devinfo, inst, src1.type);
   brw_inst_set_3src_a1_src2_type(devinfo, inst, src2.type);
 
-  assert((src0.vstride == BRW_VERTICAL_STRIDE_0 &&
-  src0.hstride == BRW_HORIZONTAL_STRIDE_0) ||
- (src0.vstride == BRW_VERTICAL_STRIDE_8 &&
-  src0.hstride == BRW_HORIZONTAL_STRIDE_1));
-  assert((src1.vstride == BRW_VERTICAL_STRIDE_0 &&
-  src1.hstride == BRW_HORIZONTAL_STRIDE_0) ||
- (src1.vstride == BRW_VERTICAL_STRIDE_8 &&
-  src1.hstride == BRW_HORIZONTAL_STRIDE_1));
-  assert((src2.vstride == BRW_VERTICAL_STRIDE_0 &&
-  src2.hstride == BRW_HORIZONTAL_STRIDE_0) ||
- (src2.vstride == BRW_VERTICAL_STRIDE_8 &&
-  src2.hstride == BRW_HORIZONTAL_STRIDE_1));
-
   brw_inst_set_3src_a1_src0_vstride(devinfo, inst,
-src0.vstride == BRW_VERTICAL_STRIDE_0 ?
-BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0 :
-BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8);
+to_3src_align1_vstride(src0.vstride));
   brw_inst_set_3src_a1_src1_vstride(devinfo, inst,
-src1.vstride == BRW_VERTICAL_STRIDE_0 ?
-BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0 :
-BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8);
+to_3src_align1_vstride(src1.vstride));
   /* no vstride on src2 */
 
   brw_inst_set_3src_a1_src0_hstride(devinfo, inst,
-src0.hstride == 
BRW_HORIZONTAL_STRIDE_0 ?
-
BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 :
-
BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1);
+to_3src_align1_hstride(src0.hstride));
   brw_inst_set_3src_a1_src1_hstride(devinfo, inst,
-src1.hstride == 
BRW_HORIZONTAL_STRIDE_0 ?
-
BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 :
-
BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1);
+to_3src_align1_hstride(src1.hstride));
   brw_inst_set_3src_a1_src2_hstride(devinf

Mesa (master): i965: Emit CS stall before MEDIA_VFE_STATE.

[Matt Turner]

Module: Mesa
Branch: master
Commit: 55a97db52347f62111a24715078c6035380d3e19
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=55a97db52347f62111a24715078c6035380d3e19

Author: Kenneth Graunke <kenn...@whitecape.org>
Date:   Tue Oct 31 09:57:54 2017 -0700

i965: Emit CS stall before MEDIA_VFE_STATE.

This fixes hangs on GFXBench 5's Aztec Ruins benchmark.

Unfortunately, it regresses OglCSCloth performance by about 10%. There
are some ideas for fixing that.

The Vulkan driver already emits this stall.

Reviewed-by: Matt Turner <matts...@gmail.com>

---

 src/mesa/drivers/dri/i965/genX_state_upload.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 533ef8b703..04a492539a 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -4169,6 +4169,18 @@ genX(upload_cs_state)(struct brw_context *brw)
uint32_t *bind = brw_state_batch(brw, prog_data->binding_table.size_bytes,
 32, _state->bind_bo_offset);
 
+   /* The MEDIA_VFE_STATE documentation for Gen8+ says:
+*
+* "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
+*  the only bits that are changed are scoreboard related: Scoreboard
+*  Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
+*  these scoreboard related states, a MEDIA_STATE_FLUSH is sufficient."
+*
+* Earlier generations say "MI_FLUSH" instead of "stalling PIPE_CONTROL",
+* but MI_FLUSH isn't really a thing, so we assume they meant PIPE_CONTROL.
+*/
+   brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
+
brw_batch_emit(brw, GENX(MEDIA_VFE_STATE), vfe) {
   if (prog_data->total_scratch) {
  uint32_t bo_offset;

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Mesa (master): i965: Move PIPE_CONTROL defines and prototypes to brw_pipe_control.h.

[Matt Turner]

Module: Mesa
Branch: master
Commit: bfe0f3a7027c3104a6ddc662129091c8093e7410
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bfe0f3a7027c3104a6ddc662129091c8093e7410

Author: Kenneth Graunke <kenn...@whitecape.org>
Date:   Tue Oct 31 10:02:02 2017 -0700

i965: Move PIPE_CONTROL defines and prototypes to brw_pipe_control.h.

We need to be able to emit PIPE_CONTROLs from genX_state_upload.c,
which can't safely include brw_defines.h because it conflicts with
genxml.  Move all the PIPE_CONTROL related stuff together into a
separate header.

Reviewed-by: Matt Turner <matts...@gmail.com>

---

 src/mesa/drivers/dri/i965/brw_context.h   | 17 +
 src/mesa/drivers/dri/i965/brw_defines.h   | 43 -
 src/mesa/drivers/dri/i965/brw_pipe_control.h  | 89 +++
 src/mesa/drivers/dri/i965/genX_state_upload.c |  3 -
 4 files changed, 90 insertions(+), 62 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 0670483806..aa91380b96 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -37,6 +37,7 @@
 #include "main/macros.h"
 #include "main/mtypes.h"
 #include "brw_structs.h"
+#include "brw_pipe_control.h"
 #include "compiler/brw_compiler.h"
 
 #include "isl/isl.h"
@@ -1674,22 +1675,6 @@ bool
 gen9_use_linear_1d_layout(const struct brw_context *brw,
   const struct intel_mipmap_tree *mt);
 
-/* brw_pipe_control.c */
-int brw_init_pipe_control(struct brw_context *brw,
- const struct gen_device_info *info);
-void brw_fini_pipe_control(struct brw_context *brw);
-
-void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags);
-void brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
- struct brw_bo *bo, uint32_t offset,
- uint64_t imm);
-void brw_emit_end_of_pipe_sync(struct brw_context *brw, uint32_t flags);
-void brw_emit_mi_flush(struct brw_context *brw);
-void brw_emit_post_sync_nonzero_flush(struct brw_context *brw);
-void brw_emit_depth_stall_flushes(struct brw_context *brw);
-void gen7_emit_vs_workaround_flush(struct brw_context *brw);
-void gen7_emit_cs_stall_flush(struct brw_context *brw);
-
 /* brw_queryformat.c */
 void brw_query_internal_format(struct gl_context *ctx, GLenum target,
GLenum internalFormat, GLenum pname,
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 59d9e5cf21..99d41cf1a5 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1490,49 +1490,6 @@ enum brw_pixel_shader_coverage_mask_mode {
 #define MI_MATH_OPERAND_ZF   0x32
 #define MI_MATH_OPERAND_CF   0x33
 
-/** @{
- *
- * PIPE_CONTROL operation, a combination MI_FLUSH and register write with
- * additional flushing control.
- */
-#define _3DSTATE_PIPE_CONTROL  (CMD_3D | (3 << 27) | (2 << 24))
-#define PIPE_CONTROL_CS_STALL  (1 << 20)
-#define PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET   (1 << 19)
-#define PIPE_CONTROL_TLB_INVALIDATE(1 << 18)
-#define PIPE_CONTROL_SYNC_GFDT (1 << 17)
-#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1 << 16)
-#define PIPE_CONTROL_NO_WRITE  (0 << 14)
-#define PIPE_CONTROL_WRITE_IMMEDIATE   (1 << 14)
-#define PIPE_CONTROL_WRITE_DEPTH_COUNT (2 << 14)
-#define PIPE_CONTROL_WRITE_TIMESTAMP   (3 << 14)
-#define PIPE_CONTROL_DEPTH_STALL   (1 << 13)
-#define PIPE_CONTROL_RENDER_TARGET_FLUSH (1 << 12)
-#define PIPE_CONTROL_INSTRUCTION_INVALIDATE (1 << 11)
-#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE  (1 << 10) /* GM45+ only */
-#define PIPE_CONTROL_ISP_DIS   (1 << 9)
-#define PIPE_CONTROL_INTERRUPT_ENABLE  (1 << 8)
-#define PIPE_CONTROL_FLUSH_ENABLE  (1 << 7) /* Gen7+ only */
-/* GT */
-#define PIPE_CONTROL_DATA_CACHE_FLUSH  (1 << 5)
-#define PIPE_CONTROL_VF_CACHE_INVALIDATE   (1 << 4)
-#define PIPE_CONTROL_CONST_CACHE_INVALIDATE(1 << 3)
-#define PIPE_CONTROL_STATE_CACHE_INVALIDATE(1 << 2)
-#define PIPE_CONTROL_STALL_AT_SCOREBOARD   (1 << 1)
-#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0)
-#define PIPE_CONTROL_PPGTT_WRITE   (0 << 2)
-#define PIPE_CONTROL_GLOBAL_GTT_WRITE  (1 << 2)
-
-#define PIPE_CONTROL_CACHE_FLUSH_BITS \
-   (PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_DATA_CACHE_FLUSH | \
-PIPE_CONTROL_RENDER_TARGET_FLUSH)
-
-#define PIPE_CONTROL_CACHE_INVALIDATE_BITS \
-   (PIPE_CONTROL_STATE_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE 
| \
-PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | 
\
-PIPE_CONTROL_INSTRUCTION_INVALIDATE)
-
-

Mesa (master): util: Just give up and define PIPE_ARCH_LITTLE_ENDIAN on MSVC

[Matt Turner]

Module: Mesa
Branch: master
Commit: 676761252b731a6bf408e4dca694c31d74a995fc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=676761252b731a6bf408e4dca694c31d74a995fc

Author: Matt Turner <matts...@gmail.com>
Date:   Sat Nov 25 16:45:27 2017 -0800

util: Just give up and define PIPE_ARCH_LITTLE_ENDIAN on MSVC

MSVC doesn't support #warning?! Getting really tired of this.

---

 src/util/u_endian.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/util/u_endian.h b/src/util/u_endian.h
index 980b1ab2e1..50f94c578e 100644
--- a/src/util/u_endian.h
+++ b/src/util/u_endian.h
@@ -65,9 +65,10 @@
 # define PIPE_ARCH_BIG_ENDIAN
 #endif
 
-#endif
+#elif defined(_MSC_VER)
 
-#warning Unknown Endianness for this platform. Assuming little endian
 #define PIPE_ARCH_LITTLE_ENDIAN
 
 #endif
+
+#endif

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Mesa (master): util: Use preprocessor correctly

[Matt Turner]

Module: Mesa
Branch: master
Commit: b8cbad624b8198949d63c0211fe4925fc3bb9a7a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b8cbad624b8198949d63c0211fe4925fc3bb9a7a

Author: Matt Turner <matts...@gmail.com>
Date:   Sat Nov 25 15:56:43 2017 -0800

util: Use preprocessor correctly

Fixes: 6a353479a757 ("util: Assume little endian in the absence of
  platform-specific handling")

---

 src/util/u_endian.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/util/u_endian.h b/src/util/u_endian.h
index 3d5c006f35..980b1ab2e1 100644
--- a/src/util/u_endian.h
+++ b/src/util/u_endian.h
@@ -67,7 +67,7 @@
 
 #endif
 
-#warn Unknown Endianness for this platform. Assuming little endian
+#warning Unknown Endianness for this platform. Assuming little endian
 #define PIPE_ARCH_LITTLE_ENDIAN
 
 #endif

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Mesa (master): util: Fix SHA1 implementation on big endian

[Matt Turner]

Module: Mesa
Branch: master
Commit: 532674303a92c438cb1c48d224e9dee9dece91ec
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=532674303a92c438cb1c48d224e9dee9dece91ec

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Nov 22 22:39:51 2017 -0800

util: Fix SHA1 implementation on big endian

The code defines a macro blk0(i) based on the preprocessor condition
BYTE_ORDER == LITTLE_ENDIAN. If true, blk0(i) is defined as a byte swap
operation. Unfortunately, if the preprocessor macros used in the test
are no defined, then the comparison becomes 0 == 0 and it evaluates as
true.

Fixes: d1efa09d342b ("util: import sha1 implementation from OpenBSD")
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>

---

 src/util/sha1/sha1.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/util/sha1/sha1.c b/src/util/sha1/sha1.c
index ef59ea1dfc..f36a77c202 100644
--- a/src/util/sha1/sha1.c
+++ b/src/util/sha1/sha1.c
@@ -16,6 +16,7 @@
 
 #include 
 #include 
+#include "u_endian.h"
 #include "sha1.h"
 
 #define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits
@@ -24,7 +25,7 @@
  * blk0() and blk() perform the initial expand.
  * I got the idea of expanding during the round function from SSLeay
  */
-#if BYTE_ORDER == LITTLE_ENDIAN
+#ifdef PIPE_ARCH_LITTLE_ENDIAN
 # define blk0(i) (block->l[i] = (rol(block->l[i],24)&0xFF00FF00) \
 |(rol(block->l[i],8)&0x00FF00FF))
 #else

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Mesa (master): util: Add a SHA1 unit test program

[Matt Turner]

Module: Mesa
Branch: master
Commit: 513d7ffa23d42e96f831148fa13bf470087424c3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=513d7ffa23d42e96f831148fa13bf470087424c3

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Nov 22 15:10:47 2017 -0800

util: Add a SHA1 unit test program

Reviewed-by: Emil Velikov <emil.veli...@collabora.com>

---

 src/util/Makefile.am  |  3 ++-
 src/util/mesa-sha1_test.c | 65 +++
 2 files changed, 67 insertions(+), 1 deletion(-)

diff --git a/src/util/Makefile.am b/src/util/Makefile.am
index b57da3cd94..a5241ad27b 100644
--- a/src/util/Makefile.am
+++ b/src/util/Makefile.am
@@ -68,8 +68,9 @@ sysconf_DATA = drirc
 
 u_atomic_test_LDADD = libmesautil.la
 roundeven_test_LDADD = -lm
+mesa_sha1_test_LDADD = libmesautil.la
 
-check_PROGRAMS = u_atomic_test roundeven_test
+check_PROGRAMS = u_atomic_test roundeven_test mesa-sha1_test
 TESTS = $(check_PROGRAMS)
 
 BUILT_SOURCES = $(MESA_UTIL_GENERATED_FILES)
diff --git a/src/util/mesa-sha1_test.c b/src/util/mesa-sha1_test.c
new file mode 100644
index 00..9b3b477c7f
--- /dev/null
+++ b/src/util/mesa-sha1_test.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+
+#include "macros.h"
+#include "mesa-sha1.h"
+
+#define SHA1_LENGTH 40
+
+int main(int argc, char *argv[])
+{
+   static const struct {
+  const char *string;
+  const char *sha1;
+   } test_data[] = {
+  {"Mesa Rocks! 273", "7fb99737373d65a73f049cdabc01e73aa6bc60f3"},
+  {"Mesa Rocks! 300", "b2180263e37d3bed6a4be0afe41b1a82ebbcf4c3"},
+  {"Mesa Rocks! 583", "7fb9734108a62503e8a149c1051facd7fb112d05"},
+   };
+
+   bool failed = false;
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(test_data); i++) {
+  unsigned char sha1[20];
+  _mesa_sha1_compute(test_data[i].string, strlen(test_data[i].string),
+ sha1);
+
+  char buf[41];
+  _mesa_sha1_format(buf, sha1);
+
+  if (memcmp(test_data[i].sha1, buf, SHA1_LENGTH) != 0) {
+ printf("For string \"%s\", length %zu:\n"
+"\tExpected: %s\n\t Got: %s\n",
+test_data[i].string, strlen(test_data[i].string),
+test_data[i].sha1, buf);
+ failed = true;
+  }
+   }
+
+   return failed;
+}

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Mesa (master): util: Fix disk_cache index calculation on big endian

[Matt Turner]

Module: Mesa
Branch: master
Commit: c690a7a8cdfb6425547bbb782020098405851194
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c690a7a8cdfb6425547bbb782020098405851194

Author: Matt Turner <matts...@gmail.com>
Date:   Thu Nov 23 10:41:34 2017 -0800

util: Fix disk_cache index calculation on big endian

The cache-test test program attempts to create a collision (using key_a
and key_a_collide) by making the first two bytes identical. The idea is
fine -- the shader cache wants to use the first four characters of a
SHA1 hex digest as the index.

The following program

unsigned char array[4] = {1, 2, 3, 4};
int *ptr = (int *)array;

for (int i = 0; i < 4; i++) {
printf("%02x", array[i]);
}
printf("\n");

printf("%08x\n", *ptr);

prints

   01020304
   04030201

on little endian, and

   01020304
   01020304

on big endian.

On big endian platforms reading the character array back as an int (as
is done in disk_cache.c) does not yield the same results as reading the
byte array.

To get the first four characters of the SHA1 hex digest when we mask
with CACHE_INDEX_KEY_MASK, we need to byte swap the int on big endian
platforms.

Bugzilla: https://bugs.freedesktop.org/103668
Bugzilla: https://bugs.gentoo.org/637060
Bugzilla: https://bugs.gentoo.org/636326
Fixes: 87ab26b2ab35 ("glsl: Add initial functions to implement an
  on-disk cache")
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>

---

 src/util/disk_cache.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/util/disk_cache.c b/src/util/disk_cache.c
index fde6e2e097..e95406565e 100644
--- a/src/util/disk_cache.c
+++ b/src/util/disk_cache.c
@@ -1170,7 +1170,7 @@ void
 disk_cache_put_key(struct disk_cache *cache, const cache_key key)
 {
const uint32_t *key_chunk = (const uint32_t *) key;
-   int i = *key_chunk & CACHE_INDEX_KEY_MASK;
+   int i = CPU_TO_LE32(*key_chunk) & CACHE_INDEX_KEY_MASK;
unsigned char *entry;
 
entry = >stored_keys[i * CACHE_KEY_SIZE];
@@ -1189,7 +1189,7 @@ bool
 disk_cache_has_key(struct disk_cache *cache, const cache_key key)
 {
const uint32_t *key_chunk = (const uint32_t *) key;
-   int i = *key_chunk & CACHE_INDEX_KEY_MASK;
+   int i = CPU_TO_LE32(*key_chunk) & CACHE_INDEX_KEY_MASK;
unsigned char *entry;
 
entry = >stored_keys[i * CACHE_KEY_SIZE];

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Mesa (master): util: Assume little endian in the absence of platform-specific handling

[Matt Turner]

Module: Mesa
Branch: master
Commit: 6a353479a7577dcff7c7a31809f27b59270648fb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a353479a7577dcff7c7a31809f27b59270648fb

Author: Matt Turner <matts...@gmail.com>
Date:   Fri Nov 24 20:25:04 2017 -0800

util: Assume little endian in the absence of platform-specific handling

---

 src/util/u_endian.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/util/u_endian.h b/src/util/u_endian.h
index 7bbd7dc215..3d5c006f35 100644
--- a/src/util/u_endian.h
+++ b/src/util/u_endian.h
@@ -67,4 +67,7 @@
 
 #endif
 
+#warn Unknown Endianness for this platform. Assuming little endian
+#define PIPE_ARCH_LITTLE_ENDIAN
+
 #endif

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Mesa (master): i965/fs: Check ADD/MAD with immediates in satprop unit test

[Matt Turner]

Module: Mesa
Branch: master
Commit: beaea7abfa9f25460284f739fa50050a889ce6cd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=beaea7abfa9f25460284f739fa50050a889ce6cd

Author: Matt Turner <matts...@gmail.com>
Date:   Mon Nov 20 14:21:43 2017 -0800

i965/fs: Check ADD/MAD with immediates in satprop unit test

The gen had to be changed from 4 to 6 so that we could test MAD, which
is new on Gen6.

mad_imm_float_neg_mov_sat tests the case fixed by the previous commit.

Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>

---

 .../compiler/test_fs_saturate_propagation.cpp  | 126 -
 1 file changed, 125 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/test_fs_saturate_propagation.cpp 
b/src/intel/compiler/test_fs_saturate_propagation.cpp
index db47214399..360f735220 100644
--- a/src/intel/compiler/test_fs_saturate_propagation.cpp
+++ b/src/intel/compiler/test_fs_saturate_propagation.cpp
@@ -65,7 +65,7 @@ void saturate_propagation_test::SetUp()
 
v = new saturate_propagation_fs_visitor(compiler, prog_data, shader);
 
-   devinfo->gen = 4;
+   devinfo->gen = 6;
 }
 
 static fs_inst *
@@ -278,6 +278,44 @@ TEST_F(saturate_propagation_test, add_neg_mov_sat)
EXPECT_FALSE(instruction(block0, 1)->saturate);
 }
 
+TEST_F(saturate_propagation_test, add_imm_float_neg_mov_sat)
+{
+   const fs_builder  = v->bld;
+   fs_reg dst0 = v->vgrf(glsl_type::float_type);
+   fs_reg dst1 = v->vgrf(glsl_type::float_type);
+   fs_reg src0 = v->vgrf(glsl_type::float_type);
+   fs_reg src1 = brw_imm_f(1.0f);
+   bld.ADD(dst0, src0, src1);
+   dst0.negate = true;
+   set_saturate(true, bld.MOV(dst1, dst0));
+
+   /* = Before =
+*
+* 0: add(8)dst0  src0  1.0f
+* 1: mov.sat(8)dst1  -dst0
+*
+* = After =
+* 0: add.sat(8)dst0  -src0 -1.0f
+* 1: mov(8)dst1  dst0
+*/
+
+   v->calculate_cfg();
+   bblock_t *block0 = v->cfg->blocks[0];
+
+   EXPECT_EQ(0, block0->start_ip);
+   EXPECT_EQ(1, block0->end_ip);
+
+   EXPECT_TRUE(saturate_propagation(v));
+   EXPECT_EQ(0, block0->start_ip);
+   EXPECT_EQ(1, block0->end_ip);
+   EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
+   EXPECT_TRUE(instruction(block0, 0)->saturate);
+   EXPECT_TRUE(instruction(block0, 0)->src[0].negate);
+   EXPECT_EQ(instruction(block0, 0)->src[1].f, -1.0f);
+   EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode);
+   EXPECT_FALSE(instruction(block0, 1)->saturate);
+}
+
 TEST_F(saturate_propagation_test, mul_neg_mov_sat)
 {
const fs_builder  = v->bld;
@@ -316,6 +354,92 @@ TEST_F(saturate_propagation_test, mul_neg_mov_sat)
EXPECT_FALSE(instruction(block0, 1)->src[0].negate);
 }
 
+TEST_F(saturate_propagation_test, mad_neg_mov_sat)
+{
+   const fs_builder  = v->bld;
+   fs_reg dst0 = v->vgrf(glsl_type::float_type);
+   fs_reg dst1 = v->vgrf(glsl_type::float_type);
+   fs_reg src0 = v->vgrf(glsl_type::float_type);
+   fs_reg src1 = v->vgrf(glsl_type::float_type);
+   fs_reg src2 = v->vgrf(glsl_type::float_type);
+   bld.MAD(dst0, src0, src1, src2);
+   dst0.negate = true;
+   set_saturate(true, bld.MOV(dst1, dst0));
+
+   /* = Before =
+*
+* 0: mad(8)dst0  src0  src1 src2
+* 1: mov.sat(8)dst1  -dst0
+*
+* = After =
+* 0: mad.sat(8)dst0  -src0 -src1 src2
+* 1: mov(8)dst1  dst0
+*/
+
+   v->calculate_cfg();
+   bblock_t *block0 = v->cfg->blocks[0];
+
+   EXPECT_EQ(0, block0->start_ip);
+   EXPECT_EQ(1, block0->end_ip);
+
+   EXPECT_TRUE(saturate_propagation(v));
+   EXPECT_EQ(0, block0->start_ip);
+   EXPECT_EQ(1, block0->end_ip);
+   EXPECT_EQ(BRW_OPCODE_MAD, instruction(block0, 0)->opcode);
+   EXPECT_TRUE(instruction(block0, 0)->saturate);
+   EXPECT_TRUE(instruction(block0, 0)->src[0].negate);
+   EXPECT_TRUE(instruction(block0, 0)->src[1].negate);
+   EXPECT_FALSE(instruction(block0, 0)->src[2].negate);
+   EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode);
+   EXPECT_FALSE(instruction(block0, 1)->saturate);
+   EXPECT_FALSE(instruction(block0, 1)->src[0].negate);
+}
+
+TEST_F(saturate_propagation_test, mad_imm_float_neg_mov_sat)
+{
+   const fs_builder  = v->bld;
+   fs_reg dst0 = v->vgrf(glsl_type::float_type);
+   fs_reg dst1 = v->vgrf(glsl_type::float_type);
+   fs_reg src0 = brw_imm_f(1.0f);
+   fs_reg src1 = brw_imm_f(-2.0f);
+   fs_reg src2 = v->vgrf(glsl_type::float_type);
+   /* The builder for MAD tries to be helpful and not put immediates as direct
+* sources. We want to test specifically that case.
+*/
+   fs_inst *mad = bld.MAD(dst0, src2, src2, src2);
+   mad->src[0]= src0;
+   mad->src[1] = src1;
+   dst0.negate = true;
+   set_saturate(true, bld.MOV(dst1, dst0));
+
+   /* = Before =
+*
+* 0: mad(8)dst0  1.0f -2.0f src2
+* 1: mov.sat(8)dst1  -dst0
+*
+* = Aft

Mesa (master): i965/fs: Handle negating immediates on MADs when propagating saturates

[Matt Turner]

Module: Mesa
Branch: master
Commit: a05af1f7b8f82a38513bba31f9573cd62d82f18d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a05af1f7b8f82a38513bba31f9573cd62d82f18d

Author: Matt Turner <matts...@gmail.com>
Date:   Mon Nov 20 14:24:57 2017 -0800

i965/fs: Handle negating immediates on MADs when propagating saturates

MADs don't take immediate sources, but we allow them in the IR since it
simplifies a lot of things. I neglected to consider that case.

Fixes: 4009a9ead490 ("i965/fs: Allow saturate propagation to propagate
  negations into MADs.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103616
Reported-and-Tested-by: Ruslan Kabatsayev <b7.10110...@gmail.com>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>

---

 src/intel/compiler/brw_fs_saturate_propagation.cpp | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_fs_saturate_propagation.cpp 
b/src/intel/compiler/brw_fs_saturate_propagation.cpp
index 1c97a507d8..d6cfa79a61 100644
--- a/src/intel/compiler/brw_fs_saturate_propagation.cpp
+++ b/src/intel/compiler/brw_fs_saturate_propagation.cpp
@@ -88,8 +88,14 @@ opt_saturate_propagation_local(fs_visitor *v, bblock_t 
*block)
 scan_inst->src[0].negate = !scan_inst->src[0].negate;
 inst->src[0].negate = false;
  } else if (scan_inst->opcode == BRW_OPCODE_MAD) {
-scan_inst->src[0].negate = !scan_inst->src[0].negate;
-scan_inst->src[1].negate = !scan_inst->src[1].negate;
+for (int i = 0; i < 2; i++) {
+   if (scan_inst->src[i].file == IMM) {
+  brw_negate_immediate(scan_inst->src[i].type,
+   
_inst->src[i].as_brw_reg());
+   } else {
+  scan_inst->src[i].negate = 
!scan_inst->src[i].negate;
+   }
+}
 inst->src[0].negate = false;
  } else if (scan_inst->opcode == BRW_OPCODE_ADD) {
 if (scan_inst->src[1].file == IMM) {

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Mesa (master): i965: Move common code out of #ifdef

[Matt Turner]

Module: Mesa
Branch: master
Commit: f4276ef7ef4b92bdcb2f43b34ff95a3189fc0ce1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f4276ef7ef4b92bdcb2f43b34ff95a3189fc0ce1

Author: Matt Turner <matts...@gmail.com>
Date:   Thu Nov 16 13:35:01 2017 -0800

i965: Move common code out of #ifdef

I'm going to change the call in a later patch and with the difference in
indentation level it wasn't immediately obvious that the calls were
identical.

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/brw_fs_generator.cpp   | 7 ++-
 src/intel/compiler/brw_vec4_generator.cpp | 6 ++
 2 files changed, 4 insertions(+), 9 deletions(-)

diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index 46f9a338ea..96691ac3ff 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -2192,17 +2192,14 @@ fs_generator::generate_code(const cfg_t *cfg, int 
dispatch_width)
annotation_finalize(, p->next_insn_offset);
 
 #ifndef NDEBUG
-   bool validated = brw_validate_instructions(devinfo, p->store,
-  start_offset,
-  p->next_insn_offset,
-  );
+   bool validated =
 #else
if (unlikely(debug_flag))
+#endif
   brw_validate_instructions(devinfo, p->store,
 start_offset,
 p->next_insn_offset,
 );
-#endif
 
int before_size = p->next_insn_offset - start_offset;
brw_compact_instructions(p, start_offset, annotation.ann_count,
diff --git a/src/intel/compiler/brw_vec4_generator.cpp 
b/src/intel/compiler/brw_vec4_generator.cpp
index bde4110e54..63831e4ad6 100644
--- a/src/intel/compiler/brw_vec4_generator.cpp
+++ b/src/intel/compiler/brw_vec4_generator.cpp
@@ -2178,15 +2178,13 @@ generate_code(struct brw_codegen *p,
annotation_finalize(, p->next_insn_offset);
 
 #ifndef NDEBUG
-   bool validated = brw_validate_instructions(devinfo, p->store,
-  0, p->next_insn_offset,
-  );
+   bool validated =
 #else
if (unlikely(debug_flag))
+#endif
   brw_validate_instructions(devinfo, p->store,
 0, p->next_insn_offset,
 );
-#endif
 
int before_size = p->next_insn_offset;
brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann);

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Mesa (master): i965: Simplify annotation_insert_error()

[Matt Turner]

Module: Mesa
Branch: master
Commit: f80e97346b0da9fab3d60b46bdcf0a0d702f97c9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f80e97346b0da9fab3d60b46bdcf0a0d702f97c9

Author: Matt Turner <matts...@gmail.com>
Date:   Thu Nov 16 13:42:41 2017 -0800

i965: Simplify annotation_insert_error()

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/intel_asm_annotation.c | 15 ++-
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/src/intel/compiler/intel_asm_annotation.c 
b/src/intel/compiler/intel_asm_annotation.c
index b07a545a12..26ab4b9818 100644
--- a/src/intel/compiler/intel_asm_annotation.c
+++ b/src/intel/compiler/intel_asm_annotation.c
@@ -159,8 +159,6 @@ void
 annotation_insert_error(struct annotation_info *annotation, unsigned offset,
 const char *error)
 {
-   struct annotation *ann;
-
if (!annotation->ann_count)
   return;
 
@@ -175,7 +173,6 @@ annotation_insert_error(struct annotation_info *annotation, 
unsigned offset,
for (int i = 0; i < annotation->ann_count; i++) {
   struct annotation *cur = >ann[i];
   struct annotation *next = >ann[i + 1];
-  ann = cur;
 
   if (next->offset <= offset)
  continue;
@@ -190,11 +187,11 @@ annotation_insert_error(struct annotation_info 
*annotation, unsigned offset,
  next->block_start = NULL;
  annotation->ann_count++;
   }
-  break;
-   }
 
-   if (ann->error)
-  ralloc_strcat(>error, error);
-   else
-  ann->error = ralloc_strdup(annotation->mem_ctx, error);
+  if (cur->error)
+ ralloc_strcat(>error, error);
+  else
+ cur->error = ralloc_strdup(annotation->mem_ctx, error);
+  return;
+   }
 }

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Mesa (master): i965: Rename intel_asm_annotation -> brw_disasm_info

[Matt Turner]

Module: Mesa
Branch: master
Commit: 821ec473a862762b3e9d4004d062293fa27e102b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=821ec473a862762b3e9d4004d062293fa27e102b

Author: Matt Turner <matts...@gmail.com>
Date:   Thu Nov 16 11:43:51 2017 -0800

i965: Rename intel_asm_annotation -> brw_disasm_info

It was the only file named intel_* in the compiler.

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/Makefile.sources   | 6 +++---
 src/intel/compiler/{intel_asm_annotation.c => brw_disasm_info.c} | 2 +-
 src/intel/compiler/{intel_asm_annotation.h => brw_disasm_info.h} | 0
 src/intel/compiler/brw_eu.h  | 2 +-
 src/intel/compiler/brw_eu_compact.c  | 2 +-
 src/intel/compiler/meson.build   | 4 ++--
 6 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index 5a09e6d916..cdb10ece35 100644
--- a/src/intel/Makefile.sources
+++ b/src/intel/Makefile.sources
@@ -38,6 +38,8 @@ COMPILER_FILES = \
compiler/brw_dead_control_flow.cpp \
compiler/brw_dead_control_flow.h \
compiler/brw_disasm.c \
+   compiler/brw_disasm_info.c \
+   compiler/brw_disasm_info.h \
compiler/brw_eu.c \
compiler/brw_eu_compact.c \
compiler/brw_eu_defines.h \
@@ -115,9 +117,7 @@ COMPILER_FILES = \
compiler/brw_vue_map.c \
compiler/brw_wm_iz.cpp \
compiler/gen6_gs_visitor.cpp \
-   compiler/gen6_gs_visitor.h \
-   compiler/intel_asm_annotation.c \
-   compiler/intel_asm_annotation.h
+   compiler/gen6_gs_visitor.h
 
 COMPILER_GENERATED_FILES = \
compiler/brw_nir_trig_workarounds.c
diff --git a/src/intel/compiler/intel_asm_annotation.c 
b/src/intel/compiler/brw_disasm_info.c
similarity index 99%
rename from src/intel/compiler/intel_asm_annotation.c
rename to src/intel/compiler/brw_disasm_info.c
index 2ebe6dd846..3db79ede70 100644
--- a/src/intel/compiler/intel_asm_annotation.c
+++ b/src/intel/compiler/brw_disasm_info.c
@@ -23,8 +23,8 @@
 
 #include "brw_cfg.h"
 #include "brw_eu.h"
+#include "brw_disasm_info.h"
 #include "common/gen_debug.h"
-#include "intel_asm_annotation.h"
 #include "compiler/nir/nir.h"
 
 __attribute__((weak)) void nir_print_instr(const nir_instr *instr, FILE *fp) {}
diff --git a/src/intel/compiler/intel_asm_annotation.h 
b/src/intel/compiler/brw_disasm_info.h
similarity index 100%
rename from src/intel/compiler/intel_asm_annotation.h
rename to src/intel/compiler/brw_disasm_info.h
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index d66988da56..b5a206b3f1 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -37,7 +37,7 @@
 #include "brw_inst.h"
 #include "brw_eu_defines.h"
 #include "brw_reg.h"
-#include "intel_asm_annotation.h"
+#include "brw_disasm_info.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/src/intel/compiler/brw_eu_compact.c 
b/src/intel/compiler/brw_eu_compact.c
index d2edb5586c..8d33e2adff 100644
--- a/src/intel/compiler/brw_eu_compact.c
+++ b/src/intel/compiler/brw_eu_compact.c
@@ -74,7 +74,7 @@
 
 #include "brw_eu.h"
 #include "brw_shader.h"
-#include "intel_asm_annotation.h"
+#include "brw_disasm_info.h"
 #include "common/gen_debug.h"
 
 static const uint32_t g45_control_index_table[32] = {
diff --git a/src/intel/compiler/meson.build b/src/intel/compiler/meson.build
index d6fb8f4a64..fe0a1f6e8a 100644
--- a/src/intel/compiler/meson.build
+++ b/src/intel/compiler/meson.build
@@ -34,6 +34,8 @@ libintel_compiler_files = files(
   'brw_dead_control_flow.cpp',
   'brw_dead_control_flow.h',
   'brw_disasm.c',
+  'brw_disasm_info.c',
+  'brw_disasm_info.h',
   'brw_eu.c',
   'brw_eu_compact.c',
   'brw_eu_defines.h',
@@ -112,8 +114,6 @@ libintel_compiler_files = files(
   'brw_wm_iz.cpp',
   'gen6_gs_visitor.cpp',
   'gen6_gs_visitor.h',
-  'intel_asm_annotation.c',
-  'intel_asm_annotation.h',
 )
 
 brw_nir_trig = custom_target(

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Mesa (master): i965: Rewrite disassembly annotation code

[Matt Turner]

Module: Mesa
Branch: master
Commit: 4f82b17287194ca7d10816f6cfe4712a3e0a03fc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f82b17287194ca7d10816f6cfe4712a3e0a03fc

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Nov 15 17:08:42 2017 -0800

i965: Rewrite disassembly annotation code

The old code used an array to store each "instruction group" (the new,
better name than the old overloaded "annotation"), and required a
memmove() to shift elements over in the array when we needed to split a
group so that we could add an error message. This was confusing and
difficult to get right, not the least of which was  because the array
has a tail sentinel not included in .ann_count.

Instead use a linked list, a data structure made for efficient
insertion.

Acked-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/brw_compile_clip.c |   2 +-
 src/intel/compiler/brw_eu.h   |   4 +-
 src/intel/compiler/brw_eu_compact.c   |  26 +++--
 src/intel/compiler/brw_eu_validate.c  |   6 +-
 src/intel/compiler/brw_fs_generator.cpp   |  21 ++--
 src/intel/compiler/brw_vec4_generator.cpp |  18 ++--
 src/intel/compiler/intel_asm_annotation.c | 169 +++---
 src/intel/compiler/intel_asm_annotation.h |  39 ---
 src/intel/compiler/test_eu_validate.cpp   |  17 ++-
 src/intel/tools/disasm.c  |  41 
 src/mesa/drivers/dri/i965/brw_ff_gs.c |   2 +-
 11 files changed, 174 insertions(+), 171 deletions(-)

diff --git a/src/intel/compiler/brw_compile_clip.c 
b/src/intel/compiler/brw_compile_clip.c
index 83788e4b64..c04d1a8277 100644
--- a/src/intel/compiler/brw_compile_clip.c
+++ b/src/intel/compiler/brw_compile_clip.c
@@ -79,7 +79,7 @@ brw_compile_clip(const struct brw_compiler *compiler,
   unreachable("not reached");
}
 
-   brw_compact_instructions(, 0, 0, NULL);
+   brw_compact_instructions(, 0, NULL);
 
*prog_data = c.prog_data;
 
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 95503d5513..d66988da56 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -548,7 +548,7 @@ enum brw_conditional_mod brw_swap_cmod(uint32_t cmod);
 /* brw_eu_compact.c */
 void brw_init_compaction_tables(const struct gen_device_info *devinfo);
 void brw_compact_instructions(struct brw_codegen *p, int start_offset,
-  int num_annotations, struct annotation 
*annotation);
+  struct disasm_info *disasm);
 void brw_uncompact_instruction(const struct gen_device_info *devinfo,
brw_inst *dst, brw_compact_inst *src);
 bool brw_try_compact_instruction(const struct gen_device_info *devinfo,
@@ -560,7 +560,7 @@ void brw_debug_compact_uncompact(const struct 
gen_device_info *devinfo,
 /* brw_eu_validate.c */
 bool brw_validate_instructions(const struct gen_device_info *devinfo,
const void *assembly, int start_offset, int 
end_offset,
-   struct annotation_info *annotation);
+   struct disasm_info *disasm);
 
 static inline int
 next_offset(const struct gen_device_info *devinfo, void *store, int offset)
diff --git a/src/intel/compiler/brw_eu_compact.c 
b/src/intel/compiler/brw_eu_compact.c
index a9da46957a..d2edb5586c 100644
--- a/src/intel/compiler/brw_eu_compact.c
+++ b/src/intel/compiler/brw_eu_compact.c
@@ -1486,7 +1486,7 @@ brw_init_compaction_tables(const struct gen_device_info 
*devinfo)
 
 void
 brw_compact_instructions(struct brw_codegen *p, int start_offset,
- int num_annotations, struct annotation *annotation)
+ struct disasm_info *disasm)
 {
if (unlikely(INTEL_DEBUG & DEBUG_NO_COMPACTION))
   return;
@@ -1501,7 +1501,7 @@ brw_compact_instructions(struct brw_codegen *p, int 
start_offset,
/* For an instruction at byte offset 8*i after compaction, this was its IP
 * (in 16-byte units) before compaction.
 */
-   int old_ip[(p->next_insn_offset - start_offset) / sizeof(brw_compact_inst)];
+   int old_ip[(p->next_insn_offset - start_offset) / sizeof(brw_compact_inst) 
+ 1];
 
if (devinfo->gen == 4 && !devinfo->is_g4x)
   return;
@@ -1556,6 +1556,12 @@ brw_compact_instructions(struct brw_codegen *p, int 
start_offset,
   }
}
 
+   /* Add an entry for the ending offset of the program. This greatly
+* simplifies the linked list walk at the end of the function.
+*/
+   old_ip[offset / sizeof(brw_compact_inst)] =
+  (p->next_insn_offset - start_offset) / sizeof(brw_inst);
+
/* Fix up control flow offsets. */
p->next_insn_offset = start_offset + offset;
for (offset = 0; offset < p->next_insn_offset - start_offset;
@@ -1651,21 +1657,21 @@ brw_compact_instructions(struct br

Mesa (master): Revert "intel/fs: Use a pure vertical stride for large register strides"

[Matt Turner]

Module: Mesa
Branch: master
Commit: a31d0382084c8aa860ffcef9b12592c5c44e192f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a31d0382084c8aa860ffcef9b12592c5c44e192f

Author: Matt Turner <matts...@gmail.com>
Date:   Tue Nov 14 11:24:08 2017 -0800

Revert "intel/fs: Use a pure vertical stride for large register strides"

This reverts commit e8c9e65185de3e821e1e482e77906d1d51efa3ec.

With the actual bug fixed (by commit 6ac2d1690192), this is not
necessary. I'm doubtful of its correctness in any case.

---

 src/intel/compiler/brw_fs_generator.cpp | 16 +++-
 1 file changed, 3 insertions(+), 13 deletions(-)

diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index 5b1121aa01..46f9a338ea 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -90,19 +90,9 @@ brw_reg_from_fs_reg(const struct gen_device_info *devinfo, 
fs_inst *inst,
   *   different execution size when the number of components
   *   written to each destination GRF is not the same.
   */
- if (reg->stride > 4) {
-/* For registers with an exceptionally large stride, we use a
- * width of 1 and only use the vertical stride.  This only works
- * for sources since destinations require hstride == 1.
- */
-assert(reg != >dst);
-brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
-brw_reg = stride(brw_reg, reg->stride, 1, 0);
- } else {
-const unsigned width = MIN2(reg_width, phys_width);
-brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg), reg->nr, 0);
-brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride);
- }
+ const unsigned width = MIN2(reg_width, phys_width);
+ brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg), reg->nr, 0);
+ brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride);
 
  if (devinfo->gen == 7 && !devinfo->is_haswell) {
 /* From the IvyBridge PRM (EU Changes by Processor Generation, 
page 13):

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Mesa (master): i965/fs: Fix extract_i8/u8 to a 64-bit destination

[Matt Turner]

Module: Mesa
Branch: master
Commit: 6ac2d16901927013393f873a34c717ece5014c1a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ac2d16901927013393f873a34c717ece5014c1a

Author: Matt Turner <matts...@gmail.com>
Date:   Fri Nov 10 14:00:24 2017 -0800

i965/fs: Fix extract_i8/u8 to a 64-bit destination

The MOV instruction can extract bytes to words/double words, and
words/double words to quadwords, but not byte to quadwords.

For unsigned byte to quadword, we can read them as words and AND off the
high byte and extract to quadword in one instruction. For signed bytes,
we need to first sign extend to word and the sign extend that word to a
quadword.

Fixes the following test on CHV, BXT, and GLK:
   KHR-GL46.shader_ballot_tests.ShaderBallotBitmasks
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103628
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>

---

 src/intel/compiler/brw_fs_nir.cpp | 25 +++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp
index 38d0d357e8..ca3707db90 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -1395,10 +1395,31 @@ fs_visitor::nir_emit_alu(const fs_builder , 
nir_alu_instr *instr)
 
case nir_op_extract_u8:
case nir_op_extract_i8: {
-  const brw_reg_type type = brw_int_type(1, instr->op == 
nir_op_extract_i8);
   nir_const_value *byte = nir_src_as_const_value(instr->src[1].src);
   assert(byte != NULL);
-  bld.MOV(result, subscript(op[0], type, byte->u32[0]));
+
+  /* The PRMs say:
+   *
+   *BDW+
+   *There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
+   *Use two instructions and a word or DWord intermediate integer type.
+   */
+  if (nir_dest_bit_size(instr->dest.dest) == 64) {
+ const brw_reg_type type = brw_int_type(2, instr->op == 
nir_op_extract_i8);
+
+ if (instr->op == nir_op_extract_i8) {
+/* If we need to sign extend, extract to a word first */
+fs_reg w_temp = bld.vgrf(BRW_REGISTER_TYPE_W);
+bld.MOV(w_temp, subscript(op[0], type, byte->u32[0]));
+bld.MOV(result, w_temp);
+ } else {
+/* Otherwise use an AND with 0xff and a word type */
+bld.AND(result, subscript(op[0], type, byte->u32[0] / 2), 
brw_imm_uw(0xff));
+ }
+  } else {
+ const brw_reg_type type = brw_int_type(1, instr->op == 
nir_op_extract_i8);
+ bld.MOV(result, subscript(op[0], type, byte->u32[0]));
+  }
   break;
}
 

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Mesa (master): i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLK

[Matt Turner]

Module: Mesa
Branch: master
Commit: cfcfa0b9cd1b1d563a988b1250950057c4612ac9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cfcfa0b9cd1b1d563a988b1250950057c4612ac9

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Nov  8 15:14:19 2017 -0800

i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLK

Fixes the following tests on CHV, BXT, and GLK:
KHR-GL46.shader_ballot_tests.ShaderBallotFunctionBallot
dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint32_to_int64
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103115

---

 src/intel/compiler/brw_fs_nir.cpp | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp
index 15f2d88624..38d0d357e8 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -725,8 +725,12 @@ fs_visitor::nir_emit_alu(const fs_builder , 
nir_alu_instr *instr)
   break;
 
case nir_op_f2f64:
+   case nir_op_f2i64:
+   case nir_op_f2u64:
case nir_op_i2f64:
+   case nir_op_i2i64:
case nir_op_u2f64:
+   case nir_op_u2u64:
   /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
*
*"When source or destination is 64b (...), regioning in Align1
@@ -754,12 +758,8 @@ fs_visitor::nir_emit_alu(const fs_builder , 
nir_alu_instr *instr)
case nir_op_f2f32:
case nir_op_f2i32:
case nir_op_f2u32:
-   case nir_op_f2i64:
-   case nir_op_f2u64:
case nir_op_i2i32:
-   case nir_op_i2i64:
case nir_op_u2u32:
-   case nir_op_u2u64:
   inst = bld.MOV(result, op[0]);
   inst->saturate = instr->dest.saturate;
   break;

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Mesa (master): nir: Don' t print swizzles when there are more than 4 components

[Matt Turner]

Module: Mesa
Branch: master
Commit: 77a63d190a9bd6bcb6d6d8eb9bc734c0b18ee0e3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=77a63d190a9bd6bcb6d6d8eb9bc734c0b18ee0e3

Author: Matt Turner <matts...@gmail.com>
Date:   Fri Oct 27 18:15:46 2017 -0700

nir: Don't print swizzles when there are more than 4 components

... as can happen with various types like mat4, or else we'll smash the
stack writing past the end of components_local[].

Fixes: 5a0d3e1129b7 ("nir: Print the components referenced for split or
  packed shader in/outs.")
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>

---

 src/compiler/nir/nir_print.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c
index 4b7ad5c6ba..fcc8025346 100644
--- a/src/compiler/nir/nir_print.c
+++ b/src/compiler/nir/nir_print.c
@@ -457,7 +457,7 @@ print_var_decl(nir_variable *var, print_state *state)
   switch (var->data.mode) {
   case nir_var_shader_in:
   case nir_var_shader_out:
- if (num_components != 4 && num_components != 0) {
+ if (num_components < 4 && num_components != 0) {
 const char *xyzw = "xyzw";
 for (int i = 0; i < num_components; i++)
components_local[i + 1] = xyzw[i + var->data.location_frac];

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Mesa (master): i965: Print subreg in units of type-size on ternary instructions

[Matt Turner]

Module: Mesa
Branch: master
Commit: ba50b538af81164476bb79fd686b48c2d43a0b22
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba50b538af81164476bb79fd686b48c2d43a0b22

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Jun 14 15:05:39 2017 -0700

i965: Print subreg in units of type-size on ternary instructions

The instruction word contains SubRegNum[4:2] so it's in units of dwords
(hence the * 4 to get it in terms of bytes). Before this patch, the
subreg would have been wrong for DF arguments.

Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>

---

 src/intel/compiler/brw_disasm.c | 31 ++-
 1 file changed, 26 insertions(+), 5 deletions(-)

diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index 2043d64b27..8bcd3d35cd 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -764,6 +764,12 @@ dest_3src(FILE *file, const struct gen_device_info 
*devinfo, const brw_inst *ins
 {
int err = 0;
uint32_t reg_file;
+   enum brw_reg_type type =
+  brw_hw_3src_type_to_reg_type(devinfo,
+   brw_inst_3src_dst_type(devinfo, inst));
+   unsigned dst_subreg_nr =
+  brw_inst_3src_dst_subreg_nr(devinfo, inst) * 4 /
+  brw_reg_type_to_size(type);
 
if (devinfo->gen == 6 && brw_inst_3src_dst_reg_file(devinfo, inst))
   reg_file = BRW_MESSAGE_REGISTER_FILE;
@@ -773,8 +779,8 @@ dest_3src(FILE *file, const struct gen_device_info 
*devinfo, const brw_inst *ins
err |= reg(file, reg_file, brw_inst_3src_dst_reg_nr(devinfo, inst));
if (err == -1)
   return 0;
-   if (brw_inst_3src_dst_subreg_nr(devinfo, inst))
-  format(file, ".%"PRIu64, brw_inst_3src_dst_subreg_nr(devinfo, inst));
+   if (dst_subreg_nr)
+  format(file, ".%u", dst_subreg_nr);
string(file, "<1>");
err |= control(file, "writemask", writemask,
   brw_inst_3src_dst_writemask(devinfo, inst), NULL);
@@ -928,7 +934,12 @@ static int
 src0_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst 
*inst)
 {
int err = 0;
-   unsigned src0_subreg_nr = brw_inst_3src_src0_subreg_nr(devinfo, inst);
+   enum brw_reg_type type =
+  brw_hw_3src_type_to_reg_type(devinfo,
+   brw_inst_3src_src_type(devinfo, inst));
+   unsigned src0_subreg_nr =
+  brw_inst_3src_src0_subreg_nr(devinfo, inst) * 4 /
+  brw_reg_type_to_size(type);
 
err |= control(file, "negate", m_negate,
   brw_inst_3src_src0_negate(devinfo, inst), NULL);
@@ -955,7 +966,12 @@ static int
 src1_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst 
*inst)
 {
int err = 0;
-   unsigned src1_subreg_nr = brw_inst_3src_src1_subreg_nr(devinfo, inst);
+   enum brw_reg_type type =
+  brw_hw_3src_type_to_reg_type(devinfo,
+   brw_inst_3src_src_type(devinfo, inst));
+   unsigned src1_subreg_nr =
+  brw_inst_3src_src1_subreg_nr(devinfo, inst) * 4 /
+  brw_reg_type_to_size(type);
 
err |= control(file, "negate", m_negate,
   brw_inst_3src_src1_negate(devinfo, inst), NULL);
@@ -983,7 +999,12 @@ static int
 src2_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst 
*inst)
 {
int err = 0;
-   unsigned src2_subreg_nr = brw_inst_3src_src2_subreg_nr(devinfo, inst);
+   enum brw_reg_type type =
+  brw_hw_3src_type_to_reg_type(devinfo,
+   brw_inst_3src_src_type(devinfo, inst));
+   unsigned src2_subreg_nr =
+  brw_inst_3src_src2_subreg_nr(devinfo, inst) * 4 /
+  brw_reg_type_to_size(type);
 
err |= control(file, "negate", m_negate,
   brw_inst_3src_src2_negate(devinfo, inst), NULL);

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Mesa (master): i965: Add align1 ternary instruction support to conversion functions

[Matt Turner]

Module: Mesa
Branch: master
Commit: 3b2c868848c12ea772ac818c0833850a2940eb7e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b2c868848c12ea772ac818c0833850a2940eb7e

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Jun 14 14:49:31 2017 -0700

i965: Add align1 ternary instruction support to conversion functions

Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>

---

 src/intel/compiler/brw_disasm.c   | 16 ++-
 src/intel/compiler/brw_inst.h |  4 +-
 src/intel/compiler/brw_reg_type.c | 99 ---
 src/intel/compiler/brw_reg_type.h | 16 +--
 4 files changed, 101 insertions(+), 34 deletions(-)

diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index e91961028e..ef7f623ceb 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -764,9 +764,7 @@ dest_3src(FILE *file, const struct gen_device_info 
*devinfo, const brw_inst *ins
 {
int err = 0;
uint32_t reg_file;
-   enum brw_reg_type type =
-  brw_hw_3src_type_to_reg_type(devinfo,
-   brw_inst_3src_a16_dst_hw_type(devinfo, 
inst));
+   enum brw_reg_type type = brw_inst_3src_a16_dst_type(devinfo, inst);
unsigned dst_subreg_nr =
   brw_inst_3src_a16_dst_subreg_nr(devinfo, inst) * 4 /
   brw_reg_type_to_size(type);
@@ -934,9 +932,7 @@ static int
 src0_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst 
*inst)
 {
int err = 0;
-   enum brw_reg_type type =
-  brw_hw_3src_type_to_reg_type(devinfo,
-   brw_inst_3src_a16_src_hw_type(devinfo, 
inst));
+   enum brw_reg_type type = brw_inst_3src_a16_src_type(devinfo, inst);
unsigned src0_subreg_nr =
   brw_inst_3src_a16_src0_subreg_nr(devinfo, inst) * 4 /
   brw_reg_type_to_size(type);
@@ -966,9 +962,7 @@ static int
 src1_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst 
*inst)
 {
int err = 0;
-   enum brw_reg_type type =
-  brw_hw_3src_type_to_reg_type(devinfo,
-   brw_inst_3src_a16_src_hw_type(devinfo, 
inst));
+   enum brw_reg_type type = brw_inst_3src_a16_src_type(devinfo, inst);
unsigned src1_subreg_nr =
   brw_inst_3src_a16_src1_subreg_nr(devinfo, inst) * 4 /
   brw_reg_type_to_size(type);
@@ -999,9 +993,7 @@ static int
 src2_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst 
*inst)
 {
int err = 0;
-   enum brw_reg_type type =
-  brw_hw_3src_type_to_reg_type(devinfo,
-   brw_inst_3src_a16_src_hw_type(devinfo, 
inst));
+   enum brw_reg_type type = brw_inst_3src_a16_src_type(devinfo, inst);
unsigned src2_subreg_nr =
   brw_inst_3src_a16_src2_subreg_nr(devinfo, inst) * 4 /
   brw_reg_type_to_size(type);
diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h
index 0cc1a3e911..1ddee77164 100644
--- a/src/intel/compiler/brw_inst.h
+++ b/src/intel/compiler/brw_inst.h
@@ -251,7 +251,7 @@ static inline void  
  \
 brw_inst_set_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
brw_inst *inst, enum brw_reg_type type)\
 { \
-   unsigned hw_type = brw_reg_type_to_hw_3src_type(devinfo, type);\
+   unsigned hw_type = brw_reg_type_to_a16_hw_3src_type(devinfo, type);\
brw_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \
 } \
   \
@@ -260,7 +260,7 @@ brw_inst_3src_a16_##reg##_type(const struct gen_device_info 
*devinfo, \
const brw_inst *inst)  \
 { \
unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst);   \
-   return brw_hw_3src_type_to_reg_type(devinfo, hw_type); \
+   return brw_a16_hw_3src_type_to_reg_type(devinfo, hw_type); \
 }
 
 REG_TYPE(dst)
diff --git a/src/intel/compiler/brw_reg_type.c 
b/src/intel/compiler/brw_reg_type.c
index f5aadf88bb..b7fff0867f 100644
--- a/src/intel/compiler/brw_reg_type.c
+++ b/src/intel/compiler/brw_reg_type.c
@@ -84,20 +84,57 @@ static const struct {
  * and unsigned doublewords, so a new field is also available in the da3src
  * struct (part of struct brw_instruction.bits1 in brw_structs.h) to select
  * dst and shared-src types.
+ *
+ * CNL adds support for 3-src instructions in align1 mode, and with it support
+ * for most register types.
  */
 enum hw_3src_reg_type {
GEN7_3SRC_TYPE_F  = 0,
GEN7_3SRC_TYPE_D  = 1,
GEN7_3SRC_TYPE_UD = 2,
GEN7_3SRC_TYPE_DF = 3,
+

Mesa (master): i965: Rename brw_inst 3src functions in preparation for align1

[Matt Turner]

Module: Mesa
Branch: master
Commit: e7f3b82e033f7c963386e89780a8b652611d0f32
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e7f3b82e033f7c963386e89780a8b652611d0f32

Author: Matt Turner <matts...@gmail.com>
Date:   Tue Jun  6 15:43:23 2017 -0700

i965: Rename brw_inst 3src functions in preparation for align1

Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>

---

 src/intel/compiler/brw_disasm.c | 46 +++
 src/intel/compiler/brw_eu_compact.c | 30 -
 src/intel/compiler/brw_eu_emit.c| 48 -
 src/intel/compiler/brw_inst.h   | 54 ++---
 4 files changed, 92 insertions(+), 86 deletions(-)

diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index 8bcd3d35cd..b70e8a5186 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -766,12 +766,12 @@ dest_3src(FILE *file, const struct gen_device_info 
*devinfo, const brw_inst *ins
uint32_t reg_file;
enum brw_reg_type type =
   brw_hw_3src_type_to_reg_type(devinfo,
-   brw_inst_3src_dst_type(devinfo, inst));
+   brw_inst_3src_a16_dst_type(devinfo, inst));
unsigned dst_subreg_nr =
-  brw_inst_3src_dst_subreg_nr(devinfo, inst) * 4 /
+  brw_inst_3src_a16_dst_subreg_nr(devinfo, inst) * 4 /
   brw_reg_type_to_size(type);
 
-   if (devinfo->gen == 6 && brw_inst_3src_dst_reg_file(devinfo, inst))
+   if (devinfo->gen == 6 && brw_inst_3src_a16_dst_reg_file(devinfo, inst))
   reg_file = BRW_MESSAGE_REGISTER_FILE;
else
   reg_file = BRW_GENERAL_REGISTER_FILE;
@@ -783,9 +783,9 @@ dest_3src(FILE *file, const struct gen_device_info 
*devinfo, const brw_inst *ins
   format(file, ".%u", dst_subreg_nr);
string(file, "<1>");
err |= control(file, "writemask", writemask,
-  brw_inst_3src_dst_writemask(devinfo, inst), NULL);
+  brw_inst_3src_a16_dst_writemask(devinfo, inst), NULL);
err |= control(file, "dest reg encoding", three_source_reg_encoding,
-  brw_inst_3src_dst_type(devinfo, inst), NULL);
+  brw_inst_3src_a16_dst_type(devinfo, inst), NULL);
 
return 0;
 }
@@ -936,9 +936,9 @@ src0_3src(FILE *file, const struct gen_device_info 
*devinfo, const brw_inst *ins
int err = 0;
enum brw_reg_type type =
   brw_hw_3src_type_to_reg_type(devinfo,
-   brw_inst_3src_src_type(devinfo, inst));
+   brw_inst_3src_a16_src_type(devinfo, inst));
unsigned src0_subreg_nr =
-  brw_inst_3src_src0_subreg_nr(devinfo, inst) * 4 /
+  brw_inst_3src_a16_src0_subreg_nr(devinfo, inst) * 4 /
   brw_reg_type_to_size(type);
 
err |= control(file, "negate", m_negate,
@@ -949,16 +949,16 @@ src0_3src(FILE *file, const struct gen_device_info 
*devinfo, const brw_inst *ins
   brw_inst_3src_src0_reg_nr(devinfo, inst));
if (err == -1)
   return 0;
-   if (src0_subreg_nr || brw_inst_3src_src0_rep_ctrl(devinfo, inst))
+   if (src0_subreg_nr || brw_inst_3src_a16_src0_rep_ctrl(devinfo, inst))
   format(file, ".%d", src0_subreg_nr);
-   if (brw_inst_3src_src0_rep_ctrl(devinfo, inst))
+   if (brw_inst_3src_a16_src0_rep_ctrl(devinfo, inst))
   string(file, "<0,1,0>");
else {
   string(file, "<4,4,1>");
-  err |= src_swizzle(file, brw_inst_3src_src0_swizzle(devinfo, inst));
+  err |= src_swizzle(file, brw_inst_3src_a16_src0_swizzle(devinfo, inst));
}
err |= control(file, "src da16 reg type", three_source_reg_encoding,
-  brw_inst_3src_src_type(devinfo, inst), NULL);
+  brw_inst_3src_a16_src_type(devinfo, inst), NULL);
return err;
 }
 
@@ -968,9 +968,9 @@ src1_3src(FILE *file, const struct gen_device_info 
*devinfo, const brw_inst *ins
int err = 0;
enum brw_reg_type type =
   brw_hw_3src_type_to_reg_type(devinfo,
-   brw_inst_3src_src_type(devinfo, inst));
+   brw_inst_3src_a16_src_type(devinfo, inst));
unsigned src1_subreg_nr =
-  brw_inst_3src_src1_subreg_nr(devinfo, inst) * 4 /
+  brw_inst_3src_a16_src1_subreg_nr(devinfo, inst) * 4 /
   brw_reg_type_to_size(type);
 
err |= control(file, "negate", m_negate,
@@ -981,16 +981,16 @@ src1_3src(FILE *file, const struct gen_device_info 
*devinfo, const brw_inst *ins
   brw_inst_3src_src1_reg_nr(devinfo, inst));
if (err == -1)
   return 0;
-   if (src1_subreg_nr || brw_inst_3src_src1_rep_ctrl(devinfo, inst))
+   if (src1_subreg_nr || brw_inst_3src_a16_src1_rep_ctrl(devinfo, inst))
   format(file, ".%d", src1_subreg_nr);
-   if (brw_inst_3src_src1_rep_

Mesa (master): i965: Add align1 ternary instruction disassembler support

[Matt Turner]

Module: Mesa
Branch: master
Commit: f11fa5ac6c5f955097c79e6bf27cd1a437c90ca5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f11fa5ac6c5f955097c79e6bf27cd1a437c90ca5

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Jun 14 16:04:07 2017 -0700

i965: Add align1 ternary instruction disassembler support

Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>

---

 src/intel/compiler/brw_disasm.c | 352 +---
 src/intel/compiler/brw_eu_defines.h |  11 --
 2 files changed, 288 insertions(+), 75 deletions(-)

diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index ef7f623ceb..1a94ed3954 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -30,6 +30,7 @@
 #include "brw_reg.h"
 #include "brw_inst.h"
 #include "brw_eu.h"
+#include "util/half_float.h"
 
 static bool
 has_jip(const struct gen_device_info *devinfo, enum opcode opcode)
@@ -237,13 +238,6 @@ static const char *const access_mode[2] = {
[1] = "align16",
 };
 
-static const char *const three_source_reg_encoding[] = {
-   [BRW_3SRC_TYPE_F]  = "F",
-   [BRW_3SRC_TYPE_D]  = "D",
-   [BRW_3SRC_TYPE_UD] = "UD",
-   [BRW_3SRC_TYPE_DF] = "DF",
-};
-
 static const char *const reg_file[4] = {
[0] = "A",
[1] = "g",
@@ -762,14 +756,15 @@ dest(FILE *file, const struct gen_device_info *devinfo, 
const brw_inst *inst)
 static int
 dest_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst 
*inst)
 {
+   bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
int err = 0;
uint32_t reg_file;
-   enum brw_reg_type type = brw_inst_3src_a16_dst_type(devinfo, inst);
-   unsigned dst_subreg_nr =
-  brw_inst_3src_a16_dst_subreg_nr(devinfo, inst) * 4 /
-  brw_reg_type_to_size(type);
+   unsigned subreg_nr;
+   enum brw_reg_type type;
 
-   if (devinfo->gen == 6 && brw_inst_3src_a16_dst_reg_file(devinfo, inst))
+   if (is_align1 && brw_inst_3src_a1_dst_reg_file(devinfo, inst))
+  reg_file = BRW_ARCHITECTURE_REGISTER_FILE;
+   else if (devinfo->gen == 6 && brw_inst_3src_a16_dst_reg_file(devinfo, inst))
   reg_file = BRW_MESSAGE_REGISTER_FILE;
else
   reg_file = BRW_GENERAL_REGISTER_FILE;
@@ -777,13 +772,25 @@ dest_3src(FILE *file, const struct gen_device_info 
*devinfo, const brw_inst *ins
err |= reg(file, reg_file, brw_inst_3src_dst_reg_nr(devinfo, inst));
if (err == -1)
   return 0;
-   if (dst_subreg_nr)
-  format(file, ".%u", dst_subreg_nr);
+
+   if (is_align1) {
+  type = brw_inst_3src_a1_dst_type(devinfo, inst);
+  subreg_nr = brw_inst_3src_a1_dst_subreg_nr(devinfo, inst);
+   } else {
+  type = brw_inst_3src_a16_dst_type(devinfo, inst);
+  subreg_nr = brw_inst_3src_a16_dst_subreg_nr(devinfo, inst) * 4;
+   }
+   subreg_nr /= brw_reg_type_to_size(type);
+
+   if (subreg_nr)
+  format(file, ".%u", subreg_nr);
string(file, "<1>");
-   err |= control(file, "writemask", writemask,
-  brw_inst_3src_a16_dst_writemask(devinfo, inst), NULL);
-   err |= control(file, "dest reg encoding", three_source_reg_encoding,
-  brw_inst_3src_a16_dst_hw_type(devinfo, inst), NULL);
+
+   if (!is_align1) {
+  err |= control(file, "writemask", writemask,
+ brw_inst_3src_a16_dst_writemask(devinfo, inst), NULL);
+   }
+   string(file, brw_reg_type_to_letters(type));
 
return 0;
 }
@@ -928,33 +935,161 @@ src_da16(FILE *file,
return err;
 }
 
+static enum brw_vertical_stride
+vstride_from_align1_3src_vstride(enum gen10_align1_3src_vertical_stride 
vstride)
+{
+   switch (vstride) {
+   case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0: return BRW_VERTICAL_STRIDE_0;
+   case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2: return BRW_VERTICAL_STRIDE_2;
+   case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4: return BRW_VERTICAL_STRIDE_4;
+   case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8: return BRW_VERTICAL_STRIDE_8;
+   default:
+  unreachable("not reached");
+   }
+}
+
+static enum brw_horizontal_stride
+hstride_from_align1_3src_hstride(enum gen10_align1_3src_src_horizontal_stride 
hstride)
+{
+   switch (hstride) {
+   case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0: return 
BRW_HORIZONTAL_STRIDE_0;
+   case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1: return 
BRW_HORIZONTAL_STRIDE_1;
+   case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2: return 
BRW_HORIZONTAL_STRIDE_2;
+   case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4: return 
BRW_HORIZONTAL_STRIDE_4;
+   default:
+  unreachable("not reached");
+   }
+}
+
+static enum brw_vertical_stride
+vstride_from_align1_3src_hstride(enum gen10_align1_3src_src_horizontal_stride 
hstride)
+{
+   switch (hstride) {
+   case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0: return B

Mesa (master): i965: Add functions for brw_reg_type <-> hw 3src type

[Matt Turner]

Module: Mesa
Branch: master
Commit: 3f14150e9ac9478bbbe4a93b9bb449d740971958
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f14150e9ac9478bbbe4a93b9bb449d740971958

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Jun 14 14:08:32 2017 -0700

i965: Add functions for brw_reg_type <-> hw 3src type

Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>

---

 src/intel/compiler/brw_reg_type.c | 50 +++
 src/intel/compiler/brw_reg_type.h |  8 +++
 2 files changed, 58 insertions(+)

diff --git a/src/intel/compiler/brw_reg_type.c 
b/src/intel/compiler/brw_reg_type.c
index 98c4cf7234..f5aadf88bb 100644
--- a/src/intel/compiler/brw_reg_type.c
+++ b/src/intel/compiler/brw_reg_type.c
@@ -79,6 +79,27 @@ static const struct {
[BRW_REGISTER_TYPE_UV] = { INVALID, BRW_HW_IMM_TYPE_UV  },
 };
 
+/* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so
+ * the types were implied. IVB adds BFE and BFI2 that operate on doublewords
+ * and unsigned doublewords, so a new field is also available in the da3src
+ * struct (part of struct brw_instruction.bits1 in brw_structs.h) to select
+ * dst and shared-src types.
+ */
+enum hw_3src_reg_type {
+   GEN7_3SRC_TYPE_F  = 0,
+   GEN7_3SRC_TYPE_D  = 1,
+   GEN7_3SRC_TYPE_UD = 2,
+   GEN7_3SRC_TYPE_DF = 3,
+};
+
+static const enum hw_3src_reg_type gen7_3src_type[] = {
+   [0 ... BRW_REGISTER_TYPE_LAST] = INVALID,
+   [BRW_REGISTER_TYPE_F]  = GEN7_3SRC_TYPE_F,
+   [BRW_REGISTER_TYPE_D]  = GEN7_3SRC_TYPE_D,
+   [BRW_REGISTER_TYPE_UD] = GEN7_3SRC_TYPE_UD,
+   [BRW_REGISTER_TYPE_DF] = GEN7_3SRC_TYPE_DF,
+};
+
 /**
  * Convert a brw_reg_type enumeration value into the hardware representation.
  *
@@ -126,6 +147,35 @@ brw_hw_type_to_reg_type(const struct gen_device_info 
*devinfo,
 }
 
 /**
+ * Convert a brw_reg_type enumeration value into the hardware representation
+ * for a 3-src instruction
+ */
+unsigned
+brw_reg_type_to_hw_3src_type(const struct gen_device_info *devinfo,
+ enum brw_reg_type type)
+{
+   assert(type < ARRAY_SIZE(gen7_3src_type));
+   assert(gen7_3src_type[type] != -1);
+   return gen7_3src_type[type];
+}
+
+/**
+ * Convert the hardware representation for a 3-src instruction into a
+ * brw_reg_type enumeration value.
+ */
+enum brw_reg_type
+brw_hw_3src_type_to_reg_type(const struct gen_device_info *devinfo,
+ unsigned hw_type)
+{
+   for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) {
+  if (gen7_3src_type[i] == hw_type) {
+ return i;
+  }
+   }
+   unreachable("not reached");
+}
+
+/**
  * Return the element size given a register type.
  */
 unsigned
diff --git a/src/intel/compiler/brw_reg_type.h 
b/src/intel/compiler/brw_reg_type.h
index 0b40906d92..ed249d77e6 100644
--- a/src/intel/compiler/brw_reg_type.h
+++ b/src/intel/compiler/brw_reg_type.h
@@ -89,6 +89,14 @@ brw_hw_type_to_reg_type(const struct gen_device_info 
*devinfo,
 enum brw_reg_file file, unsigned hw_type);
 
 unsigned
+brw_reg_type_to_hw_3src_type(const struct gen_device_info *devinfo,
+ enum brw_reg_type type);
+
+enum brw_reg_type
+brw_hw_3src_type_to_reg_type(const struct gen_device_info *devinfo,
+ unsigned hw_type);
+
+unsigned
 brw_reg_type_to_size(enum brw_reg_type type);
 
 const char *

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Mesa (master): i965: Add functions to abstract access to 3src register types

[Matt Turner]

Module: Mesa
Branch: master
Commit: 5f6ee55e681c59fb6e012c1882e2fcb062b7e4e4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f6ee55e681c59fb6e012c1882e2fcb062b7e4e4

Author: Matt Turner <matts...@gmail.com>
Date:   Thu Aug 24 16:14:35 2017 -0700

i965: Add functions to abstract access to 3src register types

Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>

---

 src/intel/compiler/brw_eu_emit.c | 22 ++
 src/intel/compiler/brw_inst.h| 21 +
 2 files changed, 23 insertions(+), 20 deletions(-)

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 5fd9a2b3fe..468cbabe4f 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -736,26 +736,8 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct 
brw_reg dest,
* may send us mixed D and UD types and want us to ignore that and use
* the destination type.
*/
-  switch (dest.type) {
-  case BRW_REGISTER_TYPE_F:
- brw_inst_set_3src_a16_src_hw_type(devinfo, inst, BRW_3SRC_TYPE_F);
- brw_inst_set_3src_a16_dst_hw_type(devinfo, inst, BRW_3SRC_TYPE_F);
- break;
-  case BRW_REGISTER_TYPE_DF:
- brw_inst_set_3src_a16_src_hw_type(devinfo, inst, BRW_3SRC_TYPE_DF);
- brw_inst_set_3src_a16_dst_hw_type(devinfo, inst, BRW_3SRC_TYPE_DF);
- break;
-  case BRW_REGISTER_TYPE_D:
- brw_inst_set_3src_a16_src_hw_type(devinfo, inst, BRW_3SRC_TYPE_D);
- brw_inst_set_3src_a16_dst_hw_type(devinfo, inst, BRW_3SRC_TYPE_D);
- break;
-  case BRW_REGISTER_TYPE_UD:
- brw_inst_set_3src_a16_src_hw_type(devinfo, inst, BRW_3SRC_TYPE_UD);
- brw_inst_set_3src_a16_dst_hw_type(devinfo, inst, BRW_3SRC_TYPE_UD);
- break;
-  default:
- unreachable("not reached");
-  }
+  brw_inst_set_3src_a16_src_type(devinfo, inst, dest.type);
+  brw_inst_set_3src_a16_dst_type(devinfo, inst, dest.type);
}
 
return inst;
diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h
index e0bc2c1ceb..0cc1a3e911 100644
--- a/src/intel/compiler/brw_inst.h
+++ b/src/intel/compiler/brw_inst.h
@@ -246,6 +246,27 @@ F(3src_access_mode,  8,  8)
 F(3src_opcode,   6,  0)
 /** @} */
 
+#define REG_TYPE(reg) \
+static inline void\
+brw_inst_set_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
+   brw_inst *inst, enum brw_reg_type type)\
+{ \
+   unsigned hw_type = brw_reg_type_to_hw_3src_type(devinfo, type);\
+   brw_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \
+} \
+  \
+static inline enum brw_reg_type   \
+brw_inst_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
+   const brw_inst *inst)  \
+{ \
+   unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst);   \
+   return brw_hw_3src_type_to_reg_type(devinfo, hw_type); \
+}
+
+REG_TYPE(dst)
+REG_TYPE(src)
+#undef REG_TYPE
+
 /**
  * Flow control instruction bits:
  *  @{

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Mesa (master): i965: Add align1 ternary instruction emission support

[Matt Turner]

Module: Mesa
Branch: master
Commit: 8c16c9c677087f0b4eb2160a28d0fbd66202df86
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c16c9c677087f0b4eb2160a28d0fbd66202df86

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Jun 14 14:49:52 2017 -0700

i965: Add align1 ternary instruction emission support

Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>

---

 src/intel/compiler/brw_eu_emit.c | 215 +--
 1 file changed, 160 insertions(+), 55 deletions(-)

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 468cbabe4f..062c631737 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -678,66 +678,171 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct 
brw_reg dest,
 
gen7_convert_mrf_to_grf(p, );
 
-   assert(brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_16);
-
-   assert(dest.file == BRW_GENERAL_REGISTER_FILE ||
- dest.file == BRW_MESSAGE_REGISTER_FILE);
assert(dest.nr < 128);
+   assert(src0.nr < 128);
+   assert(src1.nr < 128);
+   assert(src2.nr < 128);
assert(dest.address_mode == BRW_ADDRESS_DIRECT);
-   assert(dest.type == BRW_REGISTER_TYPE_F  ||
-  dest.type == BRW_REGISTER_TYPE_DF ||
-  dest.type == BRW_REGISTER_TYPE_D  ||
-  dest.type == BRW_REGISTER_TYPE_UD);
-   if (devinfo->gen == 6) {
-  brw_inst_set_3src_a16_dst_reg_file(devinfo, inst,
- dest.file == 
BRW_MESSAGE_REGISTER_FILE);
-   }
-   brw_inst_set_3src_dst_reg_nr(devinfo, inst, dest.nr);
-   brw_inst_set_3src_a16_dst_subreg_nr(devinfo, inst, dest.subnr / 16);
-   brw_inst_set_3src_a16_dst_writemask(devinfo, inst, dest.writemask);
-
-   assert(src0.file == BRW_GENERAL_REGISTER_FILE);
assert(src0.address_mode == BRW_ADDRESS_DIRECT);
-   assert(src0.nr < 128);
-   brw_inst_set_3src_a16_src0_swizzle(devinfo, inst, src0.swizzle);
-   brw_inst_set_3src_a16_src0_subreg_nr(devinfo, inst, 
get_3src_subreg_nr(src0));
-   brw_inst_set_3src_src0_reg_nr(devinfo, inst, src0.nr);
-   brw_inst_set_3src_src0_abs(devinfo, inst, src0.abs);
-   brw_inst_set_3src_src0_negate(devinfo, inst, src0.negate);
-   brw_inst_set_3src_a16_src0_rep_ctrl(devinfo, inst,
-   src0.vstride == BRW_VERTICAL_STRIDE_0);
-
-   assert(src1.file == BRW_GENERAL_REGISTER_FILE);
assert(src1.address_mode == BRW_ADDRESS_DIRECT);
-   assert(src1.nr < 128);
-   brw_inst_set_3src_a16_src1_swizzle(devinfo, inst, src1.swizzle);
-   brw_inst_set_3src_a16_src1_subreg_nr(devinfo, inst, 
get_3src_subreg_nr(src1));
-   brw_inst_set_3src_src1_reg_nr(devinfo, inst, src1.nr);
-   brw_inst_set_3src_src1_abs(devinfo, inst, src1.abs);
-   brw_inst_set_3src_src1_negate(devinfo, inst, src1.negate);
-   brw_inst_set_3src_a16_src1_rep_ctrl(devinfo, inst,
-   src1.vstride == BRW_VERTICAL_STRIDE_0);
-
-   assert(src2.file == BRW_GENERAL_REGISTER_FILE);
assert(src2.address_mode == BRW_ADDRESS_DIRECT);
-   assert(src2.nr < 128);
-   brw_inst_set_3src_a16_src2_swizzle(devinfo, inst, src2.swizzle);
-   brw_inst_set_3src_a16_src2_subreg_nr(devinfo, inst, 
get_3src_subreg_nr(src2));
-   brw_inst_set_3src_src2_reg_nr(devinfo, inst, src2.nr);
-   brw_inst_set_3src_src2_abs(devinfo, inst, src2.abs);
-   brw_inst_set_3src_src2_negate(devinfo, inst, src2.negate);
-   brw_inst_set_3src_a16_src2_rep_ctrl(devinfo, inst,
-   src2.vstride == BRW_VERTICAL_STRIDE_0);
-
-   if (devinfo->gen >= 7) {
-  /* Set both the source and destination types based on dest.type,
-   * ignoring the source register types.  The MAD and LRP emitters ensure
-   * that all four types are float.  The BFE and BFI2 emitters, however,
-   * may send us mixed D and UD types and want us to ignore that and use
-   * the destination type.
-   */
-  brw_inst_set_3src_a16_src_type(devinfo, inst, dest.type);
-  brw_inst_set_3src_a16_dst_type(devinfo, inst, dest.type);
+
+   if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
+  assert(dest.file == BRW_GENERAL_REGISTER_FILE ||
+ dest.file == BRW_ARCHITECTURE_REGISTER_FILE);
+
+  if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE) {
+ brw_inst_set_3src_a1_dst_reg_file(devinfo, inst,
+   BRW_ALIGN1_3SRC_ACCUMULATOR);
+ brw_inst_set_3src_dst_reg_nr(devinfo, inst, BRW_ARF_ACCUMULATOR);
+  } else {
+ brw_inst_set_3src_a1_dst_reg_file(devinfo, inst,
+   
BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE);
+ brw_inst_set_3src_dst_reg_nr(devinfo, inst, dest.nr);
+  }
+  brw_inst_set_3src_a1_dst_subreg_nr(devinfo, inst, dest.subnr / 8);
+
+  brw_inst_set_3src_a1_dst_hstride(devinfo, inst, 
BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1);
+
+  if

Mesa (master): i965: Add align1 ternary instruction-word support

[Matt Turner]

Module: Mesa
Branch: master
Commit: 6c7fc9b73a2919dbc246a888002210d7e4b9818b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6c7fc9b73a2919dbc246a888002210d7e4b9818b

Author: Matt Turner <matts...@gmail.com>
Date:   Tue Jun  6 16:15:21 2017 -0700

i965: Add align1 ternary instruction-word support

Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>

---

 src/intel/compiler/brw_inst.h | 108 ++
 1 file changed, 108 insertions(+)

diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h
index 1ddee77164..99e637e660 100644
--- a/src/intel/compiler/brw_inst.h
+++ b/src/intel/compiler/brw_inst.h
@@ -268,6 +268,114 @@ REG_TYPE(src)
 #undef REG_TYPE
 
 /**
+ * Three-source align1 instructions:
+ *  @{
+ */
+/* Reserved 127:126 */
+/* src2_reg_nr same in align16 */
+FC(3src_a1_src2_subreg_nr, 117, 113, devinfo->gen >= 10)
+FC(3src_a1_src2_hstride,   112, 111, devinfo->gen >= 10)
+/* Reserved 110:109. src2 vstride is an implied parameter */
+FC(3src_a1_src2_hw_type,   108, 106, devinfo->gen >= 10)
+/* Reserved 105 */
+/* src1_reg_nr same in align16 */
+FC(3src_a1_src1_subreg_nr,  96,  92, devinfo->gen >= 10)
+FC(3src_a1_src1_hstride,91,  90, devinfo->gen >= 10)
+FC(3src_a1_src1_vstride,89,  88, devinfo->gen >= 10)
+FC(3src_a1_src1_hw_type,87,  85, devinfo->gen >= 10)
+/* Reserved 84 */
+/* src0_reg_nr same in align16 */
+FC(3src_a1_src0_subreg_nr,  75,  71, devinfo->gen >= 10)
+FC(3src_a1_src0_hstride,70,  69, devinfo->gen >= 10)
+FC(3src_a1_src0_vstride,68,  67, devinfo->gen >= 10)
+FC(3src_a1_src0_hw_type,66,  64, devinfo->gen >= 10)
+/* dst_reg_nr same in align16 */
+FC(3src_a1_dst_subreg_nr,   55,  54, devinfo->gen >= 10)
+FC(3src_a1_special_acc, 55,  52, devinfo->gen >= 10) /* aliases 
dst_subreg_nr */
+/* Reserved 51:50 */
+FC(3src_a1_dst_hstride, 49,  49, devinfo->gen >= 10)
+FC(3src_a1_dst_hw_type, 48,  46, devinfo->gen >= 10)
+FC(3src_a1_src2_reg_file,   45,  45, devinfo->gen >= 10)
+FC(3src_a1_src1_reg_file,   44,  44, devinfo->gen >= 10)
+FC(3src_a1_src0_reg_file,   43,  43, devinfo->gen >= 10)
+/* Source Modifier fields same in align16 */
+FC(3src_a1_dst_reg_file,36,  36, devinfo->gen >= 10)
+FC(3src_a1_exec_type,   35,  35, devinfo->gen >= 10)
+/* Fields below this same in align16 */
+/** @} */
+
+#define REG_TYPE(reg) \
+static inline void\
+brw_inst_set_3src_a1_##reg##_type(const struct gen_device_info *devinfo,  \
+  brw_inst *inst, enum brw_reg_type type) \
+{ \
+   UNUSED enum gen10_align1_3src_exec_type exec_type =\
+  (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo,  \
+inst);\
+   if (brw_reg_type_is_floating_point(type)) {\
+  assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT);   \
+   } else {   \
+  assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \
+   }  \
+   unsigned hw_type = brw_reg_type_to_a1_hw_3src_type(devinfo, type); \
+   brw_inst_set_3src_a1_##reg##_hw_type(devinfo, inst, hw_type);  \
+} \
+  \
+static inline enum brw_reg_type   \
+brw_inst_3src_a1_##reg##_type(const struct gen_device_info *devinfo,  \
+  const brw_inst *inst)   \
+{ \
+   enum gen10_align1_3src_exec_type exec_type =   \
+  (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo,  \
+inst);\
+   unsigned hw_type = brw_inst_3src_a1_##reg##_hw_type(devinfo, inst);\
+   return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type);   \
+}
+
+REG_TYPE(dst)
+REG_TYPE(src0)
+REG_TYPE(src1)
+REG_TYPE(src2)
+#undef REG_TYPE
+
+/**
+ * Three-source align1 instruction immediates:
+ *  @{
+ */
+static inline uint16_t
+brw_inst_3src_a1_src0_imm(const struct gen_device_info *devinfo,
+  const brw_inst *insn)
+{
+   assert(devinfo->gen >= 10);
+   return brw_inst_bits(insn, 82, 67);
+}
+
+static inline uint16_

Mesa (master): i965/fs: Use align1 mode on ternary instructions on Gen10+

[Matt Turner]

Module: Mesa
Branch: master
Commit: 9cd60fce9c22737000a8f8dc711141f8a523fe75
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9cd60fce9c22737000a8f8dc711141f8a523fe75

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Jun 14 14:48:11 2017 -0700

i965/fs: Use align1 mode on ternary instructions on Gen10+

Align1 mode offers some nice features over align16, like access to more
data types and the ability to use a 16-bit immediate. This patch does
not start using any new features. It just emits ternary instructions in
align1 mode.

Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>

---

 src/intel/compiler/brw_fs_generator.cpp | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index 2622a91917..bdf2f916cb 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1729,13 +1729,15 @@ fs_generator::generate_code(const cfg_t *cfg, int 
dispatch_width)
 
   case BRW_OPCODE_MAD:
  assert(devinfo->gen >= 6);
-brw_set_default_access_mode(p, BRW_ALIGN_16);
+ if (devinfo->gen < 10)
+brw_set_default_access_mode(p, BRW_ALIGN_16);
  brw_MAD(p, dst, src[0], src[1], src[2]);
 break;
 
   case BRW_OPCODE_LRP:
  assert(devinfo->gen >= 6);
-brw_set_default_access_mode(p, BRW_ALIGN_16);
+ if (devinfo->gen < 10)
+brw_set_default_access_mode(p, BRW_ALIGN_16);
  brw_LRP(p, dst, src[0], src[1], src[2]);
 break;
 
@@ -1833,7 +1835,8 @@ fs_generator::generate_code(const cfg_t *cfg, int 
dispatch_width)
 
   case BRW_OPCODE_BFE:
  assert(devinfo->gen >= 7);
- brw_set_default_access_mode(p, BRW_ALIGN_16);
+ if (devinfo->gen < 10)
+brw_set_default_access_mode(p, BRW_ALIGN_16);
  brw_BFE(p, dst, src[0], src[1], src[2]);
  break;
 
@@ -1843,7 +1846,8 @@ fs_generator::generate_code(const cfg_t *cfg, int 
dispatch_width)
  break;
   case BRW_OPCODE_BFI2:
  assert(devinfo->gen >= 7);
- brw_set_default_access_mode(p, BRW_ALIGN_16);
+ if (devinfo->gen < 10)
+brw_set_default_access_mode(p, BRW_ALIGN_16);
  brw_BFI2(p, dst, src[0], src[1], src[2]);
  break;
 

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Mesa (master): i965: Move brw_reg_type_is_floating_point to brw_reg_type.h

[Matt Turner]

Module: Mesa
Branch: master
Commit: 4c857d1f3bffc38d0aeed56ee8074979435ddd7a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4c857d1f3bffc38d0aeed56ee8074979435ddd7a

Author: Matt Turner <matts...@gmail.com>
Date:   Thu Aug 24 16:04:26 2017 -0700

i965: Move brw_reg_type_is_floating_point to brw_reg_type.h

I'm going to call this from brw_inst.h, and I don't want to have to
include all of brw_reg.h.

Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>

---

 src/intel/compiler/brw_reg.h  | 13 -
 src/intel/compiler/brw_reg_type.h | 15 +++
 2 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h
index 441dfb2447..d68d64f003 100644
--- a/src/intel/compiler/brw_reg.h
+++ b/src/intel/compiler/brw_reg.h
@@ -289,19 +289,6 @@ type_sz(unsigned type)
}
 }
 
-static inline bool
-brw_reg_type_is_floating_point(enum brw_reg_type type)
-{
-   switch (type) {
-   case BRW_REGISTER_TYPE_F:
-   case BRW_REGISTER_TYPE_HF:
-   case BRW_REGISTER_TYPE_DF:
-  return true;
-   default:
-  return false;
-   }
-}
-
 static inline enum brw_reg_type
 get_exec_type(const enum brw_reg_type type)
 {
diff --git a/src/intel/compiler/brw_reg_type.h 
b/src/intel/compiler/brw_reg_type.h
index 87d9fe31e8..0b40906d92 100644
--- a/src/intel/compiler/brw_reg_type.h
+++ b/src/intel/compiler/brw_reg_type.h
@@ -24,6 +24,8 @@
 #ifndef BRW_REG_TYPE_H
 #define BRW_REG_TYPE_H
 
+#include 
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -65,6 +67,19 @@ enum PACKED brw_reg_type {
BRW_REGISTER_TYPE_LAST = BRW_REGISTER_TYPE_UV
 };
 
+static inline bool
+brw_reg_type_is_floating_point(enum brw_reg_type type)
+{
+   switch (type) {
+   case BRW_REGISTER_TYPE_DF:
+   case BRW_REGISTER_TYPE_F:
+   case BRW_REGISTER_TYPE_HF:
+  return true;
+   default:
+  return false;
+   }
+}
+
 unsigned
 brw_reg_type_to_hw_type(const struct gen_device_info *devinfo,
 enum brw_reg_file file, enum brw_reg_type type);

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Mesa (master): i965: Add align1 ternary instruction field encodings

[Matt Turner]

Module: Mesa
Branch: master
Commit: 281e8b8f278ef23f24b331e03c751fa8d1c5f7c2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=281e8b8f278ef23f24b331e03c751fa8d1c5f7c2

Author: Matt Turner <matts...@gmail.com>
Date:   Thu Dec 17 12:33:38 2015 -0500

i965: Add align1 ternary instruction field encodings

Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>

---

 src/intel/compiler/brw_eu_defines.h | 35 +++
 1 file changed, 35 insertions(+)

diff --git a/src/intel/compiler/brw_eu_defines.h 
b/src/intel/compiler/brw_eu_defines.h
index da482b73c5..3af55e830c 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -148,6 +148,18 @@ enum PACKED brw_horizontal_stride {
BRW_HORIZONTAL_STRIDE_4 = 3,
 };
 
+enum PACKED gen10_align1_3src_src_horizontal_stride {
+   BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 = 0,
+   BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1 = 1,
+   BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2 = 2,
+   BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4 = 3,
+};
+
+enum PACKED gen10_align1_3src_dst_horizontal_stride {
+   BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1 = 0,
+   BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_2 = 1,
+};
+
 #define BRW_INSTRUCTION_NORMAL0
 #define BRW_INSTRUCTION_SATURATE  1
 
@@ -819,6 +831,12 @@ enum PACKED brw_reg_file {
BAD_FILE,
 };
 
+enum PACKED gen10_align1_3src_reg_file {
+   BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE = 0,
+   BRW_ALIGN1_3SRC_IMMEDIATE_VALUE   = 1, /* src0, src2 */
+   BRW_ALIGN1_3SRC_ACCUMULATOR   = 1, /* dest, src1 */
+};
+
 /* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so
  * the types were implied. IVB adds BFE and BFI2 that operate on doublewords
  * and unsigned doublewords, so a new field is also available in the da3src
@@ -830,6 +848,16 @@ enum PACKED brw_reg_file {
 #define BRW_3SRC_TYPE_UD 2
 #define BRW_3SRC_TYPE_DF 3
 
+/* CNL adds Align1 support for 3-src instructions. Bit 35 of the instruction
+ * word is "Execution Datatype" which controls whether the instruction operates
+ * on float or integer types. The register arguments have fields that offer
+ * more fine control their respective types.
+ */
+enum PACKED gen10_align1_3src_exec_type {
+   BRW_ALIGN1_3SRC_EXEC_TYPE_INT   = 0,
+   BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT = 1,
+};
+
 #define BRW_ARF_NULL  0x00
 #define BRW_ARF_ADDRESS   0x10
 #define BRW_ARF_ACCUMULATOR   0x20
@@ -868,6 +896,13 @@ enum PACKED brw_vertical_stride {
BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF,
 };
 
+enum PACKED gen10_align1_3src_vertical_stride {
+   BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0,
+   BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1,
+   BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4 = 2,
+   BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8 = 3,
+};
+
 enum PACKED brw_width {
BRW_WIDTH_1  = 0,
BRW_WIDTH_2  = 1,

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Mesa (master): i965: Use a union to bitcast a float

[Matt Turner]

Module: Mesa
Branch: master
Commit: e9796ebca7d2977700ff51ade9193e33368bd4af
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9796ebca7d2977700ff51ade9193e33368bd4af

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Oct 18 22:16:05 2017 -0700

i965: Use a union to bitcast a float

... which does not break C's aliasing rules.

---

 src/mesa/drivers/dri/i965/gen6_constant_state.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_constant_state.c 
b/src/mesa/drivers/dri/i965/gen6_constant_state.c
index 62ad6b0497..121ba67257 100644
--- a/src/mesa/drivers/dri/i965/gen6_constant_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_constant_state.c
@@ -32,7 +32,8 @@
 static uint32_t
 f_as_u32(float f)
 {
-   return *(uint32_t *)
+   union fi fi = { .f = f };
+   return fi.ui;
 }
 
 static uint32_t

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Mesa (master): i965: Fix support for disassembling 64-bit integer immediates

[Matt Turner]

Module: Mesa
Branch: master
Commit: 6db5ec7debd283db0c4e9582f07340efa8e94f66
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6db5ec7debd283db0c4e9582f07340efa8e94f66

Author: Matt Turner <matts...@gmail.com>
Date:   Thu Sep 21 13:52:28 2017 -0700

i965: Fix support for disassembling 64-bit integer immediates

The type suffixes were wrong, and the 16 was missing the 0 prefix.

Fixes: 92f787ff86ab ("i965: Add support for disassembling 64-bit integer 
immediates")
Reviewed-by: Iago Toral Quiroga <ito...@igalia.com>

---

 src/intel/compiler/brw_disasm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index e2675b5f4c..2043d64b27 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -1012,10 +1012,10 @@ imm(FILE *file, const struct gen_device_info *devinfo, 
enum brw_reg_type type,
 {
switch (type) {
case BRW_REGISTER_TYPE_UQ:
-  format(file, "0x%16lxUD", brw_inst_imm_uq(devinfo, inst));
+  format(file, "0x%016lxUQ", brw_inst_imm_uq(devinfo, inst));
   break;
case BRW_REGISTER_TYPE_Q:
-  format(file, "%ldD", brw_inst_imm_uq(devinfo, inst));
+  format(file, "%ldQ", brw_inst_imm_uq(devinfo, inst));
   break;
case BRW_REGISTER_TYPE_UD:
   format(file, "0x%08xUD", brw_inst_imm_ud(devinfo, inst));

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Mesa (master): i965: Only insert error message if not already present

[Matt Turner]

Module: Mesa
Branch: master
Commit: 122ef3799d5612748afd8b15392c4a819a1b1847
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=122ef3799d5612748afd8b15392c4a819a1b1847

Author: Matt Turner <matts...@gmail.com>
Date:   Mon Sep 18 14:07:20 2017 -0700

i965: Only insert error message if not already present

Some restrictions require something like strides to match between src
and dest. For multi-source instructions, I'd rather encapsulate the
logic for not inserting already present errors in ERROR_IF than
open-coding it multiple places.

---

 src/intel/compiler/brw_eu_validate.c | 18 +-
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/src/intel/compiler/brw_eu_validate.c 
b/src/intel/compiler/brw_eu_validate.c
index 99abc6b4f9..8fcc529366 100644
--- a/src/intel/compiler/brw_eu_validate.c
+++ b/src/intel/compiler/brw_eu_validate.c
@@ -44,15 +44,23 @@ cat(struct string *dest, const struct string src)
 }
 #define CAT(dest, src) cat(, (struct string){src, strlen(src)})
 
+static bool
+contains(const struct string haystack, const struct string needle)
+{
+   return memmem(haystack.str, haystack.len, needle.str, needle.len) != NULL;
+}
+#define CONTAINS(haystack, needle) \
+   contains(haystack, (struct string){needle, strlen(needle)})
+
 #define error(str)   "\tERROR: " str "\n"
 #define ERROR_INDENT "\t   "
 
 #define ERROR(msg) ERROR_IF(true, msg)
-#define ERROR_IF(cond, msg)  \
-   do {  \
-  if (cond) {\
- CAT(error_msg, error(msg)); \
-  }  \
+#define ERROR_IF(cond, msg) \
+   do { \
+  if ((cond) && !CONTAINS(error_msg, error(msg))) { \
+ CAT(error_msg, error(msg));\
+  } \
} while(0)
 
 #define CHECK(func, args...) \

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Mesa (master): i965: Fix and enable forgotten validation test

[Matt Turner]

Module: Mesa
Branch: master
Commit: 98298c7e3da3a8368d618199d8a50e638c257779
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=98298c7e3da3a8368d618199d8a50e638c257779

Author: Matt Turner <matts...@gmail.com>
Date:   Fri Sep  1 15:22:40 2017 -0700

i965: Fix and enable forgotten validation test

I seem to have forgotten I still had work to do.

---

 src/intel/compiler/test_eu_validate.cpp | 31 +--
 1 file changed, 17 insertions(+), 14 deletions(-)

diff --git a/src/intel/compiler/test_eu_validate.cpp 
b/src/intel/compiler/test_eu_validate.cpp
index 3dd560074f..4e0317ec74 100644
--- a/src/intel/compiler/test_eu_validate.cpp
+++ b/src/intel/compiler/test_eu_validate.cpp
@@ -679,11 +679,8 @@ TEST_P(validation_test, 
two_src_two_dst_source_offsets_must_be_same)
EXPECT_TRUE(validate(p));
 }
 
-#if 0
 TEST_P(validation_test, two_src_two_dst_each_dst_must_be_derived_from_one_src)
 {
-   // mov (16) r10.0<2>:w r12.4<4;4,1>:w
-
brw_MOV(p, g0, g0);
brw_inst_set_exec_size(, last_inst, BRW_EXECUTE_16);
brw_inst_set_dst_file_type(, last_inst, BRW_GENERAL_REGISTER_FILE, 
BRW_REGISTER_TYPE_W);
@@ -692,23 +689,29 @@ TEST_P(validation_test, 
two_src_two_dst_each_dst_must_be_derived_from_one_src)
brw_inst_set_src0_da1_subreg_nr(, last_inst, 8);
brw_inst_set_src0_vstride(, last_inst, BRW_VERTICAL_STRIDE_4);
brw_inst_set_src0_width(, last_inst, BRW_WIDTH_4);
-   brw_inst_set_src0_hstride(, last_inst, BRW_HORIZONTAL_STRIDE_4);
+   brw_inst_set_src0_hstride(, last_inst, BRW_HORIZONTAL_STRIDE_1);
 
-   EXPECT_FALSE(validate(p));
+   if (devinfo.gen <= 7) {
+  EXPECT_FALSE(validate(p));
+   } else {
+  EXPECT_TRUE(validate(p));
+   }
 
clear_instructions(p);
 
-#if 0
-   brw_ADD(p, g0, g0, g0);
-   brw_inst_set_src1_da1_subreg_nr(, last_inst, 16);
-   brw_inst_set_src1_vstride(, last_inst, BRW_VERTICAL_STRIDE_4);
-   brw_inst_set_src1_width(, last_inst, BRW_WIDTH_4);
-   brw_inst_set_src1_hstride(, last_inst, BRW_HORIZONTAL_STRIDE_1);
+   brw_MOV(p, g0, g0);
+   brw_inst_set_dst_da1_subreg_nr(, last_inst, 16);
+   brw_inst_set_src0_da1_subreg_nr(, last_inst, 8);
+   brw_inst_set_src0_vstride(, last_inst, BRW_VERTICAL_STRIDE_2);
+   brw_inst_set_src0_width(, last_inst, BRW_WIDTH_2);
+   brw_inst_set_src0_hstride(, last_inst, BRW_HORIZONTAL_STRIDE_1);
 
-   EXPECT_FALSE(validate(p));
-   #endif
+   if (devinfo.gen <= 7) {
+  EXPECT_FALSE(validate(p));
+   } else {
+  EXPECT_TRUE(validate(p));
+   }
 }
-#endif
 
 TEST_P(validation_test, one_src_two_dst)
 {

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Mesa (master): i965: Add Atom graphics names to parse_devid_override()

[Matt Turner]

Module: Mesa
Branch: master
Commit: d4c39e9cfff16d401a4d1874c9ec19f3a3036df2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d4c39e9cfff16d401a4d1874c9ec19f3a3036df2

Author: Matt Turner <matts...@gmail.com>
Date:   Tue Aug 29 15:32:11 2017 -0700

i965: Add Atom graphics names to parse_devid_override()

---

 src/mesa/drivers/dri/i965/intel_screen.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 77df6eddba..93f4f9fba4 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -2195,8 +2195,11 @@ parse_devid_override(const char *devid_override)
   { "hsw", 0x0d2e },
   { "byt", 0x0f33 },
   { "bdw", 0x162e },
+  { "chv", 0x22B3 },
   { "skl", 0x1912 },
+  { "bxt", 0x5A85 },
   { "kbl", 0x5912 },
+  { "glk", 0x3185 },
   { "cnl", 0x5a52 },
};
 

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Mesa (master): i965/fs: Unpack count argument to 64-bit shift ops on Atom

[Matt Turner]

Module: Mesa
Branch: master
Commit: b541945c2027990ac571184bbf8e01285be0e33a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b541945c2027990ac571184bbf8e01285be0e33a

Author: Matt Turner <matts...@gmail.com>
Date:   Thu Sep 21 16:42:02 2017 -0700

i965/fs: Unpack count argument to 64-bit shift ops on Atom

64-bit operations on Atom parts have additional restrictions over their
big-core counterparts (validated by later patches).

Specifically, the restriction that "Source and Destination horizontal
stride must be aligned to the same qword" is violated by most shift
operations since NIR uses a 32-bit value as the shift count argument,
and this causes instructions like

   shl(8)  g19<1>Q g5<4,4,1>Q  g23<4,4,1>UD

where src1 has a 32-bit stride, but the dest and src0 have a 64-bit
stride.

This caused ~4 pixels in the ARB_shader_ballot piglit test
fs-readInvocation-uint.shader_test to be incorrect. Unfortunately no
ARB_gpu_shader_int64 test hit this case because they operate on
uniforms, and their scalar regions are an exception to the restriction.

We work around this by effectively unpacking the shift count, so that we
can read it with a 64-bit stride in the shift instruction. Unfortunately
the unpack (a MOV with a dst stride of 2) is a partial write, and cannot
be copy-propagated or CSE'd.

Bugzilla: https://bugs.freedesktop.org/101984

---

 src/intel/compiler/brw_fs_nir.cpp | 34 --
 1 file changed, 28 insertions(+), 6 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp
index aa57bb9d78..7eae052027 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -1267,14 +1267,36 @@ fs_visitor::nir_emit_alu(const fs_builder , 
nir_alu_instr *instr)
   unreachable("not reached: should have been lowered");
 
case nir_op_ishl:
-  bld.SHL(result, op[0], op[1]);
-  break;
case nir_op_ishr:
-  bld.ASR(result, op[0], op[1]);
-  break;
-   case nir_op_ushr:
-  bld.SHR(result, op[0], op[1]);
+   case nir_op_ushr: {
+  fs_reg shift_count = op[1];
+
+  if (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo)) {
+ if (op[1].file == VGRF &&
+ (result.type == BRW_REGISTER_TYPE_Q ||
+  result.type == BRW_REGISTER_TYPE_UQ)) {
+shift_count = fs_reg(VGRF, alloc.allocate(dispatch_width / 4),
+ BRW_REGISTER_TYPE_UD);
+shift_count.stride = 2;
+bld.MOV(shift_count, op[1]);
+ }
+  }
+
+  switch (instr->op) {
+  case nir_op_ishl:
+ bld.SHL(result, op[0], shift_count);
+ break;
+  case nir_op_ishr:
+ bld.ASR(result, op[0], shift_count);
+ break;
+  case nir_op_ushr:
+ bld.SHR(result, op[0], shift_count);
+ break;
+  default:
+ unreachable("not reached");
+  }
   break;
+   }
 
case nir_op_pack_half_2x16_split:
   bld.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT, result, op[0], op[1]);

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Mesa (master): i965: Add parentheses around usage of macro arguments

[Matt Turner]

Module: Mesa
Branch: master
Commit: 4c961a5e79f40596e19e88ad780377a3fccc7a92
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4c961a5e79f40596e19e88ad780377a3fccc7a92

Author: Matt Turner <matts...@gmail.com>
Date:   Fri Sep  1 15:34:54 2017 -0700

i965: Add parentheses around usage of macro arguments

Otherwise I cannot use this macro in test_eu_validate.cpp

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com>

---

 src/intel/common/gen_device_info.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/common/gen_device_info.h 
b/src/intel/common/gen_device_info.h
index ede4915e28..59b345e949 100644
--- a/src/intel/common/gen_device_info.h
+++ b/src/intel/common/gen_device_info.h
@@ -193,7 +193,7 @@ struct gen_device_info
 };
 
 #define gen_device_info_is_9lp(devinfo) \
-   (devinfo->is_broxton || devinfo->is_geminilake)
+   ((devinfo)->is_broxton || (devinfo)->is_geminilake)
 
 bool gen_get_device_info(int devid, struct gen_device_info *devinfo);
 const char *gen_get_device_name(int devid);

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Mesa (master): i965: Avoid validation error when src1 is not present

[Matt Turner]

Module: Mesa
Branch: master
Commit: 5e76cf153c980d5c4719376e6653729bcf2db512
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e76cf153c980d5c4719376e6653729bcf2db512

Author: Matt Turner <matts...@gmail.com>
Date:   Fri Sep  1 15:21:48 2017 -0700

i965: Avoid validation error when src1 is not present

There can be no violation of the restriction that source offsets are
aligned if there is only one source offset.

---

 src/intel/compiler/brw_eu_validate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_eu_validate.c 
b/src/intel/compiler/brw_eu_validate.c
index ff10b83d78..99abc6b4f9 100644
--- a/src/intel/compiler/brw_eu_validate.c
+++ b/src/intel/compiler/brw_eu_validate.c
@@ -941,7 +941,7 @@ region_alignment_rules(const struct gen_device_info 
*devinfo,
 } \
  }\
   \
- ERROR_IF(offset_0 != offset_1,   \
+ ERROR_IF(num_sources == 2 && offset_0 != offset_1,   \
   "The offset from the two source registers " \
   "must be the same")
 

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Mesa (master): i965: Add GLK, CFL, CNL to test_eu_validate.c

[Matt Turner]

Module: Mesa
Branch: master
Commit: 1fcdb1cbeae058cc23349485dca7cc6c7de398f1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1fcdb1cbeae058cc23349485dca7cc6c7de398f1

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Aug 30 15:45:22 2017 -0700

i965: Add GLK, CFL, CNL to test_eu_validate.c

---

 src/intel/compiler/test_eu_validate.cpp | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/src/intel/compiler/test_eu_validate.cpp 
b/src/intel/compiler/test_eu_validate.cpp
index 46d2b83e34..3dd560074f 100644
--- a/src/intel/compiler/test_eu_validate.cpp
+++ b/src/intel/compiler/test_eu_validate.cpp
@@ -32,6 +32,8 @@ enum subgen {
IS_CHV,
IS_BXT,
IS_KBL,
+   IS_GLK,
+   IS_CFL,
 };
 
 static const struct gen_info {
@@ -51,6 +53,9 @@ static const struct gen_info {
{ "skl", 9 },
{ "bxt", 9, IS_BXT },
{ "kbl", 9, IS_KBL },
+   { "glk", 9, IS_GLK },
+   { "cfl", 9, IS_CFL },
+   { "cnl", 10 },
 };
 
 class validation_test: public ::testing::TestWithParam {
@@ -86,6 +91,8 @@ void validation_test::SetUp()
devinfo.is_cherryview = info.subgen == IS_CHV;
devinfo.is_broxton= info.subgen == IS_BXT;
devinfo.is_kabylake   = info.subgen == IS_KBL;
+   devinfo.is_geminilake = info.subgen == IS_GLK;
+   devinfo.is_coffeelake = info.subgen == IS_CFL;
 
brw_init_codegen(, p, p);
 }

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Mesa (master): i965/fs: Don't apply POW/FDIV workaround on Gen10+

[Matt Turner]

Module: Mesa
Branch: master
Commit: 2082c32950a9e3a4debc00b0d6da85404b923920
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2082c32950a9e3a4debc00b0d6da85404b923920

Author: Matt Turner <matts...@gmail.com>
Date:   Fri Aug 25 15:52:27 2017 -0700

i965/fs: Don't apply POW/FDIV workaround on Gen10+

The documentation says it applies only to Gens 8 and 9.

Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>

---

 src/intel/compiler/brw_fs_generator.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index 6489cc0d38..2622a91917 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1639,6 +1639,7 @@ fs_generator::generate_code(const cfg_t *cfg, int 
dispatch_width)
* and empirically this affects CHV as well.
*/
   if (devinfo->gen >= 8 &&
+  devinfo->gen <= 9 &&
   p->nr_insn > 1 &&
   brw_inst_opcode(devinfo, brw_last_inst) == BRW_OPCODE_MATH &&
   brw_inst_math_function(devinfo, brw_last_inst) == 
BRW_MATH_FUNCTION_POW &&

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Mesa (master): i965: Add and use STRIDE and WIDTH macros

[Matt Turner]

Module: Mesa
Branch: master
Commit: 678d88bceecb2b944c41ca5ceef24e3aa0137bc6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=678d88bceecb2b944c41ca5ceef24e3aa0137bc6

Author: Matt Turner <matts...@gmail.com>
Date:   Tue Aug 29 18:25:54 2017 -0700

i965: Add and use STRIDE and WIDTH macros

You'll notice there were bugs in some of the code being replaced.

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com>

---

 src/intel/compiler/brw_eu_validate.c | 33 +++--
 1 file changed, 15 insertions(+), 18 deletions(-)

diff --git a/src/intel/compiler/brw_eu_validate.c 
b/src/intel/compiler/brw_eu_validate.c
index 7453218c2b..ff10b83d78 100644
--- a/src/intel/compiler/brw_eu_validate.c
+++ b/src/intel/compiler/brw_eu_validate.c
@@ -64,6 +64,9 @@ cat(struct string *dest, const struct string src)
   }  \
} while (0)
 
+#define STRIDE(stride) (stride != 0 ? 1 << ((stride) - 1) : 0)
+#define WIDTH(width)   (1 << (width))
+
 static bool
 inst_is_send(const struct gen_device_info *devinfo, const brw_inst *inst)
 {
@@ -418,7 +421,7 @@ general_restrictions_based_on_operand_types(const struct 
gen_device_info *devinf
 * In fact, checking it would weaken testing of the other rules.
 */
 
-   unsigned dst_stride = 1 << (brw_inst_dst_hstride(devinfo, inst) - 1);
+   unsigned dst_stride = STRIDE(brw_inst_dst_hstride(devinfo, inst));
enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst);
bool dst_type_is_byte =
   brw_inst_dst_type(devinfo, inst) == BRW_REGISTER_TYPE_B ||
@@ -542,11 +545,9 @@ general_restrictions_on_region_parameters(const struct 
gen_device_info *devinfo,
   BRW_IMMEDIATE_VALUE) 
\
  continue; 
\

\
-  vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? 
\
-(1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; 
\
-  width = 1 << brw_inst_src ## n ## _width(devinfo, inst); 
\
-  hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? 
\
-(1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; 
\
+  vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst));  
\
+  width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst));   
\
+  hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst));  
\
   type = brw_inst_src ## n ## _type(devinfo, inst);
\
   element_size = brw_reg_type_to_size(type);   
\
   subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst)
@@ -742,11 +743,9 @@ region_alignment_rules(const struct gen_device_info 
*devinfo,
   BRW_IMMEDIATE_VALUE) 
\
  continue; 
\

\
-  vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? 
\
-(1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; 
\
-  width = 1 << brw_inst_src ## n ## _width(devinfo, inst); 
\
-  hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? 
\
-(1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; 
\
+  vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst));  
\
+  width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst));   
\
+  hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst));  
\
   type = brw_inst_src ## n ## _type(devinfo, inst);
\
   element_size = brw_reg_type_to_size(type);   
\
   subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); 
\
@@ -774,7 +773,7 @@ region_alignment_rules(const struct gen_device_info 
*devinfo,
if (desc->ndst == 0 || dst_is_null(devinfo, inst))
   return error_msg;
 
-   unsigned stride = 1 << (brw_inst_dst_hstride(devinfo, inst) - 1);
+   unsigned stride = STRIDE(brw_inst_dst_hstride(devinfo, inst));
enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst);
unsigned element_size = brw_reg_type_to_size(dst_type);
unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst);
@@ -990,11 +989,9 @@ region_alignment_rules(const struct gen_device_info 
*devinfo,
   for (unsigned i = 0; i < num_sources; i++) {
 #define DO_SRC(n)  
\
  unsigned vstride, width, hstride; 

Mesa (master): i965/fs: Rewrite fsign64 to skip the float -> double conversion

[Matt Turner]

Module: Mesa
Branch: master
Commit: 7e88f934697fd4ce05093c077b5f11454e377ed0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e88f934697fd4ce05093c077b5f11454e377ed0

Author: Matt Turner <matts...@gmail.com>
Date:   Thu Sep 28 20:59:49 2017 -0700

i965/fs: Rewrite fsign64 to skip the float -> double conversion

... without the float -> double conversion. Low power parts have
additional restrictions when it comes to operating on 64-bit types, and
the instruction used to do the conversion violates one of them:
specifically, the restriction that "Source and Destination horizontal
stride must be aligned to the same qword".

Previously we generated a float and then converted, but we can avoid the
conversion by using the same extract-the-sign-bit + or-in-1.0 algorithm
by directly operating on the high four bytes of each double-precision
component in the result.

In SIMD8 and SIMD16 this cuts one instruction from the implementation,
and more importantly that instruction is the one which violated the
regioning restriction.

Along the way I removed some comments that I did not think helped, and
some code about double comparisons which does not seem to be necessary
today.

This prevents validation failures caught by the new EU validation code
added in later patches.

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com>

---

 src/intel/compiler/brw_fs_nir.cpp | 50 +++
 1 file changed, 9 insertions(+), 41 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp
index 7eae052027..5b8ccd50bf 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -693,53 +693,21 @@ fs_visitor::nir_emit_alu(const fs_builder , 
nir_alu_instr *instr)
   *
   * - 2-src instructions can't operate with 64-bit immediates
   * - The sign is encoded in the high 32-bit of each DF
-  * - CMP with DF requires special handling in SIMD16
   * - We need to produce a DF result.
   */
 
- /* 2-src instructions can't have 64-bit immediates, so put 0.0 in
-  * a register and compare with that.
-  */
- fs_reg tmp = vgrf(glsl_type::double_type);
- bld.MOV(tmp, setup_imm_df(bld, 0.0));
-
- /* A direct DF CMP using the flag register (null dst) won't work in
-  * SIMD16 because the CMP will be split in two by lower_simd_width,
-  * resulting in two CMP instructions with the same dst (NULL),
-  * leading to dead code elimination of the first one. In SIMD8,
-  * however, there is no need to split the CMP and we can save some
-  * work.
-  */
- fs_reg dst_tmp = vgrf(glsl_type::double_type);
- bld.CMP(dst_tmp, op[0], tmp, BRW_CONDITIONAL_NZ);
-
- /* In SIMD16 we want to avoid using a NULL dst register with DF CMP,
-  * so we store the result of the comparison in a vgrf instead and
-  * then we generate a UD comparison from that that won't have to
-  * be split by lower_simd_width. This is what NIR does to handle
-  * double comparisons in the general case.
-  */
- if (bld.dispatch_width() == 16 ) {
-fs_reg dst_tmp_ud = retype(dst_tmp, BRW_REGISTER_TYPE_UD);
-bld.MOV(dst_tmp_ud, subscript(dst_tmp, BRW_REGISTER_TYPE_UD, 0));
-bld.CMP(bld.null_reg_ud(),
-dst_tmp_ud, brw_imm_ud(0), BRW_CONDITIONAL_NZ);
- }
-
- /* Get the high 32-bit of each double component where the sign is */
- fs_reg result_int = retype(result, BRW_REGISTER_TYPE_UD);
- bld.MOV(result_int, subscript(op[0], BRW_REGISTER_TYPE_UD, 1));
+ fs_reg zero = vgrf(glsl_type::double_type);
+ bld.MOV(zero, setup_imm_df(bld, 0.0));
+ bld.CMP(bld.null_reg_df(), op[0], zero, BRW_CONDITIONAL_NZ);
 
- /* Get the sign bit */
- bld.AND(result_int, result_int, brw_imm_ud(0x8000u));
+ bld.MOV(result, zero);
 
- /* Add 1.0 to the sign, predicated to skip the case of op[0] == 0.0 */
- inst = bld.OR(result_int, result_int, brw_imm_ud(0x3f80u));
- inst->predicate = BRW_PREDICATE_NORMAL;
+ fs_reg r = subscript(result, BRW_REGISTER_TYPE_UD, 1);
+ bld.AND(r, subscript(op[0], BRW_REGISTER_TYPE_UD, 1),
+ brw_imm_ud(0x8000u));
 
- /* Convert from 32-bit float to 64-bit double */
- result.type = BRW_REGISTER_TYPE_DF;
- inst = bld.MOV(result, retype(result_int, BRW_REGISTER_TYPE_F));
+ set_predicate(BRW_PREDICATE_NORMAL,
+   bld.OR(r, r, brw_imm_ud(0x3ff0u)));
 
  if (instr->dest.saturate) {
 inst = bld.MOV(result, result);

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Mesa (master): i965: Fix src0 vs src1 typo

[Matt Turner]

Module: Mesa
Branch: master
Commit: d4079353278b115ca4d6596fdc84a64915ab4524
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d4079353278b115ca4d6596fdc84a64915ab4524

Author: Matt Turner <matts...@gmail.com>
Date:   Mon Oct  2 22:15:07 2017 -0700

i965: Fix src0 vs src1 typo

A typo caused us to copy src0's reg file to src1 rather than reading
src1's as intended. This caused us to fail to compact instructions like

   mov(8)   g4<1>D0D  { align1 1Q };

because src1 was set to immediate rather than architecture file. Fixing
this reenables compaction (after the precompact() pass changes the data
types):

   mov(8)   g4<1>UD   0xUD{ align1 1Q compacted };

Fixes: 1cb0a7941b27 ("i965: Switch to using the logical register types")
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/brw_eu_compact.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_eu_compact.c 
b/src/intel/compiler/brw_eu_compact.c
index 7674aa8b85..7b32270957 100644
--- a/src/intel/compiler/brw_eu_compact.c
+++ b/src/intel/compiler/brw_eu_compact.c
@@ -998,7 +998,7 @@ precompact(const struct gen_device_info *devinfo, brw_inst 
inst)
  (brw_inst_src0_type(devinfo, ) == BRW_REGISTER_TYPE_DF ||
   brw_inst_src0_type(devinfo, ) == BRW_REGISTER_TYPE_UQ ||
   brw_inst_src0_type(devinfo, ) == BRW_REGISTER_TYPE_Q))) {
-  enum brw_reg_file file = brw_inst_src0_reg_file(devinfo, );
+  enum brw_reg_file file = brw_inst_src1_reg_file(devinfo, );
   brw_inst_set_src1_file_type(devinfo, , file, BRW_REGISTER_TYPE_UD);
}
 

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Mesa (master): i965: Validate " Special Requirements for Handling Double Precision Data Types"

[Matt Turner]

Module: Mesa
Branch: master
Commit: 2572c2771d0cab0b9bc489d354ede44dfc88547b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2572c2771d0cab0b9bc489d354ede44dfc88547b

Author: Matt Turner <matts...@gmail.com>
Date:   Tue Aug 29 18:29:29 2017 -0700

i965: Validate "Special Requirements for Handling Double Precision Data Types"

I did not implement:

   CNL's restriction on 64-bit int + align16, because I don't think
   we'll ever use this combination regardless of hardware generation.

   The restriction on immediate DF -> F conversions, because there's no
   reason to ever generate that, and I don't even know how DF -> F
   conversions are supposed to work in Align16 since (1) the dst stride
   must be 1, but (2) the dst stride would have to be 2 for src and dst
   strides to be aligned.

---

 src/intel/compiler/brw_eu_validate.c| 169 +
 src/intel/compiler/test_eu_validate.cpp | 623 
 2 files changed, 792 insertions(+)

diff --git a/src/intel/compiler/brw_eu_validate.c 
b/src/intel/compiler/brw_eu_validate.c
index 8fcc529366..8568f712d7 100644
--- a/src/intel/compiler/brw_eu_validate.c
+++ b/src/intel/compiler/brw_eu_validate.c
@@ -1085,6 +1085,174 @@ vector_immediate_restrictions(const struct 
gen_device_info *devinfo,
return error_msg;
 }
 
+static struct string
+special_requirements_for_handling_double_precision_data_types(
+   const struct gen_device_info *devinfo,
+   const brw_inst *inst)
+{
+   unsigned num_sources = num_sources_from_inst(devinfo, inst);
+   struct string error_msg = { .str = NULL, .len = 0 };
+
+   if (num_sources == 3 || num_sources == 0)
+  return (struct string){};
+
+   enum brw_reg_type exec_type = execution_type(devinfo, inst);
+   unsigned exec_type_size = brw_reg_type_to_size(exec_type);
+
+   enum brw_reg_file dst_file = brw_inst_dst_reg_file(devinfo, inst);
+   enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst);
+   unsigned dst_type_size = brw_reg_type_to_size(dst_type);
+   unsigned dst_hstride = STRIDE(brw_inst_dst_hstride(devinfo, inst));
+   unsigned dst_reg = brw_inst_dst_da_reg_nr(devinfo, inst);
+   unsigned dst_subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst);
+   unsigned dst_address_mode = brw_inst_dst_address_mode(devinfo, inst);
+
+   bool is_integer_dword_multiply =
+  devinfo->gen >= 8 &&
+  brw_inst_opcode(devinfo, inst) == BRW_OPCODE_MUL &&
+  (brw_inst_src0_type(devinfo, inst) == BRW_REGISTER_TYPE_D ||
+   brw_inst_src0_type(devinfo, inst) == BRW_REGISTER_TYPE_UD) &&
+  (brw_inst_src1_type(devinfo, inst) == BRW_REGISTER_TYPE_D ||
+   brw_inst_src1_type(devinfo, inst) == BRW_REGISTER_TYPE_UD);
+
+   if (dst_type_size != 8 && exec_type_size != 8 && !is_integer_dword_multiply)
+  return (struct string){};
+
+   for (unsigned i = 0; i < num_sources; i++) {
+  unsigned vstride, width, hstride, type_size, reg, subreg, address_mode;
+  bool is_scalar_region;
+  enum brw_reg_file file;
+  enum brw_reg_type type;
+
+#define DO_SRC(n)  
\
+  if (brw_inst_src ## n ## _reg_file(devinfo, inst) == 
\
+  BRW_IMMEDIATE_VALUE) 
\
+ continue; 
\
+   
\
+  is_scalar_region = src ## n ## _has_scalar_region(devinfo, inst);
\
+  vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst));  
\
+  width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst));   
\
+  hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst));  
\
+  file = brw_inst_src ## n ## _reg_file(devinfo, inst);
\
+  type = brw_inst_src ## n ## _type(devinfo, inst);
\
+  type_size = brw_reg_type_to_size(type);  
\
+  reg = brw_inst_src ## n ## _da_reg_nr(devinfo, inst);
\
+  subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); 
\
+  address_mode = brw_inst_src ## n ## _address_mode(devinfo, inst)
+
+  if (i == 0) {
+ DO_SRC(0);
+  } else {
+ DO_SRC(1);
+  }
+#undef DO_SRC
+
+  /* The PRMs say that for CHV, BXT:
+   *
+   *When source or destination datatype is 64b or operation is integer
+   *DWord multiply, regioning in Align1 must follow these rules:
+   *
+   *1. Source and Destination horizontal stride must be aligned to the
+   *   same qword.
+   *2. Regioning must ensure Src.Vstride = Src.Width * Src.Hstride.
+   *3. Source and Destination offset must be the same, except t

Mesa (master): docs: GL_ARB_indirect_parameters is now supported on i965/ gen7+

[Matt Turner]

Module: Mesa
Branch: master
Commit: e057cda2efe83201637b0398cc45fed797432863
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e057cda2efe83201637b0398cc45fed797432863

Author: Matt Turner <matts...@gmail.com>
Date:   Mon Oct  2 22:27:46 2017 -0700

docs: GL_ARB_indirect_parameters is now supported on i965/gen7+

---

 docs/features.txt | 2 +-
 docs/relnotes/17.3.0.html | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/docs/features.txt b/docs/features.txt
index c186dc70da..61fff7459b 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -224,7 +224,7 @@ GL 4.5, GLSL 4.50 -- all DONE: nvc0, radeonsi
 GL 4.6, GLSL 4.60
 
   GL_ARB_gl_spirv   in progress (Nicolai 
Hähnle, Ian Romanick)
-  GL_ARB_indirect_parametersDONE (nvc0, radeonsi)
+  GL_ARB_indirect_parametersDONE (i965/gen7+, 
nvc0, radeonsi)
   GL_ARB_pipeline_statistics_query  DONE (i965, nvc0, 
radeonsi, llvmpipe, softpipe, swr)
   GL_ARB_polygon_offset_clamp   DONE (i965, nv50, 
nvc0, r600, radeonsi, llvmpipe, swr)
   GL_ARB_shader_atomic_counter_ops  DONE (i965/gen7+, 
nvc0, radeonsi, softpipe)
diff --git a/docs/relnotes/17.3.0.html b/docs/relnotes/17.3.0.html
index 4a74284632..2c3f6c110d 100644
--- a/docs/relnotes/17.3.0.html
+++ b/docs/relnotes/17.3.0.html
@@ -44,6 +44,7 @@ Note: some of the new features are only available with 
certain drivers.
 
 
 
+GL_ARB_indirect_parameters on i965/gen7+
 GL_ARB_polygon_offset_clamp on i965, nv50, nvc0, r600, radeonsi, llvmpipe, 
swr
 GL_ARB_transform_feedback_overflow_query on radeonsi
 GL_ARB_texture_filter_anisotropic on i965, nv50, nvc0, r600, radeonsi

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Mesa (master): docs: Document that libtxc_dxtn is now no longer needed

[Matt Turner]

Module: Mesa
Branch: master
Commit: d400348c73f0901eb24ff4d1562043d3119ef439
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d400348c73f0901eb24ff4d1562043d3119ef439

Author: Matt Turner <matts...@gmail.com>
Date:   Mon Oct  2 22:30:29 2017 -0700

docs: Document that libtxc_dxtn is now no longer needed

---

 docs/relnotes/17.3.0.html | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/relnotes/17.3.0.html b/docs/relnotes/17.3.0.html
index 2c3f6c110d..1239d1bfae 100644
--- a/docs/relnotes/17.3.0.html
+++ b/docs/relnotes/17.3.0.html
@@ -44,6 +44,7 @@ Note: some of the new features are only available with 
certain drivers.
 
 
 
+libtxc_dxtn is now integrated into Mesa. GL_EXT_texture_compression_s3tc 
and GL_ANGLE_texture_compression_dxt are now always enabled on drivers that 
support them
 GL_ARB_indirect_parameters on i965/gen7+
 GL_ARB_polygon_offset_clamp on i965, nv50, nvc0, r600, radeonsi, llvmpipe, 
swr
 GL_ARB_transform_feedback_overflow_query on radeonsi

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Mesa (master): mesa/st: Drop has_lib_dxtc argument from st_init_extensions ()

[Matt Turner]

Module: Mesa
Branch: master
Commit: f6c56e07fc5a8e81fd90688c9fee239f18c3480e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f6c56e07fc5a8e81fd90688c9fee239f18c3480e

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Sep 27 21:19:23 2017 -0700

mesa/st: Drop has_lib_dxtc argument from st_init_extensions()

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>

---

 src/mesa/state_tracker/st_context.c| 2 +-
 src/mesa/state_tracker/st_extensions.c | 8 +---
 src/mesa/state_tracker/st_extensions.h | 3 +--
 src/mesa/state_tracker/st_manager.c| 2 +-
 4 files changed, 4 insertions(+), 11 deletions(-)

diff --git a/src/mesa/state_tracker/st_context.c 
b/src/mesa/state_tracker/st_context.c
index 2422640d84..9610ad3014 100644
--- a/src/mesa/state_tracker/st_context.c
+++ b/src/mesa/state_tracker/st_context.c
@@ -406,7 +406,7 @@ st_create_context_priv( struct gl_context *ctx, struct 
pipe_context *pipe,
/* GL limits and extensions */
st_init_limits(pipe->screen, >Const, >Extensions);
st_init_extensions(pipe->screen, >Const,
-  >Extensions, >options, GL_TRUE);
+  >Extensions, >options);
 
if (st_have_perfmon(st)) {
   ctx->Extensions.AMD_performance_monitor = GL_TRUE;
diff --git a/src/mesa/state_tracker/st_extensions.c 
b/src/mesa/state_tracker/st_extensions.c
index 4f2ad35d56..c3c7d6f9f8 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -572,8 +572,7 @@ get_max_samples_for_formats(struct pipe_screen *screen,
 void st_init_extensions(struct pipe_screen *screen,
 struct gl_constants *consts,
 struct gl_extensions *extensions,
-struct st_config_options *options,
-boolean has_lib_dxtc)
+struct st_config_options *options)
 {
unsigned i;
GLboolean *extension_table = (GLboolean *) extensions;
@@ -966,11 +965,6 @@ void st_init_extensions(struct pipe_screen *screen,
 
/* Below are the cases which cannot be moved into tables easily. */
 
-   if (!has_lib_dxtc && !options->force_s3tc_enable) {
-  extensions->EXT_texture_compression_s3tc = GL_FALSE;
-  extensions->ANGLE_texture_compression_dxt = GL_FALSE;
-   }
-
if (screen->get_shader_param(screen, PIPE_SHADER_TESS_CTRL,
 PIPE_SHADER_CAP_MAX_INSTRUCTIONS) > 0) {
   extensions->ARB_tessellation_shader = GL_TRUE;
diff --git a/src/mesa/state_tracker/st_extensions.h 
b/src/mesa/state_tracker/st_extensions.h
index faff11fd5d..951185caa3 100644
--- a/src/mesa/state_tracker/st_extensions.h
+++ b/src/mesa/state_tracker/st_extensions.h
@@ -40,8 +40,7 @@ extern void st_init_limits(struct pipe_screen *screen,
 extern void st_init_extensions(struct pipe_screen *screen,
struct gl_constants *consts,
struct gl_extensions *extensions,
-   struct st_config_options *options,
-   boolean has_lib_dxtc);
+   struct st_config_options *options);
 
 
 #endif /* ST_EXTENSIONS_H */
diff --git a/src/mesa/state_tracker/st_manager.c 
b/src/mesa/state_tracker/st_manager.c
index 6c7d836827..50bc3c33c6 100644
--- a/src/mesa/state_tracker/st_manager.c
+++ b/src/mesa/state_tracker/st_manager.c
@@ -1166,7 +1166,7 @@ get_version(struct pipe_screen *screen,
_mesa_init_extensions();
 
st_init_limits(screen, , );
-   st_init_extensions(screen, , , options, GL_TRUE);
+   st_init_extensions(screen, , , options);
 
return _mesa_get_version(, , api);
 }

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Mesa (master): gallium: Remove util_format_s3tc_enabled

[Matt Turner]

Module: Mesa
Branch: master
Commit: 3a8a5e77e8f992aaa3539e060885138c2fcddad1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3a8a5e77e8f992aaa3539e060885138c2fcddad1

Author: Matt Turner <matts...@gmail.com>
Date:   Thu Sep 28 14:16:18 2017 -0700

gallium: Remove util_format_s3tc_enabled

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>

---

 src/gallium/auxiliary/util/u_format.c |  4 --
 src/gallium/auxiliary/util/u_format_s3tc.c| 54 +--
 src/gallium/auxiliary/util/u_format_s3tc.h|  2 -
 src/gallium/drivers/llvmpipe/lp_screen.c  |  4 --
 src/gallium/drivers/llvmpipe/lp_test_format.c |  5 ---
 src/gallium/drivers/r300/r300_screen.c|  2 +-
 src/gallium/drivers/r300/r300_texture.c   |  4 --
 src/gallium/drivers/r600/r600_state_common.c  |  4 --
 src/gallium/drivers/radeonsi/si_state.c   |  4 --
 src/gallium/drivers/softpipe/sp_screen.c  |  4 --
 src/gallium/drivers/swr/swr_screen.cpp|  4 --
 src/gallium/drivers/virgl/virgl_screen.c  |  4 +-
 src/gallium/state_trackers/dri/dri_screen.c   | 13 ---
 src/gallium/tests/unit/u_format_test.c|  5 ---
 14 files changed, 3 insertions(+), 110 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_format.c 
b/src/gallium/auxiliary/util/u_format.c
index a6d42a428d..0fc3231654 100644
--- a/src/gallium/auxiliary/util/u_format.c
+++ b/src/gallium/auxiliary/util/u_format.c
@@ -242,10 +242,6 @@ util_format_is_supported(enum pipe_format format, unsigned 
bind)
   return FALSE;
}
 
-   if (util_format_is_s3tc(format) && !util_format_s3tc_enabled) {
-  return FALSE;
-   }
-
 #ifndef TEXTURE_FLOAT_ENABLED
if ((bind & PIPE_BIND_RENDER_TARGET) &&
format != PIPE_FORMAT_R9G9B9E5_FLOAT &&
diff --git a/src/gallium/auxiliary/util/u_format_s3tc.c 
b/src/gallium/auxiliary/util/u_format_s3tc.c
index 8c4f2150be..031255f2b3 100644
--- a/src/gallium/auxiliary/util/u_format_s3tc.c
+++ b/src/gallium/auxiliary/util/u_format_s3tc.c
@@ -28,17 +28,7 @@
 #include "u_format.h"
 #include "u_format_s3tc.h"
 #include "util/format_srgb.h"
-
-
-#if defined(_WIN32) || defined(WIN32)
-#define DXTN_LIBNAME "dxtn.dll"
-#elif defined(__CYGWIN__)
-#define DXTN_LIBNAME "cygtxc_dxtn.dll"
-#elif defined(__APPLE__)
-#define DXTN_LIBNAME "libtxc_dxtn.dylib"
-#else
-#define DXTN_LIBNAME "libtxc_dxtn.so"
-#endif
+#include "../../../mesa/main/texcompress_s3tc_tmp.h"
 
 
 static void
@@ -93,8 +83,6 @@ util_format_dxtn_pack_stub(int src_comps,
 }
 
 
-boolean util_format_s3tc_enabled = FALSE;
-
 util_format_dxtn_fetch_t util_format_dxt1_rgb_fetch = 
util_format_dxt1_rgb_fetch_stub;
 util_format_dxtn_fetch_t util_format_dxt1_rgba_fetch = 
util_format_dxt1_rgba_fetch_stub;
 util_format_dxtn_fetch_t util_format_dxt3_rgba_fetch = 
util_format_dxt3_rgba_fetch_stub;
@@ -107,56 +95,16 @@ void
 util_format_s3tc_init(void)
 {
static boolean first_time = TRUE;
-   struct util_dl_library *library = NULL;
-   util_dl_proc fetch_2d_texel_rgb_dxt1;
-   util_dl_proc fetch_2d_texel_rgba_dxt1;
-   util_dl_proc fetch_2d_texel_rgba_dxt3;
-   util_dl_proc fetch_2d_texel_rgba_dxt5;
-   util_dl_proc tx_compress_dxtn;
 
if (!first_time)
   return;
first_time = FALSE;
 
-   if (util_format_s3tc_enabled)
-  return;
-
-   library = util_dl_open(DXTN_LIBNAME);
-   if (!library) {
-  debug_printf("couldn't open " DXTN_LIBNAME ", software DXTn "
-   "compression/decompression unavailable\n");
-  return;
-   }
-
-   fetch_2d_texel_rgb_dxt1 =
- util_dl_get_proc_address(library, "fetch_2d_texel_rgb_dxt1");
-   fetch_2d_texel_rgba_dxt1 =
- util_dl_get_proc_address(library, "fetch_2d_texel_rgba_dxt1");
-   fetch_2d_texel_rgba_dxt3 =
- util_dl_get_proc_address(library, "fetch_2d_texel_rgba_dxt3");
-   fetch_2d_texel_rgba_dxt5 =
- util_dl_get_proc_address(library, "fetch_2d_texel_rgba_dxt5");
-   tx_compress_dxtn =
- util_dl_get_proc_address(library, "tx_compress_dxtn");
-
-   if (!util_format_dxt1_rgb_fetch ||
-   !util_format_dxt1_rgba_fetch ||
-   !util_format_dxt3_rgba_fetch ||
-   !util_format_dxt5_rgba_fetch ||
-   !util_format_dxtn_pack) {
-  debug_printf("couldn't reference all symbols in " DXTN_LIBNAME
-   ", software DXTn compression/decompression "
-   "unavailable\n");
-  util_dl_close(library);
-  return;
-   }
-
util_format_dxt1_rgb_fetch = 
(util_format_dxtn_fetch_t)fetch_2d_texel_rgb_dxt1;
util_format_dxt1_rgba_fetch = 
(util_format_dxtn_fetch_t)fetch_2d_texel_rgba_dxt1;
util_format_dxt3_rgba_fetch = 
(util_format_dxtn_fetch_t)fetch_2d_texel_rgba_dxt3;
util_format_dxt5_

Mesa (master): travis: Remove libtxc_dxtn from the build

[Matt Turner]

Module: Mesa
Branch: master
Commit: 40ef8362e5524d497eba10a10a775270329ad814
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=40ef8362e5524d497eba10a10a775270329ad814

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Sep 27 21:41:26 2017 -0700

travis: Remove libtxc_dxtn from the build

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>

---

 .travis.yml | 14 --
 1 file changed, 14 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index d9a8bf5a9d..088295e133 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -20,7 +20,6 @@ env:
 - XCBPROTO_VERSION=xcb-proto-1.11
 - LIBXCB_VERSION=libxcb-1.11
 - LIBXSHMFENCE_VERSION=libxshmfence-1.2
-- LIBTXC_DXTN_VERSION=libtxc_dxtn-1.0.1
 - LIBVDPAU_VERSION=libvdpau-1.1
 - LIBVA_VERSION=libva-1.6.2
 - LIBWAYLAND_VERSION=wayland-1.11.1
@@ -442,19 +441,6 @@ install:
   - tar -jxvf $LIBXSHMFENCE_VERSION.tar.bz2
   - (cd $LIBXSHMFENCE_VERSION && ./configure --prefix=$HOME/prefix && make 
install)
 
-  # libtxc-dxtn uses the patented S3 Texture Compression
-  # algorithm. Therefore, we don't want to use this library but it is
-  # still possible through setting the USE_TXC_DXTN variable to yes in
-  # the travis web UI.
-  #
-  # According to Wikipedia, the patent expires on October 2, 2017:
-  # https://en.wikipedia.org/wiki/S3_Texture_Compression#Patent
-  - if test "x$USE_TXC_DXTN" = xyes; then
-  wget 
https://people.freedesktop.org/~cbrill/libtxc_dxtn/$LIBTXC_DXTN_VERSION.tar.bz2;
-  tar -jxvf $LIBTXC_DXTN_VERSION.tar.bz2;
-  (cd $LIBTXC_DXTN_VERSION && ./configure --prefix=$HOME/prefix && make 
install);
-fi
-
   - wget 
http://people.freedesktop.org/~aplattner/vdpau/$LIBVDPAU_VERSION.tar.bz2
   - tar -jxvf $LIBVDPAU_VERSION.tar.bz2
   - (cd $LIBVDPAU_VERSION && ./configure --prefix=$HOME/prefix && make install)

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Mesa (master): mesa: Drop function pointer checks in s3tc code

[Matt Turner]

Module: Mesa
Branch: master
Commit: 78c6221f18ab451f2e57bc61852595a60f82e3cb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=78c6221f18ab451f2e57bc61852595a60f82e3cb

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Sep 27 21:24:27 2017 -0700

mesa: Drop function pointer checks in s3tc code

Now never null!

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>

---

 src/mesa/main/texcompress_s3tc.c | 193 ---
 1 file changed, 60 insertions(+), 133 deletions(-)

diff --git a/src/mesa/main/texcompress_s3tc.c b/src/mesa/main/texcompress_s3tc.c
index e74e4c402a..14067f0e99 100644
--- a/src/mesa/main/texcompress_s3tc.c
+++ b/src/mesa/main/texcompress_s3tc.c
@@ -92,14 +92,9 @@ _mesa_texstore_rgb_dxt1(TEXSTORE_PARAMS)
 
dst = dstSlices[0];
 
-   if (tx_compress_dxtn) {
-  (*tx_compress_dxtn)(3, srcWidth, srcHeight, pixels,
-  GL_COMPRESSED_RGB_S3TC_DXT1_EXT,
-  dst, dstRowStride);
-   }
-   else {
-  _mesa_warning(ctx, "external dxt library not available: 
texstore_rgb_dxt1");
-   }
+   tx_compress_dxtn(3, srcWidth, srcHeight, pixels,
+GL_COMPRESSED_RGB_S3TC_DXT1_EXT,
+dst, dstRowStride);
 
free((void *) tempImage);
 
@@ -150,14 +145,9 @@ _mesa_texstore_rgba_dxt1(TEXSTORE_PARAMS)
 
dst = dstSlices[0];
 
-   if (tx_compress_dxtn) {
-  (*tx_compress_dxtn)(4, srcWidth, srcHeight, pixels,
-  GL_COMPRESSED_RGBA_S3TC_DXT1_EXT,
-  dst, dstRowStride);
-   }
-   else {
-  _mesa_warning(ctx, "external dxt library not available: 
texstore_rgba_dxt1");
-   }
+   tx_compress_dxtn(4, srcWidth, srcHeight, pixels,
+GL_COMPRESSED_RGBA_S3TC_DXT1_EXT,
+dst, dstRowStride);
 
free((void*) tempImage);
 
@@ -207,14 +197,9 @@ _mesa_texstore_rgba_dxt3(TEXSTORE_PARAMS)
 
dst = dstSlices[0];
 
-   if (tx_compress_dxtn) {
-  (*tx_compress_dxtn)(4, srcWidth, srcHeight, pixels,
-  GL_COMPRESSED_RGBA_S3TC_DXT3_EXT,
-  dst, dstRowStride);
-   }
-   else {
-  _mesa_warning(ctx, "external dxt library not available: 
texstore_rgba_dxt3");
-   }
+   tx_compress_dxtn(4, srcWidth, srcHeight, pixels,
+GL_COMPRESSED_RGBA_S3TC_DXT3_EXT,
+dst, dstRowStride);
 
free((void *) tempImage);
 
@@ -264,14 +249,9 @@ _mesa_texstore_rgba_dxt5(TEXSTORE_PARAMS)
 
dst = dstSlices[0];
 
-   if (tx_compress_dxtn) {
-  (*tx_compress_dxtn)(4, srcWidth, srcHeight, pixels,
-  GL_COMPRESSED_RGBA_S3TC_DXT5_EXT,
-  dst, dstRowStride);
-   }
-   else {
-  _mesa_warning(ctx, "external dxt library not available: 
texstore_rgba_dxt5");
-   }
+   tx_compress_dxtn(4, srcWidth, srcHeight, pixels,
+GL_COMPRESSED_RGBA_S3TC_DXT5_EXT,
+dst, dstRowStride);
 
free((void *) tempImage);
 
@@ -279,85 +259,52 @@ _mesa_texstore_rgba_dxt5(TEXSTORE_PARAMS)
 }
 
 
-/** Report problem with dxt texture decompression, once */
-static void
-problem(const char *func)
-{
-   static GLboolean warned = GL_FALSE;
-   if (!warned) {
-  _mesa_debug(NULL, "attempted to decode DXT texture without "
-  "library available: %s\n", func);
-  warned = GL_TRUE;
-   }
-}
-
-
 static void
 fetch_rgb_dxt1(const GLubyte *map,
GLint rowStride, GLint i, GLint j, GLfloat *texel)
 {
-   if (fetch_2d_texel_rgb_dxt1) {
-  GLubyte tex[4];
-  fetch_2d_texel_rgb_dxt1(rowStride, map, i, j, tex);
-  texel[RCOMP] = UBYTE_TO_FLOAT(tex[RCOMP]);
-  texel[GCOMP] = UBYTE_TO_FLOAT(tex[GCOMP]);
-  texel[BCOMP] = UBYTE_TO_FLOAT(tex[BCOMP]);
-  texel[ACOMP] = UBYTE_TO_FLOAT(tex[ACOMP]);
-   }
-   else {
-  problem("rgb_dxt1");
-   }
+   GLubyte tex[4];
+   fetch_2d_texel_rgb_dxt1(rowStride, map, i, j, tex);
+   texel[RCOMP] = UBYTE_TO_FLOAT(tex[RCOMP]);
+   texel[GCOMP] = UBYTE_TO_FLOAT(tex[GCOMP]);
+   texel[BCOMP] = UBYTE_TO_FLOAT(tex[BCOMP]);
+   texel[ACOMP] = UBYTE_TO_FLOAT(tex[ACOMP]);
 }
 
 static void
 fetch_rgba_dxt1(const GLubyte *map,
 GLint rowStride, GLint i, GLint j, GLfloat *texel)
 {
-   if (fetch_2d_texel_rgba_dxt1) {
-  GLubyte tex[4];
-  fetch_2d_texel_rgba_dxt1(rowStride, map, i, j, tex);
-  texel[RCOMP] = UBYTE_TO_FLOAT(tex[RCOMP]);
-  texel[GCOMP] = UBYTE_TO_FLOAT(tex[GCOMP]);
-  texel[BCOMP] = UBYTE_TO_FLOAT(tex[BCOMP]);
-  texel[ACOMP] = UBYTE_TO_FLOAT(tex[ACOMP]);
-   }
-   else {
-  problem("rgba_dxt1");
-   }
+   GLubyte tex[4];
+   fetch_2d_texel_rgba_dxt1(rowStride, map, i, j, tex);
+   texel[RCOMP] = UBYTE_TO_FLOAT(tex[RCOMP]);
+   texel[GCOMP] = UBYTE_TO_F

Mesa (master): mesa: Remove force_s3tc_enable driconf variable

[Matt Turner]

Module: Mesa
Branch: master
Commit: c17c47207b96172ca9c85a16f7fb7f1d3ea959d8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c17c47207b96172ca9c85a16f7fb7f1d3ea959d8

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Sep 27 21:37:46 2017 -0700

mesa: Remove force_s3tc_enable driconf variable

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>

---

 src/gallium/auxiliary/pipe-loader/driinfo_gallium.h | 1 -
 src/gallium/include/state_tracker/st_api.h  | 1 -
 src/gallium/state_trackers/dri/dri_screen.c | 2 --
 src/gallium/state_trackers/osmesa/osmesa.c  | 1 -
 src/mesa/drivers/dri/i915/intel_screen.c| 1 -
 src/mesa/drivers/dri/i965/intel_screen.c| 2 --
 src/mesa/drivers/dri/radeon/radeon_screen.c | 2 --
 src/util/xmlpool/t_options.h| 5 -
 8 files changed, 15 deletions(-)

diff --git a/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h 
b/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
index 48a57c981e..d2d2c9d3a5 100644
--- a/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
+++ b/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
@@ -7,7 +7,6 @@ DRI_CONF_SECTION_PERFORMANCE
 DRI_CONF_SECTION_END
 
 DRI_CONF_SECTION_QUALITY
-   DRI_CONF_FORCE_S3TC_ENABLE("false")
DRI_CONF_PP_CELSHADE(0)
DRI_CONF_PP_NORED(0)
DRI_CONF_PP_NOGREEN(0)
diff --git a/src/gallium/include/state_tracker/st_api.h 
b/src/gallium/include/state_tracker/st_api.h
index 2eaf891ab7..4d27dad5c5 100644
--- a/src/gallium/include/state_tracker/st_api.h
+++ b/src/gallium/include/state_tracker/st_api.h
@@ -246,7 +246,6 @@ struct st_config_options
boolean disable_shader_bit_encoding;
boolean force_glsl_extensions_warn;
unsigned force_glsl_version;
-   boolean force_s3tc_enable;
boolean allow_glsl_extension_directive_midshader;
boolean allow_glsl_builtin_variable_redeclaration;
boolean allow_higher_compat_version;
diff --git a/src/gallium/state_trackers/dri/dri_screen.c 
b/src/gallium/state_trackers/dri/dri_screen.c
index 803264a58f..91f50fe8e3 100644
--- a/src/gallium/state_trackers/dri/dri_screen.c
+++ b/src/gallium/state_trackers/dri/dri_screen.c
@@ -72,8 +72,6 @@ dri_fill_st_options(struct dri_screen *screen)
   driQueryOptionb(optionCache, "force_glsl_extensions_warn");
options->force_glsl_version =
   driQueryOptioni(optionCache, "force_glsl_version");
-   options->force_s3tc_enable =
-  driQueryOptionb(optionCache, "force_s3tc_enable");
options->allow_glsl_extension_directive_midshader =
   driQueryOptionb(optionCache, "allow_glsl_extension_directive_midshader");
options->allow_glsl_builtin_variable_redeclaration =
diff --git a/src/gallium/state_trackers/osmesa/osmesa.c 
b/src/gallium/state_trackers/osmesa/osmesa.c
index 751d255c54..2f9558db31 100644
--- a/src/gallium/state_trackers/osmesa/osmesa.c
+++ b/src/gallium/state_trackers/osmesa/osmesa.c
@@ -688,7 +688,6 @@ OSMesaCreateContextAttribs(const int *attribList, 
OSMesaContext sharelist)
attribs.options.disable_blend_func_extended = FALSE;
attribs.options.disable_glsl_line_continuations = FALSE;
attribs.options.disable_shader_bit_encoding = FALSE;
-   attribs.options.force_s3tc_enable = FALSE;
attribs.options.force_glsl_version = 0;
 
osmesa_init_st_visual(,
diff --git a/src/mesa/drivers/dri/i915/intel_screen.c 
b/src/mesa/drivers/dri/i915/intel_screen.c
index 6e32ac22cb..ba49e90fef 100644
--- a/src/mesa/drivers/dri/i915/intel_screen.c
+++ b/src/mesa/drivers/dri/i915/intel_screen.c
@@ -67,7 +67,6 @@ DRI_CONF_BEGIN
 
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
-  DRI_CONF_FORCE_S3TC_ENABLE("false")
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
   DRI_CONF_NO_RAST("false")
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index bd1365f232..77df6eddba 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -61,8 +61,6 @@ DRI_CONF_BEGIN
DRI_CONF_SECTION_END
 
DRI_CONF_SECTION_QUALITY
-  DRI_CONF_FORCE_S3TC_ENABLE("false")
-
   DRI_CONF_PRECISE_TRIG("false")
 
   DRI_CONF_OPT_BEGIN(clamp_max_samples, int, -1)
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c 
b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 750a654922..51af452e24 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -86,7 +86,6 @@ DRI_CONF_BEGIN
 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
 DRI_CONF_NO_NEG_LOD_BIAS("false")
-DRI_CONF_FORCE_S3TC_ENABLE("false")
 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_D

Mesa (master): mesa: Call DXTn functions directly

[Matt Turner]

Module: Mesa
Branch: master
Commit: 34cf3c43beed2fafb4512e921f39c818478f86d7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=34cf3c43beed2fafb4512e921f39c818478f86d7

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Sep 27 21:04:36 2017 -0700

mesa: Call DXTn functions directly

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>

---

 src/mesa/main/texcompress_s3tc.c | 117 +--
 1 file changed, 25 insertions(+), 92 deletions(-)

diff --git a/src/mesa/main/texcompress_s3tc.c b/src/mesa/main/texcompress_s3tc.c
index e08ed23d3a..e74e4c402a 100644
--- a/src/mesa/main/texcompress_s3tc.c
+++ b/src/mesa/main/texcompress_s3tc.c
@@ -43,78 +43,11 @@
 #include "util/format_srgb.h"
 
 
-#if defined(_WIN32) || defined(WIN32)
-#define DXTN_LIBNAME "dxtn.dll"
-#define RTLD_LAZY 0
-#define RTLD_GLOBAL 0
-#elif defined(__CYGWIN__)
-#define DXTN_LIBNAME "cygtxc_dxtn.dll"
-#else
-#define DXTN_LIBNAME "libtxc_dxtn.so"
-#endif
-
-typedef void (*dxtFetchTexelFuncExt)( GLint srcRowstride, const GLubyte 
*pixdata, GLint col, GLint row, GLvoid *texelOut );
-
-static dxtFetchTexelFuncExt fetch_ext_rgb_dxt1 = NULL;
-static dxtFetchTexelFuncExt fetch_ext_rgba_dxt1 = NULL;
-static dxtFetchTexelFuncExt fetch_ext_rgba_dxt3 = NULL;
-static dxtFetchTexelFuncExt fetch_ext_rgba_dxt5 = NULL;
-
-typedef void (*dxtCompressTexFuncExt)(GLint srccomps, GLint width,
-  GLint height, const GLubyte *srcPixData,
-  GLenum destformat, GLubyte *dest,
-  GLint dstRowStride);
-
-static dxtCompressTexFuncExt ext_tx_compress_dxtn = NULL;
-
-static void *dxtlibhandle = NULL;
-
-
 void
 _mesa_init_texture_s3tc( struct gl_context *ctx )
 {
/* called during context initialization */
-   ctx->Mesa_DXTn = GL_FALSE;
-   if (!dxtlibhandle) {
-  dxtlibhandle = _mesa_dlopen(DXTN_LIBNAME, 0);
-  if (!dxtlibhandle) {
-_mesa_warning(ctx, "couldn't open " DXTN_LIBNAME ", software DXTn "
-   "compression/decompression unavailable");
-  }
-  else {
- /* the fetch functions are not per context! Might be problematic... */
- fetch_ext_rgb_dxt1 = (dxtFetchTexelFuncExt)
-_mesa_dlsym(dxtlibhandle, "fetch_2d_texel_rgb_dxt1");
- fetch_ext_rgba_dxt1 = (dxtFetchTexelFuncExt)
-_mesa_dlsym(dxtlibhandle, "fetch_2d_texel_rgba_dxt1");
- fetch_ext_rgba_dxt3 = (dxtFetchTexelFuncExt)
-_mesa_dlsym(dxtlibhandle, "fetch_2d_texel_rgba_dxt3");
- fetch_ext_rgba_dxt5 = (dxtFetchTexelFuncExt)
-_mesa_dlsym(dxtlibhandle, "fetch_2d_texel_rgba_dxt5");
- ext_tx_compress_dxtn = (dxtCompressTexFuncExt)
-_mesa_dlsym(dxtlibhandle, "tx_compress_dxtn");
-
- if (!fetch_ext_rgb_dxt1 ||
- !fetch_ext_rgba_dxt1 ||
- !fetch_ext_rgba_dxt3 ||
- !fetch_ext_rgba_dxt5 ||
- !ext_tx_compress_dxtn) {
-   _mesa_warning(ctx, "couldn't reference all symbols in "
-  DXTN_LIBNAME ", software DXTn compression/decompression "
-  "unavailable");
-fetch_ext_rgb_dxt1 = NULL;
-fetch_ext_rgba_dxt1 = NULL;
-fetch_ext_rgba_dxt3 = NULL;
-fetch_ext_rgba_dxt5 = NULL;
-ext_tx_compress_dxtn = NULL;
-_mesa_dlclose(dxtlibhandle);
-dxtlibhandle = NULL;
- }
-  }
-   }
-   if (dxtlibhandle) {
-  ctx->Mesa_DXTn = GL_TRUE;
-   }
+   ctx->Mesa_DXTn = GL_TRUE;
 }
 
 /**
@@ -159,8 +92,8 @@ _mesa_texstore_rgb_dxt1(TEXSTORE_PARAMS)
 
dst = dstSlices[0];
 
-   if (ext_tx_compress_dxtn) {
-  (*ext_tx_compress_dxtn)(3, srcWidth, srcHeight, pixels,
+   if (tx_compress_dxtn) {
+  (*tx_compress_dxtn)(3, srcWidth, srcHeight, pixels,
   GL_COMPRESSED_RGB_S3TC_DXT1_EXT,
   dst, dstRowStride);
}
@@ -217,8 +150,8 @@ _mesa_texstore_rgba_dxt1(TEXSTORE_PARAMS)
 
dst = dstSlices[0];
 
-   if (ext_tx_compress_dxtn) {
-  (*ext_tx_compress_dxtn)(4, srcWidth, srcHeight, pixels,
+   if (tx_compress_dxtn) {
+  (*tx_compress_dxtn)(4, srcWidth, srcHeight, pixels,
   GL_COMPRESSED_RGBA_S3TC_DXT1_EXT,
   dst, dstRowStride);
}
@@ -274,8 +207,8 @@ _mesa_texstore_rgba_dxt3(TEXSTORE_PARAMS)
 
dst = dstSlices[0];
 
-   if (ext_tx_compress_dxtn) {
-  (*ext_tx_compress_dxtn)(4, srcWidth, srcHeight, pixels,
+   if (tx_compress_dxtn) {
+  (*tx_compress_dxtn)(4, srcWidth, srcHeight, pixels,
   GL_COMPRESSED_RGBA_S3TC_DXT3_EXT,
   dst, dstRowStride);
}
@@ -33

Mesa (master): mesa: Remove commented-out DXTn fetch code

[Matt Turner]

Module: Mesa
Branch: master
Commit: 7ce166f24996d24d56d3effcae181d40
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ce166f24996d24d56d3effcae181d40

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Sep 27 21:43:50 2017 -0700

mesa: Remove commented-out DXTn fetch code

Has been disabled for 12 years.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>

---

 src/mesa/main/texcompress_s3tc_tmp.h | 80 
 1 file changed, 80 deletions(-)

diff --git a/src/mesa/main/texcompress_s3tc_tmp.h 
b/src/mesa/main/texcompress_s3tc_tmp.h
index b67b7a299e..57bbf7e0ae 100644
--- a/src/mesa/main/texcompress_s3tc_tmp.h
+++ b/src/mesa/main/texcompress_s3tc_tmp.h
@@ -150,26 +150,9 @@ void fetch_2d_texel_rgba_dxt3(GLint srcRowStride, const 
GLubyte *pixdata,
 
GLchan *rgba = (GLchan *) texel;
const GLubyte *blksrc = (pixdata + ((srcRowStride + 3) / 4 * (j / 4) + (i / 
4)) * 16);
-#if 0
-   /* Simple 32bit version. */
-/* that's pretty brain-dead for a single pixel, isn't it? */
-   const GLubyte bit_pos = 4 * ((j&3) * 4 + (i&3));
-   const GLuint alpha_low = blksrc[0] | (blksrc[1] << 8) | (blksrc[2] << 16) | 
(blksrc[3] << 24);
-   const GLuint alpha_high = blksrc[4] | (blksrc[5] << 8) | (blksrc[6] << 16) 
| (blksrc[7] << 24);
-
-   dxt135_decode_imageblock(blksrc + 8, (i&3), (j&3), 2, texel);
-   if (bit_pos < 32)
-  rgba[ACOMP] = UBYTE_TO_CHAN( (GLubyte)(EXP4TO8((alpha_low >> bit_pos) & 
15)) );
-   else
-  rgba[ACOMP] = UBYTE_TO_CHAN( (GLubyte)(EXP4TO8((alpha_high >> (bit_pos - 
32)) & 15)) );
-#endif
-#if 1
-/* TODO test this! */
const GLubyte anibble = (blksrc[((j&3) * 4 + (i&3)) / 2] >> (4 * (i&1))) & 
0xf;
dxt135_decode_imageblock(blksrc + 8, (i&3), (j&3), 2, texel);
rgba[ACOMP] = UBYTE_TO_CHAN( (GLubyte)(EXP4TO8(anibble)) );
-#endif
-
 }
 
 void fetch_2d_texel_rgba_dxt5(GLint srcRowStride, const GLubyte *pixdata,
@@ -183,74 +166,12 @@ void fetch_2d_texel_rgba_dxt5(GLint srcRowStride, const 
GLubyte *pixdata,
const GLubyte *blksrc = (pixdata + ((srcRowStride + 3) / 4 * (j / 4) + (i / 
4)) * 16);
const GLubyte alpha0 = blksrc[0];
const GLubyte alpha1 = blksrc[1];
-#if 0
-   const GLubyte bit_pos = 3 * ((j&3) * 4 + (i&3));
-   /* simple 32bit version */
-   const GLuint bits_low = blksrc[2] | (blksrc[3] << 8) | (blksrc[4] << 16) | 
(blksrc[5] << 24);
-   const GLuint bits_high = blksrc[6] | (blksrc[7] << 8);
-   GLubyte code;
-
-   if (bit_pos < 30)
-  code = (GLubyte) ((bits_low >> bit_pos) & 7);
-   else if (bit_pos == 30)
-  code = (GLubyte) ((bits_low >> 30) & 3) | ((bits_high << 2) & 4);
-   else
-  code = (GLubyte) ((bits_high >> (bit_pos - 32)) & 7);
-#endif
-#if 1
-/* TODO test this! */
const GLubyte bit_pos = ((j&3) * 4 + (i&3)) * 3;
const GLubyte acodelow = blksrc[2 + bit_pos / 8];
const GLubyte acodehigh = blksrc[3 + bit_pos / 8];
const GLubyte code = (acodelow >> (bit_pos & 0x7) |
   (acodehigh  << (8 - (bit_pos & 0x7 & 0x7;
-#endif
dxt135_decode_imageblock(blksrc + 8, (i&3), (j&3), 2, texel);
-#if 0
-   if (alpha0 > alpha1) {
-  switch (code) {
-  case 0:
- rgba[ACOMP] = UBYTE_TO_CHAN( alpha0 );
- break;
-  case 1:
- rgba[ACOMP] = UBYTE_TO_CHAN( alpha1 );
- break;
-  case 2:
-  case 3:
-  case 4:
-  case 5:
-  case 6:
-  case 7:
- rgba[ACOMP] = UBYTE_TO_CHAN( ((alpha0 * (8 - code) + (alpha1 * (code 
- 1))) / 7) );
- break;
-  }
-   }
-   else {
-  switch (code) {
-  case 0:
- rgba[ACOMP] = UBYTE_TO_CHAN( alpha0 );
- break;
-  case 1:
- rgba[ACOMP] = UBYTE_TO_CHAN( alpha1 );
- break;
-  case 2:
-  case 3:
-  case 4:
-  case 5:
- rgba[ACOMP] = UBYTE_TO_CHAN( ((alpha0 * (6 - code) + (alpha1 * (code 
- 1))) / 5) );
- break;
-  case 6:
- rgba[ACOMP] = 0;
- break;
-  case 7:
- rgba[ACOMP] = CHAN_MAX;
- break;
-  }
-   }
-#endif
-/* not sure. Which version is faster? */
-#if 1
-/* TODO test this */
if (code == 0)
   rgba[ACOMP] = UBYTE_TO_CHAN( alpha0 );
else if (code == 1)
@@ -263,7 +184,6 @@ void fetch_2d_texel_rgba_dxt5(GLint srcRowStride, const 
GLubyte *pixdata,
   rgba[ACOMP] = 0;
else
   rgba[ACOMP] = CHAN_MAX;
-#endif
 }
 
 

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Mesa (master): build: Remove HAVE_DLOPEN

[Matt Turner]

Module: Mesa
Branch: master
Commit: 74b5568978968f580b9809135198db1015bc55b7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=74b5568978968f580b9809135198db1015bc55b7

Author: Matt Turner <matts...@gmail.com>
Date:   Sun Oct  1 23:20:55 2017 -0700

build: Remove HAVE_DLOPEN

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>

---

 Android.common.mk   | 1 -
 configure.ac| 4 ++--
 meson.build | 1 -
 src/mesa/SConscript | 4 
 4 files changed, 2 insertions(+), 8 deletions(-)

diff --git a/Android.common.mk b/Android.common.mk
index 4d5daf8e9d..483f6c5be2 100644
--- a/Android.common.mk
+++ b/Android.common.mk
@@ -64,7 +64,6 @@ LOCAL_CFLAGS += \
-DHAVE___BUILTIN_UNREACHABLE \
-DHAVE_PTHREAD=1 \
-DHAVE_DLADDR \
-   -DHAVE_DLOPEN \
-DHAVE_DL_ITERATE_PHDR \
-DMAJOR_IN_SYSMACROS \
-fvisibility=hidden \
diff --git a/configure.ac b/configure.ac
index cfc97d9f06..903a3979d4 100644
--- a/configure.ac
+++ b/configure.ac
@@ -831,9 +831,9 @@ AC_LINK_IFELSE([AC_LANG_SOURCE([[
 
 dnl Check to see if dlopen is in default libraries (like Solaris, which
 dnl has it in libc), or if libdl is needed to get it.
-AC_CHECK_FUNC([dlopen], [DEFINES="$DEFINES -DHAVE_DLOPEN"],
+AC_CHECK_FUNC([dlopen], [],
 [AC_CHECK_LIB([dl], [dlopen],
-   [DEFINES="$DEFINES -DHAVE_DLOPEN"; DLOPEN_LIBS="-ldl"])])
+   [DLOPEN_LIBS="-ldl"])])
 AC_SUBST([DLOPEN_LIBS])
 
 dnl Check if that library also has dladdr
diff --git a/meson.build b/meson.build
index 1e0b95fcb1..ecd08651ff 100644
--- a/meson.build
+++ b/meson.build
@@ -264,7 +264,6 @@ if cc.has_function('dlopen')
 else
   dep_dl = cc.find_library('dl')
 endif
-pre_args += '-DHAVE_DLOPEN'
 
 if not cc.has_function('dladdr', dependencies : dep_dl)
   error('dl library doesn\'t have dladdr')
diff --git a/src/mesa/SConscript b/src/mesa/SConscript
index b63e15a3f0..ba98ad4323 100644
--- a/src/mesa/SConscript
+++ b/src/mesa/SConscript
@@ -31,10 +31,6 @@ if env['platform'] == 'windows':
 if not env['gles']:
 # prevent _glapi_* from being declared __declspec(dllimport)
 env.Append(CPPDEFINES = ['_GLAPI_NO_EXPORTS'])
-else:
-env.Append(CPPDEFINES = [
-('HAVE_DLOPEN', '1'),
-])
 
 # parse Makefile.sources
 source_lists = env.ParseSourceList('Makefile.sources')

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Mesa (master): mesa: Remove fprintf referring to libdxtn

[Matt Turner]

Module: Mesa
Branch: master
Commit: fb5338c4b77db70ea26b0745cff1cb3e330a5139
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb5338c4b77db70ea26b0745cff1cb3e330a5139

Author: Matt Turner <matts...@gmail.com>
Date:   Thu Sep 28 14:09:55 2017 -0700

mesa: Remove fprintf referring to libdxtn

When this file is included by Gallium, the fprintf causes it to fail to
compile. This is an unreachable error case, and we shouldn't be calling
fprintf directly.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>

---

 src/mesa/main/texcompress_s3tc_tmp.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/main/texcompress_s3tc_tmp.h 
b/src/mesa/main/texcompress_s3tc_tmp.h
index 3abce6e904..61630f2475 100644
--- a/src/mesa/main/texcompress_s3tc_tmp.h
+++ b/src/mesa/main/texcompress_s3tc_tmp.h
@@ -983,7 +983,7 @@ static void tx_compress_dxtn(GLint srccomps, GLint width, 
GLint height, const GL
   }
   break;
default:
-  fprintf(stderr, "libdxtn: Bad dstFormat %d in tx_compress_dxtn\n", 
destFormat);
+  assert(false);
   return;
}
 }

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Mesa (master): mesa: Combine libtxc_dxtn sources into texcompress_s3tc_tmp.h

[Matt Turner]

Module: Mesa
Branch: master
Commit: f7daa737d17df6d0a847e5c61e48d25e598671f4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f7daa737d17df6d0a847e5c61e48d25e598671f4

Author: Matt Turner <matts...@gmail.com>
Date:   Thu Sep 28 11:29:25 2017 -0700

mesa: Combine libtxc_dxtn sources into texcompress_s3tc_tmp.h

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>

---

 src/mesa/Makefile.sources  |   3 -
 src/mesa/main/texcompress_s3tc.c   |   1 +
 ...{txc_compress_dxtn.c => texcompress_s3tc_tmp.h} | 249 -
 src/mesa/main/txc_dxtn.h   |  55 -
 src/mesa/main/txc_fetch_dxtn.c | 243 
 5 files changed, 245 insertions(+), 306 deletions(-)

diff --git a/src/mesa/Makefile.sources b/src/mesa/Makefile.sources
index 3042da5c8c..2e4cf6f638 100644
--- a/src/mesa/Makefile.sources
+++ b/src/mesa/Makefile.sources
@@ -249,9 +249,6 @@ MAIN_FILES = \
main/textureview.h \
main/transformfeedback.c \
main/transformfeedback.h \
-   main/txc_compress_dxtn.c \
-   main/txc_dxtn.h \
-   main/txc_fetch_dxtn.c \
main/uniform_query.cpp \
main/uniforms.c \
main/uniforms.h \
diff --git a/src/mesa/main/texcompress_s3tc.c b/src/mesa/main/texcompress_s3tc.c
index 992ad058bf..e08ed23d3a 100644
--- a/src/mesa/main/texcompress_s3tc.c
+++ b/src/mesa/main/texcompress_s3tc.c
@@ -37,6 +37,7 @@
 #include "mtypes.h"
 #include "texcompress.h"
 #include "texcompress_s3tc.h"
+#include "texcompress_s3tc_tmp.h"
 #include "texstore.h"
 #include "format_unpack.h"
 #include "util/format_srgb.h"
diff --git a/src/mesa/main/txc_compress_dxtn.c 
b/src/mesa/main/texcompress_s3tc_tmp.h
similarity index 81%
rename from src/mesa/main/txc_compress_dxtn.c
rename to src/mesa/main/texcompress_s3tc_tmp.h
index cf83d08eea..b67b7a299e 100644
--- a/src/mesa/main/txc_compress_dxtn.c
+++ b/src/mesa/main/texcompress_s3tc_tmp.h
@@ -22,9 +22,250 @@
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include 
-#include 
-#include "txc_dxtn.h"
+#ifdef __APPLE__
+#include 
+#else
+#include 
+#endif
+
+typedef GLubyte GLchan;
+#define UBYTE_TO_CHAN(b)  (b)
+#define CHAN_MAX 255
+#define RCOMP 0
+#define GCOMP 1
+#define BCOMP 2
+#define ACOMP 3
+
+void fetch_2d_texel_rgb_dxt1(GLint srcRowStride, const GLubyte *pixdata,
+GLint i, GLint j, GLvoid *texel);
+void fetch_2d_texel_rgba_dxt1(GLint srcRowStride, const GLubyte *pixdata,
+GLint i, GLint j, GLvoid *texel);
+void fetch_2d_texel_rgba_dxt3(GLint srcRowStride, const GLubyte *pixdata,
+GLint i, GLint j, GLvoid *texel);
+void fetch_2d_texel_rgba_dxt5(GLint srcRowStride, const GLubyte *pixdata,
+GLint i, GLint j, GLvoid *texel);
+
+void tx_compress_dxtn(GLint srccomps, GLint width, GLint height,
+ const GLubyte *srcPixData, GLenum destformat,
+ GLubyte *dest, GLint dstRowStride);
+
+#define EXP5TO8R(packedcol)\
+   packedcol) >> 8) & 0xf8) | (((packedcol) >> 13) & 0x7))
+
+#define EXP6TO8G(packedcol)\
+   packedcol) >> 3) & 0xfc) | (((packedcol) >>  9) & 0x3))
+
+#define EXP5TO8B(packedcol)\
+   packedcol) << 3) & 0xf8) | (((packedcol) >>  2) & 0x7))
+
+#define EXP4TO8(col)   \
+   ((col) | ((col) << 4))
+
+/* inefficient. To be efficient, it would be necessary to decode 16 pixels at 
once */
+
+static void dxt135_decode_imageblock ( const GLubyte *img_block_src,
+ GLint i, GLint j, GLuint dxt_type, GLvoid *texel ) {
+   GLchan *rgba = (GLchan *) texel;
+   const GLushort color0 = img_block_src[0] | (img_block_src[1] << 8);
+   const GLushort color1 = img_block_src[2] | (img_block_src[3] << 8);
+   const GLuint bits = img_block_src[4] | (img_block_src[5] << 8) |
+  (img_block_src[6] << 16) | (img_block_src[7] << 24);
+   /* What about big/little endian? */
+   GLubyte bit_pos = 2 * (j * 4 + i) ;
+   GLubyte code = (GLubyte) ((bits >> bit_pos) & 3);
+
+   rgba[ACOMP] = CHAN_MAX;
+   switch (code) {
+   case 0:
+  rgba[RCOMP] = UBYTE_TO_CHAN( EXP5TO8R(color0) );
+  rgba[GCOMP] = UBYTE_TO_CHAN( EXP6TO8G(color0) );
+  rgba[BCOMP] = UBYTE_TO_CHAN( EXP5TO8B(color0) );
+  break;
+   case 1:
+  rgba[RCOMP] = UBYTE_TO_CHAN( EXP5TO8R(color1) );
+  rgba[GCOMP] = UBYTE_TO_CHAN( EXP6TO8G(color1) );
+  rgba[BCOMP] = UBYTE_TO_CHAN( EXP5TO8B(color1) );
+  break;
+   case 2:
+  if ((dxt_type

Mesa (master): gallium: Remove util_format_s3tc_init()

[Matt Turner]

Module: Mesa
Branch: master
Commit: dc546a7bb3fae1d597e5a22d9527540ec4f072c8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dc546a7bb3fae1d597e5a22d9527540ec4f072c8

Author: Matt Turner <matts...@gmail.com>
Date:   Thu Sep 28 14:23:39 2017 -0700

gallium: Remove util_format_s3tc_init()

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>

---

 src/gallium/auxiliary/util/u_format_s3tc.c   | 79 ++--
 src/gallium/auxiliary/util/u_format_s3tc.h   |  4 --
 src/gallium/drivers/freedreno/freedreno_screen.c |  2 -
 src/gallium/drivers/i915/i915_screen.c   |  2 -
 src/gallium/drivers/llvmpipe/lp_screen.c |  2 -
 src/gallium/drivers/llvmpipe/lp_test_format.c|  2 -
 src/gallium/drivers/nouveau/nouveau_screen.c |  2 -
 src/gallium/drivers/r300/r300_screen.c   |  1 -
 src/gallium/drivers/r600/r600_pipe_common.c  |  1 -
 src/gallium/drivers/radeon/r600_pipe_common.c|  1 -
 src/gallium/drivers/softpipe/sp_screen.c |  2 -
 src/gallium/drivers/swr/swr_screen.cpp   |  2 -
 src/gallium/drivers/virgl/virgl_screen.c |  1 -
 src/gallium/tests/unit/u_format_test.c   |  2 -
 14 files changed, 5 insertions(+), 98 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_format_s3tc.c 
b/src/gallium/auxiliary/util/u_format_s3tc.c
index 031255f2b3..3f755e5363 100644
--- a/src/gallium/auxiliary/util/u_format_s3tc.c
+++ b/src/gallium/auxiliary/util/u_format_s3tc.c
@@ -31,81 +31,12 @@
 #include "../../../mesa/main/texcompress_s3tc_tmp.h"
 
 
-static void
-util_format_dxt1_rgb_fetch_stub(int src_stride,
-const uint8_t *src,
-int col, int row,
-uint8_t *dst)
-{
-   assert(0);
-}
-
-
-static void
-util_format_dxt1_rgba_fetch_stub(int src_stride,
- const uint8_t *src,
- int col, int row,
- uint8_t *dst )
-{
-   assert(0);
-}
-
-
-static void
-util_format_dxt3_rgba_fetch_stub(int src_stride,
- const uint8_t *src,
- int col, int row,
- uint8_t *dst )
-{
-   assert(0);
-}
-
-
-static void
-util_format_dxt5_rgba_fetch_stub(int src_stride,
- const uint8_t *src,
- int col, int row,
- uint8_t *dst )
-{
-   assert(0);
-}
+util_format_dxtn_fetch_t util_format_dxt1_rgb_fetch = 
(util_format_dxtn_fetch_t)fetch_2d_texel_rgb_dxt1;
+util_format_dxtn_fetch_t util_format_dxt1_rgba_fetch = 
(util_format_dxtn_fetch_t)fetch_2d_texel_rgba_dxt1;
+util_format_dxtn_fetch_t util_format_dxt3_rgba_fetch = 
(util_format_dxtn_fetch_t)fetch_2d_texel_rgba_dxt3;
+util_format_dxtn_fetch_t util_format_dxt5_rgba_fetch = 
(util_format_dxtn_fetch_t)fetch_2d_texel_rgba_dxt5;
 
-
-static void
-util_format_dxtn_pack_stub(int src_comps,
-   int width, int height,
-   const uint8_t *src,
-   enum util_format_dxtn dst_format,
-   uint8_t *dst,
-   int dst_stride)
-{
-   assert(0);
-}
-
-
-util_format_dxtn_fetch_t util_format_dxt1_rgb_fetch = 
util_format_dxt1_rgb_fetch_stub;
-util_format_dxtn_fetch_t util_format_dxt1_rgba_fetch = 
util_format_dxt1_rgba_fetch_stub;
-util_format_dxtn_fetch_t util_format_dxt3_rgba_fetch = 
util_format_dxt3_rgba_fetch_stub;
-util_format_dxtn_fetch_t util_format_dxt5_rgba_fetch = 
util_format_dxt5_rgba_fetch_stub;
-
-util_format_dxtn_pack_t util_format_dxtn_pack = util_format_dxtn_pack_stub;
-
-
-void
-util_format_s3tc_init(void)
-{
-   static boolean first_time = TRUE;
-
-   if (!first_time)
-  return;
-   first_time = FALSE;
-
-   util_format_dxt1_rgb_fetch = 
(util_format_dxtn_fetch_t)fetch_2d_texel_rgb_dxt1;
-   util_format_dxt1_rgba_fetch = 
(util_format_dxtn_fetch_t)fetch_2d_texel_rgba_dxt1;
-   util_format_dxt3_rgba_fetch = 
(util_format_dxtn_fetch_t)fetch_2d_texel_rgba_dxt3;
-   util_format_dxt5_rgba_fetch = 
(util_format_dxtn_fetch_t)fetch_2d_texel_rgba_dxt5;
-   util_format_dxtn_pack = (util_format_dxtn_pack_t)tx_compress_dxtn;
-}
+util_format_dxtn_pack_t util_format_dxtn_pack = 
(util_format_dxtn_pack_t)tx_compress_dxtn;
 
 
 /*
diff --git a/src/gallium/auxiliary/util/u_format_s3tc.h 
b/src/gallium/auxiliary/util/u_format_s3tc.h
index 42e62bdbb2..6f188c67f9 100644
--- a/src/gallium/auxiliary/util/u_format_s3tc.h
+++ b/src/gallium/auxiliary/util/u_format_s3tc.h
@@ -67,10 +67,6 @@ extern util_format_dxtn_pack_t util_format_dxtn_pack;
 
 
 void
-util_format_s3tc_init(void);
-
-
-void
 util_format_dxt1_rgb_unpack_rgba_8unorm(uint8_t *dst_row, unsigned dst_stride, 
const uint8_t *src_row, unsigned src_stride, unsigned width, unsigned height);
 
 void
diff

Mesa (master): mesa: Drop Mesa_DXTn from gl_context

[Matt Turner]

Module: Mesa
Branch: master
Commit: c5d508028454f42923aee1ea1ab876f01f680ae7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c5d508028454f42923aee1ea1ab876f01f680ae7

Author: Matt Turner <matts...@gmail.com>
Date:   Wed Sep 27 21:17:45 2017 -0700

mesa: Drop Mesa_DXTn from gl_context

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>

---

 src/mesa/drivers/dri/i915/intel_extensions.c |  5 +
 src/mesa/drivers/dri/i965/intel_extensions.c |  4 +---
 src/mesa/drivers/dri/nouveau/nv10_context.c  |  6 ++
 src/mesa/drivers/dri/nouveau/nv20_context.c  |  6 ++
 src/mesa/drivers/dri/r200/r200_context.c | 10 ++---
 src/mesa/drivers/dri/radeon/radeon_context.c | 10 ++---
 src/mesa/main/context.c  |  2 --
 src/mesa/main/extensions.c   |  6 ++
 src/mesa/main/mtypes.h   |  3 ---
 src/mesa/main/texcompress_s3tc.c |  7 --
 src/mesa/main/texcompress_s3tc.h |  3 ---
 src/mesa/main/texformat.c| 14 
 src/mesa/main/teximage.c | 32 
 src/mesa/state_tracker/st_context.c  |  2 +-
 src/mesa/state_tracker/st_format.c   |  4 ++--
 15 files changed, 19 insertions(+), 95 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/intel_extensions.c 
b/src/mesa/drivers/dri/i915/intel_extensions.c
index 4f2c6fa34e..c85bd787fe 100644
--- a/src/mesa/drivers/dri/i915/intel_extensions.c
+++ b/src/mesa/drivers/dri/i915/intel_extensions.c
@@ -100,9 +100,6 @@ intelInitExtensions(struct gl_context *ctx)
  ctx->Extensions.ARB_occlusion_query = true;
}
 
-   if (intel->ctx.Mesa_DXTn
-   || driQueryOptionb(>optionCache, "force_s3tc_enable"))
-  ctx->Extensions.EXT_texture_compression_s3tc = true;
-
+   ctx->Extensions.EXT_texture_compression_s3tc = true;
ctx->Extensions.ANGLE_texture_compression_dxt = true;
 }
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 8aaea6fda2..9487b4ae70 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -301,8 +301,6 @@ intelInitExtensions(struct gl_context *ctx)
if (ctx->API != API_OPENGL_CORE)
   ctx->Extensions.ARB_color_buffer_float = true;
 
-   if (ctx->Mesa_DXTn || driQueryOptionb(>optionCache, 
"force_s3tc_enable"))
-  ctx->Extensions.EXT_texture_compression_s3tc = true;
-
+   ctx->Extensions.EXT_texture_compression_s3tc = true;
ctx->Extensions.ANGLE_texture_compression_dxt = true;
 }
diff --git a/src/mesa/drivers/dri/nouveau/nv10_context.c 
b/src/mesa/drivers/dri/nouveau/nv10_context.c
index 7a86ba2358..be2178fb79 100644
--- a/src/mesa/drivers/dri/nouveau/nv10_context.c
+++ b/src/mesa/drivers/dri/nouveau/nv10_context.c
@@ -451,10 +451,8 @@ nv10_context_create(struct nouveau_screen *screen, gl_api 
api,
ctx->Extensions.EXT_texture_env_dot3 = true;
ctx->Extensions.NV_fog_distance = true;
ctx->Extensions.NV_texture_rectangle = true;
-   if (ctx->Mesa_DXTn) {
-   ctx->Extensions.EXT_texture_compression_s3tc = true;
-   ctx->Extensions.ANGLE_texture_compression_dxt = true;
-   }
+   ctx->Extensions.EXT_texture_compression_s3tc = true;
+   ctx->Extensions.ANGLE_texture_compression_dxt = true;
 
/* GL constants. */
ctx->Const.MaxTextureLevels = 12;
diff --git a/src/mesa/drivers/dri/nouveau/nv20_context.c 
b/src/mesa/drivers/dri/nouveau/nv20_context.c
index ec638c036b..0ab2db0b08 100644
--- a/src/mesa/drivers/dri/nouveau/nv20_context.c
+++ b/src/mesa/drivers/dri/nouveau/nv20_context.c
@@ -462,10 +462,8 @@ nv20_context_create(struct nouveau_screen *screen, gl_api 
api,
ctx->Extensions.EXT_texture_env_dot3 = true;
ctx->Extensions.NV_fog_distance = true;
ctx->Extensions.NV_texture_rectangle = true;
-   if (ctx->Mesa_DXTn) {
-   ctx->Extensions.EXT_texture_compression_s3tc = true;
-   ctx->Extensions.ANGLE_texture_compression_dxt = true;
-   }
+   ctx->Extensions.EXT_texture_compression_s3tc = true;
+   ctx->Extensions.ANGLE_texture_compression_dxt = true;
 
/* GL constants. */
ctx->Const.MaxTextureCoordUnits = NV20_TEXTURE_UNITS;
diff --git a/src/mesa/drivers/dri/r200/r200_context.c 
b/src/mesa/drivers/dri/r200/r200_context.c
index 0a27985de7..b6354dccbb 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -363,14 +363,8 @@ GLboolean r200CreateContext( gl_api api,
others get the bit ordering right but don't actually do YUV-RGB 
conversion */
   ctx->Extensions.MESA_ycbcr_texture = true;
}
-   if (rmesa->radeon.glCtx.Mesa_DXTn)