[Mesa-dev] [PATCH 2/2] nvc0: add a memory barrier when there are persistent UBOs

[Ilia Mirkin]

Signed-off-by: Ilia Mirkin 
---
 src/gallium/drivers/nouveau/nvc0/nvc0_context.c | 22 +++-
 src/gallium/drivers/nouveau/nvc0/nvc0_context.h |  2 ++
 src/gallium/drivers/nouveau/nvc0/nvc0_state.c   |  5 +
 src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c | 27 -
 src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h  |  5 +++--
 5 files changed, 57 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_context.c
index e5040c4..5928c99 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.c
@@ -60,7 +60,7 @@ static void
 nvc0_memory_barrier(struct pipe_context *pipe, unsigned flags)
 {
struct nvc0_context *nvc0 = nvc0_context(pipe);
-   int i;
+   int i, s;
 
if (flags & PIPE_BARRIER_MAPPED_BUFFER) {
   for (i = 0; i < nvc0->num_vtxbufs; ++i) {
@@ -73,6 +73,26 @@ nvc0_memory_barrier(struct pipe_context *pipe, unsigned 
flags)
   if (nvc0->idxbuf.buffer &&
   nvc0->idxbuf.buffer->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT)
  nvc0->base.vbo_dirty = TRUE;
+
+  for (s = 0; s < 5 && !nvc0->cb_dirty; ++s) {
+ uint32_t valid = nvc0->constbuf_valid[s];
+
+ while (valid && !nvc0->cb_dirty) {
+const unsigned i = ffs(valid) - 1;
+struct pipe_resource *res;
+
+valid &= ~(1 << i);
+if (nvc0->constbuf[s][i].user)
+   continue;
+
+res = nvc0->constbuf[s][i].u.buf;
+if (!res)
+   continue;
+
+if (res->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT)
+   nvc0->cb_dirty = TRUE;
+ }
+  }
}
 }
 
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h 
b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
index 052f0ba..ebeb8c4 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
@@ -154,6 +154,8 @@ struct nvc0_context {
 
struct nvc0_constbuf constbuf[6][NVC0_MAX_PIPE_CONSTBUFS];
uint16_t constbuf_dirty[6];
+   uint16_t constbuf_valid[6];
+   boolean cb_dirty;
 
struct pipe_vertex_buffer vtxbuf[PIPE_MAX_ATTRIBS];
unsigned num_vtxbufs;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
index ef9d479..d1a7cf5 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
@@ -808,10 +808,15 @@ nvc0_set_constant_buffer(struct pipe_context *pipe, uint 
shader, uint index,
if (nvc0->constbuf[s][i].user) {
   nvc0->constbuf[s][i].u.data = cb->user_buffer;
   nvc0->constbuf[s][i].size = cb->buffer_size;
+  nvc0->constbuf_valid[s] |= 1 << i;
} else
if (cb) {
   nvc0->constbuf[s][i].offset = cb->buffer_offset;
   nvc0->constbuf[s][i].size = align(cb->buffer_size, 0x100);
+  nvc0->constbuf_valid[s] |= 1 << i;
+   }
+   else {
+  nvc0->constbuf_valid[s] &= ~(1 << i);
}
 }
 
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
index 83d406d..e92ca9c 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
@@ -799,7 +799,7 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct 
pipe_draw_info *info)
 {
struct nvc0_context *nvc0 = nvc0_context(pipe);
struct nouveau_pushbuf *push = nvc0->base.pushbuf;
-   int i;
+   int i, s;
 
/* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
nvc0->vb_elt_first = info->min_index + info->index_bias;
@@ -832,6 +832,31 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct 
pipe_draw_info *info)
 
push->kick_notify = nvc0_draw_vbo_kick_notify;
 
+   for (s = 0; s < 5 && !nvc0->cb_dirty; ++s) {
+  uint32_t valid = nvc0->constbuf_valid[s];
+
+  while (valid && !nvc0->cb_dirty) {
+ const unsigned i = ffs(valid) - 1;
+ struct pipe_resource *res;
+
+ valid &= ~(1 << i);
+ if (nvc0->constbuf[s][i].user)
+continue;
+
+ res = nvc0->constbuf[s][i].u.buf;
+ if (!res)
+continue;
+
+ if (res->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT)
+nvc0->cb_dirty = TRUE;
+  }
+   }
+
+   if (nvc0->cb_dirty) {
+  IMMED_NVC0(push, NVC0_3D(MEM_BARRIER), 0x1011);
+  nvc0->cb_dirty = FALSE;
+   }
+
if (nvc0->state.vbo_mode) {
   nvc0_push_vbo(nvc0, info);
   push->kick_notify = nvc0_default_kick_notify;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h 
b/src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h
index 3514d9d..a83b31d 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h
@@ -80,8 +80,9 @@ NVC0_FIFO_PKHDR_NI(int subc, int mthd, unsigned size)
 }
 
 static INLINE uint32_t
-NVC0_FIFO_PKHDR_IL(int subc, int mthd, uint8_t data)
+NVC0_FIFO_P

[Mesa-dev] [PATCH 1/2] nv50: do an explicit flush on draw when there are persistent buffers

[Ilia Mirkin]

Signed-off-by: Ilia Mirkin 
---
 src/gallium/drivers/nouveau/nv50/nv50_context.c | 22 ++-
 src/gallium/drivers/nouveau/nv50/nv50_context.h |  1 +
 src/gallium/drivers/nouveau/nv50/nv50_vbo.c | 29 -
 3 files changed, 50 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_context.c 
b/src/gallium/drivers/nouveau/nv50/nv50_context.c
index 3f3a888..c2eb0c0 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_context.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_context.c
@@ -61,7 +61,7 @@ static void
 nv50_memory_barrier(struct pipe_context *pipe, unsigned flags)
 {
struct nv50_context *nv50 = nv50_context(pipe);
-   int i;
+   int i, s;
 
if (flags & PIPE_BARRIER_MAPPED_BUFFER) {
   for (i = 0; i < nv50->num_vtxbufs; ++i) {
@@ -74,6 +74,26 @@ nv50_memory_barrier(struct pipe_context *pipe, unsigned 
flags)
   if (nv50->idxbuf.buffer &&
   nv50->idxbuf.buffer->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT)
  nv50->base.vbo_dirty = TRUE;
+
+  for (s = 0; s < 3 && !nv50->cb_dirty; ++s) {
+ uint32_t valid = nv50->constbuf_valid[s];
+
+ while (valid && !nv50->cb_dirty) {
+const unsigned i = ffs(valid) - 1;
+struct pipe_resource *res;
+
+valid &= ~(1 << i);
+if (nv50->constbuf[s][i].user)
+   continue;
+
+res = nv50->constbuf[s][i].u.buf;
+if (!res)
+   continue;
+
+if (res->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT)
+   nv50->cb_dirty = TRUE;
+ }
+  }
}
 }
 
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_context.h 
b/src/gallium/drivers/nouveau/nv50/nv50_context.h
index 3b7cb18..9c2af40 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_context.h
+++ b/src/gallium/drivers/nouveau/nv50/nv50_context.h
@@ -106,6 +106,7 @@ struct nv50_context {
struct nouveau_bufctx *bufctx;
 
uint32_t dirty;
+   boolean cb_dirty;
 
struct {
   uint32_t instance_elts; /* bitmask of per-instance elements */
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c 
b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
index 7c2b7ff..5a4a457 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
@@ -747,7 +747,7 @@ nv50_draw_vbo(struct pipe_context *pipe, const struct 
pipe_draw_info *info)
 {
struct nv50_context *nv50 = nv50_context(pipe);
struct nouveau_pushbuf *push = nv50->base.pushbuf;
-   int i;
+   int i, s;
 
/* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
nv50->vb_elt_first = info->min_index + info->index_bias;
@@ -776,6 +776,33 @@ nv50_draw_vbo(struct pipe_context *pipe, const struct 
pipe_draw_info *info)
 
push->kick_notify = nv50_draw_vbo_kick_notify;
 
+   for (s = 0; s < 3 && !nv50->cb_dirty; ++s) {
+  uint32_t valid = nv50->constbuf_valid[s];
+
+  while (valid && !nv50->cb_dirty) {
+ const unsigned i = ffs(valid) - 1;
+ struct pipe_resource *res;
+
+ valid &= ~(1 << i);
+ if (nv50->constbuf[s][i].user)
+continue;
+
+ res = nv50->constbuf[s][i].u.buf;
+ if (!res)
+continue;
+
+ if (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
+nv50->cb_dirty = TRUE;
+  }
+   }
+
+   /* If there are any coherent constbufs, flush the cache */
+   if (nv50->cb_dirty) {
+  BEGIN_NV04(push, NV50_3D(CODE_CB_FLUSH), 1);
+  PUSH_DATA (push, 0);
+  nv50->cb_dirty = FALSE;
+   }
+
if (nv50->vbo_fifo) {
   nv50_push_vbo(nv50, info);
   push->kick_notify = nv50_default_kick_notify;
-- 
1.8.5.5

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[Mesa-dev] [PATCH] nv50: disable dedicated ubo upload method

[Ilia Mirkin]

The hardware allows multiple simultaneous renders with the same
memory-backed constbufs but with each invocation having different
values. However in order for that to work, the data has to be streamed
in via the right constbuf slot. We weren't doing that for UBOs.

Signed-off-by: Ilia Mirkin 
Cc: "10.2 10.1" 
---
 src/gallium/drivers/nouveau/nv50/nv50_context.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_context.c 
b/src/gallium/drivers/nouveau/nv50/nv50_context.c
index f844592..3f3a888 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_context.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_context.c
@@ -253,7 +253,14 @@ nv50_create(struct pipe_screen *pscreen, void *priv)
nv50->base.screen= &screen->base;
nv50->base.copy_data = nv50_m2mf_copy_linear;
nv50->base.push_data = nv50_sifc_linear_u8;
+   /* FIXME: Make it possible to use this again. The problem is that there is
+* some clever logic in the card that allows for multiple renders to happen
+* when there are only constbuf changes. However that relies on the
+* constbuf updates happening to the right constbuf slots. Currently
+* implementation just makes it go through a separate slot which doesn't
+* properly update the right constbuf data.
nv50->base.push_cb   = nv50_cb_push;
+*/
 
nv50->screen = screen;
pipe->screen = pscreen;
-- 
1.8.5.5

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Re: [Mesa-dev] [PATCH 1/4] i965/vec4: Add basic common subexpression elimination.

[Kenneth Graunke]

On Monday, June 30, 2014 12:06:56 PM Matt Turner wrote:
> On Mon, Jun 30, 2014 at 11:49 AM, Ian Romanick  wrote:
> > On 06/25/2014 02:12 PM, Matt Turner wrote:
> >> From: Kenneth Graunke 
> >> 
> >> [mattst88]: Modified to perform CSE on instructions with
> >> 
> >> the same writemask. Offered no improvement before.
> >> 
> >> total instructions in shared programs: 1995633 -> 1995185 (-0.02%)
> >> instructions in affected programs: 14410 -> 13962 (-3.11%)
> >> 
> >> Reviewed-by: Matt Turner 
> >> Signed-off-by: Kenneth Graunke 
> >> ---
> >> 
> >>  src/mesa/drivers/dri/i965/Makefile.sources |   1 +
> >>  src/mesa/drivers/dri/i965/brw_vec4.cpp |   1 +
> >>  src/mesa/drivers/dri/i965/brw_vec4.h   |   2 +
> >>  src/mesa/drivers/dri/i965/brw_vec4_cse.cpp | 237
> >>  + 4 files changed, 241 insertions(+)
> >>  create mode 100644 src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
> >> 
> >> diff --git a/src/mesa/drivers/dri/i965/Makefile.sources
> >> b/src/mesa/drivers/dri/i965/Makefile.sources index 2570059..8f1d272
> >> 100644
> >> --- a/src/mesa/drivers/dri/i965/Makefile.sources
> >> +++ b/src/mesa/drivers/dri/i965/Makefile.sources
> >> @@ -102,6 +102,7 @@ i965_FILES = \
> >> 
> >>   brw_util.c \
> >>   brw_vec4.cpp \
> >>   brw_vec4_copy_propagation.cpp \
> >> 
> >> + brw_vec4_cse.cpp \
> >> 
> >>   brw_vec4_generator.cpp \
> >>   brw_vec4_gs.c \
> >>   brw_vec4_gs_visitor.cpp \
> >> 
> >> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
> >> b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 24903f9..0d57399 100644
> >> --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
> >> +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> >> @@ -1747,6 +1747,7 @@ vec4_visitor::run()
> >> 
> >>progress = dead_control_flow_eliminate(this) || progress;
> >>progress = opt_copy_propagation() || progress;
> >>progress = opt_algebraic() || progress;
> >> 
> >> +  progress = opt_cse() || progress;
> >> 
> >>progress = opt_register_coalesce() || progress;
> >> 
> >> } while (progress);
> >> 
> >> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
> >> b/src/mesa/drivers/dri/i965/brw_vec4.h index 366198c..4a8eabb 100644
> >> --- a/src/mesa/drivers/dri/i965/brw_vec4.h
> >> +++ b/src/mesa/drivers/dri/i965/brw_vec4.h
> >> 
> >> @@ -426,6 +426,8 @@ public:
> >> bool dead_code_eliminate();
> >> bool virtual_grf_interferes(int a, int b);
> >> bool opt_copy_propagation();
> >> 
> >> +   bool opt_cse_local(bblock_t *, exec_list *);
> >> +   bool opt_cse();
> >> 
> >> bool opt_algebraic();
> >> bool opt_register_coalesce();
> >> void opt_set_dependency_control();
> >> 
> >> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
> >> b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp new file mode 100644
> >> index 000..33c7430
> >> --- /dev/null
> >> +++ b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
> >> @@ -0,0 +1,237 @@
> >> +/*
> >> + * Copyright © 2012, 2013, 2014 Intel Corporation
> >> + *
> >> + * Permission is hereby granted, free of charge, to any person obtaining
> >> a
> >> + * copy of this software and associated documentation files (the
> >> "Software"), + * to deal in the Software without restriction, including
> >> without limitation + * the rights to use, copy, modify, merge, publish,
> >> distribute, sublicense, + * and/or sell copies of the Software, and to
> >> permit persons to whom the + * Software is furnished to do so, subject
> >> to the following conditions: + *
> >> + * The above copyright notice and this permission notice (including the
> >> next + * paragraph) shall be included in all copies or substantial
> >> portions of the + * Software.
> >> + *
> >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> >> EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> >> MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND
> >> NONINFRINGEMENT.  IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS
> >> BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN
> >> ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN
> >> CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE
> >> SOFTWARE.
> >> + */
> >> +
> >> +#include "brw_vec4.h"
> >> +#include "brw_cfg.h"
> >> +
> >> +using namespace brw;
> >> +
> >> +/** @file brw_vec4_cse.cpp
> >> + *
> >> + * Support for local common subexpression elimination.
> >> + *
> >> + * See Muchnick's Advanced Compiler Design and Implementation, section
> >> + * 13.1 (p378).
> >> + */
> >> +
> >> +namespace {
> >> +struct aeb_entry : public exec_node {
> >> +   /** The instruction that generates the expression value. */
> >> +   vec4_instruction *generator;
> >> +
> >> +   /** The temporary where the value is stored. */
> >> +   src_reg tmp;
> >> +};
> >> +}
> >> +
> >> +static bool
> >> +is_expression(const vec4_instruction *const inst)
> > 
> > is_expression seems like a weird

Re: [Mesa-dev] [PATCH] meta: Call glObjectLabel before linking.

[Matt Turner]

Reviewed-by: Matt Turner 
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[Mesa-dev] [PATCH] meta: Call glObjectLabel before linking.

[Kenneth Graunke]

i965 precompiles shaders at link time, and prints a disassembly if
INTEL_DEBUG=vs,gs,fs, including the shader name.  However, blit shaders
were showing up as "unnamed" since we hadn't set a name prior to
linking.

Signed-off-by: Kenneth Graunke 
---
 src/mesa/drivers/common/meta.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 1a2e453..89d2d75 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -217,6 +217,7 @@ _mesa_meta_compile_and_link_program(struct gl_context *ctx,
 fs_source);
 
*program = _mesa_CreateProgram();
+   _mesa_ObjectLabel(GL_PROGRAM, *program, -1, name);
_mesa_AttachShader(*program, fs);
_mesa_DeleteShader(fs);
_mesa_AttachShader(*program, vs);
@@ -224,7 +225,6 @@ _mesa_meta_compile_and_link_program(struct gl_context *ctx,
_mesa_BindAttribLocation(*program, 0, "position");
_mesa_BindAttribLocation(*program, 1, "texcoords");
_mesa_meta_link_program_with_debug(ctx, *program);
-   _mesa_ObjectLabel(GL_PROGRAM, *program, -1, name);
 
_mesa_UseProgram(*program);
 }
-- 
2.0.0

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Re: [Mesa-dev] [PATCH 5/5] meta: Add a meta implementation of GL_ARB_clear_texture

[Ian Romanick]

On 06/13/2014 05:59 PM, Neil Roberts wrote:
> Adds an implementation of the ClearTexSubImage driver entry point that tries
> to set up an FBO to render to the texture and then calls glClear with a
> scissor to perform the actual clear. If an FBO can't be created for the
> texture then it will fall back to using _mesa_store_ClearTexSubImage.
> ---
>  src/mesa/drivers/common/driverfuncs.c |   2 +-
>  src/mesa/drivers/common/meta.c| 162 
> ++
>  src/mesa/drivers/common/meta.h|   7 ++
>  3 files changed, 170 insertions(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/common/driverfuncs.c 
> b/src/mesa/drivers/common/driverfuncs.c
> index 34b6fef..1ac2aee 100644
> --- a/src/mesa/drivers/common/driverfuncs.c
> +++ b/src/mesa/drivers/common/driverfuncs.c
> @@ -95,7 +95,7 @@ _mesa_init_driver_functions(struct dd_function_table 
> *driver)
> driver->TexImage = _mesa_store_teximage;
> driver->TexSubImage = _mesa_store_texsubimage;
> driver->GetTexImage = _mesa_meta_GetTexImage;
> -   driver->ClearTexSubImage = _mesa_store_cleartexsubimage;
> +   driver->ClearTexSubImage = _mesa_meta_ClearTexSubImage;
> driver->CopyTexSubImage = _mesa_meta_CopyTexSubImage;
> driver->GenerateMipmap = _mesa_meta_GenerateMipmap;
> driver->TestProxyTexImage = _mesa_test_proxy_teximage;
> diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
> index cab0dd8..7308ce6 100644
> --- a/src/mesa/drivers/common/meta.c
> +++ b/src/mesa/drivers/common/meta.c
> @@ -40,6 +40,7 @@
>  #include "main/blit.h"
>  #include "main/bufferobj.h"
>  #include "main/buffers.h"
> +#include "main/clear.h"
>  #include "main/colortab.h"
>  #include "main/condrender.h"
>  #include "main/depth.h"
> @@ -47,6 +48,7 @@
>  #include "main/fbobject.h"
>  #include "main/feedback.h"
>  #include "main/formats.h"
> +#include "main/format_unpack.h"
>  #include "main/glformats.h"
>  #include "main/image.h"
>  #include "main/macros.h"
> @@ -71,6 +73,7 @@
>  #include "main/teximage.h"
>  #include "main/texparam.h"
>  #include "main/texstate.h"
> +#include "main/texstore.h"
>  #include "main/transformfeedback.h"
>  #include "main/uniforms.h"
>  #include "main/varray.h"
> @@ -3360,3 +3363,162 @@ _mesa_meta_DrawTex(struct gl_context *ctx, GLfloat x, 
> GLfloat y, GLfloat z,
>  
> _mesa_meta_end(ctx);
>  }
> +
> +static void
> +set_color_clear_value(struct gl_context *ctx,
> +  mesa_format format,
> +  const GLvoid *clearValue)
> +{
> +   if (clearValue == 0) {
> + memset(&ctx->Color.ClearColor, 0, sizeof ctx->Color.ClearColor);
> +   }
> +   else {
> +  switch (_mesa_get_format_datatype(format)) {
> +  case GL_UNSIGNED_INT:
> +  case GL_INT:
> + _mesa_unpack_uint_rgba_row(format, 1, clearValue,
> +(GLuint (*)[4]) 
> ctx->Color.ClearColor.ui);
> + break;
> +  default:
> + _mesa_unpack_rgba_row(format, 1, clearValue,
> +   (GLfloat (*)[4]) ctx->Color.ClearColor.f);
> + break;
> +  }
> +   }
> +}
> +
> +static bool
> +cleartexsubimage_using_fbo_for_zoffset(struct gl_context *ctx,
> +   struct gl_texture_image *texImage,
> +   GLint xoffset, GLint yoffset,
> +   GLint zoffset,
> +   GLsizei width, GLsizei height,
> +   const GLvoid *clearValue)
> +{
> +   GLuint fbo;
> +   bool success = false;
> +   GLbitfield mask;
> +   GLenum status;
> +   GLuint depthStencilValue[2];
> +   GLfloat depthValue;
> +
> +   _mesa_GenFramebuffers(1, &fbo);
> +   _mesa_BindFramebuffer(GL_DRAW_FRAMEBUFFER, fbo);
> +
> +   if (texImage->_BaseFormat == GL_DEPTH_STENCIL ||
> +   texImage->_BaseFormat == GL_DEPTH_COMPONENT) {
> +  _mesa_meta_bind_fbo_image(GL_DEPTH_ATTACHMENT, texImage, zoffset);
> +  mask = GL_DEPTH_BUFFER_BIT;
> +
> +  if (clearValue)
> + 
> _mesa_unpack_float_32_uint_24_8_depth_stencil_row(texImage->TexFormat,
> +   1, /* n */
> +   clearValue,
> +   
> depthStencilValue);
> +  else
> + memset(depthStencilValue, 0, sizeof depthStencilValue);
> +
> +  memcpy(&depthValue, depthStencilValue, sizeof depthValue);
> +  ctx->Depth.Clear = depthValue;
> +
> +  if (texImage->_BaseFormat == GL_DEPTH_STENCIL) {
> + _mesa_meta_bind_fbo_image(GL_STENCIL_ATTACHMENT, texImage, zoffset);
> + mask |= GL_STENCIL_BUFFER_BIT;
> + ctx->Stencil.Clear = depthStencilValue[1] & 0xff;
> +  }
> +  _mesa_DrawBuffer(GL_NONE);
> +   } else {
> +  _mesa_meta_bind_fbo_image(GL_COLOR_ATTACHMENT0, texImage, zoffset);
> +  _mesa_DrawBuff

Re: [Mesa-dev] [PATCH 2/5] mesa/main: Add generic bits of ARB_clear_texture implementation

[Ian Romanick]

On 06/13/2014 05:59 PM, Neil Roberts wrote:
> This adds the driver entry point for glClearTexSubImage and fills in the
> _mesa_ClearTexImage and _mesa_ClearTexSubImage functions that call it.
> ---
>  src/mesa/main/dd.h   |  14 +++
>  src/mesa/main/teximage.c | 241 
> ++-
>  src/mesa/main/teximage.h |  12 +++
>  3 files changed, 266 insertions(+), 1 deletion(-)
> 
> diff --git a/src/mesa/main/dd.h b/src/mesa/main/dd.h
> index 633ea2c..8976535 100644
> --- a/src/mesa/main/dd.h
> +++ b/src/mesa/main/dd.h
> @@ -239,6 +239,20 @@ struct dd_function_table {
>  struct gl_texture_image *texImage );
>  
> /**
> +* Called by glClearTex[Sub]Image
> +*
> +* Clears a rectangular region of the image to a given value. The
> +* clearValue argument is either NULL or points to a single texel to use 
> as
> +* the clear value in the same internal format as the texture image. If it
> +* is NULL then the texture should be cleared to zeroes.
> +*/
> +   void (*ClearTexSubImage)(struct gl_context *ctx,
> +struct gl_texture_image *texImage,
> +GLint xoffset, GLint yoffset, GLint zoffset,
> +GLsizei width, GLsizei height, GLsizei depth,
> +const GLvoid *clearValue);
> +
> +   /**
>  * Called by glCopyTex[Sub]Image[123]D().
>  *
>  * This function should copy a rectangular region in the rb to a single
> diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
> index a893c70..d5baac8 100644
> --- a/src/mesa/main/teximage.c
> +++ b/src/mesa/main/teximage.c
> @@ -51,6 +51,7 @@
>  #include "textureview.h"
>  #include "mtypes.h"
>  #include "glformats.h"
> +#include "texstore.h"
>  
>  
>  /**
> @@ -3848,20 +3849,259 @@ _mesa_CopyTexSubImage3D( GLenum target, GLint level,
> x, y, width, height);
>  }
>  
> +static bool
> +clear_tex_image(struct gl_context *ctx,
> +const char *function,
> +struct gl_texture_image *texImage, GLint level,
> +GLint xoffset, GLint yoffset, GLint zoffset,
> +GLsizei width, GLsizei height, GLsizei depth,
> +GLenum format, GLenum type,
> +const void *data)
> +{
> +   struct gl_texture_object *texObj = texImage->TexObject;
> +   static const GLubyte zeroData[MAX_PIXEL_BYTES];
> +   GLubyte clearValue[MAX_PIXEL_BYTES];
> +   GLubyte *clearValuePtr = clearValue;
> +   GLenum internalFormat = texImage->InternalFormat;
> +   GLenum err;
> +
> +   if (texObj->Target == GL_TEXTURE_BUFFER) {
> +  _mesa_error(ctx, GL_INVALID_OPERATION,
> +  "%s(buffer texture)", function);
> +  return false;
> +   }
> +
> +   if (_mesa_is_compressed_format(ctx, internalFormat)) {
> +  _mesa_error(ctx, GL_INVALID_OPERATION,
> +  "%s(compressed texture)", function);
> +  return false;
> +   }
> +
> +   err = _mesa_error_check_format_and_type(ctx, format, type);
> +   if (err != GL_NO_ERROR) {
> +  _mesa_error(ctx, err,
> +  "%s(incompatible format = %s, type = %s)",
> +  function,
> +  _mesa_lookup_enum_by_nr(format),
> +  _mesa_lookup_enum_by_nr(type));
> +  return false;
> +   }
> +
> +   /* make sure internal format and format basically agree */
> +   if (!texture_formats_agree(internalFormat, format)) {
> +  _mesa_error(ctx, GL_INVALID_OPERATION,
> +  "%s(incompatible internalFormat = %s, format = %s)",
> +  function,
> +  _mesa_lookup_enum_by_nr(internalFormat),
> +  _mesa_lookup_enum_by_nr(format));
> +  return false;
> +   }
> +
> +   if (ctx->Version >= 30 || ctx->Extensions.EXT_texture_integer) {
> +  /* both source and dest must be integer-valued, or neither */
> +  if (_mesa_is_format_integer_color(texImage->TexFormat) !=
> +  _mesa_is_enum_format_integer(format)) {
> + _mesa_error(ctx, GL_INVALID_OPERATION,
> + "%s(integer/non-integer format mismatch)",
> + function);
> + return false;
> +  }
> +   }
> +
> +   if (!_mesa_texstore(ctx,
> +   1, /* dims */
> +   texImage->_BaseFormat,
> +   texImage->TexFormat,
> +   0, /* dstRowStride */
> +   &clearValuePtr,
> +   1, 1, 1, /* srcWidth/Height/Depth */
> +   format, type,
> +   data ? data : zeroData,
> +   &ctx->DefaultPacking)) {
> +  _mesa_error(ctx, GL_INVALID_OPERATION, "%s(invalid format)", function);
> +  return false;
> +   }
> +
> +   ctx->Driver.ClearTexSubImage(ctx,
> +texImage,
> +xoffset, yoffset, zoffset,
> +

Re: [Mesa-dev] [PATCH 3/5] Add a place to enable extensions that are common to all DRI drivers

[Ian Romanick]

On 06/13/2014 05:59 PM, Neil Roberts wrote:
> This adds a function called _mesa_init_driver_extensions that is called by all
> DRI-based drivers. The intention is that any extensions that are implemented
> directly by _mesa_init_driver_functions without any driver-specific
> entrypoints will be enabled here.

Ken and I talked about this a couple weeks back, but it seems that
neither one of us sent a message to the list.  My recollection is that
we both think this (and Jason's suggestion variation) is a bad idea.  We
don't want to enable new extensions, perhaps "surprisingly," on hardware
that nobody is building or testing.  We also don't want to gate landing
new feature work on testing old hardware.  For example, it's bad enough
that this work has been blocked waiting for reviews... I wouldn't want
to block it further waiting for someone to test r200.

The cost of adding (and maintaining) the enables in individual drivers
is really low.  Having the cost be non-zero means that somebody has to
think and do something before an extension gets enabled in a driver.  I
think that's a good thing.

> ---
>  src/mesa/drivers/common/driverfuncs.c  | 8 
>  src/mesa/drivers/common/driverfuncs.h  | 2 ++
>  src/mesa/drivers/dri/i915/intel_extensions.c   | 3 +++
>  src/mesa/drivers/dri/i965/intel_extensions.c   | 3 +++
>  src/mesa/drivers/dri/nouveau/nouveau_context.c | 1 +
>  src/mesa/drivers/dri/r200/r200_context.c   | 2 ++
>  src/mesa/drivers/dri/radeon/radeon_context.c   | 2 ++
>  src/mesa/drivers/dri/swrast/swrast.c   | 1 +
>  8 files changed, 22 insertions(+)
> 
> diff --git a/src/mesa/drivers/common/driverfuncs.c 
> b/src/mesa/drivers/common/driverfuncs.c
> index 6ece5d8..ee8b390 100644
> --- a/src/mesa/drivers/common/driverfuncs.c
> +++ b/src/mesa/drivers/common/driverfuncs.c
> @@ -326,3 +326,11 @@ _mesa_init_driver_state(struct gl_context *ctx)
>  
> ctx->Driver.DrawBuffer(ctx, ctx->Color.DrawBuffer[0]);
>  }
> +
> +/**
> + * Enable extensions that are available for all DRI-based drivers.
> + */
> +void
> +_mesa_init_driver_extensions(struct gl_context *ctx)
> +{
> +}
> diff --git a/src/mesa/drivers/common/driverfuncs.h 
> b/src/mesa/drivers/common/driverfuncs.h
> index 6b9a900..520c059 100644
> --- a/src/mesa/drivers/common/driverfuncs.h
> +++ b/src/mesa/drivers/common/driverfuncs.h
> @@ -33,5 +33,7 @@ _mesa_init_driver_functions(struct dd_function_table 
> *driver);
>  extern void
>  _mesa_init_driver_state(struct gl_context *ctx);
>  
> +extern void
> +_mesa_init_driver_extensions(struct gl_context *ctx);
>  
>  #endif
> diff --git a/src/mesa/drivers/dri/i915/intel_extensions.c 
> b/src/mesa/drivers/dri/i915/intel_extensions.c
> index 76f608e..3a8744a 100644
> --- a/src/mesa/drivers/dri/i915/intel_extensions.c
> +++ b/src/mesa/drivers/dri/i915/intel_extensions.c
> @@ -31,6 +31,7 @@
>  #include "intel_context.h"
>  #include "intel_extensions.h"
>  #include "intel_reg.h"
> +#include "drivers/common/driverfuncs.h"
>  #include "utils.h"
>  
>  /**
> @@ -44,6 +45,8 @@ intelInitExtensions(struct gl_context *ctx)
>  
> assert(intel->gen == 2 || intel->gen == 3);
>  
> +   _mesa_init_driver_extensions(ctx);
> +
> ctx->Extensions.ARB_draw_elements_base_vertex = true;
> ctx->Extensions.ARB_explicit_attrib_location = true;
> ctx->Extensions.ARB_framebuffer_object = true;
> diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
> b/src/mesa/drivers/dri/i965/intel_extensions.c
> index 39d0ab5..fe47464 100644
> --- a/src/mesa/drivers/dri/i965/intel_extensions.c
> +++ b/src/mesa/drivers/dri/i965/intel_extensions.c
> @@ -31,6 +31,7 @@
>  #include "intel_batchbuffer.h"
>  #include "intel_reg.h"
>  #include "utils.h"
> +#include "drivers/common/driverfuncs.h"
>  
>  /**
>   * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
> @@ -162,6 +163,8 @@ intelInitExtensions(struct gl_context *ctx)
>  
> assert(brw->gen >= 4);
>  
> +   _mesa_init_driver_extensions(ctx);
> +
> ctx->Extensions.ARB_buffer_storage = true;
> ctx->Extensions.ARB_depth_buffer_float = true;
> ctx->Extensions.ARB_depth_clamp = true;
> diff --git a/src/mesa/drivers/dri/nouveau/nouveau_context.c 
> b/src/mesa/drivers/dri/nouveau/nouveau_context.c
> index f8c8dc3..ad7ee86 100644
> --- a/src/mesa/drivers/dri/nouveau/nouveau_context.c
> +++ b/src/mesa/drivers/dri/nouveau/nouveau_context.c
> @@ -183,6 +183,7 @@ nouveau_context_init(struct gl_context *ctx, gl_api api,
>   }
>  
>   /* Enable any supported extensions. */
> +_mesa_init_driver_extensions(ctx);
>   ctx->Extensions.EXT_blend_color = true;
>   ctx->Extensions.EXT_blend_minmax = true;
>   ctx->Extensions.EXT_texture_filter_anisotropic = true;
> diff --git a/src/mesa/drivers/dri/r200/r200_context.c 
> b/src/mesa/drivers/dri/r200/r200_context.c
> index 71dfcf3..93ca23d 100644
> --- a/src/mesa/drivers/dri/r200/r200_context.c
> +++ b/src/mesa/drivers/dri/r200/r200_context.c
> @@ -366,6 +36

[Mesa-dev] [Bug 77449] Tracker bug for all bugs related to Steam titles

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=77449

Courtney Goeltzenleuchter  changed:

   What|Removed |Added

 Depends on||79373

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[Mesa-dev] [Bug 77449] Tracker bug for all bugs related to Steam titles

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=77449

Courtney Goeltzenleuchter  changed:

   What|Removed |Added

 Depends on||80500

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[Mesa-dev] [Bug 77449] Tracker bug for all bugs related to Steam titles

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=77449

Courtney Goeltzenleuchter  changed:

   What|Removed |Added

 Depends on||79948

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Re: [Mesa-dev] [PATCH] i965: Extend compute-to-mrf pass to understand blocks of MOVs

[Matt Turner]

On Fri, Jun 27, 2014 at 12:00 PM, Kristian Høgsberg  wrote:
> From: Kristian Høgsberg 

With your email address fixed,

Reviewed-by: Matt Turner 
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Re: [Mesa-dev] [PATCH 07/13] i965: Make a brw_conditional_mod enum.

[Matt Turner]

On Mon, Jun 30, 2014 at 2:40 PM, Matt Turner  wrote:
> diff --git a/src/mesa/drivers/dri/i965/gen8_instruction.c 
> b/src/mesa/drivers/dri/i965/gen8_instruction.c
> index c9cbab6..47955e1 100644
> --- a/src/mesa/drivers/dri/i965/gen8_instruction.c
> +++ b/src/mesa/drivers/dri/i965/gen8_instruction.c
> @@ -28,6 +28,7 @@
>   * and set various fields.  This is the actual hardware format.
>   */
>
> +#include "main/compiler.h"
>  #include "brw_defines.h"
>  #include "gen8_instruction.h"
>
> --

A preemptive explanation: this hunk is because brw_defines.h includes
an enum (brw_conditional_mod) marked with PACKED, which is defined in
compiler.h. Kind of ugly, but this file should be going away soon
anyway.
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Re: [Mesa-dev] [PATCH] configure.ac: (trivial) Fixing a typo

[Emil Velikov]

On 30/06/14 22:05, Alexandre Demers wrote:
> Signed-off-by: Alexandre Demers 
Reviewed-by: Emil Velikov 

and pushed to master.
> ---
>  configure.ac | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/configure.ac b/configure.ac
> index faf1485..98efa43 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -1603,7 +1603,7 @@ fi
>  
>  AC_ARG_WITH([egl-driver-dir],
>  [AS_HELP_STRING([--with-egl-driver-dir=DIR],
> -[directory for EGL drivers [[default=${libdir}/egl]]])],
> +[directory for EGL drivers 
> @<:@default=${libdir}/egl@:>@])],
>  [EGL_DRIVER_INSTALL_DIR="$withval"],
>  [EGL_DRIVER_INSTALL_DIR='${libdir}/egl'])
>  AC_SUBST([EGL_DRIVER_INSTALL_DIR])
> 

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Re: [Mesa-dev] [PATCH 01/13] i965: Use immediate storage in brw_reg for visitor regs.

[Matt Turner]

On Mon, Jun 30, 2014 at 2:46 PM, Chris Forbes  wrote:
> On Tue, Jul 1, 2014 at 9:40 AM, Matt Turner  wrote:
>>
>>  /** Fixed brw_reg. */
>> @@ -452,7 +452,7 @@ fs_reg::equals(const fs_reg &r) const
>> memcmp(&fixed_hw_reg, &r.fixed_hw_reg,
>>sizeof(fixed_hw_reg)) == 0 &&
>> stride == r.stride &&
>> -   imm.u == r.imm.u);
>> +   fixed_hw_reg.dw1.ud == r.fixed_hw_reg.dw1.ud);
>
> This check is redundant with the memcmp above
>
>>
>>  src_reg::src_reg(struct brw_reg reg)
>> @@ -334,7 +334,7 @@ src_reg::equals(const src_reg &r) const
>>!reladdr && !r.reladdr &&
>>memcmp(&fixed_hw_reg, &r.fixed_hw_reg,
>>   sizeof(fixed_hw_reg)) == 0 &&
>> -  imm.u == r.imm.u);
>> +  fixed_hw_reg.dw1.ud == r.fixed_hw_reg.dw1.ud);
>
> Ditto

Oh, good catch. Will remove these checks.
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Re: [Mesa-dev] [PATCH 01/13] i965: Use immediate storage in brw_reg for visitor regs.

[Chris Forbes]

On Tue, Jul 1, 2014 at 9:40 AM, Matt Turner  wrote:
>
>  /** Fixed brw_reg. */
> @@ -452,7 +452,7 @@ fs_reg::equals(const fs_reg &r) const
> memcmp(&fixed_hw_reg, &r.fixed_hw_reg,
>sizeof(fixed_hw_reg)) == 0 &&
> stride == r.stride &&
> -   imm.u == r.imm.u);
> +   fixed_hw_reg.dw1.ud == r.fixed_hw_reg.dw1.ud);

This check is redundant with the memcmp above

>
>  src_reg::src_reg(struct brw_reg reg)
> @@ -334,7 +334,7 @@ src_reg::equals(const src_reg &r) const
>!reladdr && !r.reladdr &&
>memcmp(&fixed_hw_reg, &r.fixed_hw_reg,
>   sizeof(fixed_hw_reg)) == 0 &&
> -  imm.u == r.imm.u);
> +  fixed_hw_reg.dw1.ud == r.fixed_hw_reg.dw1.ud);

Ditto
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[Mesa-dev] [PATCH 10/13] i965/cfg: Make cfg_t usable from C.

[Matt Turner]

---
 src/mesa/drivers/dri/i965/brw_cfg.h   | 10 --
 src/mesa/drivers/dri/i965/brw_fs_live_variables.h |  2 +-
 src/mesa/drivers/dri/i965/brw_shader.h|  2 +-
 3 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_cfg.h 
b/src/mesa/drivers/dri/i965/brw_cfg.h
index b55eacb..cdbadde 100644
--- a/src/mesa/drivers/dri/i965/brw_cfg.h
+++ b/src/mesa/drivers/dri/i965/brw_cfg.h
@@ -82,9 +82,8 @@ struct bblock_t {
struct backend_instruction *endif_inst;
 };
 
+struct cfg_t {
 #ifdef __cplusplus
-class cfg_t {
-public:
DECLARE_RALLOC_CXX_OPERATORS(cfg_t)
 
cfg_t(exec_list *instructions);
@@ -95,15 +94,14 @@ public:
void make_block_array();
 
void dump(backend_visitor *v);
-
+#endif
void *mem_ctx;
 
/** Ordered list (by ip) of basic blocks */
-   exec_list block_list;
-   bblock_t **blocks;
+   struct exec_list block_list;
+   struct bblock_t **blocks;
int num_blocks;
 };
-#endif
 
 #define foreach_inst_in_block(__type, __inst, __block) \
for (__type *__inst = (__type *)__block->start; \
diff --git a/src/mesa/drivers/dri/i965/brw_fs_live_variables.h 
b/src/mesa/drivers/dri/i965/brw_fs_live_variables.h
index 13c3eb4..6cc8a98 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_live_variables.h
+++ b/src/mesa/drivers/dri/i965/brw_fs_live_variables.h
@@ -28,7 +28,7 @@
 #include "brw_fs.h"
 #include "main/bitset.h"
 
-class cfg_t;
+struct cfg_t;
 
 namespace brw {
 
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h 
b/src/mesa/drivers/dri/i965/brw_shader.h
index 558d052..e021820 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -80,7 +80,7 @@ struct backend_reg
 
 #ifdef __cplusplus
 
-class cfg_t;
+struct cfg_t;
 
 struct backend_instruction : public exec_node {
 public:
-- 
1.8.3.2

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[Mesa-dev] [PATCH 04/13] i965: Move is_zero/one/null/accumulator into backend_reg.

[Matt Turner]

---
 src/mesa/drivers/dri/i965/brw_fs.cpp | 36 
 src/mesa/drivers/dri/i965/brw_fs.h   |  4 ---
 src/mesa/drivers/dri/i965/brw_shader.cpp | 37 +
 src/mesa/drivers/dri/i965/brw_shader.h   |  7 +
 src/mesa/drivers/dri/i965/brw_vec4.cpp   | 47 
 src/mesa/drivers/dri/i965/brw_vec4.h |  6 
 6 files changed, 44 insertions(+), 93 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index b260409..15d0fd5 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -481,47 +481,11 @@ fs_reg::is_contiguous() const
 }
 
 bool
-fs_reg::is_zero() const
-{
-   if (file != IMM)
-  return false;
-
-   return fixed_hw_reg.dw1.d == 0;
-}
-
-bool
-fs_reg::is_one() const
-{
-   if (file != IMM)
-  return false;
-
-   return type == BRW_REGISTER_TYPE_F
-  ? fixed_hw_reg.dw1.f == 1.0
-  : fixed_hw_reg.dw1.d == 1;
-}
-
-bool
-fs_reg::is_null() const
-{
-   return file == HW_REG &&
-  fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
-  fixed_hw_reg.nr == BRW_ARF_NULL;
-}
-
-bool
 fs_reg::is_valid_3src() const
 {
return file == GRF || file == UNIFORM;
 }
 
-bool
-fs_reg::is_accumulator() const
-{
-   return file == HW_REG &&
-  fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
-  fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
-}
-
 int
 fs_visitor::type_size(const struct glsl_type *type)
 {
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h 
b/src/mesa/drivers/dri/i965/brw_fs.h
index b6a5717..530e54b 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -79,12 +79,8 @@ public:
fs_reg(class fs_visitor *v, const struct glsl_type *type);
 
bool equals(const fs_reg &r) const;
-   bool is_zero() const;
-   bool is_one() const;
-   bool is_null() const;
bool is_valid_3src() const;
bool is_contiguous() const;
-   bool is_accumulator() const;
 
fs_reg &apply_stride(unsigned stride);
/** Smear a channel of the reg to all channels. */
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp 
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 787eb87..fa42733 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -554,6 +554,43 @@ backend_visitor::backend_visitor(struct brw_context *brw,
 }
 
 bool
+backend_reg::is_zero() const
+{
+   if (file != IMM)
+  return false;
+
+   return fixed_hw_reg.dw1.d == 0;
+}
+
+bool
+backend_reg::is_one() const
+{
+   if (file != IMM)
+  return false;
+
+   return type == BRW_REGISTER_TYPE_F
+  ? fixed_hw_reg.dw1.f == 1.0
+  : fixed_hw_reg.dw1.d == 1;
+}
+
+bool
+backend_reg::is_null() const
+{
+   return file == HW_REG &&
+  fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
+  fixed_hw_reg.nr == BRW_ARF_NULL;
+}
+
+
+bool
+backend_reg::is_accumulator() const
+{
+   return file == HW_REG &&
+  fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
+  fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
+}
+
+bool
 backend_instruction::is_tex() const
 {
return (opcode == SHADER_OPCODE_TEX ||
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h 
b/src/mesa/drivers/dri/i965/brw_shader.h
index 3896442..b0908a3 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -42,6 +42,13 @@ enum PACKED register_file {
 
 struct backend_reg
 {
+#ifdef __cplusplus
+   bool is_zero() const;
+   bool is_one() const;
+   bool is_null() const;
+   bool is_accumulator() const;
+#endif
+
enum register_file file; /**< Register file: GRF, MRF, IMM. */
uint8_t type;/**< Register type: BRW_REGISTER_TYPE_* */
 
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index c7fb4bb..35e200b 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -151,15 +151,6 @@ src_reg::src_reg(dst_reg reg)
 swizzles[2], swizzles[3]);
 }
 
-bool
-src_reg::is_accumulator() const
-{
-   return file == HW_REG &&
-  fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
-  fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
-}
-
-
 void
 dst_reg::init()
 {
@@ -222,22 +213,6 @@ dst_reg::dst_reg(src_reg reg)
 }
 
 bool
-dst_reg::is_null() const
-{
-   return file == HW_REG &&
-  fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
-  fixed_hw_reg.nr == BRW_ARF_NULL;
-}
-
-bool
-dst_reg::is_accumulator() const
-{
-   return file == HW_REG &&
-  fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
-  fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
-}
-
-bool
 vec4_instruction::is_send_from_grf()
 {
switch (opcode) {
@@ -602,28 +577,6 @@ vec4_visitor::pack_uniform_registers()
}
 }
 
-bool
-src_reg::is_zero() const
-{
-   if (file != IMM)
-  retur

[Mesa-dev] [PATCH 02/13] i965: Drop imm union from visitor register classes.

[Matt Turner]

---
 src/mesa/drivers/dri/i965/brw_fs.h   | 7 ---
 src/mesa/drivers/dri/i965/brw_vec4.h | 7 ---
 2 files changed, 14 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.h 
b/src/mesa/drivers/dri/i965/brw_fs.h
index 961c56c..c32b0a6 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -113,13 +113,6 @@ public:
 */
int subreg_offset;
 
-   /** Value for file == IMM */
-   union {
-  int32_t i;
-  uint32_t u;
-  float f;
-   } imm;
-
struct brw_reg fixed_hw_reg;
 
fs_reg *reladdr;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 6ac35d7..9a5b1cb 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -103,13 +103,6 @@ public:
/** Register type.  BRW_REGISTER_TYPE_* */
int type;
struct brw_reg fixed_hw_reg;
-
-   /** Value for file == BRW_IMMMEDIATE_FILE */
-   union {
-  int32_t i;
-  uint32_t u;
-  float f;
-   } imm;
 };
 
 class src_reg : public reg
-- 
1.8.3.2

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 12/13] i965: Rename intel_asm_printer -> intel_asm_annotation.

[Matt Turner]

The #ifndef include guards already said the right thing :)
---
 src/mesa/drivers/dri/i965/Makefile.sources   |  2 +-
 src/mesa/drivers/dri/i965/brw_eu.h   |  2 +-
 src/mesa/drivers/dri/i965/brw_eu_compact.c   |  2 +-
 src/mesa/drivers/dri/i965/brw_fs.h   |  2 +-
 src/mesa/drivers/dri/i965/brw_shader.h   |  2 +-
 src/mesa/drivers/dri/i965/brw_vec4.h |  2 +-
 src/mesa/drivers/dri/i965/intel_asm_annotation.c | 89 
 src/mesa/drivers/dri/i965/intel_asm_annotation.h | 71 +++
 src/mesa/drivers/dri/i965/intel_asm_printer.c| 89 
 src/mesa/drivers/dri/i965/intel_asm_printer.h| 71 ---
 10 files changed, 166 insertions(+), 166 deletions(-)
 create mode 100644 src/mesa/drivers/dri/i965/intel_asm_annotation.c
 create mode 100644 src/mesa/drivers/dri/i965/intel_asm_annotation.h
 delete mode 100644 src/mesa/drivers/dri/i965/intel_asm_printer.c
 delete mode 100644 src/mesa/drivers/dri/i965/intel_asm_printer.h

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 2570059..3a9bcbb 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -3,7 +3,7 @@ i965_INCLUDES = \
$(MESA_TOP)/src/mesa/drivers/dri/intel
 
 i965_FILES = \
-   intel_asm_printer.c \
+   intel_asm_annotation.c \
intel_batchbuffer.c \
intel_blit.c \
intel_buffer_objects.c \
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h 
b/src/mesa/drivers/dri/i965/brw_eu.h
index 48ef298..3164c80 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -38,7 +38,7 @@
 #include "brw_structs.h"
 #include "brw_defines.h"
 #include "brw_reg.h"
-#include "intel_asm_printer.h"
+#include "intel_asm_annotation.h"
 #include "program/prog_instruction.h"
 
 #ifdef __cplusplus
diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c 
b/src/mesa/drivers/dri/i965/brw_eu_compact.c
index b9a6500..eec6454 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_compact.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_compact.c
@@ -39,7 +39,7 @@
 
 #include "brw_context.h"
 #include "brw_eu.h"
-#include "intel_asm_printer.h"
+#include "intel_asm_annotation.h"
 
 static const uint32_t gen6_control_index_table[32] = {
0b0,
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h 
b/src/mesa/drivers/dri/i965/brw_fs.h
index fdb0efe..537f10e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -46,7 +46,7 @@ extern "C" {
 #include "brw_eu.h"
 #include "brw_wm.h"
 #include "brw_shader.h"
-#include "intel_asm_printer.h"
+#include "intel_asm_annotation.h"
 }
 #include "gen8_generator.h"
 #include "glsl/glsl_types.h"
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h 
b/src/mesa/drivers/dri/i965/brw_shader.h
index f866249..a922487 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -26,7 +26,7 @@
 #include "brw_defines.h"
 #include "main/compiler.h"
 #include "glsl/ir.h"
-#include "intel_asm_printer.h"
+#include "intel_asm_annotation.h"
 
 #pragma once
 
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 247d591..9d76bea 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -36,7 +36,7 @@ extern "C" {
 
 #include "brw_context.h"
 #include "brw_eu.h"
-#include "intel_asm_printer.h"
+#include "intel_asm_annotation.h"
 
 #ifdef __cplusplus
 }; /* extern "C" */
diff --git a/src/mesa/drivers/dri/i965/intel_asm_annotation.c 
b/src/mesa/drivers/dri/i965/intel_asm_annotation.c
new file mode 100644
index 000..f9764e4
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/intel_asm_annotation.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS

[Mesa-dev] [PATCH 07/13] i965: Make a brw_conditional_mod enum.

[Matt Turner]

---
 src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp|  2 +-
 src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h  |  7 +++---
 src/mesa/drivers/dri/i965/brw_defines.h| 26 --
 src/mesa/drivers/dri/i965/brw_eu.c |  2 +-
 src/mesa/drivers/dri/i965/brw_eu.h |  4 ++--
 src/mesa/drivers/dri/i965/brw_eu_emit.c|  2 +-
 src/mesa/drivers/dri/i965/brw_fs.cpp   |  6 +++--
 src/mesa/drivers/dri/i965/brw_fs.h |  9 
 .../drivers/dri/i965/brw_fs_copy_propagation.cpp   |  2 +-
 src/mesa/drivers/dri/i965/brw_fs_fp.cpp|  4 ++--
 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp   |  4 ++--
 src/mesa/drivers/dri/i965/brw_shader.cpp   |  2 +-
 src/mesa/drivers/dri/i965/brw_shader.h |  4 ++--
 src/mesa/drivers/dri/i965/brw_vec4.h   | 10 +
 .../drivers/dri/i965/brw_vec4_copy_propagation.cpp |  2 +-
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |  8 ---
 src/mesa/drivers/dri/i965/brw_vec4_vp.cpp  |  2 +-
 src/mesa/drivers/dri/i965/gen8_instruction.c   |  1 +
 18 files changed, 54 insertions(+), 43 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
index a2e008b..c1676a9 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
@@ -117,7 +117,7 @@ brw_blorp_eu_emitter::emit_combine(enum opcode 
combine_opcode,
 }
 
 fs_inst *
-brw_blorp_eu_emitter::emit_cmp(int op,
+brw_blorp_eu_emitter::emit_cmp(enum brw_conditional_mod op,
const struct brw_reg &x,
const struct brw_reg &y)
 {
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h 
b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
index bc927fe..0459a7e 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
@@ -59,7 +59,7 @@ protected:
 
inline void emit_cond_mov(const struct brw_reg &x,
  const struct brw_reg &y,
- int op,
+ enum brw_conditional_mod op,
  const struct brw_reg &dst,
  const struct brw_reg &src)
{
@@ -160,7 +160,7 @@ protected:
   insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_RNDD, dst, src));
}
 
-   inline void emit_cmp_if(int op,
+   inline void emit_cmp_if(enum brw_conditional_mod op,
const struct brw_reg &x,
const struct brw_reg &y)
{
@@ -179,7 +179,8 @@ protected:
}
 
 private:
-   fs_inst *emit_cmp(int op, const struct brw_reg &x, const struct brw_reg &y);
+   fs_inst *emit_cmp(enum brw_conditional_mod op, const struct brw_reg &x,
+ const struct brw_reg &y);
 
void *mem_ctx;
exec_list insts;
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 88d18a3..822156d 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -654,18 +654,20 @@ enum brw_compression {
 #define GEN6_COMPRESSION_1H0
 #define GEN6_COMPRESSION_2H2
 
-#define BRW_CONDITIONAL_NONE  0
-#define BRW_CONDITIONAL_Z 1
-#define BRW_CONDITIONAL_NZ2
-#define BRW_CONDITIONAL_EQ1/* Z */
-#define BRW_CONDITIONAL_NEQ   2/* NZ */
-#define BRW_CONDITIONAL_G 3
-#define BRW_CONDITIONAL_GE4
-#define BRW_CONDITIONAL_L 5
-#define BRW_CONDITIONAL_LE6
-#define BRW_CONDITIONAL_R 7
-#define BRW_CONDITIONAL_O 8
-#define BRW_CONDITIONAL_U 9
+enum PACKED brw_conditional_mod {
+   BRW_CONDITIONAL_NONE = 0,
+   BRW_CONDITIONAL_Z= 1,
+   BRW_CONDITIONAL_NZ   = 2,
+   BRW_CONDITIONAL_EQ   = 1,   /* Z */
+   BRW_CONDITIONAL_NEQ  = 2,   /* NZ */
+   BRW_CONDITIONAL_G= 3,
+   BRW_CONDITIONAL_GE   = 4,
+   BRW_CONDITIONAL_L= 5,
+   BRW_CONDITIONAL_LE   = 6,
+   BRW_CONDITIONAL_R= 7,
+   BRW_CONDITIONAL_O= 8,
+   BRW_CONDITIONAL_U= 9,
+};
 
 #define BRW_DEBUG_NONE0
 #define BRW_DEBUG_BREAKPOINT  1
diff --git a/src/mesa/drivers/dri/i965/brw_eu.c 
b/src/mesa/drivers/dri/i965/brw_eu.c
index 6a1e785..f4c7495 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -68,7 +68,7 @@ brw_reg_type_letters(unsigned type)
 /* Returns the corresponding conditional mod for swapping src0 and
  * src1 in e.g. CMP.
  */
-uint32_t
+enum brw_conditional_mod
 brw_swap_cmod(uint32_t cmod)
 {
switch (cmod) {
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h 
b/src/mesa/drivers/dri/i965/brw_eu.h
index 59b9232..48ef298 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -320,7 +320,7 @@ void brw_shader_time_add(struct brw_compile *p,
  * channel.
  */
 brw_inst *brw_IF(struct brw_compile *p, un

[Mesa-dev] [PATCH 13/13] i965: Move assembly annotation functions to intel_asm_annotation.c.

[Matt Turner]

It's C. Compile it as such.
---
 src/mesa/drivers/dri/i965/brw_shader.cpp | 55 --
 src/mesa/drivers/dri/i965/brw_shader.h   |  6 ---
 src/mesa/drivers/dri/i965/intel_asm_annotation.c | 58 
 src/mesa/drivers/dri/i965/intel_asm_annotation.h |  9 
 4 files changed, 67 insertions(+), 61 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp 
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index d7e127b..318802b 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -822,58 +822,3 @@ 
backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table
 
/* prog_data->base.binding_table.size will be set by brw_mark_surface_used. 
*/
 }
-
-void annotate(struct brw_context *brw,
-  struct annotation_info *annotation, cfg_t *cfg,
-  backend_instruction *inst, unsigned offset)
-{
-   if (annotation->ann_size <= annotation->ann_count) {
-  annotation->ann_size = MAX2(1024, annotation->ann_size * 2);
-  annotation->ann = reralloc(annotation->mem_ctx, annotation->ann,
- struct annotation, annotation->ann_size);
-  if (!annotation->ann)
- return;
-   }
-
-   struct annotation *ann = &annotation->ann[annotation->ann_count++];
-   ann->offset = offset;
-   if ((INTEL_DEBUG & DEBUG_NO_ANNOTATION) == 0) {
-  ann->ir = inst->ir;
-  ann->annotation = inst->annotation;
-   }
-
-   if (cfg->blocks[annotation->cur_block]->start == inst) {
-  ann->block_start = cfg->blocks[annotation->cur_block];
-   }
-
-   /* There is no hardware DO instruction on Gen6+, so since DO always
-* starts a basic block, we need to set the .block_start of the next
-* instruction's annotation with a pointer to the bblock started by
-* the DO.
-*
-* There's also only complication from emitting an annotation without
-* a corresponding hardware instruction to disassemble.
-*/
-   if (brw->gen >= 6 && inst->opcode == BRW_OPCODE_DO) {
-  annotation->ann_count--;
-   }
-
-   if (cfg->blocks[annotation->cur_block]->end == inst) {
-  ann->block_end = cfg->blocks[annotation->cur_block];
-  annotation->cur_block++;
-   }
-}
-
-void
-annotation_finalize(struct annotation_info *annotation,
-unsigned next_inst_offset)
-{
-   if (!annotation->ann_count)
-  return;
-
-   if (annotation->ann_count == annotation->ann_size) {
-  annotation->ann = reralloc(annotation->mem_ctx, annotation->ann,
- struct annotation, annotation->ann_size + 1);
-   }
-   annotation->ann[annotation->ann_count].offset = next_inst_offset;
-}
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h 
b/src/mesa/drivers/dri/i965/brw_shader.h
index a922487..cfaea9e 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -26,7 +26,6 @@
 #include "brw_defines.h"
 #include "main/compiler.h"
 #include "glsl/ir.h"
-#include "intel_asm_annotation.h"
 
 #pragma once
 
@@ -173,11 +172,6 @@ public:
 
 uint32_t brw_texture_offset(struct gl_context *ctx, ir_constant *offset);
 
-void annotate(struct brw_context *brw,
-  struct annotation_info *annotation, cfg_t *cfg,
-  backend_instruction *inst, unsigned offset);
-void annotation_finalize(struct annotation_info *annotation, unsigned offset);
-
 #endif /* __cplusplus */
 
 enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
diff --git a/src/mesa/drivers/dri/i965/intel_asm_annotation.c 
b/src/mesa/drivers/dri/i965/intel_asm_annotation.c
index f9764e4..db7f7bb 100644
--- a/src/mesa/drivers/dri/i965/intel_asm_annotation.c
+++ b/src/mesa/drivers/dri/i965/intel_asm_annotation.c
@@ -22,9 +22,12 @@
  */
 
 #include "brw_cfg.h"
+#include "brw_context.h"
+#include "intel_debug.h"
 #include "intel_asm_annotation.h"
 #include "program/prog_print.h"
 #include "program/prog_instruction.h"
+#include "main/macros.h"
 
 void
 dump_assembly(void *assembly, int num_annotations, struct annotation 
*annotation,
@@ -87,3 +90,58 @@ dump_assembly(void *assembly, int num_annotations, struct 
annotation *annotation
}
fprintf(stderr, "\n");
 }
+
+void annotate(struct brw_context *brw,
+  struct annotation_info *annotation, struct cfg_t *cfg,
+  struct backend_instruction *inst, unsigned offset)
+{
+   if (annotation->ann_size <= annotation->ann_count) {
+  annotation->ann_size = MAX2(1024, annotation->ann_size * 2);
+  annotation->ann = reralloc(annotation->mem_ctx, annotation->ann,
+ struct annotation, annotation->ann_size);
+  if (!annotation->ann)
+ return;
+   }
+
+   struct annotation *ann = &annotation->ann[annotation->ann_count++];
+   ann->offset = offset;
+   if ((INTEL_DEBUG & DEBUG_NO_ANNOTATION) == 0) {
+  ann->ir = inst->ir;
+  ann->annotation = inst->annotation;
+   }
+
+   if (c

[Mesa-dev] [PATCH 06/13] i965: Move common fields into backend_instruction.

[Matt Turner]

---
 src/mesa/drivers/dri/i965/brw_fs.h | 12 
 src/mesa/drivers/dri/i965/brw_shader.h | 13 +
 src/mesa/drivers/dri/i965/brw_vec4.h   | 13 -
 3 files changed, 13 insertions(+), 25 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.h 
b/src/mesa/drivers/dri/i965/brw_fs.h
index 4781079..da4d373 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -183,31 +183,19 @@ public:
fs_reg dst;
fs_reg *src;
 
-   uint32_t texture_offset; /**< Texture offset bitfield */
-   uint32_t offset; /* spill/unspill offset */
-
uint8_t sources; /**< Number of fs_reg sources. */
-   uint8_t conditional_mod; /**< BRW_CONDITIONAL_* */
 
/* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 * mod and predication.
 */
uint8_t flag_subreg;
 
-   uint8_t mlen; /**< SEND message length */
uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 
*/
-   int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
-   uint8_t sampler;
-   uint8_t target; /**< MRT target. */
-   bool saturate:1;
bool eot:1;
bool header_present:1;
bool shadow_compare:1;
bool force_uncompressed:1;
bool force_sechalf:1;
-   bool force_writemask_all:1;
-   bool no_dd_clear:1;
-   bool no_dd_check:1;
 };
 
 /**
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h 
b/src/mesa/drivers/dri/i965/brw_shader.h
index a5eed91..7205a85 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -111,6 +111,19 @@ public:
const void *ir;
const char *annotation;
/** @} */
+
+   uint32_t texture_offset; /**< Texture offset bitfield */
+   uint32_t offset; /**< spill/unspill offset */
+   uint8_t sampler;
+   uint8_t mlen; /**< SEND message length */
+   int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
+   uint8_t target; /**< MRT target. */
+   uint8_t conditional_mod; /**< BRW_CONDITIONAL_* */
+
+   bool force_writemask_all:1;
+   bool no_dd_clear:1;
+   bool no_dd_check:1;
+   bool saturate:1;
 };
 
 enum instruction_scheduler_mode {
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 4b6e638..21df552 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -215,23 +215,10 @@ public:
dst_reg dst;
src_reg src[3];
 
-   bool saturate;
-   bool force_writemask_all;
-   bool no_dd_clear, no_dd_check;
-
-   int conditional_mod; /**< BRW_CONDITIONAL_* */
-
-   int sampler;
-   uint32_t texture_offset; /**< Texture Offset bitfield */
-   int target; /**< MRT target. */
bool shadow_compare;
 
enum brw_urb_write_flags urb_write_flags;
bool header_present;
-   int mlen; /**< SEND message length */
-   int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
-
-   uint32_t offset; /* spill/unspill offset */
 
bool is_send_from_grf();
bool can_reswizzle_dst(int dst_writemask, int swizzle, int swizzle_mask);
-- 
1.8.3.2

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[Mesa-dev] [PATCH 11/13] i965: Make backend_instruction usable from C.

[Matt Turner]

With a hack to place an exec_node in the struct in C to be at the same
location as the inherited exec_node in C++.
---
 src/mesa/drivers/dri/i965/brw_shader.h | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_shader.h 
b/src/mesa/drivers/dri/i965/brw_shader.h
index e021820..f866249 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -78,12 +78,10 @@ struct backend_reg
bool abs;
 };
 
-#ifdef __cplusplus
-
 struct cfg_t;
 
+#ifdef __cplusplus
 struct backend_instruction : public exec_node {
-public:
bool is_tex() const;
bool is_math() const;
bool is_control_flow() const;
@@ -98,7 +96,10 @@ public:
 * optimize these out unless you know what you are doing.
 */
bool has_side_effects() const;
-
+#else
+struct backend_instruction {
+   struct exec_node link;
+#endif
/** @{
 * Annotation for the generated IR.  One of the two can be set.
 */
@@ -124,6 +125,8 @@ public:
bool saturate:1;
 };
 
+#ifdef __cplusplus
+
 enum instruction_scheduler_mode {
SCHEDULE_PRE,
SCHEDULE_PRE_NON_LIFO,
-- 
1.8.3.2

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[Mesa-dev] [PATCH 08/13] i965: Make a brw_predicate enum.

[Matt Turner]

---
 src/mesa/drivers/dri/i965/brw_defines.h| 38 ++
 src/mesa/drivers/dri/i965/brw_fs.cpp   |  2 +-
 src/mesa/drivers/dri/i965/brw_fs.h |  2 +-
 src/mesa/drivers/dri/i965/brw_shader.h |  2 +-
 src/mesa/drivers/dri/i965/brw_vec4.h   |  6 ++--
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 12 
 6 files changed, 33 insertions(+), 29 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 822156d..a0fcc51 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1015,24 +1015,26 @@ operator|(brw_urb_write_flags x, brw_urb_write_flags y)
 }
 #endif
 
-#define BRW_PREDICATE_NONE 0
-#define BRW_PREDICATE_NORMAL   1
-#define BRW_PREDICATE_ALIGN1_ANYV 2
-#define BRW_PREDICATE_ALIGN1_ALLV 3
-#define BRW_PREDICATE_ALIGN1_ANY2H4
-#define BRW_PREDICATE_ALIGN1_ALL2H5
-#define BRW_PREDICATE_ALIGN1_ANY4H6
-#define BRW_PREDICATE_ALIGN1_ALL4H7
-#define BRW_PREDICATE_ALIGN1_ANY8H8
-#define BRW_PREDICATE_ALIGN1_ALL8H9
-#define BRW_PREDICATE_ALIGN1_ANY16H   10
-#define BRW_PREDICATE_ALIGN1_ALL16H   11
-#define BRW_PREDICATE_ALIGN16_REPLICATE_X 2
-#define BRW_PREDICATE_ALIGN16_REPLICATE_Y 3
-#define BRW_PREDICATE_ALIGN16_REPLICATE_Z 4
-#define BRW_PREDICATE_ALIGN16_REPLICATE_W 5
-#define BRW_PREDICATE_ALIGN16_ANY4H   6
-#define BRW_PREDICATE_ALIGN16_ALL4H   7
+enum PACKED brw_predicate {
+   BRW_PREDICATE_NONE=  0,
+   BRW_PREDICATE_NORMAL  =  1,
+   BRW_PREDICATE_ALIGN1_ANYV =  2,
+   BRW_PREDICATE_ALIGN1_ALLV =  3,
+   BRW_PREDICATE_ALIGN1_ANY2H=  4,
+   BRW_PREDICATE_ALIGN1_ALL2H=  5,
+   BRW_PREDICATE_ALIGN1_ANY4H=  6,
+   BRW_PREDICATE_ALIGN1_ALL4H=  7,
+   BRW_PREDICATE_ALIGN1_ANY8H=  8,
+   BRW_PREDICATE_ALIGN1_ALL8H=  9,
+   BRW_PREDICATE_ALIGN1_ANY16H   = 10,
+   BRW_PREDICATE_ALIGN1_ALL16H   = 11,
+   BRW_PREDICATE_ALIGN16_REPLICATE_X =  2,
+   BRW_PREDICATE_ALIGN16_REPLICATE_Y =  3,
+   BRW_PREDICATE_ALIGN16_REPLICATE_Z =  4,
+   BRW_PREDICATE_ALIGN16_REPLICATE_W =  5,
+   BRW_PREDICATE_ALIGN16_ANY4H   =  6,
+   BRW_PREDICATE_ALIGN16_ALL4H   =  7,
+};
 
 #define BRW_ARCHITECTURE_REGISTER_FILE0
 #define BRW_GENERAL_REGISTER_FILE 1
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index f56474f..1d04061 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -189,7 +189,7 @@ ALU2(MAC)
 
 /** Gen4 predicated IF. */
 fs_inst *
-fs_visitor::IF(uint32_t predicate)
+fs_visitor::IF(enum brw_predicate predicate)
 {
fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF);
inst->predicate = predicate;
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h 
b/src/mesa/drivers/dri/i965/brw_fs.h
index bffdb2c..fdb0efe 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -272,7 +272,7 @@ public:
fs_inst *AND(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
fs_inst *OR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
fs_inst *XOR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
-   fs_inst *IF(uint32_t predicate);
+   fs_inst *IF(enum brw_predicate predicate);
fs_inst *IF(const fs_reg &src0, const fs_reg &src1,
enum brw_conditional_mod condition);
fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h 
b/src/mesa/drivers/dri/i965/brw_shader.h
index 7c84ab4..3205b67 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -101,7 +101,7 @@ public:
 
enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
 
-   uint8_t predicate;
+   enum brw_predicate predicate;
bool predicate_inverse;
bool writes_accumulator; /**< instruction implicitly writes accumulator */
 
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index d61909d..247d591 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -444,7 +444,7 @@ public:
 enum brw_conditional_mod condition);
vec4_instruction *IF(src_reg src0, src_reg src1,
 enum brw_conditional_mod condition);
-   vec4_instruction *IF(uint32_t predicate);
+   vec4_instruction *IF(enum brw_predicate predicate);
vec4_instruction *PULL_CONSTANT_LOAD(const dst_reg &dst,
 const src_reg &index);
vec4_instruction *SCRATCH_READ(const dst_reg &dst, const src_reg &index);
@@ -483,7 +483,7 @@ public:
void emit_vp_sop(enum brw_conditional_mod condmod, dst_reg dst,
 src_reg src0, src

[Mesa-dev] [PATCH 09/13] i965: Repack backend_instruction struct.

[Matt Turner]

---
 src/mesa/drivers/dri/i965/brw_shader.h | 12 +---
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_shader.h 
b/src/mesa/drivers/dri/i965/brw_shader.h
index 3205b67..558d052 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -99,12 +99,6 @@ public:
 */
bool has_side_effects() const;
 
-   enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
-
-   enum brw_predicate predicate;
-   bool predicate_inverse;
-   bool writes_accumulator; /**< instruction implicitly writes accumulator */
-
/** @{
 * Annotation for the generated IR.  One of the two can be set.
 */
@@ -118,8 +112,12 @@ public:
uint8_t mlen; /**< SEND message length */
int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
uint8_t target; /**< MRT target. */
-   enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
 
+   enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
+   enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
+   enum brw_predicate predicate;
+   bool predicate_inverse:1;
+   bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
bool force_writemask_all:1;
bool no_dd_clear:1;
bool no_dd_check:1;
-- 
1.8.3.2

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[Mesa-dev] [PATCH 05/13] i965: Use enum brw_reg_type for register types.

[Matt Turner]

---
 src/mesa/drivers/dri/i965/brw_blorp.h| 3 ++-
 src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
 src/mesa/drivers/dri/i965/brw_fs.h   | 4 ++--
 src/mesa/drivers/dri/i965/brw_reg.h  | 8 
 src/mesa/drivers/dri/i965/brw_shader.cpp | 2 +-
 src/mesa/drivers/dri/i965/brw_shader.h   | 4 ++--
 src/mesa/drivers/dri/i965/brw_vec4.h | 4 ++--
 7 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 15a7a0b..683f09e 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -26,6 +26,7 @@
 #include 
 
 #include "brw_context.h"
+#include "brw_reg.h"
 #include "intel_mipmap_tree.h"
 
 struct brw_context;
@@ -299,7 +300,7 @@ struct brw_blorp_blit_prog_key
/* Type of the data to be read from the texture (one of
 * BRW_REGISTER_TYPE_{UD,D,F}).
 */
-   unsigned texture_data_type;
+   enum brw_reg_type texture_data_type;
 
/* True if the source image is W tiled.  If true, the surface state for the
 * source image must be configured as Y tiled, and tex_samples must be 0.
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 15d0fd5..47b8d86 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -867,7 +867,7 @@ fs_reg::fs_reg(enum register_file file, int reg)
 }
 
 /** Fixed HW reg constructor. */
-fs_reg::fs_reg(enum register_file file, int reg, uint32_t type)
+fs_reg::fs_reg(enum register_file file, int reg, enum brw_reg_type type)
 {
init();
this->file = file;
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h 
b/src/mesa/drivers/dri/i965/brw_fs.h
index 530e54b..4781079 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -75,7 +75,7 @@ public:
fs_reg(uint32_t u);
fs_reg(struct brw_reg fixed_hw_reg);
fs_reg(enum register_file file, int reg);
-   fs_reg(enum register_file file, int reg, uint32_t type);
+   fs_reg(enum register_file file, int reg, enum brw_reg_type type);
fs_reg(class fs_visitor *v, const struct glsl_type *type);
 
bool equals(const fs_reg &r) const;
@@ -99,7 +99,7 @@ public:
 };
 
 static inline fs_reg
-retype(fs_reg reg, unsigned type)
+retype(fs_reg reg, enum brw_reg_type type)
 {
reg.fixed_hw_reg.type = reg.type = type;
return reg;
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h 
b/src/mesa/drivers/dri/i965/brw_reg.h
index b2273c3..494ce8c 100644
--- a/src/mesa/drivers/dri/i965/brw_reg.h
+++ b/src/mesa/drivers/dri/i965/brw_reg.h
@@ -131,7 +131,7 @@ const char *brw_reg_type_letters(unsigned brw_reg_type);
  * or "structure of array" form:
  */
 struct brw_reg {
-   unsigned type:4;
+   enum brw_reg_type type:4;
unsigned file:2;
unsigned nr:8;
unsigned subnr:5;  /* :1 in align16 */
@@ -227,7 +227,7 @@ static inline struct brw_reg
 brw_reg(unsigned file,
 unsigned nr,
 unsigned subnr,
-unsigned type,
+enum brw_reg_type type,
 unsigned vstride,
 unsigned width,
 unsigned hstride,
@@ -362,7 +362,7 @@ brw_vecn_reg(unsigned width, unsigned file, unsigned nr, 
unsigned subnr)
 }
 
 static inline struct brw_reg
-retype(struct brw_reg reg, unsigned type)
+retype(struct brw_reg reg, enum brw_reg_type type)
 {
reg.type = type;
return reg;
@@ -424,7 +424,7 @@ brw_uw1_reg(unsigned file, unsigned nr, unsigned subnr)
 }
 
 static inline struct brw_reg
-brw_imm_reg(unsigned type)
+brw_imm_reg(enum brw_reg_type type)
 {
return brw_reg(BRW_IMMEDIATE_VALUE,
   0,
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp 
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index fa42733..58ebd33 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -279,7 +279,7 @@ brw_link_shader(struct gl_context *ctx, struct 
gl_shader_program *shProg)
 }
 
 
-int
+enum brw_reg_type
 brw_type_for_base_type(const struct glsl_type *type)
 {
switch (type->base_type) {
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h 
b/src/mesa/drivers/dri/i965/brw_shader.h
index b0908a3..a5eed91 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -50,7 +50,7 @@ struct backend_reg
 #endif
 
enum register_file file; /**< Register file: GRF, MRF, IMM. */
-   uint8_t type;/**< Register type: BRW_REGISTER_TYPE_* */
+   enum brw_reg_type type;  /**< Register type: BRW_REGISTER_TYPE_* */
 
/**
 * Register number.
@@ -166,7 +166,7 @@ void annotation_finalize(struct annotation_info 
*annotation, unsigned offset);
 
 #endif /* __cplusplus */
 
-int brw_type_for_base_type(const struct glsl_type *type);
+enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
 uint32_t brw_conditional_for_comparison(unsigned int op);
 uint32_t brw_math_function(enum opcode op);
 const char *brw_instruction_name(enum opcod

[Mesa-dev] [PATCH 01/13] i965: Use immediate storage in brw_reg for visitor regs.

[Matt Turner]

---
 src/mesa/drivers/dri/i965/brw_fs.cpp   | 26 --
 .../drivers/dri/i965/brw_fs_copy_propagation.cpp   |  4 ++--
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp |  6 ++---
 src/mesa/drivers/dri/i965/brw_vec4.cpp | 24 +---
 .../drivers/dri/i965/brw_vec4_copy_propagation.cpp | 10 -
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp   |  6 ++---
 6 files changed, 37 insertions(+), 39 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index d22b1bf..b260409 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -408,7 +408,7 @@ fs_reg::fs_reg(float f)
init();
this->file = IMM;
this->type = BRW_REGISTER_TYPE_F;
-   this->imm.f = f;
+   this->fixed_hw_reg.dw1.f = f;
 }
 
 /** Immediate value constructor. */
@@ -417,7 +417,7 @@ fs_reg::fs_reg(int32_t i)
init();
this->file = IMM;
this->type = BRW_REGISTER_TYPE_D;
-   this->imm.i = i;
+   this->fixed_hw_reg.dw1.d = i;
 }
 
 /** Immediate value constructor. */
@@ -426,7 +426,7 @@ fs_reg::fs_reg(uint32_t u)
init();
this->file = IMM;
this->type = BRW_REGISTER_TYPE_UD;
-   this->imm.u = u;
+   this->fixed_hw_reg.dw1.ud = u;
 }
 
 /** Fixed brw_reg. */
@@ -452,7 +452,7 @@ fs_reg::equals(const fs_reg &r) const
memcmp(&fixed_hw_reg, &r.fixed_hw_reg,
   sizeof(fixed_hw_reg)) == 0 &&
stride == r.stride &&
-   imm.u == r.imm.u);
+   fixed_hw_reg.dw1.ud == r.fixed_hw_reg.dw1.ud);
 }
 
 fs_reg &
@@ -486,7 +486,7 @@ fs_reg::is_zero() const
if (file != IMM)
   return false;
 
-   return type == BRW_REGISTER_TYPE_F ? imm.f == 0.0 : imm.i == 0;
+   return fixed_hw_reg.dw1.d == 0;
 }
 
 bool
@@ -495,7 +495,9 @@ fs_reg::is_one() const
if (file != IMM)
   return false;
 
-   return type == BRW_REGISTER_TYPE_F ? imm.f == 1.0 : imm.i == 1;
+   return type == BRW_REGISTER_TYPE_F
+  ? fixed_hw_reg.dw1.f == 1.0
+  : fixed_hw_reg.dw1.d == 1;
 }
 
 bool
@@ -2028,7 +2030,7 @@ fs_visitor::opt_algebraic()
 case BRW_CONDITIONAL_L:
switch (inst->src[1].type) {
case BRW_REGISTER_TYPE_F:
-  if (inst->src[1].imm.f >= 1.0f) {
+  if (inst->src[1].fixed_hw_reg.dw1.f >= 1.0f) {
  inst->opcode = BRW_OPCODE_MOV;
  inst->src[1] = reg_undef;
  progress = true;
@@ -2042,7 +2044,7 @@ fs_visitor::opt_algebraic()
 case BRW_CONDITIONAL_G:
switch (inst->src[1].type) {
case BRW_REGISTER_TYPE_F:
-  if (inst->src[1].imm.f <= 0.0f) {
+  if (inst->src[1].fixed_hw_reg.dw1.f <= 0.0f) {
  inst->opcode = BRW_OPCODE_MOV;
  inst->src[1] = reg_undef;
  inst->conditional_mod = BRW_CONDITIONAL_NONE;
@@ -2537,7 +2539,7 @@ fs_visitor::lower_uniform_pull_constant_loads()
  fs_reg const_offset_reg = inst->src[1];
  assert(const_offset_reg.file == IMM &&
 const_offset_reg.type == BRW_REGISTER_TYPE_UD);
- const_offset_reg.imm.u /= 4;
+ const_offset_reg.fixed_hw_reg.dw1.ud /= 4;
  fs_reg payload = fs_reg(this, glsl_type::uint_type);
 
  /* This is actually going to be a MOV, but since only the first dword
@@ -2749,13 +2751,13 @@ fs_visitor::dump_instruction(backend_instruction 
*be_inst, FILE *file)
   case IMM:
  switch (inst->src[i].type) {
  case BRW_REGISTER_TYPE_F:
-fprintf(file, "%ff", inst->src[i].imm.f);
+fprintf(file, "%ff", inst->src[i].fixed_hw_reg.dw1.f);
 break;
  case BRW_REGISTER_TYPE_D:
-fprintf(file, "%dd", inst->src[i].imm.i);
+fprintf(file, "%dd", inst->src[i].fixed_hw_reg.dw1.d);
 break;
  case BRW_REGISTER_TYPE_UD:
-fprintf(file, "%uu", inst->src[i].imm.u);
+fprintf(file, "%uu", inst->src[i].fixed_hw_reg.dw1.ud);
 break;
  default:
 fprintf(file, "???");
diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
index 72329e1..3452a95 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
@@ -483,10 +483,10 @@ try_constant_propagate(struct brw_context *brw, fs_inst 
*inst,
   * anyway.
   */
  assert(i == 0);
- if (inst->src[0].imm.f != 0.0f) {
+ if (inst->src[0].fixed_hw_reg.dw1.f != 0.0f) {
 inst->opcode = BRW_OPCODE_MOV;
 inst->src[0] = entry->src;
-inst->src[0].imm.f = 1.0f / inst->src[0].imm.f;
+inst->src[0].fixed_hw_reg.dw1.f = 1.0f / 
inst->src[0].fixed_hw_reg.dw1.f;
 progress = true;
  }
 

[Mesa-dev] [PATCH 03/13] i965: Make a common backend_reg class.

[Matt Turner]

---
 src/mesa/drivers/dri/i965/brw_fs.h | 24 +---
 src/mesa/drivers/dri/i965/brw_shader.h | 32 ++
 src/mesa/drivers/dri/i965/brw_vec4.h   | 20 ++
 .../drivers/dri/i965/brw_vec4_reg_allocate.cpp |  2 +-
 4 files changed, 36 insertions(+), 42 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.h 
b/src/mesa/drivers/dri/i965/brw_fs.h
index c32b0a6..b6a5717 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -63,7 +63,7 @@ namespace brw {
class fs_live_variables;
 }
 
-class fs_reg {
+class fs_reg : public backend_reg {
 public:
DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
 
@@ -90,36 +90,14 @@ public:
/** Smear a channel of the reg to all channels. */
fs_reg &set_smear(unsigned subreg);
 
-   /** Register file: GRF, MRF, IMM. */
-   enum register_file file;
-   /** Register type.  BRW_REGISTER_TYPE_* */
-   uint8_t type;
-   /**
-* Register number.  For MRF, it's the hardware register.  For
-* GRF, it's a virtual register number until register allocation
-*/
-   uint16_t reg;
-   /**
-* Offset from the start of the contiguous register block.
-*
-* For pre-register-allocation GRFs, this is in units of a float per pixel
-* (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode).
-* For uniforms, this is in units of 1 float.
-*/
-   int reg_offset;
/**
 * Offset in bytes from the start of the register.  Values up to a
 * backend_reg::reg_offset unit are valid.
 */
int subreg_offset;
 
-   struct brw_reg fixed_hw_reg;
-
fs_reg *reladdr;
 
-   bool negate;
-   bool abs;
-
/** Register region horizontal stride */
uint8_t stride;
 };
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h 
b/src/mesa/drivers/dri/i965/brw_shader.h
index e602bcd..3896442 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -22,6 +22,7 @@
  */
 
 #include 
+#include "brw_reg.h"
 #include "brw_defines.h"
 #include "main/compiler.h"
 #include "glsl/ir.h"
@@ -39,6 +40,37 @@ enum PACKED register_file {
UNIFORM, /* prog_data->params[reg] */
 };
 
+struct backend_reg
+{
+   enum register_file file; /**< Register file: GRF, MRF, IMM. */
+   uint8_t type;/**< Register type: BRW_REGISTER_TYPE_* */
+
+   /**
+* Register number.
+*
+* For GRF, it's a virtual register number until register allocation.
+*
+* For MRF, it's the hardware register.
+*/
+   uint16_t reg;
+
+   /**
+* Offset within the virtual register.
+*
+* In the scalar backend, this is in units of a float per pixel for pre-
+* register allocation registers (i.e., one register in SIMD8 mode and two
+* registers in SIMD16 mode).
+*
+* For uniforms, this is in units of 1 float.
+*/
+   int reg_offset;
+
+   struct brw_reg fixed_hw_reg;
+
+   bool negate;
+   bool abs;
+};
+
 #ifdef __cplusplus
 
 class cfg_t;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 9a5b1cb..9fd14f8 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -91,21 +91,7 @@ class dst_reg;
 unsigned
 swizzle_for_size(int size);
 
-class reg
-{
-public:
-   /** Register file: GRF, MRF, IMM. */
-   enum register_file file;
-   /** virtual register number.  0 = fixed hw reg */
-   int reg;
-   /** Offset within the virtual register. */
-   int reg_offset;
-   /** Register type.  BRW_REGISTER_TYPE_* */
-   int type;
-   struct brw_reg fixed_hw_reg;
-};
-
-class src_reg : public reg
+class src_reg : public backend_reg
 {
 public:
DECLARE_RALLOC_CXX_OPERATORS(src_reg)
@@ -129,8 +115,6 @@ public:
explicit src_reg(dst_reg reg);
 
GLuint swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
-   bool negate;
-   bool abs;
 
src_reg *reladdr;
 };
@@ -174,7 +158,7 @@ negate(src_reg reg)
return reg;
 }
 
-class dst_reg : public reg
+class dst_reg : public backend_reg
 {
 public:
DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index 4ffc537..1caf5ab 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -34,7 +34,7 @@ using namespace brw;
 namespace brw {
 
 static void
-assign(unsigned int *reg_hw_locations, reg *reg)
+assign(unsigned int *reg_hw_locations, backend_reg *reg)
 {
if (reg->file == GRF) {
   reg->reg = reg_hw_locations[reg->reg];
-- 
1.8.3.2

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[Mesa-dev] [Bug 80615] Files in bellagio directory [omx tracker] don't respect installation folder

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=80615

--- Comment #5 from Emil Velikov  ---
AFAICS the whole thing is quite inconsistent.

(In reply to comment #3)
> That's something I hadn't noticed. However, it still bugs me. Why would this
> component deal with its installation path differently from the others. Let's
> have a look at opencl, vdpau and egl :
>   --with-vdpau-libdir=DIR directory for the VDPAU libraries
>   [default=${libdir}/vdpau]
Defined by libvdpau. Can be accessed/queried via pkg-config (moduledir)

>   --with-opencl-libdir=DIR
>   directory for auxiliary libraries used by the
> OpenCL
>   implementation [default=${libdir}/opencl]
Unused.

>   --with-egl-driver-dir=DIR
>   directory for EGL drivers [[default=${libdir}/egl]]
> 
Internal to mesa. Ideally we'll have this one nuked for the next release.

> And then we have omx :
>   --with-omx-libdir=DIR   directory for the OMX libraries
> 
Defined by bellagio. Can be accessed/queried via pkg-config (pluginsdir)

> It seems omx is one of a kind by not using something ${libdir}/bellagio. By
> doing this small modification, a user wouldn't be surprise to have this only
> component install not in the libdir he asked for, but he would still be able
> to set a different path if needed.
> 
It can be argued either way, yet imho we should be using pkg-config when
possible. I don't mind either way, as long as Christian is happy with the
solution.

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[Mesa-dev] [Bug 80615] Files in bellagio directory [omx tracker] don't respect installation folder

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=80615

--- Comment #4 from Alexandre Demers  ---
Emil, I just sent a patch on mesa-dev, but maybe I should have included you in
CC though. See
http://lists.freedesktop.org/archives/mesa-dev/2014-June/062477.html

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[Mesa-dev] [PATCH] configure.ac: fix omx default installation folder

[Alexandre Demers]

Making default OMX installation folder follows the same pattern as 
other state trackers / libs. Fixes bug 80615.

Signed-off-by: Alexandre Demers 
---
 configure.ac | 10 +++---
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/configure.ac b/configure.ac
index 98efa43..a684390 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1794,16 +1794,12 @@ AC_ARG_WITH([vdpau-libdir],
 [VDPAU_LIB_INSTALL_DIR='${libdir}/vdpau'])
 AC_SUBST([VDPAU_LIB_INSTALL_DIR])
 
-OMX_LIB_INSTALL_DIR_DEFAULT=''
-if test "x$enable_omx" = xyes; then
-OMX_LIB_INSTALL_DIR_DEFAULT=`$PKG_CONFIG --variable=pluginsdir 
libomxil-bellagio`
-fi
-
+dnl Directory for OMX libs
 AC_ARG_WITH([omx-libdir],
 [AS_HELP_STRING([--with-omx-libdir=DIR],
-[directory for the OMX libraries])],
+[directory for the OMX libraries @<:@default=${libdir}/bellagio@:>@])],
 [OMX_LIB_INSTALL_DIR="$withval"],
-[OMX_LIB_INSTALL_DIR="$OMX_LIB_INSTALL_DIR_DEFAULT"])
+[OMX_LIB_INSTALL_DIR="${libdir}/bellagio"])
 AC_SUBST([OMX_LIB_INSTALL_DIR])
 
 dnl Directory for OpenCL libs
-- 
2.0.0

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[Mesa-dev] [PATCH] configure.ac: (trivial) Fixing a typo

[Alexandre Demers]

Signed-off-by: Alexandre Demers 
---
 configure.ac | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configure.ac b/configure.ac
index faf1485..98efa43 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1603,7 +1603,7 @@ fi
 
 AC_ARG_WITH([egl-driver-dir],
 [AS_HELP_STRING([--with-egl-driver-dir=DIR],
-[directory for EGL drivers [[default=${libdir}/egl]]])],
+[directory for EGL drivers 
@<:@default=${libdir}/egl@:>@])],
 [EGL_DRIVER_INSTALL_DIR="$withval"],
 [EGL_DRIVER_INSTALL_DIR='${libdir}/egl'])
 AC_SUBST([EGL_DRIVER_INSTALL_DIR])
-- 
2.0.0

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Re: [Mesa-dev] [PATCH 23/23] i965/disasm: Fix INTEL_DEBUG=fs on Broadwell for ARB_fp applications.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:34:02PM -0700, Kenneth Graunke wrote:
> Apparently INTEL_DEBUG=fs has crashed on Broadwell for anything using
> ARB_fragment_program since commit 9cee3ff5.  We need to NULL-check the
> right field.
> 
> Signed-off-by: Kenneth Graunke 
> Cc: "10.2" 

Reviewed-by: Kristian Høgsberg 

> ---
>  src/mesa/drivers/dri/i965/gen8_fs_generator.cpp | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> I could've sworn I fixed this, but apparently I was thinking about
> commit 2f97119950515c841bca98a890e5110206bad945, which fixed a similar
> bug in the VS visitor.
> 
> diff --git a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp 
> b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
> index 4725774..ac8bf1d 100644
> --- a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
> @@ -1255,7 +1255,7 @@ gen8_fs_generator::generate_code(exec_list 
> *instructions)
> int before_size = next_inst_offset - start_offset;
>  
> if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
> -  if (prog) {
> +  if (shader_prog) {
>   fprintf(stderr,
>   "Native code for %s fragment shader %d (SIMD%d 
> dispatch):\n",
>  shader_prog->Label ? shader_prog->Label : "unnamed",
> -- 
> 2.0.0
> 
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Re: [Mesa-dev] [PATCH 22/23] i965/disasm: Delete gen8_disasm.c.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:34:01PM -0700, Kenneth Graunke wrote:
> The functionality has been merged into brw_disasm.c; use that instead.
> 
> Signed-off-by: Kenneth Graunke 
> ---
>  src/mesa/drivers/dri/i965/Makefile.sources   |1 -
>  src/mesa/drivers/dri/i965/gen8_disasm.c  | 1026 
> --
>  src/mesa/drivers/dri/i965/gen8_instruction.h |4 -
>  3 files changed, 1031 deletions(-)
>  delete mode 100644 src/mesa/drivers/dri/i965/gen8_disasm.c

Reviewed-by: Kristian Høgsberg 
 
> diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
> b/src/mesa/drivers/dri/i965/Makefile.sources
> index 2570059..6c513e2 100644
> --- a/src/mesa/drivers/dri/i965/Makefile.sources
> +++ b/src/mesa/drivers/dri/i965/Makefile.sources
> @@ -146,7 +146,6 @@ i965_FILES = \
>   gen7_wm_state.c \
>   gen7_wm_surface_state.c \
>   gen8_blend_state.c \
> - gen8_disasm.c \
>   gen8_depth_state.c \
>   gen8_disable.c \
>   gen8_draw_upload.c \
> diff --git a/src/mesa/drivers/dri/i965/gen8_disasm.c 
> b/src/mesa/drivers/dri/i965/gen8_disasm.c
> deleted file mode 100644
> index 98e2453..000
> --- a/src/mesa/drivers/dri/i965/gen8_disasm.c
> +++ /dev/null
> @@ -1,1026 +0,0 @@
> -/*
> - * Copyright © 2008 Keith Packard
> - * Copyright © 2009-2013 Intel Corporation
> - *
> - * Permission to use, copy, modify, distribute, and sell this software and 
> its
> - * documentation for any purpose is hereby granted without fee, provided that
> - * the above copyright notice appear in all copies and that both that 
> copyright
> - * notice and this permission notice appear in supporting documentation, and
> - * that the name of the copyright holders not be used in advertising or
> - * publicity pertaining to distribution of the software without specific,
> - * written prior permission.  The copyright holders make no representations
> - * about the suitability of this software for any purpose.  It is provided 
> "as
> - * is" without express or implied warranty.
> - *
> - * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS 
> SOFTWARE,
> - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
> - * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
> - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF 
> USE,
> - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
> - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 
> PERFORMANCE
> - * OF THIS SOFTWARE.
> - */
> -
> -#include 
> -#include 
> -#include 
> -#include 
> -#include 
> -#include 
> -
> -#include "brw_context.h"
> -#include "brw_defines.h"
> -#include "gen8_instruction.h"
> -
> -static const struct opcode_desc *m_opcode = opcode_descs;
> -
> -static const char *const m_conditional_modifier[16] = {
> -   [BRW_CONDITIONAL_NONE] = "",
> -   [BRW_CONDITIONAL_Z]= ".e",
> -   [BRW_CONDITIONAL_NZ]   = ".ne",
> -   [BRW_CONDITIONAL_G]= ".g",
> -   [BRW_CONDITIONAL_GE]   = ".ge",
> -   [BRW_CONDITIONAL_L]= ".l",
> -   [BRW_CONDITIONAL_LE]   = ".le",
> -   [BRW_CONDITIONAL_O]= ".o",
> -   [BRW_CONDITIONAL_U]= ".u",
> -};
> -
> -static const char *const m_negate[2] = { "", "-" };
> -
> -static const char *const m_abs[2] = { "", "(abs)" };
> -
> -static const char *const m_bitnot[2] = { "", "~" };
> -
> -static const char *const m_vert_stride[16] = {
> -   "0",
> -   "1",
> -   "2",
> -   "4",
> -   "8",
> -   "16",
> -   "32",
> -};
> -
> -static const char *const width[8] = {
> -   "1",
> -   "2",
> -   "4",
> -   "8",
> -   "16",
> -};
> -
> -static const char *const m_horiz_stride[4] = {
> -   "0",
> -   "1",
> -   "2",
> -   "4"
> -};
> -
> -static const char *const m_chan_sel[4] = { "x", "y", "z", "w" };
> -
> -static const char *const m_debug_ctrl[2] = { "", ".breakpoint" };
> -
> -static const char *const m_saturate[2] = { "", ".sat" };
> -
> -static const char *const m_accwr[2] = { "", "AccWrEnable" };
> -
> -static const char *const m_maskctrl[2] = { "WE_normal", "WE_all" };
> -
> -static const char *const m_exec_size[8] = {
> -   "1",
> -   "2",
> -   "4",
> -   "8",
> -   "16",
> -   "32",
> -};
> -
> -static const char *const m_pred_inv[2] = { "+", "-" };
> -
> -static const char *const m_pred_ctrl_align16[16] = {
> -   "",
> -   "",
> -   ".x",
> -   ".y",
> -   ".z",
> -   ".w",
> -   ".any4h",
> -   ".all4h",
> -};
> -
> -static const char *const m_pred_ctrl_align1[16] = {
> -   "",
> -   "",
> -   ".anyv",
> -   ".allv",
> -   ".any2h",
> -   ".all2h",
> -   ".any4h",
> -   ".all4h",
> -   ".any8h",
> -   ".all8h",
> -   ".any16h",
> -   ".all16h",
> -   ".any32h",
> -   ".all32h",
> -};
> -
> -static const char *const m_thread_ctrl[4] = {
> -   "",
> -   "atomic",
> -   "switch",
> -};
> -
> -static const char *const m_dep_clear[4] = {
> -   "",
> -   "NoDDClr",
> -};
> -
> -static const char *const m_dep_check[4] = {
> -   "",
> -   "NoDDChk",
> -};
> -
> -static const char *const m_m

Re: [Mesa-dev] [PATCH 21/23] i965/disasm: Stop using gen8_disassemble in favor of brw_disassemble.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:34:00PM -0700, Kenneth Graunke wrote:
> At this point, brw_disassemble can do everything gen8_disassemble can
> do - and, thanks to the new brw_inst API, it supports all generations.

Reviewed-by: Kristian Høgsberg 

> Signed-off-by: Kenneth Graunke 
> ---
>  src/mesa/drivers/dri/i965/brw_fs_generator.cpp|  3 +--
>  src/mesa/drivers/dri/i965/brw_vec4_generator.cpp  |  3 +--
>  src/mesa/drivers/dri/i965/gen8_fs_generator.cpp   |  3 +--
>  src/mesa/drivers/dri/i965/gen8_generator.cpp  | 22 --
>  src/mesa/drivers/dri/i965/gen8_generator.h|  4 
>  src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp |  3 +--
>  src/mesa/drivers/dri/i965/intel_asm_printer.c |  6 +++---
>  src/mesa/drivers/dri/i965/intel_asm_printer.h |  6 +-
>  8 files changed, 8 insertions(+), 42 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp 
> b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> index bdac2a2..0f41781 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> @@ -1795,8 +1795,7 @@ fs_generator::generate_code(exec_list *instructions)
>  
>const struct gl_program *prog = fp ? &fp->Base : NULL;
>  
> -  dump_assembly(p->store, annotation.ann_count, annotation.ann,
> -brw, prog, brw_disassemble);
> +  dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, 
> prog);
>ralloc_free(annotation.ann);
> }
>  }
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> index 5247616..9e0e7bb 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> @@ -1296,8 +1296,7 @@ vec4_generator::generate_code(exec_list *instructions)
>before_size / 16, before_size, after_size,
>100.0f * (before_size - after_size) / before_size);
>  
> -  dump_assembly(p->store, annotation.ann_count, annotation.ann,
> -brw, prog, brw_disassemble);
> +  dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, 
> prog);
>ralloc_free(annotation.ann);
> }
>  }
> diff --git a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp 
> b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
> index 6d455a3..4725774 100644
> --- a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
> @@ -1271,8 +1271,7 @@ gen8_fs_generator::generate_code(exec_list 
> *instructions)
>fprintf(stderr, "SIMD%d shader: %d instructions.\n",
>dispatch_width, before_size / 16);
>  
> -  dump_assembly(store, annotation.ann_count, annotation.ann, brw, prog,
> -gen8_disassemble);
> +  dump_assembly(store, annotation.ann_count, annotation.ann, brw, prog);
>ralloc_free(annotation.ann);
> }
>  }
> diff --git a/src/mesa/drivers/dri/i965/gen8_generator.cpp 
> b/src/mesa/drivers/dri/i965/gen8_generator.cpp
> index 2a9bf83..a41aa7b 100644
> --- a/src/mesa/drivers/dri/i965/gen8_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/gen8_generator.cpp
> @@ -619,25 +619,3 @@ gen8_generator::HALT()
> gen8_set_mask_control(inst, BRW_MASK_DISABLE);
> return inst;
>  }
> -
> -extern "C" void
> -gen8_disassemble(struct brw_context *brw, void *assembly,
> - int start, int end, FILE *out)
> -{
> -   bool dump_hex = false;
> -
> -   for (int offset = start; offset < end; offset += 16) {
> -  gen8_instruction *inst = &((gen8_instruction *)assembly)[offset / 16];
> -  fprintf(stderr, "0x%08x: ", offset);
> -
> -  if (dump_hex) {
> - fprintf(stderr, "0x%08x 0x%08x 0x%08x 0x%08x ",
> - ((uint32_t *) inst)[3],
> - ((uint32_t *) inst)[2],
> - ((uint32_t *) inst)[1],
> - ((uint32_t *) inst)[0]);
> -  }
> -
> -  gen8_disassemble_inst(stderr, inst, brw->gen);
> -   }
> -}
> diff --git a/src/mesa/drivers/dri/i965/gen8_generator.h 
> b/src/mesa/drivers/dri/i965/gen8_generator.h
> index cdb2741..f91044a 100644
> --- a/src/mesa/drivers/dri/i965/gen8_generator.h
> +++ b/src/mesa/drivers/dri/i965/gen8_generator.h
> @@ -194,7 +194,3 @@ protected:
>  
> void *mem_ctx;
>  };
> -
> -extern "C" void
> -gen8_disassemble(struct brw_context *brw, void *assembly,
> - int start, int end, FILE *out);
> diff --git a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp 
> b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
> index 82ea45a..da6c897 100644
> --- a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
> @@ -898,8 +898,7 @@ gen8_vec4_generator::generate_code(exec_list 
> *instructions)
>}
>fprintf(stderr, "vec4 shader: %d instructions.\n", before_size / 16);
>  
> -  dump_assembly(store, annotation.ann_count, a

Re: [Mesa-dev] [PATCH 20/23] i965/disasm: Improve render target write message disassembly.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:33:59PM -0700, Kenneth Graunke wrote:
> Previously, we decoded render target write messages as:
> 
>render ( RT write, 0, 16, 12, 0) mlen 8 rlen 0
> 
> which made you remember (or look up) what the numbers meant:
> 
> 1. The binding table index
> 2. The raw message control, undecoded:
>- Last Render Target Select
>- Slot Group Select
>- Message Type (SIMD8, normal SIMD16, SIMD16 replicate data, ...)
> 3. The dataport message type, again (already decoded as "RT write")
> 4. The write commit bit (0 or 1)
> 
> Needless to say, having to decipher that yourself is annoying.  Now, we
> do:
> 
>render RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0
> 
> with optional "Hi" and "WriteCommit" for slot group/write commit.
> 
> Thanks to the new brw_inst API, we can also stop duplicating code on a
> per-generation basis.

This is awesome, I've wanted that for a while, thanks.

Reviewed-by: Kristian Høgsberg 

> Signed-off-by: Kenneth Graunke 
> ---
>  src/mesa/drivers/dri/i965/brw_disasm.c | 77 
> +-
>  1 file changed, 47 insertions(+), 30 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index fa286b3..00c0fc4 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -381,6 +381,17 @@ static const char *const gen6_sfid[16] = {
> [HSW_SFID_CRE]  = "cre",
>  };
>  
> +static const char *const dp_write_port_msg_type[8] = {
> +   [0b000] = "OWord block write",
> +   [0b001] = "OWord dual block write",
> +   [0b010] = "media block write",
> +   [0b011] = "DWord scattered write",
> +   [0b100] = "RT write",
> +   [0b101] = "streamed VB write",
> +   [0b110] = "RT UNORM write", /* G45+ */
> +   [0b111] = "flush render cache",
> +};
> +
>  static const char *const dp_rc_msg_type_gen6[16] = {
> [BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ] = "OWORD block read",
> [GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ] = "RT UNORM read",
> @@ -401,6 +412,16 @@ static const char *const dp_rc_msg_type_gen6[16] = {
> [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE] = "RT UNORM 
> write",
>  };
>  
> +static const char *const m_rt_write_subtype[] = {
> +   [0b000] = "SIMD16",
> +   [0b001] = "SIMD16/RepData",
> +   [0b010] = "SIMD8/DualSrcLow",
> +   [0b011] = "SIMD8/DualSrcHigh",
> +   [0b100] = "SIMD8",
> +   [0b101] = "SIMD8/ImageWrite",   /* Gen6+ */
> +   [0b111] = "SIMD16/RepData-111", /* no idea how this is different than 1 */
> +};
> +
>  static const char *const dp_dc0_msg_type_gen7[16] = {
> [GEN7_DATAPORT_DC_OWORD_BLOCK_READ] = "DC OWORD block read",
> [GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ] =
> @@ -1322,40 +1343,36 @@ brw_disassemble_inst(FILE *file, struct brw_context 
> *brw, brw_inst *inst,
>   }
>   break;
>  
> -  case GEN6_SFID_DATAPORT_RENDER_CACHE:
> +  case GEN6_SFID_DATAPORT_RENDER_CACHE: {
>   /* aka BRW_SFID_DATAPORT_WRITE on Gen4-5 */
> - if (brw->gen >= 7) {
> -format(file, " (");
> -
> -err |= control(file, "DP rc message type",
> -   dp_rc_msg_type_gen6,
> -   brw_inst_dp_msg_type(brw, inst), &space);
> -
> -format(file, ", %d, %d, %d)",
> -   brw_inst_binding_table_index(brw, inst),
> -   brw_inst_dp_msg_control(brw, inst),
> -   brw_inst_dp_msg_type(brw, inst));
> - } else if (brw->gen == 6) {
> -format(file, " (");
> -
> -err |= control(file, "DP rc message type",
> -   dp_rc_msg_type_gen6,
> -   brw_inst_dp_msg_type(brw, inst), &space);
> -
> -format(file, ", %d, %d, %d, %d)",
> -   brw_inst_binding_table_index(brw, inst),
> -   brw_inst_dp_msg_control(brw, inst),
> -   brw_inst_dp_msg_type(brw, inst),
> -   brw_inst_dp_write_commit(brw, inst));
> + unsigned msg_type = brw_inst_dp_write_msg_type(brw, inst);
> +
> + err |= control(file, "DP rc message type",
> +brw->gen >= 6 ? dp_rc_msg_type_gen6
> +  : dp_write_port_msg_type,
> +msg_type, &space);
> +
> + bool is_rt_write = msg_type ==
> +(brw->gen >= 6 ? GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
> +   : BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE);
> +
> + if (is_rt_write) {
> +err |= control(file, "RT message type", m_rt_write_subtype,
> +   brw_inst_rt_message_type(brw, inst), &space);
> +if (brw->gen >= 6 && brw_inst_rt_slot_group(brw, inst))
> +   string(file, " Hi");
> +if (brw_inst_rt_last(brw, inst))
> +   string(file, " LastRT");
> + 

Re: [Mesa-dev] [PATCH 1/4] i965/vec4: Add basic common subexpression elimination.

[Matt Turner]

On Mon, Jun 30, 2014 at 11:49 AM, Ian Romanick  wrote:
> On 06/25/2014 02:12 PM, Matt Turner wrote:
>> From: Kenneth Graunke 
>>
>> [mattst88]: Modified to perform CSE on instructions with
>> the same writemask. Offered no improvement before.
>>
>> total instructions in shared programs: 1995633 -> 1995185 (-0.02%)
>> instructions in affected programs: 14410 -> 13962 (-3.11%)
>>
>> Reviewed-by: Matt Turner 
>> Signed-off-by: Kenneth Graunke 
>> ---
>>  src/mesa/drivers/dri/i965/Makefile.sources |   1 +
>>  src/mesa/drivers/dri/i965/brw_vec4.cpp |   1 +
>>  src/mesa/drivers/dri/i965/brw_vec4.h   |   2 +
>>  src/mesa/drivers/dri/i965/brw_vec4_cse.cpp | 237 
>> +
>>  4 files changed, 241 insertions(+)
>>  create mode 100644 src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
>>
>> diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
>> b/src/mesa/drivers/dri/i965/Makefile.sources
>> index 2570059..8f1d272 100644
>> --- a/src/mesa/drivers/dri/i965/Makefile.sources
>> +++ b/src/mesa/drivers/dri/i965/Makefile.sources
>> @@ -102,6 +102,7 @@ i965_FILES = \
>>   brw_util.c \
>>   brw_vec4.cpp \
>>   brw_vec4_copy_propagation.cpp \
>> + brw_vec4_cse.cpp \
>>   brw_vec4_generator.cpp \
>>   brw_vec4_gs.c \
>>   brw_vec4_gs_visitor.cpp \
>> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp 
>> b/src/mesa/drivers/dri/i965/brw_vec4.cpp
>> index 24903f9..0d57399 100644
>> --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
>> @@ -1747,6 +1747,7 @@ vec4_visitor::run()
>>progress = dead_control_flow_eliminate(this) || progress;
>>progress = opt_copy_propagation() || progress;
>>progress = opt_algebraic() || progress;
>> +  progress = opt_cse() || progress;
>>progress = opt_register_coalesce() || progress;
>> } while (progress);
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
>> b/src/mesa/drivers/dri/i965/brw_vec4.h
>> index 366198c..4a8eabb 100644
>> --- a/src/mesa/drivers/dri/i965/brw_vec4.h
>> +++ b/src/mesa/drivers/dri/i965/brw_vec4.h
>> @@ -426,6 +426,8 @@ public:
>> bool dead_code_eliminate();
>> bool virtual_grf_interferes(int a, int b);
>> bool opt_copy_propagation();
>> +   bool opt_cse_local(bblock_t *, exec_list *);
>> +   bool opt_cse();
>> bool opt_algebraic();
>> bool opt_register_coalesce();
>> void opt_set_dependency_control();
>> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp 
>> b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
>> new file mode 100644
>> index 000..33c7430
>> --- /dev/null
>> +++ b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
>> @@ -0,0 +1,237 @@
>> +/*
>> + * Copyright © 2012, 2013, 2014 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the 
>> "Software"),
>> + * to deal in the Software without restriction, including without limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including the next
>> + * paragraph) shall be included in all copies or substantial portions of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 
>> OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
>> DEALINGS
>> + * IN THE SOFTWARE.
>> + */
>> +
>> +#include "brw_vec4.h"
>> +#include "brw_cfg.h"
>> +
>> +using namespace brw;
>> +
>> +/** @file brw_vec4_cse.cpp
>> + *
>> + * Support for local common subexpression elimination.
>> + *
>> + * See Muchnick's Advanced Compiler Design and Implementation, section
>> + * 13.1 (p378).
>> + */
>> +
>> +namespace {
>> +struct aeb_entry : public exec_node {
>> +   /** The instruction that generates the expression value. */
>> +   vec4_instruction *generator;
>> +
>> +   /** The temporary where the value is stored. */
>> +   src_reg tmp;
>> +};
>> +}
>> +
>> +static bool
>> +is_expression(const vec4_instruction *const inst)
>
> is_expression seems like a weird name for this.  It's not obvious to a
> noob what this is doing.

Yeah, sort of is. I'd like to change this one and the fs CSE
implementation in sync.

Not sure what else to call it. can_cse_inst, something else?

>> +{
>> +   switch (inst->opcode) {
>> +   case BRW_OPCODE_SEL:
>> +   case BRW_OPCODE_NOT:
>> +   case BRW_OPCODE_AND:
>> +   case BRW_OPC

Re: [Mesa-dev] [PATCH 2/4] i965/vec4: Improve CSE performance by expiring some available expressions.

[Matt Turner]

On Mon, Jun 30, 2014 at 11:49 AM, Ian Romanick  wrote:
> On 06/25/2014 02:12 PM, Matt Turner wrote:
>> Port of commit 5daf867f to the vec4 code.
>> ---
>>  src/mesa/drivers/dri/i965/brw_vec4_cse.cpp | 20 
>>  1 file changed, 20 insertions(+)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp 
>> b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
>> index 33c7430..67fc58a 100644
>> --- a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
>> @@ -128,6 +128,7 @@ vec4_visitor::opt_cse_local(bblock_t *block, exec_list 
>> *aeb)
>>
>> void *cse_ctx = ralloc_context(NULL);
>>
>> +   int ip = block->start_ip;
>> for (vec4_instruction *inst = (vec4_instruction *)block->start;
>>  inst != block->end->next;
>>  inst = (vec4_instruction *) inst->next) {
>> @@ -198,6 +199,8 @@ vec4_visitor::opt_cse_local(bblock_t *block, exec_list 
>> *aeb)
>>   aeb_entry *entry = (aeb_entry *)entry_node;
>>
>>   for (int i = 0; i < 3; i++) {
>> +src_reg *src = &entry->generator->src[i];
>> +
>>  /* Kill all AEB entries that use the destination we just
>>   * overwrote.
>>   */
>> @@ -207,8 +210,23 @@ vec4_visitor::opt_cse_local(bblock_t *block, exec_list 
>> *aeb)
>> ralloc_free(entry);
>> break;
>>  }
>> +
>> +/* Kill any AEB entries using registers that don't get reused 
>> any
>> + * more -- a sure sign they'll fail operands_match().
>> + */
>> +int last_reg_use = MAX2(MAX2(virtual_grf_end[src->reg * 4 + 0],
>> + virtual_grf_end[src->reg * 4 + 1]),
>> +MAX2(virtual_grf_end[src->reg * 4 + 2],
>> + virtual_grf_end[src->reg * 4 + 
>> 3]));
>> +if (src->file == GRF && last_reg_use < ip) {
>> +   entry->remove();
>> +   ralloc_free(entry);
>> +   break;
>> +}
>>   }
>>}
>> +
>> +  ip++;
>> }
>>
>> ralloc_free(cse_ctx);
>> @@ -224,6 +242,8 @@ vec4_visitor::opt_cse()
>>  {
>> bool progress = false;
>>
>> +   calculate_live_intervals();
>> +
>> cfg_t cfg(&instructions);
>
> Does this also need a rebase on other patches you have pending?

Yep. I'll probably commit the other stuff first, so fix this patch up
before it goes in.
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Re: [Mesa-dev] [PATCH 18/23] i965/disasm: Fix typo in RT UNORM write message.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:33:57PM -0700, Kenneth Graunke wrote:
> The name of this message is "Render Target UNORM Write" (Sandybridge
> PRM, Volume 4 Part 1, Page 210).  Drop the bogus 'c'.
> 
> Signed-off-by: Kenneth Graunke 

Reviewed-by: Kristian Høgsberg 

> ---
>  src/mesa/drivers/dri/i965/brw_disasm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index b739cc8..9cada6d 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -397,7 +397,7 @@ static const char *const dp_rc_msg_type_gen6[16] = {
>"DWORD scattered write",
> [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE] = "RT write",
> [GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE] = "streamed VB write",
> -   [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE] = "RT UNORMc 
> write",
> +   [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE] = "RT UNORM 
> write",
>  };
>  
>  static const char *const dp_dc0_msg_type_gen7[16] = {
> -- 
> 2.0.0
> 
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Re: [Mesa-dev] [PATCH 19/23] i965/disasm: Rename msg_target to SFID.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:33:58PM -0700, Kenneth Graunke wrote:
> We haven't used the name "message target" in a while - there are a lot
> of things called "target", and it gets confusing.  SFID ("Shared
> Function ID") is the term commonly used in the modern documentation.
> 
> Signed-off-by: Kenneth Graunke 

Reviewed-by: Kristian Høgsberg 

> ---
>  src/mesa/drivers/dri/i965/brw_disasm.c | 20 
>  1 file changed, 8 insertions(+), 12 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index 9cada6d..fa286b3 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -352,7 +352,8 @@ static const char *const end_of_thread[2] = {
> [1] = "EOT"
>  };
>  
> -static const char *const target_function[16] = {
> +/* SFIDs on Gen4-5 */
> +static const char *const gen4_sfid[16] = {
> [BRW_SFID_NULL]= "null",
> [BRW_SFID_MATH]= "math",
> [BRW_SFID_SAMPLER] = "sampler",
> @@ -364,7 +365,7 @@ static const char *const target_function[16] = {
> [BRW_SFID_VME] = "vme",
>  };
>  
> -static const char *const target_function_gen6[16] = {
> +static const char *const gen6_sfid[16] = {
> [BRW_SFID_NULL] = "null",
> [BRW_SFID_MATH] = "math",
> [BRW_SFID_SAMPLER]  = "sampler",
> @@ -1262,22 +1263,17 @@ brw_disassemble_inst(FILE *file, struct brw_context 
> *brw, brw_inst *inst,
> }
>  
> if (opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC) {
> -  enum brw_message_target target = brw_inst_sfid(brw, inst);
> +  enum brw_message_target sfid = brw_inst_sfid(brw, inst);
>  
>newline(file);
>pad(file, 16);
>space = 0;
>  
>fprintf(file, "");
> -  if (brw->gen >= 6) {
> - err |= control(file, "target function", target_function_gen6,
> -target, &space);
> -  } else {
> - err |= control(file, "target function", target_function,
> -target, &space);
> -  }
> +  err |= control(file, "SFID", brw->gen >= 6 ? gen6_sfid : gen4_sfid,
> + sfid, &space);
>  
> -  switch (target) {
> +  switch (sfid) {
>case BRW_SFID_MATH:
>   err |= control(file, "math function", math_function,
>  brw_inst_math_msg_function(brw, inst), &space);
> @@ -1451,7 +1447,7 @@ brw_disassemble_inst(FILE *file, struct brw_context 
> *brw, brw_inst *inst,
>}
>  
>default:
> - format(file, "unsupported target %d", target);
> + format(file, "unsupported shared function ID %d", sfid);
>   break;
>}
>if (space)
> -- 
> 2.0.0
> 
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Re: [Mesa-dev] [PATCH 17/23] i965/disasm: Use Gen6+ SFID case labels.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:33:56PM -0700, Kenneth Graunke wrote:
> Most developers will recognize the Gen6+ SFID names more quickly than
> the Gen4-5 ones.  Given that they're the same values, just use the new
> names.
> 
> Signed-off-by: Kenneth Graunke 

Reviewed-by: Kristian Høgsberg 

> ---
>  src/mesa/drivers/dri/i965/brw_disasm.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index e2f2fd8..b739cc8 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -1310,7 +1310,8 @@ brw_disassemble_inst(FILE *file, struct brw_context 
> *brw, brw_inst *inst,
>  string(file, ")");
>   }
>   break;
> -  case BRW_SFID_DATAPORT_READ:
> +  case GEN6_SFID_DATAPORT_SAMPLER_CACHE:
> + /* aka BRW_SFID_DATAPORT_READ on Gen4-5 */
>   if (brw->gen >= 6) {
>  format(file, " (%d, %d, %d, %d)",
> brw_inst_binding_table_index(brw, inst),
> @@ -1325,7 +1326,8 @@ brw_disassemble_inst(FILE *file, struct brw_context 
> *brw, brw_inst *inst,
>   }
>   break;
>  
> -  case BRW_SFID_DATAPORT_WRITE:
> +  case GEN6_SFID_DATAPORT_RENDER_CACHE:
> + /* aka BRW_SFID_DATAPORT_WRITE on Gen4-5 */
>   if (brw->gen >= 7) {
>  format(file, " (");
>  
> -- 
> 2.0.0
> 
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Re: [Mesa-dev] [PATCH 16/23] i965/disasm: "Handle" Gen8+ HF/DF immediate cases.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:33:55PM -0700, Kenneth Graunke wrote:
> We should print something properly, but I'm not sure how to properly
> print an HF, and we don't have any DFs today to test with.
> 
> This is at least better than the current Gen8 disassembler, which would
> simply assert fail.
> 
> Signed-off-by: Kenneth Graunke 

Reviewed-by: Kristian Høgsberg 

> ---
>  src/mesa/drivers/dri/i965/brw_disasm.c | 7 +++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index 54435be..e2f2fd8 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -981,6 +981,13 @@ imm(FILE *file, struct brw_context *brw, unsigned type, 
> brw_inst *inst)
>break;
> case BRW_HW_REG_TYPE_F:
>format(file, "%-gF", brw_inst_imm_f(brw, inst));
> +  break;
> +   case GEN8_HW_REG_IMM_TYPE_DF:
> +  string(file, "Double IMM");
> +  break;
> +   case GEN8_HW_REG_IMM_TYPE_HF:
> +  string(file, "Half Float IMM");
> +  break;
> }
> return 0;
>  }
> -- 
> 2.0.0
> 
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Re: [Mesa-dev] [PATCH 2/4] i965/vec4: Improve CSE performance by expiring some available expressions.

[Ian Romanick]

On 06/25/2014 02:12 PM, Matt Turner wrote:
> Port of commit 5daf867f to the vec4 code.
> ---
>  src/mesa/drivers/dri/i965/brw_vec4_cse.cpp | 20 
>  1 file changed, 20 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
> index 33c7430..67fc58a 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
> @@ -128,6 +128,7 @@ vec4_visitor::opt_cse_local(bblock_t *block, exec_list 
> *aeb)
>  
> void *cse_ctx = ralloc_context(NULL);
>  
> +   int ip = block->start_ip;
> for (vec4_instruction *inst = (vec4_instruction *)block->start;
>  inst != block->end->next;
>  inst = (vec4_instruction *) inst->next) {
> @@ -198,6 +199,8 @@ vec4_visitor::opt_cse_local(bblock_t *block, exec_list 
> *aeb)
>   aeb_entry *entry = (aeb_entry *)entry_node;
>  
>   for (int i = 0; i < 3; i++) {
> +src_reg *src = &entry->generator->src[i];
> +
>  /* Kill all AEB entries that use the destination we just
>   * overwrote.
>   */
> @@ -207,8 +210,23 @@ vec4_visitor::opt_cse_local(bblock_t *block, exec_list 
> *aeb)
> ralloc_free(entry);
> break;
>  }
> +
> +/* Kill any AEB entries using registers that don't get reused any
> + * more -- a sure sign they'll fail operands_match().
> + */
> +int last_reg_use = MAX2(MAX2(virtual_grf_end[src->reg * 4 + 0],
> + virtual_grf_end[src->reg * 4 + 1]),
> +MAX2(virtual_grf_end[src->reg * 4 + 2],
> + virtual_grf_end[src->reg * 4 + 3]));
> +if (src->file == GRF && last_reg_use < ip) {
> +   entry->remove();
> +   ralloc_free(entry);
> +   break;
> +}
>   }
>}
> +
> +  ip++;
> }
>  
> ralloc_free(cse_ctx);
> @@ -224,6 +242,8 @@ vec4_visitor::opt_cse()
>  {
> bool progress = false;
>  
> +   calculate_live_intervals();
> +
> cfg_t cfg(&instructions);

Does this also need a rebase on other patches you have pending?

>  
> for (int b = 0; b < cfg.num_blocks; b++) {
> 

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Re: [Mesa-dev] [PATCH 1/4] i965/vec4: Add basic common subexpression elimination.

[Ian Romanick]

On 06/25/2014 02:12 PM, Matt Turner wrote:
> From: Kenneth Graunke 
> 
> [mattst88]: Modified to perform CSE on instructions with
> the same writemask. Offered no improvement before.
> 
> total instructions in shared programs: 1995633 -> 1995185 (-0.02%)
> instructions in affected programs: 14410 -> 13962 (-3.11%)
> 
> Reviewed-by: Matt Turner 
> Signed-off-by: Kenneth Graunke 
> ---
>  src/mesa/drivers/dri/i965/Makefile.sources |   1 +
>  src/mesa/drivers/dri/i965/brw_vec4.cpp |   1 +
>  src/mesa/drivers/dri/i965/brw_vec4.h   |   2 +
>  src/mesa/drivers/dri/i965/brw_vec4_cse.cpp | 237 
> +
>  4 files changed, 241 insertions(+)
>  create mode 100644 src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
> 
> diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
> b/src/mesa/drivers/dri/i965/Makefile.sources
> index 2570059..8f1d272 100644
> --- a/src/mesa/drivers/dri/i965/Makefile.sources
> +++ b/src/mesa/drivers/dri/i965/Makefile.sources
> @@ -102,6 +102,7 @@ i965_FILES = \
>   brw_util.c \
>   brw_vec4.cpp \
>   brw_vec4_copy_propagation.cpp \
> + brw_vec4_cse.cpp \
>   brw_vec4_generator.cpp \
>   brw_vec4_gs.c \
>   brw_vec4_gs_visitor.cpp \
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> index 24903f9..0d57399 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> @@ -1747,6 +1747,7 @@ vec4_visitor::run()
>progress = dead_control_flow_eliminate(this) || progress;
>progress = opt_copy_propagation() || progress;
>progress = opt_algebraic() || progress;
> +  progress = opt_cse() || progress;
>progress = opt_register_coalesce() || progress;
> } while (progress);
>  
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
> b/src/mesa/drivers/dri/i965/brw_vec4.h
> index 366198c..4a8eabb 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4.h
> +++ b/src/mesa/drivers/dri/i965/brw_vec4.h
> @@ -426,6 +426,8 @@ public:
> bool dead_code_eliminate();
> bool virtual_grf_interferes(int a, int b);
> bool opt_copy_propagation();
> +   bool opt_cse_local(bblock_t *, exec_list *);
> +   bool opt_cse();
> bool opt_algebraic();
> bool opt_register_coalesce();
> void opt_set_dependency_control();
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
> new file mode 100644
> index 000..33c7430
> --- /dev/null
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
> @@ -0,0 +1,237 @@
> +/*
> + * Copyright © 2012, 2013, 2014 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "brw_vec4.h"
> +#include "brw_cfg.h"
> +
> +using namespace brw;
> +
> +/** @file brw_vec4_cse.cpp
> + *
> + * Support for local common subexpression elimination.
> + *
> + * See Muchnick's Advanced Compiler Design and Implementation, section
> + * 13.1 (p378).
> + */
> +
> +namespace {
> +struct aeb_entry : public exec_node {
> +   /** The instruction that generates the expression value. */
> +   vec4_instruction *generator;
> +
> +   /** The temporary where the value is stored. */
> +   src_reg tmp;
> +};
> +}
> +
> +static bool
> +is_expression(const vec4_instruction *const inst)

is_expression seems like a weird name for this.  It's not obvious to a
noob what this is doing.

> +{
> +   switch (inst->opcode) {
> +   case BRW_OPCODE_SEL:
> +   case BRW_OPCODE_NOT:
> +   case BRW_OPCODE_AND:
> +   case BRW_OPCODE_OR:
> +   case BRW_OPCODE_XOR:
> +   case BRW_OPCODE_SHR:
> +   case BRW_OPCODE_SHL:
> +   case BRW_OPCODE_ASR:
> +   case BRW_OPCODE_ADD:
> +   case BRW_OPCODE_MUL:
> +   case BRW_OPCODE_FRC:
> +   case BRW_OPCODE_RNDU:
> +   case BRW_OPCODE_RNDD:
> +   case BRW_OPCODE_RNDE:
> +   case BRW_OPCODE_RNDZ:
> +   case BRW_OPCODE_LINE:

Re: [Mesa-dev] [PATCH 2/3] i965: Use unreachable() instead of unconditional assert().

[Ian Romanick]

On 06/30/2014 11:20 AM, Philipp Klaus Krause wrote:
> On 30.06.2014 20:03, Matt Turner wrote:
>> On Mon, Jun 30, 2014 at 10:37 AM, Ian Romanick  wrote:
>>> In the cases where a return (with a value) is removed, I'm afraid static
>>> analysis tools will start to complain.  I'll be surprised if Klocwork
>>> understands (or trusts) GCC __builtin_unreachable decorations.
>>
>> Good catch. I didn't think about this.
>>
>> I did a little bit of searching and discovered this page:
>>
>> http://www.klocwork.com/products/documentation/current/Compiler_attributes_analyzed_by_Klocwork
>>
>> which fortunately says that Klocwork recognizes gcc's
>> __attribute__((noreturn)), so I feel relatively confident that
>> Klocwork recognizes __builtin_unreachable as well.
>>
>> If it doesn't and we get warnings from Klocwork, we can easily make
>> the unreachable() macro expand to a static inline function marked with
>> __attribute__((noreturn)).
> 
> Why use gcc-specific stuff instead of the standard _Noreturn/noreturn?

As far as I can see, _noreturn is a C11 feature... we can't even count
on C99 features in core Mesa yet, sooo... yeah. :) If we start to use
any sort of noreturn decoration, we should wrap it in a macro that
expands something the compiler can support.

> Philipp
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Re: [Mesa-dev] [PATCH 2/3] i965: Use unreachable() instead of unconditional assert().

[Matt Turner]

On Mon, Jun 30, 2014 at 11:20 AM, Philipp Klaus Krause  wrote:
> On 30.06.2014 20:03, Matt Turner wrote:
>> On Mon, Jun 30, 2014 at 10:37 AM, Ian Romanick  wrote:
>>> In the cases where a return (with a value) is removed, I'm afraid static
>>> analysis tools will start to complain.  I'll be surprised if Klocwork
>>> understands (or trusts) GCC __builtin_unreachable decorations.
>>
>> Good catch. I didn't think about this.
>>
>> I did a little bit of searching and discovered this page:
>>
>> http://www.klocwork.com/products/documentation/current/Compiler_attributes_analyzed_by_Klocwork
>>
>> which fortunately says that Klocwork recognizes gcc's
>> __attribute__((noreturn)), so I feel relatively confident that
>> Klocwork recognizes __builtin_unreachable as well.
>>
>> If it doesn't and we get warnings from Klocwork, we can easily make
>> the unreachable() macro expand to a static inline function marked with
>> __attribute__((noreturn)).
>
> Why use gcc-specific stuff instead of the standard _Noreturn/noreturn?

We're limited to using C89 in core Mesa by MSVC users.
_Noreturn/noreturn appears to be a C11 feature.
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Re: [Mesa-dev] [PATCH 2/3] i965: Use unreachable() instead of unconditional assert().

[Ian Romanick]

On 06/30/2014 11:03 AM, Matt Turner wrote:
> On Mon, Jun 30, 2014 at 10:37 AM, Ian Romanick  wrote:
>> In the cases where a return (with a value) is removed, I'm afraid static
>> analysis tools will start to complain.  I'll be surprised if Klocwork
>> understands (or trusts) GCC __builtin_unreachable decorations.
> 
> Good catch. I didn't think about this.
> 
> I did a little bit of searching and discovered this page:
> 
> http://www.klocwork.com/products/documentation/current/Compiler_attributes_analyzed_by_Klocwork
> 
> which fortunately says that Klocwork recognizes gcc's
> __attribute__((noreturn)), so I feel relatively confident that
> Klocwork recognizes __builtin_unreachable as well.
> 
> If it doesn't and we get warnings from Klocwork, we can easily make
> the unreachable() macro expand to a static inline function marked with
> __attribute__((noreturn)).

Ah... okay.  Then I'm fine with this patch as-is.

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Re: [Mesa-dev] [PATCH 4/5] texstore: Add a generic implementation of GL_ARB_clear_texture

[Jason Ekstrand]

On Fri, Jun 13, 2014 at 5:59 PM, Neil Roberts  wrote:

> Adds an implmentation of the ClearTexSubImage driver entry point that just
> maps the texture and writes the values in. This should work as a reliable
> fallback on any driver.
> ---
>  src/mesa/drivers/common/driverfuncs.c |  2 +
>  src/mesa/main/texstore.c  | 70
> +++
>  src/mesa/main/texstore.h  |  7 
>  3 files changed, 79 insertions(+)
>
> diff --git a/src/mesa/drivers/common/driverfuncs.c
> b/src/mesa/drivers/common/driverfuncs.c
> index ee8b390..34b6fef 100644
> --- a/src/mesa/drivers/common/driverfuncs.c
> +++ b/src/mesa/drivers/common/driverfuncs.c
> @@ -95,6 +95,7 @@ _mesa_init_driver_functions(struct dd_function_table
> *driver)
> driver->TexImage = _mesa_store_teximage;
> driver->TexSubImage = _mesa_store_texsubimage;
> driver->GetTexImage = _mesa_meta_GetTexImage;
> +   driver->ClearTexSubImage = _mesa_store_cleartexsubimage;
> driver->CopyTexSubImage = _mesa_meta_CopyTexSubImage;
> driver->GenerateMipmap = _mesa_meta_GenerateMipmap;
> driver->TestProxyTexImage = _mesa_test_proxy_teximage;
> @@ -333,4 +334,5 @@ _mesa_init_driver_state(struct gl_context *ctx)
>  void
>  _mesa_init_driver_extensions(struct gl_context *ctx)
>  {
> +   ctx->Extensions.ARB_clear_texture = GL_TRUE;
>  }
> diff --git a/src/mesa/main/texstore.c b/src/mesa/main/texstore.c
> index cb81f3f..9c90492 100644
> --- a/src/mesa/main/texstore.c
> +++ b/src/mesa/main/texstore.c
> @@ -4157,6 +4157,76 @@ _mesa_store_texsubimage(struct gl_context *ctx,
> GLuint dims,
>   format, type, pixels, packing, "glTexSubImage");
>  }
>
> +static void
> +clear_image_to_zero(GLubyte *dstMap, GLint dstRowStride,
> +GLsizei width, GLsizei height,
> +GLsizei clearValueSize)
> +{
> +   while (height-- > 0) {
> +  memset(dstMap, 0, clearValueSize * width);
> +  dstMap += dstRowStride;
> +   }
> +}
>

Technically, this should always work, but you might want to throw in a
comment about floating-point textures.

Other than that, looks good to me. (I'll second Ilia's MS comment though.)
--Jason Ekstrand


> +
> +static void
> +clear_image_to_value(GLubyte *dstMap, GLint dstRowStride,
> + GLsizei width, GLsizei height,
> + const GLvoid *clearValue,
> + GLsizei clearValueSize)
> +{
> +   GLsizei x;
> +
> +   while (height-- > 0) {
> +  for (x = 0; x < width; x++) {
> + memcpy(dstMap, clearValue, clearValueSize);
> + dstMap += clearValueSize;
> +  }
> +  dstMap += dstRowStride - clearValueSize * width;
> +   }
> +}
> +
> +/*
> + * Fallback for Driver.ClearTexSubImage().
> + */
> +void
> +_mesa_store_cleartexsubimage(struct gl_context *ctx,
> + struct gl_texture_image *texImage,
> + GLint xoffset, GLint yoffset, GLint zoffset,
> + GLsizei width, GLsizei height, GLsizei depth,
> + const GLvoid *clearValue)
> +{
> +   GLubyte *dstMap;
> +   GLint dstRowStride;
> +   GLsizeiptr clearValueSize;
> +   GLsizei z;
> +
> +   clearValueSize = _mesa_get_format_bytes(texImage->TexFormat);
> +
> +   for (z = 0; z < depth; z++) {
> +  ctx->Driver.MapTextureImage(ctx, texImage,
> +  z + zoffset, xoffset, yoffset,
> +  width, height,
> +  GL_MAP_WRITE_BIT,
> +  &dstMap, &dstRowStride);
> +  if (dstMap == NULL) {
> + _mesa_error(ctx, GL_OUT_OF_MEMORY, "glClearTex*Image");
> + return;
> +  }
> +
> +  if (clearValue) {
> + clear_image_to_value(dstMap, dstRowStride,
> +  width, height,
> +  clearValue,
> +  clearValueSize);
> +  } else {
> + clear_image_to_zero(dstMap, dstRowStride,
> + width, height,
> + clearValueSize);
> +  }
> +
> +  ctx->Driver.UnmapTextureImage(ctx, texImage, z + zoffset);
> +   }
> +}
>
>  /**
>   * Fallback for Driver.CompressedTexImage()
> diff --git a/src/mesa/main/texstore.h b/src/mesa/main/texstore.h
> index c4cfffd..dd1e1d0 100644
> --- a/src/mesa/main/texstore.h
> +++ b/src/mesa/main/texstore.h
> @@ -118,6 +118,13 @@ _mesa_store_texsubimage(struct gl_context *ctx,
> GLuint dims,
>
>
>  extern void
> +_mesa_store_cleartexsubimage(struct gl_context *ctx,
> + struct gl_texture_image *texImage,
> + GLint xoffset, GLint yoffset, GLint zoffset,
> + GLsizei width, GLsizei height, GLsizei depth,
> + const GLvoid *clearValue);
> +
> +extern void
>  _mesa_store_compressed_teximage(struct gl_context *ctx, GLuint dims,
>   

Re: [Mesa-dev] [PATCH 01/16] glsl: Add typed foreach_in_list/_reverse macros.

[Ian Romanick]

Patches 1 through 10, 12, 13, and 16 are

Reviewed-by: Ian Romanick 

Patches 14 and 15 are

Acked-by: Ian Romanick 

We're still discussing patch 11 on IRC. :)

On 06/25/2014 11:51 AM, Matt Turner wrote:
> ---
>  src/glsl/list.h | 10 ++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/src/glsl/list.h b/src/glsl/list.h
> index 576bc14..914ce96 100644
> --- a/src/glsl/list.h
> +++ b/src/glsl/list.h
> @@ -573,6 +573,16 @@ inline void exec_node::insert_before(exec_list *before)
>   ; (__node)->next != NULL\
>   ; (__node) = (__node)->next)
>  
> +#define foreach_in_list(__type, __inst, __list)  \
> +   for (__type *(__inst) = (__type *)(__list)->head; \
> +!(__inst)->is_tail_sentinel();   \
> +(__inst) = (__type *)(__inst)->next)
> +
> +#define foreach_in_list_reverse(__type, __inst, __list) \
> +   for (__type *(__inst) = (__type *)(__list)->head;\
> +!(__inst)->is_head_sentinel();  \
> +(__inst) = (__type *)(__inst)->prev)
> +
>  /**
>   * Iterate through two lists at once.  Stops at the end of the shorter list.
>   *
> 

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Re: [Mesa-dev] [PATCH 2/5] mesa/main: Add generic bits of ARB_clear_texture implementation

[Jason Ekstrand]

On Fri, Jun 13, 2014 at 5:59 PM, Neil Roberts  wrote:

> This adds the driver entry point for glClearTexSubImage and fills in the
> _mesa_ClearTexImage and _mesa_ClearTexSubImage functions that call it.
> ---
>  src/mesa/main/dd.h   |  14 +++
>  src/mesa/main/teximage.c | 241
> ++-
>  src/mesa/main/teximage.h |  12 +++
>  3 files changed, 266 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/main/dd.h b/src/mesa/main/dd.h
> index 633ea2c..8976535 100644
> --- a/src/mesa/main/dd.h
> +++ b/src/mesa/main/dd.h
> @@ -239,6 +239,20 @@ struct dd_function_table {
>  struct gl_texture_image *texImage );
>
> /**
> +* Called by glClearTex[Sub]Image
> +*
> +* Clears a rectangular region of the image to a given value. The
> +* clearValue argument is either NULL or points to a single texel to
> use as
> +* the clear value in the same internal format as the texture image.
> If it
> +* is NULL then the texture should be cleared to zeroes.
> +*/
> +   void (*ClearTexSubImage)(struct gl_context *ctx,
> +struct gl_texture_image *texImage,
> +GLint xoffset, GLint yoffset, GLint zoffset,
> +GLsizei width, GLsizei height, GLsizei depth,
> +const GLvoid *clearValue);
> +
> +   /**
>  * Called by glCopyTex[Sub]Image[123]D().
>  *
>  * This function should copy a rectangular region in the rb to a single
> diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
> index a893c70..d5baac8 100644
> --- a/src/mesa/main/teximage.c
> +++ b/src/mesa/main/teximage.c
> @@ -51,6 +51,7 @@
>  #include "textureview.h"
>  #include "mtypes.h"
>  #include "glformats.h"
> +#include "texstore.h"
>
>
>  /**
> @@ -3848,20 +3849,259 @@ _mesa_CopyTexSubImage3D( GLenum target, GLint
> level,
> x, y, width, height);
>  }
>
> +static bool
> +clear_tex_image(struct gl_context *ctx,
> +const char *function,
> +struct gl_texture_image *texImage, GLint level,
> +GLint xoffset, GLint yoffset, GLint zoffset,
> +GLsizei width, GLsizei height, GLsizei depth,
> +GLenum format, GLenum type,
> +const void *data)
> +{
> +   struct gl_texture_object *texObj = texImage->TexObject;
> +   static const GLubyte zeroData[MAX_PIXEL_BYTES];
> +   GLubyte clearValue[MAX_PIXEL_BYTES];
> +   GLubyte *clearValuePtr = clearValue;
> +   GLenum internalFormat = texImage->InternalFormat;
> +   GLenum err;
> +
> +   if (texObj->Target == GL_TEXTURE_BUFFER) {
> +  _mesa_error(ctx, GL_INVALID_OPERATION,
> +  "%s(buffer texture)", function);
> +  return false;
> +   }
> +
> +   if (_mesa_is_compressed_format(ctx, internalFormat)) {
> +  _mesa_error(ctx, GL_INVALID_OPERATION,
> +  "%s(compressed texture)", function);
> +  return false;
> +   }
> +
> +   err = _mesa_error_check_format_and_type(ctx, format, type);
> +   if (err != GL_NO_ERROR) {
> +  _mesa_error(ctx, err,
> +  "%s(incompatible format = %s, type = %s)",
> +  function,
> +  _mesa_lookup_enum_by_nr(format),
> +  _mesa_lookup_enum_by_nr(type));
> +  return false;
> +   }
> +
> +   /* make sure internal format and format basically agree */
> +   if (!texture_formats_agree(internalFormat, format)) {
> +  _mesa_error(ctx, GL_INVALID_OPERATION,
> +  "%s(incompatible internalFormat = %s, format = %s)",
> +  function,
> +  _mesa_lookup_enum_by_nr(internalFormat),
> +  _mesa_lookup_enum_by_nr(format));
> +  return false;
> +   }
> +
> +   if (ctx->Version >= 30 || ctx->Extensions.EXT_texture_integer) {
> +  /* both source and dest must be integer-valued, or neither */
> +  if (_mesa_is_format_integer_color(texImage->TexFormat) !=
> +  _mesa_is_enum_format_integer(format)) {
> + _mesa_error(ctx, GL_INVALID_OPERATION,
> + "%s(integer/non-integer format mismatch)",
> + function);
> + return false;
> +  }
> +   }
> +
> +   if (!_mesa_texstore(ctx,
> +   1, /* dims */
> +   texImage->_BaseFormat,
> +   texImage->TexFormat,
> +   0, /* dstRowStride */
> +   &clearValuePtr,
> +   1, 1, 1, /* srcWidth/Height/Depth */
> +   format, type,
> +   data ? data : zeroData,
> +   &ctx->DefaultPacking)) {
> +  _mesa_error(ctx, GL_INVALID_OPERATION, "%s(invalid format)",
> function);
> +  return false;
> +   }
> +
> +   ctx->Driver.ClearTexSubImage(ctx,
> +texImage,
> +xoffset, yoffset, zoffse

Re: [Mesa-dev] [PATCH 2/3] i965: Use unreachable() instead of unconditional assert().

[Philipp Klaus Krause]

On 30.06.2014 20:03, Matt Turner wrote:
> On Mon, Jun 30, 2014 at 10:37 AM, Ian Romanick  wrote:
>> In the cases where a return (with a value) is removed, I'm afraid static
>> analysis tools will start to complain.  I'll be surprised if Klocwork
>> understands (or trusts) GCC __builtin_unreachable decorations.
> 
> Good catch. I didn't think about this.
> 
> I did a little bit of searching and discovered this page:
> 
> http://www.klocwork.com/products/documentation/current/Compiler_attributes_analyzed_by_Klocwork
> 
> which fortunately says that Klocwork recognizes gcc's
> __attribute__((noreturn)), so I feel relatively confident that
> Klocwork recognizes __builtin_unreachable as well.
> 
> If it doesn't and we get warnings from Klocwork, we can easily make
> the unreachable() macro expand to a static inline function marked with
> __attribute__((noreturn)).

Why use gcc-specific stuff instead of the standard _Noreturn/noreturn?

Philipp

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Re: [Mesa-dev] [PATCH 12/23] i965/disasm: Actually disassemble Gen7+ URB opcodes.

[Kenneth Graunke]

On Monday, June 30, 2014 10:20:13 AM Kristian Høgsberg wrote:
> On Sat, Jun 28, 2014 at 09:33:51PM -0700, Kenneth Graunke wrote:
> > I never bothered implementing the disassembler for Gen7+ URB opcodes, so
> > we were just disassembling them as Ironlake/Sandybridge ones.  This
> > looked pretty bad when running Paul's GS EndPrimitive tests, as the
> > "write OWord" message was decoded at ff_sync, which doesn't exist.
> > 
> > Signed-off-by: Kenneth Graunke 
> > ---
> > 
> >  src/mesa/drivers/dri/i965/brw_disasm.c | 22 +++---
> >  1 file changed, 19 insertions(+), 3 deletions(-)
> > 
> > diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c
> > b/src/mesa/drivers/dri/i965/brw_disasm.c index 14cb687..4e75cc7 100644
> > --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> > +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> > @@ -478,11 +478,24 @@ static const char *const math_precision[2] = {
> > 
> > [1] = "partial_precision"
> >  
> >  };
> > 
> > -static const char *const urb_opcode[2] = {
> > +static const char *const gen5_urb_opcode[] = {
> > 
> > [0] = "urb_write",
> > [1] = "ff_sync",
> >  
> >  };
> > 
> > +static const char *const gen7_urb_opcode[] = {
> > +   [0] = "write HWord",
> > +   [1] = "write OWord",
> > +   [2] = "read HWord",
> > +   [3] = "read OWord",
> > +   [4] = "atomic mov",  /* Gen7+ */
> > +   [5] = "atomic inc",  /* Gen7+ */
> > +   [6] = "atomic add",  /* Gen8+ */
> > +   [7] = "SIMD8 write", /* Gen8+ */
> > +   [8] = "SIMD8 read",  /* Gen8+ */
> > +   /* [9-15] - reserved */
> > +};
> 
> Do we have defines for these opcodes?  They stand out a bit now that
> all the rest are using opcode names in the array initializer.
> 
> Either way, not worth blocking this disasm improvement on,
> 
> Reviewed-by: Kristian Høgsberg 

Only for 0 and 1 (write HWord/OWord).  The rest aren't used yet, so we never 
actually added #defines.

--Ken

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Re: [Mesa-dev] [PATCH 2/3] i965: Use unreachable() instead of unconditional assert().

[Matt Turner]

On Mon, Jun 30, 2014 at 10:37 AM, Ian Romanick  wrote:
> In the cases where a return (with a value) is removed, I'm afraid static
> analysis tools will start to complain.  I'll be surprised if Klocwork
> understands (or trusts) GCC __builtin_unreachable decorations.

Good catch. I didn't think about this.

I did a little bit of searching and discovered this page:

http://www.klocwork.com/products/documentation/current/Compiler_attributes_analyzed_by_Klocwork

which fortunately says that Klocwork recognizes gcc's
__attribute__((noreturn)), so I feel relatively confident that
Klocwork recognizes __builtin_unreachable as well.

If it doesn't and we get warnings from Klocwork, we can easily make
the unreachable() macro expand to a static inline function marked with
__attribute__((noreturn)).
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Re: [Mesa-dev] [PATCH 3/4] i965/fs: Mark predicated PLN instructions with dependency hints.

[Matt Turner]

On Mon, Jun 30, 2014 at 10:29 AM, Ian Romanick  wrote:
> On 06/29/2014 11:18 PM, Matt Turner wrote:
>> To implement the unlit_centroid_workaround, previously we emitted
>>
>>(+f0) pln(8) g20<1>F g16.4<0,1,0>F g4<8,8,1>F { align1 1Q };
>>(-f0) pln(8) g20<1>F g16.4<0,1,0>F g2<8,8,1>F { align1 1Q };
>>
>> where the flag register contains the channel enable bits from g0.
>>
>> Since the predicates are complementary, the pair of pln instructions
>> write to non-overlapping components of the destination, which is the
>> case that the dependency control hints are designed for.
>>
>> Typically setting dependency control hints on predicated instructions
>> isn't safe (if an instruction doesn't execute due to the predicate, it
>> won't update the scoreboard, leaving it in a bad state) but since we
>> must have at least one channel executing (i.e., +f0 is true for some
>> channel) by virtue of the fact that the thread is running, we can put
>> the +f0 pln instruction last and set the hints:
>>
>>(-f0) pln(8) g20<1>F g16.4<0,1,0>F g2<8,8,1>F { align1 NoDDClr 1Q };
>>(+f0) pln(8) g20<1>F g16.4<0,1,0>F g4<8,8,1>F { align1 NoDDChk 1Q };
>
> And there's no chance of instruction scheduling ever putting something
> between?  Seems unlikely, but... would be bad.

It can, and does, actually:

(-f0) pln(8) g38<1>F g24.4<0,1,0>F g2<8,8,1>F { NoDDClr };
(-f0) pln(8) g39<1>F g25.4<0,1,0>F g2<8,8,1>F { NoDDClr };
(-f0) pln(8) g42<1>F g26.4<0,1,0>F g2<8,8,1>F { NoDDClr };
(-f0) pln(8) g35<1>F g27.4<0,1,0>F g2<8,8,1>F { NoDDClr };
(+f0) pln(8) g38<1>F g24.4<0,1,0>F g4<8,8,1>F { NoDDChk };
(+f0) pln(8) g39<1>F g25.4<0,1,0>F g4<8,8,1>F { NoDDChk };
(+f0) pln(8) g42<1>F g26.4<0,1,0>F g4<8,8,1>F { NoDDChk };
(+f0) pln(8) g35<1>F g27.4<0,1,0>F g4<8,8,1>F { NoDDChk };

which is safe since the dependency controls are per destination register.
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Re: [Mesa-dev] [PATCH 3/3] i965/vec4: Remove useless conditionals.

[Matt Turner]

On Mon, Jun 30, 2014 at 10:32 AM, Ian Romanick  wrote:
> On 06/30/2014 10:11 AM, Matt Turner wrote:
>> Setting a couple of bits is the same cost or less as conditionally
>> setting a couple of bits.
>> ---
>>  src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 9 +++--
>>  1 file changed, 3 insertions(+), 6 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp 
>> b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
>> index 8f5b205..509c32c 100644
>> --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
>> @@ -1266,12 +1266,9 @@ vec4_generator::generate_code(exec_list *instructions)
>>
>>   brw_inst *last = &p->store[pre_emit_nr_insn];
>>
>> - if (inst->conditional_mod)
>> -brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
>> - if (inst->no_dd_clear)
>> -brw_inst_set_no_dd_clear(brw, last, true);
>> - if (inst->no_dd_check)
>> -brw_inst_set_no_dd_check(brw, last, true);
>> + brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
>> + brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
>> + brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
>
> The old code will only set the bits.  The new code might also clear the
> bits, right?  Is that potentially a problem?

Ah, the missing piece of information here is that the bits are already
zero when this code is called.
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Re: [Mesa-dev] [PATCH v2 4/9] gallium: add a cap for max vertex streams

[Ilia Mirkin]

On Sat, Jun 28, 2014 at 8:44 AM, Roland Scheidegger  wrote:
> 3-4 look alright to me.

Does this count as a R-b? Looks like the core changes have landed, so
I'm going to be looking to push all this out ~tomorrow.

> I wonder if the cap name is actually "correct"
> or if it should have some STREAM_OUT in it. But doesn't really matter I
> guess.

It doesn't really matter to me... same as with the index thing, as
long as everyone agrees, I'm happy with whatever.

It does seem like it's specific to vertex stream quantities, not
stream-out though. With AMD_tf4, you can also rasterize multpile
vertex streams, which would also be subject to the same limit. But
it's all tied pretty closely together -- e.g. the extension is
AMD_transform_feedback4, not AMD_fragment_vertex_streams or something.

> Longer term I think we might want to merge some caps. Everybody
> (supporting stream out) will either support 1 or 4 streams along with
> other functionality anyway.

Agreed. And I like Marek's suggestion of using the GLSL level. Until
then, this is OK though?

>
> Roland
>
>
> Am 28.06.2014 05:50, schrieb Ilia Mirkin:
>> Signed-off-by: Ilia Mirkin 
>> Reviewed-by: Marek Olšák 
>> Reviewed-by: Brian Paul 
>> ---
>>
>> v1 -> v2:
>>  - add an assert to make sure it's <= 4
>>  - add a note in docs about expected values
>>
>>  src/gallium/docs/source/screen.rst   | 3 +++
>>  src/gallium/drivers/freedreno/freedreno_screen.c | 1 +
>>  src/gallium/drivers/i915/i915_screen.c   | 1 +
>>  src/gallium/drivers/ilo/ilo_screen.c | 1 +
>>  src/gallium/drivers/llvmpipe/lp_screen.c | 2 ++
>>  src/gallium/drivers/nouveau/nv30/nv30_screen.c   | 1 +
>>  src/gallium/drivers/nouveau/nv50/nv50_screen.c   | 2 ++
>>  src/gallium/drivers/nouveau/nvc0/nvc0_screen.c   | 2 ++
>>  src/gallium/drivers/r300/r300_screen.c   | 1 +
>>  src/gallium/drivers/r600/r600_pipe.c | 2 ++
>>  src/gallium/drivers/radeonsi/si_pipe.c   | 2 ++
>>  src/gallium/drivers/softpipe/sp_screen.c | 2 ++
>>  src/gallium/drivers/svga/svga_screen.c   | 1 +
>>  src/gallium/include/pipe/p_defines.h | 3 ++-
>>  src/mesa/state_tracker/st_extensions.c   | 5 +
>>  15 files changed, 28 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/gallium/docs/source/screen.rst 
>> b/src/gallium/docs/source/screen.rst
>> index 1a80b04..5e01df5 100644
>> --- a/src/gallium/docs/source/screen.rst
>> +++ b/src/gallium/docs/source/screen.rst
>> @@ -205,6 +205,9 @@ The integer capabilities:
>>  * ``PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION``: Whether
>>TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION is supported, which disables 
>> clipping
>>and viewport transformation.
>> +* ``PIPE_CAP_MAX_VERTEX_STREAMS``: The maximum number of vertex streams
>> +  supported by the geometry shader. If stream-out is supported, this should 
>> be
>> +  at least 1. If stream-out is not supported, this should be 0.
>>
>>
>>  .. _pipe_capf:
>> diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c 
>> b/src/gallium/drivers/freedreno/freedreno_screen.c
>> index e7a185d..9200962 100644
>> --- a/src/gallium/drivers/freedreno/freedreno_screen.c
>> +++ b/src/gallium/drivers/freedreno/freedreno_screen.c
>> @@ -227,6 +227,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum 
>> pipe_cap param)
>>   /* Geometry shader output, unsupported. */
>>   case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
>>   case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
>> + case PIPE_CAP_MAX_VERTEX_STREAMS:
>>   return 0;
>>
>>   /* Texturing. */
>> diff --git a/src/gallium/drivers/i915/i915_screen.c 
>> b/src/gallium/drivers/i915/i915_screen.c
>> index 79d8659..036f706 100644
>> --- a/src/gallium/drivers/i915/i915_screen.c
>> +++ b/src/gallium/drivers/i915/i915_screen.c
>> @@ -270,6 +270,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap 
>> cap)
>> /* Geometry shader output, unsupported. */
>> case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
>> case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
>> +   case PIPE_CAP_MAX_VERTEX_STREAMS:
>>return 0;
>>
>> /* Fragment coordinate conventions. */
>> diff --git a/src/gallium/drivers/ilo/ilo_screen.c 
>> b/src/gallium/drivers/ilo/ilo_screen.c
>> index b08ae20..8f8e152 100644
>> --- a/src/gallium/drivers/ilo/ilo_screen.c
>> +++ b/src/gallium/drivers/ilo/ilo_screen.c
>> @@ -375,6 +375,7 @@ ilo_get_param(struct pipe_screen *screen, enum pipe_cap 
>> param)
>>return ILO_MAX_SO_BINDINGS;
>> case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
>> case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
>> +   case PIPE_CAP_MAX_VERTEX_STREAMS:
>>return 0;
>> case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
>>if (is->dev.gen >= ILO_GEN(7))
>> diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c 
>> b/src/gallium/drivers/llvmpipe/lp_screen.c
>> index a6b712a..26ab294 100644
>> --- a/src/gallium/drivers/llvmpipe/lp_screen.c
>> ++

Re: [Mesa-dev] [PATCH 15/23] i965/disasm: Cut piles of duplicate swizzle printing.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:33:54PM -0700, Kenneth Graunke wrote:
> Making a helper function saves us from cut and pasting this four times.

Very nice,

Reviewed-by: Kristian Høgsberg 

> Signed-off-by: Kenneth Graunke 
> ---
>  src/mesa/drivers/dri/i965/brw_disasm.c | 115 
> -
>  1 file changed, 26 insertions(+), 89 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index de438cd..54435be 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -817,6 +817,28 @@ src_ia1(FILE *file,
>  }
>  
>  static int
> +src_swizzle(FILE *file, unsigned swiz)
> +{
> +   unsigned x = BRW_GET_SWZ(swiz, BRW_CHANNEL_X);
> +   unsigned y = BRW_GET_SWZ(swiz, BRW_CHANNEL_Y);
> +   unsigned z = BRW_GET_SWZ(swiz, BRW_CHANNEL_Z);
> +   unsigned w = BRW_GET_SWZ(swiz, BRW_CHANNEL_W);
> +   int err = 0;
> +
> +   if (x == y && x == z && x == w) {
> +  string(file, ".");
> +  err |= control(file, "channel select", chan_sel, x, NULL);
> +   } else if (swiz != BRW_SWIZZLE_XYZW) {
> +  string(file, ".");
> +  err |= control(file, "channel select", chan_sel, x, NULL);
> +  err |= control(file, "channel select", chan_sel, y, NULL);
> +  err |= control(file, "channel select", chan_sel, z, NULL);
> +  err |= control(file, "channel select", chan_sel, w, NULL);
> +   }
> +   return err;
> +}
> +
> +static int
>  src_da16(FILE *file,
>   const struct brw_context *brw,
>   unsigned opcode,
> @@ -848,26 +870,7 @@ src_da16(FILE *file,
> string(file, "<");
> err |= control(file, "vert stride", vert_stride, _vert_stride, NULL);
> string(file, ",4,1>");
> -   /*
> -* Three kinds of swizzle display:
> -*  identity - nothing printed
> -*  1->all   - print the single channel
> -*  1->1 - print the mapping
> -*/
> -   if (swz_x == BRW_CHANNEL_X &&
> -   swz_y == BRW_CHANNEL_Y &&
> -   swz_z == BRW_CHANNEL_Z && swz_w == BRW_CHANNEL_W) {
> -  ;
> -   } else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w) {
> -  string(file, ".");
> -  err |= control(file, "channel select", chan_sel, swz_x, NULL);
> -   } else {
> -  string(file, ".");
> -  err |= control(file, "channel select", chan_sel, swz_x, NULL);
> -  err |= control(file, "channel select", chan_sel, swz_y, NULL);
> -  err |= control(file, "channel select", chan_sel, swz_z, NULL);
> -  err |= control(file, "channel select", chan_sel, swz_w, NULL);
> -   }
> +   err |= src_swizzle(file, BRW_SWIZZLE4(swz_x, swz_y, swz_z, swz_w));
> err |= control(file, "src da16 reg type", reg_encoding, _reg_type, NULL);
> return err;
>  }
> @@ -876,11 +879,6 @@ static int
>  src0_3src(FILE *file, struct brw_context *brw, brw_inst *inst)
>  {
> int err = 0;
> -   unsigned swz = brw_inst_3src_src0_swizzle(brw, inst);
> -   unsigned swz_x = BRW_GET_SWZ(swz, BRW_CHANNEL_X);
> -   unsigned swz_y = BRW_GET_SWZ(swz, BRW_CHANNEL_Y);
> -   unsigned swz_z = BRW_GET_SWZ(swz, BRW_CHANNEL_Z);
> -   unsigned swz_w = BRW_GET_SWZ(swz, BRW_CHANNEL_W);
> unsigned src0_subreg_nr = brw_inst_3src_src0_subreg_nr(brw, inst);
>  
> err |= control(file, "negate", m_negate,
> @@ -899,24 +897,7 @@ src0_3src(FILE *file, struct brw_context *brw, brw_inst 
> *inst)
>string(file, "<4,4,1>");
> err |= control(file, "src da16 reg type", three_source_reg_encoding,
>brw_inst_3src_src_type(brw, inst), NULL);
> -   /*
> -* Three kinds of swizzle display:
> -*  identity - nothing printed
> -*  1->all   - print the single channel
> -*  1->1 - print the mapping
> -*/
> -   if (swz == BRW_SWIZZLE_XYZW) {
> -  ;
> -   } else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w) {
> -  string(file, ".");
> -  err |= control(file, "channel select", chan_sel, swz_x, NULL);
> -   } else {
> -  string(file, ".");
> -  err |= control(file, "channel select", chan_sel, swz_x, NULL);
> -  err |= control(file, "channel select", chan_sel, swz_y, NULL);
> -  err |= control(file, "channel select", chan_sel, swz_z, NULL);
> -  err |= control(file, "channel select", chan_sel, swz_w, NULL);
> -   }
> +   err |= src_swizzle(file, brw_inst_3src_src0_swizzle(brw, inst));
> return err;
>  }
>  
> @@ -924,11 +905,6 @@ static int
>  src1_3src(FILE *file, struct brw_context *brw, brw_inst *inst)
>  {
> int err = 0;
> -   unsigned swz = brw_inst_3src_src1_swizzle(brw, inst);
> -   unsigned swz_x = BRW_GET_SWZ(swz, BRW_CHANNEL_X);
> -   unsigned swz_y = BRW_GET_SWZ(swz, BRW_CHANNEL_Y);
> -   unsigned swz_z = BRW_GET_SWZ(swz, BRW_CHANNEL_Z);
> -   unsigned swz_w = BRW_GET_SWZ(swz, BRW_CHANNEL_W);
> unsigned src1_subreg_nr = brw_inst_3src_src1_subreg_nr(brw, inst);
>  
> err |= control(file, "negate", m_negate,
> @@ -947,24 +923,7 @@ src1_3src(FILE *file, struct brw_context *brw, brw_inst 
> *i

Re: [Mesa-dev] [PATCH 14/23] i965/disasm: Properly decode negate source modifiers on Broadwell.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:33:53PM -0700, Kenneth Graunke wrote:
> This is a port of Abdiel's 6f9f916b9b042a294813ab0542390846a38739da
> to brw_disasm.c.

Reviewed-by: Kristian Høgsberg 

> Signed-off-by: Kenneth Graunke 
> ---
>  src/mesa/drivers/dri/i965/brw_disasm.c | 53 
> +++---
>  1 file changed, 49 insertions(+), 4 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index 99c9bd0..de438cd 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -125,6 +125,15 @@ has_uip(struct brw_context *brw, enum opcode opcode)
>opcode == BRW_OPCODE_HALT;
>  }
>  
> +static bool
> +is_logic_instruction(unsigned opcode)
> +{
> +   return opcode == BRW_OPCODE_AND ||
> +  opcode == BRW_OPCODE_NOT ||
> +  opcode == BRW_OPCODE_OR ||
> +  opcode == BRW_OPCODE_XOR;
> +}
> +
>  const char *const conditional_modifier[16] = {
> [BRW_CONDITIONAL_NONE] = "",
> [BRW_CONDITIONAL_Z]= ".e",
> @@ -148,6 +157,8 @@ static const char *const _abs[2] = {
> [1] = "(abs)",
>  };
>  
> +static const char *const m_bitnot[2] = { "", "~" };
> +
>  static const char *const vert_stride[16] = {
> [0] = "0",
> [1] = "1",
> @@ -745,13 +756,21 @@ src_align1_region(FILE *file,
>  }
>  
>  static int
> -src_da1(FILE *file, unsigned type, unsigned _reg_file,
> +src_da1(FILE *file,
> +const struct brw_context *brw,
> +unsigned opcode,
> +unsigned type, unsigned _reg_file,
>  unsigned _vert_stride, unsigned _width, unsigned _horiz_stride,
>  unsigned reg_num, unsigned sub_reg_num, unsigned __abs,
>  unsigned _negate)
>  {
> int err = 0;
> -   err |= control(file, "negate", m_negate, _negate, NULL);
> +
> +   if (brw->gen >= 8 && is_logic_instruction(opcode))
> +  err |= control(file, "bitnot", m_bitnot, _negate, NULL);
> +   else
> +  err |= control(file, "negate", m_negate, _negate, NULL);
> +
> err |= control(file, "abs", _abs, __abs, NULL);
>  
> err |= reg(file, _reg_file, reg_num);
> @@ -766,6 +785,8 @@ src_da1(FILE *file, unsigned type, unsigned _reg_file,
>  
>  static int
>  src_ia1(FILE *file,
> +const struct brw_context *brw,
> +unsigned opcode,
>  unsigned type,
>  unsigned _reg_file,
>  int _addr_imm,
> @@ -776,7 +797,12 @@ src_ia1(FILE *file,
>  unsigned _horiz_stride, unsigned _width, unsigned _vert_stride)
>  {
> int err = 0;
> -   err |= control(file, "negate", m_negate, _negate, NULL);
> +
> +   if (brw->gen >= 8 && is_logic_instruction(opcode))
> +  err |= control(file, "bitnot", m_bitnot, _negate, NULL);
> +   else
> +  err |= control(file, "negate", m_negate, _negate, NULL);
> +
> err |= control(file, "abs", _abs, __abs, NULL);
>  
> string(file, "g[a0");
> @@ -792,6 +818,8 @@ src_ia1(FILE *file,
>  
>  static int
>  src_da16(FILE *file,
> + const struct brw_context *brw,
> + unsigned opcode,
>   unsigned _reg_type,
>   unsigned _reg_file,
>   unsigned _vert_stride,
> @@ -802,7 +830,12 @@ src_da16(FILE *file,
>   unsigned swz_x, unsigned swz_y, unsigned swz_z, unsigned swz_w)
>  {
> int err = 0;
> -   err |= control(file, "negate", m_negate, _negate, NULL);
> +
> +   if (brw->gen >= 8 && is_logic_instruction(opcode))
> +  err |= control(file, "bitnot", m_bitnot, _negate, NULL);
> +   else
> +  err |= control(file, "negate", m_negate, _negate, NULL);
> +
> err |= control(file, "abs", _abs, __abs, NULL);
>  
> err |= reg(file, _reg_file, _reg_nr);
> @@ -1023,6 +1056,8 @@ src0(FILE *file, struct brw_context *brw, brw_inst 
> *inst)
> } else if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
>if (brw_inst_src0_address_mode(brw, inst) == BRW_ADDRESS_DIRECT) {
>   return src_da1(file,
> +brw,
> +brw_inst_opcode(brw, inst),
>  brw_inst_src0_reg_type(brw, inst),
>  brw_inst_src0_reg_file(brw, inst),
>  brw_inst_src0_vstride(brw, inst),
> @@ -1034,6 +1069,8 @@ src0(FILE *file, struct brw_context *brw, brw_inst 
> *inst)
>  brw_inst_src0_negate(brw, inst));
>} else {
>   return src_ia1(file,
> +brw,
> +brw_inst_opcode(brw, inst),
>  brw_inst_src0_reg_type(brw, inst),
>  brw_inst_src0_reg_file(brw, inst),
>  brw_inst_src0_ia1_addr_imm(brw, inst),
> @@ -1048,6 +1085,8 @@ src0(FILE *file, struct brw_context *brw, brw_inst 
> *inst)
> } else {
>if (brw_inst_src0_address_mode(brw, inst) == BRW_ADDRESS_DIRECT) {
>   return src_da16(file,
> + brw,
> + brw_inst_opcode(brw, inst),
>   

Re: [Mesa-dev] [PATCH 1/3] mesa: Make unreachable macro take a string argument.

[Ian Romanick]

Patches 1 & 3 are

Reviewed-by: Ian Romanick 

On 06/30/2014 10:27 AM, Matt Turner wrote:
> To aid in debugging.
> ---
>  src/glsl/opt_vectorize.cpp|  3 +--
>  src/mesa/drivers/common/meta.c|  3 +--
>  src/mesa/drivers/dri/i965/brw_blorp_clear.cpp |  4 +---
>  src/mesa/drivers/dri/i965/brw_reg.h   |  3 +--
>  src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp  |  3 +--
>  src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp |  3 +--
>  src/mesa/main/compiler.h  | 14 +++---
>  7 files changed, 17 insertions(+), 16 deletions(-)
> 
> diff --git a/src/glsl/opt_vectorize.cpp b/src/glsl/opt_vectorize.cpp
> index f9a3b61..28534a8 100644
> --- a/src/glsl/opt_vectorize.cpp
> +++ b/src/glsl/opt_vectorize.cpp
> @@ -227,8 +227,7 @@ write_mask_to_swizzle(unsigned write_mask)
> case WRITEMASK_Z: return SWIZZLE_Z;
> case WRITEMASK_W: return SWIZZLE_W;
> }
> -   assert(!"not reached");
> -   unreachable();
> +   unreachable("not reached");
>  }
>  
>  /**
> diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
> index 1a2e453..3db3611 100644
> --- a/src/mesa/drivers/common/meta.c
> +++ b/src/mesa/drivers/common/meta.c
> @@ -2613,8 +2613,7 @@ _mesa_meta_setup_texture_coords(GLenum faceTarget,
>  coord = coords3;
>  break;
>   default:
> -assert(0);
> -unreachable();
> +unreachable("not reached");
>   }
>  
>   coord[3] = (float) (slice / 6);
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp 
> b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
> index 5efdf71..df34c72 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
> @@ -337,9 +337,7 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct 
> brw_context *brw,
>  x_scaledown = 2;
>  break;
>   default:
> -assert(!"Unexpected sample count for fast clear");
> -unreachable();
> -break;
> +unreachable("Unexpected sample count for fast clear");
>   }
>   y_scaledown = 2;
>   x_align = x_scaledown * 2;
> diff --git a/src/mesa/drivers/dri/i965/brw_reg.h 
> b/src/mesa/drivers/dri/i965/brw_reg.h
> index fc2e0b0..24346be 100644
> --- a/src/mesa/drivers/dri/i965/brw_reg.h
> +++ b/src/mesa/drivers/dri/i965/brw_reg.h
> @@ -358,9 +358,8 @@ brw_vecn_reg(unsigned width, unsigned file, unsigned nr, 
> unsigned subnr)
> case 16:
>return brw_vec16_reg(file, nr, subnr);
> default:
> -  assert(!"Invalid register width");
> +  unreachable("Invalid register width");
> }
> -   unreachable();
>  }
>  
>  static inline struct brw_reg
> diff --git a/src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp 
> b/src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp
> index fd517f8..0667465 100644
> --- a/src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp
> +++ b/src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp
> @@ -86,8 +86,7 @@ protected:
>  
> virtual vec4_instruction *emit_urb_write_opcode(bool complete)
> {
> -  assert(!"Not reached");
> -  unreachable();
> +  unreachable("Not reached");
> }
>  };
>  
> diff --git a/src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp 
> b/src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp
> index 7563aef..78c758c 100644
> --- a/src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp
> +++ b/src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp
> @@ -89,8 +89,7 @@ protected:
>  
> virtual vec4_instruction *emit_urb_write_opcode(bool complete)
> {
> -  assert(!"Not reached");
> -  unreachable();
> +  unreachable("Not reached");
> }
>  };
>  
> diff --git a/src/mesa/main/compiler.h b/src/mesa/main/compiler.h
> index 6006917..79d8740 100644
> --- a/src/mesa/main/compiler.h
> +++ b/src/mesa/main/compiler.h
> @@ -253,15 +253,23 @@ static INLINE GLuint CPU_TO_LE32(GLuint x)
>   * function" warnings.
>   */
>  #if __GNUC__ >= 4 && __GNUC_MINOR__ >= 5
> -#define unreachable() __builtin_unreachable()
> +#define unreachable(str)\
> +do {\
> +   assert(!str);\
> +   __builtin_unreachable(); \
> +} while (0)
>  #elif (defined(__clang__) && defined(__has_builtin))
>  # if __has_builtin(__builtin_unreachable)
> -#  define unreachable() __builtin_unreachable()
> +#  define unreachable(str)  \
> +do {\
> +   assert(!str);\
> +   __builtin_unreachable(); \
> +} while (0)
>  # endif
>  #endif
>  
>  #ifndef unreachable
> -#define unreachable()
> +#define unreachable(str)
>  #endif
>  
>  /*
> 

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Re: [Mesa-dev] [PATCH 13/23] i965/disasm: Improve disassembly of atomic messages on Haswell+.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:33:52PM -0700, Kenneth Graunke wrote:
> This backports the atomic message disassembly support from
> gen8_disasm.c, which additionally offers support for decoding atomic
> surface read/write messages, and showing SIMD modes and other details.
> 
> Signed-off-by: Kenneth Graunke 
> ---
>  src/mesa/drivers/dri/i965/brw_disasm.c | 28 +---
>  1 file changed, 21 insertions(+), 7 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index 4e75cc7..99c9bd0 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -1417,33 +1417,47 @@ brw_disassemble_inst(FILE *file, struct brw_context 
> *brw, brw_inst *inst,
>   }
>   /* FALLTHROUGH */
>  
> -  case HSW_SFID_DATAPORT_DATA_CACHE_1:
> +  case HSW_SFID_DATAPORT_DATA_CACHE_1: {
>   if (brw->gen >= 7) {
>  format(file, " (");
>  
> +unsigned msg_ctrl = brw_inst_dp_msg_control(brw, inst);
> +
>  err |= control(file, "DP DC1 message type",
> dp_dc1_msg_type_hsw,
> brw_inst_dp_msg_type(brw, inst), &space);
>  
> -format(file, ", %d, ", brw_inst_binding_table_index(brw, inst));
> +format(file, ", Surface = %d, ",
> +   brw_inst_binding_table_index(brw, inst));
>  
>  switch (brw_inst_dp_msg_type(brw, inst)) {
>  case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP:
> -case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2:
>  case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP:
> -case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2:
>  case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP:
> +   format(file, "SIMD%d,", (msg_ctrl & (1 << 4)) ? 8 : 16);
> +   /* fallthrough */
> +case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2:
> +case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2:
>  case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2:

I was wondering if we could print out SIMD4x2 in these three cases as
we do above for SIMD8 and SIMD16, but it's part of the atomic operand
name, of course.

Reviewed-by: Kristian Høgsberg 

> -   control(file, "atomic op", aop,
> -   brw_inst_imm_ud(brw, inst) >> 8 & 0xf, &space);
> +   control(file, "atomic op", aop, msg_ctrl & 0xf, &space);
> +   break;
> +case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ:
> +case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE:
> +case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ:
> +case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE: {
> +   static const char *simd_modes[] = { "4x2", "16", "8" };
> +   format(file, "SIMD%s, Mask = 0x%x",
> +  simd_modes[msg_ctrl >> 4], msg_ctrl & 0xf);
> break;
> +}
>  default:
> -   format(file, "%d", brw_inst_dp_msg_control(brw, inst));
> +   format(file, "0x%x", msg_ctrl);
>  }
>  format(file, ")");
>  break;
>   }
>   /* FALLTHROUGH */
> +  }
>  
>default:
>   format(file, "unsupported target %d", target);
> -- 
> 2.0.0
> 
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Re: [Mesa-dev] [PATCH 1/3] i965: Mark fields in the live interval classes protected.

[Ian Romanick]

Patches 1 & 2 are

Reviewed-by: Ian Romanick 

On 06/30/2014 10:11 AM, Matt Turner wrote:
> cfg, for instance, is a pointer to a local variable in
> calculate_live_intervals, certainly not valid after that function has
> returned.
> ---
>  src/mesa/drivers/dri/i965/brw_fs_live_variables.h  | 22 
> --
>  .../drivers/dri/i965/brw_vec4_live_variables.h | 13 +++--
>  2 files changed, 19 insertions(+), 16 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_live_variables.h 
> b/src/mesa/drivers/dri/i965/brw_fs_live_variables.h
> index 82575d8..5a7dd27 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_live_variables.h
> +++ b/src/mesa/drivers/dri/i965/brw_fs_live_variables.h
> @@ -60,19 +60,9 @@ public:
> fs_live_variables(fs_visitor *v, cfg_t *cfg);
> ~fs_live_variables();
>  
> -   void setup_def_use();
> -   void setup_one_read(bblock_t *block, fs_inst *inst, int ip, fs_reg reg);
> -   void setup_one_write(bblock_t *block, fs_inst *inst, int ip, fs_reg reg);
> -   void compute_live_variables();
> -   void compute_start_end();
> -
> bool vars_interfere(int a, int b);
> int var_from_reg(fs_reg *reg);
>  
> -   fs_visitor *v;
> -   cfg_t *cfg;
> -   void *mem_ctx;
> -
> /** Map from virtual GRF number to index in block_data arrays. */
> int *var_from_vgrf;
>  
> @@ -98,6 +88,18 @@ public:
>  
> /** Per-basic-block information on live variables */
> struct block_data *bd;
> +
> +protected:
> +   void setup_def_use();
> +   void setup_one_read(bblock_t *block, fs_inst *inst, int ip, fs_reg reg);
> +   void setup_one_write(bblock_t *block, fs_inst *inst, int ip, fs_reg reg);
> +   void compute_live_variables();
> +   void compute_start_end();
> +
> +   fs_visitor *v;
> +   cfg_t *cfg;
> +   void *mem_ctx;
> +
>  };
>  
>  } /* namespace brw */
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h 
> b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h
> index b2d8b33..03cc813 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h
> @@ -58,18 +58,19 @@ public:
> vec4_live_variables(vec4_visitor *v, cfg_t *cfg);
> ~vec4_live_variables();
>  
> +   int num_vars;
> +   int bitset_words;
> +
> +   /** Per-basic-block information on live variables */
> +   struct block_data *bd;
> +
> +protected:
> void setup_def_use();
> void compute_live_variables();
>  
> vec4_visitor *v;
> cfg_t *cfg;
> void *mem_ctx;
> -
> -   int num_vars;
> -   int bitset_words;
> -
> -   /** Per-basic-block information on live variables */
> -   struct block_data *bd;
>  };
>  
>  } /* namespace brw */
> 

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Re: [Mesa-dev] [PATCH 3/3] i965/vec4: Remove useless conditionals.

[Ian Romanick]

On 06/30/2014 10:11 AM, Matt Turner wrote:
> Setting a couple of bits is the same cost or less as conditionally
> setting a couple of bits.
> ---
>  src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 9 +++--
>  1 file changed, 3 insertions(+), 6 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> index 8f5b205..509c32c 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> @@ -1266,12 +1266,9 @@ vec4_generator::generate_code(exec_list *instructions)
>  
>   brw_inst *last = &p->store[pre_emit_nr_insn];
>  
> - if (inst->conditional_mod)
> -brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
> - if (inst->no_dd_clear)
> -brw_inst_set_no_dd_clear(brw, last, true);
> - if (inst->no_dd_check)
> -brw_inst_set_no_dd_check(brw, last, true);
> + brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
> + brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
> + brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);

The old code will only set the bits.  The new code might also clear the
bits, right?  Is that potentially a problem?

>}
> }
>  

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Re: [Mesa-dev] [PATCH 3/4] i965/fs: Mark predicated PLN instructions with dependency hints.

[Ian Romanick]

On 06/29/2014 11:18 PM, Matt Turner wrote:
> To implement the unlit_centroid_workaround, previously we emitted
> 
>(+f0) pln(8) g20<1>F g16.4<0,1,0>F g4<8,8,1>F { align1 1Q };
>(-f0) pln(8) g20<1>F g16.4<0,1,0>F g2<8,8,1>F { align1 1Q };
> 
> where the flag register contains the channel enable bits from g0.
> 
> Since the predicates are complementary, the pair of pln instructions
> write to non-overlapping components of the destination, which is the
> case that the dependency control hints are designed for.
> 
> Typically setting dependency control hints on predicated instructions
> isn't safe (if an instruction doesn't execute due to the predicate, it
> won't update the scoreboard, leaving it in a bad state) but since we
> must have at least one channel executing (i.e., +f0 is true for some
> channel) by virtue of the fact that the thread is running, we can put
> the +f0 pln instruction last and set the hints:
> 
>(-f0) pln(8) g20<1>F g16.4<0,1,0>F g2<8,8,1>F { align1 NoDDClr 1Q };
>(+f0) pln(8) g20<1>F g16.4<0,1,0>F g4<8,8,1>F { align1 NoDDChk 1Q };

And there's no chance of instruction scheduling ever putting something
between?  Seems unlikely, but... would be bad.

> ---
>  src/mesa/drivers/dri/i965/brw_fs.cpp | 13 +
>  1 file changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
> b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index 3b7a170..5a3d1d3 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -1178,15 +1178,20 @@ fs_visitor::emit_general_interpolation(ir_variable 
> *ir)
>  
>fs_inst *inst;
>inst = emit_linterp(attr, fs_reg(interp), 
> interpolation_mode,
> +  false, false);
> +  inst->predicate = BRW_PREDICATE_NORMAL;
> +  inst->predicate_inverse = true;
> +  if (brw->has_pln)
> + inst->no_dd_clear = true;
> +
> +  inst = emit_linterp(attr, fs_reg(interp), 
> interpolation_mode,
>ir->data.centroid && 
> !key->persample_shading,
>ir->data.sample || 
> key->persample_shading);
>inst->predicate = BRW_PREDICATE_NORMAL;
>inst->predicate_inverse = false;
> +  if (brw->has_pln)
> + inst->no_dd_check = true;
>  
> -  inst = emit_linterp(attr, fs_reg(interp), 
> interpolation_mode,
> -  false, false);
> -  inst->predicate = BRW_PREDICATE_NORMAL;
> -  inst->predicate_inverse = true;
> } else {
>emit_linterp(attr, fs_reg(interp), interpolation_mode,
> ir->data.centroid && !key->persample_shading,
> 

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[Mesa-dev] [PATCH 3/3] i965/fs: Mark case unreachable to silence warning.

[Matt Turner]

---
 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 06ae4a1..90528ed 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1449,6 +1449,8 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, 
fs_reg coordinate,
   else
  opcode = SHADER_OPCODE_TG4;
   break;
+   default:
+  unreachable("not reached");
}
fs_inst *inst = emit(opcode, dst, src_payload);
inst->base_mrf = -1;
-- 
1.8.3.2

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[Mesa-dev] [PATCH 1/3] mesa: Make unreachable macro take a string argument.

[Matt Turner]

To aid in debugging.
---
 src/glsl/opt_vectorize.cpp|  3 +--
 src/mesa/drivers/common/meta.c|  3 +--
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp |  4 +---
 src/mesa/drivers/dri/i965/brw_reg.h   |  3 +--
 src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp  |  3 +--
 src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp |  3 +--
 src/mesa/main/compiler.h  | 14 +++---
 7 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/src/glsl/opt_vectorize.cpp b/src/glsl/opt_vectorize.cpp
index f9a3b61..28534a8 100644
--- a/src/glsl/opt_vectorize.cpp
+++ b/src/glsl/opt_vectorize.cpp
@@ -227,8 +227,7 @@ write_mask_to_swizzle(unsigned write_mask)
case WRITEMASK_Z: return SWIZZLE_Z;
case WRITEMASK_W: return SWIZZLE_W;
}
-   assert(!"not reached");
-   unreachable();
+   unreachable("not reached");
 }
 
 /**
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 1a2e453..3db3611 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -2613,8 +2613,7 @@ _mesa_meta_setup_texture_coords(GLenum faceTarget,
 coord = coords3;
 break;
  default:
-assert(0);
-unreachable();
+unreachable("not reached");
  }
 
  coord[3] = (float) (slice / 6);
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 5efdf71..df34c72 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -337,9 +337,7 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct 
brw_context *brw,
 x_scaledown = 2;
 break;
  default:
-assert(!"Unexpected sample count for fast clear");
-unreachable();
-break;
+unreachable("Unexpected sample count for fast clear");
  }
  y_scaledown = 2;
  x_align = x_scaledown * 2;
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h 
b/src/mesa/drivers/dri/i965/brw_reg.h
index fc2e0b0..24346be 100644
--- a/src/mesa/drivers/dri/i965/brw_reg.h
+++ b/src/mesa/drivers/dri/i965/brw_reg.h
@@ -358,9 +358,8 @@ brw_vecn_reg(unsigned width, unsigned file, unsigned nr, 
unsigned subnr)
case 16:
   return brw_vec16_reg(file, nr, subnr);
default:
-  assert(!"Invalid register width");
+  unreachable("Invalid register width");
}
-   unreachable();
 }
 
 static inline struct brw_reg
diff --git a/src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp 
b/src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp
index fd517f8..0667465 100644
--- a/src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp
@@ -86,8 +86,7 @@ protected:
 
virtual vec4_instruction *emit_urb_write_opcode(bool complete)
{
-  assert(!"Not reached");
-  unreachable();
+  unreachable("Not reached");
}
 };
 
diff --git a/src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp 
b/src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp
index 7563aef..78c758c 100644
--- a/src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp
+++ b/src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp
@@ -89,8 +89,7 @@ protected:
 
virtual vec4_instruction *emit_urb_write_opcode(bool complete)
{
-  assert(!"Not reached");
-  unreachable();
+  unreachable("Not reached");
}
 };
 
diff --git a/src/mesa/main/compiler.h b/src/mesa/main/compiler.h
index 6006917..79d8740 100644
--- a/src/mesa/main/compiler.h
+++ b/src/mesa/main/compiler.h
@@ -253,15 +253,23 @@ static INLINE GLuint CPU_TO_LE32(GLuint x)
  * function" warnings.
  */
 #if __GNUC__ >= 4 && __GNUC_MINOR__ >= 5
-#define unreachable() __builtin_unreachable()
+#define unreachable(str)\
+do {\
+   assert(!str);\
+   __builtin_unreachable(); \
+} while (0)
 #elif (defined(__clang__) && defined(__has_builtin))
 # if __has_builtin(__builtin_unreachable)
-#  define unreachable() __builtin_unreachable()
+#  define unreachable(str)  \
+do {\
+   assert(!str);\
+   __builtin_unreachable(); \
+} while (0)
 # endif
 #endif
 
 #ifndef unreachable
-#define unreachable()
+#define unreachable(str)
 #endif
 
 /*
-- 
1.8.3.2

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Re: [Mesa-dev] [PATCH 12/23] i965/disasm: Actually disassemble Gen7+ URB opcodes.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:33:51PM -0700, Kenneth Graunke wrote:
> I never bothered implementing the disassembler for Gen7+ URB opcodes, so
> we were just disassembling them as Ironlake/Sandybridge ones.  This
> looked pretty bad when running Paul's GS EndPrimitive tests, as the
> "write OWord" message was decoded at ff_sync, which doesn't exist.
> 
> Signed-off-by: Kenneth Graunke 
> ---
>  src/mesa/drivers/dri/i965/brw_disasm.c | 22 +++---
>  1 file changed, 19 insertions(+), 3 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index 14cb687..4e75cc7 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -478,11 +478,24 @@ static const char *const math_precision[2] = {
> [1] = "partial_precision"
>  };
>  
> -static const char *const urb_opcode[2] = {
> +static const char *const gen5_urb_opcode[] = {
> [0] = "urb_write",
> [1] = "ff_sync",
>  };
>  
> +static const char *const gen7_urb_opcode[] = {
> +   [0] = "write HWord",
> +   [1] = "write OWord",
> +   [2] = "read HWord",
> +   [3] = "read OWord",
> +   [4] = "atomic mov",  /* Gen7+ */
> +   [5] = "atomic inc",  /* Gen7+ */
> +   [6] = "atomic add",  /* Gen8+ */
> +   [7] = "SIMD8 write", /* Gen8+ */
> +   [8] = "SIMD8 read",  /* Gen8+ */
> +   /* [9-15] - reserved */
> +};

Do we have defines for these opcodes?  They stand out a bit now that
all the rest are using opcode names in the array initializer.

Either way, not worth blocking this disasm improvement on,

Reviewed-by: Kristian Høgsberg 


>  static const char *const urb_swizzle[4] = {
> [BRW_URB_SWIZZLE_NONE]   = "",
> [BRW_URB_SWIZZLE_INTERLEAVE] = "interleave",
> @@ -1361,8 +1374,11 @@ brw_disassemble_inst(FILE *file, struct brw_context 
> *brw, brw_inst *inst,
>   format(file, " %d", brw_inst_urb_global_offset(brw, inst));
>  
>   space = 1;
> - if (brw->gen >= 5) {
> -err |= control(file, "urb opcode", urb_opcode,
> + if (brw->gen >= 7) {
> +err |= control(file, "urb opcode", gen7_urb_opcode,
> +   brw_inst_urb_opcode(brw, inst), &space);
> + } else if (brw->gen >= 5) {
> +err |= control(file, "urb opcode", gen5_urb_opcode,
> brw_inst_urb_opcode(brw, inst), &space);
>   }
>   err |= control(file, "urb swizzle", urb_swizzle,
> -- 
> 2.0.0
> 
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Re: [Mesa-dev] [PATCH 11/23] i965/disasm: Decode Broadwell's invm/rsqrtm math functions.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:33:50PM -0700, Kenneth Graunke wrote:
> We don't use these yet, but we may as well disassemble them.
> 
> Signed-off-by: Kenneth Graunke 

Reviewed-by: Kristian Høgsberg 

> ---
>  src/mesa/drivers/dri/i965/brw_disasm.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index b651120..14cb687 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -454,6 +454,8 @@ static const char *const math_function[16] = {
> [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER] = "intdivmod",
> [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT]  = "intdiv",
> [BRW_MATH_FUNCTION_INT_DIV_REMAINDER] = "intmod",
> +   [GEN8_MATH_FUNCTION_INVM]  = "invm",
> +   [GEN8_MATH_FUNCTION_RSQRTM] = "rsqrtm",
>  };
>  
>  static const char *const math_saturate[2] = {
> -- 
> 2.0.0
> 
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Re: [Mesa-dev] [PATCH 09/23] i965/disasm: Properly disassemble all32h/any32h align1 predicates.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:33:48PM -0700, Kenneth Graunke wrote:
> While we're adding things, use symbolic constants rather than magic
> numbers.
> 
> Signed-off-by: Kenneth Graunke 

Reviewed-by: Kristian Høgsberg 

> ---
>  src/mesa/drivers/dri/i965/brw_disasm.c | 24 +---
>  1 file changed, 13 insertions(+), 11 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index e40938a..26b60b6 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -231,17 +231,19 @@ static const char *const pred_ctrl_align16[16] = {
>  };
>  
>  static const char *const pred_ctrl_align1[16] = {
> -   [1] = "",
> -   [2] = ".anyv",
> -   [3] = ".allv",
> -   [4] = ".any2h",
> -   [5] = ".all2h",
> -   [6] = ".any4h",
> -   [7] = ".all4h",
> -   [8] = ".any8h",
> -   [9] = ".all8h",
> -   [10] = ".any16h",
> -   [11] = ".all16h",
> +   [BRW_PREDICATE_NORMAL]= "",
> +   [BRW_PREDICATE_ALIGN1_ANYV]   = ".anyv",
> +   [BRW_PREDICATE_ALIGN1_ALLV]   = ".allv",
> +   [BRW_PREDICATE_ALIGN1_ANY2H]  = ".any2h",
> +   [BRW_PREDICATE_ALIGN1_ALL2H]  = ".all2h",
> +   [BRW_PREDICATE_ALIGN1_ANY4H]  = ".any4h",
> +   [BRW_PREDICATE_ALIGN1_ALL4H]  = ".all4h",
> +   [BRW_PREDICATE_ALIGN1_ANY8H]  = ".any8h",
> +   [BRW_PREDICATE_ALIGN1_ALL8H]  = ".all8h",
> +   [BRW_PREDICATE_ALIGN1_ANY16H] = ".any16h",
> +   [BRW_PREDICATE_ALIGN1_ANY16H] = ".all16h",
> +   [BRW_PREDICATE_ALIGN1_ANY32H] = ".any32h",
> +   [BRW_PREDICATE_ALIGN1_ANY32H] = ".all32h",
>  };
>  
>  static const char *const thread_ctrl[4] = {
> -- 
> 2.0.0
> 
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[Mesa-dev] [PATCH] glapi: Mark old ATI_envmap_bumpmap functions as "skip"

[Ian Romanick]

From: Ian Romanick 

There's still a slot for them in the dispatch table, but Mesa won't put
anything in that slot anymore.

Signed-off-by: Ian Romanick 
---

Fixes the build. :) This should get squashed in with Jason's v3 patch.

 src/mapi/glapi/gen/gl_API.xml | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml
index 0a486f0..882e66e 100644
--- a/src/mapi/glapi/gen/gl_API.xml
+++ b/src/mapi/glapi/gen/gl_API.xml
@@ -12157,22 +12157,22 @@
 
 
 
-
+
   
   
   
 
-
+
   
   
   
 
-
+
   
   
   
 
-
+
   
   
   
-- 
1.8.1.4

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Re: [Mesa-dev] [PATCH 10/23] i965/disasm: Properly disassemble the "atomic" ThreadCtrl value.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:33:49PM -0700, Kenneth Graunke wrote:
> Signed-off-by: Kenneth Graunke 
> ---
>  src/mesa/drivers/dri/i965/brw_disasm.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)

Double checked the spec, looks right.

Reviewed-by: Kristian Høgsberg 

> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index 26b60b6..b651120 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -247,8 +247,9 @@ static const char *const pred_ctrl_align1[16] = {
>  };
>  
>  static const char *const thread_ctrl[4] = {
> -   [0] = "",
> -   [2] = "switch"
> +   [BRW_THREAD_NORMAL] = "",
> +   [BRW_THREAD_ATOMIC] = "atomic",
> +   [BRW_THREAD_SWITCH] = "switch",
>  };
>  
>  static const char *const compr_ctrl[4] = {
> -- 
> 2.0.0
> 
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Re: [Mesa-dev] [PATCH 08/23] i965: Add #defines for any32h/all32h predication.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:33:47PM -0700, Kenneth Graunke wrote:
> These have existed since Ivybridge.  We don't use them today, but the
> Gen8+ disassembler supports them, and I'd like to use symbolic names
> rather than magic numbers.

Reviewed-by: Kristian Høgsberg 

> Signed-off-by: Kenneth Graunke 
> ---
>  src/mesa/drivers/dri/i965/brw_defines.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index 88d18a3..858d9af 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -1025,6 +1025,8 @@ operator|(brw_urb_write_flags x, brw_urb_write_flags y)
>  #define BRW_PREDICATE_ALIGN1_ALL8H9
>  #define BRW_PREDICATE_ALIGN1_ANY16H   10
>  #define BRW_PREDICATE_ALIGN1_ALL16H   11
> +#define BRW_PREDICATE_ALIGN1_ANY32H   12
> +#define BRW_PREDICATE_ALIGN1_ALL32H   13
>  #define BRW_PREDICATE_ALIGN16_REPLICATE_X 2
>  #define BRW_PREDICATE_ALIGN16_REPLICATE_Y 3
>  #define BRW_PREDICATE_ALIGN16_REPLICATE_Z 4
> -- 
> 2.0.0
> 
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[Mesa-dev] [PATCH 2/3] i965/fs: Pass cfg to calculate_live_intervals().

[Matt Turner]

We've often created the CFG immediately before, so use it when
available.
---
 src/mesa/drivers/dri/i965/brw_fs.h|  2 +-
 src/mesa/drivers/dri/i965/brw_fs_cse.cpp  |  3 +--
 src/mesa/drivers/dri/i965/brw_fs_dead_code_eliminate.cpp  |  2 +-
 src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp   | 12 
 src/mesa/drivers/dri/i965/brw_fs_live_variables.h |  4 ++--
 src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp |  4 ++--
 6 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.h 
b/src/mesa/drivers/dri/i965/brw_fs.h
index 58e7175..961c56c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -373,7 +373,7 @@ public:
void assign_constant_locations();
void demote_pull_constants();
void invalidate_live_intervals();
-   void calculate_live_intervals();
+   void calculate_live_intervals(const cfg_t *cfg = NULL);
void calculate_register_pressure();
bool opt_algebraic();
bool opt_cse();
diff --git a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
index 381c569..5727801 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
@@ -317,9 +317,8 @@ fs_visitor::opt_cse()
 {
bool progress = false;
 
-   calculate_live_intervals();
-
cfg_t cfg(&instructions);
+   calculate_live_intervals(&cfg);
 
for (int b = 0; b < cfg.num_blocks; b++) {
   bblock_t *block = cfg.blocks[b];
diff --git a/src/mesa/drivers/dri/i965/brw_fs_dead_code_eliminate.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_dead_code_eliminate.cpp
index 7b2d4aa..d41a42c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_dead_code_eliminate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_dead_code_eliminate.cpp
@@ -41,7 +41,7 @@ fs_visitor::dead_code_eliminate()
 
cfg_t cfg(&instructions);
 
-   calculate_live_intervals();
+   calculate_live_intervals(&cfg);
 
int num_vars = live_intervals->num_vars;
BITSET_WORD *live = ralloc_array(NULL, BITSET_WORD, BITSET_WORDS(num_vars));
diff --git a/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
index 0973dc9..585dc3d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
@@ -243,7 +243,7 @@ fs_live_variables::var_from_reg(fs_reg *reg)
return var_from_vgrf[reg->reg] + reg->reg_offset;
 }
 
-fs_live_variables::fs_live_variables(fs_visitor *v, cfg_t *cfg)
+fs_live_variables::fs_live_variables(fs_visitor *v, const cfg_t *cfg)
: v(v), cfg(cfg)
 {
mem_ctx = ralloc_context(NULL);
@@ -304,7 +304,7 @@ fs_visitor::invalidate_live_intervals()
  * information about whole VGRFs.
  */
 void
-fs_visitor::calculate_live_intervals()
+fs_visitor::calculate_live_intervals(const cfg_t *cfg)
 {
if (this->live_intervals)
   return;
@@ -320,8 +320,12 @@ fs_visitor::calculate_live_intervals()
   virtual_grf_end[i] = -1;
}
 
-   cfg_t cfg(&instructions);
-   this->live_intervals = new(mem_ctx) fs_live_variables(this, &cfg);
+   if (cfg) {
+  this->live_intervals = new(mem_ctx) fs_live_variables(this, cfg);
+   } else {
+  cfg_t cfg(&instructions);
+  this->live_intervals = new(mem_ctx) fs_live_variables(this, &cfg);
+   }
 
/* Merge the per-component live ranges to whole VGRF live ranges. */
for (int i = 0; i < live_intervals->num_vars; i++) {
diff --git a/src/mesa/drivers/dri/i965/brw_fs_live_variables.h 
b/src/mesa/drivers/dri/i965/brw_fs_live_variables.h
index 5a7dd27..13c3eb4 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_live_variables.h
+++ b/src/mesa/drivers/dri/i965/brw_fs_live_variables.h
@@ -57,7 +57,7 @@ class fs_live_variables {
 public:
DECLARE_RALLOC_CXX_OPERATORS(fs_live_variables)
 
-   fs_live_variables(fs_visitor *v, cfg_t *cfg);
+   fs_live_variables(fs_visitor *v, const cfg_t *cfg);
~fs_live_variables();
 
bool vars_interfere(int a, int b);
@@ -97,7 +97,7 @@ protected:
void compute_start_end();
 
fs_visitor *v;
-   cfg_t *cfg;
+   const cfg_t *cfg;
void *mem_ctx;
 
 };
diff --git a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
index 079eb2e..1287adb 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
@@ -93,10 +93,10 @@ fs_visitor::opt_saturate_propagation()
 {
bool progress = false;
 
-   calculate_live_intervals();
-
cfg_t cfg(&instructions);
 
+   calculate_live_intervals(&cfg);
+
for (int b = 0; b < cfg.num_blocks; b++) {
   progress = opt_saturate_propagation_local(this, cfg.blocks[b])
  || progress;
-- 
1.8.3.2

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[Mesa-dev] [PATCH 1/3] i965: Mark fields in the live interval classes protected.

[Matt Turner]

cfg, for instance, is a pointer to a local variable in
calculate_live_intervals, certainly not valid after that function has
returned.
---
 src/mesa/drivers/dri/i965/brw_fs_live_variables.h  | 22 --
 .../drivers/dri/i965/brw_vec4_live_variables.h | 13 +++--
 2 files changed, 19 insertions(+), 16 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_live_variables.h 
b/src/mesa/drivers/dri/i965/brw_fs_live_variables.h
index 82575d8..5a7dd27 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_live_variables.h
+++ b/src/mesa/drivers/dri/i965/brw_fs_live_variables.h
@@ -60,19 +60,9 @@ public:
fs_live_variables(fs_visitor *v, cfg_t *cfg);
~fs_live_variables();
 
-   void setup_def_use();
-   void setup_one_read(bblock_t *block, fs_inst *inst, int ip, fs_reg reg);
-   void setup_one_write(bblock_t *block, fs_inst *inst, int ip, fs_reg reg);
-   void compute_live_variables();
-   void compute_start_end();
-
bool vars_interfere(int a, int b);
int var_from_reg(fs_reg *reg);
 
-   fs_visitor *v;
-   cfg_t *cfg;
-   void *mem_ctx;
-
/** Map from virtual GRF number to index in block_data arrays. */
int *var_from_vgrf;
 
@@ -98,6 +88,18 @@ public:
 
/** Per-basic-block information on live variables */
struct block_data *bd;
+
+protected:
+   void setup_def_use();
+   void setup_one_read(bblock_t *block, fs_inst *inst, int ip, fs_reg reg);
+   void setup_one_write(bblock_t *block, fs_inst *inst, int ip, fs_reg reg);
+   void compute_live_variables();
+   void compute_start_end();
+
+   fs_visitor *v;
+   cfg_t *cfg;
+   void *mem_ctx;
+
 };
 
 } /* namespace brw */
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h 
b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h
index b2d8b33..03cc813 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h
@@ -58,18 +58,19 @@ public:
vec4_live_variables(vec4_visitor *v, cfg_t *cfg);
~vec4_live_variables();
 
+   int num_vars;
+   int bitset_words;
+
+   /** Per-basic-block information on live variables */
+   struct block_data *bd;
+
+protected:
void setup_def_use();
void compute_live_variables();
 
vec4_visitor *v;
cfg_t *cfg;
void *mem_ctx;
-
-   int num_vars;
-   int bitset_words;
-
-   /** Per-basic-block information on live variables */
-   struct block_data *bd;
 };
 
 } /* namespace brw */
-- 
1.8.3.2

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[Mesa-dev] [PATCH 3/3] i965/vec4: Remove useless conditionals.

[Matt Turner]

Setting a couple of bits is the same cost or less as conditionally
setting a couple of bits.
---
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 8f5b205..509c32c 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -1266,12 +1266,9 @@ vec4_generator::generate_code(exec_list *instructions)
 
  brw_inst *last = &p->store[pre_emit_nr_insn];
 
- if (inst->conditional_mod)
-brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
- if (inst->no_dd_clear)
-brw_inst_set_no_dd_clear(brw, last, true);
- if (inst->no_dd_check)
-brw_inst_set_no_dd_check(brw, last, true);
+ brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
+ brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
+ brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
   }
}
 
-- 
1.8.3.2

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Re: [Mesa-dev] [PATCH] Remove the ATI_envmap_bumpmap extension

[Ian Romanick]

On 06/27/2014 06:42 PM, Jason Ekstrand wrote:
> On Fri, Jun 27, 2014 at 5:59 PM, Ian Romanick  > wrote:
> On 06/27/2014 03:19 PM, Jason Ekstrand wrote:
> > diff --git a/src/mapi/glapi/gen/gl_API.xml
> b/src/mapi/glapi/gen/gl_API.xml
> > index 0a486f0..7b8b9d2 100644
> > --- a/src/mapi/glapi/gen/gl_API.xml
> > +++ b/src/mapi/glapi/gen/gl_API.xml
> > @@ -12129,56 +12129,6 @@
> >   value="0x886F"/>
> >  
> 
> We can't remove these.  That will break compatibility between newer
> libGL and olded driver builds.
> 
> Which "these"?  The uniforms or the gl_API.xml stuff?

At the very least, the function entries cannot be removed.  Try running
the libGL with your patch with an i965 driver without your patch to see
why.  In a practical sense, it's probably better not to remove any of
the XML.

Also... be sure that you actually run 'make check'.

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Re: [Mesa-dev] [PATCH 07/23] i965/disasm: Mark ELSE as having UIP on Gen8+.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:33:46PM -0700, Kenneth Graunke wrote:
> This makes brw_disasm.c able to disassemble ELSE instructions correctly
> on Broadwell.  (gen8_disasm.c already handles this correctly.)
> 
> Signed-off-by: Kenneth Graunke 

Looks correct, the spec agrees.

Reviewed-by: Kristian Høgsberg 

> ---
>  src/mesa/drivers/dri/i965/brw_disasm.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index 7773ad9..e40938a 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -119,6 +119,7 @@ has_uip(struct brw_context *brw, enum opcode opcode)
>return false;
>  
> return (brw->gen >= 7 && opcode == BRW_OPCODE_IF) ||
> +  (brw->gen >= 8 && opcode == BRW_OPCODE_ELSE) ||
>opcode == BRW_OPCODE_BREAK ||
>opcode == BRW_OPCODE_CONTINUE ||
>opcode == BRW_OPCODE_HALT;
> -- 
> 2.0.0
> 
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Re: [Mesa-dev] [PATCH 05/23] i965/disasm: Improve disassembly of jump targets on Gen6+.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:33:44PM -0700, Kenneth Graunke wrote:
> Previously, flow control instructions generated output like:
> 
> (+f0) if(8) 12 8  null 0x000c0008UD { align16 WE_normal 1Q };
> 
> which included a dissasembly of the register fields, even though those
> are meaningless for flow control instructions---those bits are reused
> for another purpose.
> 
> It also wasn't immediately obvious which number was UIP and which was
> JIP.
> 
> With this patch, we instead output:
> 
> (+f0) if(8)   JIP: 8   UIP: 12  { align16 WE_normal 1Q };
> 
> which is much clearer.

Yeah, makes sense.  Ideally we'd pass a start address to the
disassembler and have it compute the absolute jump addresses too.

Reviewed-by: Kristian Høgsberg 

> The patch also introduces has_uip/has_jip helper functions which clear
> up a some generation/opcode checking mess.
> 
> Signed-off-by: Kenneth Graunke 
> ---
>  src/mesa/drivers/dri/i965/brw_disasm.c | 59 
> +++---
>  1 file changed, 41 insertions(+), 18 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index 569dd68..8966eda 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -100,6 +100,30 @@ const struct opcode_desc opcode_descs[128] = {
> [BRW_OPCODE_ENDIF]= { .name = "endif",   .nsrc = 2, .ndst = 0 },
>  };
>  
> +static bool
> +has_jip(struct brw_context *brw, enum opcode opcode)
> +{
> +   if (brw->gen < 6)
> +  return false;
> +
> +   return opcode == BRW_OPCODE_IF ||
> +  opcode == BRW_OPCODE_ELSE ||
> +  opcode == BRW_OPCODE_ENDIF ||
> +  opcode == BRW_OPCODE_WHILE;
> +}
> +
> +static bool
> +has_uip(struct brw_context *brw, enum opcode opcode)
> +{
> +   if (brw->gen < 6)
> +  return false;
> +
> +   return (brw->gen >= 7 && opcode == BRW_OPCODE_IF) ||
> +  opcode == BRW_OPCODE_BREAK ||
> +  opcode == BRW_OPCODE_CONTINUE ||
> +  opcode == BRW_OPCODE_HALT;
> +}
> +
>  const char *const conditional_modifier[16] = {
> [BRW_CONDITIONAL_NONE] = "",
> [BRW_CONDITIONAL_Z]= ".e",
> @@ -1170,7 +1194,22 @@ brw_disassemble_inst(FILE *file, struct brw_context 
> *brw, brw_inst *inst,
> if (opcode == BRW_OPCODE_SEND && brw->gen < 6)
>format(file, " %d", brw_inst_base_mrf(brw, inst));
>  
> -   if (opcode_descs[opcode].nsrc == 3) {
> +   if (has_uip(brw, opcode)) {
> +  /* Instructions that have UIP also have JIP. */
> +  pad(file, 16);
> +  format(file, "JIP: %d", brw_inst_jip(brw, inst));
> +  pad(file, 32);
> +  format(file, "UIP: %d", brw_inst_uip(brw, inst));
> +   } else if (has_jip(brw, opcode)) {
> +  pad(file, 16);
> +  if (brw->gen >= 7) {
> + format(file, "JIP: %d", brw_inst_jip(brw, inst));
> +  } else {
> + format(file, "JIP: %d", brw_inst_gen6_jump_count(brw, inst));
> +  }
> +   } else if (opcode == BRW_OPCODE_JMPI) {
> +  format(file, " %d", brw_inst_imm_d(brw, inst));
> +   } else if (opcode_descs[opcode].nsrc == 3) {
>pad(file, 16);
>err |= dest_3src(file, brw, inst);
>  
> @@ -1186,29 +1225,13 @@ brw_disassemble_inst(FILE *file, struct brw_context 
> *brw, brw_inst *inst,
>if (opcode_descs[opcode].ndst > 0) {
>   pad(file, 16);
>   err |= dest(file, brw, inst);
> -  } else if (brw->gen == 7 && (opcode == BRW_OPCODE_ELSE ||
> -   opcode == BRW_OPCODE_ENDIF ||
> -   opcode == BRW_OPCODE_WHILE)) {
> - format(file, " %d", brw_inst_jip(brw, inst));
> -  } else if (brw->gen == 6 && (opcode == BRW_OPCODE_IF ||
> -   opcode == BRW_OPCODE_ELSE ||
> -   opcode == BRW_OPCODE_ENDIF ||
> -   opcode == BRW_OPCODE_WHILE)) {
> - format(file, " %d", brw_inst_gen6_jump_count(brw, inst));
> -  } else if ((brw->gen >= 6 && (opcode == BRW_OPCODE_BREAK ||
> -opcode == BRW_OPCODE_CONTINUE ||
> -opcode == BRW_OPCODE_HALT)) ||
> - (brw->gen == 7 && opcode == BRW_OPCODE_IF)) {
> - format(file, " %d %d", brw_inst_uip(brw, inst),
> -brw_inst_jip(brw, inst));
> -  } else if (opcode == BRW_OPCODE_JMPI) {
> - format(file, " %d", brw_inst_imm_d(brw, inst));
>}
>  
>if (opcode_descs[opcode].nsrc > 0) {
>   pad(file, 32);
>   err |= src0(file, brw, inst);
>}
> +
>if (opcode_descs[opcode].nsrc > 1) {
>   pad(file, 48);
>   err |= src1(file, brw, inst);
> -- 
> 2.0.0
> 
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mes

Re: [Mesa-dev] [PATCH 06/23] i965/disasm: Properly disassemble jump targets on Gen4-5.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:33:45PM -0700, Kenneth Graunke wrote:
> Previously, our dissasembly for flow control instructions looked like:
> 
> 0x0040: else(8) ip  65540D { align16 switch };
> 
> It didn't print InstCount properly for ELSE/ENDIF, and didn't even
> attempt to disassemble PopCount.
> 
> Now it looks like:
> 
> 0x0040: else(8) Jump: 4 Pop: 1 { align16 switch };
> 
> which is much more readable.
> 
> Signed-off-by: Kenneth Graunke 

Reviewed-by: Kristian Høgsberg 

> ---
>  src/mesa/drivers/dri/i965/brw_disasm.c | 15 +++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index 8966eda..7773ad9 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -1207,6 +1207,21 @@ brw_disassemble_inst(FILE *file, struct brw_context 
> *brw, brw_inst *inst,
>} else {
>   format(file, "JIP: %d", brw_inst_gen6_jump_count(brw, inst));
>}
> +   } else if (brw->gen < 6 && (opcode == BRW_OPCODE_BREAK ||
> +   opcode == BRW_OPCODE_CONTINUE ||
> +   opcode == BRW_OPCODE_ELSE)) {
> +  pad(file, 16);
> +  format(file, "Jump: %d", brw_inst_gen4_jump_count(brw, inst));
> +  pad(file, 32);
> +  format(file, "Pop: %d", brw_inst_gen4_pop_count(brw, inst));
> +   } else if (brw->gen < 6 && (opcode == BRW_OPCODE_IF ||
> +   opcode == BRW_OPCODE_IFF ||
> +   opcode == BRW_OPCODE_HALT)) {
> +  pad(file, 16);
> +  format(file, "Jump: %d", brw_inst_gen4_pop_count(brw, inst));
> +   } else if (brw->gen < 6 && opcode == BRW_OPCODE_ENDIF) {
> +  pad(file, 16);
> +  format(file, "Pop: %d", brw_inst_gen4_pop_count(brw, inst));
> } else if (opcode == BRW_OPCODE_JMPI) {
>format(file, " %d", brw_inst_imm_d(brw, inst));
> } else if (opcode_descs[opcode].nsrc == 3) {
> -- 
> 2.0.0
> 
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Re: [Mesa-dev] [PATCH 04/23] i965/disasm: Add support for new Gen8+ register types.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:33:43PM -0700, Kenneth Graunke wrote:
> While we're at it, use proper names rather than magic numbers for the
> existing fields.
> 
> Signed-off-by: Kenneth Graunke 

That's a lot less magic.

Reviewed-by: Kristian Høgsberg 

> ---
>  src/mesa/drivers/dri/i965/brw_disasm.c | 40 
> --
>  1 file changed, 24 insertions(+), 16 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index bb69c0e..569dd68 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -248,14 +248,18 @@ static const char *const access_mode[2] = {
> [1] = "align16",
>  };
>  
> -static const char *const reg_encoding[8] = {
> -   [0] = "UD",
> -   [1] = "D",
> -   [2] = "UW",
> -   [3] = "W",
> -   [4] = "UB",
> -   [5] = "B",
> -   [7] = "F"
> +static const char * const reg_encoding[] = {
> +   [BRW_HW_REG_TYPE_UD]  = "UD",
> +   [BRW_HW_REG_TYPE_D]   = "D",
> +   [BRW_HW_REG_TYPE_UW]  = "UW",
> +   [BRW_HW_REG_TYPE_W]   = "W",
> +   [BRW_HW_REG_NON_IMM_TYPE_UB]  = "UB",
> +   [BRW_HW_REG_NON_IMM_TYPE_B]   = "B",
> +   [GEN7_HW_REG_NON_IMM_TYPE_DF] = "DF",
> +   [BRW_HW_REG_TYPE_F]   = "F",
> +   [GEN8_HW_REG_TYPE_UQ] = "UQ",
> +   [GEN8_HW_REG_TYPE_Q]  = "Q",
> +   [GEN8_HW_REG_NON_IMM_TYPE_HF] = "HF",
>  };
>  
>  static const char *const three_source_reg_encoding[] = {
> @@ -264,14 +268,18 @@ static const char *const three_source_reg_encoding[] = {
> [BRW_3SRC_TYPE_UD] = "UD",
>  };
>  
> -const int reg_type_size[8] = {
> -   [0] = 4,
> -   [1] = 4,
> -   [2] = 2,
> -   [3] = 2,
> -   [4] = 1,
> -   [5] = 1,
> -   [7] = 4
> +const int reg_type_size[] = {
> +   [BRW_HW_REG_TYPE_UD]  = 4,
> +   [BRW_HW_REG_TYPE_D]   = 4,
> +   [BRW_HW_REG_TYPE_UW]  = 2,
> +   [BRW_HW_REG_TYPE_W]   = 2,
> +   [BRW_HW_REG_NON_IMM_TYPE_UB]  = 1,
> +   [BRW_HW_REG_NON_IMM_TYPE_B]   = 1,
> +   [GEN7_HW_REG_NON_IMM_TYPE_DF] = 8,
> +   [BRW_HW_REG_TYPE_F]   = 4,
> +   [GEN8_HW_REG_TYPE_UQ] = 8,
> +   [GEN8_HW_REG_TYPE_Q]  = 8,
> +   [GEN8_HW_REG_NON_IMM_TYPE_HF] = 2,
>  };
>  
>  static const char *const reg_file[4] = {
> -- 
> 2.0.0
> 
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Re: [Mesa-dev] [PATCH 01/23] i965/disasm: Eliminate opcode pointer.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:33:40PM -0700, Kenneth Graunke wrote:
> opcode is just a pointer to opcode_descs; we may as well use that
> directly.
> 
> Signed-off-by: Kenneth Graunke 

Reviewed-by: Kristian Høgsberg 

> ---
>  src/mesa/drivers/dri/i965/brw_disasm.c | 15 +++
>  1 file changed, 7 insertions(+), 8 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index 2e02732..f970d02 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -99,7 +99,6 @@ const struct opcode_desc opcode_descs[128] = {
>  [BRW_OPCODE_DO] = { .name = "do", .nsrc = 0, .ndst = 0 },
>  [BRW_OPCODE_ENDIF] = { .name = "endif", .nsrc = 2, .ndst = 0 },
>  };
> -static const struct opcode_desc *opcode = opcode_descs;
>  
>  const char * const conditional_modifier[16] = {
>  [BRW_CONDITIONAL_NONE] = "",
> @@ -525,11 +524,11 @@ static int control (FILE *file, const char *name, const 
> char * const ctrl[],
>  
>  static int print_opcode (FILE *file, int id)
>  {
> -if (!opcode[id].name) {
> +if (!opcode_descs[id].name) {
>   format (file, "*** invalid opcode value %d ", id);
>   return 1;
>  }
> -string (file, opcode[id].name);
> +string (file, opcode_descs[id].name);
>  return 0;
>  }
>  
> @@ -1171,7 +1170,7 @@ brw_disassemble_inst(FILE *file, struct brw_context 
> *brw, brw_inst *inst,
>  if (brw_inst_opcode(brw, inst) == BRW_OPCODE_SEND && brw->gen < 6)
>   format (file, " %d", brw_inst_base_mrf(brw, inst));
>  
> -if (opcode[brw_inst_opcode(brw, inst)].nsrc == 3) {
> +if (opcode_descs[brw_inst_opcode(brw, inst)].nsrc == 3) {
> pad (file, 16);
> err |= dest_3src (file, brw, inst);
>  
> @@ -1184,7 +1183,7 @@ brw_disassemble_inst(FILE *file, struct brw_context 
> *brw, brw_inst *inst,
> pad (file, 64);
> err |= src2_3src (file, brw, inst);
>  } else {
> -   if (opcode[brw_inst_opcode(brw, inst)].ndst > 0) {
> +   if (opcode_descs[brw_inst_opcode(brw, inst)].ndst > 0) {
> pad (file, 16);
> err |= dest (file, brw, inst);
> } else if (brw->gen == 7 && (brw_inst_opcode(brw, inst) == 
> BRW_OPCODE_ELSE ||
> @@ -1205,11 +1204,11 @@ brw_disassemble_inst(FILE *file, struct brw_context 
> *brw, brw_inst *inst,
> format (file, " %d", brw_inst_imm_d(brw, inst));
> }
>  
> -   if (opcode[brw_inst_opcode(brw, inst)].nsrc > 0) {
> +   if (opcode_descs[brw_inst_opcode(brw, inst)].nsrc > 0) {
> pad (file, 32);
> err |= src0 (file, brw, inst);
> }
> -   if (opcode[brw_inst_opcode(brw, inst)].nsrc > 1) {
> +   if (opcode_descs[brw_inst_opcode(brw, inst)].nsrc > 1) {
> pad (file, 48);
> err |= src1 (file, brw, inst);
> }
> @@ -1413,7 +1412,7 @@ brw_disassemble_inst(FILE *file, struct brw_context 
> *brw, brw_inst *inst,
>   err |= qtr_ctrl (file, brw, inst);
>   else {
>   if (brw_inst_qtr_control(brw, inst) == BRW_COMPRESSION_COMPRESSED &&
> - opcode[brw_inst_opcode(brw, inst)].ndst > 0 &&
> + opcode_descs[brw_inst_opcode(brw, inst)].ndst > 0 &&
>   brw_inst_dst_reg_file(brw, inst) == BRW_MESSAGE_REGISTER_FILE &&
>   brw_inst_dst_da_reg_nr(brw, inst) & (1 << 7)) {
>   format (file, " compr4");
> -- 
> 2.0.0
> 
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Re: [Mesa-dev] [PATCH 02/23] i965/disasm: Create an "opcode" temporary.

[Kristian Høgsberg]

On Sat, Jun 28, 2014 at 09:33:41PM -0700, Kenneth Graunke wrote:
> This saves typing brw_inst_opcode(brw, inst) everywhere.

Reviewed-by: Kristian Høgsberg 

> 
> Signed-off-by: Kenneth Graunke 
> ---
>  src/mesa/drivers/dri/i965/brw_disasm.c | 61 
> +-
>  1 file changed, 30 insertions(+), 31 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index f970d02..a050e15 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -1115,6 +1115,8 @@ brw_disassemble_inst(FILE *file, struct brw_context 
> *brw, brw_inst *inst,
>  int  err = 0;
>  int space = 0;
>  
> +const enum opcode opcode = brw_inst_opcode(brw, inst);
> +
>  if (brw_inst_pred_control(brw, inst)) {
>   string (file, "(");
>   err |= control (file, "predicate inverse", pred_inv,
> @@ -1131,19 +1133,18 @@ brw_disassemble_inst(FILE *file, struct brw_context 
> *brw, brw_inst *inst,
>   string (file, ") ");
>  }
>  
> -err |= print_opcode (file, brw_inst_opcode(brw, inst));
> +err |= print_opcode (file, opcode);
>  err |= control (file, "saturate", saturate, brw_inst_saturate(brw, inst),
>NULL);
>  
>  err |= control (file, "debug control", debug_ctrl,
>brw_inst_debug_control(brw, inst), NULL);
>  
> -if (brw_inst_opcode(brw, inst) == BRW_OPCODE_MATH) {
> +if (opcode == BRW_OPCODE_MATH) {
>   string (file, " ");
>   err |= control (file, "function", math_function,
>   brw_inst_math_function(brw, inst), NULL);
> -} else if (brw_inst_opcode(brw, inst) != BRW_OPCODE_SEND &&
> -brw_inst_opcode(brw, inst) != BRW_OPCODE_SENDC) {
> +} else if (opcode != BRW_OPCODE_SEND && opcode != BRW_OPCODE_SENDC) {
>   err |= control (file, "conditional modifier", conditional_modifier,
>   brw_inst_cond_modifier(brw, inst), NULL);
>  
> @@ -1152,25 +1153,25 @@ brw_disassemble_inst(FILE *file, struct brw_context 
> *brw, brw_inst *inst,
>   * control flow doesn't update flags.
>   */
>   if (brw_inst_cond_modifier(brw, inst) &&
> -(brw->gen < 6 || (brw_inst_opcode(brw, inst) != BRW_OPCODE_SEL &&
> - brw_inst_opcode(brw, inst) != BRW_OPCODE_IF &&
> - brw_inst_opcode(brw, inst) != BRW_OPCODE_WHILE))) {
> +(brw->gen < 6 || (opcode != BRW_OPCODE_SEL &&
> + opcode != BRW_OPCODE_IF &&
> + opcode != BRW_OPCODE_WHILE))) {
>   format (file, ".f%d", brw->gen >= 7 ? brw_inst_flag_reg_nr(brw, 
> inst) : 0);
>   if (brw_inst_flag_subreg_nr(brw, inst))
>   format (file, ".%d", brw_inst_flag_subreg_nr(brw, inst));
>  }
>  }
>  
> -if (brw_inst_opcode(brw, inst) != BRW_OPCODE_NOP) {
> +if (opcode != BRW_OPCODE_NOP) {
>   string (file, "(");
>   err |= control (file, "execution size", exec_size, 
> brw_inst_exec_size(brw, inst), NULL);
>   string (file, ")");
>  }
>  
> -if (brw_inst_opcode(brw, inst) == BRW_OPCODE_SEND && brw->gen < 6)
> +if (opcode == BRW_OPCODE_SEND && brw->gen < 6)
>   format (file, " %d", brw_inst_base_mrf(brw, inst));
>  
> -if (opcode_descs[brw_inst_opcode(brw, inst)].nsrc == 3) {
> +if (opcode_descs[opcode].nsrc == 3) {
> pad (file, 16);
> err |= dest_3src (file, brw, inst);
>  
> @@ -1183,39 +1184,38 @@ brw_disassemble_inst(FILE *file, struct brw_context 
> *brw, brw_inst *inst,
> pad (file, 64);
> err |= src2_3src (file, brw, inst);
>  } else {
> -   if (opcode_descs[brw_inst_opcode(brw, inst)].ndst > 0) {
> +   if (opcode_descs[opcode].ndst > 0) {
> pad (file, 16);
> err |= dest (file, brw, inst);
> -   } else if (brw->gen == 7 && (brw_inst_opcode(brw, inst) == 
> BRW_OPCODE_ELSE ||
> - brw_inst_opcode(brw, inst) == 
> BRW_OPCODE_ENDIF ||
> - brw_inst_opcode(brw, inst) == 
> BRW_OPCODE_WHILE)) {
> +   } else if (brw->gen == 7 && (opcode == BRW_OPCODE_ELSE ||
> + opcode == BRW_OPCODE_ENDIF ||
> + opcode == BRW_OPCODE_WHILE)) {
> format (file, " %d", brw_inst_jip(brw, inst));
> -   } else if (brw->gen == 6 && (brw_inst_opcode(brw, inst) == 
> BRW_OPCODE_IF ||
> - brw_inst_opcode(brw, inst) == 
> BRW_OPCODE_ELSE ||
> - brw_inst_opcode(brw, inst) == 
> BRW_OPCODE_ENDIF ||
> - brw_inst_opcode(brw, inst) == 
> BRW_OPCODE_WHILE)) {
> +   } else if (brw->gen == 6 && (opcode == BRW_OPCODE_IF ||
> + opcode == BRW_OPCODE_ELSE ||
> + opcode == BRW_OPCODE_ENDIF ||

Re: [Mesa-dev] [PATCH 3/4] i965/fs: Mark predicated PLN instructions with dependency hints.

[Kristian Høgsberg]

On Sun, Jun 29, 2014 at 11:18:16PM -0700, Matt Turner wrote:
> To implement the unlit_centroid_workaround, previously we emitted
> 
>(+f0) pln(8) g20<1>F g16.4<0,1,0>F g4<8,8,1>F { align1 1Q };
>(-f0) pln(8) g20<1>F g16.4<0,1,0>F g2<8,8,1>F { align1 1Q };
> 
> where the flag register contains the channel enable bits from g0.
> 
> Since the predicates are complementary, the pair of pln instructions
> write to non-overlapping components of the destination, which is the
> case that the dependency control hints are designed for.
> 
> Typically setting dependency control hints on predicated instructions
> isn't safe (if an instruction doesn't execute due to the predicate, it
> won't update the scoreboard, leaving it in a bad state) but since we
> must have at least one channel executing (i.e., +f0 is true for some
> channel) by virtue of the fact that the thread is running, we can put
> the +f0 pln instruction last and set the hints:
> 
>(-f0) pln(8) g20<1>F g16.4<0,1,0>F g2<8,8,1>F { align1 NoDDClr 1Q };
>(+f0) pln(8) g20<1>F g16.4<0,1,0>F g4<8,8,1>F { align1 NoDDChk 1Q };

Reviewed-by: Kristian Høgsberg 

> ---
>  src/mesa/drivers/dri/i965/brw_fs.cpp | 13 +
>  1 file changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
> b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index 3b7a170..5a3d1d3 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -1178,15 +1178,20 @@ fs_visitor::emit_general_interpolation(ir_variable 
> *ir)
>  
>fs_inst *inst;
>inst = emit_linterp(attr, fs_reg(interp), 
> interpolation_mode,
> +  false, false);
> +  inst->predicate = BRW_PREDICATE_NORMAL;
> +  inst->predicate_inverse = true;
> +  if (brw->has_pln)
> + inst->no_dd_clear = true;
> +
> +  inst = emit_linterp(attr, fs_reg(interp), 
> interpolation_mode,
>ir->data.centroid && 
> !key->persample_shading,
>ir->data.sample || 
> key->persample_shading);
>inst->predicate = BRW_PREDICATE_NORMAL;
>inst->predicate_inverse = false;
> +  if (brw->has_pln)
> + inst->no_dd_check = true;
>  
> -  inst = emit_linterp(attr, fs_reg(interp), 
> interpolation_mode,
> -  false, false);
> -  inst->predicate = BRW_PREDICATE_NORMAL;
> -  inst->predicate_inverse = true;
> } else {
>emit_linterp(attr, fs_reg(interp), interpolation_mode,
> ir->data.centroid && !key->persample_shading,
> -- 
> 1.8.3.2
> 
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Re: [Mesa-dev] [PATCH 2/4] i965/fs: Predicate PLN instructions used in unlit centroid WA.

[Kristian Høgsberg]

On Sun, Jun 29, 2014 at 11:18:15PM -0700, Matt Turner wrote:
> Maybe lets us skip some PLN instructions if whole subspans are disabled?

Reviewed-by: Kristian Høgsberg 

> ---
>  src/mesa/drivers/dri/i965/brw_fs.cpp | 20 ++--
>  1 file changed, 14 insertions(+), 6 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
> b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index 1d58615..3b7a170 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -1168,9 +1168,6 @@ fs_visitor::emit_general_interpolation(ir_variable *ir)
>   /* Smooth/noperspective interpolation case. */
>   for (unsigned int k = 0; k < type->vector_elements; k++) {
> struct brw_reg interp = interp_reg(location, k);
> -   emit_linterp(attr, fs_reg(interp), interpolation_mode,
> -ir->data.centroid && !key->persample_shading,
> -ir->data.sample || key->persample_shading);
> if (brw->needs_unlit_centroid_workaround && 
> ir->data.centroid) {
>/* Get the pixel/sample mask into f0 so that we know
> * which pixels are lit.  Then, for each channel that is
> @@ -1178,11 +1175,22 @@ fs_visitor::emit_general_interpolation(ir_variable 
> *ir)
> * data.
> */
>emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS);
> -  fs_inst *inst = emit_linterp(attr, fs_reg(interp),
> -   interpolation_mode,
> -   false, false);
> +
> +  fs_inst *inst;
> +  inst = emit_linterp(attr, fs_reg(interp), 
> interpolation_mode,
> +  ir->data.centroid && 
> !key->persample_shading,
> +  ir->data.sample || 
> key->persample_shading);
> +  inst->predicate = BRW_PREDICATE_NORMAL;
> +  inst->predicate_inverse = false;
> +
> +  inst = emit_linterp(attr, fs_reg(interp), 
> interpolation_mode,
> +  false, false);
>inst->predicate = BRW_PREDICATE_NORMAL;
>inst->predicate_inverse = true;
> +   } else {
> +  emit_linterp(attr, fs_reg(interp), interpolation_mode,
> +   ir->data.centroid && !key->persample_shading,
> +   ir->data.sample || key->persample_shading);
> }
> if (brw->gen < 6 && interpolation_mode == 
> INTERP_QUALIFIER_SMOOTH) {
>emit(BRW_OPCODE_MUL, attr, attr, this->pixel_w);
> -- 
> 1.8.3.2
> 
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Re: [Mesa-dev] [PATCH 1/4] i965/fs: Add no_dd_{clear, check} fields to fs_inst.

[Kristian Høgsberg]

On Sun, Jun 29, 2014 at 11:18:14PM -0700, Matt Turner wrote:
> And plumb them through. Also make the assert in the generator look like
> the vec4 one.
> ---
>  src/mesa/drivers/dri/i965/brw_fs.h |  2 ++
>  src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 14 --
>  2 files changed, 10 insertions(+), 6 deletions(-)

Reviewed-by: Kristian Høgsberg 

> diff --git a/src/mesa/drivers/dri/i965/brw_fs.h 
> b/src/mesa/drivers/dri/i965/brw_fs.h
> index 3d0da23..58e7175 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.h
> +++ b/src/mesa/drivers/dri/i965/brw_fs.h
> @@ -239,6 +239,8 @@ public:
> bool force_uncompressed:1;
> bool force_sechalf:1;
> bool force_writemask_all:1;
> +   bool no_dd_clear:1;
> +   bool no_dd_check:1;
>  };
>  
>  /**
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp 
> b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> index 871fc95..8c5fe07 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> @@ -1753,14 +1753,16 @@ fs_generator::generate_code(exec_list *instructions)
>   break;
>}
>  
> -  if (inst->conditional_mod) {
> - /* Set the conditional modifier on the last instruction we 
> generated.
> -  * Also, make sure we only emitted one instruction - anything else
> -  * doesn't make sense.
> -  */
> - assert(p->next_insn_offset == last_insn_offset + 16);
> +  if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
> + assert(p->next_insn_offset == last_insn_offset + 16 ||
> +!"conditional_mod, no_dd_check, or no_dd_clear set for IR "
> + "emitting more than 1 instruction");
> +
>   brw_inst *last = &p->store[last_insn_offset / 16];
> +
>   brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
> + brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
> + brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
>}
> }
>  
> -- 
> 1.8.3.2
> 
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Re: [Mesa-dev] [PATCH 4/4] i965/fs: Disable unlit_centroid_workaround on Haswell.

[Matt Turner]

On Mon, Jun 30, 2014 at 12:31 AM, Kenneth Graunke  wrote:
> On Sunday, June 29, 2014 11:18:17 PM Matt Turner wrote:
>
>> Although the HSW PRM shows it, the BSpec lists this workaround as being
>
>> for Ivybridge only.
>
>>
>
>> total instructions in shared programs: 1994951 -> 1993675 (-0.06%)
>
>> instructions in affected programs: 27325 -> 26049 (-4.67%)
>
>> ---
>
>> src/mesa/drivers/dri/i965/brw_device_info.c | 6 --
>
>> 1 file changed, 4 insertions(+), 2 deletions(-)
>
>
>
> Were you able to observe something breaking on Ivybridge with the workaround
> dropped (proving that we can observe that the workaround is necessary)?

As I said in the cover letter, no. The tests mentioned by Paul still
pass with the workaround disabled on Ivy Bridge.
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Re: [Mesa-dev] [PATCH 0/6] Enable Pixman for Mesa

[Jason Ekstrand]

On Mon, Jun 30, 2014 at 3:18 AM, Juha-Pekka Heikkila <
juhapekka.heikk...@gmail.com> wrote:

> On 25.06.2014 23:47, Matt Turner wrote:
> > On Wed, Jun 25, 2014 at 5:38 AM, Juha-Pekka Heikkila
> >  wrote:
> >> This is my old set which enable using Pixman on Mesa for some texture
> >> conversion fast paths. As is this passes Piglit quick set on my IVB.
> >
> > Pixman doesn't actually have fast paths for swizzling, like we're
> > using in this series. I imagine improvements we're seeing here are
> > simply because Mesa's code is slow.
> >
> > I never pursued this idea for a couple of reasons. One is that we
> > should probably use the GPU to do the conversions in the ideal case.
> > Also, pixman doesn't support floating-point formats. Some work has
> > been done in the last year or so to make this much easier to implement
> > though.
> >
> > The first reason above shouldn't block other improvements, and the
> > second reason is fixable with some contributions to pixman. And pixman
> > is really a trivial dependency, so that shouldn't be a problem.
> >
> > Soren thinks this is worth doing and I trust him.
> >
> > I think a worthwhile goal would be to add support to pixman for doing
> > a bunch of the conversions Mesa requires and then dropping the code in
> > Mesa. Are you interested in doing that? I know Jason (Cc'd) is working
> > on cleaning up a bunch of this code.
> >
> > Are you planning to contribute swizzling fast paths to pixman? The
> > power-of-two-sized-component formats should be really easy to optimize
> > using the SSE shuffle instructions.
> >
>
> Hi Matt, Jason,
>
> Which parts of texture conversion are you Jason touching, does your
> changes overlap with the patches I put here?
>

Juha-Pekka,
Sorry, I haven't had much of a chance to look at your patchs.  My stuff is
probably going to touch all of the texture upload code and (hopefully) give
us some speed improvements all-around.  In particular, I'm hoping to reduce
conversion to/from floating point and add generalized fast-paths whenever
possible.  That said, going directly to pixman may still be better in some
certain cases.  As Ken said, I'm not sure if pixman has actual fast-paths,
so it would be worth looking into what Mesa is doing different from Pixman.


>
> As for doing (more) Pixmanization for Mesa on this part I think I can do
> it and start to look into making patches for Pixman to support Mesa
> better. I hope to be away from keyboards for few weeks so it'll be
> August when I start anything on this.


Actually, that will work out fairly well.  I'm going to be hitting the
texture upload code pretty hard the next week or two and should have
results by the time you have a chance to start back up.  That way we won't
be stepping on each other too badly.

Also, what was your set-up for doing power comparisons?  As I dive into
this, I'd like to see how my results compare.

Thanks,
--Jason Ekstrand
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Re: [Mesa-dev] [PATCH 2/4] gallium: add cap to show that fs can accept layer/viewport inputs

[Ilia Mirkin]

Looks like it'll be a while before someone can look at my r600 patch
which makes layer/viewport available in the fragment shader. Roland,
would you be OK with a version of this patch which adds a new CAP for
viewport/layer support in FS? (To be enabled only on nv50/nvc0 for
now.) The cap can later be removed.

On Sun, Jun 22, 2014 at 11:10 AM, Ilia Mirkin  wrote:
> Signed-off-by: Ilia Mirkin 
> ---
>  src/gallium/docs/source/screen.rst   | 2 ++
>  src/gallium/drivers/freedreno/freedreno_screen.c | 1 +
>  src/gallium/drivers/i915/i915_screen.c   | 1 +
>  src/gallium/drivers/ilo/ilo_screen.c | 1 +
>  src/gallium/drivers/llvmpipe/lp_screen.c | 1 +
>  src/gallium/drivers/nouveau/nv30/nv30_screen.c   | 1 +
>  src/gallium/drivers/nouveau/nv50/nv50_screen.c   | 1 +
>  src/gallium/drivers/nouveau/nvc0/nvc0_screen.c   | 1 +
>  src/gallium/drivers/r300/r300_screen.c   | 1 +
>  src/gallium/drivers/r600/r600_pipe.c | 1 +
>  src/gallium/drivers/radeonsi/si_pipe.c   | 1 +
>  src/gallium/drivers/softpipe/sp_screen.c | 1 +
>  src/gallium/drivers/svga/svga_screen.c   | 1 +
>  src/gallium/include/pipe/p_defines.h | 3 ++-
>  src/mesa/state_tracker/st_extensions.c   | 1 +
>  15 files changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/docs/source/screen.rst 
> b/src/gallium/docs/source/screen.rst
> index 1a80b04..ebebfe8 100644
> --- a/src/gallium/docs/source/screen.rst
> +++ b/src/gallium/docs/source/screen.rst
> @@ -205,6 +205,8 @@ The integer capabilities:
>  * ``PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION``: Whether
>TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION is supported, which disables 
> clipping
>and viewport transformation.
> +* ``PIPE_CAP_TGSI_FS_LAYER_VIEWPORT``: Whether the fragment shader can accept
> +  ``TGSI_SEMANTIC_LAYER`` and ``TGSI_SEMANTIC_VIEWPORT_INDEX`` inputs.
>
>
>  .. _pipe_capf:
> diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c 
> b/src/gallium/drivers/freedreno/freedreno_screen.c
> index e7a185d..fa201ce 100644
> --- a/src/gallium/drivers/freedreno/freedreno_screen.c
> +++ b/src/gallium/drivers/freedreno/freedreno_screen.c
> @@ -215,6 +215,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum 
> pipe_cap param)
> case PIPE_CAP_SAMPLE_SHADING:
> case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
> case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
> +   case PIPE_CAP_TGSI_FS_LAYER_VIEWPORT:
> return 0;
>
> /* Stream output. */
> diff --git a/src/gallium/drivers/i915/i915_screen.c 
> b/src/gallium/drivers/i915/i915_screen.c
> index 79d8659..b776c49 100644
> --- a/src/gallium/drivers/i915/i915_screen.c
> +++ b/src/gallium/drivers/i915/i915_screen.c
> @@ -223,6 +223,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap 
> cap)
> case PIPE_CAP_SAMPLE_SHADING:
> case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
> case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
> +   case PIPE_CAP_TGSI_FS_LAYER_VIEWPORT:
>return 0;
>
> case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
> diff --git a/src/gallium/drivers/ilo/ilo_screen.c 
> b/src/gallium/drivers/ilo/ilo_screen.c
> index b08ae20..4b1fe35 100644
> --- a/src/gallium/drivers/ilo/ilo_screen.c
> +++ b/src/gallium/drivers/ilo/ilo_screen.c
> @@ -442,6 +442,7 @@ ilo_get_param(struct pipe_screen *screen, enum pipe_cap 
> param)
> case PIPE_CAP_SAMPLE_SHADING:
> case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
> case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
> +   case PIPE_CAP_TGSI_FS_LAYER_VIEWPORT:
>return 0;
>
> default:
> diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c 
> b/src/gallium/drivers/llvmpipe/lp_screen.c
> index a6b712a..3ccbcd3 100644
> --- a/src/gallium/drivers/llvmpipe/lp_screen.c
> +++ b/src/gallium/drivers/llvmpipe/lp_screen.c
> @@ -244,6 +244,7 @@ llvmpipe_get_param(struct pipe_screen *screen, enum 
> pipe_cap param)
> case PIPE_CAP_SAMPLE_SHADING:
> case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
> case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
> +   case PIPE_CAP_TGSI_FS_LAYER_VIEWPORT:
>return 0;
> case PIPE_CAP_FAKE_SW_MSAA:
> return 1;
> diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c 
> b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
> index 5c3d783..db4755b 100644
> --- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c
> +++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
> @@ -146,6 +146,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum 
> pipe_cap param)
> case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
> case PIPE_CAP_USER_VERTEX_BUFFERS:
> case PIPE_CAP_COMPUTE:
> +   case PIPE_CAP_TGSI_FS_LAYER_VIEWPORT:
>return 0;
> }
>
> diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c 
> b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
> index c09a8c6..68becec 100644
> --- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
> +++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c

[Mesa-dev] [PATCH] mesa: Fix regression introduced by commit "mesa: fix packing of float texels to GL_SHORT/GL_BYTE".

[Pavel Popov]

This commit "mesa: fix packing of float texels to GL_SHORT/GL_BYTE" replaced 
*_TO_BYTE to *_TO_BYTE_TEX because *_TO_FLOAT_TEX are used to unpack the texels 
to floats.
In this case *_TO_FLOATZ in function extract_float_rgba also should be replaced 
to *_TO_FLOAT_TEX. Underline that these macros automatically preserve zero when 
converting.

The regression was observed on 3 oglconform tests:
snorm-textures basic.getTexImage
snorm-textures advanced.mipmap.manual.getTex
snorm-textures advanced.mipmap.upload.getTex

Signed-off-by: Pavel Popov 
---
 src/mesa/main/pack.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mesa/main/pack.c b/src/mesa/main/pack.c
index 1df6568..70c8b93 100644
--- a/src/mesa/main/pack.c
+++ b/src/mesa/main/pack.c
@@ -3253,10 +3253,10 @@ extract_float_rgba(GLuint n, GLfloat rgba[][4],
  PROCESS(aSrc, ACOMP, 1.0F, 255, GLubyte, UBYTE_TO_FLOAT);
  break;
   case GL_BYTE:
- PROCESS(rSrc, RCOMP, 0.0F,   0, GLbyte, BYTE_TO_FLOATZ);
- PROCESS(gSrc, GCOMP, 0.0F,   0, GLbyte, BYTE_TO_FLOATZ);
- PROCESS(bSrc, BCOMP, 0.0F,   0, GLbyte, BYTE_TO_FLOATZ);
- PROCESS(aSrc, ACOMP, 1.0F, 127, GLbyte, BYTE_TO_FLOATZ);
+ PROCESS(rSrc, RCOMP, 0.0F,   0, GLbyte, BYTE_TO_FLOAT_TEX);
+ PROCESS(gSrc, GCOMP, 0.0F,   0, GLbyte, BYTE_TO_FLOAT_TEX);
+ PROCESS(bSrc, BCOMP, 0.0F,   0, GLbyte, BYTE_TO_FLOAT_TEX);
+ PROCESS(aSrc, ACOMP, 1.0F, 127, GLbyte, BYTE_TO_FLOAT_TEX);
  break;
   case GL_UNSIGNED_SHORT:
  PROCESS(rSrc, RCOMP, 0.0F,  0, GLushort, USHORT_TO_FLOAT);
@@ -3265,10 +3265,10 @@ extract_float_rgba(GLuint n, GLfloat rgba[][4],
  PROCESS(aSrc, ACOMP, 1.0F, 0x, GLushort, USHORT_TO_FLOAT);
  break;
   case GL_SHORT:
- PROCESS(rSrc, RCOMP, 0.0F, 0, GLshort, SHORT_TO_FLOATZ);
- PROCESS(gSrc, GCOMP, 0.0F, 0, GLshort, SHORT_TO_FLOATZ);
- PROCESS(bSrc, BCOMP, 0.0F, 0, GLshort, SHORT_TO_FLOATZ);
- PROCESS(aSrc, ACOMP, 1.0F, 32767, GLshort, SHORT_TO_FLOATZ);
+ PROCESS(rSrc, RCOMP, 0.0F, 0, GLshort, SHORT_TO_FLOAT_TEX);
+ PROCESS(gSrc, GCOMP, 0.0F, 0, GLshort, SHORT_TO_FLOAT_TEX);
+ PROCESS(bSrc, BCOMP, 0.0F, 0, GLshort, SHORT_TO_FLOAT_TEX);
+ PROCESS(aSrc, ACOMP, 1.0F, 32767, GLshort, SHORT_TO_FLOAT_TEX);
  break;
   case GL_UNSIGNED_INT:
  PROCESS(rSrc, RCOMP, 0.0F,  0, GLuint, UINT_TO_FLOAT);
-- 
1.9.1



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[Mesa-dev] [Bug 80069] rendering problems: black areas in KDE desktop. [mesa 10.2.1 (not with 10.1.4)]

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=80069

CarlEitsger <4607vrfcr84spd21...@weg-werf-email.de> changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

--- Comment #5 from CarlEitsger <4607vrfcr84spd21...@weg-werf-email.de> ---
With the new mesa version the problem seems to not appear any more:

* mesa 10.2.2-1
* mesa-libgl 10.2.2-1
* intel-dri 10.2.2-1

and (same as before) xf86-video-intel 2.99.912-1.

Thank you, devs!

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[Mesa-dev] [Bug 79706] [TRACKER] Mesa regression tracker

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=79706

Bug 79706 depends on bug 80069, which changed state.

Bug 80069 Summary: rendering problems: black areas in KDE desktop. [mesa 10.2.1 
(not with 10.1.4)]
https://bugs.freedesktop.org/show_bug.cgi?id=80069

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

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Re: [Mesa-dev] [PATCH 0/6] Enable Pixman for Mesa

[Juha-Pekka Heikkila]

On 25.06.2014 23:47, Matt Turner wrote:
> On Wed, Jun 25, 2014 at 5:38 AM, Juha-Pekka Heikkila
>  wrote:
>> This is my old set which enable using Pixman on Mesa for some texture
>> conversion fast paths. As is this passes Piglit quick set on my IVB.
> 
> Pixman doesn't actually have fast paths for swizzling, like we're
> using in this series. I imagine improvements we're seeing here are
> simply because Mesa's code is slow.
> 
> I never pursued this idea for a couple of reasons. One is that we
> should probably use the GPU to do the conversions in the ideal case.
> Also, pixman doesn't support floating-point formats. Some work has
> been done in the last year or so to make this much easier to implement
> though.
> 
> The first reason above shouldn't block other improvements, and the
> second reason is fixable with some contributions to pixman. And pixman
> is really a trivial dependency, so that shouldn't be a problem.
> 
> Soren thinks this is worth doing and I trust him.
> 
> I think a worthwhile goal would be to add support to pixman for doing
> a bunch of the conversions Mesa requires and then dropping the code in
> Mesa. Are you interested in doing that? I know Jason (Cc'd) is working
> on cleaning up a bunch of this code.
> 
> Are you planning to contribute swizzling fast paths to pixman? The
> power-of-two-sized-component formats should be really easy to optimize
> using the SSE shuffle instructions.
> 

Hi Matt, Jason,

Which parts of texture conversion are you Jason touching, does your
changes overlap with the patches I put here?

As for doing (more) Pixmanization for Mesa on this part I think I can do
it and start to look into making patches for Pixman to support Mesa
better. I hope to be away from keyboards for few weeks so it'll be
August when I start anything on this.

/Juha-Pekka
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[Mesa-dev] [PATCH 2/2] i965: Workaround for hardware bug in multi-stream transform feedback.

[Iago Toral Quiroga]

There is a hardware bug that breaks TF recording in multi-stream mode when
emitting vertices to a stream that does not have any varyings to record. If
that happens, and the vertex is the last vertex emitted by the geometry shader,
varying data is not recorded for any stream and primitive queries (transform
feedback written and primitives generated) return 0 for all streams.

This problem could affect a likely scenario where the application uses stream0
only for rendering (no TF) and other streams to capture TF, since in this case
the application would be emitting vertices to stream0 but would not have any
varyings to record for it.

If the vertex is not the last one emitted by the geometry shader, TF will work
fine, but primtive count on that stream will be 0. This is not what we want but
is the expected behavior according to the Ivy Bridge documentation:

"8.3 Stream Output Function:

If a stream has no SO_DECL state defined (NumEntries is 0), incoming
objects targeting that stream are effectively ignored. As there is no
attempt to perform stream output, overflow detection is neither
required nor performed."

These issues can be worked around by configuring at least one fake declaration
for such streams and redirecting their output to a disabled transform feedback
buffer (so that no recording actually happens). This workaround is not perfect
though, since we need to have at least one unused (disabled) TF buffer
available.
---
 src/mesa/drivers/dri/i965/gen7_sol_state.c | 59 ++
 1 file changed, 59 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c 
b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index 1aae659..50169a9 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -189,6 +189,65 @@ gen7_upload_3dstate_so_decl_list(struct brw_context *brw,
  max_decls = decls[stream_id];
}
 
+   /* There is a hardware bug that breaks TF recording in multi-stream mode
+* when emitting vertices to a stream that does not have any varyings to
+* record. If that happens, and the vertex is the last vertex emitted by the
+* geometry shader, varying data is not recorded for any stream and
+* primitive queries (transform feedback written and primitives generated)
+* return 0 for all streams.
+*
+* This problem could affect a likely scenario where the application uses
+* stream0 only for rendering (no TF) and other streams to capture TF, since
+* in this case the application would be emitting vertices to stream0 but
+* would not have any varyings to record for it.
+*
+* If the vertex is not the last one emitted by the geometry shader, TF will
+* work fine, but primtive count on that stream will be 0. This is not what
+* we want but is the expected behavior according to the Ivy Bridge
+* documentation:
+*
+*"8.3 Stream Output Function:
+*
+*If a stream has no SO_DECL state defined (NumEntries is 0), incoming
+*objects targeting that stream are effectively ignored. As there is no
+*attempt to perform stream output, overflow detection is neither
+*required nor performed."
+*
+* These issues can be worked around by configuring at least one fake
+* declaration for such streams and redirecting their output to a disabled
+* transform feedback buffer (so that no recording actually happens).
+* This workaround is not perfect though, since we need to have at least one
+* unused (disabled) TF buffer available.
+*/
+   if (ctx->GeometryProgram._Current &&
+   ctx->GeometryProgram._Current->UsesStreams) {
+  int disabled_buffer = -1;
+  bool tf_buffers_checked = false;
+  for (int i = 0; i < MAX_VERTEX_STREAMS; i++) {
+ if (decls[i] > 0)
+continue;
+ /* This stream has no varyings to record: see if we have at least one
+  * disabled TF buffer available
+  */
+ if (!tf_buffers_checked) {
+tf_buffers_checked = true;
+for (int i = 0; i < 4; i++) {
+   if (linked_xfb_info->BufferStride[i] == 0) {
+  disabled_buffer = i;
+  break;
+   }
+}
+ }
+ if (disabled_buffer < 0)
+break;
+ /* We have at least one disabled TF buffer, so redirect output from
+  * this stream to it and add a fake declaration
+  */
+ decls[i] = 1;
+ buffer_mask[i] = 1 << disabled_buffer;
+  }
+   }
+
BEGIN_BATCH(max_decls * 2 + 3);
OUT_BATCH(_3DSTATE_SO_DECL_LIST << 16 | (max_decls * 2 + 1));
 
-- 
1.9.1

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[Mesa-dev] [PATCH 1/2] i965: Disable unused transform feedback buffers.

[Iago Toral Quiroga]

If we are not recording any varying data to a particular transform feedback
buffer, disable it.
---
 src/mesa/drivers/dri/i965/gen7_sol_state.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c 
b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index d2c3ae3..1aae659 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -220,6 +220,8 @@ upload_3dstate_streamout(struct brw_context *brw, bool 
active,
/* BRW_NEW_TRANSFORM_FEEDBACK */
struct gl_transform_feedback_object *xfb_obj =
   ctx->TransformFeedback.CurrentObject;
+   const struct gl_transform_feedback_info *linked_xfb_info =
+  &xfb_obj->shader_program->LinkedTransformFeedback;
uint32_t dw1 = 0, dw2 = 0;
int i;
 
@@ -250,9 +252,9 @@ upload_3dstate_streamout(struct brw_context *brw, bool 
active,
 dw1 |= SO_REORDER_TRAILING;
 
   for (i = 0; i < 4; i++) {
-if (xfb_obj->Buffers[i]) {
-   dw1 |= SO_BUFFER_ENABLE(i);
-}
+ if (xfb_obj->Buffers[i] && linked_xfb_info->BufferStride[i] > 0) {
+dw1 |= SO_BUFFER_ENABLE(i);
+ }
   }
 
   /* We always read the whole vertex.  This could be reduced at some
-- 
1.9.1

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[Mesa-dev] [PATCH 0/2] Workaround for hardware bug in multi-stream transform feedback.

[Iago Toral Quiroga]

These are two patches implementing a work around for the possible hardware bug
I introduced in another e-mail. I think the first patch is valid in any case,
the second one implements the actual workaround but it requires the first patch
for it to work.

We will also write a couple of piglit tests to check this scenario. One in
which this workaround is enough to fix the problem (expected to fail without
these patches), and one in which this workaround won't be enough (expected to
fail with and without the patches).

Iago Toral Quiroga (2):
  i965: Disable unused transform feedback buffers.
  i965: Workaround for hardware bug in multi-stream transform feedback.

 src/mesa/drivers/dri/i965/gen7_sol_state.c | 67 --
 1 file changed, 64 insertions(+), 3 deletions(-)

-- 
1.9.1

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Re: [Mesa-dev] OpenGL on Wayland

[Kenneth Graunke]

On Friday, June 27, 2014 08:08:21 PM Kalrish Bäakjen wrote:
> Hello,
>
> I am working on a project that uses EGL and defers drawing to render
> modules. To maintain compatibility with Wayland and avoid being tied to X,
> I have chosen OpenGL ES 3. As it is difficult for me to find information
> about this API, I would rather use its desktop counterpart; however, as
> said, this would make it impossible to run my application on Wayland.
>
> What is the status of OpenGL on Wayland? Are there any plans on
> emancipating it from GLX?
>
> Thank you, and, please, forgive me if this message does not correspond to
> these lists. Regards,
> Kalrish

You can run desktop OpenGL on Wayland just fine.  As an example, Piglit/Waffle
contains hundreds of small OpenGL applications which at can run on
EGL/Wayland, EGL/X11, or GLX, and decide which to use purely at run-time.

libGL does contain GLX, so there are X build dependencies.  But that doesn't
mean your application is "tied to X".  X does not need to be running.

That said, it would be great if someone who knows dispatch would revisit the
new OpenGL ABI issue.  nVidia put together a great proposal for new separate
libOpenGL.so and libGLX.so libraries, and us Mesa folks have pretty much
dropped the ball. :(

--Ken

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Re: [Mesa-dev] [PATCH 4/4] i965/fs: Disable unlit_centroid_workaround on Haswell.

[Kenneth Graunke]

On Sunday, June 29, 2014 11:18:17 PM Matt Turner wrote:
> Although the HSW PRM shows it, the BSpec lists this workaround as being
> for Ivybridge only.
>
> total instructions in shared programs: 1994951 -> 1993675 (-0.06%)
> instructions in affected programs: 27325 -> 26049 (-4.67%)
> ---
>  src/mesa/drivers/dri/i965/brw_device_info.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)

Were you able to observe something breaking on Ivybridge with the workaround
dropped (proving that we can observe that the workaround is necessary)?

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Re: [Mesa-dev] [PATCH] i965/fs: Let sat-prop ignore live ranges if producer already has sat.

[Kenneth Graunke]

On Sunday, June 29, 2014 11:18:33 PM Matt Turner wrote:
> This sequence (where both x and w are used afterwards) wasn't handled.
>
>mul.sat x, y, z
>...
>mov.sat w, x
>
> We assumed that if x was used after the mov.sat, that we couldn't
> propagate the saturate modifier, but in fact x was already saturated.
>
> So ignore the live range check if the producing instruction already
> saturates its result. Cuts one instruction from hundreds of TF2 shaders.
>
> total instructions in shared programs: 1995631 -> 1994951 (-0.03%)
> instructions in affected programs: 155248 -> 154568 (-0.44%)
> ---
>  src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp | 11 +++
>  1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp index
> 4b5b5ca..079eb2e 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
> @@ -47,8 +47,6 @@ opt_saturate_propagation_local(fs_visitor *v, bblock_t
> *block)
>
>int src_var = v->live_intervals->var_from_reg(&inst->src[0]);
>int src_end_ip = v->live_intervals->end[src_var];
> -  if (src_end_ip > ip && !inst->dst.equals(inst->src[0]))
> - continue;
>
>int scan_ip = ip;
>bool interfered = false;
> @@ -61,10 +59,15 @@ opt_saturate_propagation_local(fs_visitor *v, bblock_t
> *block) scan_inst->dst.reg == inst->src[0].reg &&
>   scan_inst->dst.reg_offset == inst->src[0].reg_offset &&
>   !scan_inst->is_partial_write()) {
> -if (scan_inst->can_do_saturate()) {
> -   scan_inst->saturate = true;
> +if (scan_inst->saturate) {
> inst->saturate = false;
> progress = true;
> +} else if (src_end_ip <= ip || inst->dst.equals(inst->src[0]))
> { +   if (scan_inst->can_do_saturate()) {
> +  scan_inst->saturate = true;
> +  inst->saturate = false;
> +  progress = true;
> +   }
>  }
>  break;
>   }

Reviewed-by: Kenneth Graunke 

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