[Mesa-dev] [PATCH v2 08/10] glsl: A shader cannot redefine or overload built-in functions in GLSL ES 3.00
Create a new search function to look for matching built-in functions by name
and use it for built-in function redefinition or overload in GLSL ES 3.00.
GLSL ES 3.0 spec, chapter 6.1 "Function Definitions", page 71
"A shader cannot redefine or overload built-in functions."
While in GLSL ES 1.0 specification, chapter 8 "Built-in Functions"
"User code can overload the built-in functions but cannot redefine them."
So this check is specific to GLSL ES 3.00.
This patch fixes the following dEQP tests:
dEQP-GLES3.functional.shaders.functions.invalid.overload_builtin_function_vertex
dEQP-GLES3.functional.shaders.functions.invalid.overload_builtin_function_fragment
dEQP-GLES3.functional.shaders.functions.invalid.redefine_builtin_function_vertex
dEQP-GLES3.functional.shaders.functions.invalid.redefine_builtin_function_fragment
No piglit regressions.
Signed-off-by: Samuel Iglesias Gonsalvez
---
src/glsl/ast_to_hir.cpp| 21 +
src/glsl/builtin_functions.cpp | 11 +++
src/glsl/ir.h | 4
3 files changed, 36 insertions(+)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 2c63de0..acb5c76 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -4205,6 +4205,27 @@ ast_function::hir(exec_list *instructions,
emit_function(state, f);
}
+ /* From GLSL ES 3.0 spec, chapter 6.1 "Function Definitions", page 71:
+*
+* "A shader cannot redefine or overload built-in functions."
+*
+* While in GLSL ES 1.0 specification, chapter 8 "Built-in Functions":
+*
+* "User code can overload the built-in functions but cannot redefine
+* them."
+*/
+ if (state->es_shader && state->language_version >= 300) {
+ /* Local shader has no exact candidates; check the built-ins. */
+ _mesa_glsl_initialize_builtin_functions();
+ if (_mesa_glsl_find_builtin_function_by_name(state, name)) {
+ YYLTYPE loc = this->get_location();
+ _mesa_glsl_error(& loc, state,
+ "A shader cannot redefine or overload built-in "
+ "function `%s' in GLSL ES 3.00", name);
+ return NULL;
+ }
+ }
+
/* Verify that this function's signature either doesn't match a previously
* seen signature for a function with the same name, or, if a match is
found,
* that the previously seen signature does not have an associated
definition.
diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp
index fb31dad..b643927 100644
--- a/src/glsl/builtin_functions.cpp
+++ b/src/glsl/builtin_functions.cpp
@@ -4851,6 +4851,17 @@ _mesa_glsl_find_builtin_function(_mesa_glsl_parse_state
*state,
return s;
}
+ir_function *
+_mesa_glsl_find_builtin_function_by_name(_mesa_glsl_parse_state *state,
+ const char *name)
+{
+ ir_function *f;
+ mtx_lock(&builtins_lock);
+ f = builtins.shader->symbols->get_function(name);
+ mtx_unlock(&builtins_lock);
+ return f;
+}
+
gl_shader *
_mesa_glsl_get_builtin_function_shader()
{
diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index 8c3845f..ce35b2b 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -2439,6 +2439,10 @@ extern ir_function_signature *
_mesa_glsl_find_builtin_function(_mesa_glsl_parse_state *state,
const char *name, exec_list
*actual_parameters);
+extern ir_function *
+_mesa_glsl_find_builtin_function_by_name(_mesa_glsl_parse_state *state,
+ const char *name);
+
extern gl_shader *
_mesa_glsl_get_builtin_function_shader(void);
--
2.1.0
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Re: [Mesa-dev] [PATCH v2 08/10] glsl: A shader cannot redefine or overload built-in functions in GLSL ES 3.00
On Thursday, February 19, 2015 09:55:35 AM Samuel Iglesias Gonsalvez wrote: > Create a new search function to look for matching built-in functions by name > and use it for built-in function redefinition or overload in GLSL ES 3.00. > > GLSL ES 3.0 spec, chapter 6.1 "Function Definitions", page 71 > > "A shader cannot redefine or overload built-in functions." > > While in GLSL ES 1.0 specification, chapter 8 "Built-in Functions" > > "User code can overload the built-in functions but cannot redefine them." > > So this check is specific to GLSL ES 3.00. > > This patch fixes the following dEQP tests: > > dEQP-GLES3.functional.shaders.functions.invalid.overload_builtin_function_vertex > dEQP-GLES3.functional.shaders.functions.invalid.overload_builtin_function_fragment > dEQP-GLES3.functional.shaders.functions.invalid.redefine_builtin_function_vertex > dEQP-GLES3.functional.shaders.functions.invalid.redefine_builtin_function_fragment > > No piglit regressions. > > Signed-off-by: Samuel Iglesias Gonsalvez > --- > src/glsl/ast_to_hir.cpp| 21 + > src/glsl/builtin_functions.cpp | 11 +++ > src/glsl/ir.h | 4 > 3 files changed, 36 insertions(+) This looks great - thanks! Reviewed-by: Kenneth Graunke signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2 08/10] glsl: A shader cannot redefine or overload built-in functions in GLSL ES 3.00
On Thursday 19 February 2015 00:59:56 Kenneth Graunke wrote: > On Thursday, February 19, 2015 09:55:35 AM Samuel Iglesias Gonsalvez wrote: > > Create a new search function to look for matching built-in functions by > > name and use it for built-in function redefinition or overload in GLSL ES > > 3.00. > > > > GLSL ES 3.0 spec, chapter 6.1 "Function Definitions", page 71 > > > > "A shader cannot redefine or overload built-in functions." > > > > While in GLSL ES 1.0 specification, chapter 8 "Built-in Functions" > > > > "User code can overload the built-in functions but cannot redefine > > them." > > > > So this check is specific to GLSL ES 3.00. > > > > This patch fixes the following dEQP tests: > > > > dEQP-GLES3.functional.shaders.functions.invalid.overload_builtin_function_ > > vertex > > dEQP-GLES3.functional.shaders.functions.invalid.overload_builtin_function > > _fragment > > dEQP-GLES3.functional.shaders.functions.invalid.redefine_builtin_function > > _vertex > > dEQP-GLES3.functional.shaders.functions.invalid.redefine_builtin_function > > _fragment > > > > No piglit regressions. > > > > Signed-off-by: Samuel Iglesias Gonsalvez > > --- > > > > src/glsl/ast_to_hir.cpp| 21 + > > src/glsl/builtin_functions.cpp | 11 +++ > > src/glsl/ir.h | 4 > > 3 files changed, 36 insertions(+) > > This looks great - thanks! > > Reviewed-by: Kenneth Graunke Thanks!! pushed! Sam signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] i965/skl: Layout a 1D miptree horizontally
Ian Romanick writes: > There aren't any compressed formats that support 1D textures, so I > don't think this can occur. Does the bspec say anything about > compressed 1D textures? Ah yes, you're right. I just copied it from brw_miptree_layout_2d without really thinking it through. The SKL bspec explicitly states that compressed formats can't be used with SURFTYPE_1D. I'll remove and send a v2 along with the patches to fix 3D textures too. Thanks for the review. - Neil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radeonsi: don't use SQC_CACHES to flush ICACHE and KCACHE on SI
From: Marek Olšák
This reverts 73c2b0d18c51459697d8ec194ecfc4438c98c139.
It doesn't seem to be reliable. It's probably missing a wait packet or
something, because it's just a register write and doesn't wait for anything.
SURFACE_SYNC at least seems to wait until the flush is done. Just guessing.
Let's not complicate things and revert this.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88561
Cc: 10.5
---
src/gallium/drivers/radeonsi/si_state_draw.c | 29 +++-
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 128ea04..511bea2 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -367,24 +367,21 @@ void si_emit_cache_flush(struct r600_common_context
*sctx, struct r600_atom *ato
{
struct radeon_winsys_cs *cs = sctx->rings.gfx.cs;
uint32_t cp_coher_cntl = 0;
- uint32_t sqc_caches = 0;
uint32_t compute =
PKT3_SHADER_TYPE_S(!!(sctx->flags & SI_CONTEXT_FLAG_COMPUTE));
/* SI has a bug that it always flushes ICACHE and KCACHE if either
-* bit is set. An alternative way is to write SQC_CACHES. */
- if (sctx->chip_class == SI &&
- sctx->flags & BOTH_ICACHE_KCACHE &&
- (sctx->flags & BOTH_ICACHE_KCACHE) != BOTH_ICACHE_KCACHE) {
- sqc_caches =
- S_008C08_INST_INVALIDATE(!!(sctx->flags &
SI_CONTEXT_INV_ICACHE)) |
- S_008C08_DATA_INVALIDATE(!!(sctx->flags &
SI_CONTEXT_INV_KCACHE));
- } else {
- if (sctx->flags & SI_CONTEXT_INV_ICACHE)
- cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
- if (sctx->flags & SI_CONTEXT_INV_KCACHE)
- cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
- }
+* bit is set. An alternative way is to write SQC_CACHES, but that
+* doesn't seem to work reliably. Since the bug doesn't affect
+* correctness (it only does more work than necessary) and
+* the performance impact is likely negligible, there is no plan
+* to fix it.
+*/
+
+ if (sctx->flags & SI_CONTEXT_INV_ICACHE)
+ cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
+ if (sctx->flags & SI_CONTEXT_INV_KCACHE)
+ cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
if (sctx->flags & SI_CONTEXT_INV_TC_L1)
cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
@@ -451,10 +448,6 @@ void si_emit_cache_flush(struct r600_common_context *sctx,
struct r600_atom *ato
* It looks like SURFACE_SYNC flushes caches immediately and doesn't
* wait for any engines. This should be last.
*/
- if (sqc_caches) {
- r600_write_config_reg(cs, R_008C08_SQC_CACHES, sqc_caches);
- cs->buf[cs->cdw-3] |= compute; /* set the compute bit in the
header */
- }
if (cp_coher_cntl) {
if (sctx->chip_class >= CIK) {
radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) | compute);
--
2.1.0
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Re: [Mesa-dev] [Mesa-announce] Mesa 10.3 release candidate 1
Am Freitag, den 07.11.2014, 01:19 -0800 schrieb Matt Turner: > On Fri, Nov 7, 2014 at 1:07 AM, Thierry Vignaud > wrote: > > On 5 November 2014 04:44, Matt Turner wrote: > >I tried to reproduce this today and couldn't. > > > > (...) > > > Thanks. Maybe you could give a little more information, like an error > message or something? > >>> > >>> Same error as Thierry reported in this thread in August: > >> > >> Unfortunately Thierry's was from a re-run of make, so it wasn't useful. > > > > No It wasn't a re-run! > > It was a clean build in our build system with make -jXX with XX auto set to > > the number of cores and is always reproducable given enough cores > > Oh, weird. > > >> I've gone over this all and can't spot the problem. The dependencies > >> look fine. I tried automake-1.13 and 1.14, and make-3.82 and 4.0. > >> Maybe I'll have more luck on a 40 core system. > > > > As already explained, in order to be able to reproduce, you must either have > > a large system or force make -j to a high value (eg: -j24) > > Did you see the rest of the thread where I said I couldn't reproduce > on a 40 core system? > > Perhaps someone who can reproduce could try to take a look? Ok, here is what happens: This failure is only reproducible with the following config options: --disable-shared-glapi --disable-gles1 --disable-gles2 Which makes it pretty obvious what is to be blamed here. With those options set no installable libraries will be build below src/mapi, the only target is a static glapi.la. As lib_LTLIBRARIES is empty in that case the install-mesa-links target has no dependencies and gets executed immediately. This fails as it races with the compilation to create the .libs dir. As the install-mesa-links target works perfectly fine with an empty lib_LTLIBRARIES the fix is simply to not depends on the .libs directory for the state file of this target. A patch is on the list. Regards, Lucas -- Pengutronix e.K. | Lucas Stach | Industrial Linux Solutions | http://www.pengutronix.de/ | ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] install-lib-links: don't depend on .libs directory
This snippet can be included in Makefiles that may, depending on the project configuration, not actually build any installable libraries. In that case we don't have anything to depend on and this part of the makefile may be executed before the .libs directory is created, so do not depend on it being there. Signed-off-by: Lucas Stach Cc: "10.3 10.4" --- install-lib-links.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/install-lib-links.mk b/install-lib-links.mk index 6976ca4911ab..3545b268ebd1 100644 --- a/install-lib-links.mk +++ b/install-lib-links.mk @@ -3,9 +3,9 @@ if BUILD_SHARED if HAVE_COMPAT_SYMLINKS -all-local : .libs/install-mesa-links +all-local : .install-mesa-links -.libs/install-mesa-links : $(lib_LTLIBRARIES) +.install-mesa-links : $(lib_LTLIBRARIES) $(AM_V_GEN)$(MKDIR_P) $(top_builddir)/$(LIB_DIR); \ for f in $(join $(addsuffix .libs/,$(dir $(lib_LTLIBRARIES))),$(notdir $(lib_LTLIBRARIES:%.la=%.$(LIB_EXT)*))); do \ if test -h .libs/$$f; then \ -- 2.1.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radeonsi: don't use SQC_CACHES to flush ICACHE and KCACHE on SI
On Thu, Feb 19, 2015 at 7:10 AM, Marek Olšák wrote:
> From: Marek Olšák
>
> This reverts 73c2b0d18c51459697d8ec194ecfc4438c98c139.
>
> It doesn't seem to be reliable. It's probably missing a wait packet or
> something, because it's just a register write and doesn't wait for anything.
> SURFACE_SYNC at least seems to wait until the flush is done. Just guessing.
>
> Let's not complicate things and revert this.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88561
>
> Cc: 10.5
Reviewed-by: Alex Deucher
> ---
> src/gallium/drivers/radeonsi/si_state_draw.c | 29
> +++-
> 1 file changed, 11 insertions(+), 18 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
> b/src/gallium/drivers/radeonsi/si_state_draw.c
> index 128ea04..511bea2 100644
> --- a/src/gallium/drivers/radeonsi/si_state_draw.c
> +++ b/src/gallium/drivers/radeonsi/si_state_draw.c
> @@ -367,24 +367,21 @@ void si_emit_cache_flush(struct r600_common_context
> *sctx, struct r600_atom *ato
> {
> struct radeon_winsys_cs *cs = sctx->rings.gfx.cs;
> uint32_t cp_coher_cntl = 0;
> - uint32_t sqc_caches = 0;
> uint32_t compute =
> PKT3_SHADER_TYPE_S(!!(sctx->flags & SI_CONTEXT_FLAG_COMPUTE));
>
> /* SI has a bug that it always flushes ICACHE and KCACHE if either
> -* bit is set. An alternative way is to write SQC_CACHES. */
> - if (sctx->chip_class == SI &&
> - sctx->flags & BOTH_ICACHE_KCACHE &&
> - (sctx->flags & BOTH_ICACHE_KCACHE) != BOTH_ICACHE_KCACHE) {
> - sqc_caches =
> - S_008C08_INST_INVALIDATE(!!(sctx->flags &
> SI_CONTEXT_INV_ICACHE)) |
> - S_008C08_DATA_INVALIDATE(!!(sctx->flags &
> SI_CONTEXT_INV_KCACHE));
> - } else {
> - if (sctx->flags & SI_CONTEXT_INV_ICACHE)
> - cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
> - if (sctx->flags & SI_CONTEXT_INV_KCACHE)
> - cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
> - }
> +* bit is set. An alternative way is to write SQC_CACHES, but that
> +* doesn't seem to work reliably. Since the bug doesn't affect
> +* correctness (it only does more work than necessary) and
> +* the performance impact is likely negligible, there is no plan
> +* to fix it.
> +*/
> +
> + if (sctx->flags & SI_CONTEXT_INV_ICACHE)
> + cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
> + if (sctx->flags & SI_CONTEXT_INV_KCACHE)
> + cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
>
> if (sctx->flags & SI_CONTEXT_INV_TC_L1)
> cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
> @@ -451,10 +448,6 @@ void si_emit_cache_flush(struct r600_common_context
> *sctx, struct r600_atom *ato
> * It looks like SURFACE_SYNC flushes caches immediately and doesn't
> * wait for any engines. This should be last.
> */
> - if (sqc_caches) {
> - r600_write_config_reg(cs, R_008C08_SQC_CACHES, sqc_caches);
> - cs->buf[cs->cdw-3] |= compute; /* set the compute bit in the
> header */
> - }
> if (cp_coher_cntl) {
> if (sctx->chip_class >= CIK) {
> radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) |
> compute);
> --
> 2.1.0
>
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Re: [Mesa-dev] [PATCH v4] Fixing an x86 FPU bug.
Looks better, just a bunch of nit-picks...
First, I think the summary/subject line can be improved. How about
"mesa: use fi_type in vertex attribute code"
On 02/18/2015 10:00 AM, marius.pre...@intel.com wrote:
From: Marius Predut
On 32-bit, for floating point operations is used x86 FPU registers
instead SSE, reason for when reinterprets an integer as a float
result is unexpected (modify floats when they are written to memory).
How about this:
"For 32-bit builds, floating point operations use x86 FPU registers,
not SSE registers. If we're actually storing an integer in a float
variable, the value might get modified when written to memory. This
patch changes the VBO code to use the fi_type (float/int union) to
store/copy vertex attributes."
The patch was checked with and without -O3 compiler flag.
Also, it add performace improvement because treat GLfloats as GLint.
On x86 systems, moving a float as a int (thereby using integer registers
instead of FP registers) is a performance win.
Maybe:
"Also, this can improve performance on x86 because moving floats with
integer registers instead of FP registers is faster."
Neil Roberts review:
-include changes on all places that are storing attribute values.
Brian Paul review:
- use fi_type type instead gl_constant_value
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82668
Signed-off-by: Marius Predut
---
src/mesa/main/context.c |3 ++-
src/mesa/main/macros.h| 32
src/mesa/vbo/vbo_attrib_tmp.h | 20
src/mesa/vbo/vbo_context.h| 14 +++---
src/mesa/vbo/vbo_exec.h | 11 ++-
src/mesa/vbo/vbo_exec_api.c | 35 +--
src/mesa/vbo/vbo_exec_draw.c |6 +++---
src/mesa/vbo/vbo_exec_eval.c | 22 +++---
src/mesa/vbo/vbo_save.h | 16
src/mesa/vbo/vbo_save_api.c | 34 +-
src/mesa/vbo/vbo_save_draw.c |4 ++--
11 files changed, 105 insertions(+), 92 deletions(-)
diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index 63d30a2..f0597e2 100644
--- a/src/mesa/main/context.c
+++ b/src/mesa/main/context.c
@@ -134,6 +134,7 @@
#include "math/m_matrix.h"
#include "main/dispatch.h" /* for _gloffset_COUNT */
#include "uniforms.h"
+#include "macros.h"
#ifdef USE_SPARC_ASM
#include "sparc/sparc.h"
@@ -656,7 +657,7 @@ _mesa_init_constants(struct gl_constants *consts, gl_api
api)
consts->MaxSamples = 0;
/* GLSL default if NativeIntegers == FALSE */
- consts->UniformBooleanTrue = FLT_AS_UINT(1.0f);
+ consts->UniformBooleanTrue = FLOAT_AS_UNION(1.0f).u;
/* GL_ARB_sync */
consts->MaxServerWaitTimeout = 0x1fff7fffULL;
diff --git a/src/mesa/main/macros.h b/src/mesa/main/macros.h
index 2d59c6f..9ca3460 100644
--- a/src/mesa/main/macros.h
+++ b/src/mesa/main/macros.h
@@ -170,25 +170,25 @@ extern GLfloat _mesa_ubyte_to_float_color_tab[256];
ub = ((GLubyte) F_TO_I((f) * 255.0F))
#endif
-static inline GLfloat INT_AS_FLT(GLint i)
+static fi_type UINT_AS_UNION(GLuint u)
{
fi_type tmp;
- tmp.i = i;
- return tmp.f;
+ tmp.u = u;
+ return tmp;
}
-static inline GLfloat UINT_AS_FLT(GLuint u)
+static inline fi_type INT_AS_UNION(GLint i)
{
fi_type tmp;
- tmp.u = u;
- return tmp.f;
+ tmp.i = i;
+ return tmp;
}
-static inline unsigned FLT_AS_UINT(float f)
+static inline fi_type FLOAT_AS_UNION(GLfloat f)
{
fi_type tmp;
tmp.f = f;
- return tmp.u;
+ return tmp;
}
/**
@@ -620,24 +620,24 @@ do { \
* The default values are chosen based on \p type.
*/
static inline void
-COPY_CLEAN_4V_TYPE_AS_FLOAT(GLfloat dst[4], int sz, const GLfloat src[4],
+COPY_CLEAN_4V_TYPE_AS_UNION(fi_type dst[4], int sz, const fi_type src[4],
GLenum type)
{
switch (type) {
case GL_FLOAT:
- ASSIGN_4V(dst, 0, 0, 0, 1);
+ ASSIGN_4V(dst, FLOAT_AS_UNION(0), FLOAT_AS_UNION(0), FLOAT_AS_UNION(0),
FLOAT_AS_UNION(1));
Wrap to <= 78 columns.
break;
case GL_INT:
- ASSIGN_4V(dst, INT_AS_FLT(0), INT_AS_FLT(0),
- INT_AS_FLT(0), INT_AS_FLT(1));
+ ASSIGN_4V(dst, INT_AS_UNION(0), INT_AS_UNION(0),
+INT_AS_UNION(0), INT_AS_UNION(1));
break;
case GL_UNSIGNED_INT:
- ASSIGN_4V(dst, UINT_AS_FLT(0), UINT_AS_FLT(0),
- UINT_AS_FLT(0), UINT_AS_FLT(1));
+ ASSIGN_4V(dst, UINT_AS_UNION(0), UINT_AS_UNION(0),
+UINT_AS_UNION(0), UINT_AS_UNION(1));
break;
default:
- ASSIGN_4V(dst, 0.0f, 0.0f, 0.0f, 1.0f); /* silence warnings */
- ASSERT(!"Unexpected type in COPY_CLEAN_4V_TYPE_AS_FLOAT macro");
+ ASSIGN_4V(dst, FLOAT_AS_UNION(0), FLOAT_AS_UNION(0), FLOAT_AS_UNION(0),
FLOAT_AS_UNION(1)); /* silence warnings */
Line wrap.
+ ASSERT(!"Unexpected ty
[Mesa-dev] [PATCH 1/2] nir: add missing GLSL_TYPE_DOUBLE case in type_size()
To silence compiler warning about unhandled switch case. --- src/glsl/nir/nir_lower_io.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/glsl/nir/nir_lower_io.c b/src/glsl/nir/nir_lower_io.c index ddbc249..23499e5 100644 --- a/src/glsl/nir/nir_lower_io.c +++ b/src/glsl/nir/nir_lower_io.c @@ -49,6 +49,7 @@ type_size(const struct glsl_type *type) case GLSL_TYPE_UINT: case GLSL_TYPE_INT: case GLSL_TYPE_FLOAT: + case GLSL_TYPE_DOUBLE: case GLSL_TYPE_BOOL: return glsl_get_components(type); case GLSL_TYPE_ARRAY: -- 1.9.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] st/mesa: add GSL_TYPE_DOUBLE, new ir_unop_* switch cases
To silence compiler warnings about unhandled switch cases.
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 12
1 file changed, 12 insertions(+)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 3dac004..9969fac 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -974,6 +974,7 @@ type_size(const struct glsl_type *type)
case GLSL_TYPE_UINT:
case GLSL_TYPE_INT:
case GLSL_TYPE_FLOAT:
+ case GLSL_TYPE_DOUBLE:
case GLSL_TYPE_BOOL:
if (type->is_matrix()) {
return type->matrix_columns;
@@ -2025,6 +2026,17 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir)
case ir_binop_ldexp:
case ir_binop_carry:
case ir_binop_borrow:
+ case ir_unop_d2f:
+ case ir_unop_f2d:
+ case ir_unop_d2i:
+ case ir_unop_i2d:
+ case ir_unop_d2u:
+ case ir_unop_u2d:
+ case ir_unop_d2b:
+ case ir_unop_pack_double_2x32:
+ case ir_unop_unpack_double_2x32:
+ case ir_unop_frexp_sig:
+ case ir_unop_frexp_exp:
/* This operation is not supported, or should have already been handled.
*/
assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
--
1.9.1
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[Mesa-dev] [Bug 89199] u_math.h:591:4: error: implicit declaration of function 'ffsll'
https://bugs.freedesktop.org/show_bug.cgi?id=89199 --- Comment #2 from Brian Paul --- Hi Vinson, Is that with gcc? Which compiler version? I'll attach a patch proposal for you to try... -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 89199] u_math.h:591:4: error: implicit declaration of function 'ffsll'
https://bugs.freedesktop.org/show_bug.cgi?id=89199 --- Comment #3 from Brian Paul --- Created attachment 113670 --> https://bugs.freedesktop.org/attachment.cgi?id=113670&action=edit proposed patch If you're using gcc, maybe a gcc version check would be better. This patch also assumes the radeonsi driver isn't used on NetBSD (the only user of u_bit_scan64() at this time.) -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] mesa: Check that draw buffers are valid for glDrawBuffers on GLES3
Section 4.2 (Whole Framebuffer Operations) of the OpenGL 3.0 specification
says:
"Each buffer listed in bufs must be BACK, NONE, or one of the values from
table 4.3 (NONE, COLOR_ATTACHMENTi)".
Fixes 1 dEQP test:
* dEQP-GLES3.functional.negative_api.buffer.draw_buffers
---
src/mesa/main/buffers.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/mesa/main/buffers.c b/src/mesa/main/buffers.c
index a2d02d5..e5076e9 100644
--- a/src/mesa/main/buffers.c
+++ b/src/mesa/main/buffers.c
@@ -336,6 +336,20 @@ _mesa_DrawBuffers(GLsizei n, const GLenum *buffers)
/* complicated error checking... */
for (output = 0; output < n; output++) {
+ /* Section 4.2 (Whole Framebuffer Operations) of the OpenGL 3.0
+ * specification says:
+ *
+ * "Each buffer listed in bufs must be BACK, NONE, or one of the
values
+ * from table 4.3 (NONE, COLOR_ATTACHMENTi)"
+ */
+ if (_mesa_is_gles3(ctx) && buffers[output] != GL_NONE &&
+ buffers[output] != GL_BACK &&
+ (buffers[output] < GL_COLOR_ATTACHMENT0 ||
+ buffers[output] >= GL_COLOR_ATTACHMENT0 +
ctx->Const.MaxColorAttachments)) {
+ _mesa_error(ctx, GL_INVALID_ENUM, "glDrawBuffers(buffer)");
+ return;
+ }
+
if (buffers[output] == GL_NONE) {
destMask[output] = 0x0;
}
--
2.1.3
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Re: [Mesa-dev] [PATCH v2] mesa: Check first that draw buffers are valid for glDrawBuffers on GLES3
On 02/18/2015 09:09 PM, Matt Turner wrote: > On Tue, Jan 13, 2015 at 3:29 AM, Eduardo Lima Mitev wrote: >> This patch was updated and is pending review. > > I think we're waiting on a new version with Tapani's comment addressed. > > The patch looks right, FWIW. > Hi Matt, I completely missed Tappani's comment, sorry. I just sent a new version of the patch addressing those: http://lists.freedesktop.org/archives/mesa-dev/2015-February/077290.html Thank you, Eduardo ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa: Check that draw buffers are valid for glDrawBuffers on GLES3
Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [Mesa-announce] Mesa 10.3 release candidate 1
On Thu, Feb 19, 2015 at 5:53 AM, Lucas Stach wrote: > Am Freitag, den 07.11.2014, 01:19 -0800 schrieb Matt Turner: >> On Fri, Nov 7, 2014 at 1:07 AM, Thierry Vignaud >> wrote: >> > On 5 November 2014 04:44, Matt Turner wrote: >> >I tried to reproduce this today and couldn't. >> > >> > (...) >> > >> Thanks. Maybe you could give a little more information, like an error >> message or something? >> >>> >> >>> Same error as Thierry reported in this thread in August: >> >> >> >> Unfortunately Thierry's was from a re-run of make, so it wasn't useful. >> > >> > No It wasn't a re-run! >> > It was a clean build in our build system with make -jXX with XX auto set to >> > the number of cores and is always reproducable given enough cores >> >> Oh, weird. >> >> >> I've gone over this all and can't spot the problem. The dependencies >> >> look fine. I tried automake-1.13 and 1.14, and make-3.82 and 4.0. >> >> Maybe I'll have more luck on a 40 core system. >> > >> > As already explained, in order to be able to reproduce, you must either >> > have >> > a large system or force make -j to a high value (eg: -j24) >> >> Did you see the rest of the thread where I said I couldn't reproduce >> on a 40 core system? >> >> Perhaps someone who can reproduce could try to take a look? > > Ok, here is what happens: > > This failure is only reproducible with the following config options: > --disable-shared-glapi > --disable-gles1 > --disable-gles2 > > Which makes it pretty obvious what is to be blamed here. With those > options set no installable libraries will be build below src/mapi, the > only target is a static glapi.la. As lib_LTLIBRARIES is empty in that > case the install-mesa-links target has no dependencies and gets executed > immediately. This fails as it races with the compilation to create > the .libs dir. > > As the install-mesa-links target works perfectly fine with an empty > lib_LTLIBRARIES the fix is simply to not depends on the .libs directory > for the state file of this target. A patch is on the list. > > Regards, > Lucas > > -- > Pengutronix e.K. | Lucas Stach | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Thanks Lucas. That makes a lot of sense. I never suspected that the reporters were using non-default options and forgot to say so. I'll take a look at the patch. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] install-lib-links: don't depend on .libs directory
On Thu, Feb 19, 2015 at 5:52 AM, Lucas Stach wrote: > This snippet can be included in Makefiles that may, depending on the > project configuration, not actually build any installable libraries. > > In that case we don't have anything to depend on and this part of > the makefile may be executed before the .libs directory is created, > so do not depend on it being there. > > Signed-off-by: Lucas Stach > Cc: "10.3 10.4" > --- > install-lib-links.mk | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/install-lib-links.mk b/install-lib-links.mk > index 6976ca4911ab..3545b268ebd1 100644 > --- a/install-lib-links.mk > +++ b/install-lib-links.mk > @@ -3,9 +3,9 @@ > > if BUILD_SHARED > if HAVE_COMPAT_SYMLINKS > -all-local : .libs/install-mesa-links > +all-local : .install-mesa-links > > -.libs/install-mesa-links : $(lib_LTLIBRARIES) > +.install-mesa-links : $(lib_LTLIBRARIES) > $(AM_V_GEN)$(MKDIR_P) $(top_builddir)/$(LIB_DIR); \ > for f in $(join $(addsuffix .libs/,$(dir > $(lib_LTLIBRARIES))),$(notdir $(lib_LTLIBRARIES:%.la=%.$(LIB_EXT)*))); do \ > if test -h .libs/$$f; then \ > -- > 2.1.4 > Thanks a bunch Lucas. Reviewed-by: Matt Turner I'll commit this and tag it for 10.5 as well. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] st/mesa: add GSL_TYPE_DOUBLE, new ir_unop_* switch cases
On Thu, Feb 19, 2015 at 8:27 AM, Brian Paul wrote:
>
> To silence compiler warnings about unhandled switch cases.
> ---
> src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> index 3dac004..9969fac 100644
> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> @@ -974,6 +974,7 @@ type_size(const struct glsl_type *type)
> case GLSL_TYPE_UINT:
> case GLSL_TYPE_INT:
> case GLSL_TYPE_FLOAT:
> + case GLSL_TYPE_DOUBLE:
> case GLSL_TYPE_BOOL:
>if (type->is_matrix()) {
> return type->matrix_columns;
> @@ -2025,6 +2026,17 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir)
> case ir_binop_ldexp:
> case ir_binop_carry:
> case ir_binop_borrow:
> + case ir_unop_d2f:
> + case ir_unop_f2d:
> + case ir_unop_d2i:
> + case ir_unop_i2d:
> + case ir_unop_d2u:
> + case ir_unop_u2d:
> + case ir_unop_d2b:
> + case ir_unop_pack_double_2x32:
> + case ir_unop_unpack_double_2x32:
> + case ir_unop_frexp_sig:
> + case ir_unop_frexp_exp:
>/* This operation is not supported, or should have already been
> handled.
> */
>assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
> --
> 1.9.1
>
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Both patches are:
Reviewed-by: Anuj Phogat
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Re: [Mesa-dev] [PATCH 9/9] i965/vec4: Print "VS" or "GS" when compiles fail, not "vec4".
On Wed, Feb 18, 2015 at 9:37 PM, Jason Ekstrand wrote: > Series is > Reviewed-by: Jason Ekstrand Me too: Reviewed-by: Kristian Høgsberg > On Feb 18, 2015 9:00 PM, "Kenneth Graunke" wrote: >> >> This is now trivial to do right. >> >> Signed-off-by: Kenneth Graunke >> --- >> src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp >> b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp >> index 4f66b62..562fc30 100644 >> --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp >> +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp >> @@ -3656,7 +3656,7 @@ vec4_visitor::fail(const char *format, ...) >> va_start(va, format); >> msg = ralloc_vasprintf(mem_ctx, format, va); >> va_end(va); >> - msg = ralloc_asprintf(mem_ctx, "vec4 compile failed: %s\n", msg); >> + msg = ralloc_asprintf(mem_ctx, "%s compile failed: %s\n", >> stage_abbrev, msg); >> >> this->fail_msg = msg; >> >> -- >> 2.2.2 >> >> ___ >> mesa-dev mailing list >> mesa-dev@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/mesa-dev > > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/mesa-dev > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 10/32] i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().
On Fri, Feb 6, 2015 at 4:01 PM, Francisco Jerez wrote: > Hey Matt, > > Matt Turner writes: > > > On Fri, Feb 6, 2015 at 6:42 AM, Francisco Jerez > wrote: > >> MRFs cannot be read from anyway so they cannot possibly be a valid > >> source of LOAD_PAYLOAD. > >> --- > > > > The function only seems to test inst->dst.file == MRF. I don't see any > > code for handling MRF sources. What am I missing? > > That test is for "handling" MRF sources -- More precisely, it's > collecting the writemask and half flags for MRF writes, which can only > possibly be useful if we're going to use them later on to read something > out of an MRF into a payload, which we shouldn't be doing in the first > place. > > Aside from simplifying the function somewhat, that allows us to drop the > 16 register gap reserved for MRFs at register offset zero, what will > allow us to drop the vgrf_to_reg[] offset calculation completely (also > in split_virtual_grfs()) in a future patch (not sent for review yet). > No, we do read from MRF's sort-of... Send messages have an implicit "read" from an MRF. This was written precicely so that we could use LOAD_PAYLOAD to build MRF payloads. We do on pre-GEN6. > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/mesa-dev > > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] glsl: don't allow invariant qualifiers for interface blocks
On 12/09/2014 02:52 AM, Eduardo Lima Mitev wrote: > From: Samuel Iglesias Gonsalvez > > GLSL 1.50 and GLSL 4.40 specs, they both say the same in > "Interface Blocks" section: > > "If no optional qualifier is used in a member-declaration, the qualification > of > the member includes all in, out, patch, uniform, or buffer as determined by > interface-qualifier. If optional qualifiers are used, they can include > interpolation qualifiers, auxiliary storage qualifiers, and storage qualifiers > and they must declare an input, output, or uniform member consistent with the > interface qualifier of the block" > > From GLSL ES 3.0, chapter 4.3.7 "Interface Blocks", page 38: > > "GLSL ES 3.0 does not support interface blocks for shader inputs or outputs." > > and from GLSL ES 3.0, chapter 4.6.1 "The invariant qualifier", page 52. > > "Only variables output from a shader can be candidates for invariance. This > includes user-defined output variables and the built-in output variables. As > only outputs can be declared as invariant, an invariant output from one shader > stage will still match an input of a subsequent stage without the input being > declared as invariant." > > From GLSL ES 1.0, chapter 4.6.1 "The invariant qualifier", page 37. > > "Only the following variables may be declared as invariant: > * Built-in special variables output from the vertex shader > * Varying variables output from the vertex shader > * Built-in special variables input to the fragment shader > * Varying variables input to the fragment shader > * Built-in special variables output from the fragment shader." > > This patch fixes the following dEQP tests: > > dEQP-GLES3.functional.shaders.declarations.invalid_declarations.invariant_uniform_block_2_vertex > dEQP-GLES3.functional.shaders.declarations.invalid_declarations.invariant_uniform_block_2_fragment > > No piglit regressions. > > Signed-off-by: Samuel Iglesias Gonsalvez > > v2: > > - Enable this check for GLSL. > > Signed-off-by: Samuel Iglesias Gonsalvez > --- > src/glsl/glsl_parser.yy | 35 +++ > 1 file changed, 35 insertions(+) > > diff --git a/src/glsl/glsl_parser.yy b/src/glsl/glsl_parser.yy > index 7fb8c38..9f2a0a3 100644 > --- a/src/glsl/glsl_parser.yy > +++ b/src/glsl/glsl_parser.yy > @@ -2539,6 +2539,41 @@ basic_interface_block: > "interface block member does not match " > "the interface block"); > } Blank line here. > + /* From GLSL ES 3.0, chapter 4.3.7 "Interface Blocks", page 38: > + * > + * "GLSL ES 3.0 does not support interface blocks for shader inputs > or > + * outputs." > + * > + * And from GLSL ES 3.0, chapter 4.6.1 "The invariant qualifier", > page 52. > + * > + * "Only variables output from a shader can be candidates for > + * invariance. This includes user-defined output variables and the > + * built-in output variables. As only outputs can be declared as > + * invariant, an invariant output from one shader stage will > + * still match an input of a subsequent stage without the input > being > + * declared as invariant." > + * > + * From GLSL ES 1.0, chapter 4.6.1 "The invariant qualifier", page > 37. > + * > + * "Only the following variables may be declared as invariant: > + * * Built-in special variables output from the vertex shader > + * * Varying variables output from the vertex shader > + * * Built-in special variables input to the fragment shader > + * * Varying variables input to the fragment shader > + * * Built-in special variables output from the fragment shader." In addition to Matt's comments about the comment... I don't think there's any reason to mention GLSL ES 1.0. There are no interface blocks in GLSL ES 1.0, and this is inside processing an interface block. With this and Matt's suggestions applied, this patch is Reviewed-by: Ian Romanick > + * > + * From GLSL 4.40 and GLSL 1.50, section "Interface Blocks": > + * > + * "If no optional qualifier is used in a member-declaration, the > + * qualification of the member includes all in, out, patch, uniform, > + * or buffer as determined by interface-qualifier. If optional > + * qualifiers are used, they can include interpolation qualifiers, > + * auxiliary storage qualifiers, and storage qualifiers and they > must > + * declare an input, output, or uniform member consistent with the > + * interface qualifier of the block" > + */ > + if (qualifier.flags.q.invariant) > +_mesa_glsl_error(&@1, state, "invariant qualifiers cannot be > used with interface blocks members"); >} > >$$ = block; > _
Re: [Mesa-dev] [PATCH 3/9] glsl: Create a _mesa_shader_stage_to_abbrev() function.
On 02/18/2015 09:00 PM, Kenneth Graunke wrote:
> This is similar to _mesa_shader_stage_to_string(), but returns "VS"
> instead of "vertex".
>
> Signed-off-by: Kenneth Graunke
> ---
> src/glsl/glsl_parser_extras.cpp | 17 +
> src/glsl/glsl_parser_extras.h | 3 +++
> 2 files changed, 20 insertions(+)
>
> diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp
> index ccdf031..0334e4a 100644
> --- a/src/glsl/glsl_parser_extras.cpp
> +++ b/src/glsl/glsl_parser_extras.cpp
> @@ -376,6 +376,23 @@ _mesa_shader_stage_to_string(unsigned stage)
> return "unknown";
> }
>
> +/**
> + * Translate a gl_shader_stage to a shader stage abbreviation (VS, GS, FS)
> + * for debug printouts and error messages.
> + */
> +const char *
> +_mesa_shader_stage_to_abbrev(unsigned stage)
> +{
> + switch (stage) {
> + case MESA_SHADER_VERTEX: return "VS";
> + case MESA_SHADER_FRAGMENT: return "FS";
> + case MESA_SHADER_GEOMETRY: return "GS";
The next patch has some compute bits, should this also do compute?
> + }
> +
> + assert(!"Should not get here.");
> + return "unknown";
unreachable("Bad shader stage.");
> +}
> +
> /* This helper function will append the given message to the shader's
> info log and report it via GL_ARB_debug_output. Per that extension,
> 'type' is one of the enum values classifying the message, and
> diff --git a/src/glsl/glsl_parser_extras.h b/src/glsl/glsl_parser_extras.h
> index 843fdae..6861fac 100644
> --- a/src/glsl/glsl_parser_extras.h
> +++ b/src/glsl/glsl_parser_extras.h
> @@ -576,6 +576,9 @@ extern "C" {
> extern const char *
> _mesa_shader_stage_to_string(unsigned stage);
>
> +extern const char *
> +_mesa_shader_stage_to_abbrev(unsigned stage);
> +
> extern int glcpp_preprocess(void *ctx, const char **shader, char **info_log,
>const struct gl_extensions *extensions, struct
> gl_context *gl_ctx);
>
>
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Re: [Mesa-dev] [PATCH 3/9] glsl: Create a _mesa_shader_stage_to_abbrev() function.
On 02/19/2015 11:43 AM, Ian Romanick wrote:
> On 02/18/2015 09:00 PM, Kenneth Graunke wrote:
>> This is similar to _mesa_shader_stage_to_string(), but returns "VS"
>> instead of "vertex".
>>
>> Signed-off-by: Kenneth Graunke
>> ---
>> src/glsl/glsl_parser_extras.cpp | 17 +
>> src/glsl/glsl_parser_extras.h | 3 +++
>> 2 files changed, 20 insertions(+)
>>
>> diff --git a/src/glsl/glsl_parser_extras.cpp
>> b/src/glsl/glsl_parser_extras.cpp
>> index ccdf031..0334e4a 100644
>> --- a/src/glsl/glsl_parser_extras.cpp
>> +++ b/src/glsl/glsl_parser_extras.cpp
>> @@ -376,6 +376,23 @@ _mesa_shader_stage_to_string(unsigned stage)
>> return "unknown";
>> }
>>
>> +/**
>> + * Translate a gl_shader_stage to a shader stage abbreviation (VS, GS, FS)
>> + * for debug printouts and error messages.
>> + */
>> +const char *
>> +_mesa_shader_stage_to_abbrev(unsigned stage)
>> +{
>> + switch (stage) {
>> + case MESA_SHADER_VERTEX: return "VS";
>> + case MESA_SHADER_FRAGMENT: return "FS";
>> + case MESA_SHADER_GEOMETRY: return "GS";
>
> The next patch has some compute bits, should this also do compute?
>
>> + }
>> +
>> + assert(!"Should not get here.");
>> + return "unknown";
>
> unreachable("Bad shader stage.");
With that fixed, this patch is
Reviewed-by: Ian Romanick
Either way, the rest of the series is
Reviewed-by: Ian Romanick
>> +}
>> +
>> /* This helper function will append the given message to the shader's
>> info log and report it via GL_ARB_debug_output. Per that extension,
>> 'type' is one of the enum values classifying the message, and
>> diff --git a/src/glsl/glsl_parser_extras.h b/src/glsl/glsl_parser_extras.h
>> index 843fdae..6861fac 100644
>> --- a/src/glsl/glsl_parser_extras.h
>> +++ b/src/glsl/glsl_parser_extras.h
>> @@ -576,6 +576,9 @@ extern "C" {
>> extern const char *
>> _mesa_shader_stage_to_string(unsigned stage);
>>
>> +extern const char *
>> +_mesa_shader_stage_to_abbrev(unsigned stage);
>> +
>> extern int glcpp_preprocess(void *ctx, const char **shader, char **info_log,
>>const struct gl_extensions *extensions, struct
>> gl_context *gl_ctx);
>>
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[Mesa-dev] [PATCH] glsl: Use the without_array predicate
---
src/glsl/ir.h | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index a0f48b2..9c60b07 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -450,11 +450,8 @@ public:
*/
inline bool is_interface_instance() const
{
- const glsl_type *const t = this->type;
-
- return (t == this->interface_type)
- || (t->is_array() && t->fields.array == this->interface_type);
-}
+ return (this->type->without_array() == this->interface_type);
+ }
/**
* Set this->interface_type on a newly created variable.
--
2.1.0
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Re: [Mesa-dev] [PATCH 10/32] i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().
Jason Ekstrand writes: > On Fri, Feb 6, 2015 at 4:01 PM, Francisco Jerez > wrote: > >> Hey Matt, >> >> Matt Turner writes: >> >> > On Fri, Feb 6, 2015 at 6:42 AM, Francisco Jerez >> wrote: >> >> MRFs cannot be read from anyway so they cannot possibly be a valid >> >> source of LOAD_PAYLOAD. >> >> --- >> > >> > The function only seems to test inst->dst.file == MRF. I don't see any >> > code for handling MRF sources. What am I missing? >> >> That test is for "handling" MRF sources -- More precisely, it's >> collecting the writemask and half flags for MRF writes, which can only >> possibly be useful if we're going to use them later on to read something >> out of an MRF into a payload, which we shouldn't be doing in the first >> place. >> >> Aside from simplifying the function somewhat, that allows us to drop the >> 16 register gap reserved for MRFs at register offset zero, what will >> allow us to drop the vgrf_to_reg[] offset calculation completely (also >> in split_virtual_grfs()) in a future patch (not sent for review yet). >> > > No, we do read from MRF's sort-of... Send messages have an implicit "read" > from an MRF. Heh, and that's pretty much the only way you "read" from it. > This was written precicely so that we could use LOAD_PAYLOAD > to build MRF payloads. We do on pre-GEN6. > I'm aware, but you don't need any of this meta-data to LOAD_PAYLOAD *into* an MRF, and LOAD_PAYLOAD with an MRF as source should be illegal anyway. > >> ___ >> mesa-dev mailing list >> mesa-dev@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/mesa-dev >> >> pgpfF5PKyva7v.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] st/mesa: add GSL_TYPE_DOUBLE, new ir_unop_* switch cases
On Thu, Feb 19, 2015 at 11:27 AM, Brian Paul wrote:
> To silence compiler warnings about unhandled switch cases.
> ---
> src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> index 3dac004..9969fac 100644
> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> @@ -974,6 +974,7 @@ type_size(const struct glsl_type *type)
> case GLSL_TYPE_UINT:
> case GLSL_TYPE_INT:
> case GLSL_TYPE_FLOAT:
> + case GLSL_TYPE_DOUBLE:
> case GLSL_TYPE_BOOL:
>if (type->is_matrix()) {
> return type->matrix_columns;
Both here and in the other patch, I'd rather you put this along with
the other "unexpected" types. The st/mesa patch will fix it up
properly -- double has more complex type_size() requirements.
-ilia
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[Mesa-dev] [PATCH 2/2] st/mesa: add GSL_TYPE_DOUBLE, new ir_unop_* switch cases
To silence compiler warnings about unhandled switch cases. v2: move GSL_TYPE_DOUBLE case to the "Invalid type in type_size" section, per Ilia. --- src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 12 1 file changed, 12 insertions(+) diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index 3dac004..035152a 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -1004,6 +1004,7 @@ type_size(const struct glsl_type *type) case GLSL_TYPE_INTERFACE: case GLSL_TYPE_VOID: case GLSL_TYPE_ERROR: + case GLSL_TYPE_DOUBLE: assert(!"Invalid type in type_size"); break; } @@ -2025,6 +2026,17 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir) case ir_binop_ldexp: case ir_binop_carry: case ir_binop_borrow: + case ir_unop_d2f: + case ir_unop_f2d: + case ir_unop_d2i: + case ir_unop_i2d: + case ir_unop_d2u: + case ir_unop_u2d: + case ir_unop_d2b: + case ir_unop_pack_double_2x32: + case ir_unop_unpack_double_2x32: + case ir_unop_frexp_sig: + case ir_unop_frexp_exp: /* This operation is not supported, or should have already been handled. */ assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()"); -- 1.9.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] nir: add missing GLSL_TYPE_DOUBLE case in type_size()
To silence compiler warning about unhandled switch case.
v2: move GLSL_TYPE_DOUBLE to the "not reached" section, per Ilia.
---
src/glsl/nir/nir_lower_io.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/glsl/nir/nir_lower_io.c b/src/glsl/nir/nir_lower_io.c
index ddbc249..207f8da 100644
--- a/src/glsl/nir/nir_lower_io.c
+++ b/src/glsl/nir/nir_lower_io.c
@@ -69,6 +69,7 @@ type_size(const struct glsl_type *type)
return 0;
case GLSL_TYPE_VOID:
case GLSL_TYPE_ERROR:
+ case GLSL_TYPE_DOUBLE:
unreachable("not reached");
}
--
1.9.1
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Re: [Mesa-dev] [PATCH 1/2] nir: add missing GLSL_TYPE_DOUBLE case in type_size()
Series is Reviewed-by: Ilia Mirkin
On Thu, Feb 19, 2015 at 3:51 PM, Brian Paul wrote:
> To silence compiler warning about unhandled switch case.
> v2: move GLSL_TYPE_DOUBLE to the "not reached" section, per Ilia.
> ---
> src/glsl/nir/nir_lower_io.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/glsl/nir/nir_lower_io.c b/src/glsl/nir/nir_lower_io.c
> index ddbc249..207f8da 100644
> --- a/src/glsl/nir/nir_lower_io.c
> +++ b/src/glsl/nir/nir_lower_io.c
> @@ -69,6 +69,7 @@ type_size(const struct glsl_type *type)
>return 0;
> case GLSL_TYPE_VOID:
> case GLSL_TYPE_ERROR:
> + case GLSL_TYPE_DOUBLE:
>unreachable("not reached");
> }
>
> --
> 1.9.1
>
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Re: [Mesa-dev] [PATCH 10/32] i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().
On Thu, Feb 19, 2015 at 12:13 PM, Francisco Jerez wrote: > Jason Ekstrand writes: > > > On Fri, Feb 6, 2015 at 4:01 PM, Francisco Jerez > > wrote: > > > >> Hey Matt, > >> > >> Matt Turner writes: > >> > >> > On Fri, Feb 6, 2015 at 6:42 AM, Francisco Jerez < > curroje...@riseup.net> > >> wrote: > >> >> MRFs cannot be read from anyway so they cannot possibly be a valid > >> >> source of LOAD_PAYLOAD. > >> >> --- > >> > > >> > The function only seems to test inst->dst.file == MRF. I don't see any > >> > code for handling MRF sources. What am I missing? > >> > >> That test is for "handling" MRF sources -- More precisely, it's > >> collecting the writemask and half flags for MRF writes, which can only > >> possibly be useful if we're going to use them later on to read something > >> out of an MRF into a payload, which we shouldn't be doing in the first > >> place. > >> > >> Aside from simplifying the function somewhat, that allows us to drop the > >> 16 register gap reserved for MRFs at register offset zero, what will > >> allow us to drop the vgrf_to_reg[] offset calculation completely (also > >> in split_virtual_grfs()) in a future patch (not sent for review yet). > >> > > > > No, we do read from MRF's sort-of... Send messages have an implicit > "read" > > from an MRF. > > Heh, and that's pretty much the only way you "read" from it. > > > This was written precicely so that we could use LOAD_PAYLOAD > > to build MRF payloads. We do on pre-GEN6. > > > I'm aware, but you don't need any of this meta-data to LOAD_PAYLOAD > *into* an MRF, and LOAD_PAYLOAD with an MRF as source should be illegal > anyway. > And no one is using it that way. All of the metadata checks you are deleting are checks on the *destination*. > > > >> ___ > >> mesa-dev mailing list > >> mesa-dev@lists.freedesktop.org > >> http://lists.freedesktop.org/mailman/listinfo/mesa-dev > >> > >> > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] glsl: Use the without_array predicate
On Thu, Feb 19, 2015 at 11:57 AM, Timothy Arceri wrote:
> ---
> src/glsl/ir.h | 7 ++-
> 1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/src/glsl/ir.h b/src/glsl/ir.h
> index a0f48b2..9c60b07 100644
> --- a/src/glsl/ir.h
> +++ b/src/glsl/ir.h
> @@ -450,11 +450,8 @@ public:
> */
> inline bool is_interface_instance() const
> {
> - const glsl_type *const t = this->type;
> -
> - return (t == this->interface_type)
> - || (t->is_array() && t->fields.array == this->interface_type);
> -}
> + return (this->type->without_array() == this->interface_type);
Remove the superfluous parentheses, and
Reviewed-by: Matt Turner
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Re: [Mesa-dev] [PATCH] st/mesa: fix sampler view reference counting bug in glDraw/CopyPixels
Ping.
On 02/18/2015 11:20 AM, Brian Paul wrote:
Use pipe_sampler_view_reference() instead of ordinary assignment.
Also add a new sanity check assertion.
Fixes piglit gl-1.0-drawpixels-color-index test crash. But note
that the test still fails.
Cc: "10.4, 10.5"
---
src/mesa/state_tracker/st_cb_drawpixels.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c
b/src/mesa/state_tracker/st_cb_drawpixels.c
index 939fc20..3d13b5c 100644
--- a/src/mesa/state_tracker/st_cb_drawpixels.c
+++ b/src/mesa/state_tracker/st_cb_drawpixels.c
@@ -1154,8 +1154,10 @@ st_DrawPixels(struct gl_context *ctx, GLint x, GLint y,
color = NULL;
if (st->pixel_xfer.pixelmap_enabled) {
- sv[1] = st->pixel_xfer.pixelmap_sampler_view;
- num_sampler_view++;
+ sv[1] = NULL;
+ pipe_sampler_view_reference(&sv[1],
+ st->pixel_xfer.pixelmap_sampler_view);
+ num_sampler_view++;
}
}
@@ -1176,7 +1178,8 @@ st_DrawPixels(struct gl_context *ctx, GLint x, GLint y,
if (write_stencil) {
enum pipe_format stencil_format =
util_format_stencil_only(pt->format);
-
+ /* we should not be doing pixel map/transfer (see above) */
+ assert(num_sampler_view == 1);
sv[1] = st_create_texture_sampler_view_format(st->pipe, pt,
stencil_format);
num_sampler_view++;
@@ -1516,7 +1519,9 @@ st_CopyPixels(struct gl_context *ctx, GLint srcx, GLint
srcy,
driver_vp = make_passthrough_vertex_shader(st, GL_FALSE);
if (st->pixel_xfer.pixelmap_enabled) {
- sv[1] = st->pixel_xfer.pixelmap_sampler_view;
+ sv[1] = NULL;
+ pipe_sampler_view_reference(&sv[1],
+ st->pixel_xfer.pixelmap_sampler_view);
num_sampler_view++;
}
}
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Re: [Mesa-dev] [PATCH 10/32] i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().
Jason Ekstrand writes: > On Thu, Feb 19, 2015 at 12:13 PM, Francisco Jerez > wrote: > >> Jason Ekstrand writes: >> >> > On Fri, Feb 6, 2015 at 4:01 PM, Francisco Jerez >> > wrote: >> > >> >> Hey Matt, >> >> >> >> Matt Turner writes: >> >> >> >> > On Fri, Feb 6, 2015 at 6:42 AM, Francisco Jerez < >> curroje...@riseup.net> >> >> wrote: >> >> >> MRFs cannot be read from anyway so they cannot possibly be a valid >> >> >> source of LOAD_PAYLOAD. >> >> >> --- >> >> > >> >> > The function only seems to test inst->dst.file == MRF. I don't see any >> >> > code for handling MRF sources. What am I missing? >> >> >> >> That test is for "handling" MRF sources -- More precisely, it's >> >> collecting the writemask and half flags for MRF writes, which can only >> >> possibly be useful if we're going to use them later on to read something >> >> out of an MRF into a payload, which we shouldn't be doing in the first >> >> place. >> >> >> >> Aside from simplifying the function somewhat, that allows us to drop the >> >> 16 register gap reserved for MRFs at register offset zero, what will >> >> allow us to drop the vgrf_to_reg[] offset calculation completely (also >> >> in split_virtual_grfs()) in a future patch (not sent for review yet). >> >> >> > >> > No, we do read from MRF's sort-of... Send messages have an implicit >> "read" >> > from an MRF. >> >> Heh, and that's pretty much the only way you "read" from it. >> >> > This was written precicely so that we could use LOAD_PAYLOAD >> > to build MRF payloads. We do on pre-GEN6. >> > >> I'm aware, but you don't need any of this meta-data to LOAD_PAYLOAD >> *into* an MRF, and LOAD_PAYLOAD with an MRF as source should be illegal >> anyway. >> > > And no one is using it that way. All of the metadata checks you are > deleting are checks on the *destination*. > Didn't you write this code yourself? The only use for the collected metadata is initializing the instruction flags of the MOVs subsequent LOAD_PAYLOAD instructions are lowered to, based on the metadata already collected for its source registers, which can never be MRFs, so the metadata you collect from MRF writes is never actually used. > >> > >> >> ___ >> >> mesa-dev mailing list >> >> mesa-dev@lists.freedesktop.org >> >> http://lists.freedesktop.org/mailman/listinfo/mesa-dev >> >> >> >> >> pgpznbosO3BD6.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/3] gallium: add double opcodes and TGSI execution (v3.1)
I've addressed most of these,
>>
>> + /* double modifiers handled by caller */
>> + if (dtype)
>> + return;
>
> Should the below code just get moved to fetch_source? Or does it rely
> on local args which makes that a pain? If it's not too hard, I think
> it'd be a lot cleaner / clearer than an extra param here.
I've reworked it, for fetch_source its not so bad, for store_dest its a
bit messy as it needs to return the dst pointer but with that it isn't
that much uglier. I'll post a followup.
>> +
>> + wmask = inst->Dst[0].Register.WriteMask;
>> + if (wmask & TGSI_WRITEMASK_XY) {
>
> Please comment as to why this is written differently than the
> unary/trinary cases. I assume it's for something like DSLT?
Okay added something small here.
>> +}
>> +
>> diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c
>> b/src/gallium/auxiliary/tgsi/tgsi_info.c
>> index c90d24c..8313722 100644
>> --- a/src/gallium/auxiliary/tgsi/tgsi_info.c
>> +++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
>> @@ -231,10 +231,33 @@ static const struct tgsi_opcode_info
>> opcode_info[TGSI_OPCODE_LAST] =
>> { 1, 1, 0, 0, 0, 0, COMP, "LSB", TGSI_OPCODE_LSB },
>> { 1, 1, 0, 0, 0, 0, COMP, "IMSB", TGSI_OPCODE_IMSB },
>> { 1, 1, 0, 0, 0, 0, COMP, "UMSB", TGSI_OPCODE_UMSB },
>> -
>> { 1, 1, 0, 0, 0, 0, OTHR, "INTERP_CENTROID", TGSI_OPCODE_INTERP_CENTROID
>> },
>> { 1, 2, 0, 0, 0, 0, OTHR, "INTERP_SAMPLE", TGSI_OPCODE_INTERP_SAMPLE },
>> { 1, 2, 0, 0, 0, 0, OTHR, "INTERP_OFFSET", TGSI_OPCODE_INTERP_OFFSET },
>> + { 1, 1, 0, 0, 0, 0, COMP, "F2D", TGSI_OPCODE_F2D },
>
> I'd group these with the other COMP ones... That's why I had added the
> whitespace for INTERP_*.
eh? these are in opcode order, grouping them makes no sense.
I've updated all the docs with the correct channel assignments as well.
Dave.
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[Mesa-dev] [PATCH] gallium: add double opcodes and TGSI execution (v4.1)
This patch adds support for a set of double opcodes
to TGSI. It is an update of work done originally
by Michal Krol on the gallium-double-opcodes branch.
The opcodes have a hint where they came from in the
header file.
v2: add unsigned/int <-> double
v2.1: update docs.
v3: add DRSQ (Glenn), fix review comments (Glenn).
v4: drop DDIV
v4.1: cleanups, fix some docs bugs, (Ilia)
rework store_dest and fetch_source fns. (Ilia)
This is based on code by Michael Krol
Signed-off-by: Dave Airlie
---
src/gallium/auxiliary/tgsi/tgsi_exec.c | 765 -
src/gallium/auxiliary/tgsi/tgsi_info.c | 24 +-
src/gallium/docs/source/tgsi.rst | 92 +++-
src/gallium/include/pipe/p_shader_tokens.h | 26 +-
4 files changed, 877 insertions(+), 30 deletions(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c
b/src/gallium/auxiliary/tgsi/tgsi_exec.c
index 834568b..1deca82 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
@@ -72,6 +72,16 @@
#define TILE_BOTTOM_LEFT 2
#define TILE_BOTTOM_RIGHT 3
+union tgsi_double_channel {
+ double d[TGSI_QUAD_SIZE];
+ unsigned u[TGSI_QUAD_SIZE][2];
+};
+
+struct tgsi_double_vector {
+ union tgsi_double_channel xy;
+ union tgsi_double_channel zw;
+};
+
static void
micro_abs(union tgsi_exec_channel *dst,
const union tgsi_exec_channel *src)
@@ -147,6 +157,55 @@ micro_cos(union tgsi_exec_channel *dst,
}
static void
+micro_d2f(union tgsi_exec_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst->f[0] = (float)src->d[0];
+ dst->f[1] = (float)src->d[1];
+ dst->f[2] = (float)src->d[2];
+ dst->f[3] = (float)src->d[3];
+}
+
+static void
+micro_d2i(union tgsi_exec_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst->i[0] = (int)src->d[0];
+ dst->i[1] = (int)src->d[1];
+ dst->i[2] = (int)src->d[2];
+ dst->i[3] = (int)src->d[3];
+}
+
+static void
+micro_d2u(union tgsi_exec_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst->u[0] = (unsigned)src->d[0];
+ dst->u[1] = (unsigned)src->d[1];
+ dst->u[2] = (unsigned)src->d[2];
+ dst->u[3] = (unsigned)src->d[3];
+}
+static void
+micro_dabs(union tgsi_double_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst->d[0] = src->d[0] >= 0.0 ? src->d[0] : -src->d[0];
+ dst->d[1] = src->d[1] >= 0.0 ? src->d[1] : -src->d[1];
+ dst->d[2] = src->d[2] >= 0.0 ? src->d[2] : -src->d[2];
+ dst->d[3] = src->d[3] >= 0.0 ? src->d[3] : -src->d[3];
+}
+
+static void
+micro_dadd(union tgsi_double_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst->d[0] = src[0].d[0] + src[1].d[0];
+ dst->d[1] = src[0].d[1] + src[1].d[1];
+ dst->d[2] = src[0].d[2] + src[1].d[2];
+ dst->d[3] = src[0].d[3] + src[1].d[3];
+}
+
+static void
micro_ddx(union tgsi_exec_channel *dst,
const union tgsi_exec_channel *src)
{
@@ -167,6 +226,158 @@ micro_ddy(union tgsi_exec_channel *dst,
}
static void
+micro_dmul(union tgsi_double_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst->d[0] = src[0].d[0] * src[1].d[0];
+ dst->d[1] = src[0].d[1] * src[1].d[1];
+ dst->d[2] = src[0].d[2] * src[1].d[2];
+ dst->d[3] = src[0].d[3] * src[1].d[3];
+}
+
+static void
+micro_dmax(union tgsi_double_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst->d[0] = src[0].d[0] > src[1].d[0] ? src[0].d[0] : src[1].d[0];
+ dst->d[1] = src[0].d[1] > src[1].d[1] ? src[0].d[1] : src[1].d[1];
+ dst->d[2] = src[0].d[2] > src[1].d[2] ? src[0].d[2] : src[1].d[2];
+ dst->d[3] = src[0].d[3] > src[1].d[3] ? src[0].d[3] : src[1].d[3];
+}
+
+static void
+micro_dmin(union tgsi_double_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst->d[0] = src[0].d[0] < src[1].d[0] ? src[0].d[0] : src[1].d[0];
+ dst->d[1] = src[0].d[1] < src[1].d[1] ? src[0].d[1] : src[1].d[1];
+ dst->d[2] = src[0].d[2] < src[1].d[2] ? src[0].d[2] : src[1].d[2];
+ dst->d[3] = src[0].d[3] < src[1].d[3] ? src[0].d[3] : src[1].d[3];
+}
+
+static void
+micro_dneg(union tgsi_double_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst->d[0] = -src->d[0];
+ dst->d[1] = -src->d[1];
+ dst->d[2] = -src->d[2];
+ dst->d[3] = -src->d[3];
+}
+
+static void
+micro_dslt(union tgsi_double_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst->u[0][0] = src[0].d[0] < src[1].d[0] ? ~0U : 0U;
+ dst->u[1][0] = src[0].d[1] < src[1].d[1] ? ~0U : 0U;
+ dst->u[2][0] = src[0].d[2] < src[1].d[2] ? ~0U : 0U;
+ dst->u[3][0] = src[0].d[3] < src[1].d[3] ? ~0U : 0U;
+}
+
+static void
+micro_dsne(union tgsi_double_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst->u[0][0] = src[0].d[0] != src[1].d[0] ? ~0U : 0U;
+ dst->u[1][0] = src[0].d[1] != src[1].d[1] ? ~0U : 0U;
+ dst->u[2][0] = src[0].d[2] != src[1].d[2] ? ~0U : 0U;
+ dst->u[3][0] = src[0].d[3] != src[1].d
Re: [Mesa-dev] [PATCH 10/32] i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().
On Thu, Feb 19, 2015 at 1:25 PM, Francisco Jerez wrote: > Jason Ekstrand writes: > > > On Thu, Feb 19, 2015 at 12:13 PM, Francisco Jerez > > > wrote: > > > >> Jason Ekstrand writes: > >> > >> > On Fri, Feb 6, 2015 at 4:01 PM, Francisco Jerez < > curroje...@riseup.net> > >> > wrote: > >> > > >> >> Hey Matt, > >> >> > >> >> Matt Turner writes: > >> >> > >> >> > On Fri, Feb 6, 2015 at 6:42 AM, Francisco Jerez < > >> curroje...@riseup.net> > >> >> wrote: > >> >> >> MRFs cannot be read from anyway so they cannot possibly be a valid > >> >> >> source of LOAD_PAYLOAD. > >> >> >> --- > >> >> > > >> >> > The function only seems to test inst->dst.file == MRF. I don't see > any > >> >> > code for handling MRF sources. What am I missing? > >> >> > >> >> That test is for "handling" MRF sources -- More precisely, it's > >> >> collecting the writemask and half flags for MRF writes, which can > only > >> >> possibly be useful if we're going to use them later on to read > something > >> >> out of an MRF into a payload, which we shouldn't be doing in the > first > >> >> place. > >> >> > >> >> Aside from simplifying the function somewhat, that allows us to drop > the > >> >> 16 register gap reserved for MRFs at register offset zero, what will > >> >> allow us to drop the vgrf_to_reg[] offset calculation completely > (also > >> >> in split_virtual_grfs()) in a future patch (not sent for review yet). > >> >> > >> > > >> > No, we do read from MRF's sort-of... Send messages have an implicit > >> "read" > >> > from an MRF. > >> > >> Heh, and that's pretty much the only way you "read" from it. > >> > >> > This was written precicely so that we could use LOAD_PAYLOAD > >> > to build MRF payloads. We do on pre-GEN6. > >> > > >> I'm aware, but you don't need any of this meta-data to LOAD_PAYLOAD > >> *into* an MRF, and LOAD_PAYLOAD with an MRF as source should be illegal > >> anyway. > >> > > > > And no one is using it that way. All of the metadata checks you are > > deleting are checks on the *destination*. > > > > Didn't you write this code yourself? The only use for the collected > metadata is initializing the instruction flags of the MOVs subsequent > LOAD_PAYLOAD instructions are lowered to, based on the metadata already > collected for its source registers, which can never be MRFs, so the > metadata you collect from MRF writes is never actually used. > Right... I misred something initially. Yes, we should never be tracking MRF's as a source of a LOAD_PAYLOAD. I'll give it a better look a bit later, but it looks better. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] nir: add missing GLSL_TYPE_DOUBLE case in type_size()
Reviewed-by: Jason Ekstrand
On Thu, Feb 19, 2015 at 12:51 PM, Brian Paul wrote:
> To silence compiler warning about unhandled switch case.
> v2: move GLSL_TYPE_DOUBLE to the "not reached" section, per Ilia.
> ---
> src/glsl/nir/nir_lower_io.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/glsl/nir/nir_lower_io.c b/src/glsl/nir/nir_lower_io.c
> index ddbc249..207f8da 100644
> --- a/src/glsl/nir/nir_lower_io.c
> +++ b/src/glsl/nir/nir_lower_io.c
> @@ -69,6 +69,7 @@ type_size(const struct glsl_type *type)
>return 0;
> case GLSL_TYPE_VOID:
> case GLSL_TYPE_ERROR:
> + case GLSL_TYPE_DOUBLE:
>unreachable("not reached");
> }
>
> --
> 1.9.1
>
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Re: [Mesa-dev] [PATCH] st/mesa: fix sampler view reference counting bug in glDraw/CopyPixels
On Wed, Feb 18, 2015 at 1:20 PM, Brian Paul wrote:
> Use pipe_sampler_view_reference() instead of ordinary assignment.
> Also add a new sanity check assertion.
>
> Fixes piglit gl-1.0-drawpixels-color-index test crash. But note
> that the test still fails.
Fails on nvc0 as well, for the record.
>
> Cc: "10.4, 10.5"
> ---
> src/mesa/state_tracker/st_cb_drawpixels.c | 13 +
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c
> b/src/mesa/state_tracker/st_cb_drawpixels.c
> index 939fc20..3d13b5c 100644
> --- a/src/mesa/state_tracker/st_cb_drawpixels.c
> +++ b/src/mesa/state_tracker/st_cb_drawpixels.c
> @@ -1154,8 +1154,10 @@ st_DrawPixels(struct gl_context *ctx, GLint x, GLint y,
>
>color = NULL;
>if (st->pixel_xfer.pixelmap_enabled) {
> - sv[1] = st->pixel_xfer.pixelmap_sampler_view;
> - num_sampler_view++;
> + sv[1] = NULL;
> + pipe_sampler_view_reference(&sv[1],
> + st->pixel_xfer.pixelmap_sampler_view);
I would *much* prefer a = {NULL} when sv is declared instead of
awkwardly before the reference (both here and in st_CopyPixels).
With that changed, Reviewed-by: Ilia Mirkin
> + num_sampler_view++;
>}
> }
>
> @@ -1176,7 +1178,8 @@ st_DrawPixels(struct gl_context *ctx, GLint x, GLint y,
> if (write_stencil) {
> enum pipe_format stencil_format =
> util_format_stencil_only(pt->format);
> -
> + /* we should not be doing pixel map/transfer (see above) */
> + assert(num_sampler_view == 1);
> sv[1] = st_create_texture_sampler_view_format(st->pipe, pt,
> stencil_format);
> num_sampler_view++;
> @@ -1516,7 +1519,9 @@ st_CopyPixels(struct gl_context *ctx, GLint srcx, GLint
> srcy,
>driver_vp = make_passthrough_vertex_shader(st, GL_FALSE);
>
>if (st->pixel_xfer.pixelmap_enabled) {
> - sv[1] = st->pixel_xfer.pixelmap_sampler_view;
> + sv[1] = NULL;
> + pipe_sampler_view_reference(&sv[1],
> + st->pixel_xfer.pixelmap_sampler_view);
> num_sampler_view++;
>}
> }
> --
> 1.9.1
>
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Re: [Mesa-dev] [PATCH 1/9] i965/fs: Remove type parameter from emit_vs_system_value().
On Wed, Feb 18, 2015 at 9:00 PM, Kenneth Graunke wrote:
> Every VS system value has type D. We can always add this back if that
> changes, but for now, it's extra typing.
>
> Signed-off-by: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
> src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 7 +++
> 2 files changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
> b/src/mesa/drivers/dri/i965/brw_fs.h
> index a2e6192..9375412 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.h
> +++ b/src/mesa/drivers/dri/i965/brw_fs.h
> @@ -259,7 +259,7 @@ public:
> glsl_interp_qualifier interpolation_mode,
> int location, bool mod_centroid,
> bool mod_sample);
> - fs_reg *emit_vs_system_value(enum brw_reg_type type, int location);
> + fs_reg *emit_vs_system_value(int location);
> void emit_interpolation_setup_gen4();
> void emit_interpolation_setup_gen6();
> void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> index 24cc118..a2343c6 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> @@ -51,10 +51,10 @@ extern "C" {
>
>
> fs_reg *
> -fs_visitor::emit_vs_system_value(enum brw_reg_type type, int location)
> +fs_visitor::emit_vs_system_value(int location)
> {
> fs_reg *reg = new(this->mem_ctx)
> - fs_reg(ATTR, VERT_ATTRIB_MAX, type);
> + fs_reg(ATTR, VERT_ATTRIB_MAX, BRW_REGISTER_TYPE_D);
> brw_vs_prog_data *vs_prog_data = (brw_vs_prog_data *) prog_data;
>
> switch (location) {
> @@ -191,8 +191,7 @@ fs_visitor::visit(ir_variable *ir)
>case SYSTEM_VALUE_VERTEX_ID:
>case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
>case SYSTEM_VALUE_INSTANCE_ID:
> - reg = emit_vs_system_value(brw_type_for_base_type(ir->type),
> -ir->data.location);
> + reg = emit_vs_system_value(ir->data.location);
> break;
>case SYSTEM_VALUE_SAMPLE_POS:
> reg = emit_samplepos_setup();
> --
> 2.2.2
>
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Series is:
Reviewed-by: Anuj Phogat
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Re: [Mesa-dev] [PATCH] gallium: add double opcodes and TGSI execution (v4.1)
On Thu, Feb 19, 2015 at 4:53 PM, Dave Airlie wrote:
> This patch adds support for a set of double opcodes
> to TGSI. It is an update of work done originally
> by Michal Krol on the gallium-double-opcodes branch.
>
> The opcodes have a hint where they came from in the
> header file.
>
> v2: add unsigned/int <-> double
> v2.1: update docs.
>
> v3: add DRSQ (Glenn), fix review comments (Glenn).
>
> v4: drop DDIV
> v4.1: cleanups, fix some docs bugs, (Ilia)
> rework store_dest and fetch_source fns. (Ilia)
>
> This is based on code by Michael Krol
>
> Signed-off-by: Dave Airlie
> ---
> src/gallium/auxiliary/tgsi/tgsi_exec.c | 765
> -
> src/gallium/auxiliary/tgsi/tgsi_info.c | 24 +-
> src/gallium/docs/source/tgsi.rst | 92 +++-
> src/gallium/include/pipe/p_shader_tokens.h | 26 +-
> 4 files changed, 877 insertions(+), 30 deletions(-)
>
> diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c
> b/src/gallium/auxiliary/tgsi/tgsi_exec.c
> index 834568b..1deca82 100644
> --- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
> +++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
> @@ -2980,6 +3274,355 @@ exec_endswitch(struct tgsi_exec_machine *mach)
> UPDATE_EXEC_MASK(mach);
> }
>
> +typedef void (* micro_dop)(union tgsi_double_channel *dst,
> + const union tgsi_double_channel *src);
> +
> +static void
> +fetch_double_channel(struct tgsi_exec_machine *mach,
> + union tgsi_double_channel *chan,
> + const struct tgsi_full_src_register *reg,
> + uint chan_0,
> + uint chan_1)
> +{
> + union tgsi_exec_channel src[2];
> + uint i;
> +
> + fetch_source_d(mach, &src[0], reg, chan_0, TGSI_EXEC_DATA_UINT);
> + fetch_source_d(mach, &src[1], reg, chan_1, TGSI_EXEC_DATA_UINT);
> +
> + for (i = 0; i < TGSI_QUAD_SIZE; i++) {
> + chan->u[i][0] = src[0].u[i];
> + chan->u[i][1] = src[1].u[i];
> + }
> + if (reg->Register.Absolute) {
> + micro_dabs(chan, chan);
> + }
> + if (reg->Register.Negate) {
> + micro_dneg(chan, chan);
> + }
> +
remove extra line.
> +}
> +
> +static void
> +store_double_channel(struct tgsi_exec_machine *mach,
> + const union tgsi_double_channel *chan,
> + const struct tgsi_full_dst_register *reg,
> + const struct tgsi_full_instruction *inst,
> + uint chan_0,
> + uint chan_1)
> +{
> + union tgsi_exec_channel dst[2];
> + uint i;
> + union tgsi_double_channel temp;
> + const uint execmask = mach->ExecMask;
add a blank line here
> + switch (inst->Instruction.Saturate) {
> + case TGSI_SAT_NONE:
> + for (i = 0; i < TGSI_QUAD_SIZE; i++)
> + if (execmask & (1 << i)) {
> +dst[0].u[i] = chan->u[i][0];
> +dst[1].u[i] = chan->u[i][1];
> + }
> + break;
> +
> + case TGSI_SAT_ZERO_ONE:
> + for (i = 0; i < TGSI_QUAD_SIZE; i++)
> + if (execmask & (1 << i)) {
> +if (chan->d[i] < 0.0f)
s/f//
> + temp.d[i] = 0.0;
> +else if (chan->d[i] > 1.0f)
s/f//
> + temp.d[i] = 1.0;
> +else
> + temp.d[i] = chan->d[i];
> +
> +dst[0].u[i] = temp.u[i][0];
> +dst[1].u[i] = temp.u[i][1];
> + }
> + break;
> +
> + case TGSI_SAT_MINUS_PLUS_ONE:
> + for (i = 0; i < TGSI_QUAD_SIZE; i++)
> + if (execmask & (1 << i)) {
> +if (chan->d[i] < -1.0)
> + temp.d[i] = -1.0;
> +else if (chan->d[i] > 1.0)
> + temp.d[i] = 1.0;
> +else
> + temp.d[i] = chan->d[i];
> +
> +dst[0].u[i] = temp.u[i][0];
> +dst[1].u[i] = temp.u[i][1];
> + }
> + break;
> +
> + default:
> + assert( 0 );
> + }
> +
> + store_dest_double(mach, &dst[0], reg, inst, chan_0, TGSI_EXEC_DATA_UINT);
> + if (chan_1 != -1)
> + store_dest_double(mach, &dst[1], reg, inst, chan_1,
> TGSI_EXEC_DATA_UINT);
> +}
[...]
> +static void
> +exec_dldexp(struct tgsi_exec_machine *mach,
> +const struct tgsi_full_instruction *inst)
> +{
> + union tgsi_double_channel src0;
> + union tgsi_exec_channel src1;
> + union tgsi_double_channel dst;
> + int wmask;
> +
> + wmask = inst->Dst[0].Register.WriteMask;
> + if (wmask & TGSI_WRITEMASK_XY) {
> +
remove extra line
> + fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_X,
> TGSI_CHAN_Y);
> + fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_X,
> TGSI_EXEC_DATA_INT);
> + micro_dldexp(&dst, &src0, &src1);
> + store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X,
> TGSI_CHAN_Y);
> + }
> +
> + if (wmask & TGSI_WRITEMASK_ZW) {
> + fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_Z,
> TGSI_CHAN_W);
> + fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_Z
Re: [Mesa-dev] [PATCH] st/mesa: fix sampler view reference counting bug in glDraw/CopyPixels
On 02/19/2015 02:55 PM, Ilia Mirkin wrote:
On Wed, Feb 18, 2015 at 1:20 PM, Brian Paul wrote:
Use pipe_sampler_view_reference() instead of ordinary assignment.
Also add a new sanity check assertion.
Fixes piglit gl-1.0-drawpixels-color-index test crash. But note
that the test still fails.
Fails on nvc0 as well, for the record.
Yeah, it's a state tracker issue. I started working on a fix but it's
not high priority ATM.
Cc: "10.4, 10.5"
---
src/mesa/state_tracker/st_cb_drawpixels.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c
b/src/mesa/state_tracker/st_cb_drawpixels.c
index 939fc20..3d13b5c 100644
--- a/src/mesa/state_tracker/st_cb_drawpixels.c
+++ b/src/mesa/state_tracker/st_cb_drawpixels.c
@@ -1154,8 +1154,10 @@ st_DrawPixels(struct gl_context *ctx, GLint x, GLint y,
color = NULL;
if (st->pixel_xfer.pixelmap_enabled) {
- sv[1] = st->pixel_xfer.pixelmap_sampler_view;
- num_sampler_view++;
+ sv[1] = NULL;
+ pipe_sampler_view_reference(&sv[1],
+ st->pixel_xfer.pixelmap_sampler_view);
I would *much* prefer a = {NULL} when sv is declared instead of
awkwardly before the reference (both here and in st_CopyPixels).
With that changed, Reviewed-by: Ilia Mirkin
Will do. Thx.
-Brian
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[Mesa-dev] [PATCH] glsl: add lowering for double divide to rcp/mul
From: Dave Airlie
It looks like no hw does div anyways, so we should just
lower at the GLSL level.
Signed-off-by: Dave Airlie
---
src/glsl/lower_instructions.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/glsl/lower_instructions.cpp b/src/glsl/lower_instructions.cpp
index e8a69e7..ac6715b 100644
--- a/src/glsl/lower_instructions.cpp
+++ b/src/glsl/lower_instructions.cpp
@@ -199,7 +199,7 @@ lower_instructions_visitor::sub_to_add_neg(ir_expression
*ir)
void
lower_instructions_visitor::div_to_mul_rcp(ir_expression *ir)
{
- assert(ir->operands[1]->type->is_float());
+ assert(ir->operands[1]->type->is_float() ||
ir->operands[1]->type->is_double());
/* New expression for the 1.0 / op1 */
ir_rvalue *expr;
@@ -327,7 +327,7 @@ lower_instructions_visitor::mod_to_floor(ir_expression *ir)
/* Don't generate new IR that would need to be lowered in an additional
* pass.
*/
- if (lowering(DIV_TO_MUL_RCP) && ir->type->is_float())
+ if (lowering(DIV_TO_MUL_RCP) && (ir->type->is_float() ||
ir->type->is_double()))
div_to_mul_rcp(div_expr);
ir_expression *const floor_expr =
@@ -1014,7 +1014,7 @@ lower_instructions_visitor::visit_leave(ir_expression *ir)
case ir_binop_div:
if (ir->operands[1]->type->is_integer() && lowering(INT_DIV_TO_MUL_RCP))
int_div_to_mul_rcp(ir);
- else if (ir->operands[1]->type->is_float() && lowering(DIV_TO_MUL_RCP))
+ else if ((ir->operands[1]->type->is_float() ||
ir->operands[1]->type->is_double())&& lowering(DIV_TO_MUL_RCP))
div_to_mul_rcp(ir);
break;
--
1.9.3
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Re: [Mesa-dev] [PATCH] glsl: add lowering for double divide to rcp/mul
On Thu, Feb 19, 2015 at 5:47 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> It looks like no hw does div anyways, so we should just
> lower at the GLSL level.
Sounds like radeonsi has helpers for DDIV, but they can work this out
when they add support in mesa. Like not using DIV_TO_MUL_RCP lowering.
>
> Signed-off-by: Dave Airlie
> ---
> src/glsl/lower_instructions.cpp | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/src/glsl/lower_instructions.cpp b/src/glsl/lower_instructions.cpp
> index e8a69e7..ac6715b 100644
> --- a/src/glsl/lower_instructions.cpp
> +++ b/src/glsl/lower_instructions.cpp
> @@ -199,7 +199,7 @@ lower_instructions_visitor::sub_to_add_neg(ir_expression
> *ir)
> void
> lower_instructions_visitor::div_to_mul_rcp(ir_expression *ir)
> {
> - assert(ir->operands[1]->type->is_float());
> + assert(ir->operands[1]->type->is_float() ||
> ir->operands[1]->type->is_double());
>
> /* New expression for the 1.0 / op1 */
> ir_rvalue *expr;
> @@ -327,7 +327,7 @@ lower_instructions_visitor::mod_to_floor(ir_expression
> *ir)
> /* Don't generate new IR that would need to be lowered in an additional
> * pass.
> */
> - if (lowering(DIV_TO_MUL_RCP) && ir->type->is_float())
> + if (lowering(DIV_TO_MUL_RCP) && (ir->type->is_float() ||
> ir->type->is_double()))
>div_to_mul_rcp(div_expr);
>
> ir_expression *const floor_expr =
> @@ -1014,7 +1014,7 @@ lower_instructions_visitor::visit_leave(ir_expression
> *ir)
> case ir_binop_div:
>if (ir->operands[1]->type->is_integer() &&
> lowering(INT_DIV_TO_MUL_RCP))
> int_div_to_mul_rcp(ir);
> - else if (ir->operands[1]->type->is_float() && lowering(DIV_TO_MUL_RCP))
> + else if ((ir->operands[1]->type->is_float() ||
> ir->operands[1]->type->is_double())&& lowering(DIV_TO_MUL_RCP))
80 chars. And space around &&.
With that fixed, Reviewed-by: Ilia Mirkin
> div_to_mul_rcp(ir);
>break;
>
> --
> 1.9.3
>
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[Mesa-dev] [PATCH] intel: fix EGLImage renderbuffer _BaseFormat
Correctly set _BaseFormat field when creating a gl_renderbuffer with EGLImage storage. Signed-off-by: Frank Henigman Reviewed-by: Stéphane Marchesin --- src/mesa/drivers/dri/i915/intel_fbo.c | 3 +-- src/mesa/drivers/dri/i965/intel_fbo.c | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) Otherwise, when using gles, _BaseFormat is set to 0 and a glReadPixels from the buffer hits an assert. Tested on i965. Compiled for i915. diff --git a/src/mesa/drivers/dri/i915/intel_fbo.c b/src/mesa/drivers/dri/i915/intel_fbo.c index ead1b17..6c2e181 100644 --- a/src/mesa/drivers/dri/i915/intel_fbo.c +++ b/src/mesa/drivers/dri/i915/intel_fbo.c @@ -287,8 +287,7 @@ intel_image_target_renderbuffer_storage(struct gl_context *ctx, rb->Width = image->region->width; rb->Height = image->region->height; rb->Format = image->format; - rb->_BaseFormat = _mesa_base_fbo_format(&intel->ctx, - image->internal_format); + rb->_BaseFormat = _mesa_get_format_base_format(image->format); rb->NeedsFinishRenderTexture = true; } diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index 174cea0..9394018 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.c +++ b/src/mesa/drivers/dri/i965/intel_fbo.c @@ -398,7 +398,7 @@ intel_image_target_renderbuffer_storage(struct gl_context *ctx, rb->Width = image->width; rb->Height = image->height; rb->Format = image->format; - rb->_BaseFormat = _mesa_base_fbo_format(ctx, image->internal_format); + rb->_BaseFormat = _mesa_get_format_base_format(image->format); rb->NeedsFinishRenderTexture = true; irb->layer_count = 1; } -- 2.2.0.rc0.207.ga3a616c ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] st/mesa: add st fp64 support (v7)
From: Dave Airlie
v2 : add double to int/unsigned conversion
v3: handle fp64 consts better
v4: use DRSQ
v4.1: add d2b
v4.2: drop DDIV
v5: split out some prep patches.
v5.1: add some comments.
v5.2: more comments
v6: simplify down the double instruction
generation loop.
v7: Merge Ilia's two cleanup patches.
Signed-off-by: Dave Airlie
---
src/mesa/state_tracker/st_extensions.c | 6 +
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 578 ++---
2 files changed, 458 insertions(+), 126 deletions(-)
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index 9137a50..ce29d07 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -900,4 +900,10 @@ void st_init_extensions(struct pipe_screen *screen,
PIPE_VIDEO_CAP_SUPPORTS_INTERLACED)) {
extensions->NV_vdpau_interop = GL_TRUE;
}
+
+ if (screen->get_shader_param(screen, PIPE_SHADER_VERTEX,
+PIPE_SHADER_CAP_DOUBLES) &&
+ screen->get_shader_param(screen, PIPE_SHADER_FRAGMENT,
+PIPE_SHADER_CAP_DOUBLES))
+ extensions->ARB_gpu_shader_fp64 = GL_TRUE;
}
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 56502fb..003d280 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -229,7 +229,7 @@ public:
DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction)
unsigned op;
- st_dst_reg dst[1];
+ st_dst_reg dst[2];
st_src_reg src[4];
/** Pointer to the ir source this tree came from for debugging */
ir_instruction *ir;
@@ -262,16 +262,17 @@ public:
class immediate_storage : public exec_node {
public:
- immediate_storage(gl_constant_value *values, int size, int type)
+ immediate_storage(gl_constant_value *values, int size32, int type)
{
- memcpy(this->values, values, size * sizeof(gl_constant_value));
- this->size = size;
+ memcpy(this->values, values, size32 * sizeof(gl_constant_value));
+ this->size32 = size32;
this->type = type;
}
+ /* doubles are stored across 2 gl_constant_values */
gl_constant_value values[4];
- int size; /**< Number of components (1-4) */
- int type; /**< GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
+ int size32; /**< Number of 32-bit components (1-4) */
+ int type; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
};
class function_entry : public exec_node {
@@ -334,7 +335,7 @@ public:
variable_storage *find_variable_storage(ir_variable *var);
- int add_constant(gl_register_file file, gl_constant_value values[4],
+ int add_constant(gl_register_file file, gl_constant_value values[8],
int size, int datatype, GLuint *swizzle_out);
function_entry *get_function_signature(ir_function_signature *sig);
@@ -342,6 +343,7 @@ public:
st_src_reg get_temp(const glsl_type *type);
void reladdr_to_temp(ir_instruction *ir, st_src_reg *reg, int *num_reladdr);
+ st_src_reg st_src_reg_for_double(double val);
st_src_reg st_src_reg_for_float(float val);
st_src_reg st_src_reg_for_int(int val);
st_src_reg st_src_reg_for_type(int type, int val);
@@ -397,6 +399,10 @@ public:
st_dst_reg dst, st_src_reg src0);
glsl_to_tgsi_instruction *emit(ir_instruction *ir, unsigned op,
+ st_dst_reg dst, st_dst_reg dst1,
+ st_src_reg src0);
+
+ glsl_to_tgsi_instruction *emit(ir_instruction *ir, unsigned op,
st_dst_reg dst, st_src_reg src0, st_src_reg
src1);
glsl_to_tgsi_instruction *emit(ir_instruction *ir, unsigned op,
@@ -408,6 +414,11 @@ public:
st_src_reg src0, st_src_reg src1,
st_src_reg src2, st_src_reg src3);
+ glsl_to_tgsi_instruction *emit(ir_instruction *ir, unsigned op,
+ st_dst_reg dst, st_dst_reg dst1,
+ st_src_reg src0, st_src_reg src1,
+ st_src_reg src2, st_src_reg src3);
+
unsigned get_opcode(ir_instruction *ir, unsigned op,
st_dst_reg dst,
st_src_reg src0, st_src_reg src1);
@@ -432,6 +443,7 @@ public:
void emit_scs(ir_instruction *ir, unsigned op,
st_dst_reg dst, const st_src_reg &src);
+
bool try_emit_mad(ir_expression *ir,
int mul_operand);
bool try_emit_mad_for_and_not(ir_expression *ir,
@@ -451,6 +463,8 @@ public:
void copy_propagate(void);
int eliminate_dead_code(void);
+
+ void merge_two_dsts(void);
void merge_registers(void);
void renumber_registers(void);
@@ -464,7 +478,6 @@ public:
static st_src_reg undef_src = st_src_reg(PROGRA
Re: [Mesa-dev] [PATCH 1/3] i965/fs: Add unit tests for saturate propagation pass.
This patch is
Reviewed-by: Ian Romanick
On 02/11/2015 02:54 PM, Matt Turner wrote:
> Cc:
> ---
> src/mesa/drivers/dri/i965/Makefile.am | 7 +
> .../dri/i965/test_fs_saturate_propagation.cpp | 355
> +
> 2 files changed, 362 insertions(+)
> create mode 100644 src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
>
> diff --git a/src/mesa/drivers/dri/i965/Makefile.am
> b/src/mesa/drivers/dri/i965/Makefile.am
> index 07eefce..53e91fe 100644
> --- a/src/mesa/drivers/dri/i965/Makefile.am
> +++ b/src/mesa/drivers/dri/i965/Makefile.am
> @@ -54,6 +54,7 @@ TEST_LIBS = \
>
> TESTS = \
> test_fs_cmod_propagation \
> + test_fs_saturate_propagation \
> test_eu_compact \
> test_vf_float_conversions \
> test_vec4_copy_propagation \
> @@ -67,6 +68,12 @@ test_fs_cmod_propagation_LDADD = \
> $(TEST_LIBS) \
> $(top_builddir)/src/gtest/libgtest.la
>
> +test_fs_saturate_propagation_SOURCES = \
> + test_fs_saturate_propagation.cpp
> +test_fs_saturate_propagation_LDADD = \
> + $(TEST_LIBS) \
> + $(top_builddir)/src/gtest/libgtest.la
> +
> test_vf_float_conversions_SOURCES = \
> test_vf_float_conversions.cpp
> test_vf_float_conversions_LDADD = \
> diff --git a/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
> b/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
> new file mode 100644
> index 000..2000830
> --- /dev/null
> +++ b/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
> @@ -0,0 +1,355 @@
> +/*
> + * Copyright © 2015 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include
> +#include "brw_fs.h"
> +#include "brw_cfg.h"
> +#include "program/program.h"
> +
> +class saturate_propagation_test : public ::testing::Test {
> + virtual void SetUp();
> +
> +public:
> + struct brw_context *brw;
> + struct gl_context *ctx;
> + struct brw_wm_prog_data *prog_data;
> + struct gl_shader_program *shader_prog;
> + struct brw_fragment_program *fp;
> + fs_visitor *v;
> +};
> +
> +class saturate_propagation_fs_visitor : public fs_visitor
> +{
> +public:
> + saturate_propagation_fs_visitor(struct brw_context *brw,
> + struct brw_wm_prog_data *prog_data,
> + struct gl_shader_program *shader_prog)
> + : fs_visitor(brw, NULL, NULL, prog_data, shader_prog, NULL, 8) {}
> +};
> +
> +
> +void saturate_propagation_test::SetUp()
> +{
> + brw = (struct brw_context *)calloc(1, sizeof(*brw));
> + ctx = &brw->ctx;
> +
> + fp = ralloc(NULL, struct brw_fragment_program);
> + prog_data = ralloc(NULL, struct brw_wm_prog_data);
> + shader_prog = ralloc(NULL, struct gl_shader_program);
> +
> + v = new saturate_propagation_fs_visitor(brw, prog_data, shader_prog);
> +
> + _mesa_init_fragment_program(ctx, &fp->program, GL_FRAGMENT_SHADER, 0);
> +
> + brw->gen = 4;
> +}
> +
> +static fs_inst *
> +instruction(bblock_t *block, int num)
> +{
> + fs_inst *inst = (fs_inst *)block->start();
> + for (int i = 0; i < num; i++) {
> + inst = (fs_inst *)inst->next;
> + }
> + return inst;
> +}
> +
> +static bool
> +saturate_propagation(fs_visitor *v)
> +{
> + const bool print = false;
> +
> + if (print) {
> + fprintf(stderr, "= Before =\n");
> + v->cfg->dump(v);
> + }
> +
> + bool ret = v->opt_saturate_propagation();
> +
> + if (print) {
> + fprintf(stderr, "\n= After =\n");
> + v->cfg->dump(v);
> + }
> +
> + return ret;
> +}
> +
> +TEST_F(saturate_propagation_test, basic)
> +{
> + fs_reg dst0 = v->vgrf(glsl_type::float_type);
> + fs_reg dst1 = v->vgrf(glsl_type::float_type);
> + fs_reg src0 = v->vgrf(glsl_type::float_type);
> + fs_reg src1 = v->vgrf(glsl_type::float_type);
> + v->emit(BRW_OPCODE_ADD, dst0, src0, src1);
> + v->emi
Re: [Mesa-dev] [PATCH 2/3] i965/fs: Use fs_inst::overwrites_reg() in saturate propagation.
On 02/11/2015 02:54 PM, Matt Turner wrote:
> This is safer and matches the conditional_mod propagation pass.
>
> Cc:
> ---
> .../dri/i965/brw_fs_saturate_propagation.cpp | 8 ++---
> .../dri/i965/test_fs_saturate_propagation.cpp | 40
> ++
> 2 files changed, 44 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
> index a9966a4..bc51661 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
> @@ -64,10 +64,10 @@ opt_saturate_propagation_local(fs_visitor *v, bblock_t
> *block)
>
>bool interfered = false;
>foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst,
> block) {
> - if (scan_inst->dst.file == GRF &&
> - scan_inst->dst.reg == inst->src[0].reg &&
> - scan_inst->dst.reg_offset == inst->src[0].reg_offset &&
> - !scan_inst->is_partial_write()) {
> + if (scan_inst->overwrites_reg(inst->src[0])) {
> +if (scan_inst->is_partial_write())
> + break;
> +
> if (scan_inst->saturate) {
> inst->saturate = false;
> progress = true;
> diff --git a/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
> b/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
> index 2000830..f897bdd 100644
> --- a/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
> +++ b/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
> @@ -353,3 +353,43 @@ TEST_F(saturate_propagation_test,
> intervening_saturating_copy)
> EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)->opcode);
> EXPECT_FALSE(instruction(block0, 2)->saturate);
> }
> +
> +TEST_F(saturate_propagation_test, intervening_dest_write)
Does this test pass without the other change?
> +{
> + fs_reg dst0 = v->vgrf(glsl_type::vec4_type);
> + fs_reg dst1 = v->vgrf(glsl_type::float_type);
> + fs_reg src0 = v->vgrf(glsl_type::float_type);
> + fs_reg src1 = v->vgrf(glsl_type::float_type);
> + fs_reg src2 = v->vgrf(glsl_type::vec2_type);
> + v->emit(BRW_OPCODE_ADD, offset(dst0, 2), src0, src1);
> + v->emit(SHADER_OPCODE_TEX, dst0, src2)
> + ->regs_written = 4;
> + v->emit(BRW_OPCODE_MOV, dst1, offset(dst0, 2))
> + ->saturate = true;
> +
> + /* = Before =
> +*
> +* 0: add(8)dst0+2 src0src1
> +* 1: tex(8) rlen 4 dst0+0 src2
> +* 2: mov.sat(8)dst1dst0+2
> +*
> +* = After =
> +* (no changes)
> +*/
> +
> + v->calculate_cfg();
> + bblock_t *block0 = v->cfg->blocks[0];
> +
> + EXPECT_EQ(0, block0->start_ip);
> + EXPECT_EQ(2, block0->end_ip);
> +
> + EXPECT_FALSE(saturate_propagation(v));
> + EXPECT_EQ(0, block0->start_ip);
> + EXPECT_EQ(2, block0->end_ip);
> + EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
> + EXPECT_FALSE(instruction(block0, 0)->saturate);
> + EXPECT_EQ(SHADER_OPCODE_TEX, instruction(block0, 1)->opcode);
> + EXPECT_FALSE(instruction(block0, 0)->saturate);
> + EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)->opcode);
> + EXPECT_TRUE(instruction(block0, 2)->saturate);
> +}
>
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Re: [Mesa-dev] [PATCH 3/3] i965/fs: Consider MOV.SAT to interfere if it has a source modifier.
This patch is
Reviewed-by: Ian Romanick
On 02/11/2015 02:54 PM, Matt Turner wrote:
> The saturate propagation pass recognizes that the second instruction
> below does not interfere with an attempt to propagate the saturate
> modifier from instruction 3 to 1.
>
> 1: add(8) dst0 src0 src1
> 2: mov.sat(8) dst1 dst0
> 3: mov.sat(8) dst2 dst0
>
> Unfortunately, we did not consider the case of instruction 2 having a
> source modifier on dst0. Take for instance:
>
> 1: add(8) dst0 src0 src1
> 2: mov.sat(8) dst1 -dst0
> 3: mov.sat(8) dst2 dst0
>
> Consider such an instruction to interfere. Increase instruction counts
> in Anomaly 2, which could be a bug fix depending on the values the first
> instruction produces.
>
> Cc:
> ---
> .../dri/i965/brw_fs_saturate_propagation.cpp | 12 --
> .../dri/i965/test_fs_saturate_propagation.cpp | 44
> ++
> 2 files changed, 52 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
> index bc51661..e406c28 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
> @@ -81,12 +81,16 @@ opt_saturate_propagation_local(fs_visitor *v, bblock_t
> *block)
> break;
> }
> for (int i = 0; i < scan_inst->sources; i++) {
> -if ((scan_inst->opcode != BRW_OPCODE_MOV ||
> !scan_inst->saturate) &&
> -scan_inst->src[i].file == GRF &&
> +if (scan_inst->src[i].file == GRF &&
> scan_inst->src[i].reg == inst->src[0].reg &&
> scan_inst->src[i].reg_offset == inst->src[0].reg_offset) {
> - interfered = true;
> - break;
> + if (scan_inst->opcode != BRW_OPCODE_MOV ||
> + !scan_inst->saturate ||
> + scan_inst->src[0].abs ||
> + scan_inst->src[0].negate) {
> + interfered = true;
> + break;
> + }
> }
> }
>
> diff --git a/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
> b/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
> index f897bdd..6f762bc 100644
> --- a/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
> +++ b/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
> @@ -393,3 +393,47 @@ TEST_F(saturate_propagation_test, intervening_dest_write)
> EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)->opcode);
> EXPECT_TRUE(instruction(block0, 2)->saturate);
> }
> +
> +TEST_F(saturate_propagation_test, mul_neg_mov_sat_mov_sat)
> +{
> + fs_reg dst0 = v->vgrf(glsl_type::float_type);
> + fs_reg dst1 = v->vgrf(glsl_type::float_type);
> + fs_reg dst2 = v->vgrf(glsl_type::float_type);
> + fs_reg src0 = v->vgrf(glsl_type::float_type);
> + fs_reg src1 = v->vgrf(glsl_type::float_type);
> + v->emit(BRW_OPCODE_MUL, dst0, src0, src1);
> + dst0.negate = true;
> + v->emit(BRW_OPCODE_MOV, dst1, dst0)
> + ->saturate = true;
> + dst0.negate = false;
> + v->emit(BRW_OPCODE_MOV, dst2, dst0)
> + ->saturate = true;
> +
> + /* = Before =
> +*
> +* 0: mul(8)dst0 src0 src1
> +* 1: mov.sat(8)dst1 -dst0
> +* 2: mov.sat(8)dst2 dst0
> +*
> +* = After =
> +* (no changes)
> +*/
> +
> + v->calculate_cfg();
> + bblock_t *block0 = v->cfg->blocks[0];
> +
> + EXPECT_EQ(0, block0->start_ip);
> + EXPECT_EQ(2, block0->end_ip);
> +
> + EXPECT_FALSE(saturate_propagation(v));
> + EXPECT_EQ(0, block0->start_ip);
> + EXPECT_EQ(2, block0->end_ip);
> + EXPECT_EQ(BRW_OPCODE_MUL, instruction(block0, 0)->opcode);
> + EXPECT_FALSE(instruction(block0, 0)->saturate);
> + EXPECT_FALSE(instruction(block0, 0)->src[1].negate);
> + EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode);
> + EXPECT_TRUE(instruction(block0, 1)->saturate);
> + EXPECT_TRUE(instruction(block0, 1)->src[0].negate);
> + EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)->opcode);
> + EXPECT_TRUE(instruction(block0, 2)->saturate);
> +}
>
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Re: [Mesa-dev] [PATCH 2/3] i965/fs: Use fs_inst::overwrites_reg() in saturate propagation.
On Thu, Feb 19, 2015 at 3:25 PM, Ian Romanick wrote:
> On 02/11/2015 02:54 PM, Matt Turner wrote:
>> This is safer and matches the conditional_mod propagation pass.
>>
>> Cc:
>> ---
>> .../dri/i965/brw_fs_saturate_propagation.cpp | 8 ++---
>> .../dri/i965/test_fs_saturate_propagation.cpp | 40
>> ++
>> 2 files changed, 44 insertions(+), 4 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
>> b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
>> index a9966a4..bc51661 100644
>> --- a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
>> @@ -64,10 +64,10 @@ opt_saturate_propagation_local(fs_visitor *v, bblock_t
>> *block)
>>
>>bool interfered = false;
>>foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst,
>> block) {
>> - if (scan_inst->dst.file == GRF &&
>> - scan_inst->dst.reg == inst->src[0].reg &&
>> - scan_inst->dst.reg_offset == inst->src[0].reg_offset &&
>> - !scan_inst->is_partial_write()) {
>> + if (scan_inst->overwrites_reg(inst->src[0])) {
>> +if (scan_inst->is_partial_write())
>> + break;
>> +
>> if (scan_inst->saturate) {
>> inst->saturate = false;
>> progress = true;
>> diff --git a/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
>> b/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
>> index 2000830..f897bdd 100644
>> --- a/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
>> +++ b/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
>> @@ -353,3 +353,43 @@ TEST_F(saturate_propagation_test,
>> intervening_saturating_copy)
>> EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)->opcode);
>> EXPECT_FALSE(instruction(block0, 2)->saturate);
>> }
>> +
>> +TEST_F(saturate_propagation_test, intervening_dest_write)
>
> Does this test pass without the other change?
No. The test is for the bug this is fixing.
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Re: [Mesa-dev] [PATCH 1/4] i965: Don't emit saturates for instructions without destinations.
On 02/10/2015 11:09 AM, Matt Turner wrote:
> We were special casing OPCODE_END but no other instructions that have no
> destination, like OPCODE_KIL, leading us to emitting MOVs with null
> destinations.
Should we (or do we somehow already) handle instructions with null
destinations? So...
ADD.sat.nz null, g38, g22
Or is that just impossible?
> total instructions in shared programs: 5950886 -> 5947182 (-0.06%)
> instructions in affected programs: 139700 -> 135996 (-2.65%)
> helped:904
> ---
> src/mesa/drivers/dri/i965/brw_fs_fp.cpp | 2 +-
> src/mesa/drivers/dri/i965/brw_vec4_vp.cpp | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
> index 7f2874d..dd3d331 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
> @@ -517,7 +517,7 @@ fs_visitor::emit_fragment_program_code()
>/* To handle saturates, we emit a MOV with a saturate bit, which
> * optimization should fold into the preceding instructions when safe.
> */
> - if (fpi->Opcode != OPCODE_END) {
> + if (_mesa_num_inst_dst_regs(fpi->Opcode) != 0) {
> fs_reg real_dst = get_fp_dst_reg(&fpi->DstReg);
>
> for (int i = 0; i < 4; i++) {
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
> index 85f2de5..434f032 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
> @@ -387,7 +387,7 @@ vec4_vs_visitor::emit_program_code()
>}
>
>/* Copy the temporary back into the actual destination register. */
> - if (vpi->Opcode != OPCODE_END) {
> + if (_mesa_num_inst_dst_regs(vpi->Opcode) != 0) {
> emit(MOV(get_vp_dst_reg(vpi->DstReg), src_reg(dst)));
>}
> }
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Re: [Mesa-dev] [PATCH 2/4] i965: Use greater-equal cmod to implement maximum.
This patch is
Reviewed-by: Ian Romanick
On 02/10/2015 11:09 AM, Matt Turner wrote:
> The docs specifically call out SEL with .l and .ge as the
> implementations of MIN and MAX respectively. Among other things, SEL
> with these conditional mods are commutative.
> ---
> src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 5 -
> src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp| 6 +++---
> src/mesa/drivers/dri/i965/brw_vec4_vp.cpp | 4 ++--
> src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp | 2 +-
> 4 files changed, 10 insertions(+), 7 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> index 6cddcf5..bca2139 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> @@ -322,6 +322,9 @@ void
> fs_visitor::emit_minmax(enum brw_conditional_mod conditionalmod, const
> fs_reg &dst,
> const fs_reg &src0, const fs_reg &src1)
> {
> + assert(conditionalmod == BRW_CONDITIONAL_GE ||
> + conditionalmod == BRW_CONDITIONAL_L);
> +
> fs_inst *inst;
>
> if (brw->gen >= 6) {
> @@ -1948,7 +1951,7 @@ fs_visitor::rescale_texcoord(fs_reg coordinate, int
> coord_components,
> chan = offset(chan, i);
>
> inst = emit(BRW_OPCODE_SEL, chan, chan, fs_reg(0.0f));
> - inst->conditional_mod = BRW_CONDITIONAL_G;
> + inst->conditional_mod = BRW_CONDITIONAL_GE;
>
> /* Our parameter comes in as 1.0/width or 1.0/height,
>* because that's what people normally want for doing
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> index e6a7ed0..d13c716 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> @@ -513,7 +513,7 @@ vec4_visitor::emit_unpack_snorm_4x8(const dst_reg &dst,
> src_reg src0)
> emit(MUL(scaled, src_reg(f), src_reg(1.0f / 127.0f)));
>
> dst_reg max(this, glsl_type::vec4_type);
> - emit_minmax(BRW_CONDITIONAL_G, max, src_reg(scaled), src_reg(-1.0f));
> + emit_minmax(BRW_CONDITIONAL_GE, max, src_reg(scaled), src_reg(-1.0f));
> emit_minmax(BRW_CONDITIONAL_L, dst, src_reg(max), src_reg(1.0f));
> }
>
> @@ -541,7 +541,7 @@ void
> vec4_visitor::emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0)
> {
> dst_reg max(this, glsl_type::vec4_type);
> - emit_minmax(BRW_CONDITIONAL_G, max, src0, src_reg(-1.0f));
> + emit_minmax(BRW_CONDITIONAL_GE, max, src0, src_reg(-1.0f));
>
> dst_reg min(this, glsl_type::vec4_type);
> emit_minmax(BRW_CONDITIONAL_L, min, src_reg(max), src_reg(1.0f));
> @@ -1673,7 +1673,7 @@ vec4_visitor::visit(ir_expression *ir)
>emit_minmax(BRW_CONDITIONAL_L, result_dst, op[0], op[1]);
>break;
> case ir_binop_max:
> - emit_minmax(BRW_CONDITIONAL_G, result_dst, op[0], op[1]);
> + emit_minmax(BRW_CONDITIONAL_GE, result_dst, op[0], op[1]);
>break;
>
> case ir_binop_pow:
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
> index 434f032..e2d4b7c 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
> @@ -227,7 +227,7 @@ vec4_vs_visitor::emit_program_code()
> /* if (tmp.y < 0) tmp.y = 0; */
> src_reg tmp_y = swizzle(src[0], BRW_SWIZZLE_);
> result.writemask = WRITEMASK_Z;
> - emit_minmax(BRW_CONDITIONAL_G, result, tmp_y, src_reg(0.0f));
> + emit_minmax(BRW_CONDITIONAL_GE, result, tmp_y, src_reg(0.0f));
>
> src_reg clamped_y(result);
> clamped_y.swizzle = BRW_SWIZZLE_;
> @@ -314,7 +314,7 @@ vec4_vs_visitor::emit_program_code()
>}
>
>case OPCODE_MAX:
> - emit_minmax(BRW_CONDITIONAL_G, dst, src[0], src[1]);
> + emit_minmax(BRW_CONDITIONAL_GE, dst, src[0], src[1]);
> break;
>
>case OPCODE_MIN:
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp
> index 72b6ef0..a48b730 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp
> @@ -97,7 +97,7 @@ vec4_vs_visitor::emit_prolog()
> dst.type = brw_type_for_base_type(glsl_type::vec4_type);
> emit(MOV(dst, src_reg(reg_d)));
> emit(MUL(dst, src_reg(dst), src_reg(es3_normalize_factor)));
> - emit_minmax(BRW_CONDITIONAL_G, dst, src_reg(dst),
> src_reg(-1.0f));
> + emit_minmax(BRW_CONDITIONAL_GE, dst, src_reg(dst),
> src_reg(-1.0f));
> } else {
> /* The following equations are from the OpenGL 3.2
> specification:
> *
>
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Re: [Mesa-dev] [PATCH 3/4] i965/blorp: Optimize clamping tex coords.
This patch is
Reviewed-by: Ian Romanick
On 02/10/2015 11:09 AM, Matt Turner wrote:
> Each emit_cond_mov() emits a CMP of its first to arguments using the
> specified conditional mod, followed by a predicated MOV of the fifth
> argument into the fourth. In all four cases here, it was just
> implementing MIN/MAX which we can do in a single SEL instruction.
>
> Also reorder the instructions for a slightly better schedule.
> ---
> src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 8
> src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h | 18 ++
> 2 files changed, 22 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> index 10a53dc..fc111ae 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> @@ -1308,10 +1308,10 @@ brw_blorp_blit_program::clamp_tex_coords(struct
> brw_reg regX,
> struct brw_reg clampX1,
> struct brw_reg clampY1)
> {
> - emit_cond_mov(regX, clampX0, BRW_CONDITIONAL_L, regX, clampX0);
> - emit_cond_mov(regX, clampX1, BRW_CONDITIONAL_G, regX, clampX1);
> - emit_cond_mov(regY, clampY0, BRW_CONDITIONAL_L, regY, clampY0);
> - emit_cond_mov(regY, clampY1, BRW_CONDITIONAL_G, regY, clampY1);
> + emit_max(regX, regX, clampX0);
> + emit_max(regY, regY, clampY0);
> + emit_min(regX, regX, clampX1);
> + emit_min(regY, regY, clampY1);
> }
>
> /**
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
> b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
> index 8953ce8..bfad422 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
> +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
> @@ -85,6 +85,24 @@ protected:
> new (mem_ctx) fs_inst(BRW_OPCODE_LRP, 16, dst, src1, src2, src3));
> }
>
> + inline void emit_min(const struct brw_reg& dst,
> +const struct brw_reg& src1,
> +const struct brw_reg& src2)
> + {
> + fs_inst *inst = new (mem_ctx) fs_inst(BRW_OPCODE_SEL, 16, dst, src1,
> src2);
> + inst->conditional_mod = BRW_CONDITIONAL_L;
> + insts.push_tail(inst);
> + }
> +
> + inline void emit_max(const struct brw_reg& dst,
> +const struct brw_reg& src1,
> +const struct brw_reg& src2)
> + {
> + fs_inst *inst = new (mem_ctx) fs_inst(BRW_OPCODE_SEL, 16, dst, src1,
> src2);
> + inst->conditional_mod = BRW_CONDITIONAL_GE;
> + insts.push_tail(inst);
> + }
> +
> inline void emit_mov(const struct brw_reg& dst, const struct brw_reg& src)
> {
>insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_MOV, 16, dst, src));
>
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Re: [Mesa-dev] [Mesa-stable] [PATCH 2/3] i965/fs: Use fs_inst::overwrites_reg() in saturate propagation.
On 02/19/2015 03:29 PM, Matt Turner wrote:
> On Thu, Feb 19, 2015 at 3:25 PM, Ian Romanick wrote:
>> On 02/11/2015 02:54 PM, Matt Turner wrote:
>>> This is safer and matches the conditional_mod propagation pass.
>>>
>>> Cc:
>>> ---
>>> .../dri/i965/brw_fs_saturate_propagation.cpp | 8 ++---
>>> .../dri/i965/test_fs_saturate_propagation.cpp | 40
>>> ++
>>> 2 files changed, 44 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
>>> b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
>>> index a9966a4..bc51661 100644
>>> --- a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
>>> +++ b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
>>> @@ -64,10 +64,10 @@ opt_saturate_propagation_local(fs_visitor *v, bblock_t
>>> *block)
>>>
>>>bool interfered = false;
>>>foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst,
>>> inst, block) {
>>> - if (scan_inst->dst.file == GRF &&
>>> - scan_inst->dst.reg == inst->src[0].reg &&
>>> - scan_inst->dst.reg_offset == inst->src[0].reg_offset &&
>>> - !scan_inst->is_partial_write()) {
>>> + if (scan_inst->overwrites_reg(inst->src[0])) {
>>> +if (scan_inst->is_partial_write())
>>> + break;
>>> +
>>> if (scan_inst->saturate) {
>>> inst->saturate = false;
>>> progress = true;
>>> diff --git a/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
>>> b/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
>>> index 2000830..f897bdd 100644
>>> --- a/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
>>> +++ b/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
>>> @@ -353,3 +353,43 @@ TEST_F(saturate_propagation_test,
>>> intervening_saturating_copy)
>>> EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)->opcode);
>>> EXPECT_FALSE(instruction(block0, 2)->saturate);
>>> }
>>> +
>>> +TEST_F(saturate_propagation_test, intervening_dest_write)
>>
>> Does this test pass without the other change?
>
> No. The test is for the bug this is fixing.
Okay... then that also answers my follow-up question about the apparent
behavior change in the other hunk. :) This patch is
Reviewed-by: Ian Romanick
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Re: [Mesa-dev] [PATCH 4/4] i965/blorp: Emit MADs.
Assuming that my assumption / recollection that blorp is only for GEN6+,
this patch is
Reviewed-by: Ian Romanick
On 02/10/2015 11:10 AM, Matt Turner wrote:
> Low hanging fruit: cuts a couple of instructions.
> ---
> src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 6 ++
> src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h | 9 +
> 2 files changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> index fc111ae..5c936cf 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> @@ -1255,10 +1255,8 @@ brw_blorp_blit_program::translate_dst_to_src()
> emit_mov(Xp_f, X);
> emit_mov(Yp_f, Y);
> /* Scale and offset */
> - emit_mul(X_f, Xp_f, x_transform.multiplier);
> - emit_mul(Y_f, Yp_f, y_transform.multiplier);
> - emit_add(X_f, X_f, x_transform.offset);
> - emit_add(Y_f, Y_f, y_transform.offset);
> + emit_mad(X_f, x_transform.offset, Xp_f, x_transform.multiplier);
> + emit_mad(Y_f, y_transform.offset, Yp_f, y_transform.multiplier);
> if (key->blit_scaled && key->blend) {
>/* Translate coordinates to lay out the samples in a rectangular grid
> * roughly corresponding to sample locations.
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
> b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
> index bfad422..8e44eb4 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
> +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
> @@ -85,6 +85,15 @@ protected:
> new (mem_ctx) fs_inst(BRW_OPCODE_LRP, 16, dst, src1, src2, src3));
> }
>
> + inline void emit_mad(const struct brw_reg &dst,
> +const struct brw_reg &src1,
> +const struct brw_reg &src2,
> +const struct brw_reg &src3)
> + {
> + insts.push_tail(
> + new (mem_ctx) fs_inst(BRW_OPCODE_MAD, 16, dst, src1, src2, src3));
> + }
> +
> inline void emit_min(const struct brw_reg& dst,
> const struct brw_reg& src1,
> const struct brw_reg& src2)
>
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[Mesa-dev] [PATCH] i965: just avoid warnings with fp64
This just fills in some blanks to avoid warnings in the i965 driver.
Signed-off-by: Dave Airlie
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 1 +
src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp | 13 +
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 14 ++
src/mesa/drivers/dri/i965/brw_shader.cpp | 1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 13 +
5 files changed, 42 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index a562b8a..a2a5234 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -673,6 +673,7 @@ fs_visitor::type_size(const struct glsl_type *type)
case GLSL_TYPE_VOID:
case GLSL_TYPE_ERROR:
case GLSL_TYPE_INTERFACE:
+ case GLSL_TYPE_DOUBLE:
unreachable("not reached");
}
diff --git a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
index cb0a079..c64742c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
@@ -445,6 +445,19 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment
*ir)
case ir_binop_interpolate_at_offset:
case ir_binop_interpolate_at_sample:
unreachable("not reached: expression operates on scalars only");
+
+ case ir_unop_pack_double_2x32:
+ case ir_unop_unpack_double_2x32:
+ case ir_unop_frexp_sig:
+ case ir_unop_frexp_exp:
+ case ir_unop_d2f:
+ case ir_unop_f2d:
+ case ir_unop_d2i:
+ case ir_unop_i2d:
+ case ir_unop_d2u:
+ case ir_unop_u2d:
+ case ir_unop_d2b:
+ unreachable("no fp64 support yet");
}
ir->remove();
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 04e0f9a..7486071 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1192,6 +1192,20 @@ fs_visitor::visit(ir_expression *ir)
case ir_binop_interpolate_at_sample:
unreachable("already handled above");
break;
+
+ case ir_unop_d2f:
+ case ir_unop_f2d:
+ case ir_unop_d2i:
+ case ir_unop_i2d:
+ case ir_unop_d2u:
+ case ir_unop_u2d:
+ case ir_unop_d2b:
+ case ir_unop_pack_double_2x32:
+ case ir_unop_unpack_double_2x32:
+ case ir_unop_frexp_sig:
+ case ir_unop_frexp_exp:
+ unreachable("fp64 todo");
+ break;
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 71146c5..b0e9c82 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -308,6 +308,7 @@ brw_type_for_base_type(const struct glsl_type *type)
case GLSL_TYPE_VOID:
case GLSL_TYPE_ERROR:
case GLSL_TYPE_INTERFACE:
+ case GLSL_TYPE_DOUBLE:
unreachable("not reached");
}
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 562fc30..6154e43 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -612,6 +612,7 @@ type_size(const struct glsl_type *type)
return 0;
case GLSL_TYPE_IMAGE:
case GLSL_TYPE_VOID:
+ case GLSL_TYPE_DOUBLE:
case GLSL_TYPE_ERROR:
case GLSL_TYPE_INTERFACE:
unreachable("not reached");
@@ -1889,6 +1890,18 @@ vec4_visitor::visit(ir_expression *ir)
unreachable("not reached: should not occur in vertex shader");
case ir_binop_ldexp:
unreachable("not reached: should be handled by ldexp_to_arith()");
+ case ir_unop_d2f:
+ case ir_unop_f2d:
+ case ir_unop_d2i:
+ case ir_unop_i2d:
+ case ir_unop_d2u:
+ case ir_unop_u2d:
+ case ir_unop_d2b:
+ case ir_unop_pack_double_2x32:
+ case ir_unop_unpack_double_2x32:
+ case ir_unop_frexp_sig:
+ case ir_unop_frexp_exp:
+ unreachable("fp64 todo");
}
}
--
1.9.3
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Re: [Mesa-dev] [PATCH 1/4] i965: Don't emit saturates for instructions without destinations.
On Thu, Feb 19, 2015 at 3:31 PM, Ian Romanick wrote: > On 02/10/2015 11:09 AM, Matt Turner wrote: >> We were special casing OPCODE_END but no other instructions that have no >> destination, like OPCODE_KIL, leading us to emitting MOVs with null >> destinations. > > Should we (or do we somehow already) handle instructions with null > destinations? So... > > ADD.sat.nz null, g38, g22 > > Or is that just impossible? I don't think that's possible. The cases I saw were because we were emitting MOV.SAT to copy results of instructions that don't have destinations. :) After I made this change, I grepped all of the output of shader-db and found no more MOVs (without conditional mod) with null destinations. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 4/4] i965/blorp: Emit MADs.
On Thu, Feb 19, 2015 at 3:35 PM, Ian Romanick wrote: > Assuming that my assumption / recollection that blorp is only for GEN6+, > this patch is Indeed, that's correct. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] i965/vec4: Add and use byte-MOV instruction for unpack 4x8.
FWIW, this patch is
Reviewed-by: Ian Romanick
On 02/11/2015 06:17 PM, Matt Turner wrote:
> Previously we were using a B/UB source in an Align16 instruction, which
> is illegal. It for some reason works on all platforms, except Broadwell.
>
> Cc: "10.5"
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86811
> ---
> I know! Another instruction for MOV! Sorry!
>
> src/mesa/drivers/dri/i965/brw_defines.h | 1 +
> src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 16
> src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 4 ++--
> 3 files changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index a597d6b..17c27dd 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -911,6 +911,7 @@ enum opcode {
>
> SHADER_OPCODE_URB_WRITE_SIMD8,
>
> + VEC4_OPCODE_MOV_BYTES,
> VEC4_OPCODE_PACK_BYTES,
> VEC4_OPCODE_UNPACK_UNIFORM,
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> index e38e6ea..85a92ee 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> @@ -1513,6 +1513,22 @@ vec4_generator::generate_code(const cfg_t *cfg)
> generate_unpack_flags(inst, dst);
> break;
>
> + case VEC4_OPCODE_MOV_BYTES: {
> + /* Moves the low byte from each channel, using an Align1 access mode
> + * and a <4,1,0> source region.
> + */
> + assert(src[0].type == BRW_REGISTER_TYPE_UB ||
> +src[0].type == BRW_REGISTER_TYPE_B);
> +
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
> + src[0].vstride = BRW_VERTICAL_STRIDE_4;
> + src[0].width = BRW_WIDTH_1;
> + src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
> + brw_MOV(p, dst, src[0]);
> + brw_set_default_access_mode(p, BRW_ALIGN_16);
> + break;
> + }
> +
>case VEC4_OPCODE_PACK_BYTES: {
> /* Is effectively:
>*
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> index 5638105..f15c66a 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> @@ -489,7 +489,7 @@ vec4_visitor::emit_unpack_unorm_4x8(const dst_reg &dst,
> src_reg src0)
>
> shifted.type = BRW_REGISTER_TYPE_UB;
> dst_reg f(this, glsl_type::vec4_type);
> - emit(MOV(f, src_reg(shifted)));
> + emit(VEC4_OPCODE_MOV_BYTES, f, src_reg(shifted));
>
> emit(MUL(dst, src_reg(f), src_reg(1.0f / 255.0f)));
> }
> @@ -511,7 +511,7 @@ vec4_visitor::emit_unpack_snorm_4x8(const dst_reg &dst,
> src_reg src0)
>
> shifted.type = BRW_REGISTER_TYPE_B;
> dst_reg f(this, glsl_type::vec4_type);
> - emit(MOV(f, src_reg(shifted)));
> + emit(VEC4_OPCODE_MOV_BYTES, f, src_reg(shifted));
>
> dst_reg scaled(this, glsl_type::vec4_type);
> emit(MUL(scaled, src_reg(f), src_reg(1.0f / 127.0f)));
>
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Re: [Mesa-dev] [PATCH] st/mesa: add st fp64 support (v7)
On Thu, Feb 19, 2015 at 6:09 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> v2 : add double to int/unsigned conversion
> v3: handle fp64 consts better
> v4: use DRSQ
> v4.1: add d2b
> v4.2: drop DDIV
>
> v5: split out some prep patches.
> v5.1: add some comments.
> v5.2: more comments
>
> v6: simplify down the double instruction
> generation loop.
>
> v7: Merge Ilia's two cleanup patches.
>
> Signed-off-by: Dave Airlie
> ---
> src/mesa/state_tracker/st_extensions.c | 6 +
> src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 578
> ++---
> 2 files changed, 458 insertions(+), 126 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> index 56502fb..003d280 100644
> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> @@ -464,7 +478,6 @@ public:
> static st_src_reg undef_src = st_src_reg(PROGRAM_UNDEFINED, 0,
> GLSL_TYPE_ERROR);
>
> static st_dst_reg undef_dst = st_dst_reg(PROGRAM_UNDEFINED, SWIZZLE_NOOP,
> GLSL_TYPE_ERROR);
> -
> static st_dst_reg address_reg = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
> GLSL_TYPE_FLOAT, 0);
> static st_dst_reg address_reg2 = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
> GLSL_TYPE_FLOAT, 1);
> static st_dst_reg sampler_reladdr = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
> GLSL_TYPE_FLOAT, 2);
Drop this hunk.
> @@ -597,22 +616,129 @@ glsl_to_tgsi_visitor::emit(ir_instruction *ir,
> unsigned op,
>
> this->instructions.push_tail(inst);
>
> + /*
> +* This section contains the double processing.
> +* GLSL just represents doubles as single channel values,
> +* however most HW and TGSI represent doubles as pairs of register
> channels.
> +*
> +* so we have to fixup destination writemask/index and src
> swizzle/indexes.
> +* dest writemasks need to translate from single channel write mask
> +* to a dual-channel writemask, but also need to modify the index,
> +* if we are touching the Z,W fields in the pre-translated writemask.
> +*
> +* src channels have similiar index modifications along with swizzle
> +* changes to we pick the XY, ZW pairs from the correct index.
> +*
> +* GLSL [0].x -> TGSI [0].xy
> +* GLSL [0].y -> TGSI [0].zw
> +* GLSL [0].z -> TGSI [1].xy
> +* GLSL [0].w -> TGSI [1].zw
> +*/
> + if (inst->dst[0].type == GLSL_TYPE_DOUBLE || inst->dst[1].type ==
> GLSL_TYPE_DOUBLE ||
> + inst->src[0].type == GLSL_TYPE_DOUBLE) {
> + glsl_to_tgsi_instruction *dinst = NULL;
> + int initial_src_swz[4], initial_src_idx[4];
> + int initial_dst_idx[2], initial_dst_writemask[2];
> + /* select the writemask for dst0 or dst1 */
> + unsigned writemask = inst->dst[0].file == PROGRAM_UNDEFINED ?
> inst->dst[1].writemask : inst->dst[0].writemask;
> +
> + /* copy out the writemask, index and swizzles for all src/dsts. */
> + for (j = 0; j < 2; j++) {
> + initial_dst_writemask[j] = inst->dst[j].writemask;
> + initial_dst_idx[j] = inst->dst[j].index;
> + }
> +
> + for (j = 0; j < 4; j++) {
> + initial_src_swz[j] = inst->src[j].swizzle;
> + initial_src_idx[j] = inst->src[j].index;
> + }
> +
> + /*
> + * scan all the components in the dst writemask
> + * generate an instruction for each of them if required.
> + */
> + while (writemask) {
> +
> + int i = u_bit_scan(&writemask);
> +
> + /* first time use previous instruction */
> + if (dinst == NULL) {
> +dinst = inst;
> + } else {
> +/* create a new instructions for subsequent attempts */
> +dinst = new(mem_ctx) glsl_to_tgsi_instruction();
> +*dinst = *inst;
> +dinst->next = NULL;
> +dinst->prev = NULL;
> +this->instructions.push_tail(dinst);
> + }
> +
> + /* modify the destination if we are splitting */
> + for (j = 0; j < 2; j++) {
> +if (dinst->dst[j].type == GLSL_TYPE_DOUBLE) {
> + dinst->dst[j].writemask = (i & 1) ? WRITEMASK_ZW :
> WRITEMASK_XY;
> + dinst->dst[j].index = initial_dst_idx[j];
> + if (i > 1)
> + dinst->dst[j].index++;
> +} else {
> + /* if we aren't writing to a double, just get the bit of the
> initial writemask
> + for this channel */
> + dinst->dst[j].writemask = initial_dst_writemask[j] & (1 << i);
> +}
> + }
> +
> + /* modify the src registers */
> + for (j = 0; j < 4; j++) {
> +int swz = GET_SWZ(initial_src_swz[j], i);
> +
> +if (dinst->src[j].type == GLSL_TYPE_DOUBLE) {
> + dinst->src[j].index = initial_src_idx[j];
> + if (swz > 1)
> + dinst->src[j].index++;
> +
> + if (swz & 1)
> +
[Mesa-dev] [PATCH] i965/fs: Set pixel/sample mask for compute shaders atomic ops
For fragment programs, we pull this mask from the payload header. The same mask doesn't exist for compute shaders, so we set all bits to enabled. Note: this mask is ANDed with the execution mask, so some channels may not end up issuing the atomic operation. Signed-off-by: Jordan Justen Cc: Ben Widawsky Cc: Francisco Jerez --- While it's fresh in our minds. :) This seems to work for gen7 & gen8 CS. For CS simd16, we need the 0x change, but it seems to work fine for simd8 as well. I also tested gen8 (simd8vs), and there were no piglit regressions. src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 24cc118..960a0aa 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -2998,9 +2998,9 @@ fs_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index, * mask sent in the header to compute the actual set of channels that execute * the atomic operation. */ - assert(stage == MESA_SHADER_VERTEX); + assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE); emit(MOV(component(sources[0], 7), - brw_imm_ud(0xff)))->force_writemask_all = true; + brw_imm_ud(0x)))->force_writemask_all = true; } length++; @@ -3061,9 +3061,9 @@ fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst, * mask sent in the header to compute the actual set of channels that execute * the atomic operation. */ - assert(stage == MESA_SHADER_VERTEX); + assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE); emit(MOV(component(sources[0], 7), - brw_imm_ud(0xff)))->force_writemask_all = true; + brw_imm_ud(0x)))->force_writemask_all = true; } /* Set the surface read offset. */ -- 2.1.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/4] i965: Don't emit saturates for instructions without destinations.
On 02/19/2015 03:38 PM, Matt Turner wrote: > On Thu, Feb 19, 2015 at 3:31 PM, Ian Romanick wrote: >> On 02/10/2015 11:09 AM, Matt Turner wrote: >>> We were special casing OPCODE_END but no other instructions that have no >>> destination, like OPCODE_KIL, leading us to emitting MOVs with null >>> destinations. >> >> Should we (or do we somehow already) handle instructions with null >> destinations? So... >> >> ADD.sat.nz null, g38, g22 >> >> Or is that just impossible? > > I don't think that's possible. The cases I saw were because we were > emitting MOV.SAT to copy results of instructions that don't have > destinations. :) > > After I made this change, I grepped all of the output of shader-db and > found no more MOVs (without conditional mod) with null destinations. That's about what I figured. This patch is Reviewed-by: Ian Romanick ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: just avoid warnings with fp64
Looks reasonable, if it's going to be a while before an i965 backend is ready..
Reviewed-by: Chris Forbes
On Fri, Feb 20, 2015 at 12:38 PM, Dave Airlie wrote:
> This just fills in some blanks to avoid warnings in the i965 driver.
>
> Signed-off-by: Dave Airlie
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 1 +
> src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp | 13 +
> src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 14 ++
> src/mesa/drivers/dri/i965/brw_shader.cpp | 1 +
> src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 13 +
> 5 files changed, 42 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
> b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index a562b8a..a2a5234 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -673,6 +673,7 @@ fs_visitor::type_size(const struct glsl_type *type)
> case GLSL_TYPE_VOID:
> case GLSL_TYPE_ERROR:
> case GLSL_TYPE_INTERFACE:
> + case GLSL_TYPE_DOUBLE:
>unreachable("not reached");
> }
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
> index cb0a079..c64742c 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
> @@ -445,6 +445,19 @@
> ir_channel_expressions_visitor::visit_leave(ir_assignment *ir)
> case ir_binop_interpolate_at_offset:
> case ir_binop_interpolate_at_sample:
>unreachable("not reached: expression operates on scalars only");
> +
> + case ir_unop_pack_double_2x32:
> + case ir_unop_unpack_double_2x32:
> + case ir_unop_frexp_sig:
> + case ir_unop_frexp_exp:
> + case ir_unop_d2f:
> + case ir_unop_f2d:
> + case ir_unop_d2i:
> + case ir_unop_i2d:
> + case ir_unop_d2u:
> + case ir_unop_u2d:
> + case ir_unop_d2b:
> + unreachable("no fp64 support yet");
> }
>
> ir->remove();
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> index 04e0f9a..7486071 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> @@ -1192,6 +1192,20 @@ fs_visitor::visit(ir_expression *ir)
> case ir_binop_interpolate_at_sample:
>unreachable("already handled above");
>break;
> +
> + case ir_unop_d2f:
> + case ir_unop_f2d:
> + case ir_unop_d2i:
> + case ir_unop_i2d:
> + case ir_unop_d2u:
> + case ir_unop_u2d:
> + case ir_unop_d2b:
> + case ir_unop_pack_double_2x32:
> + case ir_unop_unpack_double_2x32:
> + case ir_unop_frexp_sig:
> + case ir_unop_frexp_exp:
> + unreachable("fp64 todo");
> + break;
> }
> }
>
> diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
> b/src/mesa/drivers/dri/i965/brw_shader.cpp
> index 71146c5..b0e9c82 100644
> --- a/src/mesa/drivers/dri/i965/brw_shader.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
> @@ -308,6 +308,7 @@ brw_type_for_base_type(const struct glsl_type *type)
> case GLSL_TYPE_VOID:
> case GLSL_TYPE_ERROR:
> case GLSL_TYPE_INTERFACE:
> + case GLSL_TYPE_DOUBLE:
>unreachable("not reached");
> }
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> index 562fc30..6154e43 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> @@ -612,6 +612,7 @@ type_size(const struct glsl_type *type)
>return 0;
> case GLSL_TYPE_IMAGE:
> case GLSL_TYPE_VOID:
> + case GLSL_TYPE_DOUBLE:
> case GLSL_TYPE_ERROR:
> case GLSL_TYPE_INTERFACE:
>unreachable("not reached");
> @@ -1889,6 +1890,18 @@ vec4_visitor::visit(ir_expression *ir)
>unreachable("not reached: should not occur in vertex shader");
> case ir_binop_ldexp:
>unreachable("not reached: should be handled by ldexp_to_arith()");
> + case ir_unop_d2f:
> + case ir_unop_f2d:
> + case ir_unop_d2i:
> + case ir_unop_i2d:
> + case ir_unop_d2u:
> + case ir_unop_u2d:
> + case ir_unop_d2b:
> + case ir_unop_pack_double_2x32:
> + case ir_unop_unpack_double_2x32:
> + case ir_unop_frexp_sig:
> + case ir_unop_frexp_exp:
> + unreachable("fp64 todo");
> }
> }
>
> --
> 1.9.3
>
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Re: [Mesa-dev] [PATCH] i965: just avoid warnings with fp64
Yes, please.
Reviewed-by: Ian Romanick
On 02/19/2015 03:38 PM, Dave Airlie wrote:
> This just fills in some blanks to avoid warnings in the i965 driver.
>
> Signed-off-by: Dave Airlie
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 1 +
> src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp | 13 +
> src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 14 ++
> src/mesa/drivers/dri/i965/brw_shader.cpp | 1 +
> src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 13 +
> 5 files changed, 42 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
> b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index a562b8a..a2a5234 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -673,6 +673,7 @@ fs_visitor::type_size(const struct glsl_type *type)
> case GLSL_TYPE_VOID:
> case GLSL_TYPE_ERROR:
> case GLSL_TYPE_INTERFACE:
> + case GLSL_TYPE_DOUBLE:
>unreachable("not reached");
> }
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
> index cb0a079..c64742c 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
> @@ -445,6 +445,19 @@
> ir_channel_expressions_visitor::visit_leave(ir_assignment *ir)
> case ir_binop_interpolate_at_offset:
> case ir_binop_interpolate_at_sample:
>unreachable("not reached: expression operates on scalars only");
> +
> + case ir_unop_pack_double_2x32:
> + case ir_unop_unpack_double_2x32:
> + case ir_unop_frexp_sig:
> + case ir_unop_frexp_exp:
> + case ir_unop_d2f:
> + case ir_unop_f2d:
> + case ir_unop_d2i:
> + case ir_unop_i2d:
> + case ir_unop_d2u:
> + case ir_unop_u2d:
> + case ir_unop_d2b:
> + unreachable("no fp64 support yet");
> }
>
> ir->remove();
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> index 04e0f9a..7486071 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> @@ -1192,6 +1192,20 @@ fs_visitor::visit(ir_expression *ir)
> case ir_binop_interpolate_at_sample:
>unreachable("already handled above");
>break;
> +
> + case ir_unop_d2f:
> + case ir_unop_f2d:
> + case ir_unop_d2i:
> + case ir_unop_i2d:
> + case ir_unop_d2u:
> + case ir_unop_u2d:
> + case ir_unop_d2b:
> + case ir_unop_pack_double_2x32:
> + case ir_unop_unpack_double_2x32:
> + case ir_unop_frexp_sig:
> + case ir_unop_frexp_exp:
> + unreachable("fp64 todo");
> + break;
> }
> }
>
> diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
> b/src/mesa/drivers/dri/i965/brw_shader.cpp
> index 71146c5..b0e9c82 100644
> --- a/src/mesa/drivers/dri/i965/brw_shader.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
> @@ -308,6 +308,7 @@ brw_type_for_base_type(const struct glsl_type *type)
> case GLSL_TYPE_VOID:
> case GLSL_TYPE_ERROR:
> case GLSL_TYPE_INTERFACE:
> + case GLSL_TYPE_DOUBLE:
>unreachable("not reached");
> }
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> index 562fc30..6154e43 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> @@ -612,6 +612,7 @@ type_size(const struct glsl_type *type)
>return 0;
> case GLSL_TYPE_IMAGE:
> case GLSL_TYPE_VOID:
> + case GLSL_TYPE_DOUBLE:
> case GLSL_TYPE_ERROR:
> case GLSL_TYPE_INTERFACE:
>unreachable("not reached");
> @@ -1889,6 +1890,18 @@ vec4_visitor::visit(ir_expression *ir)
>unreachable("not reached: should not occur in vertex shader");
> case ir_binop_ldexp:
>unreachable("not reached: should be handled by ldexp_to_arith()");
> + case ir_unop_d2f:
> + case ir_unop_f2d:
> + case ir_unop_d2i:
> + case ir_unop_i2d:
> + case ir_unop_d2u:
> + case ir_unop_u2d:
> + case ir_unop_d2b:
> + case ir_unop_pack_double_2x32:
> + case ir_unop_unpack_double_2x32:
> + case ir_unop_frexp_sig:
> + case ir_unop_frexp_exp:
> + unreachable("fp64 todo");
> }
> }
>
>
___
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mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 4/6] st/mesa: add support for new double opcodes
Not having SQRT is assumed to tacitly mean that RSQ is available. Signed-off-by: Ilia Mirkin --- src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index f57e76b..63b779d 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -849,7 +849,7 @@ glsl_to_tgsi_visitor::get_opcode(ir_instruction *ir, unsigned op, case2iu(ISHR, USHR); - case2fi(SSG, ISSG); + case3fid(SSG, ISSG, DSSG); case3fid(ABS, IABS, DABS); case2iu(IBFE, UBFE); @@ -862,6 +862,10 @@ glsl_to_tgsi_visitor::get_opcode(ir_instruction *ir, unsigned op, case3fid(RSQ, RSQ, DRSQ); case3fid(FRC, FRC, DFRAC); + case3fid(TRUNC, TRUNC, DTRUNC); + case3fid(CEIL, CEIL, DCEIL); + case3fid(FLR, FLR, DFLR); + case3fid(ROUND, ROUND, DROUND); default: break; } -- 2.0.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/6] gallium: add shader cap for dldexp/dfracexp support
Signed-off-by: Ilia Mirkin --- src/gallium/auxiliary/gallivm/lp_bld_limits.h | 1 + src/gallium/auxiliary/tgsi/tgsi_exec.h | 1 + src/gallium/docs/source/screen.rst | 2 ++ src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 ++ src/gallium/drivers/r600/r600_pipe.c | 1 + src/gallium/drivers/radeonsi/si_pipe.c | 1 + src/gallium/drivers/svga/svga_screen.c | 1 + src/gallium/include/pipe/p_defines.h | 1 + 8 files changed, 10 insertions(+) diff --git a/src/gallium/auxiliary/gallivm/lp_bld_limits.h b/src/gallium/auxiliary/gallivm/lp_bld_limits.h index 1af7205..2962360 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_limits.h +++ b/src/gallium/auxiliary/gallivm/lp_bld_limits.h @@ -128,6 +128,7 @@ gallivm_get_shader_param(enum pipe_shader_cap param) return 1; case PIPE_SHADER_CAP_DOUBLES: case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: return 0; } /* if we get here, we missed a shader cap above (and should have seen diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h b/src/gallium/auxiliary/tgsi/tgsi_exec.h index 02ee4c7..609c81b 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_exec.h +++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h @@ -456,6 +456,7 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param) case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: return 1; case PIPE_SHADER_CAP_DOUBLES: + case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: return 1; case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: return 0; diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst index 0cb5425..e0fd1a2 100644 --- a/src/gallium/docs/source/screen.rst +++ b/src/gallium/docs/source/screen.rst @@ -334,6 +334,8 @@ to be 0. operations are supported. * ``PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED``: Whether double precision rounding is supported. If it is, DTRUNC/DCEIL/DFLR/DROUND opcodes may be used. +* ``PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED``: Whether DFRACEXP and + DLDEXP are supported. .. _pipe_compute_cap: diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index 868491c..8546ac8 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -294,6 +294,8 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, return 0; case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: return 0; + case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: + return 0; case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: return 16; /* would be 32 in linked (OpenGL-style) mode */ case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index 447513b..06dca25 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -490,6 +490,7 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e case PIPE_SHADER_CAP_DOUBLES: return 0; case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: return 0; } return 0; diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 4c72045..f8fd3fa 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -424,6 +424,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu return PIPE_SHADER_IR_TGSI; case PIPE_SHADER_CAP_DOUBLES: case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: return 0; } return 0; diff --git a/src/gallium/drivers/svga/svga_screen.c b/src/gallium/drivers/svga/svga_screen.c index a951792..2f2ee2a 100644 --- a/src/gallium/drivers/svga/svga_screen.c +++ b/src/gallium/drivers/svga/svga_screen.c @@ -374,6 +374,7 @@ static int svga_get_shader_param(struct pipe_screen *screen, unsigned shader, en return PIPE_SHADER_IR_TGSI; case PIPE_SHADER_CAP_DOUBLES: case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED return 0; } /* If we get here, we failed to handle a cap above */ diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h index 685e37c..ae173b3 100644 --- a/src/gallium/include/pipe/p_defines.h +++ b/src/gallium/include/pipe/p_defines.h @@ -637,6 +637,7 @@ enum pipe_shader_cap PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS, PIPE_SHADER_CAP_DOUBLES, PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED, /* all rounding modes */ + PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED, }; /** -- 2.0.5 ___ mesa-dev mai
[Mesa-dev] [PATCH 6/6] st/mesa: lower DFRACEXP/DLDEXP when they are not supported
Signed-off-by: Ilia Mirkin --- src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 4 1 file changed, 4 insertions(+) diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index e170217..4d91ca6 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -5775,6 +5775,9 @@ st_link_shader(struct gl_context *ctx, struct gl_shader_program *prog) bool have_dround = pscreen->get_shader_param( pscreen, ptarget, PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED); + bool have_dfrexp = pscreen->get_shader_param( +pscreen, ptarget, +PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED); /* If there are forms of indirect addressing that the driver * cannot handle, perform the lowering pass. @@ -5812,6 +5815,7 @@ st_link_shader(struct gl_context *ctx, struct gl_shader_program *prog) EXP_TO_EXP2 | LOG_TO_LOG2 | LDEXP_TO_ARITH | + (have_dfrexp ? 0 : DFREXP_DLDEXP_TO_ARITH) | CARRY_TO_ARITH | BORROW_TO_ARITH | (have_dround ? 0 : DOPS_TO_DFRAC) | -- 2.0.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 5/6] st/mesa: disable lowering of dops to dfrac when dround is available
Signed-off-by: Ilia Mirkin --- src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index 63b779d..e170217 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -1643,7 +1643,6 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir) emit(ir, TGSI_OPCODE_ABS, result_dst, op[0]); break; case ir_unop_sign: - assert(ir->operands[0]->type->base_type != GLSL_TYPE_DOUBLE); emit(ir, TGSI_OPCODE_SSG, result_dst, op[0]); break; case ir_unop_rcp: @@ -2119,19 +2118,15 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir) emit(ir, TGSI_OPCODE_SNE, result_dst, op[0], st_src_reg_for_float(0.0)); break; case ir_unop_trunc: - assert(ir->operands[0]->type->base_type != GLSL_TYPE_DOUBLE); emit(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]); break; case ir_unop_ceil: - assert(ir->operands[0]->type->base_type != GLSL_TYPE_DOUBLE); emit(ir, TGSI_OPCODE_CEIL, result_dst, op[0]); break; case ir_unop_floor: - assert(ir->operands[0]->type->base_type != GLSL_TYPE_DOUBLE); emit(ir, TGSI_OPCODE_FLR, result_dst, op[0]); break; case ir_unop_round_even: - assert(ir->operands[0]->type->base_type != GLSL_TYPE_DOUBLE); emit(ir, TGSI_OPCODE_ROUND, result_dst, op[0]); break; case ir_unop_fract: @@ -5773,8 +5768,13 @@ st_link_shader(struct gl_context *ctx, struct gl_shader_program *prog) bool progress; exec_list *ir = prog->_LinkedShaders[i]->ir; + gl_shader_stage stage = _mesa_shader_enum_to_shader_stage(prog->_LinkedShaders[i]->Type); const struct gl_shader_compiler_options *options = - &ctx->Const.ShaderCompilerOptions[_mesa_shader_enum_to_shader_stage(prog->_LinkedShaders[i]->Type)]; +&ctx->Const.ShaderCompilerOptions[stage]; + unsigned ptarget = shader_stage_to_ptarget(stage); + bool have_dround = pscreen->get_shader_param( +pscreen, ptarget, +PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED); /* If there are forms of indirect addressing that the driver * cannot handle, perform the lowering pass. @@ -5814,7 +5814,7 @@ st_link_shader(struct gl_context *ctx, struct gl_shader_program *prog) LDEXP_TO_ARITH | CARRY_TO_ARITH | BORROW_TO_ARITH | - DOPS_TO_DFRAC | + (have_dround ? 0 : DOPS_TO_DFRAC) | (options->EmitNoPow ? POW_TO_EXP2 : 0) | (!ctx->Const.NativeIntegers ? INT_DIV_TO_MUL_RCP : 0) | (options->EmitNoSat ? SAT_TO_CLAMP : 0)); -- 2.0.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/6] gallium: add a cap to enable double rounding opcodes
Signed-off-by: Ilia Mirkin --- src/gallium/auxiliary/gallivm/lp_bld_limits.h | 1 + src/gallium/auxiliary/tgsi/tgsi_exec.h | 2 ++ src/gallium/docs/source/screen.rst | 2 ++ src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 4 src/gallium/drivers/r600/r600_pipe.c | 2 ++ src/gallium/drivers/radeonsi/si_pipe.c | 1 + src/gallium/drivers/svga/svga_screen.c | 1 + src/gallium/include/pipe/p_defines.h | 3 ++- 8 files changed, 15 insertions(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/gallivm/lp_bld_limits.h b/src/gallium/auxiliary/gallivm/lp_bld_limits.h index 8c66f9d..1af7205 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_limits.h +++ b/src/gallium/auxiliary/gallivm/lp_bld_limits.h @@ -127,6 +127,7 @@ gallivm_get_shader_param(enum pipe_shader_cap param) case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: return 1; case PIPE_SHADER_CAP_DOUBLES: + case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: return 0; } /* if we get here, we missed a shader cap above (and should have seen diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h b/src/gallium/auxiliary/tgsi/tgsi_exec.h index 256cf72..02ee4c7 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_exec.h +++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h @@ -457,6 +457,8 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param) return 1; case PIPE_SHADER_CAP_DOUBLES: return 1; + case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + return 0; } /* if we get here, we missed a shader cap above (and should have seen * a compiler warning.) diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst index 373a2fe..0cb5425 100644 --- a/src/gallium/docs/source/screen.rst +++ b/src/gallium/docs/source/screen.rst @@ -332,6 +332,8 @@ to be 0. sampler views. Must not be lower than PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS. * ``PIPE_SHADER_CAP_DOUBLES``: Whether double precision floating-point operations are supported. +* ``PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED``: Whether double precision rounding + is supported. If it is, DTRUNC/DCEIL/DFLR/DROUND opcodes may be used. .. _pipe_compute_cap: diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index edea845..868491c 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -290,6 +290,10 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, return 1; case PIPE_SHADER_CAP_INTEGERS: return 1; + case PIPE_SHADER_CAP_DOUBLES: + return 0; + case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + return 0; case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: return 16; /* would be 32 in linked (OpenGL-style) mode */ case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index a4b7b66..447513b 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -489,6 +489,8 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e } case PIPE_SHADER_CAP_DOUBLES: return 0; + case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + return 0; } return 0; } diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index ec53331..4c72045 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -423,6 +423,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu case PIPE_SHADER_CAP_PREFERRED_IR: return PIPE_SHADER_IR_TGSI; case PIPE_SHADER_CAP_DOUBLES: + case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: return 0; } return 0; diff --git a/src/gallium/drivers/svga/svga_screen.c b/src/gallium/drivers/svga/svga_screen.c index e468a2f..a951792 100644 --- a/src/gallium/drivers/svga/svga_screen.c +++ b/src/gallium/drivers/svga/svga_screen.c @@ -373,6 +373,7 @@ static int svga_get_shader_param(struct pipe_screen *screen, unsigned shader, en case PIPE_SHADER_CAP_PREFERRED_IR: return PIPE_SHADER_IR_TGSI; case PIPE_SHADER_CAP_DOUBLES: + case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: return 0; } /* If we get here, we failed to handle a cap above */ diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h index 1785043..685e37c 100644 --- a/src/gallium/include/pipe/p_defines.h +++ b/src/gallium/include/pipe/p_defines.h @@ -635,7 +635,8 @@ enum pipe_shader_cap PIPE_SHADER_CAP_PREFERRED_IR, PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED, PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS, - PIPE_SHADER_CAP_DOUBLES + PIPE_SHADER_CAP_DOUBLES, + PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED, /* all rounding modes */ }; /**
[Mesa-dev] [PATCH 1/6] gallium: add some more double opcodes to avoid unnecessary lowering
Signed-off-by: Ilia Mirkin
---
src/gallium/auxiliary/tgsi/tgsi_info.c | 5
src/gallium/docs/source/tgsi.rst | 39 ++
src/gallium/include/pipe/p_shader_tokens.h | 7 +-
3 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c
b/src/gallium/auxiliary/tgsi/tgsi_info.c
index d04f9da..4d838fd 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
@@ -257,6 +257,11 @@ static const struct tgsi_opcode_info
opcode_info[TGSI_OPCODE_LAST] =
{ 1, 1, 0, 0, 0, 0, COMP, "D2U", TGSI_OPCODE_D2U },
{ 1, 1, 0, 0, 0, 0, COMP, "U2D", TGSI_OPCODE_U2D },
{ 1, 1, 0, 0 ,0, 0, COMP, "DRSQ", TGSI_OPCODE_DRSQ },
+ { 1, 1, 0, 0, 0, 0, COMP, "DTRUNC", TGSI_OPCODE_DTRUNC },
+ { 1, 1, 0, 0, 0, 0, COMP, "DCEIL", TGSI_OPCODE_DCEIL },
+ { 1, 1, 0, 0, 0, 0, COMP, "DFLR", TGSI_OPCODE_DFLR },
+ { 1, 1, 0, 0, 0, 0, COMP, "DROUND", TGSI_OPCODE_DROUND },
+ { 1, 1, 0, 0, 0, 0, COMP, "DSSG", TGSI_OPCODE_DSSG },
};
const struct tgsi_opcode_info *
diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst
index e20af79..15f1e9f 100644
--- a/src/gallium/docs/source/tgsi.rst
+++ b/src/gallium/docs/source/tgsi.rst
@@ -1861,6 +1861,45 @@ two-component vectors with doubled precision in each
component.
dst.zw = src.zw - \lfloor src.zw\rfloor
+.. opcode:: DTRUNC - Truncate
+
+.. math::
+
+ dst.xy = trunc(src.xy)
+
+ dst.zw = trunc(src.zw)
+
+.. opcode:: DCEIL - Ceiling
+
+.. math::
+
+ dst.xy = \lceil src.xy\rceil
+
+ dst.zw = \lceil src.zw\rceil
+
+.. opcode:: DFLR - Floor
+
+.. math::
+
+ dst.xy = \lfloor src.xy\rfloor
+
+ dst.zw = \lfloor src.zw\rfloor
+
+.. opcode:: DROUND - Fraction
+
+.. math::
+
+ dst.xy = round(src.xy)
+
+ dst.zw = round(src.zw)
+
+.. opcode:: DSSG - Set Sign
+
+.. math::
+
+ dst.xy = (src.xy > 0) ? 1 : (src.xy < 0) ? -1 : 0
+
+ dst.zw = (src.zw > 0) ? 1 : (src.zw < 0) ? -1 : 0
.. opcode:: DFRACEXP - Convert Number to Fractional and Integral Components
diff --git a/src/gallium/include/pipe/p_shader_tokens.h
b/src/gallium/include/pipe/p_shader_tokens.h
index fc41cc9..95ac590 100644
--- a/src/gallium/include/pipe/p_shader_tokens.h
+++ b/src/gallium/include/pipe/p_shader_tokens.h
@@ -519,7 +519,12 @@ struct tgsi_property_data {
#define TGSI_OPCODE_D2U 215
#define TGSI_OPCODE_U2D 216
#define TGSI_OPCODE_DRSQ217 /* eg, cayman also has DRSQ */
-#define TGSI_OPCODE_LAST218
+#define TGSI_OPCODE_DTRUNC 218 /* nvc0 */
+#define TGSI_OPCODE_DCEIL 219 /* nvc0 */
+#define TGSI_OPCODE_DFLR220 /* nvc0 */
+#define TGSI_OPCODE_DROUND 221 /* nvc0 */
+#define TGSI_OPCODE_DSSG222
+#define TGSI_OPCODE_LAST223
#define TGSI_SAT_NONE0 /* do not saturate */
#define TGSI_SAT_ZERO_ONE1 /* clamp to [0,1] */
--
2.0.5
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[Mesa-dev] [PATCH 0/6] add nvc0 fp64 prereqs to gallium + st/mesa
With these features, nvc0 can implement fp64 fairly easily (will send patches after these are in). The st/mesa changes depend on the fp64 enablement page Dave just sent out. Ilia Mirkin (6): gallium: add some more double opcodes to avoid unnecessary lowering gallium: add a cap to enable double rounding opcodes gallium: add shader cap for dldexp/dfracexp support st/mesa: add support for new double opcodes st/mesa: disable lowering of dops to dfrac when dround is available st/mesa: lower DFRACEXP/DLDEXP when they are not supported src/gallium/auxiliary/gallivm/lp_bld_limits.h | 2 ++ src/gallium/auxiliary/tgsi/tgsi_exec.h | 3 ++ src/gallium/auxiliary/tgsi/tgsi_info.c | 5 src/gallium/docs/source/screen.rst | 4 +++ src/gallium/docs/source/tgsi.rst | 39 ++ src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 6 src/gallium/drivers/r600/r600_pipe.c | 3 ++ src/gallium/drivers/radeonsi/si_pipe.c | 2 ++ src/gallium/drivers/svga/svga_screen.c | 2 ++ src/gallium/include/pipe/p_defines.h | 4 ++- src/gallium/include/pipe/p_shader_tokens.h | 7 - src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 24 ++-- 12 files changed, 91 insertions(+), 10 deletions(-) -- 2.0.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 89199] u_math.h:591:4: error: implicit declaration of function 'ffsll'
https://bugs.freedesktop.org/show_bug.cgi?id=89199 --- Comment #4 from Vinson Lee --- $ gcc --version gcc (NetBSD nb2 20110806) 4.5.3 Copyright (C) 2010 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. attachment 113670 fixes the NetBSD build. Tested-by: Vinson Lee -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 07/23] main: Add entry point for NamedBufferData.
On Wed, Feb 18, 2015 at 7:40 AM, Martin Peres
wrote:
>
> On 12/02/15 04:05, Laura Ekstrand wrote:
>
>> v2: review from Ian Romanick
>> - Fix space in ARB_direct_state_access.xml.
>> - Remove "_mesa" from the name of buffer_data static fallback.
>> - Restore VBO_DEBUG and BOUNDS_CHECK.
>> - Fix beginning of comment to start on same line as /*
>> ---
>> src/mapi/glapi/gen/ARB_direct_state_access.xml | 7 +++
>> src/mesa/main/bufferobj.c | 67
>> ++
>> src/mesa/main/bufferobj.h | 13 -
>> src/mesa/main/tests/dispatch_sanity.cpp| 1 +
>> 4 files changed, 67 insertions(+), 21 deletions(-)
>>
>> diff --git a/src/mapi/glapi/gen/ARB_direct_state_access.xml
>> b/src/mapi/glapi/gen/ARB_direct_state_access.xml
>> index ff81c21..7779262 100644
>> --- a/src/mapi/glapi/gen/ARB_direct_state_access.xml
>> +++ b/src/mapi/glapi/gen/ARB_direct_state_access.xml
>> @@ -21,6 +21,13 @@
>>
>>
>> +
>> +
>> +
>> +
>> +
>> +
>> +
>>
>>
>> diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
>> index 6259db1..ac8eed1 100644
>> --- a/src/mesa/main/bufferobj.c
>> +++ b/src/mesa/main/bufferobj.c
>> @@ -556,9 +556,9 @@ _mesa_total_buffer_object_memory(struct gl_context
>> *ctx)
>>* \sa glBufferDataARB, dd_function_table::BufferData.
>>*/
>> static GLboolean
>> -_mesa_buffer_data( struct gl_context *ctx, GLenum target, GLsizeiptrARB
>> size,
>> - const GLvoid * data, GLenum usage, GLenum storageFlags,
>> - struct gl_buffer_object * bufObj )
>> +buffer_data_fallback(struct gl_context *ctx, GLenum target, GLsizeiptr
>> size,
>> + const GLvoid *data, GLenum usage, GLenum
>> storageFlags,
>> + struct gl_buffer_object *bufObj)
>> {
>> void * new_data;
>> @@ -1112,7 +1112,7 @@ _mesa_init_buffer_object_functions(struct
>> dd_function_table *driver)
>> /* GL_ARB_vertex/pixel_buffer_object */
>> driver->NewBufferObject = _mesa_new_buffer_object;
>> driver->DeleteBuffer = _mesa_delete_buffer_object;
>> - driver->BufferData = _mesa_buffer_data;
>> + driver->BufferData = buffer_data_fallback;
>> driver->BufferSubData = _mesa_buffer_subdata;
>> driver->GetBufferSubData = _mesa_buffer_get_subdata;
>> driver->UnmapBuffer = _mesa_buffer_unmap;
>> @@ -1474,23 +1474,22 @@ _mesa_NamedBufferStorage(GLuint buffer,
>> GLsizeiptr size, const GLvoid *data,
>> }
>> -
>> -void GLAPIENTRY
>> -_mesa_BufferData(GLenum target, GLsizeiptrARB size,
>> -const GLvoid * data, GLenum usage)
>> +void
>> +_mesa_buffer_data(struct gl_context *ctx, struct gl_buffer_object
>> *bufObj,
>> + GLenum target, GLsizeiptr size, const GLvoid *data,
>> + GLenum usage, const char *func)
>> {
>> - GET_CURRENT_CONTEXT(ctx);
>> - struct gl_buffer_object *bufObj;
>> bool valid_usage;
>>if (MESA_VERBOSE & VERBOSE_API)
>> - _mesa_debug(ctx, "glBufferData(%s, %ld, %p, %s)\n",
>> + _mesa_debug(ctx, "%s(%s, %ld, %p, %s)\n",
>>
>
> Func could be on this line but I really don't care.
>
>
> + func,
>> _mesa_lookup_enum_by_nr(target),
>> (long int) size, data,
>> _mesa_lookup_enum_by_nr(usage));
>>if (size < 0) {
>> - _mesa_error(ctx, GL_INVALID_VALUE, "glBufferDataARB(size < 0)");
>> + _mesa_error(ctx, GL_INVALID_VALUE, "%s(size < 0)", func);
>> return;
>> }
>> @@ -1519,16 +1518,13 @@ _mesa_BufferData(GLenum target, GLsizeiptrARB
>> size,
>> }
>>if (!valid_usage) {
>> - _mesa_error(ctx, GL_INVALID_ENUM, "glBufferData(usage)");
>> + _mesa_error(ctx, GL_INVALID_ENUM, "%s(invalid usage: %s)", func,
>> + _mesa_lookup_enum_by_nr(usage));
>> return;
>> }
>> - bufObj = get_buffer(ctx, "glBufferDataARB", target,
>> GL_INVALID_OPERATION);
>> - if (!bufObj)
>> - return;
>> -
>> if (bufObj->Immutable) {
>> - _mesa_error(ctx, GL_INVALID_OPERATION, "glBufferData(immutable)");
>> + _mesa_error(ctx, GL_INVALID_OPERATION, "%s(immutable)", func);
>> return;
>> }
>> @@ -1554,10 +1550,43 @@ _mesa_BufferData(GLenum target, GLsizeiptrARB
>> size,
>> GL_MAP_WRITE_BIT |
>> GL_DYNAMIC_STORAGE_BIT,
>> bufObj)) {
>> - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glBufferDataARB()");
>> + _mesa_error(ctx, GL_OUT_OF_MEMORY, "%s", func);
>> }
>> }
>> +void GLAPIENTRY
>> +_mesa_BufferData(GLenum target, GLsizeiptr size,
>> + const GLvoid *data, GLenum usage)
>> +{
>> + GET_CURRENT_CONTEXT(ctx);
>> + struct gl_buffer_object *bufObj;
>> +
>> + bufObj = get_buffer(ctx, "glBufferData", target,
>> GL_INVALID_OPERATION
Re: [Mesa-dev] [PATCH 06/23] main: Add entry point for NamedBufferStorage.
This is NamedBufferStorage, not NamedBufferData. The storage function uses
a bitfield instead of an enum.
On Wed, Feb 18, 2015 at 7:04 AM, Martin Peres
wrote:
> On 12/02/15 04:05, Laura Ekstrand wrote:
>
>> ---
>> src/mapi/glapi/gen/ARB_direct_state_access.xml | 7 +++
>> src/mesa/main/bufferobj.c | 63
>> +++---
>> src/mesa/main/bufferobj.h | 9
>> src/mesa/main/tests/dispatch_sanity.cpp| 1 +
>> 4 files changed, 64 insertions(+), 16 deletions(-)
>>
>> diff --git a/src/mapi/glapi/gen/ARB_direct_state_access.xml
>> b/src/mapi/glapi/gen/ARB_direct_state_access.xml
>> index 6c9d0e8..ff81c21 100644
>> --- a/src/mapi/glapi/gen/ARB_direct_state_access.xml
>> +++ b/src/mapi/glapi/gen/ARB_direct_state_access.xml
>> @@ -14,6 +14,13 @@
>>
>>
>> +
>> +
>> +
>> +
>> +
>>
> Isn't this supposed to be an enum? Here is the prototype found in core 4.5:
> void NamedBufferData( uint buffer, sizeiptr size, const void *data, enum
> usage );
>
> Other than that, this looks good to me.
>
> Reviewed-by: Martin Peres
>
>
> +
>> +
>>
>>
>> diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
>> index 785f0ff..6259db1 100644
>> --- a/src/mesa/main/bufferobj.c
>> +++ b/src/mesa/main/bufferobj.c
>> @@ -1386,15 +1386,13 @@ _mesa_IsBuffer(GLuint id)
>> }
>> -void GLAPIENTRY
>> -_mesa_BufferStorage(GLenum target, GLsizeiptr size, const GLvoid *data,
>> -GLbitfield flags)
>> +void
>> +_mesa_buffer_storage(struct gl_context *ctx, struct gl_buffer_object
>> *bufObj,
>> + GLenum target, GLsizeiptr size, const GLvoid *data,
>> + GLbitfield flags, const char *func)
>> {
>> - GET_CURRENT_CONTEXT(ctx);
>> - struct gl_buffer_object *bufObj;
>> -
>> if (size <= 0) {
>> - _mesa_error(ctx, GL_INVALID_VALUE, "glBufferStorage(size <= 0)");
>> + _mesa_error(ctx, GL_INVALID_VALUE, "%s(size <= 0)", func);
>> return;
>> }
>> @@ -1404,27 +1402,25 @@ _mesa_BufferStorage(GLenum target, GLsizeiptr
>> size, const GLvoid *data,
>>GL_MAP_COHERENT_BIT |
>>GL_DYNAMIC_STORAGE_BIT |
>>GL_CLIENT_STORAGE_BIT)) {
>> - _mesa_error(ctx, GL_INVALID_VALUE, "glBufferStorage(flags)");
>> + _mesa_error(ctx, GL_INVALID_VALUE, "%s(invalid flag bits set)",
>> func);
>> return;
>> }
>>if (flags & GL_MAP_PERSISTENT_BIT &&
>> !(flags & (GL_MAP_READ_BIT | GL_MAP_WRITE_BIT))) {
>> - _mesa_error(ctx, GL_INVALID_VALUE, "glBufferStorage(flags!=READ/
>> WRITE)");
>> + _mesa_error(ctx, GL_INVALID_VALUE,
>> + "%s(PERSISTENT and flags!=READ/WRITE)", func);
>> return;
>> }
>>if (flags & GL_MAP_COHERENT_BIT && !(flags &
>> GL_MAP_PERSISTENT_BIT)) {
>> - _mesa_error(ctx, GL_INVALID_VALUE, "glBufferStorage(flags!=
>> PERSISTENT)");
>> + _mesa_error(ctx, GL_INVALID_VALUE,
>> + "%s(COHERENT and flags!=PERSISTENT)", func);
>> return;
>> }
>> - bufObj = get_buffer(ctx, "glBufferStorage", target,
>> GL_INVALID_OPERATION);
>> - if (!bufObj)
>> - return;
>> -
>> if (bufObj->Immutable) {
>> - _mesa_error(ctx, GL_INVALID_OPERATION,
>> "glBufferStorage(immutable)");
>> + _mesa_error(ctx, GL_INVALID_OPERATION, "%s(immutable)", func);
>> return;
>> }
>> @@ -1439,10 +1435,45 @@ _mesa_BufferStorage(GLenum target, GLsizeiptr
>> size, const GLvoid *data,
>> ASSERT(ctx->Driver.BufferData);
>> if (!ctx->Driver.BufferData(ctx, target, size, data, GL_DYNAMIC_DRAW,
>> flags, bufObj)) {
>> - _mesa_error(ctx, GL_OUT_OF_MEMORY, "glBufferStorage()");
>> + _mesa_error(ctx, GL_OUT_OF_MEMORY, "%s()", func);
>> }
>> }
>> +void GLAPIENTRY
>> +_mesa_BufferStorage(GLenum target, GLsizeiptr size, const GLvoid *data,
>> +GLbitfield flags)
>> +{
>> + GET_CURRENT_CONTEXT(ctx);
>> + struct gl_buffer_object *bufObj;
>> +
>> + bufObj = get_buffer(ctx, "glBufferStorage", target,
>> GL_INVALID_OPERATION);
>> + if (!bufObj)
>> + return;
>> +
>> + _mesa_buffer_storage(ctx, bufObj, target, size, data, flags,
>> +"glBufferStorage");
>> +}
>> +
>> +void GLAPIENTRY
>> +_mesa_NamedBufferStorage(GLuint buffer, GLsizeiptr size, const GLvoid
>> *data,
>> + GLbitfield flags)
>> +{
>> + GET_CURRENT_CONTEXT(ctx);
>> + struct gl_buffer_object *bufObj;
>> +
>> + bufObj = _mesa_lookup_bufferobj_err(ctx, buffer,
>> "glNamedBufferStorage");
>> + if (!bufObj)
>> + return;
>> +
>> + /*
>> +* In direct state access, buffer objects have an unspecified target
>> since
>> +* they are not required to be bound.
>> +*/
>> + _mesa_buffer_storage(ctx, bufObj, GL_NONE, size, data, flags,
>> +
Re: [Mesa-dev] [PATCH 0/6] add nvc0 fp64 prereqs to gallium + st/mesa
On 20 February 2015 at 09:52, Ilia Mirkin wrote: > With these features, nvc0 can implement fp64 fairly easily (will send > patches after these are in). The st/mesa changes depend on the fp64 > enablement page Dave just sent out. Apart from the style nitpick and the using 0.0 in the docs I mentioned on irc This series is Reviewed-by: Dave Airlie ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 10/32] i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().
I'm still a little pensive. But Reviewed-by: Jason Ekstrand Now for a little aside. I have come to the conclusion that I made a grave mistake when I did the LOAD_PAYLOAD stuff. In retrospect, I should have just subclassed fs_inst for load_payload. The problem is that we need to snag a bunch of information for the sources when we create the load_payload. In particular, we need to know the width of the source so that we know how much space it consumes in the payload and we need to know the information required to properly re-create the mov such as force_sechalf and force_writemask_all. Really, in order to do things properly, we need to gather this information *before* we do any optimizations. The nasty pile of code that you're editing together with the "effective_width" parameter is a lame attempt to capture/reconstruct this information. Really, we should just subclass, capture the information up-front, and do it properly. --Jason On Thu, Feb 19, 2015 at 1:53 PM, Jason Ekstrand wrote: > > > On Thu, Feb 19, 2015 at 1:25 PM, Francisco Jerez > wrote: > >> Jason Ekstrand writes: >> >> > On Thu, Feb 19, 2015 at 12:13 PM, Francisco Jerez < >> curroje...@riseup.net> >> > wrote: >> > >> >> Jason Ekstrand writes: >> >> >> >> > On Fri, Feb 6, 2015 at 4:01 PM, Francisco Jerez < >> curroje...@riseup.net> >> >> > wrote: >> >> > >> >> >> Hey Matt, >> >> >> >> >> >> Matt Turner writes: >> >> >> >> >> >> > On Fri, Feb 6, 2015 at 6:42 AM, Francisco Jerez < >> >> curroje...@riseup.net> >> >> >> wrote: >> >> >> >> MRFs cannot be read from anyway so they cannot possibly be a >> valid >> >> >> >> source of LOAD_PAYLOAD. >> >> >> >> --- >> >> >> > >> >> >> > The function only seems to test inst->dst.file == MRF. I don't >> see any >> >> >> > code for handling MRF sources. What am I missing? >> >> >> >> >> >> That test is for "handling" MRF sources -- More precisely, it's >> >> >> collecting the writemask and half flags for MRF writes, which can >> only >> >> >> possibly be useful if we're going to use them later on to read >> something >> >> >> out of an MRF into a payload, which we shouldn't be doing in the >> first >> >> >> place. >> >> >> >> >> >> Aside from simplifying the function somewhat, that allows us to >> drop the >> >> >> 16 register gap reserved for MRFs at register offset zero, what will >> >> >> allow us to drop the vgrf_to_reg[] offset calculation completely >> (also >> >> >> in split_virtual_grfs()) in a future patch (not sent for review >> yet). >> >> >> >> >> > >> >> > No, we do read from MRF's sort-of... Send messages have an implicit >> >> "read" >> >> > from an MRF. >> >> >> >> Heh, and that's pretty much the only way you "read" from it. >> >> >> >> > This was written precicely so that we could use LOAD_PAYLOAD >> >> > to build MRF payloads. We do on pre-GEN6. >> >> > >> >> I'm aware, but you don't need any of this meta-data to LOAD_PAYLOAD >> >> *into* an MRF, and LOAD_PAYLOAD with an MRF as source should be illegal >> >> anyway. >> >> >> > >> > And no one is using it that way. All of the metadata checks you are >> > deleting are checks on the *destination*. >> > >> >> Didn't you write this code yourself? The only use for the collected >> metadata is initializing the instruction flags of the MOVs subsequent >> LOAD_PAYLOAD instructions are lowered to, based on the metadata already >> collected for its source registers, which can never be MRFs, so the >> metadata you collect from MRF writes is never actually used. >> > > Right... I misred something initially. Yes, we should never be tracking > MRF's as a source of a LOAD_PAYLOAD. I'll give it a better look a bit > later, but it looks better. > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] glapi: Do not use backtrace on FreeBSD.
On Thu, Feb 5, 2015 at 4:02 AM, Ian Romanick wrote: > On 01/24/2015 05:46 AM, Vinson Lee wrote: >> Fix build error. >> >> CCLD libGL.la >> libglapi.a(glapi_libglapi_la-glapi_gentable.o): In function >> `__glapi_gentable_NoOp': >> glapi_gentable.c:76: undefined reference to `backtrace' >> >> Signed-off-by: Vinson Lee >> --- >> src/mapi/glapi/gen/gl_gentable.py | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/src/mapi/glapi/gen/gl_gentable.py >> b/src/mapi/glapi/gen/gl_gentable.py >> index 06a5ebf..fb578e3 100644 >> --- a/src/mapi/glapi/gen/gl_gentable.py >> +++ b/src/mapi/glapi/gen/gl_gentable.py >> @@ -42,7 +42,7 @@ header = """/* GLXEXT is the define used in the xserver >> when the GLX extension i >> #endif >> >> #if (defined(GLXEXT) && defined(HAVE_BACKTRACE)) \\ >> - || (!defined(GLXEXT) && defined(DEBUG) && !defined(__CYGWIN__) && >> !defined(__MINGW32__) && !defined(__OpenBSD__) && !defined(__NetBSD__) && >> !defined(__DragonFly__)) >> + || (!defined(GLXEXT) && defined(DEBUG) && !defined(__CYGWIN__) && >> !defined(__MINGW32__) && !defined(__OpenBSD__) && !defined(__NetBSD__) && >> !defined(__DragonFly__) && !defined(__FreeBSD__)) >> #define USE_BACKTRACE >> #endif > > It seems weird that we need all the BSDs in this check. Is configure > setting HAVE_BACKTRACE mistakenly? Or is this logic just broken? Does > > #if defined(HAVE_BACKTRACE) && (defined(GLXEXT) || defined(DEBUG)) > > work everywhere? > Yes, it works. I tested FreeBSD and MinGW builds. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] tgsi/scan: add uses_doubles to tgsi scanner
From: Dave Airlie
This allows drivers to work out if a shader contains any
double opcodes easily.
Signed-off-by: Dave Airlie
---
src/gallium/auxiliary/tgsi/tgsi_scan.c | 4
src/gallium/auxiliary/tgsi/tgsi_scan.h | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c
b/src/gallium/auxiliary/tgsi/tgsi_scan.c
index e6011d2..e19b8a1 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
@@ -97,6 +97,10 @@ tgsi_scan_shader(const struct tgsi_token *tokens,
assert(fullinst->Instruction.Opcode < TGSI_OPCODE_LAST);
info->opcode_count[fullinst->Instruction.Opcode]++;
+if (fullinst->Instruction.Opcode >= TGSI_OPCODE_F2D ||
+fullinst->Instruction.Opcode < TGSI_OPCODE_DRSQ)
+ info->uses_doubles = true;
+
for (i = 0; i < fullinst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *src =
&fullinst->Src[i];
diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.h
b/src/gallium/auxiliary/tgsi/tgsi_scan.h
index 5dc9267..daa73cc 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.h
@@ -86,7 +86,7 @@ struct tgsi_shader_info
boolean writes_viewport_index;
boolean writes_layer;
boolean is_msaa_sampler[PIPE_MAX_SAMPLERS];
-
+ boolean uses_doubles; /**< uses any of the double instructions */
unsigned clipdist_writemask;
unsigned culldist_writemask;
unsigned num_written_culldistance;
--
1.9.3
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[Mesa-dev] [RFC] cayman fp64 support
This just implements FP64 on cayman but disables the sb compiler for now. Dave. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] r600g: add doubles support for CAYMAN
From: Dave Airlie
Only a subset of AMD GPUs supported by r600g support doubles,
CAYMAN and CYPRESS are probably all we'll try and support, however
I don't have a CYPRESS so ignore that for now.
This disables SB support for doubles, as we think we need to
make the scheduler smarter to introduce delay slots.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_asm.c| 14 ++
src/gallium/drivers/r600/r600_asm.h| 15 ++
src/gallium/drivers/r600/r600_isa.h| 8 +-
src/gallium/drivers/r600/r600_pipe.c | 2 +
src/gallium/drivers/r600/r600_shader.c | 389 -
src/gallium/drivers/r600/r600_shader.h | 2 +
6 files changed, 424 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
index 79e7f74..dc26b63 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -252,6 +252,12 @@ static int alu_uses_rel(struct r600_bytecode *bc, struct
r600_bytecode_alu *alu)
return 0;
}
+static int is_alu_64bit_inst(struct r600_bytecode *bc, struct
r600_bytecode_alu *alu)
+{
+ const struct alu_op_info *op = r600_isa_alu(alu->op);
+ return (op->flags & AF_64);
+}
+
static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct
r600_bytecode_alu *alu)
{
unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
@@ -576,6 +582,12 @@ static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
for (i = 0; i < max_slots; ++i) {
if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) &&
!prev[i]->dst.rel) {
+
+ if (is_alu_64bit_inst(bc, prev[i])) {
+ gpr[i] = -1;
+ continue;
+ }
+
gpr[i] = prev[i]->dst.sel;
/* cube writes more than PV.X */
if (is_alu_reduction_inst(bc, prev[i]))
@@ -591,6 +603,8 @@ static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
if(!alu)
continue;
+ if (is_alu_64bit_inst(bc, alu))
+ continue;
num_src = r600_bytecode_get_num_operands(bc, alu);
for (src = 0; src < num_src; ++src) {
if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
diff --git a/src/gallium/drivers/r600/r600_asm.h
b/src/gallium/drivers/r600/r600_asm.h
index e37d926..7b2734c 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -279,4 +279,19 @@ void eg_bytecode_export_read(struct r600_bytecode *bc,
void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
unsigned *num_format, unsigned *format_comp,
unsigned *endian);
+
+static INLINE int fp64_switch(int i)
+{
+ switch (i) {
+ case 0:
+ return 1;
+ case 1:
+ return 0;
+ case 2:
+ return 3;
+ case 3:
+ return 2;
+ }
+ return 0;
+}
#endif
diff --git a/src/gallium/drivers/r600/r600_isa.h
b/src/gallium/drivers/r600/r600_isa.h
index ec3f702..3cc135e 100644
--- a/src/gallium/drivers/r600/r600_isa.h
+++ b/src/gallium/drivers/r600/r600_isa.h
@@ -339,11 +339,11 @@ static const struct alu_op_info alu_op_table[] = {
{"PRED_SETGT_64", 2, { 0x7C, 0xC7 },{ AF_V,
AF_V, AF_V, AF_V}, AF_PRED | AF_CC_GT | AF_64 },
{"PRED_SETE_64", 2, { 0x7D, 0xC8 },{ AF_V,
AF_V, AF_V, AF_V}, AF_PRED | AF_CC_E | AF_64 },
{"PRED_SETGE_64", 2, { 0x7E, 0xC9 },{ AF_V,
AF_V, AF_V, AF_V}, AF_PRED | AF_CC_GE | AF_64 },
- {"MUL_64",2, { 0x1B, 0xCA },{ AF_V,
AF_V, AF_V, AF_V}, AF_64 },
+ {"MUL_64",2, { 0x1B, 0xCA },{ AF_V,
AF_V, AF_V, AF_4V}, AF_64 },
{"ADD_64",2, { 0x17, 0xCB },{ AF_V,
AF_V, AF_V, AF_V}, AF_64 },
{"MOVA_INT", 1, { 0x18, 0xCC },{ AF_V,
AF_V, AF_V, AF_V}, AF_MOVA },
- {"FLT64_TO_FLT32",1, { 0x1C, 0xCD },{ AF_V,
AF_V, AF_V, AF_V}, 0 },
- {"FLT32_TO_FLT64",1, { 0x1D, 0xCE },{ AF_V,
AF_V, AF_V, AF_V}, 0 },
+ {"FLT64_TO_FLT32",1, { 0x1C, 0xCD },{ AF_V,
AF_V, AF_V, AF_V}, AF_64 },
+ {"FLT32_TO_FLT64",1, { 0x1D, 0xCE },{ AF_V,
AF_V, AF_V, AF_V}, AF_64 },
{"SAD_ACCUM_PREV_UINT", 2, { -1, 0xCF },{ 0,
0, AF_V, AF_V}, AF_UINT_DST | AF_PREV_NEXT },
{"DOT", 2, { -1, 0xD0 },{ 0,
0, AF_V, AF_V}, AF_PREV_NEXT },
{"MUL_PREV", 1, { -1, 0xD1 },{ 0,
0, AF_V, AF_V}, AF_PREV_INTERLEAVE },
@@ -369,7 +3
Re: [Mesa-dev] [PATCH 1/2] tgsi/scan: add uses_doubles to tgsi scanner
On Thu, Feb 19, 2015 at 7:54 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> This allows drivers to work out if a shader contains any
> double opcodes easily.
>
> Signed-off-by: Dave Airlie
> ---
> src/gallium/auxiliary/tgsi/tgsi_scan.c | 4
> src/gallium/auxiliary/tgsi/tgsi_scan.h | 2 +-
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c
> b/src/gallium/auxiliary/tgsi/tgsi_scan.c
> index e6011d2..e19b8a1 100644
> --- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
> +++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
> @@ -97,6 +97,10 @@ tgsi_scan_shader(const struct tgsi_token *tokens,
> assert(fullinst->Instruction.Opcode < TGSI_OPCODE_LAST);
> info->opcode_count[fullinst->Instruction.Opcode]++;
>
> +if (fullinst->Instruction.Opcode >= TGSI_OPCODE_F2D ||
> +fullinst->Instruction.Opcode < TGSI_OPCODE_DRSQ)
I added a few :)
> + info->uses_doubles = true;
> +
> for (i = 0; i < fullinst->Instruction.NumSrcRegs; i++) {
> const struct tgsi_full_src_register *src =
>&fullinst->Src[i];
> diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.h
> b/src/gallium/auxiliary/tgsi/tgsi_scan.h
> index 5dc9267..daa73cc 100644
> --- a/src/gallium/auxiliary/tgsi/tgsi_scan.h
> +++ b/src/gallium/auxiliary/tgsi/tgsi_scan.h
> @@ -86,7 +86,7 @@ struct tgsi_shader_info
> boolean writes_viewport_index;
> boolean writes_layer;
> boolean is_msaa_sampler[PIPE_MAX_SAMPLERS];
> -
> + boolean uses_doubles; /**< uses any of the double instructions */
> unsigned clipdist_writemask;
> unsigned culldist_writemask;
> unsigned num_written_culldistance;
> --
> 1.9.3
>
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> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
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[Mesa-dev] [Bug 89238] "nir/nir.h", line 643: Error: In this declaration "src" is of an incomplete type "nir_alu_src[]".
https://bugs.freedesktop.org/show_bug.cgi?id=89238 Bug ID: 89238 Summary: "nir/nir.h", line 643: Error: In this declaration "src" is of an incomplete type "nir_alu_src[]". Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Solaris Status: NEW Severity: blocker Priority: medium Component: Mesa core Assignee: mesa-dev@lists.freedesktop.org Reporter: v...@freedesktop.org QA Contact: mesa-dev@lists.freedesktop.org mesa: 6316c90cc0daa9e9476b00e3c52c51190e782c3f (master 10.6.0-devel) Oracle Studio build error. "nir/nir.h", line 643: Error: In this declaration "src" is of an incomplete type "nir_alu_src[]" -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 01/11] nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax
Signed-off-by: Ilia Mirkin
---
.../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 66 +-
1 file changed, 63 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index dfb093c..e38a3b8 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -92,11 +92,14 @@ private:
void emitUADD(const Instruction *);
void emitFADD(const Instruction *);
+ void emitDADD(const Instruction *);
void emitUMUL(const Instruction *);
void emitFMUL(const Instruction *);
+ void emitDMUL(const Instruction *);
void emitIMAD(const Instruction *);
void emitISAD(const Instruction *);
void emitFMAD(const Instruction *);
+ void emitDMAD(const Instruction *);
void emitMADSP(const Instruction *);
void emitNOT(Instruction *);
@@ -523,6 +526,25 @@ CodeEmitterNVC0::emitFMAD(const Instruction *i)
}
void
+CodeEmitterNVC0::emitDMAD(const Instruction *i)
+{
+ bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
+
+ emitForm_A(i, HEX64(2000, 0001));
+
+ if (i->src(2).mod.neg())
+ code[0] |= 1 << 8;
+
+ roundMode_A(i);
+
+ if (neg1)
+ code[0] |= 1 << 9;
+
+ assert(!i->saturate);
+ assert(!i->ftz);
+}
+
+void
CodeEmitterNVC0::emitFMUL(const Instruction *i)
{
bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
@@ -557,6 +579,23 @@ CodeEmitterNVC0::emitFMUL(const Instruction *i)
}
void
+CodeEmitterNVC0::emitDMUL(const Instruction *i)
+{
+ bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
+
+ emitForm_A(i, HEX64(5000, 0001));
+ roundMode_A(i);
+
+ if (neg)
+ code[0] |= 1 << 9;
+
+ assert(!i->saturate);
+ assert(!i->ftz);
+ assert(!i->dnz);
+ assert(!i->postFactor);
+}
+
+void
CodeEmitterNVC0::emitUMUL(const Instruction *i)
{
if (i->encSize == 8) {
@@ -619,6 +658,19 @@ CodeEmitterNVC0::emitFADD(const Instruction *i)
}
void
+CodeEmitterNVC0::emitDADD(const Instruction *i)
+{
+ assert(i->encSize == 8);
+ emitForm_A(i, HEX64(4800, 0001));
+ roundMode_A(i);
+ assert(!i->saturate);
+ assert(!i->ftz);
+ emitNegAbs12(i);
+ if (i->op == OP_SUB)
+ code[0] ^= 1 << 8;
+}
+
+void
CodeEmitterNVC0::emitUADD(const Instruction *i)
{
uint32_t addOp = 0;
@@ -895,6 +947,8 @@ CodeEmitterNVC0::emitMINMAX(const Instruction *i)
else
if (!isFloatType(i->dType))
op |= isSignedType(i->dType) ? 0x23 : 0x03;
+ if (i->dType == TYPE_F64)
+ op |= 0x01;
emitForm_A(i, op);
emitNegAbs12(i);
@@ -2242,20 +2296,26 @@ CodeEmitterNVC0::emitInstruction(Instruction *insn)
break;
case OP_ADD:
case OP_SUB:
- if (isFloatType(insn->dType))
+ if (insn->dType == TYPE_F64)
+ emitDADD(insn);
+ else if (isFloatType(insn->dType))
emitFADD(insn);
else
emitUADD(insn);
break;
case OP_MUL:
- if (isFloatType(insn->dType))
+ if (insn->dType == TYPE_F64)
+ emitDMUL(insn);
+ else if (isFloatType(insn->dType))
emitFMUL(insn);
else
emitUMUL(insn);
break;
case OP_MAD:
case OP_FMA:
- if (isFloatType(insn->dType))
+ if (insn->dType == TYPE_F64)
+ emitDMAD(insn);
+ else if (isFloatType(insn->dType))
emitFMAD(insn);
else
emitIMAD(insn);
--
2.0.5
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[Mesa-dev] [PATCH 08/11] nvc0/ir: handle zero and negative sqrt arguments
Signed-off-by: Ilia Mirkin
---
.../drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp| 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 8ac3b26..18e8e67 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -1567,10 +1567,22 @@ NVC0LoweringPass::handleMOD(Instruction *i)
bool
NVC0LoweringPass::handleSQRT(Instruction *i)
{
- Instruction *rsq = bld.mkOp1(OP_RSQ, i->dType,
-bld.getSSA(typeSizeof(i->dType)),
i->getSrc(0));
+ Value *pred = bld.getSSA(1, FILE_PREDICATE);
+ Value *zero = bld.getSSA();
+ Instruction *rsq;
+
+ bld.mkOp1(OP_MOV, TYPE_U32, zero, bld.mkImm(0));
+ if (i->dType == TYPE_F64)
+ zero = bld.mkOp2v(OP_MERGE, TYPE_U64, bld.getSSA(8), zero, zero);
+ bld.mkCmp(OP_SET, CC_LE, i->dType, pred, i->dType, i->getSrc(0), zero);
+ bld.mkOp1(OP_MOV, i->dType, i->getDef(0), zero)->setPredicate(CC_P, pred);
+ rsq = bld.mkOp1(OP_RSQ, i->dType,
+ bld.getSSA(typeSizeof(i->dType)), i->getSrc(0));
+ rsq->setPredicate(CC_NOT_P, pred);
i->op = OP_MUL;
i->setSrc(1, rsq->getDef(0));
+ i->setPredicate(CC_NOT_P, pred);
+
return true;
}
--
2.0.5
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[Mesa-dev] [PATCH 02/11] gk110/ir: add emission of dadd/dmul/dmad opcodes
Signed-off-by: Ilia Mirkin
---
.../drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 80 +-
1 file changed, 77 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
index d8adc93..204d911 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
@@ -84,11 +84,14 @@ private:
void emitUADD(const Instruction *);
void emitFADD(const Instruction *);
+ void emitDADD(const Instruction *);
void emitIMUL(const Instruction *);
void emitFMUL(const Instruction *);
+ void emitDMUL(const Instruction *);
void emitIMAD(const Instruction *);
void emitISAD(const Instruction *);
void emitFMAD(const Instruction *);
+ void emitDMAD(const Instruction *);
void emitNOT(const Instruction *);
void emitLogicOp(const Instruction *, uint8_t subOp);
@@ -479,6 +482,28 @@ CodeEmitterGK110::emitFMAD(const Instruction *i)
}
void
+CodeEmitterGK110::emitDMAD(const Instruction *i)
+{
+ assert(!i->saturate);
+ assert(!i->ftz);
+
+ emitForm_21(i, 0x1b8, 0xb38);
+
+ NEG_(34, 2);
+ RND_(36, F);
+
+ bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
+
+ if (code[0] & 0x1) {
+ if (neg1)
+ code[1] ^= 1 << 27;
+ } else
+ if (neg1) {
+ code[1] |= 1 << 19;
+ }
+}
+
+void
CodeEmitterGK110::emitFMUL(const Instruction *i)
{
bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
@@ -516,6 +541,29 @@ CodeEmitterGK110::emitFMUL(const Instruction *i)
}
void
+CodeEmitterGK110::emitDMUL(const Instruction *i)
+{
+ bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
+
+ assert(!i->postFactor);
+ assert(!i->saturate);
+ assert(!i->ftz);
+ assert(!i->dnz);
+
+ emitForm_21(i, 0x240, 0xc40);
+
+ RND_(2a, F);
+
+ if (code[0] & 0x1) {
+ if (neg)
+ code[1] ^= 1 << 27;
+ } else
+ if (neg) {
+ code[1] |= 1 << 19;
+ }
+}
+
+void
CodeEmitterGK110::emitIMUL(const Instruction *i)
{
assert(!i->src(0).mod.neg() && !i->src(1).mod.neg());
@@ -574,6 +622,26 @@ CodeEmitterGK110::emitFADD(const Instruction *i)
}
void
+CodeEmitterGK110::emitDADD(const Instruction *i)
+{
+ assert(!i->saturate);
+ assert(!i->ftz);
+
+ emitForm_21(i, 0x238, 0xc38);
+ RND_(2a, F);
+ ABS_(31, 0);
+ NEG_(33, 0);
+ if (code[0] & 0x1) {
+ modNegAbsF32_3b(i, 1);
+ if (i->op == OP_SUB) code[1] ^= 1 << 27;
+ } else {
+ NEG_(30, 1);
+ ABS_(34, 1);
+ if (i->op == OP_SUB) code[1] ^= 1 << 16;
+ }
+}
+
+void
CodeEmitterGK110::emitUADD(const Instruction *i)
{
uint8_t addOp = (i->src(0).mod.neg() << 1) | i->src(1).mod.neg();
@@ -1634,20 +1702,26 @@ CodeEmitterGK110::emitInstruction(Instruction *insn)
break;
case OP_ADD:
case OP_SUB:
- if (isFloatType(insn->dType))
+ if (insn->dType == TYPE_F64)
+ emitDADD(insn);
+ else if (isFloatType(insn->dType))
emitFADD(insn);
else
emitUADD(insn);
break;
case OP_MUL:
- if (isFloatType(insn->dType))
+ if (insn->dType == TYPE_F64)
+ emitDMUL(insn);
+ else if (isFloatType(insn->dType))
emitFMUL(insn);
else
emitIMUL(insn);
break;
case OP_MAD:
case OP_FMA:
- if (isFloatType(insn->dType))
+ if (insn->dType == TYPE_F64)
+ emitDMAD(insn);
+ else if (isFloatType(insn->dType))
emitFMAD(insn);
else
emitIMAD(insn);
--
2.0.5
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[Mesa-dev] [PATCH 10/11] nvc0/ir: remove merge/split pairs to allow normal propagation to occur
Because the TGSI interface creates merges for each instruction source
and then splits them back out, there are a lot of unnecessary
merge/split pairs which do essentially nothing. The various modifier/etc
propagation doesn't know how to walk though those, so just remove them
when they're unnecessary.
Signed-off-by: Ilia Mirkin
---
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 30 ++
1 file changed, 30 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 62d2ef7..6a4ea4e 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -118,6 +118,35 @@ CopyPropagation::visit(BasicBlock *bb)
//
=
+class MergeSplits : public Pass
+{
+private:
+ virtual bool visit(BasicBlock *);
+};
+
+// For SPLIT / MERGE pairs that operate on the same registers, replace the
+// post-merge def with the SPLIT's source.
+bool
+MergeSplits::visit(BasicBlock *bb)
+{
+ Instruction *i, *next, *si;
+
+ for (i = bb->getEntry(); i; i = next) {
+ next = i->next;
+ if (i->op != OP_MERGE || typeSizeof(i->dType) != 8)
+ continue;
+ si = i->getSrc(0)->getInsn();
+ if (si->op != OP_SPLIT || si != i->getSrc(1)->getInsn())
+ continue;
+ i->def(0).replace(si->getSrc(0), false);
+ delete_Instruction(prog, i);
+ }
+
+ return true;
+}
+
+//
=
+
class LoadPropagation : public Pass
{
private:
@@ -2662,6 +2691,7 @@ Program::optimizeSSA(int level)
{
RUN_PASS(1, DeadCodeElim, buryAll);
RUN_PASS(1, CopyPropagation, run);
+ RUN_PASS(1, MergeSplits, run);
RUN_PASS(2, GlobalCSE, run);
RUN_PASS(1, LocalCSE, run);
RUN_PASS(2, AlgebraicOpt, run);
--
2.0.5
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[Mesa-dev] [PATCH 09/11] nvc0/ir: add support for new TGSI double opcodes (v2)
v2: drop DDIV
Signed-off-by: Ilia Mirkin
---
.../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 196 +
1 file changed, 196 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 9ee927f..028a17e 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -441,6 +441,27 @@ nv50_ir::DataType Instruction::inferSrcType() const
case TGSI_OPCODE_IBFE:
case TGSI_OPCODE_IMSB:
return nv50_ir::TYPE_S32;
+ case TGSI_OPCODE_D2F:
+ case TGSI_OPCODE_DABS:
+ case TGSI_OPCODE_DNEG:
+ case TGSI_OPCODE_DADD:
+ case TGSI_OPCODE_DMUL:
+ case TGSI_OPCODE_DMAX:
+ case TGSI_OPCODE_DMIN:
+ case TGSI_OPCODE_DSLT:
+ case TGSI_OPCODE_DSGE:
+ case TGSI_OPCODE_DSEQ:
+ case TGSI_OPCODE_DSNE:
+ case TGSI_OPCODE_DRCP:
+ case TGSI_OPCODE_DSQRT:
+ case TGSI_OPCODE_DMAD:
+ case TGSI_OPCODE_DFRAC:
+ case TGSI_OPCODE_DRSQ:
+ case TGSI_OPCODE_DTRUNC:
+ case TGSI_OPCODE_DCEIL:
+ case TGSI_OPCODE_DFLR:
+ case TGSI_OPCODE_DROUND:
+ return nv50_ir::TYPE_F64;
default:
return nv50_ir::TYPE_F32;
}
@@ -455,10 +476,17 @@ nv50_ir::DataType Instruction::inferDstType() const
case TGSI_OPCODE_FSGE:
case TGSI_OPCODE_FSLT:
case TGSI_OPCODE_FSNE:
+ case TGSI_OPCODE_DSEQ:
+ case TGSI_OPCODE_DSGE:
+ case TGSI_OPCODE_DSLT:
+ case TGSI_OPCODE_DSNE:
return nv50_ir::TYPE_U32;
case TGSI_OPCODE_I2F:
case TGSI_OPCODE_U2F:
+ case TGSI_OPCODE_D2F:
return nv50_ir::TYPE_F32;
+ case TGSI_OPCODE_F2D:
+ return nv50_ir::TYPE_F64;
default:
return inferSrcType();
}
@@ -473,6 +501,7 @@ nv50_ir::CondCode Instruction::getSetCond() const
case TGSI_OPCODE_ISLT:
case TGSI_OPCODE_USLT:
case TGSI_OPCODE_FSLT:
+ case TGSI_OPCODE_DSLT:
return CC_LT;
case TGSI_OPCODE_SLE:
return CC_LE;
@@ -480,15 +509,18 @@ nv50_ir::CondCode Instruction::getSetCond() const
case TGSI_OPCODE_ISGE:
case TGSI_OPCODE_USGE:
case TGSI_OPCODE_FSGE:
+ case TGSI_OPCODE_DSGE:
return CC_GE;
case TGSI_OPCODE_SGT:
return CC_GT;
case TGSI_OPCODE_SEQ:
case TGSI_OPCODE_USEQ:
case TGSI_OPCODE_FSEQ:
+ case TGSI_OPCODE_DSEQ:
return CC_EQ;
case TGSI_OPCODE_SNE:
case TGSI_OPCODE_FSNE:
+ case TGSI_OPCODE_DSNE:
return CC_NEU;
case TGSI_OPCODE_USNE:
return CC_NE;
@@ -601,6 +633,25 @@ static nv50_ir::operation translateOpcode(uint opcode)
NV50_IR_OPCODE_CASE(USLT, SET);
NV50_IR_OPCODE_CASE(USNE, SET);
+ NV50_IR_OPCODE_CASE(DABS, ABS);
+ NV50_IR_OPCODE_CASE(DNEG, NEG);
+ NV50_IR_OPCODE_CASE(DADD, ADD);
+ NV50_IR_OPCODE_CASE(DMUL, MUL);
+ NV50_IR_OPCODE_CASE(DMAX, MAX);
+ NV50_IR_OPCODE_CASE(DMIN, MIN);
+ NV50_IR_OPCODE_CASE(DSLT, SET);
+ NV50_IR_OPCODE_CASE(DSGE, SET);
+ NV50_IR_OPCODE_CASE(DSEQ, SET);
+ NV50_IR_OPCODE_CASE(DSNE, SET);
+ NV50_IR_OPCODE_CASE(DRCP, RCP);
+ NV50_IR_OPCODE_CASE(DSQRT, SQRT);
+ NV50_IR_OPCODE_CASE(DMAD, MAD);
+ NV50_IR_OPCODE_CASE(DRSQ, RSQ);
+ NV50_IR_OPCODE_CASE(DTRUNC, TRUNC);
+ NV50_IR_OPCODE_CASE(DCEIL, CEIL);
+ NV50_IR_OPCODE_CASE(DFLR, FLOOR);
+ NV50_IR_OPCODE_CASE(DROUND, CVT);
+
NV50_IR_OPCODE_CASE(IMUL_HI, MUL);
NV50_IR_OPCODE_CASE(UMUL_HI, MUL);
@@ -2880,6 +2931,151 @@ Converter::handleInstruction(const struct
tgsi_full_instruction *insn)
case TGSI_OPCODE_INTERP_OFFSET:
handleINTERP(dst0);
break;
+ case TGSI_OPCODE_D2F: {
+ int pos = 0;
+ FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
+ Value *dreg = getSSA(8);
+ src0 = fetchSrc(0, pos);
+ src1 = fetchSrc(0, pos + 1);
+ mkOp2(OP_MERGE, TYPE_U64, dreg, src0, src1);
+ mkCvt(OP_CVT, dstTy, dst0[c], srcTy, dreg);
+ pos += 2;
+ }
+ break;
+ }
+ case TGSI_OPCODE_F2D:
+ FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
+ Value *dreg = getSSA(8);
+ mkCvt(OP_CVT, dstTy, dreg, srcTy, fetchSrc(0, c / 2));
+ mkSplit(&dst0[c], 4, dreg);
+ c++;
+ }
+ break;
+ case TGSI_OPCODE_DABS:
+ case TGSI_OPCODE_DNEG:
+ case TGSI_OPCODE_DRCP:
+ case TGSI_OPCODE_DSQRT:
+ case TGSI_OPCODE_DRSQ:
+ case TGSI_OPCODE_DTRUNC:
+ case TGSI_OPCODE_DCEIL:
+ case TGSI_OPCODE_DFLR:
+ FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
+ src0 = getSSA(8);
+ Value *dst = getSSA(8), *tmp[2];
+ tmp[0] = fetchSrc(0, c);
+ tmp[1] = fetchSrc(0, c + 1);
+ mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
+ mkOp1(op, dstTy, dst, src0);
+ mkSplit(&dst0[c], 4, dst);
+ c++;
+ }
+ break;
+ case TGSI_OPCODE_DFRAC:
+ FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
+ src0 = getSSA(8);
+ Value *dst = getSSA(8), *tmp[2];
+ tmp[0] = fetchSrc(0, c);
+ tmp[
[Mesa-dev] [PATCH 06/11] nvc0/ir: fix lowering of RSQ/RCP/SQRT/MOD to work with F64
Signed-off-by: Ilia Mirkin
---
src/gallium/drivers/nouveau/codegen/nv50_ir.h | 1 +
.../drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 4 +-
.../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 4 +-
.../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 4 +-
.../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 43 +-
5 files changed, 40 insertions(+), 16 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
index 0ff5e5d..529dcb9 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
@@ -175,6 +175,7 @@ enum operation
#define NV50_IR_SUBOP_MOV_FINAL1
#define NV50_IR_SUBOP_EXTBF_REV1
#define NV50_IR_SUBOP_BFIND_SAMT 1
+#define NV50_IR_SUBOP_RCPRSQ_64H 1
#define NV50_IR_SUBOP_PERMT_F4E1
#define NV50_IR_SUBOP_PERMT_B4E2
#define NV50_IR_SUBOP_PERMT_RC83
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
index 204d911..674be69 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
@@ -1771,10 +1771,10 @@ CodeEmitterGK110::emitInstruction(Instruction *insn)
emitCVT(insn);
break;
case OP_RSQ:
- emitSFnOp(insn, 5);
+ emitSFnOp(insn, 5 + 2 * insn->subOp);
break;
case OP_RCP:
- emitSFnOp(insn, 4);
+ emitSFnOp(insn, 4 + 2 * insn->subOp);
break;
case OP_LG2:
emitSFnOp(insn, 3);
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index 3e1da7e..ee0487f 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
@@ -1265,8 +1265,8 @@ CodeEmitterGM107::emitMUFU()
case OP_SIN: mufu = 1; break;
case OP_EX2: mufu = 2; break;
case OP_LG2: mufu = 3; break;
- case OP_RCP: mufu = 4; break;
- case OP_RSQ: mufu = 5; break;
+ case OP_RCP: mufu = 4 + 2 * insn->subOp; break;
+ case OP_RSQ: mufu = 5 + 2 * insn->subOp; break;
default:
assert(!"invalid mufu");
break;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index e38a3b8..1a4f6e0 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -2365,10 +2365,10 @@ CodeEmitterNVC0::emitInstruction(Instruction *insn)
emitCVT(insn);
break;
case OP_RSQ:
- emitSFnOp(insn, 5);
+ emitSFnOp(insn, 5 + 2 * insn->subOp);
break;
case OP_RCP:
- emitSFnOp(insn, 4);
+ emitSFnOp(insn, 4 + 2 * insn->subOp);
break;
case OP_LG2:
emitSFnOp(insn, 3);
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 5dfb777..8ac3b26 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -70,7 +70,30 @@ NVC0LegalizeSSA::handleDIV(Instruction *i)
void
NVC0LegalizeSSA::handleRCPRSQ(Instruction *i)
{
- // TODO
+ assert(i->dType == TYPE_F64);
+ // There are instructions that will compute the high 32 bits of the 64-bit
+ // float. We will just stick 0 in the bottom 32 bits.
+
+ bld.setPosition(i, false);
+
+ // 1. Take the source and it up.
+ Value *src[2], *dst[2], *def = i->getDef(0);
+ bld.mkSplit(src, 4, i->getSrc(0));
+
+ // 2. We don't care about the low 32 bits of the destination. Stick a 0 in.
+ dst[0] = bld.loadImm(NULL, 0);
+ dst[1] = bld.getSSA();
+
+ // 3. The new version of the instruction takes the high 32 bits of the
+ // source and outputs the high 32 bits of the destination.
+ i->setSrc(0, src[1]);
+ i->setDef(0, dst[1]);
+ i->setType(TYPE_F32);
+ i->subOp = NV50_IR_SUBOP_RCPRSQ_64H;
+
+ // 4. Recombine the two dst pieces back into the original destination.
+ bld.setPosition(i, true);
+ bld.mkOp2(OP_MERGE, TYPE_U64, def, dst[0], dst[1]);
}
bool
@@ -1520,7 +1543,7 @@ NVC0LoweringPass::handleDIV(Instruction *i)
if (!isFloatType(i->dType))
return true;
bld.setPosition(i, false);
- Instruction *rcp = bld.mkOp1(OP_RCP, i->dType, bld.getSSA(), i->getSrc(1));
+ Instruction *rcp = bld.mkOp1(OP_RCP, i->dType,
bld.getSSA(typeSizeof(i->dType)), i->getSrc(1));
i->op = OP_MUL;
i->setSrc(1, rcp->getDef(0));
return true;
@@ -1529,13 +1552,13 @@ NVC0LoweringPass::handleDIV(Instruction *i)
bool
NVC0LoweringPass::handleMOD(Instruction *i)
{
- if (i->dType != TYPE_F32)
+ if (!isFloatType(i->dType))
return true;
- LValue *value = bld.getScratch();
- bld.mkOp1(OP_RCP, TYPE_F32, value, i->getSrc(1));
- bld.mkOp2(OP_MUL, TY
[Mesa-dev] [PATCH 04/11] gm107/ir: fix DSET boolean float flag
Signed-off-by: Ilia Mirkin --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp index 9f4c435..73a65fa 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp @@ -1060,6 +1060,7 @@ CodeEmitterGM107::emitDSET() emitABS (0x36, insn->src(0)); emitNEG (0x35, insn->src(1)); + emitField(0x34, 1, insn->dType == TYPE_F32); emitCond4(0x30, insn->setCond); emitCC (0x2f); emitABS (0x2c, insn->src(1)); -- 2.0.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 07/11] nvc0/ir: no instruction can load a double immediate
Signed-off-by: Ilia Mirkin
---
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
index 817ceb8..7d4a859 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
@@ -337,6 +337,8 @@ TargetNVC0::insnCanLoad(const Instruction *i, int s,
if (sf == FILE_IMMEDIATE) {
Storage ® = ld->getSrc(0)->asImm()->reg;
+ if (typeSizeof(i->sType) > 4)
+ return false;
if (opInfo[i->op].immdBits != 0x) {
if (i->sType == TYPE_F32) {
if (reg.data.u32 & 0xfff)
--
2.0.5
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[Mesa-dev] [PATCH 05/11] gm107/ir: fix F2F flipped stype/dtype flags
Signed-off-by: Ilia Mirkin --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp index 73a65fa..3e1da7e 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp @@ -731,8 +731,8 @@ CodeEmitterGM107::emitF2F() emitField(0x2d, 1, (insn->op == OP_NEG) || insn->src(0).mod.neg()); emitFMZ (0x2c, 1); emitRND (0x27, rnd, 0x2a); - emitField(0x0a, 2, util_logbase2(typeSizeof(insn->dType))); - emitField(0x08, 2, util_logbase2(typeSizeof(insn->sType))); + emitField(0x0a, 2, util_logbase2(typeSizeof(insn->sType))); + emitField(0x08, 2, util_logbase2(typeSizeof(insn->dType))); emitGPR (0x00, insn->def(0)); } -- 2.0.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 11/11] nvc0: enable double support
Signed-off-by: Ilia Mirkin --- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index 8546ac8..686d892 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -291,9 +291,9 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, case PIPE_SHADER_CAP_INTEGERS: return 1; case PIPE_SHADER_CAP_DOUBLES: - return 0; + return 1; case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: - return 0; + return 1; case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: return 0; case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: -- 2.0.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 03/11] gm107/ir: fix DMUL opcode encoding
Signed-off-by: Ilia Mirkin
---
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index 944ceb2..9f4c435 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
@@ -924,15 +924,15 @@ CodeEmitterGM107::emitDMUL()
{
switch (insn->src(1).getFile()) {
case FILE_GPR:
- emitInsn(0x5c68);
+ emitInsn(0x5c80);
emitGPR (0x14, insn->src(1));
break;
case FILE_MEMORY_CONST:
- emitInsn(0x4c68);
+ emitInsn(0x4c80);
emitCBUF(0x22, -1, 0x14, 16, 2, insn->src(1));
break;
case FILE_IMMEDIATE:
- emitInsn(0x3868);
+ emitInsn(0x3880);
emitIMMD(0x14, 19, insn->src(1));
break;
default:
--
2.0.5
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[Mesa-dev] [Bug 89238] "nir/nir.h", line 643: Error: In this declaration "src" is of an incomplete type "nir_alu_src[]".
https://bugs.freedesktop.org/show_bug.cgi?id=89238 Jason Ekstrand changed: What|Removed |Added Status|NEW |NEEDINFO --- Comment #1 from Jason Ekstrand --- Can you try replacing "nir_alu_src src[]" with "nir_alu_src src[0]" and making the corresponding change to nir_intrinsic_instr" -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] fp64: disable varying packing for doubles.
From: Dave Airlie
I'm not sure we really care about this, but we need to
write better support if we do. For now just disable it.
piglit test:
tests/spec/arb_gpu_shader_fp64/execution/vs-out-fs-in-double-2.shader_test
Signed-off-by: Dave Airlie
---
src/glsl/lower_packed_varyings.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/glsl/lower_packed_varyings.cpp
b/src/glsl/lower_packed_varyings.cpp
index 5e844c7..3c9cbec 100644
--- a/src/glsl/lower_packed_varyings.cpp
+++ b/src/glsl/lower_packed_varyings.cpp
@@ -592,6 +592,9 @@ lower_packed_varyings_visitor::needs_lowering(ir_variable
*var)
return false;
const glsl_type *type = var->type;
+ /* don't attempt to pack double varyings yet */
+ if (type->base_type == GLSL_TYPE_DOUBLE)
+ return false;
if (this->gs_input_vertices != 0) {
assert(type->is_array());
type = type->element_type();
--
1.9.3
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Re: [Mesa-dev] [PATCH] fp64: disable varying packing for doubles.
On Thu, Feb 19, 2015 at 9:43 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> I'm not sure we really care about this, but we need to
> write better support if we do. For now just disable it.
>
> piglit test:
> tests/spec/arb_gpu_shader_fp64/execution/vs-out-fs-in-double-2.shader_test
>
> Signed-off-by: Dave Airlie
> ---
> src/glsl/lower_packed_varyings.cpp | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/src/glsl/lower_packed_varyings.cpp
> b/src/glsl/lower_packed_varyings.cpp
> index 5e844c7..3c9cbec 100644
> --- a/src/glsl/lower_packed_varyings.cpp
> +++ b/src/glsl/lower_packed_varyings.cpp
> @@ -592,6 +592,9 @@ lower_packed_varyings_visitor::needs_lowering(ir_variable
> *var)
>return false;
>
> const glsl_type *type = var->type;
> + /* don't attempt to pack double varyings yet */
> + if (type->base_type == GLSL_TYPE_DOUBLE)
> + return false;
Not sure, but I _think_ type can be an array here... (or even worse, a
struct... hopefully not). Should be simple to whip up some piglits. If
I'm right on the array, you can do type->without_array(). If it can
also be a struct, then maybe ->contains_double()?
> if (this->gs_input_vertices != 0) {
>assert(type->is_array());
>type = type->element_type();
> --
> 1.9.3
>
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Re: [Mesa-dev] [PATCH 2/2] r600g: add doubles support for CAYMAN
On Fri, 20 Feb 2015 01:54:03 +0100, Dave Airlie wrote:
From: Dave Airlie
Only a subset of AMD GPUs supported by r600g support doubles,
CAYMAN and CYPRESS are probably all we'll try and support, however
I don't have a CYPRESS so ignore that for now.
This disables SB support for doubles, as we think we need to
make the scheduler smarter to introduce delay slots.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_asm.c| 14 ++
src/gallium/drivers/r600/r600_asm.h| 15 ++
src/gallium/drivers/r600/r600_isa.h| 8 +-
src/gallium/drivers/r600/r600_pipe.c | 2 +
src/gallium/drivers/r600/r600_shader.c | 389
-
src/gallium/drivers/r600/r600_shader.h | 2 +
6 files changed, 424 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
index 79e7f74..dc26b63 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -252,6 +252,12 @@ static int alu_uses_rel(struct r600_bytecode *bc,
struct r600_bytecode_alu *alu)
return 0;
}
+static int is_alu_64bit_inst(struct r600_bytecode *bc, struct
r600_bytecode_alu *alu)
+{
+ const struct alu_op_info *op = r600_isa_alu(alu->op);
+ return (op->flags & AF_64);
+}
+
static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct
r600_bytecode_alu *alu)
{
unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
@@ -576,6 +582,12 @@ static int replace_gpr_with_pv_ps(struct
r600_bytecode *bc,
for (i = 0; i < max_slots; ++i) {
if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) &&
!prev[i]->dst.rel) {
+
+ if (is_alu_64bit_inst(bc, prev[i])) {
+ gpr[i] = -1;
+ continue;
+ }
+
gpr[i] = prev[i]->dst.sel;
/* cube writes more than PV.X */
if (is_alu_reduction_inst(bc, prev[i]))
@@ -591,6 +603,8 @@ static int replace_gpr_with_pv_ps(struct
r600_bytecode *bc,
if(!alu)
continue;
+ if (is_alu_64bit_inst(bc, alu))
+ continue;
num_src = r600_bytecode_get_num_operands(bc, alu);
for (src = 0; src < num_src; ++src) {
if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
diff --git a/src/gallium/drivers/r600/r600_asm.h
b/src/gallium/drivers/r600/r600_asm.h
index e37d926..7b2734c 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -279,4 +279,19 @@ void eg_bytecode_export_read(struct r600_bytecode
*bc,
void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
unsigned *num_format, unsigned *format_comp,
unsigned *endian);
+
+static INLINE int fp64_switch(int i)
+{
Rather hard to decipher what this function does. How about
fp64_gpr_channel_swizzle?
+ switch (i) {
+ case 0:
+ return 1;
+ case 1:
+ return 0;
+ case 2:
+ return 3;
+ case 3:
+ return 2;
+ }
+ return 0;
+}
#endif
diff --git a/src/gallium/drivers/r600/r600_isa.h
b/src/gallium/drivers/r600/r600_isa.h
index ec3f702..3cc135e 100644
--- a/src/gallium/drivers/r600/r600_isa.h
+++ b/src/gallium/drivers/r600/r600_isa.h
@@ -339,11 +339,11 @@ static const struct alu_op_info alu_op_table[] = {
Might be an idea to fix up the table entries for MULADD for R6xx/R7xx,
they are 4 slot too.
FREXP_64 is a 4 slot instruction, not 2.
{"PRED_SETGT_64", 2, { 0x7C, 0xC7 },{ AF_V, AF_V,
AF_V, AF_V}, AF_PRED | AF_CC_GT | AF_64 },
{"PRED_SETE_64", 2, { 0x7D, 0xC8 },{ AF_V, AF_V,
AF_V, AF_V}, AF_PRED | AF_CC_E | AF_64 },
{"PRED_SETGE_64", 2, { 0x7E, 0xC9 },{ AF_V, AF_V,
AF_V, AF_V}, AF_PRED | AF_CC_GE | AF_64 },
- {"MUL_64",2, { 0x1B, 0xCA },{ AF_V, AF_V,
AF_V, AF_V}, AF_64 },
+ {"MUL_64",2, { 0x1B, 0xCA },{ AF_V, AF_V,
4 slot instruction also on r600/r700/evergreen, might as well fix the
table entries while touching this
AF_V, AF_4V}, AF_64 },
{"ADD_64",2, { 0x17, 0xCB },{ AF_V, AF_V,
AF_V, AF_V}, AF_64 },
{"MOVA_INT", 1, { 0x18, 0xCC },{ AF_V, AF_V,
AF_V, AF_V}, AF_MOVA },
- {"FLT64_TO_FLT32",1, { 0x1C, 0xCD },{ AF_V, AF_V,
AF_V, AF_V}, 0 },
- {"FLT32_TO_FLT64",1, { 0x1D, 0xCE },{ AF_V, AF_V,
AF_V, AF_V}, 0 },
+ {"FLT64_TO_FLT32",1, { 0x1C, 0xCD },{ AF_V, AF_V,
AF_V, AF_V}, AF_64 },
+ {"FLT32_TO_FLT64",1, { 0x1D, 0xCE },{ AF_V, AF_V,
AF_V, AF_V}, AF_64 },
{"SAD_ACCUM_PREV_UINT", 2, { -1, 0xCF },{ 0, 0,
AF_V, AF_V}, AF_
[Mesa-dev] [Bug 89238] "nir/nir.h", line 643: Error: In this declaration "src" is of an incomplete type "nir_alu_src[]".
https://bugs.freedesktop.org/show_bug.cgi?id=89238 --- Comment #2 from Connor Abbott --- See this thread: http://lists.freedesktop.org/archives/mesa-dev/2015-February/077137.html looks like there are a few (mostly trivial) patches needed. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v5] mesa: use fi_type in vertex attribute code
From: Marius Predut
For 32-bit builds, floating point operations use x86 FPU registers,
not SSE registers. If we're actually storing an integer in a float
variable, the value might get modified when written to memory. This
patch changes the VBO code to use the fi_type (float/int union) to
store/copy vertex attributes.
Also, this can improve performance on x86 because moving floats with
integer registers instead of FP registers is faster.
Neil Roberts review:
- include changes on all places that are storing attribute values.
- check with and without -O3 compiler flag.
Brian Paul review:
- use fi_type type instead gl_constant_value type
- fix a bunch of nit-picks.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82668
Signed-off-by: Marius Predut
---
src/mesa/main/context.c |3 ++-
src/mesa/main/macros.h| 34 ++
src/mesa/vbo/vbo_attrib_tmp.h | 22 ++
src/mesa/vbo/vbo_context.h| 14 +++---
src/mesa/vbo/vbo_exec.h | 11 ++-
src/mesa/vbo/vbo_exec_api.c | 34 +-
src/mesa/vbo/vbo_exec_draw.c |6 +++---
src/mesa/vbo/vbo_exec_eval.c | 24 +---
src/mesa/vbo/vbo_save.h | 16
src/mesa/vbo/vbo_save_api.c | 34 +-
src/mesa/vbo/vbo_save_draw.c |4 ++--
11 files changed, 111 insertions(+), 91 deletions(-)
diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index 63d30a2..f0597e2 100644
--- a/src/mesa/main/context.c
+++ b/src/mesa/main/context.c
@@ -134,6 +134,7 @@
#include "math/m_matrix.h"
#include "main/dispatch.h" /* for _gloffset_COUNT */
#include "uniforms.h"
+#include "macros.h"
#ifdef USE_SPARC_ASM
#include "sparc/sparc.h"
@@ -656,7 +657,7 @@ _mesa_init_constants(struct gl_constants *consts, gl_api
api)
consts->MaxSamples = 0;
/* GLSL default if NativeIntegers == FALSE */
- consts->UniformBooleanTrue = FLT_AS_UINT(1.0f);
+ consts->UniformBooleanTrue = FLOAT_AS_UNION(1.0f).u;
/* GL_ARB_sync */
consts->MaxServerWaitTimeout = 0x1fff7fffULL;
diff --git a/src/mesa/main/macros.h b/src/mesa/main/macros.h
index 2d59c6f..70d0556 100644
--- a/src/mesa/main/macros.h
+++ b/src/mesa/main/macros.h
@@ -170,25 +170,25 @@ extern GLfloat _mesa_ubyte_to_float_color_tab[256];
ub = ((GLubyte) F_TO_I((f) * 255.0F))
#endif
-static inline GLfloat INT_AS_FLT(GLint i)
+static fi_type UINT_AS_UNION(GLuint u)
{
fi_type tmp;
- tmp.i = i;
- return tmp.f;
+ tmp.u = u;
+ return tmp;
}
-static inline GLfloat UINT_AS_FLT(GLuint u)
+static inline fi_type INT_AS_UNION(GLint i)
{
fi_type tmp;
- tmp.u = u;
- return tmp.f;
+ tmp.i = i;
+ return tmp;
}
-static inline unsigned FLT_AS_UINT(float f)
+static inline fi_type FLOAT_AS_UNION(GLfloat f)
{
fi_type tmp;
tmp.f = f;
- return tmp.u;
+ return tmp;
}
/**
@@ -620,24 +620,26 @@ do { \
* The default values are chosen based on \p type.
*/
static inline void
-COPY_CLEAN_4V_TYPE_AS_FLOAT(GLfloat dst[4], int sz, const GLfloat src[4],
+COPY_CLEAN_4V_TYPE_AS_UNION(fi_type dst[4], int sz, const fi_type src[4],
GLenum type)
{
switch (type) {
case GL_FLOAT:
- ASSIGN_4V(dst, 0, 0, 0, 1);
+ ASSIGN_4V(dst, FLOAT_AS_UNION(0), FLOAT_AS_UNION(0),
+FLOAT_AS_UNION(0), FLOAT_AS_UNION(1));
break;
case GL_INT:
- ASSIGN_4V(dst, INT_AS_FLT(0), INT_AS_FLT(0),
- INT_AS_FLT(0), INT_AS_FLT(1));
+ ASSIGN_4V(dst, INT_AS_UNION(0), INT_AS_UNION(0),
+INT_AS_UNION(0), INT_AS_UNION(1));
break;
case GL_UNSIGNED_INT:
- ASSIGN_4V(dst, UINT_AS_FLT(0), UINT_AS_FLT(0),
- UINT_AS_FLT(0), UINT_AS_FLT(1));
+ ASSIGN_4V(dst, UINT_AS_UNION(0), UINT_AS_UNION(0),
+UINT_AS_UNION(0), UINT_AS_UNION(1));
break;
default:
- ASSIGN_4V(dst, 0.0f, 0.0f, 0.0f, 1.0f); /* silence warnings */
- ASSERT(!"Unexpected type in COPY_CLEAN_4V_TYPE_AS_FLOAT macro");
+ ASSIGN_4V(dst, FLOAT_AS_UNION(0), FLOAT_AS_UNION(0),
+FLOAT_AS_UNION(0), FLOAT_AS_UNION(1)); /* silence warnings */
+ ASSERT(!"Unexpected type in COPY_CLEAN_4V_TYPE_AS_UNION macro");
}
COPY_SZ_4V(dst, sz, src);
}
diff --git a/src/mesa/vbo/vbo_attrib_tmp.h b/src/mesa/vbo/vbo_attrib_tmp.h
index ec66934..80e8aaf 100644
--- a/src/mesa/vbo/vbo_attrib_tmp.h
+++ b/src/mesa/vbo/vbo_attrib_tmp.h
@@ -28,6 +28,22 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "util/u_format_r11g11b10f.h"
#include "main/varray.h"
+
+/* ATTR */
+#define ATTR( A, N, T, V0, V1, V2, V3 ) \
+ATTR_##T((A), (N), (T), (V0), (V1), (V2), (V3))
+
+#define ATTR_GL_UNSIGNED_INT( A, N, T, V0, V1, V2, V3 ) \
+ATTR_UNION(A, N, T, UINT_AS_UNION(V0), UINT_AS_UNION(V1), \
+UINT_AS_UNION(V2), UINT_AS_UNION(V3))
+#def
[Mesa-dev] [PATCH] st/glsl_to_tgsi: fix ir_assignment hack doing bad things for doubles
From: Dave Airlie
This hack for fixing gl_FragDepth apparantly caused a GLSL shader
outputting a single double to try and output a dvec4, but we hadn't
assigned outputs for the secondary bit.
This avoids going into the hack code for scalar doubles.
Signed-off-by: Dave Airlie
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index e3f79ed..51ee98a 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -2727,6 +2727,7 @@ glsl_to_tgsi_visitor::visit(ir_assignment *ir)
assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector());
l.writemask = WRITEMASK_XYZW;
} else if (ir->lhs->type->is_scalar() &&
+ !ir->lhs->type->is_double() &&
ir->lhs->variable_referenced()->data.mode == ir_var_shader_out) {
/* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
* FINISHME: W component of fragment shader output zero, work correctly.
--
1.9.3
___
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