Re: [Mesa-dev] [PATCH v2 08/10] glsl: A shader cannot redefine or overload built-in functions in GLSL ES 3.00
On Thursday, February 19, 2015 09:55:35 AM Samuel Iglesias Gonsalvez wrote: Create a new search function to look for matching built-in functions by name and use it for built-in function redefinition or overload in GLSL ES 3.00. GLSL ES 3.0 spec, chapter 6.1 Function Definitions, page 71 A shader cannot redefine or overload built-in functions. While in GLSL ES 1.0 specification, chapter 8 Built-in Functions User code can overload the built-in functions but cannot redefine them. So this check is specific to GLSL ES 3.00. This patch fixes the following dEQP tests: dEQP-GLES3.functional.shaders.functions.invalid.overload_builtin_function_vertex dEQP-GLES3.functional.shaders.functions.invalid.overload_builtin_function_fragment dEQP-GLES3.functional.shaders.functions.invalid.redefine_builtin_function_vertex dEQP-GLES3.functional.shaders.functions.invalid.redefine_builtin_function_fragment No piglit regressions. Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com --- src/glsl/ast_to_hir.cpp| 21 + src/glsl/builtin_functions.cpp | 11 +++ src/glsl/ir.h | 4 3 files changed, 36 insertions(+) This looks great - thanks! Reviewed-by: Kenneth Graunke kenn...@whitecape.org signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2 08/10] glsl: A shader cannot redefine or overload built-in functions in GLSL ES 3.00
On Thursday 19 February 2015 00:59:56 Kenneth Graunke wrote: On Thursday, February 19, 2015 09:55:35 AM Samuel Iglesias Gonsalvez wrote: Create a new search function to look for matching built-in functions by name and use it for built-in function redefinition or overload in GLSL ES 3.00. GLSL ES 3.0 spec, chapter 6.1 Function Definitions, page 71 A shader cannot redefine or overload built-in functions. While in GLSL ES 1.0 specification, chapter 8 Built-in Functions User code can overload the built-in functions but cannot redefine them. So this check is specific to GLSL ES 3.00. This patch fixes the following dEQP tests: dEQP-GLES3.functional.shaders.functions.invalid.overload_builtin_function_ vertex dEQP-GLES3.functional.shaders.functions.invalid.overload_builtin_function _fragment dEQP-GLES3.functional.shaders.functions.invalid.redefine_builtin_function _vertex dEQP-GLES3.functional.shaders.functions.invalid.redefine_builtin_function _fragment No piglit regressions. Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com --- src/glsl/ast_to_hir.cpp| 21 + src/glsl/builtin_functions.cpp | 11 +++ src/glsl/ir.h | 4 3 files changed, 36 insertions(+) This looks great - thanks! Reviewed-by: Kenneth Graunke kenn...@whitecape.org Thanks!! pushed! Sam signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 08/10] glsl: A shader cannot redefine or overload built-in functions in GLSL ES 3.00
Create a new search function to look for matching built-in functions by name
and use it for built-in function redefinition or overload in GLSL ES 3.00.
GLSL ES 3.0 spec, chapter 6.1 Function Definitions, page 71
A shader cannot redefine or overload built-in functions.
While in GLSL ES 1.0 specification, chapter 8 Built-in Functions
User code can overload the built-in functions but cannot redefine them.
So this check is specific to GLSL ES 3.00.
This patch fixes the following dEQP tests:
dEQP-GLES3.functional.shaders.functions.invalid.overload_builtin_function_vertex
dEQP-GLES3.functional.shaders.functions.invalid.overload_builtin_function_fragment
dEQP-GLES3.functional.shaders.functions.invalid.redefine_builtin_function_vertex
dEQP-GLES3.functional.shaders.functions.invalid.redefine_builtin_function_fragment
No piglit regressions.
Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
---
src/glsl/ast_to_hir.cpp| 21 +
src/glsl/builtin_functions.cpp | 11 +++
src/glsl/ir.h | 4
3 files changed, 36 insertions(+)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 2c63de0..acb5c76 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -4205,6 +4205,27 @@ ast_function::hir(exec_list *instructions,
emit_function(state, f);
}
+ /* From GLSL ES 3.0 spec, chapter 6.1 Function Definitions, page 71:
+*
+* A shader cannot redefine or overload built-in functions.
+*
+* While in GLSL ES 1.0 specification, chapter 8 Built-in Functions:
+*
+* User code can overload the built-in functions but cannot redefine
+* them.
+*/
+ if (state-es_shader state-language_version = 300) {
+ /* Local shader has no exact candidates; check the built-ins. */
+ _mesa_glsl_initialize_builtin_functions();
+ if (_mesa_glsl_find_builtin_function_by_name(state, name)) {
+ YYLTYPE loc = this-get_location();
+ _mesa_glsl_error( loc, state,
+ A shader cannot redefine or overload built-in
+ function `%s' in GLSL ES 3.00, name);
+ return NULL;
+ }
+ }
+
/* Verify that this function's signature either doesn't match a previously
* seen signature for a function with the same name, or, if a match is
found,
* that the previously seen signature does not have an associated
definition.
diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp
index fb31dad..b643927 100644
--- a/src/glsl/builtin_functions.cpp
+++ b/src/glsl/builtin_functions.cpp
@@ -4851,6 +4851,17 @@ _mesa_glsl_find_builtin_function(_mesa_glsl_parse_state
*state,
return s;
}
+ir_function *
+_mesa_glsl_find_builtin_function_by_name(_mesa_glsl_parse_state *state,
+ const char *name)
+{
+ ir_function *f;
+ mtx_lock(builtins_lock);
+ f = builtins.shader-symbols-get_function(name);
+ mtx_unlock(builtins_lock);
+ return f;
+}
+
gl_shader *
_mesa_glsl_get_builtin_function_shader()
{
diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index 8c3845f..ce35b2b 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -2439,6 +2439,10 @@ extern ir_function_signature *
_mesa_glsl_find_builtin_function(_mesa_glsl_parse_state *state,
const char *name, exec_list
*actual_parameters);
+extern ir_function *
+_mesa_glsl_find_builtin_function_by_name(_mesa_glsl_parse_state *state,
+ const char *name);
+
extern gl_shader *
_mesa_glsl_get_builtin_function_shader(void);
--
2.1.0
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Re: [Mesa-dev] [PATCH 2/2] st/mesa: add GSL_TYPE_DOUBLE, new ir_unop_* switch cases
On Thu, Feb 19, 2015 at 11:27 AM, Brian Paul bri...@vmware.com wrote:
To silence compiler warnings about unhandled switch cases.
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 12
1 file changed, 12 insertions(+)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 3dac004..9969fac 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -974,6 +974,7 @@ type_size(const struct glsl_type *type)
case GLSL_TYPE_UINT:
case GLSL_TYPE_INT:
case GLSL_TYPE_FLOAT:
+ case GLSL_TYPE_DOUBLE:
case GLSL_TYPE_BOOL:
if (type-is_matrix()) {
return type-matrix_columns;
Both here and in the other patch, I'd rather you put this along with
the other unexpected types. The st/mesa patch will fix it up
properly -- double has more complex type_size() requirements.
-ilia
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Re: [Mesa-dev] [PATCH 3/9] glsl: Create a _mesa_shader_stage_to_abbrev() function.
On 02/18/2015 09:00 PM, Kenneth Graunke wrote:
This is similar to _mesa_shader_stage_to_string(), but returns VS
instead of vertex.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/glsl/glsl_parser_extras.cpp | 17 +
src/glsl/glsl_parser_extras.h | 3 +++
2 files changed, 20 insertions(+)
diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp
index ccdf031..0334e4a 100644
--- a/src/glsl/glsl_parser_extras.cpp
+++ b/src/glsl/glsl_parser_extras.cpp
@@ -376,6 +376,23 @@ _mesa_shader_stage_to_string(unsigned stage)
return unknown;
}
+/**
+ * Translate a gl_shader_stage to a shader stage abbreviation (VS, GS, FS)
+ * for debug printouts and error messages.
+ */
+const char *
+_mesa_shader_stage_to_abbrev(unsigned stage)
+{
+ switch (stage) {
+ case MESA_SHADER_VERTEX: return VS;
+ case MESA_SHADER_FRAGMENT: return FS;
+ case MESA_SHADER_GEOMETRY: return GS;
The next patch has some compute bits, should this also do compute?
+ }
+
+ assert(!Should not get here.);
+ return unknown;
unreachable(Bad shader stage.);
+}
+
/* This helper function will append the given message to the shader's
info log and report it via GL_ARB_debug_output. Per that extension,
'type' is one of the enum values classifying the message, and
diff --git a/src/glsl/glsl_parser_extras.h b/src/glsl/glsl_parser_extras.h
index 843fdae..6861fac 100644
--- a/src/glsl/glsl_parser_extras.h
+++ b/src/glsl/glsl_parser_extras.h
@@ -576,6 +576,9 @@ extern C {
extern const char *
_mesa_shader_stage_to_string(unsigned stage);
+extern const char *
+_mesa_shader_stage_to_abbrev(unsigned stage);
+
extern int glcpp_preprocess(void *ctx, const char **shader, char **info_log,
const struct gl_extensions *extensions, struct
gl_context *gl_ctx);
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[Mesa-dev] [PATCH] glsl: Use the without_array predicate
---
src/glsl/ir.h | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index a0f48b2..9c60b07 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -450,11 +450,8 @@ public:
*/
inline bool is_interface_instance() const
{
- const glsl_type *const t = this-type;
-
- return (t == this-interface_type)
- || (t-is_array() t-fields.array == this-interface_type);
-}
+ return (this-type-without_array() == this-interface_type);
+ }
/**
* Set this-interface_type on a newly created variable.
--
2.1.0
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Re: [Mesa-dev] [PATCH] glsl: don't allow invariant qualifiers for interface blocks
On 12/09/2014 02:52 AM, Eduardo Lima Mitev wrote: From: Samuel Iglesias Gonsalvez sigles...@igalia.com GLSL 1.50 and GLSL 4.40 specs, they both say the same in Interface Blocks section: If no optional qualifier is used in a member-declaration, the qualification of the member includes all in, out, patch, uniform, or buffer as determined by interface-qualifier. If optional qualifiers are used, they can include interpolation qualifiers, auxiliary storage qualifiers, and storage qualifiers and they must declare an input, output, or uniform member consistent with the interface qualifier of the block From GLSL ES 3.0, chapter 4.3.7 Interface Blocks, page 38: GLSL ES 3.0 does not support interface blocks for shader inputs or outputs. and from GLSL ES 3.0, chapter 4.6.1 The invariant qualifier, page 52. Only variables output from a shader can be candidates for invariance. This includes user-defined output variables and the built-in output variables. As only outputs can be declared as invariant, an invariant output from one shader stage will still match an input of a subsequent stage without the input being declared as invariant. From GLSL ES 1.0, chapter 4.6.1 The invariant qualifier, page 37. Only the following variables may be declared as invariant: * Built-in special variables output from the vertex shader * Varying variables output from the vertex shader * Built-in special variables input to the fragment shader * Varying variables input to the fragment shader * Built-in special variables output from the fragment shader. This patch fixes the following dEQP tests: dEQP-GLES3.functional.shaders.declarations.invalid_declarations.invariant_uniform_block_2_vertex dEQP-GLES3.functional.shaders.declarations.invalid_declarations.invariant_uniform_block_2_fragment No piglit regressions. Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com v2: - Enable this check for GLSL. Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com --- src/glsl/glsl_parser.yy | 35 +++ 1 file changed, 35 insertions(+) diff --git a/src/glsl/glsl_parser.yy b/src/glsl/glsl_parser.yy index 7fb8c38..9f2a0a3 100644 --- a/src/glsl/glsl_parser.yy +++ b/src/glsl/glsl_parser.yy @@ -2539,6 +2539,41 @@ basic_interface_block: interface block member does not match the interface block); } Blank line here. + /* From GLSL ES 3.0, chapter 4.3.7 Interface Blocks, page 38: + * + * GLSL ES 3.0 does not support interface blocks for shader inputs or + * outputs. + * + * And from GLSL ES 3.0, chapter 4.6.1 The invariant qualifier, page 52. + * + * Only variables output from a shader can be candidates for + * invariance. This includes user-defined output variables and the + * built-in output variables. As only outputs can be declared as + * invariant, an invariant output from one shader stage will + * still match an input of a subsequent stage without the input being + * declared as invariant. + * + * From GLSL ES 1.0, chapter 4.6.1 The invariant qualifier, page 37. + * + * Only the following variables may be declared as invariant: + * * Built-in special variables output from the vertex shader + * * Varying variables output from the vertex shader + * * Built-in special variables input to the fragment shader + * * Varying variables input to the fragment shader + * * Built-in special variables output from the fragment shader. In addition to Matt's comments about the comment... I don't think there's any reason to mention GLSL ES 1.0. There are no interface blocks in GLSL ES 1.0, and this is inside processing an interface block. With this and Matt's suggestions applied, this patch is Reviewed-by: Ian Romanick ian.d.roman...@intel.com + * + * From GLSL 4.40 and GLSL 1.50, section Interface Blocks: + * + * If no optional qualifier is used in a member-declaration, the + * qualification of the member includes all in, out, patch, uniform, + * or buffer as determined by interface-qualifier. If optional + * qualifiers are used, they can include interpolation qualifiers, + * auxiliary storage qualifiers, and storage qualifiers and they must + * declare an input, output, or uniform member consistent with the + * interface qualifier of the block + */ + if (qualifier.flags.q.invariant) +_mesa_glsl_error(@1, state, invariant qualifiers cannot be used with interface blocks members); } $$ = block; ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org
Re: [Mesa-dev] [PATCH 10/32] i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().
On Fri, Feb 6, 2015 at 4:01 PM, Francisco Jerez curroje...@riseup.net wrote: Hey Matt, Matt Turner matts...@gmail.com writes: On Fri, Feb 6, 2015 at 6:42 AM, Francisco Jerez curroje...@riseup.net wrote: MRFs cannot be read from anyway so they cannot possibly be a valid source of LOAD_PAYLOAD. --- The function only seems to test inst-dst.file == MRF. I don't see any code for handling MRF sources. What am I missing? That test is for handling MRF sources -- More precisely, it's collecting the writemask and half flags for MRF writes, which can only possibly be useful if we're going to use them later on to read something out of an MRF into a payload, which we shouldn't be doing in the first place. Aside from simplifying the function somewhat, that allows us to drop the 16 register gap reserved for MRFs at register offset zero, what will allow us to drop the vgrf_to_reg[] offset calculation completely (also in split_virtual_grfs()) in a future patch (not sent for review yet). No, we do read from MRF's sort-of... Send messages have an implicit read from an MRF. This was written precicely so that we could use LOAD_PAYLOAD to build MRF payloads. We do on pre-GEN6. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 3/9] glsl: Create a _mesa_shader_stage_to_abbrev() function.
On 02/19/2015 11:43 AM, Ian Romanick wrote:
On 02/18/2015 09:00 PM, Kenneth Graunke wrote:
This is similar to _mesa_shader_stage_to_string(), but returns VS
instead of vertex.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/glsl/glsl_parser_extras.cpp | 17 +
src/glsl/glsl_parser_extras.h | 3 +++
2 files changed, 20 insertions(+)
diff --git a/src/glsl/glsl_parser_extras.cpp
b/src/glsl/glsl_parser_extras.cpp
index ccdf031..0334e4a 100644
--- a/src/glsl/glsl_parser_extras.cpp
+++ b/src/glsl/glsl_parser_extras.cpp
@@ -376,6 +376,23 @@ _mesa_shader_stage_to_string(unsigned stage)
return unknown;
}
+/**
+ * Translate a gl_shader_stage to a shader stage abbreviation (VS, GS, FS)
+ * for debug printouts and error messages.
+ */
+const char *
+_mesa_shader_stage_to_abbrev(unsigned stage)
+{
+ switch (stage) {
+ case MESA_SHADER_VERTEX: return VS;
+ case MESA_SHADER_FRAGMENT: return FS;
+ case MESA_SHADER_GEOMETRY: return GS;
The next patch has some compute bits, should this also do compute?
+ }
+
+ assert(!Should not get here.);
+ return unknown;
unreachable(Bad shader stage.);
With that fixed, this patch is
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Either way, the rest of the series is
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
+}
+
/* This helper function will append the given message to the shader's
info log and report it via GL_ARB_debug_output. Per that extension,
'type' is one of the enum values classifying the message, and
diff --git a/src/glsl/glsl_parser_extras.h b/src/glsl/glsl_parser_extras.h
index 843fdae..6861fac 100644
--- a/src/glsl/glsl_parser_extras.h
+++ b/src/glsl/glsl_parser_extras.h
@@ -576,6 +576,9 @@ extern C {
extern const char *
_mesa_shader_stage_to_string(unsigned stage);
+extern const char *
+_mesa_shader_stage_to_abbrev(unsigned stage);
+
extern int glcpp_preprocess(void *ctx, const char **shader, char **info_log,
const struct gl_extensions *extensions, struct
gl_context *gl_ctx);
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Re: [Mesa-dev] [PATCH 10/32] i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().
Jason Ekstrand ja...@jlekstrand.net writes: On Fri, Feb 6, 2015 at 4:01 PM, Francisco Jerez curroje...@riseup.net wrote: Hey Matt, Matt Turner matts...@gmail.com writes: On Fri, Feb 6, 2015 at 6:42 AM, Francisco Jerez curroje...@riseup.net wrote: MRFs cannot be read from anyway so they cannot possibly be a valid source of LOAD_PAYLOAD. --- The function only seems to test inst-dst.file == MRF. I don't see any code for handling MRF sources. What am I missing? That test is for handling MRF sources -- More precisely, it's collecting the writemask and half flags for MRF writes, which can only possibly be useful if we're going to use them later on to read something out of an MRF into a payload, which we shouldn't be doing in the first place. Aside from simplifying the function somewhat, that allows us to drop the 16 register gap reserved for MRFs at register offset zero, what will allow us to drop the vgrf_to_reg[] offset calculation completely (also in split_virtual_grfs()) in a future patch (not sent for review yet). No, we do read from MRF's sort-of... Send messages have an implicit read from an MRF. Heh, and that's pretty much the only way you read from it. This was written precicely so that we could use LOAD_PAYLOAD to build MRF payloads. We do on pre-GEN6. I'm aware, but you don't need any of this meta-data to LOAD_PAYLOAD *into* an MRF, and LOAD_PAYLOAD with an MRF as source should be illegal anyway. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev pgpfF5PKyva7v.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] st/mesa: add GSL_TYPE_DOUBLE, new ir_unop_* switch cases
To silence compiler warnings about unhandled switch cases. v2: move GSL_TYPE_DOUBLE case to the Invalid type in type_size section, per Ilia. --- src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 12 1 file changed, 12 insertions(+) diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index 3dac004..035152a 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -1004,6 +1004,7 @@ type_size(const struct glsl_type *type) case GLSL_TYPE_INTERFACE: case GLSL_TYPE_VOID: case GLSL_TYPE_ERROR: + case GLSL_TYPE_DOUBLE: assert(!Invalid type in type_size); break; } @@ -2025,6 +2026,17 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir) case ir_binop_ldexp: case ir_binop_carry: case ir_binop_borrow: + case ir_unop_d2f: + case ir_unop_f2d: + case ir_unop_d2i: + case ir_unop_i2d: + case ir_unop_d2u: + case ir_unop_u2d: + case ir_unop_d2b: + case ir_unop_pack_double_2x32: + case ir_unop_unpack_double_2x32: + case ir_unop_frexp_sig: + case ir_unop_frexp_exp: /* This operation is not supported, or should have already been handled. */ assert(!Invalid ir opcode in glsl_to_tgsi_visitor::visit()); -- 1.9.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] nir: add missing GLSL_TYPE_DOUBLE case in type_size()
To silence compiler warning about unhandled switch case. v2: move GLSL_TYPE_DOUBLE to the not reached section, per Ilia. --- src/glsl/nir/nir_lower_io.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/glsl/nir/nir_lower_io.c b/src/glsl/nir/nir_lower_io.c index ddbc249..207f8da 100644 --- a/src/glsl/nir/nir_lower_io.c +++ b/src/glsl/nir/nir_lower_io.c @@ -69,6 +69,7 @@ type_size(const struct glsl_type *type) return 0; case GLSL_TYPE_VOID: case GLSL_TYPE_ERROR: + case GLSL_TYPE_DOUBLE: unreachable(not reached); } -- 1.9.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] nir: add missing GLSL_TYPE_DOUBLE case in type_size()
Series is Reviewed-by: Ilia Mirkin imir...@alum.mit.edu On Thu, Feb 19, 2015 at 3:51 PM, Brian Paul bri...@vmware.com wrote: To silence compiler warning about unhandled switch case. v2: move GLSL_TYPE_DOUBLE to the not reached section, per Ilia. --- src/glsl/nir/nir_lower_io.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/glsl/nir/nir_lower_io.c b/src/glsl/nir/nir_lower_io.c index ddbc249..207f8da 100644 --- a/src/glsl/nir/nir_lower_io.c +++ b/src/glsl/nir/nir_lower_io.c @@ -69,6 +69,7 @@ type_size(const struct glsl_type *type) return 0; case GLSL_TYPE_VOID: case GLSL_TYPE_ERROR: + case GLSL_TYPE_DOUBLE: unreachable(not reached); } -- 1.9.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 10/32] i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().
On Thu, Feb 19, 2015 at 12:13 PM, Francisco Jerez curroje...@riseup.net wrote: Jason Ekstrand ja...@jlekstrand.net writes: On Fri, Feb 6, 2015 at 4:01 PM, Francisco Jerez curroje...@riseup.net wrote: Hey Matt, Matt Turner matts...@gmail.com writes: On Fri, Feb 6, 2015 at 6:42 AM, Francisco Jerez curroje...@riseup.net wrote: MRFs cannot be read from anyway so they cannot possibly be a valid source of LOAD_PAYLOAD. --- The function only seems to test inst-dst.file == MRF. I don't see any code for handling MRF sources. What am I missing? That test is for handling MRF sources -- More precisely, it's collecting the writemask and half flags for MRF writes, which can only possibly be useful if we're going to use them later on to read something out of an MRF into a payload, which we shouldn't be doing in the first place. Aside from simplifying the function somewhat, that allows us to drop the 16 register gap reserved for MRFs at register offset zero, what will allow us to drop the vgrf_to_reg[] offset calculation completely (also in split_virtual_grfs()) in a future patch (not sent for review yet). No, we do read from MRF's sort-of... Send messages have an implicit read from an MRF. Heh, and that's pretty much the only way you read from it. This was written precicely so that we could use LOAD_PAYLOAD to build MRF payloads. We do on pre-GEN6. I'm aware, but you don't need any of this meta-data to LOAD_PAYLOAD *into* an MRF, and LOAD_PAYLOAD with an MRF as source should be illegal anyway. And no one is using it that way. All of the metadata checks you are deleting are checks on the *destination*. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radeonsi: don't use SQC_CACHES to flush ICACHE and KCACHE on SI
From: Marek Olšák marek.ol...@amd.com
This reverts 73c2b0d18c51459697d8ec194ecfc4438c98c139.
It doesn't seem to be reliable. It's probably missing a wait packet or
something, because it's just a register write and doesn't wait for anything.
SURFACE_SYNC at least seems to wait until the flush is done. Just guessing.
Let's not complicate things and revert this.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88561
Cc: 10.5 mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/radeonsi/si_state_draw.c | 29 +++-
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 128ea04..511bea2 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -367,24 +367,21 @@ void si_emit_cache_flush(struct r600_common_context
*sctx, struct r600_atom *ato
{
struct radeon_winsys_cs *cs = sctx-rings.gfx.cs;
uint32_t cp_coher_cntl = 0;
- uint32_t sqc_caches = 0;
uint32_t compute =
PKT3_SHADER_TYPE_S(!!(sctx-flags SI_CONTEXT_FLAG_COMPUTE));
/* SI has a bug that it always flushes ICACHE and KCACHE if either
-* bit is set. An alternative way is to write SQC_CACHES. */
- if (sctx-chip_class == SI
- sctx-flags BOTH_ICACHE_KCACHE
- (sctx-flags BOTH_ICACHE_KCACHE) != BOTH_ICACHE_KCACHE) {
- sqc_caches =
- S_008C08_INST_INVALIDATE(!!(sctx-flags
SI_CONTEXT_INV_ICACHE)) |
- S_008C08_DATA_INVALIDATE(!!(sctx-flags
SI_CONTEXT_INV_KCACHE));
- } else {
- if (sctx-flags SI_CONTEXT_INV_ICACHE)
- cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
- if (sctx-flags SI_CONTEXT_INV_KCACHE)
- cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
- }
+* bit is set. An alternative way is to write SQC_CACHES, but that
+* doesn't seem to work reliably. Since the bug doesn't affect
+* correctness (it only does more work than necessary) and
+* the performance impact is likely negligible, there is no plan
+* to fix it.
+*/
+
+ if (sctx-flags SI_CONTEXT_INV_ICACHE)
+ cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
+ if (sctx-flags SI_CONTEXT_INV_KCACHE)
+ cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
if (sctx-flags SI_CONTEXT_INV_TC_L1)
cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
@@ -451,10 +448,6 @@ void si_emit_cache_flush(struct r600_common_context *sctx,
struct r600_atom *ato
* It looks like SURFACE_SYNC flushes caches immediately and doesn't
* wait for any engines. This should be last.
*/
- if (sqc_caches) {
- r600_write_config_reg(cs, R_008C08_SQC_CACHES, sqc_caches);
- cs-buf[cs-cdw-3] |= compute; /* set the compute bit in the
header */
- }
if (cp_coher_cntl) {
if (sctx-chip_class = CIK) {
radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) | compute);
--
2.1.0
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Re: [Mesa-dev] [PATCH 2/2] i965/skl: Layout a 1D miptree horizontally
Ian Romanick i...@freedesktop.org writes: There aren't any compressed formats that support 1D textures, so I don't think this can occur. Does the bspec say anything about compressed 1D textures? Ah yes, you're right. I just copied it from brw_miptree_layout_2d without really thinking it through. The SKL bspec explicitly states that compressed formats can't be used with SURFTYPE_1D. I'll remove and send a v2 along with the patches to fix 3D textures too. Thanks for the review. - Neil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [Mesa-announce] Mesa 10.3 release candidate 1
Am Freitag, den 07.11.2014, 01:19 -0800 schrieb Matt Turner: On Fri, Nov 7, 2014 at 1:07 AM, Thierry Vignaud thierry.vign...@gmail.com wrote: On 5 November 2014 04:44, Matt Turner matts...@gmail.com wrote: I tried to reproduce this today and couldn't. (...) Thanks. Maybe you could give a little more information, like an error message or something? Same error as Thierry reported in this thread in August: Unfortunately Thierry's was from a re-run of make, so it wasn't useful. No It wasn't a re-run! It was a clean build in our build system with make -jXX with XX auto set to the number of cores and is always reproducable given enough cores Oh, weird. I've gone over this all and can't spot the problem. The dependencies look fine. I tried automake-1.13 and 1.14, and make-3.82 and 4.0. Maybe I'll have more luck on a 40 core system. As already explained, in order to be able to reproduce, you must either have a large system or force make -j to a high value (eg: -j24) Did you see the rest of the thread where I said I couldn't reproduce on a 40 core system? Perhaps someone who can reproduce could try to take a look? Ok, here is what happens: This failure is only reproducible with the following config options: --disable-shared-glapi --disable-gles1 --disable-gles2 Which makes it pretty obvious what is to be blamed here. With those options set no installable libraries will be build below src/mapi, the only target is a static glapi.la. As lib_LTLIBRARIES is empty in that case the install-mesa-links target has no dependencies and gets executed immediately. This fails as it races with the compilation to create the .libs dir. As the install-mesa-links target works perfectly fine with an empty lib_LTLIBRARIES the fix is simply to not depends on the .libs directory for the state file of this target. A patch is on the list. Regards, Lucas -- Pengutronix e.K. | Lucas Stach | Industrial Linux Solutions | http://www.pengutronix.de/ | ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] install-lib-links: don't depend on .libs directory
This snippet can be included in Makefiles that may, depending on the project configuration, not actually build any installable libraries. In that case we don't have anything to depend on and this part of the makefile may be executed before the .libs directory is created, so do not depend on it being there. Signed-off-by: Lucas Stach l.st...@pengutronix.de Cc: 10.3 10.4 mesa-sta...@lists.freedesktop.org --- install-lib-links.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/install-lib-links.mk b/install-lib-links.mk index 6976ca4911ab..3545b268ebd1 100644 --- a/install-lib-links.mk +++ b/install-lib-links.mk @@ -3,9 +3,9 @@ if BUILD_SHARED if HAVE_COMPAT_SYMLINKS -all-local : .libs/install-mesa-links +all-local : .install-mesa-links -.libs/install-mesa-links : $(lib_LTLIBRARIES) +.install-mesa-links : $(lib_LTLIBRARIES) $(AM_V_GEN)$(MKDIR_P) $(top_builddir)/$(LIB_DIR); \ for f in $(join $(addsuffix .libs/,$(dir $(lib_LTLIBRARIES))),$(notdir $(lib_LTLIBRARIES:%.la=%.$(LIB_EXT)*))); do \ if test -h .libs/$$f; then \ -- 2.1.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v4] Fixing an x86 FPU bug.
Looks better, just a bunch of nit-picks...
First, I think the summary/subject line can be improved. How about
mesa: use fi_type in vertex attribute code
On 02/18/2015 10:00 AM, marius.pre...@intel.com wrote:
From: Marius Predut marius.pre...@intel.com
On 32-bit, for floating point operations is used x86 FPU registers
instead SSE, reason for when reinterprets an integer as a float
result is unexpected (modify floats when they are written to memory).
How about this:
For 32-bit builds, floating point operations use x86 FPU registers,
not SSE registers. If we're actually storing an integer in a float
variable, the value might get modified when written to memory. This
patch changes the VBO code to use the fi_type (float/int union) to
store/copy vertex attributes.
The patch was checked with and without -O3 compiler flag.
Also, it add performace improvement because treat GLfloats as GLint.
On x86 systems, moving a float as a int (thereby using integer registers
instead of FP registers) is a performance win.
Maybe:
Also, this can improve performance on x86 because moving floats with
integer registers instead of FP registers is faster.
Neil Roberts review:
-include changes on all places that are storing attribute values.
Brian Paul review:
- use fi_type type instead gl_constant_value
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82668
Signed-off-by: Marius Predut marius.pre...@intel.com
---
src/mesa/main/context.c |3 ++-
src/mesa/main/macros.h| 32
src/mesa/vbo/vbo_attrib_tmp.h | 20
src/mesa/vbo/vbo_context.h| 14 +++---
src/mesa/vbo/vbo_exec.h | 11 ++-
src/mesa/vbo/vbo_exec_api.c | 35 +--
src/mesa/vbo/vbo_exec_draw.c |6 +++---
src/mesa/vbo/vbo_exec_eval.c | 22 +++---
src/mesa/vbo/vbo_save.h | 16
src/mesa/vbo/vbo_save_api.c | 34 +-
src/mesa/vbo/vbo_save_draw.c |4 ++--
11 files changed, 105 insertions(+), 92 deletions(-)
diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index 63d30a2..f0597e2 100644
--- a/src/mesa/main/context.c
+++ b/src/mesa/main/context.c
@@ -134,6 +134,7 @@
#include math/m_matrix.h
#include main/dispatch.h /* for _gloffset_COUNT */
#include uniforms.h
+#include macros.h
#ifdef USE_SPARC_ASM
#include sparc/sparc.h
@@ -656,7 +657,7 @@ _mesa_init_constants(struct gl_constants *consts, gl_api
api)
consts-MaxSamples = 0;
/* GLSL default if NativeIntegers == FALSE */
- consts-UniformBooleanTrue = FLT_AS_UINT(1.0f);
+ consts-UniformBooleanTrue = FLOAT_AS_UNION(1.0f).u;
/* GL_ARB_sync */
consts-MaxServerWaitTimeout = 0x1fff7fffULL;
diff --git a/src/mesa/main/macros.h b/src/mesa/main/macros.h
index 2d59c6f..9ca3460 100644
--- a/src/mesa/main/macros.h
+++ b/src/mesa/main/macros.h
@@ -170,25 +170,25 @@ extern GLfloat _mesa_ubyte_to_float_color_tab[256];
ub = ((GLubyte) F_TO_I((f) * 255.0F))
#endif
-static inline GLfloat INT_AS_FLT(GLint i)
+static fi_type UINT_AS_UNION(GLuint u)
{
fi_type tmp;
- tmp.i = i;
- return tmp.f;
+ tmp.u = u;
+ return tmp;
}
-static inline GLfloat UINT_AS_FLT(GLuint u)
+static inline fi_type INT_AS_UNION(GLint i)
{
fi_type tmp;
- tmp.u = u;
- return tmp.f;
+ tmp.i = i;
+ return tmp;
}
-static inline unsigned FLT_AS_UINT(float f)
+static inline fi_type FLOAT_AS_UNION(GLfloat f)
{
fi_type tmp;
tmp.f = f;
- return tmp.u;
+ return tmp;
}
/**
@@ -620,24 +620,24 @@ do { \
* The default values are chosen based on \p type.
*/
static inline void
-COPY_CLEAN_4V_TYPE_AS_FLOAT(GLfloat dst[4], int sz, const GLfloat src[4],
+COPY_CLEAN_4V_TYPE_AS_UNION(fi_type dst[4], int sz, const fi_type src[4],
GLenum type)
{
switch (type) {
case GL_FLOAT:
- ASSIGN_4V(dst, 0, 0, 0, 1);
+ ASSIGN_4V(dst, FLOAT_AS_UNION(0), FLOAT_AS_UNION(0), FLOAT_AS_UNION(0),
FLOAT_AS_UNION(1));
Wrap to = 78 columns.
break;
case GL_INT:
- ASSIGN_4V(dst, INT_AS_FLT(0), INT_AS_FLT(0),
- INT_AS_FLT(0), INT_AS_FLT(1));
+ ASSIGN_4V(dst, INT_AS_UNION(0), INT_AS_UNION(0),
+INT_AS_UNION(0), INT_AS_UNION(1));
break;
case GL_UNSIGNED_INT:
- ASSIGN_4V(dst, UINT_AS_FLT(0), UINT_AS_FLT(0),
- UINT_AS_FLT(0), UINT_AS_FLT(1));
+ ASSIGN_4V(dst, UINT_AS_UNION(0), UINT_AS_UNION(0),
+UINT_AS_UNION(0), UINT_AS_UNION(1));
break;
default:
- ASSIGN_4V(dst, 0.0f, 0.0f, 0.0f, 1.0f); /* silence warnings */
- ASSERT(!Unexpected type in COPY_CLEAN_4V_TYPE_AS_FLOAT macro);
+ ASSIGN_4V(dst, FLOAT_AS_UNION(0), FLOAT_AS_UNION(0), FLOAT_AS_UNION(0),
FLOAT_AS_UNION(1)); /* silence warnings */
Line wrap.
+
Re: [Mesa-dev] [PATCH 2/2] st/mesa: add GSL_TYPE_DOUBLE, new ir_unop_* switch cases
On Thu, Feb 19, 2015 at 8:27 AM, Brian Paul bri...@vmware.com wrote:
To silence compiler warnings about unhandled switch cases.
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 12
1 file changed, 12 insertions(+)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 3dac004..9969fac 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -974,6 +974,7 @@ type_size(const struct glsl_type *type)
case GLSL_TYPE_UINT:
case GLSL_TYPE_INT:
case GLSL_TYPE_FLOAT:
+ case GLSL_TYPE_DOUBLE:
case GLSL_TYPE_BOOL:
if (type-is_matrix()) {
return type-matrix_columns;
@@ -2025,6 +2026,17 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir)
case ir_binop_ldexp:
case ir_binop_carry:
case ir_binop_borrow:
+ case ir_unop_d2f:
+ case ir_unop_f2d:
+ case ir_unop_d2i:
+ case ir_unop_i2d:
+ case ir_unop_d2u:
+ case ir_unop_u2d:
+ case ir_unop_d2b:
+ case ir_unop_pack_double_2x32:
+ case ir_unop_unpack_double_2x32:
+ case ir_unop_frexp_sig:
+ case ir_unop_frexp_exp:
/* This operation is not supported, or should have already been
handled.
*/
assert(!Invalid ir opcode in glsl_to_tgsi_visitor::visit());
--
1.9.1
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Both patches are:
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
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Re: [Mesa-dev] [PATCH 9/9] i965/vec4: Print VS or GS when compiles fail, not vec4.
On Wed, Feb 18, 2015 at 9:37 PM, Jason Ekstrand ja...@jlekstrand.net wrote: Series is Reviewed-by: Jason Ekstrand jason.ekstr...@intel.com Me too: Reviewed-by: Kristian Høgsberg k...@bitplanet.net On Feb 18, 2015 9:00 PM, Kenneth Graunke kenn...@whitecape.org wrote: This is now trivial to do right. Signed-off-by: Kenneth Graunke kenn...@whitecape.org --- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index 4f66b62..562fc30 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp @@ -3656,7 +3656,7 @@ vec4_visitor::fail(const char *format, ...) va_start(va, format); msg = ralloc_vasprintf(mem_ctx, format, va); va_end(va); - msg = ralloc_asprintf(mem_ctx, vec4 compile failed: %s\n, msg); + msg = ralloc_asprintf(mem_ctx, %s compile failed: %s\n, stage_abbrev, msg); this-fail_msg = msg; -- 2.2.2 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] glsl: Use the without_array predicate
On Thu, Feb 19, 2015 at 11:57 AM, Timothy Arceri t_arc...@yahoo.com.au wrote:
---
src/glsl/ir.h | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index a0f48b2..9c60b07 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -450,11 +450,8 @@ public:
*/
inline bool is_interface_instance() const
{
- const glsl_type *const t = this-type;
-
- return (t == this-interface_type)
- || (t-is_array() t-fields.array == this-interface_type);
-}
+ return (this-type-without_array() == this-interface_type);
Remove the superfluous parentheses, and
Reviewed-by: Matt Turner matts...@gmail.com
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Re: [Mesa-dev] [PATCH 10/32] i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().
Jason Ekstrand ja...@jlekstrand.net writes: On Thu, Feb 19, 2015 at 12:13 PM, Francisco Jerez curroje...@riseup.net wrote: Jason Ekstrand ja...@jlekstrand.net writes: On Fri, Feb 6, 2015 at 4:01 PM, Francisco Jerez curroje...@riseup.net wrote: Hey Matt, Matt Turner matts...@gmail.com writes: On Fri, Feb 6, 2015 at 6:42 AM, Francisco Jerez curroje...@riseup.net wrote: MRFs cannot be read from anyway so they cannot possibly be a valid source of LOAD_PAYLOAD. --- The function only seems to test inst-dst.file == MRF. I don't see any code for handling MRF sources. What am I missing? That test is for handling MRF sources -- More precisely, it's collecting the writemask and half flags for MRF writes, which can only possibly be useful if we're going to use them later on to read something out of an MRF into a payload, which we shouldn't be doing in the first place. Aside from simplifying the function somewhat, that allows us to drop the 16 register gap reserved for MRFs at register offset zero, what will allow us to drop the vgrf_to_reg[] offset calculation completely (also in split_virtual_grfs()) in a future patch (not sent for review yet). No, we do read from MRF's sort-of... Send messages have an implicit read from an MRF. Heh, and that's pretty much the only way you read from it. This was written precicely so that we could use LOAD_PAYLOAD to build MRF payloads. We do on pre-GEN6. I'm aware, but you don't need any of this meta-data to LOAD_PAYLOAD *into* an MRF, and LOAD_PAYLOAD with an MRF as source should be illegal anyway. And no one is using it that way. All of the metadata checks you are deleting are checks on the *destination*. Didn't you write this code yourself? The only use for the collected metadata is initializing the instruction flags of the MOVs subsequent LOAD_PAYLOAD instructions are lowered to, based on the metadata already collected for its source registers, which can never be MRFs, so the metadata you collect from MRF writes is never actually used. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev pgpznbosO3BD6.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] nir: add missing GLSL_TYPE_DOUBLE case in type_size()
Reviewed-by: Jason Ekstrand jason.ekstr...@intel.com On Thu, Feb 19, 2015 at 12:51 PM, Brian Paul bri...@vmware.com wrote: To silence compiler warning about unhandled switch case. v2: move GLSL_TYPE_DOUBLE to the not reached section, per Ilia. --- src/glsl/nir/nir_lower_io.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/glsl/nir/nir_lower_io.c b/src/glsl/nir/nir_lower_io.c index ddbc249..207f8da 100644 --- a/src/glsl/nir/nir_lower_io.c +++ b/src/glsl/nir/nir_lower_io.c @@ -69,6 +69,7 @@ type_size(const struct glsl_type *type) return 0; case GLSL_TYPE_VOID: case GLSL_TYPE_ERROR: + case GLSL_TYPE_DOUBLE: unreachable(not reached); } -- 1.9.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] st/mesa: fix sampler view reference counting bug in glDraw/CopyPixels
On Wed, Feb 18, 2015 at 1:20 PM, Brian Paul bri...@vmware.com wrote:
Use pipe_sampler_view_reference() instead of ordinary assignment.
Also add a new sanity check assertion.
Fixes piglit gl-1.0-drawpixels-color-index test crash. But note
that the test still fails.
Fails on nvc0 as well, for the record.
Cc: 10.4, 10.5 mesa-sta...@lists.freedesktop.org
---
src/mesa/state_tracker/st_cb_drawpixels.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c
b/src/mesa/state_tracker/st_cb_drawpixels.c
index 939fc20..3d13b5c 100644
--- a/src/mesa/state_tracker/st_cb_drawpixels.c
+++ b/src/mesa/state_tracker/st_cb_drawpixels.c
@@ -1154,8 +1154,10 @@ st_DrawPixels(struct gl_context *ctx, GLint x, GLint y,
color = NULL;
if (st-pixel_xfer.pixelmap_enabled) {
- sv[1] = st-pixel_xfer.pixelmap_sampler_view;
- num_sampler_view++;
+ sv[1] = NULL;
+ pipe_sampler_view_reference(sv[1],
+ st-pixel_xfer.pixelmap_sampler_view);
I would *much* prefer a = {NULL} when sv is declared instead of
awkwardly before the reference (both here and in st_CopyPixels).
With that changed, Reviewed-by: Ilia Mirkin imir...@alum.mit.edu
+ num_sampler_view++;
}
}
@@ -1176,7 +1178,8 @@ st_DrawPixels(struct gl_context *ctx, GLint x, GLint y,
if (write_stencil) {
enum pipe_format stencil_format =
util_format_stencil_only(pt-format);
-
+ /* we should not be doing pixel map/transfer (see above) */
+ assert(num_sampler_view == 1);
sv[1] = st_create_texture_sampler_view_format(st-pipe, pt,
stencil_format);
num_sampler_view++;
@@ -1516,7 +1519,9 @@ st_CopyPixels(struct gl_context *ctx, GLint srcx, GLint
srcy,
driver_vp = make_passthrough_vertex_shader(st, GL_FALSE);
if (st-pixel_xfer.pixelmap_enabled) {
- sv[1] = st-pixel_xfer.pixelmap_sampler_view;
+ sv[1] = NULL;
+ pipe_sampler_view_reference(sv[1],
+ st-pixel_xfer.pixelmap_sampler_view);
num_sampler_view++;
}
}
--
1.9.1
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Re: [Mesa-dev] [PATCH] st/mesa: fix sampler view reference counting bug in glDraw/CopyPixels
Ping.
On 02/18/2015 11:20 AM, Brian Paul wrote:
Use pipe_sampler_view_reference() instead of ordinary assignment.
Also add a new sanity check assertion.
Fixes piglit gl-1.0-drawpixels-color-index test crash. But note
that the test still fails.
Cc: 10.4, 10.5 mesa-sta...@lists.freedesktop.org
---
src/mesa/state_tracker/st_cb_drawpixels.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c
b/src/mesa/state_tracker/st_cb_drawpixels.c
index 939fc20..3d13b5c 100644
--- a/src/mesa/state_tracker/st_cb_drawpixels.c
+++ b/src/mesa/state_tracker/st_cb_drawpixels.c
@@ -1154,8 +1154,10 @@ st_DrawPixels(struct gl_context *ctx, GLint x, GLint y,
color = NULL;
if (st-pixel_xfer.pixelmap_enabled) {
- sv[1] = st-pixel_xfer.pixelmap_sampler_view;
- num_sampler_view++;
+ sv[1] = NULL;
+ pipe_sampler_view_reference(sv[1],
+ st-pixel_xfer.pixelmap_sampler_view);
+ num_sampler_view++;
}
}
@@ -1176,7 +1178,8 @@ st_DrawPixels(struct gl_context *ctx, GLint x, GLint y,
if (write_stencil) {
enum pipe_format stencil_format =
util_format_stencil_only(pt-format);
-
+ /* we should not be doing pixel map/transfer (see above) */
+ assert(num_sampler_view == 1);
sv[1] = st_create_texture_sampler_view_format(st-pipe, pt,
stencil_format);
num_sampler_view++;
@@ -1516,7 +1519,9 @@ st_CopyPixels(struct gl_context *ctx, GLint srcx, GLint
srcy,
driver_vp = make_passthrough_vertex_shader(st, GL_FALSE);
if (st-pixel_xfer.pixelmap_enabled) {
- sv[1] = st-pixel_xfer.pixelmap_sampler_view;
+ sv[1] = NULL;
+ pipe_sampler_view_reference(sv[1],
+ st-pixel_xfer.pixelmap_sampler_view);
num_sampler_view++;
}
}
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[Mesa-dev] [PATCH] gallium: add double opcodes and TGSI execution (v4.1)
This patch adds support for a set of double opcodes
to TGSI. It is an update of work done originally
by Michal Krol on the gallium-double-opcodes branch.
The opcodes have a hint where they came from in the
header file.
v2: add unsigned/int - double
v2.1: update docs.
v3: add DRSQ (Glenn), fix review comments (Glenn).
v4: drop DDIV
v4.1: cleanups, fix some docs bugs, (Ilia)
rework store_dest and fetch_source fns. (Ilia)
This is based on code by Michael Krol mic...@vmware.com
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/auxiliary/tgsi/tgsi_exec.c | 765 -
src/gallium/auxiliary/tgsi/tgsi_info.c | 24 +-
src/gallium/docs/source/tgsi.rst | 92 +++-
src/gallium/include/pipe/p_shader_tokens.h | 26 +-
4 files changed, 877 insertions(+), 30 deletions(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c
b/src/gallium/auxiliary/tgsi/tgsi_exec.c
index 834568b..1deca82 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
@@ -72,6 +72,16 @@
#define TILE_BOTTOM_LEFT 2
#define TILE_BOTTOM_RIGHT 3
+union tgsi_double_channel {
+ double d[TGSI_QUAD_SIZE];
+ unsigned u[TGSI_QUAD_SIZE][2];
+};
+
+struct tgsi_double_vector {
+ union tgsi_double_channel xy;
+ union tgsi_double_channel zw;
+};
+
static void
micro_abs(union tgsi_exec_channel *dst,
const union tgsi_exec_channel *src)
@@ -147,6 +157,55 @@ micro_cos(union tgsi_exec_channel *dst,
}
static void
+micro_d2f(union tgsi_exec_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst-f[0] = (float)src-d[0];
+ dst-f[1] = (float)src-d[1];
+ dst-f[2] = (float)src-d[2];
+ dst-f[3] = (float)src-d[3];
+}
+
+static void
+micro_d2i(union tgsi_exec_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst-i[0] = (int)src-d[0];
+ dst-i[1] = (int)src-d[1];
+ dst-i[2] = (int)src-d[2];
+ dst-i[3] = (int)src-d[3];
+}
+
+static void
+micro_d2u(union tgsi_exec_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst-u[0] = (unsigned)src-d[0];
+ dst-u[1] = (unsigned)src-d[1];
+ dst-u[2] = (unsigned)src-d[2];
+ dst-u[3] = (unsigned)src-d[3];
+}
+static void
+micro_dabs(union tgsi_double_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst-d[0] = src-d[0] = 0.0 ? src-d[0] : -src-d[0];
+ dst-d[1] = src-d[1] = 0.0 ? src-d[1] : -src-d[1];
+ dst-d[2] = src-d[2] = 0.0 ? src-d[2] : -src-d[2];
+ dst-d[3] = src-d[3] = 0.0 ? src-d[3] : -src-d[3];
+}
+
+static void
+micro_dadd(union tgsi_double_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst-d[0] = src[0].d[0] + src[1].d[0];
+ dst-d[1] = src[0].d[1] + src[1].d[1];
+ dst-d[2] = src[0].d[2] + src[1].d[2];
+ dst-d[3] = src[0].d[3] + src[1].d[3];
+}
+
+static void
micro_ddx(union tgsi_exec_channel *dst,
const union tgsi_exec_channel *src)
{
@@ -167,6 +226,158 @@ micro_ddy(union tgsi_exec_channel *dst,
}
static void
+micro_dmul(union tgsi_double_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst-d[0] = src[0].d[0] * src[1].d[0];
+ dst-d[1] = src[0].d[1] * src[1].d[1];
+ dst-d[2] = src[0].d[2] * src[1].d[2];
+ dst-d[3] = src[0].d[3] * src[1].d[3];
+}
+
+static void
+micro_dmax(union tgsi_double_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst-d[0] = src[0].d[0] src[1].d[0] ? src[0].d[0] : src[1].d[0];
+ dst-d[1] = src[0].d[1] src[1].d[1] ? src[0].d[1] : src[1].d[1];
+ dst-d[2] = src[0].d[2] src[1].d[2] ? src[0].d[2] : src[1].d[2];
+ dst-d[3] = src[0].d[3] src[1].d[3] ? src[0].d[3] : src[1].d[3];
+}
+
+static void
+micro_dmin(union tgsi_double_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst-d[0] = src[0].d[0] src[1].d[0] ? src[0].d[0] : src[1].d[0];
+ dst-d[1] = src[0].d[1] src[1].d[1] ? src[0].d[1] : src[1].d[1];
+ dst-d[2] = src[0].d[2] src[1].d[2] ? src[0].d[2] : src[1].d[2];
+ dst-d[3] = src[0].d[3] src[1].d[3] ? src[0].d[3] : src[1].d[3];
+}
+
+static void
+micro_dneg(union tgsi_double_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst-d[0] = -src-d[0];
+ dst-d[1] = -src-d[1];
+ dst-d[2] = -src-d[2];
+ dst-d[3] = -src-d[3];
+}
+
+static void
+micro_dslt(union tgsi_double_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst-u[0][0] = src[0].d[0] src[1].d[0] ? ~0U : 0U;
+ dst-u[1][0] = src[0].d[1] src[1].d[1] ? ~0U : 0U;
+ dst-u[2][0] = src[0].d[2] src[1].d[2] ? ~0U : 0U;
+ dst-u[3][0] = src[0].d[3] src[1].d[3] ? ~0U : 0U;
+}
+
+static void
+micro_dsne(union tgsi_double_channel *dst,
+ const union tgsi_double_channel *src)
+{
+ dst-u[0][0] = src[0].d[0] != src[1].d[0] ? ~0U : 0U;
+ dst-u[1][0] = src[0].d[1] != src[1].d[1] ? ~0U : 0U;
+ dst-u[2][0] = src[0].d[2] != src[1].d[2] ? ~0U : 0U;
+ dst-u[3][0] = src[0].d[3] != src[1].d[3] ? ~0U : 0U;
+}
+
+static void
+micro_dsge(union
Re: [Mesa-dev] [PATCH 10/32] i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().
On Thu, Feb 19, 2015 at 1:25 PM, Francisco Jerez curroje...@riseup.net wrote: Jason Ekstrand ja...@jlekstrand.net writes: On Thu, Feb 19, 2015 at 12:13 PM, Francisco Jerez curroje...@riseup.net wrote: Jason Ekstrand ja...@jlekstrand.net writes: On Fri, Feb 6, 2015 at 4:01 PM, Francisco Jerez curroje...@riseup.net wrote: Hey Matt, Matt Turner matts...@gmail.com writes: On Fri, Feb 6, 2015 at 6:42 AM, Francisco Jerez curroje...@riseup.net wrote: MRFs cannot be read from anyway so they cannot possibly be a valid source of LOAD_PAYLOAD. --- The function only seems to test inst-dst.file == MRF. I don't see any code for handling MRF sources. What am I missing? That test is for handling MRF sources -- More precisely, it's collecting the writemask and half flags for MRF writes, which can only possibly be useful if we're going to use them later on to read something out of an MRF into a payload, which we shouldn't be doing in the first place. Aside from simplifying the function somewhat, that allows us to drop the 16 register gap reserved for MRFs at register offset zero, what will allow us to drop the vgrf_to_reg[] offset calculation completely (also in split_virtual_grfs()) in a future patch (not sent for review yet). No, we do read from MRF's sort-of... Send messages have an implicit read from an MRF. Heh, and that's pretty much the only way you read from it. This was written precicely so that we could use LOAD_PAYLOAD to build MRF payloads. We do on pre-GEN6. I'm aware, but you don't need any of this meta-data to LOAD_PAYLOAD *into* an MRF, and LOAD_PAYLOAD with an MRF as source should be illegal anyway. And no one is using it that way. All of the metadata checks you are deleting are checks on the *destination*. Didn't you write this code yourself? The only use for the collected metadata is initializing the instruction flags of the MOVs subsequent LOAD_PAYLOAD instructions are lowered to, based on the metadata already collected for its source registers, which can never be MRFs, so the metadata you collect from MRF writes is never actually used. Right... I misred something initially. Yes, we should never be tracking MRF's as a source of a LOAD_PAYLOAD. I'll give it a better look a bit later, but it looks better. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/3] gallium: add double opcodes and TGSI execution (v3.1)
I've addressed most of these,
+ /* double modifiers handled by caller */
+ if (dtype)
+ return;
Should the below code just get moved to fetch_source? Or does it rely
on local args which makes that a pain? If it's not too hard, I think
it'd be a lot cleaner / clearer than an extra param here.
I've reworked it, for fetch_source its not so bad, for store_dest its a
bit messy as it needs to return the dst pointer but with that it isn't
that much uglier. I'll post a followup.
+
+ wmask = inst-Dst[0].Register.WriteMask;
+ if (wmask TGSI_WRITEMASK_XY) {
Please comment as to why this is written differently than the
unary/trinary cases. I assume it's for something like DSLT?
Okay added something small here.
+}
+
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c
b/src/gallium/auxiliary/tgsi/tgsi_info.c
index c90d24c..8313722 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
@@ -231,10 +231,33 @@ static const struct tgsi_opcode_info
opcode_info[TGSI_OPCODE_LAST] =
{ 1, 1, 0, 0, 0, 0, COMP, LSB, TGSI_OPCODE_LSB },
{ 1, 1, 0, 0, 0, 0, COMP, IMSB, TGSI_OPCODE_IMSB },
{ 1, 1, 0, 0, 0, 0, COMP, UMSB, TGSI_OPCODE_UMSB },
-
{ 1, 1, 0, 0, 0, 0, OTHR, INTERP_CENTROID, TGSI_OPCODE_INTERP_CENTROID
},
{ 1, 2, 0, 0, 0, 0, OTHR, INTERP_SAMPLE, TGSI_OPCODE_INTERP_SAMPLE },
{ 1, 2, 0, 0, 0, 0, OTHR, INTERP_OFFSET, TGSI_OPCODE_INTERP_OFFSET },
+ { 1, 1, 0, 0, 0, 0, COMP, F2D, TGSI_OPCODE_F2D },
I'd group these with the other COMP ones... That's why I had added the
whitespace for INTERP_*.
eh? these are in opcode order, grouping them makes no sense.
I've updated all the docs with the correct channel assignments as well.
Dave.
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Re: [Mesa-dev] [PATCH 1/9] i965/fs: Remove type parameter from emit_vs_system_value().
On Wed, Feb 18, 2015 at 9:00 PM, Kenneth Graunke kenn...@whitecape.org wrote:
Every VS system value has type D. We can always add this back if that
changes, but for now, it's extra typing.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 7 +++
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index a2e6192..9375412 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -259,7 +259,7 @@ public:
glsl_interp_qualifier interpolation_mode,
int location, bool mod_centroid,
bool mod_sample);
- fs_reg *emit_vs_system_value(enum brw_reg_type type, int location);
+ fs_reg *emit_vs_system_value(int location);
void emit_interpolation_setup_gen4();
void emit_interpolation_setup_gen6();
void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 24cc118..a2343c6 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -51,10 +51,10 @@ extern C {
fs_reg *
-fs_visitor::emit_vs_system_value(enum brw_reg_type type, int location)
+fs_visitor::emit_vs_system_value(int location)
{
fs_reg *reg = new(this-mem_ctx)
- fs_reg(ATTR, VERT_ATTRIB_MAX, type);
+ fs_reg(ATTR, VERT_ATTRIB_MAX, BRW_REGISTER_TYPE_D);
brw_vs_prog_data *vs_prog_data = (brw_vs_prog_data *) prog_data;
switch (location) {
@@ -191,8 +191,7 @@ fs_visitor::visit(ir_variable *ir)
case SYSTEM_VALUE_VERTEX_ID:
case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
case SYSTEM_VALUE_INSTANCE_ID:
- reg = emit_vs_system_value(brw_type_for_base_type(ir-type),
-ir-data.location);
+ reg = emit_vs_system_value(ir-data.location);
break;
case SYSTEM_VALUE_SAMPLE_POS:
reg = emit_samplepos_setup();
--
2.2.2
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Series is:
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
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Re: [Mesa-dev] [PATCH] gallium: add double opcodes and TGSI execution (v4.1)
On Thu, Feb 19, 2015 at 4:53 PM, Dave Airlie airl...@gmail.com wrote:
This patch adds support for a set of double opcodes
to TGSI. It is an update of work done originally
by Michal Krol on the gallium-double-opcodes branch.
The opcodes have a hint where they came from in the
header file.
v2: add unsigned/int - double
v2.1: update docs.
v3: add DRSQ (Glenn), fix review comments (Glenn).
v4: drop DDIV
v4.1: cleanups, fix some docs bugs, (Ilia)
rework store_dest and fetch_source fns. (Ilia)
This is based on code by Michael Krol mic...@vmware.com
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/auxiliary/tgsi/tgsi_exec.c | 765
-
src/gallium/auxiliary/tgsi/tgsi_info.c | 24 +-
src/gallium/docs/source/tgsi.rst | 92 +++-
src/gallium/include/pipe/p_shader_tokens.h | 26 +-
4 files changed, 877 insertions(+), 30 deletions(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c
b/src/gallium/auxiliary/tgsi/tgsi_exec.c
index 834568b..1deca82 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
@@ -2980,6 +3274,355 @@ exec_endswitch(struct tgsi_exec_machine *mach)
UPDATE_EXEC_MASK(mach);
}
+typedef void (* micro_dop)(union tgsi_double_channel *dst,
+ const union tgsi_double_channel *src);
+
+static void
+fetch_double_channel(struct tgsi_exec_machine *mach,
+ union tgsi_double_channel *chan,
+ const struct tgsi_full_src_register *reg,
+ uint chan_0,
+ uint chan_1)
+{
+ union tgsi_exec_channel src[2];
+ uint i;
+
+ fetch_source_d(mach, src[0], reg, chan_0, TGSI_EXEC_DATA_UINT);
+ fetch_source_d(mach, src[1], reg, chan_1, TGSI_EXEC_DATA_UINT);
+
+ for (i = 0; i TGSI_QUAD_SIZE; i++) {
+ chan-u[i][0] = src[0].u[i];
+ chan-u[i][1] = src[1].u[i];
+ }
+ if (reg-Register.Absolute) {
+ micro_dabs(chan, chan);
+ }
+ if (reg-Register.Negate) {
+ micro_dneg(chan, chan);
+ }
+
remove extra line.
+}
+
+static void
+store_double_channel(struct tgsi_exec_machine *mach,
+ const union tgsi_double_channel *chan,
+ const struct tgsi_full_dst_register *reg,
+ const struct tgsi_full_instruction *inst,
+ uint chan_0,
+ uint chan_1)
+{
+ union tgsi_exec_channel dst[2];
+ uint i;
+ union tgsi_double_channel temp;
+ const uint execmask = mach-ExecMask;
add a blank line here
+ switch (inst-Instruction.Saturate) {
+ case TGSI_SAT_NONE:
+ for (i = 0; i TGSI_QUAD_SIZE; i++)
+ if (execmask (1 i)) {
+dst[0].u[i] = chan-u[i][0];
+dst[1].u[i] = chan-u[i][1];
+ }
+ break;
+
+ case TGSI_SAT_ZERO_ONE:
+ for (i = 0; i TGSI_QUAD_SIZE; i++)
+ if (execmask (1 i)) {
+if (chan-d[i] 0.0f)
s/f//
+ temp.d[i] = 0.0;
+else if (chan-d[i] 1.0f)
s/f//
+ temp.d[i] = 1.0;
+else
+ temp.d[i] = chan-d[i];
+
+dst[0].u[i] = temp.u[i][0];
+dst[1].u[i] = temp.u[i][1];
+ }
+ break;
+
+ case TGSI_SAT_MINUS_PLUS_ONE:
+ for (i = 0; i TGSI_QUAD_SIZE; i++)
+ if (execmask (1 i)) {
+if (chan-d[i] -1.0)
+ temp.d[i] = -1.0;
+else if (chan-d[i] 1.0)
+ temp.d[i] = 1.0;
+else
+ temp.d[i] = chan-d[i];
+
+dst[0].u[i] = temp.u[i][0];
+dst[1].u[i] = temp.u[i][1];
+ }
+ break;
+
+ default:
+ assert( 0 );
+ }
+
+ store_dest_double(mach, dst[0], reg, inst, chan_0, TGSI_EXEC_DATA_UINT);
+ if (chan_1 != -1)
+ store_dest_double(mach, dst[1], reg, inst, chan_1,
TGSI_EXEC_DATA_UINT);
+}
[...]
+static void
+exec_dldexp(struct tgsi_exec_machine *mach,
+const struct tgsi_full_instruction *inst)
+{
+ union tgsi_double_channel src0;
+ union tgsi_exec_channel src1;
+ union tgsi_double_channel dst;
+ int wmask;
+
+ wmask = inst-Dst[0].Register.WriteMask;
+ if (wmask TGSI_WRITEMASK_XY) {
+
remove extra line
+ fetch_double_channel(mach, src0, inst-Src[0], TGSI_CHAN_X,
TGSI_CHAN_Y);
+ fetch_source(mach, src1, inst-Src[1], TGSI_CHAN_X,
TGSI_EXEC_DATA_INT);
+ micro_dldexp(dst, src0, src1);
+ store_double_channel(mach, dst, inst-Dst[0], inst, TGSI_CHAN_X,
TGSI_CHAN_Y);
+ }
+
+ if (wmask TGSI_WRITEMASK_ZW) {
+ fetch_double_channel(mach, src0, inst-Src[0], TGSI_CHAN_Z,
TGSI_CHAN_W);
+ fetch_source(mach, src1, inst-Src[1], TGSI_CHAN_Z,
TGSI_EXEC_DATA_INT);
+ micro_dldexp(dst, src0, src1);
+ store_double_channel(mach, dst, inst-Dst[0], inst, TGSI_CHAN_Z,
TGSI_CHAN_W);
+
Re: [Mesa-dev] [PATCH] st/mesa: fix sampler view reference counting bug in glDraw/CopyPixels
On 02/19/2015 02:55 PM, Ilia Mirkin wrote:
On Wed, Feb 18, 2015 at 1:20 PM, Brian Paul bri...@vmware.com wrote:
Use pipe_sampler_view_reference() instead of ordinary assignment.
Also add a new sanity check assertion.
Fixes piglit gl-1.0-drawpixels-color-index test crash. But note
that the test still fails.
Fails on nvc0 as well, for the record.
Yeah, it's a state tracker issue. I started working on a fix but it's
not high priority ATM.
Cc: 10.4, 10.5 mesa-sta...@lists.freedesktop.org
---
src/mesa/state_tracker/st_cb_drawpixels.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c
b/src/mesa/state_tracker/st_cb_drawpixels.c
index 939fc20..3d13b5c 100644
--- a/src/mesa/state_tracker/st_cb_drawpixels.c
+++ b/src/mesa/state_tracker/st_cb_drawpixels.c
@@ -1154,8 +1154,10 @@ st_DrawPixels(struct gl_context *ctx, GLint x, GLint y,
color = NULL;
if (st-pixel_xfer.pixelmap_enabled) {
- sv[1] = st-pixel_xfer.pixelmap_sampler_view;
- num_sampler_view++;
+ sv[1] = NULL;
+ pipe_sampler_view_reference(sv[1],
+ st-pixel_xfer.pixelmap_sampler_view);
I would *much* prefer a = {NULL} when sv is declared instead of
awkwardly before the reference (both here and in st_CopyPixels).
With that changed, Reviewed-by: Ilia Mirkin imir...@alum.mit.edu
Will do. Thx.
-Brian
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[Mesa-dev] [PATCH] glsl: add lowering for double divide to rcp/mul
From: Dave Airlie airl...@redhat.com
It looks like no hw does div anyways, so we should just
lower at the GLSL level.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/glsl/lower_instructions.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/glsl/lower_instructions.cpp b/src/glsl/lower_instructions.cpp
index e8a69e7..ac6715b 100644
--- a/src/glsl/lower_instructions.cpp
+++ b/src/glsl/lower_instructions.cpp
@@ -199,7 +199,7 @@ lower_instructions_visitor::sub_to_add_neg(ir_expression
*ir)
void
lower_instructions_visitor::div_to_mul_rcp(ir_expression *ir)
{
- assert(ir-operands[1]-type-is_float());
+ assert(ir-operands[1]-type-is_float() ||
ir-operands[1]-type-is_double());
/* New expression for the 1.0 / op1 */
ir_rvalue *expr;
@@ -327,7 +327,7 @@ lower_instructions_visitor::mod_to_floor(ir_expression *ir)
/* Don't generate new IR that would need to be lowered in an additional
* pass.
*/
- if (lowering(DIV_TO_MUL_RCP) ir-type-is_float())
+ if (lowering(DIV_TO_MUL_RCP) (ir-type-is_float() ||
ir-type-is_double()))
div_to_mul_rcp(div_expr);
ir_expression *const floor_expr =
@@ -1014,7 +1014,7 @@ lower_instructions_visitor::visit_leave(ir_expression *ir)
case ir_binop_div:
if (ir-operands[1]-type-is_integer() lowering(INT_DIV_TO_MUL_RCP))
int_div_to_mul_rcp(ir);
- else if (ir-operands[1]-type-is_float() lowering(DIV_TO_MUL_RCP))
+ else if ((ir-operands[1]-type-is_float() ||
ir-operands[1]-type-is_double()) lowering(DIV_TO_MUL_RCP))
div_to_mul_rcp(ir);
break;
--
1.9.3
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Re: [Mesa-dev] [PATCH] fp64: disable varying packing for doubles.
On 20 February 2015 at 12:49, Ilia Mirkin imir...@alum.mit.edu wrote: On Thu, Feb 19, 2015 at 9:43 PM, Dave Airlie airl...@gmail.com wrote: From: Dave Airlie airl...@redhat.com I'm not sure we really care about this, but we need to write better support if we do. For now just disable it. piglit test: tests/spec/arb_gpu_shader_fp64/execution/vs-out-fs-in-double-2.shader_test Signed-off-by: Dave Airlie airl...@redhat.com --- src/glsl/lower_packed_varyings.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/glsl/lower_packed_varyings.cpp b/src/glsl/lower_packed_varyings.cpp index 5e844c7..3c9cbec 100644 --- a/src/glsl/lower_packed_varyings.cpp +++ b/src/glsl/lower_packed_varyings.cpp @@ -592,6 +592,9 @@ lower_packed_varyings_visitor::needs_lowering(ir_variable *var) return false; const glsl_type *type = var-type; + /* don't attempt to pack double varyings yet */ + if (type-base_type == GLSL_TYPE_DOUBLE) + return false; Not sure, but I _think_ type can be an array here... (or even worse, a struct... hopefully not). Should be simple to whip up some piglits. If I'm right on the array, you can do type-without_array(). If it can also be a struct, then maybe -contains_double()? Good point though if I move it down a few lines it should be fine, since the code checks for array and fixes type up. I'll resend and we can see. Dave. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] gallium: add new double-related shader caps to all the getters
On 20 February 2015 at 14:46, Ilia Mirkin imir...@alum.mit.edu wrote: Missed a few drivers in the earlier changes, this should fix up all the ones that print unknown caps or don't have a default statement. +++ b/src/gallium/drivers/vc4/vc4_screen.c @@ -318,6 +318,10 @@ vc4_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, return 1; case PIPE_SHADER_CAP_DOUBLES: return 0; +case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: +return 0; +case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: +return 0; case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: return VC4_MAX_TEXTURE_SAMPLERS; Why does vc4 no collapse them into one return 0? Otherwise: Reviewed-by: Dave Airlie airl...@redhat.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] glsl: don't allow invariant qualifiers for interface blocks
On Wednesday 18 February 2015 11:51:45 Matt Turner wrote: On Tue, Dec 9, 2014 at 2:52 AM, Eduardo Lima Mitev el...@igalia.com wrote: From: Samuel Iglesias Gonsalvez sigles...@igalia.com GLSL 1.50 and GLSL 4.40 specs, they both say the same in Interface Blocks section: If no optional qualifier is used in a member-declaration, the qualification of the member includes all in, out, patch, uniform, or buffer as determined by interface-qualifier. If optional qualifiers are used, they can include interpolation qualifiers, auxiliary storage qualifiers, and storage qualifiers and they must declare an input, output, or uniform member consistent with the interface qualifier of the block From GLSL ES 3.0, chapter 4.3.7 Interface Blocks, page 38: GLSL ES 3.0 does not support interface blocks for shader inputs or outputs. and from GLSL ES 3.0, chapter 4.6.1 The invariant qualifier, page 52. Only variables output from a shader can be candidates for invariance. This includes user-defined output variables and the built-in output variables. As only outputs can be declared as invariant, an invariant output from one shader stage will still match an input of a subsequent stage without the input being declared as invariant. From GLSL ES 1.0, chapter 4.6.1 The invariant qualifier, page 37. Only the following variables may be declared as invariant: * Built-in special variables output from the vertex shader * Varying variables output from the vertex shader * Built-in special variables input to the fragment shader * Varying variables input to the fragment shader * Built-in special variables output from the fragment shader. This patch fixes the following dEQP tests: dEQP-GLES3.functional.shaders.declarations.invalid_declarations.invariant_ uniform_block_2_vertex dEQP-GLES3.functional.shaders.declarations.invalid_declarations.invariant _uniform_block_2_fragment No piglit regressions. Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com v2: - Enable this check for GLSL. Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com --- src/glsl/glsl_parser.yy | 35 +++ 1 file changed, 35 insertions(+) diff --git a/src/glsl/glsl_parser.yy b/src/glsl/glsl_parser.yy index 7fb8c38..9f2a0a3 100644 --- a/src/glsl/glsl_parser.yy +++ b/src/glsl/glsl_parser.yy @@ -2539,6 +2539,41 @@ basic_interface_block: interface block member does not match the interface block); } + /* From GLSL ES 3.0, chapter 4.3.7 Interface Blocks, page 38: + * + * GLSL ES 3.0 does not support interface blocks for shader inputs or + * outputs. + * + * And from GLSL ES 3.0, chapter 4.6.1 The invariant qualifier, page 52. + * + * Only variables output from a shader can be candidates for + * invariance. I'd snip the rest of the quote after this. I don't think it makes the point clearer, and actually just makes it harder to see the important bit. This includes user-defined output variables and the + * built-in output variables. As only outputs can be declared as + * invariant, an invariant output from one shader stage will + * still match an input of a subsequent stage without the input being + * declared as invariant. + * + * From GLSL ES 1.0, chapter 4.6.1 The invariant qualifier, page 37. + * + * Only the following variables may be declared as invariant: + * * Built-in special variables output from the vertex shader + * * Varying variables output from the vertex shader + * * Built-in special variables input to the fragment shader + * * Varying variables input to the fragment shader + * * Built-in special variables output from the fragment shader. + * + * From GLSL 4.40 and GLSL 1.50, section Interface Blocks: + * + * If no optional qualifier is used in a member-declaration, the + * qualification of the member includes all in, out, patch, uniform, + * or buffer as determined by interface-qualifier. I'd snip the quote before this. If optional + * qualifiers are used, they can include interpolation qualifiers, + * auxiliary storage qualifiers, and storage qualifiers and they must + * declare an input, output, or uniform member consistent with the + * interface qualifier of the block + */ + if (qualifier.flags.q.invariant) +_mesa_glsl_error(@1, state, invariant qualifiers cannot be used with interface blocks members); Try to line wrap this. With those comments fixed: Reviewed-by: Matt
Re: [Mesa-dev] [PATCH] i965/fs: Set pixel/sample mask for compute shaders atomic ops
On Thu, Feb 19, 2015 at 11:25:56PM -0800, Jordan Justen wrote: On 2015-02-19 21:40:37, Ben Widawsky wrote: On Thu, Feb 19, 2015 at 03:42:05PM -0800, Jordan Justen wrote: For fragment programs, we pull this mask from the payload header. The same mask doesn't exist for compute shaders, so we set all bits to enabled. Note: this mask is ANDed with the execution mask, so some channels may not end up issuing the atomic operation. Signed-off-by: Jordan Justen jordan.l.jus...@intel.com Cc: Ben Widawsky b...@bwidawsk.net Cc: Francisco Jerez curroje...@riseup.net Just add to the commit message that this is needed specifically because compute is invoked as SIMD16 (and perhaps reference the other commits?) and it's: Reviewed-by: Ben Widawsky b...@bwidawsk.net Good idea. I'll add those. Sorry it advance... we may as well just go for 0x in case we ever support SIMD32. I had been setting all 32-bits previously. I mentioned to you that I thought this was needed for SIMD32. I wanted to double check it before sending the patch out. I think I found the field for IVB in the PRM: IVB Vol 4 Part 1 3.9.9.9 Message Header Pixel/Sample Mask ...and it looks like it is only 16-bits. Maybe Francisco can confirm that I got it right. I couldn't find this same information in the HSW PRMs. I'm not sure what that means for SIMD32. -Jordan I suspect it's because the docs are super suck wrt SIMD32... but if you looked and see nothing, just leave it be. Whomever enables SIMD32 can deal with it :-) [snip] ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/gen6: Fix GL_GEOMETRY_SHADER_PRIMITIVES_EMITTED_ARB
On Fri, Feb 20, 2015 at 08:21:25AM +0100, Iago Toral Quiroga wrote: In gen6 we need to compute the primitive count in the generated GS program. The current implementation only counts full primitives, that is, if the output primitive type is a triangle strip, it won't count individual triangles in the strip, only complete strips. If we want to count basic primitives instead we have two options: rework the assembly code we generate for strip primitives or simply use CL_INVOCATION_COUNT to resolve the query and let the hardware do that work for us. This patch implements the latter approach. Fixes the following piglit test: bin/arb_pipeline_statistics_query-geom -auto Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89210 Tested-by: Mark Janes mark.a.ja...@intel.com Reviewed-by: Ben Widawsky b...@bwidawsk.net ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 06/23] main: Add entry point for NamedBufferStorage.
On 20/02/2015 02:15, Laura Ekstrand wrote: This is NamedBufferStorage, not NamedBufferData. The storage function uses a bitfield instead of an enum. Oops, sorry. I was trying to match these patches with their relative piglit tests and as the order is not always the same, I must have got confused :) ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/3] i965/fs/nir: Optimize (gl_FrontFacing ? x : y) where x and y are ±1.0.
On Tue, Feb 17, 2015 at 11:46 AM, Matt Turner matts...@gmail.com wrote: total instructions in shared programs: 8013221 - 8010869 (-0.03%) instructions in affected programs: 475925 - 473573 (-0.49%) helped:2350 --- Patches 1 and 3 have been reviewed, but I'm this one hasn't. Neither has the equivalent change to brw_fs_visitor.cpp [0]. The only response to that patch was concerns about adding new optimizations only to brw_fs_visitor.cpp. The current numbers for this patch are total instructions in shared programs: 7756214 - 7753873 (-0.03%) instructions in affected programs: 455452 - 453111 (-0.51%) helped:2333 and the current numbers for the analogous brw_fs_visitor.cpp change are total instructions in shared programs: 5695356 - 5689775 (-0.10%) instructions in affected programs: 486231 - 480650 (-1.15%) helped:2604 LOST: 1 They're both available in the sent branch of my tree: git://people.freedesktop.org/~mattst88/mesa sent [0] [PATCH 3/4] i965/fs: Optimize (gl_FrontFacing ? x : y) where x and y are ±1.0. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] glsl/fp64: disable varying packing for doubles. (v2)
From: Dave Airlie airl...@redhat.com I'm not sure we really care about this, but we need to write better support if we do. For now just disable it. piglit test: tests/spec/arb_gpu_shader_fp64/execution/vs-out-fs-in-double-2.shader_test v2: move code down below to avoid getting array type. Signed-off-by: Dave Airlie airl...@redhat.com --- src/glsl/lower_packed_varyings.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/glsl/lower_packed_varyings.cpp b/src/glsl/lower_packed_varyings.cpp index 5e844c7..83b70f9 100644 --- a/src/glsl/lower_packed_varyings.cpp +++ b/src/glsl/lower_packed_varyings.cpp @@ -598,6 +598,9 @@ lower_packed_varyings_visitor::needs_lowering(ir_variable *var) } if (type-is_array()) type = type-fields.array; + /* don't attempt to pack double varyings yet */ + if (type-base_type == GLSL_TYPE_DOUBLE) + return false; if (type-vector_elements == 4) return false; return true; -- 1.9.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] gallium: add new double-related shader caps to all the getters
Missed a few drivers in the earlier changes, this should fix up all the ones that print unknown caps or don't have a default statement. Signed-off-by: Ilia Mirkin imir...@alum.mit.edu --- src/gallium/drivers/freedreno/freedreno_screen.c | 2 ++ src/gallium/drivers/i915/i915_screen.c | 4 src/gallium/drivers/nouveau/nv30/nv30_screen.c | 6 ++ src/gallium/drivers/nouveau/nv50/nv50_screen.c | 4 src/gallium/drivers/r300/r300_screen.c | 4 src/gallium/drivers/vc4/vc4_screen.c | 4 6 files changed, 24 insertions(+) diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index 45293e4..044b1bc 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -385,6 +385,8 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, return 1; case PIPE_SHADER_CAP_SUBROUTINES: case PIPE_SHADER_CAP_DOUBLES: + case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: return 0; case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: return 1; diff --git a/src/gallium/drivers/i915/i915_screen.c b/src/gallium/drivers/i915/i915_screen.c index 5fbbcf5..dc76464 100644 --- a/src/gallium/drivers/i915/i915_screen.c +++ b/src/gallium/drivers/i915/i915_screen.c @@ -155,6 +155,10 @@ i915_get_shader_param(struct pipe_screen *screen, unsigned shader, enum pipe_sha case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: return I915_TEX_UNITS; + case PIPE_SHADER_CAP_DOUBLES: + case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: + return 0; default: debug_printf(%s: Unknown cap %u.\n, __FUNCTION__, cap); return 0; diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c b/src/gallium/drivers/nouveau/nv30/nv30_screen.c index a532e53..0fca9e0 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c @@ -247,6 +247,9 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: case PIPE_SHADER_CAP_SUBROUTINES: case PIPE_SHADER_CAP_INTEGERS: + case PIPE_SHADER_CAP_DOUBLES: + case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: return 0; default: debug_printf(unknown vertex shader param %d\n, param); @@ -283,6 +286,9 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: case PIPE_SHADER_CAP_SUBROUTINES: + case PIPE_SHADER_CAP_DOUBLES: + case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: return 0; default: debug_printf(unknown fragment shader param %d\n, param); diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c b/src/gallium/drivers/nouveau/nv50/nv50_screen.c index 95d1e6c..ed07ba4 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c @@ -286,6 +286,10 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, /* The chip could handle more sampler views than samplers */ case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: return MIN2(32, PIPE_MAX_SAMPLERS); + case PIPE_SHADER_CAP_DOUBLES: + case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: + return 0; default: NOUVEAU_ERR(unknown PIPE_SHADER_CAP %d\n, param); return 0; diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 36b2996..fca8001 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -285,6 +285,8 @@ static int r300_get_shader_param(struct pipe_screen *pscreen, unsigned shader, e case PIPE_SHADER_CAP_SUBROUTINES: case PIPE_SHADER_CAP_INTEGERS: case PIPE_SHADER_CAP_DOUBLES: +case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: +case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: return 0; case PIPE_SHADER_CAP_PREFERRED_IR: return PIPE_SHADER_IR_TGSI; @@ -337,6 +339,8 @@ static int r300_get_shader_param(struct pipe_screen *pscreen, unsigned shader, e case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: case PIPE_SHADER_CAP_DOUBLES: +case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: +case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: return 0; case PIPE_SHADER_CAP_PREFERRED_IR:
Re: [Mesa-dev] [PATCH] i965/fs: Set pixel/sample mask for compute shaders atomic ops
On Thu, Feb 19, 2015 at 03:42:05PM -0800, Jordan Justen wrote: For fragment programs, we pull this mask from the payload header. The same mask doesn't exist for compute shaders, so we set all bits to enabled. Note: this mask is ANDed with the execution mask, so some channels may not end up issuing the atomic operation. Signed-off-by: Jordan Justen jordan.l.jus...@intel.com Cc: Ben Widawsky b...@bwidawsk.net Cc: Francisco Jerez curroje...@riseup.net Just add to the commit message that this is needed specifically because compute is invoked as SIMD16 (and perhaps reference the other commits?) and it's: Reviewed-by: Ben Widawsky b...@bwidawsk.net Sorry it advance... we may as well just go for 0x in case we ever support SIMD32. --- While it's fresh in our minds. :) This seems to work for gen7 gen8 CS. For CS simd16, we need the 0x change, but it seems to work fine for simd8 as well. I also tested gen8 (simd8vs), and there were no piglit regressions. src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 24cc118..960a0aa 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -2998,9 +2998,9 @@ fs_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index, * mask sent in the header to compute the actual set of channels that execute * the atomic operation. */ - assert(stage == MESA_SHADER_VERTEX); + assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE); emit(MOV(component(sources[0], 7), - brw_imm_ud(0xff)))-force_writemask_all = true; + brw_imm_ud(0x)))-force_writemask_all = true; } length++; @@ -3061,9 +3061,9 @@ fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst, * mask sent in the header to compute the actual set of channels that execute * the atomic operation. */ - assert(stage == MESA_SHADER_VERTEX); + assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE); emit(MOV(component(sources[0], 7), - brw_imm_ud(0xff)))-force_writemask_all = true; + brw_imm_ud(0x)))-force_writemask_all = true; } /* Set the surface read offset. */ -- 2.1.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] nir: Copy-propagate vecN operations that are actually moves
We were already do this for ALU operations but we haven't for non-ALU
operations. This changes that.
total NIR instructions in shared programs: 2039883 - 2022338 (-0.86%)
NIR instructions in affected programs: 1768850 - 1751305 (-0.99%)
helped:14244
HURT: 124
total FS instructions in shared programs: 4083960 - 4084036 (0.00%)
FS instructions in affected programs: 7302 - 7378 (1.04%)
helped: 12
HURT: 51
Signed-off-by: Jason Ekstrand jason.ekstr...@intel.com
---
src/glsl/nir/nir_opt_copy_propagate.c | 45 ++-
1 file changed, 29 insertions(+), 16 deletions(-)
diff --git a/src/glsl/nir/nir_opt_copy_propagate.c
b/src/glsl/nir/nir_opt_copy_propagate.c
index dd0ec01..ee78e5a 100644
--- a/src/glsl/nir/nir_opt_copy_propagate.c
+++ b/src/glsl/nir/nir_opt_copy_propagate.c
@@ -53,22 +53,6 @@ static bool is_move(nir_alu_instr *instr)
}
-static bool
-is_swizzleless_move(nir_alu_instr *instr)
-{
- if (!is_move(instr))
- return false;
-
- for (unsigned i = 0; i 4; i++) {
- if (!((instr-dest.write_mask i) 1))
- break;
- if (instr-src[0].swizzle[i] != i)
- return false;
- }
-
- return true;
-}
-
static bool is_vec(nir_alu_instr *instr)
{
for (unsigned i = 0; i nir_op_infos[instr-op].num_inputs; i++)
@@ -80,6 +64,35 @@ static bool is_vec(nir_alu_instr *instr)
instr-op == nir_op_vec4;
}
+static bool
+is_swizzleless_move(nir_alu_instr *instr)
+{
+ if (is_move(instr)) {
+ for (unsigned i = 0; i 4; i++) {
+ if (!((instr-dest.write_mask i) 1))
+break;
+ if (instr-src[0].swizzle[i] != i)
+return false;
+ }
+ return true;
+ } else if (is_vec(instr)) {
+ nir_ssa_def *def = NULL;
+ for (unsigned i = 0; i nir_op_infos[instr-op].num_inputs; i++) {
+ if (instr-src[i].swizzle[0] != i)
+return false;
+
+ if (def == NULL) {
+def = instr-src[i].src.ssa;
+ } else if (instr-src[i].src.ssa != def) {
+return false;
+ }
+ }
+ return true;
+ } else {
+ return false;
+ }
+}
+
typedef struct {
nir_ssa_def *def;
bool found;
--
2.3.0
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Re: [Mesa-dev] [PATCH] glsl: don't allow invariant qualifiers for interface blocks
On Thursday 19 February 2015 11:39:13 Ian Romanick wrote: On 12/09/2014 02:52 AM, Eduardo Lima Mitev wrote: From: Samuel Iglesias Gonsalvez sigles...@igalia.com GLSL 1.50 and GLSL 4.40 specs, they both say the same in Interface Blocks section: If no optional qualifier is used in a member-declaration, the qualification of the member includes all in, out, patch, uniform, or buffer as determined by interface-qualifier. If optional qualifiers are used, they can include interpolation qualifiers, auxiliary storage qualifiers, and storage qualifiers and they must declare an input, output, or uniform member consistent with the interface qualifier of the block From GLSL ES 3.0, chapter 4.3.7 Interface Blocks, page 38: GLSL ES 3.0 does not support interface blocks for shader inputs or outputs. and from GLSL ES 3.0, chapter 4.6.1 The invariant qualifier, page 52. Only variables output from a shader can be candidates for invariance. This includes user-defined output variables and the built-in output variables. As only outputs can be declared as invariant, an invariant output from one shader stage will still match an input of a subsequent stage without the input being declared as invariant. From GLSL ES 1.0, chapter 4.6.1 The invariant qualifier, page 37. Only the following variables may be declared as invariant: * Built-in special variables output from the vertex shader * Varying variables output from the vertex shader * Built-in special variables input to the fragment shader * Varying variables input to the fragment shader * Built-in special variables output from the fragment shader. This patch fixes the following dEQP tests: dEQP-GLES3.functional.shaders.declarations.invalid_declarations.invariant_ uniform_block_2_vertex dEQP-GLES3.functional.shaders.declarations.invalid_declarations.invariant _uniform_block_2_fragment No piglit regressions. Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com v2: - Enable this check for GLSL. Signed-off-by: Samuel Iglesias Gonsalvez sigles...@igalia.com --- src/glsl/glsl_parser.yy | 35 +++ 1 file changed, 35 insertions(+) diff --git a/src/glsl/glsl_parser.yy b/src/glsl/glsl_parser.yy index 7fb8c38..9f2a0a3 100644 --- a/src/glsl/glsl_parser.yy +++ b/src/glsl/glsl_parser.yy @@ -2539,6 +2539,41 @@ basic_interface_block: interface block member does not match the interface block); } Blank line here. + /* From GLSL ES 3.0, chapter 4.3.7 Interface Blocks, page 38: + * + * GLSL ES 3.0 does not support interface blocks for shader inputs or + * outputs. + * + * And from GLSL ES 3.0, chapter 4.6.1 The invariant qualifier, page 52. + * + * Only variables output from a shader can be candidates for + * invariance. This includes user-defined output variables and the + * built-in output variables. As only outputs can be declared as + * invariant, an invariant output from one shader stage will + * still match an input of a subsequent stage without the input being + * declared as invariant. + * + * From GLSL ES 1.0, chapter 4.6.1 The invariant qualifier, page 37. + * + * Only the following variables may be declared as invariant: + * * Built-in special variables output from the vertex shader + * * Varying variables output from the vertex shader + * * Built-in special variables input to the fragment shader + * * Varying variables input to the fragment shader + * * Built-in special variables output from the fragment shader. In addition to Matt's comments about the comment... I don't think there's any reason to mention GLSL ES 1.0. There are no interface blocks in GLSL ES 1.0, and this is inside processing an interface block. With this and Matt's suggestions applied, this patch is Reviewed-by: Ian Romanick ian.d.roman...@intel.com OK, I will fix them. Thanks for your review! Sam signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/fs: Set pixel/sample mask for compute shaders atomic ops
On 2015-02-19 21:40:37, Ben Widawsky wrote: On Thu, Feb 19, 2015 at 03:42:05PM -0800, Jordan Justen wrote: For fragment programs, we pull this mask from the payload header. The same mask doesn't exist for compute shaders, so we set all bits to enabled. Note: this mask is ANDed with the execution mask, so some channels may not end up issuing the atomic operation. Signed-off-by: Jordan Justen jordan.l.jus...@intel.com Cc: Ben Widawsky b...@bwidawsk.net Cc: Francisco Jerez curroje...@riseup.net Just add to the commit message that this is needed specifically because compute is invoked as SIMD16 (and perhaps reference the other commits?) and it's: Reviewed-by: Ben Widawsky b...@bwidawsk.net Good idea. I'll add those. Sorry it advance... we may as well just go for 0x in case we ever support SIMD32. I had been setting all 32-bits previously. I mentioned to you that I thought this was needed for SIMD32. I wanted to double check it before sending the patch out. I think I found the field for IVB in the PRM: IVB Vol 4 Part 1 3.9.9.9 Message Header Pixel/Sample Mask ...and it looks like it is only 16-bits. Maybe Francisco can confirm that I got it right. I couldn't find this same information in the HSW PRMs. I'm not sure what that means for SIMD32. -Jordan --- While it's fresh in our minds. :) This seems to work for gen7 gen8 CS. For CS simd16, we need the 0x change, but it seems to work fine for simd8 as well. I also tested gen8 (simd8vs), and there were no piglit regressions. src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 24cc118..960a0aa 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -2998,9 +2998,9 @@ fs_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index, * mask sent in the header to compute the actual set of channels that execute * the atomic operation. */ - assert(stage == MESA_SHADER_VERTEX); + assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE); emit(MOV(component(sources[0], 7), - brw_imm_ud(0xff)))-force_writemask_all = true; + brw_imm_ud(0x)))-force_writemask_all = true; } length++; @@ -3061,9 +3061,9 @@ fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst, * mask sent in the header to compute the actual set of channels that execute * the atomic operation. */ - assert(stage == MESA_SHADER_VERTEX); + assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE); emit(MOV(component(sources[0], 7), - brw_imm_ud(0xff)))-force_writemask_all = true; + brw_imm_ud(0x)))-force_writemask_all = true; } /* Set the surface read offset. */ -- 2.1.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 02/23] main: Add entry point for TextureBufferRange.
On 18/02/2015 20:10, Ian Romanick wrote:
On 02/17/2015 07:59 AM, Martin Peres wrote:
Hey Laura,
Thanks for this code. I'll be sending reviews throughout the week :)
On 12/02/15 04:05, Laura Ekstrand wrote:
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 336feff..ce6f446 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -5197,6 +5197,96 @@ _mesa_TextureBuffer(GLuint texture, GLenum
internalFormat, GLuint buffer)
bufObj, 0, buffer ? -1 : 0, false, true);
}
+void GLAPIENTRY
+_mesa_TextureBufferRange(GLuint texture, GLenum internalFormat,
GLuint buffer,
+ GLintptr offset, GLsizeiptr size)
+{
+ struct gl_texture_object *texObj;
+ struct gl_buffer_object *bufObj;
+
+ GET_CURRENT_CONTEXT(ctx);
+
+ /* NOTE: ARB_texture_buffer_object has interactions with
+* the compatibility profile that are not implemented.
+*/
+ if (!(ctx-API == API_OPENGL_CORE
+ ctx-Extensions.ARB_texture_buffer_object)) {
+ _mesa_error(ctx, GL_INVALID_OPERATION,
+ glTextureBufferRange(ARB_texture_buffer_object is
not
+ implemented for the compatibility profile));
+ return;
+ }
Can you point me to the relevant part of the spec that explains the
interaction?
In compatibility profile, TexBos can support luminance, luminance-alpha,
and intensity textures. Intel hardware doesn't support that, and none
of the TexBo common code supports it either.
But... at least for glTexBuffer and glTexBufferRange there is (almost) a
better way to do this. We should change the GL API generator code so
that we can omit functions from compatibility profile. We can already
do this for core profile (look for the deprecated='3.1' bits in
src/mapi/glapi/gen).
Due to previously mentioned issues with libraries like GLEW, we may not
be able to do this with DSA functions that are core-only if we're going
to expose DSA on compatibility profile.
Thanks Ian. How should I check for interactions with the compatibility mode
on the entry points I added? I guess I need to check Opengl 4.5 compat,
right?
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Re: [Mesa-dev] [PATCH] gallium: add new double-related shader caps to all the getters
On Thu, Feb 19, 2015 at 11:54 PM, Dave Airlie airl...@gmail.com wrote: On 20 February 2015 at 14:46, Ilia Mirkin imir...@alum.mit.edu wrote: Missed a few drivers in the earlier changes, this should fix up all the ones that print unknown caps or don't have a default statement. +++ b/src/gallium/drivers/vc4/vc4_screen.c @@ -318,6 +318,10 @@ vc4_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, return 1; case PIPE_SHADER_CAP_DOUBLES: return 0; +case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: +return 0; +case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: +return 0; case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: return VC4_MAX_TEXTURE_SAMPLERS; Why does vc4 no collapse them into one return 0? I dunno, they're mostly split up like that, I went with the flow. Otherwise: Reviewed-by: Dave Airlie airl...@redhat.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] i965/skl: Use 1 register for uniform pull constant payload
When under dispatch_width=16 the previous code would allocate 2 registers for the payload when only one is needed. This manifested itself through bugs on SKL which needs to mess with this instruction. Ken though this might impact shader-db, but apparently it doesn't Cc: Kenneth Graunke kenn...@whitecape.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89118 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88999 Signed-off-by: Ben Widawsky b...@bwidawsk.net --- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index c46e1d7..24125cc 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -3062,7 +3062,7 @@ fs_visitor::lower_uniform_pull_constant_loads() assert(const_offset_reg.file == IMM const_offset_reg.type == BRW_REGISTER_TYPE_UD); const_offset_reg.fixed_hw_reg.dw1.ud /= 4; - fs_reg payload = vgrf(glsl_type::uint_type); + fs_reg payload = fs_reg(GRF, alloc.allocate(1)); /* We have to use a message header on Skylake to get SIMD4x2 mode. * Reserve space for the register. -- 2.3.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] nir: Copy-propagate vecN operations that are actually moves
I agree with Ken that the regressions are small enough, and it seems
they're mostly stuff we can prevent by being smarter when doing the
sel peephole, so it seems like the cleanup that will probably help
other passes is worth it.
Reviewed-by: Connor Abbott cwabbo...@gmail.com
On Fri, Feb 20, 2015 at 1:03 AM, Jason Ekstrand ja...@jlekstrand.net wrote:
We were already do this for ALU operations but we haven't for non-ALU
operations. This changes that.
total NIR instructions in shared programs: 2039883 - 2022338 (-0.86%)
NIR instructions in affected programs: 1768850 - 1751305 (-0.99%)
helped:14244
HURT: 124
total FS instructions in shared programs: 4083960 - 4084036 (0.00%)
FS instructions in affected programs: 7302 - 7378 (1.04%)
helped: 12
HURT: 51
Signed-off-by: Jason Ekstrand jason.ekstr...@intel.com
---
src/glsl/nir/nir_opt_copy_propagate.c | 45
++-
1 file changed, 29 insertions(+), 16 deletions(-)
diff --git a/src/glsl/nir/nir_opt_copy_propagate.c
b/src/glsl/nir/nir_opt_copy_propagate.c
index dd0ec01..ee78e5a 100644
--- a/src/glsl/nir/nir_opt_copy_propagate.c
+++ b/src/glsl/nir/nir_opt_copy_propagate.c
@@ -53,22 +53,6 @@ static bool is_move(nir_alu_instr *instr)
}
-static bool
-is_swizzleless_move(nir_alu_instr *instr)
-{
- if (!is_move(instr))
- return false;
-
- for (unsigned i = 0; i 4; i++) {
- if (!((instr-dest.write_mask i) 1))
- break;
- if (instr-src[0].swizzle[i] != i)
- return false;
- }
-
- return true;
-}
-
static bool is_vec(nir_alu_instr *instr)
{
for (unsigned i = 0; i nir_op_infos[instr-op].num_inputs; i++)
@@ -80,6 +64,35 @@ static bool is_vec(nir_alu_instr *instr)
instr-op == nir_op_vec4;
}
+static bool
+is_swizzleless_move(nir_alu_instr *instr)
+{
+ if (is_move(instr)) {
+ for (unsigned i = 0; i 4; i++) {
+ if (!((instr-dest.write_mask i) 1))
+break;
+ if (instr-src[0].swizzle[i] != i)
+return false;
+ }
+ return true;
+ } else if (is_vec(instr)) {
+ nir_ssa_def *def = NULL;
+ for (unsigned i = 0; i nir_op_infos[instr-op].num_inputs; i++) {
+ if (instr-src[i].swizzle[0] != i)
+return false;
+
+ if (def == NULL) {
+def = instr-src[i].src.ssa;
+ } else if (instr-src[i].src.ssa != def) {
+return false;
+ }
+ }
+ return true;
+ } else {
+ return false;
+ }
+}
+
typedef struct {
nir_ssa_def *def;
bool found;
--
2.3.0
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Re: [Mesa-dev] [PATCH 07/23] main: Add entry point for NamedBufferData.
On 20/02/2015 02:12, Laura Ekstrand wrote:
On Wed, Feb 18, 2015 at 7:40 AM, Martin Peres
martin.pe...@linux.intel.com mailto:martin.pe...@linux.intel.com
wrote:
On 12/02/15 04:05, Laura Ekstrand wrote:
v2: review from Ian Romanick
- Fix space in ARB_direct_state_access.xml.
- Remove _mesa from the name of buffer_data static fallback.
- Restore VBO_DEBUG and BOUNDS_CHECK.
- Fix beginning of comment to start on same line as /*
---
src/mapi/glapi/gen/ARB_direct_state_access.xml | 7 +++
src/mesa/main/bufferobj.c | 67
++
src/mesa/main/bufferobj.h | 13 -
src/mesa/main/tests/dispatch_sanity.cpp| 1 +
4 files changed, 67 insertions(+), 21 deletions(-)
diff --git a/src/mapi/glapi/gen/ARB_direct_state_access.xml
b/src/mapi/glapi/gen/ARB_direct_state_access.xml
index ff81c21..7779262 100644
--- a/src/mapi/glapi/gen/ARB_direct_state_access.xml
+++ b/src/mapi/glapi/gen/ARB_direct_state_access.xml
@@ -21,6 +21,13 @@
param name=flags type=GLbitfield /
/function
+ function name=NamedBufferData offset=assign
+ param name=buffer type=GLuint /
+ param name=size type=GLsizeiptr /
+ param name=data type=const GLvoid * /
+ param name=usage type=GLenum /
+ /function
+
!-- Texture object functions --
function name=CreateTextures offset=assign
diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index 6259db1..ac8eed1 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -556,9 +556,9 @@ _mesa_total_buffer_object_memory(struct
gl_context *ctx)
* \sa glBufferDataARB, dd_function_table::BufferData.
*/
static GLboolean
-_mesa_buffer_data( struct gl_context *ctx, GLenum target,
GLsizeiptrARB size,
- const GLvoid * data, GLenum usage, GLenum
storageFlags,
- struct gl_buffer_object * bufObj )
+buffer_data_fallback(struct gl_context *ctx, GLenum target,
GLsizeiptr size,
+ const GLvoid *data, GLenum usage, GLenum
storageFlags,
+ struct gl_buffer_object *bufObj)
{
void * new_data;
@@ -1112,7 +1112,7 @@
_mesa_init_buffer_object_functions(struct dd_function_table
*driver)
/* GL_ARB_vertex/pixel_buffer_object */
driver-NewBufferObject = _mesa_new_buffer_object;
driver-DeleteBuffer = _mesa_delete_buffer_object;
- driver-BufferData = _mesa_buffer_data;
+ driver-BufferData = buffer_data_fallback;
driver-BufferSubData = _mesa_buffer_subdata;
driver-GetBufferSubData = _mesa_buffer_get_subdata;
driver-UnmapBuffer = _mesa_buffer_unmap;
@@ -1474,23 +1474,22 @@ _mesa_NamedBufferStorage(GLuint
buffer, GLsizeiptr size, const GLvoid *data,
}
-
-void GLAPIENTRY
-_mesa_BufferData(GLenum target, GLsizeiptrARB size,
-const GLvoid * data, GLenum usage)
+void
+_mesa_buffer_data(struct gl_context *ctx, struct
gl_buffer_object *bufObj,
+ GLenum target, GLsizeiptr size, const
GLvoid *data,
+ GLenum usage, const char *func)
{
- GET_CURRENT_CONTEXT(ctx);
- struct gl_buffer_object *bufObj;
bool valid_usage;
if (MESA_VERBOSE VERBOSE_API)
- _mesa_debug(ctx, glBufferData(%s, %ld, %p, %s)\n,
+ _mesa_debug(ctx, %s(%s, %ld, %p, %s)\n,
Func could be on this line but I really don't care.
+ func,
_mesa_lookup_enum_by_nr(target),
(long int) size, data,
_mesa_lookup_enum_by_nr(usage));
if (size 0) {
- _mesa_error(ctx, GL_INVALID_VALUE,
glBufferDataARB(size 0));
+ _mesa_error(ctx, GL_INVALID_VALUE, %s(size 0), func);
return;
}
@@ -1519,16 +1518,13 @@ _mesa_BufferData(GLenum target,
GLsizeiptrARB size,
}
if (!valid_usage) {
- _mesa_error(ctx, GL_INVALID_ENUM, glBufferData(usage));
+ _mesa_error(ctx, GL_INVALID_ENUM, %s(invalid usage:
%s), func,
+ _mesa_lookup_enum_by_nr(usage));
return;
}
- bufObj = get_buffer(ctx, glBufferDataARB, target,
GL_INVALID_OPERATION);
- if (!bufObj)
Re: [Mesa-dev] [PATCH] i965/fs: Set pixel/sample mask for compute shaders atomic ops
On Thu, Feb 19, 2015 at 3:42 PM, Jordan Justen jordan.l.jus...@intel.com wrote: For fragment programs, we pull this mask from the payload header. The same mask doesn't exist for compute shaders, so we set all bits to enabled. Note: this mask is ANDed with the execution mask, so some channels may not end up issuing the atomic operation. Signed-off-by: Jordan Justen jordan.l.jus...@intel.com Cc: Ben Widawsky b...@bwidawsk.net Cc: Francisco Jerez curroje...@riseup.net --- While it's fresh in our minds. :) This seems to work for gen7 gen8 CS. For CS simd16, we need the 0x change, but it seems to work fine for simd8 as well. I also tested gen8 (simd8vs), and there were no piglit regressions. src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 24cc118..960a0aa 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -2998,9 +2998,9 @@ fs_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index, * mask sent in the header to compute the actual set of channels that execute * the atomic operation. */ - assert(stage == MESA_SHADER_VERTEX); + assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE); emit(MOV(component(sources[0], 7), - brw_imm_ud(0xff)))-force_writemask_all = true; + brw_imm_ud(0x)))-force_writemask_all = true; brw_imm_ud returns a brw_reg, which gets converted to an fs_reg with type = HW_REG. That's not what we want (we consider HW_REGs to be barriers to instruction scheduling, for instance). Change it to fs_reg(0x) while you're modifying it. } length++; @@ -3061,9 +3061,9 @@ fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst, * mask sent in the header to compute the actual set of channels that execute * the atomic operation. */ - assert(stage == MESA_SHADER_VERTEX); + assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE); emit(MOV(component(sources[0], 7), - brw_imm_ud(0xff)))-force_writemask_all = true; + brw_imm_ud(0x)))-force_writemask_all = true; Same thing here. } /* Set the surface read offset. */ -- 2.1.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] i965/gen6: Fix GL_GEOMETRY_SHADER_PRIMITIVES_EMITTED_ARB
In gen6 we need to compute the primitive count in the generated GS program. The current implementation only counts full primitives, that is, if the output primitive type is a triangle strip, it won't count individual triangles in the strip, only complete strips. If we want to count basic primitives instead we have two options: rework the assembly code we generate for strip primitives or simply use CL_INVOCATION_COUNT to resolve the query and let the hardware do that work for us. This patch implements the latter approach. Fixes the following piglit test: bin/arb_pipeline_statistics_query-geom -auto Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89210 Tested-by: Mark Janes mark.a.ja...@intel.com --- src/mesa/drivers/dri/i965/gen6_queryobj.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c b/src/mesa/drivers/dri/i965/gen6_queryobj.c index 09b66ca..6431ed5 100644 --- a/src/mesa/drivers/dri/i965/gen6_queryobj.c +++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c @@ -147,6 +147,11 @@ emit_pipeline_stat(struct brw_context *brw, drm_intel_bo *bo, }; STATIC_ASSERT(ARRAY_SIZE(target_to_register) == MAX_PIPELINE_STATISTICS); uint32_t reg = target_to_register[pipeline_target_to_index(target)]; + /* Gen6 GS code counts full primitives, that is, it won't count individual +* triangles in a triangle strip. Use CL_INVOCATION_COUNT for that. +*/ + if (brw-gen == 6 target == GL_GEOMETRY_SHADER_PRIMITIVES_EMITTED_ARB) + reg = CL_INVOCATION_COUNT; assert(reg != 0); /* Emit a flush to make sure various parts of the pipeline are complete and -- 1.9.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] st/glsl_to_tgsi: fix ir_assignment hack doing bad things for doubles
From: Dave Airlie airl...@redhat.com
This hack for fixing gl_FragDepth apparantly caused a GLSL shader
outputting a single double to try and output a dvec4, but we hadn't
assigned outputs for the secondary bit.
This avoids going into the hack code for scalar doubles.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index e3f79ed..51ee98a 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -2727,6 +2727,7 @@ glsl_to_tgsi_visitor::visit(ir_assignment *ir)
assert(!ir-lhs-type-is_scalar() !ir-lhs-type-is_vector());
l.writemask = WRITEMASK_XYZW;
} else if (ir-lhs-type-is_scalar()
+ !ir-lhs-type-is_double()
ir-lhs-variable_referenced()-data.mode == ir_var_shader_out) {
/* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
* FINISHME: W component of fragment shader output zero, work correctly.
--
1.9.3
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Re: [Mesa-dev] [PATCH] nir: Copy-propagate vecN operations that are actually moves
On Thursday, February 19, 2015 10:03:15 PM Jason Ekstrand wrote:
We were already do this for ALU operations but we haven't for non-ALU
operations. This changes that.
total NIR instructions in shared programs: 2039883 - 2022338 (-0.86%)
NIR instructions in affected programs: 1768850 - 1751305 (-0.99%)
helped:14244
HURT: 124
It's great to see these cleaned up - programs were littered with
ssa_1 = vec4(ssa_2.x, ssa_2.y, ssa_2.z, ssa_3.w);
Now they're much better.
total FS instructions in shared programs: 4083960 - 4084036 (0.00%)
FS instructions in affected programs: 7302 - 7378 (1.04%)
helped: 12
HURT: 51
This is strange. At least many programs aren't affected.
Presumably, the backend was cleaning up most of these MOVs anyway, and
tidying up the NIR code will help down the road.
Signed-off-by: Jason Ekstrand jason.ekstr...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/glsl/nir/nir_opt_copy_propagate.c | 45
++-
1 file changed, 29 insertions(+), 16 deletions(-)
diff --git a/src/glsl/nir/nir_opt_copy_propagate.c
b/src/glsl/nir/nir_opt_copy_propagate.c
index dd0ec01..ee78e5a 100644
--- a/src/glsl/nir/nir_opt_copy_propagate.c
+++ b/src/glsl/nir/nir_opt_copy_propagate.c
@@ -53,22 +53,6 @@ static bool is_move(nir_alu_instr *instr)
}
-static bool
-is_swizzleless_move(nir_alu_instr *instr)
-{
- if (!is_move(instr))
- return false;
-
- for (unsigned i = 0; i 4; i++) {
- if (!((instr-dest.write_mask i) 1))
- break;
- if (instr-src[0].swizzle[i] != i)
- return false;
- }
-
- return true;
-}
-
static bool is_vec(nir_alu_instr *instr)
{
for (unsigned i = 0; i nir_op_infos[instr-op].num_inputs; i++)
@@ -80,6 +64,35 @@ static bool is_vec(nir_alu_instr *instr)
instr-op == nir_op_vec4;
}
+static bool
+is_swizzleless_move(nir_alu_instr *instr)
+{
+ if (is_move(instr)) {
+ for (unsigned i = 0; i 4; i++) {
+ if (!((instr-dest.write_mask i) 1))
+break;
+ if (instr-src[0].swizzle[i] != i)
+return false;
+ }
+ return true;
+ } else if (is_vec(instr)) {
+ nir_ssa_def *def = NULL;
+ for (unsigned i = 0; i nir_op_infos[instr-op].num_inputs; i++) {
+ if (instr-src[i].swizzle[0] != i)
+return false;
+
+ if (def == NULL) {
+def = instr-src[i].src.ssa;
+ } else if (instr-src[i].src.ssa != def) {
+return false;
+ }
+ }
+ return true;
+ } else {
+ return false;
+ }
+}
+
typedef struct {
nir_ssa_def *def;
bool found;
signature.asc
Description: This is a digitally signed message part.
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Re: [Mesa-dev] [PATCH] nir: Copy-propagate vecN operations that are actually moves
On Thu, Feb 19, 2015 at 11:01 PM, Connor Abbott cwabbo...@gmail.com wrote: I agree with Ken that the regressions are small enough, and it seems they're mostly stuff we can prevent by being smarter when doing the sel peephole, so it seems like the cleanup that will probably help other passes is worth it. So, usually we do that as a preparatory patch. Why aren't we doing that here? NIR instruction counts is not the metric we care about. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] glsl: add lowering for double divide to rcp/mul
On Thu, Feb 19, 2015 at 5:47 PM, Dave Airlie airl...@gmail.com wrote:
From: Dave Airlie airl...@redhat.com
It looks like no hw does div anyways, so we should just
lower at the GLSL level.
Sounds like radeonsi has helpers for DDIV, but they can work this out
when they add support in mesa. Like not using DIV_TO_MUL_RCP lowering.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/glsl/lower_instructions.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/glsl/lower_instructions.cpp b/src/glsl/lower_instructions.cpp
index e8a69e7..ac6715b 100644
--- a/src/glsl/lower_instructions.cpp
+++ b/src/glsl/lower_instructions.cpp
@@ -199,7 +199,7 @@ lower_instructions_visitor::sub_to_add_neg(ir_expression
*ir)
void
lower_instructions_visitor::div_to_mul_rcp(ir_expression *ir)
{
- assert(ir-operands[1]-type-is_float());
+ assert(ir-operands[1]-type-is_float() ||
ir-operands[1]-type-is_double());
/* New expression for the 1.0 / op1 */
ir_rvalue *expr;
@@ -327,7 +327,7 @@ lower_instructions_visitor::mod_to_floor(ir_expression
*ir)
/* Don't generate new IR that would need to be lowered in an additional
* pass.
*/
- if (lowering(DIV_TO_MUL_RCP) ir-type-is_float())
+ if (lowering(DIV_TO_MUL_RCP) (ir-type-is_float() ||
ir-type-is_double()))
div_to_mul_rcp(div_expr);
ir_expression *const floor_expr =
@@ -1014,7 +1014,7 @@ lower_instructions_visitor::visit_leave(ir_expression
*ir)
case ir_binop_div:
if (ir-operands[1]-type-is_integer()
lowering(INT_DIV_TO_MUL_RCP))
int_div_to_mul_rcp(ir);
- else if (ir-operands[1]-type-is_float() lowering(DIV_TO_MUL_RCP))
+ else if ((ir-operands[1]-type-is_float() ||
ir-operands[1]-type-is_double()) lowering(DIV_TO_MUL_RCP))
80 chars. And space around .
With that fixed, Reviewed-by: Ilia Mirkin imir...@alum.mit.edu
div_to_mul_rcp(ir);
break;
--
1.9.3
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Re: [Mesa-dev] [PATCH 3/3] i965/fs: Consider MOV.SAT to interfere if it has a source modifier.
This patch is
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
On 02/11/2015 02:54 PM, Matt Turner wrote:
The saturate propagation pass recognizes that the second instruction
below does not interfere with an attempt to propagate the saturate
modifier from instruction 3 to 1.
1: add(8) dst0 src0 src1
2: mov.sat(8) dst1 dst0
3: mov.sat(8) dst2 dst0
Unfortunately, we did not consider the case of instruction 2 having a
source modifier on dst0. Take for instance:
1: add(8) dst0 src0 src1
2: mov.sat(8) dst1 -dst0
3: mov.sat(8) dst2 dst0
Consider such an instruction to interfere. Increase instruction counts
in Anomaly 2, which could be a bug fix depending on the values the first
instruction produces.
Cc: mesa-sta...@lists.freedesktop.org
---
.../dri/i965/brw_fs_saturate_propagation.cpp | 12 --
.../dri/i965/test_fs_saturate_propagation.cpp | 44
++
2 files changed, 52 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
index bc51661..e406c28 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
@@ -81,12 +81,16 @@ opt_saturate_propagation_local(fs_visitor *v, bblock_t
*block)
break;
}
for (int i = 0; i scan_inst-sources; i++) {
-if ((scan_inst-opcode != BRW_OPCODE_MOV ||
!scan_inst-saturate)
-scan_inst-src[i].file == GRF
+if (scan_inst-src[i].file == GRF
scan_inst-src[i].reg == inst-src[0].reg
scan_inst-src[i].reg_offset == inst-src[0].reg_offset) {
- interfered = true;
- break;
+ if (scan_inst-opcode != BRW_OPCODE_MOV ||
+ !scan_inst-saturate ||
+ scan_inst-src[0].abs ||
+ scan_inst-src[0].negate) {
+ interfered = true;
+ break;
+ }
}
}
diff --git a/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
b/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
index f897bdd..6f762bc 100644
--- a/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
@@ -393,3 +393,47 @@ TEST_F(saturate_propagation_test, intervening_dest_write)
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)-opcode);
EXPECT_TRUE(instruction(block0, 2)-saturate);
}
+
+TEST_F(saturate_propagation_test, mul_neg_mov_sat_mov_sat)
+{
+ fs_reg dst0 = v-vgrf(glsl_type::float_type);
+ fs_reg dst1 = v-vgrf(glsl_type::float_type);
+ fs_reg dst2 = v-vgrf(glsl_type::float_type);
+ fs_reg src0 = v-vgrf(glsl_type::float_type);
+ fs_reg src1 = v-vgrf(glsl_type::float_type);
+ v-emit(BRW_OPCODE_MUL, dst0, src0, src1);
+ dst0.negate = true;
+ v-emit(BRW_OPCODE_MOV, dst1, dst0)
+ -saturate = true;
+ dst0.negate = false;
+ v-emit(BRW_OPCODE_MOV, dst2, dst0)
+ -saturate = true;
+
+ /* = Before =
+*
+* 0: mul(8)dst0 src0 src1
+* 1: mov.sat(8)dst1 -dst0
+* 2: mov.sat(8)dst2 dst0
+*
+* = After =
+* (no changes)
+*/
+
+ v-calculate_cfg();
+ bblock_t *block0 = v-cfg-blocks[0];
+
+ EXPECT_EQ(0, block0-start_ip);
+ EXPECT_EQ(2, block0-end_ip);
+
+ EXPECT_FALSE(saturate_propagation(v));
+ EXPECT_EQ(0, block0-start_ip);
+ EXPECT_EQ(2, block0-end_ip);
+ EXPECT_EQ(BRW_OPCODE_MUL, instruction(block0, 0)-opcode);
+ EXPECT_FALSE(instruction(block0, 0)-saturate);
+ EXPECT_FALSE(instruction(block0, 0)-src[1].negate);
+ EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)-opcode);
+ EXPECT_TRUE(instruction(block0, 1)-saturate);
+ EXPECT_TRUE(instruction(block0, 1)-src[0].negate);
+ EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)-opcode);
+ EXPECT_TRUE(instruction(block0, 2)-saturate);
+}
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[Mesa-dev] [PATCH] i965: just avoid warnings with fp64
This just fills in some blanks to avoid warnings in the i965 driver. Signed-off-by: Dave Airlie airl...@redhat.com --- src/mesa/drivers/dri/i965/brw_fs.cpp | 1 + src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp | 13 + src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 14 ++ src/mesa/drivers/dri/i965/brw_shader.cpp | 1 + src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 13 + 5 files changed, 42 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index a562b8a..a2a5234 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -673,6 +673,7 @@ fs_visitor::type_size(const struct glsl_type *type) case GLSL_TYPE_VOID: case GLSL_TYPE_ERROR: case GLSL_TYPE_INTERFACE: + case GLSL_TYPE_DOUBLE: unreachable(not reached); } diff --git a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp index cb0a079..c64742c 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp @@ -445,6 +445,19 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment *ir) case ir_binop_interpolate_at_offset: case ir_binop_interpolate_at_sample: unreachable(not reached: expression operates on scalars only); + + case ir_unop_pack_double_2x32: + case ir_unop_unpack_double_2x32: + case ir_unop_frexp_sig: + case ir_unop_frexp_exp: + case ir_unop_d2f: + case ir_unop_f2d: + case ir_unop_d2i: + case ir_unop_i2d: + case ir_unop_d2u: + case ir_unop_u2d: + case ir_unop_d2b: + unreachable(no fp64 support yet); } ir-remove(); diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 04e0f9a..7486071 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -1192,6 +1192,20 @@ fs_visitor::visit(ir_expression *ir) case ir_binop_interpolate_at_sample: unreachable(already handled above); break; + + case ir_unop_d2f: + case ir_unop_f2d: + case ir_unop_d2i: + case ir_unop_i2d: + case ir_unop_d2u: + case ir_unop_u2d: + case ir_unop_d2b: + case ir_unop_pack_double_2x32: + case ir_unop_unpack_double_2x32: + case ir_unop_frexp_sig: + case ir_unop_frexp_exp: + unreachable(fp64 todo); + break; } } diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 71146c5..b0e9c82 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -308,6 +308,7 @@ brw_type_for_base_type(const struct glsl_type *type) case GLSL_TYPE_VOID: case GLSL_TYPE_ERROR: case GLSL_TYPE_INTERFACE: + case GLSL_TYPE_DOUBLE: unreachable(not reached); } diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index 562fc30..6154e43 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp @@ -612,6 +612,7 @@ type_size(const struct glsl_type *type) return 0; case GLSL_TYPE_IMAGE: case GLSL_TYPE_VOID: + case GLSL_TYPE_DOUBLE: case GLSL_TYPE_ERROR: case GLSL_TYPE_INTERFACE: unreachable(not reached); @@ -1889,6 +1890,18 @@ vec4_visitor::visit(ir_expression *ir) unreachable(not reached: should not occur in vertex shader); case ir_binop_ldexp: unreachable(not reached: should be handled by ldexp_to_arith()); + case ir_unop_d2f: + case ir_unop_f2d: + case ir_unop_d2i: + case ir_unop_i2d: + case ir_unop_d2u: + case ir_unop_u2d: + case ir_unop_d2b: + case ir_unop_pack_double_2x32: + case ir_unop_unpack_double_2x32: + case ir_unop_frexp_sig: + case ir_unop_frexp_exp: + unreachable(fp64 todo); } } -- 1.9.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/4] i965: Don't emit saturates for instructions without destinations.
On Thu, Feb 19, 2015 at 3:31 PM, Ian Romanick i...@freedesktop.org wrote: On 02/10/2015 11:09 AM, Matt Turner wrote: We were special casing OPCODE_END but no other instructions that have no destination, like OPCODE_KIL, leading us to emitting MOVs with null destinations. Should we (or do we somehow already) handle instructions with null destinations? So... ADD.sat.nz null, g38, g22 Or is that just impossible? I don't think that's possible. The cases I saw were because we were emitting MOV.SAT to copy results of instructions that don't have destinations. :) After I made this change, I grepped all of the output of shader-db and found no more MOVs (without conditional mod) with null destinations. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 4/6] st/mesa: add support for new double opcodes
Not having SQRT is assumed to tacitly mean that RSQ is available. Signed-off-by: Ilia Mirkin imir...@alum.mit.edu --- src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index f57e76b..63b779d 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -849,7 +849,7 @@ glsl_to_tgsi_visitor::get_opcode(ir_instruction *ir, unsigned op, case2iu(ISHR, USHR); - case2fi(SSG, ISSG); + case3fid(SSG, ISSG, DSSG); case3fid(ABS, IABS, DABS); case2iu(IBFE, UBFE); @@ -862,6 +862,10 @@ glsl_to_tgsi_visitor::get_opcode(ir_instruction *ir, unsigned op, case3fid(RSQ, RSQ, DRSQ); case3fid(FRC, FRC, DFRAC); + case3fid(TRUNC, TRUNC, DTRUNC); + case3fid(CEIL, CEIL, DCEIL); + case3fid(FLR, FLR, DFLR); + case3fid(ROUND, ROUND, DROUND); default: break; } -- 2.0.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/6] gallium: add shader cap for dldexp/dfracexp support
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu --- src/gallium/auxiliary/gallivm/lp_bld_limits.h | 1 + src/gallium/auxiliary/tgsi/tgsi_exec.h | 1 + src/gallium/docs/source/screen.rst | 2 ++ src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 ++ src/gallium/drivers/r600/r600_pipe.c | 1 + src/gallium/drivers/radeonsi/si_pipe.c | 1 + src/gallium/drivers/svga/svga_screen.c | 1 + src/gallium/include/pipe/p_defines.h | 1 + 8 files changed, 10 insertions(+) diff --git a/src/gallium/auxiliary/gallivm/lp_bld_limits.h b/src/gallium/auxiliary/gallivm/lp_bld_limits.h index 1af7205..2962360 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_limits.h +++ b/src/gallium/auxiliary/gallivm/lp_bld_limits.h @@ -128,6 +128,7 @@ gallivm_get_shader_param(enum pipe_shader_cap param) return 1; case PIPE_SHADER_CAP_DOUBLES: case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: return 0; } /* if we get here, we missed a shader cap above (and should have seen diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h b/src/gallium/auxiliary/tgsi/tgsi_exec.h index 02ee4c7..609c81b 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_exec.h +++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h @@ -456,6 +456,7 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param) case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: return 1; case PIPE_SHADER_CAP_DOUBLES: + case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: return 1; case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: return 0; diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst index 0cb5425..e0fd1a2 100644 --- a/src/gallium/docs/source/screen.rst +++ b/src/gallium/docs/source/screen.rst @@ -334,6 +334,8 @@ to be 0. operations are supported. * ``PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED``: Whether double precision rounding is supported. If it is, DTRUNC/DCEIL/DFLR/DROUND opcodes may be used. +* ``PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED``: Whether DFRACEXP and + DLDEXP are supported. .. _pipe_compute_cap: diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index 868491c..8546ac8 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -294,6 +294,8 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, return 0; case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: return 0; + case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: + return 0; case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: return 16; /* would be 32 in linked (OpenGL-style) mode */ case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index 447513b..06dca25 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -490,6 +490,7 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e case PIPE_SHADER_CAP_DOUBLES: return 0; case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: return 0; } return 0; diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 4c72045..f8fd3fa 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -424,6 +424,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu return PIPE_SHADER_IR_TGSI; case PIPE_SHADER_CAP_DOUBLES: case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: return 0; } return 0; diff --git a/src/gallium/drivers/svga/svga_screen.c b/src/gallium/drivers/svga/svga_screen.c index a951792..2f2ee2a 100644 --- a/src/gallium/drivers/svga/svga_screen.c +++ b/src/gallium/drivers/svga/svga_screen.c @@ -374,6 +374,7 @@ static int svga_get_shader_param(struct pipe_screen *screen, unsigned shader, en return PIPE_SHADER_IR_TGSI; case PIPE_SHADER_CAP_DOUBLES: case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED return 0; } /* If we get here, we failed to handle a cap above */ diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h index 685e37c..ae173b3 100644 --- a/src/gallium/include/pipe/p_defines.h +++ b/src/gallium/include/pipe/p_defines.h @@ -637,6 +637,7 @@ enum pipe_shader_cap PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS, PIPE_SHADER_CAP_DOUBLES, PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED, /* all rounding modes */ + PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED, }; /** -- 2.0.5
[Mesa-dev] [PATCH 6/6] st/mesa: lower DFRACEXP/DLDEXP when they are not supported
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu --- src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 4 1 file changed, 4 insertions(+) diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index e170217..4d91ca6 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -5775,6 +5775,9 @@ st_link_shader(struct gl_context *ctx, struct gl_shader_program *prog) bool have_dround = pscreen-get_shader_param( pscreen, ptarget, PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED); + bool have_dfrexp = pscreen-get_shader_param( +pscreen, ptarget, +PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED); /* If there are forms of indirect addressing that the driver * cannot handle, perform the lowering pass. @@ -5812,6 +5815,7 @@ st_link_shader(struct gl_context *ctx, struct gl_shader_program *prog) EXP_TO_EXP2 | LOG_TO_LOG2 | LDEXP_TO_ARITH | + (have_dfrexp ? 0 : DFREXP_DLDEXP_TO_ARITH) | CARRY_TO_ARITH | BORROW_TO_ARITH | (have_dround ? 0 : DOPS_TO_DFRAC) | -- 2.0.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 5/6] st/mesa: disable lowering of dops to dfrac when dround is available
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu --- src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index 63b779d..e170217 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -1643,7 +1643,6 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir) emit(ir, TGSI_OPCODE_ABS, result_dst, op[0]); break; case ir_unop_sign: - assert(ir-operands[0]-type-base_type != GLSL_TYPE_DOUBLE); emit(ir, TGSI_OPCODE_SSG, result_dst, op[0]); break; case ir_unop_rcp: @@ -2119,19 +2118,15 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir) emit(ir, TGSI_OPCODE_SNE, result_dst, op[0], st_src_reg_for_float(0.0)); break; case ir_unop_trunc: - assert(ir-operands[0]-type-base_type != GLSL_TYPE_DOUBLE); emit(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]); break; case ir_unop_ceil: - assert(ir-operands[0]-type-base_type != GLSL_TYPE_DOUBLE); emit(ir, TGSI_OPCODE_CEIL, result_dst, op[0]); break; case ir_unop_floor: - assert(ir-operands[0]-type-base_type != GLSL_TYPE_DOUBLE); emit(ir, TGSI_OPCODE_FLR, result_dst, op[0]); break; case ir_unop_round_even: - assert(ir-operands[0]-type-base_type != GLSL_TYPE_DOUBLE); emit(ir, TGSI_OPCODE_ROUND, result_dst, op[0]); break; case ir_unop_fract: @@ -5773,8 +5768,13 @@ st_link_shader(struct gl_context *ctx, struct gl_shader_program *prog) bool progress; exec_list *ir = prog-_LinkedShaders[i]-ir; + gl_shader_stage stage = _mesa_shader_enum_to_shader_stage(prog-_LinkedShaders[i]-Type); const struct gl_shader_compiler_options *options = - ctx-Const.ShaderCompilerOptions[_mesa_shader_enum_to_shader_stage(prog-_LinkedShaders[i]-Type)]; +ctx-Const.ShaderCompilerOptions[stage]; + unsigned ptarget = shader_stage_to_ptarget(stage); + bool have_dround = pscreen-get_shader_param( +pscreen, ptarget, +PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED); /* If there are forms of indirect addressing that the driver * cannot handle, perform the lowering pass. @@ -5814,7 +5814,7 @@ st_link_shader(struct gl_context *ctx, struct gl_shader_program *prog) LDEXP_TO_ARITH | CARRY_TO_ARITH | BORROW_TO_ARITH | - DOPS_TO_DFRAC | + (have_dround ? 0 : DOPS_TO_DFRAC) | (options-EmitNoPow ? POW_TO_EXP2 : 0) | (!ctx-Const.NativeIntegers ? INT_DIV_TO_MUL_RCP : 0) | (options-EmitNoSat ? SAT_TO_CLAMP : 0)); -- 2.0.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/6] gallium: add a cap to enable double rounding opcodes
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu --- src/gallium/auxiliary/gallivm/lp_bld_limits.h | 1 + src/gallium/auxiliary/tgsi/tgsi_exec.h | 2 ++ src/gallium/docs/source/screen.rst | 2 ++ src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 4 src/gallium/drivers/r600/r600_pipe.c | 2 ++ src/gallium/drivers/radeonsi/si_pipe.c | 1 + src/gallium/drivers/svga/svga_screen.c | 1 + src/gallium/include/pipe/p_defines.h | 3 ++- 8 files changed, 15 insertions(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/gallivm/lp_bld_limits.h b/src/gallium/auxiliary/gallivm/lp_bld_limits.h index 8c66f9d..1af7205 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_limits.h +++ b/src/gallium/auxiliary/gallivm/lp_bld_limits.h @@ -127,6 +127,7 @@ gallivm_get_shader_param(enum pipe_shader_cap param) case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: return 1; case PIPE_SHADER_CAP_DOUBLES: + case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: return 0; } /* if we get here, we missed a shader cap above (and should have seen diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h b/src/gallium/auxiliary/tgsi/tgsi_exec.h index 256cf72..02ee4c7 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_exec.h +++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h @@ -457,6 +457,8 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param) return 1; case PIPE_SHADER_CAP_DOUBLES: return 1; + case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + return 0; } /* if we get here, we missed a shader cap above (and should have seen * a compiler warning.) diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst index 373a2fe..0cb5425 100644 --- a/src/gallium/docs/source/screen.rst +++ b/src/gallium/docs/source/screen.rst @@ -332,6 +332,8 @@ to be 0. sampler views. Must not be lower than PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS. * ``PIPE_SHADER_CAP_DOUBLES``: Whether double precision floating-point operations are supported. +* ``PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED``: Whether double precision rounding + is supported. If it is, DTRUNC/DCEIL/DFLR/DROUND opcodes may be used. .. _pipe_compute_cap: diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index edea845..868491c 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -290,6 +290,10 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, return 1; case PIPE_SHADER_CAP_INTEGERS: return 1; + case PIPE_SHADER_CAP_DOUBLES: + return 0; + case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + return 0; case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: return 16; /* would be 32 in linked (OpenGL-style) mode */ case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index a4b7b66..447513b 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -489,6 +489,8 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e } case PIPE_SHADER_CAP_DOUBLES: return 0; + case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + return 0; } return 0; } diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index ec53331..4c72045 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -423,6 +423,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu case PIPE_SHADER_CAP_PREFERRED_IR: return PIPE_SHADER_IR_TGSI; case PIPE_SHADER_CAP_DOUBLES: + case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: return 0; } return 0; diff --git a/src/gallium/drivers/svga/svga_screen.c b/src/gallium/drivers/svga/svga_screen.c index e468a2f..a951792 100644 --- a/src/gallium/drivers/svga/svga_screen.c +++ b/src/gallium/drivers/svga/svga_screen.c @@ -373,6 +373,7 @@ static int svga_get_shader_param(struct pipe_screen *screen, unsigned shader, en case PIPE_SHADER_CAP_PREFERRED_IR: return PIPE_SHADER_IR_TGSI; case PIPE_SHADER_CAP_DOUBLES: + case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: return 0; } /* If we get here, we failed to handle a cap above */ diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h index 1785043..685e37c 100644 --- a/src/gallium/include/pipe/p_defines.h +++ b/src/gallium/include/pipe/p_defines.h @@ -635,7 +635,8 @@ enum pipe_shader_cap PIPE_SHADER_CAP_PREFERRED_IR, PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED, PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS, - PIPE_SHADER_CAP_DOUBLES + PIPE_SHADER_CAP_DOUBLES, + PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED, /* all rounding
[Mesa-dev] [PATCH 1/6] gallium: add some more double opcodes to avoid unnecessary lowering
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
src/gallium/auxiliary/tgsi/tgsi_info.c | 5
src/gallium/docs/source/tgsi.rst | 39 ++
src/gallium/include/pipe/p_shader_tokens.h | 7 +-
3 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c
b/src/gallium/auxiliary/tgsi/tgsi_info.c
index d04f9da..4d838fd 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
@@ -257,6 +257,11 @@ static const struct tgsi_opcode_info
opcode_info[TGSI_OPCODE_LAST] =
{ 1, 1, 0, 0, 0, 0, COMP, D2U, TGSI_OPCODE_D2U },
{ 1, 1, 0, 0, 0, 0, COMP, U2D, TGSI_OPCODE_U2D },
{ 1, 1, 0, 0 ,0, 0, COMP, DRSQ, TGSI_OPCODE_DRSQ },
+ { 1, 1, 0, 0, 0, 0, COMP, DTRUNC, TGSI_OPCODE_DTRUNC },
+ { 1, 1, 0, 0, 0, 0, COMP, DCEIL, TGSI_OPCODE_DCEIL },
+ { 1, 1, 0, 0, 0, 0, COMP, DFLR, TGSI_OPCODE_DFLR },
+ { 1, 1, 0, 0, 0, 0, COMP, DROUND, TGSI_OPCODE_DROUND },
+ { 1, 1, 0, 0, 0, 0, COMP, DSSG, TGSI_OPCODE_DSSG },
};
const struct tgsi_opcode_info *
diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst
index e20af79..15f1e9f 100644
--- a/src/gallium/docs/source/tgsi.rst
+++ b/src/gallium/docs/source/tgsi.rst
@@ -1861,6 +1861,45 @@ two-component vectors with doubled precision in each
component.
dst.zw = src.zw - \lfloor src.zw\rfloor
+.. opcode:: DTRUNC - Truncate
+
+.. math::
+
+ dst.xy = trunc(src.xy)
+
+ dst.zw = trunc(src.zw)
+
+.. opcode:: DCEIL - Ceiling
+
+.. math::
+
+ dst.xy = \lceil src.xy\rceil
+
+ dst.zw = \lceil src.zw\rceil
+
+.. opcode:: DFLR - Floor
+
+.. math::
+
+ dst.xy = \lfloor src.xy\rfloor
+
+ dst.zw = \lfloor src.zw\rfloor
+
+.. opcode:: DROUND - Fraction
+
+.. math::
+
+ dst.xy = round(src.xy)
+
+ dst.zw = round(src.zw)
+
+.. opcode:: DSSG - Set Sign
+
+.. math::
+
+ dst.xy = (src.xy 0) ? 1 : (src.xy 0) ? -1 : 0
+
+ dst.zw = (src.zw 0) ? 1 : (src.zw 0) ? -1 : 0
.. opcode:: DFRACEXP - Convert Number to Fractional and Integral Components
diff --git a/src/gallium/include/pipe/p_shader_tokens.h
b/src/gallium/include/pipe/p_shader_tokens.h
index fc41cc9..95ac590 100644
--- a/src/gallium/include/pipe/p_shader_tokens.h
+++ b/src/gallium/include/pipe/p_shader_tokens.h
@@ -519,7 +519,12 @@ struct tgsi_property_data {
#define TGSI_OPCODE_D2U 215
#define TGSI_OPCODE_U2D 216
#define TGSI_OPCODE_DRSQ217 /* eg, cayman also has DRSQ */
-#define TGSI_OPCODE_LAST218
+#define TGSI_OPCODE_DTRUNC 218 /* nvc0 */
+#define TGSI_OPCODE_DCEIL 219 /* nvc0 */
+#define TGSI_OPCODE_DFLR220 /* nvc0 */
+#define TGSI_OPCODE_DROUND 221 /* nvc0 */
+#define TGSI_OPCODE_DSSG222
+#define TGSI_OPCODE_LAST223
#define TGSI_SAT_NONE0 /* do not saturate */
#define TGSI_SAT_ZERO_ONE1 /* clamp to [0,1] */
--
2.0.5
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[Mesa-dev] [PATCH 1/2] tgsi/scan: add uses_doubles to tgsi scanner
From: Dave Airlie airl...@redhat.com
This allows drivers to work out if a shader contains any
double opcodes easily.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/auxiliary/tgsi/tgsi_scan.c | 4
src/gallium/auxiliary/tgsi/tgsi_scan.h | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c
b/src/gallium/auxiliary/tgsi/tgsi_scan.c
index e6011d2..e19b8a1 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
@@ -97,6 +97,10 @@ tgsi_scan_shader(const struct tgsi_token *tokens,
assert(fullinst-Instruction.Opcode TGSI_OPCODE_LAST);
info-opcode_count[fullinst-Instruction.Opcode]++;
+if (fullinst-Instruction.Opcode = TGSI_OPCODE_F2D ||
+fullinst-Instruction.Opcode TGSI_OPCODE_DRSQ)
+ info-uses_doubles = true;
+
for (i = 0; i fullinst-Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *src =
fullinst-Src[i];
diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.h
b/src/gallium/auxiliary/tgsi/tgsi_scan.h
index 5dc9267..daa73cc 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.h
@@ -86,7 +86,7 @@ struct tgsi_shader_info
boolean writes_viewport_index;
boolean writes_layer;
boolean is_msaa_sampler[PIPE_MAX_SAMPLERS];
-
+ boolean uses_doubles; /** uses any of the double instructions */
unsigned clipdist_writemask;
unsigned culldist_writemask;
unsigned num_written_culldistance;
--
1.9.3
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Re: [Mesa-dev] [PATCH] fp64: disable varying packing for doubles.
On Thu, Feb 19, 2015 at 9:43 PM, Dave Airlie airl...@gmail.com wrote:
From: Dave Airlie airl...@redhat.com
I'm not sure we really care about this, but we need to
write better support if we do. For now just disable it.
piglit test:
tests/spec/arb_gpu_shader_fp64/execution/vs-out-fs-in-double-2.shader_test
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/glsl/lower_packed_varyings.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/glsl/lower_packed_varyings.cpp
b/src/glsl/lower_packed_varyings.cpp
index 5e844c7..3c9cbec 100644
--- a/src/glsl/lower_packed_varyings.cpp
+++ b/src/glsl/lower_packed_varyings.cpp
@@ -592,6 +592,9 @@ lower_packed_varyings_visitor::needs_lowering(ir_variable
*var)
return false;
const glsl_type *type = var-type;
+ /* don't attempt to pack double varyings yet */
+ if (type-base_type == GLSL_TYPE_DOUBLE)
+ return false;
Not sure, but I _think_ type can be an array here... (or even worse, a
struct... hopefully not). Should be simple to whip up some piglits. If
I'm right on the array, you can do type-without_array(). If it can
also be a struct, then maybe -contains_double()?
if (this-gs_input_vertices != 0) {
assert(type-is_array());
type = type-element_type();
--
1.9.3
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[Mesa-dev] [PATCH 1/2] nir: add missing GLSL_TYPE_DOUBLE case in type_size()
To silence compiler warning about unhandled switch case. --- src/glsl/nir/nir_lower_io.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/glsl/nir/nir_lower_io.c b/src/glsl/nir/nir_lower_io.c index ddbc249..23499e5 100644 --- a/src/glsl/nir/nir_lower_io.c +++ b/src/glsl/nir/nir_lower_io.c @@ -49,6 +49,7 @@ type_size(const struct glsl_type *type) case GLSL_TYPE_UINT: case GLSL_TYPE_INT: case GLSL_TYPE_FLOAT: + case GLSL_TYPE_DOUBLE: case GLSL_TYPE_BOOL: return glsl_get_components(type); case GLSL_TYPE_ARRAY: -- 1.9.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] st/mesa: add GSL_TYPE_DOUBLE, new ir_unop_* switch cases
To silence compiler warnings about unhandled switch cases.
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 12
1 file changed, 12 insertions(+)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 3dac004..9969fac 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -974,6 +974,7 @@ type_size(const struct glsl_type *type)
case GLSL_TYPE_UINT:
case GLSL_TYPE_INT:
case GLSL_TYPE_FLOAT:
+ case GLSL_TYPE_DOUBLE:
case GLSL_TYPE_BOOL:
if (type-is_matrix()) {
return type-matrix_columns;
@@ -2025,6 +2026,17 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir)
case ir_binop_ldexp:
case ir_binop_carry:
case ir_binop_borrow:
+ case ir_unop_d2f:
+ case ir_unop_f2d:
+ case ir_unop_d2i:
+ case ir_unop_i2d:
+ case ir_unop_d2u:
+ case ir_unop_u2d:
+ case ir_unop_d2b:
+ case ir_unop_pack_double_2x32:
+ case ir_unop_unpack_double_2x32:
+ case ir_unop_frexp_sig:
+ case ir_unop_frexp_exp:
/* This operation is not supported, or should have already been handled.
*/
assert(!Invalid ir opcode in glsl_to_tgsi_visitor::visit());
--
1.9.1
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[Mesa-dev] [Bug 89199] u_math.h:591:4: error: implicit declaration of function 'ffsll'
https://bugs.freedesktop.org/show_bug.cgi?id=89199 --- Comment #2 from Brian Paul bri...@vmware.com --- Hi Vinson, Is that with gcc? Which compiler version? I'll attach a patch proposal for you to try... -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 89199] u_math.h:591:4: error: implicit declaration of function 'ffsll'
https://bugs.freedesktop.org/show_bug.cgi?id=89199 --- Comment #3 from Brian Paul bri...@vmware.com --- Created attachment 113670 -- https://bugs.freedesktop.org/attachment.cgi?id=113670action=edit proposed patch If you're using gcc, maybe a gcc version check would be better. This patch also assumes the radeonsi driver isn't used on NetBSD (the only user of u_bit_scan64() at this time.) -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] mesa: Check that draw buffers are valid for glDrawBuffers on GLES3
Section 4.2 (Whole Framebuffer Operations) of the OpenGL 3.0 specification
says:
Each buffer listed in bufs must be BACK, NONE, or one of the values from
table 4.3 (NONE, COLOR_ATTACHMENTi).
Fixes 1 dEQP test:
* dEQP-GLES3.functional.negative_api.buffer.draw_buffers
---
src/mesa/main/buffers.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/mesa/main/buffers.c b/src/mesa/main/buffers.c
index a2d02d5..e5076e9 100644
--- a/src/mesa/main/buffers.c
+++ b/src/mesa/main/buffers.c
@@ -336,6 +336,20 @@ _mesa_DrawBuffers(GLsizei n, const GLenum *buffers)
/* complicated error checking... */
for (output = 0; output n; output++) {
+ /* Section 4.2 (Whole Framebuffer Operations) of the OpenGL 3.0
+ * specification says:
+ *
+ * Each buffer listed in bufs must be BACK, NONE, or one of the
values
+ * from table 4.3 (NONE, COLOR_ATTACHMENTi)
+ */
+ if (_mesa_is_gles3(ctx) buffers[output] != GL_NONE
+ buffers[output] != GL_BACK
+ (buffers[output] GL_COLOR_ATTACHMENT0 ||
+ buffers[output] = GL_COLOR_ATTACHMENT0 +
ctx-Const.MaxColorAttachments)) {
+ _mesa_error(ctx, GL_INVALID_ENUM, glDrawBuffers(buffer));
+ return;
+ }
+
if (buffers[output] == GL_NONE) {
destMask[output] = 0x0;
}
--
2.1.3
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Re: [Mesa-dev] [PATCH v2] mesa: Check first that draw buffers are valid for glDrawBuffers on GLES3
On 02/18/2015 09:09 PM, Matt Turner wrote: On Tue, Jan 13, 2015 at 3:29 AM, Eduardo Lima Mitev el...@igalia.com wrote: This patch was updated and is pending review. I think we're waiting on a new version with Tapani's comment addressed. The patch looks right, FWIW. Hi Matt, I completely missed Tappani's comment, sorry. I just sent a new version of the patch addressing those: http://lists.freedesktop.org/archives/mesa-dev/2015-February/077290.html Thank you, Eduardo ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa: Check that draw buffers are valid for glDrawBuffers on GLES3
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Re: [Mesa-dev] [Mesa-announce] Mesa 10.3 release candidate 1
On Thu, Feb 19, 2015 at 5:53 AM, Lucas Stach l.st...@pengutronix.de wrote: Am Freitag, den 07.11.2014, 01:19 -0800 schrieb Matt Turner: On Fri, Nov 7, 2014 at 1:07 AM, Thierry Vignaud thierry.vign...@gmail.com wrote: On 5 November 2014 04:44, Matt Turner matts...@gmail.com wrote: I tried to reproduce this today and couldn't. (...) Thanks. Maybe you could give a little more information, like an error message or something? Same error as Thierry reported in this thread in August: Unfortunately Thierry's was from a re-run of make, so it wasn't useful. No It wasn't a re-run! It was a clean build in our build system with make -jXX with XX auto set to the number of cores and is always reproducable given enough cores Oh, weird. I've gone over this all and can't spot the problem. The dependencies look fine. I tried automake-1.13 and 1.14, and make-3.82 and 4.0. Maybe I'll have more luck on a 40 core system. As already explained, in order to be able to reproduce, you must either have a large system or force make -j to a high value (eg: -j24) Did you see the rest of the thread where I said I couldn't reproduce on a 40 core system? Perhaps someone who can reproduce could try to take a look? Ok, here is what happens: This failure is only reproducible with the following config options: --disable-shared-glapi --disable-gles1 --disable-gles2 Which makes it pretty obvious what is to be blamed here. With those options set no installable libraries will be build below src/mapi, the only target is a static glapi.la. As lib_LTLIBRARIES is empty in that case the install-mesa-links target has no dependencies and gets executed immediately. This fails as it races with the compilation to create the .libs dir. As the install-mesa-links target works perfectly fine with an empty lib_LTLIBRARIES the fix is simply to not depends on the .libs directory for the state file of this target. A patch is on the list. Regards, Lucas -- Pengutronix e.K. | Lucas Stach | Industrial Linux Solutions | http://www.pengutronix.de/ | Thanks Lucas. That makes a lot of sense. I never suspected that the reporters were using non-default options and forgot to say so. I'll take a look at the patch. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radeonsi: don't use SQC_CACHES to flush ICACHE and KCACHE on SI
On Thu, Feb 19, 2015 at 7:10 AM, Marek Olšák mar...@gmail.com wrote:
From: Marek Olšák marek.ol...@amd.com
This reverts 73c2b0d18c51459697d8ec194ecfc4438c98c139.
It doesn't seem to be reliable. It's probably missing a wait packet or
something, because it's just a register write and doesn't wait for anything.
SURFACE_SYNC at least seems to wait until the flush is done. Just guessing.
Let's not complicate things and revert this.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88561
Cc: 10.5 mesa-sta...@lists.freedesktop.org
Reviewed-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/drivers/radeonsi/si_state_draw.c | 29
+++-
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 128ea04..511bea2 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -367,24 +367,21 @@ void si_emit_cache_flush(struct r600_common_context
*sctx, struct r600_atom *ato
{
struct radeon_winsys_cs *cs = sctx-rings.gfx.cs;
uint32_t cp_coher_cntl = 0;
- uint32_t sqc_caches = 0;
uint32_t compute =
PKT3_SHADER_TYPE_S(!!(sctx-flags SI_CONTEXT_FLAG_COMPUTE));
/* SI has a bug that it always flushes ICACHE and KCACHE if either
-* bit is set. An alternative way is to write SQC_CACHES. */
- if (sctx-chip_class == SI
- sctx-flags BOTH_ICACHE_KCACHE
- (sctx-flags BOTH_ICACHE_KCACHE) != BOTH_ICACHE_KCACHE) {
- sqc_caches =
- S_008C08_INST_INVALIDATE(!!(sctx-flags
SI_CONTEXT_INV_ICACHE)) |
- S_008C08_DATA_INVALIDATE(!!(sctx-flags
SI_CONTEXT_INV_KCACHE));
- } else {
- if (sctx-flags SI_CONTEXT_INV_ICACHE)
- cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
- if (sctx-flags SI_CONTEXT_INV_KCACHE)
- cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
- }
+* bit is set. An alternative way is to write SQC_CACHES, but that
+* doesn't seem to work reliably. Since the bug doesn't affect
+* correctness (it only does more work than necessary) and
+* the performance impact is likely negligible, there is no plan
+* to fix it.
+*/
+
+ if (sctx-flags SI_CONTEXT_INV_ICACHE)
+ cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
+ if (sctx-flags SI_CONTEXT_INV_KCACHE)
+ cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
if (sctx-flags SI_CONTEXT_INV_TC_L1)
cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
@@ -451,10 +448,6 @@ void si_emit_cache_flush(struct r600_common_context
*sctx, struct r600_atom *ato
* It looks like SURFACE_SYNC flushes caches immediately and doesn't
* wait for any engines. This should be last.
*/
- if (sqc_caches) {
- r600_write_config_reg(cs, R_008C08_SQC_CACHES, sqc_caches);
- cs-buf[cs-cdw-3] |= compute; /* set the compute bit in the
header */
- }
if (cp_coher_cntl) {
if (sctx-chip_class = CIK) {
radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) |
compute);
--
2.1.0
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Re: [Mesa-dev] [PATCH] install-lib-links: don't depend on .libs directory
On Thu, Feb 19, 2015 at 5:52 AM, Lucas Stach l.st...@pengutronix.de wrote: This snippet can be included in Makefiles that may, depending on the project configuration, not actually build any installable libraries. In that case we don't have anything to depend on and this part of the makefile may be executed before the .libs directory is created, so do not depend on it being there. Signed-off-by: Lucas Stach l.st...@pengutronix.de Cc: 10.3 10.4 mesa-sta...@lists.freedesktop.org --- install-lib-links.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/install-lib-links.mk b/install-lib-links.mk index 6976ca4911ab..3545b268ebd1 100644 --- a/install-lib-links.mk +++ b/install-lib-links.mk @@ -3,9 +3,9 @@ if BUILD_SHARED if HAVE_COMPAT_SYMLINKS -all-local : .libs/install-mesa-links +all-local : .install-mesa-links -.libs/install-mesa-links : $(lib_LTLIBRARIES) +.install-mesa-links : $(lib_LTLIBRARIES) $(AM_V_GEN)$(MKDIR_P) $(top_builddir)/$(LIB_DIR); \ for f in $(join $(addsuffix .libs/,$(dir $(lib_LTLIBRARIES))),$(notdir $(lib_LTLIBRARIES:%.la=%.$(LIB_EXT)*))); do \ if test -h .libs/$$f; then \ -- 2.1.4 Thanks a bunch Lucas. Reviewed-by: Matt Turner matts...@gmail.com I'll commit this and tag it for 10.5 as well. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/4] i965: Don't emit saturates for instructions without destinations.
On 02/10/2015 11:09 AM, Matt Turner wrote:
We were special casing OPCODE_END but no other instructions that have no
destination, like OPCODE_KIL, leading us to emitting MOVs with null
destinations.
Should we (or do we somehow already) handle instructions with null
destinations? So...
ADD.sat.nz null, g38, g22
Or is that just impossible?
total instructions in shared programs: 5950886 - 5947182 (-0.06%)
instructions in affected programs: 139700 - 135996 (-2.65%)
helped:904
---
src/mesa/drivers/dri/i965/brw_fs_fp.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_vec4_vp.cpp | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
index 7f2874d..dd3d331 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
@@ -517,7 +517,7 @@ fs_visitor::emit_fragment_program_code()
/* To handle saturates, we emit a MOV with a saturate bit, which
* optimization should fold into the preceding instructions when safe.
*/
- if (fpi-Opcode != OPCODE_END) {
+ if (_mesa_num_inst_dst_regs(fpi-Opcode) != 0) {
fs_reg real_dst = get_fp_dst_reg(fpi-DstReg);
for (int i = 0; i 4; i++) {
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
index 85f2de5..434f032 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
@@ -387,7 +387,7 @@ vec4_vs_visitor::emit_program_code()
}
/* Copy the temporary back into the actual destination register. */
- if (vpi-Opcode != OPCODE_END) {
+ if (_mesa_num_inst_dst_regs(vpi-Opcode) != 0) {
emit(MOV(get_vp_dst_reg(vpi-DstReg), src_reg(dst)));
}
}
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[Mesa-dev] [PATCH] fp64: disable varying packing for doubles.
From: Dave Airlie airl...@redhat.com
I'm not sure we really care about this, but we need to
write better support if we do. For now just disable it.
piglit test:
tests/spec/arb_gpu_shader_fp64/execution/vs-out-fs-in-double-2.shader_test
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/glsl/lower_packed_varyings.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/glsl/lower_packed_varyings.cpp
b/src/glsl/lower_packed_varyings.cpp
index 5e844c7..3c9cbec 100644
--- a/src/glsl/lower_packed_varyings.cpp
+++ b/src/glsl/lower_packed_varyings.cpp
@@ -592,6 +592,9 @@ lower_packed_varyings_visitor::needs_lowering(ir_variable
*var)
return false;
const glsl_type *type = var-type;
+ /* don't attempt to pack double varyings yet */
+ if (type-base_type == GLSL_TYPE_DOUBLE)
+ return false;
if (this-gs_input_vertices != 0) {
assert(type-is_array());
type = type-element_type();
--
1.9.3
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Re: [Mesa-dev] [PATCH 2/4] i965: Use greater-equal cmod to implement maximum.
This patch is
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
On 02/10/2015 11:09 AM, Matt Turner wrote:
The docs specifically call out SEL with .l and .ge as the
implementations of MIN and MAX respectively. Among other things, SEL
with these conditional mods are commutative.
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 5 -
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp| 6 +++---
src/mesa/drivers/dri/i965/brw_vec4_vp.cpp | 4 ++--
src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp | 2 +-
4 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 6cddcf5..bca2139 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -322,6 +322,9 @@ void
fs_visitor::emit_minmax(enum brw_conditional_mod conditionalmod, const
fs_reg dst,
const fs_reg src0, const fs_reg src1)
{
+ assert(conditionalmod == BRW_CONDITIONAL_GE ||
+ conditionalmod == BRW_CONDITIONAL_L);
+
fs_inst *inst;
if (brw-gen = 6) {
@@ -1948,7 +1951,7 @@ fs_visitor::rescale_texcoord(fs_reg coordinate, int
coord_components,
chan = offset(chan, i);
inst = emit(BRW_OPCODE_SEL, chan, chan, fs_reg(0.0f));
- inst-conditional_mod = BRW_CONDITIONAL_G;
+ inst-conditional_mod = BRW_CONDITIONAL_GE;
/* Our parameter comes in as 1.0/width or 1.0/height,
* because that's what people normally want for doing
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index e6a7ed0..d13c716 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -513,7 +513,7 @@ vec4_visitor::emit_unpack_snorm_4x8(const dst_reg dst,
src_reg src0)
emit(MUL(scaled, src_reg(f), src_reg(1.0f / 127.0f)));
dst_reg max(this, glsl_type::vec4_type);
- emit_minmax(BRW_CONDITIONAL_G, max, src_reg(scaled), src_reg(-1.0f));
+ emit_minmax(BRW_CONDITIONAL_GE, max, src_reg(scaled), src_reg(-1.0f));
emit_minmax(BRW_CONDITIONAL_L, dst, src_reg(max), src_reg(1.0f));
}
@@ -541,7 +541,7 @@ void
vec4_visitor::emit_pack_snorm_4x8(const dst_reg dst, const src_reg src0)
{
dst_reg max(this, glsl_type::vec4_type);
- emit_minmax(BRW_CONDITIONAL_G, max, src0, src_reg(-1.0f));
+ emit_minmax(BRW_CONDITIONAL_GE, max, src0, src_reg(-1.0f));
dst_reg min(this, glsl_type::vec4_type);
emit_minmax(BRW_CONDITIONAL_L, min, src_reg(max), src_reg(1.0f));
@@ -1673,7 +1673,7 @@ vec4_visitor::visit(ir_expression *ir)
emit_minmax(BRW_CONDITIONAL_L, result_dst, op[0], op[1]);
break;
case ir_binop_max:
- emit_minmax(BRW_CONDITIONAL_G, result_dst, op[0], op[1]);
+ emit_minmax(BRW_CONDITIONAL_GE, result_dst, op[0], op[1]);
break;
case ir_binop_pow:
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
index 434f032..e2d4b7c 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
@@ -227,7 +227,7 @@ vec4_vs_visitor::emit_program_code()
/* if (tmp.y 0) tmp.y = 0; */
src_reg tmp_y = swizzle(src[0], BRW_SWIZZLE_);
result.writemask = WRITEMASK_Z;
- emit_minmax(BRW_CONDITIONAL_G, result, tmp_y, src_reg(0.0f));
+ emit_minmax(BRW_CONDITIONAL_GE, result, tmp_y, src_reg(0.0f));
src_reg clamped_y(result);
clamped_y.swizzle = BRW_SWIZZLE_;
@@ -314,7 +314,7 @@ vec4_vs_visitor::emit_program_code()
}
case OPCODE_MAX:
- emit_minmax(BRW_CONDITIONAL_G, dst, src[0], src[1]);
+ emit_minmax(BRW_CONDITIONAL_GE, dst, src[0], src[1]);
break;
case OPCODE_MIN:
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp
index 72b6ef0..a48b730 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp
@@ -97,7 +97,7 @@ vec4_vs_visitor::emit_prolog()
dst.type = brw_type_for_base_type(glsl_type::vec4_type);
emit(MOV(dst, src_reg(reg_d)));
emit(MUL(dst, src_reg(dst), src_reg(es3_normalize_factor)));
- emit_minmax(BRW_CONDITIONAL_G, dst, src_reg(dst),
src_reg(-1.0f));
+ emit_minmax(BRW_CONDITIONAL_GE, dst, src_reg(dst),
src_reg(-1.0f));
} else {
/* The following equations are from the OpenGL 3.2
specification:
*
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Re: [Mesa-dev] [PATCH 1/4] i965: Don't emit saturates for instructions without destinations.
On 02/19/2015 03:38 PM, Matt Turner wrote: On Thu, Feb 19, 2015 at 3:31 PM, Ian Romanick i...@freedesktop.org wrote: On 02/10/2015 11:09 AM, Matt Turner wrote: We were special casing OPCODE_END but no other instructions that have no destination, like OPCODE_KIL, leading us to emitting MOVs with null destinations. Should we (or do we somehow already) handle instructions with null destinations? So... ADD.sat.nz null, g38, g22 Or is that just impossible? I don't think that's possible. The cases I saw were because we were emitting MOV.SAT to copy results of instructions that don't have destinations. :) After I made this change, I grepped all of the output of shader-db and found no more MOVs (without conditional mod) with null destinations. That's about what I figured. This patch is Reviewed-by: Ian Romanick ian.d.roman...@intel.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: just avoid warnings with fp64
Looks reasonable, if it's going to be a while before an i965 backend is ready.. Reviewed-by: Chris Forbes chr...@ijw.co.nz On Fri, Feb 20, 2015 at 12:38 PM, Dave Airlie airl...@gmail.com wrote: This just fills in some blanks to avoid warnings in the i965 driver. Signed-off-by: Dave Airlie airl...@redhat.com --- src/mesa/drivers/dri/i965/brw_fs.cpp | 1 + src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp | 13 + src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 14 ++ src/mesa/drivers/dri/i965/brw_shader.cpp | 1 + src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 13 + 5 files changed, 42 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index a562b8a..a2a5234 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -673,6 +673,7 @@ fs_visitor::type_size(const struct glsl_type *type) case GLSL_TYPE_VOID: case GLSL_TYPE_ERROR: case GLSL_TYPE_INTERFACE: + case GLSL_TYPE_DOUBLE: unreachable(not reached); } diff --git a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp index cb0a079..c64742c 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp @@ -445,6 +445,19 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment *ir) case ir_binop_interpolate_at_offset: case ir_binop_interpolate_at_sample: unreachable(not reached: expression operates on scalars only); + + case ir_unop_pack_double_2x32: + case ir_unop_unpack_double_2x32: + case ir_unop_frexp_sig: + case ir_unop_frexp_exp: + case ir_unop_d2f: + case ir_unop_f2d: + case ir_unop_d2i: + case ir_unop_i2d: + case ir_unop_d2u: + case ir_unop_u2d: + case ir_unop_d2b: + unreachable(no fp64 support yet); } ir-remove(); diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 04e0f9a..7486071 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -1192,6 +1192,20 @@ fs_visitor::visit(ir_expression *ir) case ir_binop_interpolate_at_sample: unreachable(already handled above); break; + + case ir_unop_d2f: + case ir_unop_f2d: + case ir_unop_d2i: + case ir_unop_i2d: + case ir_unop_d2u: + case ir_unop_u2d: + case ir_unop_d2b: + case ir_unop_pack_double_2x32: + case ir_unop_unpack_double_2x32: + case ir_unop_frexp_sig: + case ir_unop_frexp_exp: + unreachable(fp64 todo); + break; } } diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 71146c5..b0e9c82 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -308,6 +308,7 @@ brw_type_for_base_type(const struct glsl_type *type) case GLSL_TYPE_VOID: case GLSL_TYPE_ERROR: case GLSL_TYPE_INTERFACE: + case GLSL_TYPE_DOUBLE: unreachable(not reached); } diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index 562fc30..6154e43 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp @@ -612,6 +612,7 @@ type_size(const struct glsl_type *type) return 0; case GLSL_TYPE_IMAGE: case GLSL_TYPE_VOID: + case GLSL_TYPE_DOUBLE: case GLSL_TYPE_ERROR: case GLSL_TYPE_INTERFACE: unreachable(not reached); @@ -1889,6 +1890,18 @@ vec4_visitor::visit(ir_expression *ir) unreachable(not reached: should not occur in vertex shader); case ir_binop_ldexp: unreachable(not reached: should be handled by ldexp_to_arith()); + case ir_unop_d2f: + case ir_unop_f2d: + case ir_unop_d2i: + case ir_unop_i2d: + case ir_unop_d2u: + case ir_unop_u2d: + case ir_unop_d2b: + case ir_unop_pack_double_2x32: + case ir_unop_unpack_double_2x32: + case ir_unop_frexp_sig: + case ir_unop_frexp_exp: + unreachable(fp64 todo); } } -- 1.9.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 10/32] i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().
I'm still a little pensive. But Reviewed-by: Jason Ekstrand jason.ekstr...@intel.com Now for a little aside. I have come to the conclusion that I made a grave mistake when I did the LOAD_PAYLOAD stuff. In retrospect, I should have just subclassed fs_inst for load_payload. The problem is that we need to snag a bunch of information for the sources when we create the load_payload. In particular, we need to know the width of the source so that we know how much space it consumes in the payload and we need to know the information required to properly re-create the mov such as force_sechalf and force_writemask_all. Really, in order to do things properly, we need to gather this information *before* we do any optimizations. The nasty pile of code that you're editing together with the effective_width parameter is a lame attempt to capture/reconstruct this information. Really, we should just subclass, capture the information up-front, and do it properly. --Jason On Thu, Feb 19, 2015 at 1:53 PM, Jason Ekstrand ja...@jlekstrand.net wrote: On Thu, Feb 19, 2015 at 1:25 PM, Francisco Jerez curroje...@riseup.net wrote: Jason Ekstrand ja...@jlekstrand.net writes: On Thu, Feb 19, 2015 at 12:13 PM, Francisco Jerez curroje...@riseup.net wrote: Jason Ekstrand ja...@jlekstrand.net writes: On Fri, Feb 6, 2015 at 4:01 PM, Francisco Jerez curroje...@riseup.net wrote: Hey Matt, Matt Turner matts...@gmail.com writes: On Fri, Feb 6, 2015 at 6:42 AM, Francisco Jerez curroje...@riseup.net wrote: MRFs cannot be read from anyway so they cannot possibly be a valid source of LOAD_PAYLOAD. --- The function only seems to test inst-dst.file == MRF. I don't see any code for handling MRF sources. What am I missing? That test is for handling MRF sources -- More precisely, it's collecting the writemask and half flags for MRF writes, which can only possibly be useful if we're going to use them later on to read something out of an MRF into a payload, which we shouldn't be doing in the first place. Aside from simplifying the function somewhat, that allows us to drop the 16 register gap reserved for MRFs at register offset zero, what will allow us to drop the vgrf_to_reg[] offset calculation completely (also in split_virtual_grfs()) in a future patch (not sent for review yet). No, we do read from MRF's sort-of... Send messages have an implicit read from an MRF. Heh, and that's pretty much the only way you read from it. This was written precicely so that we could use LOAD_PAYLOAD to build MRF payloads. We do on pre-GEN6. I'm aware, but you don't need any of this meta-data to LOAD_PAYLOAD *into* an MRF, and LOAD_PAYLOAD with an MRF as source should be illegal anyway. And no one is using it that way. All of the metadata checks you are deleting are checks on the *destination*. Didn't you write this code yourself? The only use for the collected metadata is initializing the instruction flags of the MOVs subsequent LOAD_PAYLOAD instructions are lowered to, based on the metadata already collected for its source registers, which can never be MRFs, so the metadata you collect from MRF writes is never actually used. Right... I misred something initially. Yes, we should never be tracking MRF's as a source of a LOAD_PAYLOAD. I'll give it a better look a bit later, but it looks better. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] glapi: Do not use backtrace on FreeBSD.
On Thu, Feb 5, 2015 at 4:02 AM, Ian Romanick i...@freedesktop.org wrote: On 01/24/2015 05:46 AM, Vinson Lee wrote: Fix build error. CCLD libGL.la libglapi.a(glapi_libglapi_la-glapi_gentable.o): In function `__glapi_gentable_NoOp': glapi_gentable.c:76: undefined reference to `backtrace' Signed-off-by: Vinson Lee v...@freedesktop.org --- src/mapi/glapi/gen/gl_gentable.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mapi/glapi/gen/gl_gentable.py b/src/mapi/glapi/gen/gl_gentable.py index 06a5ebf..fb578e3 100644 --- a/src/mapi/glapi/gen/gl_gentable.py +++ b/src/mapi/glapi/gen/gl_gentable.py @@ -42,7 +42,7 @@ header = /* GLXEXT is the define used in the xserver when the GLX extension i #endif #if (defined(GLXEXT) defined(HAVE_BACKTRACE)) \\ - || (!defined(GLXEXT) defined(DEBUG) !defined(__CYGWIN__) !defined(__MINGW32__) !defined(__OpenBSD__) !defined(__NetBSD__) !defined(__DragonFly__)) + || (!defined(GLXEXT) defined(DEBUG) !defined(__CYGWIN__) !defined(__MINGW32__) !defined(__OpenBSD__) !defined(__NetBSD__) !defined(__DragonFly__) !defined(__FreeBSD__)) #define USE_BACKTRACE #endif It seems weird that we need all the BSDs in this check. Is configure setting HAVE_BACKTRACE mistakenly? Or is this logic just broken? Does #if defined(HAVE_BACKTRACE) (defined(GLXEXT) || defined(DEBUG)) work everywhere? Yes, it works. I tested FreeBSD and MinGW builds. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] r600g: add doubles support for CAYMAN
From: Dave Airlie airl...@redhat.com
Only a subset of AMD GPUs supported by r600g support doubles,
CAYMAN and CYPRESS are probably all we'll try and support, however
I don't have a CYPRESS so ignore that for now.
This disables SB support for doubles, as we think we need to
make the scheduler smarter to introduce delay slots.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/r600/r600_asm.c| 14 ++
src/gallium/drivers/r600/r600_asm.h| 15 ++
src/gallium/drivers/r600/r600_isa.h| 8 +-
src/gallium/drivers/r600/r600_pipe.c | 2 +
src/gallium/drivers/r600/r600_shader.c | 389 -
src/gallium/drivers/r600/r600_shader.h | 2 +
6 files changed, 424 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
index 79e7f74..dc26b63 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -252,6 +252,12 @@ static int alu_uses_rel(struct r600_bytecode *bc, struct
r600_bytecode_alu *alu)
return 0;
}
+static int is_alu_64bit_inst(struct r600_bytecode *bc, struct
r600_bytecode_alu *alu)
+{
+ const struct alu_op_info *op = r600_isa_alu(alu-op);
+ return (op-flags AF_64);
+}
+
static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct
r600_bytecode_alu *alu)
{
unsigned slots = r600_isa_alu_slots(bc-isa-hw_class, alu-op);
@@ -576,6 +582,12 @@ static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
for (i = 0; i max_slots; ++i) {
if (prev[i] (prev[i]-dst.write || prev[i]-is_op3)
!prev[i]-dst.rel) {
+
+ if (is_alu_64bit_inst(bc, prev[i])) {
+ gpr[i] = -1;
+ continue;
+ }
+
gpr[i] = prev[i]-dst.sel;
/* cube writes more than PV.X */
if (is_alu_reduction_inst(bc, prev[i]))
@@ -591,6 +603,8 @@ static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
if(!alu)
continue;
+ if (is_alu_64bit_inst(bc, alu))
+ continue;
num_src = r600_bytecode_get_num_operands(bc, alu);
for (src = 0; src num_src; ++src) {
if (!is_gpr(alu-src[src].sel) || alu-src[src].rel)
diff --git a/src/gallium/drivers/r600/r600_asm.h
b/src/gallium/drivers/r600/r600_asm.h
index e37d926..7b2734c 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -279,4 +279,19 @@ void eg_bytecode_export_read(struct r600_bytecode *bc,
void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
unsigned *num_format, unsigned *format_comp,
unsigned *endian);
+
+static INLINE int fp64_switch(int i)
+{
+ switch (i) {
+ case 0:
+ return 1;
+ case 1:
+ return 0;
+ case 2:
+ return 3;
+ case 3:
+ return 2;
+ }
+ return 0;
+}
#endif
diff --git a/src/gallium/drivers/r600/r600_isa.h
b/src/gallium/drivers/r600/r600_isa.h
index ec3f702..3cc135e 100644
--- a/src/gallium/drivers/r600/r600_isa.h
+++ b/src/gallium/drivers/r600/r600_isa.h
@@ -339,11 +339,11 @@ static const struct alu_op_info alu_op_table[] = {
{PRED_SETGT_64, 2, { 0x7C, 0xC7 },{ AF_V,
AF_V, AF_V, AF_V}, AF_PRED | AF_CC_GT | AF_64 },
{PRED_SETE_64, 2, { 0x7D, 0xC8 },{ AF_V,
AF_V, AF_V, AF_V}, AF_PRED | AF_CC_E | AF_64 },
{PRED_SETGE_64, 2, { 0x7E, 0xC9 },{ AF_V,
AF_V, AF_V, AF_V}, AF_PRED | AF_CC_GE | AF_64 },
- {MUL_64,2, { 0x1B, 0xCA },{ AF_V,
AF_V, AF_V, AF_V}, AF_64 },
+ {MUL_64,2, { 0x1B, 0xCA },{ AF_V,
AF_V, AF_V, AF_4V}, AF_64 },
{ADD_64,2, { 0x17, 0xCB },{ AF_V,
AF_V, AF_V, AF_V}, AF_64 },
{MOVA_INT, 1, { 0x18, 0xCC },{ AF_V,
AF_V, AF_V, AF_V}, AF_MOVA },
- {FLT64_TO_FLT32,1, { 0x1C, 0xCD },{ AF_V,
AF_V, AF_V, AF_V}, 0 },
- {FLT32_TO_FLT64,1, { 0x1D, 0xCE },{ AF_V,
AF_V, AF_V, AF_V}, 0 },
+ {FLT64_TO_FLT32,1, { 0x1C, 0xCD },{ AF_V,
AF_V, AF_V, AF_V}, AF_64 },
+ {FLT32_TO_FLT64,1, { 0x1D, 0xCE },{ AF_V,
AF_V, AF_V, AF_V}, AF_64 },
{SAD_ACCUM_PREV_UINT, 2, { -1, 0xCF },{ 0,
0, AF_V, AF_V}, AF_UINT_DST | AF_PREV_NEXT },
{DOT, 2, { -1, 0xD0 },{ 0,
0, AF_V, AF_V}, AF_PREV_NEXT },
{MUL_PREV, 1, { -1, 0xD1 },{ 0,
0, AF_V, AF_V}, AF_PREV_INTERLEAVE },
@@ -369,7 +369,7 @@
[Mesa-dev] [RFC] cayman fp64 support
This just implements FP64 on cayman but disables the sb compiler for now. Dave. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] tgsi/scan: add uses_doubles to tgsi scanner
On Thu, Feb 19, 2015 at 7:54 PM, Dave Airlie airl...@gmail.com wrote:
From: Dave Airlie airl...@redhat.com
This allows drivers to work out if a shader contains any
double opcodes easily.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/auxiliary/tgsi/tgsi_scan.c | 4
src/gallium/auxiliary/tgsi/tgsi_scan.h | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c
b/src/gallium/auxiliary/tgsi/tgsi_scan.c
index e6011d2..e19b8a1 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
@@ -97,6 +97,10 @@ tgsi_scan_shader(const struct tgsi_token *tokens,
assert(fullinst-Instruction.Opcode TGSI_OPCODE_LAST);
info-opcode_count[fullinst-Instruction.Opcode]++;
+if (fullinst-Instruction.Opcode = TGSI_OPCODE_F2D ||
+fullinst-Instruction.Opcode TGSI_OPCODE_DRSQ)
I added a few :)
+ info-uses_doubles = true;
+
for (i = 0; i fullinst-Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *src =
fullinst-Src[i];
diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.h
b/src/gallium/auxiliary/tgsi/tgsi_scan.h
index 5dc9267..daa73cc 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.h
@@ -86,7 +86,7 @@ struct tgsi_shader_info
boolean writes_viewport_index;
boolean writes_layer;
boolean is_msaa_sampler[PIPE_MAX_SAMPLERS];
-
+ boolean uses_doubles; /** uses any of the double instructions */
unsigned clipdist_writemask;
unsigned culldist_writemask;
unsigned num_written_culldistance;
--
1.9.3
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[Mesa-dev] [PATCH v5] mesa: use fi_type in vertex attribute code
From: Marius Predut marius.pre...@intel.com
For 32-bit builds, floating point operations use x86 FPU registers,
not SSE registers. If we're actually storing an integer in a float
variable, the value might get modified when written to memory. This
patch changes the VBO code to use the fi_type (float/int union) to
store/copy vertex attributes.
Also, this can improve performance on x86 because moving floats with
integer registers instead of FP registers is faster.
Neil Roberts review:
- include changes on all places that are storing attribute values.
- check with and without -O3 compiler flag.
Brian Paul review:
- use fi_type type instead gl_constant_value type
- fix a bunch of nit-picks.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82668
Signed-off-by: Marius Predut marius.pre...@intel.com
---
src/mesa/main/context.c |3 ++-
src/mesa/main/macros.h| 34 ++
src/mesa/vbo/vbo_attrib_tmp.h | 22 ++
src/mesa/vbo/vbo_context.h| 14 +++---
src/mesa/vbo/vbo_exec.h | 11 ++-
src/mesa/vbo/vbo_exec_api.c | 34 +-
src/mesa/vbo/vbo_exec_draw.c |6 +++---
src/mesa/vbo/vbo_exec_eval.c | 24 +---
src/mesa/vbo/vbo_save.h | 16
src/mesa/vbo/vbo_save_api.c | 34 +-
src/mesa/vbo/vbo_save_draw.c |4 ++--
11 files changed, 111 insertions(+), 91 deletions(-)
diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index 63d30a2..f0597e2 100644
--- a/src/mesa/main/context.c
+++ b/src/mesa/main/context.c
@@ -134,6 +134,7 @@
#include math/m_matrix.h
#include main/dispatch.h /* for _gloffset_COUNT */
#include uniforms.h
+#include macros.h
#ifdef USE_SPARC_ASM
#include sparc/sparc.h
@@ -656,7 +657,7 @@ _mesa_init_constants(struct gl_constants *consts, gl_api
api)
consts-MaxSamples = 0;
/* GLSL default if NativeIntegers == FALSE */
- consts-UniformBooleanTrue = FLT_AS_UINT(1.0f);
+ consts-UniformBooleanTrue = FLOAT_AS_UNION(1.0f).u;
/* GL_ARB_sync */
consts-MaxServerWaitTimeout = 0x1fff7fffULL;
diff --git a/src/mesa/main/macros.h b/src/mesa/main/macros.h
index 2d59c6f..70d0556 100644
--- a/src/mesa/main/macros.h
+++ b/src/mesa/main/macros.h
@@ -170,25 +170,25 @@ extern GLfloat _mesa_ubyte_to_float_color_tab[256];
ub = ((GLubyte) F_TO_I((f) * 255.0F))
#endif
-static inline GLfloat INT_AS_FLT(GLint i)
+static fi_type UINT_AS_UNION(GLuint u)
{
fi_type tmp;
- tmp.i = i;
- return tmp.f;
+ tmp.u = u;
+ return tmp;
}
-static inline GLfloat UINT_AS_FLT(GLuint u)
+static inline fi_type INT_AS_UNION(GLint i)
{
fi_type tmp;
- tmp.u = u;
- return tmp.f;
+ tmp.i = i;
+ return tmp;
}
-static inline unsigned FLT_AS_UINT(float f)
+static inline fi_type FLOAT_AS_UNION(GLfloat f)
{
fi_type tmp;
tmp.f = f;
- return tmp.u;
+ return tmp;
}
/**
@@ -620,24 +620,26 @@ do { \
* The default values are chosen based on \p type.
*/
static inline void
-COPY_CLEAN_4V_TYPE_AS_FLOAT(GLfloat dst[4], int sz, const GLfloat src[4],
+COPY_CLEAN_4V_TYPE_AS_UNION(fi_type dst[4], int sz, const fi_type src[4],
GLenum type)
{
switch (type) {
case GL_FLOAT:
- ASSIGN_4V(dst, 0, 0, 0, 1);
+ ASSIGN_4V(dst, FLOAT_AS_UNION(0), FLOAT_AS_UNION(0),
+FLOAT_AS_UNION(0), FLOAT_AS_UNION(1));
break;
case GL_INT:
- ASSIGN_4V(dst, INT_AS_FLT(0), INT_AS_FLT(0),
- INT_AS_FLT(0), INT_AS_FLT(1));
+ ASSIGN_4V(dst, INT_AS_UNION(0), INT_AS_UNION(0),
+INT_AS_UNION(0), INT_AS_UNION(1));
break;
case GL_UNSIGNED_INT:
- ASSIGN_4V(dst, UINT_AS_FLT(0), UINT_AS_FLT(0),
- UINT_AS_FLT(0), UINT_AS_FLT(1));
+ ASSIGN_4V(dst, UINT_AS_UNION(0), UINT_AS_UNION(0),
+UINT_AS_UNION(0), UINT_AS_UNION(1));
break;
default:
- ASSIGN_4V(dst, 0.0f, 0.0f, 0.0f, 1.0f); /* silence warnings */
- ASSERT(!Unexpected type in COPY_CLEAN_4V_TYPE_AS_FLOAT macro);
+ ASSIGN_4V(dst, FLOAT_AS_UNION(0), FLOAT_AS_UNION(0),
+FLOAT_AS_UNION(0), FLOAT_AS_UNION(1)); /* silence warnings */
+ ASSERT(!Unexpected type in COPY_CLEAN_4V_TYPE_AS_UNION macro);
}
COPY_SZ_4V(dst, sz, src);
}
diff --git a/src/mesa/vbo/vbo_attrib_tmp.h b/src/mesa/vbo/vbo_attrib_tmp.h
index ec66934..80e8aaf 100644
--- a/src/mesa/vbo/vbo_attrib_tmp.h
+++ b/src/mesa/vbo/vbo_attrib_tmp.h
@@ -28,6 +28,22 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#include util/u_format_r11g11b10f.h
#include main/varray.h
+
+/* ATTR */
+#define ATTR( A, N, T, V0, V1, V2, V3 ) \
+ATTR_##T((A), (N), (T), (V0), (V1), (V2), (V3))
+
+#define ATTR_GL_UNSIGNED_INT( A, N, T, V0, V1, V2, V3 ) \
+ATTR_UNION(A, N, T, UINT_AS_UNION(V0), UINT_AS_UNION(V1), \
+UINT_AS_UNION(V2),
Re: [Mesa-dev] [PATCH 2/3] i965/fs: Use fs_inst::overwrites_reg() in saturate propagation.
On Thu, Feb 19, 2015 at 3:25 PM, Ian Romanick i...@freedesktop.org wrote:
On 02/11/2015 02:54 PM, Matt Turner wrote:
This is safer and matches the conditional_mod propagation pass.
Cc: mesa-sta...@lists.freedesktop.org
---
.../dri/i965/brw_fs_saturate_propagation.cpp | 8 ++---
.../dri/i965/test_fs_saturate_propagation.cpp | 40
++
2 files changed, 44 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
index a9966a4..bc51661 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
@@ -64,10 +64,10 @@ opt_saturate_propagation_local(fs_visitor *v, bblock_t
*block)
bool interfered = false;
foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst,
block) {
- if (scan_inst-dst.file == GRF
- scan_inst-dst.reg == inst-src[0].reg
- scan_inst-dst.reg_offset == inst-src[0].reg_offset
- !scan_inst-is_partial_write()) {
+ if (scan_inst-overwrites_reg(inst-src[0])) {
+if (scan_inst-is_partial_write())
+ break;
+
if (scan_inst-saturate) {
inst-saturate = false;
progress = true;
diff --git a/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
b/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
index 2000830..f897bdd 100644
--- a/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
@@ -353,3 +353,43 @@ TEST_F(saturate_propagation_test,
intervening_saturating_copy)
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)-opcode);
EXPECT_FALSE(instruction(block0, 2)-saturate);
}
+
+TEST_F(saturate_propagation_test, intervening_dest_write)
Does this test pass without the other change?
No. The test is for the bug this is fixing.
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Re: [Mesa-dev] [PATCH] st/mesa: add st fp64 support (v7)
On Thu, Feb 19, 2015 at 6:09 PM, Dave Airlie airl...@gmail.com wrote:
From: Dave Airlie airl...@redhat.com
v2 : add double to int/unsigned conversion
v3: handle fp64 consts better
v4: use DRSQ
v4.1: add d2b
v4.2: drop DDIV
v5: split out some prep patches.
v5.1: add some comments.
v5.2: more comments
v6: simplify down the double instruction
generation loop.
v7: Merge Ilia's two cleanup patches.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/mesa/state_tracker/st_extensions.c | 6 +
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 578
++---
2 files changed, 458 insertions(+), 126 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 56502fb..003d280 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -464,7 +478,6 @@ public:
static st_src_reg undef_src = st_src_reg(PROGRAM_UNDEFINED, 0,
GLSL_TYPE_ERROR);
static st_dst_reg undef_dst = st_dst_reg(PROGRAM_UNDEFINED, SWIZZLE_NOOP,
GLSL_TYPE_ERROR);
-
static st_dst_reg address_reg = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
GLSL_TYPE_FLOAT, 0);
static st_dst_reg address_reg2 = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
GLSL_TYPE_FLOAT, 1);
static st_dst_reg sampler_reladdr = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
GLSL_TYPE_FLOAT, 2);
Drop this hunk.
@@ -597,22 +616,129 @@ glsl_to_tgsi_visitor::emit(ir_instruction *ir,
unsigned op,
this-instructions.push_tail(inst);
+ /*
+* This section contains the double processing.
+* GLSL just represents doubles as single channel values,
+* however most HW and TGSI represent doubles as pairs of register
channels.
+*
+* so we have to fixup destination writemask/index and src
swizzle/indexes.
+* dest writemasks need to translate from single channel write mask
+* to a dual-channel writemask, but also need to modify the index,
+* if we are touching the Z,W fields in the pre-translated writemask.
+*
+* src channels have similiar index modifications along with swizzle
+* changes to we pick the XY, ZW pairs from the correct index.
+*
+* GLSL [0].x - TGSI [0].xy
+* GLSL [0].y - TGSI [0].zw
+* GLSL [0].z - TGSI [1].xy
+* GLSL [0].w - TGSI [1].zw
+*/
+ if (inst-dst[0].type == GLSL_TYPE_DOUBLE || inst-dst[1].type ==
GLSL_TYPE_DOUBLE ||
+ inst-src[0].type == GLSL_TYPE_DOUBLE) {
+ glsl_to_tgsi_instruction *dinst = NULL;
+ int initial_src_swz[4], initial_src_idx[4];
+ int initial_dst_idx[2], initial_dst_writemask[2];
+ /* select the writemask for dst0 or dst1 */
+ unsigned writemask = inst-dst[0].file == PROGRAM_UNDEFINED ?
inst-dst[1].writemask : inst-dst[0].writemask;
+
+ /* copy out the writemask, index and swizzles for all src/dsts. */
+ for (j = 0; j 2; j++) {
+ initial_dst_writemask[j] = inst-dst[j].writemask;
+ initial_dst_idx[j] = inst-dst[j].index;
+ }
+
+ for (j = 0; j 4; j++) {
+ initial_src_swz[j] = inst-src[j].swizzle;
+ initial_src_idx[j] = inst-src[j].index;
+ }
+
+ /*
+ * scan all the components in the dst writemask
+ * generate an instruction for each of them if required.
+ */
+ while (writemask) {
+
+ int i = u_bit_scan(writemask);
+
+ /* first time use previous instruction */
+ if (dinst == NULL) {
+dinst = inst;
+ } else {
+/* create a new instructions for subsequent attempts */
+dinst = new(mem_ctx) glsl_to_tgsi_instruction();
+*dinst = *inst;
+dinst-next = NULL;
+dinst-prev = NULL;
+this-instructions.push_tail(dinst);
+ }
+
+ /* modify the destination if we are splitting */
+ for (j = 0; j 2; j++) {
+if (dinst-dst[j].type == GLSL_TYPE_DOUBLE) {
+ dinst-dst[j].writemask = (i 1) ? WRITEMASK_ZW :
WRITEMASK_XY;
+ dinst-dst[j].index = initial_dst_idx[j];
+ if (i 1)
+ dinst-dst[j].index++;
+} else {
+ /* if we aren't writing to a double, just get the bit of the
initial writemask
+ for this channel */
+ dinst-dst[j].writemask = initial_dst_writemask[j] (1 i);
+}
+ }
+
+ /* modify the src registers */
+ for (j = 0; j 4; j++) {
+int swz = GET_SWZ(initial_src_swz[j], i);
+
+if (dinst-src[j].type == GLSL_TYPE_DOUBLE) {
+ dinst-src[j].index = initial_src_idx[j];
+ if (swz 1)
+ dinst-src[j].index++;
+
+ if (swz 1)
+ dinst-src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z,
SWIZZLE_W, SWIZZLE_Z, SWIZZLE_W);
+ else
+
[Mesa-dev] [PATCH] i965/fs: Set pixel/sample mask for compute shaders atomic ops
For fragment programs, we pull this mask from the payload header. The same mask doesn't exist for compute shaders, so we set all bits to enabled. Note: this mask is ANDed with the execution mask, so some channels may not end up issuing the atomic operation. Signed-off-by: Jordan Justen jordan.l.jus...@intel.com Cc: Ben Widawsky b...@bwidawsk.net Cc: Francisco Jerez curroje...@riseup.net --- While it's fresh in our minds. :) This seems to work for gen7 gen8 CS. For CS simd16, we need the 0x change, but it seems to work fine for simd8 as well. I also tested gen8 (simd8vs), and there were no piglit regressions. src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 24cc118..960a0aa 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -2998,9 +2998,9 @@ fs_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index, * mask sent in the header to compute the actual set of channels that execute * the atomic operation. */ - assert(stage == MESA_SHADER_VERTEX); + assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE); emit(MOV(component(sources[0], 7), - brw_imm_ud(0xff)))-force_writemask_all = true; + brw_imm_ud(0x)))-force_writemask_all = true; } length++; @@ -3061,9 +3061,9 @@ fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst, * mask sent in the header to compute the actual set of channels that execute * the atomic operation. */ - assert(stage == MESA_SHADER_VERTEX); + assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE); emit(MOV(component(sources[0], 7), - brw_imm_ud(0xff)))-force_writemask_all = true; + brw_imm_ud(0x)))-force_writemask_all = true; } /* Set the surface read offset. */ -- 2.1.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 89199] u_math.h:591:4: error: implicit declaration of function 'ffsll'
https://bugs.freedesktop.org/show_bug.cgi?id=89199 --- Comment #4 from Vinson Lee v...@freedesktop.org --- $ gcc --version gcc (NetBSD nb2 20110806) 4.5.3 Copyright (C) 2010 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. attachment 113670 fixes the NetBSD build. Tested-by: Vinson Lee v...@freedesktop.org -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 06/23] main: Add entry point for NamedBufferStorage.
This is NamedBufferStorage, not NamedBufferData. The storage function uses
a bitfield instead of an enum.
On Wed, Feb 18, 2015 at 7:04 AM, Martin Peres martin.pe...@linux.intel.com
wrote:
On 12/02/15 04:05, Laura Ekstrand wrote:
---
src/mapi/glapi/gen/ARB_direct_state_access.xml | 7 +++
src/mesa/main/bufferobj.c | 63
+++---
src/mesa/main/bufferobj.h | 9
src/mesa/main/tests/dispatch_sanity.cpp| 1 +
4 files changed, 64 insertions(+), 16 deletions(-)
diff --git a/src/mapi/glapi/gen/ARB_direct_state_access.xml
b/src/mapi/glapi/gen/ARB_direct_state_access.xml
index 6c9d0e8..ff81c21 100644
--- a/src/mapi/glapi/gen/ARB_direct_state_access.xml
+++ b/src/mapi/glapi/gen/ARB_direct_state_access.xml
@@ -14,6 +14,13 @@
param name=buffers type=GLuint * /
/function
+ function name=NamedBufferStorage offset=assign
+ param name=buffer type=GLuint /
+ param name=size type=GLsizeiptr /
+ param name=data type=const GLvoid * /
+ param name=flags type=GLbitfield /
Isn't this supposed to be an enum? Here is the prototype found in core 4.5:
void NamedBufferData( uint buffer, sizeiptr size, const void *data, enum
usage );
Other than that, this looks good to me.
Reviewed-by: Martin Peres martin.pe...@linux.intel.com
+ /function
+
!-- Texture object functions --
function name=CreateTextures offset=assign
diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index 785f0ff..6259db1 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -1386,15 +1386,13 @@ _mesa_IsBuffer(GLuint id)
}
-void GLAPIENTRY
-_mesa_BufferStorage(GLenum target, GLsizeiptr size, const GLvoid *data,
-GLbitfield flags)
+void
+_mesa_buffer_storage(struct gl_context *ctx, struct gl_buffer_object
*bufObj,
+ GLenum target, GLsizeiptr size, const GLvoid *data,
+ GLbitfield flags, const char *func)
{
- GET_CURRENT_CONTEXT(ctx);
- struct gl_buffer_object *bufObj;
-
if (size = 0) {
- _mesa_error(ctx, GL_INVALID_VALUE, glBufferStorage(size = 0));
+ _mesa_error(ctx, GL_INVALID_VALUE, %s(size = 0), func);
return;
}
@@ -1404,27 +1402,25 @@ _mesa_BufferStorage(GLenum target, GLsizeiptr
size, const GLvoid *data,
GL_MAP_COHERENT_BIT |
GL_DYNAMIC_STORAGE_BIT |
GL_CLIENT_STORAGE_BIT)) {
- _mesa_error(ctx, GL_INVALID_VALUE, glBufferStorage(flags));
+ _mesa_error(ctx, GL_INVALID_VALUE, %s(invalid flag bits set),
func);
return;
}
if (flags GL_MAP_PERSISTENT_BIT
!(flags (GL_MAP_READ_BIT | GL_MAP_WRITE_BIT))) {
- _mesa_error(ctx, GL_INVALID_VALUE, glBufferStorage(flags!=READ/
WRITE));
+ _mesa_error(ctx, GL_INVALID_VALUE,
+ %s(PERSISTENT and flags!=READ/WRITE), func);
return;
}
if (flags GL_MAP_COHERENT_BIT !(flags
GL_MAP_PERSISTENT_BIT)) {
- _mesa_error(ctx, GL_INVALID_VALUE, glBufferStorage(flags!=
PERSISTENT));
+ _mesa_error(ctx, GL_INVALID_VALUE,
+ %s(COHERENT and flags!=PERSISTENT), func);
return;
}
- bufObj = get_buffer(ctx, glBufferStorage, target,
GL_INVALID_OPERATION);
- if (!bufObj)
- return;
-
if (bufObj-Immutable) {
- _mesa_error(ctx, GL_INVALID_OPERATION,
glBufferStorage(immutable));
+ _mesa_error(ctx, GL_INVALID_OPERATION, %s(immutable), func);
return;
}
@@ -1439,10 +1435,45 @@ _mesa_BufferStorage(GLenum target, GLsizeiptr
size, const GLvoid *data,
ASSERT(ctx-Driver.BufferData);
if (!ctx-Driver.BufferData(ctx, target, size, data, GL_DYNAMIC_DRAW,
flags, bufObj)) {
- _mesa_error(ctx, GL_OUT_OF_MEMORY, glBufferStorage());
+ _mesa_error(ctx, GL_OUT_OF_MEMORY, %s(), func);
}
}
+void GLAPIENTRY
+_mesa_BufferStorage(GLenum target, GLsizeiptr size, const GLvoid *data,
+GLbitfield flags)
+{
+ GET_CURRENT_CONTEXT(ctx);
+ struct gl_buffer_object *bufObj;
+
+ bufObj = get_buffer(ctx, glBufferStorage, target,
GL_INVALID_OPERATION);
+ if (!bufObj)
+ return;
+
+ _mesa_buffer_storage(ctx, bufObj, target, size, data, flags,
+glBufferStorage);
+}
+
+void GLAPIENTRY
+_mesa_NamedBufferStorage(GLuint buffer, GLsizeiptr size, const GLvoid
*data,
+ GLbitfield flags)
+{
+ GET_CURRENT_CONTEXT(ctx);
+ struct gl_buffer_object *bufObj;
+
+ bufObj = _mesa_lookup_bufferobj_err(ctx, buffer,
glNamedBufferStorage);
+ if (!bufObj)
+ return;
+
+ /*
+* In direct state access, buffer objects have an unspecified target
since
+* they are not required to be bound.
+*/
+ _mesa_buffer_storage(ctx, bufObj,
[Mesa-dev] [Bug 89238] nir/nir.h, line 643: Error: In this declaration src is of an incomplete type nir_alu_src[].
https://bugs.freedesktop.org/show_bug.cgi?id=89238 Bug ID: 89238 Summary: nir/nir.h, line 643: Error: In this declaration src is of an incomplete type nir_alu_src[]. Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Solaris Status: NEW Severity: blocker Priority: medium Component: Mesa core Assignee: mesa-dev@lists.freedesktop.org Reporter: v...@freedesktop.org QA Contact: mesa-dev@lists.freedesktop.org mesa: 6316c90cc0daa9e9476b00e3c52c51190e782c3f (master 10.6.0-devel) Oracle Studio build error. nir/nir.h, line 643: Error: In this declaration src is of an incomplete type nir_alu_src[] -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 01/11] nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
.../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 66 +-
1 file changed, 63 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index dfb093c..e38a3b8 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -92,11 +92,14 @@ private:
void emitUADD(const Instruction *);
void emitFADD(const Instruction *);
+ void emitDADD(const Instruction *);
void emitUMUL(const Instruction *);
void emitFMUL(const Instruction *);
+ void emitDMUL(const Instruction *);
void emitIMAD(const Instruction *);
void emitISAD(const Instruction *);
void emitFMAD(const Instruction *);
+ void emitDMAD(const Instruction *);
void emitMADSP(const Instruction *);
void emitNOT(Instruction *);
@@ -523,6 +526,25 @@ CodeEmitterNVC0::emitFMAD(const Instruction *i)
}
void
+CodeEmitterNVC0::emitDMAD(const Instruction *i)
+{
+ bool neg1 = (i-src(0).mod ^ i-src(1).mod).neg();
+
+ emitForm_A(i, HEX64(2000, 0001));
+
+ if (i-src(2).mod.neg())
+ code[0] |= 1 8;
+
+ roundMode_A(i);
+
+ if (neg1)
+ code[0] |= 1 9;
+
+ assert(!i-saturate);
+ assert(!i-ftz);
+}
+
+void
CodeEmitterNVC0::emitFMUL(const Instruction *i)
{
bool neg = (i-src(0).mod ^ i-src(1).mod).neg();
@@ -557,6 +579,23 @@ CodeEmitterNVC0::emitFMUL(const Instruction *i)
}
void
+CodeEmitterNVC0::emitDMUL(const Instruction *i)
+{
+ bool neg = (i-src(0).mod ^ i-src(1).mod).neg();
+
+ emitForm_A(i, HEX64(5000, 0001));
+ roundMode_A(i);
+
+ if (neg)
+ code[0] |= 1 9;
+
+ assert(!i-saturate);
+ assert(!i-ftz);
+ assert(!i-dnz);
+ assert(!i-postFactor);
+}
+
+void
CodeEmitterNVC0::emitUMUL(const Instruction *i)
{
if (i-encSize == 8) {
@@ -619,6 +658,19 @@ CodeEmitterNVC0::emitFADD(const Instruction *i)
}
void
+CodeEmitterNVC0::emitDADD(const Instruction *i)
+{
+ assert(i-encSize == 8);
+ emitForm_A(i, HEX64(4800, 0001));
+ roundMode_A(i);
+ assert(!i-saturate);
+ assert(!i-ftz);
+ emitNegAbs12(i);
+ if (i-op == OP_SUB)
+ code[0] ^= 1 8;
+}
+
+void
CodeEmitterNVC0::emitUADD(const Instruction *i)
{
uint32_t addOp = 0;
@@ -895,6 +947,8 @@ CodeEmitterNVC0::emitMINMAX(const Instruction *i)
else
if (!isFloatType(i-dType))
op |= isSignedType(i-dType) ? 0x23 : 0x03;
+ if (i-dType == TYPE_F64)
+ op |= 0x01;
emitForm_A(i, op);
emitNegAbs12(i);
@@ -2242,20 +2296,26 @@ CodeEmitterNVC0::emitInstruction(Instruction *insn)
break;
case OP_ADD:
case OP_SUB:
- if (isFloatType(insn-dType))
+ if (insn-dType == TYPE_F64)
+ emitDADD(insn);
+ else if (isFloatType(insn-dType))
emitFADD(insn);
else
emitUADD(insn);
break;
case OP_MUL:
- if (isFloatType(insn-dType))
+ if (insn-dType == TYPE_F64)
+ emitDMUL(insn);
+ else if (isFloatType(insn-dType))
emitFMUL(insn);
else
emitUMUL(insn);
break;
case OP_MAD:
case OP_FMA:
- if (isFloatType(insn-dType))
+ if (insn-dType == TYPE_F64)
+ emitDMAD(insn);
+ else if (isFloatType(insn-dType))
emitFMAD(insn);
else
emitIMAD(insn);
--
2.0.5
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[Mesa-dev] [PATCH] intel: fix EGLImage renderbuffer _BaseFormat
Correctly set _BaseFormat field when creating a gl_renderbuffer with EGLImage storage. Signed-off-by: Frank Henigman fjhenig...@google.com Reviewed-by: Stéphane Marchesin marc...@chromium.org --- src/mesa/drivers/dri/i915/intel_fbo.c | 3 +-- src/mesa/drivers/dri/i965/intel_fbo.c | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) Otherwise, when using gles, _BaseFormat is set to 0 and a glReadPixels from the buffer hits an assert. Tested on i965. Compiled for i915. diff --git a/src/mesa/drivers/dri/i915/intel_fbo.c b/src/mesa/drivers/dri/i915/intel_fbo.c index ead1b17..6c2e181 100644 --- a/src/mesa/drivers/dri/i915/intel_fbo.c +++ b/src/mesa/drivers/dri/i915/intel_fbo.c @@ -287,8 +287,7 @@ intel_image_target_renderbuffer_storage(struct gl_context *ctx, rb-Width = image-region-width; rb-Height = image-region-height; rb-Format = image-format; - rb-_BaseFormat = _mesa_base_fbo_format(intel-ctx, - image-internal_format); + rb-_BaseFormat = _mesa_get_format_base_format(image-format); rb-NeedsFinishRenderTexture = true; } diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index 174cea0..9394018 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.c +++ b/src/mesa/drivers/dri/i965/intel_fbo.c @@ -398,7 +398,7 @@ intel_image_target_renderbuffer_storage(struct gl_context *ctx, rb-Width = image-width; rb-Height = image-height; rb-Format = image-format; - rb-_BaseFormat = _mesa_base_fbo_format(ctx, image-internal_format); + rb-_BaseFormat = _mesa_get_format_base_format(image-format); rb-NeedsFinishRenderTexture = true; irb-layer_count = 1; } -- 2.2.0.rc0.207.ga3a616c ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/3] i965/fs: Use fs_inst::overwrites_reg() in saturate propagation.
On 02/11/2015 02:54 PM, Matt Turner wrote:
This is safer and matches the conditional_mod propagation pass.
Cc: mesa-sta...@lists.freedesktop.org
---
.../dri/i965/brw_fs_saturate_propagation.cpp | 8 ++---
.../dri/i965/test_fs_saturate_propagation.cpp | 40
++
2 files changed, 44 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
index a9966a4..bc51661 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
@@ -64,10 +64,10 @@ opt_saturate_propagation_local(fs_visitor *v, bblock_t
*block)
bool interfered = false;
foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst,
block) {
- if (scan_inst-dst.file == GRF
- scan_inst-dst.reg == inst-src[0].reg
- scan_inst-dst.reg_offset == inst-src[0].reg_offset
- !scan_inst-is_partial_write()) {
+ if (scan_inst-overwrites_reg(inst-src[0])) {
+if (scan_inst-is_partial_write())
+ break;
+
if (scan_inst-saturate) {
inst-saturate = false;
progress = true;
diff --git a/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
b/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
index 2000830..f897bdd 100644
--- a/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
@@ -353,3 +353,43 @@ TEST_F(saturate_propagation_test,
intervening_saturating_copy)
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)-opcode);
EXPECT_FALSE(instruction(block0, 2)-saturate);
}
+
+TEST_F(saturate_propagation_test, intervening_dest_write)
Does this test pass without the other change?
+{
+ fs_reg dst0 = v-vgrf(glsl_type::vec4_type);
+ fs_reg dst1 = v-vgrf(glsl_type::float_type);
+ fs_reg src0 = v-vgrf(glsl_type::float_type);
+ fs_reg src1 = v-vgrf(glsl_type::float_type);
+ fs_reg src2 = v-vgrf(glsl_type::vec2_type);
+ v-emit(BRW_OPCODE_ADD, offset(dst0, 2), src0, src1);
+ v-emit(SHADER_OPCODE_TEX, dst0, src2)
+ -regs_written = 4;
+ v-emit(BRW_OPCODE_MOV, dst1, offset(dst0, 2))
+ -saturate = true;
+
+ /* = Before =
+*
+* 0: add(8)dst0+2 src0src1
+* 1: tex(8) rlen 4 dst0+0 src2
+* 2: mov.sat(8)dst1dst0+2
+*
+* = After =
+* (no changes)
+*/
+
+ v-calculate_cfg();
+ bblock_t *block0 = v-cfg-blocks[0];
+
+ EXPECT_EQ(0, block0-start_ip);
+ EXPECT_EQ(2, block0-end_ip);
+
+ EXPECT_FALSE(saturate_propagation(v));
+ EXPECT_EQ(0, block0-start_ip);
+ EXPECT_EQ(2, block0-end_ip);
+ EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)-opcode);
+ EXPECT_FALSE(instruction(block0, 0)-saturate);
+ EXPECT_EQ(SHADER_OPCODE_TEX, instruction(block0, 1)-opcode);
+ EXPECT_FALSE(instruction(block0, 0)-saturate);
+ EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 2)-opcode);
+ EXPECT_TRUE(instruction(block0, 2)-saturate);
+}
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Re: [Mesa-dev] [PATCH 4/4] i965/blorp: Emit MADs.
Assuming that my assumption / recollection that blorp is only for GEN6+,
this patch is
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
On 02/10/2015 11:10 AM, Matt Turner wrote:
Low hanging fruit: cuts a couple of instructions.
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 6 ++
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h | 9 +
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index fc111ae..5c936cf 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1255,10 +1255,8 @@ brw_blorp_blit_program::translate_dst_to_src()
emit_mov(Xp_f, X);
emit_mov(Yp_f, Y);
/* Scale and offset */
- emit_mul(X_f, Xp_f, x_transform.multiplier);
- emit_mul(Y_f, Yp_f, y_transform.multiplier);
- emit_add(X_f, X_f, x_transform.offset);
- emit_add(Y_f, Y_f, y_transform.offset);
+ emit_mad(X_f, x_transform.offset, Xp_f, x_transform.multiplier);
+ emit_mad(Y_f, y_transform.offset, Yp_f, y_transform.multiplier);
if (key-blit_scaled key-blend) {
/* Translate coordinates to lay out the samples in a rectangular grid
* roughly corresponding to sample locations.
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
index bfad422..8e44eb4 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
@@ -85,6 +85,15 @@ protected:
new (mem_ctx) fs_inst(BRW_OPCODE_LRP, 16, dst, src1, src2, src3));
}
+ inline void emit_mad(const struct brw_reg dst,
+const struct brw_reg src1,
+const struct brw_reg src2,
+const struct brw_reg src3)
+ {
+ insts.push_tail(
+ new (mem_ctx) fs_inst(BRW_OPCODE_MAD, 16, dst, src1, src2, src3));
+ }
+
inline void emit_min(const struct brw_reg dst,
const struct brw_reg src1,
const struct brw_reg src2)
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Re: [Mesa-dev] [PATCH] i965: just avoid warnings with fp64
Yes, please. Reviewed-by: Ian Romanick ian.d.roman...@intel.com On 02/19/2015 03:38 PM, Dave Airlie wrote: This just fills in some blanks to avoid warnings in the i965 driver. Signed-off-by: Dave Airlie airl...@redhat.com --- src/mesa/drivers/dri/i965/brw_fs.cpp | 1 + src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp | 13 + src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 14 ++ src/mesa/drivers/dri/i965/brw_shader.cpp | 1 + src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 13 + 5 files changed, 42 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index a562b8a..a2a5234 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -673,6 +673,7 @@ fs_visitor::type_size(const struct glsl_type *type) case GLSL_TYPE_VOID: case GLSL_TYPE_ERROR: case GLSL_TYPE_INTERFACE: + case GLSL_TYPE_DOUBLE: unreachable(not reached); } diff --git a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp index cb0a079..c64742c 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp @@ -445,6 +445,19 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment *ir) case ir_binop_interpolate_at_offset: case ir_binop_interpolate_at_sample: unreachable(not reached: expression operates on scalars only); + + case ir_unop_pack_double_2x32: + case ir_unop_unpack_double_2x32: + case ir_unop_frexp_sig: + case ir_unop_frexp_exp: + case ir_unop_d2f: + case ir_unop_f2d: + case ir_unop_d2i: + case ir_unop_i2d: + case ir_unop_d2u: + case ir_unop_u2d: + case ir_unop_d2b: + unreachable(no fp64 support yet); } ir-remove(); diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 04e0f9a..7486071 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -1192,6 +1192,20 @@ fs_visitor::visit(ir_expression *ir) case ir_binop_interpolate_at_sample: unreachable(already handled above); break; + + case ir_unop_d2f: + case ir_unop_f2d: + case ir_unop_d2i: + case ir_unop_i2d: + case ir_unop_d2u: + case ir_unop_u2d: + case ir_unop_d2b: + case ir_unop_pack_double_2x32: + case ir_unop_unpack_double_2x32: + case ir_unop_frexp_sig: + case ir_unop_frexp_exp: + unreachable(fp64 todo); + break; } } diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 71146c5..b0e9c82 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -308,6 +308,7 @@ brw_type_for_base_type(const struct glsl_type *type) case GLSL_TYPE_VOID: case GLSL_TYPE_ERROR: case GLSL_TYPE_INTERFACE: + case GLSL_TYPE_DOUBLE: unreachable(not reached); } diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index 562fc30..6154e43 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp @@ -612,6 +612,7 @@ type_size(const struct glsl_type *type) return 0; case GLSL_TYPE_IMAGE: case GLSL_TYPE_VOID: + case GLSL_TYPE_DOUBLE: case GLSL_TYPE_ERROR: case GLSL_TYPE_INTERFACE: unreachable(not reached); @@ -1889,6 +1890,18 @@ vec4_visitor::visit(ir_expression *ir) unreachable(not reached: should not occur in vertex shader); case ir_binop_ldexp: unreachable(not reached: should be handled by ldexp_to_arith()); + case ir_unop_d2f: + case ir_unop_f2d: + case ir_unop_d2i: + case ir_unop_i2d: + case ir_unop_d2u: + case ir_unop_u2d: + case ir_unop_d2b: + case ir_unop_pack_double_2x32: + case ir_unop_unpack_double_2x32: + case ir_unop_frexp_sig: + case ir_unop_frexp_exp: + unreachable(fp64 todo); } } ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
