Re: [Mesa-dev] [PATCH v2 15/35] i965/blorp: Add an isl_view to blorp_surface_info

[Jason Ekstrand]

On Jul 26, 2016 10:39 PM, "Pohjolainen, Topi" 
wrote:
>
> On Tue, Jul 26, 2016 at 03:02:06PM -0700, Jason Ekstrand wrote:
> > Eventually, this will be the actual view that gets passed into isl to
> > create the surface state.  For now, we just use it for the format and
the
> > swizzle.
> > ---
> >  src/mesa/drivers/dri/i965/brw_blorp.c | 38
+++
> >  src/mesa/drivers/dri/i965/brw_blorp.h | 16 ++-
> >  src/mesa/drivers/dri/i965/brw_blorp_blit.cpp  | 34

> >  src/mesa/drivers/dri/i965/brw_blorp_clear.cpp |  2 +-
> >  src/mesa/drivers/dri/i965/gen8_blorp.c| 29 
> >  5 files changed, 64 insertions(+), 55 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
> > index 8f7690c..ef256a7 100644
> > --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> > +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> > @@ -43,9 +43,11 @@ brw_blorp_surface_info_init(struct brw_context *brw,
> >  * using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it
had better
> >  * be a multiple of num_samples.
> >  */
> > +   unsigned layer_multiplier = 1;
> > if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
> > mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
> >assert(mt->num_samples <= 1 || layer % mt->num_samples == 0);
> > +  layer_multiplier = MAX2(mt->num_samples, 1);
> > }
> >
> > intel_miptree_check_level_layer(mt, level, layer);
> > @@ -61,13 +63,27 @@ brw_blorp_surface_info_init(struct brw_context *brw,
> >info->aux_usage = ISL_AUX_USAGE_NONE;
> > }
> >
> > +   info->view = (struct isl_view) {
> > +  .usage = is_render_target ? ISL_SURF_USAGE_RENDER_TARGET_BIT :
> > +  ISL_SURF_USAGE_TEXTURE_BIT,
> > +  .format = ISL_FORMAT_UNSUPPORTED, /* Set later */
> > +  .base_level = level,
> > +  .levels = 1,
> > +  .base_array_layer = layer / layer_multiplier,
> > +  .array_len = 1,
> > +  .channel_select = {
> > + ISL_CHANNEL_SELECT_RED,
> > + ISL_CHANNEL_SELECT_GREEN,
> > + ISL_CHANNEL_SELECT_BLUE,
> > + ISL_CHANNEL_SELECT_ALPHA,
> > +  },
> > +   };
> > +
> > info->level = level;
> > info->layer = layer;
> > info->width = minify(mt->physical_width0, level - mt->first_level);
> > info->height = minify(mt->physical_height0, level -
mt->first_level);
> >
> > -   info->swizzle = SWIZZLE_XYZW;
> > -
> > if (format == MESA_FORMAT_NONE)
> >format = mt->format;
> >
> > @@ -75,8 +91,8 @@ brw_blorp_surface_info_init(struct brw_context *brw,
> > case MESA_FORMAT_S_UINT8:
> >assert(info->surf.tiling == ISL_TILING_W);
> >/* Prior to Broadwell, we can't render to R8_UINT */
> > -  info->brw_surfaceformat = brw->gen >= 8 ?
BRW_SURFACEFORMAT_R8_UINT :
> > -
BRW_SURFACEFORMAT_R8_UNORM;
> > +  info->view.format = brw->gen >= 8 ? BRW_SURFACEFORMAT_R8_UINT :
> > +  BRW_SURFACEFORMAT_R8_UNORM;
>
> Should we use ISL_FORMAT_ instead? Or at least the cast. Assigning an enum
> with another always looks bad unless it is clear they happen to have exact
> same values.

Somewhere in the series that gets cleaned up.  Eventually we need to just
kill BRW_SURFACEFORMAT all together.

> >break;
> > case MESA_FORMAT_Z24_UNORM_X8_UINT:
> >/* It would make sense to use
BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
> > @@ -89,20 +105,20 @@ brw_blorp_surface_info_init(struct brw_context
*brw,
> > * pattern as long as we copy the right amount of data, so just
map it
> > * as 8-bit BGRA.
> > */
> > -  info->brw_surfaceformat = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
> > +  info->view.format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
> >break;
> > case MESA_FORMAT_Z_FLOAT32:
> > -  info->brw_surfaceformat = BRW_SURFACEFORMAT_R32_FLOAT;
> > +  info->view.format = BRW_SURFACEFORMAT_R32_FLOAT;
> >break;
> > case MESA_FORMAT_Z_UNORM16:
> > -  info->brw_surfaceformat = BRW_SURFACEFORMAT_R16_UNORM;
> > +  info->view.format = BRW_SURFACEFORMAT_R16_UNORM;
> >break;
> > default: {
> >if (is_render_target) {
> >   assert(brw->format_supported_as_render_target[format]);
> > - info->brw_surfaceformat = brw->render_target_format[format];
> > + info->view.format = brw->render_target_format[format];
>
> Perhaps use the cast such as you do further down in the patch:
>
> info->view.format =
>(enum isl_format)brw->render_target_format[format];

The reason I do further down is because it's C++.  Again, this will get
cleaned up eventually...

> >} else {
> > - info->brw_surfaceformat = brw_format_for_mesa_format(format);
> > + info->view.format = brw_format_for_mesa_format(format);
> >}
> >break;
> > }
> > @@ -111,7 +127,7 @@

Re: [Mesa-dev] [PATCH v2 15/35] i965/blorp: Add an isl_view to blorp_surface_info

[Jason Ekstrand]

On Jul 26, 2016 10:41 PM, "Pohjolainen, Topi" 
wrote:
>
> On Tue, Jul 26, 2016 at 03:02:06PM -0700, Jason Ekstrand wrote:
> > Eventually, this will be the actual view that gets passed into isl to
> > create the surface state.  For now, we just use it for the format and
the
> > swizzle.
> > ---
> >  src/mesa/drivers/dri/i965/brw_blorp.c | 38
+++
> >  src/mesa/drivers/dri/i965/brw_blorp.h | 16 ++-
> >  src/mesa/drivers/dri/i965/brw_blorp_blit.cpp  | 34

> >  src/mesa/drivers/dri/i965/brw_blorp_clear.cpp |  2 +-
> >  src/mesa/drivers/dri/i965/gen8_blorp.c| 29 
> >  5 files changed, 64 insertions(+), 55 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
> > index 8f7690c..ef256a7 100644
> > --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> > +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> > @@ -43,9 +43,11 @@ brw_blorp_surface_info_init(struct brw_context *brw,
> >  * using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it
had better
> >  * be a multiple of num_samples.
> >  */
> > +   unsigned layer_multiplier = 1;
>
> In principle we could just:
>
>   const unsigned layer_multiplier = MAX2(mt->num_samples, 1);

No, it only applies to array multisampling and not interleaved

> > if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
> > mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
> >assert(mt->num_samples <= 1 || layer % mt->num_samples == 0);
> > +  layer_multiplier = MAX2(mt->num_samples, 1);
> > }
> >
> > intel_miptree_check_level_layer(mt, level, layer);
> > @@ -61,13 +63,27 @@ brw_blorp_surface_info_init(struct brw_context *brw,
> >info->aux_usage = ISL_AUX_USAGE_NONE;
> > }
> >
> > +   info->view = (struct isl_view) {
> > +  .usage = is_render_target ? ISL_SURF_USAGE_RENDER_TARGET_BIT :
> > +  ISL_SURF_USAGE_TEXTURE_BIT,
> > +  .format = ISL_FORMAT_UNSUPPORTED, /* Set later */
> > +  .base_level = level,
> > +  .levels = 1,
> > +  .base_array_layer = layer / layer_multiplier,
> > +  .array_len = 1,
> > +  .channel_select = {
> > + ISL_CHANNEL_SELECT_RED,
> > + ISL_CHANNEL_SELECT_GREEN,
> > + ISL_CHANNEL_SELECT_BLUE,
> > + ISL_CHANNEL_SELECT_ALPHA,
> > +  },
> > +   };
> > +
> > info->level = level;
> > info->layer = layer;
> > info->width = minify(mt->physical_width0, level - mt->first_level);
> > info->height = minify(mt->physical_height0, level -
mt->first_level);
> >
> > -   info->swizzle = SWIZZLE_XYZW;
> > -
> > if (format == MESA_FORMAT_NONE)
> >format = mt->format;
> >
> > @@ -75,8 +91,8 @@ brw_blorp_surface_info_init(struct brw_context *brw,
> > case MESA_FORMAT_S_UINT8:
> >assert(info->surf.tiling == ISL_TILING_W);
> >/* Prior to Broadwell, we can't render to R8_UINT */
> > -  info->brw_surfaceformat = brw->gen >= 8 ?
BRW_SURFACEFORMAT_R8_UINT :
> > -
BRW_SURFACEFORMAT_R8_UNORM;
> > +  info->view.format = brw->gen >= 8 ? BRW_SURFACEFORMAT_R8_UINT :
> > +  BRW_SURFACEFORMAT_R8_UNORM;
> >break;
> > case MESA_FORMAT_Z24_UNORM_X8_UINT:
> >/* It would make sense to use
BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
> > @@ -89,20 +105,20 @@ brw_blorp_surface_info_init(struct brw_context
*brw,
> > * pattern as long as we copy the right amount of data, so just
map it
> > * as 8-bit BGRA.
> > */
> > -  info->brw_surfaceformat = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
> > +  info->view.format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
> >break;
> > case MESA_FORMAT_Z_FLOAT32:
> > -  info->brw_surfaceformat = BRW_SURFACEFORMAT_R32_FLOAT;
> > +  info->view.format = BRW_SURFACEFORMAT_R32_FLOAT;
> >break;
> > case MESA_FORMAT_Z_UNORM16:
> > -  info->brw_surfaceformat = BRW_SURFACEFORMAT_R16_UNORM;
> > +  info->view.format = BRW_SURFACEFORMAT_R16_UNORM;
> >break;
> > default: {
> >if (is_render_target) {
> >   assert(brw->format_supported_as_render_target[format]);
> > - info->brw_surfaceformat = brw->render_target_format[format];
> > + info->view.format = brw->render_target_format[format];
> >} else {
> > - info->brw_surfaceformat = brw_format_for_mesa_format(format);
> > + info->view.format = brw_format_for_mesa_format(format);
> >}
> >break;
> > }
> > @@ -111,7 +127,7 @@ brw_blorp_surface_info_init(struct brw_context *brw,
> > uint32_t x_offset, y_offset;
> > intel_miptree_get_image_offset(mt, level, layer, &x_offset,
&y_offset);
> >
> > -   uint8_t bs = isl_format_get_layout(info->brw_surfaceformat)->bpb /
8;
> > +   uint8_t bs = isl_format_get_layout(info->view.format)->bpb / 8;
> > isl_tiling_get_intratile_offset_el(&brw->isl_dev,
info-

Re: [Mesa-dev] Call i965 GLSL IR backend optimisation from the common linker

[Timothy Arceri]

On Tue, 2016-07-26 at 22:56 -0700, Matt Turner wrote:
> On Tue, Jul 26, 2016 at 10:20 PM, Timothy Arceri
>  wrote:
> > The ultimate goal is to be able to convert to NIR and make use of
> > its
> > optimisations before assigning varying and uniform locations. This
> > should allow us to start removing some of the GLSL IR optimisation
> > passes.
> 
> I'm very excited about this!

:)

> 
> > This series falls short of making use of NIR because
> > lower_packed_varyings()
> > modifies the IR after we assign varying locations. I can see two
> > ways
> > around this, listing them in increasing difficultly level they
> > would be:
> > 
> > - replacing the current packing pass with one that follows the
> > packing
> > rules of ARB_enhanced_layouts this would mean we can no longer pack
> > across slots and matrix and array packing effectivness would be
> > slightly
> > decreased.
> > - write a NIR packing pass.
> 
> Specifically a NIR implementation of lower_packed_varyings(), right?

Correct. I should have also mentioned that after assigning the
locations in the GLSL IR linker my current plan would be to insert
these locations into the existing NIR that gets created. I haven't
figured out how I would do this just yet but I'm hoping it can be done
and without being too hacky. Hence why is why we could do option 1 as
we would just be updating component and location fields rather than
altering the IR.

> 
> > 
> > Even without converting to NIR this series solves a number of the
> > other
> > problems with converting to NIR earlier and provides a nice shader-
> > db
> > improvement on its own.
> > 
> > Broadwell shader-db results:
> > 
> > total instructions in shared programs: 8651650 -> 8644415 (-0.08%)
> > instructions in affected programs: 38754 -> 31519 (-18.67%)
> > total loops in shared programs:2085 -> 2085 (0.00%)
> > helped:320
> > HURT:  0
> > GAINED:0
> 
> Impressive.
> 
> > Ivybridge reported no difference.
> 
> I suspect that's because Ivybridge's vertex shader is vec4, and we
> don't dead code eliminate individual *components* of varyings,
> whereas
> on Broadwell with scalar vertex shaders we're able to eliminate those
> dead components.

Yeah I was wondering why at first I thought I forgot to switch branches
but after looking at the code I assumed this to be the case thanks.

> 
> Thanks so much for working on this!

No problem. I'm happy to let someone else take this further if they
would like to, I just thought I would see how hard it would be to do.

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Re: [Mesa-dev] Call i965 GLSL IR backend optimisation from the common linker

[Matt Turner]

On Tue, Jul 26, 2016 at 10:20 PM, Timothy Arceri
 wrote:
> The ultimate goal is to be able to convert to NIR and make use of its
> optimisations before assigning varying and uniform locations. This
> should allow us to start removing some of the GLSL IR optimisation
> passes.

I'm very excited about this!

> This series falls short of making use of NIR because lower_packed_varyings()
> modifies the IR after we assign varying locations. I can see two ways
> around this, listing them in increasing difficultly level they would be:
>
> - replacing the current packing pass with one that follows the packing
> rules of ARB_enhanced_layouts this would mean we can no longer pack
> across slots and matrix and array packing effectivness would be slightly
> decreased.
> - write a NIR packing pass.

Specifically a NIR implementation of lower_packed_varyings(), right?

>
> Even without converting to NIR this series solves a number of the other
> problems with converting to NIR earlier and provides a nice shader-db
> improvement on its own.
>
> Broadwell shader-db results:
>
> total instructions in shared programs: 8651650 -> 8644415 (-0.08%)
> instructions in affected programs: 38754 -> 31519 (-18.67%)
> total loops in shared programs:2085 -> 2085 (0.00%)
> helped:320
> HURT:  0
> GAINED:0

Impressive.

> Ivybridge reported no difference.

I suspect that's because Ivybridge's vertex shader is vec4, and we
don't dead code eliminate individual *components* of varyings, whereas
on Broadwell with scalar vertex shaders we're able to eliminate those
dead components.

Thanks so much for working on this!
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Re: [Mesa-dev] [PATCH 00/11] Make more use of state already tracked in the VAO.

[Mathias Fröhlich]

Hi,

This should have been some preparing cleanup for some patches doing less work in
the fast draw path.

I have updated the comment as requested and now resent with the new comment.
And I believe that _mesa_all_varyings_in_vbos is equivalent
to vbo_all_varyings_in_vbos but working on a VAO. Else we would get a
change in behavior.

So: Ping.

Thanks

Mathias

On Friday, June 17, 2016 20:03:52 mathias.froehl...@gmx.net wrote:
> From: Mathias Fröhlich 
> 
> Hi,
> 
> The first two patches fix a bug in tracking the VAO internal
> state. The majority of the changeset makes more use of the
> state currently tracked in the VAO and transitions to use
> more of the first order information found in the VAO instead
> of relying on the gl_client_array members that mirror the
> VAO fields. The last two patches rip out members from
> gl_client_array that are set but no longer used.
> 
> Please review,
> 
> Thanks
> 
> Mathias
> 
> 
> Mathias Fröhlich (11):
>   mesa: Add flush_vertices argument to _mesa_bind_vertex_buffer.
>   mesa: Unbind deleted vbo using _mesa_bind_vertex_buffer.
>   mesa: Implement _mesa_all_varyings_in_vbos.
>   vbo: Walk the VAO to see if all varyings are in vbos.
>   vbo: Walk the VAO to check for mapped buffers.
>   mesa: Walk the VAO in _mesa_print_arrays.
>   vbo: Walk the VAO in print_draw_arrays.
>   vbo: Walk the VAO in check_array_data.
>   vbo: Use the VAO array enabled flags in vbo_exec_array.
>   mesa: Remove set but not used gl_client_array::Enabled.
>   mesa: Remove set but not used gl_client_array::Stride.
> 
>  src/mesa/drivers/common/meta.c   |  16 ++--
>  src/mesa/main/arrayobj.c |  35 
>  src/mesa/main/arrayobj.h |   4 +
>  src/mesa/main/bufferobj.c|  11 ++-
>  src/mesa/main/mtypes.h   |   2 -
>  src/mesa/main/varray.c   |  70 +++
>  src/mesa/main/varray.h   |   4 +-
>  src/mesa/state_tracker/st_cb_rasterpos.c |   2 -
>  src/mesa/vbo/vbo_context.c   |   2 -
>  src/mesa/vbo/vbo_exec_array.c| 141 
> ++-
>  src/mesa/vbo/vbo_exec_draw.c |   2 -
>  src/mesa/vbo/vbo_save_draw.c |   2 -
>  src/mesa/vbo/vbo_split_copy.c|   8 +-
>  13 files changed, 171 insertions(+), 128 deletions(-)
> 
> 

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Re: [Mesa-dev] [PATCH 03/11] mesa: Implement _mesa_all_varyings_in_vbos.

[Mathias Fröhlich]

Hi,

On Thursday, June 23, 2016 16:53:59 Fredrik Höglund wrote:
> On Friday 17 June 2016, mathias.froehl...@gmx.net wrote:
> > From: Mathias Fröhlich 
> > 
> > Implement the equivalent of vbo_all_varyings_in_vbos for
> > vertex array objects.
> > 
> > Signed-off-by: Mathias Fröhlich 
> > ---
> >  src/mesa/main/arrayobj.c | 35 +++
> >  src/mesa/main/arrayobj.h |  4 
> >  2 files changed, 39 insertions(+)
> > 
> > diff --git a/src/mesa/main/arrayobj.c b/src/mesa/main/arrayobj.c
> > index 9c3451e..041ee63 100644
> > --- a/src/mesa/main/arrayobj.c
> > +++ b/src/mesa/main/arrayobj.c
> > @@ -359,6 +359,41 @@ _mesa_update_vao_client_arrays(struct gl_context *ctx,
> >  }
> >  
> >  
> > +bool
> > +_mesa_all_varyings_in_vbos(const struct gl_vertex_array_object *vao)
> > +{
> > +   /* Walk those enabled arrays that have the default vbo attached */
> > +   GLbitfield64 mask = vao->_Enabled & ~vao->VertexAttribBufferMask;
> > +
> > +   while (mask) {
> > +  /** We do not use u_bit_scan64 as we can here walk
> > +   *  multiple attrib arrays at once
> > +   */
> > +  const int i = ffsll(mask) - 1;
> > +  const struct gl_vertex_attrib_array *attrib_array =
> > + &vao->VertexAttrib[i];
> > +  const struct gl_vertex_buffer_binding *buffer_binding =
> > + &vao->VertexBinding[attrib_array->VertexBinding];
> > +
> > +  /* Only enabled arrays shall appear in the _Enabled bitmask */
> > +  assert(attrib_array->Enabled);
> > +  /* We have already masked out vao->VertexAttribBufferMask  */
> > +  assert(!_mesa_is_bufferobj(buffer_binding->BufferObj));
> > +
> > +  /* Bail out once we find the first non vbo with a non zero stride */
> > +  if (buffer_binding->Stride != 0)
> > + return false;
> 
> I'm not sure if this is correct.  The default value for Stride is 16,
> not 0.  The only way Stride can be zero in a binding point that doesn't
> have a buffer object bound is if the user has explicitly called
> glBindVertexBuffer() with both the buffer and stride parameters set
> to zero.
> 
> StrideB in gl_client_array on the other hand is always zero when the array
> is one of the currval arrays managed by the VBO context.  It is never zero
> when the array is a user array that has been specified with gl*Pointer().
> 
> I think the point of vbo_all_varyings_in_vbos() is to return false if any
> enabled array doesn't have a VBO bound, and is not one of the currval
> arrays.

Additionally vbo_all_varyings_in_vbos() treats zero stride user
arrays like a current vertex attribute values. Already because
vbo_all_varyings_in_vbos() does not distinguish between a user
zero stride array and a current attribute value which is presented likewise.
Also I believe it's legal to call glBindVertexBuffer() with zero buffer
and stride - or am I wrong here?
So IMO what you write would result in a change of behavior.

Mathias
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Re: [Mesa-dev] [PATCH v2 15/35] i965/blorp: Add an isl_view to blorp_surface_info

[Pohjolainen, Topi]

On Tue, Jul 26, 2016 at 03:02:06PM -0700, Jason Ekstrand wrote:
> Eventually, this will be the actual view that gets passed into isl to
> create the surface state.  For now, we just use it for the format and the
> swizzle.
> ---
>  src/mesa/drivers/dri/i965/brw_blorp.c | 38 
> +++
>  src/mesa/drivers/dri/i965/brw_blorp.h | 16 ++-
>  src/mesa/drivers/dri/i965/brw_blorp_blit.cpp  | 34 
>  src/mesa/drivers/dri/i965/brw_blorp_clear.cpp |  2 +-
>  src/mesa/drivers/dri/i965/gen8_blorp.c| 29 
>  5 files changed, 64 insertions(+), 55 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index 8f7690c..ef256a7 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -43,9 +43,11 @@ brw_blorp_surface_info_init(struct brw_context *brw,
>  * using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it had 
> better
>  * be a multiple of num_samples.
>  */
> +   unsigned layer_multiplier = 1;

In principle we could just:

  const unsigned layer_multiplier = MAX2(mt->num_samples, 1);

> if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
> mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
>assert(mt->num_samples <= 1 || layer % mt->num_samples == 0);
> +  layer_multiplier = MAX2(mt->num_samples, 1);
> }
>  
> intel_miptree_check_level_layer(mt, level, layer);
> @@ -61,13 +63,27 @@ brw_blorp_surface_info_init(struct brw_context *brw,
>info->aux_usage = ISL_AUX_USAGE_NONE;
> }
>  
> +   info->view = (struct isl_view) {
> +  .usage = is_render_target ? ISL_SURF_USAGE_RENDER_TARGET_BIT :
> +  ISL_SURF_USAGE_TEXTURE_BIT,
> +  .format = ISL_FORMAT_UNSUPPORTED, /* Set later */
> +  .base_level = level,
> +  .levels = 1,
> +  .base_array_layer = layer / layer_multiplier,
> +  .array_len = 1,
> +  .channel_select = {
> + ISL_CHANNEL_SELECT_RED,
> + ISL_CHANNEL_SELECT_GREEN,
> + ISL_CHANNEL_SELECT_BLUE,
> + ISL_CHANNEL_SELECT_ALPHA,
> +  },
> +   };
> +
> info->level = level;
> info->layer = layer;
> info->width = minify(mt->physical_width0, level - mt->first_level);
> info->height = minify(mt->physical_height0, level - mt->first_level);
>  
> -   info->swizzle = SWIZZLE_XYZW;
> -
> if (format == MESA_FORMAT_NONE)
>format = mt->format;
>  
> @@ -75,8 +91,8 @@ brw_blorp_surface_info_init(struct brw_context *brw,
> case MESA_FORMAT_S_UINT8:
>assert(info->surf.tiling == ISL_TILING_W);
>/* Prior to Broadwell, we can't render to R8_UINT */
> -  info->brw_surfaceformat = brw->gen >= 8 ? BRW_SURFACEFORMAT_R8_UINT :
> -BRW_SURFACEFORMAT_R8_UNORM;
> +  info->view.format = brw->gen >= 8 ? BRW_SURFACEFORMAT_R8_UINT :
> +  BRW_SURFACEFORMAT_R8_UNORM;
>break;
> case MESA_FORMAT_Z24_UNORM_X8_UINT:
>/* It would make sense to use BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
> @@ -89,20 +105,20 @@ brw_blorp_surface_info_init(struct brw_context *brw,
> * pattern as long as we copy the right amount of data, so just map it
> * as 8-bit BGRA.
> */
> -  info->brw_surfaceformat = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
> +  info->view.format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
>break;
> case MESA_FORMAT_Z_FLOAT32:
> -  info->brw_surfaceformat = BRW_SURFACEFORMAT_R32_FLOAT;
> +  info->view.format = BRW_SURFACEFORMAT_R32_FLOAT;
>break;
> case MESA_FORMAT_Z_UNORM16:
> -  info->brw_surfaceformat = BRW_SURFACEFORMAT_R16_UNORM;
> +  info->view.format = BRW_SURFACEFORMAT_R16_UNORM;
>break;
> default: {
>if (is_render_target) {
>   assert(brw->format_supported_as_render_target[format]);
> - info->brw_surfaceformat = brw->render_target_format[format];
> + info->view.format = brw->render_target_format[format];
>} else {
> - info->brw_surfaceformat = brw_format_for_mesa_format(format);
> + info->view.format = brw_format_for_mesa_format(format);
>}
>break;
> }
> @@ -111,7 +127,7 @@ brw_blorp_surface_info_init(struct brw_context *brw,
> uint32_t x_offset, y_offset;
> intel_miptree_get_image_offset(mt, level, layer, &x_offset, &y_offset);
>  
> -   uint8_t bs = isl_format_get_layout(info->brw_surfaceformat)->bpb / 8;
> +   uint8_t bs = isl_format_get_layout(info->view.format)->bpb / 8;
> isl_tiling_get_intratile_offset_el(&brw->isl_dev, info->surf.tiling, bs,
>info->surf.row_pitch, x_offset, 
> y_offset,
>&info->bo_offset,
> @@ -287,7 +303,7 @@ brw_blorp_emit_surface_state(struct brw_context *brw,
> }
>  
> struct

Re: [Mesa-dev] [PATCH v2 15/35] i965/blorp: Add an isl_view to blorp_surface_info

[Pohjolainen, Topi]

On Tue, Jul 26, 2016 at 03:02:06PM -0700, Jason Ekstrand wrote:
> Eventually, this will be the actual view that gets passed into isl to
> create the surface state.  For now, we just use it for the format and the
> swizzle.
> ---
>  src/mesa/drivers/dri/i965/brw_blorp.c | 38 
> +++
>  src/mesa/drivers/dri/i965/brw_blorp.h | 16 ++-
>  src/mesa/drivers/dri/i965/brw_blorp_blit.cpp  | 34 
>  src/mesa/drivers/dri/i965/brw_blorp_clear.cpp |  2 +-
>  src/mesa/drivers/dri/i965/gen8_blorp.c| 29 
>  5 files changed, 64 insertions(+), 55 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index 8f7690c..ef256a7 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -43,9 +43,11 @@ brw_blorp_surface_info_init(struct brw_context *brw,
>  * using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it had 
> better
>  * be a multiple of num_samples.
>  */
> +   unsigned layer_multiplier = 1;
> if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
> mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
>assert(mt->num_samples <= 1 || layer % mt->num_samples == 0);
> +  layer_multiplier = MAX2(mt->num_samples, 1);
> }
>  
> intel_miptree_check_level_layer(mt, level, layer);
> @@ -61,13 +63,27 @@ brw_blorp_surface_info_init(struct brw_context *brw,
>info->aux_usage = ISL_AUX_USAGE_NONE;
> }
>  
> +   info->view = (struct isl_view) {
> +  .usage = is_render_target ? ISL_SURF_USAGE_RENDER_TARGET_BIT :
> +  ISL_SURF_USAGE_TEXTURE_BIT,
> +  .format = ISL_FORMAT_UNSUPPORTED, /* Set later */
> +  .base_level = level,
> +  .levels = 1,
> +  .base_array_layer = layer / layer_multiplier,
> +  .array_len = 1,
> +  .channel_select = {
> + ISL_CHANNEL_SELECT_RED,
> + ISL_CHANNEL_SELECT_GREEN,
> + ISL_CHANNEL_SELECT_BLUE,
> + ISL_CHANNEL_SELECT_ALPHA,
> +  },
> +   };
> +
> info->level = level;
> info->layer = layer;
> info->width = minify(mt->physical_width0, level - mt->first_level);
> info->height = minify(mt->physical_height0, level - mt->first_level);
>  
> -   info->swizzle = SWIZZLE_XYZW;
> -
> if (format == MESA_FORMAT_NONE)
>format = mt->format;
>  
> @@ -75,8 +91,8 @@ brw_blorp_surface_info_init(struct brw_context *brw,
> case MESA_FORMAT_S_UINT8:
>assert(info->surf.tiling == ISL_TILING_W);
>/* Prior to Broadwell, we can't render to R8_UINT */
> -  info->brw_surfaceformat = brw->gen >= 8 ? BRW_SURFACEFORMAT_R8_UINT :
> -BRW_SURFACEFORMAT_R8_UNORM;
> +  info->view.format = brw->gen >= 8 ? BRW_SURFACEFORMAT_R8_UINT :
> +  BRW_SURFACEFORMAT_R8_UNORM;

Should we use ISL_FORMAT_ instead? Or at least the cast. Assigning an enum
with another always looks bad unless it is clear they happen to have exact
same values.

>break;
> case MESA_FORMAT_Z24_UNORM_X8_UINT:
>/* It would make sense to use BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
> @@ -89,20 +105,20 @@ brw_blorp_surface_info_init(struct brw_context *brw,
> * pattern as long as we copy the right amount of data, so just map it
> * as 8-bit BGRA.
> */
> -  info->brw_surfaceformat = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
> +  info->view.format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
>break;
> case MESA_FORMAT_Z_FLOAT32:
> -  info->brw_surfaceformat = BRW_SURFACEFORMAT_R32_FLOAT;
> +  info->view.format = BRW_SURFACEFORMAT_R32_FLOAT;
>break;
> case MESA_FORMAT_Z_UNORM16:
> -  info->brw_surfaceformat = BRW_SURFACEFORMAT_R16_UNORM;
> +  info->view.format = BRW_SURFACEFORMAT_R16_UNORM;
>break;
> default: {
>if (is_render_target) {
>   assert(brw->format_supported_as_render_target[format]);
> - info->brw_surfaceformat = brw->render_target_format[format];
> + info->view.format = brw->render_target_format[format];

Perhaps use the cast such as you do further down in the patch:

info->view.format =
   (enum isl_format)brw->render_target_format[format];

>} else {
> - info->brw_surfaceformat = brw_format_for_mesa_format(format);
> + info->view.format = brw_format_for_mesa_format(format);
>}
>break;
> }
> @@ -111,7 +127,7 @@ brw_blorp_surface_info_init(struct brw_context *brw,
> uint32_t x_offset, y_offset;
> intel_miptree_get_image_offset(mt, level, layer, &x_offset, &y_offset);
>  
> -   uint8_t bs = isl_format_get_layout(info->brw_surfaceformat)->bpb / 8;
> +   uint8_t bs = isl_format_get_layout(info->view.format)->bpb / 8;
> isl_tiling_get_intratile_offset_el(&brw->isl_dev, info->surf.tiling, bs,
>   

[Mesa-dev] [PATCH 03/11] mesa: Implement _mesa_all_varyings_in_vbos.

[Mathias . Froehlich]

From: Mathias Fröhlich 

Implement the equivalent of vbo_all_varyings_in_vbos for
vertex array objects.

v2: Update comment.

Signed-off-by: Mathias Fröhlich 
---
 src/mesa/main/arrayobj.c | 35 +++
 src/mesa/main/arrayobj.h |  4 
 2 files changed, 39 insertions(+)

diff --git a/src/mesa/main/arrayobj.c b/src/mesa/main/arrayobj.c
index 9c3451e..becf32f 100644
--- a/src/mesa/main/arrayobj.c
+++ b/src/mesa/main/arrayobj.c
@@ -359,6 +359,41 @@ _mesa_update_vao_client_arrays(struct gl_context *ctx,
 }
 
 
+bool
+_mesa_all_varyings_in_vbos(const struct gl_vertex_array_object *vao)
+{
+   /* Walk those enabled arrays that have the default vbo attached */
+   GLbitfield64 mask = vao->_Enabled & ~vao->VertexAttribBufferMask;
+
+   while (mask) {
+  /* Do not use u_bit_scan64 as we can walk multiple
+   * attrib arrays at once
+   */
+  const int i = ffsll(mask) - 1;
+  const struct gl_vertex_attrib_array *attrib_array =
+ &vao->VertexAttrib[i];
+  const struct gl_vertex_buffer_binding *buffer_binding =
+ &vao->VertexBinding[attrib_array->VertexBinding];
+
+  /* Only enabled arrays shall appear in the _Enabled bitmask */
+  assert(attrib_array->Enabled);
+  /* We have already masked out vao->VertexAttribBufferMask  */
+  assert(!_mesa_is_bufferobj(buffer_binding->BufferObj));
+
+  /* Bail out once we find the first non vbo with a non zero stride */
+  if (buffer_binding->Stride != 0)
+ return false;
+
+  /* Note that we cannot use the xor variant since the _BoundArray mask
+   * may contain array attributes that are bound but not enabled.
+   */
+  mask &= ~buffer_binding->_BoundArrays;
+   }
+
+   return true;
+}
+
+
 /**/
 /* API Functions  */
 /**/
diff --git a/src/mesa/main/arrayobj.h b/src/mesa/main/arrayobj.h
index 6a4247f..d30c85c 100644
--- a/src/mesa/main/arrayobj.h
+++ b/src/mesa/main/arrayobj.h
@@ -81,6 +81,10 @@ extern void
 _mesa_update_vao_client_arrays(struct gl_context *ctx,
struct gl_vertex_array_object *vao);
 
+/* Returns true if all varying arrays reside in vbos */
+extern bool
+_mesa_all_varyings_in_vbos(const struct gl_vertex_array_object *vao);
+
 /*
  * API functions
  */
-- 
2.5.5

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[Mesa-dev] [PATCH 13/13] glsl: free hash tables earlier

[Timothy Arceri]

These are only used by get_matching_input() which has been call
at this point so free the hash tables.
---
 src/compiler/glsl/link_varyings.cpp | 10 +++---
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/src/compiler/glsl/link_varyings.cpp 
b/src/compiler/glsl/link_varyings.cpp
index d48c680..91d8974 100644
--- a/src/compiler/glsl/link_varyings.cpp
+++ b/src/compiler/glsl/link_varyings.cpp
@@ -2156,6 +2156,9 @@ assign_varying_locations(struct gl_context *ctx,
   }
}
 
+   hash_table_dtor(consumer_inputs);
+   hash_table_dtor(consumer_interface_inputs);
+
for (unsigned i = 0; i < num_tfeedback_decls; ++i) {
   if (!tfeedback_decls[i].is_varying())
  continue;
@@ -2165,8 +2168,6 @@ assign_varying_locations(struct gl_context *ctx,
 
   if (matched_candidate == NULL) {
  hash_table_dtor(tfeedback_candidates);
- hash_table_dtor(consumer_inputs);
- hash_table_dtor(consumer_interface_inputs);
  return false;
   }
 
@@ -2185,15 +2186,10 @@ assign_varying_locations(struct gl_context *ctx,
 
   if (!tfeedback_decls[i].assign_location(ctx, prog)) {
  hash_table_dtor(tfeedback_candidates);
- hash_table_dtor(consumer_inputs);
- hash_table_dtor(consumer_interface_inputs);
  return false;
   }
}
-
hash_table_dtor(tfeedback_candidates);
-   hash_table_dtor(consumer_inputs);
-   hash_table_dtor(consumer_interface_inputs);
 
if (consumer && producer) {
   foreach_in_list(ir_instruction, node, consumer->ir) {
-- 
2.7.4

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[Mesa-dev] [PATCH 07/13] glsl: disable dead code removal of lowered ubos

[Timothy Arceri]

This lets us assign uniform storage for packed UBOs after
they have been lowered otherwise the var is removed too early.
---
 src/compiler/glsl/glsl_parser_extras.cpp   | 5 +++--
 src/compiler/glsl/ir_optimization.h| 4 +++-
 src/compiler/glsl/link_varyings.cpp| 2 +-
 src/compiler/glsl/linker.cpp   | 1 +
 src/compiler/glsl/opt_dead_code.cpp| 8 +---
 src/compiler/glsl/test_optpass.cpp | 5 +++--
 src/mesa/drivers/dri/i965/brw_link.cpp | 2 +-
 src/mesa/main/ff_fragment_shader.cpp   | 2 +-
 src/mesa/program/ir_to_mesa.cpp| 2 +-
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 +-
 10 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/src/compiler/glsl/glsl_parser_extras.cpp 
b/src/compiler/glsl/glsl_parser_extras.cpp
index e702291..7842020 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -1879,7 +1879,7 @@ _mesa_glsl_compile_shader(struct gl_context *ctx, struct 
gl_shader *shader,
   /* Do some optimization at compile time to reduce shader IR size
* and reduce later work if the same shader is linked multiple times
*/
-  while (do_common_optimization(shader->ir, false, false, options,
+  while (do_common_optimization(shader->ir, false, false, false, options,
 ctx->Const.NativeIntegers))
  ;
 
@@ -1977,6 +1977,7 @@ _mesa_glsl_compile_shader(struct gl_context *ctx, struct 
gl_shader *shader,
 bool
 do_common_optimization(exec_list *ir, bool linked,
   bool uniform_locations_assigned,
+   bool ubos_lowered,
const struct gl_shader_compiler_options *options,
bool native_integers)
 {
@@ -2019,7 +2020,7 @@ do_common_optimization(exec_list *ir, bool linked,
}
 
if (linked)
-  OPT(do_dead_code, ir, uniform_locations_assigned);
+  OPT(do_dead_code, ir, uniform_locations_assigned, ubos_lowered);
else
   OPT(do_dead_code_unlinked, ir);
OPT(do_dead_code_local, ir);
diff --git a/src/compiler/glsl/ir_optimization.h 
b/src/compiler/glsl/ir_optimization.h
index c29260a..d129210 100644
--- a/src/compiler/glsl/ir_optimization.h
+++ b/src/compiler/glsl/ir_optimization.h
@@ -77,6 +77,7 @@ enum lower_packing_builtins_op {
 
 bool do_common_optimization(exec_list *ir, bool linked,
bool uniform_locations_assigned,
+bool ubos_lowered,
 const struct gl_shader_compiler_options *options,
 bool native_integers);
 
@@ -97,7 +98,8 @@ void do_dead_builtin_varyings(struct gl_context *ctx,
   gl_linked_shader *consumer,
   unsigned num_tfeedback_decls,
   class tfeedback_decl *tfeedback_decls);
-bool do_dead_code(exec_list *instructions, bool uniform_locations_assigned);
+bool do_dead_code(exec_list *instructions, bool uniform_locations_assigned,
+  bool ubos_lowered);
 bool do_dead_code_local(exec_list *instructions);
 bool do_dead_code_unlinked(exec_list *instructions);
 bool do_dead_functions(exec_list *instructions);
diff --git a/src/compiler/glsl/link_varyings.cpp 
b/src/compiler/glsl/link_varyings.cpp
index f6778b6..d48c680 100644
--- a/src/compiler/glsl/link_varyings.cpp
+++ b/src/compiler/glsl/link_varyings.cpp
@@ -582,7 +582,7 @@ remove_unused_shader_inputs_and_outputs(bool 
is_separate_shader_object,
/* Eliminate code that is now dead due to unused inputs/outputs being
 * demoted.
 */
-   while (do_dead_code(sh->ir, false))
+   while (do_dead_code(sh->ir, false, true))
   ;
 
 }
diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index 61f6c42..ba61d39 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -4992,6 +4992,7 @@ link_shaders(struct gl_context *ctx, struct 
gl_shader_program *prog)
   }
 
   while (do_common_optimization(prog->_LinkedShaders[i]->ir, true, false,
+false,
 &ctx->Const.ShaderCompilerOptions[i],
 ctx->Const.NativeIntegers))
 ;
diff --git a/src/compiler/glsl/opt_dead_code.cpp 
b/src/compiler/glsl/opt_dead_code.cpp
index 75e668a..980660e 100644
--- a/src/compiler/glsl/opt_dead_code.cpp
+++ b/src/compiler/glsl/opt_dead_code.cpp
@@ -43,7 +43,8 @@ static bool debug = false;
  * for usage on an unlinked instruction stream.
  */
 bool
-do_dead_code(exec_list *instructions, bool uniform_locations_assigned)
+do_dead_code(exec_list *instructions, bool uniform_locations_assigned,
+ bool ubos_lowered)
 {
ir_variable_refcount_visitor v;
bool progress = false;
@@ -144,7 +145,8 @@ do_dead_code(exec_list *instructions, bool 
uniform_locations_assigned)
  * layouts, do not eliminate it.
   

[Mesa-dev] [PATCH 11/13] mesa/i965: create Driver.ProcessGLSLIR()

[Timothy Arceri]

This allows us to do backend specific processing on GLSL IR from
the shared linker.
---
 src/mesa/drivers/dri/i965/brw_link.cpp  | 12 ++--
 src/mesa/drivers/dri/i965/brw_program.c |  1 +
 src/mesa/drivers/dri/i965/brw_shader.h  |  4 
 src/mesa/main/dd.h  |  3 +++
 4 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
b/src/mesa/drivers/dri/i965/brw_link.cpp
index e56df93..244c8f0 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -114,12 +114,12 @@ brw_common_opts(struct gl_linked_shader *shader, struct 
gl_context *ctx,
} while (progress);
 }
 
-static void
-process_glsl_ir(struct brw_context *brw,
-struct gl_shader_program *shader_prog,
-struct gl_linked_shader *shader)
+extern "C" void
+brw_process_glsl_ir(struct gl_context *ctx,
+struct gl_shader_program *shader_prog,
+struct gl_linked_shader *shader)
 {
-   struct gl_context *ctx = &brw->ctx;
+   struct brw_context *brw = brw_context(ctx);
const struct brw_compiler *compiler = brw->intelScreen->compiler;
const struct gl_shader_compiler_options *options =
   &ctx->Const.ShaderCompilerOptions[shader->Stage];
@@ -233,7 +233,7 @@ brw_link_shader(struct gl_context *ctx, struct 
gl_shader_program *shProg)
 
   _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 
-  process_glsl_ir(brw, shProg, shader);
+  brw_process_glsl_ir(ctx, shProg, shader);
 
   /* Make a pass over the IR to add state references for any built-in
* uniforms that are used.  This has to be done now (during linking).
diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
b/src/mesa/drivers/dri/i965/brw_program.c
index 7785490..559bb4d 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -377,6 +377,7 @@ void brwInitFragProgFuncs( struct dd_function_table 
*functions )
 
functions->NewShader = brw_new_shader;
functions->LinkShader = brw_link_shader;
+   functions->ProcessGLSLIR = brw_process_glsl_ir;
 
functions->MemoryBarrier = brw_memory_barrier;
 }
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h 
b/src/mesa/drivers/dri/i965/brw_shader.h
index e61c080..65acc30 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -290,6 +290,10 @@ bool brw_cs_precompile(struct gl_context *ctx,
 
 GLboolean brw_link_shader(struct gl_context *ctx, struct gl_shader_program 
*prog);
 struct gl_linked_shader *brw_new_shader(gl_shader_stage stage);
+void
+brw_process_glsl_ir(struct gl_context *ctx,
+struct gl_shader_program *shader_prog,
+struct gl_linked_shader *shader);
 
 int type_size_scalar(const struct glsl_type *type);
 int type_size_vec4(const struct glsl_type *type);
diff --git a/src/mesa/main/dd.h b/src/mesa/main/dd.h
index 114cbd2..3f9ebdf 100644
--- a/src/mesa/main/dd.h
+++ b/src/mesa/main/dd.h
@@ -786,6 +786,9 @@ struct dd_function_table {
/*@{*/
struct gl_linked_shader *(*NewShader)(gl_shader_stage stage);
void (*UseProgram)(struct gl_context *ctx, struct gl_shader_program 
*shProg);
+   void (*ProcessGLSLIR)(struct gl_context *ctx,
+ struct gl_shader_program *shader_prog,
+ struct gl_linked_shader *shader);
/*@}*/
 
/**
-- 
2.7.4

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[Mesa-dev] [PATCH 10/13] i965: move common optimisation loop to a helper

[Timothy Arceri]

---
 src/mesa/drivers/dri/i965/brw_link.cpp | 50 --
 1 file changed, 30 insertions(+), 20 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
b/src/mesa/drivers/dri/i965/brw_link.cpp
index efd67e7..e56df93 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -86,6 +86,35 @@ brw_lower_packing_builtins(struct brw_context *brw,
 }
 
 static void
+brw_common_opts(struct gl_linked_shader *shader, struct gl_context *ctx,
+bool uniform_locs_assigned,
+const struct brw_compiler *compiler,
+const struct gl_shader_compiler_options *options)
+{
+   bool progress;
+   do {
+  progress = false;
+
+  if (compiler->scalar_stage[shader->Stage]) {
+ if (shader->Stage == MESA_SHADER_VERTEX ||
+ shader->Stage == MESA_SHADER_FRAGMENT)
+brw_do_channel_expressions(shader->ir);
+ brw_do_vector_splitting(shader->ir);
+  }
+
+  progress = do_lower_jumps(shader->ir, true, true,
+true, /* main return */
+false, /* continue */
+false /* loops */
+) || progress;
+
+  progress = do_common_optimization(shader->ir, true,
+uniform_locs_assigned, true, options,
+ctx->Const.NativeIntegers) || progress;
+   } while (progress);
+}
+
+static void
 process_glsl_ir(struct brw_context *brw,
 struct gl_shader_program *shader_prog,
 struct gl_linked_shader *shader)
@@ -149,26 +178,7 @@ process_glsl_ir(struct brw_context *brw,
  _mesa_shader_stage_to_abbrev(shader->Stage));
}
 
-   bool progress;
-   do {
-  progress = false;
-
-  if (compiler->scalar_stage[shader->Stage]) {
- if (shader->Stage == MESA_SHADER_VERTEX ||
- shader->Stage == MESA_SHADER_FRAGMENT)
-brw_do_channel_expressions(shader->ir);
- brw_do_vector_splitting(shader->ir);
-  }
-
-  progress = do_lower_jumps(shader->ir, true, true,
-true, /* main return */
-false, /* continue */
-false /* loops */
-) || progress;
-
-  progress = do_common_optimization(shader->ir, true, true, true,
-options, ctx->Const.NativeIntegers) || 
progress;
-   } while (progress);
+   brw_common_opts(shader, ctx, false, compiler, options);
 
validate_ir_tree(shader->ir);
 
-- 
2.7.4

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[Mesa-dev] [PATCH 04/13] glsl: remove remaining tabs in link_uniform_initializers.cpp

[Timothy Arceri]

---
 src/compiler/glsl/link_uniform_initializers.cpp | 78 -
 1 file changed, 39 insertions(+), 39 deletions(-)

diff --git a/src/compiler/glsl/link_uniform_initializers.cpp 
b/src/compiler/glsl/link_uniform_initializers.cpp
index 3750021..021e950 100644
--- a/src/compiler/glsl/link_uniform_initializers.cpp
+++ b/src/compiler/glsl/link_uniform_initializers.cpp
@@ -46,30 +46,30 @@ get_storage(struct gl_shader_program *prog, const char 
*name)
 
 void
 copy_constant_to_storage(union gl_constant_value *storage,
-const ir_constant *val,
-const enum glsl_base_type base_type,
+ const ir_constant *val,
+ const enum glsl_base_type base_type,
  const unsigned int elements,
  unsigned int boolean_true)
 {
for (unsigned int i = 0; i < elements; i++) {
   switch (base_type) {
   case GLSL_TYPE_UINT:
-storage[i].u = val->value.u[i];
-break;
+ storage[i].u = val->value.u[i];
+ break;
   case GLSL_TYPE_INT:
   case GLSL_TYPE_SAMPLER:
-storage[i].i = val->value.i[i];
-break;
+ storage[i].i = val->value.i[i];
+ break;
   case GLSL_TYPE_FLOAT:
-storage[i].f = val->value.f[i];
-break;
+ storage[i].f = val->value.f[i];
+ break;
   case GLSL_TYPE_DOUBLE:
  /* XXX need to check on big-endian */
  memcpy(&storage[i * 2].u, &val->value.d[i], sizeof(double));
  break;
   case GLSL_TYPE_BOOL:
-storage[i].b = val->value.b[i] ? boolean_true : 0;
-break;
+ storage[i].b = val->value.b[i] ? boolean_true : 0;
+ break;
   case GLSL_TYPE_ARRAY:
   case GLSL_TYPE_STRUCT:
   case GLSL_TYPE_IMAGE:
@@ -79,11 +79,11 @@ copy_constant_to_storage(union gl_constant_value *storage,
   case GLSL_TYPE_SUBROUTINE:
   case GLSL_TYPE_FUNCTION:
   case GLSL_TYPE_ERROR:
-/* All other types should have already been filtered by other
- * paths in the caller.
- */
-assert(!"Should not get here.");
-break;
+ /* All other types should have already been filtered by other
+  * paths in the caller.
+  */
+ assert(!"Should not get here.");
+ break;
   }
}
 }
@@ -102,9 +102,9 @@ set_opaque_binding(void *mem_ctx, gl_shader_program *prog,
   const glsl_type *const element_type = type->fields.array;
 
   for (unsigned int i = 0; i < type->length; i++) {
-const char *element_name = ralloc_asprintf(mem_ctx, "%s[%d]", name, i);
+ const char *element_name = ralloc_asprintf(mem_ctx, "%s[%d]", name, 
i);
 
-set_opaque_binding(mem_ctx, prog, element_type,
+ set_opaque_binding(mem_ctx, prog, element_type,
 element_name, binding);
   }
} else {
@@ -172,7 +172,7 @@ set_block_binding(gl_shader_program *prog, const char 
*block_name,
 
 void
 set_uniform_initializer(void *mem_ctx, gl_shader_program *prog,
-   const char *name, const glsl_type *type,
+const char *name, const glsl_type *type,
 ir_constant *val, unsigned int boolean_true)
 {
const glsl_type *t_without_array = type->without_array();
@@ -182,12 +182,12 @@ set_uniform_initializer(void *mem_ctx, gl_shader_program 
*prog,
   field_constant = (ir_constant *)val->components.get_head();
 
   for (unsigned int i = 0; i < type->length; i++) {
-const glsl_type *field_type = type->fields.structure[i].type;
-const char *field_name = ralloc_asprintf(mem_ctx, "%s.%s", name,
-   type->fields.structure[i].name);
-set_uniform_initializer(mem_ctx, prog, field_name,
+ const glsl_type *field_type = type->fields.structure[i].type;
+ const char *field_name = ralloc_asprintf(mem_ctx, "%s.%s", name,
+type->fields.structure[i].name);
+ set_uniform_initializer(mem_ctx, prog, field_name,
  field_type, field_constant, boolean_true);
-field_constant = (ir_constant *)field_constant->next;
+ field_constant = (ir_constant *)field_constant->next;
   }
   return;
} else if (t_without_array->is_record() ||
@@ -195,9 +195,9 @@ set_uniform_initializer(void *mem_ctx, gl_shader_program 
*prog,
   const glsl_type *const element_type = type->fields.array;
 
   for (unsigned int i = 0; i < type->length; i++) {
-const char *element_name = ralloc_asprintf(mem_ctx, "%s[%d]", name, i);
+ const char *element_name = ralloc_asprintf(mem_ctx, "%s[%d]", name, 
i);
 
-set_uniform_initializer(mem_ctx, prog, element_name,
+ set_uniform_initializer(mem_ctx, prog, element_name,
  element_type, val->array_el

Re: [Mesa-dev] [PATCH v2 13/35] i965/blorp: Refactor interleaved multisample destination handling

[Pohjolainen, Topi]

On Tue, Jul 26, 2016 at 03:02:04PM -0700, Jason Ekstrand wrote:
> We put all of the code for fake IMS together.  This requires moving a bit
> of the program key setup code further down so that it gets the right values
> out of the final surface.
> 
> Reviewed-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 71 
> +---
>  1 file changed, 34 insertions(+), 37 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
> b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> index c337a86..03e4984 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> @@ -1698,28 +1698,6 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
>unreachable("Unrecognized blorp format");
> }
>  
> -   if (brw->gen > 6) {
> -  /* Gen7's rendering hardware only supports the IMS layout for depth and
> -   * stencil render targets.  Blorp always maps its destination surface 
> as
> -   * a color render target (even if it's actually a depth or stencil
> -   * buffer).  So if the destination is IMS, we'll have to map it as a
> -   * single-sampled texture and interleave the samples ourselves.
> -   */
> -  if (dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
> - params.dst.surf.samples = 1;
> - params.dst.surf.msaa_layout = ISL_MSAA_LAYOUT_NONE;
> -  }
> -   }
> -
> -   if (params.src.surf.samples > 0 && params.dst.surf.samples > 1) {
> -  /* We are blitting from a multisample buffer to a multisample buffer, 
> so
> -   * we must preserve samples within a pixel.  This means we have to
> -   * arrange for the WM program to run once per sample rather than once
> -   * per pixel.
> -   */
> -  wm_prog_key.persample_msaa_dispatch = true;
> -   }
> -
> /* Scaled blitting or not. */
> wm_prog_key.blit_scaled =
>((dst_x1 - dst_x0) == (src_x1 - src_x0) &&
> @@ -1759,20 +1737,8 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
> wm_prog_key.src_samples = src_mt->num_samples;
> wm_prog_key.dst_samples = dst_mt->num_samples;
>  
> -   /* tex_samples and rt_samples are the sample counts that are set up in
> -* SURFACE_STATE.
> -*/
> -   wm_prog_key.tex_samples = params.src.surf.samples;
> -   wm_prog_key.rt_samples  = params.dst.surf.samples;
> -
> wm_prog_key.tex_aux_usage = params.src.aux_usage;
>  
> -   /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
> -* use to access the source and destination surfaces.
> -*/
> -   wm_prog_key.tex_layout = params.src.surf.msaa_layout;
> -   wm_prog_key.rt_layout = params.dst.surf.msaa_layout;
> -
> /* src_layout and dst_layout indicate the true MSAA layout used by src and
>  * dst.
>  */
> @@ -1809,7 +1775,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
>params.wm_inputs.src_z = 0;
> }
>  
> -   if (params.dst.surf.samples <= 1 && dst_mt->num_samples > 1) {
> +   if (brw->gen > 6 && dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
>/* We must expand the rectangle we send through the rendering pipeline,
> * to account for the fact that we are mapping the destination region 
> as
> * single-sampled when it is in fact multisampled.  We must also align
> @@ -1822,8 +1788,8 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
> * If it's UMS, then we have no choice but to set up the rendering
> * pipeline as multisampled.
> */
> -  assert(dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS);
> -  switch (dst_mt->num_samples) {
> +  assert(params.dst.surf.msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED);

==

> +  switch (params.dst.surf.samples) {
>case 2:
>   params.x0 = ROUND_DOWN_TO(params.x0 * 2, 4);
>   params.y0 = ROUND_DOWN_TO(params.y0, 4);
> @@ -1851,6 +1817,16 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
>default:
>   unreachable("Unrecognized sample count in brw_blorp_blit_params 
> ctor");
>}
> +
> +  /* Gen7's rendering hardware only supports the IMS layout for depth and
> +   * stencil render targets.  Blorp always maps its destination surface 
> as
> +   * a color render target (even if it's actually a depth or stencil
> +   * buffer).  So if the destination is IMS, we'll have to map it as a
> +   * single-sampled texture and interleave the samples ourselves.
> +   */
> +  params.dst.surf.samples = 1;
> +  params.dst.surf.msaa_layout = ISL_MSAA_LAYOUT_NONE;
> +
>wm_prog_key.use_kill = true;
> }
>  
> @@ -1952,6 +1928,27 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
>params.src.y_offset /= 2;
> }
>  
> +   /* tex_samples and rt_samples are the sample counts that are set up in
> +* SURFACE_STATE.
> +*/
> +   wm_prog_key.tex_samples = params.src.surf.samples;
> +   wm_prog_key.rt_sample

[Mesa-dev] [PATCH 05/13] glsl: move uniform linking code to new link_setup_uniform_remap_tables()

[Timothy Arceri]

This makes link_assign_uniform_locations() easier to follow.
---
 src/compiler/glsl/link_uniforms.cpp | 330 +++-
 src/compiler/glsl/linker.cpp|   4 +-
 src/compiler/glsl/linker.h  |   5 +-
 3 files changed, 177 insertions(+), 162 deletions(-)

diff --git a/src/compiler/glsl/link_uniforms.cpp 
b/src/compiler/glsl/link_uniforms.cpp
index dbe808f..89196e6 100644
--- a/src/compiler/glsl/link_uniforms.cpp
+++ b/src/compiler/glsl/link_uniforms.cpp
@@ -998,12 +998,168 @@ find_empty_block(struct gl_shader_program *prog,
return -1;
 }
 
+static void
+link_setup_uniform_remap_tables(struct gl_context *ctx,
+struct gl_shader_program *prog,
+unsigned num_explicit_uniform_locs)
+{
+   unsigned total_entries = num_explicit_uniform_locs;
+   unsigned empty_locs =
+  prog->NumUniformRemapTable - num_explicit_uniform_locs;
+
+   /* Reserve all the explicit locations of the active uniforms. */
+   for (unsigned i = 0; i < prog->NumUniformStorage; i++) {
+  if (prog->UniformStorage[i].type->is_subroutine() ||
+  prog->UniformStorage[i].is_shader_storage)
+ continue;
+
+  if (prog->UniformStorage[i].remap_location != UNMAPPED_UNIFORM_LOC) {
+ /* How many new entries for this uniform? */
+ const unsigned entries =
+MAX2(1, prog->UniformStorage[i].array_elements);
+
+ /* Set remap table entries point to correct gl_uniform_storage. */
+ for (unsigned j = 0; j < entries; j++) {
+unsigned element_loc = prog->UniformStorage[i].remap_location + j;
+assert(prog->UniformRemapTable[element_loc] ==
+   INACTIVE_UNIFORM_EXPLICIT_LOCATION);
+prog->UniformRemapTable[element_loc] = &prog->UniformStorage[i];
+ }
+  }
+   }
+
+   /* Reserve locations for rest of the uniforms. */
+   for (unsigned i = 0; i < prog->NumUniformStorage; i++) {
+
+  if (prog->UniformStorage[i].type->is_subroutine() ||
+  prog->UniformStorage[i].is_shader_storage)
+ continue;
+
+  /* Built-in uniforms should not get any location. */
+  if (prog->UniformStorage[i].builtin)
+ continue;
+
+  /* Explicit ones have been set already. */
+  if (prog->UniformStorage[i].remap_location != UNMAPPED_UNIFORM_LOC)
+ continue;
+
+  /* how many new entries for this uniform? */
+  const unsigned entries = MAX2(1, prog->UniformStorage[i].array_elements);
+
+  /* Find UniformRemapTable for empty blocks where we can fit this 
uniform. */
+  int chosen_location = -1;
+
+  if (empty_locs)
+ chosen_location = find_empty_block(prog, &prog->UniformStorage[i]);
+
+  /* Add new entries to the total amount of entries. */
+  total_entries += entries;
+
+  if (chosen_location != -1) {
+ empty_locs -= entries;
+  } else {
+ chosen_location = prog->NumUniformRemapTable;
+
+ /* resize remap table to fit new entries */
+ prog->UniformRemapTable =
+reralloc(prog,
+ prog->UniformRemapTable,
+ gl_uniform_storage *,
+ prog->NumUniformRemapTable + entries);
+ prog->NumUniformRemapTable += entries;
+  }
+
+  /* set pointers for this uniform */
+  for (unsigned j = 0; j < entries; j++)
+ prog->UniformRemapTable[chosen_location + j] =
+&prog->UniformStorage[i];
+
+  /* set the base location in remap table for the uniform */
+  prog->UniformStorage[i].remap_location = chosen_location;
+   }
+
+   /* Verify that total amount of entries for explicit and implicit locations
+* is less than MAX_UNIFORM_LOCATIONS.
+*/
+
+   if (total_entries > ctx->Const.MaxUserAssignableUniformLocations) {
+  linker_error(prog, "count of uniform locations > MAX_UNIFORM_LOCATIONS"
+   "(%u > %u)", total_entries,
+   ctx->Const.MaxUserAssignableUniformLocations);
+   }
+
+   /* Reserve all the explicit locations of the active subroutine uniforms. */
+   for (unsigned i = 0; i < prog->NumUniformStorage; i++) {
+  if (!prog->UniformStorage[i].type->is_subroutine())
+ continue;
+
+  if (prog->UniformStorage[i].remap_location == UNMAPPED_UNIFORM_LOC)
+ continue;
+
+  for (unsigned j = 0; j < MESA_SHADER_STAGES; j++) {
+ struct gl_linked_shader *sh = prog->_LinkedShaders[j];
+ if (!sh)
+continue;
+
+ if (!prog->UniformStorage[i].opaque[j].active)
+continue;
+
+ /* How many new entries for this uniform? */
+ const unsigned entries =
+MAX2(1, prog->UniformStorage[i].array_elements);
+
+ /* Set remap table entries point to correct gl_uniform_storage. */
+ for (unsigned k = 0; k < entries; k++) {
+unsigned element_loc = prog->UniformStorage[i].remap_location + k;
+a

[Mesa-dev] [PATCH 02/13] glsl: remove dead builtins before assigning varying locations

[Timothy Arceri]

Builtins already have locations assigned so this shouldn't
changing anything. We want to call it earlier so we can tranform
GLSL IR to NIR earlier.
---
 src/compiler/glsl/linker.cpp | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index 02d16ec..2fefccf 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -4587,8 +4587,12 @@ link_varyings_and_uniforms(unsigned first, unsigned last,
 
   /* If the program is made up of only a single stage */
   if (first == last) {
-
  gl_linked_shader *const sh = prog->_LinkedShaders[last];
+
+ do_dead_builtin_varyings(ctx, NULL, sh, 0, NULL);
+ do_dead_builtin_varyings(ctx, sh, NULL, num_tfeedback_decls,
+  tfeedback_decls);
+
  if (prog->SeparateShader) {
 const uint64_t reserved_slots =
reserved_varying_slot(sh, ir_var_shader_in);
@@ -4604,10 +4608,6 @@ link_varyings_and_uniforms(unsigned first, unsigned last,
   reserved_slots))
return false;
  }
-
- do_dead_builtin_varyings(ctx, NULL, sh, 0, NULL);
- do_dead_builtin_varyings(ctx, sh, NULL, num_tfeedback_decls,
-  tfeedback_decls);
   } else {
  /* Linking the stages in the opposite order (from fragment to vertex)
   * ensures that inter-shader outputs written to in an earlier stage
@@ -4627,16 +4627,16 @@ link_varyings_and_uniforms(unsigned first, unsigned 
last,
 const uint64_t reserved_in_slots =
reserved_varying_slot(sh_next, ir_var_shader_in);
 
+do_dead_builtin_varyings(ctx, sh_i, sh_next,
+  next == MESA_SHADER_FRAGMENT ? num_tfeedback_decls : 0,
+  tfeedback_decls);
+
 if (!assign_varying_locations(ctx, mem_ctx, prog, sh_i, sh_next,
   next == MESA_SHADER_FRAGMENT ? num_tfeedback_decls : 0,
   tfeedback_decls,
   reserved_out_slots | reserved_in_slots))
return false;
 
-do_dead_builtin_varyings(ctx, sh_i, sh_next,
-  next == MESA_SHADER_FRAGMENT ? num_tfeedback_decls : 0,
-  tfeedback_decls);
-
 /* This must be done after all dead varyings are eliminated. */
 if (sh_i != NULL) {
unsigned slots_used = _mesa_bitcount_64(reserved_out_slots);
-- 
2.7.4

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[Mesa-dev] [PATCH 09/13] i965: stop passing stage as a function parameter

[Timothy Arceri]

We already pass the shader so we can just get the stage from this.
---
 src/mesa/drivers/dri/i965/brw_link.cpp | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
b/src/mesa/drivers/dri/i965/brw_link.cpp
index 3b85f79..efd67e7 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -86,8 +86,7 @@ brw_lower_packing_builtins(struct brw_context *brw,
 }
 
 static void
-process_glsl_ir(gl_shader_stage stage,
-struct brw_context *brw,
+process_glsl_ir(struct brw_context *brw,
 struct gl_shader_program *shader_prog,
 struct gl_linked_shader *shader)
 {
@@ -138,8 +137,7 @@ process_glsl_ir(gl_shader_stage stage,
do_copy_propagation(shader->ir);
 
bool lowered_variable_indexing =
-  lower_variable_index_to_cond_assign((gl_shader_stage)stage,
-  shader->ir,
+  lower_variable_index_to_cond_assign(shader->Stage, shader->ir,
   options->EmitNoIndirectInput,
   options->EmitNoIndirectOutput,
   options->EmitNoIndirectTemp,
@@ -225,7 +223,7 @@ brw_link_shader(struct gl_context *ctx, struct 
gl_shader_program *shProg)
 
   _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 
-  process_glsl_ir((gl_shader_stage) stage, brw, shProg, shader);
+  process_glsl_ir(brw, shProg, shader);
 
   /* Make a pass over the IR to add state references for any built-in
* uniforms that are used.  This has to be done now (during linking).
-- 
2.7.4

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[Mesa-dev] [PATCH 03/13] glsl: use UniformHash to find storage location

[Timothy Arceri]

There is no need to be looping over all the uniforms.
---
 src/compiler/glsl/link_uniform_initializers.cpp | 29 ++---
 1 file changed, 11 insertions(+), 18 deletions(-)

diff --git a/src/compiler/glsl/link_uniform_initializers.cpp 
b/src/compiler/glsl/link_uniform_initializers.cpp
index 17660a7..3750021 100644
--- a/src/compiler/glsl/link_uniform_initializers.cpp
+++ b/src/compiler/glsl/link_uniform_initializers.cpp
@@ -22,6 +22,7 @@
  */
 
 #include "main/core.h"
+#include "program/hash_table.h"
 #include "ir.h"
 #include "linker.h"
 #include "ir_uniform.h"
@@ -33,14 +34,13 @@
 namespace linker {
 
 gl_uniform_storage *
-get_storage(gl_uniform_storage *storage, unsigned num_storage,
-   const char *name)
+get_storage(struct gl_shader_program *prog, const char *name)
 {
-   for (unsigned int i = 0; i < num_storage; i++) {
-  if (strcmp(name, storage[i].name) == 0)
-return &storage[i];
-   }
+   unsigned id;
+   if (prog->UniformHash->get(id, name))
+  return &prog->UniformStorage[id];
 
+   assert(!"No uniform storage found!");
return NULL;
 }
 
@@ -108,13 +108,10 @@ set_opaque_binding(void *mem_ctx, gl_shader_program *prog,
 element_name, binding);
   }
} else {
-  struct gl_uniform_storage *const storage =
- get_storage(prog->UniformStorage, prog->NumUniformStorage, name);
+  struct gl_uniform_storage *const storage = get_storage(prog, name);
 
-  if (storage == NULL) {
- assert(storage != NULL);
+  if (!storage)
  return;
-  }
 
   const unsigned elements = MAX2(storage->array_elements, 1);
 
@@ -207,14 +204,10 @@ set_uniform_initializer(void *mem_ctx, gl_shader_program 
*prog,
   return;
}
 
-   struct gl_uniform_storage *const storage =
-  get_storage(prog->UniformStorage,
-  prog->NumUniformStorage,
- name);
-   if (storage == NULL) {
-  assert(storage != NULL);
+   struct gl_uniform_storage *const storage = get_storage(prog, name);
+
+   if (!storage)
   return;
-   }
 
if (val->type->is_array()) {
   const enum glsl_base_type base_type =
-- 
2.7.4

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[Mesa-dev] [PATCH 08/13] glsl: move update_uniform_buffer_variables() to lower UBO

[Timothy Arceri]

This make more sense here as its lowering that uses the results of
this function.

This allows us to call lower_ubo_reference() before assigning uniform
locations which is useful for calling backend specific optimisations
on the IR before assigning uniform and varying locations.

While we are at it we also call the other lowering passes before
assigning locations.
---
 src/compiler/glsl/link_uniforms.cpp   | 71 --
 src/compiler/glsl/linker.cpp  | 38 
 src/compiler/glsl/lower_ubo_reference.cpp | 72 +++
 3 files changed, 91 insertions(+), 90 deletions(-)

diff --git a/src/compiler/glsl/link_uniforms.cpp 
b/src/compiler/glsl/link_uniforms.cpp
index 793f12c..bb8905b 100644
--- a/src/compiler/glsl/link_uniforms.cpp
+++ b/src/compiler/glsl/link_uniforms.cpp
@@ -882,75 +882,6 @@ public:
 };
 
 /**
- * Walks the IR and update the references to uniform blocks in the
- * ir_variables to point at linked shader's list (previously, they
- * would point at the uniform block list in one of the pre-linked
- * shaders).
- */
-static void
-link_update_uniform_buffer_variables(struct gl_linked_shader *shader)
-{
-   foreach_in_list(ir_instruction, node, shader->ir) {
-  ir_variable *const var = node->as_variable();
-
-  if ((var == NULL) || !var->is_in_buffer_block())
- continue;
-
-  assert(var->data.mode == ir_var_uniform ||
- var->data.mode == ir_var_shader_storage);
-
-  if (var->is_interface_instance()) {
- var->data.location = 0;
- continue;
-  }
-
-  bool found = false;
-  char sentinel = '\0';
-
-  if (var->type->is_record()) {
- sentinel = '.';
-  } else if (var->type->is_array() && (var->type->fields.array->is_array()
- || var->type->without_array()->is_record())) {
- sentinel = '[';
-  }
-
-  unsigned num_blocks = var->data.mode == ir_var_uniform ?
- shader->NumUniformBlocks : shader->NumShaderStorageBlocks;
-  struct gl_uniform_block **blks = var->data.mode == ir_var_uniform ?
- shader->UniformBlocks : shader->ShaderStorageBlocks;
-
-  const unsigned l = strlen(var->name);
-  for (unsigned i = 0; i < num_blocks; i++) {
- for (unsigned j = 0; j < blks[i]->NumUniforms; j++) {
-if (sentinel) {
-   const char *begin = blks[i]->Uniforms[j].Name;
-   const char *end = strchr(begin, sentinel);
-
-   if (end == NULL)
-  continue;
-
-   if ((ptrdiff_t) l != (end - begin))
-  continue;
-
-   if (strncmp(var->name, begin, l) == 0) {
-  found = true;
-  var->data.location = j;
-  break;
-   }
-} else if (!strcmp(var->name, blks[i]->Uniforms[j].Name)) {
-   found = true;
-   var->data.location = j;
-   break;
-}
- }
- if (found)
-break;
-  }
-  assert(found);
-   }
-}
-
-/**
  * Combine the hidden uniform hash map with the uniform hash map so that the
  * hidden uniforms will be given indicies at the end of the uniform storage
  * array.
@@ -1261,8 +1192,6 @@ link_assign_uniform_locations(struct gl_shader_program 
*prog,
   memset(sh->SamplerUnits, 0, sizeof(sh->SamplerUnits));
   memset(sh->ImageUnits, 0, sizeof(sh->ImageUnits));
 
-  link_update_uniform_buffer_variables(sh);
-
   /* Reset various per-shader target counts.
*/
   uniform_size.start_shader();
diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index ba61d39..a2b1ce2 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -4559,6 +4559,25 @@ link_varyings_and_uniforms(unsigned first, unsigned last,
  return false;
}
 
+   for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
+  struct gl_linked_shader *sh = prog->_LinkedShaders[i];
+  if (sh == NULL)
+ continue;
+
+  const struct gl_shader_compiler_options *options =
+ &ctx->Const.ShaderCompilerOptions[i];
+
+  if (options->LowerBufferInterfaceBlocks)
+ lower_ubo_reference(prog->_LinkedShaders[i],
+ options->ClampBlockIndicesToArrayBounds);
+
+  if (options->LowerShaderSharedVariables)
+ lower_shared_reference(sh, &prog->Comp.SharedSize);
+
+  lower_vector_derefs(sh);
+  do_vec_index_to_swizzle(sh->ir);
+   }
+
/* If there is no fragment shader we need to set transform feedback.
 *
 * For SSO we also need to assign output locations.  We assign them here
@@ -4671,25 +4690,6 @@ link_varyings_and_uniforms(unsigned first, unsigned last,
if (!prog->LinkStatus)
   return false;
 
-   for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
-  if (prog->_LinkedShaders[i] == NULL)
- continue;
-
-  const struct gl_shader_compiler_optio

[Mesa-dev] [PATCH 01/13] glsl: split out varying and uniform linking code

[Timothy Arceri]

Here a new function link_varyings_and_uniforms() is created this
should help make it easier to follow the code in link_shader()
which was getting very large.

Note the end of the new function contains a for loop with some
lowering calls that currently don't seem related to varyings or
uniforms but they are a dependancy for converting to NIR ealier
so we move things here now to keep things easy to follow.
---
 src/compiler/glsl/linker.cpp | 429 ++-
 1 file changed, 222 insertions(+), 207 deletions(-)

diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index 6d45a02..02d16ec 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -4475,6 +4475,226 @@ disable_varying_optimizations_for_sso(struct 
gl_shader_program *prog)
}
 }
 
+static bool
+link_varyings_and_uniforms(unsigned first, unsigned last,
+   unsigned num_explicit_uniform_locs,
+   struct gl_context *ctx,
+   struct gl_shader_program *prog, void *mem_ctx)
+{
+   bool has_xfb_qualifiers = false;
+   unsigned num_tfeedback_decls = 0;
+   char **varying_names = NULL;
+   tfeedback_decl *tfeedback_decls = NULL;
+
+   /* Mark all generic shader inputs and outputs as unpaired. */
+   for (unsigned i = MESA_SHADER_VERTEX; i <= MESA_SHADER_FRAGMENT; i++) {
+  if (prog->_LinkedShaders[i] != NULL) {
+ link_invalidate_variable_locations(prog->_LinkedShaders[i]->ir);
+  }
+   }
+
+   unsigned prev = first;
+   for (unsigned i = prev + 1; i <= MESA_SHADER_FRAGMENT; i++) {
+  if (prog->_LinkedShaders[i] == NULL)
+ continue;
+
+  match_explicit_outputs_to_inputs(prog->_LinkedShaders[prev],
+   prog->_LinkedShaders[i]);
+  prev = i;
+   }
+
+   if (!assign_attribute_or_color_locations(prog, &ctx->Const,
+MESA_SHADER_VERTEX)) {
+  return false;
+   }
+
+   if (!assign_attribute_or_color_locations(prog, &ctx->Const,
+MESA_SHADER_FRAGMENT)) {
+  return false;
+   }
+
+   /* From the ARB_enhanced_layouts spec:
+*
+*"If the shader used to record output variables for transform feedback
+*varyings uses the "xfb_buffer", "xfb_offset", or "xfb_stride" layout
+*qualifiers, the values specified by TransformFeedbackVaryings are
+*ignored, and the set of variables captured for transform feedback is
+*instead derived from the specified layout qualifiers."
+*/
+   for (int i = MESA_SHADER_FRAGMENT - 1; i >= 0; i--) {
+  /* Find last stage before fragment shader */
+  if (prog->_LinkedShaders[i]) {
+ has_xfb_qualifiers =
+process_xfb_layout_qualifiers(mem_ctx, prog->_LinkedShaders[i],
+  &num_tfeedback_decls,
+  &varying_names);
+ break;
+  }
+   }
+
+   if (!has_xfb_qualifiers) {
+  num_tfeedback_decls = prog->TransformFeedback.NumVarying;
+  varying_names = prog->TransformFeedback.VaryingNames;
+   }
+
+   if (num_tfeedback_decls != 0) {
+  /* From GL_EXT_transform_feedback:
+   *   A program will fail to link if:
+   *
+   *   * the  specified by TransformFeedbackVaryingsEXT is
+   * non-zero, but the program object has no vertex or geometry
+   * shader;
+   */
+  if (first >= MESA_SHADER_FRAGMENT) {
+ linker_error(prog, "Transform feedback varyings specified, but "
+  "no vertex, tessellation, or geometry shader is "
+  "present.\n");
+ return false;
+  }
+
+  tfeedback_decls = ralloc_array(mem_ctx, tfeedback_decl,
+ num_tfeedback_decls);
+  if (!parse_tfeedback_decls(ctx, prog, mem_ctx, num_tfeedback_decls,
+ varying_names, tfeedback_decls))
+ return false;
+   }
+
+   /* If there is no fragment shader we need to set transform feedback.
+*
+* For SSO we also need to assign output locations.  We assign them here
+* because we need to do it for both single stage programs and multi stage
+* programs.
+*/
+   if (last < MESA_SHADER_FRAGMENT &&
+   (num_tfeedback_decls != 0 || prog->SeparateShader)) {
+  const uint64_t reserved_out_slots =
+ reserved_varying_slot(prog->_LinkedShaders[last], ir_var_shader_out);
+  if (!assign_varying_locations(ctx, mem_ctx, prog,
+prog->_LinkedShaders[last], NULL,
+num_tfeedback_decls, tfeedback_decls,
+reserved_out_slots))
+ return false;
+   }
+
+   if (last <= MESA_SHADER_FRAGMENT) {
+  /* Remove unused varyings from the first/last stage unless SSO */
+  remove_unused_shader_inputs_and_outputs(prog->Separat

[Mesa-dev] [PATCH 06/13] glsl: move uniform linking code to link_assign_uniform_storage()

[Timothy Arceri]

This makes link_assign_uniform_locations() easier to follow.
---
 src/compiler/glsl/link_uniforms.cpp | 132 +++-
 1 file changed, 69 insertions(+), 63 deletions(-)

diff --git a/src/compiler/glsl/link_uniforms.cpp 
b/src/compiler/glsl/link_uniforms.cpp
index 89196e6..793f12c 100644
--- a/src/compiler/glsl/link_uniforms.cpp
+++ b/src/compiler/glsl/link_uniforms.cpp
@@ -1153,13 +1153,77 @@ link_setup_uniform_remap_tables(struct gl_context *ctx,
}
 }
 
+static void
+link_assign_uniform_storage(struct gl_context *ctx,
+struct gl_shader_program *prog,
+const unsigned num_data_slots,
+unsigned num_explicit_uniform_locs)
+{
+   /* On the outside chance that there were no uniforms, bail out.
+*/
+   if (prog->NumUniformStorage == 0)
+  return;
+
+   unsigned int boolean_true = ctx->Const.UniformBooleanTrue;
+
+   prog->UniformStorage = rzalloc_array(prog, struct gl_uniform_storage,
+prog->NumUniformStorage);
+   union gl_constant_value *data = rzalloc_array(prog->UniformStorage,
+ union gl_constant_value,
+ num_data_slots);
+#ifndef NDEBUG
+   union gl_constant_value *data_end = &data[num_data_slots];
+#endif
+
+   parcel_out_uniform_storage parcel(prog, prog->UniformHash,
+ prog->UniformStorage, data);
+
+   for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
+  if (prog->_LinkedShaders[i] == NULL)
+ continue;
+
+  parcel.start_shader((gl_shader_stage)i);
+
+  foreach_in_list(ir_instruction, node, prog->_LinkedShaders[i]->ir) {
+ ir_variable *const var = node->as_variable();
+
+ if ((var == NULL) || (var->data.mode != ir_var_uniform &&
+   var->data.mode != ir_var_shader_storage))
+continue;
+
+ parcel.set_and_process(var);
+  }
+
+  prog->_LinkedShaders[i]->active_samplers = parcel.shader_samplers_used;
+  prog->_LinkedShaders[i]->shadow_samplers = parcel.shader_shadow_samplers;
+
+  STATIC_ASSERT(sizeof(prog->_LinkedShaders[i]->SamplerTargets) ==
+sizeof(parcel.targets));
+  memcpy(prog->_LinkedShaders[i]->SamplerTargets, parcel.targets,
+ sizeof(prog->_LinkedShaders[i]->SamplerTargets));
+   }
+
+#ifndef NDEBUG
+   for (unsigned i = 0; i < prog->NumUniformStorage; i++) {
+  assert(prog->UniformStorage[i].storage != NULL ||
+ prog->UniformStorage[i].builtin ||
+ prog->UniformStorage[i].is_shader_storage ||
+ prog->UniformStorage[i].block_index != -1);
+   }
+
+   assert(parcel.values == data_end);
+#endif
+
+   link_setup_uniform_remap_tables(ctx, prog, num_explicit_uniform_locs);
+
+   link_set_uniform_initializers(prog, boolean_true);
+}
+
 void
 link_assign_uniform_locations(struct gl_shader_program *prog,
   struct gl_context *ctx,
   unsigned int num_explicit_uniform_locs)
 {
-   unsigned int boolean_true = ctx->Const.UniformBooleanTrue;
-
ralloc_free(prog->UniformStorage);
prog->UniformStorage = NULL;
prog->NumUniformStorage = 0;
@@ -1225,70 +1289,12 @@ link_assign_uniform_locations(struct gl_shader_program 
*prog,
}
 
prog->NumUniformStorage = uniform_size.num_active_uniforms;
-   const unsigned num_data_slots = uniform_size.num_values;
-   const unsigned hidden_uniforms = uniform_size.num_hidden_uniforms;
+   prog->NumHiddenUniforms = uniform_size.num_hidden_uniforms;
 
/* assign hidden uniforms a slot id */
hiddenUniforms->iterate(assign_hidden_uniform_slot_id, &uniform_size);
delete hiddenUniforms;
 
-   /* On the outside chance that there were no uniforms, bail out.
-*/
-   if (prog->NumUniformStorage == 0)
-  return;
-
-   prog->UniformStorage = rzalloc_array(prog, struct gl_uniform_storage,
-prog->NumUniformStorage);
-   union gl_constant_value *data = rzalloc_array(prog->UniformStorage,
- union gl_constant_value,
- num_data_slots);
-#ifndef NDEBUG
-   union gl_constant_value *data_end = &data[num_data_slots];
-#endif
-
-   parcel_out_uniform_storage parcel(prog, prog->UniformHash,
- prog->UniformStorage, data);
-
-   for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
-  if (prog->_LinkedShaders[i] == NULL)
- continue;
-
-  parcel.start_shader((gl_shader_stage)i);
-
-  foreach_in_list(ir_instruction, node, prog->_LinkedShaders[i]->ir) {
- ir_variable *const var = node->as_variable();
-
- if ((var == NULL) || (var->data.mode != ir_var_uniform &&
-   var->data.mode != ir_var_shader_storage))
-co

[Mesa-dev] [PATCH 12/13] glsl/i965: call backend optimisations from glsl linker

[Timothy Arceri]

Here we get the backend to do its extra GLSL IR passes before
assigning varying and uniform locations.

We move the lower_variable_index_to_cond_assign() call to
brw_link_shader() as this must be called after we have done
varying packing to avoid regressions.

Broadwell shader-db results:

total instructions in shared programs: 8651650 -> 8644415 (-0.08%)
instructions in affected programs: 38754 -> 31519 (-18.67%)
helped:320
HURT:  0
---
 src/compiler/glsl/linker.cpp   | 18 ++
 src/mesa/drivers/dri/i965/brw_link.cpp | 32 +---
 2 files changed, 35 insertions(+), 15 deletions(-)

diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index a2b1ce2..c5e75e3 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -4612,6 +4612,10 @@ link_varyings_and_uniforms(unsigned first, unsigned last,
  do_dead_builtin_varyings(ctx, sh, NULL, num_tfeedback_decls,
   tfeedback_decls);
 
+ if (ctx->Driver.ProcessGLSLIR) {
+ctx->Driver.ProcessGLSLIR(ctx, prog, sh);
+ }
+
  if (prog->SeparateShader) {
 const uint64_t reserved_slots =
reserved_varying_slot(sh, ir_var_shader_in);
@@ -4650,6 +4654,10 @@ link_varyings_and_uniforms(unsigned first, unsigned last,
   next == MESA_SHADER_FRAGMENT ? num_tfeedback_decls : 0,
   tfeedback_decls);
 
+if (ctx->Driver.ProcessGLSLIR) {
+   ctx->Driver.ProcessGLSLIR(ctx, prog, sh_next);
+}
+
 if (!assign_varying_locations(ctx, mem_ctx, prog, sh_i, sh_next,
   next == MESA_SHADER_FRAGMENT ? num_tfeedback_decls : 0,
   tfeedback_decls,
@@ -4670,6 +4678,10 @@ link_varyings_and_uniforms(unsigned first, unsigned last,
 
 next = i;
  }
+
+ if (ctx->Driver.ProcessGLSLIR) {
+ctx->Driver.ProcessGLSLIR(ctx, prog, prog->_LinkedShaders[first]);
+ }
   }
}
 
@@ -4677,6 +4689,12 @@ link_varyings_and_uniforms(unsigned first, unsigned last,
  has_xfb_qualifiers))
   return false;
 
+   if (last == MESA_SHADER_COMPUTE) {
+  if (ctx->Driver.ProcessGLSLIR) {
+ ctx->Driver.ProcessGLSLIR(ctx, prog, prog->_LinkedShaders[last]);
+  }
+   }
+
update_array_sizes(prog);
link_assign_uniform_locations(prog, ctx, num_explicit_uniform_locs);
link_assign_atomic_counter_resources(ctx, prog);
diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
b/src/mesa/drivers/dri/i965/brw_link.cpp
index 244c8f0..4c3a508 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -165,19 +165,6 @@ brw_process_glsl_ir(struct gl_context *ctx,
 
do_copy_propagation(shader->ir);
 
-   bool lowered_variable_indexing =
-  lower_variable_index_to_cond_assign(shader->Stage, shader->ir,
-  options->EmitNoIndirectInput,
-  options->EmitNoIndirectOutput,
-  options->EmitNoIndirectTemp,
-  options->EmitNoIndirectUniform);
-
-   if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
-  perf_debug("Unsupported form of variable indexing in %s; falling "
- "back to very inefficient code generation\n",
- _mesa_shader_stage_to_abbrev(shader->Stage));
-   }
-
brw_common_opts(shader, ctx, false, compiler, options);
 
validate_ir_tree(shader->ir);
@@ -231,9 +218,24 @@ brw_link_shader(struct gl_context *ctx, struct 
gl_shader_program *shProg)
 return false;
   prog->Parameters = _mesa_new_parameter_list();
 
-  _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
+  const struct gl_shader_compiler_options *options =
+ &ctx->Const.ShaderCompilerOptions[shader->Stage];
+  bool lowered_variable_indexing =
+ lower_variable_index_to_cond_assign(shader->Stage, shader->ir,
+ options->EmitNoIndirectInput,
+ options->EmitNoIndirectOutput,
+ options->EmitNoIndirectTemp,
+ options->EmitNoIndirectUniform);
+
+  if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
+ perf_debug("Unsupported form of variable indexing in %s; falling "
+"back to very inefficient code generation\n",
+_mesa_shader_stage_to_abbrev(shader->Stage));
+  }
+
+  brw_common_opts(shader, ctx, true, compiler, options);
 
-  brw_process_glsl_ir(ctx, shProg, shader);
+  _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 

[Mesa-dev] Call i965 GLSL IR backend optimisation from the common linker

[Timothy Arceri]

The ultimate goal is to be able to convert to NIR and make use of its
optimisations before assigning varying and uniform locations. This
should allow us to start removing some of the GLSL IR optimisation
passes.

This series falls short of making use of NIR because lower_packed_varyings()
modifies the IR after we assign varying locations. I can see two ways
around this, listing them in increasing difficultly level they would be:

- replacing the current packing pass with one that follows the packing
rules of ARB_enhanced_layouts this would mean we can no longer pack
across slots and matrix and array packing effectivness would be slightly
decreased.
- write a NIR packing pass.

Even without converting to NIR this series solves a number of the other
problems with converting to NIR earlier and provides a nice shader-db
improvement on its own.

Broadwell shader-db results:

total instructions in shared programs: 8651650 -> 8644415 (-0.08%)
instructions in affected programs: 38754 -> 31519 (-18.67%)
total loops in shared programs:2085 -> 2085 (0.00%)
helped:320
HURT:  0
GAINED:0

Ivybridge reported no difference.

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Re: [Mesa-dev] [PATCH 1/5] i965/surface_formats: Don't advertise 8 or 16-bit RGB formats

[Ilia Mirkin]

On Wed, Jul 27, 2016 at 1:04 AM, Jason Ekstrand  wrote:
> We have implicitly been not advertising these formats since we had them
> turned off in the format capabilities table.  We are about to update that
> table and this prevents a change in behavior.  The only change in behavior
> created by this patch is that we no longer advertise support for
> R16G16B16_FLOAT which means that it's now renderable which seems like a
> bonus.  Maybe someday we'll want to change things to start supporting
> 16-bit RGB formats natively but, at the moment, there's no need.
> ---
>  src/mesa/drivers/dri/i965/brw_surface_formats.c | 10 ++
>  1 file changed, 10 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c 
> b/src/mesa/drivers/dri/i965/brw_surface_formats.c
> index 2543f4b..69d3bd4 100644
> --- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
> +++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
> @@ -311,6 +311,16 @@ brw_init_surface_formats(struct brw_context *brw)
>if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32)
>  continue;
>
> +  /* Don't advertisel 8 and 16-bit RGB formats to core mesa.  This 
> ensures

advertise

You might also want to exclude RGB32. It's required for texture
buffers (GL 4.0+), but not for renderable surfaces.

> +   * that they are renderable from an API perspective since core mesa 
> will
> +   * fall back to RGBA or RGBX (we can't render to non-power-of-two
> +   * formats).  For 8-bit, formats, this also keeps us from hitting some
> +   * nasty corners in intel_miptree_map_blit if you ever try to map one.
> +   */
> +  int format_size = _mesa_get_format_bytes(format);
> +  if (format_size == 3 || format_size == 6)
> + continue;
> +
>if (isl_format_supports_sampling(devinfo, texture) &&
>(isl_format_supports_filtering(devinfo, texture) || is_integer))
>  ctx->TextureFormatSupported[format] = true;
> --
> 2.5.0.400.gff86faf
>
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[Mesa-dev] [PATCH 4/5] anv/image: Don't create invalid render target surfaces

[Jason Ekstrand]

---
 src/intel/vulkan/anv_image.c | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index dff51bc..ce08979 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -531,7 +531,18 @@ anv_image_view_init(struct anv_image_view *iview,
   iview->sampler_surface_state.alloc_size = 0;
}
 
-   if (image->usage & usage_mask & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) {
+   /* This is kind-of hackish.  It is possible, due to get_full_usage above,
+* to get a surface state with a non-renderable format but with
+* VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT.  This happens in particular for
+* formats which aren't renderable but where we want to use Vulkan copy
+* commands so VK_IMAGE_USAGE_TRANSFER_DST_BIT is set.  In the case of a
+* copy, meta will use a format that we can render to, but most of the rest
+* of the time, we don't want to create those surface states.  Once we
+* start using blorp for copies, this problem will go away and we can
+* remove a lot of hacks.
+*/
+   if ((image->usage & usage_mask & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
+   isl_format_supports_rendering(&device->info, isl_view.format)) {
   iview->color_rt_surface_state = alloc_surface_state(device, cmd_buffer);
 
   isl_view.usage = cube_usage | ISL_SURF_USAGE_RENDER_TARGET_BIT;
-- 
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[Mesa-dev] [PATCH 5/5] isl/state: Add some asserts about format capabilities

[Jason Ekstrand]

This keeps invalid surface states from leaking through and potentially
hanging the GPU.  We shouldn't actually be hitting this on a regular basis,
but a helpful assert is better than a hang.
---
 src/intel/isl/isl_surface_state.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/intel/isl/isl_surface_state.c 
b/src/intel/isl/isl_surface_state.c
index d1c8f17..a30086d 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -210,6 +210,11 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, 
void *state,
struct GENX(RENDER_SURFACE_STATE) s = { 0 };
 
s.SurfaceType = get_surftype(info->surf->dim, info->view->usage);
+
+   if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
+  assert(isl_format_supports_rendering(dev->info, info->view->format));
+   else if (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT)
+  assert(isl_format_supports_sampling(dev->info, info->view->format));
s.SurfaceFormat = info->view->format;
 
 #if GEN_IS_HASWELL
-- 
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[Mesa-dev] [PATCH 3/5] isl/formats: Update the table with more samplable formats

[Jason Ekstrand]

There were a lot of formats where support was added on Haswell or later but
we never updated the format table.
---
 src/intel/isl/isl_format.c | 30 +++---
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
index 366d32e..73688a7 100644
--- a/src/intel/isl/isl_format.c
+++ b/src/intel/isl/isl_format.c
@@ -218,8 +218,8 @@ static const struct surface_format_info format_info[] = {
SF(50, 50,  x,  x,  x,  x,  x,  x,  x,x,   P8A8_UNORM_PALETTE1)
SF( x,  x,  x,  x,  x,  x,  x,  x,  x,x,   A1B5G5R5_UNORM)
SF(90, 90,  x,  x, 90,  x,  x,  x,  x,x,   A4B4G4R4_UNORM)
-   SF( x,  x,  x,  x,  x,  x,  x,  x,  x,x,   L8A8_UINT)
-   SF( x,  x,  x,  x,  x,  x,  x,  x,  x,x,   L8A8_SINT)
+   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   L8A8_UINT)
+   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   L8A8_SINT)
SF( Y,  Y,  x, 45,  Y,  Y,  Y,  x,  x,x,   R8_UNORM)
SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x,x,   R8_SNORM)
SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x,x,   R8_SINT)
@@ -237,10 +237,10 @@ static const struct surface_format_info format_info[] = {
SF(45, 45,  x,  x,  x,  x,  x,  x,  x,x,   P4A4_UNORM_PALETTE1)
SF(45, 45,  x,  x,  x,  x,  x,  x,  x,x,   A4P4_UNORM_PALETTE1)
SF( x,  x,  x,  x,  x,  x,  x,  x,  x,x,   Y8_UNORM)
-   SF( x,  x,  x,  x,  x,  x,  x,  x,  x,x,   L8_UINT)
-   SF( x,  x,  x,  x,  x,  x,  x,  x,  x,x,   L8_SINT)
-   SF( x,  x,  x,  x,  x,  x,  x,  x,  x,x,   I8_UINT)
-   SF( x,  x,  x,  x,  x,  x,  x,  x,  x,x,   I8_SINT)
+   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   L8_UINT)
+   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   L8_SINT)
+   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   I8_UINT)
+   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   I8_SINT)
SF(45, 45,  x,  x,  x,  x,  x,  x,  x,x,   DXT1_RGB_SRGB)
SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x,x,   R1_UNORM)
SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60,x,   YCRCB_NORMAL)
@@ -261,8 +261,8 @@ static const struct surface_format_info format_info[] = {
SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x,x,   DXT1_RGB)
 /* smpl filt shad CK  RT  AB  VB  SO  color ccs_e */
SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x,x,   FXT1)
-   SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,   R8G8B8_UNORM)
-   SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,   R8G8B8_SNORM)
+   SF(75, 75,  x,  x,  x,  x,  Y,  x,  x,x,   R8G8B8_UNORM)
+   SF(75, 75,  x,  x,  x,  x,  Y,  x,  x,x,   R8G8B8_SNORM)
SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,   R8G8B8_SSCALED)
SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,   R8G8B8_USCALED)
SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,   R64G64B64A64_FLOAT)
@@ -270,8 +270,8 @@ static const struct surface_format_info format_info[] = {
SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x,x,   BC4_SNORM)
SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x,x,   BC5_SNORM)
SF(50, 50,  x,  x,  x,  x, 60,  x,  x,x,   R16G16B16_FLOAT)
-   SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,   R16G16B16_UNORM)
-   SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,   R16G16B16_SNORM)
+   SF(75, 75,  x,  x,  x,  x,  Y,  x,  x,x,   R16G16B16_UNORM)
+   SF(75, 75,  x,  x,  x,  x,  Y,  x,  x,x,   R16G16B16_SNORM)
SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,   R16G16B16_SSCALED)
SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,   R16G16B16_USCALED)
SF(70, 70,  x,  x,  x,  x,  x,  x,  x,x,   BC6H_SF16)
@@ -279,7 +279,7 @@ static const struct surface_format_info format_info[] = {
SF(70, 70,  x,  x,  x,  x,  x,  x,  x,x,   BC7_UNORM_SRGB)
SF(70, 70,  x,  x,  x,  x,  x,  x,  x,x,   BC6H_UF16)
SF( x,  x,  x,  x,  x,  x,  x,  x,  x,x,   PLANAR_420_8)
-   SF( x,  x,  x,  x,  x,  x,  x,  x,  x,x,   R8G8B8_UNORM_SRGB)
+   SF(75, 75,  x,  x,  x,  x,  x,  x,  x,x,   R8G8B8_UNORM_SRGB)
SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ETC1_RGB8)
SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ETC2_RGB8)
SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   EAC_R11)
@@ -287,8 +287,8 @@ static const struct surface_format_info format_info[] = {
SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   EAC_SIGNED_R11)
SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   EAC_SIGNED_RG11)
SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ETC2_SRGB8)
-   SF( x,  x,  x,  x,  x,  x, 75,  x,  x,x,   R16G16B16_UINT)
-   SF( x,  x,  x,  x,  x,  x, 75,  x,  x,x,   R16G16B16_SINT)
+   SF(90, 90,  x,  x,  x,  x, 75,  x,  x,x,   R16G16B16_UINT)
+   SF(90, 90,  x,  x,  x,  x, 75,  x,  x,x,   R16G16B16_SINT)
SF( x,  x,  x,  x,  x,  x, 75,  x,  x,x,   R32_SFIXED)
SF( x,  x,  x,  x,  x,  x, 75,  x,  x,x,   R10G10B10A2_SNORM)
SF( x,  x,  x,  x,  x,  x, 75,  x,  x,x,   R10G10B10A2_USCALED)
@@ -305,8 +305,8 @@ static const struct surface_format_info format_info[] = {
SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,  

[Mesa-dev] [PATCH 0/5] isl: Update the format table and add asserts

[Jason Ekstrand]

The real objective of this series is patch 5 which prevents us from
accidentally creating a surface state with a format unsupported by the
hardware.  This turns some of the new Vulkan CTS tests from a hang into an
informative crash.  In order to get there, however, we needed to update the
format table in isl with some of the new formats added on Haswell and later
generations.  In order to do that, we had to fix up the dri driver, and own
the rabbit hole we go!

At the end of the series, the hangs in the latest CTS are gone (they came
from trying to clear an unsupported image format).

Jason Ekstrand (5):
  i965/surface_formats: Don't advertise 8 or 16-bit RGB formats
  isl/formats: Report ETC as being samplable on Bay Trail
  isl/formats: Update the table with more samplable formats
  anv/image: Don't create invalid render target surfaces
  isl/state: Add some asserts about format capabilities

 src/intel/isl/isl_format.c  | 48 +
 src/intel/isl/isl_surface_state.c   |  5 +++
 src/intel/vulkan/anv_image.c| 13 ++-
 src/mesa/drivers/dri/i965/brw_surface_formats.c | 10 ++
 4 files changed, 60 insertions(+), 16 deletions(-)

-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 2/5] isl/formats: Report ETC as being samplable on Bay Trail

[Jason Ekstrand]

---
 src/intel/isl/isl_format.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
index e0b91bb..366d32e 100644
--- a/src/intel/isl/isl_format.c
+++ b/src/intel/isl/isl_format.c
@@ -372,6 +372,15 @@ isl_format_supports_sampling(const struct brw_device_info 
*devinfo,
if (!format_info[format].exists)
   return false;
 
+   if (devinfo->is_baytrail) {
+  const struct isl_format_layout *fmtl = isl_format_get_layout(format);
+  /* Support for ETC1 and ETC2 exists on Bay Trail even though big-core
+   * GPUs didn't get it until Broadwell.
+   */
+  if (fmtl->txc == ISL_TXC_ETC1 || fmtl->txc == ISL_TXC_ETC2)
+ return true;
+   }
+
return format_gen(devinfo) >= format_info[format].sampling;
 }
 
@@ -382,6 +391,15 @@ isl_format_supports_filtering(const struct brw_device_info 
*devinfo,
if (!format_info[format].exists)
   return false;
 
+   if (devinfo->is_baytrail) {
+  const struct isl_format_layout *fmtl = isl_format_get_layout(format);
+  /* Support for ETC1 and ETC2 exists on Bay Trail even though big-core
+   * GPUs didn't get it until Broadwell.
+   */
+  if (fmtl->txc == ISL_TXC_ETC1 || fmtl->txc == ISL_TXC_ETC2)
+ return true;
+   }
+
return format_gen(devinfo) >= format_info[format].filtering;
 }
 
-- 
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[Mesa-dev] [PATCH 1/5] i965/surface_formats: Don't advertise 8 or 16-bit RGB formats

[Jason Ekstrand]

We have implicitly been not advertising these formats since we had them
turned off in the format capabilities table.  We are about to update that
table and this prevents a change in behavior.  The only change in behavior
created by this patch is that we no longer advertise support for
R16G16B16_FLOAT which means that it's now renderable which seems like a
bonus.  Maybe someday we'll want to change things to start supporting
16-bit RGB formats natively but, at the moment, there's no need.
---
 src/mesa/drivers/dri/i965/brw_surface_formats.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c 
b/src/mesa/drivers/dri/i965/brw_surface_formats.c
index 2543f4b..69d3bd4 100644
--- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
+++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
@@ -311,6 +311,16 @@ brw_init_surface_formats(struct brw_context *brw)
   if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32)
 continue;
 
+  /* Don't advertisel 8 and 16-bit RGB formats to core mesa.  This ensures
+   * that they are renderable from an API perspective since core mesa will
+   * fall back to RGBA or RGBX (we can't render to non-power-of-two
+   * formats).  For 8-bit, formats, this also keeps us from hitting some
+   * nasty corners in intel_miptree_map_blit if you ever try to map one.
+   */
+  int format_size = _mesa_get_format_bytes(format);
+  if (format_size == 3 || format_size == 6)
+ continue;
+
   if (isl_format_supports_sampling(devinfo, texture) &&
   (isl_format_supports_filtering(devinfo, texture) || is_integer))
 ctx->TextureFormatSupported[format] = true;
-- 
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Re: [Mesa-dev] [PATCH v2 11/35] i965/blorp: Use isl_msaa_layout instead of intel_msaa_layout

[Pohjolainen, Topi]

On Tue, Jul 26, 2016 at 03:02:02PM -0700, Jason Ekstrand wrote:
> We also remove brw_blorp_surface_info::msaa_layout.
> ---
>  src/mesa/drivers/dri/i965/brw_blorp.c|  18 -
>  src/mesa/drivers/dri/i965/brw_blorp.h|  14 +---
>  src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 111 
> +--
>  3 files changed, 39 insertions(+), 104 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index d38be8a..96201e4 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -70,7 +70,6 @@ brw_blorp_surface_info_init(struct brw_context *brw,
>&info->x_offset, &info->y_offset);
>  
> info->array_layout = mt->array_layout;
> -   info->msaa_layout = mt->msaa_layout;
> info->swizzle = SWIZZLE_XYZW;
>  
> if (format == MESA_FORMAT_NONE)
> @@ -210,22 +209,6 @@ brw_blorp_compile_nir_shader(struct brw_context *brw, 
> struct nir_shader *nir,
> return program;
>  }
>  
> -static enum isl_msaa_layout
> -get_isl_msaa_layout(enum intel_msaa_layout layout)
> -{
> -   switch (layout) {
> -   case INTEL_MSAA_LAYOUT_NONE:
> -  return ISL_MSAA_LAYOUT_NONE;
> -   case INTEL_MSAA_LAYOUT_IMS:
> -  return ISL_MSAA_LAYOUT_INTERLEAVED;
> -   case INTEL_MSAA_LAYOUT_UMS:
> -   case INTEL_MSAA_LAYOUT_CMS:
> -  return ISL_MSAA_LAYOUT_ARRAY;
> -   default:
> -  unreachable("Invalid MSAA layout");
> -   }
> -}
> -
>  struct surface_state_info {
> unsigned num_dwords;
> unsigned ss_align; /* Required alignment of RENDER_SURFACE_STATE in bytes 
> */
> @@ -255,7 +238,6 @@ brw_blorp_emit_surface_state(struct brw_context *brw,
> /* Stomp surface dimensions and tiling (if needed) with info from blorp */
> surf.dim = ISL_SURF_DIM_2D;
> surf.dim_layout = ISL_DIM_LAYOUT_GEN4_2D;
> -   surf.msaa_layout = get_isl_msaa_layout(surface->msaa_layout);
> surf.logical_level0_px.width = surface->width;
> surf.logical_level0_px.height = surface->height;
> surf.logical_level0_px.depth = 1;
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
> b/src/mesa/drivers/dri/i965/brw_blorp.h
> index 0f142b4..d60b988 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.h
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.h
> @@ -134,12 +134,6 @@ struct brw_blorp_surface_info
> uint32_t brw_surfaceformat;
>  
> /**
> -* For MSAA surfaces, MSAA layout that should be used when setting up the
> -* surface state for this surface.
> -*/
> -   enum intel_msaa_layout msaa_layout;
> -
> -   /**
>  * In order to support cases where RGBA format is backing client requested
>  * RGB, one needs to have means to force alpha channel to one when user
>  * requested RGB surface is used as blit source. This is possible by
> @@ -298,7 +292,7 @@ struct brw_blorp_blit_prog_key
> /* MSAA layout that has been configured in the surface state for texturing
>  * from.
>  */
> -   enum intel_msaa_layout tex_layout;
> +   enum isl_msaa_layout tex_layout;
>  
> enum isl_aux_usage tex_aux_usage;
>  
> @@ -306,7 +300,7 @@ struct brw_blorp_blit_prog_key
> unsigned src_samples;
>  
> /* Actual MSAA layout used by the source image. */
> -   enum intel_msaa_layout src_layout;
> +   enum isl_msaa_layout src_layout;
>  
> /* Number of samples per pixel that have been configured in the render
>  * target.
> @@ -314,13 +308,13 @@ struct brw_blorp_blit_prog_key
> unsigned rt_samples;
>  
> /* MSAA layout that has been configured in the render target. */
> -   enum intel_msaa_layout rt_layout;
> +   enum isl_msaa_layout rt_layout;
>  
> /* Actual number of samples per pixel in the destination image. */
> unsigned dst_samples;
>  
> /* Actual MSAA layout used by the destination image. */
> -   enum intel_msaa_layout dst_layout;
> +   enum isl_msaa_layout dst_layout;
>  
> /* Type of the data to be read from the texture (one of
>  * BRW_REGISTER_TYPE_{UD,D,F}).
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
> b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> index ce00bb7..c337a86 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> @@ -684,23 +684,18 @@ blorp_nir_retile_w_to_y(nir_builder *b, nir_ssa_def 
> *pos)
>   */
>  static inline nir_ssa_def *
>  blorp_nir_encode_msaa(nir_builder *b, nir_ssa_def *pos,
> -  unsigned num_samples, enum intel_msaa_layout layout)
> +  unsigned num_samples, enum isl_msaa_layout layout)
>  {
> assert(pos->num_components == 2 || pos->num_components == 3);
>  
> switch (layout) {
> -   case INTEL_MSAA_LAYOUT_NONE:
> +   case ISL_MSAA_LAYOUT_NONE:
>assert(pos->num_components == 2);
>return pos;
> -   case INTEL_MSAA_LAYOUT_CMS:
> -  /* We can't compensate for compressed layout since at this point in the
> -   * program we 

Re: [Mesa-dev] [PATCH v2 08/35] i965/blorp: Make sample count asserts a bit more lazy

[Pohjolainen, Topi]

We could have a small rational here:

Until now blorp used internally the sample count of zero to represent
single sampled surfaces. However, incoming single sampled surfaces may
have the sample count set as zero or one, and once the stomping to
zero is dropped these asserts would fire.

On Tue, Jul 26, 2016 at 03:01:59PM -0700, Jason Ekstrand wrote:
> Reviewed-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 10 +-
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
> b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> index a68e406..e0a6d7c 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> @@ -1302,7 +1302,7 @@ brw_blorp_build_nir_shader(struct brw_context *brw,
> nir_ssa_def *src_pos, *dst_pos, *color;
>  
> /* Sanity checks */
> -   if (key->dst_tiled_w && key->rt_samples > 0) {
> +   if (key->dst_tiled_w && key->rt_samples > 1) {
>/* If the destination image is W tiled and multisampled, then the 
> thread
> * must be dispatched once per sample, not once per pixel.  This is
> * necessary because after conversion between W and Y tiling, there's 
> no
> @@ -1333,13 +1333,13 @@ brw_blorp_build_nir_shader(struct brw_context *brw,
>  
> /* Make sure layout is consistent with sample count */
> assert((key->tex_layout == INTEL_MSAA_LAYOUT_NONE) ==
> -  (key->tex_samples == 0));
> +  (key->tex_samples <= 1));
> assert((key->rt_layout == INTEL_MSAA_LAYOUT_NONE) ==
> -  (key->rt_samples == 0));
> +  (key->rt_samples <= 1));
> assert((key->src_layout == INTEL_MSAA_LAYOUT_NONE) ==
> -  (key->src_samples == 0));
> +  (key->src_samples <= 1));
> assert((key->dst_layout == INTEL_MSAA_LAYOUT_NONE) ==
> -  (key->dst_samples == 0));
> +  (key->dst_samples <= 1));
>  
> nir_builder b;
> nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
> -- 
> 2.5.0.400.gff86faf
> 
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[Mesa-dev] [Bug 96950] Another regression from bc4e0c486: vbo: Use a bitmask to track the active arrays in vbo_exec*.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=96950

--- Comment #9 from Mathias Fröhlich  ---
I have verified 0ad with the provided trace here, updated as requested and
pushed.
Thanks for testing and review on your side.

I assume the originator verifies and closes the bug?

Mathias

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Re: [Mesa-dev] Interest in GL_ARB_gl_spirv support?

[Matt Turner]

On Tue, Jul 26, 2016 at 9:16 PM, Jason Ekstrand  wrote:
> On Tue, Jul 26, 2016 at 4:50 PM, Ilia Mirkin  wrote:
>>
>> On Tue, Jul 26, 2016 at 7:44 PM, Marek Olšák  wrote:
>> > On Wed, Jul 27, 2016 at 12:29 AM, oscar bg  wrote:
>> >> Hi,
>> >> seems this year 2016 OpenGL ARB update brings a small number of
>> >> extensions..
>> >> seems the most important is GL_ARB_gl_spirv.. seems like SPIRV as a
>> >> binary
>> >> format for OpenGL and Mesa doesn't have any binary format even
>> >> supporting
>> >> ARB_program_binary ext.. a Nvidia driver is already providing support
>> >> from
>> >> day 1 for Linux as always..
>> >>
>> >> just asking how difficult would be to bring support to Mesa drivers..
>> >> and if
>> >> there is any interest by Mesa devs start working on it soon..
>> >>
>> >> seems already we have SPIRV support in Mesa in Vulkan drivers: Anvil
>> >> Vulkan
>> >> Intel driver and some days ago RADV a open source Vulkan driver for AMD
>> >> GPUs
>> >> has been anounced.. as this drivers already eat SPIRV code seems this
>> >> extension would take less work to port to this two vendor GPUs?
>
>
> We're thinking about it but, unfortunately, I haven't had much time to look
> into the extension.  One thing that I can say right now, is that the
> spirv_to_nir pass isn't what you'd call OpenGL-friendly.  If you pass it
> invalid SPIR-V, it will crash.  What little error checking it does do is
> done via asserts.  That's perfectly acceptable in the Vulkan world but
> unless they went out of their way to ok it in the extension, crashing
> generally isn't acceptable in OpenGL.  Also, it's not entirely clear what
> all hoops we would have to go through to tie a NIR shader into the OpenGL
> state upload paths for things like uniforms, inputs/outputs, etc.  This
> isn't to say that it can't be done but it's substantially more than zero
> work.

The spec says

The OpenGL API expects the SPIR-V module to have already been validated,
and can return an error if it discovers anything invalid in
the module.  An invalid SPIR-V module is allowed to result in undefined
behavior.
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Re: [Mesa-dev] Interest in GL_ARB_gl_spirv support?

[Jason Ekstrand]

On Tue, Jul 26, 2016 at 4:50 PM, Ilia Mirkin  wrote:

> On Tue, Jul 26, 2016 at 7:44 PM, Marek Olšák  wrote:
> > On Wed, Jul 27, 2016 at 12:29 AM, oscar bg  wrote:
> >> Hi,
> >> seems this year 2016 OpenGL ARB update brings a small number of
> extensions..
> >> seems the most important is GL_ARB_gl_spirv.. seems like SPIRV as a
> binary
> >> format for OpenGL and Mesa doesn't have any binary format even
> supporting
> >> ARB_program_binary ext.. a Nvidia driver is already providing support
> from
> >> day 1 for Linux as always..
> >>
> >> just asking how difficult would be to bring support to Mesa drivers..
> and if
> >> there is any interest by Mesa devs start working on it soon..
> >>
> >> seems already we have SPIRV support in Mesa in Vulkan drivers: Anvil
> Vulkan
> >> Intel driver and some days ago RADV a open source Vulkan driver for AMD
> GPUs
> >> has been anounced.. as this drivers already eat SPIRV code seems this
> >> extension would take less work to port to this two vendor GPUs?
>

We're thinking about it but, unfortunately, I haven't had much time to look
into the extension.  One thing that I can say right now, is that the
spirv_to_nir pass isn't what you'd call OpenGL-friendly.  If you pass it
invalid SPIR-V, it will crash.  What little error checking it does do is
done via asserts.  That's perfectly acceptable in the Vulkan world but
unless they went out of their way to ok it in the extension, crashing
generally isn't acceptable in OpenGL.  Also, it's not entirely clear what
all hoops we would have to go through to tie a NIR shader into the OpenGL
state upload paths for things like uniforms, inputs/outputs, etc.  This
isn't to say that it can't be done but it's substantially more than zero
work.


> > The showstopper for sharing Vulkan code is that OpenGL doesn't have
> > pipeline state objects. Because of that, you can ignore RADV. I think
> > nobody has enough resources to replicate what the radeonsi TGSI path
> > does, so you are pretty much stuck with TGSI.
> >
> > SPIRV -> NIR -> TGSI should work.
>

Eric's NIR -> TGSI pass is a bit rusty at this point, but it wouldn't be
hard to revive it.


> FWIW my plans for nouveau definitely involve direct SPIR-V input. This
> will also be useful for an independent Vulkan driver, as well as
> OpenCL SPIR-V. However I'm not sure when such plans will materialize.
>

I've just got to say it.  You're crazy...

--Jason
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Re: [Mesa-dev] [PATCH] anv/pipeline: Enable only one dispatch width in case of per sample shading

[Jason Ekstrand]

On Jul 26, 2016 12:54 PM, "Anuj Phogat"  wrote:
>
> Fixes ~45 DEQP sample shading tests:
> ./deqp-vk --deqp-case=dEQP-VK.pipeline.multisample.min_sample_shading*
>
> Many tests exited with VK_ERROR_OUT_OF_DEVICE_MEMORY without this patch.
>
> Cc: Jason Ekstrand 
> Signed-off-by: Anuj Phogat 
>
> ---
> Another patch enabling the sample shading is required to test this patch.
> I'll send out the enabling patch once we pass all the sample shading
tests.
> Use https://github.com/aphogat/mesa, branch: review to test the patch.
> ---
>  src/intel/vulkan/gen7_pipeline.c |  9 -
>  src/intel/vulkan/gen8_pipeline.c | 12 
>  2 files changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/src/intel/vulkan/gen7_pipeline.c
b/src/intel/vulkan/gen7_pipeline.c
> index 8ce50be..23535f5 100644
> --- a/src/intel/vulkan/gen7_pipeline.c
> +++ b/src/intel/vulkan/gen7_pipeline.c
> @@ -249,6 +249,8 @@ genX(graphics_pipeline_create)(
>   anv_finishme("primitive_id needs sbe swizzling setup");
>
>emit_3dstate_sbe(pipeline);
> +  bool per_sample_ps = pCreateInfo->pMultisampleState &&
> +
 pCreateInfo->pMultisampleState->sampleShadingEnable;
>
>anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) {
>   ps.KernelStartPointer0   = pipeline->ps_ksp0;
> @@ -274,7 +276,12 @@ genX(graphics_pipeline_create)(
>
>   ps._32PixelDispatchEnable= false;
>   ps._16PixelDispatchEnable= wm_prog_data->dispatch_16;
> - ps._8PixelDispatchEnable = wm_prog_data->dispatch_8;
> + /* On all hardware generations, the only configurations
supporting
> +  * persample dispatch are in which only one dispatch width is
enabled.
> +  */
> + ps._8PixelDispatchEnable = wm_prog_data->dispatch_8 &&
> +(!per_sample_ps ||
> + !wm_prog_data->dispatch_16);

I don't think we need to do this.  brw_compile_fs in brw_fs.cpp should
handle this for us based on the shader key.  We should be able to just set
the shader key bits correctly and then trust brw_compile_fs to give us only
one dispatch width.

--Jason

>
>   ps.DispatchGRFStartRegisterforConstantSetupData0 =
>  wm_prog_data->base.dispatch_grf_start_reg,
> diff --git a/src/intel/vulkan/gen8_pipeline.c
b/src/intel/vulkan/gen8_pipeline.c
> index cc10d3a..bde7660 100644
> --- a/src/intel/vulkan/gen8_pipeline.c
> +++ b/src/intel/vulkan/gen8_pipeline.c
> @@ -333,12 +333,19 @@ genX(graphics_pipeline_create)(
>}
> } else {
>emit_3dstate_sbe(pipeline);
> +  bool per_sample_ps = pCreateInfo->pMultisampleState &&
> +
 pCreateInfo->pMultisampleState->sampleShadingEnable;
>
>anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) {
>   ps.KernelStartPointer0 = pipeline->ps_ksp0;
>   ps.KernelStartPointer1 = 0;
>   ps.KernelStartPointer2 = pipeline->ps_ksp0 +
wm_prog_data->prog_offset_2;
> - ps._8PixelDispatchEnable   = wm_prog_data->dispatch_8;
> + /* On all hardware generations, the only configurations
supporting
> +  * persample dispatch are in which only one dispatch width is
enabled.
> +  */
> + ps._8PixelDispatchEnable   = wm_prog_data->dispatch_8 &&
> +  (!per_sample_ps ||
> +   !wm_prog_data->dispatch_16);
>   ps._16PixelDispatchEnable  = wm_prog_data->dispatch_16;
>   ps._32PixelDispatchEnable  = false;
>   ps.SingleProgramFlow   = false;
> @@ -365,9 +372,6 @@ genX(graphics_pipeline_create)(
>  wm_prog_data->dispatch_grf_start_reg_2;
>}
>
> -  bool per_sample_ps = pCreateInfo->pMultisampleState &&
> -
 pCreateInfo->pMultisampleState->sampleShadingEnable;
> -
>anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA), ps) {
>   ps.PixelShaderValid  = true;
>   ps.PixelShaderKillsPixel = wm_prog_data->uses_kill;
> --
> 2.5.5
>
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Re: [Mesa-dev] [PATCH v2 26/27] i965/blorp: brw_blorp_blit.cpp -> blorp_blit.c

[Jason Ekstrand]

On Jul 26, 2016 6:49 PM, "Matt Turner"  wrote:
>
> On Tue, Jul 26, 2016 at 3:11 PM, Jason Ekstrand 
wrote:
> > ---
> >  src/mesa/drivers/dri/i965/Makefile.sources   |2 +-
> >  src/mesa/drivers/dri/i965/blorp_blit.c   | 1662
++
> >  src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 1662
--
> >  3 files changed, 1663 insertions(+), 1663 deletions(-)
> >  create mode 100644 src/mesa/drivers/dri/i965/blorp_blit.c
> >  delete mode 100644 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
>
> Same comment about the other rename patches: what's the point of
> dropping the "brw_"?

Eventually, these are going to move to src/intel/blorp.  When they do, the
blorp prefix will be sufficient.  At the moment, it makes it clear that
they're is little to nothing brw about them (hence the distinction between
brw_blorp.c and blorp.c in patch 25) and avoids the annoying dependency
issues of renaming a fine from .c to .cpp.

--Jason
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Re: [Mesa-dev] [PATCH v2 26/27] i965/blorp: brw_blorp_blit.cpp -> blorp_blit.c

[Matt Turner]

On Tue, Jul 26, 2016 at 3:11 PM, Jason Ekstrand  wrote:
> ---
>  src/mesa/drivers/dri/i965/Makefile.sources   |2 +-
>  src/mesa/drivers/dri/i965/blorp_blit.c   | 1662 
> ++
>  src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 1662 
> --
>  3 files changed, 1663 insertions(+), 1663 deletions(-)
>  create mode 100644 src/mesa/drivers/dri/i965/blorp_blit.c
>  delete mode 100644 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp

Same comment about the other rename patches: what's the point of
dropping the "brw_"?
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Re: [Mesa-dev] [PATCH] st_glsl_to_tgsi: only skip over slots of an input array that are present

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Mon, Jul 25, 2016 at 6:08 PM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> When an application declares varying arrays but does not actually do any
> indirect indexing, some array indices may end up unused in the consuming
> shader, so the number of input slots that correspond to the array ends
> up less than the array_size.
>
> Cc: mesa-sta...@lists.freedesktop.org
> ---
> See also the shader_runner Piglit test that I sent out a moment ago.
>
>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 6 +-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> index 7564119..38e2c4a 100644
> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> @@ -6058,7 +6058,11 @@ st_translate_program(
>inputSemanticName[i], inputSemanticIndex[i],
>interpMode[i], 0, interpLocation[i],
>array_id, array_size);
> -i += array_size - 1;
> +
> +GLuint base_attr = inputSlotToAttr[i];
> +while (i + 1 < numInputs &&
> +   inputSlotToAttr[i + 1] < base_attr + array_size)
> +   ++i;
>   }
>   else {
>  t->inputs[i] = ureg_DECL_fs_input_cyl_centroid(ureg,
> --
> 2.7.4
>
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[Mesa-dev] [PATCH] glsl: free hash tables earlier

[Timothy Arceri]

These are only used by get_matching_input() which has been call
at this point so free the hash tables.
---
 src/compiler/glsl/link_varyings.cpp | 10 +++---
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/src/compiler/glsl/link_varyings.cpp 
b/src/compiler/glsl/link_varyings.cpp
index d48c680..91d8974 100644
--- a/src/compiler/glsl/link_varyings.cpp
+++ b/src/compiler/glsl/link_varyings.cpp
@@ -2156,6 +2156,9 @@ assign_varying_locations(struct gl_context *ctx,
   }
}
 
+   hash_table_dtor(consumer_inputs);
+   hash_table_dtor(consumer_interface_inputs);
+
for (unsigned i = 0; i < num_tfeedback_decls; ++i) {
   if (!tfeedback_decls[i].is_varying())
  continue;
@@ -2165,8 +2168,6 @@ assign_varying_locations(struct gl_context *ctx,
 
   if (matched_candidate == NULL) {
  hash_table_dtor(tfeedback_candidates);
- hash_table_dtor(consumer_inputs);
- hash_table_dtor(consumer_interface_inputs);
  return false;
   }
 
@@ -2185,15 +2186,10 @@ assign_varying_locations(struct gl_context *ctx,
 
   if (!tfeedback_decls[i].assign_location(ctx, prog)) {
  hash_table_dtor(tfeedback_candidates);
- hash_table_dtor(consumer_inputs);
- hash_table_dtor(consumer_interface_inputs);
  return false;
   }
}
-
hash_table_dtor(tfeedback_candidates);
-   hash_table_dtor(consumer_inputs);
-   hash_table_dtor(consumer_interface_inputs);
 
if (consumer && producer) {
   foreach_in_list(ir_instruction, node, consumer->ir) {
-- 
2.7.4

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Re: [Mesa-dev] Interest in GL_ARB_gl_spirv support?

[Ilia Mirkin]

On Tue, Jul 26, 2016 at 7:44 PM, Marek Olšák  wrote:
> On Wed, Jul 27, 2016 at 12:29 AM, oscar bg  wrote:
>> Hi,
>> seems this year 2016 OpenGL ARB update brings a small number of extensions..
>> seems the most important is GL_ARB_gl_spirv.. seems like SPIRV as a binary
>> format for OpenGL and Mesa doesn't have any binary format even supporting
>> ARB_program_binary ext.. a Nvidia driver is already providing support from
>> day 1 for Linux as always..
>>
>> just asking how difficult would be to bring support to Mesa drivers.. and if
>> there is any interest by Mesa devs start working on it soon..
>>
>> seems already we have SPIRV support in Mesa in Vulkan drivers: Anvil Vulkan
>> Intel driver and some days ago RADV a open source Vulkan driver for AMD GPUs
>> has been anounced.. as this drivers already eat SPIRV code seems this
>> extension would take less work to port to this two vendor GPUs?
>
> The showstopper for sharing Vulkan code is that OpenGL doesn't have
> pipeline state objects. Because of that, you can ignore RADV. I think
> nobody has enough resources to replicate what the radeonsi TGSI path
> does, so you are pretty much stuck with TGSI.
>
> SPIRV -> NIR -> TGSI should work.

FWIW my plans for nouveau definitely involve direct SPIR-V input. This
will also be useful for an independent Vulkan driver, as well as
OpenCL SPIR-V. However I'm not sure when such plans will materialize.

  -ilia
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Re: [Mesa-dev] Mesa (master): Revert "radeon/llvm: Use alloca instructions for larger arrays"

[Matt Arsenault]

> On Jul 26, 2016, at 14:37, Marek Olšák  wrote:
> 
> On Sat, Jul 23, 2016 at 4:07 PM, Nicolai Hähnle  > wrote:
>> On 22.07.2016 12:08, Michel Dänzer wrote:
>>> 
>>> On 21.07.2016 18:17, Matt Arsenault wrote:
> 
> On Jul 21, 2016, at 01:03, Michel Dänzer  > wrote:
> 
> On 21.07.2016 00:04, Michel Dänzer wrote:
>> 
>> On 15.07.2016 05:15, Marek =?UNKNOWN?B?T2zFocOhaw==?= wrote:
>>> 
>>> Module: Mesa
>>> Branch: master
>>> Commit: f84e9d749fbb6da73a60fb70e6725db773c9b8f8
>>> URL:
>>> 
>>> http://cgit.freedesktop.org/mesa/mesa/commit/?id=f84e9d749fbb6da73a60fb70e6725db773c9b8f8
>>> 
>>> Author: Marek Olšák mailto:marek.ol...@amd.com>>
>>> Date:   Thu Jul 14 22:07:46 2016 +0200
>>> 
>>> Revert "radeon/llvm: Use alloca instructions for larger arrays"
>>> 
>>> This reverts commit 513fccdfb68e6a71180e21827f071617c93fd09b.
>>> 
>>> Bioshock Infinite hangs with that.
>> 
>> 
>> Unfortunately, this change caused the piglit test
>> shaders@glsl-fs-vec4-indexing-temp-dst-in-loop (and possibly others) to
>> hang my Kaveri. Any ideas for how we can get out of this conundrum?
> 
> 
> The hang was introduced by LLVM SVN r275934 ("AMDGPU: Expand register
> indexing pseudos in custom inserter"). The good/bad (without/with
> r275934) shader dumps and the GALLIUM_DDEBUG=800 dump corresponding to
> the hang are attached.
> 
> 
> BTW, even with Marek's change above reverted, I still see some piglit
> regressions compared to last week, but I'm not sure if those are all
> related to the same LLVM change.
> 
> 
> --
> Earthling Michel Dänzer   |
>  http://www.amd.com 
> Libre software enthusiast | Mesa and X developer
> 
> 
 
 
 This fixes the verifier error in it: https://reviews.llvm.org/D22616
>>> 
>>> 
>>> This seems to fix the hang, thanks!
>>> 
>>> 
 This fixes another issue which may be
 related: https://reviews.llvm.org/D22556
>>> 
>>> 
>>> Even with that applied as well, there are still piglit regressions
>>> compared to early last week, see the attached dumps (look for "LLVM
>>> triggered Diagnostic Handler:").
>> 
>> 
>> Looks like the "rewrite undef" part of the Two Address Instruction Pass also
>> needs to be adjusted -- I've attached a bugpoint-reduced test case.
>> 
>> Also, the hang that motivated the original revert in Mesa should be fixed
>> with https://reviews.llvm.org/D22673 (and the related
>> https://reviews.llvm.org/D22675 is also needed for correctness, though
>> probably not for fixing the hang).
> 
> FYI, I've reverted the revert.
> 
> Marek


It might be nice if this could be an option, since this was probably the main 
stressor of the register indexing code

-Matt

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Re: [Mesa-dev] Interest in GL_ARB_gl_spirv support?

[Marek Olšák]

On Wed, Jul 27, 2016 at 12:29 AM, oscar bg  wrote:
> Hi,
> seems this year 2016 OpenGL ARB update brings a small number of extensions..
> seems the most important is GL_ARB_gl_spirv.. seems like SPIRV as a binary
> format for OpenGL and Mesa doesn't have any binary format even supporting
> ARB_program_binary ext.. a Nvidia driver is already providing support from
> day 1 for Linux as always..
>
> just asking how difficult would be to bring support to Mesa drivers.. and if
> there is any interest by Mesa devs start working on it soon..
>
> seems already we have SPIRV support in Mesa in Vulkan drivers: Anvil Vulkan
> Intel driver and some days ago RADV a open source Vulkan driver for AMD GPUs
> has been anounced.. as this drivers already eat SPIRV code seems this
> extension would take less work to port to this two vendor GPUs?

The showstopper for sharing Vulkan code is that OpenGL doesn't have
pipeline state objects. Because of that, you can ignore RADV. I think
nobody has enough resources to replicate what the radeonsi TGSI path
does, so you are pretty much stuck with TGSI.

SPIRV -> NIR -> TGSI should work.

Marek
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Re: [Mesa-dev] [PATCH 1/3] nvc0: fix up TCP header on GM107+

[Ilia Mirkin]

On Tue, Jul 26, 2016 at 6:53 PM, Samuel Pitoiset
 wrote:
> The number of outputs patch (limited to 255) has moved in the TCP
> header, but blob seems to also set the old position. Also, the high
> 8-bits are now located inbetween the min/max parallel output read
> address at position 20.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 9 +
>  1 file changed, 9 insertions(+)
>
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c 
> b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
> index 5fc2753..8ed3e10 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
> @@ -346,6 +346,15 @@ nvc0_tcp_gen_header(struct nvc0_program *tcp, struct 
> nv50_ir_prog_info *info)
>
> nvc0_vtgp_gen_header(tcp, info);
>
> +   if (info->target >= NVISA_GM107_CHIPSET) {
> +  /* On GM107+, the number of output patch components has moved in the 
> TCP
> +   * header, but it seems like blob still also uses the old position.
> +   * Also, the high 8-bits are located inbetween the min/max parallel
> +   * field and has to be set after updating the outputs. */
> +  tcp->hdr[3] = opcs << 28;

Semantically identical, but I think it'll help out the poor casual reader:

tcp->hdr[3] = (opcs & 0x0f) << 28;

Otherwise this is

Acked-by: Ilia Mirkin 

[to reflect the fact that I've done absolutely no verification of your
claims about how the hw works]

> +  tcp->hdr[4] |= (opcs & 0xf0) << 16;
> +   }
> +
> nvc0_tp_get_tess_mode(tcp, info);
>
> return 0;
> --
> 2.9.0
>
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Re: [Mesa-dev] [PATCH 2/3] gm107/ir: add a legalize SSA pass for PFETCH

[Ilia Mirkin]

On Tue, Jul 26, 2016 at 6:53 PM, Samuel Pitoiset
 wrote:
> PFETCH, actually ISBERD on GM107+ ISA only accepts a GPR for src0.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  .../nouveau/codegen/nv50_ir_lowering_gm107.cpp | 33 
> ++
>  .../nouveau/codegen/nv50_ir_lowering_gm107.h   | 11 
>  .../nouveau/codegen/nv50_ir_target_gm107.cpp   |  2 +-
>  3 files changed, 45 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
> index a5deaef..84ef4e0 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
> @@ -41,6 +41,39 @@ namespace nv50_ir {
> ((QOP_##q << 6) | (QOP_##r << 4) |   \
>  (QOP_##s << 2) | (QOP_##t << 0))
>
> +void
> +GM107LegalizeSSA::handlePFETCH(Instruction *i)
> +{
> +   Value *src0;
> +
> +   if (i->src(0).getFile() == FILE_GPR && !i->srcExists(1))
> +  return;
> +
> +   bld.setPosition(i, false);
> +   src0 = bld.getSSA();
> +
> +   if (i->srcExists(1))
> +  bld.mkOp2(OP_ADD , TYPE_U32, src0, i->getSrc(0), i->getSrc(1));
> +   else
> +  bld.mkOp1(OP_MOV , TYPE_U32, src0, i->getSrc(0));
> +
> +   i->setSrc(0, src0);
> +   i->setSrc(1, NULL);
> +}
> +
> +bool
> +GM107LegalizeSSA::visit(Instruction *i)
> +{
> +   switch (i->op) {
> +   case OP_PFETCH:
> +  handlePFETCH(i);
> +  break;
> +   default:
> +  break;
> +   }
> +   return true;

This should probably be

return NVC0LegalizeSSA::visit(i);

I'm a bit surprised that this passed without that... do we really not
do anything useful in there?

> +}
> +
>  bool
>  GM107LoweringPass::handleManualTXD(TexInstruction *i)
>  {
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h
> index 036abf0..d8e326f 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h
> @@ -15,4 +15,15 @@ private:
> bool handlePOPCNT(Instruction *);
>  };
>
> +class GM107LegalizeSSA : public NVC0LegalizeSSA
> +{
> +private:
> +   virtual bool visit(Instruction *);
> +
> +   void handlePFETCH(Instruction *);
> +
> +private:
> +   BuildUtil bld;

Make the other one protected instead...

> +};
> +
>  } // namespace nv50_ir
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
> index 92caeb2..6b8f767 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
> @@ -80,7 +80,7 @@ TargetGM107::runLegalizePass(Program *prog, CGStage stage) 
> const
>return pass.run(prog, false, true);
> } else
> if (stage == CG_STAGE_SSA) {
> -  NVC0LegalizeSSA pass;
> +  GM107LegalizeSSA pass;
>return pass.run(prog, false, true);
> }
> return false;
> --
> 2.9.0
>
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Re: [Mesa-dev] Mesa (master): gallium/radeon: degrade tiled textures mapped often to linear

[Marek Olšák]

On Tue, Jun 7, 2016 at 11:02 AM, Marek Olšák  wrote:
> On Tue, Jun 7, 2016 at 9:14 AM, Michel Dänzer  wrote:
>> On 02.06.2016 21:20, Michel Dänzer wrote:
>>> On 02.06.2016 00:35, Marek =?UNKNOWN?B?T2zFocOhaw==?= wrote:
 Module: Mesa
 Branch: master
 Commit: fc1479a95432f291623fa5bafe524701e77af3ca
 URL:
 http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc1479a95432f291623fa5bafe524701e77af3ca

 Author: Marek Olšák 
 Date:   Thu May 12 13:33:06 2016 +0200

 gallium/radeon: degrade tiled textures mapped often to linear

 Reviewed-by: Nicolai Hähnle 
 Reviewed-by: Bas Nieuwenhuizen 
>>>
>>> This commit broke the piglit test spec@!opengl 1.2@tex3d-maxsize on my
>>> Kaveri (radeon driver, 1GB VRAM, 2GB GTT). It prints lots of lines
>>>
>>>  radeon: Not enough memory for command submission.
>>>
>>> to stderr, with corresponding lines
>>>
>>>  [drm:radeon_cs_ioctl [radeon]] *ERROR* Failed to parse relocation -12!
>>>
>>> in dmesg.
>>
>> Marek, any ideas for this regression? Do you need more information about it?
>
> Sorry, I have yet to test it. Tonga & Fiji (amdgpu) aren't affected.

I think the problem is that textures are added to the buffer list and
then the draw call checks memory usage and flushes accordingly. The
problem is the textures are not removed from the buffer list at that
point.

Example:
- Limit: 2 GB GTT
- Draw call 1: 1 GB GTT usage
- Draw call 2: +1.5 GB GTT usage
- Flushes the IB without draw call 2 but with 2.5GB GTT usage.

Marek
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[Mesa-dev] [PATCH 0/3] nvc0: add support for tessellation on Maxwell+

[Samuel Pitoiset]

Hi,

This series adds support for GL_ARB_tessellation_shader on GM107+ *and*
exposes GL 4.1! :)

This has been tested on GM107 and GM206 (this also enables tess on Pascal,
but I can't test, hopefully it will not break the universe)

Actually, it seems like we can re-use most of the existing code and so the
number of changed lines is relatively small.

All piglit tests pass except
spec/arb_tessellation_shader/execution/tes-input/tes-input-gl_clipdistance
which also fails on previous generations, and has to be fixed at some point.

Heaven looks fine as well.

Please review,
Thanks!

Samuel Pitoiset (3):
  nvc0: fix up TCP header on GM107+
  gm107/ir: add a legalize SSA pass for PFETCH
  nvc0: enable ARB_tessellation_shader on GM107+

 .../nouveau/codegen/nv50_ir_lowering_gm107.cpp | 33 ++
 .../nouveau/codegen/nv50_ir_lowering_gm107.h   | 11 
 .../nouveau/codegen/nv50_ir_target_gm107.cpp   |  2 +-
 src/gallium/drivers/nouveau/nvc0/nvc0_program.c|  9 ++
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c |  3 --
 5 files changed, 54 insertions(+), 4 deletions(-)

-- 
2.9.0

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[Mesa-dev] [PATCH 3/3] nvc0: enable ARB_tessellation_shader on GM107+

[Samuel Pitoiset]

This exposes OpenGL 4.1 on Maxwell (tested on GM107 and GM206).

Signed-off-by: Samuel Pitoiset 
---
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 6d924c3..fb0a9c8 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -308,11 +308,8 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, 
unsigned shader,
case PIPE_SHADER_GEOMETRY:
case PIPE_SHADER_FRAGMENT:
case PIPE_SHADER_COMPUTE:
-  break;
case PIPE_SHADER_TESS_CTRL:
case PIPE_SHADER_TESS_EVAL:
-  if (class_3d >= GM107_3D_CLASS)
- return 0;
   break;
default:
   return 0;
-- 
2.9.0

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[Mesa-dev] [PATCH 1/3] nvc0: fix up TCP header on GM107+

[Samuel Pitoiset]

The number of outputs patch (limited to 255) has moved in the TCP
header, but blob seems to also set the old position. Also, the high
8-bits are now located inbetween the min/max parallel output read
address at position 20.

Signed-off-by: Samuel Pitoiset 
---
 src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index 5fc2753..8ed3e10 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -346,6 +346,15 @@ nvc0_tcp_gen_header(struct nvc0_program *tcp, struct 
nv50_ir_prog_info *info)
 
nvc0_vtgp_gen_header(tcp, info);
 
+   if (info->target >= NVISA_GM107_CHIPSET) {
+  /* On GM107+, the number of output patch components has moved in the TCP
+   * header, but it seems like blob still also uses the old position.
+   * Also, the high 8-bits are located inbetween the min/max parallel
+   * field and has to be set after updating the outputs. */
+  tcp->hdr[3] = opcs << 28;
+  tcp->hdr[4] |= (opcs & 0xf0) << 16;
+   }
+
nvc0_tp_get_tess_mode(tcp, info);
 
return 0;
-- 
2.9.0

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[Mesa-dev] [PATCH 2/3] gm107/ir: add a legalize SSA pass for PFETCH

[Samuel Pitoiset]

PFETCH, actually ISBERD on GM107+ ISA only accepts a GPR for src0.

Signed-off-by: Samuel Pitoiset 
---
 .../nouveau/codegen/nv50_ir_lowering_gm107.cpp | 33 ++
 .../nouveau/codegen/nv50_ir_lowering_gm107.h   | 11 
 .../nouveau/codegen/nv50_ir_target_gm107.cpp   |  2 +-
 3 files changed, 45 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
index a5deaef..84ef4e0 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
@@ -41,6 +41,39 @@ namespace nv50_ir {
((QOP_##q << 6) | (QOP_##r << 4) |   \
 (QOP_##s << 2) | (QOP_##t << 0))
 
+void
+GM107LegalizeSSA::handlePFETCH(Instruction *i)
+{
+   Value *src0;
+
+   if (i->src(0).getFile() == FILE_GPR && !i->srcExists(1))
+  return;
+
+   bld.setPosition(i, false);
+   src0 = bld.getSSA();
+
+   if (i->srcExists(1))
+  bld.mkOp2(OP_ADD , TYPE_U32, src0, i->getSrc(0), i->getSrc(1));
+   else
+  bld.mkOp1(OP_MOV , TYPE_U32, src0, i->getSrc(0));
+
+   i->setSrc(0, src0);
+   i->setSrc(1, NULL);
+}
+
+bool
+GM107LegalizeSSA::visit(Instruction *i)
+{
+   switch (i->op) {
+   case OP_PFETCH:
+  handlePFETCH(i);
+  break;
+   default:
+  break;
+   }
+   return true;
+}
+
 bool
 GM107LoweringPass::handleManualTXD(TexInstruction *i)
 {
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h
index 036abf0..d8e326f 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h
@@ -15,4 +15,15 @@ private:
bool handlePOPCNT(Instruction *);
 };
 
+class GM107LegalizeSSA : public NVC0LegalizeSSA
+{
+private:
+   virtual bool visit(Instruction *);
+
+   void handlePFETCH(Instruction *);
+
+private:
+   BuildUtil bld;
+};
+
 } // namespace nv50_ir
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
index 92caeb2..6b8f767 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
@@ -80,7 +80,7 @@ TargetGM107::runLegalizePass(Program *prog, CGStage stage) 
const
   return pass.run(prog, false, true);
} else
if (stage == CG_STAGE_SSA) {
-  NVC0LegalizeSSA pass;
+  GM107LegalizeSSA pass;
   return pass.run(prog, false, true);
}
return false;
-- 
2.9.0

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Re: [Mesa-dev] [RFC] i965: Delete brw_do_channel_expressions().

[Kenneth Graunke]

I re-ran these numbers with my SSO patches for shader-db and my
move_interpolation_to_top() pass fixed.  They're pretty similar:

(didn't run Haswell)

On Broadwell:

total instructions in shared programs: 11632138 -> 11641224 (0.08%)
instructions in affected programs: 1525250 -> 1534336 (0.60%)
helped: 1775
HURT: 5621

total cycles in shared programs: 144771824 -> 144924416 (0.11%)
cycles in affected programs: 115845654 -> 115998246 (0.13%)
helped: 20545
HURT: 36635

total loops in shared programs: 3345 -> 3345 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total spills in shared programs: 2924 -> 3129 (7.01%)
spills in affected programs: 1002 -> 1207 (20.46%)
helped: 0
HURT: 7

total fills in shared programs: 4394 -> 4563 (3.85%)
fills in affected programs: 851 -> 1020 (19.86%)
helped: 0
HURT: 7

LOST:   18
GAINED: 31

On Skylake:

total instructions in shared programs: 11947696 -> 11956226 (0.07%)
instructions in affected programs: 1549219 -> 1557749 (0.55%)
helped: 1757
HURT: 5579

total cycles in shared programs: 134233408 -> 134336690 (0.08%)
cycles in affected programs: 105950250 -> 106053532 (0.10%)
helped: 20278
HURT: 36719

total loops in shared programs: 3209 -> 3209 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total spills in shared programs: 3805 -> 3898 (2.44%)
spills in affected programs: 705 -> 798 (13.19%)
helped: 2
HURT: 61

total fills in shared programs: 5318 -> 5409 (1.71%)
fills in affected programs: 659 -> 750 (13.81%)
helped: 2
HURT: 61

LOST:   30
GAINED: 15


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[Mesa-dev] [PATCH shader-db v2 2/2] run: Mark shaders with only one stage as separable.

[Kenneth Graunke]

There are a couple cases where a single shader might happen:

- compute shaders
  (only one stage, no inputs and outputs; separable shouldn't matter)
- vertex shaders with transform feedback
  (we want to retain outputs, but transform feedback varyings are
   specified via the API, not the shader - setting SSO fixes this)
- old shader_test files captured before we started adding "SSO ENABLED".

In any case, it seems harmless or beneficial to enable SSO for all
.shader_test files containing a single shader.

Based on a patch by Marek.

v2: Ignore VP/FP shaders.
---
 run.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/run.c b/run.c
index 2fed284..e8bc2c1 100644
--- a/run.c
+++ b/run.c
@@ -633,10 +633,15 @@ main(int argc, char **argv)
 }
 ctx_is_core = type == TYPE_CORE;
 
+/* If there's only one GLSL shader, mark it separable so
+ * inputs and outputs aren't eliminated.
+ */
+if (num_shaders == 1 && type != TYPE_VP && type != TYPE_FP)
+use_separate_shader_objects = true;
+
 if (use_separate_shader_objects) {
 for (unsigned i = 0; i < num_shaders; i++) {
-GLuint prog = glCreateShaderProgramv(shader[i].type, 1,
- &shader[i].text);
+glCreateShaderProgramv(shader[i].type, 1, &shader[i].text);
 }
 } else if (type == TYPE_CORE || type == TYPE_COMPAT) {
 GLuint prog = glCreateProgram();
-- 
2.9.0

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[Mesa-dev] [PATCH shader-db v2 1/2] run: Add separate shader objects support.

[Kenneth Graunke]

With this patch, if a .shader_test file contains

[require]
...
SSO ENABLED

then we'll use glCreateShaderProgramv to create each shader, so that
they're compiled as separate shader objects.  This prevents the linker
from removing unused inputs and outputs.  Drivers may also choose to lay
out interfaces of SSO programs differently, resulting in different code.

v2:
- Actually initialize use_separate_shader_objects
- Fix memcmp length parameter (thanks to Matt)

v3:
- Search for "SSO ENABLED" instead of "GL_ARB_separate_shader_objects",
  to match what Timothy did in shader_runner.
- Use GL_PROGRAM_SEPARABLE (suggested by Tapani).  This allows
  multi-stage SSO programs to optimize internal interfaces, while
  still making the end-stages separable.

v4:
- Go back to glCreateShaderProgramv.  Timothy pointed out that Piglit's
  shader_runner compiles each shader separately, and wouldn't optimize
  interfaces between programs.  I want to preserve the same semantics
  between both .shader_test file processors.  Today, it looks like
  multi-stage SSO programs are pretty uncommon (typically every stage
  is separable), so we'll punt on solving that until later.
---
 run.c | 16 +++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/run.c b/run.c
index 0e6e248..2fed284 100644
--- a/run.c
+++ b/run.c
@@ -73,12 +73,14 @@ static struct shader *
 get_shaders(const struct context_info *core, const struct context_info *compat,
 const char *text, size_t text_size,
 enum shader_type *type, unsigned *num_shaders,
+bool *use_separate_shader_objects,
 const char *shader_name)
 {
 static const char *req = "[require]";
 static const char *glsl_req = "\nGLSL >= ";
 static const char *fp_req = "\nGL_ARB_fragment_program";
 static const char *vp_req = "\nGL_ARB_vertex_program";
+static const char *sso_req = "SSO ENABLED";
 static const char *gs = "geometry shader]\n";
 static const char *fs = "fragment ";
 static const char *vs = "vertex ";
@@ -90,6 +92,8 @@ get_shaders(const struct context_info *core, const struct 
context_info *compat,
 static const char *test = "test]\n";
 const char *end_text = text + text_size;
 
+*use_separate_shader_objects = false;
+
 /* Find the [require] block and parse it first. */
 text = memmem(text, end_text - text, req, strlen(req)) + strlen(req);
 
@@ -137,6 +141,9 @@ get_shaders(const struct context_info *core, const struct 
context_info *compat,
 shader_name, (int)(newline - extension_text), 
extension_text);
 return NULL;
 }
+if (memcmp(extension_text, sso_req, strlen(sso_req)) == 0) {
+*use_separate_shader_objects = true;
+}
 }
 
 /* Find the shaders. */
@@ -606,9 +613,11 @@ main(int argc, char **argv)
 
 enum shader_type type;
 unsigned num_shaders;
+bool use_separate_shader_objects;
 struct shader *shader = get_shaders(&core, &compat,
 text, shader_test[i].filesize,
 &type, &num_shaders,
+&use_separate_shader_objects,
 current_shader_name);
 if (unlikely(shader == NULL)) {
 continue;
@@ -624,7 +633,12 @@ main(int argc, char **argv)
 }
 ctx_is_core = type == TYPE_CORE;
 
-if (type == TYPE_CORE || type == TYPE_COMPAT) {
+if (use_separate_shader_objects) {
+for (unsigned i = 0; i < num_shaders; i++) {
+GLuint prog = glCreateShaderProgramv(shader[i].type, 1,
+ &shader[i].text);
+}
+} else if (type == TYPE_CORE || type == TYPE_COMPAT) {
 GLuint prog = glCreateProgram();
 
 for (unsigned i = 0; i < num_shaders; i++) {
-- 
2.9.0

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[Mesa-dev] Interest in GL_ARB_gl_spirv support?

[oscar bg]

Hi,
seems this year 2016 OpenGL ARB update brings a small number of extensions..
seems the most important is GL_ARB_gl_spirv.. seems like SPIRV as a binary
format for OpenGL and Mesa doesn't have any binary format even supporting
ARB_program_binary ext.. a Nvidia driver is already providing support from
day 1 for Linux as always..

just asking how difficult would be to bring support to Mesa drivers.. and
if there is any interest by Mesa devs start working on it soon..

seems already we have SPIRV support in Mesa in Vulkan drivers: Anvil Vulkan
Intel driver and some days ago RADV a open source Vulkan driver for AMD
GPUs has been anounced.. as this drivers already eat SPIRV code seems this
extension would take less work to port to this two vendor GPUs?

would like to hear feedback,
thanks..
Oscar.
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[Mesa-dev] [PATCH v2 01/35] isl: Fix the parameter names for get_intratile_offset

[Jason Ekstrand]

It's been in elements for a while but, for whatever reason, the parameter
names in the header file never got updated.
---
 src/intel/isl/isl.h | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 19673f8..d0bac5d 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1353,11 +1353,11 @@ isl_tiling_get_intratile_offset_el(const struct 
isl_device *dev,
enum isl_tiling tiling,
uint8_t bs,
uint32_t row_pitch,
-   uint32_t total_x_offset_B,
-   uint32_t total_y_offset_rows,
+   uint32_t total_x_offset_el,
+   uint32_t total_y_offset_el,
uint32_t *base_address_offset,
-   uint32_t *x_offset_B,
-   uint32_t *y_offset_rows);
+   uint32_t *x_offset_el,
+   uint32_t *y_offset_el);
 
 /**
  * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 14/35] i965/blorp: Move intratile offset calculations out of surface state setup

[Jason Ekstrand]

Previously we multiplied full x/y offsets, resolved tile aligned buffer
offset and intra tile offset based on that.  Now we let ISL to take into
account the msaa setting and we only multiply the resolved intra tile
offsets.

Reviewed-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.c| 24 
 src/mesa/drivers/dri/i965/brw_blorp.h| 15 ++-
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp |  8 
 3 files changed, 18 insertions(+), 29 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 48755fc..8f7690c 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -66,9 +66,6 @@ brw_blorp_surface_info_init(struct brw_context *brw,
info->width = minify(mt->physical_width0, level - mt->first_level);
info->height = minify(mt->physical_height0, level - mt->first_level);
 
-   intel_miptree_get_image_offset(mt, level, layer,
-  &info->x_offset, &info->y_offset);
-
info->swizzle = SWIZZLE_XYZW;
 
if (format == MESA_FORMAT_NONE)
@@ -110,6 +107,15 @@ brw_blorp_surface_info_init(struct brw_context *brw,
   break;
}
}
+
+   uint32_t x_offset, y_offset;
+   intel_miptree_get_image_offset(mt, level, layer, &x_offset, &y_offset);
+
+   uint8_t bs = isl_format_get_layout(info->brw_surfaceformat)->bpb / 8;
+   isl_tiling_get_intratile_offset_el(&brw->isl_dev, info->surf.tiling, bs,
+  info->surf.row_pitch, x_offset, y_offset,
+  &info->bo_offset,
+  &info->tile_x_sa, &info->tile_y_sa);
 }
 
 
@@ -296,13 +302,6 @@ brw_blorp_emit_surface_state(struct brw_context *brw,
   ISL_SURF_USAGE_TEXTURE_BIT,
};
 
-   uint32_t offset, tile_x, tile_y;
-   isl_tiling_get_intratile_offset_el(&brw->isl_dev, surf.tiling,
-  isl_format_get_layout(view.format)->bpb 
/ 8,
-  surf.row_pitch,
-  surface->x_offset, surface->y_offset,
-  &offset, &tile_x, &tile_y);
-
uint32_t surf_offset;
uint32_t *dw = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
   ss_info.num_dwords * 4, ss_info.ss_align,
@@ -311,11 +310,12 @@ brw_blorp_emit_surface_state(struct brw_context *brw,
const uint32_t mocs = is_render_target ? ss_info.rb_mocs : ss_info.tex_mocs;
 
isl_surf_fill_state(&brw->isl_dev, dw, .surf = &surf, .view = &view,
-   .address = surface->mt->bo->offset64 + offset,
+   .address = surface->mt->bo->offset64 + 
surface->bo_offset,
.aux_surf = aux_surf, .aux_usage = surface->aux_usage,
.aux_address = aux_offset,
.mocs = mocs, .clear_color = clear_color,
-   .x_offset_sa = tile_x, .y_offset_sa = tile_y);
+   .x_offset_sa = surface->tile_x_sa,
+   .y_offset_sa = surface->tile_y_sa);
 
/* Emit relocation to surface contents */
drm_intel_bo_emit_reloc(brw->batch.bo,
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 7aa67be..e591f41 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -104,19 +104,8 @@ struct brw_blorp_surface_info
 */
uint32_t height;
 
-   /**
-* X offset within the surface to texture from (or render to).  For
-* surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
-* pixels.
-*/
-   uint32_t x_offset;
-
-   /**
-* Y offset within the surface to texture from (or render to).  For
-* surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
-* pixels.
-*/
-   uint32_t y_offset;
+   uint32_t bo_offset;
+   uint32_t tile_x_sa, tile_y_sa;
 
/**
 * Format that should be used when setting up the surface state for this
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 03e4984..fc0aada 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1899,8 +1899,8 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
   params.y1 = ALIGN(params.y1, y_align) / 2;
   params.dst.width = ALIGN(params.dst.width, x_align) * 2;
   params.dst.height = ALIGN(params.dst.height, y_align) / 2;
-  params.dst.x_offset *= 2;
-  params.dst.y_offset /= 2;
+  params.dst.tile_x_sa *= 2;
+  params.dst.tile_y_sa /= 2;
   wm_prog_key.use_kill = true;
}
 
@@ -1924,8 +1924,8 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
   const unsigned x_align = 8, y_align = params.src.surf.samples != 0 ? 8 : 
4;
   params.src.width = ALIGN(p

[Mesa-dev] [PATCH v2 07/35] i965/blorp: Get rid of brw_blorp_surface_info::map_stencil_as_y_tiled

[Jason Ekstrand]

Now that we're carrying around the isl_surf, we can just modify it
directly instead of passing an extra bit around.

Reviewed-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.c| 12 ++---
 src/mesa/drivers/dri/i965/brw_blorp.h| 15 ---
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 38 ++--
 3 files changed, 26 insertions(+), 39 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 220be83..7a4b94b 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -71,7 +71,6 @@ brw_blorp_surface_info_init(struct brw_context *brw,
 
info->num_samples = mt->num_samples;
info->array_layout = mt->array_layout;
-   info->map_stencil_as_y_tiled = false;
info->msaa_layout = mt->msaa_layout;
info->swizzle = SWIZZLE_XYZW;
 
@@ -80,11 +79,8 @@ brw_blorp_surface_info_init(struct brw_context *brw,
 
switch (format) {
case MESA_FORMAT_S_UINT8:
-  /* The miptree is a W-tiled stencil buffer.  Surface states can't be set
-   * up for W tiling, so we'll need to use Y tiling and have the WM
-   * program swizzle the coordinates.
-   */
-  info->map_stencil_as_y_tiled = true;
+  assert(info->surf.tiling == ISL_TILING_W);
+  /* Prior to Broadwell, we can't render to R8_UINT */
   info->brw_surfaceformat = brw->gen >= 8 ? BRW_SURFACEFORMAT_R8_UINT :
 BRW_SURFACEFORMAT_R8_UNORM;
   break;
@@ -290,10 +286,6 @@ brw_blorp_emit_surface_state(struct brw_context *brw,
   surf.image_alignment_el = isl_extent3d(4, 2, 1);
}
 
-   /* We need to fake W-tiling with Y-tiling */
-   if (surface->map_stencil_as_y_tiled)
-  surf.tiling = ISL_TILING_Y0;
-
union isl_color_value clear_color = { .u32 = { 0, 0, 0, 0 } };
 
const struct isl_surf *aux_surf = NULL;
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 0694181..010b760 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -118,21 +118,6 @@ struct brw_blorp_surface_info
 */
uint32_t y_offset;
 
-   /* Setting this flag indicates that the buffer's contents are W-tiled
-* stencil data, but the surface state should be set up for Y tiled
-* MESA_FORMAT_R_UNORM8 data (this is necessary because surface states don't
-* support W tiling).
-*
-* Since W tiles are 64 pixels wide by 64 pixels high, whereas Y tiles of
-* MESA_FORMAT_R_UNORM8 data are 128 pixels wide by 32 pixels high, the 
width and
-* pitch stored in the surface state will be multiplied by 2, and the
-* height will be halved.  Also, since W and Y tiles store their data in a
-* different order, the width and height will be rounded up to a multiple
-* of the tile size, to ensure that the WM program can access the full
-* width and height of the buffer.
-*/
-   bool map_stencil_as_y_tiled;
-
unsigned num_samples;
 
/**
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index a54680e..a68e406 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1737,16 +1737,6 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
  params.dst.num_samples = 0;
}
 
-   if (params.dst.map_stencil_as_y_tiled && params.dst.num_samples > 1) {
-  /* If the destination surface is a W-tiled multisampled stencil buffer
-   * that we're mapping as Y tiled, then we need to arrange for the WM
-   * program to run once per sample rather than once per pixel, because
-   * the memory layout of related samples doesn't match between W and Y
-   * tiling.
-   */
-  wm_prog_key.persample_msaa_dispatch = true;
-   }
-
if (params.src.num_samples > 0 && params.dst.num_samples > 1) {
   /* We are blitting from a multisample buffer to a multisample buffer, so
* we must preserve samples within a pixel.  This means we have to
@@ -1830,8 +1820,6 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS)
   wm_prog_key.dst_layout = INTEL_MSAA_LAYOUT_NONE;
 
-   wm_prog_key.src_tiled_w = params.src.map_stencil_as_y_tiled;
-   wm_prog_key.dst_tiled_w = params.dst.map_stencil_as_y_tiled;
/* Round floating point values to nearest integer to avoid "off by one 
texel"
 * kind of errors when blitting.
 */
@@ -1905,7 +1893,22 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
   wm_prog_key.use_kill = true;
}
 
-   if (params.dst.map_stencil_as_y_tiled) {
+   if (params.dst.surf.tiling == ISL_TILING_W) {
+  /* We need to fake W-tiling with Y-tiling */
+  params.dst.surf.tiling = ISL_TILING_Y0;
+
+  wm_prog_key.dst_tiled_w = true;
+
+  if (params.dst.num_samples > 1) {
+ /* If the destination surface is

[Mesa-dev] [PATCH v2 23/35] isl: Take the slice0_extent shortcut for interleaved MSAA

[Jason Ekstrand]

The shortcut works just fine for MSAA and the comment even says so.

Reviewed-by: Nanley Chery 
---
 src/intel/isl/isl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index a9208f6..500eb2d 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -623,7 +623,7 @@ isl_calc_phys_slice0_extent_sa_gen4_2d(
 
assert(phys_level0_sa->depth == 1);
 
-   if (info->levels == 1 && msaa_layout != ISL_MSAA_LAYOUT_INTERLEAVED) {
+   if (info->levels == 1) {
   /* Do not pad the surface to the image alignment. Instead, pad it only
* to the pixel format's block alignment.
*
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 21/35] i965/blorp: Use the isl_view from the blorp_surface_info

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_blorp.c | 18 +-
 1 file changed, 1 insertion(+), 17 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 78707ca..d9b5554 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -386,22 +386,6 @@ brw_blorp_emit_surface_state(struct brw_context *brw,
   clear_color = intel_miptree_get_isl_clear_color(brw, surface->mt);
}
 
-   struct isl_view view = {
-  .format = surface->view.format,
-  .base_level = 0,
-  .levels = 1,
-  .base_array_layer = 0,
-  .array_len = 1,
-  .channel_select = {
- ISL_CHANNEL_SELECT_RED,
- ISL_CHANNEL_SELECT_GREEN,
- ISL_CHANNEL_SELECT_BLUE,
- ISL_CHANNEL_SELECT_ALPHA,
-  },
-  .usage = is_render_target ? ISL_SURF_USAGE_RENDER_TARGET_BIT :
-  ISL_SURF_USAGE_TEXTURE_BIT,
-   };
-
uint32_t surf_offset;
uint32_t *dw = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
   ss_info.num_dwords * 4, ss_info.ss_align,
@@ -409,7 +393,7 @@ brw_blorp_emit_surface_state(struct brw_context *brw,
 
const uint32_t mocs = is_render_target ? ss_info.rb_mocs : ss_info.tex_mocs;
 
-   isl_surf_fill_state(&brw->isl_dev, dw, .surf = &surf, .view = &view,
+   isl_surf_fill_state(&brw->isl_dev, dw, .surf = &surf, .view = 
&surface->view,
.address = surface->mt->bo->offset64 + 
surface->bo_offset,
.aux_surf = aux_surf, .aux_usage = surface->aux_usage,
.aux_address = aux_offset,
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 08/35] i965/blorp: Make sample count asserts a bit more lazy

[Jason Ekstrand]

Reviewed-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index a68e406..e0a6d7c 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1302,7 +1302,7 @@ brw_blorp_build_nir_shader(struct brw_context *brw,
nir_ssa_def *src_pos, *dst_pos, *color;
 
/* Sanity checks */
-   if (key->dst_tiled_w && key->rt_samples > 0) {
+   if (key->dst_tiled_w && key->rt_samples > 1) {
   /* If the destination image is W tiled and multisampled, then the thread
* must be dispatched once per sample, not once per pixel.  This is
* necessary because after conversion between W and Y tiling, there's no
@@ -1333,13 +1333,13 @@ brw_blorp_build_nir_shader(struct brw_context *brw,
 
/* Make sure layout is consistent with sample count */
assert((key->tex_layout == INTEL_MSAA_LAYOUT_NONE) ==
-  (key->tex_samples == 0));
+  (key->tex_samples <= 1));
assert((key->rt_layout == INTEL_MSAA_LAYOUT_NONE) ==
-  (key->rt_samples == 0));
+  (key->rt_samples <= 1));
assert((key->src_layout == INTEL_MSAA_LAYOUT_NONE) ==
-  (key->src_samples == 0));
+  (key->src_samples <= 1));
assert((key->dst_layout == INTEL_MSAA_LAYOUT_NONE) ==
-  (key->dst_samples == 0));
+  (key->dst_samples <= 1));
 
nir_builder b;
nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 25/35] i965/blorp: Map 1-D render targets with DIM_LAYOUT_GEN4_2D as 2D on gen9

[Jason Ekstrand]

The sampling hardware can handle them ok.  It just looks at the tiling to
determine whether it's the new gen9 1-D layout or the old one.  The render
hardware isn't so smart.
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index d9b5554..2cf0f99 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -371,6 +371,12 @@ brw_blorp_emit_surface_state(struct brw_context *brw,
 
struct isl_surf surf = surface->surf;
 
+   if (surf.dim == ISL_SURF_DIM_1D &&
+   surf.dim_layout == ISL_DIM_LAYOUT_GEN4_2D) {
+  assert(surf.logical_level0_px.height == 1);
+  surf.dim = ISL_SURF_DIM_2D;
+   }
+
union isl_color_value clear_color = { .u32 = { 0, 0, 0, 0 } };
 
const struct isl_surf *aux_surf = NULL;
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 17/35] isl: Add functions for computing surface offsets in samples

[Jason Ekstrand]

---
 src/intel/isl/isl.c | 24 
 src/intel/isl/isl.h | 48 
 2 files changed, 60 insertions(+), 12 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index a713eeb..f65f9c8 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1475,13 +1475,13 @@ get_image_offset_sa_gen9_1d(const struct isl_surf *surf,
  * @invariant logical_array_layer < logical array length of surface
  * @invariant logical_z_offset_px < logical depth of surface at level
  */
-static void
-get_image_offset_sa(const struct isl_surf *surf,
-uint32_t level,
-uint32_t logical_array_layer,
-uint32_t logical_z_offset_px,
-uint32_t *x_offset_sa,
-uint32_t *y_offset_sa)
+void
+isl_surf_get_image_offset_sa(const struct isl_surf *surf,
+ uint32_t level,
+ uint32_t logical_array_layer,
+ uint32_t logical_z_offset_px,
+ uint32_t *x_offset_sa,
+ uint32_t *y_offset_sa)
 {
assert(level < surf->levels);
assert(logical_array_layer < surf->logical_level0_px.array_len);
@@ -1524,11 +1524,11 @@ isl_surf_get_image_offset_el(const struct isl_surf 
*surf,
   < isl_minify(surf->logical_level0_px.depth, level));
 
uint32_t x_offset_sa, y_offset_sa;
-   get_image_offset_sa(surf, level,
-   logical_array_layer,
-   logical_z_offset_px,
-   &x_offset_sa,
-   &y_offset_sa);
+   isl_surf_get_image_offset_sa(surf, level,
+logical_array_layer,
+logical_z_offset_px,
+&x_offset_sa,
+&y_offset_sa);
 
*x_offset_el = x_offset_sa / fmtl->bw;
*y_offset_el = y_offset_sa / fmtl->bh;
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index d0bac5d..68ad8a4 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1323,6 +1323,22 @@ isl_surf_get_array_pitch(const struct isl_surf *surf)
 }
 
 /**
+ * Calculate the offset, in units of surface samples, to a subimage in the
+ * surface.
+ *
+ * @invariant level < surface levels
+ * @invariant logical_array_layer < logical array length of surface
+ * @invariant logical_z_offset_px < logical depth of surface at level
+ */
+void
+isl_surf_get_image_offset_sa(const struct isl_surf *surf,
+ uint32_t level,
+ uint32_t logical_array_layer,
+ uint32_t logical_z_offset_px,
+ uint32_t *x_offset_sa,
+ uint32_t *y_offset_sa);
+
+/**
  * Calculate the offset, in units of surface elements, to a subimage in the
  * surface.
  *
@@ -1359,6 +1375,38 @@ isl_tiling_get_intratile_offset_el(const struct 
isl_device *dev,
uint32_t *x_offset_el,
uint32_t *y_offset_el);
 
+static inline void
+isl_tiling_get_intratile_offset_sa(const struct isl_device *dev,
+   enum isl_tiling tiling,
+   enum isl_format format,
+   uint32_t row_pitch,
+   uint32_t total_x_offset_sa,
+   uint32_t total_y_offset_sa,
+   uint32_t *base_address_offset,
+   uint32_t *x_offset_sa,
+   uint32_t *y_offset_sa)
+{
+   const struct isl_format_layout *fmtl = isl_format_get_layout(format);
+
+   assert(fmtl->bpb % 8 == 0);
+
+   /* For computing the intratile offsets, we actually want a strange unit
+* which is samples for multisampled surfaces but elements for compressed
+* surfaces.
+*/
+   assert(total_x_offset_sa % fmtl->bw == 0);
+   assert(total_y_offset_sa % fmtl->bw == 0);
+   const uint32_t total_x_offset = total_x_offset_sa / fmtl->bw;
+   const uint32_t total_y_offset = total_y_offset_sa / fmtl->bh;
+
+   isl_tiling_get_intratile_offset_el(dev, tiling, fmtl->bpb / 8, row_pitch,
+  total_x_offset, total_y_offset,
+  base_address_offset,
+  x_offset_sa, y_offset_sa);
+   *x_offset_sa *= fmtl->bw;
+   *y_offset_sa *= fmtl->bh;
+}
+
 /**
  * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
  *
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 28/35] i965/blorp: Add a z_offset field to blorp_surface_info

[Jason Ekstrand]

The layer field is in terms of physical layers which isn't quite what the
sampler will want for 2-D MS array textures.
---
 src/mesa/drivers/dri/i965/brw_blorp.c|  9 +
 src/mesa/drivers/dri/i965/brw_blorp.h|  3 +++
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 11 ++-
 3 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index bc26e41..64e507a 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -201,6 +201,15 @@ brw_blorp_surface_info_init(struct brw_context *brw,
   },
};
 
+   if (brw->gen >= 8 && !is_render_target && info->surf.dim == 
ISL_SURF_DIM_3D) {
+  /* On gen8+ we use actual 3-D textures so we need to pass the layer
+   * through to the sampler.
+   */
+  info->z_offset = layer / layer_multiplier;
+   } else {
+  info->z_offset = 0;
+   }
+
info->level = level;
info->layer = layer;
 
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 282235d..ec12dfe 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -78,6 +78,9 @@ struct brw_blorp_surface_info
 
struct isl_view view;
 
+   /* Z offset into a 3-D texture or slice of a 2-D array texture. */
+   uint32_t z_offset;
+
/**
 * The miplevel to use.
 */
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index a76d130..a35cdb3 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1779,15 +1779,8 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
brw_blorp_setup_coord_transform(¶ms.wm_inputs.coord_transform[1],
src_y0, src_y1, dst_y0, dst_y1, mirror_y);
 
-   if (brw->gen >= 8 && params.src.mt->target == GL_TEXTURE_3D) {
-  /* On gen8+ we use actual 3-D textures so we need to pass the layer
-   * through to the sampler.
-   */
-  params.wm_inputs.src_z = params.src.layer;
-   } else {
-  /* On gen7 and earlier, we fake everything with 2-D textures */
-  params.wm_inputs.src_z = 0;
-   }
+   /* For some texture types, we need to pass the layer through the sampler. */
+   params.wm_inputs.src_z = params.src.z_offset;
 
if (brw->gen > 6 && dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
   /* We must expand the rectangle we send through the rendering pipeline,
-- 
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Re: [Mesa-dev] [PATCH] glsl: fix optimization of discard nested multiple levels

[Kenneth Graunke]

On Tuesday, July 26, 2016 10:14:12 AM PDT Nicolai Hähnle wrote:
> From: Nicolai Hähnle 
> 
> The order of optimizations can lead to the conditional discard optimization
> being applied twice to the same discard statement. In this case, we must
> ensure that both conditions are applied.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96762
> Cc: mesa-sta...@lists.freedesktop.org
> ---
>  src/compiler/glsl/opt_conditional_discard.cpp | 9 -
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/src/compiler/glsl/opt_conditional_discard.cpp 
> b/src/compiler/glsl/opt_conditional_discard.cpp
> index 1ca8803..a27bead 100644
> --- a/src/compiler/glsl/opt_conditional_discard.cpp
> +++ b/src/compiler/glsl/opt_conditional_discard.cpp
> @@ -72,7 +72,14 @@ opt_conditional_discard_visitor::visit_leave(ir_if *ir)
>  
> /* Move the condition and replace the ir_if with the ir_discard. */
> ir_discard *discard = (ir_discard *) ir->then_instructions.head;
> -   discard->condition = ir->condition;
> +   if (!discard->condition)
> +  discard->condition = ir->condition;
> +   else {
> +  void *ctx = ralloc_parent(ir);
> +  discard->condition = new(ctx) ir_expression(ir_binop_logic_and,
> +  ir->condition,
> +  discard->condition);
> +   }
> ir->replace_with(discard);
>  
> progress = true;
> 

Whoops, thanks for fixing this!

Reviewed-by: Kenneth Graunke 


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[Mesa-dev] [PATCH v2 35/35] isl/state: Add an assertion for IVB multisample array textures

[Jason Ekstrand]

---
 src/intel/isl/isl_surface_state.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/src/intel/isl/isl_surface_state.c 
b/src/intel/isl/isl_surface_state.c
index fb23414..990b763 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -239,6 +239,19 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, 
void *state,
switch (s.SurfaceType) {
case SURFTYPE_1D:
case SURFTYPE_2D:
+  /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement:
+   *
+   *"If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
+   *must be set to zero if this surface is used with sampling engine
+   *messages."
+   *
+   * This restriction appears to exist only on Ivy Bridge.
+   */
+  if (GEN_GEN == 7 && !GEN_IS_HASWELL && !ISL_DEV_IS_BAYTRAIL(dev) &&
+  (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) &&
+  info->surf->samples > 1)
+ assert(info->view->base_array_layer == 0);
+
   s.MinimumArrayElement = info->view->base_array_layer;
 
   /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
-- 
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[Mesa-dev] [PATCH v2 13/35] i965/blorp: Refactor interleaved multisample destination handling

[Jason Ekstrand]

We put all of the code for fake IMS together.  This requires moving a bit
of the program key setup code further down so that it gets the right values
out of the final surface.

Reviewed-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 71 +---
 1 file changed, 34 insertions(+), 37 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index c337a86..03e4984 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1698,28 +1698,6 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
   unreachable("Unrecognized blorp format");
}
 
-   if (brw->gen > 6) {
-  /* Gen7's rendering hardware only supports the IMS layout for depth and
-   * stencil render targets.  Blorp always maps its destination surface as
-   * a color render target (even if it's actually a depth or stencil
-   * buffer).  So if the destination is IMS, we'll have to map it as a
-   * single-sampled texture and interleave the samples ourselves.
-   */
-  if (dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
- params.dst.surf.samples = 1;
- params.dst.surf.msaa_layout = ISL_MSAA_LAYOUT_NONE;
-  }
-   }
-
-   if (params.src.surf.samples > 0 && params.dst.surf.samples > 1) {
-  /* We are blitting from a multisample buffer to a multisample buffer, so
-   * we must preserve samples within a pixel.  This means we have to
-   * arrange for the WM program to run once per sample rather than once
-   * per pixel.
-   */
-  wm_prog_key.persample_msaa_dispatch = true;
-   }
-
/* Scaled blitting or not. */
wm_prog_key.blit_scaled =
   ((dst_x1 - dst_x0) == (src_x1 - src_x0) &&
@@ -1759,20 +1737,8 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
wm_prog_key.src_samples = src_mt->num_samples;
wm_prog_key.dst_samples = dst_mt->num_samples;
 
-   /* tex_samples and rt_samples are the sample counts that are set up in
-* SURFACE_STATE.
-*/
-   wm_prog_key.tex_samples = params.src.surf.samples;
-   wm_prog_key.rt_samples  = params.dst.surf.samples;
-
wm_prog_key.tex_aux_usage = params.src.aux_usage;
 
-   /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
-* use to access the source and destination surfaces.
-*/
-   wm_prog_key.tex_layout = params.src.surf.msaa_layout;
-   wm_prog_key.rt_layout = params.dst.surf.msaa_layout;
-
/* src_layout and dst_layout indicate the true MSAA layout used by src and
 * dst.
 */
@@ -1809,7 +1775,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
   params.wm_inputs.src_z = 0;
}
 
-   if (params.dst.surf.samples <= 1 && dst_mt->num_samples > 1) {
+   if (brw->gen > 6 && dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
   /* We must expand the rectangle we send through the rendering pipeline,
* to account for the fact that we are mapping the destination region as
* single-sampled when it is in fact multisampled.  We must also align
@@ -1822,8 +1788,8 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
* If it's UMS, then we have no choice but to set up the rendering
* pipeline as multisampled.
*/
-  assert(dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS);
-  switch (dst_mt->num_samples) {
+  assert(params.dst.surf.msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED);
+  switch (params.dst.surf.samples) {
   case 2:
  params.x0 = ROUND_DOWN_TO(params.x0 * 2, 4);
  params.y0 = ROUND_DOWN_TO(params.y0, 4);
@@ -1851,6 +1817,16 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
   default:
  unreachable("Unrecognized sample count in brw_blorp_blit_params 
ctor");
   }
+
+  /* Gen7's rendering hardware only supports the IMS layout for depth and
+   * stencil render targets.  Blorp always maps its destination surface as
+   * a color render target (even if it's actually a depth or stencil
+   * buffer).  So if the destination is IMS, we'll have to map it as a
+   * single-sampled texture and interleave the samples ourselves.
+   */
+  params.dst.surf.samples = 1;
+  params.dst.surf.msaa_layout = ISL_MSAA_LAYOUT_NONE;
+
   wm_prog_key.use_kill = true;
}
 
@@ -1952,6 +1928,27 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
   params.src.y_offset /= 2;
}
 
+   /* tex_samples and rt_samples are the sample counts that are set up in
+* SURFACE_STATE.
+*/
+   wm_prog_key.tex_samples = params.src.surf.samples;
+   wm_prog_key.rt_samples  = params.dst.surf.samples;
+
+   /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
+* use to access the source and destination surfaces.
+*/
+   wm_prog_key.tex_layout = params.src.surf.msaa_layout;
+   wm_prog_key.rt_layout = params.dst.surf.msaa_layout;
+
+   if (params.src.surf.samples > 0 && params.dst.surf.s

[Mesa-dev] [PATCH v2 22/35] isl: Remove duplicate px->sa conversions

[Jason Ekstrand]

In all three cases, we start with width and height taken from
isl_surf::phys_slice0_extent_sa which is already in samples.  There is no
need to do the conversion and doing so gives us an incorrect value.

Reviewed-by: Nanley Chery 
---
 src/intel/isl/isl.c | 20 
 1 file changed, 20 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index f65f9c8..a9208f6 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -658,18 +658,6 @@ isl_calc_phys_slice0_extent_sa_gen4_2d(
   uint32_t W = isl_minify(W0, l);
   uint32_t H = isl_minify(H0, l);
 
-  if (msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) {
- /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip 
Level
-  * Sizes (p133):
-  *
-  *If the surface is multisampled and it is a depth or stencil
-  *surface or Multisampled Surface StorageFormat in
-  *SURFACE_STATE is MSFMT_DEPTH_STENCIL, W_L and H_L must be
-  *adjusted as follows before proceeding: [...]
-  */
- isl_msaa_interleaved_scale_px_to_sa(info->samples, &W, &H);
-  }
-
   uint32_t w = isl_align_npot(W, image_align_sa->w);
   uint32_t h = isl_align_npot(H, image_align_sa->h);
 
@@ -1370,17 +1358,9 @@ get_image_offset_sa_gen4_2d(const struct isl_surf *surf,
for (uint32_t l = 0; l < level; ++l) {
   if (l == 1) {
  uint32_t W = isl_minify(W0, l);
-
- if (surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED)
-isl_msaa_interleaved_scale_px_to_sa(surf->samples, &W, NULL);
-
  x += isl_align_npot(W, image_align_sa.w);
   } else {
  uint32_t H = isl_minify(H0, l);
-
- if (surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED)
-isl_msaa_interleaved_scale_px_to_sa(surf->samples, NULL, &H);
-
  y += isl_align_npot(H, image_align_sa.h);
   }
}
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 16/35] isl: Fix get_image_offset_sa_gen4_2d for multisample surfaces

[Jason Ekstrand]

The function takes a logical array layer but was assuming it was a physical
array layer.  While we'er here, we also make it not assert-fail on gen9 3-D
surfaces.
---
 src/intel/isl/isl.c | 13 +
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 92658ec..a713eeb 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1345,13 +1345,15 @@ isl_buffer_fill_state_s(const struct isl_device *dev, 
void *state,
  */
 static void
 get_image_offset_sa_gen4_2d(const struct isl_surf *surf,
-uint32_t level, uint32_t layer,
+uint32_t level, uint32_t logical_array_layer,
 uint32_t *x_offset_sa,
 uint32_t *y_offset_sa)
 {
assert(level < surf->levels);
-   assert(layer < surf->phys_level0_sa.array_len);
-   assert(surf->phys_level0_sa.depth == 1);
+   if (surf->dim == ISL_SURF_DIM_3D)
+  assert(logical_array_layer < surf->logical_level0_px.depth);
+   else
+  assert(logical_array_layer < surf->logical_level0_px.array_len);
 
const struct isl_extent3d image_align_sa =
   isl_surf_get_image_alignment_sa(surf);
@@ -1359,8 +1361,11 @@ get_image_offset_sa_gen4_2d(const struct isl_surf *surf,
const uint32_t W0 = surf->phys_level0_sa.width;
const uint32_t H0 = surf->phys_level0_sa.height;
 
+   const uint32_t phys_layer = logical_array_layer *
+  (surf->msaa_layout == ISL_MSAA_LAYOUT_ARRAY ? surf->samples : 1);
+
uint32_t x = 0;
-   uint32_t y = layer * isl_surf_get_array_pitch_sa_rows(surf);
+   uint32_t y = phys_layer * isl_surf_get_array_pitch_sa_rows(surf);
 
for (uint32_t l = 0; l < level; ++l) {
   if (l == 1) {
-- 
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[Mesa-dev] [PATCH v2 15/35] i965/blorp: Add an isl_view to blorp_surface_info

[Jason Ekstrand]

Eventually, this will be the actual view that gets passed into isl to
create the surface state.  For now, we just use it for the format and the
swizzle.
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 38 +++
 src/mesa/drivers/dri/i965/brw_blorp.h | 16 ++-
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp  | 34 
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp |  2 +-
 src/mesa/drivers/dri/i965/gen8_blorp.c| 29 
 5 files changed, 64 insertions(+), 55 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 8f7690c..ef256a7 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -43,9 +43,11 @@ brw_blorp_surface_info_init(struct brw_context *brw,
 * using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it had better
 * be a multiple of num_samples.
 */
+   unsigned layer_multiplier = 1;
if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
   assert(mt->num_samples <= 1 || layer % mt->num_samples == 0);
+  layer_multiplier = MAX2(mt->num_samples, 1);
}
 
intel_miptree_check_level_layer(mt, level, layer);
@@ -61,13 +63,27 @@ brw_blorp_surface_info_init(struct brw_context *brw,
   info->aux_usage = ISL_AUX_USAGE_NONE;
}
 
+   info->view = (struct isl_view) {
+  .usage = is_render_target ? ISL_SURF_USAGE_RENDER_TARGET_BIT :
+  ISL_SURF_USAGE_TEXTURE_BIT,
+  .format = ISL_FORMAT_UNSUPPORTED, /* Set later */
+  .base_level = level,
+  .levels = 1,
+  .base_array_layer = layer / layer_multiplier,
+  .array_len = 1,
+  .channel_select = {
+ ISL_CHANNEL_SELECT_RED,
+ ISL_CHANNEL_SELECT_GREEN,
+ ISL_CHANNEL_SELECT_BLUE,
+ ISL_CHANNEL_SELECT_ALPHA,
+  },
+   };
+
info->level = level;
info->layer = layer;
info->width = minify(mt->physical_width0, level - mt->first_level);
info->height = minify(mt->physical_height0, level - mt->first_level);
 
-   info->swizzle = SWIZZLE_XYZW;
-
if (format == MESA_FORMAT_NONE)
   format = mt->format;
 
@@ -75,8 +91,8 @@ brw_blorp_surface_info_init(struct brw_context *brw,
case MESA_FORMAT_S_UINT8:
   assert(info->surf.tiling == ISL_TILING_W);
   /* Prior to Broadwell, we can't render to R8_UINT */
-  info->brw_surfaceformat = brw->gen >= 8 ? BRW_SURFACEFORMAT_R8_UINT :
-BRW_SURFACEFORMAT_R8_UNORM;
+  info->view.format = brw->gen >= 8 ? BRW_SURFACEFORMAT_R8_UINT :
+  BRW_SURFACEFORMAT_R8_UNORM;
   break;
case MESA_FORMAT_Z24_UNORM_X8_UINT:
   /* It would make sense to use BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
@@ -89,20 +105,20 @@ brw_blorp_surface_info_init(struct brw_context *brw,
* pattern as long as we copy the right amount of data, so just map it
* as 8-bit BGRA.
*/
-  info->brw_surfaceformat = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
+  info->view.format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
   break;
case MESA_FORMAT_Z_FLOAT32:
-  info->brw_surfaceformat = BRW_SURFACEFORMAT_R32_FLOAT;
+  info->view.format = BRW_SURFACEFORMAT_R32_FLOAT;
   break;
case MESA_FORMAT_Z_UNORM16:
-  info->brw_surfaceformat = BRW_SURFACEFORMAT_R16_UNORM;
+  info->view.format = BRW_SURFACEFORMAT_R16_UNORM;
   break;
default: {
   if (is_render_target) {
  assert(brw->format_supported_as_render_target[format]);
- info->brw_surfaceformat = brw->render_target_format[format];
+ info->view.format = brw->render_target_format[format];
   } else {
- info->brw_surfaceformat = brw_format_for_mesa_format(format);
+ info->view.format = brw_format_for_mesa_format(format);
   }
   break;
}
@@ -111,7 +127,7 @@ brw_blorp_surface_info_init(struct brw_context *brw,
uint32_t x_offset, y_offset;
intel_miptree_get_image_offset(mt, level, layer, &x_offset, &y_offset);
 
-   uint8_t bs = isl_format_get_layout(info->brw_surfaceformat)->bpb / 8;
+   uint8_t bs = isl_format_get_layout(info->view.format)->bpb / 8;
isl_tiling_get_intratile_offset_el(&brw->isl_dev, info->surf.tiling, bs,
   info->surf.row_pitch, x_offset, y_offset,
   &info->bo_offset,
@@ -287,7 +303,7 @@ brw_blorp_emit_surface_state(struct brw_context *brw,
}
 
struct isl_view view = {
-  .format = surface->brw_surfaceformat,
+  .format = surface->view.format,
   .base_level = 0,
   .levels = 1,
   .base_array_layer = 0,
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index e591f41..185406e 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h

[Mesa-dev] [PATCH v2 34/35] isl: Add a #define for DEV_IS_BAYTRAIL

[Jason Ekstrand]

---
 src/intel/isl/isl.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 68ad8a4..b8b48f0 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -79,6 +79,10 @@ struct brw_image_param;
 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
 #endif
 
+#ifndef ISL_DEV_IS_BAYTRAIL
+#define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail)
+#endif
+
 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
 /**
  * You can define this as a compile-time constant in the CFLAGS. For example,
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 04/35] i965/blorp/clear: Initialize surface info after allocating an MCS

[Jason Ekstrand]

Reviewed-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 1bc0dbb..1e00719 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -135,12 +135,6 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
if (!encode_srgb && _mesa_get_format_color_encoding(format) == GL_SRGB)
   format = _mesa_get_srgb_format_linear(format);
 
-   brw_blorp_surface_info_init(brw, ¶ms.dst, irb->mt, irb->mt_level,
-   layer, format, true);
-
-   /* Override the surface format according to the context's sRGB rules. */
-   params.dst.brw_surfaceformat = brw->render_target_format[format];
-
params.x0 = fb->_Xmin;
params.x1 = fb->_Xmax;
if (rb->Name != 0) {
@@ -218,6 +212,12 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
   }
}
 
+   brw_blorp_surface_info_init(brw, ¶ms.dst, irb->mt, irb->mt_level,
+   layer, format, true);
+
+   /* Override the surface format according to the context's sRGB rules. */
+   params.dst.brw_surfaceformat = brw->render_target_format[format];
+
const char *clear_type;
if (is_fast_clear)
   clear_type = "fast";
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 20/35] i965/blorp: Get rid of brw_blorp_surface_info::width/height

[Jason Ekstrand]

Instead, we manually mutate the surface size as needed.
---
 src/mesa/drivers/dri/i965/brw_blorp.c| 21 ++---
 src/mesa/drivers/dri/i965/brw_blorp.h| 12 
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 19 +++
 src/mesa/drivers/dri/i965/gen6_blorp.c   |  4 ++--
 src/mesa/drivers/dri/i965/gen7_blorp.c   |  4 ++--
 5 files changed, 25 insertions(+), 35 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 8ccb8da..78707ca 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -203,8 +203,6 @@ brw_blorp_surface_info_init(struct brw_context *brw,
 
info->level = level;
info->layer = layer;
-   info->width = minify(mt->physical_width0, level - mt->first_level);
-   info->height = minify(mt->physical_height0, level - mt->first_level);
 
if (format == MESA_FORMAT_NONE)
   format = mt->format;
@@ -373,10 +371,6 @@ brw_blorp_emit_surface_state(struct brw_context *brw,
 
struct isl_surf surf = surface->surf;
 
-   /* Stomp surface dimensions and tiling (if needed) with info from blorp */
-   surf.logical_level0_px.width = surface->width;
-   surf.logical_level0_px.height = surface->height;
-
union isl_color_value clear_color = { .u32 = { 0, 0, 0, 0 } };
 
const struct isl_surf *aux_surf = NULL;
@@ -610,16 +604,13 @@ gen6_blorp_hiz_exec(struct brw_context *brw, struct 
intel_mipmap_tree *mt,
 * prevents the clobbering.
 */
params.dst.surf.samples = MAX2(mt->num_samples, 1);
-   if (params.depth.surf.samples > 1) {
-  params.depth.width = ALIGN(mt->logical_width0, 8);
-  params.depth.height = ALIGN(mt->logical_height0, 4);
-   } else {
-  params.depth.width = ALIGN(params.depth.width, 8);
-  params.depth.height = ALIGN(params.depth.height, 4);
-   }
+   params.depth.surf.logical_level0_px.width =
+  ALIGN(params.depth.surf.logical_level0_px.width, 8);
+   params.depth.surf.logical_level0_px.height =
+  ALIGN(params.depth.surf.logical_level0_px.height, 4);
 
-   params.x1 = params.depth.width;
-   params.y1 = params.depth.height;
+   params.x1 = params.depth.surf.logical_level0_px.width;
+   params.y1 = params.depth.surf.logical_level0_px.height;
 
assert(intel_miptree_level_has_hiz(mt, level));
 
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 185406e..282235d 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -94,18 +94,6 @@ struct brw_blorp_surface_info
 */
uint32_t layer;
 
-   /**
-* Width of the miplevel to be used.  For surfaces using
-* INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
-*/
-   uint32_t width;
-
-   /**
-* Height of the miplevel to be used.  For surfaces using
-* INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
-*/
-   uint32_t height;
-
uint32_t bo_offset;
uint32_t tile_x_sa, tile_y_sa;
 };
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 32450aa..fb81a22 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1816,24 +1816,31 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
  params.y0 = ROUND_DOWN_TO(params.y0, 4);
  params.x1 = ALIGN(params.x1 * 2, 4);
  params.y1 = ALIGN(params.y1, 4);
+ params.dst.surf.logical_level0_px.width *= 2;
  break;
   case 4:
  params.x0 = ROUND_DOWN_TO(params.x0 * 2, 4);
  params.y0 = ROUND_DOWN_TO(params.y0 * 2, 4);
  params.x1 = ALIGN(params.x1 * 2, 4);
  params.y1 = ALIGN(params.y1 * 2, 4);
+ params.dst.surf.logical_level0_px.width *= 2;
+ params.dst.surf.logical_level0_px.height *= 2;
  break;
   case 8:
  params.x0 = ROUND_DOWN_TO(params.x0 * 4, 8);
  params.y0 = ROUND_DOWN_TO(params.y0 * 2, 4);
  params.x1 = ALIGN(params.x1 * 4, 8);
  params.y1 = ALIGN(params.y1 * 2, 4);
+ params.dst.surf.logical_level0_px.width *= 4;
+ params.dst.surf.logical_level0_px.height *= 2;
  break;
   case 16:
  params.x0 = ROUND_DOWN_TO(params.x0 * 4, 8);
  params.y0 = ROUND_DOWN_TO(params.y0 * 4, 8);
  params.x1 = ALIGN(params.x1 * 4, 8);
  params.y1 = ALIGN(params.y1 * 4, 8);
+ params.dst.surf.logical_level0_px.width *= 4;
+ params.dst.surf.logical_level0_px.height *= 4;
  break;
   default:
  unreachable("Unrecognized sample count in brw_blorp_blit_params 
ctor");
@@ -1918,8 +1925,10 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
   params.y0 = ROUND_DOWN_TO(params.y0, y_align) / 2;
   params.x1 = ALIGN(params.x1, x_align) * 2;
   params.y1 = ALIGN(params.y1, y_align) / 2;
-  params.dst.width = ALIGN(params.dst.wid

[Mesa-dev] [PATCH v2 12/35] i965/blorp: Get rid of brw_blorp_surface_info::array_layout

[Jason Ekstrand]

Reviewed-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 1 -
 src/mesa/drivers/dri/i965/brw_blorp.h | 9 -
 2 files changed, 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 96201e4..48755fc 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -69,7 +69,6 @@ brw_blorp_surface_info_init(struct brw_context *brw,
intel_miptree_get_image_offset(mt, level, layer,
   &info->x_offset, &info->y_offset);
 
-   info->array_layout = mt->array_layout;
info->swizzle = SWIZZLE_XYZW;
 
if (format == MESA_FORMAT_NONE)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index d60b988..7aa67be 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -119,15 +119,6 @@ struct brw_blorp_surface_info
uint32_t y_offset;
 
/**
-* Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
-* or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
-*
-* If ALL_SLICES_AT_EACH_LOD is set, then ARYSPC_LOD0 can be used. Ignored
-* prior to Gen7.
-*/
-   enum miptree_array_layout array_layout;
-
-   /**
 * Format that should be used when setting up the surface state for this
 * surface.  Should correspond to one of the BRW_SURFACEFORMAT_* enums.
 */
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 03/35] isl/state: Use a valid alignment for 1-D textures

[Jason Ekstrand]

The alignment we use doesn't matter (see the comment) but it should at
least be an alignment we can represent with the enums.

Reviewed-by: Topi Pohjolainen 
---
 src/intel/isl/isl_surface_state.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/isl/isl_surface_state.c 
b/src/intel/isl/isl_surface_state.c
index d1c8f17..6febcbf 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -142,7 +142,7 @@ get_image_alignment(const struct isl_surf *surf)
   * true alignment is likely outside the enum range of HALIGN* and
   * VALIGN*.
   */
- return isl_extent3d(0, 0, 0);
+ return isl_extent3d(4, 4, 1);
   } else {
  /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in 
units
   * of surface elements (not pixels nor samples). For compressed 
formats,
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 05/35] i965/blorp: Create the isl_surf up-front

[Jason Ekstrand]

Reviewed-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 25 ++---
 src/mesa/drivers/dri/i965/brw_blorp.h |  5 +
 2 files changed, 19 insertions(+), 11 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index e0d9526..5889e95 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -51,6 +51,16 @@ brw_blorp_surface_info_init(struct brw_context *brw,
intel_miptree_check_level_layer(mt, level, layer);
 
info->mt = mt;
+
+   intel_miptree_get_isl_surf(brw, mt, &info->surf);
+
+   if (mt->mcs_mt) {
+  intel_miptree_get_aux_isl_surf(brw, mt, &info->aux_surf,
+ &info->aux_usage);
+   } else {
+  info->aux_usage = ISL_AUX_USAGE_NONE;
+   }
+
info->level = level;
info->layer = layer;
info->width = minify(mt->physical_width0, level - mt->first_level);
@@ -273,8 +283,7 @@ brw_blorp_emit_surface_state(struct brw_context *brw,
 {
const struct surface_state_info ss_info = surface_state_infos[brw->gen];
 
-   struct isl_surf surf;
-   intel_miptree_get_isl_surf(brw, surface->mt, &surf);
+   struct isl_surf surf = surface->surf;
 
/* Stomp surface dimensions and tiling (if needed) with info from blorp */
surf.dim = ISL_SURF_DIM_2D;
@@ -315,16 +324,10 @@ brw_blorp_emit_surface_state(struct brw_context *brw,
 
union isl_color_value clear_color = { .u32 = { 0, 0, 0, 0 } };
 
-   struct isl_surf *aux_surf = NULL, aux_surf_s;
+   const struct isl_surf *aux_surf = NULL;
uint64_t aux_offset = 0;
-   enum isl_aux_usage aux_usage = ISL_AUX_USAGE_NONE;
if (surface->mt->mcs_mt) {
-  /* We should probably to similar stomping to above but most of the aux
-   * surf gets ignored when we fill out the surface state anyway so
-   * there's no point.
-   */
-  intel_miptree_get_aux_isl_surf(brw, surface->mt, &aux_surf_s, 
&aux_usage);
-  aux_surf = &aux_surf_s;
+  aux_surf = &surface->aux_surf;
   assert(surface->mt->mcs_mt->offset == 0);
   aux_offset = surface->mt->mcs_mt->bo->offset64;
 
@@ -362,7 +365,7 @@ brw_blorp_emit_surface_state(struct brw_context *brw,
 
isl_surf_fill_state(&brw->isl_dev, dw, .surf = &surf, .view = &view,
.address = surface->mt->bo->offset64 + offset,
-   .aux_surf = aux_surf, .aux_usage = aux_usage,
+   .aux_surf = aux_surf, .aux_usage = surface->aux_usage,
.aux_address = aux_offset,
.mocs = mocs, .clear_color = clear_color,
.x_offset_sa = tile_x, .y_offset_sa = tile_y);
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index beef90e..e23f48b 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -71,6 +71,11 @@ struct brw_blorp_surface_info
 {
struct intel_mipmap_tree *mt;
 
+   struct isl_surf surf;
+
+   struct isl_surf aux_surf;
+   enum isl_aux_usage aux_usage;
+
/**
 * The miplevel to use.
 */
-- 
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[Mesa-dev] [PATCH v2 00/35] i965: Rework blorp to use ISL internally

[Jason Ekstrand]

This series is mostly just a resend of an earlier series that makes blorp
use ISL internally.  The original series can be found here:

https://lists.freedesktop.org/archives/mesa-dev/2016-June/121891.html

The patches haven't really changed but they've been rebased and a few new
patches squashed in as other i965 bits have changed.

Jason Ekstrand (35):
  isl: Fix the parameter names for get_intratile_offset
  i965/miptree: Remove the stencil_as_y_tiled parameter from
get_tile_masks
  isl/state: Use a valid alignment for 1-D textures
  i965/blorp/clear: Initialize surface info after allocating an MCS
  i965/blorp: Create the isl_surf up-front
  i965/blorp: Remove compute_tile_offsets
  i965/blorp: Get rid of brw_blorp_surface_info::map_stencil_as_y_tiled
  i965/blorp: Make sample count asserts a bit more lazy
  i965/blorp: Get rid of brw_blorp_surface_info::num_samples
  i965/blorp: Use the ISL aux_layout for deciding whether to do an MCS
fetch
  i965/blorp: Use isl_msaa_layout instead of intel_msaa_layout
  i965/blorp: Get rid of brw_blorp_surface_info::array_layout
  i965/blorp: Refactor interleaved multisample destination handling
  i965/blorp: Move intratile offset calculations out of surface state
setup
  i965/blorp: Add an isl_view to blorp_surface_info
  isl: Fix get_image_offset_sa_gen4_2d for multisample surfaces
  isl: Add functions for computing surface offsets in samples
  i965/blorp: Use ISL to compute image offsets
  i965/blorp: Move surface offset calculations into a helper
  i965/blorp: Get rid of brw_blorp_surface_info::width/height
  i965/blorp: Use the isl_view from the blorp_surface_info
  isl: Remove duplicate px->sa conversions
  isl: Take the slice0_extent shortcut for interleaved MSAA
  i965/miptree: Fill out the isl_surf::usage field
  i965/blorp: Map 1-D render targets with DIM_LAYOUT_GEN4_2D as 2D on
gen9
  i965/blorp: Rework hiz rect alignment calculations
  i965/blorp: Pass the Z component into all texture operations
  i965/blorp: Add a z_offset field to blorp_surface_info
  i965/blorp: Only do offset hacks for fake W-tiling and IMS
  isl: Add asserts for gen8+ X/YOffset rules
  i965/blorp: Use the generic surface state path for gen8 textures
  i965/blorp: Simplify depth buffer state setup a bit
  i965/blorp: Remove unused fields from blorp_surface_info
  isl: Add a #define for DEV_IS_BAYTRAIL
  isl/state: Add an assertion for IVB multisample array textures

 src/intel/isl/isl.c  |  59 ++-
 src/intel/isl/isl.h  |  60 ++-
 src/intel/isl/isl_surface_state.c|  25 +-
 src/mesa/drivers/dri/i965/brw_blorp.c| 290 +++---
 src/mesa/drivers/dri/i965/brw_blorp.h| 112 +-
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 468 +--
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp|  12 +-
 src/mesa/drivers/dri/i965/brw_misc_state.c   |   6 +-
 src/mesa/drivers/dri/i965/brw_state.h|   7 -
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |   2 +-
 src/mesa/drivers/dri/i965/gen6_blorp.c   |  44 +--
 src/mesa/drivers/dri/i965/gen7_blorp.c   |  48 +--
 src/mesa/drivers/dri/i965/gen8_blorp.c   |  73 +---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c|  30 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h|   1 -
 15 files changed, 608 insertions(+), 629 deletions(-)

-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 02/35] i965/miptree: Remove the stencil_as_y_tiled parameter from get_tile_masks

[Jason Ekstrand]

It's only used to stomp the tiling to Y and it's only used by blorp so
there's no reason why blorp can't do it itself.

Reviewed-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 6 --
 src/mesa/drivers/dri/i965/brw_misc_state.c| 6 +++---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 +
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 1 -
 4 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 282a5b2..e0d9526 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -122,9 +122,11 @@ brw_blorp_compute_tile_offsets(const struct 
brw_blorp_surface_info *info,
uint32_t *tile_x, uint32_t *tile_y)
 {
uint32_t mask_x, mask_y;
+   uint32_t tiling = info->mt->tiling;
+   if (info->map_stencil_as_y_tiled)
+  tiling = I915_TILING_Y;
 
-   intel_get_tile_masks(info->mt->tiling, info->mt->tr_mode, info->mt->cpp,
-info->map_stencil_as_y_tiled,
+   intel_get_tile_masks(tiling, info->mt->tr_mode, info->mt->cpp,
 &mask_x, &mask_y);
 
*tile_x = info->x_offset & mask_x;
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index c3d341f..cc62dab 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -177,7 +177,7 @@ brw_get_depthstencil_tile_masks(struct intel_mipmap_tree 
*depth_mt,
 
if (depth_mt) {
   intel_get_tile_masks(depth_mt->tiling, depth_mt->tr_mode,
-   depth_mt->cpp, false,
+   depth_mt->cpp,
&tile_mask_x, &tile_mask_y);
 
   if (intel_miptree_level_has_hiz(depth_mt, depth_level)) {
@@ -185,7 +185,7 @@ brw_get_depthstencil_tile_masks(struct intel_mipmap_tree 
*depth_mt,
  intel_get_tile_masks(depth_mt->hiz_buf->mt->tiling,
   depth_mt->hiz_buf->mt->tr_mode,
   depth_mt->hiz_buf->mt->cpp,
-  false, &hiz_tile_mask_x,
+  &hiz_tile_mask_x,
   &hiz_tile_mask_y);
 
  /* Each HiZ row represents 2 rows of pixels */
@@ -209,7 +209,7 @@ brw_get_depthstencil_tile_masks(struct intel_mipmap_tree 
*depth_mt,
  intel_get_tile_masks(stencil_mt->tiling,
   stencil_mt->tr_mode,
   stencil_mt->cpp,
-  false, &stencil_tile_mask_x,
+  &stencil_tile_mask_x,
   &stencil_tile_mask_y);
 
  tile_mask_x |= stencil_tile_mask_x;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 1e03f7e..3860088 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1232,12 +1232,9 @@ intel_get_tile_dims(uint32_t tiling, uint32_t tr_mode, 
uint32_t cpp,
  */
 void
 intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
- bool map_stencil_as_y_tiled,
  uint32_t *mask_x, uint32_t *mask_y)
 {
uint32_t tile_w_bytes, tile_h;
-   if (map_stencil_as_y_tiled)
-  tiling = I915_TILING_Y;
 
intel_get_tile_dims(tiling, tr_mode, cpp, &tile_w_bytes, &tile_h);
 
@@ -1307,7 +1304,7 @@ intel_miptree_get_tile_offsets(const struct 
intel_mipmap_tree *mt,
uint32_t x, y;
uint32_t mask_x, mask_y;
 
-   intel_get_tile_masks(mt->tiling, mt->tr_mode, mt->cpp, false, &mask_x, 
&mask_y);
+   intel_get_tile_masks(mt->tiling, mt->tr_mode, mt->cpp, &mask_x, &mask_y);
intel_miptree_get_image_offset(mt, level, slice, &x, &y);
 
*tile_x = x & mask_x;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 4388741..c28fb33 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -817,7 +817,6 @@ intel_get_image_dims(struct gl_texture_image *image,
 
 void
 intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
- bool map_stencil_as_y_tiled,
  uint32_t *mask_x, uint32_t *mask_y);
 
 void
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 27/35] i965/blorp: Pass the Z component into all texture operations

[Jason Ekstrand]

Multisample array surfaces on IVB don't support the minimum array element
surface attribute so it needs to come through the sampler message.  We may
as well just pass it through everything.
---
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 77 +---
 1 file changed, 35 insertions(+), 42 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index fb81a22..a76d130 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -432,11 +432,11 @@ blorp_nir_discard_if_outside_rect(nir_builder *b, 
nir_ssa_def *pos,
 }
 
 static nir_tex_instr *
-blorp_create_nir_tex_instr(nir_shader *shader, nir_texop op,
-   nir_ssa_def *pos, unsigned num_srcs,
+blorp_create_nir_tex_instr(nir_builder *b, struct brw_blorp_blit_vars *v,
+   nir_texop op, nir_ssa_def *pos, unsigned num_srcs,
enum brw_reg_type dst_type)
 {
-   nir_tex_instr *tex = nir_tex_instr_create(shader, num_srcs);
+   nir_tex_instr *tex = nir_tex_instr_create(b->shader, num_srcs);
 
tex->op = op;
 
@@ -463,22 +463,32 @@ blorp_create_nir_tex_instr(nir_shader *shader, nir_texop 
op,
tex->texture_index = 0;
tex->sampler_index = 0;
 
+   /* To properly handle 3-D and 2-D array textures, we pull the Z component
+* from a uniform.  TODO: This is a bit magic; we should probably make this
+* more explicit in the future.
+*/
+   assert(pos->num_components >= 2);
+   pos = nir_vec3(b, nir_channel(b, pos, 0), nir_channel(b, pos, 1),
+ nir_load_var(b, v->v_src_z));
+
+   tex->src[0].src_type = nir_tex_src_coord;
+   tex->src[0].src = nir_src_for_ssa(pos);
+   tex->coord_components = 3;
+
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, NULL);
 
return tex;
 }
 
 static nir_ssa_def *
-blorp_nir_tex(nir_builder *b, nir_ssa_def *pos, enum brw_reg_type dst_type)
+blorp_nir_tex(nir_builder *b, struct brw_blorp_blit_vars *v,
+  nir_ssa_def *pos, enum brw_reg_type dst_type)
 {
nir_tex_instr *tex =
-  blorp_create_nir_tex_instr(b->shader, nir_texop_tex, pos, 2, dst_type);
+  blorp_create_nir_tex_instr(b, v, nir_texop_tex, pos, 2, dst_type);
 
assert(pos->num_components == 2);
tex->sampler_dim = GLSL_SAMPLER_DIM_2D;
-   tex->coord_components = 2;
-   tex->src[0].src_type = nir_tex_src_coord;
-   tex->src[0].src = nir_src_for_ssa(pos);
tex->src[1].src_type = nir_tex_src_lod;
tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
 
@@ -492,20 +502,9 @@ blorp_nir_txf(nir_builder *b, struct brw_blorp_blit_vars 
*v,
   nir_ssa_def *pos, enum brw_reg_type dst_type)
 {
nir_tex_instr *tex =
-  blorp_create_nir_tex_instr(b->shader, nir_texop_txf, pos, 2, dst_type);
-
-   /* In order to properly handle 3-D textures, we pull the Z component from
-* a uniform.  TODO: This is a bit magic; we should probably make this
-* more explicit in the future.
-*/
-   assert(pos->num_components == 2);
-   pos = nir_vec3(b, nir_channel(b, pos, 0), nir_channel(b, pos, 1),
- nir_load_var(b, v->v_src_z));
+  blorp_create_nir_tex_instr(b, v, nir_texop_txf, pos, 2, dst_type);
 
tex->sampler_dim = GLSL_SAMPLER_DIM_3D;
-   tex->coord_components = 3;
-   tex->src[0].src_type = nir_tex_src_coord;
-   tex->src[0].src = nir_src_for_ssa(pos);
tex->src[1].src_type = nir_tex_src_lod;
tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
 
@@ -515,17 +514,14 @@ blorp_nir_txf(nir_builder *b, struct brw_blorp_blit_vars 
*v,
 }
 
 static nir_ssa_def *
-blorp_nir_txf_ms(nir_builder *b, nir_ssa_def *pos, nir_ssa_def *mcs,
- enum brw_reg_type dst_type)
+blorp_nir_txf_ms(nir_builder *b, struct brw_blorp_blit_vars *v,
+ nir_ssa_def *pos, nir_ssa_def *mcs, enum brw_reg_type 
dst_type)
 {
nir_tex_instr *tex =
-  blorp_create_nir_tex_instr(b->shader, nir_texop_txf_ms, pos,
+  blorp_create_nir_tex_instr(b, v, nir_texop_txf_ms, pos,
  mcs != NULL ? 3 : 2, dst_type);
 
tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
-   tex->coord_components = 2;
-   tex->src[0].src_type = nir_tex_src_coord;
-   tex->src[0].src = nir_src_for_ssa(pos);
 
tex->src[1].src_type = nir_tex_src_ms_index;
if (pos->num_components == 2) {
@@ -546,16 +542,13 @@ blorp_nir_txf_ms(nir_builder *b, nir_ssa_def *pos, 
nir_ssa_def *mcs,
 }
 
 static nir_ssa_def *
-blorp_nir_txf_ms_mcs(nir_builder *b, nir_ssa_def *pos)
+blorp_nir_txf_ms_mcs(nir_builder *b, struct brw_blorp_blit_vars *v, 
nir_ssa_def *pos)
 {
nir_tex_instr *tex =
-  blorp_create_nir_tex_instr(b->shader, nir_texop_txf_ms_mcs,
+  blorp_create_nir_tex_instr(b, v, nir_texop_txf_ms_mcs,
  pos, 1, BRW_REGISTER_TYPE_D);
 
tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
-   tex->coord_components = 2;
-   tex->src[0].src_type 

[Mesa-dev] [PATCH v2 10/35] i965/blorp: Use the ISL aux_layout for deciding whether to do an MCS fetch

[Jason Ekstrand]

Reviewed-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.h|  2 ++
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 16 +---
 2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 7c38d10..0f142b4 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -300,6 +300,8 @@ struct brw_blorp_blit_prog_key
 */
enum intel_msaa_layout tex_layout;
 
+   enum isl_aux_usage tex_aux_usage;
+
/* Actual number of samples per pixel in the source image. */
unsigned src_samples;
 
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 5a4cbed..ce00bb7 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -901,7 +901,7 @@ static inline int count_trailing_one_bits(unsigned value)
 static nir_ssa_def *
 blorp_nir_manual_blend_average(nir_builder *b, nir_ssa_def *pos,
unsigned tex_samples,
-   enum intel_msaa_layout tex_layout,
+   enum isl_aux_usage tex_aux_usage,
enum brw_reg_type dst_type)
 {
/* If non-null, this is the outer-most if statement */
@@ -911,7 +911,7 @@ blorp_nir_manual_blend_average(nir_builder *b, nir_ssa_def 
*pos,
   nir_local_variable_create(b->impl, glsl_vec4_type(), "color");
 
nir_ssa_def *mcs = NULL;
-   if (tex_layout == INTEL_MSAA_LAYOUT_CMS)
+   if (tex_aux_usage == ISL_AUX_USAGE_MCS)
   mcs = blorp_nir_txf_ms_mcs(b, pos);
 
/* We add together samples using a binary tree structure, e.g. for 4x MSAA:
@@ -956,7 +956,7 @@ blorp_nir_manual_blend_average(nir_builder *b, nir_ssa_def 
*pos,
 nir_imm_int(b, i));
   texture_data[stack_depth++] = blorp_nir_txf_ms(b, ms_pos, mcs, dst_type);
 
-  if (i == 0 && tex_layout == INTEL_MSAA_LAYOUT_CMS) {
+  if (i == 0 && tex_aux_usage == ISL_AUX_USAGE_MCS) {
  /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
   * suggests an optimization:
   *
@@ -1073,7 +1073,7 @@ blorp_nir_manual_blend_bilinear(nir_builder *b, 
nir_ssa_def *pos,
* here inside the loop after computing the pixel coordinates.
*/
   nir_ssa_def *mcs = NULL;
-  if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS)
+  if (key->tex_aux_usage == ISL_AUX_USAGE_MCS)
  mcs = blorp_nir_txf_ms_mcs(b, sample_coords_int);
 
   /* Compute sample index and map the sample index to a sample number.
@@ -1432,7 +1432,7 @@ brw_blorp_build_nir_shader(struct brw_context *brw,
   } else {
  /* Gen7+ hardware doesn't automaticaly blend. */
  color = blorp_nir_manual_blend_average(&b, src_pos, key->src_samples,
-key->src_layout,
+key->tex_aux_usage,
 key->texture_data_type);
   }
} else if (key->blend && key->blit_scaled) {
@@ -1485,7 +1485,7 @@ brw_blorp_build_nir_shader(struct brw_context *brw,
 color = blorp_nir_txf(&b, &v, src_pos, key->texture_data_type);
  } else {
 nir_ssa_def *mcs = NULL;
-if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS)
+if (key->tex_aux_usage == ISL_AUX_USAGE_MCS)
mcs = blorp_nir_txf_ms_mcs(&b, src_pos);
 
 color = blorp_nir_txf_ms(&b, src_pos, mcs, key->texture_data_type);
@@ -1519,7 +1519,7 @@ brw_blorp_get_blit_kernel(struct brw_context *brw,
struct brw_wm_prog_key wm_key;
brw_blorp_init_wm_prog_key(&wm_key);
wm_key.tex.compressed_multisample_layout_mask =
-  prog_key->tex_layout == INTEL_MSAA_LAYOUT_CMS;
+  prog_key->tex_aux_usage == ISL_AUX_USAGE_MCS;
wm_key.tex.msaa_16 = prog_key->tex_samples == 16;
wm_key.multisample_fbo = prog_key->rt_samples > 1;
 
@@ -1791,6 +1791,8 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
wm_prog_key.tex_samples = params.src.surf.samples;
wm_prog_key.rt_samples  = params.dst.surf.samples;
 
+   wm_prog_key.tex_aux_usage = params.src.aux_usage;
+
/* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
 * use to access the source and destination surfaces.
 */
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 23/27] i965/blorp: Break the guts of do_single_blorp_clear into two helpers

[Jason Ekstrand]

The helpers are completely miptree-unaware and each fairly cleanly do a
single thing.  This does come at the downside of not doing proper debug
reporting on whether or not we're doing replicated clears.
---
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 175 --
 1 file changed, 111 insertions(+), 64 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 6cb28d0..4b4b8af 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -120,33 +120,51 @@ set_write_disables(const struct intel_renderbuffer *irb,
return disables;
 }
 
-static bool
-do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
-  struct gl_renderbuffer *rb, unsigned buf,
-  bool partial_clear, bool encode_srgb, unsigned layer)
-{
-   struct gl_context *ctx = &brw->ctx;
-   struct intel_renderbuffer *irb = intel_renderbuffer(rb);
-   mesa_format format = irb->mt->format;
 
+static void
+blorp_fast_clear(struct brw_context *brw, const struct brw_blorp_surf *surf,
+ uint32_t level, uint32_t layer,
+ uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1)
+{
struct brw_blorp_params params;
brw_blorp_params_init(¶ms);
 
-   /* Override the surface format according to the context's sRGB rules. */
-   if (!encode_srgb && _mesa_get_format_color_encoding(format) == GL_SRGB)
-  format = _mesa_get_srgb_format_linear(format);
+   params.x0 = x0;
+   params.y0 = y0;
+   params.x1 = x1;
+   params.y1 = y1;
 
-   params.x0 = fb->_Xmin;
-   params.x1 = fb->_Xmax;
-   if (rb->Name != 0) {
-  params.y0 = fb->_Ymin;
-  params.y1 = fb->_Ymax;
-   } else {
-  params.y0 = rb->Height - fb->_Ymax;
-  params.y1 = rb->Height - fb->_Ymin;
-   }
+   memset(¶ms.wm_inputs, 0xff, 4*sizeof(float));
+   params.fast_clear_op = GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE;
+
+   brw_get_fast_clear_rect(brw, surf->aux_surf, ¶ms.x0, ¶ms.y0,
+   ¶ms.x1, ¶ms.y1);
+
+   brw_blorp_params_get_clear_kernel(brw, ¶ms, true);
+
+   brw_blorp_surface_info_init(brw, ¶ms.dst, surf, level, layer,
+   surf->surf->format, true);
+
+   brw_blorp_exec(brw, ¶ms);
+}
 
-   memcpy(¶ms.wm_inputs, ctx->Color.ClearColor.f, sizeof(float) * 4);
+
+static void
+blorp_clear(struct brw_context *brw, const struct brw_blorp_surf *surf,
+uint32_t level, uint32_t layer,
+uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1,
+enum isl_format format, union isl_color_value clear_color,
+bool color_write_disable[4])
+{
+   struct brw_blorp_params params;
+   brw_blorp_params_init(¶ms);
+
+   params.x0 = x0;
+   params.y0 = y0;
+   params.x1 = x1;
+   params.y1 = y1;
+
+   memcpy(¶ms.wm_inputs, clear_color.f32, sizeof(float) * 4);
 
bool use_simd16_replicated_data = true;
 
@@ -156,21 +174,60 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
 *  accessing tiled memory.  Using this Message Type to access linear
 *  (untiled) memory is UNDEFINED."
 */
-   if (irb->mt->tiling == I915_TILING_NONE)
+   if (surf->surf->tiling == ISL_TILING_LINEAR)
   use_simd16_replicated_data = false;
 
/* Constant color writes ignore everyting in blend and color calculator
 * state.  This is not documented.
 */
-   if (set_write_disables(irb, ctx->Color.ColorMask[buf],
-  params.color_write_disable))
-  use_simd16_replicated_data = false;
+   for (unsigned i = 0; i < 4; i++) {
+  params.color_write_disable[i] = color_write_disable[i];
+  if (color_write_disable[i])
+ use_simd16_replicated_data = false;
+   }
+
+   brw_blorp_params_get_clear_kernel(brw, ¶ms, use_simd16_replicated_data);
+
+   brw_blorp_surface_info_init(brw, ¶ms.dst, surf, level, layer,
+   format, true);
 
-   bool is_fast_clear = false;
-   if (irb->mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_NO_MCS &&
-   !partial_clear && use_simd16_replicated_data &&
-   brw_is_color_fast_clear_compatible(brw, irb->mt,
-  &ctx->Color.ClearColor)) {
+   brw_blorp_exec(brw, ¶ms);
+}
+
+static bool
+do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
+  struct gl_renderbuffer *rb, unsigned buf,
+  bool partial_clear, bool encode_srgb, unsigned layer)
+{
+   struct gl_context *ctx = &brw->ctx;
+   struct intel_renderbuffer *irb = intel_renderbuffer(rb);
+   mesa_format format = irb->mt->format;
+   uint32_t x0, x1, y0, y1;
+
+   if (!encode_srgb && _mesa_get_format_color_encoding(format) == GL_SRGB)
+  format = _mesa_get_srgb_format_linear(format);
+
+   x0 = fb->_Xmin;
+   x1 = fb->_Xmax;
+   if (rb->Name != 0) {
+  y0 = fb->_Ymin;
+  y1 = fb->_Ymax;
+   } else {
+ 

[Mesa-dev] [PATCH v2 06/35] i965/blorp: Remove compute_tile_offsets

[Jason Ekstrand]

We have a handy little function is ISL that does exactly the same thing.

Reviewed-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 34 +-
 src/mesa/drivers/dri/i965/brw_blorp.h |  5 -
 2 files changed, 5 insertions(+), 34 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 5889e95..220be83 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -120,34 +120,6 @@ brw_blorp_surface_info_init(struct brw_context *brw,
 }
 
 
-/**
- * Split x_offset and y_offset into a base offset (in bytes) and a remaining
- * x/y offset (in pixels).  Note: we can't do this by calling
- * intel_renderbuffer_tile_offsets(), because the offsets may have been
- * adjusted to account for Y vs. W tiling differences.  So we compute it
- * directly from the adjusted offsets.
- */
-uint32_t
-brw_blorp_compute_tile_offsets(const struct brw_blorp_surface_info *info,
-   uint32_t *tile_x, uint32_t *tile_y)
-{
-   uint32_t mask_x, mask_y;
-   uint32_t tiling = info->mt->tiling;
-   if (info->map_stencil_as_y_tiled)
-  tiling = I915_TILING_Y;
-
-   intel_get_tile_masks(tiling, info->mt->tr_mode, info->mt->cpp,
-&mask_x, &mask_y);
-
-   *tile_x = info->x_offset & mask_x;
-   *tile_y = info->y_offset & mask_y;
-
-   return intel_miptree_get_aligned_offset(info->mt, info->x_offset & ~mask_x,
-   info->y_offset & ~mask_y,
-   info->map_stencil_as_y_tiled);
-}
-
-
 void
 brw_blorp_params_init(struct brw_blorp_params *params)
 {
@@ -354,7 +326,11 @@ brw_blorp_emit_surface_state(struct brw_context *brw,
};
 
uint32_t offset, tile_x, tile_y;
-   offset = brw_blorp_compute_tile_offsets(surface, &tile_x, &tile_y);
+   isl_tiling_get_intratile_offset_el(&brw->isl_dev, surf.tiling,
+  isl_format_get_layout(view.format)->bpb 
/ 8,
+  surf.row_pitch,
+  surface->x_offset, surface->y_offset,
+  &offset, &tile_x, &tile_y);
 
uint32_t surf_offset;
uint32_t *dw = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index e23f48b..0694181 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -172,11 +172,6 @@ brw_blorp_surface_info_init(struct brw_context *brw,
 unsigned int level, unsigned int layer,
 mesa_format format, bool is_render_target);
 
-uint32_t
-brw_blorp_compute_tile_offsets(const struct brw_blorp_surface_info *info,
-   uint32_t *tile_x, uint32_t *tile_y);
-
-
 
 struct brw_blorp_coord_transform
 {
-- 
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[Mesa-dev] [PATCH v2 26/35] i965/blorp: Rework hiz rect alignment calculations

[Jason Ekstrand]

At the moment, the minify operation does nothing because
params.depth.view.base_level is always zero.  However, as soon as we start
using actual base miplevels and array slices, we are going to need the
minification.  Also, we only need to align the surface dimensions in the
case where we are operating on miplevel 0.  Previously, it didn't matter
because it aligned on miplevel 0 and, for all other miplevels, the miptree
code guaranteed that the level was already aligned.
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 23 +++
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 2cf0f99..bc26e41 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -593,14 +593,21 @@ gen6_blorp_hiz_exec(struct brw_context *brw, struct 
intel_mipmap_tree *mt,
 * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
 * prevents the clobbering.
 */
-   params.dst.surf.samples = MAX2(mt->num_samples, 1);
-   params.depth.surf.logical_level0_px.width =
-  ALIGN(params.depth.surf.logical_level0_px.width, 8);
-   params.depth.surf.logical_level0_px.height =
-  ALIGN(params.depth.surf.logical_level0_px.height, 4);
-
-   params.x1 = params.depth.surf.logical_level0_px.width;
-   params.y1 = params.depth.surf.logical_level0_px.height;
+   params.x1 = minify(params.depth.surf.logical_level0_px.width,
+  params.depth.view.base_level);
+   params.y1 = minify(params.depth.surf.logical_level0_px.height,
+  params.depth.view.base_level);
+   params.x1 = ALIGN(params.x1, 8);
+   params.y1 = ALIGN(params.y1, 4);
+
+   if (params.depth.view.base_level == 0) {
+  /* TODO: What about MSAA? */
+  params.depth.surf.logical_level0_px.width = params.x1;
+  params.depth.surf.logical_level0_px.height = params.y1;
+   }
+
+   params.dst.surf.samples = params.depth.surf.samples;
+   params.dst.surf.logical_level0_px = params.depth.surf.logical_level0_px;
 
assert(intel_miptree_level_has_hiz(mt, level));
 
-- 
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[Mesa-dev] [PATCH v2 18/35] i965/blorp: Use ISL to compute image offsets

[Jason Ekstrand]

For the moment, we still call the old miptree function; we just assert that
the two are equal.
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 94 +--
 1 file changed, 91 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index ef256a7..c8cb41a 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -32,6 +32,88 @@
 
 #define FILE_DEBUG_FLAG DEBUG_BLORP
 
+/**
+ * A variant of isl_surf_get_image_offset_sa() specific to gen6 stencil and
+ * HiZ surfaces.
+ */
+static void
+get_image_offset_sa_gen6_stencil(const struct isl_surf *surf,
+ uint32_t level, uint32_t logical_array_layer,
+ uint32_t *x_offset_sa,
+ uint32_t *y_offset_sa)
+{
+   assert(surf->tiling == ISL_TILING_W || surf->format == ISL_FORMAT_HIZ);
+   assert(level < surf->levels);
+   assert(logical_array_layer < surf->logical_level0_px.array_len);
+
+   const struct isl_extent3d image_align_sa =
+  isl_surf_get_image_alignment_sa(surf);
+
+   const uint32_t W0 = surf->phys_level0_sa.width;
+   const uint32_t H0 = surf->phys_level0_sa.height;
+
+   uint32_t x = 0, y = 0;
+   for (uint32_t l = 0; l < level; ++l) {
+  if (l == 1) {
+ uint32_t W = minify(W0, l);
+
+ if (surf->samples > 1) {
+assert(surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED);
+assert(surf->samples == 4);
+W = ALIGN(W, 2) * 2;
+ }
+
+ x += ALIGN(W, image_align_sa.w);
+  } else {
+ uint32_t H = minify(H0, l);
+
+ if (surf->samples > 1) {
+assert(surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED);
+assert(surf->samples == 4);
+H = ALIGN(H, 2) * 2;
+ }
+
+ y += ALIGN(H, image_align_sa.h) * surf->logical_level0_px.array_len;
+  }
+   }
+
+   /* Now account for our location within the given LOD */
+   uint32_t Hl = minify(H0, level);
+   if (surf->samples > 1) {
+  assert(surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED);
+  assert(surf->samples == 4);
+  Hl = ALIGN(Hl, 2) * 2;
+   }
+   y += ALIGN(Hl, image_align_sa.h) * logical_array_layer;
+
+   *x_offset_sa = x;
+   *y_offset_sa = y;
+}
+
+static void
+blorp_get_image_offset_sa(struct isl_device *dev, const struct isl_surf *surf,
+  uint32_t level, uint32_t layer,
+  uint32_t *x_offset_sa,
+  uint32_t *y_offset_sa)
+{
+   if (ISL_DEV_GEN(dev) == 6 && surf->tiling == ISL_TILING_W) {
+  get_image_offset_sa_gen6_stencil(surf, level, layer,
+   x_offset_sa, y_offset_sa);
+   } else {
+  /* Using base_array_layer for Z in 3-D surfaces is a bit abusive, but it
+   * will go away soon enough.
+   */
+  uint32_t z = 0;
+  if (surf->dim == ISL_SURF_DIM_3D) {
+ z = layer;
+ layer = 0;
+  }
+
+  isl_surf_get_image_offset_sa(surf, level, layer, z,
+   x_offset_sa, y_offset_sa);
+   }
+}
+
 void
 brw_blorp_surface_info_init(struct brw_context *brw,
 struct brw_blorp_surface_info *info,
@@ -125,10 +207,16 @@ brw_blorp_surface_info_init(struct brw_context *brw,
}
 
uint32_t x_offset, y_offset;
-   intel_miptree_get_image_offset(mt, level, layer, &x_offset, &y_offset);
+   blorp_get_image_offset_sa(&brw->isl_dev, &info->surf,
+ level, layer / layer_multiplier,
+ &x_offset, &y_offset);
+
+   uint32_t mt_x, mt_y;
+   intel_miptree_get_image_offset(mt, level, layer, &mt_x, &mt_y);
+   assert(mt_x == x_offset && mt_y == y_offset);
 
-   uint8_t bs = isl_format_get_layout(info->view.format)->bpb / 8;
-   isl_tiling_get_intratile_offset_el(&brw->isl_dev, info->surf.tiling, bs,
+   isl_tiling_get_intratile_offset_sa(&brw->isl_dev, info->surf.tiling,
+  info->view.format,
   info->surf.row_pitch, x_offset, y_offset,
   &info->bo_offset,
   &info->tile_x_sa, &info->tile_y_sa);
-- 
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[Mesa-dev] [PATCH v2 20/27] i965/blorp: Refactor fast-clear logic a bit

[Jason Ekstrand]

This pulls the mcs allocation into the if statement where we initially
determine that we are doing a fast clear and moves the programming of
wm_inputs and figuring out the fast clear rect into it's own if statement.
The next commit will put code inbetween the two.
---
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 25 +
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 4d3fe58..a66e955 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -166,22 +166,11 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
   params.color_write_disable))
   use_simd16_replicated_data = false;
 
+   bool is_fast_clear = false;
if (irb->mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_NO_MCS &&
!partial_clear && use_simd16_replicated_data &&
brw_is_color_fast_clear_compatible(brw, irb->mt,
   &ctx->Color.ClearColor)) {
-  memset(¶ms.wm_inputs, 0xff, 4*sizeof(float));
-  params.fast_clear_op = GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE;
-
-  brw_get_fast_clear_rect(brw, irb->mt, ¶ms.x0, ¶ms.y0,
-  ¶ms.x1, ¶ms.y1);
-   }
-
-   brw_blorp_params_get_clear_kernel(brw, ¶ms, use_simd16_replicated_data);
-
-   const bool is_fast_clear =
-  params.fast_clear_op == GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE;
-   if (is_fast_clear) {
   /* Record the clear color in the miptree so that it will be
* programmed in SURFACE_STATE by later rendering and resolve
* operations.
@@ -208,8 +197,20 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
 return false;
  }
   }
+
+  is_fast_clear = true;
}
 
+   if (is_fast_clear) {
+  memset(¶ms.wm_inputs, 0xff, 4*sizeof(float));
+  params.fast_clear_op = GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE;
+
+  brw_get_fast_clear_rect(brw, irb->mt, ¶ms.x0, ¶ms.y0,
+  ¶ms.x1, ¶ms.y1);
+   }
+
+   brw_blorp_params_get_clear_kernel(brw, ¶ms, use_simd16_replicated_data);
+
intel_miptree_check_level_layer(irb->mt, irb->mt_level, layer);
intel_miptree_used_for_rendering(irb->mt);
 
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 17/27] i965/blorp: Stop calling brw_meta_get_buffer_rect

[Jason Ekstrand]

We already have an inlined version of the function slightly higher up in
do_single_blorp_clear and all calling it does is stomp the values with the
same thing.  We might as well just get rid of it.
---
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp |  3 ---
 src/mesa/drivers/dri/i965/brw_meta_util.c | 16 
 src/mesa/drivers/dri/i965/brw_meta_util.h |  5 -
 3 files changed, 24 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index d574eac..f67a1a4 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -174,9 +174,6 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
 
   brw_get_fast_clear_rect(brw, fb, irb->mt, ¶ms.x0, ¶ms.y0,
   ¶ms.x1, ¶ms.y1);
-   } else {
-  brw_meta_get_buffer_rect(fb, ¶ms.x0, ¶ms.y0,
-   ¶ms.x1, ¶ms.y1);
}
 
brw_blorp_params_get_clear_kernel(brw, ¶ms, use_simd16_replicated_data);
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c 
b/src/mesa/drivers/dri/i965/brw_meta_util.c
index a81190d..59c9af8 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
@@ -569,22 +569,6 @@ brw_get_fast_clear_rect(const struct brw_context *brw,
 }
 
 void
-brw_meta_get_buffer_rect(const struct gl_framebuffer *fb,
- unsigned *x0, unsigned *y0,
- unsigned *x1, unsigned *y1)
-{
-   *x0 = fb->_Xmin;
-   *x1 = fb->_Xmax;
-   if (fb->Name != 0) {
-  *y0 = fb->_Ymin;
-  *y1 = fb->_Ymax;
-   } else {
-  *y0 = fb->Height - fb->_Ymax;
-  *y1 = fb->Height - fb->_Ymin;
-   }
-}
-
-void
 brw_get_ccs_resolve_rect(const struct isl_device *dev,
  const struct isl_surf *ccs_surf,
  unsigned *x0, unsigned *y0,
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.h 
b/src/mesa/drivers/dri/i965/brw_meta_util.h
index 7d4e5f6..198ffe5 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.h
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.h
@@ -55,11 +55,6 @@ brw_get_ccs_resolve_rect(const struct isl_device *dev,
  unsigned *x0, unsigned *y0,
  unsigned *x1, unsigned *y1);
 
-void
-brw_meta_get_buffer_rect(const struct gl_framebuffer *fb, 
- unsigned *x0, unsigned *y0,
- unsigned *x1, unsigned *y1);
-
 bool
 brw_meta_set_fast_clear_color(struct brw_context *brw,
   struct intel_mipmap_tree *mt,
-- 
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[Mesa-dev] [PATCH v2 22/27] i965/meta_util: Convert get_fast_clear_rect to take an isl_surf

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp |  2 +-
 src/mesa/drivers/dri/i965/brw_meta_util.c | 27 +++
 src/mesa/drivers/dri/i965/brw_meta_util.h |  2 +-
 3 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index cb288de..6cb28d0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -216,7 +216,7 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
   memset(¶ms.wm_inputs, 0xff, 4*sizeof(float));
   params.fast_clear_op = GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE;
 
-  brw_get_fast_clear_rect(brw, irb->mt, ¶ms.x0, ¶ms.y0,
+  brw_get_fast_clear_rect(brw, ¶ms.dst.aux_surf, ¶ms.x0, 
¶ms.y0,
   ¶ms.x1, ¶ms.y1);
}
 
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c 
b/src/mesa/drivers/dri/i965/brw_meta_util.c
index d280375..c3af167 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
@@ -446,7 +446,7 @@ brw_meta_set_fast_clear_color(struct brw_context *brw,
  */
 void
 brw_get_fast_clear_rect(const struct brw_context *brw,
-const struct intel_mipmap_tree* mt,
+const struct isl_surf *aux_surf,
 unsigned *x0, unsigned *y0,
 unsigned *x1, unsigned *y1)
 {
@@ -454,8 +454,7 @@ brw_get_fast_clear_rect(const struct brw_context *brw,
unsigned int x_scaledown, y_scaledown;
 
/* Only single sampled surfaces need to (and actually can) be resolved. */
-   if (mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE ||
-   intel_miptree_is_lossless_compressed(brw, mt)) {
+   if (aux_surf->usage == ISL_SURF_USAGE_CCS_BIT) {
   /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
* Target(s)", beneath the "Fast Color Clear" bullet (p327):
*
@@ -468,10 +467,12 @@ brw_get_fast_clear_rect(const struct brw_context *brw,
* follows the requirement and covers the RT.
*
* The alignment size in the table that follows is related to the
-   * alignment size returned by intel_get_non_msrt_mcs_alignment(), but
-   * with X alignment multiplied by 16 and Y alignment multiplied by 32.
+   * alignment size that is baked into the CCS surface format but with X
+   * alignment multiplied by 16 and Y alignment multiplied by 32.
*/
-  intel_get_non_msrt_mcs_alignment(mt, &x_align, &y_align);
+  x_align = isl_format_get_layout(aux_surf->format)->bw;
+  y_align = isl_format_get_layout(aux_surf->format)->bh;
+
   x_align *= 16;
 
   /* SKL+ line alignment requirement for Y-tiled are half those of the 
prior
@@ -507,6 +508,8 @@ brw_get_fast_clear_rect(const struct brw_context *brw,
   x_align *= 2;
   y_align *= 2;
} else {
+  assert(aux_surf->usage == ISL_SURF_USAGE_MCS_BIT);
+
   /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
* Target(s)", beneath the "MSAA Compression" bullet (p326):
*
@@ -535,19 +538,19 @@ brw_get_fast_clear_rect(const struct brw_context *brw,
* vertically and either 4 or 16 horizontally, and the scaledown
* factor is 2 vertically and either 2 or 8 horizontally.
*/
-  switch (mt->num_samples) {
-  case 2:
-  case 4:
+  switch (aux_surf->format) {
+  case ISL_FORMAT_MCS_2X:
+  case ISL_FORMAT_MCS_4X:
  x_scaledown = 8;
  break;
-  case 8:
+  case ISL_FORMAT_MCS_8X:
  x_scaledown = 2;
  break;
-  case 16:
+  case ISL_FORMAT_MCS_16X:
  x_scaledown = 1;
  break;
   default:
- unreachable("Unexpected sample count for fast clear");
+ unreachable("Unexpected MCS format for fast clear");
   }
   y_scaledown = 2;
   x_align = x_scaledown * 2;
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.h 
b/src/mesa/drivers/dri/i965/brw_meta_util.h
index 35c06a8..8613921 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.h
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.h
@@ -44,7 +44,7 @@ brw_meta_mirror_clip_and_scissor(const struct gl_context *ctx,
 
 void
 brw_get_fast_clear_rect(const struct brw_context *brw,
-const struct intel_mipmap_tree* mt,
+const struct isl_surf *aux_surf,
 unsigned *x0, unsigned *y0,
 unsigned *x1, unsigned *y1);
 
-- 
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[Mesa-dev] [PATCH v2 16/27] i965/blorp: Pull the guts of resolve_color into a miptree-agnostic helper

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 43 ---
 1 file changed, 25 insertions(+), 18 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index d242f24..d574eac 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -304,33 +304,21 @@ brw_blorp_clear_color(struct brw_context *brw, struct 
gl_framebuffer *fb,
return true;
 }
 
-void
-brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt)
+static void
+brw_blorp_ccs_resolve(struct brw_context *brw, struct brw_blorp_surf *surf,
+  enum isl_format format)
 {
-   DBG("%s to mt %p\n", __FUNCTION__, mt);
-
-   const mesa_format format = _mesa_get_srgb_format_linear(mt->format);
-
-   intel_miptree_check_level_layer(mt, 0 /* level */, 0 /* layer */);
-   intel_miptree_used_for_rendering(mt);
-
struct brw_blorp_params params;
brw_blorp_params_init(¶ms);
 
-   struct isl_surf isl_tmp[2];
-   struct brw_blorp_surf surf;
-   unsigned level = 0;
-   brw_blorp_surf_for_miptree(brw, &surf, mt, &level, isl_tmp);
-   brw_blorp_surface_info_init(brw, ¶ms.dst, &surf,
-   0 /* level */, 0 /* layer */,
-   brw_blorp_to_isl_format(brw, format, true),
-   true);
+   brw_blorp_surface_info_init(brw, ¶ms.dst, surf,
+   0 /* level */, 0 /* layer */, format, true);
 
brw_get_ccs_resolve_rect(&brw->isl_dev, ¶ms.dst.aux_surf,
 ¶ms.x0, ¶ms.y0,
 ¶ms.x1, ¶ms.y1);
 
-   if (intel_miptree_is_lossless_compressed(brw, mt))
+   if (params.dst.aux_usage == ISL_AUX_USAGE_CCS_E)
   params.resolve_type = GEN9_PS_RENDER_TARGET_RESOLVE_FULL;
else
   params.resolve_type = GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE;
@@ -344,6 +332,25 @@ brw_blorp_resolve_color(struct brw_context *brw, struct 
intel_mipmap_tree *mt)
brw_blorp_params_get_clear_kernel(brw, ¶ms, true);
 
brw_blorp_exec(brw, ¶ms);
+}
+
+void
+brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt)
+{
+   DBG("%s to mt %p\n", __FUNCTION__, mt);
+
+   const mesa_format format = _mesa_get_srgb_format_linear(mt->format);
+
+   intel_miptree_check_level_layer(mt, 0 /* level */, 0 /* layer */);
+   intel_miptree_used_for_rendering(mt);
+
+   struct isl_surf isl_tmp[2];
+   struct brw_blorp_surf surf;
+   unsigned level = 0;
+   brw_blorp_surf_for_miptree(brw, &surf, mt, &level, isl_tmp);
+
+   brw_blorp_ccs_resolve(brw, &surf, brw_blorp_to_isl_format(brw, format, 
true));
+
mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
 }
 
-- 
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[Mesa-dev] [PATCH v2 24/27] i965/blorp: Factor the guts of blorp_hiz_exec into a helper

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_blorp.c | 43 ---
 1 file changed, 25 insertions(+), 18 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 64bbf4c..c862dfd 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -548,24 +548,17 @@ retry:
brw_emit_mi_flush(brw);
 }
 
-void
-gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
-unsigned int level, unsigned int layer, enum gen6_hiz_op 
op)
+static void
+blorp_gen6_hiz_op(struct brw_context *brw, struct brw_blorp_surf *surf,
+  unsigned level, unsigned layer, enum gen6_hiz_op op)
 {
struct brw_blorp_params params;
brw_blorp_params_init(¶ms);
 
params.hiz_op = op;
 
-   intel_miptree_check_level_layer(mt, level, layer);
-   intel_miptree_used_for_rendering(mt);
-
-   struct isl_surf isl_tmp[2];
-   struct brw_blorp_surf surf;
-   brw_blorp_surf_for_miptree(brw, &surf, mt, &level, isl_tmp);
-   brw_blorp_surface_info_init(brw, ¶ms.depth, &surf, level, layer,
-   brw_blorp_to_isl_format(brw, mt->format, true),
-   true);
+   brw_blorp_surface_info_init(brw, ¶ms.depth, surf, level, layer,
+   surf->surf->format, true);
 
/* Align the rectangle primitive to 8x4 pixels.
 *
@@ -608,16 +601,14 @@ gen6_blorp_hiz_exec(struct brw_context *brw, struct 
intel_mipmap_tree *mt,
params.dst.surf.samples = params.depth.surf.samples;
params.dst.surf.logical_level0_px = params.depth.surf.logical_level0_px;
 
-   assert(intel_miptree_level_has_hiz(mt, level));
-
-   switch (mt->format) {
-   case MESA_FORMAT_Z_UNORM16:
+   switch (surf->surf->format) {
+   case ISL_FORMAT_R16_UNORM:
   params.depth_format = BRW_DEPTHFORMAT_D16_UNORM;
   break;
-   case MESA_FORMAT_Z_FLOAT32:
+   case ISL_FORMAT_R32_FLOAT:
   params.depth_format = BRW_DEPTHFORMAT_D32_FLOAT;
   break;
-   case MESA_FORMAT_Z24_UNORM_X8_UINT:
+   case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
   params.depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
   break;
default:
@@ -626,3 +617,19 @@ gen6_blorp_hiz_exec(struct brw_context *brw, struct 
intel_mipmap_tree *mt,
 
brw_blorp_exec(brw, ¶ms);
 }
+
+void
+gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
+unsigned int level, unsigned int layer, enum gen6_hiz_op 
op)
+{
+   intel_miptree_check_level_layer(mt, level, layer);
+   intel_miptree_used_for_rendering(mt);
+
+   assert(intel_miptree_level_has_hiz(mt, level));
+
+   struct isl_surf isl_tmp[2];
+   struct brw_blorp_surf surf;
+   brw_blorp_surf_for_miptree(brw, &surf, mt, &level, isl_tmp);
+
+   blorp_gen6_hiz_op(brw, &surf, level, layer, op);
+}
-- 
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[Mesa-dev] [PATCH v2 13/27] i965/blorp: Add a new brw_blorp_surf intermediate struct

[Jason Ekstrand]

At the moment, this seems to make all of the interfaces messier rather than
clener.  However, it does provide a representation of a surface that
simultaneously contains everything and is completely unaware of miptrees.
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 205 +++---
 src/mesa/drivers/dri/i965/brw_blorp.h |  29 +++-
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp  |  20 ++-
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp |  25 +++-
 4 files changed, 182 insertions(+), 97 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 094299f..64bbf4c 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -64,31 +64,16 @@ apply_gen6_stencil_hiz_offset(struct isl_surf *surf,
 }
 
 void
-brw_blorp_surface_info_init(struct brw_context *brw,
-struct brw_blorp_surface_info *info,
-struct intel_mipmap_tree *mt,
-unsigned int level, unsigned int layer,
-mesa_format format, bool is_render_target)
+brw_blorp_surf_for_miptree(struct brw_context *brw,
+   struct brw_blorp_surf *surf,
+   struct intel_mipmap_tree *mt,
+   unsigned *level,
+   struct isl_surf tmp_surfs[2])
 {
-   /* Layer is a physical layer, so if this is a 2D multisample array texture
-* using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it had better
-* be a multiple of num_samples.
-*/
-   unsigned layer_multiplier = 1;
-   if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
-   mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
-  assert(mt->num_samples <= 1 || layer % mt->num_samples == 0);
-  layer_multiplier = MAX2(mt->num_samples, 1);
-   }
-
-   intel_miptree_check_level_layer(mt, level, layer);
-
-   if (is_render_target)
-  intel_miptree_used_for_rendering(mt);
-
-   intel_miptree_get_isl_surf(brw, mt, &info->surf);
-   info->bo = mt->bo;
-   info->offset = mt->offset;
+   intel_miptree_get_isl_surf(brw, mt, &tmp_surfs[0]);
+   surf->surf = &tmp_surfs[0];
+   surf->bo = mt->bo;
+   surf->offset = mt->offset;
 
if (brw->gen == 6 && mt->format == MESA_FORMAT_S_UINT8 &&
mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
@@ -103,53 +88,132 @@ brw_blorp_surface_info_init(struct brw_context *brw,
* See also gen6_depth_stencil_state.c
*/
   uint32_t offset;
-  apply_gen6_stencil_hiz_offset(&info->surf, mt, level, &offset);
-  info->offset += offset;
-  level = 0;
+  apply_gen6_stencil_hiz_offset(&tmp_surfs[0], mt, *level, &offset);
+  surf->offset += offset;
+  *level = 0;
}
 
-   intel_miptree_get_aux_isl_surf(brw, mt, &info->aux_surf,
-  &info->aux_usage);
-   if (info->aux_usage != ISL_AUX_USAGE_NONE) {
+   struct isl_surf *aux_surf = &tmp_surfs[1];
+   intel_miptree_get_aux_isl_surf(brw, mt, aux_surf, &surf->aux_usage);
+   if (surf->aux_usage != ISL_AUX_USAGE_NONE) {
   /* We only really need a clear color if we also have an auxiliary
* surface.  Without one, it does nothing.
*/
-  info->clear_color = intel_miptree_get_isl_clear_color(brw, mt);
+  surf->clear_color = intel_miptree_get_isl_clear_color(brw, mt);
 
+  surf->aux_surf = aux_surf;
   if (mt->mcs_mt) {
- info->aux_bo = mt->mcs_mt->bo;
- info->aux_offset = mt->mcs_mt->offset;
+ surf->aux_bo = mt->mcs_mt->bo;
+ surf->aux_offset = mt->mcs_mt->offset;
   } else {
- assert(info->aux_usage == ISL_AUX_USAGE_HIZ);
+ assert(surf->aux_usage == ISL_AUX_USAGE_HIZ);
  struct intel_mipmap_tree *hiz_mt = mt->hiz_buf->mt;
  if (hiz_mt) {
-info->aux_bo = hiz_mt->bo;
+surf->aux_bo = hiz_mt->bo;
 if (hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
/* gen6 requires the HiZ buffer to be manually offset to the
 * right location.  We could fixup the surf but it doesn't
 * matter since most of those fields don't matter.
 */
-   apply_gen6_stencil_hiz_offset(&info->aux_surf, hiz_mt, level,
- &info->aux_offset);
+   apply_gen6_stencil_hiz_offset(aux_surf, hiz_mt, *level,
+ &surf->aux_offset);
 } else {
-   info->aux_offset = 0;
+   surf->aux_offset = 0;
 }
-assert(hiz_mt->pitch == info->aux_surf.row_pitch);
+assert(hiz_mt->pitch == aux_surf->row_pitch);
  } else {
-info->aux_bo = mt->hiz_buf->bo;
-info->aux_offset = 0;
+surf->aux_bo = mt->hiz_buf->bo;
+surf->aux_offset = 0;
  }
   }
} else {
-  info->aux_bo = 

[Mesa-dev] [PATCH v2 21/27] i965/blorp/clear: Move isl_surf setup higher in the function

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index a66e955..cb288de 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -201,16 +201,6 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
   is_fast_clear = true;
}
 
-   if (is_fast_clear) {
-  memset(¶ms.wm_inputs, 0xff, 4*sizeof(float));
-  params.fast_clear_op = GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE;
-
-  brw_get_fast_clear_rect(brw, irb->mt, ¶ms.x0, ¶ms.y0,
-  ¶ms.x1, ¶ms.y1);
-   }
-
-   brw_blorp_params_get_clear_kernel(brw, ¶ms, use_simd16_replicated_data);
-
intel_miptree_check_level_layer(irb->mt, irb->mt_level, layer);
intel_miptree_used_for_rendering(irb->mt);
 
@@ -222,6 +212,16 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
brw_blorp_to_isl_format(brw, format, true),
true);
 
+   if (is_fast_clear) {
+  memset(¶ms.wm_inputs, 0xff, 4*sizeof(float));
+  params.fast_clear_op = GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE;
+
+  brw_get_fast_clear_rect(brw, irb->mt, ¶ms.x0, ¶ms.y0,
+  ¶ms.x1, ¶ms.y1);
+   }
+
+   brw_blorp_params_get_clear_kernel(brw, ¶ms, use_simd16_replicated_data);
+
const char *clear_type;
if (is_fast_clear)
   clear_type = "fast";
-- 
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[Mesa-dev] [PATCH v2 08/27] i965/blorp: Stop using the miptree in state setup for tex/rt surfaces

[Jason Ekstrand]

Instead, we add a bo and offset field to brw_blorp_surface_info and use
those in the backend.
---
 src/mesa/drivers/dri/i965/brw_blorp.c| 10 +---
 src/mesa/drivers/dri/i965/brw_blorp.h|  3 ++-
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp |  4 +++-
 src/mesa/drivers/dri/i965/gen6_blorp.c   | 33 +++---
 src/mesa/drivers/dri/i965/gen7_blorp.c   | 35 
 src/mesa/drivers/dri/i965/gen8_blorp.c   | 10 
 6 files changed, 45 insertions(+), 50 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 87d8929..cf1615f 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -126,8 +126,12 @@ brw_blorp_surface_info_init(struct brw_context *brw,
intel_miptree_check_level_layer(mt, level, layer);
 
info->mt = mt;
+   if (is_render_target)
+  intel_miptree_used_for_rendering(mt);
 
intel_miptree_get_isl_surf(brw, mt, &info->surf);
+   info->bo = mt->bo;
+   info->offset = mt->offset;
 
if (mt->mcs_mt) {
   intel_miptree_get_aux_isl_surf(brw, mt, &info->aux_surf,
@@ -360,7 +364,7 @@ brw_blorp_emit_surface_state(struct brw_context *brw,
const uint32_t mocs = is_render_target ? ss_info.rb_mocs : ss_info.tex_mocs;
 
isl_surf_fill_state(&brw->isl_dev, dw, .surf = &surf, .view = 
&surface->view,
-   .address = surface->mt->bo->offset64 + 
surface->bo_offset,
+   .address = surface->bo->offset64 + surface->offset,
.aux_surf = aux_surf, .aux_usage = surface->aux_usage,
.aux_address = aux_offset,
.mocs = mocs, .clear_color = clear_color,
@@ -370,8 +374,8 @@ brw_blorp_emit_surface_state(struct brw_context *brw,
/* Emit relocation to surface contents */
drm_intel_bo_emit_reloc(brw->batch.bo,
surf_offset + ss_info.reloc_dw * 4,
-   surface->mt->bo,
-   dw[ss_info.reloc_dw] - surface->mt->bo->offset64,
+   surface->bo,
+   dw[ss_info.reloc_dw] - surface->bo->offset64,
read_domains, write_domain);
 
if (aux_surf) {
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 076d26d..98a9436 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -72,6 +72,8 @@ struct brw_blorp_surface_info
struct intel_mipmap_tree *mt;
 
struct isl_surf surf;
+   drm_intel_bo *bo;
+   uint32_t offset;
 
struct isl_surf aux_surf;
enum isl_aux_usage aux_usage;
@@ -81,7 +83,6 @@ struct brw_blorp_surface_info
/* Z offset into a 3-D texture or slice of a 2-D array texture. */
uint32_t z_offset;
 
-   uint32_t bo_offset;
uint32_t tile_x_sa, tile_y_sa;
 };
 
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index ed68734..ee34a70 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1604,11 +1604,13 @@ surf_convert_to_single_slice(struct brw_context *brw,
  info->view.base_array_layer,
  &x_offset_sa, &y_offset_sa);
 
+   uint32_t byte_offset;
isl_tiling_get_intratile_offset_sa(&brw->isl_dev, info->surf.tiling,
   info->view.format, info->surf.row_pitch,
   x_offset_sa, y_offset_sa,
-  &info->bo_offset,
+  &byte_offset,
   &info->tile_x_sa, &info->tile_y_sa);
+   info->offset += byte_offset;
 
/* TODO: Once this file gets converted to C, we shouls just use designated
 * initializers.
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c 
b/src/mesa/drivers/dri/i965/gen6_blorp.c
index 9e08374..6f3073b 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.c
@@ -634,7 +634,7 @@ gen6_blorp_emit_wm_config(struct brw_context *brw,
  dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
}
 
-   if (params->src.mt) {
+   if (params->src.bo) {
   dw5 |= GEN6_WM_KILL_ENABLE; /* TODO: temporarily smash on */
   dw2 |= 1 << GEN6_WM_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
}
@@ -700,20 +700,16 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context 
*brw,
  const struct brw_blorp_params *params)
 {
uint32_t surftype;
-   GLenum gl_target = params->depth.mt->target;
-
-   switch (gl_target) {
-   case GL_TEXTURE_CUBE_MAP_ARRAY:
-   case GL_TEXTURE_CUBE_MAP:
-  /* The PRM claims that we should use BRW_SURFACE_CUBE for this
-   * situation, but experiments show that gl_Layer doesn't work when we do
-   * this.  So we use BRW_SURFA

[Mesa-dev] [PATCH v2 27/27] i965/blorp: brw_blorp_clear.cpp -> blorp_clear.c

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/Makefile.sources|   2 +-
 src/mesa/drivers/dri/i965/blorp_clear.c   | 190 +
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 194 --
 3 files changed, 191 insertions(+), 195 deletions(-)
 create mode 100644 src/mesa/drivers/dri/i965/blorp_clear.c
 delete mode 100644 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index b4362ce..02705a1 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -98,11 +98,11 @@ i965_FILES = \
blorp.c \
blorp.h \
blorp_blit.c \
+   blorp_clear.c \
blorp_priv.h \
brw_binding_tables.c \
brw_blorp.c \
brw_blorp.h \
-   brw_blorp_clear.cpp \
brw_cc.c \
brw_clear.c \
brw_clip.c \
diff --git a/src/mesa/drivers/dri/i965/blorp_clear.c 
b/src/mesa/drivers/dri/i965/blorp_clear.c
new file mode 100644
index 000..4603caa
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/blorp_clear.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "blorp_priv.h"
+#include "brw_meta_util.h"
+#include "brw_context.h"
+#include "brw_state.h"
+
+#include "nir_builder.h"
+
+#define FILE_DEBUG_FLAG DEBUG_BLORP
+
+struct brw_blorp_const_color_prog_key
+{
+   bool use_simd16_replicated_data;
+   bool pad[3];
+};
+
+static void
+brw_blorp_params_get_clear_kernel(struct brw_context *brw,
+  struct brw_blorp_params *params,
+  bool use_replicated_data)
+{
+   struct brw_blorp_const_color_prog_key blorp_key;
+   memset(&blorp_key, 0, sizeof(blorp_key));
+   blorp_key.use_simd16_replicated_data = use_replicated_data;
+
+   if (brw_search_cache(&brw->cache, BRW_CACHE_BLORP_PROG,
+&blorp_key, sizeof(blorp_key),
+¶ms->wm_prog_kernel, ¶ms->wm_prog_data))
+  return;
+
+   void *mem_ctx = ralloc_context(NULL);
+
+   nir_builder b;
+   nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
+   b.shader->info.name = ralloc_strdup(b.shader, "BLORP-clear");
+
+   nir_variable *v_color = nir_variable_create(b.shader, nir_var_shader_in,
+   glsl_vec4_type(), "v_color");
+   v_color->data.location = VARYING_SLOT_VAR0;
+   v_color->data.interpolation = INTERP_MODE_FLAT;
+
+   nir_variable *frag_color = nir_variable_create(b.shader, nir_var_shader_out,
+  glsl_vec4_type(),
+  "gl_FragColor");
+   frag_color->data.location = FRAG_RESULT_COLOR;
+
+   nir_copy_var(&b, frag_color, v_color);
+
+   struct brw_wm_prog_key wm_key;
+   brw_blorp_init_wm_prog_key(&wm_key);
+
+   struct brw_blorp_prog_data prog_data;
+   unsigned program_size;
+   const unsigned *program =
+  brw_blorp_compile_nir_shader(brw, b.shader, &wm_key, use_replicated_data,
+   &prog_data, &program_size);
+
+   brw_upload_cache(&brw->cache, BRW_CACHE_BLORP_PROG,
+&blorp_key, sizeof(blorp_key),
+program, program_size,
+&prog_data, sizeof(prog_data),
+¶ms->wm_prog_kernel, ¶ms->wm_prog_data);
+
+   ralloc_free(mem_ctx);
+}
+
+void
+blorp_fast_clear(struct brw_context *brw, const struct brw_blorp_surf *surf,
+ uint32_t level, uint32_t layer,
+ uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1)
+{
+   struct brw_blorp_params params;
+   brw_blorp_params_init(¶ms);
+
+   params.x0 = x0;
+   params.y0 = y0;
+   params.x1 = x1;
+   params.y1 = y1;
+
+   memset(¶ms.wm_inputs, 0xff, 4*sizeof(float));
+   params.

[Mesa-dev] [PATCH v2 11/27] i965/blorp: Do gen6 stencil offsets up-front

[Jason Ekstrand]

This keeps all of the nastyness of gen6 stencil on the i965 side of the API
line and lets us delete that nasty hand-rolled ISL-based offset path that
we were using for ALL_SLICES_AT_EACH_LOD.
---
 src/mesa/drivers/dri/i965/brw_blorp.c| 108 ---
 src/mesa/drivers/dri/i965/brw_blorp.h|   6 --
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp |   6 +-
 3 files changed, 34 insertions(+), 86 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 47801f0..094299f 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -32,79 +32,6 @@
 
 #define FILE_DEBUG_FLAG DEBUG_BLORP
 
-/**
- * A variant of isl_surf_get_image_offset_sa() specific to gen6 stencil and
- * HiZ surfaces.
- */
-static void
-get_image_offset_sa_gen6_stencil(const struct isl_surf *surf,
- uint32_t level, uint32_t logical_array_layer,
- uint32_t *x_offset_sa,
- uint32_t *y_offset_sa)
-{
-   assert(surf->tiling == ISL_TILING_W || surf->format == ISL_FORMAT_HIZ);
-   assert(level < surf->levels);
-   assert(logical_array_layer < surf->logical_level0_px.array_len);
-
-   const struct isl_extent3d image_align_sa =
-  isl_surf_get_image_alignment_sa(surf);
-
-   const uint32_t W0 = surf->phys_level0_sa.width;
-   const uint32_t H0 = surf->phys_level0_sa.height;
-
-   uint32_t x = 0, y = 0;
-   for (uint32_t l = 0; l < level; ++l) {
-  if (l == 1) {
- uint32_t W = minify(W0, l);
-
- if (surf->samples > 1) {
-assert(surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED);
-assert(surf->samples == 4);
-W = ALIGN(W, 2) * 2;
- }
-
- x += ALIGN(W, image_align_sa.w);
-  } else {
- uint32_t H = minify(H0, l);
-
- if (surf->samples > 1) {
-assert(surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED);
-assert(surf->samples == 4);
-H = ALIGN(H, 2) * 2;
- }
-
- y += ALIGN(H, image_align_sa.h) * surf->logical_level0_px.array_len;
-  }
-   }
-
-   /* Now account for our location within the given LOD */
-   uint32_t Hl = minify(H0, level);
-   if (surf->samples > 1) {
-  assert(surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED);
-  assert(surf->samples == 4);
-  Hl = ALIGN(Hl, 2) * 2;
-   }
-   y += ALIGN(Hl, image_align_sa.h) * logical_array_layer;
-
-   *x_offset_sa = x;
-   *y_offset_sa = y;
-}
-
-void
-blorp_get_image_offset_sa(struct isl_device *dev, const struct isl_surf *surf,
-  uint32_t level, uint32_t layer,
-  uint32_t *x_offset_sa,
-  uint32_t *y_offset_sa)
-{
-   if (ISL_DEV_GEN(dev) == 6 && surf->tiling == ISL_TILING_W) {
-  get_image_offset_sa_gen6_stencil(surf, level, layer,
-   x_offset_sa, y_offset_sa);
-   } else {
-  isl_surf_get_image_offset_sa(surf, level, layer, 0,
-   x_offset_sa, y_offset_sa);
-   }
-}
-
 static void
 apply_gen6_stencil_hiz_offset(struct isl_surf *surf,
   struct intel_mipmap_tree *mt,
@@ -113,10 +40,19 @@ apply_gen6_stencil_hiz_offset(struct isl_surf *surf,
 {
assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD);
 
-   *offset = intel_miptree_get_aligned_offset(mt,
-  mt->level[lod].level_x,
-  mt->level[lod].level_y,
-  false);
+   if (mt->format == MESA_FORMAT_S_UINT8) {
+  /* Note: we can't compute the stencil offset using
+   * intel_miptree_get_aligned_offset(), because the miptree
+   * claims that the region is untiled even though it's W tiled.
+   */
+  *offset = mt->level[lod].level_y * mt->pitch +
+mt->level[lod].level_x * 64;
+   } else {
+  *offset = intel_miptree_get_aligned_offset(mt,
+ mt->level[lod].level_x,
+ mt->level[lod].level_y,
+ false);
+   }
 
surf->logical_level0_px.width = minify(surf->logical_level0_px.width, lod);
surf->logical_level0_px.height = minify(surf->logical_level0_px.height, 
lod);
@@ -154,6 +90,24 @@ brw_blorp_surface_info_init(struct brw_context *brw,
info->bo = mt->bo;
info->offset = mt->offset;
 
+   if (brw->gen == 6 && mt->format == MESA_FORMAT_S_UINT8 &&
+   mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
+  /* Sandy bridge stencil and HiZ use this ALL_SLICES_AT_EACH_LOD hack in
+   * order to allow for layered rendering.  The hack makes each LOD of the
+   * stencil or HiZ buffer a single tightly packed array surface at some
+   * offset into the surface.  Since ISL doesn't know how to d

[Mesa-dev] [PATCH v2 18/27] i965/meta_util: Only modify the input parameters in get_fast_clear_rect

[Jason Ekstrand]

We had another inline copy of brw_meta_get_buffer_rect embedded in
get_fast_clear_rect for no good reason.  This lets us get rid of the
gl_frameuffer parameter to get_fast_clear_rect.
---
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp |  2 +-
 src/mesa/drivers/dri/i965/brw_meta_util.c | 14 +++---
 src/mesa/drivers/dri/i965/brw_meta_util.h |  1 -
 3 files changed, 4 insertions(+), 13 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index f67a1a4..daab5db 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -172,7 +172,7 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
   memset(¶ms.wm_inputs, 0xff, 4*sizeof(float));
   params.fast_clear_op = GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE;
 
-  brw_get_fast_clear_rect(brw, fb, irb->mt, ¶ms.x0, ¶ms.y0,
+  brw_get_fast_clear_rect(brw, irb->mt, ¶ms.x0, ¶ms.y0,
   ¶ms.x1, ¶ms.y1);
}
 
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c 
b/src/mesa/drivers/dri/i965/brw_meta_util.c
index 59c9af8..d280375 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
@@ -441,9 +441,11 @@ brw_meta_set_fast_clear_color(struct brw_context *brw,
return updated;
 }
 
+/* The x0, y0, x1, and y1 parameters must already be populated with the render
+ * area of the framebuffer to be cleared.
+ */
 void
 brw_get_fast_clear_rect(const struct brw_context *brw,
-const struct gl_framebuffer *fb,
 const struct intel_mipmap_tree* mt,
 unsigned *x0, unsigned *y0,
 unsigned *x1, unsigned *y1)
@@ -552,16 +554,6 @@ brw_get_fast_clear_rect(const struct brw_context *brw,
   y_align = y_scaledown * 2;
}
 
-   *x0 = fb->_Xmin;
-   *x1 = fb->_Xmax;
-   if (fb->Name != 0) {
-  *y0 = fb->_Ymin;
-  *y1 = fb->_Ymax;
-   } else {
-  *y0 = fb->Height - fb->_Ymax;
-  *y1 = fb->Height - fb->_Ymin;
-   }
-
*x0 = ROUND_DOWN_TO(*x0,  x_align) / x_scaledown;
*y0 = ROUND_DOWN_TO(*y0, y_align) / y_scaledown;
*x1 = ALIGN(*x1, x_align) / x_scaledown;
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.h 
b/src/mesa/drivers/dri/i965/brw_meta_util.h
index 198ffe5..35c06a8 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.h
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.h
@@ -44,7 +44,6 @@ brw_meta_mirror_clip_and_scissor(const struct gl_context *ctx,
 
 void
 brw_get_fast_clear_rect(const struct brw_context *brw,
-const struct gl_framebuffer *fb,
 const struct intel_mipmap_tree* mt,
 unsigned *x0, unsigned *y0,
 unsigned *x1, unsigned *y1);
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 15/27] i965/meta_util: Convert get_resolve_rect to use ISL

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp |  5 ++--
 src/mesa/drivers/dri/i965/brw_meta_util.c | 43 +--
 src/mesa/drivers/dri/i965/brw_meta_util.h |  8 ++---
 3 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index e2b1d5a..d242f24 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -326,8 +326,9 @@ brw_blorp_resolve_color(struct brw_context *brw, struct 
intel_mipmap_tree *mt)
brw_blorp_to_isl_format(brw, format, true),
true);
 
-   brw_get_resolve_rect(brw, mt, ¶ms.x0, ¶ms.y0,
-¶ms.x1, ¶ms.y1);
+   brw_get_ccs_resolve_rect(&brw->isl_dev, ¶ms.dst.aux_surf,
+¶ms.x0, ¶ms.y0,
+¶ms.x1, ¶ms.y1);
 
if (intel_miptree_is_lossless_compressed(brw, mt))
   params.resolve_type = GEN9_PS_RENDER_TARGET_RESOLVE_FULL;
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c 
b/src/mesa/drivers/dri/i965/brw_meta_util.c
index 77c6b83..a81190d 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
@@ -585,12 +585,11 @@ brw_meta_get_buffer_rect(const struct gl_framebuffer *fb,
 }
 
 void
-brw_get_resolve_rect(const struct brw_context *brw,
- const struct intel_mipmap_tree *mt,
- unsigned *x0, unsigned *y0,
- unsigned *x1, unsigned *y1)
+brw_get_ccs_resolve_rect(const struct isl_device *dev,
+ const struct isl_surf *ccs_surf,
+ unsigned *x0, unsigned *y0,
+ unsigned *x1, unsigned *y1)
 {
-   unsigned x_align, y_align;
unsigned x_scaledown, y_scaledown;
 
/* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
@@ -598,25 +597,25 @@ brw_get_resolve_rect(const struct brw_context *brw,
 * A rectangle primitive must be scaled down by the following factors
 * with respect to render target being resolved.
 *
-* The scaledown factors in the table that follows are related to the
-* alignment size returned by intel_get_non_msrt_mcs_alignment() by a
-* multiplier. For IVB and HSW, we divide by two, for BDW we multiply
-* by 8 and 16. Similar to the fast clear, SKL eases the BDW vertical 
scaling
-* by a factor of 2.
+* The scaledown factors in the table that follows are related to the block
+* size of the CCS format.  For IVB and HSW, we divide by two, for BDW we
+* multiply by 8 and 16. On Sky Lake, we multiply by 8.
 */
-
-   intel_get_non_msrt_mcs_alignment(mt, &x_align, &y_align);
-   if (brw->gen >= 9) {
-  x_scaledown = x_align * 8;
-  y_scaledown = y_align * 8;
-   } else if (brw->gen >= 8) {
-  x_scaledown = x_align * 8;
-  y_scaledown = y_align * 16;
+   const struct isl_format_layout *fmtl =
+  isl_format_get_layout(ccs_surf->format);
+   assert(fmtl->txc == ISL_TXC_CCS);
+
+   if (ISL_DEV_GEN(dev) >= 9) {
+  x_scaledown = fmtl->bw * 8;
+  y_scaledown = fmtl->bh * 8;
+   } else if (ISL_DEV_GEN(dev) >= 8) {
+  x_scaledown = fmtl->bw * 8;
+  y_scaledown = fmtl->bh * 16;
} else {
-  x_scaledown = x_align / 2;
-  y_scaledown = y_align / 2;
+  x_scaledown = fmtl->bw / 2;
+  y_scaledown = fmtl->bh / 2;
}
*x0 = *y0 = 0;
-   *x1 = ALIGN(mt->logical_width0, x_scaledown) / x_scaledown;
-   *y1 = ALIGN(mt->logical_height0, y_scaledown) / y_scaledown;
+   *x1 = ALIGN(ccs_surf->logical_level0_px.width, x_scaledown) / x_scaledown;
+   *y1 = ALIGN(ccs_surf->logical_level0_px.height, y_scaledown) / y_scaledown;
 }
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.h 
b/src/mesa/drivers/dri/i965/brw_meta_util.h
index 0929497..7d4e5f6 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.h
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.h
@@ -50,10 +50,10 @@ brw_get_fast_clear_rect(const struct brw_context *brw,
 unsigned *x1, unsigned *y1);
 
 void
-brw_get_resolve_rect(const struct brw_context *brw,
- const struct intel_mipmap_tree *mt,
- unsigned *x0, unsigned *y0,
- unsigned *x1, unsigned *y1);
+brw_get_ccs_resolve_rect(const struct isl_device *dev,
+ const struct isl_surf *ccs_surf,
+ unsigned *x0, unsigned *y0,
+ unsigned *x1, unsigned *y1);
 
 void
 brw_meta_get_buffer_rect(const struct gl_framebuffer *fb, 
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 19/27] i965/blorp/clear: Stop stomping the destination format

[Jason Ekstrand]

The blorp_surface_info_init call above should ste the format for us and
stomping it later does nothing whatsoever.
---
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index daab5db..4d3fe58 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -132,6 +132,7 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
struct brw_blorp_params params;
brw_blorp_params_init(¶ms);
 
+   /* Override the surface format according to the context's sRGB rules. */
if (!encode_srgb && _mesa_get_format_color_encoding(format) == GL_SRGB)
   format = _mesa_get_srgb_format_linear(format);
 
@@ -220,9 +221,6 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
brw_blorp_to_isl_format(brw, format, true),
true);
 
-   /* Override the surface format according to the context's sRGB rules. */
-   params.dst.view.format = (enum isl_format)brw->render_target_format[format];
-
const char *clear_type;
if (is_fast_clear)
   clear_type = "fast";
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 12/27] i965/blorp: Use the isl_surf for more params setup

[Jason Ekstrand]

The isl_surf munging doesn't happen until fairly late in the blorp_blit
function.  We can use the isl_surf for the vast majority if not all of our
params setup.
---
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 79 
 1 file changed, 21 insertions(+), 58 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index af75cfa..3ce64e4 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1387,7 +1387,7 @@ brw_blorp_build_nir_shader(struct brw_context *brw,
/* If the source image is not multisampled, then we want to fetch sample
 * number 0, because that's the only sample there is.
 */
-   if (key->src_samples == 0)
+   if (key->src_samples == 1)
   src_pos = nir_channels(&b, src_pos, 0x3);
 
/* X, Y, and S are now the coordinates of the pixel in the source image
@@ -1464,7 +1464,7 @@ brw_blorp_build_nir_shader(struct brw_context *brw,
   * the texturing unit, will cause data to be read from the correct
   * memory location.  So we can fetch the texel now.
   */
- if (key->src_samples == 0) {
+ if (key->src_samples == 1) {
 color = blorp_nir_txf(&b, &v, src_pos, key->texture_data_type);
  } else {
 nir_ssa_def *mcs = NULL;
@@ -1547,26 +1547,6 @@ brw_blorp_setup_coord_transform(struct 
brw_blorp_coord_transform *xform,
}
 }
 
-static enum isl_msaa_layout
-get_isl_msaa_layout(unsigned samples, enum intel_msaa_layout layout)
-{
-   if (samples > 1) {
-  switch (layout) {
-  case INTEL_MSAA_LAYOUT_NONE:
- return ISL_MSAA_LAYOUT_NONE;
-  case INTEL_MSAA_LAYOUT_IMS:
- return ISL_MSAA_LAYOUT_INTERLEAVED;
-  case INTEL_MSAA_LAYOUT_UMS:
-  case INTEL_MSAA_LAYOUT_CMS:
- return ISL_MSAA_LAYOUT_ARRAY;
-  default:
- unreachable("Invalid MSAA layout");
-  }
-   } else {
-  return ISL_MSAA_LAYOUT_NONE;
-   }
-}
-
 /**
  * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
  * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED).  The mappings are
@@ -1797,28 +1777,12 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
struct brw_blorp_blit_prog_key wm_prog_key;
memset(&wm_prog_key, 0, sizeof(wm_prog_key));
 
-   /* texture_data_type indicates the register type that should be used to
-* manipulate texture data.
-*/
-   switch (_mesa_get_format_datatype(src_mt->format)) {
-   case GL_UNSIGNED_NORMALIZED:
-   case GL_SIGNED_NORMALIZED:
-   case GL_FLOAT:
-  wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_F;
-  break;
-   case GL_UNSIGNED_INT:
-  if (src_mt->format == MESA_FORMAT_S_UINT8) {
- /* We process stencil as though it's an unsigned normalized color */
- wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_F;
-  } else {
- wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_UD;
-  }
-  break;
-   case GL_INT:
+   if (isl_format_has_sint_channel(params.src.view.format)) {
   wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_D;
-  break;
-   default:
-  unreachable("Unrecognized blorp format");
+   } else if (isl_format_has_uint_channel(params.src.view.format)) {
+  wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_UD;
+   } else {
+  wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_F;
}
 
/* Scaled blitting or not. */
@@ -1829,21 +1793,20 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
/* Scaling factors used for bilinear filtering in multisample scaled
 * blits.
 */
-   if (src_mt->num_samples == 16)
+   if (params.src.surf.samples == 16)
   wm_prog_key.x_scale = 4.0f;
else
   wm_prog_key.x_scale = 2.0f;
-   wm_prog_key.y_scale = src_mt->num_samples / wm_prog_key.x_scale;
+   wm_prog_key.y_scale = params.src.surf.samples / wm_prog_key.x_scale;
 
if (filter == GL_LINEAR &&
params.src.surf.samples <= 1 && params.dst.surf.samples <= 1)
   wm_prog_key.bilinear_filter = true;
 
-   GLenum base_format = _mesa_get_format_base_format(src_mt->format);
-   if (base_format != GL_DEPTH_COMPONENT && /* TODO: what about depth/stencil? 
*/
-   base_format != GL_STENCIL_INDEX &&
-   !_mesa_is_format_integer(src_mt->format) &&
-   src_mt->num_samples > 1 && dst_mt->num_samples <= 1) {
+   if ((params.src.surf.usage & ISL_SURF_USAGE_DEPTH_BIT) == 0 &&
+   (params.src.surf.usage & ISL_SURF_USAGE_STENCIL_BIT) == 0 &&
+   !isl_format_has_int_channel(params.src.surf.format) &&
+   params.src.surf.samples > 1 && params.dst.surf.samples <= 1) {
   /* We are downsampling a non-integer color buffer, so blend.
*
* Regarding integer color buffers, the OpenGL ES 3.2 spec says:
@@ -1857,18 +1820,16 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
}
 
/* src_samples and dst_samples are the true sample counts */
-   wm_prog_key.src_samples 

[Mesa-dev] [PATCH v2 07/27] i965/blorp/blit: Move format work-arounds before surface_info_init

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 30 +---
 1 file changed, 14 insertions(+), 16 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 007c061..ed68734 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1744,14 +1744,6 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
if (!encode_srgb && _mesa_get_format_color_encoding(dst_format) == GL_SRGB)
   dst_format = _mesa_get_srgb_format_linear(dst_format);
 
-   struct brw_blorp_params params;
-   brw_blorp_params_init(¶ms);
-
-   brw_blorp_surface_info_init(brw, ¶ms.src, src_mt, src_level,
-   src_layer, src_format, false);
-   brw_blorp_surface_info_init(brw, ¶ms.dst, dst_mt, dst_level,
-   dst_layer, dst_format, true);
-
/* Even though we do multisample resolves at the time of the blit, OpenGL
 * specification defines them as if they happen at the time of rendering,
 * which means that the type of averaging we do during the resolve should
@@ -1767,15 +1759,12 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
 * (aside from the color space), we choose to blit in sRGB space to get
 * this higher quality image.
 */
-   if (params.src.surf.samples > 1 &&
+   if (src_mt->num_samples > 1 &&
_mesa_get_format_color_encoding(dst_mt->format) == GL_SRGB &&
_mesa_get_srgb_format_linear(src_mt->format) ==
_mesa_get_srgb_format_linear(dst_mt->format)) {
   assert(brw->format_supported_as_render_target[dst_mt->format]);
-  params.dst.view.format =
- (enum isl_format)brw->render_target_format[dst_mt->format];
-  params.src.view.format =
- (enum isl_format)brw_format_for_mesa_format(dst_mt->format);
+  src_format = dst_format = dst_mt->format;
}
 
/* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
@@ -1788,12 +1777,21 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
 * R32_FLOAT, so only the contents of the red channel matters.
 */
if (brw->gen == 6 &&
-   params.src.surf.samples > 1 && params.dst.surf.samples <= 1 &&
+   src_mt->num_samples > 1 && dst_mt->num_samples <= 1 &&
src_mt->format == dst_mt->format &&
-   params.dst.view.format == ISL_FORMAT_R32_FLOAT) {
-  params.src.view.format = params.dst.view.format;
+   (dst_format == MESA_FORMAT_L_FLOAT32 ||
+dst_format == MESA_FORMAT_I_FLOAT32)) {
+  src_format = dst_format = MESA_FORMAT_R_FLOAT32;
}
 
+   struct brw_blorp_params params;
+   brw_blorp_params_init(¶ms);
+
+   brw_blorp_surface_info_init(brw, ¶ms.src, src_mt, src_level,
+   src_layer, src_format, false);
+   brw_blorp_surface_info_init(brw, ¶ms.dst, dst_mt, dst_level,
+   dst_layer, dst_format, true);
+
struct brw_blorp_blit_prog_key wm_prog_key;
memset(&wm_prog_key, 0, sizeof(wm_prog_key));
 
-- 
2.5.0.400.gff86faf

___
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mesa-dev@lists.freedesktop.org
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[Mesa-dev] [PATCH v2 10/27] i965/blorp: Set up HiZ surfaces up-front

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_blorp.c  | 59 +-
 src/mesa/drivers/dri/i965/brw_blorp.h  |  2 --
 src/mesa/drivers/dri/i965/gen6_blorp.c | 19 +++
 src/mesa/drivers/dri/i965/gen7_blorp.c | 10 +++---
 4 files changed, 59 insertions(+), 31 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 97eddf9..47801f0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -105,6 +105,28 @@ blorp_get_image_offset_sa(struct isl_device *dev, const 
struct isl_surf *surf,
}
 }
 
+static void
+apply_gen6_stencil_hiz_offset(struct isl_surf *surf,
+  struct intel_mipmap_tree *mt,
+  uint32_t lod,
+  uint32_t *offset)
+{
+   assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD);
+
+   *offset = intel_miptree_get_aligned_offset(mt,
+  mt->level[lod].level_x,
+  mt->level[lod].level_y,
+  false);
+
+   surf->logical_level0_px.width = minify(surf->logical_level0_px.width, lod);
+   surf->logical_level0_px.height = minify(surf->logical_level0_px.height, 
lod);
+   surf->phys_level0_sa.width = minify(surf->phys_level0_sa.width, lod);
+   surf->phys_level0_sa.height = minify(surf->phys_level0_sa.height, lod);
+   surf->levels = 1;
+   surf->array_pitch_el_rows =
+  ALIGN(surf->phys_level0_sa.height, surf->image_alignment_el.height);
+}
+
 void
 brw_blorp_surface_info_init(struct brw_context *brw,
 struct brw_blorp_surface_info *info,
@@ -125,7 +147,6 @@ brw_blorp_surface_info_init(struct brw_context *brw,
 
intel_miptree_check_level_layer(mt, level, layer);
 
-   info->mt = mt;
if (is_render_target)
   intel_miptree_used_for_rendering(mt);
 
@@ -133,21 +154,43 @@ brw_blorp_surface_info_init(struct brw_context *brw,
info->bo = mt->bo;
info->offset = mt->offset;
 
-   if (mt->mcs_mt) {
-  intel_miptree_get_aux_isl_surf(brw, mt, &info->aux_surf,
- &info->aux_usage);
-  info->aux_bo = mt->mcs_mt->bo;
-  info->aux_offset = mt->mcs_mt->offset;
-
+   intel_miptree_get_aux_isl_surf(brw, mt, &info->aux_surf,
+  &info->aux_usage);
+   if (info->aux_usage != ISL_AUX_USAGE_NONE) {
   /* We only really need a clear color if we also have an auxiliary
* surface.  Without one, it does nothing.
*/
   info->clear_color = intel_miptree_get_isl_clear_color(brw, mt);
+
+  if (mt->mcs_mt) {
+ info->aux_bo = mt->mcs_mt->bo;
+ info->aux_offset = mt->mcs_mt->offset;
+  } else {
+ assert(info->aux_usage == ISL_AUX_USAGE_HIZ);
+ struct intel_mipmap_tree *hiz_mt = mt->hiz_buf->mt;
+ if (hiz_mt) {
+info->aux_bo = hiz_mt->bo;
+if (hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
+   /* gen6 requires the HiZ buffer to be manually offset to the
+* right location.  We could fixup the surf but it doesn't
+* matter since most of those fields don't matter.
+*/
+   apply_gen6_stencil_hiz_offset(&info->aux_surf, hiz_mt, level,
+ &info->aux_offset);
+} else {
+   info->aux_offset = 0;
+}
+assert(hiz_mt->pitch == info->aux_surf.row_pitch);
+ } else {
+info->aux_bo = mt->hiz_buf->bo;
+info->aux_offset = 0;
+ }
+  }
} else {
-  info->aux_usage = ISL_AUX_USAGE_NONE;
   info->aux_bo = NULL;
   info->aux_offset = 0;
}
+   assert((info->aux_usage == ISL_AUX_USAGE_NONE) == (info->aux_bo == NULL));
 
info->view = (struct isl_view) {
   .usage = is_render_target ? ISL_SURF_USAGE_RENDER_TARGET_BIT :
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index d747880..95a6257 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -69,8 +69,6 @@ enum {
 
 struct brw_blorp_surface_info
 {
-   struct intel_mipmap_tree *mt;
-
struct isl_surf surf;
drm_intel_bo *bo;
uint32_t offset;
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c 
b/src/mesa/drivers/dri/i965/gen6_blorp.c
index 6f3073b..8aeaf61 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.c
@@ -759,23 +759,12 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context 
*brw,
 
/* 3DSTATE_HIER_DEPTH_BUFFER */
{
-  struct intel_mipmap_tree *hiz_mt = params->depth.mt->hiz_buf->mt;
-  uint32_t offset = 0;
-
-  if (hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
- const unsigned lod = params->depth.view.base_level;
- offset = intel_miptree_get_aligned_