[Mesa-dev] [v2 25/39] i965: Prepare blit engine for isl based miptrees

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_blit.c | 37 +-
 src/mesa/drivers/dri/i965/intel_blit.h | 13 
 2 files changed, 41 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
b/src/mesa/drivers/dri/i965/intel_blit.c
index 4cd86dd..be6a851 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -131,6 +131,10 @@ set_blitter_tiling(struct brw_context *brw,
 static int
 blt_pitch(struct intel_mipmap_tree *mt)
 {
+   if (mt->surf.size > 0)
+  return (mt->surf.tiling != ISL_TILING_LINEAR) ?
+ mt->surf.row_pitch / 4 : mt->surf.row_pitch;
+
int pitch = mt->pitch;
if (mt->tiling)
   pitch /= 4;
@@ -171,9 +175,13 @@ get_blit_intratile_offset_el(const struct brw_context *brw,
  uint32_t *x_offset_el,
  uint32_t *y_offset_el)
 {
+   const unsigned cpp = mt->surf.size > 0 ?
+  isl_format_get_layout(mt->surf.format)->bpb / 8 : mt->cpp;
+   const unsigned pitch = mt->surf.size > 0 ? mt->surf.row_pitch : mt->pitch;
+
enum isl_tiling tiling = intel_miptree_get_isl_tiling(mt);
isl_tiling_get_intratile_offset_el(>isl_dev,
-  tiling, mt->cpp, mt->pitch,
+  tiling, cpp, pitch,
   total_x_offset_el, total_y_offset_el,
   base_address_offset,
   x_offset_el, y_offset_el);
@@ -188,11 +196,11 @@ get_blit_intratile_offset_el(const struct brw_context 
*brw,
* The offsets we get from ISL in the tiled case are already aligned.
* In the linear case, we need to do some of our own aligning.
*/
-  assert(mt->pitch % 64 == 0);
+  assert(pitch % 64 == 0);
   uint32_t delta = *base_address_offset & 63;
-  assert(delta % mt->cpp == 0);
+  assert(delta % cpp == 0);
   *base_address_offset -= delta;
-  *x_offset_el += delta / mt->cpp;
+  *x_offset_el += delta / cpp;
} else {
   assert(*base_address_offset % 4096 == 0);
}
@@ -207,6 +215,17 @@ emit_miptree_blit(struct brw_context *brw,
   uint32_t width, uint32_t height,
   bool reverse, GLenum logicop)
 {
+   const unsigned src_cpp = src_mt->surf.size > 0 ?
+  isl_format_get_layout(src_mt->surf.format)->bpb / 8 : src_mt->cpp;
+   const unsigned src_pitch =
+  src_mt->surf.size > 0 ? src_mt->surf.row_pitch : src_mt->pitch;
+   const unsigned dst_pitch =
+  dst_mt->surf.size > 0 ? dst_mt->surf.row_pitch : dst_mt->pitch;
+   const unsigned src_tiling = src_mt->surf.size > 0 ?
+  isl_tiling_to_bufmgr_tiling(src_mt->surf.tiling) : src_mt->tiling;
+   const unsigned dst_tiling = dst_mt->surf.size > 0 ?
+  isl_tiling_to_bufmgr_tiling(dst_mt->surf.tiling) : dst_mt->tiling;
+
/* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
 * Data Size Limitations):
 *
@@ -251,13 +270,13 @@ emit_miptree_blit(struct brw_context *brw,
   _offset, _tile_x, _tile_y);
 
  if (!intelEmitCopyBlit(brw,
-src_mt->cpp,
-reverse ? -src_mt->pitch : src_mt->pitch,
+src_cpp,
+reverse ? -src_pitch : src_pitch,
 src_mt->bo, src_mt->offset + src_offset,
-src_mt->tiling,
-dst_mt->pitch,
+src_tiling,
+dst_pitch,
 dst_mt->bo, dst_mt->offset + dst_offset,
-dst_mt->tiling,
+dst_tiling,
 src_tile_x, src_tile_y,
 dst_tile_x, dst_tile_y,
 chunk_w, chunk_h,
diff --git a/src/mesa/drivers/dri/i965/intel_blit.h 
b/src/mesa/drivers/dri/i965/intel_blit.h
index 2604417..5e4d1f5 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.h
+++ b/src/mesa/drivers/dri/i965/intel_blit.h
@@ -28,6 +28,19 @@
 
 #include "brw_context.h"
 
+static inline unsigned
+isl_tiling_to_bufmgr_tiling(enum isl_tiling tiling)
+{
+   if (tiling == ISL_TILING_X)
+  return I915_TILING_X;
+
+   if (tiling == ISL_TILING_Y0)
+  return I915_TILING_Y;
+
+   /* All other are unknown to buffer allocator. */
+   return I915_TILING_NONE;
+}
+
 bool
 intelEmitCopyBlit(struct brw_context *brw,
   GLuint cpp,
-- 
2.9.3

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[Mesa-dev] [v2 26/39] i965: Prepare image validation for isl based miptrees

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 3a4ac14..55f6027 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1012,6 +1012,18 @@ intel_miptree_match_image(struct intel_mipmap_tree *mt,
if (mt->target == GL_TEXTURE_CUBE_MAP)
   depth = 6;
 
+   if (mt->surf.size > 0) {
+  const unsigned level_depth =
+ mt->surf.dim_layout == ISL_DIM_LAYOUT_GEN4_3D ?
+minify(mt->surf.logical_level0_px.depth, level) :
+mt->surf.logical_level0_px.array_len;
+
+  return width == minify(mt->surf.logical_level0_px.width, level) &&
+ height == minify(mt->surf.logical_level0_px.height, level) &&
+ depth == level_depth &&
+ MAX2(image->NumSamples, 1) == mt->surf.samples;
+   }
+
int level_depth = mt->level[level].depth;
if (mt->num_samples > 1) {
   switch (mt->msaa_layout) {
-- 
2.9.3

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[Mesa-dev] [v2 23/39] i965/blorp: Add support for isl based miptrees

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 0235681..158cf66 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -131,8 +131,13 @@ blorp_surf_for_miptree(struct brw_context *brw,
  intel_miptree_check_level_layer(mt, *level, start_layer + i);
}
 
-   intel_miptree_get_isl_surf(brw, mt, _surfs[0]);
-   surf->surf = _surfs[0];
+   if (mt->surf.size > 0) {
+  surf->surf = >surf;
+   } else {
+  intel_miptree_get_isl_surf(brw, mt, _surfs[0]);
+  surf->surf = _surfs[0];
+   }
+
surf->addr = (struct blorp_address) {
   .buffer = mt->bo,
   .offset = mt->offset,
-- 
2.9.3

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[Mesa-dev] [v2 31/39] i965/tex: Prepare image update for isl based miptrees

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_tex_image.c | 19 ---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c 
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 9aa2f70..14de748 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -56,11 +56,24 @@ intel_miptree_create_for_teximage(struct brw_context *brw,
 {
GLuint lastLevel;
int width, height, depth;
+   unsigned old_width = 0, old_height = 0, old_depth = 0;
const struct intel_mipmap_tree *old_mt = intelObj->mt;
const unsigned level = intelImage->base.Base.Level;
 
intel_get_image_dims(>base.Base, , , );
 
+   if (old_mt && old_mt->surf.size > 0) {
+  old_width = old_mt->surf.logical_level0_px.width;
+  old_height = old_mt->surf.logical_level0_px.height;
+  old_depth = old_mt->surf.dim_layout == ISL_DIM_LAYOUT_GEN4_3D ?
+ old_mt->surf.logical_level0_px.depth :
+ old_mt->surf.logical_level0_px.array_len;
+   } else if (old_mt) {
+  old_width = old_mt->logical_width0;
+  old_height = old_mt->logical_height0;
+  old_depth = old_mt->logical_depth0;
+   }
+
DBG("%s\n", __func__);
 
/* Figure out image dimensions at start level. */
@@ -72,19 +85,19 @@ intel_miptree_create_for_teximage(struct brw_context *brw,
   assert(level == 0);
   break;
case GL_TEXTURE_3D:
-  depth = old_mt ? get_base_dim(old_mt->logical_depth0, depth, level) :
+  depth = old_mt ? get_base_dim(old_depth, depth, level) :
depth << level;
   /* Fall through */
case GL_TEXTURE_2D:
case GL_TEXTURE_2D_ARRAY:
case GL_TEXTURE_CUBE_MAP:
case GL_TEXTURE_CUBE_MAP_ARRAY:
-  height = old_mt ? get_base_dim(old_mt->logical_height0, height, level) :
+  height = old_mt ? get_base_dim(old_height, height, level) :
 height << level;
   /* Fall through */
case GL_TEXTURE_1D:
case GL_TEXTURE_1D_ARRAY:
-  width = old_mt ? get_base_dim(old_mt->logical_width0, width, level) :
+  width = old_mt ? get_base_dim(old_width, width, level) :
width << level;
   break;
default:
-- 
2.9.3

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[Mesa-dev] [v2 22/39] i965/miptree: Add support for resolving offsets using isl

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_misc_state.c   |  12 +--
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  11 ++-
 src/mesa/drivers/dri/i965/intel_blit.c   |   8 +-
 src/mesa/drivers/dri/i965/intel_fbo.c|   9 +-
 src/mesa/drivers/dri/i965/intel_fbo.h|   9 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 102 +--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h|   8 +-
 src/mesa/drivers/dri/i965/intel_screen.c |   3 +-
 src/mesa/drivers/dri/i965/intel_tex_image.c  |   2 +-
 9 files changed, 115 insertions(+), 49 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 9dd6ab8..2911739 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -313,7 +313,7 @@ brw_workaround_depthstencil_alignment(struct brw_context 
*brw,
  stencil_irb != depth_irb &&
  stencil_irb->mt == depth_mt) {
 intel_miptree_reference(_irb->mt, depth_irb->mt);
-intel_renderbuffer_set_draw_offset(stencil_irb);
+intel_renderbuffer_set_draw_offset(>isl_dev, stencil_irb);
  }
 
  stencil_mt = get_stencil_miptree(stencil_irb);
@@ -324,7 +324,7 @@ brw_workaround_depthstencil_alignment(struct brw_context 
*brw,
 
   if (stencil_irb) {
  stencil_mt = get_stencil_miptree(stencil_irb);
- intel_miptree_get_image_offset(stencil_mt,
+ intel_miptree_get_image_offset(>isl_dev, stencil_mt,
 stencil_irb->mt_level,
 stencil_irb->mt_layer,
 _draw_x, _draw_y);
@@ -345,7 +345,7 @@ brw_workaround_depthstencil_alignment(struct brw_context 
*brw,
 
/* If we have (just) stencil, check it for ignored low bits as well */
if (stencil_irb) {
-  intel_miptree_get_image_offset(stencil_mt,
+  intel_miptree_get_image_offset(>isl_dev, stencil_mt,
  stencil_irb->mt_level,
  stencil_irb->mt_layer,
  _draw_x, _draw_y);
@@ -369,7 +369,7 @@ brw_workaround_depthstencil_alignment(struct brw_context 
*brw,
   intel_renderbuffer_move_to_temp(brw, stencil_irb, invalidate_stencil);
   stencil_mt = get_stencil_miptree(stencil_irb);
 
-  intel_miptree_get_image_offset(stencil_mt,
+  intel_miptree_get_image_offset(>isl_dev, stencil_mt,
  stencil_irb->mt_level,
  stencil_irb->mt_layer,
  _draw_x, _draw_y);
@@ -378,7 +378,7 @@ brw_workaround_depthstencil_alignment(struct brw_context 
*brw,
 
   if (depth_irb && depth_irb->mt == stencil_irb->mt) {
  intel_miptree_reference(_irb->mt, stencil_irb->mt);
- intel_renderbuffer_set_draw_offset(depth_irb);
+ intel_renderbuffer_set_draw_offset(>isl_dev, depth_irb);
   } else if (depth_irb && !rebase_depth) {
  if (tile_x != stencil_tile_x ||
  tile_y != stencil_tile_y) {
@@ -397,7 +397,7 @@ brw_workaround_depthstencil_alignment(struct brw_context 
*brw,
 
 if (stencil_irb && stencil_irb->mt == depth_mt) {
intel_miptree_reference(_irb->mt, depth_irb->mt);
-   intel_renderbuffer_set_draw_offset(stencil_irb);
+   intel_renderbuffer_set_draw_offset(>isl_dev, stencil_irb);
 }
 
 WARN_ONCE(stencil_tile_x != tile_x ||
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index b2eca07..b3d9382 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -105,7 +105,8 @@ brw_emit_surface_state(struct brw_context *brw,
   assert(view.levels == 1 && view.array_len == 1);
   assert(tile_x == 0 && tile_y == 0);
 
-  offset += intel_miptree_get_tile_offsets(mt, view.base_level,
+  offset += intel_miptree_get_tile_offsets(>isl_dev, mt,
+   view.base_level,
view.base_array_layer,
_x, _y);
 
@@ -999,7 +1000,8 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
assert(!(flags & INTEL_AUX_BUFFER_DISABLED));
 
if (rb->TexImage && !brw->has_surface_tile_offset) {
-  intel_renderbuffer_get_tile_offsets(irb, _x, _y);
+  intel_renderbuffer_get_tile_offsets(>isl_dev, irb,
+  _x, _y);
 
   if (tile_x != 0 || tile_y != 0) {
 /* Original gen4 hardware couldn't draw to a non-tile-aligned
@@ -1026,7 +1028,8 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
 
/* reloc */
 

[Mesa-dev] [v2 21/39] intel/isl/gen6/hack: Use hiz vertical alignment of 16 instead of 8

[Topi Pohjolainen]

Looking PRMs (SNB, IVB) it also looks to me that the height of hiz
buffer would need to be half the height of depth. How this is taken
into account in i965 legacy or isl is unclear to me also.

Signed-off-by: Topi Pohjolainen 
---
 src/intel/isl/isl_gen6.c | 40 ++--
 1 file changed, 38 insertions(+), 2 deletions(-)

diff --git a/src/intel/isl/isl_gen6.c b/src/intel/isl/isl_gen6.c
index 19430e9..c78a558 100644
--- a/src/intel/isl/isl_gen6.c
+++ b/src/intel/isl/isl_gen6.c
@@ -146,6 +146,39 @@ isl_gen6_choose_image_alignment_el(const struct isl_device 
*dev,
*image_align_el = isl_extent3d(4, 2, 1);
 }
 
+static uint32_t
+get_valign(const struct isl_extent3d *image_align_sa, enum isl_tiling tiling)
+{
+   assert(tiling == ISL_TILING_W || tiling == ISL_TILING_HIZ); 
+
+   if (tiling == ISL_TILING_W)
+  return image_align_sa->h;
+
+   /* Using simply:
+*array_pitch = d * isl_align_npot(h, image_align_sa.h);
+*
+* results into individual slices of array to be aligned by 8
+* (image_align_sa.h) rows. In practise, this upsets piglit test:
+*tex-miplevel-selection "texture()" 2DArrayShadow -auto -fbo
+*
+* Using 16 instead seems to work.
+*
+* From the Sandrybridge PRM (2011-05), Volume 2, Part 1, Section 7.5.3
+* Hierarchical Depth Buffer:
+*
+*   ceiling(Z_height / 8) * 4 * Z_Depth
+*
+* This, however, results into even tighter packing than align by eight.
+*
+* It should be noted that i965 GL driver used alignment of even greater
+* alignment of 32 before switching to this here. Also important to see is
+* that this only affects the amount of padding between arrays of slices
+* of two subsequent levels. Driver doesn't try to offset to slices within
+* an array, driver only offsets to levels, i.e., to first slice of array.
+*/
+   return 16;
+}
+
 void
 get_image_offset_sa_gen6_back_to_back(const struct isl_surf *surf,
   uint32_t level,
@@ -154,6 +187,9 @@ get_image_offset_sa_gen6_back_to_back(const struct isl_surf 
*surf,
   uint32_t *x_offset_sa,
   uint32_t *y_offset_sa)
 {
+   /* Alignment of individual slices may be broken. */
+   assert(surf->tiling != ISL_TILING_HIZ ||
+  (logical_array_layer == 0 && logical_z_offset_px == 0));
assert(level < surf->levels);
 
const struct isl_extent3d image_align_sa =
@@ -169,7 +205,7 @@ get_image_offset_sa_gen6_back_to_back(const struct isl_surf 
*surf,
  isl_minify(surf->phys_level0_sa.depth, i) :
  surf->phys_level0_sa.array_len;
   const unsigned h = isl_minify(surf->phys_level0_sa.height, i);
-  y += d * isl_align_npot(h, image_align_sa.h);
+  y += d * isl_align_npot(h, get_valign(_align_sa, surf->tiling));
 
   /* Align on tile boundary so that driver can offset without intra-tile
* offsets.
@@ -208,7 +244,7 @@ isl_gen6_calc_back_to_back_total_h(const struct 
isl_extent4d *phys_level0_sa,
  isl_minify(phys_level0_sa->depth, i) :
  phys_level0_sa->array_len;
   const unsigned h = isl_minify(phys_level0_sa->height, i);
-  total_h += d * isl_align_npot(h, image_align_sa->h);
+  total_h += d * isl_align_npot(h, get_valign(image_align_sa, tiling));
 
   /* Align on tile boundary so that driver can offset without intra-tile
* offsets.
-- 
2.9.3

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[Mesa-dev] [v2 17/39] i965: Use stored hiz surface instead of creating copy

[Topi Pohjolainen]

Now the last user of intel_miptree_get_aux_isl_surf() is gone.

Reviewed-by: Jason Ekstrand 
Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  5 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 77 
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h|  6 --
 3 files changed, 2 insertions(+), 86 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 8811d62..b2eca07 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -134,7 +134,7 @@ brw_emit_surface_state(struct brw_context *brw,
union isl_color_value clear_color = { .u32 = { 0, 0, 0, 0 } };
 
struct brw_bo *aux_bo;
-   struct isl_surf *aux_surf = NULL, aux_surf_s;
+   struct isl_surf *aux_surf = NULL;
uint64_t aux_offset = 0;
enum isl_aux_usage aux_usage = ISL_AUX_USAGE_NONE;
if ((mt->mcs_buf || intel_miptree_sample_with_hiz(brw, mt)) &&
@@ -148,8 +148,7 @@ brw_emit_surface_state(struct brw_context *brw,
  aux_bo = mt->mcs_buf->bo;
  aux_offset = mt->mcs_buf->bo->offset64 + mt->mcs_buf->offset;
   } else {
- intel_miptree_get_aux_isl_surf(brw, mt, aux_usage, _surf_s);
- aux_surf = _surf_s;
+ aux_surf = >hiz_buf->surf;
 
  aux_bo = mt->hiz_buf->bo;
  aux_offset = mt->hiz_buf->bo->offset64;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 2f711ed..82ffd11 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -3163,83 +3163,6 @@ intel_miptree_get_aux_isl_usage(const struct brw_context 
*brw,
unreachable("Invalid MCS miptree");
 }
 
-/* WARNING: THE SURFACE CREATED BY THIS FUNCTION IS NOT COMPLETE AND CANNOT BE
- * USED FOR ANY REAL CALCULATIONS.  THE ONLY VALID USE OF SUCH A SURFACE IS TO
- * PASS IT INTO isl_surf_fill_state.
- */
-void
-intel_miptree_get_aux_isl_surf(struct brw_context *brw,
-   const struct intel_mipmap_tree *mt,
-   enum isl_aux_usage usage,
-   struct isl_surf *surf)
-{
-   uint32_t aux_pitch, aux_qpitch;
-   if (mt->mcs_buf) {
-  aux_pitch = mt->mcs_buf->pitch;
-  aux_qpitch = mt->mcs_buf->qpitch;
-   } else if (mt->hiz_buf) {
-  aux_pitch = mt->hiz_buf->pitch;
-  aux_qpitch = mt->hiz_buf->qpitch;
-   } else {
-  return;
-   }
-
-   /* Start with a copy of the original surface. */
-   intel_miptree_get_isl_surf(brw, mt, surf);
-
-   /* Figure out the format and tiling of the auxiliary surface */
-   switch (usage) {
-   case ISL_AUX_USAGE_NONE:
-  unreachable("Invalid auxiliary usage");
-
-   case ISL_AUX_USAGE_HIZ:
-  isl_surf_get_hiz_surf(>isl_dev, surf, surf);
-  break;
-
-   case ISL_AUX_USAGE_MCS:
-  /*
-   * From the SKL PRM:
-   *"When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
-   *HALIGN 16 must be used."
-   */
-  if (brw->gen >= 9)
- assert(mt->halign == 16);
-
-  isl_surf_get_mcs_surf(>isl_dev, surf, surf);
-  break;
-
-   case ISL_AUX_USAGE_CCS_D:
-   case ISL_AUX_USAGE_CCS_E:
-  /*
-   * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
-   *
-   *"When MCS is enabled for non-MSRT, HALIGN_16 must be used"
-   *
-   * From the hardware spec for GEN9:
-   *
-   *"When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
-   *HALIGN 16 must be used."
-   */
-  assert(mt->num_samples <= 1);
-  if (brw->gen >= 8)
- assert(mt->halign == 16);
-
-  isl_surf_get_ccs_surf(>isl_dev, surf, surf);
-  break;
-   }
-
-   /* We want the pitch of the actual aux buffer. */
-   surf->row_pitch = aux_pitch;
-
-   /* Auxiliary surfaces in ISL have compressed formats and array_pitch_el_rows
-* is in elements.  This doesn't match intel_mipmap_tree::qpitch which is
-* in elements of the primary color surface so we have to divide by the
-* compression block height.
-*/
-   surf->array_pitch_el_rows =
-  aux_qpitch / isl_format_get_layout(surf->format)->bh;
-}
-
 union isl_color_value
 intel_miptree_get_isl_clear_color(struct brw_context *brw,
   const struct intel_mipmap_tree *mt)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 5172a3f..dd77621 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -771,12 +771,6 @@ enum isl_aux_usage
 intel_miptree_get_aux_isl_usage(const struct brw_context *brw,
 const struct intel_mipmap_tree *mt);
 
-void
-intel_miptree_get_aux_isl_surf(struct brw_context *brw,
- 

[Mesa-dev] [v2 18/39] intel/isl/gen6: Add offsetting support for back-to-back layouts

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/intel/blorp/blorp_blit.c  |  2 +-
 src/intel/isl/isl.c   | 29 +---
 src/intel/isl/isl.h   | 14 ++--
 src/intel/isl/isl_gen6.c  | 46 +++
 src/intel/isl/isl_storage_image.c |  3 ++-
 5 files changed, 87 insertions(+), 7 deletions(-)

diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 8e3fc31..ca42600 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -1398,7 +1398,7 @@ surf_convert_to_single_slice(const struct isl_device 
*isl_dev,
   layer = info->view.base_array_layer;
 
uint32_t x_offset_sa, y_offset_sa;
-   isl_surf_get_image_offset_sa(>surf, info->view.base_level,
+   isl_surf_get_image_offset_sa(isl_dev, >surf, info->view.base_level,
 layer, z, _offset_sa, _offset_sa);
 
uint32_t byte_offset;
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index f89f351..e06bb94 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1295,6 +1295,20 @@ isl_apply_surface_padding(const struct isl_device *dev,
}
 }
 
+/* On Gen6 hardware doesn't support mipmapping for stencil (W-tiled) and
+ * for HIZ. As workaround one places all slices back-to-back. Slices for
+ * level zero are back-to-back, followed by slices to level one, etc. This
+ * allows layered rendering once driver offsets the image to the first
+ * slice of particular level.
+ */
+static bool
+isl_surf_needs_back_to_back_layout(const struct isl_device *dev,
+   enum isl_tiling tiling)
+{
+   return ISL_DEV_GEN(dev) == 6 &&
+  (tiling == ISL_TILING_W || tiling == ISL_TILING_HIZ);
+}
+
 bool
 isl_surf_init_s(const struct isl_device *dev,
 struct isl_surf *surf,
@@ -1906,7 +1920,8 @@ get_image_offset_sa_gen9_1d(const struct isl_surf *surf,
  * @invariant logical_z_offset_px < logical depth of surface at level
  */
 void
-isl_surf_get_image_offset_sa(const struct isl_surf *surf,
+isl_surf_get_image_offset_sa(const struct isl_device *dev,
+ const struct isl_surf *surf,
  uint32_t level,
  uint32_t logical_array_layer,
  uint32_t logical_z_offset_px,
@@ -1918,6 +1933,13 @@ isl_surf_get_image_offset_sa(const struct isl_surf *surf,
assert(logical_z_offset_px
   < isl_minify(surf->logical_level0_px.depth, level));
 
+   if (isl_surf_needs_back_to_back_layout(dev, surf->tiling)) {
+  get_image_offset_sa_gen6_back_to_back(surf, level, logical_array_layer,
+logical_z_offset_px,
+x_offset_sa, y_offset_sa);
+  return;
+   }
+
switch (surf->dim_layout) {
case ISL_DIM_LAYOUT_GEN9_1D:
   get_image_offset_sa_gen9_1d(surf, level, logical_array_layer,
@@ -1939,7 +1961,8 @@ isl_surf_get_image_offset_sa(const struct isl_surf *surf,
 }
 
 void
-isl_surf_get_image_offset_el(const struct isl_surf *surf,
+isl_surf_get_image_offset_el(const struct isl_device *dev,
+ const struct isl_surf *surf,
  uint32_t level,
  uint32_t logical_array_layer,
  uint32_t logical_z_offset_px,
@@ -1954,7 +1977,7 @@ isl_surf_get_image_offset_el(const struct isl_surf *surf,
   < isl_minify(surf->logical_level0_px.depth, level));
 
uint32_t x_offset_sa, y_offset_sa;
-   isl_surf_get_image_offset_sa(surf, level,
+   isl_surf_get_image_offset_sa(dev, surf, level,
 logical_array_layer,
 logical_z_offset_px,
 _offset_sa,
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 7778551..3685ddf 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1484,6 +1484,14 @@ isl_surf_get_array_pitch(const struct isl_surf *surf)
return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch;
 }
 
+void
+get_image_offset_sa_gen6_back_to_back(const struct isl_surf *surf,
+  uint32_t level,
+  uint32_t logical_array_layer,
+  uint32_t logical_z_offset_px,
+  uint32_t *x_offset_sa,
+  uint32_t *y_offset_sa);
+
 /**
  * Calculate the offset, in units of surface samples, to a subimage in the
  * surface.
@@ -1493,7 +1501,8 @@ isl_surf_get_array_pitch(const struct isl_surf *surf)
  * @invariant logical_z_offset_px < logical depth of surface at level
  */
 void
-isl_surf_get_image_offset_sa(const struct isl_surf *surf,
+isl_surf_get_image_offset_sa(const struct isl_device *dev,
+ const struct isl_surf *surf,
  

[Mesa-dev] [v2 19/39] intel/isl/gen6: Add size calculator for back-to-back layouts

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/intel/isl/isl.c  | 26 ++
 src/intel/isl/isl.h  |  6 ++
 src/intel/isl/isl_gen6.c | 27 +++
 3 files changed, 51 insertions(+), 8 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index e06bb94..e21ef06 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1351,9 +1351,6 @@ isl_surf_init_s(const struct isl_device *dev,
assert(phys_level0_sa.w % fmtl->bw == 0);
assert(phys_level0_sa.h % fmtl->bh == 0);
 
-   enum isl_array_pitch_span array_pitch_span =
-  isl_choose_array_pitch_span(dev, info, dim_layout, _level0_sa);
-
struct isl_extent2d phys_slice0_sa;
isl_calc_phys_slice0_extent_sa(dev, info, dim_layout, msaa_layout,
   _align_sa, _level0_sa,
@@ -1361,12 +1358,25 @@ isl_surf_init_s(const struct isl_device *dev,
assert(phys_slice0_sa.w % fmtl->bw == 0);
assert(phys_slice0_sa.h % fmtl->bh == 0);
 
-   const uint32_t array_pitch_el_rows =
-  isl_calc_array_pitch_el_rows(dev, info, _info, dim_layout,
-   array_pitch_span, _align_sa,
-   _level0_sa, _slice0_sa);
+   enum isl_array_pitch_span array_pitch_span;
+   uint32_t array_pitch_el_rows;
+   uint32_t total_h_el;
 
-   uint32_t total_h_el = phys_level0_sa.array_len * array_pitch_el_rows;
+   if (isl_surf_needs_back_to_back_layout(dev, tiling)) {
+  array_pitch_span = 0;
+  array_pitch_el_rows = 0;
+  total_h_el = isl_gen6_calc_back_to_back_total_h(
+  _level0_sa, _align_sa,
+  dim_layout, tiling, info->levels);
+   } else {
+  array_pitch_span = isl_choose_array_pitch_span(dev, info, dim_layout,
+ _level0_sa);
+  array_pitch_el_rows = isl_calc_array_pitch_el_rows(
+   dev, info, _info, dim_layout,
+   array_pitch_span, _align_sa,
+   _level0_sa, _slice0_sa);
+  total_h_el = phys_level0_sa.array_len * array_pitch_el_rows;
+   }
 
uint32_t pad_bytes;
isl_apply_surface_padding(dev, info, _info, _h_el, _bytes);
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 3685ddf..d1ea0d5 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1492,6 +1492,12 @@ get_image_offset_sa_gen6_back_to_back(const struct 
isl_surf *surf,
   uint32_t *x_offset_sa,
   uint32_t *y_offset_sa);
 
+uint32_t
+isl_gen6_calc_back_to_back_total_h(const struct isl_extent4d *phys_level0_sa,
+   const struct isl_extent3d *image_align_sa,
+   enum isl_dim_layout dim_layout,
+   enum isl_tiling tiling, uint32_t levels);
+
 /**
  * Calculate the offset, in units of surface samples, to a subimage in the
  * surface.
diff --git a/src/intel/isl/isl_gen6.c b/src/intel/isl/isl_gen6.c
index 8bd5dbc..19430e9 100644
--- a/src/intel/isl/isl_gen6.c
+++ b/src/intel/isl/isl_gen6.c
@@ -191,3 +191,30 @@ get_image_offset_sa_gen6_back_to_back(const struct 
isl_surf *surf,
*x_offset_sa = 0;
*y_offset_sa = y;
 }
+
+uint32_t
+isl_gen6_calc_back_to_back_total_h(const struct isl_extent4d *phys_level0_sa,
+   const struct isl_extent3d *image_align_sa,
+   enum isl_dim_layout dim_layout,
+   enum isl_tiling tiling, uint32_t levels)
+{
+   assert(tiling == ISL_TILING_W ||
+  tiling == ISL_TILING_HIZ); 
+   const uint32_t tile_align_h = tiling == ISL_TILING_W ? 64 : 32;
+
+   uint32_t total_h = 0;
+   for (unsigned i = 0; i < levels; ++i) {
+  const unsigned d = dim_layout == ISL_DIM_LAYOUT_GEN4_3D ?
+ isl_minify(phys_level0_sa->depth, i) :
+ phys_level0_sa->array_len;
+  const unsigned h = isl_minify(phys_level0_sa->height, i);
+  total_h += d * isl_align_npot(h, image_align_sa->h);
+
+  /* Align on tile boundary so that driver can offset without intra-tile
+   * offsets.
+   */
+  total_h = isl_align(total_h, tile_align_h);
+   }
+
+   return total_h;
+}
-- 
2.9.3

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[Mesa-dev] [v2 20/39] i965/hiz/gen6: Use isl back-to-back layout

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 11 +++-
 src/mesa/drivers/dri/i965/brw_tex_layout.c| 56 --
 src/mesa/drivers/dri/i965/gen6_depth_state.c  | 18 +++---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 84 ---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 12 
 5 files changed, 27 insertions(+), 154 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index c0aa139..0235681 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -241,9 +241,14 @@ blorp_surf_for_miptree(struct brw_context *brw,
 /* gen6 requires the HiZ buffer to be manually offset to the
  * right location. 
  */
-surf->aux_addr.offset = brw_hiz_all_slices_at_each_lod_offset(
-   >surf->phys_level0_sa, surf->surf->dim,
-   surf->surf->levels, surf->surf->format, *level);
+uint32_t x_offset_sa, y_offset_sa;
+get_image_offset_sa_gen6_back_to_back(>hiz_buf->surf,
+  *level, 0, 0, 
+  _offset_sa, _offset_sa);
+assert(x_offset_sa == 0);
+
+surf->aux_addr.offset = y_offset_sa * mt->hiz_buf->surf.row_pitch;
+assert(surf->aux_addr.offset % 4096 == 0);
 
 /* In depth state setup only surf->aux_surf.row_pitch gets
  * consulted. Otherwise surf->aux_surf is ignored and there is
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c 
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index b58a846..deac692 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -236,62 +236,6 @@ brw_get_mipmap_total_width(unsigned w0, unsigned 
num_levels, unsigned halign)
return ALIGN(MAX2(w0, w1 + w2), halign);
 }
 
-uint32_t
-brw_hiz_all_slices_at_each_lod_offset(
-   const struct isl_extent4d *phys_level0_sa,
-   enum isl_surf_dim dim, unsigned num_levels,
-   enum isl_format format, unsigned level)
-{
-   const uint32_t cpp = isl_format_get_layout(format)->bpb / 8;
-   const uint32_t halign = 128 / cpp;
-   const uint32_t valign = 32;
-   const uint32_t level_x = all_slices_at_each_lod_x_offset(
-   phys_level0_sa->width, halign, level);
-   const uint32_t level_y = all_slices_at_each_lod_y_offset(
-   phys_level0_sa, dim, valign, level);
-   const uint32_t pitch = brw_get_mipmap_total_width(
- phys_level0_sa->width, num_levels, halign) * cpp;
-
-   return level_y * pitch + level_x / halign * 4096;
-}
-
-uint32_t
-brw_all_slices_at_each_lod_total_height(
-   const struct isl_extent4d *phys_level0_sa,
-   enum isl_surf_dim dim, isl_surf_usage_flags_t usage,
-   unsigned last_level, unsigned valign)
-{
-   /* The 965's sampler lays cachelines out according to how accesses
-* in the texture surfaces run, so they may be "vertical" through
-* memory.  As a result, the docs say in Surface Padding Requirements:
-* Sampling Engine Surfaces that two extra rows of padding are required.
-*/
-   const unsigned extra_padding = usage & ISL_SURF_USAGE_CUBE_BIT ? 2 : 0;
-   const unsigned second_level_y = all_slices_at_each_lod_y_offset(
-  phys_level0_sa, dim, valign, 1);
-
-   /* Second level would be just below first, and its start position is equal
-* to the aligned size needed for the the first.
-*/
-   if (last_level == 0)
-  return second_level_y + extra_padding;
-
-   const unsigned last_level_y = all_slices_at_each_lod_y_offset(
-phys_level0_sa, dim, valign, last_level);
-   const unsigned second_level_h =
-  phys_level0_sa->array_len *
-  ALIGN(minify(phys_level0_sa->height, 1), valign);
-   const unsigned last_level_h =
-  phys_level0_sa->array_len *
-  ALIGN(minify(phys_level0_sa->height, last_level), valign);
-
-   /* Choose the taller of the two: end of the second or end of the last. */
-   const unsigned total_h = MAX2(second_level_y + second_level_h,
- last_level_y + last_level_h);
-
-   return ALIGN(total_h, valign) + extra_padding;
-}
-
 static void
 brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
 {
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c 
b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index e057c3e..16fb209 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -162,15 +162,15 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
   if (hiz) {
  assert(depth_mt);
 
- struct isl_surf temp_surf;
- intel_miptree_get_isl_surf(brw, mt, _surf);
-
- /* Main and hiz surfaces agree on the base level 

[Mesa-dev] [v2 16/39] i965/blorp: Use hiz surface instead of creating copy

[Topi Pohjolainen]

Reviewed-by: Jason Ekstrand 
Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 25 -
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c |  6 ++
 2 files changed, 18 insertions(+), 13 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 01d7dda..c0aa139 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -115,7 +115,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
uint32_t safe_aux_usage,
unsigned *level,
unsigned start_layer, unsigned num_layers,
-   struct isl_surf tmp_surfs[2])
+   struct isl_surf tmp_surfs[1])
 {
if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
@@ -173,12 +173,12 @@ blorp_surf_for_miptree(struct brw_context *brw,
 
surf->aux_usage = intel_miptree_get_aux_isl_usage(brw, mt);
 
-   struct isl_surf *aux_surf = _surfs[1];
+   struct isl_surf *aux_surf = NULL;
 
if (mt->mcs_buf)
-  *aux_surf = mt->mcs_buf->surf;
-   else
-  intel_miptree_get_aux_isl_surf(brw, mt, surf->aux_usage, aux_surf);
+  aux_surf = >mcs_buf->surf;
+   else if (mt->hiz_buf)
+  aux_surf = >hiz_buf->surf;
 
if (surf->aux_usage != ISL_AUX_USAGE_NONE) {
   if (surf->aux_usage == ISL_AUX_USAGE_HIZ) {
@@ -249,7 +249,6 @@ blorp_surf_for_miptree(struct brw_context *brw,
  * consulted. Otherwise surf->aux_surf is ignored and there is
  * no need to adjust it.  See blorp_emit_depth_stencil_config().
  */
-aux_surf->row_pitch = mt->hiz_buf->pitch;
  }
   }
} else {
@@ -392,12 +391,12 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
  (1 << ISL_AUX_USAGE_CCS_D);
}
 
-   struct isl_surf tmp_surfs[4];
+   struct isl_surf tmp_surfs[2];
struct blorp_surf src_surf, dst_surf;
blorp_surf_for_miptree(brw, _surf, src_mt, false, src_usage_flags,
   _level, src_layer, 1, _surfs[0]);
blorp_surf_for_miptree(brw, _surf, dst_mt, true, dst_usage_flags,
-  _level, dst_layer, 1, _surfs[2]);
+  _level, dst_layer, 1, _surfs[1]);
 
struct isl_swizzle src_isl_swizzle = {
   .r = swizzle_to_scs(GET_SWZ(src_swizzle, 0)),
@@ -437,7 +436,7 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
dst_mt->num_samples, _mesa_get_format_name(dst_mt->format), dst_mt,
dst_level, dst_layer, dst_x, dst_y);
 
-   struct isl_surf tmp_surfs[4];
+   struct isl_surf tmp_surfs[2];
struct blorp_surf src_surf, dst_surf;
blorp_surf_for_miptree(brw, _surf, src_mt, false,
   (1 << ISL_AUX_USAGE_MCS) |
@@ -446,7 +445,7 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
blorp_surf_for_miptree(brw, _surf, dst_mt, true,
   (1 << ISL_AUX_USAGE_MCS) |
   (1 << ISL_AUX_USAGE_CCS_E),
-  _level, dst_layer, 1, _surfs[2]);
+  _level, dst_layer, 1, _surfs[1]);
 
struct blorp_batch batch;
blorp_batch_init(>blorp, , brw, 0);
@@ -852,7 +851,7 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
const unsigned num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
 
/* We can't setup the blorp_surf until we've allocated the MCS above */
-   struct isl_surf isl_tmp[2];
+   struct isl_surf isl_tmp[1];
struct blorp_surf surf;
unsigned level = irb->mt_level;
blorp_surf_for_miptree(brw, , irb->mt, true,
@@ -950,7 +949,7 @@ brw_blorp_resolve_color(struct brw_context *brw, struct 
intel_mipmap_tree *mt,
 
const mesa_format format = _mesa_get_srgb_format_linear(mt->format);
 
-   struct isl_surf isl_tmp[2];
+   struct isl_surf isl_tmp[1];
struct blorp_surf surf;
blorp_surf_for_miptree(brw, , mt, true,
   (1 << ISL_AUX_USAGE_CCS_E) |
@@ -995,7 +994,7 @@ gen6_blorp_hiz_exec(struct brw_context *brw, struct 
intel_mipmap_tree *mt,
 {
assert(intel_miptree_level_has_hiz(mt, level));
 
-   struct isl_surf isl_tmp[2];
+   struct isl_surf isl_tmp[1];
struct blorp_surf surf;
blorp_surf_for_miptree(brw, , mt, true, (1 << ISL_AUX_USAGE_HIZ),
   , layer, 1, isl_tmp);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index f42ad76..2f711ed 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -320,6 +320,12 @@ all_slices_at_each_lod_aux_create(struct brw_context *brw,
 */
buf->qpitch = 0;
 
+   /* Blorp depth state setup relies on ISL surface. Fortunately only
+* ::row_pitch gets consulted while the rest gets ignored.
+* See 

[Mesa-dev] [v2 12/39] i965/miptree: Refactor ISL aux usage resolver

[Topi Pohjolainen]

Reviewed-by: Jason Ekstrand 
Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.c|  4 +-
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  3 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 47 +++-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h|  9 -
 4 files changed, 41 insertions(+), 22 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index c72d433..3433a8e 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -171,8 +171,10 @@ blorp_surf_for_miptree(struct brw_context *brw,
   *level = 0;
}
 
+   surf->aux_usage = intel_miptree_get_aux_isl_usage(brw, mt);
+
struct isl_surf *aux_surf = _surfs[1];
-   intel_miptree_get_aux_isl_surf(brw, mt, aux_surf, >aux_usage);
+   intel_miptree_get_aux_isl_surf(brw, mt, surf->aux_usage, aux_surf);
 
if (surf->aux_usage != ISL_AUX_USAGE_NONE) {
   if (surf->aux_usage == ISL_AUX_USAGE_HIZ) {
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 6b078c0..bd64c67 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -139,7 +139,8 @@ brw_emit_surface_state(struct brw_context *brw,
enum isl_aux_usage aux_usage = ISL_AUX_USAGE_NONE;
if ((mt->mcs_buf || intel_miptree_sample_with_hiz(brw, mt)) &&
!(flags & INTEL_AUX_BUFFER_DISABLED)) {
-  intel_miptree_get_aux_isl_surf(brw, mt, _surf_s, _usage);
+  aux_usage = intel_miptree_get_aux_isl_usage(brw, mt);
+  intel_miptree_get_aux_isl_surf(brw, mt, aux_usage, _surf_s);
   aux_surf = _surf_s;
 
   if (mt->mcs_buf) {
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 8a676ed..f67c2d0 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -3370,6 +3370,32 @@ intel_miptree_get_isl_surf(struct brw_context *brw,
   surf->usage |= ISL_SURF_USAGE_CUBE_BIT;
 }
 
+enum isl_aux_usage
+intel_miptree_get_aux_isl_usage(const struct brw_context *brw,
+const struct intel_mipmap_tree *mt)
+{
+   if (mt->hiz_buf)
+  return ISL_AUX_USAGE_HIZ;
+
+   if (!mt->mcs_buf)
+  return ISL_AUX_USAGE_NONE;
+
+   if (mt->num_samples > 1) {
+  assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS);
+  return ISL_AUX_USAGE_MCS;
+   }
+
+   if (intel_miptree_is_lossless_compressed(brw, mt)) {
+  assert(brw->gen >= 9);
+  return ISL_AUX_USAGE_CCS_E;
+   }
+
+   if ((mt->aux_disable & INTEL_AUX_DISABLE_CCS) == 0)
+  return ISL_AUX_USAGE_CCS_D;
+
+   unreachable("Invalid MCS miptree");
+}
+
 /* WARNING: THE SURFACE CREATED BY THIS FUNCTION IS NOT COMPLETE AND CANNOT BE
  * USED FOR ANY REAL CALCULATIONS.  THE ONLY VALID USE OF SUCH A SURFACE IS TO
  * PASS IT INTO isl_surf_fill_state.
@@ -3377,32 +3403,17 @@ intel_miptree_get_isl_surf(struct brw_context *brw,
 void
 intel_miptree_get_aux_isl_surf(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
-   struct isl_surf *surf,
-   enum isl_aux_usage *usage)
+   enum isl_aux_usage usage,
+   struct isl_surf *surf)
 {
uint32_t aux_pitch, aux_qpitch;
if (mt->mcs_buf) {
   aux_pitch = mt->mcs_buf->pitch;
   aux_qpitch = mt->mcs_buf->qpitch;
-
-  if (mt->num_samples > 1) {
- assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS);
- *usage = ISL_AUX_USAGE_MCS;
-  } else if (intel_miptree_is_lossless_compressed(brw, mt)) {
- assert(brw->gen >= 9);
- *usage = ISL_AUX_USAGE_CCS_E;
-  } else if ((mt->aux_disable & INTEL_AUX_DISABLE_CCS) == 0) {
- *usage = ISL_AUX_USAGE_CCS_D;
-  } else {
- unreachable("Invalid MCS miptree");
-  }
} else if (mt->hiz_buf) {
   aux_pitch = mt->hiz_buf->aux_base.pitch;
   aux_qpitch = mt->hiz_buf->aux_base.qpitch;
-
-  *usage = ISL_AUX_USAGE_HIZ;
} else {
-  *usage = ISL_AUX_USAGE_NONE;
   return;
}
 
@@ -3410,7 +3421,7 @@ intel_miptree_get_aux_isl_surf(struct brw_context *brw,
intel_miptree_get_isl_surf(brw, mt, surf);
 
/* Figure out the format and tiling of the auxiliary surface */
-   switch (*usage) {
+   switch (usage) {
case ISL_AUX_USAGE_NONE:
   unreachable("Invalid auxiliary usage");
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index c951e1a..3c9c2fe 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -773,11 +773,16 @@ void
 intel_miptree_get_isl_surf(struct brw_context *brw,
const 

[Mesa-dev] [v2 14/39] i965/miptree: Drop MIPTREE_LAYOUT_ACCELERATED_UPLOAD in mcs init

[Topi Pohjolainen]

because buffers get unconditionally initialised by cpu writing.

Reviewed-by: Jason Ekstrand 
Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index ce6002d..3a0f42f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1486,7 +1486,12 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
assert(temp_mcs_surf.size &&
   (temp_mcs_surf.size % temp_mcs_surf.row_pitch == 0));
 
-   const uint32_t alloc_flags = BO_ALLOC_FOR_RENDER;
+   /* Buffer needs to be initialised requiring the buffer to be immediately
+* mapped to cpu space for writing. Therefore do not use the gpu access
+* flag which can cause an unnecessary delay if the backing pages happened
+* to be just used by the GPU.
+*/
+   const uint32_t alloc_flags = 0;
mt->mcs_buf = intel_alloc_aux_buffer(brw, "mcs-miptree",
 _main_surf, _mcs_surf,
 alloc_flags, mt);
-- 
2.9.3

___
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mesa-dev@lists.freedesktop.org
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[Mesa-dev] [v2 13/39] i965/miptree: Use ISL for MCS layouts

[Topi Pohjolainen]

Reviewed-by: Jason Ekstrand 
Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.c|   6 +-
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |   8 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 101 ---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h|   2 +
 4 files changed, 29 insertions(+), 88 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 3433a8e..e995759 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -174,7 +174,11 @@ blorp_surf_for_miptree(struct brw_context *brw,
surf->aux_usage = intel_miptree_get_aux_isl_usage(brw, mt);
 
struct isl_surf *aux_surf = _surfs[1];
-   intel_miptree_get_aux_isl_surf(brw, mt, surf->aux_usage, aux_surf);
+
+   if (mt->mcs_buf)
+  *aux_surf = mt->mcs_buf->surf;
+   else
+  intel_miptree_get_aux_isl_surf(brw, mt, surf->aux_usage, aux_surf);
 
if (surf->aux_usage != ISL_AUX_USAGE_NONE) {
   if (surf->aux_usage == ISL_AUX_USAGE_HIZ) {
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index bd64c67..68bc605 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -140,13 +140,17 @@ brw_emit_surface_state(struct brw_context *brw,
if ((mt->mcs_buf || intel_miptree_sample_with_hiz(brw, mt)) &&
!(flags & INTEL_AUX_BUFFER_DISABLED)) {
   aux_usage = intel_miptree_get_aux_isl_usage(brw, mt);
-  intel_miptree_get_aux_isl_surf(brw, mt, aux_usage, _surf_s);
-  aux_surf = _surf_s;
 
   if (mt->mcs_buf) {
+ aux_surf = >mcs_buf->surf;
+
+ assert(mt->mcs_buf->offset == 0);
  aux_bo = mt->mcs_buf->bo;
  aux_offset = mt->mcs_buf->bo->offset64 + mt->mcs_buf->offset;
   } else {
+ intel_miptree_get_aux_isl_surf(brw, mt, aux_usage, _surf_s);
+ aux_surf = _surf_s;
+
  aux_bo = mt->hiz_buf->aux_base.bo;
  aux_offset = mt->hiz_buf->aux_base.bo->offset64;
   }
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index f67c2d0..ce6002d 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1430,56 +1430,6 @@ intel_miptree_init_mcs(struct brw_context *brw,
 }
 
 static struct intel_miptree_aux_buffer *
-intel_mcs_miptree_buf_create(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- mesa_format format,
- unsigned mcs_width,
- unsigned mcs_height,
- uint32_t layout_flags)
-{
-   struct intel_miptree_aux_buffer *buf = calloc(sizeof(*buf), 1);
-   struct intel_mipmap_tree *temp_mt;
-
-   if (!buf)
-  return NULL;
-
-   /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
-*
-* "The MCS surface must be stored as Tile Y."
-*/
-   layout_flags |= MIPTREE_LAYOUT_TILING_Y;
-   temp_mt = miptree_create(brw,
-mt->target,
-format,
-mt->first_level,
-mt->last_level,
-mcs_width,
-mcs_height,
-mt->logical_depth0,
-0 /* num_samples */,
-layout_flags);
-   if (!temp_mt) {
-  free(buf);
-  return NULL;
-   }
-
-   buf->bo = temp_mt->bo;
-   buf->offset = temp_mt->offset;
-   buf->size = temp_mt->total_height * temp_mt->pitch;
-   buf->pitch = temp_mt->pitch;
-   buf->qpitch = temp_mt->qpitch;
-
-   /* Just hang on to the BO which backs the AUX buffer; the rest of the 
miptree
-* structure should go away. We use miptree create simply as a means to make
-* sure all the constraints for the buffer are satisfied.
-*/
-   brw_bo_reference(temp_mt->bo);
-   intel_miptree_release(_mt);
-
-   return buf;
-}
-
-static struct intel_miptree_aux_buffer *
 intel_alloc_aux_buffer(struct brw_context *brw,
const char *name,
const struct isl_surf *main_surf,
@@ -1510,6 +1460,7 @@ intel_alloc_aux_buffer(struct brw_context *brw,
}
 
assert(pitch == buf->pitch);
+   buf->surf = *aux_surf;
 
return buf;
 }
@@ -1523,42 +1474,22 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
assert(mt->mcs_buf == NULL);
assert((mt->aux_disable & INTEL_AUX_DISABLE_MCS) == 0);
 
-   /* Choose the correct format for the MCS buffer.  All that really matters
-* is that we allocate the right buffer size, since we'll always be
-* accessing this miptree using MCS-specific hardware mechanisms, which
-* infer the correct format based on num_samples.
+   

[Mesa-dev] [v2 15/39] i965/miptree/gen7+: Use ISL for HIZ layouts

[Topi Pohjolainen]

Reviewed-by: Jason Ekstrand 
Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.c|   6 +-
 src/mesa/drivers/dri/i965/brw_misc_state.c   |   4 +-
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |   4 +-
 src/mesa/drivers/dri/i965/gen6_depth_state.c |   4 +-
 src/mesa/drivers/dri/i965/gen7_misc_state.c  |   5 +-
 src/mesa/drivers/dri/i965/gen8_depth_state.c |   6 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 263 ---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h|  11 +-
 8 files changed, 59 insertions(+), 244 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index e995759..01d7dda 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -234,8 +234,8 @@ blorp_surf_for_miptree(struct brw_context *brw,
   } else {
  assert(surf->aux_usage == ISL_AUX_USAGE_HIZ);
 
- surf->aux_addr.buffer = mt->hiz_buf->aux_base.bo;
- surf->aux_addr.offset = mt->hiz_buf->aux_base.offset;
+ surf->aux_addr.buffer = mt->hiz_buf->bo;
+ surf->aux_addr.offset = mt->hiz_buf->offset;
 
  if (brw->gen == 6) {
 /* gen6 requires the HiZ buffer to be manually offset to the
@@ -249,7 +249,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
  * consulted. Otherwise surf->aux_surf is ignored and there is
  * no need to adjust it.  See blorp_emit_depth_stencil_config().
  */
-aux_surf->row_pitch = mt->hiz_buf->aux_base.pitch;
+aux_surf->row_pitch = mt->hiz_buf->pitch;
  }
   }
} else {
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 83c1810..9dd6ab8 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -633,8 +633,8 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
  assert(depth_mt);
 BEGIN_BATCH(3);
 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
-OUT_BATCH(depth_mt->hiz_buf->aux_base.pitch - 1);
-OUT_RELOC(depth_mt->hiz_buf->aux_base.bo,
+OUT_BATCH(depth_mt->hiz_buf->pitch - 1);
+OUT_RELOC(depth_mt->hiz_buf->bo,
   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
   brw->depthstencil.hiz_offset);
 ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 68bc605..8811d62 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -151,8 +151,8 @@ brw_emit_surface_state(struct brw_context *brw,
  intel_miptree_get_aux_isl_surf(brw, mt, aux_usage, _surf_s);
  aux_surf = _surf_s;
 
- aux_bo = mt->hiz_buf->aux_base.bo;
- aux_offset = mt->hiz_buf->aux_base.bo->offset64;
+ aux_bo = mt->hiz_buf->bo;
+ aux_offset = mt->hiz_buf->bo->offset64;
   }
 
   /* We only really need a clear color if we also have an auxiliary
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c 
b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index 9bc1daf..e057c3e 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -174,8 +174,8 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
 
 BEGIN_BATCH(3);
 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
-OUT_BATCH(depth_mt->hiz_buf->aux_base.pitch - 1);
-OUT_RELOC(depth_mt->hiz_buf->aux_base.bo,
+OUT_BATCH(depth_mt->hiz_buf->pitch - 1);
+OUT_RELOC(depth_mt->hiz_buf->bo,
   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
   offset);
 ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c 
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index af9be66..8e87222 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -146,13 +146,12 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
   ADVANCE_BATCH();
} else {
   assert(depth_mt);
-  struct intel_miptree_hiz_buffer *hiz_buf = depth_mt->hiz_buf;
 
   BEGIN_BATCH(3);
   OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
   OUT_BATCH((mocs << 25) |
-(hiz_buf->aux_base.pitch - 1));
-  OUT_RELOC(hiz_buf->aux_base.bo,
+(depth_mt->hiz_buf->pitch - 1));
+  OUT_RELOC(depth_mt->hiz_buf->bo,
 I915_GEM_DOMAIN_RENDER,
 I915_GEM_DOMAIN_RENDER,
 0);
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c 
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 6105c3e..8210e7c 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ 

[Mesa-dev] [v2 10/39] i965/gen6: Allocate hiz directly without miptree

[Topi Pohjolainen]

Reviewed-by: Jason Ekstrand 
Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 13 +---
 src/mesa/drivers/dri/i965/gen6_depth_state.c  |  8 -
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 46 +--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  5 ---
 4 files changed, 16 insertions(+), 56 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 63bda23..c72d433 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -231,11 +231,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
  surf->aux_addr.buffer = mt->hiz_buf->aux_base.bo;
  surf->aux_addr.offset = mt->hiz_buf->aux_base.offset;
 
- struct intel_mipmap_tree *hiz_mt = mt->hiz_buf->mt;
- if (hiz_mt) {
-assert(brw->gen == 6 &&
-   hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD);
-
+ if (brw->gen == 6) {
 /* gen6 requires the HiZ buffer to be manually offset to the
  * right location. 
  */
@@ -243,13 +239,6 @@ blorp_surf_for_miptree(struct brw_context *brw,
>surf->phys_level0_sa, surf->surf->dim,
surf->surf->levels, surf->surf->format, *level);
 
-assert(surf->aux_addr.offset ==
-   intel_miptree_get_aligned_offset(
-  hiz_mt,
-  hiz_mt->level[*level].level_x,
-  hiz_mt->level[*level].level_y));
-assert(mt->hiz_buf->aux_base.pitch == hiz_mt->pitch);
-
 /* In depth state setup only surf->aux_surf.row_pitch gets
  * consulted. Otherwise surf->aux_surf is ignored and there is
  * no need to adjust it.  See blorp_emit_depth_stencil_config().
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c 
b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index f709ee7..9bc1daf 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -161,9 +161,6 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
   /* Emit hiz buffer. */
   if (hiz) {
  assert(depth_mt);
- struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_buf->mt;
-
- assert(hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD);
 
  struct isl_surf temp_surf;
  intel_miptree_get_isl_surf(brw, mt, _surf);
@@ -175,11 +172,6 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
 _surf.phys_level0_sa, temp_surf.dim, temp_surf.levels,
 temp_surf.format, lod);
 
- assert(offset == intel_miptree_get_aligned_offset(
- hiz_mt,
- hiz_mt->level[lod].level_x,
- hiz_mt->level[lod].level_y));
-
 BEGIN_BATCH(3);
 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 OUT_BATCH(depth_mt->hiz_buf->aux_base.pitch - 1);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index d5267df..684c371 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -288,6 +288,7 @@ static void
 all_slices_at_each_lod_aux_init(struct brw_context *brw,
 const struct intel_mipmap_tree *mt,
 unsigned halign_bytes, unsigned valign,
+uint32_t tiling, const char *name,
 struct intel_miptree_aux_buffer *buf)
 {
const uint32_t format = translate_tex_format(brw, mt->format, false);
@@ -315,6 +316,12 @@ all_slices_at_each_lod_aux_init(struct brw_context *brw,
 * hardware qpitch setting of hiz on gen6.
 */
buf->qpitch = 0;
+
+   unsigned pitch = buf->pitch;
+   buf->bo = brw_bo_alloc_tiled(brw->bufmgr, name, total_w, total_h, cpp,
+tiling, , BO_ALLOC_FOR_RENDER);
+ 
+   assert(!buf->bo || pitch == buf->pitch);
 }
 
 /**
@@ -938,10 +945,7 @@ intel_miptree_hiz_buffer_free(struct 
intel_miptree_hiz_buffer *hiz_buf)
if (hiz_buf == NULL)
   return;
 
-   if (hiz_buf->mt)
-  intel_miptree_release(_buf->mt);
-   else
-  brw_bo_unreference(hiz_buf->aux_base.bo);
+   brw_bo_unreference(hiz_buf->aux_base.bo);
 
free(hiz_buf);
 }
@@ -1818,39 +1822,19 @@ intel_hiz_miptree_buf_create(struct brw_context *brw,
  struct intel_mipmap_tree *mt)
 {
struct intel_miptree_hiz_buffer *buf = calloc(sizeof(*buf), 1);
-   uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
-
-   if (brw->gen == 6)
-  layout_flags |= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD;
-
if (!buf)
   return NULL;
 
-   layout_flags |= MIPTREE_LAYOUT_TILING_ANY;
-   buf->mt = intel_miptree_create(brw,
-  

[Mesa-dev] [v2 11/39] i965/miptree: Refactor aux surface allocation

[Topi Pohjolainen]

Reviewed-by: Jason Ekstrand  (v1)
Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 60 +--
 1 file changed, 39 insertions(+), 21 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 684c371..8a676ed 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1479,6 +1479,41 @@ intel_mcs_miptree_buf_create(struct brw_context *brw,
return buf;
 }
 
+static struct intel_miptree_aux_buffer *
+intel_alloc_aux_buffer(struct brw_context *brw,
+   const char *name,
+   const struct isl_surf *main_surf,
+   const struct isl_surf *aux_surf,
+   uint32_t alloc_flags,
+   struct intel_mipmap_tree *mt)
+{
+   struct intel_miptree_aux_buffer *buf = calloc(sizeof(*buf), 1);
+   if (!buf)
+  return false;
+
+   buf->size = aux_surf->size;
+   buf->pitch = aux_surf->row_pitch;
+   buf->qpitch = isl_surf_get_array_pitch_sa_rows(aux_surf);
+
+   unsigned pitch = aux_surf->row_pitch;
+
+   /* ISL has stricter set of alignment rules then the drm allocator.
+* Therefore one can pass the ISL dimensions in terms of bytes instead of
+* trying to recalculate based on different format block sizes.
+*/
+   buf->bo = brw_bo_alloc_tiled(brw->bufmgr, name,
+buf->pitch, buf->size / buf->pitch,
+1, I915_TILING_Y, , alloc_flags);
+   if (!buf->bo) {
+  free(buf);
+  return NULL;
+   }
+
+   assert(pitch == buf->pitch);
+
+   return buf;
+}
+
 static bool
 intel_miptree_alloc_mcs(struct brw_context *brw,
 struct intel_mipmap_tree *mt,
@@ -1560,14 +1595,6 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
assert(temp_ccs_surf.size &&
   (temp_ccs_surf.size % temp_ccs_surf.row_pitch == 0));
 
-   struct intel_miptree_aux_buffer *buf = calloc(sizeof(*buf), 1);
-   if (!buf)
-  return false;
-
-   buf->size = temp_ccs_surf.size;
-   buf->pitch = temp_ccs_surf.row_pitch;
-   buf->qpitch = isl_surf_get_array_pitch_sa_rows(_ccs_surf);
-
/* In case of compression mcs buffer needs to be initialised requiring the
 * buffer to be immediately mapped to cpu space for writing. Therefore do
 * not use the gpu access flag which can cause an unnecessary delay if the
@@ -1575,20 +1602,11 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context 
*brw,
 */
const uint32_t alloc_flags =
   is_lossless_compressed ? 0 : BO_ALLOC_FOR_RENDER;
-
-   /* ISL has stricter set of alignment rules then the drm allocator.
-* Therefore one can pass the ISL dimensions in terms of bytes instead of
-* trying to recalculate based on different format block sizes.
-*/
-   buf->bo = brw_bo_alloc_tiled(brw->bufmgr, "ccs-miptree",
-buf->pitch, buf->size / buf->pitch,
-1, I915_TILING_Y, >pitch, alloc_flags);
-   if (!buf->bo) {
-  free(buf);
+   mt->mcs_buf = intel_alloc_aux_buffer(brw, "ccs-miptree",
+_main_surf, _ccs_surf,
+alloc_flags, mt);
+   if (!mt->mcs_buf)
   return false;
-   }
-
-   mt->mcs_buf = buf;
 
/* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
 * used for lossless compression which requires similar initialisation
-- 
2.9.3

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[Mesa-dev] [v2 07/39] i965/gen6: Drop miptrees in depth/stencil offset resolvers

[Topi Pohjolainen]

Reviewed-by: Jason Ekstrand 
Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.c |  8 
 src/mesa/drivers/dri/i965/brw_tex_layout.c| 19 +--
 src/mesa/drivers/dri/i965/gen6_depth_state.c  |  4 ++--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  5 +
 4 files changed, 8 insertions(+), 28 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 5a9d21c..fda3e6f 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -162,10 +162,9 @@ blorp_surf_for_miptree(struct brw_context *brw,
* it any further.  See blorp_emit_depth_stencil_config().
*/
   surf->addr.offset += brw_stencil_all_slices_at_each_lod_offset(
-  surf->surf, mt, *level);
+  surf->surf, *level);
 
-  assert(brw_stencil_all_slices_at_each_lod_offset(
-surf->surf, mt, *level) ==
+  assert(brw_stencil_all_slices_at_each_lod_offset(surf->surf, *level) ==
  mt->level[*level].level_y * mt->pitch +
  mt->level[*level].level_x * 64);
 
@@ -248,7 +247,8 @@ blorp_surf_for_miptree(struct brw_context *brw,
  */
 surf->aux_addr.offset = brw_hiz_all_slices_at_each_lod_offset(
>surf->phys_level0_sa, surf->surf->dim,
-   surf->surf->levels, surf->surf->format, hiz_mt, *level);
+   surf->surf->levels, surf->surf->format, *level);
+
 assert(surf->aux_addr.offset ==
intel_miptree_get_aligned_offset(
   hiz_mt,
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c 
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index e8eedd7..76d6ba0 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -198,11 +198,8 @@ all_slices_at_each_lod_y_offset(const struct isl_extent4d 
*phys_level0_sa,
 
 uint32_t
 brw_stencil_all_slices_at_each_lod_offset(const struct isl_surf *surf,
-  const struct intel_mipmap_tree *mt,
   unsigned level)
 {
-   assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD);
-
const unsigned halign = 64;
const unsigned valign = 64;
const unsigned level_x = all_slices_at_each_lod_x_offset(
@@ -210,9 +207,6 @@ brw_stencil_all_slices_at_each_lod_offset(const struct 
isl_surf *surf,
const unsigned level_y = all_slices_at_each_lod_y_offset(
   >phys_level0_sa, surf->dim, valign, level);
 
-   assert(level_x == mt->level[level].level_x);
-   assert(level_y == mt->level[level].level_y);
-
/* From Vol 2a, 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
 *The pitch must be set to 2x the value computed based on width, as
 *the stencil buffer is stored with two rows interleaved.
@@ -223,8 +217,6 @@ brw_stencil_all_slices_at_each_lod_offset(const struct 
isl_surf *surf,
 */
const unsigned two_rows_interleaved_pitch = surf->row_pitch / 2;
 
-   assert(two_rows_interleaved_pitch == mt->pitch);
-
return level_y * two_rows_interleaved_pitch + level_x * 64;
 }
 
@@ -248,12 +240,8 @@ uint32_t
 brw_hiz_all_slices_at_each_lod_offset(
const struct isl_extent4d *phys_level0_sa,
enum isl_surf_dim dim, unsigned num_levels,
-   enum isl_format format,
-   const struct intel_mipmap_tree *mt,
-   unsigned level)
+   enum isl_format format, unsigned level)
 {
-   assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD);
-
const uint32_t cpp = isl_format_get_layout(format)->bpb / 8;
const uint32_t halign = 128 / cpp;
const uint32_t valign = 32;
@@ -264,11 +252,6 @@ brw_hiz_all_slices_at_each_lod_offset(
const uint32_t pitch = brw_get_mipmap_total_width(
  phys_level0_sa->width, num_levels, halign) * cpp;
 
-   assert(level_x == mt->level[level].level_x);
-   assert(level_y == mt->level[level].level_y);
-   assert(pitch == mt->pitch);
-   assert(cpp == mt->cpp);
-
return level_y * pitch + level_x / halign * 4096;
 }
 
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c 
b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index e84ecac..f709ee7 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -173,7 +173,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
   */
  const uint32_t offset = brw_hiz_all_slices_at_each_lod_offset(
 _surf.phys_level0_sa, temp_surf.dim, temp_surf.levels,
-temp_surf.format, hiz_mt, lod);
+temp_surf.format, lod);
 
  assert(offset == intel_miptree_get_aligned_offset(
  hiz_mt,
@@ -206,7 +206,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
 intel_miptree_get_isl_surf(brw, stencil_mt, _surf);
 
 

[Mesa-dev] [v2 09/39] i965/gen6/hiz: Add direct buffer size resolver

[Topi Pohjolainen]

The apparent hack adding unconditionally two lines into cube
maps is taken directly from align_cube().

v2: Apply the cube map hack also for non-mipmapped. But apply
it only for cube-map, not for cube-map-array to keep things
as they were (use mt->target == GL_TEXTURE_CUBE_MAP instead
of _mesa_is_cube_map_texture(mt->target)).
v3: Take vertical alignment as argument allowing to be re-used
for stencil. Also introduce all_slices_at_each_lod_aux_init()
that hiz and stencil can both share.

Reviewed-by: Jason Ekstrand  (v1)
Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_tex_layout.c| 37 +
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 47 ++-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  6 
 3 files changed, 82 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c 
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 76d6ba0..b58a846 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -255,6 +255,43 @@ brw_hiz_all_slices_at_each_lod_offset(
return level_y * pitch + level_x / halign * 4096;
 }
 
+uint32_t
+brw_all_slices_at_each_lod_total_height(
+   const struct isl_extent4d *phys_level0_sa,
+   enum isl_surf_dim dim, isl_surf_usage_flags_t usage,
+   unsigned last_level, unsigned valign)
+{
+   /* The 965's sampler lays cachelines out according to how accesses
+* in the texture surfaces run, so they may be "vertical" through
+* memory.  As a result, the docs say in Surface Padding Requirements:
+* Sampling Engine Surfaces that two extra rows of padding are required.
+*/
+   const unsigned extra_padding = usage & ISL_SURF_USAGE_CUBE_BIT ? 2 : 0;
+   const unsigned second_level_y = all_slices_at_each_lod_y_offset(
+  phys_level0_sa, dim, valign, 1);
+
+   /* Second level would be just below first, and its start position is equal
+* to the aligned size needed for the the first.
+*/
+   if (last_level == 0)
+  return second_level_y + extra_padding;
+
+   const unsigned last_level_y = all_slices_at_each_lod_y_offset(
+phys_level0_sa, dim, valign, last_level);
+   const unsigned second_level_h =
+  phys_level0_sa->array_len *
+  ALIGN(minify(phys_level0_sa->height, 1), valign);
+   const unsigned last_level_h =
+  phys_level0_sa->array_len *
+  ALIGN(minify(phys_level0_sa->height, last_level), valign);
+
+   /* Choose the taller of the two: end of the second or end of the last. */
+   const unsigned total_h = MAX2(second_level_y + second_level_h,
+ last_level_y + last_level_h);
+
+   return ALIGN(total_h, valign) + extra_padding;
+}
+
 static void
 brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
 {
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 54ef1ba..d5267df 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -284,6 +284,38 @@ intel_depth_format_for_depthstencil_format(mesa_format 
format) {
}
 }
 
+static void
+all_slices_at_each_lod_aux_init(struct brw_context *brw,
+const struct intel_mipmap_tree *mt,
+unsigned halign_bytes, unsigned valign,
+struct intel_miptree_aux_buffer *buf)
+{
+   const uint32_t format = translate_tex_format(brw, mt->format, false);
+   const unsigned cpp = isl_format_get_layout(format)->bpb / 8;
+   const unsigned halign = halign_bytes / cpp;
+   const enum isl_surf_dim dim = get_isl_surf_dim(mt->target);
+   const struct isl_extent4d phys_level0_sa = {
+ { mt->physical_width0 }, 
+ { mt->physical_height0 },  
+ { dim == ISL_SURF_DIM_3D ? mt->physical_depth0 : 1 },
+ { dim == ISL_SURF_DIM_3D ? 1 : mt->physical_depth0 } };
+   const isl_surf_usage_flags_t usage =
+  mt->target == GL_TEXTURE_CUBE_MAP ? ISL_SURF_USAGE_CUBE_BIT : 0;
+   const unsigned total_h = brw_all_slices_at_each_lod_total_height(
+  _level0_sa, dim, usage, mt->last_level, valign);
+   const unsigned total_w = brw_get_mipmap_total_width(
+  phys_level0_sa.width, mt->last_level + 1, halign);
+
+   buf->pitch = total_w * cpp;
+   buf->size = total_h * buf->pitch;
+
+   /* On gen6 hiz is unconditionally laid out packing all slices
+* at each level-of-detail (LOD). This means there is no valid qpitch
+* setting. In fact, this is ignored when hardware is setup - there is no
+* hardware qpitch setting of hiz on gen6.
+*/
+   buf->qpitch = 0;
+}
 
 /**
  * @param for_bo Indicates that the caller is
@@ -1810,16 +1842,15 @@ intel_hiz_miptree_buf_create(struct brw_context *brw,
   return NULL;
}
 
+   const unsigned halign_bytes = 128;
+   const unsigned 

[Mesa-dev] [v2 08/39] i965/blorp/gen6: Set aux pitch directly

[Topi Pohjolainen]

dropping dependency to intel_miptree_get_aux_isl_surf().

Reviewed-by: Jason Ekstrand 
Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index fda3e6f..63bda23 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -238,12 +238,6 @@ blorp_surf_for_miptree(struct brw_context *brw,
 
 /* gen6 requires the HiZ buffer to be manually offset to the
  * right location. 
- * In depth state setup only surf->aux_surf.row_pitch gets
- * consulted. Otherwise surf->aux_surf is ignored and there is
- * no need to adjust it.  See blorp_emit_depth_stencil_config().
- *
- * surf->aux_surf.row_pitch in turn is set by
- * intel_miptree_get_aux_isl_surf().
  */
 surf->aux_addr.offset = brw_hiz_all_slices_at_each_lod_offset(
>surf->phys_level0_sa, surf->surf->dim,
@@ -254,7 +248,13 @@ blorp_surf_for_miptree(struct brw_context *brw,
   hiz_mt,
   hiz_mt->level[*level].level_x,
   hiz_mt->level[*level].level_y));
-assert(hiz_mt->pitch == aux_surf->row_pitch);
+assert(mt->hiz_buf->aux_base.pitch == hiz_mt->pitch);
+
+/* In depth state setup only surf->aux_surf.row_pitch gets
+ * consulted. Otherwise surf->aux_surf is ignored and there is
+ * no need to adjust it.  See blorp_emit_depth_stencil_config().
+ */
+aux_surf->row_pitch = mt->hiz_buf->aux_base.pitch;
  }
   }
} else {
-- 
2.9.3

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[Mesa-dev] [v2 06/39] i965/blorp/gen6: Use on-demand stencil/hiz offset resolvers

[Topi Pohjolainen]

Reviewed-by: Jason Ekstrand 
Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 21 -
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index bb40885..5a9d21c 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -161,8 +161,14 @@ blorp_surf_for_miptree(struct brw_context *brw,
* consulted. Otherwise surf is ignored and there is no need to adjust
* it any further.  See blorp_emit_depth_stencil_config().
*/
-  surf->addr.offset += (mt->level[*level].level_y * mt->pitch +
-mt->level[*level].level_x * 64);
+  surf->addr.offset += brw_stencil_all_slices_at_each_lod_offset(
+  surf->surf, mt, *level);
+
+  assert(brw_stencil_all_slices_at_each_lod_offset(
+surf->surf, mt, *level) ==
+ mt->level[*level].level_y * mt->pitch +
+ mt->level[*level].level_x * 64);
+
   *level = 0;
}
 
@@ -240,9 +246,14 @@ blorp_surf_for_miptree(struct brw_context *brw,
  * surf->aux_surf.row_pitch in turn is set by
  * intel_miptree_get_aux_isl_surf().
  */
-surf->aux_addr.offset = intel_miptree_get_aligned_offset(hiz_mt,
-   hiz_mt->level[*level].level_x,
-   hiz_mt->level[*level].level_y);
+surf->aux_addr.offset = brw_hiz_all_slices_at_each_lod_offset(
+   >surf->phys_level0_sa, surf->surf->dim,
+   surf->surf->levels, surf->surf->format, hiz_mt, *level);
+assert(surf->aux_addr.offset ==
+   intel_miptree_get_aligned_offset(
+  hiz_mt,
+  hiz_mt->level[*level].level_x,
+  hiz_mt->level[*level].level_y));
 assert(hiz_mt->pitch == aux_surf->row_pitch);
  }
   }
-- 
2.9.3

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[Mesa-dev] [v2 05/39] i965/gen6: Calculate hiz offset on demand

[Topi Pohjolainen]

This is kept on purpose in i965. It can be moved to ISL if it
is needed in vulkan.

Pointers to miptrees are given solely for verification purposes.
These will be dropped in following patches.

Reviewed-by: Jason Ekstrand 
Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_tex_layout.c| 44 +++
 src/mesa/drivers/dri/i965/gen6_depth_state.c  | 18 ---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 11 +++
 3 files changed, 69 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c 
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 3fbb78f..e8eedd7 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -228,6 +228,50 @@ brw_stencil_all_slices_at_each_lod_offset(const struct 
isl_surf *surf,
return level_y * two_rows_interleaved_pitch + level_x * 64;
 }
 
+uint32_t
+brw_get_mipmap_total_width(unsigned w0, unsigned num_levels, unsigned halign)
+{
+   /* If there is not level two, no adjustment is needed. */
+   if (num_levels < 2)
+  return ALIGN(w0, halign);
+
+   const uint32_t w1 = ALIGN(minify(w0, 1), halign);
+   const uint32_t w2 = minify(w0, 2);
+
+   /* Levels one and two sit side-by-side below level zero. Due to alignment
+* of level one levels one and two may require more space than level zero.
+*/
+   return ALIGN(MAX2(w0, w1 + w2), halign);
+}
+
+uint32_t
+brw_hiz_all_slices_at_each_lod_offset(
+   const struct isl_extent4d *phys_level0_sa,
+   enum isl_surf_dim dim, unsigned num_levels,
+   enum isl_format format,
+   const struct intel_mipmap_tree *mt,
+   unsigned level)
+{
+   assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD);
+
+   const uint32_t cpp = isl_format_get_layout(format)->bpb / 8;
+   const uint32_t halign = 128 / cpp;
+   const uint32_t valign = 32;
+   const uint32_t level_x = all_slices_at_each_lod_x_offset(
+   phys_level0_sa->width, halign, level);
+   const uint32_t level_y = all_slices_at_each_lod_y_offset(
+   phys_level0_sa, dim, valign, level);
+   const uint32_t pitch = brw_get_mipmap_total_width(
+ phys_level0_sa->width, num_levels, halign) * cpp;
+
+   assert(level_x == mt->level[level].level_x);
+   assert(level_y == mt->level[level].level_y);
+   assert(pitch == mt->pitch);
+   assert(cpp == mt->cpp);
+
+   return level_y * pitch + level_x / halign * 4096;
+}
+
 static void
 brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
 {
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c 
b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index a055c10..e84ecac 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -165,10 +165,20 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
 
  assert(hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD);
 
- const uint32_t offset = intel_miptree_get_aligned_offset(
-hiz_mt,
-hiz_mt->level[lod].level_x,
-hiz_mt->level[lod].level_y);
+ struct isl_surf temp_surf;
+ intel_miptree_get_isl_surf(brw, mt, _surf);
+
+ /* Main and hiz surfaces agree on the base level dimensions and
+  * format. Therefore one can calculate against the main surface.
+  */
+ const uint32_t offset = brw_hiz_all_slices_at_each_lod_offset(
+_surf.phys_level0_sa, temp_surf.dim, temp_surf.levels,
+temp_surf.format, hiz_mt, lod);
+
+ assert(offset == intel_miptree_get_aligned_offset(
+ hiz_mt,
+ hiz_mt->level[lod].level_x,
+ hiz_mt->level[lod].level_y));
 
 BEGIN_BATCH(3);
 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 8f938ee..6dea82b 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -974,10 +974,21 @@ brw_miptree_get_vertical_slice_pitch(const struct 
brw_context *brw,
  unsigned level);
 
 uint32_t
+brw_get_mipmap_total_width(unsigned w0, unsigned num_levels, unsigned halign);
+
+uint32_t
 brw_stencil_all_slices_at_each_lod_offset(const struct isl_surf *surf,
   const struct intel_mipmap_tree *mt,
   uint32_t level);
 
+uint32_t
+brw_hiz_all_slices_at_each_lod_offset(
+   const struct isl_extent4d *phys_level0_sa, 
+   enum isl_surf_dim dim, unsigned num_levels,
+   enum isl_format format,
+   const struct intel_mipmap_tree *mt,
+   unsigned level);
+
 bool
 brw_miptree_layout(struct brw_context *brw,

[Mesa-dev] [v2 04/39] i965/gen6: Calculate stencil offset on demand

[Topi Pohjolainen]

This is kept on purpose in i965. It can be moved to ISL if it
is needed in vulkan.

Pointers to miptrees are given solely for verification purposes.
These will be dropped in following patches.

Reviewed-by: Jason Ekstrand 
Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_tex_layout.c| 65 +++
 src/mesa/drivers/dri/i965/gen6_depth_state.c  | 14 +++---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  5 +++
 3 files changed, 78 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c 
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index bfa8afa..3fbb78f 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -163,6 +163,71 @@ gen9_miptree_layout_1d(struct intel_mipmap_tree *mt)
}
 }
 
+static unsigned
+all_slices_at_each_lod_x_offset(unsigned w0, unsigned align, unsigned level)
+{
+   const unsigned w = level >= 2 ? minify(w0, 1) : 0;
+   return ALIGN(w, align);
+}
+
+static unsigned
+all_slices_at_each_lod_y_offset(const struct isl_extent4d *phys_level0_sa,
+enum isl_surf_dim dim, unsigned align,
+unsigned level)
+{
+   unsigned y = 0;
+
+   /* Add vertical space taken by lower levels one by one. Levels one and two
+* are side-by-side just below level zero. Levels three and greater are
+* stacked one after another below level two.
+*/
+   for (unsigned i = 1; i <= level; ++i) {
+  const unsigned d = dim == ISL_SURF_DIM_3D ?
+ minify(phys_level0_sa->depth, i - 1) :
+ phys_level0_sa->array_len;
+
+  /* Levels two and greater are stacked just below level zero. */
+  if (i != 2) {
+ const unsigned h = minify(phys_level0_sa->height, i - 1);
+ y += d * ALIGN(h, align);
+  }
+   }
+
+   return y;
+}
+
+uint32_t
+brw_stencil_all_slices_at_each_lod_offset(const struct isl_surf *surf,
+  const struct intel_mipmap_tree *mt,
+  unsigned level)
+{
+   assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD);
+
+   const unsigned halign = 64;
+   const unsigned valign = 64;
+   const unsigned level_x = all_slices_at_each_lod_x_offset(
+  surf->phys_level0_sa.width, halign, level);
+   const unsigned level_y = all_slices_at_each_lod_y_offset(
+  >phys_level0_sa, surf->dim, valign, level);
+
+   assert(level_x == mt->level[level].level_x);
+   assert(level_y == mt->level[level].level_y);
+
+   /* From Vol 2a, 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
+*The pitch must be set to 2x the value computed based on width, as
+*the stencil buffer is stored with two rows interleaved.
+*
+* While ISL surface stores the pitch expected by hardware, the offset
+* into individual slices needs to be calculated as if rows are
+* interleaved.
+*/
+   const unsigned two_rows_interleaved_pitch = surf->row_pitch / 2;
+
+   assert(two_rows_interleaved_pitch == mt->pitch);
+
+   return level_y * two_rows_interleaved_pitch + level_x * 64;
+}
+
 static void
 brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
 {
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c 
b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index cda66e8..a055c10 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -192,12 +192,14 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
  if (stencil_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
 assert(stencil_mt->format == MESA_FORMAT_S_UINT8);
 
-/* Note: we can't compute the stencil offset using
- * intel_region_get_aligned_offset(), because stencil_region
- * claims that the region is untiled even though it's W tiled.
- */
-offset = stencil_mt->level[lod].level_y * stencil_mt->pitch +
- stencil_mt->level[lod].level_x * 64;
+struct isl_surf temp_surf;
+intel_miptree_get_isl_surf(brw, stencil_mt, _surf);
+
+offset = brw_stencil_all_slices_at_each_lod_offset(
+_surf, stencil_mt, lod);
+assert(offset ==
+stencil_mt->level[lod].level_y * stencil_mt->pitch +
+stencil_mt->level[lod].level_x * 64);
  }
 
 BEGIN_BATCH(3);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 4bc30a2..8f938ee 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -973,6 +973,11 @@ brw_miptree_get_vertical_slice_pitch(const struct 
brw_context *brw,
  const struct intel_mipmap_tree *mt,
  unsigned level);
 
+uint32_t

[Mesa-dev] [v2 03/39] i965/blorp/gen6: Drop unnecessary stencil/hiz surf dimension adjust

[Topi Pohjolainen]

Hardware state setup only needs offset and pitch and ignores the
rest.

Reviewed-by: Jason Ekstrand 
Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 57 ---
 1 file changed, 20 insertions(+), 37 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index b69cb4f..bb40885 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -108,36 +108,6 @@ brw_blorp_init(struct brw_context *brw)
 }
 
 static void
-apply_gen6_stencil_hiz_offset(struct isl_surf *surf,
-  struct intel_mipmap_tree *mt,
-  uint32_t lod,
-  uint32_t *offset)
-{
-   assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD);
-
-   if (mt->format == MESA_FORMAT_S_UINT8) {
-  /* Note: we can't compute the stencil offset using
-   * intel_miptree_get_aligned_offset(), because the miptree
-   * claims that the region is untiled even though it's W tiled.
-   */
-  *offset = mt->level[lod].level_y * mt->pitch +
-mt->level[lod].level_x * 64;
-   } else {
-  *offset = intel_miptree_get_aligned_offset(mt,
- mt->level[lod].level_x,
- mt->level[lod].level_y);
-   }
-
-   surf->logical_level0_px.width = minify(surf->logical_level0_px.width, lod);
-   surf->logical_level0_px.height = minify(surf->logical_level0_px.height, 
lod);
-   surf->phys_level0_sa.width = minify(surf->phys_level0_sa.width, lod);
-   surf->phys_level0_sa.height = minify(surf->phys_level0_sa.height, lod);
-   surf->levels = 1;
-   surf->array_pitch_el_rows =
-  ALIGN(surf->phys_level0_sa.height, surf->image_alignment_el.height);
-}
-
-static void
 blorp_surf_for_miptree(struct brw_context *brw,
struct blorp_surf *surf,
struct intel_mipmap_tree *mt,
@@ -182,10 +152,17 @@ blorp_surf_for_miptree(struct brw_context *brw,
* hacks inside the i965 driver.
*
* See also gen6_depth_stencil_state.c
+   *
+   * Note: we can't compute the stencil offset using
+   * intel_miptree_get_aligned_offset(), because the miptree
+   * claims that the region is untiled even though it's W tiled.
+   *
+   * In stencil state setup only surf->row_pitch and surf->addr get
+   * consulted. Otherwise surf is ignored and there is no need to adjust
+   * it any further.  See blorp_emit_depth_stencil_config().
*/
-  uint32_t offset;
-  apply_gen6_stencil_hiz_offset(_surfs[0], mt, *level, );
-  surf->addr.offset += offset;
+  surf->addr.offset += (mt->level[*level].level_y * mt->pitch +
+mt->level[*level].level_x * 64);
   *level = 0;
}
 
@@ -255,11 +232,17 @@ blorp_surf_for_miptree(struct brw_context *brw,
hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD);
 
 /* gen6 requires the HiZ buffer to be manually offset to the
- * right location.  We could fixup the surf but it doesn't
- * matter since most of those fields don't matter.
+ * right location. 
+ * In depth state setup only surf->aux_surf.row_pitch gets
+ * consulted. Otherwise surf->aux_surf is ignored and there is
+ * no need to adjust it.  See blorp_emit_depth_stencil_config().
+ *
+ * surf->aux_surf.row_pitch in turn is set by
+ * intel_miptree_get_aux_isl_surf().
  */
-apply_gen6_stencil_hiz_offset(aux_surf, hiz_mt, *level,
-  >aux_addr.offset);
+surf->aux_addr.offset = intel_miptree_get_aligned_offset(hiz_mt,
+   hiz_mt->level[*level].level_x,
+   hiz_mt->level[*level].level_y);
 assert(hiz_mt->pitch == aux_surf->row_pitch);
  }
   }
-- 
2.9.3

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[Mesa-dev] [v2 02/39] i965/gen6: Remove dead code in hiz surface setup

[Topi Pohjolainen]

In intel_hiz_miptree_buf_create() the miptree is unconditionally
created with MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD.

Reviewed-by: Jason Ekstrand 
Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/gen6_depth_state.c | 13 ++---
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c 
b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index 0ff2407..cda66e8 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -162,14 +162,13 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
   if (hiz) {
  assert(depth_mt);
  struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_buf->mt;
- uint32_t offset = 0;
 
- if (hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
-offset = intel_miptree_get_aligned_offset(
-hiz_mt,
-hiz_mt->level[lod].level_x,
-hiz_mt->level[lod].level_y);
- }
+ assert(hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD);
+
+ const uint32_t offset = intel_miptree_get_aligned_offset(
+hiz_mt,
+hiz_mt->level[lod].level_x,
+hiz_mt->level[lod].level_y);
 
 BEGIN_BATCH(3);
 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
-- 
2.9.3

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[Mesa-dev] [v2 01/39] i965/dbg: Add means for forcing stencil sampling using y-tiled copy

[Topi Pohjolainen]

While gen >= 8 can sample w-tiled stencil surfaces just fine, this
option allows testing of the legacy behavior even on gen8+.

Signed-off-by: Topi Pohjolainen 
---
 src/intel/blorp/blorp.c  |  4 +++-
 src/intel/blorp/blorp_blit.c |  9 +++--
 src/intel/common/gen_debug.c |  1 +
 src/intel/common/gen_debug.h |  1 +
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  5 +++--
 src/mesa/drivers/dri/i965/gen8_depth_state.c |  3 +++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 10 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h|  3 +++
 8 files changed, 30 insertions(+), 6 deletions(-)

diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c
index 0b2395d..14a13f3 100644
--- a/src/intel/blorp/blorp.c
+++ b/src/intel/blorp/blorp.c
@@ -28,6 +28,7 @@
 #include "blorp_priv.h"
 #include "compiler/brw_compiler.h"
 #include "compiler/brw_nir.h"
+#include "common/gen_debug.h"
 
 void
 blorp_init(struct blorp_context *blorp, void *driver_ctx,
@@ -84,7 +85,8 @@ brw_blorp_surface_info_init(struct blorp_context *blorp,
} else if (surf->surf->usage & ISL_SURF_USAGE_STENCIL_BIT) {
   assert(surf->surf->format == ISL_FORMAT_R8_UINT);
   /* Prior to Broadwell, we can't render to R8_UINT */
-  if (blorp->isl_dev->info->gen < 8)
+  if (blorp->isl_dev->info->gen < 8 ||
+  unlikely(INTEL_DEBUG & DEBUG_R8_STENCIL))
  format = ISL_FORMAT_R8_UNORM;
}
 
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 691564c..8e3fc31 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -22,6 +22,7 @@
  */
 
 #include "compiler/nir/nir_builder.h"
+#include "common/gen_debug.h"
 
 #include "blorp_priv.h"
 
@@ -,7 +1112,9 @@ brw_blorp_build_nir_shader(struct blorp_context *blorp, 
void *mem_ctx,
 
/* Render target and texture hardware don't support W tiling until Gen8. */
const bool rt_tiled_w = false;
-   const bool tex_tiled_w = devinfo->gen >= 8 && key->src_tiled_w;
+   const bool can_sample_w_tiled =
+  devinfo->gen >= 8 && !unlikely(INTEL_DEBUG & DEBUG_R8_STENCIL);
+   const bool tex_tiled_w = can_sample_w_tiled && key->src_tiled_w;
 
/* The address that data will be written to is determined by the
 * coordinates supplied to the WM thread and the tiling and sample count of
@@ -1766,7 +1769,9 @@ try_blorp_blit(struct blorp_batch *batch,
   }
}
 
-   if (devinfo->gen < 8 && params->src.surf.tiling == ISL_TILING_W) {
+   const bool needs_y_tiled_stencil =
+  devinfo->gen <= 7 || unlikely(INTEL_DEBUG & DEBUG_R8_STENCIL);
+   if (needs_y_tiled_stencil && params->src.surf.tiling == ISL_TILING_W) {
   /* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled.
* Broadwell adds support for sampling from stencil.
*
diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_debug.c
index be6fcdb..48aefc3 100644
--- a/src/intel/common/gen_debug.c
+++ b/src/intel/common/gen_debug.c
@@ -84,6 +84,7 @@ static const struct debug_control debug_control[] = {
{ "norbc",   DEBUG_NO_RBC },
{ "nohiz",   DEBUG_NO_HIZ },
{ "color",   DEBUG_COLOR },
+   { "r8_stencil",  DEBUG_R8_STENCIL},
{ NULL,0 }
 };
 
diff --git a/src/intel/common/gen_debug.h b/src/intel/common/gen_debug.h
index c0b74ea..582fd5b 100644
--- a/src/intel/common/gen_debug.h
+++ b/src/intel/common/gen_debug.h
@@ -82,6 +82,7 @@ extern uint64_t INTEL_DEBUG;
 #define DEBUG_NO_RBC  (1ull << 38)
 #define DEBUG_NO_HIZ  (1ull << 39)
 #define DEBUG_COLOR   (1ull << 40)
+#define DEBUG_R8_STENCIL  (1ull << 41)
 
 #ifdef HAVE_ANDROID_PLATFORM
 #define LOG_TAG "INTEL-MESA"
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 49383c7..6b078c0 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -597,14 +597,15 @@ brw_update_texture_surface(struct gl_context *ctx,
   }
 
   if (obj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL) 
{
- if (brw->gen <= 7) {
+ if (intel_miptree_wants_r8_stencil(brw)) {
 assert(mt->r8stencil_mt && 
!mt->stencil_mt->r8stencil_needs_update);
 mt = mt->r8stencil_mt;
  } else {
 mt = mt->stencil_mt;
  }
  format = ISL_FORMAT_R8_UINT;
-  } else if (brw->gen <= 7 && mt->format == MESA_FORMAT_S_UINT8) {
+  } else if (intel_miptree_wants_r8_stencil(brw) &&
+ mt->format == MESA_FORMAT_S_UINT8) {
  assert(mt->r8stencil_mt && !mt->r8stencil_needs_update);
  mt = mt->r8stencil_mt;
  format = ISL_FORMAT_R8_UINT;
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c 
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 2a19b79..6105c3e 

[Mesa-dev] i965: Use isl for hiz and stencil

[Topi Pohjolainen]

Patches 1-17 are revision that

  - rework hiz on gen6 to use on-demand offset calculator allowing
one to drop dependency to miptree structure and 
  - rework all auxiliary surfaces to be created against isl directly.

Patches 18 and 19 introduce new surface layout in ISL. This is called
back-to-back and similar to layout ALL_SLICES_AT_EACH_LOD found in
i965 for gen6 hiz and stencil. This layout stacks slices for each level
after one and other, or back to back. All slices ate each lod is almost
the same except that it places levels one and two side-by-side trying
to preserve space. Back-to-back wastes a little more memory but aligns
each level on page boundary simplifying driver logic.

Patch 20 switches gen6 hiz to use back-to-back.

Patches 22-37 prepare i965 driver to work with miptrees based on isl.
Patches 38 and 39 start to use isl for stencil surfaces and effectively
switches to back-to-back stencil layout on gen6.
Patch 25 is mostly unneeded but it doesn't hurt and it provides me the
tiling converter I need in patch 36.

There are two uglies, patches 21 and 37. Perhaps Nanley, Jason or Chad
can help me with 21...

Jason: You have reviewed most of 1-17, and I don't think they have
   changed that much.

Rafael: I have conflicting patches with your series addressing depth
and stencil state emission. We should try to land your patches
first and then I'll rebase this on top.


If we agree on the approach here, I'll continue with gen4/5 depth
surface alignment workaround aiming to base depth surfaces also on
isl. That should allow me to start using isl state emitter for
depth-hiz-stencil.

CC: Jason Ekstrand 
CC: Nanley Chery 
CC: Chad Versace 
CC: Rafael Antognolli 

Topi Pohjolainen (39):
  i965/dbg: Add means for forcing stencil sampling using y-tiled copy
  i965/gen6: Remove dead code in hiz surface setup
  i965/blorp/gen6: Drop unnecessary stencil/hiz surf dimension adjust
  i965/gen6: Calculate stencil offset on demand
  i965/gen6: Calculate hiz offset on demand
  i965/blorp/gen6: Use on-demand stencil/hiz offset resolvers
  i965/gen6: Drop miptrees in depth/stencil offset resolvers
  i965/blorp/gen6: Set aux pitch directly
  i965/gen6/hiz: Add direct buffer size resolver
  i965/gen6: Allocate hiz directly without miptree
  i965/miptree: Refactor aux surface allocation
  i965/miptree: Refactor ISL aux usage resolver
  i965/miptree: Use ISL for MCS layouts
  i965/miptree: Drop MIPTREE_LAYOUT_ACCELERATED_UPLOAD in mcs init
  i965/miptree/gen7+: Use ISL for HIZ layouts
  i965/blorp: Use hiz surface instead of creating copy
  i965: Use stored hiz surface instead of creating copy
  intel/isl/gen6: Add offsetting support for back-to-back layouts
  intel/isl/gen6: Add size calculator for back-to-back layouts
  i965/hiz/gen6: Use isl back-to-back layout
  intel/isl/gen6/hack: Use hiz vertical alignment of 16 instead of 8
  i965/miptree: Add support for resolving offsets using isl
  i965/blorp: Add support for isl based miptrees
  i965: Prepare up/downsampling for isl based miptrees
  i965: Prepare blit engine for isl based miptrees
  i965: Prepare image validation for isl based miptrees
  i965: Refactor miptree to isl converter and adjustment
  i965: Prepare tex, img and rt state emission for isl based miptrees
  i965: Prepare slice validator for isl based miptrees
  i965: Prepare framebuffer validator for isl based miptrees
  i965/tex: Prepare image update for isl based miptrees
  i965: Prepare texture validator for isl based miptrees
  i965: Prepare slice copy for isl based miptrees
  i965/gen7: Prepare depth state emission for isl based miptrees
  i965/gen8+: Prepare depth state emission for isl based miptrees
  i965: Add isl based miptree creator
  intel/isl/gen7/hack: Use stencil vertical alignment of 8 instead of 4
  i965/miptree: Represent w-tiled stencil surfaces with isl
  i965/miptree: Represent y-tiled stencil copies with isl

 src/intel/blorp/blorp.c  |   4 +-
 src/intel/blorp/blorp_blit.c |  11 +-
 src/intel/common/gen_debug.c |   1 +
 src/intel/common/gen_debug.h |   1 +
 src/intel/isl/isl.c  |  55 +-
 src/intel/isl/isl.h  |  20 +-
 src/intel/isl/isl_gen6.c | 109 +++
 src/intel/isl/isl_gen7.c |   6 +-
 src/intel/isl/isl_storage_image.c|   3 +-
 src/mesa/drivers/dri/i965/brw_blorp.c| 124 ++--
 src/mesa/drivers/dri/i965/brw_misc_state.c   |  16 +-
 src/mesa/drivers/dri/i965/brw_tex_layout.c   |  16 +
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 114 ++--
 src/mesa/drivers/dri/i965/gen6_depth_state.c |  50 +-
 src/mesa/drivers/dri/i965/gen7_misc_state.c  |  31 +-
 src/mesa/drivers/dri/i965/gen8_depth_state.c |  47 +-
 

[Mesa-dev] [PATCH] glsl: rename image_* qualifiers to memory_*

[Samuel Pitoiset]

It doesn't make sense to prefix them with 'image' because
they are called "Memory Qualifiers" and they can be applied
to members of storage buffer blocks.

Signed-off-by: Samuel Pitoiset 
---
 src/compiler/glsl/ast_function.cpp | 10 +++---
 src/compiler/glsl/ast_to_hir.cpp   | 54 +++---
 src/compiler/glsl/builtin_functions.cpp| 30 -
 src/compiler/glsl/builtin_variables.cpp| 10 +++---
 src/compiler/glsl/glsl_to_nir.cpp  | 10 +++---
 src/compiler/glsl/ir.cpp   | 20 +--
 src/compiler/glsl/ir.h | 12 +++
 src/compiler/glsl/link_uniforms.cpp|  4 +--
 src/compiler/glsl/lower_ubo_reference.cpp  | 12 +++
 src/compiler/glsl_types.cpp| 20 +--
 src/compiler/glsl_types.h  | 18 +-
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp |  6 ++--
 12 files changed, 103 insertions(+), 103 deletions(-)

diff --git a/src/compiler/glsl/ast_function.cpp 
b/src/compiler/glsl/ast_function.cpp
index 1b90937ec8..bee5f0588b 100644
--- a/src/compiler/glsl/ast_function.cpp
+++ b/src/compiler/glsl/ast_function.cpp
@@ -107,35 +107,35 @@ verify_image_parameter(YYLTYPE *loc, 
_mesa_glsl_parse_state *state,
 *  qualifiers. [...] It is legal to have additional qualifiers
 *  on a formal parameter, but not to have fewer."
 */
-   if (actual->data.image_coherent && !formal->data.image_coherent) {
+   if (actual->data.memory_coherent && !formal->data.memory_coherent) {
   _mesa_glsl_error(loc, state,
"function call parameter `%s' drops "
"`coherent' qualifier", formal->name);
   return false;
}
 
-   if (actual->data.image_volatile && !formal->data.image_volatile) {
+   if (actual->data.memory_volatile && !formal->data.memory_volatile) {
   _mesa_glsl_error(loc, state,
"function call parameter `%s' drops "
"`volatile' qualifier", formal->name);
   return false;
}
 
-   if (actual->data.image_restrict && !formal->data.image_restrict) {
+   if (actual->data.memory_restrict && !formal->data.memory_restrict) {
   _mesa_glsl_error(loc, state,
"function call parameter `%s' drops "
"`restrict' qualifier", formal->name);
   return false;
}
 
-   if (actual->data.image_read_only && !formal->data.image_read_only) {
+   if (actual->data.memory_read_only && !formal->data.memory_read_only) {
   _mesa_glsl_error(loc, state,
"function call parameter `%s' drops "
"`readonly' qualifier", formal->name);
   return false;
}
 
-   if (actual->data.image_write_only && !formal->data.image_write_only) {
+   if (actual->data.memory_write_only && !formal->data.memory_write_only) {
   _mesa_glsl_error(loc, state,
"function call parameter `%s' drops "
"`writeonly' qualifier", formal->name);
diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index 20a0f11755..4cb62cdb23 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -86,17 +86,17 @@ public:
  return visit_continue;
 
   ir_variable *var = ir->variable_referenced();
-  /* We can have image_write_only set on both images and buffer variables,
+  /* We can have memory_write_only set on both images and buffer variables,
* but in the former there is a distinction between reads from
* the variable itself (write_only) and from the memory they point to
-   * (image_write_only), while in the case of buffer variables there is
+   * (memory_write_only), while in the case of buffer variables there is
* no such distinction, that is why this check here is limited to
* buffer variables alone.
*/
   if (!var || var->data.mode != ir_var_shader_storage)
  return visit_continue;
 
-  if (var->data.image_write_only) {
+  if (var->data.memory_write_only) {
  found = var;
  return visit_stop;
   }
@@ -947,11 +947,11 @@ do_assignment(exec_list *instructions, struct 
_mesa_glsl_parse_state *state,
  error_emitted = true;
   } else if (lhs_var != NULL && (lhs_var->data.read_only ||
  (lhs_var->data.mode == ir_var_shader_storage &&
-  lhs_var->data.image_read_only))) {
- /* We can have image_read_only set on both images and buffer 
variables,
+  lhs_var->data.memory_read_only))) {
+ /* We can have memory_read_only set on both images and buffer 
variables,
   * but in the former there is a distinction between assignments to
   * the variable itself (read_only) and to the memory they point to
-  * (image_read_only), while in the case of buffer variables there is
+  * 

Re: [Mesa-dev] [PATCH] st/glsl_to_tgsi: remove unrequired tgsi_get_opcode_info() call

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Wed, May 3, 2017 at 2:48 AM, Timothy Arceri  wrote:
> This is already set for the instruction at initialisation.
> ---
>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> index ce4a2cb..1e606d5 100644
> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> @@ -4652,21 +4652,21 @@ glsl_to_tgsi_visitor::simplify_cmp(void)
> unsigned outputWrites[VARYING_SLOT_TESS_MAX];
>
> memset(outputWrites, 0, sizeof(outputWrites));
>
> foreach_in_list(glsl_to_tgsi_instruction, inst, >instructions) {
>unsigned prevWriteMask = 0;
>
>/* Give up if we encounter relative addressing or flow control. */
>if (inst->dst[0].reladdr || inst->dst[0].reladdr2 ||
>inst->dst[1].reladdr || inst->dst[1].reladdr2 ||
> -  tgsi_get_opcode_info(inst->op)->is_branch ||
> +  inst->info->is_branch ||
>inst->op == TGSI_OPCODE_CONT ||
>inst->op == TGSI_OPCODE_END ||
>inst->op == TGSI_OPCODE_RET) {
>   break;
>}
>
>if (inst->dst[0].file == PROGRAM_OUTPUT) {
>   assert(inst->dst[0].index < (signed)ARRAY_SIZE(outputWrites));
>   prevWriteMask = outputWrites[inst->dst[0].index];
>   outputWrites[inst->dst[0].index] |= inst->dst[0].writemask;
> --
> 2.9.3
>
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[Mesa-dev] [PATCH] i965: Set modifier for imported and duplicated images

[Daniel Stone]

When a buffer is being created from FD or GEM flink import, the current
API makes no provision for passing modifier information along with this.
Set the modifier for such images to DRM_FORMAT_MOD_INVALID.

Also preserve the modifier when duplicating an image, as will be done by
GBM when importing from a wl_buffer.

This doubly tripped up Wayland, as the images would first have been
created (as wl_buffers) with a 0 modifier, and then lost what modifier
they would've had when being duplicated into gbm_bos.

This patch does not address the renderbuffer/texture targets, which
require more thought.

Signed-off-by: Daniel Stone 
Cc: Ben Widawsky 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 23a4bd6d6c..a729dd98c9 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -398,6 +398,7 @@ intel_create_image_from_name(__DRIscreen *dri_screen,
 else
cpp = _mesa_get_format_bytes(image->format);
 
+image->modifier = DRM_FORMAT_MOD_INVALID;
 image->width = width;
 image->height = height;
 image->pitch = pitch * cpp;
@@ -710,6 +711,7 @@ intel_dup_image(__DRIimage *orig_image, void *loaderPrivate)
image->planar_format   = orig_image->planar_format;
image->dri_format  = orig_image->dri_format;
image->format  = orig_image->format;
+   image->modifier= orig_image->modifier;
image->offset  = orig_image->offset;
image->width   = orig_image->width;
image->height  = orig_image->height;
@@ -805,6 +807,7 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
if (image == NULL)
   return NULL;
 
+   image->modifier = DRM_FORMAT_MOD_INVALID;
image->width = width;
image->height = height;
image->pitch = strides[0];
-- 
2.12.2

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[Mesa-dev] [PATCH] anv: anv_gem_mmap() returns MAP_FAILED as mapping error

[Samuel Iglesias Gonsálvez]

Take it into account when checking if the mapping failed.

Signed-off-by: Samuel Iglesias Gonsálvez 
---
 src/intel/vulkan/anv_allocator.c | 2 +-
 src/intel/vulkan/anv_image.c | 4 
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c
index 554ca4ac5f..6ab2da5d64 100644
--- a/src/intel/vulkan/anv_allocator.c
+++ b/src/intel/vulkan/anv_allocator.c
@@ -889,7 +889,7 @@ anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo 
*bo, uint32_t size)
assert(new_bo.size == pow2_size);
 
new_bo.map = anv_gem_mmap(pool->device, new_bo.gem_handle, 0, pow2_size, 0);
-   if (new_bo.map == NULL) {
+   if (new_bo.map == MAP_FAILED) {
   anv_gem_close(pool->device, new_bo.gem_handle);
   return vk_error(VK_ERROR_MEMORY_MAP_FAILED);
}
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 4874f2f3d3..d7d53f96a4 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -26,6 +26,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "anv_private.h"
 #include "util/debug.h"
@@ -369,6 +370,9 @@ VkResult anv_BindImageMemory(
   if (map == NULL)
  return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 
+  if (map == MAP_FAILED)
+ return vk_error(VK_ERROR_MEMORY_MAP_FAILED);
+
   memset(map, 0, image->aux_surface.isl.size);
 
   anv_gem_munmap(map, image->aux_surface.isl.size);
-- 
2.11.0

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Re: [Mesa-dev] [PATCH] st/glsl_to_tgsi: remove unrequired tgsi_get_opcode_info() call

[Samuel Pitoiset]

Reviewed-by: Samuel Pitoiset 

On 05/03/2017 02:48 AM, Timothy Arceri wrote:

This is already set for the instruction at initialisation.
---
  src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index ce4a2cb..1e606d5 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -4652,21 +4652,21 @@ glsl_to_tgsi_visitor::simplify_cmp(void)
 unsigned outputWrites[VARYING_SLOT_TESS_MAX];
  
 memset(outputWrites, 0, sizeof(outputWrites));
  
 foreach_in_list(glsl_to_tgsi_instruction, inst, >instructions) {

unsigned prevWriteMask = 0;
  
/* Give up if we encounter relative addressing or flow control. */

if (inst->dst[0].reladdr || inst->dst[0].reladdr2 ||
inst->dst[1].reladdr || inst->dst[1].reladdr2 ||
-  tgsi_get_opcode_info(inst->op)->is_branch ||
+  inst->info->is_branch ||
inst->op == TGSI_OPCODE_CONT ||
inst->op == TGSI_OPCODE_END ||
inst->op == TGSI_OPCODE_RET) {
   break;
}
  
if (inst->dst[0].file == PROGRAM_OUTPUT) {

   assert(inst->dst[0].index < (signed)ARRAY_SIZE(outputWrites));
   prevWriteMask = outputWrites[inst->dst[0].index];
   outputWrites[inst->dst[0].index] |= inst->dst[0].writemask;


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Re: [Mesa-dev] [PATCH 1/2] mesa: tidy up accum.h

[Samuel Pitoiset]

Reviewed-by: Samuel Pitoiset 

On 05/03/2017 05:38 AM, Timothy Arceri wrote:

These were unused.
---
  src/mesa/main/accum.h | 2 --
  1 file changed, 2 deletions(-)

diff --git a/src/mesa/main/accum.h b/src/mesa/main/accum.h
index a5665c7..ede2ecc 100644
--- a/src/mesa/main/accum.h
+++ b/src/mesa/main/accum.h
@@ -32,23 +32,21 @@
   * OTHER DEALINGS IN THE SOFTWARE.
   */
  
  
  
  #ifndef ACCUM_H

  #define ACCUM_H
  
  #include "main/glheader.h"
  
-struct _glapi_table;

  struct gl_context;
-struct gl_renderbuffer;
  
  extern void GLAPIENTRY

  _mesa_ClearAccum( GLfloat red, GLfloat green, GLfloat blue, GLfloat alpha );
  void GLAPIENTRY
  _mesa_Accum( GLenum op, GLfloat value );
  
  extern void

  _mesa_accum(struct gl_context *ctx, GLenum op, GLfloat value);
  
  extern void



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Re: [Mesa-dev] [PATCH 2/2] mesa: make _mesa_accum() static

[Samuel Pitoiset]

Why don't inline _mesa_acum()? Usually, we remove the '_' for static 
mesa functions right?


On 05/03/2017 05:38 AM, Timothy Arceri wrote:

---
  src/mesa/main/accum.c | 104 +-
  src/mesa/main/accum.h |   3 --
  2 files changed, 52 insertions(+), 55 deletions(-)

diff --git a/src/mesa/main/accum.c b/src/mesa/main/accum.c
index ef74468..919c441 100644
--- a/src/mesa/main/accum.c
+++ b/src/mesa/main/accum.c
@@ -46,71 +46,20 @@ _mesa_ClearAccum( GLfloat red, GLfloat green, GLfloat blue, 
GLfloat alpha )
 tmp[2] = CLAMP( blue,  -1.0F, 1.0F );
 tmp[3] = CLAMP( alpha, -1.0F, 1.0F );
  
 if (TEST_EQ_4V(tmp, ctx->Accum.ClearColor))

return;
  
 COPY_4FV( ctx->Accum.ClearColor, tmp );

  }
  
  
-void GLAPIENTRY

-_mesa_Accum( GLenum op, GLfloat value )
-{
-   GET_CURRENT_CONTEXT(ctx);
-   FLUSH_VERTICES(ctx, 0);
-
-   switch (op) {
-   case GL_ADD:
-   case GL_MULT:
-   case GL_ACCUM:
-   case GL_LOAD:
-   case GL_RETURN:
-  /* OK */
-  break;
-   default:
-  _mesa_error(ctx, GL_INVALID_ENUM, "glAccum(op)");
-  return;
-   }
-
-   if (ctx->DrawBuffer->Visual.haveAccumBuffer == 0) {
-  _mesa_error(ctx, GL_INVALID_OPERATION, "glAccum(no accum buffer)");
-  return;
-   }
-
-   if (ctx->DrawBuffer != ctx->ReadBuffer) {
-  /* See GLX_SGI_make_current_read or WGL_ARB_make_current_read,
-   * or GL_EXT_framebuffer_blit.
-   */
-  _mesa_error(ctx, GL_INVALID_OPERATION,
-  "glAccum(different read/draw buffers)");
-  return;
-   }
-
-   if (ctx->NewState)
-  _mesa_update_state(ctx);
-
-   if (ctx->DrawBuffer->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) {
-  _mesa_error(ctx, GL_INVALID_FRAMEBUFFER_OPERATION_EXT,
-  "glAccum(incomplete framebuffer)");
-  return;
-   }
-
-   if (ctx->RasterDiscard)
-  return;
-
-   if (ctx->RenderMode == GL_RENDER) {
-  _mesa_accum(ctx, op, value);
-   }
-}
-
-
  /**
   * Clear the accumulation buffer by mapping the renderbuffer and
   * writing the clear color to it.  Called by the driver's implementation
   * of the glClear function.
   */
  void
  _mesa_clear_accum_buffer(struct gl_context *ctx)
  {
 GLuint x, y, width, height;
 GLubyte *accMap;
@@ -429,21 +378,21 @@ accum_return(struct gl_context *ctx, GLfloat value,
 ctx->Driver.UnmapRenderbuffer(ctx, accRb);
  }
  
  
  
  /**

   * Software fallback for glAccum.  A hardware driver that supports
   * signed 16-bit color channels could implement hardware accumulation
   * operations, but no driver does so at this time.
   */
-void
+static void
  _mesa_accum(struct gl_context *ctx, GLenum op, GLfloat value)
  {
 GLint xpos, ypos, width, height;
  
 if (!ctx->DrawBuffer->Attachment[BUFFER_ACCUM].Renderbuffer) {

_mesa_warning(ctx, "Calling glAccum() without an accumulation buffer");
return;
 }
  
 if (!_mesa_check_conditional_render(ctx))

@@ -482,10 +431,61 @@ _mesa_accum(struct gl_context *ctx, GLenum op, GLfloat 
value)
 }
  }
  
  
  void

  _mesa_init_accum( struct gl_context *ctx )
  {
 /* Accumulate buffer group */
 ASSIGN_4V( ctx->Accum.ClearColor, 0.0, 0.0, 0.0, 0.0 );
  }
+
+
+void GLAPIENTRY
+_mesa_Accum( GLenum op, GLfloat value )
+{
+   GET_CURRENT_CONTEXT(ctx);
+   FLUSH_VERTICES(ctx, 0);
+
+   switch (op) {
+   case GL_ADD:
+   case GL_MULT:
+   case GL_ACCUM:
+   case GL_LOAD:
+   case GL_RETURN:
+  /* OK */
+  break;
+   default:
+  _mesa_error(ctx, GL_INVALID_ENUM, "glAccum(op)");
+  return;
+   }
+
+   if (ctx->DrawBuffer->Visual.haveAccumBuffer == 0) {
+  _mesa_error(ctx, GL_INVALID_OPERATION, "glAccum(no accum buffer)");
+  return;
+   }
+
+   if (ctx->DrawBuffer != ctx->ReadBuffer) {
+  /* See GLX_SGI_make_current_read or WGL_ARB_make_current_read,
+   * or GL_EXT_framebuffer_blit.
+   */
+  _mesa_error(ctx, GL_INVALID_OPERATION,
+  "glAccum(different read/draw buffers)");
+  return;
+   }
+
+   if (ctx->NewState)
+  _mesa_update_state(ctx);
+
+   if (ctx->DrawBuffer->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) {
+  _mesa_error(ctx, GL_INVALID_FRAMEBUFFER_OPERATION_EXT,
+  "glAccum(incomplete framebuffer)");
+  return;
+   }
+
+   if (ctx->RasterDiscard)
+  return;
+
+   if (ctx->RenderMode == GL_RENDER) {
+  _mesa_accum(ctx, op, value);
+   }
+}
diff --git a/src/mesa/main/accum.h b/src/mesa/main/accum.h
index ede2ecc..fe253a2 100644
--- a/src/mesa/main/accum.h
+++ b/src/mesa/main/accum.h
@@ -40,19 +40,16 @@
  #include "main/glheader.h"
  
  struct gl_context;
  
  extern void GLAPIENTRY

  _mesa_ClearAccum( GLfloat red, GLfloat green, GLfloat blue, GLfloat alpha );
  void GLAPIENTRY
  _mesa_Accum( GLenum op, GLfloat value );
  
  extern void

-_mesa_accum(struct gl_context *ctx, GLenum op, GLfloat value);
-
-extern void
  _mesa_clear_accum_buffer(struct gl_context *ctx);
  
  extern void

  _mesa_init_accum( 

Re: [Mesa-dev] [PATCH v3 00/13] anv: Implement VK_KHX_multiview

[Iago Toral]

Hi Jason

Sorry that I missed this. All the changes look good to me and I have
sent reviews for the patches that missed them. With this series we pass
all the multiview tests.

Iago

On Thu, 2017-04-27 at 09:31 -0700, Jason Ekstrand wrote:
> This is mostly a re-send of my earlier patches but there are a few
> changes.
> I think, at this point, that I'm ready to merge it assuming Iago is
> ok with
> the changes.  The important chages are:
> 
>  1. The lowering pass has been altered to take a view mask instead of
> a
> subpass.  The rest of the anv_pipeline code has also been
> modified to
> properly incorporate the view mask into the shader key.
>  2. There have been two fixes to the code which multiplies the number
> of
> invocations by the number of views.  First was that I
> accidentally used
> AND instead of ADD.  Second was an off-by-one error when adding
> ALU
> operations to an MI_MATH instruction that made us stomp the
> MI_MATH
> instruction itself instead of starting on dword 1.
> 
>  3. I've added a trivial implementation of multiDrawIndirect.  This
> isn't
> really required but some of the tests erroneously required it by
> mistake.  I'm not 100% sure that I like having a software
> implementation of multiDrawIndirect but it's no worse (and
> probably
> slightly better) than an application fall-back would be.
> Jason Ekstrand (14):
>   compiler: Add a system value and varying for ViewIndex
>   spirv: Bump the SPIR-V header to the latest public version
>   spirv: Add support for SPV_KHR_multiview
>   anv/nir: Delete the apply_dynamic_offsets prototype
>   anv: Add the KHX_multiview boilerplate
>   anv/pass: Store the per-subpass view mask
>   anv: Move shader hashing to anv_pipeline
>   anv/pipeline: Call nir_gather_info later
>   anv/pipeline: Add a subpass field to anv_pipeline
>   anv/pipeline: Add shader lowering for multiview
>   anv/cmd_buffer: Pull indirect draw parameter loading into a helper
>   anv/cmd_buffer: Emit instanced draws for multiple views
>   anv: Enable VK_KHX_multiview and SPV_KHR_multiview
>   anv: Trivially implement multiDrawIndirect
> 
>  src/compiler/nir/nir.c |   4 +
>  src/compiler/nir/nir_intrinsics.h  |   1 +
>  src/compiler/shader_enums.c|   2 +
>  src/compiler/shader_enums.h|   4 +
>  src/compiler/spirv/nir_spirv.h |   1 +
>  src/compiler/spirv/spirv.h |  34 -
>  src/compiler/spirv/spirv_to_nir.c  |   4 +
>  src/compiler/spirv/vtn_variables.c |   4 +
>  src/intel/Makefile.sources |   1 +
>  src/intel/vulkan/anv_device.c  |  23 ++-
>  src/intel/vulkan/anv_entrypoints_gen.py|   1 +
>  src/intel/vulkan/anv_nir.h |   5 +-
>  src/intel/vulkan/anv_nir_lower_multiview.c | 234
> +
>  src/intel/vulkan/anv_pass.c|  19 +++
>  src/intel/vulkan/anv_pipeline.c|  83 +++---
>  src/intel/vulkan/anv_pipeline_cache.c  |  27 
>  src/intel/vulkan/anv_private.h |  15 +-
>  src/intel/vulkan/genX_cmd_buffer.c | 209
> ++
>  src/intel/vulkan/genX_pipeline.c   |   9 +-
>  src/mesa/program/prog_print.c  |   2 +
>  20 files changed, 588 insertions(+), 94 deletions(-)
>  create mode 100644 src/intel/vulkan/anv_nir_lower_multiview.c
> 
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Re: [Mesa-dev] [PATCH v3 14/14] anv: Trivially implement multiDrawIndirect

[Iago Toral]

On Wed, 2017-05-03 at 09:04 +0200, Iago Toral wrote:
> On Thu, 2017-04-27 at 09:31 -0700, Jason Ekstrand wrote:
> > 
> > ---
> >  src/intel/vulkan/anv_device.c  |  2 +-
> >  src/intel/vulkan/genX_cmd_buffer.c | 56 ++
> > 
> >  2 files changed, 34 insertions(+), 24 deletions(-)
> > 
> > diff --git a/src/intel/vulkan/anv_device.c
> > b/src/intel/vulkan/anv_device.c
> > index b2edb54..93f7401 100644
> > --- a/src/intel/vulkan/anv_device.c
> > +++ b/src/intel/vulkan/anv_device.c
> > @@ -522,7 +522,7 @@ void anv_GetPhysicalDeviceFeatures(
> >    .sampleRateShading= true,
> >    .dualSrcBlend = true,
> >    .logicOp  = true,
> > -  .multiDrawIndirect= false,
> > +  .multiDrawIndirect= true,
> >    .drawIndirectFirstInstance= true,
> >    .depthClamp   = true,
> >    .depthBiasClamp   = true,
> > diff --git a/src/intel/vulkan/genX_cmd_buffer.c
> > b/src/intel/vulkan/genX_cmd_buffer.c
> > index 163c022..bfb5472 100644
> > --- a/src/intel/vulkan/genX_cmd_buffer.c
> > +++ b/src/intel/vulkan/genX_cmd_buffer.c
> > @@ -1880,25 +1880,30 @@ void genX(CmdDrawIndirect)(
> > ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
> > struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
> > const struct brw_vs_prog_data *vs_prog_data =
> > get_vs_prog_data(pipeline);
> > -   struct anv_bo *bo = buffer->bo;
> > -   uint32_t bo_offset = buffer->offset + offset;
> >  
> > if (anv_batch_has_error(_buffer->batch))
> >    return;
> >  
> > genX(cmd_buffer_flush_state)(cmd_buffer);
> >  
> > -   if (vs_prog_data->uses_basevertex || vs_prog_data-
> > > 
> > > uses_baseinstance)
> > -  emit_base_vertex_instance_bo(cmd_buffer, bo, bo_offset + 8);
> > -   if (vs_prog_data->uses_drawid)
> > -  emit_draw_index(cmd_buffer, 0);
> > +   for (uint32_t i = 0; i < drawCount; i++) {
> > +  struct anv_bo *bo = buffer->bo;
> You can put the line above before the loop, maybe make 'bo' const
> too.

Forget the const part since that will make the compiler spit a bunch of
warnings for the qualifier being discarded by the various emit
functions below.

> Reviewed-by: Iago Toral Quiroga 
> 
> > 
> > +  uint32_t bo_offset = buffer->offset + offset;
> >  
> > -   load_indirect_parameters(cmd_buffer, buffer, offset, false);
> > +  if (vs_prog_data->uses_basevertex || vs_prog_data-
> > > 
> > > uses_baseinstance)
> > + emit_base_vertex_instance_bo(cmd_buffer, bo, bo_offset +
> > 8);
> > +  if (vs_prog_data->uses_drawid)
> > + emit_draw_index(cmd_buffer, i);
> >  
> > -   anv_batch_emit(_buffer->batch, GENX(3DPRIMITIVE), prim) {
> > -  prim.IndirectParameterEnable  = true;
> > -  prim.VertexAccessType = SEQUENTIAL;
> > -  prim.PrimitiveTopologyType= pipeline->topology;
> > +  load_indirect_parameters(cmd_buffer, buffer, offset, false);
> > +
> > +  anv_batch_emit(_buffer->batch, GENX(3DPRIMITIVE), prim)
> > {
> > + prim.IndirectParameterEnable  = true;
> > + prim.VertexAccessType = SEQUENTIAL;
> > + prim.PrimitiveTopologyType= pipeline->topology;
> > +  }
> > +
> > +  offset += stride;
> > }
> >  }
> >  
> > @@ -1913,26 +1918,31 @@ void genX(CmdDrawIndexedIndirect)(
> > ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
> > struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
> > const struct brw_vs_prog_data *vs_prog_data =
> > get_vs_prog_data(pipeline);
> > -   struct anv_bo *bo = buffer->bo;
> > -   uint32_t bo_offset = buffer->offset + offset;
> >  
> > if (anv_batch_has_error(_buffer->batch))
> >    return;
> >  
> > genX(cmd_buffer_flush_state)(cmd_buffer);
> >  
> > -   /* TODO: We need to stomp base vertex to 0 somehow */
> > -   if (vs_prog_data->uses_basevertex || vs_prog_data-
> > > 
> > > uses_baseinstance)
> > -  emit_base_vertex_instance_bo(cmd_buffer, bo, bo_offset +
> > 12);
> > -   if (vs_prog_data->uses_drawid)
> > -  emit_draw_index(cmd_buffer, 0);
> > +   for (uint32_t i = 0; i < drawCount; i++) {
> > +  struct anv_bo *bo = buffer->bo;
> > +  uint32_t bo_offset = buffer->offset + offset;
> >  
> > -   load_indirect_parameters(cmd_buffer, buffer, offset, true);
> > +  /* TODO: We need to stomp base vertex to 0 somehow */
> > +  if (vs_prog_data->uses_basevertex || vs_prog_data-
> > > 
> > > uses_baseinstance)
> > + emit_base_vertex_instance_bo(cmd_buffer, bo, bo_offset +
> > 12);
> > +  if (vs_prog_data->uses_drawid)
> > + emit_draw_index(cmd_buffer, i);
> >  
> > -   anv_batch_emit(_buffer->batch, GENX(3DPRIMITIVE), prim) {
> > -  prim.IndirectParameterEnable  = true;
> > -  prim.VertexAccessType = RANDOM;
> > -  

Re: [Mesa-dev] [PATCH v3 14/14] anv: Trivially implement multiDrawIndirect

[Iago Toral]

On Thu, 2017-04-27 at 09:31 -0700, Jason Ekstrand wrote:
> ---
>  src/intel/vulkan/anv_device.c  |  2 +-
>  src/intel/vulkan/genX_cmd_buffer.c | 56 ++
> 
>  2 files changed, 34 insertions(+), 24 deletions(-)
> 
> diff --git a/src/intel/vulkan/anv_device.c
> b/src/intel/vulkan/anv_device.c
> index b2edb54..93f7401 100644
> --- a/src/intel/vulkan/anv_device.c
> +++ b/src/intel/vulkan/anv_device.c
> @@ -522,7 +522,7 @@ void anv_GetPhysicalDeviceFeatures(
>    .sampleRateShading= true,
>    .dualSrcBlend = true,
>    .logicOp  = true,
> -  .multiDrawIndirect= false,
> +  .multiDrawIndirect= true,
>    .drawIndirectFirstInstance= true,
>    .depthClamp   = true,
>    .depthBiasClamp   = true,
> diff --git a/src/intel/vulkan/genX_cmd_buffer.c
> b/src/intel/vulkan/genX_cmd_buffer.c
> index 163c022..bfb5472 100644
> --- a/src/intel/vulkan/genX_cmd_buffer.c
> +++ b/src/intel/vulkan/genX_cmd_buffer.c
> @@ -1880,25 +1880,30 @@ void genX(CmdDrawIndirect)(
> ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
> struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
> const struct brw_vs_prog_data *vs_prog_data =
> get_vs_prog_data(pipeline);
> -   struct anv_bo *bo = buffer->bo;
> -   uint32_t bo_offset = buffer->offset + offset;
>  
> if (anv_batch_has_error(_buffer->batch))
>    return;
>  
> genX(cmd_buffer_flush_state)(cmd_buffer);
>  
> -   if (vs_prog_data->uses_basevertex || vs_prog_data-
> >uses_baseinstance)
> -  emit_base_vertex_instance_bo(cmd_buffer, bo, bo_offset + 8);
> -   if (vs_prog_data->uses_drawid)
> -  emit_draw_index(cmd_buffer, 0);
> +   for (uint32_t i = 0; i < drawCount; i++) {
> +  struct anv_bo *bo = buffer->bo;

You can put the line above before the loop, maybe make 'bo' const too.

Reviewed-by: Iago Toral Quiroga 

> +  uint32_t bo_offset = buffer->offset + offset;
>  
> -   load_indirect_parameters(cmd_buffer, buffer, offset, false);
> +  if (vs_prog_data->uses_basevertex || vs_prog_data-
> >uses_baseinstance)
> + emit_base_vertex_instance_bo(cmd_buffer, bo, bo_offset +
> 8);
> +  if (vs_prog_data->uses_drawid)
> + emit_draw_index(cmd_buffer, i);
>  
> -   anv_batch_emit(_buffer->batch, GENX(3DPRIMITIVE), prim) {
> -  prim.IndirectParameterEnable  = true;
> -  prim.VertexAccessType = SEQUENTIAL;
> -  prim.PrimitiveTopologyType= pipeline->topology;
> +  load_indirect_parameters(cmd_buffer, buffer, offset, false);
> +
> +  anv_batch_emit(_buffer->batch, GENX(3DPRIMITIVE), prim) {
> + prim.IndirectParameterEnable  = true;
> + prim.VertexAccessType = SEQUENTIAL;
> + prim.PrimitiveTopologyType= pipeline->topology;
> +  }
> +
> +  offset += stride;
> }
>  }
>  
> @@ -1913,26 +1918,31 @@ void genX(CmdDrawIndexedIndirect)(
> ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
> struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
> const struct brw_vs_prog_data *vs_prog_data =
> get_vs_prog_data(pipeline);
> -   struct anv_bo *bo = buffer->bo;
> -   uint32_t bo_offset = buffer->offset + offset;
>  
> if (anv_batch_has_error(_buffer->batch))
>    return;
>  
> genX(cmd_buffer_flush_state)(cmd_buffer);
>  
> -   /* TODO: We need to stomp base vertex to 0 somehow */
> -   if (vs_prog_data->uses_basevertex || vs_prog_data-
> >uses_baseinstance)
> -  emit_base_vertex_instance_bo(cmd_buffer, bo, bo_offset + 12);
> -   if (vs_prog_data->uses_drawid)
> -  emit_draw_index(cmd_buffer, 0);
> +   for (uint32_t i = 0; i < drawCount; i++) {
> +  struct anv_bo *bo = buffer->bo;
> +  uint32_t bo_offset = buffer->offset + offset;
>  
> -   load_indirect_parameters(cmd_buffer, buffer, offset, true);
> +  /* TODO: We need to stomp base vertex to 0 somehow */
> +  if (vs_prog_data->uses_basevertex || vs_prog_data-
> >uses_baseinstance)
> + emit_base_vertex_instance_bo(cmd_buffer, bo, bo_offset +
> 12);
> +  if (vs_prog_data->uses_drawid)
> + emit_draw_index(cmd_buffer, i);
>  
> -   anv_batch_emit(_buffer->batch, GENX(3DPRIMITIVE), prim) {
> -  prim.IndirectParameterEnable  = true;
> -  prim.VertexAccessType = RANDOM;
> -  prim.PrimitiveTopologyType= pipeline->topology;
> +  load_indirect_parameters(cmd_buffer, buffer, offset, true);
> +
> +  anv_batch_emit(_buffer->batch, GENX(3DPRIMITIVE), prim) {
> + prim.IndirectParameterEnable  = true;
> + prim.VertexAccessType = RANDOM;
> + prim.PrimitiveTopologyType= pipeline->topology;
> +  }
> +
> +  offset += stride;
> }
>  }
>  
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Re: [Mesa-dev] [PATCH v3 07/14] anv: Move shader hashing to anv_pipeline

[Iago Toral]

On Thu, 2017-04-27 at 09:31 -0700, Jason Ekstrand wrote:
> Shader hashing is very closely related to shader
> compilation.  Putting
> them right next to each other in anv_pipeline makes it easier to
> verify
> that we're actually hashing everything we need to be hashing.

Maybe add that this version also hashes the shader stage.

> ---
>  src/intel/vulkan/anv_pipeline.c   | 59
> ---
>  src/intel/vulkan/anv_pipeline_cache.c | 27 
>  src/intel/vulkan/anv_private.h|  6 
>  3 files changed, 47 insertions(+), 45 deletions(-)
> 
> diff --git a/src/intel/vulkan/anv_pipeline.c
> b/src/intel/vulkan/anv_pipeline.c
> index 9d0dc69..0685d0a 100644
> --- a/src/intel/vulkan/anv_pipeline.c
> +++ b/src/intel/vulkan/anv_pipeline.c
> @@ -331,6 +331,35 @@ populate_cs_prog_key(const struct
> gen_device_info *devinfo,
> populate_sampler_prog_key(devinfo, >tex);
>  }
>  
> +static void
> +anv_pipeline_hash_shader(struct anv_pipeline *pipeline,
> + struct anv_shader_module *module,
> + const char *entrypoint,
> + gl_shader_stage stage,
> + const VkSpecializationInfo *spec_info,
> + const void *key, size_t key_size,
> + unsigned char *sha1_out)
> +{
> +   struct mesa_sha1 ctx;
> +
> +   _mesa_sha1_init();
> +   if (pipeline->layout) {
> +  _mesa_sha1_update(, pipeline->layout->sha1,
> +sizeof(pipeline->layout->sha1));
> +   }
> +   _mesa_sha1_update(, module->sha1, sizeof(module->sha1));
> +   _mesa_sha1_update(, entrypoint, strlen(entrypoint));
> +   _mesa_sha1_update(, , sizeof(stage));
> +   /* hash in shader stage, pipeline layout? */

This comment above seems outdated.

Reviewed-by: Iago Toral Quiroga 

> +   if (spec_info) {
> +  _mesa_sha1_update(, spec_info->pMapEntries,
> +spec_info->mapEntryCount *
> sizeof(*spec_info->pMapEntries));
> +  _mesa_sha1_update(, spec_info->pData, spec_info-
> >dataSize);
> +   }
> +   _mesa_sha1_update(, key, key_size);
> +   _mesa_sha1_final(, sha1_out);
> +}
> +
>  static nir_shader *
>  anv_pipeline_compile(struct anv_pipeline *pipeline,
>   struct anv_shader_module *module,
> @@ -463,8 +492,9 @@ anv_pipeline_compile_vs(struct anv_pipeline
> *pipeline,
> populate_vs_prog_key(>device->info, );
>  
> if (cache) {
> -  anv_hash_shader(sha1, , sizeof(key), module, entrypoint,
> -  pipeline->layout, spec_info);
> +  anv_pipeline_hash_shader(pipeline, module, entrypoint,
> +   MESA_SHADER_VERTEX, spec_info,
> +   , sizeof(key), sha1);
>    bin = anv_pipeline_cache_search(cache, sha1, 20);
> }
>  
> @@ -587,10 +617,12 @@ anv_pipeline_compile_tcs_tes(struct
> anv_pipeline *pipeline,
> tcs_key.input_vertices = info->pTessellationState-
> >patchControlPoints;
>  
> if (cache) {
> -  anv_hash_shader(tcs_sha1, _key, sizeof(tcs_key),
> tcs_module,
> -  tcs_entrypoint, pipeline->layout,
> tcs_spec_info);
> -  anv_hash_shader(tes_sha1, _key, sizeof(tes_key),
> tes_module,
> -  tes_entrypoint, pipeline->layout,
> tes_spec_info);
> +  anv_pipeline_hash_shader(pipeline, tcs_module, tcs_entrypoint,
> +   MESA_SHADER_TESS_CTRL, tcs_spec_info,
> +   _key, sizeof(tcs_key), tcs_sha1);
> +  anv_pipeline_hash_shader(pipeline, tes_module, tes_entrypoint,
> +   MESA_SHADER_TESS_EVAL, tes_spec_info,
> +   _key, sizeof(tes_key), tes_sha1);
>    memcpy(_sha1[20], tes_sha1, 20);
>    memcpy(_sha1[20], tcs_sha1, 20);
>    tcs_bin = anv_pipeline_cache_search(cache, tcs_sha1,
> sizeof(tcs_sha1));
> @@ -724,8 +756,9 @@ anv_pipeline_compile_gs(struct anv_pipeline
> *pipeline,
> populate_gs_prog_key(>device->info, );
>  
> if (cache) {
> -  anv_hash_shader(sha1, , sizeof(key), module, entrypoint,
> -  pipeline->layout, spec_info);
> +  anv_pipeline_hash_shader(pipeline, module, entrypoint,
> +   MESA_SHADER_GEOMETRY, spec_info,
> +   , sizeof(key), sha1);
>    bin = anv_pipeline_cache_search(cache, sha1, 20);
> }
>  
> @@ -801,8 +834,9 @@ anv_pipeline_compile_fs(struct anv_pipeline
> *pipeline,
> populate_wm_prog_key(pipeline, info, );
>  
> if (cache) {
> -  anv_hash_shader(sha1, , sizeof(key), module, entrypoint,
> -  pipeline->layout, spec_info);
> +  anv_pipeline_hash_shader(pipeline, module, entrypoint,
> +   MESA_SHADER_FRAGMENT, spec_info,
> +   , sizeof(key), sha1);
>    bin = anv_pipeline_cache_search(cache, sha1, 20);
> }
>  
>