Re: [Mesa-dev] [PATCH] glcpp: fix #undef to match latest spec update and GLSLang implementation

[Iago Toral]

This didn't get any reviews, any takers? It fixes a couple of CTS tests
so it would be good to have it merged.

Iago

On Tue, 2017-05-30 at 13:25 +0200, Iago Toral Quiroga wrote:
> GLSL ES spec includes the following:
> 
>    "It is an error to undefine or to redefine a built-in
> (pre-defined) macro name."
> 
> But desktop GLSL doesn't. This has sparked some discussion
> in Khronos, and the final conclusion was to update the
> GLSL 4.50 spec to include the following:
> 
>    "By convention, all macro names containing two consecutive
> underscores ( __ ) are reserved for use by underlying
> software layers.  Defining or undefining such a name in a
> shader does not itself result in an error, but may result
> in unintended behaviors that stem from having multiple
> definitions of the same name.  All macro names prefixed
> with “GL_” (“GL” followed by a single underscore) are also
> reserved, and defining or undefining such a name results in
> a compile-time error."
> 
> In other words, undefining GL_* names should be an error, but
> undefining other names with a double underscore in them is
> not strictly prohibited in desktop GLSL.
> 
> This patch fixes the preprocessor to apply these rules,
> following exactly the implementation already present
> in GLSLang. This fixes some tests in CTS.
> 
> Kronos bug:
> https://cvs.khronos.org/bugzilla/show_bug.cgi?id=16003
> 
> Fixes:
> KHR-
> GL45.shaders.preprocessor.definitions.undefine_core_profile_vertex
> KHR-
> GL45.shaders.preprocessor.definitions.undefine_core_profile_fragment
> ---
>  src/compiler/glsl/glcpp/glcpp-parse.y | 45 -
> --
>  1 file changed, 31 insertions(+), 14 deletions(-)
> 
> diff --git a/src/compiler/glsl/glcpp/glcpp-parse.y
> b/src/compiler/glsl/glcpp/glcpp-parse.y
> index fe211a0..f1719f9 100644
> --- a/src/compiler/glsl/glcpp/glcpp-parse.y
> +++ b/src/compiler/glsl/glcpp/glcpp-parse.y
> @@ -287,24 +287,41 @@ control_line_success:
>   * The GLSL ES 1.00 spec does not contain this text,
> but
>   * dEQP's preprocess test in GLES2 checks for it.
>   *
> - * Section 3.3 (Preprocessor) of the GLSL 1.30 spec
> says:
> + * Section 3.3 (Preprocessor) revision 7, of the
> GLSL 4.50
> + * spec says:
>   *
> - *#define and #undef functionality are defined
> as is
> - *standard for C++ preprocessors for macro
> definitions
> - *both with and without macro parameters.
> + *By convention, all macro names containing two
> consecutive
> + *underscores ( __ ) are reserved for use by
> underlying
> + *software layers. Defining or undefining such a
> name
> + *in a shader does not itself result in an
> error, but may
> + *result in unintended behaviors that stem from
> having
> + *multiple definitions of the same name. All
> macro names
> + *prefixed with "GL_" (...) are also reseved,
> and defining
> + *such a name results in a compile-time error.
>   *
> - * At least as far as I can tell GCC allow '#undef
> __FILE__'.
> - * Furthermore, there are desktop OpenGL conformance
> tests
> - * that expect '#undef __VERSION__' and '#undef
> - * GL_core_profile' to work.
> + * The code below implements the same checks as
> GLSLang.
>   */
> - if (parser->is_gles &&
> -(strcmp("__LINE__", $3) == 0
> - || strcmp("__FILE__", $3) == 0
> - || strcmp("__VERSION__", $3) == 0
> - || strncmp("GL_", $3, 3) == 0))
> + if (strncmp("GL_", $3, 3) == 0)
>   glcpp_error(& @1, parser, "Built-in (pre-
> defined)"
> - " macro names cannot be
> undefined.");
> + " names beginning with GL_
> cannot be undefined.");
> + else if (strstr($3, "__") != NULL) {
> + if (parser->is_gles
> + && parser->version >= 300
> + && (strcmp("__LINE__", $3) == 0
> + || strcmp("__FILE__", $3) == 0
> + || strcmp("__VERSION__", $3) == 0))
> {
> + glcpp_error(& @1, parser, "Built-in
> (pre-defined)"
> + " names cannot be
> undefined.");
> + } else if (parser->is_gles && parser-
> >version <= 300) {
> + glcpp_error(& @1, parser,
> + " names containing
> consecutive underscores"
> + " are reserved.

Re: [Mesa-dev] [PATCH] dri3/GLX: Fix drawable invalidation

[Michel Dänzer]

On 01/06/17 07:13 PM, Thomas Hellstrom wrote:
> A number of internal VMware apitrace traces image comparisons fail with
> dri3 because the viewport transformation becomes incorrect after an X
> drawable resize. The incorrect viewport transformation sometimes persist
> until the second draw-call after a swapBuffer.
> 
> Comparing with the dri2 glx code there are a couple of places where dri2
> invalidates the drawable in the absence of server-triggered invalidation,
> where dri3 doesn't do that. When these invalidation points are added to
> dri3, the image comparisons become correct.
> 
> Cc: 
> Signed-off-by: Thomas Hellstrom 
> ---
>  src/glx/dri3_glx.c | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c
> index 4264fd8..7732279 100644
> --- a/src/glx/dri3_glx.c
> +++ b/src/glx/dri3_glx.c
> @@ -235,6 +235,11 @@ dri3_bind_context(struct glx_context *context, struct 
> glx_context *old,
> if (!(*psc->core->bindContext) (pcp->driContext, dri_draw, dri_read))
>return GLXBadContext;
>  
> +   if (dri_draw)
> +  (*psc->f->invalidate)(dri_draw);
> +   if (dri_read)

Make this

   if (dri_read && dri_read != dri_draw)

to match dri2_bind_context.


> +  (*psc->f->invalidate)(dri_read);
> +
> return Success;
>  }
>  
> @@ -493,6 +498,7 @@ dri3_flush_front_buffer(__DRIdrawable *driDrawable, void 
> *loaderPrivate)
>  
> loader_dri3_flush(draw, __DRI2_FLUSH_DRAWABLE, 
> __DRI2_THROTTLE_FLUSHFRONT);
>  
> +   (*psc->f->invalidate)(driDrawable);
> loader_dri3_wait_gl(draw);
>  }
>  
> 

Looks like a good catch. With the above fixed,

Reviewed-and-Tested-by: Michel Dänzer 


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer

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Re: [Mesa-dev] [PATCH 0/3] Fix missing initializer errors in generated tables

[Marek Olšák]

On Tue, Jun 6, 2017 at 7:16 AM, Chih-Wei Huang  wrote:
> 2017-06-05 3:57 GMT+08:00 Marek Olšák :
>> NAK.
>>
>> In C/C++, the initializer is used to clear the memory to 0s, thus,
>> adding 0s to the initializer is redundant and unnecessary. Empty
>> initializer {} is also commonly used instead of memset.
>
> Commonly used doesn't mean it's the right thing.
> Otherwise the compiler should not generate such warnings.
>
> The compiler tries to tell you "hey, you may miss setting something?"
> If that's what you want (init to 0), please express it explicitly.
>
> It's about readability of the code.
> When people like me read the code,
> I have exact the same question as the compiler:
> "does the developer forget to set something?"
>
>> You need to suppress this warning if you don't want to see it.
>
> Not a good suggestion.
>
> Making the code warning-free is the responsibility
> of the one who wrote the code instead of
> the one who builds the code.
>
> So fix the code, please.

No, the code is OK. Do we get a warning for every memset we use? No,
we don't. {} is like memset. Always has been.

The warning is an optional feature of the compiler. Somebody thought that would
be useful, so they put it in there, but in this case it's not.

Marek
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Re: [Mesa-dev] [PATCH] glcpp: fix #undef to match latest spec update and GLSLang implementation

[Samuel Pitoiset]

Looks good to me.

Reviewed-by: Samuel Pitoiset 

On 05/30/2017 01:25 PM, Iago Toral Quiroga wrote:

GLSL ES spec includes the following:

"It is an error to undefine or to redefine a built-in
 (pre-defined) macro name."

But desktop GLSL doesn't. This has sparked some discussion
in Khronos, and the final conclusion was to update the
GLSL 4.50 spec to include the following:

"By convention, all macro names containing two consecutive
 underscores ( __ ) are reserved for use by underlying
 software layers.  Defining or undefining such a name in a
 shader does not itself result in an error, but may result
 in unintended behaviors that stem from having multiple
 definitions of the same name.  All macro names prefixed
 with “GL_” (“GL” followed by a single underscore) are also
 reserved, and defining or undefining such a name results in
 a compile-time error."

In other words, undefining GL_* names should be an error, but
undefining other names with a double underscore in them is
not strictly prohibited in desktop GLSL.

This patch fixes the preprocessor to apply these rules,
following exactly the implementation already present
in GLSLang. This fixes some tests in CTS.

Kronos bug:
https://cvs.khronos.org/bugzilla/show_bug.cgi?id=16003

Fixes:
KHR-GL45.shaders.preprocessor.definitions.undefine_core_profile_vertex
KHR-GL45.shaders.preprocessor.definitions.undefine_core_profile_fragment
---
  src/compiler/glsl/glcpp/glcpp-parse.y | 45 ---
  1 file changed, 31 insertions(+), 14 deletions(-)

diff --git a/src/compiler/glsl/glcpp/glcpp-parse.y 
b/src/compiler/glsl/glcpp/glcpp-parse.y
index fe211a0..f1719f9 100644
--- a/src/compiler/glsl/glcpp/glcpp-parse.y
+++ b/src/compiler/glsl/glcpp/glcpp-parse.y
@@ -287,24 +287,41 @@ control_line_success:
   * The GLSL ES 1.00 spec does not contain this text, but
   * dEQP's preprocess test in GLES2 checks for it.
   *
- * Section 3.3 (Preprocessor) of the GLSL 1.30 spec says:
+ * Section 3.3 (Preprocessor) revision 7, of the GLSL 4.50
+ * spec says:
   *
- *#define and #undef functionality are defined as is
- *standard for C++ preprocessors for macro definitions
- *both with and without macro parameters.
+ *By convention, all macro names containing two consecutive
+ *underscores ( __ ) are reserved for use by underlying
+ *software layers. Defining or undefining such a name
+ *in a shader does not itself result in an error, but may
+ *result in unintended behaviors that stem from having
+ *multiple definitions of the same name. All macro names
+ *prefixed with "GL_" (...) are also reseved, and defining
+ *such a name results in a compile-time error.
   *
- * At least as far as I can tell GCC allow '#undef __FILE__'.
- * Furthermore, there are desktop OpenGL conformance tests
- * that expect '#undef __VERSION__' and '#undef
- * GL_core_profile' to work.
+ * The code below implements the same checks as GLSLang.
   */
-   if (parser->is_gles &&
-(strcmp("__LINE__", $3) == 0
- || strcmp("__FILE__", $3) == 0
- || strcmp("__VERSION__", $3) == 0
- || strncmp("GL_", $3, 3) == 0))
+   if (strncmp("GL_", $3, 3) == 0)
glcpp_error(& @1, parser, "Built-in (pre-defined)"
-   " macro names cannot be undefined.");
+   " names beginning with GL_ cannot be 
undefined.");
+   else if (strstr($3, "__") != NULL) {
+   if (parser->is_gles
+   && parser->version >= 300
+   && (strcmp("__LINE__", $3) == 0
+   || strcmp("__FILE__", $3) == 0
+   || strcmp("__VERSION__", $3) == 0)) {
+   glcpp_error(& @1, parser, "Built-in 
(pre-defined)"
+   " names cannot be undefined.");
+   } else if (parser->is_gles && parser->version <= 300) {
+   glcpp_error(& @1, parser,
+   " names containing consecutive 
underscores"
+   " are reserved.");
+   } else {
+   glcpp_warning(& @1, parser,
+ " names containing consecutive 
underscores"
+ " are reserved.");
+ 

Re: [Mesa-dev] [PATCH 5/5] st/mesa: use texture_barrier before CopyPixels blits where src == dst

[Marek Olšák]

On Tue, Jun 6, 2017 at 4:28 AM, Michel Dänzer  wrote:
> On 06/06/17 01:50 AM, Marek Olšák wrote:
>> From: Marek Olšák 
>>
>> radeonsi won't flush caches if set_framebuffer_state doesn't change
>> anything.
>> ---
>>  src/mesa/state_tracker/st_cb_drawpixels.c | 7 +++
>>  1 file changed, 7 insertions(+)
>>
>> diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c 
>> b/src/mesa/state_tracker/st_cb_drawpixels.c
>> index 33d10f6..0ef05ef 100644
>> --- a/src/mesa/state_tracker/st_cb_drawpixels.c
>> +++ b/src/mesa/state_tracker/st_cb_drawpixels.c
>> @@ -1400,20 +1400,27 @@ blit_copy_pixels(struct gl_context *ctx, GLint srcx, 
>> GLint srcy,
>>  st_window_rectangles_to_blit(ctx, &blit);
>>
>>   if (screen->is_format_supported(screen, blit.src.format,
>>   blit.src.resource->target,
>>   blit.src.resource->nr_samples,
>>   PIPE_BIND_SAMPLER_VIEW) &&
>>   screen->is_format_supported(screen, blit.dst.format,
>>   blit.dst.resource->target,
>>   blit.dst.resource->nr_samples,
>>   PIPE_BIND_RENDER_TARGET)) {
>> +/* If src == dst, make sure src is coherent with recent dst
>> + * updates.
>> + */
>> +if (blit.src.resource == blit.dst.resource &&
>> +screen->get_param(screen, PIPE_CAP_TEXTURE_BARRIER))
>> +   pipe->texture_barrier(pipe, PIPE_TEXTURE_BARRIER_SAMPLER);
>> +
>>  pipe->blit(pipe, &blit);
>
> Maybe this should be handled within the pipe->blit hook? E.g., is this
> necessary when using the SDMA engine in radeonsi?

It's not necessary in that case, yet it's a CopyPixels optimization
not worth spending time on.

Marek
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Re: [Mesa-dev] [PATCH] i965: Don't try to resolve CCS with MESA_FORMAT_NONE.

[Eero Tamminen]

Hi,

On 06.06.2017 02:58, Kenneth Graunke wrote:

On Monday, June 5, 2017 2:03:45 AM PDT Tapani Pälli wrote:

FWIW this change fixes also regression on Android wallpaper since that
commit.


I'm planning on dropping this patch, as it seems that

commit 708664159e18487b6676fd5b4c33f52003f81d9e
Author: Jason Ekstrand 
Date:   Fri May 26 10:57:33 2017 -0700

i965: Finalize miptrees before prepare_texture

has already fixed the problem for me.


Benchmarks and compiz also work now, so the fix seems good (except maybe 
for the AppVeyor fail mail).



- Eero


Hopefully that also fixes the Android wallpaper issue?


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Re: [Mesa-dev] [PATCH] glthread: remove extra _mesa_glthread_finish() from generated code

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Tue, Jun 6, 2017 at 7:08 AM, Timothy Arceri  wrote:
> The other user of print_sync_dispatch() was ending up with code that
> looked like:
>
>   _mesa_glthread_finish(ctx);
>   _mesa_glthread_restore_dispatch(ctx);
>   _mesa_glthread_finish(ctx);
> ---
>  src/mapi/glapi/gen/gl_marshal.py | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mapi/glapi/gen/gl_marshal.py 
> b/src/mapi/glapi/gen/gl_marshal.py
> index 51475e1..f52b9b7 100644
> --- a/src/mapi/glapi/gen/gl_marshal.py
> +++ b/src/mapi/glapi/gen/gl_marshal.py
> @@ -83,21 +83,20 @@ class PrintCode(gl_XML.gl_print_base):
>
>  def print_sync_call(self, func):
>  call = 'CALL_{0}(ctx->CurrentServerDispatch, ({1}))'.format(
>  func.name, func.get_called_parameter_string())
>  if func.return_type == 'void':
>  out('{0};'.format(call))
>  else:
>  out('return {0};'.format(call))
>
>  def print_sync_dispatch(self, func):
> -out('_mesa_glthread_finish(ctx);')
>  out('debug_print_sync_fallback("{0}");'.format(func.name))
>  self.print_sync_call(func)
>
>  def print_sync_body(self, func):
>  out('/* {0}: marshalled synchronously */'.format(func.name))
>  out('static {0} GLAPIENTRY'.format(func.return_type))
>  out('_mesa_marshal_{0}({1})'.format(func.name, 
> func.get_parameter_string()))
>  out('{')
>  with indent():
>  out('GET_CURRENT_CONTEXT(ctx);')
> @@ -252,20 +251,21 @@ class PrintCode(gl_XML.gl_print_base):
>  out('if (cmd_size <= MARSHAL_MAX_CMD_SIZE) {')
>  with indent():
>  self.print_async_dispatch(func)
>  out('return;')
>  out('}')
>
>  out('')
>  if need_fallback_sync:
>  out('fallback_to_sync:')
>  with indent():
> +out('_mesa_glthread_finish(ctx);')
>  self.print_sync_dispatch(func)
>
>  out('}')
>
>  def print_async_body(self, func):
>  out('/* {0}: marshalled asynchronously */'.format(func.name))
>  self.print_async_struct(func)
>  self.print_async_unmarshal(func)
>  self.print_async_marshal(func)
>  out('')
> --
> 2.9.4
>
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[Mesa-dev] [PATCH 2/3] radv/vulkan: Move radv_get_driver_version to src/vulkan/util

[Alex Smith]

This means it can be reused for other Vulkan drivers. Also fix up a
typo, need to search for '.' in the version string rather than ','.

Signed-off-by: Alex Smith 
---
 src/amd/vulkan/radv_device.c | 24 +
 src/vulkan/Makefile.sources  |  1 +
 src/vulkan/util/vk_util.c| 50 
 src/vulkan/util/vk_util.h|  2 ++
 4 files changed, 54 insertions(+), 23 deletions(-)
 create mode 100644 src/vulkan/util/vk_util.c

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index a812527..5fdb894 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -574,28 +574,6 @@ void radv_GetPhysicalDeviceFeatures2KHR(
return radv_GetPhysicalDeviceFeatures(physicalDevice, 
&pFeatures->features);
 }
 
-static uint32_t radv_get_driver_version()
-{
-   const char *minor_string = strchr(VERSION, '.');
-   const char *patch_string = minor_string ? strchr(minor_string + 1, 
','): NULL;
-   int major = atoi(VERSION);
-   int minor = minor_string ? atoi(minor_string + 1) : 0;
-   int patch = patch_string ? atoi(patch_string + 1) : 0;
-   if (strstr(VERSION, "devel")) {
-   if (patch == 0) {
-   patch = 99;
-   if (minor == 0) {
-   minor = 99;
-   --major;
-   } else
-   --minor;
-   } else
-   --patch;
-   }
-   uint32_t version = VK_MAKE_VERSION(major, minor, patch);
-   return version;
-}
-
 void radv_GetPhysicalDeviceProperties(
VkPhysicalDevicephysicalDevice,
VkPhysicalDeviceProperties* pProperties)
@@ -731,7 +709,7 @@ void radv_GetPhysicalDeviceProperties(
 
*pProperties = (VkPhysicalDeviceProperties) {
.apiVersion = VK_MAKE_VERSION(1, 0, 42),
-   .driverVersion = radv_get_driver_version(),
+   .driverVersion = vk_get_driver_version(),
.vendorID = 0x1002,
.deviceID = pdevice->rad_info.pci_id,
.deviceType = pdevice->rad_info.has_dedicated_vram ? 
VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
diff --git a/src/vulkan/Makefile.sources b/src/vulkan/Makefile.sources
index 9962c1b..2cf7218 100644
--- a/src/vulkan/Makefile.sources
+++ b/src/vulkan/Makefile.sources
@@ -17,6 +17,7 @@ VULKAN_WSI_X11_FILES := \
 
 VULKAN_UTIL_FILES := \
util/vk_alloc.h \
+   util/vk_util.c \
util/vk_util.h
 
 VULKAN_UTIL_GENERATED_FILES := \
diff --git a/src/vulkan/util/vk_util.c b/src/vulkan/util/vk_util.c
new file mode 100644
index 000..5e5235a
--- /dev/null
+++ b/src/vulkan/util/vk_util.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright © 2016 Red Hat.
+ * Copyright © 2016 Bas Nieuwenhuizen
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include "vk_util.h"
+
+uint32_t vk_get_driver_version(void)
+{
+   const char *minor_string = strchr(VERSION, '.');
+   const char *patch_string = minor_string ? strchr(minor_string + 1, '.') : 
NULL;
+   int major = atoi(VERSION);
+   int minor = minor_string ? atoi(minor_string + 1) : 0;
+   int patch = patch_string ? atoi(patch_string + 1) : 0;
+   if (strstr(VERSION, "devel")) {
+  if (patch == 0) {
+ patch = 99;
+ if (minor == 0) {
+minor = 99;
+--major;
+ } else
+--minor;
+  } else
+ --patch;
+   }
+   uint32_t version = VK_MAKE_VERSION(major, minor, patch);
+   return version;
+}
diff --git a/src/vulkan/util/vk_util.h b/src/vulkan/util/vk_util.h
index 5ff1f00..2ed601f 100644
--- a/src/vulkan/util/vk_util.h
+++ b/src/vulkan/util/vk_util.h
@@ -197,4 +197,6 @@ __vk_find_struct(void *st

[Mesa-dev] [PATCH 1/3] util/vulkan: Move Vulkan utilities to src/vulkan/util

[Alex Smith]

We have Vulkan utilities in both src/util and src/vulkan/util. The
latter seems a more appropriate place for Vulkan-specific things, so
move them there.

Signed-off-by: Alex Smith 
---
 src/amd/vulkan/radv_device.c| 2 +-
 src/amd/vulkan/radv_formats.c   | 3 ++-
 src/amd/vulkan/radv_private.h   | 2 +-
 src/amd/vulkan/radv_wsi.c   | 2 +-
 src/intel/vulkan/anv_device.c   | 2 +-
 src/intel/vulkan/anv_formats.c  | 3 +--
 src/intel/vulkan/anv_pass.c | 2 +-
 src/intel/vulkan/anv_private.h  | 2 +-
 src/intel/vulkan/anv_queue.c| 2 +-
 src/intel/vulkan/anv_wsi.c  | 2 +-
 src/intel/vulkan/genX_cmd_buffer.c  | 2 +-
 src/util/Makefile.sources   | 4 +---
 src/vulkan/Makefile.am  | 7 ++-
 src/vulkan/Makefile.sources | 4 
 src/{ => vulkan}/util/vk_alloc.h| 0
 src/{ => vulkan}/util/vk_util.h | 0
 src/vulkan/wsi/wsi_common.h | 2 +-
 src/vulkan/wsi/wsi_common_wayland.c | 2 +-
 src/vulkan/wsi/wsi_common_x11.c | 2 +-
 19 files changed, 26 insertions(+), 19 deletions(-)
 rename src/{ => vulkan}/util/vk_alloc.h (100%)
 rename src/{ => vulkan}/util/vk_util.h (100%)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 887916f..a812527 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -33,7 +33,7 @@
 #include "radv_cs.h"
 #include "util/disk_cache.h"
 #include "util/strtod.h"
-#include "util/vk_util.h"
+#include "vk_util.h"
 #include 
 #include 
 #include 
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index 6cff0a5..b13adb9 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -28,7 +28,8 @@
 #include "sid.h"
 #include "r600d_common.h"
 
-#include "util/vk_util.h"
+#include "vk_util.h"
+
 #include "util/u_half.h"
 #include "util/format_srgb.h"
 #include "util/format_r11g11b10f.h"
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index ed80ba7..a3920a7 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -47,8 +47,8 @@
 #include "compiler/shader_enums.h"
 #include "util/macros.h"
 #include "util/list.h"
-#include "util/vk_alloc.h"
 #include "main/macros.h"
+#include "vk_alloc.h"
 
 #include "radv_radeon_winsys.h"
 #include "ac_binary.h"
diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index 51fe159..cdb04ca 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -26,7 +26,7 @@
 #include "radv_private.h"
 #include "radv_meta.h"
 #include "wsi_common.h"
-#include "util/vk_util.h"
+#include "vk_util.h"
 
 static const struct wsi_callbacks wsi_cbs = {
.get_phys_device_format_properties = radv_GetPhysicalDeviceFormatProperties,
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index aacd07f..6079588 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -35,7 +35,7 @@
 #include "util/debug.h"
 #include "util/build_id.h"
 #include "util/mesa-sha1.h"
-#include "util/vk_util.h"
+#include "vk_util.h"
 
 #include "genxml/gen7_pack.h"
 
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 25801e8..104d4f7 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -23,8 +23,7 @@
 
 #include "anv_private.h"
 #include "vk_format_info.h"
-
-#include "util/vk_util.h"
+#include "vk_util.h"
 
 /*
  * gcc-4 and earlier don't allow compound literals where a constant
diff --git a/src/intel/vulkan/anv_pass.c b/src/intel/vulkan/anv_pass.c
index 93f1483..1b30c14 100644
--- a/src/intel/vulkan/anv_pass.c
+++ b/src/intel/vulkan/anv_pass.c
@@ -23,7 +23,7 @@
 
 #include "anv_private.h"
 
-#include "util/vk_util.h"
+#include "vk_util.h"
 
 static unsigned
 num_subpass_attachments(const VkSubpassDescription *desc)
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index c261faa..fe6ac3b 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -47,7 +47,7 @@
 #include "util/macros.h"
 #include "util/list.h"
 #include "util/u_vector.h"
-#include "util/vk_alloc.h"
+#include "vk_alloc.h"
 
 /* Pre-declarations needed for WSI entrypoints */
 struct wl_surface;
diff --git a/src/intel/vulkan/anv_queue.c b/src/intel/vulkan/anv_queue.c
index be7fd31..fd4d362 100644
--- a/src/intel/vulkan/anv_queue.c
+++ b/src/intel/vulkan/anv_queue.c
@@ -30,7 +30,7 @@
 #include 
 
 #include "anv_private.h"
-#include "util/vk_util.h"
+#include "vk_util.h"
 
 #include "genxml/gen7_pack.h"
 
diff --git a/src/intel/vulkan/anv_wsi.c b/src/intel/vulkan/anv_wsi.c
index 7575f58..9369f26 100644
--- a/src/intel/vulkan/anv_wsi.c
+++ b/src/intel/vulkan/anv_wsi.c
@@ -24,7 +24,7 @@
 #include "anv_private.h"
 #include "wsi_common.h"
 #include "vk_format_info.h"
-#include "util/vk_util.h"
+#include "vk_util.h"
 
 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
 static const struct wsi_callbacks wsi_cbs = {
diff --git a/src/intel/vulkan/genX_c

[Mesa-dev] [PATCH v2 3/3] anv: Set driver version to Mesa version

[Alex Smith]

As already done by RADV.

v2: Move version calculation function to src/vulkan/util to share with
RADV.

Signed-off-by: Alex Smith 
---
 src/intel/vulkan/anv_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 6079588..72a96b7 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -886,7 +886,7 @@ void anv_GetPhysicalDeviceProperties(
 
*pProperties = (VkPhysicalDeviceProperties) {
   .apiVersion = VK_MAKE_VERSION(1, 0, 42),
-  .driverVersion = 1,
+  .driverVersion = vk_get_driver_version(),
   .vendorID = 0x8086,
   .deviceID = pdevice->chipset_id,
   .deviceType = VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
-- 
2.9.4

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Re: [Mesa-dev] [PATCH 06/14] radv: add GFX9 to initialisation cmd buffer.

[Marek Olšák]

On Tue, Jun 6, 2017 at 1:14 AM, Dave Airlie  wrote:
> From: Dave Airlie 
>
> This just adds support for initialising some GFX9 registers,
> and handles the different init for the VGT reuse reg.
>
> Signed-off-by: Dave Airlie 
> ---
>  src/amd/vulkan/radv_cmd_buffer.c |  5 +--
>  src/amd/vulkan/si_cmd_buffer.c   | 72 
> 
>  2 files changed, 61 insertions(+), 16 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c 
> b/src/amd/vulkan/radv_cmd_buffer.c
> index e7b8c41..d66f897 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -557,8 +557,9 @@ radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
> radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
>pipeline->graphics.pa_cl_vs_out_cntl);
>
> -   radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
> -  
> S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
> +   if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
> +   radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
> +  
> S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
>  }
>
>  static void
> diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
> index b848325..eda24be 100644
> --- a/src/amd/vulkan/si_cmd_buffer.c
> +++ b/src/amd/vulkan/si_cmd_buffer.c
> @@ -242,6 +242,9 @@ si_emit_config(struct radv_physical_device 
> *physical_device,
> radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 
> 0);
>
> radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
> +   radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
> +   if (physical_device->rad_info.chip_class >= GFX9)
> +   radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF, 0);
> radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
> if (physical_device->rad_info.chip_class < CIK)
> radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, 
> S_008A14_NUM_CLIP_SEQ(3) |
> @@ -374,22 +377,31 @@ si_emit_config(struct radv_physical_device 
> *physical_device,
>
> S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
>
> S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
>
> -   radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
> -   radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
> -   radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
> +   if (physical_device->rad_info.chip_class >= GFX9) {
> +   radeon_set_context_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
> +   radeon_set_context_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
> +   radeon_set_context_reg(cs, R_030928_VGT_INDX_OFFSET, 0);

All registers with offset 0x30xxx are uconfig regs.

Marek

> +   } else {
> +   radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
> +   radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
> +   radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
> +   }
>
> if (physical_device->rad_info.chip_class >= CIK) {
> -   /* If this is 0, Bonaire can hang even if GS isn't being used.
> -* Other chips are unaffected. These are suboptimal values,
> -* but we don't use on-chip GS.
> -*/
> -   radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
> -  S_028A44_ES_VERTS_PER_SUBGRP(64) |
> -  S_028A44_GS_PRIMS_PER_SUBGRP(4));
> -
> -   radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, 
> S_00B51C_CU_EN(0x));
> -   radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
> -   radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, 
> S_00B31C_CU_EN(0x));
> +   if (physical_device->rad_info.chip_class >= GFX9) {
> +   radeon_set_sh_reg(cs, 
> R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0x));
> +   } else {
> +   radeon_set_sh_reg(cs, 
> R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0x));
> +   radeon_set_sh_reg(cs, 
> R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
> +   radeon_set_sh_reg(cs, 
> R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0x));
> +   /* If this is 0, Bonaire can hang even if GS isn't 
> being used.
> +* Other chips are unaffected. These are suboptimal 
> values,
> +* but we don't use on-chip GS.
> +*/
> +   radeon_set_context_reg(cs, 
> R_028A44_VGT_GS_ONCHIP_CNTL,
> +  
> S_028A44_ES_VERTS_PER_SUBGRP(64) 

Re: [Mesa-dev] [PATCH 7/7] util: Add extern c to u_dynarray.h

[Thomas Helland]

2017-06-05 23:27 GMT+02:00 Marek Olšák :
> For the series:
>
> Reviewed-by: Marek Olšák 
>
> Marek
>

As-is? Or with Eric's suggestions of splitting patch 6?
If it is OK as it is, do you mind pushing this for me?
Thanks for the review =)

Regards,
Thomas

>
> On Sat, Jun 3, 2017 at 8:11 PM, Thomas Helland
>  wrote:
>> ---
>>  src/util/u_dynarray.h | 8 
>>  1 file changed, 8 insertions(+)
>>
>> diff --git a/src/util/u_dynarray.h b/src/util/u_dynarray.h
>> index ad3889a7c8..e9109ccd2d 100644
>> --- a/src/util/u_dynarray.h
>> +++ b/src/util/u_dynarray.h
>> @@ -30,6 +30,10 @@
>>  #include 
>>  #include "ralloc.h"
>>
>> +#ifdef __cplusplus
>> +extern "C" {
>> +#endif
>> +
>>  /* A zero-initialized version of this is guaranteed to represent an
>>   * empty array.
>>   *
>> @@ -134,5 +138,9 @@ util_dynarray_trim(struct util_dynarray *buf)
>> for (type *elem = (type *)(buf)->data; \
>>  elem < (type *)((char *)(buf)->data + (buf)->size); elem++)
>>
>> +#ifdef __cplusplus
>> +}
>> +#endif
>> +
>>  #endif /* U_DYNARRAY_H */
>>
>> --
>> 2.13.0
>>
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>> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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[Mesa-dev] [PATCH 2/2] etnaviv: flush resource when binding as sampler view

[Lucas Stach]

As TS is also allowed on sampler resources, we need to make sure to resolve
to self when binding the resource as a texture, to avoid stale content
being sampled.

Signed-off-by: Lucas Stach 
---
 src/gallium/drivers/etnaviv/etnaviv_texture.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/drivers/etnaviv/etnaviv_texture.c 
b/src/gallium/drivers/etnaviv/etnaviv_texture.c
index 6f77af286f26..df77829078c0 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_texture.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_texture.c
@@ -120,6 +120,9 @@ etna_update_sampler_source(struct pipe_sampler_view *view)
   etna_copy_resource(view->context, res->texture, view->texture, 0,
  view->texture->last_level);
   etna_resource(res->texture)->seqno = res->seqno;
+   } else if (etna_resource_needs_flush(res)) {
+  etna_copy_resource(view->context, view->texture, view->texture, 0, 0);
+  res->flush_seqno = res->seqno;
}
 }
 
-- 
2.11.0

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[Mesa-dev] [PATCH 1/2] etnaviv: don't flush resource to self without TS

[Lucas Stach]

From: Lucas Stach 

A resolve to self is only necessary if the resource is fast cleared, so
there is never a need to do so if there is no TS allocated.

Signed-off-by: Lucas Stach 
---
 src/gallium/drivers/etnaviv/etnaviv_resource.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.h 
b/src/gallium/drivers/etnaviv/etnaviv_resource.h
index a8d42ee1a09f..1084103386ef 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_resource.h
+++ b/src/gallium/drivers/etnaviv/etnaviv_resource.h
@@ -102,7 +102,7 @@ etna_resource_older(struct etna_resource *a, struct 
etna_resource *b)
 static inline bool
 etna_resource_needs_flush(struct etna_resource *res)
 {
-   return (int)(res->seqno - res->flush_seqno) > 0;
+   return res->ts_bo && ((int)(res->seqno - res->flush_seqno) > 0);
 }
 
 /* is the resource only used on the sampler? */
-- 
2.11.0

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Re: [Mesa-dev] [PATCH 7/7] util: Add extern c to u_dynarray.h

[Marek Olšák]

On Tue, Jun 6, 2017 at 12:07 PM, Thomas Helland
 wrote:
> 2017-06-05 23:27 GMT+02:00 Marek Olšák :
>> For the series:
>>
>> Reviewed-by: Marek Olšák 
>>
>> Marek
>>
>
> As-is? Or with Eric's suggestions of splitting patch 6?
> If it is OK as it is, do you mind pushing this for me?
> Thanks for the review =)

You can apply Eric's suggestions and then send me a git link I can
pull from. In parallel with that, you can apply for an FDO account.

Marek
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Re: [Mesa-dev] [PATCH 3/6] etnaviv: honor PIPE_TRANSFER_UNSYNCHRONIZED flag

[Lucas Stach]

Am Dienstag, den 30.05.2017, 17:40 +0200 schrieb Philipp Zabel:
> On Fri, 2017-05-19 at 11:41 +0200, Lucas Stach wrote:
> > This gets rid of quite a bit of CPU/GPU sync on frequent vertex buffer
> > uploads and I haven't seen any of the issues mentioned in the comment,
> > so this one seems stale.
> > 
> > Ignore the flag if there exists a temporary resource, as those ones are
> > never busy.
> > 
> > Signed-off-by: Lucas Stach 
> > ---
> >  src/gallium/drivers/etnaviv/etnaviv_transfer.c | 22 ++
> >  1 file changed, 10 insertions(+), 12 deletions(-)
> > 
> > diff --git a/src/gallium/drivers/etnaviv/etnaviv_transfer.c 
> > b/src/gallium/drivers/etnaviv/etnaviv_transfer.c
> > index 269bd498f89f..a2cd4e6234dd 100644
> > --- a/src/gallium/drivers/etnaviv/etnaviv_transfer.c
> > +++ b/src/gallium/drivers/etnaviv/etnaviv_transfer.c
> > @@ -114,7 +114,7 @@ etna_transfer_unmap(struct pipe_context *pctx, struct 
> > pipe_transfer *ptrans)
> >}
> > }
> >  
> > -   if (!trans->rsc)
> > +   if (!trans->rsc && !(ptrans->usage & PIPE_TRANSFER_UNSYNCHRONIZED))
> 
> As we just talked about, this looks like it should be '||' ...

This is actually correct as-is, the || below is for the "have temp
resource" case, while this cpu_fini is for the "no temp resource" path.

This deserves a comment, which I'll add before pushing out.

Regards,
Lucas

> >etna_bo_cpu_fini(rsc->bo);
> >  
> > pipe_resource_reference(&trans->rsc, NULL);
> > @@ -260,19 +260,17 @@ etna_transfer_map(struct pipe_context *pctx, struct 
> > pipe_resource *prsc,
> > (rsc->layout == ETNA_LAYOUT_TILED &&
> >  util_format_is_compressed(prsc->format));
> >  
> > -   /* Ignore PIPE_TRANSFER_UNSYNCHRONIZED and PIPE_TRANSFER_DONTBLOCK here.
> > -* It appears that Gallium operates the index/vertex buffers in a
> > -* circular fashion, and the CPU can catch up with the GPU and starts
> > -* overwriting yet-to-be-processed entries, causing rendering 
> > corruption. */
> > -   uint32_t prep_flags = 0;
> > +   if (trans->rsc || !(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
> 
> ... for symmetry with etna_bo_cpu_prep call below.
> 
> > +  uint32_t prep_flags = 0;
> >  
> > -   if (usage & PIPE_TRANSFER_READ)
> > -  prep_flags |= DRM_ETNA_PREP_READ;
> > -   if (usage & PIPE_TRANSFER_WRITE)
> > -  prep_flags |= DRM_ETNA_PREP_WRITE;
> > +  if (usage & PIPE_TRANSFER_READ)
> > + prep_flags |= DRM_ETNA_PREP_READ;
> > +  if (usage & PIPE_TRANSFER_WRITE)
> > + prep_flags |= DRM_ETNA_PREP_WRITE;
> >  
> > -   if (etna_bo_cpu_prep(rsc->bo, prep_flags))
> > -  goto fail_prep;
> > +  if (etna_bo_cpu_prep(rsc->bo, prep_flags))
> > + goto fail_prep;
> > +   }
> >  
> > /* map buffer object */
> > void *mapped = etna_bo_map(rsc->bo);
> 
> regards
> Philipp
> 
> ___
> etnaviv mailing list
> etna...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/etnaviv


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Re: [Mesa-dev] [PATCH v2 02/23] mesa: add KHR_no_error support for glVertexArrayVertexBuffers()

[Samuel Pitoiset]

On 06/06/2017 01:04 AM, Fredrik Höglund wrote:

On Monday 05 June 2017, Samuel Pitoiset wrote:

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Timothy Arceri 
---
  src/mapi/glapi/gen/ARB_direct_state_access.xml |  2 +-
  src/mesa/main/varray.c | 15 +++
  src/mesa/main/varray.h |  6 ++
  3 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/src/mapi/glapi/gen/ARB_direct_state_access.xml 
b/src/mapi/glapi/gen/ARB_direct_state_access.xml
index f13a1444a9..cb24d7981c 100644
--- a/src/mapi/glapi/gen/ARB_direct_state_access.xml
+++ b/src/mapi/glapi/gen/ARB_direct_state_access.xml
@@ -607,7 +607,7 @@

 
  
-   

+   



diff --git a/src/mesa/main/varray.c b/src/mesa/main/varray.c
index c2c771c173..0cc8b56c64 100644
--- a/src/mesa/main/varray.c
+++ b/src/mesa/main/varray.c
@@ -2273,6 +2273,21 @@ _mesa_BindVertexBuffers(GLuint first, GLsizei count, 
const GLuint *buffers,
  
  
  void GLAPIENTRY

+_mesa_VertexArrayVertexBuffers_no_error(GLuint vaobj, GLuint first,
+GLsizei count, const GLuint *buffers,
+const GLintptr *offsets,
+const GLsizei *strides)
+{
+   GET_CURRENT_CONTEXT(ctx);
+
+   struct gl_vertex_array_object *vao = _mesa_lookup_vao(ctx, vaobj);


_mesa_lookup_vao_err() has an optimization for DSA entry points
in that it keeps a reference to the last looked up VAO in the context,
and checks if the ID of that object matches the requested ID before
it calls _mesa_HashLookup(). The idea is that when a client makes a
series of calls like this:

glVertexArrayAttribFormat(vaobj, ...);
glVertexArrayAttribBinding(vaobj, ...);
glEnableVertexArrayAttrib(vaobj, ...);

We only look up the object once.

By using _mesa_lookup_vao() here, you bypass that optimization.

That being said, glVertexArrayVertexBuffers() may be the one vertex
array function that doesn't benefit from that optimization.


Your are right, thanks for reporting this. I will probably change this 
to try to keep that optimization.





+   vertex_array_vertex_buffers(ctx, vao, first, count,
+   buffers, offsets, strides, true,
+   "glVertexArrayVertexBuffers");
+}
+
+
+void GLAPIENTRY
  _mesa_VertexArrayVertexBuffers(GLuint vaobj, GLuint first, GLsizei count,
 const GLuint *buffers,
 const GLintptr *offsets, const GLsizei 
*strides)
diff --git a/src/mesa/main/varray.h b/src/mesa/main/varray.h
index 24e37a9bf7..90ca8483ca 100644
--- a/src/mesa/main/varray.h
+++ b/src/mesa/main/varray.h
@@ -379,6 +379,12 @@ extern void GLAPIENTRY
  _mesa_BindVertexBuffers(GLuint first, GLsizei count, const GLuint *buffers,
  const GLintptr *offsets, const GLsizei *strides);
  
+void GLAPIENTRY

+_mesa_VertexArrayVertexBuffers_no_error(GLuint vaobj, GLuint first,
+GLsizei count, const GLuint *buffers,
+const GLintptr *offsets,
+const GLsizei *strides);
+
  extern void GLAPIENTRY
  _mesa_VertexArrayVertexBuffers(GLuint vaobj, GLuint first, GLsizei count,
 const GLuint *buffers,




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Re: [Mesa-dev] [PATCH 1/2] etnaviv: don't flush resource to self without TS

[Wladimir J. van der Laan]

On Tue, Jun 06, 2017 at 12:38:23PM +0200, Lucas Stach wrote:
> From: Lucas Stach 
> 
> A resolve to self is only necessary if the resource is fast cleared, so
> there is never a need to do so if there is no TS allocated.
> 
> Signed-off-by: Lucas Stach 

Does this take into account the case on GC2000, where there can be a texture 
resource
that is out of date with the rendered-to resource?

If so:
Reviewed-By: Wladimir J. van der Laan 

> ---
>  src/gallium/drivers/etnaviv/etnaviv_resource.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.h 
> b/src/gallium/drivers/etnaviv/etnaviv_resource.h
> index a8d42ee1a09f..1084103386ef 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_resource.h
> +++ b/src/gallium/drivers/etnaviv/etnaviv_resource.h
> @@ -102,7 +102,7 @@ etna_resource_older(struct etna_resource *a, struct 
> etna_resource *b)
>  static inline bool
>  etna_resource_needs_flush(struct etna_resource *res)
>  {
> -   return (int)(res->seqno - res->flush_seqno) > 0;
> +   return res->ts_bo && ((int)(res->seqno - res->flush_seqno) > 0);
>  }
>  
>  /* is the resource only used on the sampler? */
> -- 
> 2.11.0
> 
> ___
> etnaviv mailing list
> etna...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/etnaviv
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[Mesa-dev] [PATCH] android: build system changes for Vulkan utilities move

[Tapani Pälli]

Signed-off-by: Tapani Pälli 
---

Android build system changes required for:
   https://lists.freedesktop.org/archives/mesa-dev/2017-June/158027.html

 Android.common.mk   | 1 +
 src/intel/Android.vulkan.mk | 1 +
 src/vulkan/Android.mk   | 2 ++
 3 files changed, 4 insertions(+)

diff --git a/Android.common.mk b/Android.common.mk
index bf4d709..c2de22b 100644
--- a/Android.common.mk
+++ b/Android.common.mk
@@ -38,6 +38,7 @@ LOCAL_CFLAGS += \
-Wno-missing-field-initializers \
-Wno-initializer-overrides \
-Wno-mismatched-tags \
+   -DVERSION=\"$(MESA_VERSION)\" \
-DPACKAGE_VERSION=\"$(MESA_VERSION)\" \

-DPACKAGE_BUGREPORT=\"https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa\";
 
diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk
index be23a00..0bca2ad 100644
--- a/src/intel/Android.vulkan.mk
+++ b/src/intel/Android.vulkan.mk
@@ -31,6 +31,7 @@ VULKAN_COMMON_INCLUDES := \
$(MESA_TOP)/src/gallium/include \
$(MESA_TOP)/src/mesa \
$(MESA_TOP)/src/vulkan/wsi \
+   $(MESA_TOP)/src/vulkan/util \
$(MESA_TOP)/src/intel \
$(MESA_TOP)/src/intel/vulkan \
frameworks/native/libs/nativewindow/include \
diff --git a/src/vulkan/Android.mk b/src/vulkan/Android.mk
index 2e34093..c8b886d 100644
--- a/src/vulkan/Android.mk
+++ b/src/vulkan/Android.mk
@@ -44,6 +44,8 @@ LOCAL_C_INCLUDES := \
 LOCAL_GENERATED_SOURCES := $(addprefix $(intermediates)/, \
$(VULKAN_UTIL_GENERATED_FILES))
 
+LOCAL_SRC_FILES := $(VULKAN_UTIL_FILES))
+
 vulkan_api_xml = $(MESA_TOP)/src/vulkan/registry/vk.xml
 
 $(LOCAL_GENERATED_SOURCES): $(MESA_TOP)/src/vulkan/util/gen_enum_to_str.py 
$(vulkan_api_xml)
-- 
2.9.4

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Re: [Mesa-dev] [PATCH 1/3] util/vulkan: Move Vulkan utilities to src/vulkan/util

[Tapani Pälli]

Looks nice to me, I've sent required changes to Android build system for 
this change as addition.


On 06/06/2017 12:42 PM, Alex Smith wrote:

We have Vulkan utilities in both src/util and src/vulkan/util. The
latter seems a more appropriate place for Vulkan-specific things, so
move them there.

Signed-off-by: Alex Smith 
---
  src/amd/vulkan/radv_device.c| 2 +-
  src/amd/vulkan/radv_formats.c   | 3 ++-
  src/amd/vulkan/radv_private.h   | 2 +-
  src/amd/vulkan/radv_wsi.c   | 2 +-
  src/intel/vulkan/anv_device.c   | 2 +-
  src/intel/vulkan/anv_formats.c  | 3 +--
  src/intel/vulkan/anv_pass.c | 2 +-
  src/intel/vulkan/anv_private.h  | 2 +-
  src/intel/vulkan/anv_queue.c| 2 +-
  src/intel/vulkan/anv_wsi.c  | 2 +-
  src/intel/vulkan/genX_cmd_buffer.c  | 2 +-
  src/util/Makefile.sources   | 4 +---
  src/vulkan/Makefile.am  | 7 ++-
  src/vulkan/Makefile.sources | 4 
  src/{ => vulkan}/util/vk_alloc.h| 0
  src/{ => vulkan}/util/vk_util.h | 0
  src/vulkan/wsi/wsi_common.h | 2 +-
  src/vulkan/wsi/wsi_common_wayland.c | 2 +-
  src/vulkan/wsi/wsi_common_x11.c | 2 +-
  19 files changed, 26 insertions(+), 19 deletions(-)
  rename src/{ => vulkan}/util/vk_alloc.h (100%)
  rename src/{ => vulkan}/util/vk_util.h (100%)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 887916f..a812527 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -33,7 +33,7 @@
  #include "radv_cs.h"
  #include "util/disk_cache.h"
  #include "util/strtod.h"
-#include "util/vk_util.h"
+#include "vk_util.h"
  #include 
  #include 
  #include 
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index 6cff0a5..b13adb9 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -28,7 +28,8 @@
  #include "sid.h"
  #include "r600d_common.h"
  
-#include "util/vk_util.h"

+#include "vk_util.h"
+
  #include "util/u_half.h"
  #include "util/format_srgb.h"
  #include "util/format_r11g11b10f.h"
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index ed80ba7..a3920a7 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -47,8 +47,8 @@
  #include "compiler/shader_enums.h"
  #include "util/macros.h"
  #include "util/list.h"
-#include "util/vk_alloc.h"
  #include "main/macros.h"
+#include "vk_alloc.h"
  
  #include "radv_radeon_winsys.h"

  #include "ac_binary.h"
diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index 51fe159..cdb04ca 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -26,7 +26,7 @@
  #include "radv_private.h"
  #include "radv_meta.h"
  #include "wsi_common.h"
-#include "util/vk_util.h"
+#include "vk_util.h"
  
  static const struct wsi_callbacks wsi_cbs = {

 .get_phys_device_format_properties = 
radv_GetPhysicalDeviceFormatProperties,
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index aacd07f..6079588 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -35,7 +35,7 @@
  #include "util/debug.h"
  #include "util/build_id.h"
  #include "util/mesa-sha1.h"
-#include "util/vk_util.h"
+#include "vk_util.h"
  
  #include "genxml/gen7_pack.h"
  
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c

index 25801e8..104d4f7 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -23,8 +23,7 @@
  
  #include "anv_private.h"

  #include "vk_format_info.h"
-
-#include "util/vk_util.h"
+#include "vk_util.h"
  
  /*

   * gcc-4 and earlier don't allow compound literals where a constant
diff --git a/src/intel/vulkan/anv_pass.c b/src/intel/vulkan/anv_pass.c
index 93f1483..1b30c14 100644
--- a/src/intel/vulkan/anv_pass.c
+++ b/src/intel/vulkan/anv_pass.c
@@ -23,7 +23,7 @@
  
  #include "anv_private.h"
  
-#include "util/vk_util.h"

+#include "vk_util.h"
  
  static unsigned

  num_subpass_attachments(const VkSubpassDescription *desc)
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index c261faa..fe6ac3b 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -47,7 +47,7 @@
  #include "util/macros.h"
  #include "util/list.h"
  #include "util/u_vector.h"
-#include "util/vk_alloc.h"
+#include "vk_alloc.h"
  
  /* Pre-declarations needed for WSI entrypoints */

  struct wl_surface;
diff --git a/src/intel/vulkan/anv_queue.c b/src/intel/vulkan/anv_queue.c
index be7fd31..fd4d362 100644
--- a/src/intel/vulkan/anv_queue.c
+++ b/src/intel/vulkan/anv_queue.c
@@ -30,7 +30,7 @@
  #include 
  
  #include "anv_private.h"

-#include "util/vk_util.h"
+#include "vk_util.h"
  
  #include "genxml/gen7_pack.h"
  
diff --git a/src/intel/vulkan/anv_wsi.c b/src/intel/vulkan/anv_wsi.c

index 7575f58..9369f26 100644
--- a/src/intel/vulkan/anv_wsi.c
+++ b/src/intel/vulkan/anv_wsi.c
@@ -24,7 +24,7 @@
  #include "anv_p

Re: [Mesa-dev] [PATCH 1/3] util/vulkan: Move Vulkan utilities to src/vulkan/util

[Alex Smith]

Aha, sorry, I missed that. Do you want me to fold your patch into this one
and send a v2?

Alex

On 6 June 2017 at 12:11, Tapani Pälli  wrote:

> Looks nice to me, I've sent required changes to Android build system for
> this change as addition.
>
>
> On 06/06/2017 12:42 PM, Alex Smith wrote:
>
>> We have Vulkan utilities in both src/util and src/vulkan/util. The
>> latter seems a more appropriate place for Vulkan-specific things, so
>> move them there.
>>
>> Signed-off-by: Alex Smith 
>> ---
>>   src/amd/vulkan/radv_device.c| 2 +-
>>   src/amd/vulkan/radv_formats.c   | 3 ++-
>>   src/amd/vulkan/radv_private.h   | 2 +-
>>   src/amd/vulkan/radv_wsi.c   | 2 +-
>>   src/intel/vulkan/anv_device.c   | 2 +-
>>   src/intel/vulkan/anv_formats.c  | 3 +--
>>   src/intel/vulkan/anv_pass.c | 2 +-
>>   src/intel/vulkan/anv_private.h  | 2 +-
>>   src/intel/vulkan/anv_queue.c| 2 +-
>>   src/intel/vulkan/anv_wsi.c  | 2 +-
>>   src/intel/vulkan/genX_cmd_buffer.c  | 2 +-
>>   src/util/Makefile.sources   | 4 +---
>>   src/vulkan/Makefile.am  | 7 ++-
>>   src/vulkan/Makefile.sources | 4 
>>   src/{ => vulkan}/util/vk_alloc.h| 0
>>   src/{ => vulkan}/util/vk_util.h | 0
>>   src/vulkan/wsi/wsi_common.h | 2 +-
>>   src/vulkan/wsi/wsi_common_wayland.c | 2 +-
>>   src/vulkan/wsi/wsi_common_x11.c | 2 +-
>>   19 files changed, 26 insertions(+), 19 deletions(-)
>>   rename src/{ => vulkan}/util/vk_alloc.h (100%)
>>   rename src/{ => vulkan}/util/vk_util.h (100%)
>>
>> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
>> index 887916f..a812527 100644
>> --- a/src/amd/vulkan/radv_device.c
>> +++ b/src/amd/vulkan/radv_device.c
>> @@ -33,7 +33,7 @@
>>   #include "radv_cs.h"
>>   #include "util/disk_cache.h"
>>   #include "util/strtod.h"
>> -#include "util/vk_util.h"
>> +#include "vk_util.h"
>>   #include 
>>   #include 
>>   #include 
>> diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.
>> c
>> index 6cff0a5..b13adb9 100644
>> --- a/src/amd/vulkan/radv_formats.c
>> +++ b/src/amd/vulkan/radv_formats.c
>> @@ -28,7 +28,8 @@
>>   #include "sid.h"
>>   #include "r600d_common.h"
>>   -#include "util/vk_util.h"
>> +#include "vk_util.h"
>> +
>>   #include "util/u_half.h"
>>   #include "util/format_srgb.h"
>>   #include "util/format_r11g11b10f.h"
>> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.
>> h
>> index ed80ba7..a3920a7 100644
>> --- a/src/amd/vulkan/radv_private.h
>> +++ b/src/amd/vulkan/radv_private.h
>> @@ -47,8 +47,8 @@
>>   #include "compiler/shader_enums.h"
>>   #include "util/macros.h"
>>   #include "util/list.h"
>> -#include "util/vk_alloc.h"
>>   #include "main/macros.h"
>> +#include "vk_alloc.h"
>> #include "radv_radeon_winsys.h"
>>   #include "ac_binary.h"
>> diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
>> index 51fe159..cdb04ca 100644
>> --- a/src/amd/vulkan/radv_wsi.c
>> +++ b/src/amd/vulkan/radv_wsi.c
>> @@ -26,7 +26,7 @@
>>   #include "radv_private.h"
>>   #include "radv_meta.h"
>>   #include "wsi_common.h"
>> -#include "util/vk_util.h"
>> +#include "vk_util.h"
>> static const struct wsi_callbacks wsi_cbs = {
>>  .get_phys_device_format_properties = radv_GetPhysicalDeviceFormatPr
>> operties,
>> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.
>> c
>> index aacd07f..6079588 100644
>> --- a/src/intel/vulkan/anv_device.c
>> +++ b/src/intel/vulkan/anv_device.c
>> @@ -35,7 +35,7 @@
>>   #include "util/debug.h"
>>   #include "util/build_id.h"
>>   #include "util/mesa-sha1.h"
>> -#include "util/vk_util.h"
>> +#include "vk_util.h"
>> #include "genxml/gen7_pack.h"
>>   diff --git a/src/intel/vulkan/anv_formats.c
>> b/src/intel/vulkan/anv_formats.c
>> index 25801e8..104d4f7 100644
>> --- a/src/intel/vulkan/anv_formats.c
>> +++ b/src/intel/vulkan/anv_formats.c
>> @@ -23,8 +23,7 @@
>> #include "anv_private.h"
>>   #include "vk_format_info.h"
>> -
>> -#include "util/vk_util.h"
>> +#include "vk_util.h"
>> /*
>>* gcc-4 and earlier don't allow compound literals where a constant
>> diff --git a/src/intel/vulkan/anv_pass.c b/src/intel/vulkan/anv_pass.c
>> index 93f1483..1b30c14 100644
>> --- a/src/intel/vulkan/anv_pass.c
>> +++ b/src/intel/vulkan/anv_pass.c
>> @@ -23,7 +23,7 @@
>> #include "anv_private.h"
>>   -#include "util/vk_util.h"
>> +#include "vk_util.h"
>> static unsigned
>>   num_subpass_attachments(const VkSubpassDescription *desc)
>> diff --git a/src/intel/vulkan/anv_private.h
>> b/src/intel/vulkan/anv_private.h
>> index c261faa..fe6ac3b 100644
>> --- a/src/intel/vulkan/anv_private.h
>> +++ b/src/intel/vulkan/anv_private.h
>> @@ -47,7 +47,7 @@
>>   #include "util/macros.h"
>>   #include "util/list.h"
>>   #include "util/u_vector.h"
>> -#include "util/vk_alloc.h"
>> +#include "vk_alloc.h"
>> /* Pre-declarations needed for WSI entrypoints */
>>   struct wl_surfa

Re: [Mesa-dev] [PATCH 2/6] etnaviv: slim down resource waiting

[Wladimir J. van der Laan]

On Fri, May 19, 2017 at 11:41:08AM +0200, Lucas Stach wrote:
> cpu_prep() already does all the required waiting, so the only thing that
> needs to be done is flushing the commandstream, if a GPU write is pending.

Looks good to me.

Reviewed-By: Wladimir J. van der Laan 

> Signed-off-by: Lucas Stach 
> ---
>  src/gallium/drivers/etnaviv/etnaviv_clear_blit.c |  5 +++--
>  src/gallium/drivers/etnaviv/etnaviv_resource.c   | 16 
>  src/gallium/drivers/etnaviv/etnaviv_resource.h   |  3 ---
>  src/gallium/drivers/etnaviv/etnaviv_transfer.c   |  5 +++--
>  4 files changed, 6 insertions(+), 23 deletions(-)
> 
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c 
> b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
> index ae1c5862880f..ea416bf192f3 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
> @@ -528,8 +528,9 @@ etna_try_rs_blit(struct pipe_context *pctx,
>  
>  manual:
> if (src->layout == ETNA_LAYOUT_TILED && dst->layout == ETNA_LAYOUT_TILED) 
> {
> -  etna_resource_wait(pctx, dst);
> -  etna_resource_wait(pctx, src);
> +  if ((src->status & ETNA_PENDING_WRITE) ||
> +  (dst->status & ETNA_PENDING_WRITE))
> + pctx->flush(pctx, NULL, 0);
>return etna_manual_blit(dst, dst_lev, dst_offset, src, src_lev, 
> src_offset, blit_info);
> }
>  
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.c 
> b/src/gallium/drivers/etnaviv/etnaviv_resource.c
> index 1341e1ea2314..9aa1aa617a51 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_resource.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_resource.c
> @@ -429,22 +429,6 @@ etna_resource_used(struct etna_context *ctx, struct 
> pipe_resource *prsc,
>  }
>  
>  void
> -etna_resource_wait(struct pipe_context *pctx, struct etna_resource *rsc)
> -{
> -   if (rsc->status & ETNA_PENDING_WRITE) {
> -  struct pipe_fence_handle *fence;
> -  struct pipe_screen *pscreen = pctx->screen;
> -
> -  pctx->flush(pctx, &fence, 0);
> -
> -  if (!pscreen->fence_finish(pscreen, pctx, fence, 50ULL))
> - BUG("fence timed out (hung GPU?)");
> -
> -  pscreen->fence_reference(pscreen, &fence, NULL);
> -   }
> -}
> -
> -void
>  etna_resource_screen_init(struct pipe_screen *pscreen)
>  {
> pscreen->can_create_resource = etna_screen_can_create_resource;
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.h 
> b/src/gallium/drivers/etnaviv/etnaviv_resource.h
> index a8d42ee1a09f..913316f193c2 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_resource.h
> +++ b/src/gallium/drivers/etnaviv/etnaviv_resource.h
> @@ -124,9 +124,6 @@ void
>  etna_resource_used(struct etna_context *ctx, struct pipe_resource *prsc,
> enum etna_resource_status status);
>  
> -void
> -etna_resource_wait(struct pipe_context *ctx, struct etna_resource *rsc);
> -
>  static inline void
>  resource_read(struct etna_context *ctx, struct pipe_resource *prsc)
>  {
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_transfer.c 
> b/src/gallium/drivers/etnaviv/etnaviv_transfer.c
> index 4809b04ff95f..269bd498f89f 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_transfer.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_transfer.c
> @@ -199,8 +199,9 @@ etna_transfer_map(struct pipe_context *pctx, struct 
> pipe_resource *prsc,
> /* Always sync if we have the temporary resource.  The PIPE_TRANSFER_READ
>  * case could be optimised if we knew whether the resource has outstanding
>  * rendering. */
> -   if (usage & PIPE_TRANSFER_READ || trans->rsc)
> -  etna_resource_wait(pctx, rsc);
> +   if ((usage & PIPE_TRANSFER_READ || trans->rsc) &&
> +   rsc->status & ETNA_PENDING_WRITE)
> +  pctx->flush(pctx, NULL, 0);
>  
> /* XXX we don't handle PIPE_TRANSFER_FLUSH_EXPLICIT; this flag can be 
> ignored
>  * when mapping in-place,
> -- 
> 2.11.0
> 
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Re: [Mesa-dev] [PATCH 1/3] util/vulkan: Move Vulkan utilities to src/vulkan/util

[Tapani Pälli]

On 06/06/2017 02:13 PM, Alex Smith wrote:
Aha, sorry, I missed that. Do you want me to fold your patch into this 
one and send a v2?


That would be ideal as working build makes bisecting a lot less painful, 
thanks!



Alex

On 6 June 2017 at 12:11, Tapani Pälli > wrote:


Looks nice to me, I've sent required changes to Android build system
for this change as addition.


On 06/06/2017 12:42 PM, Alex Smith wrote:

We have Vulkan utilities in both src/util and src/vulkan/util. The
latter seems a more appropriate place for Vulkan-specific things, so
move them there.

Signed-off-by: Alex Smith mailto:asm...@feralinteractive.com>>
---
   src/amd/vulkan/radv_device.c| 2 +-
   src/amd/vulkan/radv_formats.c   | 3 ++-
   src/amd/vulkan/radv_private.h   | 2 +-
   src/amd/vulkan/radv_wsi.c   | 2 +-
   src/intel/vulkan/anv_device.c   | 2 +-
   src/intel/vulkan/anv_formats.c  | 3 +--
   src/intel/vulkan/anv_pass.c | 2 +-
   src/intel/vulkan/anv_private.h  | 2 +-
   src/intel/vulkan/anv_queue.c| 2 +-
   src/intel/vulkan/anv_wsi.c  | 2 +-
   src/intel/vulkan/genX_cmd_buffer.c  | 2 +-
   src/util/Makefile.sources   | 4 +---
   src/vulkan/Makefile.am  | 7 ++-
   src/vulkan/Makefile.sources | 4 
   src/{ => vulkan}/util/vk_alloc.h| 0
   src/{ => vulkan}/util/vk_util.h | 0
   src/vulkan/wsi/wsi_common.h | 2 +-
   src/vulkan/wsi/wsi_common_wayland.c | 2 +-
   src/vulkan/wsi/wsi_common_x11.c | 2 +-
   19 files changed, 26 insertions(+), 19 deletions(-)
   rename src/{ => vulkan}/util/vk_alloc.h (100%)
   rename src/{ => vulkan}/util/vk_util.h (100%)

diff --git a/src/amd/vulkan/radv_device.c
b/src/amd/vulkan/radv_device.c
index 887916f..a812527 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -33,7 +33,7 @@
   #include "radv_cs.h"
   #include "util/disk_cache.h"
   #include "util/strtod.h"
-#include "util/vk_util.h"
+#include "vk_util.h"
   #include 
   #include 
   #include 
diff --git a/src/amd/vulkan/radv_formats.c
b/src/amd/vulkan/radv_formats.c
index 6cff0a5..b13adb9 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -28,7 +28,8 @@
   #include "sid.h"
   #include "r600d_common.h"
   -#include "util/vk_util.h"
+#include "vk_util.h"
+
   #include "util/u_half.h"
   #include "util/format_srgb.h"
   #include "util/format_r11g11b10f.h"
diff --git a/src/amd/vulkan/radv_private.h
b/src/amd/vulkan/radv_private.h
index ed80ba7..a3920a7 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -47,8 +47,8 @@
   #include "compiler/shader_enums.h"
   #include "util/macros.h"
   #include "util/list.h"
-#include "util/vk_alloc.h"
   #include "main/macros.h"
+#include "vk_alloc.h"
 #include "radv_radeon_winsys.h"
   #include "ac_binary.h"
diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index 51fe159..cdb04ca 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -26,7 +26,7 @@
   #include "radv_private.h"
   #include "radv_meta.h"
   #include "wsi_common.h"
-#include "util/vk_util.h"
+#include "vk_util.h"
 static const struct wsi_callbacks wsi_cbs = {
  .get_phys_device_format_properties =
radv_GetPhysicalDeviceFormatProperties,
diff --git a/src/intel/vulkan/anv_device.c
b/src/intel/vulkan/anv_device.c
index aacd07f..6079588 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -35,7 +35,7 @@
   #include "util/debug.h"
   #include "util/build_id.h"
   #include "util/mesa-sha1.h"
-#include "util/vk_util.h"
+#include "vk_util.h"
 #include "genxml/gen7_pack.h"
   diff --git a/src/intel/vulkan/anv_formats.c
b/src/intel/vulkan/anv_formats.c
index 25801e8..104d4f7 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -23,8 +23,7 @@
 #include "anv_private.h"
   #include "vk_format_info.h"
-
-#include "util/vk_util.h"
+#include "vk_util.h"
 /*
* gcc-4 and earlier don't allow compound literals where a
constant
diff --git a/s

Re: [Mesa-dev] [PATCH 3/6] etnaviv: honor PIPE_TRANSFER_UNSYNCHRONIZED flag

[Wladimir J. van der Laan]

On Fri, May 19, 2017 at 11:41:09AM +0200, Lucas Stach wrote:
> This gets rid of quite a bit of CPU/GPU sync on frequent vertex buffer
> uploads and I haven't seen any of the issues mentioned in the comment,
> so this one seems stale.

Interesting. I don't quite remember what prompted adding this, it may have to
do with other hacks to support single-vertex-stream GPUs which have since been
removed, so it's likely stale.

In any case heeding PIPE_TRANSFER_UNSYNCHRONIZED makes sense. It should not just
be ignored because the driver thinks it knows better.

> Ignore the flag if there exists a temporary resource, as those ones are
> never busy.

OK. 

Reviewed-By: Wladimir J. van der Laan 

> Signed-off-by: Lucas Stach 
> ---
>  src/gallium/drivers/etnaviv/etnaviv_transfer.c | 22 ++
>  1 file changed, 10 insertions(+), 12 deletions(-)
> 
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_transfer.c 
> b/src/gallium/drivers/etnaviv/etnaviv_transfer.c
> index 269bd498f89f..a2cd4e6234dd 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_transfer.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_transfer.c
> @@ -114,7 +114,7 @@ etna_transfer_unmap(struct pipe_context *pctx, struct 
> pipe_transfer *ptrans)
>}
> }
>  
> -   if (!trans->rsc)
> +   if (!trans->rsc && !(ptrans->usage & PIPE_TRANSFER_UNSYNCHRONIZED))
>etna_bo_cpu_fini(rsc->bo);
>  
> pipe_resource_reference(&trans->rsc, NULL);
> @@ -260,19 +260,17 @@ etna_transfer_map(struct pipe_context *pctx, struct 
> pipe_resource *prsc,
> (rsc->layout == ETNA_LAYOUT_TILED &&
>  util_format_is_compressed(prsc->format));
>  
> -   /* Ignore PIPE_TRANSFER_UNSYNCHRONIZED and PIPE_TRANSFER_DONTBLOCK here.
> -* It appears that Gallium operates the index/vertex buffers in a
> -* circular fashion, and the CPU can catch up with the GPU and starts
> -* overwriting yet-to-be-processed entries, causing rendering corruption. 
> */
> -   uint32_t prep_flags = 0;
> +   if (trans->rsc || !(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
> +  uint32_t prep_flags = 0;
>  
> -   if (usage & PIPE_TRANSFER_READ)
> -  prep_flags |= DRM_ETNA_PREP_READ;
> -   if (usage & PIPE_TRANSFER_WRITE)
> -  prep_flags |= DRM_ETNA_PREP_WRITE;
> +  if (usage & PIPE_TRANSFER_READ)
> + prep_flags |= DRM_ETNA_PREP_READ;
> +  if (usage & PIPE_TRANSFER_WRITE)
> + prep_flags |= DRM_ETNA_PREP_WRITE;
>  
> -   if (etna_bo_cpu_prep(rsc->bo, prep_flags))
> -  goto fail_prep;
> +  if (etna_bo_cpu_prep(rsc->bo, prep_flags))
> + goto fail_prep;
> +   }
>  
> /* map buffer object */
> void *mapped = etna_bo_map(rsc->bo);
> -- 
> 2.11.0
> 
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[Mesa-dev] [PATCH v2] util/vulkan: Move Vulkan utilities to src/vulkan/util

[Alex Smith]

We have Vulkan utilities in both src/util and src/vulkan/util. The
latter seems a more appropriate place for Vulkan-specific things, so
move them there.

v2: Android build system changes (from Tapani Pälli)

Signed-off-by: Alex Smith 
---
 Android.common.mk   | 1 +
 src/amd/vulkan/radv_device.c| 2 +-
 src/amd/vulkan/radv_formats.c   | 3 ++-
 src/amd/vulkan/radv_private.h   | 2 +-
 src/amd/vulkan/radv_wsi.c   | 2 +-
 src/intel/Android.vulkan.mk | 1 +
 src/intel/vulkan/anv_device.c   | 2 +-
 src/intel/vulkan/anv_formats.c  | 3 +--
 src/intel/vulkan/anv_pass.c | 2 +-
 src/intel/vulkan/anv_private.h  | 2 +-
 src/intel/vulkan/anv_queue.c| 2 +-
 src/intel/vulkan/anv_wsi.c  | 2 +-
 src/intel/vulkan/genX_cmd_buffer.c  | 2 +-
 src/util/Makefile.sources   | 4 +---
 src/vulkan/Android.mk   | 2 ++
 src/vulkan/Makefile.am  | 7 ++-
 src/vulkan/Makefile.sources | 4 
 src/{ => vulkan}/util/vk_alloc.h| 0
 src/{ => vulkan}/util/vk_util.h | 0
 src/vulkan/wsi/wsi_common.h | 2 +-
 src/vulkan/wsi/wsi_common_wayland.c | 2 +-
 src/vulkan/wsi/wsi_common_x11.c | 2 +-
 22 files changed, 30 insertions(+), 19 deletions(-)
 rename src/{ => vulkan}/util/vk_alloc.h (100%)
 rename src/{ => vulkan}/util/vk_util.h (100%)

diff --git a/Android.common.mk b/Android.common.mk
index 44ad97b..6bd3081 100644
--- a/Android.common.mk
+++ b/Android.common.mk
@@ -37,6 +37,7 @@ LOCAL_CFLAGS += \
-Wno-missing-field-initializers \
-Wno-initializer-overrides \
-Wno-mismatched-tags \
+   -DVERSION=\"$(MESA_VERSION)\" \
-DPACKAGE_VERSION=\"$(MESA_VERSION)\" \

-DPACKAGE_BUGREPORT=\"https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa\";
 
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 887916f..a812527 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -33,7 +33,7 @@
 #include "radv_cs.h"
 #include "util/disk_cache.h"
 #include "util/strtod.h"
-#include "util/vk_util.h"
+#include "vk_util.h"
 #include 
 #include 
 #include 
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index 6cff0a5..b13adb9 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -28,7 +28,8 @@
 #include "sid.h"
 #include "r600d_common.h"
 
-#include "util/vk_util.h"
+#include "vk_util.h"
+
 #include "util/u_half.h"
 #include "util/format_srgb.h"
 #include "util/format_r11g11b10f.h"
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index ed80ba7..a3920a7 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -47,8 +47,8 @@
 #include "compiler/shader_enums.h"
 #include "util/macros.h"
 #include "util/list.h"
-#include "util/vk_alloc.h"
 #include "main/macros.h"
+#include "vk_alloc.h"
 
 #include "radv_radeon_winsys.h"
 #include "ac_binary.h"
diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index 51fe159..cdb04ca 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -26,7 +26,7 @@
 #include "radv_private.h"
 #include "radv_meta.h"
 #include "wsi_common.h"
-#include "util/vk_util.h"
+#include "vk_util.h"
 
 static const struct wsi_callbacks wsi_cbs = {
.get_phys_device_format_properties = radv_GetPhysicalDeviceFormatProperties,
diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk
index 2ede3f7..e31c439 100644
--- a/src/intel/Android.vulkan.mk
+++ b/src/intel/Android.vulkan.mk
@@ -31,6 +31,7 @@ VULKAN_COMMON_INCLUDES := \
$(MESA_TOP)/src/gallium/include \
$(MESA_TOP)/src/mesa \
$(MESA_TOP)/src/vulkan/wsi \
+   $(MESA_TOP)/src/vulkan/util \
$(MESA_TOP)/src/intel \
$(MESA_TOP)/src/intel/vulkan
 
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index aacd07f..6079588 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -35,7 +35,7 @@
 #include "util/debug.h"
 #include "util/build_id.h"
 #include "util/mesa-sha1.h"
-#include "util/vk_util.h"
+#include "vk_util.h"
 
 #include "genxml/gen7_pack.h"
 
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 25801e8..104d4f7 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -23,8 +23,7 @@
 
 #include "anv_private.h"
 #include "vk_format_info.h"
-
-#include "util/vk_util.h"
+#include "vk_util.h"
 
 /*
  * gcc-4 and earlier don't allow compound literals where a constant
diff --git a/src/intel/vulkan/anv_pass.c b/src/intel/vulkan/anv_pass.c
index 93f1483..1b30c14 100644
--- a/src/intel/vulkan/anv_pass.c
+++ b/src/intel/vulkan/anv_pass.c
@@ -23,7 +23,7 @@
 
 #include "anv_private.h"
 
-#include "util/vk_util.h"
+#include "vk_util.h"
 
 static unsigned
 num_subpass_attachments(const VkSubpassDescription *desc)
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.

Re: [Mesa-dev] [PATCH] i965: Don't try to resolve CCS with MESA_FORMAT_NONE.

[Tapani Pälli]

On 06/06/2017 02:58 AM, Kenneth Graunke wrote:

On Monday, June 5, 2017 2:03:45 AM PDT Tapani Pälli wrote:

FWIW this change fixes also regression on Android wallpaper since that
commit.


I'm planning on dropping this patch, as it seems that

commit 708664159e18487b6676fd5b4c33f52003f81d9e
Author: Jason Ekstrand 
Date:   Fri May 26 10:57:33 2017 -0700

 i965: Finalize miptrees before prepare_texture

has already fixed the problem for me.  Hopefully that also fixes the
Android wallpaper issue?



Yep, I verified that it fixes the issue!

// Tapani
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Re: [Mesa-dev] [PATCH 4/6] etnaviv: don't read back resource if transfer discards contents

[Wladimir J. van der Laan]

On Fri, May 19, 2017 at 11:41:10AM +0200, Lucas Stach wrote:
> Reduces bandwidth usage of transfers which discard the buffer contents,
> as well as skipping unnecessary command stream flushes and CPU/GPU
> synchronization.

Looks obviously correct. The contents of the temporary resource
don't matter if DISCARD_WHOLE_RESOURCE.

Reviewed-By: Wladimir J. van der Laan

> Signed-off-by: Lucas Stach 
> ---
>  src/gallium/drivers/etnaviv/etnaviv_transfer.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_transfer.c 
> b/src/gallium/drivers/etnaviv/etnaviv_transfer.c
> index a2cd4e6234dd..f7871f485371 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_transfer.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_transfer.c
> @@ -188,7 +188,9 @@ etna_transfer_map(struct pipe_context *pctx, struct 
> pipe_resource *prsc,
>   return NULL;
>}
>  
> -  etna_copy_resource(pctx, trans->rsc, prsc, level, 
> trans->rsc->last_level);
> +  if (!(usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE))
> + etna_copy_resource(pctx, trans->rsc, prsc, level,
> +trans->rsc->last_level);
>  
>/* Switch to using the temporary resource instead */
>rsc = etna_resource(trans->rsc);
> -- 
> 2.11.0
> 
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Re: [Mesa-dev] [PATCH 1/2] etnaviv: don't flush resource to self without TS

[Lucas Stach]

Am Dienstag, den 06.06.2017, 12:59 +0200 schrieb Wladimir J. van der
Laan:
> On Tue, Jun 06, 2017 at 12:38:23PM +0200, Lucas Stach wrote:
> > From: Lucas Stach 
> > 
> > A resolve to self is only necessary if the resource is fast cleared, so
> > there is never a need to do so if there is no TS allocated.
> > 
> > Signed-off-by: Lucas Stach 
> 
> Does this take into account the case on GC2000, where there can be a texture 
> resource
> that is out of date with the rendered-to resource?

Yes, etna_resource_needs_flush is only used for the self-resolve cases.
Other cases are handled by explicitly comparing the seqno of the
resource with the seqno of the derived (like texture) resources.

Regards,
Lucas

> If so:
> Reviewed-By: Wladimir J. van der Laan 
> 
> > ---
> >  src/gallium/drivers/etnaviv/etnaviv_resource.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.h 
> > b/src/gallium/drivers/etnaviv/etnaviv_resource.h
> > index a8d42ee1a09f..1084103386ef 100644
> > --- a/src/gallium/drivers/etnaviv/etnaviv_resource.h
> > +++ b/src/gallium/drivers/etnaviv/etnaviv_resource.h
> > @@ -102,7 +102,7 @@ etna_resource_older(struct etna_resource *a, struct 
> > etna_resource *b)
> >  static inline bool
> >  etna_resource_needs_flush(struct etna_resource *res)
> >  {
> > -   return (int)(res->seqno - res->flush_seqno) > 0;
> > +   return res->ts_bo && ((int)(res->seqno - res->flush_seqno) > 0);
> >  }
> >  
> >  /* is the resource only used on the sampler? */
> > -- 
> > 2.11.0
> > 
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> > https://lists.freedesktop.org/mailman/listinfo/etnaviv


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Re: [Mesa-dev] [PATCH 5/6] etnaviv: simplify transfer tiling handling

[Wladimir J. van der Laan]

On Fri, May 19, 2017 at 11:41:11AM +0200, Lucas Stach wrote:
> There is no need to special case compressed resources, as they are already
> marked as linear on allocation. With that out of the way, there is room to
> cut down on the number of if clauses used.

Code change looks good to me. Resource layout is explicit, and not dependent
on the compressed-ness of the texture format.

Reviewed-By: Wladimir J. van der Laan 

> Signed-off-by: Lucas Stach 
> ---
>  src/gallium/drivers/etnaviv/etnaviv_transfer.c | 70 
> +++---
>  1 file changed, 29 insertions(+), 41 deletions(-)
> 
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_transfer.c 
> b/src/gallium/drivers/etnaviv/etnaviv_transfer.c
> index f7871f485371..05cdbc599956 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_transfer.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_transfer.c
> @@ -85,21 +85,19 @@ etna_transfer_unmap(struct pipe_context *pctx, struct 
> pipe_transfer *ptrans)
>   struct etna_resource_level *res_level = &rsc->levels[ptrans->level];
>   void *mapped = etna_bo_map(rsc->bo) + res_level->offset;
>  
> - if (rsc->layout == ETNA_LAYOUT_LINEAR || rsc->layout == 
> ETNA_LAYOUT_TILED) {
> -if (rsc->layout == ETNA_LAYOUT_TILED && 
> !util_format_is_compressed(rsc->base.format)) {
> -   etna_texture_tile(
> -  mapped + ptrans->box.z * res_level->layer_stride,
> -  trans->staging, ptrans->box.x, ptrans->box.y,
> -  res_level->stride, ptrans->box.width, ptrans->box.height,
> -  ptrans->stride, 
> util_format_get_blocksize(rsc->base.format));
> -} else { /* non-tiled or compressed format */
> -   util_copy_box(mapped, rsc->base.format, res_level->stride,
> - res_level->layer_stride, ptrans->box.x,
> - ptrans->box.y, ptrans->box.z, ptrans->box.width,
> - ptrans->box.height, ptrans->box.depth,
> - trans->staging, ptrans->stride,
> - ptrans->layer_stride, 0, 0, 0 /* src x,y,z */);
> -}

> + if (rsc->layout == ETNA_LAYOUT_TILED) {
> +etna_texture_tile(
> +   mapped + ptrans->box.z * res_level->layer_stride,
> +   trans->staging, ptrans->box.x, ptrans->box.y,
> +   res_level->stride, ptrans->box.width, ptrans->box.height,
> +   ptrans->stride, util_format_get_blocksize(rsc->base.format));
> + } else if (rsc->layout == ETNA_LAYOUT_LINEAR) {
> +util_copy_box(mapped, rsc->base.format, res_level->stride,
> +  res_level->layer_stride, ptrans->box.x,
> +  ptrans->box.y, ptrans->box.z, ptrans->box.width,
> +  ptrans->box.height, ptrans->box.depth,
> +  trans->staging, ptrans->stride,
> +  ptrans->layer_stride, 0, 0, 0 /* src x,y,z */);
>   } else {
>  BUG("unsupported tiling %i", rsc->layout);
>   }
> @@ -255,13 +253,6 @@ etna_transfer_map(struct pipe_context *pctx, struct 
> pipe_resource *prsc,
>PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE is set.
>  */
>  
> -   /* No need to allocate a buffer for copying if the resource is not in use,
> -* and no tiling is needed, can just return a direct pointer.
> -*/
> -   bool in_place = rsc->layout == ETNA_LAYOUT_LINEAR ||
> -   (rsc->layout == ETNA_LAYOUT_TILED &&
> -util_format_is_compressed(prsc->format));
> -
> if (trans->rsc || !(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
>uint32_t prep_flags = 0;
>  
> @@ -281,7 +272,7 @@ etna_transfer_map(struct pipe_context *pctx, struct 
> pipe_resource *prsc,
>  
> *out_transfer = ptrans;
>  
> -   if (in_place) {
> +   if (rsc->layout == ETNA_LAYOUT_LINEAR) {
>ptrans->stride = res_level->stride;
>ptrans->layer_stride = res_level->layer_stride;
>  
> @@ -308,24 +299,21 @@ etna_transfer_map(struct pipe_context *pctx, struct 
> pipe_resource *prsc,
>   goto fail;
>  
>if (usage & PIPE_TRANSFER_READ) {
> - /* untile or copy resource for reading */
> - if (rsc->layout == ETNA_LAYOUT_LINEAR || rsc->layout == 
> ETNA_LAYOUT_TILED) {
> -if (rsc->layout == ETNA_LAYOUT_TILED && 
> !util_format_is_compressed(rsc->base.format)) {
> -   etna_texture_untile(trans->staging,
> -   mapped + ptrans->box.z * 
> res_level->layer_stride,
> -   ptrans->box.x, ptrans->box.y, 
> res_level->stride,
> -   ptrans->box.width, ptrans->box.height, 
> ptrans->stride,
> -   
> util_format_get_blocksize(rsc->base.format));
> -} else { /* non-tiled or compressed format */
> -   util_copy_b

Re: [Mesa-dev] [PATCH 2/3] radv/vulkan: Move radv_get_driver_version to src/vulkan/util

[Emil Velikov]

Hi Alex,

On 6 June 2017 at 10:42, Alex Smith  wrote:
> This means it can be reused for other Vulkan drivers. Also fix up a
> typo, need to search for '.' in the version string rather than ','.
>
> Signed-off-by: Alex Smith 
> ---

> +uint32_t vk_get_driver_version(void)
> +{
...
> +   uint32_t version = VK_MAKE_VERSION(major, minor, patch);
> +   return version;
Nit: return directly?

Either way, the series is (thanks for the Android squash and dropping
the util/ bit)
Reviewed-by: Emil Velikov 

If anyone wants to pursue the devel vs rc topic, below is an idea how.
Some devs thought it was confusing a while back, so be warned.

17.0.0 dev -> 16.90.0
18.0.0 dev -> 17.90.0

17.0.0 rc1 -> 16.91.0
18.0.0 rc2 -> 17.92.0

17.1.0 dev -> 17.0.90
18.2.0 dev -> 17.1.90

17.1.0 rc1 -> 17.0.91
18.2.0 rc2 -> 18.1.92

-Emil
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Re: [Mesa-dev] [PATCH v2 02/23] mesa: add KHR_no_error support for glVertexArrayVertexBuffers()

[Samuel Pitoiset]

On 06/06/2017 12:57 PM, Samuel Pitoiset wrote:



On 06/06/2017 01:04 AM, Fredrik Höglund wrote:

On Monday 05 June 2017, Samuel Pitoiset wrote:

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Timothy Arceri 
---
  src/mapi/glapi/gen/ARB_direct_state_access.xml |  2 +-
  src/mesa/main/varray.c | 15 +++
  src/mesa/main/varray.h |  6 ++
  3 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/src/mapi/glapi/gen/ARB_direct_state_access.xml 
b/src/mapi/glapi/gen/ARB_direct_state_access.xml

index f13a1444a9..cb24d7981c 100644
--- a/src/mapi/glapi/gen/ARB_direct_state_access.xml
+++ b/src/mapi/glapi/gen/ARB_direct_state_access.xml
@@ -607,7 +607,7 @@

 
-   
+   



diff --git a/src/mesa/main/varray.c b/src/mesa/main/varray.c
index c2c771c173..0cc8b56c64 100644
--- a/src/mesa/main/varray.c
+++ b/src/mesa/main/varray.c
@@ -2273,6 +2273,21 @@ _mesa_BindVertexBuffers(GLuint first, GLsizei 
count, const GLuint *buffers,

  void GLAPIENTRY
+_mesa_VertexArrayVertexBuffers_no_error(GLuint vaobj, GLuint first,
+GLsizei count, const GLuint 
*buffers,

+const GLintptr *offsets,
+const GLsizei *strides)
+{
+   GET_CURRENT_CONTEXT(ctx);
+
+   struct gl_vertex_array_object *vao = _mesa_lookup_vao(ctx, vaobj);


_mesa_lookup_vao_err() has an optimization for DSA entry points
in that it keeps a reference to the last looked up VAO in the context,
and checks if the ID of that object matches the requested ID before
it calls _mesa_HashLookup(). The idea is that when a client makes a
series of calls like this:

glVertexArrayAttribFormat(vaobj, ...);
glVertexArrayAttribBinding(vaobj, ...);
glEnableVertexArrayAttrib(vaobj, ...);

We only look up the object once.

By using _mesa_lookup_vao() here, you bypass that optimization.

That being said, glVertexArrayVertexBuffers() may be the one vertex
array function that doesn't benefit from that optimization.


Your are right, thanks for reporting this. I will probably change this 
to try to keep that optimization.


Oh well, that optimization has been removed to 
glVertexArrayVertexBuffer() when Timothy added KHR_no_error.


I would prefer to keep this patch as-is for now and rework that area in 
a separate series. One thing we can do too is to replace _mesa_HashTable 
with an ordinary hash table, and probably some other improvements here 
and there.







+   vertex_array_vertex_buffers(ctx, vao, first, count,
+   buffers, offsets, strides, true,
+   "glVertexArrayVertexBuffers");
+}
+
+
+void GLAPIENTRY
  _mesa_VertexArrayVertexBuffers(GLuint vaobj, GLuint first, GLsizei 
count,

 const GLuint *buffers,
 const GLintptr *offsets, const 
GLsizei *strides)

diff --git a/src/mesa/main/varray.h b/src/mesa/main/varray.h
index 24e37a9bf7..90ca8483ca 100644
--- a/src/mesa/main/varray.h
+++ b/src/mesa/main/varray.h
@@ -379,6 +379,12 @@ extern void GLAPIENTRY
  _mesa_BindVertexBuffers(GLuint first, GLsizei count, const GLuint 
*buffers,
  const GLintptr *offsets, const GLsizei 
*strides);

+void GLAPIENTRY
+_mesa_VertexArrayVertexBuffers_no_error(GLuint vaobj, GLuint first,
+GLsizei count, const GLuint 
*buffers,

+const GLintptr *offsets,
+const GLsizei *strides);
+
  extern void GLAPIENTRY
  _mesa_VertexArrayVertexBuffers(GLuint vaobj, GLuint first, GLsizei 
count,

 const GLuint *buffers,




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Re: [Mesa-dev] [PATCH 2/3] radv/vulkan: Move radv_get_driver_version to src/vulkan/util

[Eric Engestrom]

On Tuesday, 2017-06-06 10:42:40 +0100, Alex Smith wrote:
> This means it can be reused for other Vulkan drivers. Also fix up a
> typo, need to search for '.' in the version string rather than ','.
> 
> Signed-off-by: Alex Smith 
> ---
>  src/amd/vulkan/radv_device.c | 24 +
>  src/vulkan/Makefile.sources  |  1 +
>  src/vulkan/util/vk_util.c| 50 
> 
>  src/vulkan/util/vk_util.h|  2 ++
>  4 files changed, 54 insertions(+), 23 deletions(-)
>  create mode 100644 src/vulkan/util/vk_util.c
> 
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index a812527..5fdb894 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -574,28 +574,6 @@ void radv_GetPhysicalDeviceFeatures2KHR(
>   return radv_GetPhysicalDeviceFeatures(physicalDevice, 
> &pFeatures->features);
>  }
>  
> -static uint32_t radv_get_driver_version()
> -{
> - const char *minor_string = strchr(VERSION, '.');
> - const char *patch_string = minor_string ? strchr(minor_string + 1, 
> ','): NULL;
> - int major = atoi(VERSION);
> - int minor = minor_string ? atoi(minor_string + 1) : 0;
> - int patch = patch_string ? atoi(patch_string + 1) : 0;
> - if (strstr(VERSION, "devel")) {
> - if (patch == 0) {
> - patch = 99;
> - if (minor == 0) {
> - minor = 99;
> - --major;
> - } else
> - --minor;
> - } else
> - --patch;
> - }
> - uint32_t version = VK_MAKE_VERSION(major, minor, patch);
> - return version;
> -}
> -
>  void radv_GetPhysicalDeviceProperties(
>   VkPhysicalDevicephysicalDevice,
>   VkPhysicalDeviceProperties* pProperties)
> @@ -731,7 +709,7 @@ void radv_GetPhysicalDeviceProperties(
>  
>   *pProperties = (VkPhysicalDeviceProperties) {
>   .apiVersion = VK_MAKE_VERSION(1, 0, 42),
> - .driverVersion = radv_get_driver_version(),
> + .driverVersion = vk_get_driver_version(),
>   .vendorID = 0x1002,
>   .deviceID = pdevice->rad_info.pci_id,
>   .deviceType = pdevice->rad_info.has_dedicated_vram ? 
> VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
> diff --git a/src/vulkan/Makefile.sources b/src/vulkan/Makefile.sources
> index 9962c1b..2cf7218 100644
> --- a/src/vulkan/Makefile.sources
> +++ b/src/vulkan/Makefile.sources
> @@ -17,6 +17,7 @@ VULKAN_WSI_X11_FILES := \
>  
>  VULKAN_UTIL_FILES := \
>   util/vk_alloc.h \
> + util/vk_util.c \
>   util/vk_util.h
>  
>  VULKAN_UTIL_GENERATED_FILES := \
> diff --git a/src/vulkan/util/vk_util.c b/src/vulkan/util/vk_util.c
> new file mode 100644
> index 000..5e5235a
> --- /dev/null
> +++ b/src/vulkan/util/vk_util.c
> @@ -0,0 +1,50 @@
> +/*
> + * Copyright © 2016 Red Hat.
> + * Copyright © 2016 Bas Nieuwenhuizen
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include 
> +#include 
> +#include "vk_util.h"
> +
> +uint32_t vk_get_driver_version(void)
> +{
> +   const char *minor_string = strchr(VERSION, '.');
> +   const char *patch_string = minor_string ? strchr(minor_string + 1, '.') : 
> NULL;
> +   int major = atoi(VERSION);
> +   int minor = minor_string ? atoi(minor_string + 1) : 0;
> +   int patch = patch_string ? atoi(patch_string + 1) : 0;
> +   if (strstr(VERSION, "devel")) {
> +  if (patch == 0) {
> + patch = 99;
> + if (minor == 0) {
> +minor = 99;
> +--major;
> + } else
> +--minor;
> +  } else
> + --patch;
> +   }
> +   uint32_t version = VK_MAKE_VERSION(ma

[Mesa-dev] [PATCH] mesa: wrap blit_framebuffer() into blit_framebuffer_err()

[Samuel Pitoiset]

Also add ALWAYS_INLINE to blit_framebuffer().

Signed-off-by: Samuel Pitoiset 
---

NOTE: Patch introduced between 9 and 10 in this series. Nothing changed
except some rebase conflicts.

 src/mesa/main/blit.c | 35 ++-
 1 file changed, 26 insertions(+), 9 deletions(-)

diff --git a/src/mesa/main/blit.c b/src/mesa/main/blit.c
index 970c357335..0af5539951 100644
--- a/src/mesa/main/blit.c
+++ b/src/mesa/main/blit.c
@@ -177,7 +177,7 @@ is_valid_blit_filter(const struct gl_context *ctx, GLenum 
filter)
 }
 
 
-static void
+static ALWAYS_INLINE void
 blit_framebuffer(struct gl_context *ctx,
  struct gl_framebuffer *readFb, struct gl_framebuffer *drawFb,
  GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
@@ -537,6 +537,23 @@ blit_framebuffer(struct gl_context *ctx,
 }
 
 
+static void
+blit_framebuffer_err(struct gl_context *ctx,
+ struct gl_framebuffer *readFb, struct gl_framebuffer 
*drawFb,
+ GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
+ GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
+ GLbitfield mask, GLenum filter, const char *func)
+{
+   /* We are wrapping the err variant of the always inlined
+* blit_framebuffer() to avoid inlining it in every caller.
+*/
+   blit_framebuffer(ctx, ctx->ReadBuffer, ctx->DrawBuffer,
+srcX0, srcY0, srcX1, srcY1,
+dstX0, dstY0, dstX1, dstY1,
+mask, filter, false, "glBlitFramebuffer");
+}
+
+
 /**
  * Blit rectangular region, optionally from one framebuffer to another.
  *
@@ -558,10 +575,10 @@ _mesa_BlitFramebuffer(GLint srcX0, GLint srcY0, GLint 
srcX1, GLint srcY1,
   dstX0, dstY0, dstX1, dstY1,
   mask, _mesa_enum_to_string(filter));
 
-   blit_framebuffer(ctx, ctx->ReadBuffer, ctx->DrawBuffer,
-srcX0, srcY0, srcX1, srcY1,
-dstX0, dstY0, dstX1, dstY1,
-mask, filter, false, "glBlitFramebuffer");
+   blit_framebuffer_err(ctx, ctx->ReadBuffer, ctx->DrawBuffer,
+srcX0, srcY0, srcX1, srcY1,
+dstX0, dstY0, dstX1, dstY1,
+mask, filter, "glBlitFramebuffer");
 }
 
 
@@ -609,8 +626,8 @@ _mesa_BlitNamedFramebuffer(GLuint readFramebuffer, GLuint 
drawFramebuffer,
else
   drawFb = ctx->WinSysDrawBuffer;
 
-   blit_framebuffer(ctx, readFb, drawFb,
-srcX0, srcY0, srcX1, srcY1,
-dstX0, dstY0, dstX1, dstY1,
-mask, filter, false, "glBlitNamedFramebuffer");
+   blit_framebuffer_err(ctx, readFb, drawFb,
+srcX0, srcY0, srcX1, srcY1,
+dstX0, dstY0, dstX1, dstY1,
+mask, filter, "glBlitNamedFramebuffer");
 }
-- 
2.13.0

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Re: [Mesa-dev] [PATCH 2/2] RFC: radeon/compute: Limit allocations for VRAM-based chips to 3/4 VRAM

[Aaron Watry]

On Mon, Jun 5, 2017, 3:08 PM Marek Olšák  wrote:

> Hi Aaron,
>
> Can you make the change in radeon_drm_winsys.c instead?
>

I'll give it a shot.

--Aaron


> Thanks,
> Marek
>
> On Mon, Jun 5, 2017 at 2:32 AM, Aaron Watry  wrote:
> > The CL CTS queries the max allocation size, and then attempts to
> > allocate buffers of that size. If any of the VRAM is in use, this
> > causes errors in the radeon kernel module.
> >
> > It's a bit of a hack, but experimentally on my system, I can use 3/4
> > of the card's VRAM for a single global/constant buffer allocation given
> > current GUI/compositor use.
> >
> > If there's a way to get the actual amount of free VRAM, I'd love to hear
> about it.
> >
> > Also, I'm unsure if the radeon kernel module requires all allocated
> memory to be
> > contiguous, if so, then we'd need to be able to get at that value.. I'm
> suspecting
> > that's not actually the case.
> >
> > For a 1GB Pitcairn (HD7850) this gets me from the reported clinfo values
> of:
> > Global memory size  2143076352 (1.996GiB)
> > Max memory allocation   1500153446 (1.397GiB)
> > Max constant buffer size1500153446 (1.397GiB)
> >
> > To:
> > Global memory size  2143076352 (1.996GiB)
> > Max memory allocation   805306368 (768MiB)
> > Max constant buffer size805306368 (768MiB)
> >
> > Fixes: OpenCL CTS test/conformance/api/min_max_mem_alloc_size,
> >OpenCL CTS test/conformance/api/min_max_constant_buffer_size
> >
> > Signed-off-by: Aaron Watry 
> > ---
> >  src/gallium/drivers/radeon/r600_pipe_common.c | 17 +++--
> >  1 file changed, 15 insertions(+), 2 deletions(-)
> >
> > diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
> b/src/gallium/drivers/radeon/r600_pipe_common.c
> > index 2c0cadb030..cdd4062fd3 100644
> > --- a/src/gallium/drivers/radeon/r600_pipe_common.c
> > +++ b/src/gallium/drivers/radeon/r600_pipe_common.c
> > @@ -1144,8 +1144,21 @@ static int r600_get_compute_param(struct
> pipe_screen *screen,
> > if (ret) {
> > uint64_t *max_mem_alloc_size = ret;
> >
> > -   *max_mem_alloc_size =
> rscreen->info.max_alloc_size;
> > -   }
> > +   uint64_t max_alloc =
> rscreen->info.max_alloc_size;
> > +
> > +   if (rscreen->info.has_dedicated_vram) {
> > +   /* XXX: Hack to prevent system hangs...
> > +* Limit to 3/4 VRAM for any single
> allocation.
> > +* Prevents:
> > +* radeon: Not enough memory for
> command submission.
> > +*/
> > +   *max_mem_alloc_size = MIN2(
> > +   rscreen->info.vram_size * 3 / 4,
> max_alloc
> > +   );
> > +   } else {
> > +   *max_mem_alloc_size = max_alloc;
> > +   }
> > +}
> > return sizeof(uint64_t);
> >
> > case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
> > --
> > 2.11.0
> >
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
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[Mesa-dev] [Bug 101291] FAIL: glsl/tests/optimization-test

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101291

Vedran Miletić  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #3 from Vedran Miletić  ---
Indeed, fixed in 17.1. Thanks.

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Re: [Mesa-dev] [PATCH v2 1/2] intel: gen-decoder: rework how we handle groups

[Lionel Landwerlin]

On 05/06/17 23:54, Rafael Antognolli wrote:


realloc() does not initialize the newly added memory, unlike calloc(). So you
can't depend on those new pointers to be zero. It doesn't look like you depend
on that because you have the nfields variable anyways. But if you really don't
care about initializing it, you could simply do a realloc (there's no need for
the calloc part), since if ctx->group->fields is NULL it will act as a simple
malloc anyway.

With this fixed, this patch is:

Reviewed-by: Rafael Antognolli 


Thanks a bunch!


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Re: [Mesa-dev] [PATCH] mesa: wrap blit_framebuffer() into blit_framebuffer_err()

[Eric Engestrom]

On Tuesday, 2017-06-06 14:40:28 +0200, Samuel Pitoiset wrote:
> Also add ALWAYS_INLINE to blit_framebuffer().
> 
> Signed-off-by: Samuel Pitoiset 
> ---
> 
> NOTE: Patch introduced between 9 and 10 in this series. Nothing changed
> except some rebase conflicts.
> 
>  src/mesa/main/blit.c | 35 ++-
>  1 file changed, 26 insertions(+), 9 deletions(-)
> 
> diff --git a/src/mesa/main/blit.c b/src/mesa/main/blit.c
> index 970c357335..0af5539951 100644
> --- a/src/mesa/main/blit.c
> +++ b/src/mesa/main/blit.c
> @@ -177,7 +177,7 @@ is_valid_blit_filter(const struct gl_context *ctx, GLenum 
> filter)
>  }
>  
>  
> -static void
> +static ALWAYS_INLINE void
>  blit_framebuffer(struct gl_context *ctx,
>   struct gl_framebuffer *readFb, struct gl_framebuffer 
> *drawFb,
>   GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
> @@ -537,6 +537,23 @@ blit_framebuffer(struct gl_context *ctx,
>  }
>  
>  
> +static void
> +blit_framebuffer_err(struct gl_context *ctx,
> + struct gl_framebuffer *readFb, struct gl_framebuffer 
> *drawFb,
> + GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
> + GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
> + GLbitfield mask, GLenum filter, const char *func)
> +{
> +   /* We are wrapping the err variant of the always inlined
> +* blit_framebuffer() to avoid inlining it in every caller.
> +*/
> +   blit_framebuffer(ctx, ctx->ReadBuffer, ctx->DrawBuffer,
> +srcX0, srcY0, srcX1, srcY1,
> +dstX0, dstY0, dstX1, dstY1,
> +mask, filter, false, "glBlitFramebuffer");

Incorrect params: blit_framebuffer(..., readFb, drawFb, ..., func);

> +}
> +
> +
>  /**
>   * Blit rectangular region, optionally from one framebuffer to another.
>   *
> @@ -558,10 +575,10 @@ _mesa_BlitFramebuffer(GLint srcX0, GLint srcY0, GLint 
> srcX1, GLint srcY1,
>dstX0, dstY0, dstX1, dstY1,
>mask, _mesa_enum_to_string(filter));
>  
> -   blit_framebuffer(ctx, ctx->ReadBuffer, ctx->DrawBuffer,
> -srcX0, srcY0, srcX1, srcY1,
> -dstX0, dstY0, dstX1, dstY1,
> -mask, filter, false, "glBlitFramebuffer");
> +   blit_framebuffer_err(ctx, ctx->ReadBuffer, ctx->DrawBuffer,
> +srcX0, srcY0, srcX1, srcY1,
> +dstX0, dstY0, dstX1, dstY1,
> +mask, filter, "glBlitFramebuffer");
>  }
>  
>  
> @@ -609,8 +626,8 @@ _mesa_BlitNamedFramebuffer(GLuint readFramebuffer, GLuint 
> drawFramebuffer,
> else
>drawFb = ctx->WinSysDrawBuffer;
>  
> -   blit_framebuffer(ctx, readFb, drawFb,
> -srcX0, srcY0, srcX1, srcY1,
> -dstX0, dstY0, dstX1, dstY1,
> -mask, filter, false, "glBlitNamedFramebuffer");
> +   blit_framebuffer_err(ctx, readFb, drawFb,
> +srcX0, srcY0, srcX1, srcY1,
> +dstX0, dstY0, dstX1, dstY1,
> +mask, filter, "glBlitNamedFramebuffer");
>  }
> -- 
> 2.13.0
> 
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Re: [Mesa-dev] [PATCH 2/4] configure/r600: Only require libdrm_amdgpu if CL is enabled

[Emil Velikov]

On 5 June 2017 at 21:31, Aaron Watry  wrote:
> Otherwise r600g will fail to build when the amdgpu drm library is missing
>
And the code that pulls amdgpu is not used by r600g, which makes this
misplaced duck tape.
As you/Jan don't have the time to properly address this, I'll try to
find some later today.

-Emil
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Re: [Mesa-dev] [PATCH v3] egl/android: support for EGL_KHR_partial_update

[Eric Engestrom]

On Monday, 2017-06-05 17:04:28 +0100, Emil Velikov wrote:
> > + * If the width of the passed rect is greater than the surface's
> > + * width then it is clamped to the width of the surface. Same with
> > + * height.
> > + */
> > +
> > +static void
> > +_eglSetDamageRegionKHRClampRects(_EGLDisplay* disp, _EGLSurface* surf,
> > + EGLint *rects, EGLint n_rects)
> > +{
> > +   EGLint i;
> > +   EGLint surfHeight = surf->Height;
> > +   EGLint surfWidth = surf->Width;
> > +
> > +   for (i = 0; i < (4 * n_rects); i += 4) {
> Do we really need the "4 *" here?

We need it somewhere, and I prefer it in the for(i < 4 * n) rather than
in each rects[4*i + foo] :)
Agreed with everything else you said though.
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[Mesa-dev] [PATCH v3] i965: Support dmabuf import with modifiers

[Varad Gautam]

Add support for createImageFromDmaBufs2, adding a modifier to the
original, and allow importing CCS resources with auxiliary data from
dmabufs.

v2: avoid DRIimageExtension version bump, pass single modifier to
createImageFromDmaBufs2.
v3: rebase to 'i965: Improve same-buffer restriction for imports' v2

Signed-off-by: Varad Gautam 
Signed-off-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c |   6 ++
 src/mesa/drivers/dri/i965/intel_screen.c  | 114 +++---
 2 files changed, 107 insertions(+), 13 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 962d220..0693b94 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -848,6 +848,12 @@ intel_miptree_create_for_image(struct brw_context *intel,
assert(mt->logical_depth0 == 1);
 
create_ccs_buf_for_image(intel, image, mt);
+   if (image->dma_buf_imported)
+  /* We have an imported image with aux data. Mark it unresolved.
+   */
+  intel_miptree_set_fast_clear_state(intel, mt, mt->first_level,
+ 0, mt->logical_depth0,
+ INTEL_FAST_CLEAR_STATE_UNRESOLVED);
 
return mt;
 }
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 0469960..30ec9d2 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -920,16 +920,19 @@ intel_create_image_from_names(__DRIscreen *dri_screen,
 }
 
 static __DRIimage *
-intel_create_image_from_fds(__DRIscreen *dri_screen,
-int width, int height, int fourcc,
-int *fds, int num_fds, int *strides, int *offsets,
-void *loaderPrivate)
+intel_create_image_from_fds_common(__DRIscreen *dri_screen,
+   int width, int height, int fourcc,
+   uint64_t modifier, int *fds,
+   int num_fds, int *strides,
+   int *offsets, void *loaderPrivate)
 {
struct intel_screen *screen = dri_screen->driverPrivate;
struct intel_image_format *f;
__DRIimage *image;
struct brw_bo *bo;
-   uint32_t tiling = I915_TILING_X; /* default to X-tiling */
+   uint32_t tiling;
+   unsigned tiled_height;
+   unsigned ccs_height;
int i, index, size = 0;
 
if (fds == NULL || num_fds < 1)
@@ -939,10 +942,26 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
if (f == NULL)
   return NULL;
 
+   switch (modifier) {
+   case fourcc_mod_code(INTEL, 4):
+  tiling = modifier_to_tiling(modifier);
+  ccs_height = get_aux_height(modifier, height);
+   case DRM_FORMAT_MOD_INVALID:
+  /* X-tiling is the default, and also allows us to infer the tiling
+   * mode from the BO */
+  tiling = I915_TILING_X;
+  ccs_height = 0;
+   default:
+  return NULL;
+   }
+   tiled_height = get_tiled_height(tiling, height);
+
for (i = 0; i < f->nplanes; i++) {
   index = f->planes[i].buffer_index;
-  const int plane_height = height >> f->planes[i].height_shift;
-  const int end = offsets[index] + plane_height * strides[index];
+  const int plane_height = tiled_height >> f->planes[i].height_shift;
+  const int end = offsets[index] +
+  (plane_height + ccs_height) * strides[index];
+
   if (size < end)
  size = end;
}
@@ -988,10 +1007,18 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
}
 
image->bo = bo;
-   image->modifier = tiling_to_modifier(image->bo->tiling_mode);
+
+   /* If we've explicitly specified a modifier, then we use that; else
+* we infer the modifier from the BO's tiling mode. */
+   if (modifier != DRM_FORMAT_MOD_INVALID)
+  image->modifier = modifier;
+   else
+  image->modifier = tiling_to_modifier(image->bo->tiling_mode);
 
if (f->nplanes == 1) {
   image->offset = image->offsets[0];
+  if (ccs_height)
+ image->aux_offset = tiled_height * image->pitch;
   intel_image_warn_if_unaligned(image, __func__);
}
 
@@ -999,9 +1026,21 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
 }
 
 static __DRIimage *
-intel_create_image_from_dma_bufs(__DRIscreen *dri_screen,
+intel_create_image_from_fds(__DRIscreen *dri_screen,
+int width, int height, int fourcc,
+int *fds, int num_fds, int *strides, int *offsets,
+void *loaderPrivate)
+{
+   return intel_create_image_from_fds_common(dri_screen, width, height,
+ fourcc, DRM_FORMAT_MOD_INVALID,
+ fds, num_fds, strides, offsets,
+ loaderPrivate);
+}
+
+static __DRIimage *
+intel_c

Re: [Mesa-dev] [PATCH v3] egl/android: support for EGL_KHR_partial_update

[Emil Velikov]

On 6 June 2017 at 14:54, Eric Engestrom  wrote:
> On Monday, 2017-06-05 17:04:28 +0100, Emil Velikov wrote:
>> > + * If the width of the passed rect is greater than the surface's
>> > + * width then it is clamped to the width of the surface. Same with
>> > + * height.
>> > + */
>> > +
>> > +static void
>> > +_eglSetDamageRegionKHRClampRects(_EGLDisplay* disp, _EGLSurface* surf,
>> > + EGLint *rects, EGLint n_rects)
>> > +{
>> > +   EGLint i;
>> > +   EGLint surfHeight = surf->Height;
>> > +   EGLint surfWidth = surf->Width;
>> > +
>> > +   for (i = 0; i < (4 * n_rects); i += 4) {
>> Do we really need the "4 *" here?
>
> We need it somewhere, and I prefer it in the for(i < 4 * n) rather than
> in each rects[4*i + foo] :)
> Agreed with everything else you said though.

FTR Harish poked me about this and seemingly I've misread the spec -
rects length's is not n_rects :-\
Hence my suggestion here and the similar one in
droid_set_damage_region() is misleading.

-Emil
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[Mesa-dev] [PATCH v2] i965: Add tiling mode to BO import

[Varad Gautam]

From: Daniel Stone 

When importing a dmabuf, verify that the tiling mode matches what was
expected.

v2: rebase to 'i965: Improve same-buffer restriction for imports' v2.

Signed-off-by: Daniel Stone 
Signed-off-by: Varad Gautam 
---
 src/mesa/drivers/dri/i965/brw_bufmgr.c   | 12 ++--
 src/mesa/drivers/dri/i965/brw_bufmgr.h   |  3 ++-
 src/mesa/drivers/dri/i965/intel_screen.c |  5 +++--
 3 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 2f17934..56cf979 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -1014,7 +1014,7 @@ brw_bo_get_tiling(struct brw_bo *bo, uint32_t 
*tiling_mode,
 
 struct brw_bo *
 brw_bo_gem_create_from_prime(struct brw_bufmgr *bufmgr, int prime_fd,
- int size)
+ int size, uint32_t tiling)
 {
int ret;
uint32_t handle;
@@ -1071,8 +1071,16 @@ brw_bo_gem_create_from_prime(struct brw_bufmgr *bufmgr, 
int prime_fd,
if (drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling))
   goto err;
 
-   bo->tiling_mode = get_tiling.tiling_mode;
bo->swizzle_mode = get_tiling.swizzle_mode;
+   bo->tiling_mode = get_tiling.tiling_mode;
+
+   /* If the import explicitly specifies a tiling mode, verify that it matches;
+* TILING_X is taken as the default where a mismatch is not fatal, and means
+* to infer the real tiling mode. */
+   if (tiling != I915_TILING_X &&
+   (bo->tiling_mode != tiling && bo->tiling_mode != I915_TILING_NONE))
+  goto err;
+
/* XXX stride is unknown */
 
 out:
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 56ec206..0a85d9d 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -272,7 +272,8 @@ void brw_destroy_hw_context(struct brw_bufmgr *bufmgr, 
uint32_t ctx_id);
 
 int brw_bo_gem_export_to_prime(struct brw_bo *bo, int *prime_fd);
 struct brw_bo *brw_bo_gem_create_from_prime(struct brw_bufmgr *bufmgr,
-int prime_fd, int size);
+int prime_fd, int size,
+uint32_t tiling);
 
 int brw_reg_read(struct brw_bufmgr *bufmgr, uint32_t offset,
  uint64_t *result);
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index eaa7915..0469960 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -929,6 +929,7 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
struct intel_image_format *f;
__DRIimage *image;
struct brw_bo *bo;
+   uint32_t tiling = I915_TILING_X; /* default to X-tiling */
int i, index, size = 0;
 
if (fds == NULL || num_fds < 1)
@@ -946,7 +947,7 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
  size = end;
}
 
-   bo = brw_bo_gem_create_from_prime(screen->bufmgr, fds[0], size);
+   bo = brw_bo_gem_create_from_prime(screen->bufmgr, fds[0], size, tiling);
if (bo == NULL)
   return NULL;
 
@@ -955,7 +956,7 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
 * fds received here */
for (i = 1; i < num_fds; i++) {
   struct brw_bo *aux =
- brw_bo_gem_create_from_prime(screen->bufmgr, fds[i], size);
+ brw_bo_gem_create_from_prime(screen->bufmgr, fds[i], size, tiling);
   brw_bo_unreference(aux);
   if (aux != bo) {
  brw_bo_unreference(bo);
-- 
2.10.0

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[Mesa-dev] [PATCH v2] i965: Improve same-buffer restriction for imports

[Varad Gautam]

From: Daniel Stone 

Intel hardware requires that all planes of an image come from the same
buffer, which is currently implemented by testing that all FDs are
numerically the same.

However, when going through a winsys (e.g.) or anything which transits
FDs individually, the FDs may be different even if the underlying buffer
is the same.

Instead of checking the FDs for equality, we must check if they actually
point to the same buffer (Jason).

v2: stop leaking bo references (Daniel Stone). buildfix.

Signed-off-by: Daniel Stone 
Signed-off-by: Varad Gautam 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 50 
 1 file changed, 31 insertions(+), 19 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 9842de6..f6bba8b 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -815,20 +815,41 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
struct intel_screen *screen = dri_screen->driverPrivate;
struct intel_image_format *f;
__DRIimage *image;
-   int i, index;
+   struct brw_bo *bo;
+   int i, index, size = 0;
 
if (fds == NULL || num_fds < 1)
   return NULL;
 
-   /* We only support all planes from the same bo */
-   for (i = 0; i < num_fds; i++)
-  if (fds[0] != fds[i])
- return NULL;
-
f = intel_image_format_lookup(fourcc);
if (f == NULL)
   return NULL;
 
+   for (i = 0; i < f->nplanes; i++) {
+  index = f->planes[i].buffer_index;
+  const int plane_height = height >> f->planes[i].height_shift;
+  const int end = offsets[index] + plane_height * strides[index];
+  if (size < end)
+ size = end;
+   }
+
+   bo = brw_bo_gem_create_from_prime(screen->bufmgr, fds[0], size);
+   if (bo == NULL)
+  return NULL;
+
+   /* We only support all planes from the same bo.
+* brw_bo_gem_create_from_prime() should return the same pointer for all
+* fds received here */
+   for (i = 1; i < num_fds; i++) {
+  struct brw_bo *aux =
+ brw_bo_gem_create_from_prime(screen->bufmgr, fds[i], size);
+  brw_bo_unreference(aux);
+  if (aux != bo) {
+ brw_bo_unreference(bo);
+ return NULL;
+  }
+   }
+
if (f->nplanes == 1)
   image = intel_allocate_image(screen, f->planes[0].dri_format,
loaderPrivate);
@@ -836,32 +857,23 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
   image = intel_allocate_image(screen, __DRI_IMAGE_FORMAT_NONE,
loaderPrivate);
 
-   if (image == NULL)
+   if (image == NULL) {
+  brw_bo_unreference(bo);
   return NULL;
+   }
 
image->width = width;
image->height = height;
image->pitch = strides[0];
 
image->planar_format = f;
-   int size = 0;
for (i = 0; i < f->nplanes; i++) {
   index = f->planes[i].buffer_index;
   image->offsets[index] = offsets[index];
   image->strides[index] = strides[index];
-
-  const int plane_height = height >> f->planes[i].height_shift;
-  const int end = offsets[index] + plane_height * strides[index];
-  if (size < end)
- size = end;
}
 
-   image->bo = brw_bo_gem_create_from_prime(screen->bufmgr,
-  fds[0], size);
-   if (image->bo == NULL) {
-  free(image);
-  return NULL;
-   }
+   image->bo = bo;
image->modifier = tiling_to_modifier(image->bo->tiling_mode);
 
if (f->nplanes == 1) {
-- 
2.10.0

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Re: [Mesa-dev] [PATCH v3] egl/android: support for EGL_KHR_partial_update

[Eric Engestrom]

On Monday, 2017-06-05 19:37:55 +0530, Harish Krupo wrote:
> This patch adds support for the EGL_KHR_partial_update extension for
> android platform. It passes 36/37 tests in dEQP for EGL_KHR_partial_update.
> 1 test not supported.
> 
> v2: add fallback for eglSetDamageRegionKHR (Tapani)
> 
> v3: The native_window_set_surface_damage call is available only from
> Android version 6.0. Reintroduce the ANDROID_VERSION guard and
> advertise extension only if version is >= 6.0. (Emil Velikov)
> 
> Signed-off-by: Harish Krupo 
> ---
>  Android.common.mk   |  3 +-
>  Android.mk  |  2 +
>  src/egl/drivers/dri2/egl_dri2.c | 12 +
>  src/egl/drivers/dri2/egl_dri2.h |  4 ++
>  src/egl/drivers/dri2/platform_android.c | 37 ++
>  src/egl/main/eglapi.c   | 87 
> +
>  src/egl/main/eglapi.h   |  2 +
>  src/egl/main/egldisplay.h   |  1 +
>  src/egl/main/eglentrypoint.h|  1 +
>  src/egl/main/eglfallbacks.c |  1 +
>  src/egl/main/eglsurface.c   |  8 +++
>  src/egl/main/eglsurface.h   | 12 +
>  12 files changed, 169 insertions(+), 1 deletion(-)
> 
[snip]
> diff --git a/src/egl/drivers/dri2/platform_android.c 
> b/src/egl/drivers/dri2/platform_android.c
> index 1ae779e59c..8e9530b7ed 100644
> --- a/src/egl/drivers/dri2/platform_android.c
> +++ b/src/egl/drivers/dri2/platform_android.c
> @@ -651,6 +651,39 @@ droid_swap_buffers(_EGLDriver *drv, _EGLDisplay *disp, 
> _EGLSurface *draw)
> return EGL_TRUE;
>  }
>  
> +static EGLBoolean
> +droid_set_damage_region(_EGLDriver *drv,
> +_EGLDisplay *disp,
> +_EGLSurface *draw, const EGLint* rects, EGLint 
> n_rects)
> +{
> +   struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
> +   struct dri2_egl_surface *dri2_surf = dri2_egl_surface(draw);
> +   android_native_rect_t* droid_rects = NULL;
> +   if (n_rects != 0)
> +  droid_rects = (android_native_rect_t *)
> + calloc(n_rects, sizeof(android_native_rect_t));

if (n_rects == 0)
   return EGL_TRUE;

Nothing else will happen in this function when no rectangle is passed
in, so we might as well return right away, and carry on with the rest of
the code normally.
(Note that `native_window_set_surface_damage(..., NULL, 0)` has the same
effect as not calling it for the frame, ie. full damage.)

> +
> +   EGLint surfWidth = dri2_surf->base.Width;
> +   EGLint surfHeight = dri2_surf->base.Height;
> +   EGLint dIndex;
> +
> +   for (dIndex = 0; dIndex < n_rects; dIndex++) {
> +  EGLint i = dIndex * 4;
> +  droid_rects[dIndex].left = rects[i]; // left == x
> +  droid_rects[dIndex].bottom = rects[i + 1]; // bottom == y
> +  droid_rects[dIndex].right = rects[i] + rects[i + 2]; // left + width
> +  droid_rects[dIndex].top = rects[i + 1] + rects[i + 3]; // bottom + 
> height
> +   }
> +
> +#if ANDROID_VERSION >= 0x600
> +   native_window_set_surface_damage(dri2_surf->window, droid_rects, n_rects);
> +#endif
> +
> +   free(droid_rects);
> +
> +   return EGL_TRUE;
> +}
> +
>  static _EGLImage *
>  droid_create_image_from_prime_fd_yuv(_EGLDisplay *disp, _EGLContext *ctx,
>   struct ANativeWindowBuffer *buf, int fd)
[snip]
> diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
> index 9cea2f41ff..0da07e6e1f 100644
> --- a/src/egl/main/eglapi.c
> +++ b/src/egl/main/eglapi.c
> @@ -1281,6 +1300,74 @@ eglSwapBuffersWithDamageKHR(EGLDisplay dpy, EGLSurface 
> surface,
> return _eglSwapBuffersWithDamageCommon(disp, surf, rects, n_rects);
>  }
>  
> +/*
> + * If the width of the passed rect is greater than the surface's
> + * width then it is clamped to the width of the surface. Same with
> + * height.
> + */
> +
> +static void
> +_eglSetDamageRegionKHRClampRects(_EGLDisplay* disp, _EGLSurface* surf,
> + EGLint *rects, EGLint n_rects)
> +{
> +   EGLint i;
> +   EGLint surfHeight = surf->Height;
> +   EGLint surfWidth = surf->Width;
> +
> +   for (i = 0; i < (4 * n_rects); i += 4) {
> +  EGLint x, y, rectWidth, rectHeight;
> +  x = rects[i];
> +  y = rects[i + 1];
> +  rectWidth = rects[i + 2];
> +  rectHeight = rects[i + 3];
> +
> +  if (rectWidth + x > surfWidth)
> + rects[i + 2] = surfWidth - x;
> +
> +  if (rectHeight + y > surfHeight)
> + rects[i + 3] = surfHeight - y;
> +   }
> +}
> +
> +static EGLBoolean EGLAPIENTRY
> +eglSetDamageRegionKHR(EGLDisplay dpy, EGLSurface surface,
> +  EGLint *rects, EGLint n_rects)
> +{
> +   _EGLDisplay *disp = _eglLockDisplay(dpy);
> +   _EGLSurface *surf = _eglLookupSurface(surface, disp);
> +   _EGL_FUNC_START(disp, EGL_OBJECT_SURFACE_KHR, surf, EGL_FALSE);
> +   _EGLContext *ctx = _eglGetCurrentContext();
> +   _EGLDriver *drv;
> +   EGLBoolean ret;
> +   _EGL_CHECK_SURFACE(disp, surf

[Mesa-dev] [PATCH 1/5] radeonsi: enable TC-compatible stencil compression on VI

[Marek Olšák]

From: Marek Olšák 

Most things are in place. Ideally we won't see decompress blits for stencil
anymore.
---
 src/gallium/drivers/radeonsi/si_blit.c| 2 ++
 src/gallium/drivers/radeonsi/si_descriptors.c | 8 
 src/gallium/drivers/radeonsi/si_state_draw.c  | 3 ++-
 3 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 448533d..59334db 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -337,20 +337,22 @@ si_flush_depth_texture(struct si_context *sctx,
 
if (levels_s) {
if (r600_can_sample_zs(tex, true))
inplace_planes |= PIPE_MASK_S;
else
copy_planes |= PIPE_MASK_S;
}
}
 
assert(!tex->tc_compatible_htile || levels_z == 0);
+   assert(!tex->tc_compatible_htile || levels_s == 0 ||
+  !r600_can_sample_zs(tex, true));
 
/* We may have to allocate the flushed texture here when called from
 * si_decompress_subresource.
 */
if (copy_planes &&
(tex->flushed_depth_texture ||
 r600_init_flushed_depth_texture(&sctx->b.b, &tex->resource.b.b, 
NULL))) {
struct r600_texture *dst = tex->flushed_depth_texture;
unsigned fully_copied_levels;
unsigned levels = 0;
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 61eb2f1..7a2b71d 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -332,22 +332,21 @@ static void si_sampler_view_add_buffer(struct si_context 
*sctx,
 
/* Now add separate DCC or HTILE. */
rtex = (struct r600_texture*)resource;
if (rtex->dcc_separate_buffer) {
radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
rtex->dcc_separate_buffer, 
usage,
RADEON_PRIO_DCC, check_mem);
}
 
if (rtex->htile_buffer &&
-   rtex->tc_compatible_htile &&
-   !is_stencil_sampler) {
+   rtex->tc_compatible_htile) {
radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
rtex->htile_buffer, usage,
RADEON_PRIO_HTILE, 
check_mem);
}
 }
 
 static void si_sampler_views_begin_new_cs(struct si_context *sctx,
  struct si_sampler_views *views)
 {
unsigned mask = views->enabled_mask;
@@ -417,21 +416,21 @@ void si_set_mutable_tex_desc_fields(struct si_screen 
*sscreen,
if (sscreen->b.chip_class >= VI) {
state[6] &= C_008F28_COMPRESSION_EN;
state[7] = 0;
 
if (vi_dcc_enabled(tex, first_level)) {
meta_va = (!tex->dcc_separate_buffer ? 
tex->resource.gpu_address : 0) +
  tex->dcc_offset;
 
if (sscreen->b.chip_class <= VI)
meta_va += base_level_info->dcc_offset;
-   } else if (tex->tc_compatible_htile && !is_stencil) {
+   } else if (tex->tc_compatible_htile) {
meta_va = tex->htile_buffer->gpu_address;
}
 
if (meta_va) {
state[6] |= S_008F28_COMPRESSION_EN(1);
state[7] = meta_va >> 8;
}
}
 
if (sscreen->b.chip_class >= GFX9) {
@@ -564,21 +563,22 @@ static bool is_compressed_colortex(struct r600_texture 
*rtex)
 {
return rtex->fmask.size ||
   (rtex->dirty_level_mask &&
(rtex->cmask.size || rtex->dcc_offset));
 }
 
 static bool depth_needs_decompression(struct r600_texture *rtex,
  struct si_sampler_view *sview)
 {
return rtex->db_compatible &&
-  (!rtex->tc_compatible_htile || sview->is_stencil_sampler);
+  (!rtex->tc_compatible_htile ||
+   !r600_can_sample_zs(rtex, sview->is_stencil_sampler));
 }
 
 static void si_update_compressed_tex_shader_mask(struct si_context *sctx,
 unsigned shader)
 {
struct si_textures_info *samplers = &sctx->samplers[shader];
unsigned shader_bit = 1 << shader;
 
if (samplers->depth_texture_mask ||
samplers->compressed_colortex_mask ||
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c 
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 77df643..cd069e3 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1391,21 +1391,

[Mesa-dev] [PATCH 3/5] radeonsi: disable the patch ID workaround on SI when the patch ID isn't used

[Marek Olšák]

From: Marek Olšák 

The workaround causes a massive performance decrease on 1-SE parts.
(Cape Verde, Hainan, Oland)

The performance regression is already part of 17.0 and 17.1.

Cc: 17.0 17.1 
---
 src/gallium/drivers/radeonsi/si_state_draw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c 
b/src/gallium/drivers/radeonsi/si_state_draw.c
index cd069e3..75e83ff 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -188,21 +188,21 @@ static void si_emit_derived_tess_state(struct si_context 
*sctx,
 */
*num_patches = MIN2(*num_patches, 40);
 
if (sctx->b.chip_class == SI) {
/* SI bug workaround, related to power management. Limit LS-HS
 * threadgroups to only one wave.
 */
unsigned one_wave = 64 / MAX2(num_tcs_input_cp, 
num_tcs_output_cp);
*num_patches = MIN2(*num_patches, one_wave);
 
-   if (sctx->screen->b.info.max_se == 1) {
+   if (sctx->screen->b.info.max_se == 1 && tcs->info.uses_primid) {
/* The VGT HS block increments the patch ID 
unconditionally
 * within a single threadgroup. This results in 
incorrect
 * patch IDs when instanced draws are used.
 *
 * The intended solution is to restrict threadgroups to
 * a single instance by setting SWITCH_ON_EOI, which
 * should cause IA to split instances up. However, this
 * doesn't work correctly on SI when there is no other
 * SE to switch to.
 */
-- 
2.7.4

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[Mesa-dev] [PATCH 4/5] gallium/radeon: clean up a misleading statement from the old days

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/r600_texture.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index f0c1bec..663d6fc 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -233,24 +233,21 @@ static int r600_init_surface(struct r600_common_screen 
*rscreen,
unsigned i, bpe, flags = 0;
 
is_depth = util_format_has_depth(desc);
is_stencil = util_format_has_stencil(desc);
 
if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
bpe = 4; /* stencil is allocated separately on evergreen */
} else {
bpe = util_format_get_blocksize(ptex->format);
-   /* align byte per element on dword */
-   if (bpe == 3) {
-   bpe = 4;
-   }
+   assert(util_is_power_of_two(bpe));
}
 
if (!is_flushed_depth && is_depth) {
flags |= RADEON_SURF_ZBUFFER;
 
if (tc_compatible_htile &&
(rscreen->chip_class >= GFX9 ||
 array_mode == RADEON_SURF_MODE_2D)) {
/* TC-compatible HTILE only supports Z32_FLOAT.
 * GFX9 also supports Z16_UNORM.
-- 
2.7.4

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[Mesa-dev] [PATCH 5/5] radeonsi: clean up decompress blend state names

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_blit.c  | 4 ++--
 src/gallium/drivers/radeonsi/si_pipe.c  | 8 
 src/gallium/drivers/radeonsi/si_pipe.h  | 4 ++--
 src/gallium/drivers/radeonsi/si_state.c | 4 ++--
 4 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 59334db..46cb646 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -438,23 +438,23 @@ static void si_blit_decompress_color(struct pipe_context 
*ctx,
 
if (rtex->dcc_offset && need_dcc_decompress) {
custom_blend = sctx->custom_blend_dcc_decompress;
 
/* disable levels without DCC */
for (int i = first_level; i <= last_level; i++) {
if (!vi_dcc_enabled(rtex, i))
level_mask &= ~(1 << i);
}
} else if (rtex->fmask.size) {
-   custom_blend = sctx->custom_blend_decompress;
+   custom_blend = sctx->custom_blend_fmask_decompress;
} else {
-   custom_blend = sctx->custom_blend_fastclear;
+   custom_blend = sctx->custom_blend_eliminate_fastclear;
}
 
bool old_update_dirtiness = sctx->framebuffer.do_update_surf_dirtiness;
sctx->decompression_enabled = true;
sctx->framebuffer.do_update_surf_dirtiness = false;
 
while (level_mask) {
unsigned level = u_bit_scan(&level_mask);
 
/* The smaller the mipmap level, the less layers there are
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 805392d..cb37226 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -69,24 +69,24 @@ static void si_destroy_context(struct pipe_context *context)
si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
si_pm4_delete_state(sctx, vgt_shader_config, 
sctx->vgt_shader_config[i]);
 
if (sctx->fixed_func_tcs_shader.cso)
sctx->b.b.delete_tcs_state(&sctx->b.b, 
sctx->fixed_func_tcs_shader.cso);
if (sctx->custom_dsa_flush)
sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, 
sctx->custom_dsa_flush);
if (sctx->custom_blend_resolve)
sctx->b.b.delete_blend_state(&sctx->b.b, 
sctx->custom_blend_resolve);
-   if (sctx->custom_blend_decompress)
-   sctx->b.b.delete_blend_state(&sctx->b.b, 
sctx->custom_blend_decompress);
-   if (sctx->custom_blend_fastclear)
-   sctx->b.b.delete_blend_state(&sctx->b.b, 
sctx->custom_blend_fastclear);
+   if (sctx->custom_blend_fmask_decompress)
+   sctx->b.b.delete_blend_state(&sctx->b.b, 
sctx->custom_blend_fmask_decompress);
+   if (sctx->custom_blend_eliminate_fastclear)
+   sctx->b.b.delete_blend_state(&sctx->b.b, 
sctx->custom_blend_eliminate_fastclear);
if (sctx->custom_blend_dcc_decompress)
sctx->b.b.delete_blend_state(&sctx->b.b, 
sctx->custom_blend_dcc_decompress);
 
if (sctx->blitter)
util_blitter_destroy(sctx->blitter);
 
r600_common_context_cleanup(&sctx->b);
 
LLVMDisposeTargetMachine(sctx->tm);
 
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h 
b/src/gallium/drivers/radeonsi/si_pipe.h
index db747d6..108929c 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -226,22 +226,22 @@ union si_vgt_param_key {
unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
} u;
uint32_t index;
 };
 
 struct si_context {
struct r600_common_context  b;
struct blitter_context  *blitter;
void*custom_dsa_flush;
void*custom_blend_resolve;
-   void*custom_blend_decompress;
-   void*custom_blend_fastclear;
+   void*custom_blend_fmask_decompress;
+   void*custom_blend_eliminate_fastclear;
void*custom_blend_dcc_decompress;
struct si_screen*screen;
 
struct radeon_winsys_cs *ce_ib;
struct radeon_winsys_cs *ce_preamble_ib;
struct r600_resource*ce_ram_saved_buffer;
unsignedce_ram_saved_offset;
unsignedtotal_ce_ram_allocated;
boolce_need_synchronization;
struct u_suballocator   *ce_suballocator;
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 323ec5e..28dcec0 100644
--- a/src/gallium/drivers

[Mesa-dev] [PATCH 2/5] radeonsi: don't use 1D tiling for Z/S on VI to get TC-compatible HTILE

[Marek Olšák]

From: Marek Olšák 

It's always good to have fewer decompress blits.
---
 src/gallium/drivers/radeon/r600_texture.c | 16 +---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 48ae788..f0c1bec 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1274,42 +1274,52 @@ r600_texture_create_object(struct pipe_screen *screen,
 
return rtex;
 }
 
 static enum radeon_surf_mode
 r600_choose_tiling(struct r600_common_screen *rscreen,
   const struct pipe_resource *templ)
 {
const struct util_format_description *desc = 
util_format_description(templ->format);
bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
+   bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format) 
&&
+   !(templ->flags & 
R600_RESOURCE_FLAG_FLUSHED_DEPTH);
 
/* MSAA resources must be 2D tiled. */
if (templ->nr_samples > 1)
return RADEON_SURF_MODE_2D;
 
/* Transfer resources should be linear. */
if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
return RADEON_SURF_MODE_LINEAR_ALIGNED;
 
+   /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
+* which requires 2D tiling.
+*/
+   if (rscreen->chip_class == VI &&
+   is_depth_stencil &&
+   (templ->flags & PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY))
+   return RADEON_SURF_MODE_2D;
+
/* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. 
*/
if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
(templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
(templ->target == PIPE_TEXTURE_2D ||
 templ->target == PIPE_TEXTURE_3D))
force_tiling = true;
 
/* Handle common candidates for the linear mode.
 * Compressed textures and DB surfaces must always be tiled.
 */
-   if (!force_tiling && !util_format_is_compressed(templ->format) &&
-   (!util_format_is_depth_or_stencil(templ->format) ||
-templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH)) {
+   if (!force_tiling &&
+   !is_depth_stencil &&
+   !util_format_is_compressed(templ->format)) {
if (rscreen->debug_flags & DBG_NO_TILING)
return RADEON_SURF_MODE_LINEAR_ALIGNED;
 
/* Tiling doesn't work with the 422 (SUBSAMPLED) formats on 
R600+. */
if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
return RADEON_SURF_MODE_LINEAR_ALIGNED;
 
/* Cursors are linear on SI.
 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
if (rscreen->chip_class >= SI &&
-- 
2.7.4

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Re: [Mesa-dev] [PATCH v2] util/vulkan: Move Vulkan utilities to src/vulkan/util

[Jason Ekstrand]

Acked-by: Jason Ekstrand 

I haven't looked at the details, but it's a good idea.  Thanks for doing it!

On Tue, Jun 6, 2017 at 4:31 AM, Alex Smith 
wrote:

> We have Vulkan utilities in both src/util and src/vulkan/util. The
> latter seems a more appropriate place for Vulkan-specific things, so
> move them there.
>
> v2: Android build system changes (from Tapani Pälli)
>
> Signed-off-by: Alex Smith 
> ---
>  Android.common.mk   | 1 +
>  src/amd/vulkan/radv_device.c| 2 +-
>  src/amd/vulkan/radv_formats.c   | 3 ++-
>  src/amd/vulkan/radv_private.h   | 2 +-
>  src/amd/vulkan/radv_wsi.c   | 2 +-
>  src/intel/Android.vulkan.mk | 1 +
>  src/intel/vulkan/anv_device.c   | 2 +-
>  src/intel/vulkan/anv_formats.c  | 3 +--
>  src/intel/vulkan/anv_pass.c | 2 +-
>  src/intel/vulkan/anv_private.h  | 2 +-
>  src/intel/vulkan/anv_queue.c| 2 +-
>  src/intel/vulkan/anv_wsi.c  | 2 +-
>  src/intel/vulkan/genX_cmd_buffer.c  | 2 +-
>  src/util/Makefile.sources   | 4 +---
>  src/vulkan/Android.mk   | 2 ++
>  src/vulkan/Makefile.am  | 7 ++-
>  src/vulkan/Makefile.sources | 4 
>  src/{ => vulkan}/util/vk_alloc.h| 0
>  src/{ => vulkan}/util/vk_util.h | 0
>  src/vulkan/wsi/wsi_common.h | 2 +-
>  src/vulkan/wsi/wsi_common_wayland.c | 2 +-
>  src/vulkan/wsi/wsi_common_x11.c | 2 +-
>  22 files changed, 30 insertions(+), 19 deletions(-)
>  rename src/{ => vulkan}/util/vk_alloc.h (100%)
>  rename src/{ => vulkan}/util/vk_util.h (100%)
>
> diff --git a/Android.common.mk b/Android.common.mk
> index 44ad97b..6bd3081 100644
> --- a/Android.common.mk
> +++ b/Android.common.mk
> @@ -37,6 +37,7 @@ LOCAL_CFLAGS += \
> -Wno-missing-field-initializers \
> -Wno-initializer-overrides \
> -Wno-mismatched-tags \
> +   -DVERSION=\"$(MESA_VERSION)\" \
> -DPACKAGE_VERSION=\"$(MESA_VERSION)\" \
> -DPACKAGE_BUGREPORT=\"https://bugs.freedesktop.org/enter_
> bug.cgi?product=Mesa\"
>
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index 887916f..a812527 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -33,7 +33,7 @@
>  #include "radv_cs.h"
>  #include "util/disk_cache.h"
>  #include "util/strtod.h"
> -#include "util/vk_util.h"
> +#include "vk_util.h"
>  #include 
>  #include 
>  #include 
> diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
> index 6cff0a5..b13adb9 100644
> --- a/src/amd/vulkan/radv_formats.c
> +++ b/src/amd/vulkan/radv_formats.c
> @@ -28,7 +28,8 @@
>  #include "sid.h"
>  #include "r600d_common.h"
>
> -#include "util/vk_util.h"
> +#include "vk_util.h"
> +
>  #include "util/u_half.h"
>  #include "util/format_srgb.h"
>  #include "util/format_r11g11b10f.h"
> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
> index ed80ba7..a3920a7 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -47,8 +47,8 @@
>  #include "compiler/shader_enums.h"
>  #include "util/macros.h"
>  #include "util/list.h"
> -#include "util/vk_alloc.h"
>  #include "main/macros.h"
> +#include "vk_alloc.h"
>
>  #include "radv_radeon_winsys.h"
>  #include "ac_binary.h"
> diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
> index 51fe159..cdb04ca 100644
> --- a/src/amd/vulkan/radv_wsi.c
> +++ b/src/amd/vulkan/radv_wsi.c
> @@ -26,7 +26,7 @@
>  #include "radv_private.h"
>  #include "radv_meta.h"
>  #include "wsi_common.h"
> -#include "util/vk_util.h"
> +#include "vk_util.h"
>
>  static const struct wsi_callbacks wsi_cbs = {
> .get_phys_device_format_properties = radv_
> GetPhysicalDeviceFormatProperties,
> diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk
> index 2ede3f7..e31c439 100644
> --- a/src/intel/Android.vulkan.mk
> +++ b/src/intel/Android.vulkan.mk
> @@ -31,6 +31,7 @@ VULKAN_COMMON_INCLUDES := \
> $(MESA_TOP)/src/gallium/include \
> $(MESA_TOP)/src/mesa \
> $(MESA_TOP)/src/vulkan/wsi \
> +   $(MESA_TOP)/src/vulkan/util \
> $(MESA_TOP)/src/intel \
> $(MESA_TOP)/src/intel/vulkan
>
> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
> index aacd07f..6079588 100644
> --- a/src/intel/vulkan/anv_device.c
> +++ b/src/intel/vulkan/anv_device.c
> @@ -35,7 +35,7 @@
>  #include "util/debug.h"
>  #include "util/build_id.h"
>  #include "util/mesa-sha1.h"
> -#include "util/vk_util.h"
> +#include "vk_util.h"
>
>  #include "genxml/gen7_pack.h"
>
> diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_
> formats.c
> index 25801e8..104d4f7 100644
> --- a/src/intel/vulkan/anv_formats.c
> +++ b/src/intel/vulkan/anv_formats.c
> @@ -23,8 +23,7 @@
>
>  #include "anv_private.h"
>  #include "vk_format_info.h"
> -
> -#include "util/vk_util.h"
> +#include "vk_util.h"
>
>  /*
>   * gcc-4 and earlier don't allow compound literals where a constan

Re: [Mesa-dev] [PATCH 2/3] radv/vulkan: Move radv_get_driver_version to src/vulkan/util

[Jason Ekstrand]

On Tue, Jun 6, 2017 at 5:17 AM, Emil Velikov 
wrote:

> Hi Alex,
>
> On 6 June 2017 at 10:42, Alex Smith  wrote:
> > This means it can be reused for other Vulkan drivers. Also fix up a
> > typo, need to search for '.' in the version string rather than ','.
> >
> > Signed-off-by: Alex Smith 
> > ---
>
> > +uint32_t vk_get_driver_version(void)
> > +{
> ...
> > +   uint32_t version = VK_MAKE_VERSION(major, minor, patch);
> > +   return version;
> Nit: return directly?
>
> Either way, the series is (thanks for the Android squash and dropping
> the util/ bit)
>

Agreed.


> Reviewed-by: Emil Velikov 
>
> If anyone wants to pursue the devel vs rc topic, below is an idea how.
> Some devs thought it was confusing a while back, so be warned.
>
> 17.0.0 dev -> 16.90.0
> 18.0.0 dev -> 17.90.0
>
> 17.0.0 rc1 -> 16.91.0
> 18.0.0 rc2 -> 17.92.0
>
> 17.1.0 dev -> 17.0.90
> 18.2.0 dev -> 17.1.90
>
> 17.1.0 rc1 -> 17.0.91
> 18.2.0 rc2 -> 18.1.92
>

That shouldn't be too hard to implement but someone who's feeling pedantic
can do that as part of a later patch.

--Jason
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Re: [Mesa-dev] [PATCH v2 3/3] anv: Set driver version to Mesa version

[Jason Ekstrand]

Both patch 2 and 3 are

Reviewed-by: Jason Ekstrand 

On Tue, Jun 6, 2017 at 2:42 AM, Alex Smith 
wrote:

> As already done by RADV.
>
> v2: Move version calculation function to src/vulkan/util to share with
> RADV.
>
> Signed-off-by: Alex Smith 
> ---
>  src/intel/vulkan/anv_device.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
> index 6079588..72a96b7 100644
> --- a/src/intel/vulkan/anv_device.c
> +++ b/src/intel/vulkan/anv_device.c
> @@ -886,7 +886,7 @@ void anv_GetPhysicalDeviceProperties(
>
> *pProperties = (VkPhysicalDeviceProperties) {
>.apiVersion = VK_MAKE_VERSION(1, 0, 42),
> -  .driverVersion = 1,
> +  .driverVersion = vk_get_driver_version(),
>.vendorID = 0x8086,
>.deviceID = pdevice->chipset_id,
>.deviceType = VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
> --
> 2.9.4
>
> ___
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> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
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Re: [Mesa-dev] [PATCH 2/4] configure/r600: Only require libdrm_amdgpu if CL is enabled

[Aaron Watry]

On Tue, Jun 6, 2017 at 8:51 AM, Emil Velikov  wrote:
>
> On 5 June 2017 at 21:31, Aaron Watry  wrote:
> > Otherwise r600g will fail to build when the amdgpu drm library is missing
> >
> And the code that pulls amdgpu is not used by r600g, which makes this
> misplaced duck tape.
> As you/Jan don't have the time to properly address this, I'll try to
> find some later today.


Thank you.

You're right that I don't have a lot of time.  If I'm lucky, I get 30
minutes in the average evening to poke at any of my own hobbies,
including this. I'd love to be able to spend the whole day ripping the
amdgpu dependency out of the parts of amd/common that r600 uses, but
that's just not possible this week (or next week), hence the bandaid.

Combine that with a lack of understanding of autotools and you can see
how we ended up here.

What Jan and I sent gets the r600 build working again, without losing
functionality, and buys us time to deal with the amdgpu dependency in
the amd/common and gallium/radeon parts, which honestly is all I had
time to do at the moment without taking a day off of work to rip
amd/common apart to fix and test it properly.

--Aaron

>
>
> -Emil
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[Mesa-dev] [PATCH v2] radv/vulkan: Move radv_get_driver_version to src/vulkan/util

[Alex Smith]

This means it can be reused for other Vulkan drivers. Also fix up a
typo, need to search for '.' in the version string rather than ','.

v2: Remove unneeded temporary version variable (Emil, Eric)

Signed-off-by: Alex Smith 
---
 src/amd/vulkan/radv_device.c | 24 +-
 src/vulkan/Makefile.sources  |  1 +
 src/vulkan/util/vk_util.c| 49 
 src/vulkan/util/vk_util.h|  2 ++
 4 files changed, 53 insertions(+), 23 deletions(-)
 create mode 100644 src/vulkan/util/vk_util.c

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index a812527..5fdb894 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -574,28 +574,6 @@ void radv_GetPhysicalDeviceFeatures2KHR(
return radv_GetPhysicalDeviceFeatures(physicalDevice, 
&pFeatures->features);
 }
 
-static uint32_t radv_get_driver_version()
-{
-   const char *minor_string = strchr(VERSION, '.');
-   const char *patch_string = minor_string ? strchr(minor_string + 1, 
','): NULL;
-   int major = atoi(VERSION);
-   int minor = minor_string ? atoi(minor_string + 1) : 0;
-   int patch = patch_string ? atoi(patch_string + 1) : 0;
-   if (strstr(VERSION, "devel")) {
-   if (patch == 0) {
-   patch = 99;
-   if (minor == 0) {
-   minor = 99;
-   --major;
-   } else
-   --minor;
-   } else
-   --patch;
-   }
-   uint32_t version = VK_MAKE_VERSION(major, minor, patch);
-   return version;
-}
-
 void radv_GetPhysicalDeviceProperties(
VkPhysicalDevicephysicalDevice,
VkPhysicalDeviceProperties* pProperties)
@@ -731,7 +709,7 @@ void radv_GetPhysicalDeviceProperties(
 
*pProperties = (VkPhysicalDeviceProperties) {
.apiVersion = VK_MAKE_VERSION(1, 0, 42),
-   .driverVersion = radv_get_driver_version(),
+   .driverVersion = vk_get_driver_version(),
.vendorID = 0x1002,
.deviceID = pdevice->rad_info.pci_id,
.deviceType = pdevice->rad_info.has_dedicated_vram ? 
VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
diff --git a/src/vulkan/Makefile.sources b/src/vulkan/Makefile.sources
index 9962c1b..2cf7218 100644
--- a/src/vulkan/Makefile.sources
+++ b/src/vulkan/Makefile.sources
@@ -17,6 +17,7 @@ VULKAN_WSI_X11_FILES := \
 
 VULKAN_UTIL_FILES := \
util/vk_alloc.h \
+   util/vk_util.c \
util/vk_util.h
 
 VULKAN_UTIL_GENERATED_FILES := \
diff --git a/src/vulkan/util/vk_util.c b/src/vulkan/util/vk_util.c
new file mode 100644
index 000..769e690
--- /dev/null
+++ b/src/vulkan/util/vk_util.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright © 2016 Red Hat.
+ * Copyright © 2016 Bas Nieuwenhuizen
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include "vk_util.h"
+
+uint32_t vk_get_driver_version(void)
+{
+   const char *minor_string = strchr(VERSION, '.');
+   const char *patch_string = minor_string ? strchr(minor_string + 1, '.') : 
NULL;
+   int major = atoi(VERSION);
+   int minor = minor_string ? atoi(minor_string + 1) : 0;
+   int patch = patch_string ? atoi(patch_string + 1) : 0;
+   if (strstr(VERSION, "devel")) {
+  if (patch == 0) {
+ patch = 99;
+ if (minor == 0) {
+minor = 99;
+--major;
+ } else
+--minor;
+  } else
+ --patch;
+   }
+   return VK_MAKE_VERSION(major, minor, patch);
+}
diff --git a/src/vulkan/util/vk_util.h b/src/vulkan/util/vk_util.h
index 5ff1f00..2ed601f 100644
--- a/src/vulkan/util/vk_util.h
+++ b/src/vulkan/util/vk_util.h
@@ -197,4 +197,

Re: [Mesa-dev] [PATCH v2] radv/vulkan: Move radv_get_driver_version to src/vulkan/util

[Jason Ekstrand]

Reviewed-by: Jason Ekstrand 

Alex, do you need someone to push these for you?

On Tue, Jun 6, 2017 at 8:09 AM, Alex Smith 
wrote:

> This means it can be reused for other Vulkan drivers. Also fix up a
> typo, need to search for '.' in the version string rather than ','.
>
> v2: Remove unneeded temporary version variable (Emil, Eric)
>
> Signed-off-by: Alex Smith 
> ---
>  src/amd/vulkan/radv_device.c | 24 +-
>  src/vulkan/Makefile.sources  |  1 +
>  src/vulkan/util/vk_util.c| 49 ++
> ++
>  src/vulkan/util/vk_util.h|  2 ++
>  4 files changed, 53 insertions(+), 23 deletions(-)
>  create mode 100644 src/vulkan/util/vk_util.c
>
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index a812527..5fdb894 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -574,28 +574,6 @@ void radv_GetPhysicalDeviceFeatures2KHR(
> return radv_GetPhysicalDeviceFeatures(physicalDevice,
> &pFeatures->features);
>  }
>
> -static uint32_t radv_get_driver_version()
> -{
> -   const char *minor_string = strchr(VERSION, '.');
> -   const char *patch_string = minor_string ? strchr(minor_string + 1,
> ','): NULL;
> -   int major = atoi(VERSION);
> -   int minor = minor_string ? atoi(minor_string + 1) : 0;
> -   int patch = patch_string ? atoi(patch_string + 1) : 0;
> -   if (strstr(VERSION, "devel")) {
> -   if (patch == 0) {
> -   patch = 99;
> -   if (minor == 0) {
> -   minor = 99;
> -   --major;
> -   } else
> -   --minor;
> -   } else
> -   --patch;
> -   }
> -   uint32_t version = VK_MAKE_VERSION(major, minor, patch);
> -   return version;
> -}
> -
>  void radv_GetPhysicalDeviceProperties(
> VkPhysicalDevicephysicalDevice,
> VkPhysicalDeviceProperties* pProperties)
> @@ -731,7 +709,7 @@ void radv_GetPhysicalDeviceProperties(
>
> *pProperties = (VkPhysicalDeviceProperties) {
> .apiVersion = VK_MAKE_VERSION(1, 0, 42),
> -   .driverVersion = radv_get_driver_version(),
> +   .driverVersion = vk_get_driver_version(),
> .vendorID = 0x1002,
> .deviceID = pdevice->rad_info.pci_id,
> .deviceType = pdevice->rad_info.has_dedicated_vram ?
> VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_
> INTEGRATED_GPU,
> diff --git a/src/vulkan/Makefile.sources b/src/vulkan/Makefile.sources
> index 9962c1b..2cf7218 100644
> --- a/src/vulkan/Makefile.sources
> +++ b/src/vulkan/Makefile.sources
> @@ -17,6 +17,7 @@ VULKAN_WSI_X11_FILES := \
>
>  VULKAN_UTIL_FILES := \
> util/vk_alloc.h \
> +   util/vk_util.c \
> util/vk_util.h
>
>  VULKAN_UTIL_GENERATED_FILES := \
> diff --git a/src/vulkan/util/vk_util.c b/src/vulkan/util/vk_util.c
> new file mode 100644
> index 000..769e690
> --- /dev/null
> +++ b/src/vulkan/util/vk_util.c
> @@ -0,0 +1,49 @@
> +/*
> + * Copyright © 2016 Red Hat.
> + * Copyright © 2016 Bas Nieuwenhuizen
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the
> "Software"),
> + * to deal in the Software without restriction, including without
> limitation
> + * the rights to use, copy, modify, merge, publish, distribute,
> sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the
> next
> + * paragraph) shall be included in all copies or substantial portions of
> the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT
> SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include 
> +#include 
> +#include "vk_util.h"
> +
> +uint32_t vk_get_driver_version(void)
> +{
> +   const char *minor_string = strchr(VERSION, '.');
> +   const char *patch_string = minor_string ? strchr(minor_string + 1,
> '.') : NULL;
> +   int major = atoi(VERSION);
> +   int minor = minor_string ? atoi(minor_string + 1) : 0;
> +   int patch = patch_string ? atoi(patch_string + 1) : 0;
> +   if (strstr(VERSION, "devel")) {
> +  if (patch == 0) {
> + patch = 99;
> + 

Re: [Mesa-dev] [PATCH v2] radv/vulkan: Move radv_get_driver_version to src/vulkan/util

[Alex Smith]

Yes, please!

On 6 June 2017 at 16:12, Jason Ekstrand  wrote:

> Reviewed-by: Jason Ekstrand 
>
> Alex, do you need someone to push these for you?
>
> On Tue, Jun 6, 2017 at 8:09 AM, Alex Smith 
> wrote:
>
>> This means it can be reused for other Vulkan drivers. Also fix up a
>> typo, need to search for '.' in the version string rather than ','.
>>
>> v2: Remove unneeded temporary version variable (Emil, Eric)
>>
>> Signed-off-by: Alex Smith 
>> ---
>>  src/amd/vulkan/radv_device.c | 24 +-
>>  src/vulkan/Makefile.sources  |  1 +
>>  src/vulkan/util/vk_util.c| 49 ++
>> ++
>>  src/vulkan/util/vk_util.h|  2 ++
>>  4 files changed, 53 insertions(+), 23 deletions(-)
>>  create mode 100644 src/vulkan/util/vk_util.c
>>
>> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
>> index a812527..5fdb894 100644
>> --- a/src/amd/vulkan/radv_device.c
>> +++ b/src/amd/vulkan/radv_device.c
>> @@ -574,28 +574,6 @@ void radv_GetPhysicalDeviceFeatures2KHR(
>> return radv_GetPhysicalDeviceFeatures(physicalDevice,
>> &pFeatures->features);
>>  }
>>
>> -static uint32_t radv_get_driver_version()
>> -{
>> -   const char *minor_string = strchr(VERSION, '.');
>> -   const char *patch_string = minor_string ? strchr(minor_string +
>> 1, ','): NULL;
>> -   int major = atoi(VERSION);
>> -   int minor = minor_string ? atoi(minor_string + 1) : 0;
>> -   int patch = patch_string ? atoi(patch_string + 1) : 0;
>> -   if (strstr(VERSION, "devel")) {
>> -   if (patch == 0) {
>> -   patch = 99;
>> -   if (minor == 0) {
>> -   minor = 99;
>> -   --major;
>> -   } else
>> -   --minor;
>> -   } else
>> -   --patch;
>> -   }
>> -   uint32_t version = VK_MAKE_VERSION(major, minor, patch);
>> -   return version;
>> -}
>> -
>>  void radv_GetPhysicalDeviceProperties(
>> VkPhysicalDevicephysicalDevice,
>> VkPhysicalDeviceProperties* pProperties)
>> @@ -731,7 +709,7 @@ void radv_GetPhysicalDeviceProperties(
>>
>> *pProperties = (VkPhysicalDeviceProperties) {
>> .apiVersion = VK_MAKE_VERSION(1, 0, 42),
>> -   .driverVersion = radv_get_driver_version(),
>> +   .driverVersion = vk_get_driver_version(),
>> .vendorID = 0x1002,
>> .deviceID = pdevice->rad_info.pci_id,
>> .deviceType = pdevice->rad_info.has_dedicated_vram ?
>> VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGR
>> ATED_GPU,
>> diff --git a/src/vulkan/Makefile.sources b/src/vulkan/Makefile.sources
>> index 9962c1b..2cf7218 100644
>> --- a/src/vulkan/Makefile.sources
>> +++ b/src/vulkan/Makefile.sources
>> @@ -17,6 +17,7 @@ VULKAN_WSI_X11_FILES := \
>>
>>  VULKAN_UTIL_FILES := \
>> util/vk_alloc.h \
>> +   util/vk_util.c \
>> util/vk_util.h
>>
>>  VULKAN_UTIL_GENERATED_FILES := \
>> diff --git a/src/vulkan/util/vk_util.c b/src/vulkan/util/vk_util.c
>> new file mode 100644
>> index 000..769e690
>> --- /dev/null
>> +++ b/src/vulkan/util/vk_util.c
>> @@ -0,0 +1,49 @@
>> +/*
>> + * Copyright © 2016 Red Hat.
>> + * Copyright © 2016 Bas Nieuwenhuizen
>> + * Copyright © 2017 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining
>> a
>> + * copy of this software and associated documentation files (the
>> "Software"),
>> + * to deal in the Software without restriction, including without
>> limitation
>> + * the rights to use, copy, modify, merge, publish, distribute,
>> sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including the
>> next
>> + * paragraph) shall be included in all copies or substantial portions of
>> the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT
>> SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> DEALINGS
>> + * IN THE SOFTWARE.
>> + */
>> +
>> +#include 
>> +#include 
>> +#include "vk_util.h"
>> +
>> +uint32_t vk_get_driver_version(void)
>> +{
>> +   const char *minor_string = strchr(VERSION, '.');
>> +   const char *patch_string = minor_string ? strchr(minor_string + 1,
>> '.') : NULL;
>> +   int major = atoi(VERSION);
>> +   int 

Re: [Mesa-dev] [PATCH] intel/blorp: Set needs_(dst|src)_offset for Gen4 cubemaps

[Ian Romanick]

On 06/05/2017 06:03 PM, Jason Ekstrand wrote:
> On Mon, Jun 5, 2017 at 5:22 PM, Ian Romanick  > wrote:
> 
> From: Jason Ekstrand  >
> 
> We call convert_to_single_slice so they may end up with a non-trivial
> offset that needs to be taken into account.
> 
> v2 (idr): Also set needs_src_offset.  Suggested by Jason.
> 
> Fixes
> ES2-CTS.functional.texture.specification.basic_copyteximage2d.cube_rgba
> and
> ES2-CTS.functional.texture.specification.basic_copytexsubimage2d.cube_rgba
> on G45.
> 
> 
> Don't we also need the patch which makes us respect needs_src_offset for
> the bilinear filter case?

I had expected that we would, but it didn't seem to matter for this
test.  I was going to wait on the other patches until the whole series
is ready, but I could send out the speculative fixes sooner.

> Signed-off-by: Ian Romanick  >
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101284
> 
> ---
>  src/intel/blorp/blorp_blit.c | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
> index d93cde2..e48e5da 100644
> --- a/src/intel/blorp/blorp_blit.c
> +++ b/src/intel/blorp/blorp_blit.c
> @@ -1672,11 +1672,15 @@ try_blorp_blit(struct blorp_batch *batch,
>/* The MinLOD and MinimumArrayElement don't work properly for
> cube maps.
> * Convert them to a single slice on gen4.
> */
> -  if (params->dst.surf.usage & ISL_SURF_USAGE_CUBE_BIT)
> +  if (params->dst.surf.usage & ISL_SURF_USAGE_CUBE_BIT) {
>   blorp_surf_convert_to_single_slice(batch->blorp->isl_dev,
> ¶ms->dst);
> + wm_prog_key->need_dst_offset = true;
> +  }
> 
> -  if (params->src.surf.usage & ISL_SURF_USAGE_CUBE_BIT)
> +  if (params->src.surf.usage & ISL_SURF_USAGE_CUBE_BIT) {
>   blorp_surf_convert_to_single_slice(batch->blorp->isl_dev,
> ¶ms->src);
> + wm_prog_key->need_src_offset = true;
> +  }
> }
> 
> if (devinfo->gen > 6 &&
> --
> 2.9.4
> 
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> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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[Mesa-dev] [PATCH 02/10] genxml: Rename SF_STATE field to match gen6+.

[Rafael Antognolli]

Rename "Use Point Width State" to "Point Width Source". It accepts the same
values and has the same meaning as gen6+, so lets keep them with the same name
to simplify the code.

Signed-off-by: Rafael Antognolli 
---
 src/intel/genxml/gen4.xml  | 6 +++---
 src/intel/genxml/gen45.xml | 6 +++---
 src/intel/genxml/gen5.xml  | 6 +++---
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/intel/genxml/gen4.xml b/src/intel/genxml/gen4.xml
index 72be95b..d37c85a 100644
--- a/src/intel/genxml/gen4.xml
+++ b/src/intel/genxml/gen4.xml
@@ -686,9 +686,9 @@
   
   
 
-
-  
-  
+
+  
+  
 
 
   
diff --git a/src/intel/genxml/gen45.xml b/src/intel/genxml/gen45.xml
index ff7d72f..730231a 100644
--- a/src/intel/genxml/gen45.xml
+++ b/src/intel/genxml/gen45.xml
@@ -700,9 +700,9 @@
   
   
 
-
-  
-  
+
+  
+  
 
 
   
diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml
index bd2e417..fdaa579 100644
--- a/src/intel/genxml/gen5.xml
+++ b/src/intel/genxml/gen5.xml
@@ -791,9 +791,9 @@
   
   
 
-
-  
-  
+
+  
+  
 
 
   
-- 
2.9.3

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[Mesa-dev] [PATCH 00/10] Convert a couple more states to genxml.

[Rafael Antognolli]

This series converts SF_STATE, COLOR_CALC_STATE adn BLEND_CONSTANT_COLOR state
to use genxml. It has to be applied on top of this series from Ken:

https://patchwork.freedesktop.org/series/24245/

Kenneth Graunke (1):
  i965: Make a helper function for depth/stencil related state.

Rafael Antognolli (9):
  i965: aa_line_distance_mode should be before the padding.
  genxml: Rename SF_STATE field to match gen6+.
  genxml: Rename fields to match gen6+.
  genxml: The viewport state offset is actually an address.
  i965: Convert SF_STATE to genxml.
  i965: Make a helper function for blend entry related state.
  i965: Check for alpha channel just like in gen6+.
  i965: Convert CC state on gen4-5 to genxml.
  i965: Convert BLEND_CONSTANT_COLOR state to genxml.

 src/intel/genxml/gen4.xml |   8 +-
 src/intel/genxml/gen45.xml|  10 +-
 src/intel/genxml/gen5.xml |   8 +-
 src/mesa/drivers/dri/i965/Makefile.sources|   2 -
 src/mesa/drivers/dri/i965/brw_cc.c| 233 
 src/mesa/drivers/dri/i965/brw_sf_state.c  | 200 ---
 src/mesa/drivers/dri/i965/brw_state.h |   2 -
 src/mesa/drivers/dri/i965/brw_structs.h   | 151 
 src/mesa/drivers/dri/i965/brw_util.h  |   1 -
 src/mesa/drivers/dri/i965/genX_state_upload.c | 495 ++
 10 files changed, 351 insertions(+), 759 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/brw_cc.c
 delete mode 100644 src/mesa/drivers/dri/i965/brw_sf_state.c

-- 
2.9.3

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[Mesa-dev] [PATCH 01/10] i965: aa_line_distance_mode should be before the padding.

[Rafael Antognolli]

It seems that it was never set correctly.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/brw_structs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_structs.h 
b/src/mesa/drivers/dri/i965/brw_structs.h
index 35db2f5..73641da 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -321,8 +321,8 @@ struct brw_sf_unit_state
   unsigned use_point_size_state:1;
   unsigned subpixel_precision:1;
   unsigned sprite_point:1;
-  unsigned pad0:10;
   unsigned aa_line_distance_mode:1;
+  unsigned pad0:10;
   unsigned trifan_pv:2;
   unsigned linestrip_pv:2;
   unsigned tristrip_pv:2;
-- 
2.9.3

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[Mesa-dev] [PATCH 04/10] genxml: The viewport state offset is actually an address.

[Rafael Antognolli]

This fixes code generation on gen45.

Signed-off-by: Rafael Antognolli 
---
 src/intel/genxml/gen45.xml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/genxml/gen45.xml b/src/intel/genxml/gen45.xml
index 46d1949..59460fd 100644
--- a/src/intel/genxml/gen45.xml
+++ b/src/intel/genxml/gen45.xml
@@ -646,7 +646,7 @@
 
 
 
-
+
 
 
   
-- 
2.9.3

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[Mesa-dev] [PATCH 09/10] i965: Convert CC state on gen4-5 to genxml.

[Rafael Antognolli]

Use set_blend_entry_bits and set_depth_stencil_bits to fill most of the
color calc struct, and then manually update the rest.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/brw_cc.c| 174 --
 src/mesa/drivers/dri/i965/brw_state.h |   1 -
 src/mesa/drivers/dri/i965/brw_structs.h   |  92 --
 src/mesa/drivers/dri/i965/brw_util.h  |   1 -
 src/mesa/drivers/dri/i965/genX_state_upload.c |  99 ---
 5 files changed, 81 insertions(+), 286 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_cc.c 
b/src/mesa/drivers/dri/i965/brw_cc.c
index cdaa696..503ec83 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -39,180 +39,6 @@
 #include "main/stencil.h"
 #include "intel_batchbuffer.h"
 
-/**
- * Modify blend function to force destination alpha to 1.0
- *
- * If \c function specifies a blend function that uses destination alpha,
- * replace it with a function that hard-wires destination alpha to 1.0.  This
- * is used when rendering to xRGB targets.
- */
-GLenum
-brw_fix_xRGB_alpha(GLenum function)
-{
-   switch (function) {
-   case GL_DST_ALPHA:
-  return GL_ONE;
-
-   case GL_ONE_MINUS_DST_ALPHA:
-   case GL_SRC_ALPHA_SATURATE:
-  return GL_ZERO;
-   }
-
-   return function;
-}
-
-/**
- * Creates a CC unit packet from the current blend state.
- */
-static void upload_cc_unit(struct brw_context *brw)
-{
-   struct gl_context *ctx = &brw->ctx;
-   struct brw_cc_unit_state *cc;
-
-   cc = brw_state_batch(brw, sizeof(*cc), 64, &brw->cc.state_offset);
-   memset(cc, 0, sizeof(*cc));
-
-   /* _NEW_STENCIL | _NEW_BUFFERS */
-   if (ctx->Stencil._Enabled) {
-  const unsigned back = ctx->Stencil._BackFace;
-
-  cc->cc0.stencil_enable = 1;
-  cc->cc0.stencil_func =
-intel_translate_compare_func(ctx->Stencil.Function[0]);
-  cc->cc0.stencil_fail_op =
-intel_translate_stencil_op(ctx->Stencil.FailFunc[0]);
-  cc->cc0.stencil_pass_depth_fail_op =
-intel_translate_stencil_op(ctx->Stencil.ZFailFunc[0]);
-  cc->cc0.stencil_pass_depth_pass_op =
-intel_translate_stencil_op(ctx->Stencil.ZPassFunc[0]);
-  cc->cc1.stencil_ref = _mesa_get_stencil_ref(ctx, 0);
-  cc->cc1.stencil_write_mask = ctx->Stencil.WriteMask[0];
-  cc->cc1.stencil_test_mask = ctx->Stencil.ValueMask[0];
-
-  if (ctx->Stencil._TestTwoSide) {
-cc->cc0.bf_stencil_enable = 1;
-cc->cc0.bf_stencil_func =
-   intel_translate_compare_func(ctx->Stencil.Function[back]);
-cc->cc0.bf_stencil_fail_op =
-   intel_translate_stencil_op(ctx->Stencil.FailFunc[back]);
-cc->cc0.bf_stencil_pass_depth_fail_op =
-   intel_translate_stencil_op(ctx->Stencil.ZFailFunc[back]);
-cc->cc0.bf_stencil_pass_depth_pass_op =
-   intel_translate_stencil_op(ctx->Stencil.ZPassFunc[back]);
-cc->cc1.bf_stencil_ref = _mesa_get_stencil_ref(ctx, back);
-cc->cc2.bf_stencil_write_mask = ctx->Stencil.WriteMask[back];
-cc->cc2.bf_stencil_test_mask = ctx->Stencil.ValueMask[back];
-  }
-
-  /* Not really sure about this:
-   */
-  if (ctx->Stencil.WriteMask[0] ||
- (ctx->Stencil._TestTwoSide && ctx->Stencil.WriteMask[back]))
-cc->cc0.stencil_write_enable = 1;
-   }
-
-   /* _NEW_COLOR */
-   if (ctx->Color.ColorLogicOpEnabled && ctx->Color.LogicOp != GL_COPY) {
-  cc->cc2.logicop_enable = 1;
-  cc->cc5.logicop_func = intel_translate_logic_op(ctx->Color.LogicOp);
-   } else if (ctx->Color.BlendEnabled && !ctx->Color._AdvancedBlendMode) {
-  GLenum eqRGB = ctx->Color.Blend[0].EquationRGB;
-  GLenum eqA = ctx->Color.Blend[0].EquationA;
-  GLenum srcRGB = ctx->Color.Blend[0].SrcRGB;
-  GLenum dstRGB = ctx->Color.Blend[0].DstRGB;
-  GLenum srcA = ctx->Color.Blend[0].SrcA;
-  GLenum dstA = ctx->Color.Blend[0].DstA;
-
-  if (eqRGB == GL_MIN || eqRGB == GL_MAX) {
-srcRGB = dstRGB = GL_ONE;
-  }
-
-  if (eqA == GL_MIN || eqA == GL_MAX) {
-srcA = dstA = GL_ONE;
-  }
-
-  /* If the renderbuffer is XRGB, we have to frob the blend function to
-   * force the destination alpha to 1.0.  This means replacing GL_DST_ALPHA
-   * with GL_ONE and GL_ONE_MINUS_DST_ALPHA with GL_ZERO.
-   */
-  const struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
-  if (rb && !_mesa_base_format_has_channel(rb->_BaseFormat,
-   GL_TEXTURE_ALPHA_TYPE)) {
-srcRGB = brw_fix_xRGB_alpha(srcRGB);
-srcA   = brw_fix_xRGB_alpha(srcA);
-dstRGB = brw_fix_xRGB_alpha(dstRGB);
-dstA   = brw_fix_xRGB_alpha(dstA);
-  }
-
-  cc->cc6.dest_blend_factor = brw_translate_blend_factor(dstRGB);
-  cc->cc6.src_blend_factor = brw_translate_blend_factor(srcRGB);
-  cc->cc6.blend_function = brw_translate_blend_equation(eqRGB);
-
-  cc->cc5

[Mesa-dev] [PATCH 05/10] i965: Convert SF_STATE to genxml.

[Rafael Antognolli]

This patch finishes the work done by Ken of converting SF_STATE to genxml, and
merges it with gen6+ code for emitting that state.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/Makefile.sources|   1 -
 src/mesa/drivers/dri/i965/brw_sf_state.c  | 200 --
 src/mesa/drivers/dri/i965/brw_state.h |   1 -
 src/mesa/drivers/dri/i965/brw_structs.h   |  59 
 src/mesa/drivers/dri/i965/genX_state_upload.c | 110 ++
 5 files changed, 83 insertions(+), 288 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/brw_sf_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index cc030c2..9f00d40 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -45,7 +45,6 @@ i965_FILES = \
brw_reset.c \
brw_sampler_state.c \
brw_sf.c \
-   brw_sf_state.c \
brw_state_batch.c \
brw_state.h \
brw_state_upload.c \
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c 
b/src/mesa/drivers/dri/i965/brw_sf_state.c
deleted file mode 100644
index 0c3cbce..000
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- Copyright (C) Intel Corp.  2006.  All Rights Reserved.
- Intel funded Tungsten Graphics to
- develop this 3D driver.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice (including the
- next paragraph) shall be included in all copies or substantial
- portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
- **/
- /*
-  * Authors:
-  *   Keith Whitwell 
-  */
-
-
-
-#include "main/mtypes.h"
-#include "main/macros.h"
-#include "main/fbobject.h"
-#include "main/viewport.h"
-#include "intel_batchbuffer.h"
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "brw_util.h"
-
-static void upload_sf_unit( struct brw_context *brw )
-{
-   struct gl_context *ctx = &brw->ctx;
-   struct brw_sf_unit_state *sf;
-   int chipset_max_threads;
-   bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
-
-   sf = brw_state_batch(brw, sizeof(*sf), 64, &brw->sf.state_offset);
-
-   memset(sf, 0, sizeof(*sf));
-
-   /* BRW_NEW_PROGRAM_CACHE | BRW_NEW_SF_PROG_DATA */
-   sf->thread0.grf_reg_count = ALIGN(brw->sf.prog_data->total_grf, 16) / 16 - 
1;
-   sf->thread0.kernel_start_pointer =
-  brw_program_reloc(brw,
-   brw->sf.state_offset +
-   offsetof(struct brw_sf_unit_state, thread0),
-   brw->sf.prog_offset +
-   (sf->thread0.grf_reg_count << 1)) >> 6;
-
-   sf->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
-
-   sf->thread3.dispatch_grf_start_reg = 3;
-   sf->thread3.urb_entry_read_offset = BRW_SF_URB_ENTRY_READ_OFFSET;
-
-   /* BRW_NEW_SF_PROG_DATA */
-   sf->thread3.urb_entry_read_length = brw->sf.prog_data->urb_read_length;
-
-   /* BRW_NEW_URB_FENCE */
-   sf->thread4.nr_urb_entries = brw->urb.nr_sf_entries;
-   sf->thread4.urb_entry_allocation_size = brw->urb.sfsize - 1;
-
-   /* Each SF thread produces 1 PUE, and there can be up to 24 (Pre-Ironlake) 
or
-* 48 (Ironlake) threads.
-*/
-   if (brw->gen == 5)
-  chipset_max_threads = 48;
-   else
-  chipset_max_threads = 24;
-
-   /* BRW_NEW_URB_FENCE */
-   sf->thread4.max_threads = MIN2(chipset_max_threads,
- brw->urb.nr_sf_entries) - 1;
-
-   /* BRW_NEW_SF_VP */
-   sf->sf5.sf_viewport_state_offset = (brw->batch.bo->offset64 +
-  brw->sf.vp_offset) >> 5; /* reloc */
-
-   sf->sf5.viewport_transform = 1;
-
-   sf->sf6.scissor = 1;
-
-   /* _NEW_POLYGON */
-   if (ctx->Polygon._FrontBit)
-  sf->sf5.front_winding = BRW_FRONTWINDING_CW;
-   else
-  sf->sf5.front_winding = BRW_FRONTWINDING_CCW;
-
-   /* _NEW_BUFFERS
-* The viewport is inverted for rendering to a FBO, and that inverts
-* polygon front/back orientation.
-*/
-   s

[Mesa-dev] [PATCH 08/10] i965: Check for alpha channel just like in gen6+.

[Rafael Antognolli]

gen6+ uses _mesa_base_format_has_channel() to check for the alpha
channel, while gen4-5 use ctx->DrawBuffer->Visual.alphaBits. By using
_mesa_base_format_has_channel() here we keep the same behavior accross
all gen.

While initially both ways of checking the alpha channel seemed correct
to me, this change also seems to fix fbo-blending-formats piglit test on
gen4.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/brw_cc.c | 21 -
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_cc.c 
b/src/mesa/drivers/dri/i965/brw_cc.c
index 78d3bc8..cdaa696 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -34,6 +34,7 @@
 #include "brw_state.h"
 #include "brw_defines.h"
 #include "brw_util.h"
+#include "main/glformats.h"
 #include "main/macros.h"
 #include "main/stencil.h"
 #include "intel_batchbuffer.h"
@@ -122,25 +123,27 @@ static void upload_cc_unit(struct brw_context *brw)
   GLenum srcA = ctx->Color.Blend[0].SrcA;
   GLenum dstA = ctx->Color.Blend[0].DstA;
 
+  if (eqRGB == GL_MIN || eqRGB == GL_MAX) {
+srcRGB = dstRGB = GL_ONE;
+  }
+
+  if (eqA == GL_MIN || eqA == GL_MAX) {
+srcA = dstA = GL_ONE;
+  }
+
   /* If the renderbuffer is XRGB, we have to frob the blend function to
* force the destination alpha to 1.0.  This means replacing GL_DST_ALPHA
* with GL_ONE and GL_ONE_MINUS_DST_ALPHA with GL_ZERO.
*/
-  if (ctx->DrawBuffer->Visual.alphaBits == 0) {
+  const struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
+  if (rb && !_mesa_base_format_has_channel(rb->_BaseFormat,
+   GL_TEXTURE_ALPHA_TYPE)) {
 srcRGB = brw_fix_xRGB_alpha(srcRGB);
 srcA   = brw_fix_xRGB_alpha(srcA);
 dstRGB = brw_fix_xRGB_alpha(dstRGB);
 dstA   = brw_fix_xRGB_alpha(dstA);
   }
 
-  if (eqRGB == GL_MIN || eqRGB == GL_MAX) {
-srcRGB = dstRGB = GL_ONE;
-  }
-
-  if (eqA == GL_MIN || eqA == GL_MAX) {
-srcA = dstA = GL_ONE;
-  }
-
   cc->cc6.dest_blend_factor = brw_translate_blend_factor(dstRGB);
   cc->cc6.src_blend_factor = brw_translate_blend_factor(srcRGB);
   cc->cc6.blend_function = brw_translate_blend_equation(eqRGB);
-- 
2.9.3

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[Mesa-dev] [PATCH 10/10] i965: Convert BLEND_CONSTANT_COLOR state to genxml.

[Rafael Antognolli]

It's a very simple conversion, and it allows us to delete brw_cc.c.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/Makefile.sources|  1 -
 src/mesa/drivers/dri/i965/brw_cc.c| 62 ---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 28 +++-
 3 files changed, 27 insertions(+), 64 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/brw_cc.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 9f00d40..e7f4eda 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -4,7 +4,6 @@ i965_FILES = \
brw_blorp.h \
brw_bufmgr.c \
brw_bufmgr.h \
-   brw_cc.c \
brw_clear.c \
brw_clip.c \
brw_clip_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c 
b/src/mesa/drivers/dri/i965/brw_cc.c
deleted file mode 100644
index 503ec83..000
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- Copyright (C) Intel Corp.  2006.  All Rights Reserved.
- Intel funded Tungsten Graphics to
- develop this 3D driver.
-
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
-
- The above copyright notice and this permission notice (including the
- next paragraph) shall be included in all copies or substantial
- portions of the Software.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
- **/
- /*
-  * Authors:
-  *   Keith Whitwell 
-  */
-
-
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "brw_util.h"
-#include "main/glformats.h"
-#include "main/macros.h"
-#include "main/stencil.h"
-#include "intel_batchbuffer.h"
-
-static void upload_blend_constant_color(struct brw_context *brw)
-{
-   struct gl_context *ctx = &brw->ctx;
-
-   BEGIN_BATCH(5);
-   OUT_BATCH(_3DSTATE_BLEND_CONSTANT_COLOR << 16 | (5-2));
-   OUT_BATCH_F(ctx->Color.BlendColorUnclamped[0]);
-   OUT_BATCH_F(ctx->Color.BlendColorUnclamped[1]);
-   OUT_BATCH_F(ctx->Color.BlendColorUnclamped[2]);
-   OUT_BATCH_F(ctx->Color.BlendColorUnclamped[3]);
-   ADVANCE_BATCH();
-}
-
-const struct brw_tracked_state brw_blend_constant_color = {
-   .dirty = {
-  .mesa = _NEW_COLOR,
-  .brw = BRW_NEW_CONTEXT |
- BRW_NEW_BLORP,
-   },
-   .emit = upload_blend_constant_color
-};
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index af85af2..f29ce78 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -4267,6 +4267,32 @@ static const struct brw_tracked_state genX(vf_topology) 
= {
 
 /* -- */
 
+#if GEN_GEN <= 5
+
+static void genX(upload_blend_constant_color)(struct brw_context *brw)
+{
+   struct gl_context *ctx = &brw->ctx;
+
+   brw_batch_emit(brw, GENX(3DSTATE_CONSTANT_COLOR), blend_cc) {
+  blend_cc.BlendConstantColorRed = ctx->Color.BlendColorUnclamped[0];
+  blend_cc.BlendConstantColorGreen = ctx->Color.BlendColorUnclamped[1];
+  blend_cc.BlendConstantColorBlue = ctx->Color.BlendColorUnclamped[2];
+  blend_cc.BlendConstantColorAlpha = ctx->Color.BlendColorUnclamped[3];
+   }
+}
+
+static const struct brw_tracked_state genX(blend_constant_color) = {
+   .dirty = {
+  .mesa = _NEW_COLOR,
+  .brw = BRW_NEW_CONTEXT |
+ BRW_NEW_BLORP,
+   },
+   .emit = genX(upload_blend_constant_color)
+};
+#endif
+
+/* -- */
+
 void
 genX(init_atoms)(struct brw_context *brw)
 {
@@ -4310,7 +4336,7 @@ genX(init_atoms)(struct brw_context *brw)
   &brw_invariant_state,
 
   &brw_binding_table_pointers,
-  &brw_blend_constant_color,
+  &genX(blend_constant_color),
 
   &brw_depthbuffer,
 
-- 
2.9.3

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[Mesa-dev] [PATCH 06/10] i965: Make a helper function for depth/stencil related state.

[Rafael Antognolli]

From: Kenneth Graunke 

Gen4-5 basically glue DEPTH_STENCIL_STATE, COLOR_CALC_STATE, and
BLEND_STATE together into a single COLOR_CALC_STATE structure.

By making a helper function, we'll be able to reuse it when filling
out Gen4-5 COLOR_CALC_STATE without replicating any actual logic.

We use generation-defined typedef to handle the polymorphism.
---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 113 +++---
 1 file changed, 65 insertions(+), 48 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 4233de2..f0068e1 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -1151,9 +1151,16 @@ genX(calculate_attr_overrides)(const struct brw_context 
*brw,
 
 /* -- */
 
-#if GEN_GEN >= 6
-static void
-genX(upload_depth_stencil_state)(struct brw_context *brw)
+#if GEN_GEN >= 8
+typedef struct GENX(3DSTATE_WM_DEPTH_STENCIL) DEPTH_STENCIL_GENXML;
+#elif GEN_GEN >= 6
+typedef struct GENX(DEPTH_STENCIL_STATE)  DEPTH_STENCIL_GENXML;
+#else
+typedef struct GENX(COLOR_CALC_STATE) DEPTH_STENCIL_GENXML;
+#endif
+
+static inline void
+set_depth_stencil_bits(struct brw_context *brw, DEPTH_STENCIL_GENXML *ds)
 {
struct gl_context *ctx = &brw->ctx;
 
@@ -1168,66 +1175,76 @@ genX(upload_depth_stencil_state)(struct brw_context 
*brw)
struct gl_stencil_attrib *stencil = &ctx->Stencil;
const int b = stencil->_BackFace;
 
-#if GEN_GEN >= 8
-   brw_batch_emit(brw, GENX(3DSTATE_WM_DEPTH_STENCIL), wmds) {
-#else
-   uint32_t ds_offset;
-   brw_state_emit(brw, GENX(DEPTH_STENCIL_STATE), 64, &ds_offset, wmds) {
-#endif
-  if (depth->Test && depth_irb) {
- wmds.DepthTestEnable = true;
- wmds.DepthBufferWriteEnable = brw_depth_writes_enabled(brw);
- wmds.DepthTestFunction = intel_translate_compare_func(depth->Func);
-  }
+   if (depth->Test && depth_irb) {
+  ds->DepthTestEnable = true;
+  ds->DepthBufferWriteEnable = brw_depth_writes_enabled(brw);
+  ds->DepthTestFunction = intel_translate_compare_func(depth->Func);
+   }
 
-  if (stencil->_Enabled) {
- wmds.StencilTestEnable = true;
- wmds.StencilWriteMask = stencil->WriteMask[0] & 0xff;
- wmds.StencilTestMask = stencil->ValueMask[0] & 0xff;
-
- wmds.StencilTestFunction =
-intel_translate_compare_func(stencil->Function[0]);
- wmds.StencilFailOp =
-intel_translate_stencil_op(stencil->FailFunc[0]);
- wmds.StencilPassDepthPassOp =
-intel_translate_stencil_op(stencil->ZPassFunc[0]);
- wmds.StencilPassDepthFailOp =
-intel_translate_stencil_op(stencil->ZFailFunc[0]);
-
- wmds.StencilBufferWriteEnable = stencil->_WriteEnabled;
-
- if (stencil->_TestTwoSide) {
-wmds.DoubleSidedStencilEnable = true;
-wmds.BackfaceStencilWriteMask = stencil->WriteMask[b] & 0xff;
-wmds.BackfaceStencilTestMask = stencil->ValueMask[b] & 0xff;
-
-wmds.BackfaceStencilTestFunction =
-   intel_translate_compare_func(stencil->Function[b]);
-wmds.BackfaceStencilFailOp =
-   intel_translate_stencil_op(stencil->FailFunc[b]);
-wmds.BackfaceStencilPassDepthPassOp =
-   intel_translate_stencil_op(stencil->ZPassFunc[b]);
-wmds.BackfaceStencilPassDepthFailOp =
-   intel_translate_stencil_op(stencil->ZFailFunc[b]);
- }
+   if (stencil->_Enabled) {
+  ds->StencilTestEnable = true;
+  ds->StencilWriteMask = stencil->WriteMask[0] & 0xff;
+  ds->StencilTestMask = stencil->ValueMask[0] & 0xff;
+
+  ds->StencilTestFunction =
+ intel_translate_compare_func(stencil->Function[0]);
+  ds->StencilFailOp =
+ intel_translate_stencil_op(stencil->FailFunc[0]);
+  ds->StencilPassDepthPassOp =
+ intel_translate_stencil_op(stencil->ZPassFunc[0]);
+  ds->StencilPassDepthFailOp =
+ intel_translate_stencil_op(stencil->ZFailFunc[0]);
+
+  ds->StencilBufferWriteEnable = stencil->_WriteEnabled;
+
+  if (stencil->_TestTwoSide) {
+ ds->DoubleSidedStencilEnable = true;
+ ds->BackfaceStencilWriteMask = stencil->WriteMask[b] & 0xff;
+ ds->BackfaceStencilTestMask = stencil->ValueMask[b] & 0xff;
+
+ ds->BackfaceStencilTestFunction =
+intel_translate_compare_func(stencil->Function[b]);
+ ds->BackfaceStencilFailOp =
+intel_translate_stencil_op(stencil->FailFunc[b]);
+ ds->BackfaceStencilPassDepthPassOp =
+intel_translate_stencil_op(stencil->ZPassFunc[b]);
+ ds->BackfaceStencilPassDepthFailOp =
+intel_translate_stencil_op(stencil->ZFailFunc[b]);
+  }
 
 #if GEN_GEN >= 9
- wmds.StencilReferenceValue = _mesa_get_stencil_ref(ctx, 0);
- 

[Mesa-dev] [PATCH 07/10] i965: Make a helper function for blend entry related state.

[Rafael Antognolli]

Add a helper function to reuse code that fills blend entry related
state, and make genX(upload_blend_state) use it. This function can later
be used by gen4-5 color calc state to set the blend related bits.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 155 +++---
 1 file changed, 87 insertions(+), 68 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index f0068e1..089596e 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -2512,6 +2512,90 @@ static const struct brw_tracked_state genX(gs_state) = {
 #define blend_eqn(x) brw_translate_blend_equation(x)
 
 #if GEN_GEN >= 6
+typedef struct GENX(BLEND_STATE_ENTRY) BLEND_ENTRY_GENXML;
+#else
+typedef struct GENX(COLOR_CALC_STATE) BLEND_ENTRY_GENXML;
+#endif
+
+UNUSED static bool
+set_blend_entry_bits(struct brw_context *brw, BLEND_ENTRY_GENXML *entry, int i)
+{
+   struct gl_context *ctx = &brw->ctx;
+
+   /* _NEW_BUFFERS */
+   const struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
+
+   bool independent_alpha_blend = false;
+
+   /* Used for implementing the following bit of GL_EXT_texture_integer:
+* "Per-fragment operations that require floating-point color
+*  components, including multisample alpha operations, alpha test,
+*  blending, and dithering, have no effect when the corresponding
+*  colors are written to an integer color buffer."
+*/
+   const bool integer = ctx->DrawBuffer->_IntegerBuffers & (0x1 << i);
+
+   /* _NEW_COLOR */
+   if (ctx->Color.ColorLogicOpEnabled) {
+  GLenum rb_type = rb ? _mesa_get_format_datatype(rb->Format)
+ : GL_UNSIGNED_NORMALIZED;
+  WARN_ONCE(ctx->Color.LogicOp != GL_COPY &&
+rb_type != GL_UNSIGNED_NORMALIZED &&
+rb_type != GL_FLOAT, "Ignoring %s logic op on %s "
+"renderbuffer\n",
+_mesa_enum_to_string(ctx->Color.LogicOp),
+_mesa_enum_to_string(rb_type));
+  if (GEN_GEN >= 8 || rb_type == GL_UNSIGNED_NORMALIZED) {
+ entry->LogicOpEnable = true;
+ entry->LogicOpFunction =
+intel_translate_logic_op(ctx->Color.LogicOp);
+  }
+   } else if (ctx->Color.BlendEnabled & (1 << i) && !integer &&
+  !ctx->Color._AdvancedBlendMode) {
+  GLenum eqRGB = ctx->Color.Blend[i].EquationRGB;
+  GLenum eqA = ctx->Color.Blend[i].EquationA;
+  GLenum srcRGB = ctx->Color.Blend[i].SrcRGB;
+  GLenum dstRGB = ctx->Color.Blend[i].DstRGB;
+  GLenum srcA = ctx->Color.Blend[i].SrcA;
+  GLenum dstA = ctx->Color.Blend[i].DstA;
+
+  if (eqRGB == GL_MIN || eqRGB == GL_MAX)
+ srcRGB = dstRGB = GL_ONE;
+
+  if (eqA == GL_MIN || eqA == GL_MAX)
+ srcA = dstA = GL_ONE;
+
+  /* Due to hardware limitations, the destination may have information
+   * in an alpha channel even when the format specifies no alpha
+   * channel. In order to avoid getting any incorrect blending due to
+   * that alpha channel, coerce the blend factors to values that will
+   * not read the alpha channel, but will instead use the correct
+   * implicit value for alpha.
+   */
+  if (rb && !_mesa_base_format_has_channel(rb->_BaseFormat,
+   GL_TEXTURE_ALPHA_TYPE)) {
+ srcRGB = brw_fix_xRGB_alpha(srcRGB);
+ srcA = brw_fix_xRGB_alpha(srcA);
+ dstRGB = brw_fix_xRGB_alpha(dstRGB);
+ dstA = brw_fix_xRGB_alpha(dstA);
+  }
+
+  entry->ColorBufferBlendEnable = true;
+  entry->DestinationBlendFactor = blend_factor(dstRGB);
+  entry->SourceBlendFactor = blend_factor(srcRGB);
+  entry->DestinationAlphaBlendFactor = blend_factor(dstA);
+  entry->SourceAlphaBlendFactor = blend_factor(srcA);
+  entry->ColorBlendFunction = blend_eqn(eqRGB);
+  entry->AlphaBlendFunction = blend_eqn(eqA);
+
+  if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB)
+ independent_alpha_blend = true;
+   }
+
+   return independent_alpha_blend;
+}
+
+#if GEN_GEN >= 6
 static void
 genX(upload_blend_state)(struct brw_context *brw)
 {
@@ -2578,74 +2662,9 @@ genX(upload_blend_state)(struct brw_context *brw)
 #else
   {
 #endif
-
- /* _NEW_BUFFERS */
- struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
-
- /* Used for implementing the following bit of GL_EXT_texture_integer:
-  * "Per-fragment operations that require floating-point color
-  *  components, including multisample alpha operations, alpha test,
-  *  blending, and dithering, have no effect when the corresponding
-  *  colors are written to an integer color buffer."
-  */
- bool integer = ctx->DrawBuffer->_IntegerBuffers & (0x1 << i);
-
- /* _NEW_COLOR */
- if (ctx->Color.ColorLogicOpEnabled)

[Mesa-dev] [PATCH 03/10] genxml: Rename fields to match gen6+.

[Rafael Antognolli]

"Anti-aliasing Enable" to "Anti-Aliasing Enable".

Signed-off-by: Rafael Antognolli 
---
 src/intel/genxml/gen4.xml  | 2 +-
 src/intel/genxml/gen45.xml | 2 +-
 src/intel/genxml/gen5.xml  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/intel/genxml/gen4.xml b/src/intel/genxml/gen4.xml
index d37c85a..d873422 100644
--- a/src/intel/genxml/gen4.xml
+++ b/src/intel/genxml/gen4.xml
@@ -642,7 +642,7 @@
   
   
 
-
+
 
   
   
diff --git a/src/intel/genxml/gen45.xml b/src/intel/genxml/gen45.xml
index 730231a..46d1949 100644
--- a/src/intel/genxml/gen45.xml
+++ b/src/intel/genxml/gen45.xml
@@ -652,7 +652,7 @@
   
   
 
-
+
 
   
   
diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml
index fdaa579..65479d2 100644
--- a/src/intel/genxml/gen5.xml
+++ b/src/intel/genxml/gen5.xml
@@ -743,7 +743,7 @@
   
   
 
-
+
 
   
   
-- 
2.9.3

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Re: [Mesa-dev] [PATCH] intel/blorp: Set needs_(dst|src)_offset for Gen4 cubemaps

[Jason Ekstrand]

On Tue, Jun 6, 2017 at 9:10 AM, Ian Romanick  wrote:

> On 06/05/2017 06:03 PM, Jason Ekstrand wrote:
> > On Mon, Jun 5, 2017 at 5:22 PM, Ian Romanick  > > wrote:
> >
> > From: Jason Ekstrand  > >
> >
> > We call convert_to_single_slice so they may end up with a non-trivial
> > offset that needs to be taken into account.
> >
> > v2 (idr): Also set needs_src_offset.  Suggested by Jason.
> >
> > Fixes
> > ES2-CTS.functional.texture.specification.basic_
> copyteximage2d.cube_rgba
> > and
> > ES2-CTS.functional.texture.specification.basic_
> copytexsubimage2d.cube_rgba
> > on G45.
> >
> >
> > Don't we also need the patch which makes us respect needs_src_offset for
> > the bilinear filter case?
>
> I had expected that we would, but it didn't seem to matter for this
> test.  I was going to wait on the other patches until the whole series
> is ready, but I could send out the speculative fixes sooner.
>

I don't think the other fix is speculative.  It just only happens to get
triggered by generatemipmaps tests.  If we had blitframebuffers tests which
blit into a cube, they'd trigger it too.


> > Signed-off-by: Ian Romanick  > >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101284
> > 
> > ---
> >  src/intel/blorp/blorp_blit.c | 8 ++--
> >  1 file changed, 6 insertions(+), 2 deletions(-)
> >
> > diff --git a/src/intel/blorp/blorp_blit.c
> b/src/intel/blorp/blorp_blit.c
> > index d93cde2..e48e5da 100644
> > --- a/src/intel/blorp/blorp_blit.c
> > +++ b/src/intel/blorp/blorp_blit.c
> > @@ -1672,11 +1672,15 @@ try_blorp_blit(struct blorp_batch *batch,
> >/* The MinLOD and MinimumArrayElement don't work properly for
> > cube maps.
> > * Convert them to a single slice on gen4.
> > */
> > -  if (params->dst.surf.usage & ISL_SURF_USAGE_CUBE_BIT)
> > +  if (params->dst.surf.usage & ISL_SURF_USAGE_CUBE_BIT) {
> >   blorp_surf_convert_to_single_slice(batch->blorp->isl_dev,
> > ¶ms->dst);
> > + wm_prog_key->need_dst_offset = true;
> > +  }
> >
> > -  if (params->src.surf.usage & ISL_SURF_USAGE_CUBE_BIT)
> > +  if (params->src.surf.usage & ISL_SURF_USAGE_CUBE_BIT) {
> >   blorp_surf_convert_to_single_slice(batch->blorp->isl_dev,
> > ¶ms->src);
> > + wm_prog_key->need_src_offset = true;
> > +  }
> > }
> >
> > if (devinfo->gen > 6 &&
> > --
> > 2.9.4
> >
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org  freedesktop.org>
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> > 
>
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Re: [Mesa-dev] [PATCH v2] radv/vulkan: Move radv_get_driver_version to src/vulkan/util

[Jason Ekstrand]

On Tue, Jun 6, 2017 at 8:14 AM, Alex Smith 
wrote:

> Yes, please!
>

These three as well as the anv limits patch have now landed.  Thanks!

--Jason


> On 6 June 2017 at 16:12, Jason Ekstrand  wrote:
>
>> Reviewed-by: Jason Ekstrand 
>>
>> Alex, do you need someone to push these for you?
>>
>> On Tue, Jun 6, 2017 at 8:09 AM, Alex Smith 
>> wrote:
>>
>>> This means it can be reused for other Vulkan drivers. Also fix up a
>>> typo, need to search for '.' in the version string rather than ','.
>>>
>>> v2: Remove unneeded temporary version variable (Emil, Eric)
>>>
>>> Signed-off-by: Alex Smith 
>>> ---
>>>  src/amd/vulkan/radv_device.c | 24 +-
>>>  src/vulkan/Makefile.sources  |  1 +
>>>  src/vulkan/util/vk_util.c| 49 ++
>>> ++
>>>  src/vulkan/util/vk_util.h|  2 ++
>>>  4 files changed, 53 insertions(+), 23 deletions(-)
>>>  create mode 100644 src/vulkan/util/vk_util.c
>>>
>>> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
>>> index a812527..5fdb894 100644
>>> --- a/src/amd/vulkan/radv_device.c
>>> +++ b/src/amd/vulkan/radv_device.c
>>> @@ -574,28 +574,6 @@ void radv_GetPhysicalDeviceFeatures2KHR(
>>> return radv_GetPhysicalDeviceFeatures(physicalDevice,
>>> &pFeatures->features);
>>>  }
>>>
>>> -static uint32_t radv_get_driver_version()
>>> -{
>>> -   const char *minor_string = strchr(VERSION, '.');
>>> -   const char *patch_string = minor_string ? strchr(minor_string +
>>> 1, ','): NULL;
>>> -   int major = atoi(VERSION);
>>> -   int minor = minor_string ? atoi(minor_string + 1) : 0;
>>> -   int patch = patch_string ? atoi(patch_string + 1) : 0;
>>> -   if (strstr(VERSION, "devel")) {
>>> -   if (patch == 0) {
>>> -   patch = 99;
>>> -   if (minor == 0) {
>>> -   minor = 99;
>>> -   --major;
>>> -   } else
>>> -   --minor;
>>> -   } else
>>> -   --patch;
>>> -   }
>>> -   uint32_t version = VK_MAKE_VERSION(major, minor, patch);
>>> -   return version;
>>> -}
>>> -
>>>  void radv_GetPhysicalDeviceProperties(
>>> VkPhysicalDevicephysicalDevice,
>>> VkPhysicalDeviceProperties* pProperties)
>>> @@ -731,7 +709,7 @@ void radv_GetPhysicalDeviceProperties(
>>>
>>> *pProperties = (VkPhysicalDeviceProperties) {
>>> .apiVersion = VK_MAKE_VERSION(1, 0, 42),
>>> -   .driverVersion = radv_get_driver_version(),
>>> +   .driverVersion = vk_get_driver_version(),
>>> .vendorID = 0x1002,
>>> .deviceID = pdevice->rad_info.pci_id,
>>> .deviceType = pdevice->rad_info.has_dedicated_vram ?
>>> VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGR
>>> ATED_GPU,
>>> diff --git a/src/vulkan/Makefile.sources b/src/vulkan/Makefile.sources
>>> index 9962c1b..2cf7218 100644
>>> --- a/src/vulkan/Makefile.sources
>>> +++ b/src/vulkan/Makefile.sources
>>> @@ -17,6 +17,7 @@ VULKAN_WSI_X11_FILES := \
>>>
>>>  VULKAN_UTIL_FILES := \
>>> util/vk_alloc.h \
>>> +   util/vk_util.c \
>>> util/vk_util.h
>>>
>>>  VULKAN_UTIL_GENERATED_FILES := \
>>> diff --git a/src/vulkan/util/vk_util.c b/src/vulkan/util/vk_util.c
>>> new file mode 100644
>>> index 000..769e690
>>> --- /dev/null
>>> +++ b/src/vulkan/util/vk_util.c
>>> @@ -0,0 +1,49 @@
>>> +/*
>>> + * Copyright © 2016 Red Hat.
>>> + * Copyright © 2016 Bas Nieuwenhuizen
>>> + * Copyright © 2017 Intel Corporation
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person
>>> obtaining a
>>> + * copy of this software and associated documentation files (the
>>> "Software"),
>>> + * to deal in the Software without restriction, including without
>>> limitation
>>> + * the rights to use, copy, modify, merge, publish, distribute,
>>> sublicense,
>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>> + * Software is furnished to do so, subject to the following conditions:
>>> + *
>>> + * The above copyright notice and this permission notice (including the
>>> next
>>> + * paragraph) shall be included in all copies or substantial portions
>>> of the
>>> + * Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>> EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>>> MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT
>>> SHALL
>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>>> OTHER
>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>>> ARISING
>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>>> DEALINGS
>>> + * IN THE SOFTWARE.
>>> + */
>>> +
>>> +#include 
>>> +#include 
>>>

[Mesa-dev] [PATCH 5/7] i965: Improve same-buffer restriction for imports

[Daniel Stone]

Intel hardware requires that all planes of an image come from the same
buffer, which is currently implemented by testing that all FDs are
numerically the same.

However, when going through a winsys (e.g.) or anything which transits
FDs individually, the FDs may be different even if the underlying buffer
is the same.

Instead of checking the FDs for equality, we must check if they actually
point to the same buffer (Jason).

Signed-off-by: Daniel Stone 
Signed-off-by: Varad Gautam 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 18 +-
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 89e911a357..05ac784fa6 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -841,11 +841,6 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
if (fds == NULL || num_fds < 1)
   return NULL;
 
-   /* We only support all planes from the same bo */
-   for (i = 0; i < num_fds; i++)
-  if (fds[0] != fds[i])
- return NULL;
-
f = intel_image_format_lookup(fourcc);
if (f == NULL)
   return NULL;
@@ -872,6 +867,19 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
   return NULL;
}
 
+   /* We only support all planes from the same bo.
+* brw_bo_gem_create_from_prime() should return the same pointer for all
+* fds received here */
+   for (i = 1; i < num_fds; i++) {
+  struct brw_bo *aux = brw_bo_gem_create_from_prime(screen->bufmgr, 
fds[i]);
+  brw_bo_unreference(aux);
+  if (aux != image->bo) {
+ brw_bo_unreference(image->bo);
+ free(image);
+ return NULL;
+  }
+   }
+
image->modifier = tiling_to_modifier(image->bo->tiling_mode);
tiled_height = get_tiled_height(image->modifier, height);
 
-- 
2.13.0

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[Mesa-dev] [PATCH 7/7] i965: Add format/modifier advertising

[Daniel Stone]

From: Varad Gautam 

v2: Rebase and reuse tiling/modifier map. (Daniel Stone)
v3: bump DRIimageExtension to version 15, fill external_only array.

Signed-off-by: Varad Gautam 
Signed-off-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 76 ++--
 1 file changed, 72 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index e7d2af7852..10835f991a 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -294,14 +294,15 @@ static struct intel_image_format intel_image_formats[] = {
 static const struct {
uint32_t tiling;
uint64_t modifier;
+   unsigned since_gen;
unsigned height_align;
 } tiling_modifier_map[] = {
{ .tiling = I915_TILING_NONE, .modifier = DRM_FORMAT_MOD_LINEAR,
- .height_align = 1 },
+ .since_gen = 1, .height_align = 1 },
{ .tiling = I915_TILING_X, .modifier = I915_FORMAT_MOD_X_TILED,
- .height_align = 8 },
+ .since_gen = 1, .height_align = 8 },
{ .tiling = I915_TILING_Y, .modifier = I915_FORMAT_MOD_Y_TILED,
- .height_align = 32 },
+ .since_gen = 9, .height_align = 32 },
 };
 
 static bool
@@ -1014,6 +1015,71 @@ intel_create_image_from_dma_bufs(__DRIscreen *dri_screen,
 loaderPrivate);
 }
 
+static GLboolean
+intel_query_dma_buf_formats(__DRIscreen *screen, int max,
+int *formats, int *count)
+{
+   int i, j = 0;
+
+   if (max == 0) {
+  *count = ARRAY_SIZE(intel_image_formats) - 1; /* not SARGB */
+  return true;
+   }
+
+   for (i = 0; i < (ARRAY_SIZE(intel_image_formats)) && j < max; i++) {
+ if (intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SARGB)
+   continue;
+ formats[j++] = intel_image_formats[i].fourcc;
+   }
+
+   *count = j;
+   return true;
+}
+
+static GLboolean
+intel_query_dma_buf_modifiers(__DRIscreen *_screen, int fourcc, int max,
+  uint64_t *modifiers,
+  unsigned int *external_only,
+  int *count)
+{
+   struct intel_screen *screen = _screen->driverPrivate;
+   struct intel_image_format *f;
+   int num_mods = 0, i;
+
+   f = intel_image_format_lookup(fourcc);
+   if (f == NULL)
+  return false;
+
+   for (i = 0; i < ARRAY_SIZE(tiling_modifier_map); i++) {
+  if (screen->devinfo.gen < tiling_modifier_map[i].since_gen)
+ continue;
+
+  num_mods++;
+  if (max == 0)
+ continue;
+
+  modifiers[num_mods - 1] = tiling_modifier_map[i].modifier;
+  if (num_mods >= max)
+break;
+   }
+
+   if (external_only != NULL) {
+  for (i = 0; i < num_mods && i < max; i++) {
+ if (f->components == __DRI_IMAGE_COMPONENTS_Y_U_V ||
+ f->components == __DRI_IMAGE_COMPONENTS_Y_UV ||
+ f->components == __DRI_IMAGE_COMPONENTS_Y_XUXV) {
+external_only[i] = GL_TRUE;
+ }
+ else {
+external_only[i] = GL_FALSE;
+ }
+  }
+   }
+
+   *count = num_mods;
+   return true;
+}
+
 static __DRIimage *
 intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate)
 {
@@ -1061,7 +1127,7 @@ intel_from_planar(__DRIimage *parent, int plane, void 
*loaderPrivate)
 }
 
 static const __DRIimageExtension intelImageExtension = {
-.base = { __DRI_IMAGE, 14 },
+.base = { __DRI_IMAGE, 15 },
 
 .createImageFromName= intel_create_image_from_name,
 .createImageFromRenderbuffer= intel_create_image_from_renderbuffer,
@@ -1081,6 +1147,8 @@ static const __DRIimageExtension intelImageExtension = {
 .unmapImage = NULL,
 .createImageWithModifiers   = intel_create_image_with_modifiers,
 .createImageFromDmaBufs2= intel_create_image_from_dma_bufs2,
+.queryDmaBufFormats = intel_query_dma_buf_formats,
+.queryDmaBufModifiers   = intel_query_dma_buf_modifiers,
 };
 
 static uint64_t
-- 
2.13.0

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[Mesa-dev] [PATCH 4/7] i965: Allocate tile aligned height

[Daniel Stone]

From: Ben Widawsky 

This patch shouldn't actually do anything because the libdrm function
should already do this alignment. However, it preps us for a future
patch where we add in the CCS AUX size, and in the process it serves as
a good place to find bisectable issues if libdrm or kernel does
something incorrectly.

v2: Do proper alignment for X tiling, and make sure non-tiled case is
handled (Jason)
v3: Rebase (Daniel)

Cc: Jason Ekstrand 
Signed-off-by: Ben Widawsky 
Acked-by: Daniel Stone 
Signed-off-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 31 ++-
 1 file changed, 26 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 65a60bfefe..89e911a357 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -294,10 +294,14 @@ static struct intel_image_format intel_image_formats[] = {
 static const struct {
uint32_t tiling;
uint64_t modifier;
+   unsigned height_align;
 } tiling_modifier_map[] = {
-   { .tiling = I915_TILING_NONE, .modifier = DRM_FORMAT_MOD_LINEAR },
-   { .tiling = I915_TILING_X, .modifier = I915_FORMAT_MOD_X_TILED },
-   { .tiling = I915_TILING_Y, .modifier = I915_FORMAT_MOD_Y_TILED },
+   { .tiling = I915_TILING_NONE, .modifier = DRM_FORMAT_MOD_LINEAR,
+ .height_align = 1 },
+   { .tiling = I915_TILING_X, .modifier = I915_FORMAT_MOD_X_TILED,
+ .height_align = 8 },
+   { .tiling = I915_TILING_Y, .modifier = I915_FORMAT_MOD_Y_TILED,
+ .height_align = 32 },
 };
 
 static uint32_t
@@ -326,6 +330,19 @@ tiling_to_modifier(uint32_t tiling)
unreachable("tiling_to_modifier received unknown tiling mode");
 }
 
+static unsigned
+get_tiled_height(uint64_t modifier, unsigned height)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(tiling_modifier_map); i++) {
+  if (tiling_modifier_map[i].modifier == modifier)
+ return ALIGN(height, tiling_modifier_map[i].height_align);
+   }
+
+   unreachable("get_tiled_height received unknown tiling mode");
+}
+
 static void
 intel_image_warn_if_unaligned(__DRIimage *image, const char *func)
 {
@@ -609,6 +626,7 @@ intel_create_image_common(__DRIscreen *dri_screen,
struct intel_screen *screen = dri_screen->driverPrivate;
uint32_t tiling;
uint64_t modifier = DRM_FORMAT_MOD_INVALID;
+   unsigned tiled_height;
int cpp;
 
/* Callers of this may specify a modifier, or a dri usage, but not both. The
@@ -640,6 +658,7 @@ intel_create_image_common(__DRIscreen *dri_screen,
   }
}
tiling = modifier_to_tiling(modifier);
+   tiled_height = get_tiled_height(modifier, height);
 
image = intel_allocate_image(screen, format, loaderPrivate);
if (image == NULL)
@@ -647,7 +666,7 @@ intel_create_image_common(__DRIscreen *dri_screen,
 
cpp = _mesa_get_format_bytes(image->format);
image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image",
-  width, height, cpp, tiling,
+  width, tiled_height, cpp, tiling,
   &image->pitch, 0);
if (image->bo == NULL) {
   free(image);
@@ -816,6 +835,7 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
struct intel_screen *screen = dri_screen->driverPrivate;
struct intel_image_format *f;
__DRIimage *image;
+   unsigned tiled_height;
int i, index;
 
if (fds == NULL || num_fds < 1)
@@ -853,6 +873,7 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
}
 
image->modifier = tiling_to_modifier(image->bo->tiling_mode);
+   tiled_height = get_tiled_height(image->modifier, height);
 
int size = 0;
for (i = 0; i < f->nplanes; i++) {
@@ -860,7 +881,7 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
   image->offsets[index] = offsets[index];
   image->strides[index] = strides[index];
 
-  const int plane_height = height >> f->planes[i].height_shift;
+  const int plane_height = tiled_height >> f->planes[i].height_shift;
   const int end = offsets[index] + plane_height * strides[index];
   if (size < end)
  size = end;
-- 
2.13.0

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[Mesa-dev] [PATCH 1/7] egl/dri2: Avoid sign extension when building modifier

[Daniel Stone]

Since the EGL attributes are signed integers, a straight OR would
also perform sign extension,

Fixes: 6f10e7c37a ("egl/dri2: Create EGLImages with dmabuf modifiers")
Cc: Varad Gautam 
Signed-off-by: Daniel Stone 
---
 src/egl/drivers/dri2/egl_dri2.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index d31a0bf8e0..7175e827c9 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -2278,9 +2278,8 @@ dri2_create_image_dma_buf(_EGLDisplay *disp, _EGLContext 
*ctx,
 * will be present in attrs.DMABufPlaneModifiersLo[0] and
 * attrs.DMABufPlaneModifiersHi[0] */
if (attrs.DMABufPlaneModifiersLo[0].IsPresent) {
-  modifier =
- ((uint64_t) attrs.DMABufPlaneModifiersHi[0].Value << 32) |
- attrs.DMABufPlaneModifiersLo[0].Value;
+  modifier = (uint64_t) attrs.DMABufPlaneModifiersHi[0].Value << 32;
+  modifier |= (uint64_t) (attrs.DMABufPlaneModifiersLo[0].Value & 
0x);
   has_modifier = true;
} else {
   modifier = DRM_FORMAT_MOD_INVALID;
-- 
2.13.0

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[Mesa-dev] [PATCH 2/7] i965: Invert image modifier/tiling inference

[Daniel Stone]

When allocating images, we record a tiling mode and then work backwards
to infer the modifier. Unfortunately this is the wrong way around, since
it is a one:many mapping (e.g. TILING_Y can be plain Y-tiling, or
Y-tiling with CCS).

Invert the mapping, so we record a modifier first and then map this to a
tiling mode.

Signed-off-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 35 
 1 file changed, 18 insertions(+), 17 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 22f6d9af03..ceb1f0d480 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -608,6 +608,7 @@ intel_create_image_common(__DRIscreen *dri_screen,
__DRIimage *image;
struct intel_screen *screen = dri_screen->driverPrivate;
uint32_t tiling;
+   uint64_t modifier = DRM_FORMAT_MOD_INVALID;
int cpp;
 
/* Callers of this may specify a modifier, or a dri usage, but not both. The
@@ -616,29 +617,29 @@ intel_create_image_common(__DRIscreen *dri_screen,
 */
assert(!(use && count));
 
-   uint64_t modifier = select_best_modifier(&screen->devinfo, modifiers, 
count);
-   if (modifier == DRM_FORMAT_MOD_INVALID) {
-  /* User requested specific modifiers, none of which work */
-  if (modifiers)
- return NULL;
-
-  /* Historically, X-tiled was the default, and so lack of modifier means
-   * X-tiled.
-   */
-  tiling = I915_TILING_X;
-   } else {
-  /* select_best_modifier has found a modifier we support */
-  tiling = modifier_to_tiling(modifier);
-   }
-
if (use & __DRI_IMAGE_USE_CURSOR) {
   if (width != 64 || height != 64)
 return NULL;
-  tiling = I915_TILING_NONE;
+  modifier = DRM_FORMAT_MOD_LINEAR;
}
 
if (use & __DRI_IMAGE_USE_LINEAR)
-  tiling = I915_TILING_NONE;
+  modifier = DRM_FORMAT_MOD_LINEAR;
+
+   if (modifier == DRM_FORMAT_MOD_INVALID) {
+  if (modifiers) {
+ /* User requested specific modifiers */
+ modifier = select_best_modifier(&screen->devinfo, modifiers, count);
+ if (modifier == DRM_FORMAT_MOD_INVALID)
+return NULL;
+  } else {
+ /* Historically, X-tiled was the default, and so lack of modifier 
means
+  * X-tiled.
+  */
+ modifier = I915_FORMAT_MOD_X_TILED;
+  }
+   }
+   tiling = modifier_to_tiling(modifier);
 
image = intel_allocate_image(screen, format, loaderPrivate);
if (image == NULL)
-- 
2.13.0

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[Mesa-dev] [PATCH 6/7] i965: Support dmabuf import with modifiers

[Daniel Stone]

From: Varad Gautam 

Add support for createImageFromDmaBufs2, adding a modifier to the
original, and allow importing CCS resources with auxiliary data from
dmabufs.

v2: avoid DRIimageExtension version bump, pass single modifier to
createImageFromDmaBufs2.

Signed-off-by: Varad Gautam 
Signed-off-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 94 ++--
 1 file changed, 76 insertions(+), 18 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 05ac784fa6..e7d2af7852 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -304,6 +304,19 @@ static const struct {
  .height_align = 32 },
 };
 
+static bool
+modifier_is_supported(uint64_t modifier)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(tiling_modifier_map); i++) {
+  if (tiling_modifier_map[i].modifier == modifier)
+ return true;
+   }
+
+   return false;
+}
+
 static uint32_t
 modifier_to_tiling(uint64_t modifier)
 {
@@ -827,10 +840,11 @@ intel_create_image_from_names(__DRIscreen *dri_screen,
 }
 
 static __DRIimage *
-intel_create_image_from_fds(__DRIscreen *dri_screen,
-int width, int height, int fourcc,
-int *fds, int num_fds, int *strides, int *offsets,
-void *loaderPrivate)
+intel_create_image_from_fds_common(__DRIscreen *dri_screen,
+   int width, int height, int fourcc,
+   uint64_t modifier, int *fds, int num_fds,
+   int *strides, int *offsets,
+   void *loaderPrivate)
 {
struct intel_screen *screen = dri_screen->driverPrivate;
struct intel_image_format *f;
@@ -845,6 +859,9 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
if (f == NULL)
   return NULL;
 
+   if (modifier != DRM_FORMAT_MOD_INVALID && !modifier_is_supported(modifier))
+ return NULL;
+
if (f->nplanes == 1)
   image = intel_allocate_image(screen, f->planes[0].dri_format,
loaderPrivate);
@@ -880,7 +897,10 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
   }
}
 
-   image->modifier = tiling_to_modifier(image->bo->tiling_mode);
+   if (modifier != DRM_FORMAT_MOD_INVALID)
+  image->modifier = modifier;
+   else
+  image->modifier = tiling_to_modifier(image->bo->tiling_mode);
tiled_height = get_tiled_height(image->modifier, height);
 
int size = 0;
@@ -914,16 +934,29 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
 }
 
 static __DRIimage *
-intel_create_image_from_dma_bufs(__DRIscreen *dri_screen,
- int width, int height, int fourcc,
- int *fds, int num_fds,
- int *strides, int *offsets,
- enum __DRIYUVColorSpace yuv_color_space,
- enum __DRISampleRange sample_range,
- enum __DRIChromaSiting horizontal_siting,
- enum __DRIChromaSiting vertical_siting,
- unsigned *error,
- void *loaderPrivate)
+intel_create_image_from_fds(__DRIscreen *dri_screen,
+int width, int height, int fourcc,
+int *fds, int num_fds, int *strides, int *offsets,
+void *loaderPrivate)
+{
+   return intel_create_image_from_fds_common(dri_screen, width, height, fourcc,
+ DRM_FORMAT_MOD_INVALID,
+ fds, num_fds, strides, offsets,
+ loaderPrivate);
+}
+
+static __DRIimage *
+intel_create_image_from_dma_bufs2(__DRIscreen *dri_screen,
+  int width, int height,
+  int fourcc, uint64_t modifier,
+  int *fds, int num_fds,
+  int *strides, int *offsets,
+  enum __DRIYUVColorSpace yuv_color_space,
+  enum __DRISampleRange sample_range,
+  enum __DRIChromaSiting horizontal_siting,
+  enum __DRIChromaSiting vertical_siting,
+  unsigned *error,
+  void *loaderPrivate)
 {
__DRIimage *image;
struct intel_image_format *f = intel_image_format_lookup(fourcc);
@@ -933,9 +966,10 @@ intel_create_image_from_dma_bufs(__DRIscreen *dri_screen,
   return NULL;
}
 
-   image = intel_create_image_from_fds(dri_screen, width, height, fourcc, fds,
-   num_fds, strides, offsets,
- 

[Mesa-dev] [PATCH v15 0/7] i965 modifier import and advertisement

[Daniel Stone]

Hi,
With the initial modifier enablement patches being merged, and Jason's
comments about doing a lot of work in the vicinity of CCS with blorp/ISL,
I'm cleaving this patch series into 3.

Varad is taking over the Gallium/Freedreno parts as an independent
series, since there are no longer any shared parts between the two.

This series is enough to fully support
EGL_EXT_image_dma_buf_import_modifiers on i965, with the 'classic'
single-plane tiling modes: linear, X, and Y0. I've left out support for
Yf, CCS, and other exotic modes. Tested with Weston and its
simple-dmabuf-drm sample client.

I've rebased the last set of CCS patches on top of this, and will send
those out momentarily, but am going to park them until Jason's finished
blowing up i965 miptree/resolve handling.

Cheers,
Daniel

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[Mesa-dev] [PATCH 3/7] i965: Move fallback size assignment out of bufmgr

[Daniel Stone]

The bufmgr took a mandatory size argument, which would only be used if
the kernel size query failed, i.e. an older kernel. It didn't actually
check that the BO size was sufficient for use.

Pull the check out of the bufmgr, and actually check that the BO is
sufficiently-sized for our import one level up. This also resolves a
chicken/egg we have when importing bufers without explicit modifiers,
namely that we need the tiling mode to calculate the size, but we need
the BO imported to query the tiling mode.

Signed-off-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/brw_bufmgr.c   |  5 +
 src/mesa/drivers/dri/i965/brw_bufmgr.h   |  2 +-
 src/mesa/drivers/dri/i965/intel_screen.c | 19 +++
 3 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 2f17934700..b74fa9708b 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -1013,8 +1013,7 @@ brw_bo_get_tiling(struct brw_bo *bo, uint32_t 
*tiling_mode,
 }
 
 struct brw_bo *
-brw_bo_gem_create_from_prime(struct brw_bufmgr *bufmgr, int prime_fd,
- int size)
+brw_bo_gem_create_from_prime(struct brw_bufmgr *bufmgr, int prime_fd)
 {
int ret;
uint32_t handle;
@@ -1055,8 +1054,6 @@ brw_bo_gem_create_from_prime(struct brw_bufmgr *bufmgr, 
int prime_fd,
ret = lseek(prime_fd, 0, SEEK_END);
if (ret != -1)
   bo->size = ret;
-   else
-  bo->size = size;
 
bo->bufmgr = bufmgr;
 
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 56ec206d30..f708c30f05 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -272,7 +272,7 @@ void brw_destroy_hw_context(struct brw_bufmgr *bufmgr, 
uint32_t ctx_id);
 
 int brw_bo_gem_export_to_prime(struct brw_bo *bo, int *prime_fd);
 struct brw_bo *brw_bo_gem_create_from_prime(struct brw_bufmgr *bufmgr,
-int prime_fd, int size);
+int prime_fd);
 
 int brw_reg_read(struct brw_bufmgr *bufmgr, uint32_t offset,
  uint64_t *result);
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index ceb1f0d480..65a60bfefe 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -845,6 +845,15 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
image->pitch = strides[0];
 
image->planar_format = f;
+
+   image->bo = brw_bo_gem_create_from_prime(screen->bufmgr, fds[0]);
+   if (image->bo == NULL) {
+  free(image);
+  return NULL;
+   }
+
+   image->modifier = tiling_to_modifier(image->bo->tiling_mode);
+
int size = 0;
for (i = 0; i < f->nplanes; i++) {
   index = f->planes[i].buffer_index;
@@ -857,13 +866,15 @@ intel_create_image_from_fds(__DRIscreen *dri_screen,
  size = end;
}
 
-   image->bo = brw_bo_gem_create_from_prime(screen->bufmgr,
-  fds[0], size);
-   if (image->bo == NULL) {
+   /* Check that the requested image actually fits within the BO. 'size'
+* is already relative to the offsets, so we don't need to add that. */
+   if (image->bo->size == 0) {
+  image->bo->size = size;
+   } else if (size > image->bo->size) {
+  brw_bo_unreference(image->bo);
   free(image);
   return NULL;
}
-   image->modifier = tiling_to_modifier(image->bo->tiling_mode);
 
if (f->nplanes == 1) {
   image->offset = image->offsets[0];
-- 
2.13.0

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[Mesa-dev] [PATCH v15 00/16] i965: CCS support

[Daniel Stone]

Hi,
Building on top of the previous v15 to add support for buffers with
modifiers to i965, this adds CCS support.

I'm parking this until Jason has finished his blorp/etc work, so this
should be purely informational until then. It also depends on a kernel
series which hasn't got any review yet.

Cheers,
Daniel

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[Mesa-dev] [PATCH v15 04/16] i965: Restructure CCS disabling

[Daniel Stone]

From: Ben Widawsky 

Make the code only disable CCS when it has to, unlike before where it
disabled CCS and enabled it when it could. This is much more inline with
how it should work in a few patches, where we have fewer restrictions as
to when we disable CCS.

v2: Change CCS disabling to an assertion in layout creation (Topi)

v3: Make sure to disable aux buffers when creating a miptree from a BO.
Today, this only happens via intel_update_image_buffer. At the end of
the modifier series, we should be able to undo this. Some fixes from
Topi in here as well.

v4: Split no_aux into a separate patch (Jason)

Cc: "Pohjolainen, Topi" 
Signed-off-by: Ben Widawsky 
Signed-off-by: Daniel Stone 
Cc: Jason Ekstrand 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index a48ebc7f5e..2b6beab83f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -329,7 +329,6 @@ intel_miptree_create_layout(struct brw_context *brw,
mt->logical_depth0 = depth0;
mt->aux_disable = (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) != 0 ?
   INTEL_AUX_DISABLE_ALL : INTEL_AUX_DISABLE_NONE;
-   mt->aux_disable |= INTEL_AUX_DISABLE_CCS;
mt->is_scanout = (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT) != 0;
exec_list_make_empty(&mt->hiz_map);
exec_list_make_empty(&mt->color_resolve_map);
@@ -522,6 +521,8 @@ intel_miptree_create_layout(struct brw_context *brw,
} else if (brw->gen >= 9 && num_samples > 1) {
   layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
} else {
+  mt->aux_disable |= INTEL_AUX_DISABLE_CCS;
+
   const UNUSED bool is_lossless_compressed_aux =
  brw->gen >= 9 && num_samples == 1 &&
  mt->format == MESA_FORMAT_R_UINT32;
@@ -697,7 +698,6 @@ intel_miptree_create(struct brw_context *brw,
 */
if (intel_tiling_supports_non_msrt_mcs(brw, mt->tiling) &&
intel_miptree_supports_non_msrt_fast_clear(brw, mt)) {
-  mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS;
   assert(brw->gen < 8 || mt->halign == 16 || num_samples <= 1);
 
   /* On Gen9+ clients are not currently capable of consuming compressed
@@ -711,8 +711,11 @@ intel_miptree_create(struct brw_context *brw,
  intel_miptree_supports_lossless_compressed(brw, mt);
 
   if (is_lossless_compressed) {
+ assert(!(mt->aux_disable & INTEL_AUX_DISABLE_CCS));
  intel_miptree_alloc_non_msrt_mcs(brw, mt, is_lossless_compressed);
   }
+   } else {
+  mt->aux_disable |= INTEL_AUX_DISABLE_CCS;
}
 
return mt;
@@ -804,7 +807,7 @@ create_ccs_buf_for_image(struct brw_context *intel,
mt->mcs_buf->qpitch = isl_surf_get_array_pitch_sa_rows(&temp_ccs_surf);
 
intel_miptree_init_mcs(intel, mt, 0);
-   mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS;
+   assert(!(mt->aux_disable & INTEL_AUX_DISABLE_CCS));
mt->msaa_layout = INTEL_MSAA_LAYOUT_CMS;
 
return true;
@@ -900,14 +903,14 @@ intel_update_winsys_renderbuffer_miptree(struct 
brw_context *intel,
if (!singlesample_mt)
   goto fail;
 
-   /* If this miptree is capable of supporting fast color clears, set
-* mcs_state appropriately to ensure that fast clears will occur.
+   /* If this miptree is not capable of supporting fast color clears, flag
+* mcs allocation disabled.
 * Allocation of the MCS miptree will be deferred until the first fast
 * clear actually occurs.
 */
-   if (intel_tiling_supports_non_msrt_mcs(intel, singlesample_mt->tiling) &&
-   intel_miptree_supports_non_msrt_fast_clear(intel, singlesample_mt)) {
-  singlesample_mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS;
+   if (!intel_tiling_supports_non_msrt_mcs(intel, singlesample_mt->tiling) ||
+   !intel_miptree_supports_non_msrt_fast_clear(intel, singlesample_mt)) {
+  singlesample_mt->aux_disable |= INTEL_AUX_DISABLE_CCS;
}
 
if (num_samples == 0) {
-- 
2.13.0

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[Mesa-dev] [PATCH v15 02/16] i965/miptree: Add a helper function for image creation

[Daniel Stone]

From: Ben Widawsky 

This provides a common function or creating miptrees when there is an
existing DRIimage to use. That provides an easy way to add CCS
allocation.

v2: Make the new function assume there are always no layout flags. This
will be adjusted later.

Signed-off-by: Ben Widawsky 
Acked-by: Daniel Stone 
Signed-off-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/intel_fbo.c | 17 -
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 25 -
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 10 ++
 src/mesa/drivers/dri/i965/intel_tex_image.c   | 17 -
 4 files changed, 50 insertions(+), 19 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c 
b/src/mesa/drivers/dri/i965/intel_fbo.c
index a24ddd0d88..48c0529ffc 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -362,15 +362,14 @@ intel_image_target_renderbuffer_storage(struct gl_context 
*ctx,
 * buffer's content to the main buffer nor for invalidating the aux buffer's
 * content.
 */
-   irb->mt = intel_miptree_create_for_bo(brw,
- image->bo,
- image->format,
- image->offset,
- image->width,
- image->height,
- 1,
- image->pitch,
- MIPTREE_LAYOUT_DISABLE_AUX);
+   irb->mt = intel_miptree_create_for_image(brw,
+image,
+image->format,
+image->offset,
+image->width,
+image->height,
+image->pitch,
+0);
if (!irb->mt)
   return;
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index b77b7fdadd..e7c511d229 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -24,7 +24,6 @@
  */
 
 #include 
-#include 
 
 #include "intel_batchbuffer.h"
 #include "intel_mipmap_tree.h"
@@ -32,6 +31,7 @@
 #include "intel_tex.h"
 #include "intel_blit.h"
 #include "intel_fbo.h"
+#include "intel_image.h"
 
 #include "brw_blorp.h"
 #include "brw_context.h"
@@ -766,6 +766,29 @@ intel_miptree_create_for_bo(struct brw_context *brw,
return mt;
 }
 
+struct intel_mipmap_tree *
+intel_miptree_create_for_image(struct brw_context *intel,
+   __DRIimage *image,
+   mesa_format format,
+   uint32_t offset,
+   uint32_t width,
+   uint32_t height,
+   uint32_t pitch,
+   uint32_t layout_flags)
+{
+   assert(layout_flags == 0);
+   layout_flags = MIPTREE_LAYOUT_DISABLE_AUX;
+   return intel_miptree_create_for_bo(intel,
+  image->bo,
+  format,
+  offset,
+  width,
+  height,
+  1,
+  pitch,
+  layout_flags);
+}
+
 /**
  * For a singlesample renderbuffer, this simply wraps the given BO with a
  * miptree.
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 6096cabbdf..654ef3c787 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -742,6 +742,16 @@ intel_miptree_create_for_bo(struct brw_context *brw,
 int pitch,
 uint32_t layout_flags);
 
+struct intel_mipmap_tree *
+intel_miptree_create_for_image(struct brw_context *intel,
+   __DRIimage *image,
+   mesa_format format,
+   uint32_t offset,
+   uint32_t width,
+   uint32_t height,
+   uint32_t pitch,
+   uint32_t layout_flags);
+
 void
 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
  struct intel_renderbuffer *irb,
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c 
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 649b3907d1..1089cae1a0 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -221,1

[Mesa-dev] [PATCH v15 13/16] i965: Use partial resolves for CCS buffers being scanned out

[Daniel Stone]

From: Ben Widawsky 

On Gen9 hardware, the display engine is able to scanout a compressed
framebuffer by providing an offset to auxiliary compression information.
Unfortunately, the hardware is incapable of doing the same thing for the
fast clear color.

To mitigate this, the hardware introduced a new resolve type called a
partial resolve. The partial resolve will only do a resolve of the fast
clear color and leave the rest of the compressed data alone.

This patch enables using this resolve type for cases where the
framebuffer will be passed along to the kernel for display.

v2: Add early exit from intel_miptree_make_shareable() when it's
scanout.
v3: Add another assert for mt->mcs_buf->offset. (Topi)

Signed-off-by: Ben Widawsky 
Acked-by: Daniel Stone 
Reviewed-by: Topi Pohjolainen 
Signed-off-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/brw_context.c   |  3 ++-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 10 +-
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 5e722cd6da..1b50cff338 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1381,7 +1381,8 @@ intel_resolve_for_dri2_flush(struct brw_context *brw,
   if (rb->mt->num_samples <= 1) {
  assert(rb->mt_layer == 0 && rb->mt_level == 0 &&
 rb->layer_count == 1);
- intel_miptree_resolve_color(brw, rb->mt, 0, 0, 1, 0);
+ intel_miptree_resolve_color(brw, rb->mt, 0, 0, 1,
+ INTEL_RESOLVE_HINT_CLEAR_COLOR);
   } else {
  intel_renderbuffer_downsample(brw, rb);
   }
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 267e46a284..79429a8c86 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2325,7 +2325,15 @@ intel_miptree_make_shareable(struct brw_context *brw,
assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE || mt->num_samples <= 1);
 
if (mt->mcs_buf) {
-  intel_miptree_all_slices_resolve_color(brw, mt, 0);
+  intel_miptree_all_slices_resolve_color(brw, mt, mt->is_scanout ?
+ INTEL_RESOLVE_HINT_CLEAR_COLOR :
+ INTEL_RESOLVE_HINT_FULL);
+  if (mt->is_scanout) {
+ assert(!mt->hiz_buf);
+ assert(mt->mcs_buf->offset);
+ return;
+  }
+
   mt->aux_disable |= (INTEL_AUX_DISABLE_CCS | INTEL_AUX_DISABLE_MCS);
   brw_bo_unreference(mt->mcs_buf->bo);
   free(mt->mcs_buf);
-- 
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[Mesa-dev] [PATCH v15 01/16] i965: Support images with offset aux buffers

[Daniel Stone]

From: Ben Widawsky 

Previously our aux buffers (MCS, and HiZ) never had an offset because
they were in their own buffer object. When using the CCS lossless
compression feature, it's desirable to store the data at an offset from
the main framebuffer, ie. share a buffer object. This patch just makes
having an aux offset possible.

Signed-off-by: Ben Widawsky 
Acked-by: Daniel Stone 
Signed-off-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/intel_image.h  | 3 +++
 src/mesa/drivers/dri/i965/intel_screen.c | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_image.h 
b/src/mesa/drivers/dri/i965/intel_image.h
index cf0610540f..45f1a51827 100644
--- a/src/mesa/drivers/dri/i965/intel_image.h
+++ b/src/mesa/drivers/dri/i965/intel_image.h
@@ -92,6 +92,9 @@ struct __DRIimageRec {
/** The image was created with EGL_EXT_image_dma_buf_import. */
bool dma_buf_imported;
 
+   /** The image has some ancillary data associated with it at offset. */
+   uint32_t aux_offset;
+
/**
 * Provided by EGL_EXT_image_dma_buf_import.
 * \{
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 10835f991a..9bc0895f39 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -690,6 +690,8 @@ intel_create_image_common(__DRIscreen *dri_screen,
image->height = height;
image->modifier = modifier;
 
+   image->aux_offset = 0; /* y_tiled_height * pitch */
+
return image;
 }
 
-- 
2.13.0

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[Mesa-dev] [PATCH v15 11/16] i965: Plumb resolve hints from miptrees to blorp

[Daniel Stone]

From: Ben Widawsky 

Signed-off-by: Ben Widawsky 
Acked-by: Daniel Stone 
Reviewed-by: Topi Pohjolainen 
Signed-off-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 3 ++-
 src/mesa/drivers/dri/i965/brw_blorp.h | 3 ++-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 ++--
 3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 126a77862a..36d25a1706 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -927,7 +927,8 @@ brw_blorp_clear_color(struct brw_context *brw, struct 
gl_framebuffer *fb,
 
 void
 brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt,
-unsigned level, unsigned layer)
+unsigned level, unsigned layer,
+enum intel_resolve_hint hint)
 {
DBG("%s to mt %p level %u layer %u\n", __FUNCTION__, mt, level, layer);
 
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 8743d963ab..87ec1ffba7 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -66,7 +66,8 @@ brw_blorp_clear_color(struct brw_context *brw, struct 
gl_framebuffer *fb,
 void
 brw_blorp_resolve_color(struct brw_context *brw,
 struct intel_mipmap_tree *mt,
-unsigned level, unsigned layer);
+unsigned level, unsigned layer,
+enum intel_resolve_hint hint);
 
 void
 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 44bf2885e5..267e46a284 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2277,7 +2277,7 @@ intel_miptree_resolve_color(struct brw_context *brw,
   if (item) {
  assert(item->fast_clear_state != INTEL_FAST_CLEAR_STATE_RESOLVED);
 
- brw_blorp_resolve_color(brw, mt, level, start_layer);
+ brw_blorp_resolve_color(brw, mt, level, start_layer, hint);
  intel_resolve_map_remove(item);
  resolved = true;
   }
@@ -2298,7 +2298,7 @@ intel_miptree_all_slices_resolve_color(struct brw_context 
*brw,
&mt->color_resolve_map) {
   assert(map->fast_clear_state != INTEL_FAST_CLEAR_STATE_RESOLVED);
 
-  brw_blorp_resolve_color(brw, mt, map->level, map->layer);
+  brw_blorp_resolve_color(brw, mt, map->level, map->layer, hint);
   intel_resolve_map_remove(map);
}
 }
-- 
2.13.0

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[Mesa-dev] [PATCH v15 03/16] i965/miptree: Allocate mcs_buf for an image's CCS_E

[Daniel Stone]

From: Ben Widawsky 

This code will disable actually creating these buffers for the scanout,
but it puts the allocation in place.

Primarily this patch is split out for review, it can be squashed in
later if preferred.

v2:
assert(mt->offset == 0) in ccs creation (as requested by Topi)
Remove bogus is_scanout check in miptree_release

v3:
Remove is_scanout assert in intel_miptree_create. It doesn't work with
latest codebase - not sure it ever should have worked.

v4:
assert(mt->last_level == 0) and assert(mt->first_level == 0) in ccs setup
(Topi)

Signed-off-by: Ben Widawsky 
Acked-by: Daniel Stone 
Reviewed-by: Topi Pohjolainen 
Signed-off-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 92 +++
 1 file changed, 81 insertions(+), 11 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index e7c511d229..a48ebc7f5e 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -58,6 +58,11 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
 struct intel_mipmap_tree *mt,
 GLuint num_samples);
 
+static void
+intel_miptree_init_mcs(struct brw_context *brw,
+   struct intel_mipmap_tree *mt,
+   int init_value);
+
 /**
  * Determine which MSAA layout should be used by the MSAA surface being
  * created, based on the chip generation and the surface type.
@@ -766,6 +771,45 @@ intel_miptree_create_for_bo(struct brw_context *brw,
return mt;
 }
 
+static bool
+create_ccs_buf_for_image(struct brw_context *intel,
+ __DRIimage *image,
+ struct intel_mipmap_tree *mt)
+{
+
+   struct isl_surf temp_main_surf;
+   struct isl_surf temp_ccs_surf;
+
+   /* There isn't anything specifically wrong with there being an offset, in
+* which case, the CCS miptree's offset should be mt->offset +
+* image->aux_offset. However, the code today only will have an offset when
+* this miptree is pointing to a slice from another miptree, and in that 
case
+* we'd need to offset within the AUX CCS buffer properly. It's questionable
+* whether our code handles that case properly, and since it can never 
happen
+* for scanout, just use the assertion to prevent it.
+*/
+   assert(mt->offset == 0);
+
+   intel_miptree_get_isl_surf(intel, mt, &temp_main_surf);
+   if (!isl_surf_get_ccs_surf(&intel->isl_dev, &temp_main_surf, 
&temp_ccs_surf))
+  return false;
+
+   mt->mcs_buf = calloc(1, sizeof(*mt->mcs_buf));
+   mt->mcs_buf->bo = image->bo;
+   brw_bo_reference(image->bo);
+
+   mt->mcs_buf->offset = image->aux_offset;
+   mt->mcs_buf->size = temp_ccs_surf.size;
+   mt->mcs_buf->pitch = temp_ccs_surf.row_pitch;
+   mt->mcs_buf->qpitch = isl_surf_get_array_pitch_sa_rows(&temp_ccs_surf);
+
+   intel_miptree_init_mcs(intel, mt, 0);
+   mt->aux_disable &= ~INTEL_AUX_DISABLE_CCS;
+   mt->msaa_layout = INTEL_MSAA_LAYOUT_CMS;
+
+   return true;
+}
+
 struct intel_mipmap_tree *
 intel_miptree_create_for_image(struct brw_context *intel,
__DRIimage *image,
@@ -776,17 +820,43 @@ intel_miptree_create_for_image(struct brw_context *intel,
uint32_t pitch,
uint32_t layout_flags)
 {
-   assert(layout_flags == 0);
-   layout_flags = MIPTREE_LAYOUT_DISABLE_AUX;
-   return intel_miptree_create_for_bo(intel,
-  image->bo,
-  format,
-  offset,
-  width,
-  height,
-  1,
-  pitch,
-  layout_flags);
+   struct intel_mipmap_tree *mt;
+
+   /* Other flags will be ignored, so make sure the caller didn't pass any. */
+   assert((layout_flags & ~MIPTREE_LAYOUT_FOR_SCANOUT) == 0);
+
+   if (!image->aux_offset)
+  layout_flags |= MIPTREE_LAYOUT_DISABLE_AUX;
+   else
+  layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
+
+   mt = intel_miptree_create_for_bo(intel,
+image->bo,
+format,
+offset,
+width,
+height,
+1,
+pitch,
+layout_flags);
+
+   if (!intel_tiling_supports_non_msrt_mcs(intel, mt->tiling)) {
+  assert(image->aux_offset == 0);
+  return mt;
+   }
+
+   if (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX)
+  return mt;
+
+   assert(image->aux_offset);
+   assert(mt->num_samples <= 1);
+   assert(mt->first_level == 0);
+   assert(mt->last_level == 0);
+   assert(mt

[Mesa-dev] [PATCH v15 12/16] i965: Add new resolve hints full and partial

[Daniel Stone]

From: Ben Widawsky 

Upper layers of the code will have the need to specify full or partial
resolves (more on this in the next patch). This code simply adds the new
enums and plumbs it in as minimally as necessary.

Signed-off-by: Ben Widawsky 
Acked-by: Daniel Stone 
Reviewed-by: Topi Pohjolainen 
Signed-off-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 3 ++-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 4 +++-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 36d25a1706..8598ce6711 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -944,7 +944,8 @@ brw_blorp_resolve_color(struct brw_context *brw, struct 
intel_mipmap_tree *mt,
 
enum blorp_fast_clear_op resolve_op;
if (brw->gen >= 9) {
-  if (surf.aux_usage == ISL_AUX_USAGE_CCS_E)
+  if (surf.aux_usage == ISL_AUX_USAGE_CCS_E &&
+  hint != INTEL_RESOLVE_HINT_CLEAR_COLOR)
  resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
   else
  resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 68bee043b3..099e46f785 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -973,7 +973,9 @@ intel_miptree_used_for_rendering(const struct brw_context 
*brw,
  */
 enum intel_resolve_hint {
INTEL_RESOLVE_HINT_NO_HINT = 0,
-   INTEL_RESOLVE_HINT_IGNORE_CCS_E
+   INTEL_RESOLVE_HINT_IGNORE_CCS_E,
+   INTEL_RESOLVE_HINT_CLEAR_COLOR,
+   INTEL_RESOLVE_HINT_FULL,
 };
 
 bool
-- 
2.13.0

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[Mesa-dev] [PATCH v15 08/16] i965/miptree: Allocate mt earlier in update winsys

[Daniel Stone]

From: Ben Widawsky 

Allows us to continue utilizing common miptree creation using __DRIimage
without creating a new DRIimage (for the intel_process_dri2_buffer()
case).

This is a bit ugly, but I think it's the best one can do.

v2: This patch let's us remove the temporary no_aux variable since mt
allocation should work correctly now.
Unref the BO is miptree creation fails (Jason)
v3: Rebase (Daniel)

Cc: Jason Ekstrand 
Signed-off-by: Ben Widawsky 
Acked-by: Daniel Stone 
Signed-off-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/brw_context.c   | 31 ++-
 src/mesa/drivers/dri/i965/intel_fbo.h |  7 --
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 17 ++-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  2 +-
 4 files changed, 29 insertions(+), 28 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 4c94b99a11..d7e30cdc92 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1667,10 +1667,25 @@ intel_process_dri2_buffer(struct brw_context *brw,
   return;
}
 
-   if (!intel_update_winsys_renderbuffer_miptree(brw, rb, bo,
+   struct intel_mipmap_tree *mt = intel_miptree_create_for_bo(brw,
+  bo,
+  
intel_rb_format(rb),
+  0,
+  drawable->w,
+  drawable->h,
+  1,
+  buffer->pitch,
+  
MIPTREE_LAYOUT_FOR_SCANOUT);
+   if (!mt) {
+  brw_bo_unreference(bo);
+  return;
+   }
+
+   if (!intel_update_winsys_renderbuffer_miptree(brw, rb, mt,
  drawable->w, drawable->h,
  buffer->pitch)) {
   brw_bo_unreference(bo);
+  intel_miptree_release(&mt);
   return;
}
 
@@ -1728,13 +1743,19 @@ intel_update_image_buffer(struct brw_context *intel,
if (last_mt && last_mt->bo == buffer->bo)
   return;
 
-   if (!buffer->aux_offset)
-  rb->no_aux = true;
+   struct intel_mipmap_tree *mt = intel_miptree_create_for_image(intel,
+ buffer, 
intel_rb_format(rb), 0,
+ 
buffer->width, buffer->height,
+ 
buffer->pitch, MIPTREE_LAYOUT_FOR_SCANOUT);
+   if (!mt)
+  return;
 
-   if (!intel_update_winsys_renderbuffer_miptree(intel, rb, buffer->bo,
+   if (!intel_update_winsys_renderbuffer_miptree(intel, rb, mt,
  buffer->width, buffer->height,
- buffer->pitch))
+ buffer->pitch)) {
+  intel_miptree_release(&mt);
   return;
+   }
 
if (_mesa_is_front_buffer_drawing(fb) &&
buffer_type == __DRI_IMAGE_BUFFER_FRONT &&
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.h 
b/src/mesa/drivers/dri/i965/intel_fbo.h
index 7fd95bb816..2d2ef1ebc6 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.h
+++ b/src/mesa/drivers/dri/i965/intel_fbo.h
@@ -111,13 +111,6 @@ struct intel_renderbuffer
 * for the duration of a mapping.
 */
bool singlesample_mt_is_tmp;
-
-   /**
-* Set to true if this buffer definitely does not have auxiliary data, like
-* CCS, associated with it. It's generally to be used when importing a
-* DRIimage, where that DRIimage had no modifier.
-*/
-   bool no_aux;
 };
 
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index dff992c90f..0a3b6e2fa1 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -875,11 +875,10 @@ intel_miptree_create_for_image(struct brw_context *intel,
 bool
 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
  struct intel_renderbuffer *irb,
- struct brw_bo *bo,
+ struct intel_mipmap_tree 
*singlesample_mt,
  uint32_t width, uint32_t height,
  uint32_t pitch)
 {
-   struct intel_mipmap_tree *singlesample_mt = NULL;
struct intel_mipmap_tree *multisample_mt = NULL;
struct gl_renderbuffer *rb = &irb->Base.Base;
mesa_format format = rb->Format;
@@ -891,18 +890,7 @@ intel_update_winsys_renderbuffer_miptree(struct 
brw_context *int

[Mesa-dev] [PATCH v15 16/16] i965: Handle compression modifier

[Daniel Stone]

From: Ben Widawsky 

v2: Rename modifier to be more smart (Jason)

FINISHME: Use the kernel's final choice for the fb modifier

bwidawsk@norris2:~/intel-gfx/kmscube (modifiers $) 
~/scripts/measure_bandwidth.sh ./kmscube none
Read bandwidth: 603.91 MiB/s
Write bandwidth: 615.28 MiB/s
bwidawsk@norris2:~/intel-gfx/kmscube (modifiers $) 
~/scripts/measure_bandwidth.sh ./kmscube ytile
Read bandwidth: 571.13 MiB/s
Write bandwidth: 555.51 MiB/s
bwidawsk@norris2:~/intel-gfx/kmscube (modifiers $) 
~/scripts/measure_bandwidth.sh ./kmscube ccs
Read bandwidth: 259.34 MiB/s
Write bandwidth: 337.83 MiB/s

v2: Move all references to the new fourcc code(s) to this patch.
v3: Rebase, remove Yf_CCS (Daniel)

Cc: Jason Ekstrand 
Signed-off-by: Ben Widawsky 
Acked-by: Daniel Stone 
Signed-off-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 9c5534d531..b7489455d1 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -307,6 +307,10 @@ static const struct {
  .since_gen = 1, .height_align = 8 },
{ .tiling = I915_TILING_Y, .modifier = I915_FORMAT_MOD_Y_TILED,
  .since_gen = 9, .height_align = 32 },
+   { .tiling = I915_TILING_Y, .modifier = /* I915_FORMAT_MOD_Y_TILED_CCS */ 
fourcc_mod_code(INTEL, 4),
+ .since_gen = 9, .height_align = 32,
+ .aux_w_block = 32, .aux_w_align = 128,
+ .aux_h_block = 16, .aux_h_align = 32 },
 };
 
 static bool
@@ -647,6 +651,7 @@ enum modifier_priority {
MODIFIER_PRIORITY_LINEAR,
MODIFIER_PRIORITY_X,
MODIFIER_PRIORITY_Y,
+   MODIFIER_PRIORITY_Y_CCS,
 };
 
 const uint64_t priority_to_modifier[] = {
@@ -654,6 +659,7 @@ const uint64_t priority_to_modifier[] = {
[MODIFIER_PRIORITY_LINEAR] = DRM_FORMAT_MOD_LINEAR,
[MODIFIER_PRIORITY_X] = I915_FORMAT_MOD_X_TILED,
[MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED,
+   [MODIFIER_PRIORITY_Y_CCS] =  /* I915_FORMAT_MOD_Y_TILED_CCS */ 
fourcc_mod_code(INTEL, 4),
 };
 
 static uint64_t
@@ -665,6 +671,9 @@ select_best_modifier(struct gen_device_info *devinfo,
 
for (int i = 0; i < count; i++) {
   switch (modifiers[i]) {
+  case /* I915_FORMAT_MOD_Y_TILED_CCS */ fourcc_mod_code(INTEL, 4):
+ prio = MAX2(prio, MODIFIER_PRIORITY_Y_CCS);
+ break;
   case I915_FORMAT_MOD_Y_TILED:
  prio = MAX2(prio, MODIFIER_PRIORITY_Y);
  break;
@@ -729,6 +738,7 @@ intel_create_image_common(__DRIscreen *dri_screen,
}
tiling = modifier_to_tiling(modifier);
tiled_height = get_tiled_height(modifier, height);
+   ccs_height = get_aux_height(modifier, height);
 
image = intel_allocate_image(screen, format, loaderPrivate);
if (image == NULL)
-- 
2.13.0

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[Mesa-dev] [PATCH v15 05/16] i965: add a no_aux field to identify buffers without aux data

[Daniel Stone]

From: Varad Gautam 

v2: split this into a separate patch (Jason)

Signed-off-by: Ben Widawsky 
Signed-off-by: Daniel Stone 
Cc: Jason Ekstrand 
---
 src/mesa/drivers/dri/i965/brw_context.c   | 3 +++
 src/mesa/drivers/dri/i965/intel_fbo.h | 7 +++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 ++-
 3 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 0a5120d32d..5a3a5e4cce 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1725,6 +1725,9 @@ intel_update_image_buffer(struct brw_context *intel,
if (last_mt && last_mt->bo == buffer->bo)
   return;
 
+   if (!buffer->aux_offset)
+  rb->no_aux = true;
+
intel_update_winsys_renderbuffer_miptree(intel, rb, buffer->bo,
 buffer->width, buffer->height,
 buffer->pitch);
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.h 
b/src/mesa/drivers/dri/i965/intel_fbo.h
index 2d2ef1ebc6..7fd95bb816 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.h
+++ b/src/mesa/drivers/dri/i965/intel_fbo.h
@@ -111,6 +111,13 @@ struct intel_renderbuffer
 * for the duration of a mapping.
 */
bool singlesample_mt_is_tmp;
+
+   /**
+* Set to true if this buffer definitely does not have auxiliary data, like
+* CCS, associated with it. It's generally to be used when importing a
+* DRIimage, where that DRIimage had no modifier.
+*/
+   bool no_aux;
 };
 
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 2b6beab83f..d321ce85e7 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -899,7 +899,8 @@ intel_update_winsys_renderbuffer_miptree(struct brw_context 
*intel,
  height,
  1,
  pitch,
- MIPTREE_LAYOUT_FOR_SCANOUT);
+ MIPTREE_LAYOUT_FOR_SCANOUT |
+ irb->no_aux ? 
MIPTREE_LAYOUT_DISABLE_AUX: 0);
if (!singlesample_mt)
   goto fail;
 
-- 
2.13.0

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[Mesa-dev] [PATCH v15 09/16] i965: Pretend that CCS modified images are two planes

[Daniel Stone]

From: Ben Widawsky 

v2: move is_aux into if block. (Jason)
Use else block instead of goto (Jason)

v3: Fix up logic for is_aux (Ben)
Fix up size calculations and add FIXME (Ben)

Cc: Jason Ekstrand 
Signed-off-by: Ben Widawsky 
Acked-by: Daniel Stone 
Signed-off-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 98 +++-
 1 file changed, 83 insertions(+), 15 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 16f9fe9cec..9c5534d531 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -296,6 +296,10 @@ static const struct {
uint64_t modifier;
unsigned since_gen;
unsigned height_align;
+   unsigned aux_w_block;
+   unsigned aux_w_align;
+   unsigned aux_h_block;
+   unsigned aux_h_align;
 } tiling_modifier_map[] = {
{ .tiling = I915_TILING_NONE, .modifier = DRM_FORMAT_MOD_LINEAR,
  .since_gen = 1, .height_align = 1 },
@@ -357,6 +361,57 @@ get_tiled_height(uint64_t modifier, unsigned height)
unreachable("get_tiled_height received unknown tiling mode");
 }
 
+static unsigned
+get_aux_width(uint64_t modifier, unsigned width)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(tiling_modifier_map); i++) {
+  if (tiling_modifier_map[i].modifier != modifier)
+ continue;
+  if (tiling_modifier_map[i].aux_w_block == 0)
+ return 0;
+  return ALIGN(DIV_ROUND_UP(width, tiling_modifier_map[i].aux_w_block),
+   tiling_modifier_map[i].aux_w_align);
+   }
+
+   unreachable("get_aux_width received unknown modifier");
+}
+
+static unsigned
+get_aux_stride(uint64_t modifier, unsigned stride)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(tiling_modifier_map); i++) {
+  if (tiling_modifier_map[i].modifier != modifier)
+ continue;
+  if (tiling_modifier_map[i].aux_w_block == 0)
+ return 0;
+  return ALIGN(stride / tiling_modifier_map[i].aux_w_block,
+   tiling_modifier_map[i].aux_w_align);
+   }
+
+   unreachable("get_aux_stride received unknown modifier");
+}
+
+static unsigned
+get_aux_height(uint64_t modifier, unsigned height)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(tiling_modifier_map); i++) {
+  if (tiling_modifier_map[i].modifier != modifier)
+ continue;
+  if (tiling_modifier_map[i].aux_h_block == 0)
+ return 0;
+  return ALIGN(DIV_ROUND_UP(height, tiling_modifier_map[i].aux_h_block),
+   tiling_modifier_map[i].aux_h_align);
+   }
+
+   unreachable("get_aux_height received unknown modifier");
+}
+
 static void
 intel_image_warn_if_unaligned(__DRIimage *image, const char *func)
 {
@@ -774,7 +829,7 @@ intel_query_image(__DRIimage *image, int attrib, int *value)
case __DRI_IMAGE_ATTRIB_FOURCC:
   return intel_lookup_fourcc(image->dri_format, value);
case __DRI_IMAGE_ATTRIB_NUM_PLANES:
-  *value = 1;
+  *value = image->aux_offset ? 2: 1;
   return true;
case __DRI_IMAGE_ATTRIB_OFFSET:
   *value = image->offset;
@@ -1116,20 +1171,33 @@ intel_from_planar(__DRIimage *parent, int plane, void 
*loaderPrivate)
 struct intel_image_format *f;
 __DRIimage *image;
 
-if (parent == NULL || parent->planar_format == NULL)
-return NULL;
-
-f = parent->planar_format;
-
-if (plane >= f->nplanes)
-return NULL;
-
-width = parent->width >> f->planes[plane].width_shift;
-height = parent->height >> f->planes[plane].height_shift;
-dri_format = f->planes[plane].dri_format;
-index = f->planes[plane].buffer_index;
-offset = parent->offsets[index];
-stride = parent->strides[index];
+if (parent == NULL) {
+   return NULL;
+} else if (parent->planar_format == NULL) {
+   const bool is_aux = parent->aux_offset && plane == 1;
+   if (!is_aux)
+  return NULL;
+
+   width = get_aux_width(parent->modifier, parent->width);
+   height = get_aux_width(parent->modifier, parent->height);
+   stride = get_aux_stride(parent->modifier, parent->pitch);
+   dri_format = parent->dri_format;
+   offset = parent->aux_offset;
+} else {
+   /* Planar formats don't support aux buffers/images */
+   assert(!parent->aux_offset);
+   f = parent->planar_format;
+
+   if (plane >= f->nplanes)
+  return NULL;
+
+   width = parent->width >> f->planes[plane].width_shift;
+   height = parent->height >> f->planes[plane].height_shift;
+   dri_format = f->planes[plane].dri_format;
+   index = f->planes[plane].buffer_index;
+   offset = parent->offsets[index];
+   stride = parent->strides[index];
+}
 
 image = intel_allocate_image(parent->screen, dri_format, loaderPrivate);
 if (image == NULL)
-- 
2.13.0

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[Mesa-dev] [PATCH v15 10/16] i965: Change resolve flags to enum

[Daniel Stone]

From: Ben Widawsky 

In the foreseeable future it doesn't seem to make sense to have multiple
resolve flags. What does make sense is to have the caller give an
indication to the lower layers what it things should be done for
resolve. The enum change distinguishes this binary selection.

v2: Make setting the hint more concise (Topi)

Signed-off-by: Ben Widawsky 
Acked-by: Daniel Stone 
Reviewed-by: Topi Pohjolainen 
Signed-off-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/brw_blorp.c |  8 
 src/mesa/drivers/dri/i965/brw_context.c   | 13 +++--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 12 ++--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 13 -
 4 files changed, 25 insertions(+), 21 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 28be620429..126a77862a 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -172,12 +172,12 @@ blorp_surf_for_miptree(struct brw_context *brw,
 surf->aux_usage = ISL_AUX_USAGE_NONE;
  }
   } else if (!(safe_aux_usage & (1 << surf->aux_usage))) {
- uint32_t flags = 0;
- if (safe_aux_usage & (1 << ISL_AUX_USAGE_CCS_E))
-flags |= INTEL_MIPTREE_IGNORE_CCS_E;
+ const enum intel_resolve_hint hint =
+safe_aux_usage & (1 << ISL_AUX_USAGE_CCS_E) ?
+INTEL_RESOLVE_HINT_IGNORE_CCS_E : 0;
 
  intel_miptree_resolve_color(brw, mt,
- *level, start_layer, num_layers, flags);
+ *level, start_layer, num_layers, hint);
 
  assert(!intel_miptree_has_color_unresolved(mt, *level, 1,
 start_layer, num_layers));
diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index d7e30cdc92..5e722cd6da 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -264,9 +264,10 @@ intel_update_state(struct gl_context * ctx, GLuint 
new_state)
   /* Sampling engine understands lossless compression and resolving
* those surfaces should be skipped for performance reasons.
*/
-  const int flags = intel_texture_view_requires_resolve(brw, tex_obj) ?
-   0 : INTEL_MIPTREE_IGNORE_CCS_E;
-  intel_miptree_all_slices_resolve_color(brw, tex_obj->mt, flags);
+  const enum intel_resolve_hint hint =
+ intel_texture_view_requires_resolve(brw, tex_obj) ? 0 :
+ INTEL_RESOLVE_HINT_IGNORE_CCS_E;
+  intel_miptree_all_slices_resolve_color(brw, tex_obj->mt, hint);
   brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
 
   if (tex_obj->base.StencilSampling ||
@@ -318,9 +319,9 @@ intel_update_state(struct gl_context * ctx, GLuint 
new_state)
 intel_renderbuffer(fb->_ColorDrawBuffers[i]);
 
  if (irb &&
- intel_miptree_resolve_color(
-brw, irb->mt, irb->mt_level, irb->mt_layer, irb->layer_count,
-INTEL_MIPTREE_IGNORE_CCS_E))
+ intel_miptree_resolve_color(brw, irb->mt, irb->mt_level,
+ irb->mt_layer, irb->layer_count,
+ INTEL_RESOLVE_HINT_IGNORE_CCS_E))
 brw_render_cache_set_check_flush(brw, irb->mt->bo);
   }
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 0a3b6e2fa1..44bf2885e5 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2230,7 +2230,7 @@ intel_miptree_used_for_rendering(const struct brw_context 
*brw,
 static bool
 intel_miptree_needs_color_resolve(const struct brw_context *brw,
   const struct intel_mipmap_tree *mt,
-  int flags)
+  enum intel_resolve_hint hint)
 {
if (mt->aux_disable & INTEL_AUX_DISABLE_CCS)
   return false;
@@ -2242,7 +2242,7 @@ intel_miptree_needs_color_resolve(const struct 
brw_context *brw,
 * surfaces called "lossless compressed". These don't need to be always
 * resolved.
 */
-   if ((flags & INTEL_MIPTREE_IGNORE_CCS_E) && is_lossless_compressed)
+   if ((hint == INTEL_RESOLVE_HINT_IGNORE_CCS_E) && is_lossless_compressed)
   return false;
 
/* Fast color clear resolves only make sense for non-MSAA buffers. */
@@ -2256,11 +2256,11 @@ bool
 intel_miptree_resolve_color(struct brw_context *brw,
 struct intel_mipmap_tree *mt, unsigned level,
 unsigned start_layer, unsigned num_layers,
-int flags)
+enum intel_resolve_hint hint)
 {
intel_miptree_check_color_resolve(brw, mt, level, start_layer);
 
-   if (!intel_miptree_needs_

[Mesa-dev] [PATCH v15 15/16] i965: Remove scanout restriction from lossless compression

[Daniel Stone]

From: Ben Widawsky 

v2: Try to keep the assert as recommended by Topi. This requires
modifying the num_samples check to be <= 1 because internally created
buffers set num_samples = 0.

v3: Buffers are proactively marked as scanout, often, and so checking
is_scanout in whether or not the buffer supports non-msrt fast clears
will return false. To avoid this, only check buffers which are destined
to use ccs (is a scanout buffer, and has an "mcs" buffer). Chad found
this issue.

v4: Use a better assertion based off of change in last patch. (Topi)

v5: Remove the assert entirely

Cc: Topi Pohjolainen 
Cc: Chad Versace 
Signed-off-by: Ben Widawsky 
Acked-by: Daniel Stone 
Reviewed-by: Topi Pohjolainen 
Signed-off-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index fe8aedcd10..c635f95ab9 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -699,8 +699,7 @@ intel_miptree_create(struct brw_context *brw,
   const bool lossless_compression_disabled = INTEL_DEBUG & DEBUG_NO_RBC;
   const bool is_lossless_compressed =
  unlikely(!lossless_compression_disabled) &&
- brw->gen >= 9 && !mt->is_scanout &&
- intel_miptree_supports_lossless_compressed(brw, mt);
+ brw->gen >= 9 && intel_miptree_supports_lossless_compressed(brw, mt);
 
   if (is_lossless_compressed) {
  assert(!(mt->aux_disable & INTEL_AUX_DISABLE_CCS));
-- 
2.13.0

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[Mesa-dev] [PATCH v15 14/16] i965/miptree: Remove dead code assertion

[Daniel Stone]

From: Ben Widawsky 

We no longer allocate a miptree for the mcs_buf, so this is not a useful
assertion.

Recommended-by: Topi Pohjolainen 
Signed-off-by: Ben Widawsky 
Reviewed-by: Topi Pohjolainen 
Signed-off-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 
 1 file changed, 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 79429a8c86..fe8aedcd10 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -522,14 +522,6 @@ intel_miptree_create_layout(struct brw_context *brw,
   layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
} else {
   mt->aux_disable |= INTEL_AUX_DISABLE_CCS;
-
-  const UNUSED bool is_lossless_compressed_aux =
- brw->gen >= 9 && num_samples == 1 &&
- mt->format == MESA_FORMAT_R_UINT32;
-
-  /* For now, nothing else has this requirement */
-  assert(is_lossless_compressed_aux ||
- (layout_flags & MIPTREE_LAYOUT_FORCE_HALIGN16) == 0);
}
 
if (!brw_miptree_layout(brw, mt, layout_flags)) {
-- 
2.13.0

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[Mesa-dev] [PATCH v15 07/16] i965/miptree: Add a return for updating of winsys

[Daniel Stone]

From: Ben Widawsky 

There is nothing particularly useful to do currently if the update
fails, but there is no point carrying on either. As a result, this has a
behavior change.

v2: Make the return type a bool (Topi)

v3: Don't leak the bo if update_winsys_renderbuffer fails. (Jason)

Signed-off-by: Ben Widawsky 
Acked-by: Daniel Stone 
Reviewed-by: Topi Pohjolainen  (v2)
Signed-off-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/brw_context.c   | 16 ++--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c |  6 +++---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  2 +-
 3 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 5a3a5e4cce..4c94b99a11 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1667,9 +1667,12 @@ intel_process_dri2_buffer(struct brw_context *brw,
   return;
}
 
-   intel_update_winsys_renderbuffer_miptree(brw, rb, bo,
-drawable->w, drawable->h,
-buffer->pitch);
+   if (!intel_update_winsys_renderbuffer_miptree(brw, rb, bo,
+ drawable->w, drawable->h,
+ buffer->pitch)) {
+  brw_bo_unreference(bo);
+  return;
+   }
 
if (_mesa_is_front_buffer_drawing(fb) &&
(buffer->attachment == __DRI_BUFFER_FRONT_LEFT ||
@@ -1728,9 +1731,10 @@ intel_update_image_buffer(struct brw_context *intel,
if (!buffer->aux_offset)
   rb->no_aux = true;
 
-   intel_update_winsys_renderbuffer_miptree(intel, rb, buffer->bo,
-buffer->width, buffer->height,
-buffer->pitch);
+   if (!intel_update_winsys_renderbuffer_miptree(intel, rb, buffer->bo,
+ buffer->width, buffer->height,
+ buffer->pitch))
+  return;
 
if (_mesa_is_front_buffer_drawing(fb) &&
buffer_type == __DRI_IMAGE_BUFFER_FRONT &&
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index d321ce85e7..dff992c90f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -872,7 +872,7 @@ intel_miptree_create_for_image(struct brw_context *intel,
  * that will contain the actual rendering (which is lazily resolved to
  * irb->singlesample_mt).
  */
-void
+bool
 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
  struct intel_renderbuffer *irb,
  struct brw_bo *bo,
@@ -939,12 +939,12 @@ intel_update_winsys_renderbuffer_miptree(struct 
brw_context *intel,
  irb->mt = multisample_mt;
   }
}
-   return;
+   return true;
 
 fail:
intel_miptree_release(&irb->singlesample_mt);
intel_miptree_release(&irb->mt);
-   return;
+   return false;
 }
 
 struct intel_mipmap_tree*
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 654ef3c787..35dc56e7db 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -752,7 +752,7 @@ intel_miptree_create_for_image(struct brw_context *intel,
uint32_t pitch,
uint32_t layout_flags);
 
-void
+bool
 intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
  struct intel_renderbuffer *irb,
  struct brw_bo *bo,
-- 
2.13.0

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[Mesa-dev] [PATCH v15 06/16] i965: Add logic for allocating BO with CCS

[Daniel Stone]

From: Ben Widawsky 

This patch provides the support (and comments) for allocating the BO
with space for the CCS buffer just underneath it.

This patch was originally titled:
"i965: Create correctly sized mcs for an image"

In order to make things more bisectable, reviewable, and to have the
CCS_MODIFIER token saved for the last patch, this patch now does less so
it was renamed.

v2: Leave "image+mod" (Topi)

Signed-off-by: Ben Widawsky 
Acked-by: Daniel Stone 
Reviewed-by: Topi Pohjolainen 
Signed-off-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 35 
 1 file changed, 31 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 9bc0895f39..16f9fe9cec 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -641,6 +641,7 @@ intel_create_image_common(__DRIscreen *dri_screen,
uint32_t tiling;
uint64_t modifier = DRM_FORMAT_MOD_INVALID;
unsigned tiled_height;
+   unsigned ccs_height = 0;
int cpp;
 
/* Callers of this may specify a modifier, or a dri usage, but not both. The
@@ -678,10 +679,33 @@ intel_create_image_common(__DRIscreen *dri_screen,
if (image == NULL)
   return NULL;
 
+   /*
+* CCS width is always going to be less than or equal to the image's width.
+* All we need to do is make sure we add extra rows (height) for the CCS.
+*
+* A pair of CCS bits correspond to 8x4 pixels, and must be cacheline
+* granularity. Each CCS tile is laid out in 8b strips, which corresponds to
+* 1024x512 pixel region. In memory, it looks like the following:
+*
+* ┌─┐
+* │ │
+* │ │
+* │ │
+* │  Image  │
+* │ │
+* │ │
+* │x│
+* ├─┬───┘
+* │ │   |
+* │ccs  │  unused   |
+* └─┘---┘
+* <--pitch-->
+*/
cpp = _mesa_get_format_bytes(image->format);
-   image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image",
-  width, tiled_height, cpp, tiling,
-  &image->pitch, 0);
+   image->bo = brw_bo_alloc_tiled(screen->bufmgr,
+  ccs_height ? "image+ccs" : "image+mod",
+  width, tiled_height + ccs_height,
+  cpp, tiling, &image->pitch, 0);
if (image->bo == NULL) {
   free(image);
   return NULL;
@@ -690,7 +714,10 @@ intel_create_image_common(__DRIscreen *dri_screen,
image->height = height;
image->modifier = modifier;
 
-   image->aux_offset = 0; /* y_tiled_height * pitch */
+   if (ccs_height)
+  image->aux_offset = tiled_height * image->pitch /* + mt->offset */;
+   else
+  image->aux_offset = 0;
 
return image;
 }
-- 
2.13.0

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Re: [Mesa-dev] [PATCH 1/7] egl/dri2: Avoid sign extension when building modifier

[Eric Engestrom]

On Tuesday, 2017-06-06 18:18:31 +0100, Daniel Stone wrote:
> Since the EGL attributes are signed integers, a straight OR would
> also perform sign extension,
> 
> Fixes: 6f10e7c37a ("egl/dri2: Create EGLImages with dmabuf modifiers")
> Cc: Varad Gautam 
> Signed-off-by: Daniel Stone 
> ---
>  src/egl/drivers/dri2/egl_dri2.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
> index d31a0bf8e0..7175e827c9 100644
> --- a/src/egl/drivers/dri2/egl_dri2.c
> +++ b/src/egl/drivers/dri2/egl_dri2.c
> @@ -2278,9 +2278,8 @@ dri2_create_image_dma_buf(_EGLDisplay *disp, 
> _EGLContext *ctx,
>  * will be present in attrs.DMABufPlaneModifiersLo[0] and
>  * attrs.DMABufPlaneModifiersHi[0] */
> if (attrs.DMABufPlaneModifiersLo[0].IsPresent) {
> -  modifier =
> - ((uint64_t) attrs.DMABufPlaneModifiersHi[0].Value << 32) |
> - attrs.DMABufPlaneModifiersLo[0].Value;
> +  modifier = (uint64_t) attrs.DMABufPlaneModifiersHi[0].Value << 32;
> +  modifier |= (uint64_t) (attrs.DMABufPlaneModifiersLo[0].Value & 
> 0x);

To be clear, the fix is to cast Lo before OR'ing it, right?
The rest is just aesthetic?

Reviewed-by: Eric Engestrom 

>has_modifier = true;
> } else {
>modifier = DRM_FORMAT_MOD_INVALID;
> -- 
> 2.13.0
> 
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Re: [Mesa-dev] [PATCH 1/7] egl/dri2: Avoid sign extension when building modifier

[Daniel Stone]

Hi Eric,

On 6 June 2017 at 18:27, Eric Engestrom  wrote:
> On Tuesday, 2017-06-06 18:18:31 +0100, Daniel Stone wrote:
>> diff --git a/src/egl/drivers/dri2/egl_dri2.c 
>> b/src/egl/drivers/dri2/egl_dri2.c
>> index d31a0bf8e0..7175e827c9 100644
>> --- a/src/egl/drivers/dri2/egl_dri2.c
>> +++ b/src/egl/drivers/dri2/egl_dri2.c
>> @@ -2278,9 +2278,8 @@ dri2_create_image_dma_buf(_EGLDisplay *disp, 
>> _EGLContext *ctx,
>>  * will be present in attrs.DMABufPlaneModifiersLo[0] and
>>  * attrs.DMABufPlaneModifiersHi[0] */
>> if (attrs.DMABufPlaneModifiersLo[0].IsPresent) {
>> -  modifier =
>> - ((uint64_t) attrs.DMABufPlaneModifiersHi[0].Value << 32) |
>> - attrs.DMABufPlaneModifiersLo[0].Value;
>> +  modifier = (uint64_t) attrs.DMABufPlaneModifiersHi[0].Value << 32;
>> +  modifier |= (uint64_t) (attrs.DMABufPlaneModifiersLo[0].Value & 
>> 0x);
>
> To be clear, the fix is to cast Lo before OR'ing it, right?
> The rest is just aesthetic?

Yeah, pretty much. A quick test suggests that the cast isn't even
strictly necessary: presumably the promotion (and sign-extension) from
int32 -> uint64 happens before the AND op in (u64 = i32 & 0x).
I figured being explicit couldn't do any harm anyway.

Cheers,
Daniel
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Re: [Mesa-dev] [PATCH 04/10] i965/blorp: Inline gen6_blorp_exec

[Pohjolainen, Topi]

On Mon, Jun 05, 2017 at 05:55:39PM -0700, Jason Ekstrand wrote:
> ---
>  src/mesa/drivers/dri/i965/brw_blorp.c | 29 +++--
>  1 file changed, 11 insertions(+), 18 deletions(-)

Patches 1-4:

Reviewed-by: Topi Pohjolainen 

> 
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index 097903e..7fd6760 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -979,23 +979,6 @@ brw_blorp_resolve_color(struct brw_context *brw, struct 
> intel_mipmap_tree *mt,
> PIPE_CONTROL_CS_STALL);
>  }
>  
> -static void
> -gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
> -unsigned int level, unsigned int layer, enum 
> blorp_hiz_op op)
> -{
> -   assert(intel_miptree_level_has_hiz(mt, level));
> -
> -   struct isl_surf isl_tmp[2];
> -   struct blorp_surf surf;
> -   blorp_surf_for_miptree(brw, &surf, mt, true, (1 << ISL_AUX_USAGE_HIZ),
> -  &level, layer, 1, isl_tmp);
> -
> -   struct blorp_batch batch;
> -   blorp_batch_init(&brw->blorp, &batch, brw, 0);
> -   blorp_gen6_hiz_op(&batch, &surf, level, layer, op);
> -   blorp_batch_finish(&batch);
> -}
> -
>  /**
>   * Perform a HiZ or depth resolve operation.
>   *
> @@ -1082,8 +1065,18 @@ intel_hiz_exec(struct brw_context *brw, struct 
> intel_mipmap_tree *mt,
>for (unsigned a = 0; a < num_layers; a++)
>   gen8_hiz_exec(brw, mt, level, start_layer + a, op);
> } else {
> +  assert(intel_miptree_level_has_hiz(mt, level));
> +
> +  struct isl_surf isl_tmp[2];
> +  struct blorp_surf surf;
> +  blorp_surf_for_miptree(brw, &surf, mt, true, (1 << ISL_AUX_USAGE_HIZ),
> + &level, start_layer, num_layers, isl_tmp);
> +
> +  struct blorp_batch batch;
> +  blorp_batch_init(&brw->blorp, &batch, brw, 0);
>for (unsigned a = 0; a < num_layers; a++)
> - gen6_blorp_hiz_exec(brw, mt, level, start_layer + a, op);
> + blorp_gen6_hiz_op(&batch, &surf, level, start_layer + a, op);
> +  blorp_batch_finish(&batch);
> }
>  
>  
> -- 
> 2.5.0.400.gff86faf
> 
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Re: [Mesa-dev] [PATCH 04/10] i965/blorp: Inline gen6_blorp_exec

[Pohjolainen, Topi]

On Tue, Jun 06, 2017 at 08:35:06PM +0300, Pohjolainen, Topi wrote:
> On Mon, Jun 05, 2017 at 05:55:39PM -0700, Jason Ekstrand wrote:
> > ---
> >  src/mesa/drivers/dri/i965/brw_blorp.c | 29 +++--
> >  1 file changed, 11 insertions(+), 18 deletions(-)
> 
> Patches 1-4:
> 
> Reviewed-by: Topi Pohjolainen 

In fact patches 5 and 7-10 also:

Reviewed-by: Topi Pohjolainen 
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Re: [Mesa-dev] [PATCH 8/8] radeonsi: don't update dependent states if it has no effect

[Samuel Pitoiset]

I really like the idea. :-)

Though, I have two general comments:

1) I think it would be better to introduce some sort of compare helper 
functions for the different state changes. Also, for correctness it 
might be safer to do the opposite checks (if someone introduce a new 
field and forget to update the relevant part).


2) I would suggest to introduce uses_instance_divisors in a separate patch.

Btw, I'm not going to review patch 4 because I'm not familiar enough 
with this part.


On 06/05/2017 06:51 PM, Marek Olšák wrote:

From: Marek Olšák 

This and the previous commit decrease IB sizes and the number of
si_update_shaders invocations as follows:

  IB size   si_update_shader calls
Borderlands 2  -10%-27%
Deus Ex: MD -5%-11%
Talos Principle -8%-30%
---
  src/gallium/drivers/radeonsi/si_state.c | 68 ++---
  src/gallium/drivers/radeonsi/si_state.h |  1 +
  src/gallium/drivers/radeonsi/si_state_shaders.c | 24 +++--
  3 files changed, 80 insertions(+), 13 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 5e5f564..323ec5e 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -596,23 +596,41 @@ static void *si_create_blend_state_mode(struct 
pipe_context *ctx,
  
  static void *si_create_blend_state(struct pipe_context *ctx,

   const struct pipe_blend_state *state)
  {
return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
  }
  
  static void si_bind_blend_state(struct pipe_context *ctx, void *state)

  {
struct si_context *sctx = (struct si_context *)ctx;
-   si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
-   si_mark_atom_dirty(sctx, &sctx->cb_render_state);
-   sctx->do_update_shaders = true;
+   struct si_state_blend *old_blend = sctx->queued.named.blend;
+   struct si_state_blend *blend = (struct si_state_blend *)state;
+
+   if (!state)
+   return;
+
+   if (!old_blend ||
+old_blend->cb_target_mask != blend->cb_target_mask ||
+old_blend->dual_src_blend != blend->dual_src_blend)
+   si_mark_atom_dirty(sctx, &sctx->cb_render_state);
+
+   si_pm4_bind_state(sctx, blend, state);
+
+   if (!old_blend ||
+   old_blend->cb_target_mask != blend->cb_target_mask ||
+   old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
+   old_blend->alpha_to_one != blend->alpha_to_one ||
+   old_blend->dual_src_blend != blend->dual_src_blend ||
+   old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
+   old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
+   sctx->do_update_shaders = true;
  }
  
  static void si_delete_blend_state(struct pipe_context *ctx, void *state)

  {
struct si_context *sctx = (struct si_context *)ctx;
si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
  }
  
  static void si_set_blend_color(struct pipe_context *ctx,

   const struct pipe_blend_color *state)
@@ -914,24 +932,41 @@ static void si_bind_rs_state(struct pipe_context *ctx, 
void *state)
}
  
  	sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;

sctx->current_vs_state |= 
S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
  
  	r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
  
  	si_pm4_bind_state(sctx, rasterizer, rs);

si_update_poly_offset_state(sctx);
  
-	si_mark_atom_dirty(sctx, &sctx->clip_regs);

+   if (!old_rs ||
+   old_rs->clip_plane_enable != rs->clip_plane_enable ||
+   old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
+   si_mark_atom_dirty(sctx, &sctx->clip_regs);
+
sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
rs->line_stipple_enable;
-   sctx->do_update_shaders = true;
+
+   if (!old_rs ||
+   old_rs->clip_plane_enable != rs->clip_plane_enable ||
+   old_rs->rasterizer_discard != rs->rasterizer_discard ||
+   old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
+   old_rs->flatshade != rs->flatshade ||
+   old_rs->two_side != rs->two_side ||
+   old_rs->multisample_enable != rs->multisample_enable ||
+   old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
+   old_rs->poly_smooth != rs->poly_smooth ||
+   old_rs->line_smooth != rs->line_smooth ||
+   old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
+   old_rs->force_persample_interp != rs->force_persample_interp)
+   sctx->do_update_shaders = true;
  }
  
  static void si_delete_rs_state(struct pipe_context *ctx, void *state)

  {
struct si_context *sctx = (struct si_context *)ctx;
  
  	if (sct