date:20171014

Re: [Mesa-dev] [PATCH v3 16/43] i965/fs: Define new shader opcode to set rounding modes

2017-10-14 Thread Pohjolainen, Topi

On Thu, Oct 12, 2017 at 08:38:05PM +0200, Jose Maria Casanova Crespo wrote:
> From: Alejandro Piñeiro 
> 
> Although it is possible to emit them directly as AND/OR on brw_fs_nir,
> having a specific opcode makes it easier to remove duplicate settings
> later.
> 
> v2: (Curro)
>   - Set thread control to 'switch' when using the control register
>   - Use a single SHADER_OPCODE_RND_MODE opcode taking an immediate
> with the rounding mode.
>   - Avoid magic numbers setting rounding mode field at control register.
> v3: (Curro)
>   - Remove redundant and add missing whitespace lines.
>   - Match printing instruction to IR opcode "rnd_mode"
> 
> Signed-off-by:  Alejandro Piñeiro 
> Signed-off-by:  Jose Maria Casanova Crespo 
> Reviewed-by: Francisco Jerez 
> ---
>  src/intel/compiler/brw_eu.h |  4 
>  src/intel/compiler/brw_eu_defines.h | 16 
>  src/intel/compiler/brw_eu_emit.c| 33 
> +
>  src/intel/compiler/brw_fs_generator.cpp |  5 +
>  src/intel/compiler/brw_shader.cpp   |  4 
>  5 files changed, 62 insertions(+)
> 
> diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
> index 8e597b212a..145942a54f 100644
> --- a/src/intel/compiler/brw_eu.h
> +++ b/src/intel/compiler/brw_eu.h
> @@ -500,6 +500,10 @@ brw_broadcast(struct brw_codegen *p,
>struct brw_reg src,
>struct brw_reg idx);
>  
> +void
> +brw_rounding_mode(struct brw_codegen *p,
> +  enum brw_rnd_mode mode);
> +
>  /***
>   * brw_eu_util.c:
>   */
> diff --git a/src/intel/compiler/brw_eu_defines.h 
> b/src/intel/compiler/brw_eu_defines.h
> index da482b73c5..6687883bfb 100644
> --- a/src/intel/compiler/brw_eu_defines.h
> +++ b/src/intel/compiler/brw_eu_defines.h
> @@ -388,6 +388,8 @@ enum opcode {
> SHADER_OPCODE_TYPED_SURFACE_WRITE,
> SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
>  
> +   SHADER_OPCODE_RND_MODE,
> +
> SHADER_OPCODE_MEMORY_FENCE,
>  
> SHADER_OPCODE_GEN4_SCRATCH_READ,
> @@ -1214,4 +1216,18 @@ enum brw_message_target {
>  /* R0 */
>  # define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT   27
>  
> +/* CR0.0[5:4] Floating-Point Rounding Modes
> + *  Skylake PRM, Volume 7 Part 1, "Control Register", page 756
> + */
> +
> +#define BRW_CR0_RND_MODE_MASK 0x30
> +#define BRW_CR0_RND_MODE_SHIFT4
> +
> +enum PACKED brw_rnd_mode {
> +   BRW_RND_MODE_RTNE = 0,  /* Round to Nearest or Even */
> +   BRW_RND_MODE_RU = 1,/* Round Up, toward +inf */
> +   BRW_RND_MODE_RD = 2,/* Round Down, toward -inf */
> +   BRW_RND_MODE_RTZ = 3,   /* Round Toward Zero */
> +};
> +
>  #endif /* BRW_EU_DEFINES_H */
> diff --git a/src/intel/compiler/brw_eu_emit.c 
> b/src/intel/compiler/brw_eu_emit.c
> index 2b38d959d1..8c1e4c5eae 100644
> --- a/src/intel/compiler/brw_eu_emit.c
> +++ b/src/intel/compiler/brw_eu_emit.c
> @@ -3450,3 +3450,36 @@ brw_WAIT(struct brw_codegen *p)
> brw_inst_set_exec_size(devinfo, insn, BRW_EXECUTE_1);
> brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
>  }
> +
> +/**
> + * Changes the floating point rounding mode updating the control register
> + * field defined at cr0.0[5-6] bits. This function supports the changes to
> + * RTNE (00), RU (01), RD (10) and RTZ (11) rounding using bitwise 
> operations.
> + * Only RTNE and RTZ rounding are enabled at nir.
> + */
> +void
> +brw_rounding_mode(struct brw_codegen *p,
> +  enum brw_rnd_mode mode)
> +{
> +   const unsigned bits  = mode << BRW_CR0_RND_MODE_SHIFT;

Extra space before '='.
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Re: [Mesa-dev] [PATCH v3 14/43] i965/fs: Handle 32-bit to 16-bit conversions

2017-10-14 Thread Pohjolainen, Topi

On Thu, Oct 12, 2017 at 08:38:03PM +0200, Jose Maria Casanova Crespo wrote:
> From: Alejandro Piñeiro 
> 
> Conversions to 16-bit need having aligment between the 16-bit
> and 32-bit types. So the conversion operations unpack 16-bit types
> to with an stride=2 and then applies a MOV with the conversion.
> 
> v2 (Jason Ekstrand):
>   - Avoid the general use of stride=2 for 16-bit register types.
> 
> Signed-off-by: Eduardo Lima 
> Signed-off-by: Alejandro Piñeiro 
> Signed-off-by: Jose Maria Casanova Crespo 
> ---
>  src/intel/compiler/brw_fs_nir.cpp | 25 +
>  1 file changed, 25 insertions(+)
> 
> diff --git a/src/intel/compiler/brw_fs_nir.cpp 
> b/src/intel/compiler/brw_fs_nir.cpp
> index affe65d5e9..6908c7ea02 100644
> --- a/src/intel/compiler/brw_fs_nir.cpp
> +++ b/src/intel/compiler/brw_fs_nir.cpp
> @@ -693,6 +693,31 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, 
> nir_alu_instr *instr)
>inst->saturate = instr->dest.saturate;
>break;
>  
> +  /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
> +   * on the HW gen, it is a special hw opcode or just a MOV, and
> +   * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
> +   *
> +   * But if we want to use that opcode, we need to provide support on
> +   * different optimizations and lowerings. As right now HF support is
> +   * only for gen8+, it will be better to use directly the MOV, and use
> +   * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
> +   */
> +
> +   case nir_op_f2f16:
> +   case nir_op_i2i16:
> +   case nir_op_u2u16: {
> +  /* TODO: Fixing aligment rules for conversions from 32-bits to
> +   * 16-bit types should be moved to lower_conversions
> +   */
> +  fs_reg tmp = bld.vgrf(op[0].type, 1);
> +  tmp = subscript(tmp, result.type, 0);
> +  inst = bld.MOV(tmp, op[0]);
> +  inst->saturate = instr->dest.saturate;
> +  inst = bld.MOV(result ,tmp);

Move space after ','

> +  inst->saturate = instr->dest.saturate;
> +  break;
> +   }
> +
> case nir_op_f2f64:
> case nir_op_i2f64:
> case nir_op_u2f64:
> -- 
> 2.13.6
> 
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Re: [Mesa-dev] [PATCH v3 19/43] i965/fs: Support push constants of 16-bit types

2017-10-14 Thread Pohjolainen, Topi

On Thu, Oct 12, 2017 at 08:38:08PM +0200, Jose Maria Casanova Crespo wrote:
> We enable the use of 16-bit values in push constants
> modifying the assign_constant_locations function to work
> with 16-bit types.
> 
> The API to access buffers in Vulkan use multiples of 4-byte for
> offsets and sizes. Current accountability of uniforms based on 4-byte
> slots will work for 16-bit values if they are allowed to use 32-bit
> slots. For that, we replace the division by 4 by a DIV_ROUND_UP, so
> 2-byte elements will use 1 slot instead of 0.
> 
> We aligns the 16-bit locations after assigning the 32-bit

s/aligns/align/
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Re: [Mesa-dev] [PATCH v4 0/2] build system: Unify c++11 detection and used [was: configure+mesa/st:check -std=c++11 support and enable tests accordingly]

2017-10-14 Thread Gert Wollny

Hi Emil, 

regarding this patch, I now think we can indeed drop the second part
(the one that adds the g++4.4 test), because it would only check
whether one sets the -std=c++11 flag somewhere accidently. Checking
that no c++11 code makes it into core mesa is already happening as long
as travis uses a pre g++6 compiler.

Considerig the choice between checking for support of the flag 
-std=c++11 and checking whether the compiler supports c++11 features by
default the discussion on debian-devel started by this mail 

  https://lists.debian.org/debian-devel/2017/10/msg00174.html

might be of interest. In short it is preferred that the code is
compiled with the standard the compiler sets by default. From that
point of view the version of the patch that checks for the features
would be better, or I could rework the patch to check whether  g++ is
>= 6.0, but that is, of course, not as generic. 

Another consideration is that with g++ >= 6 with the current approach
of setting the flags we end up with the somewhat paradox situation
where the "more modern" code requiring -std=c++11 is compiled like
this, but the "older" code is compiled with the default, newer, c++14,
so no setting flags unless it is really needed would IMHO be more
consistent. 

Best, 
Gert 

Am Dienstag, den 03.10.2017, 16:47 +0200 schrieb Gert Wollny:
> 
> Following Emils comments I've updated the patches. 
> 
> Compiling was tested on travis on top of 677edff5cf (wayland-egl:
> rework ...) 
> plus the patch  "wayland-egl: redistribute wayland.egl.h include"
> proposed by 
> Tobias Klausmann: https://travis-ci.org/gerddie/mesa/builds/282591233
>  to fix 
> some build configurations.  
> 
> Changes versus v3:
> 
> patch 1: 
> - use AX_CHECK_COMPILE_FLAG to test for support of -std=c++11, this 
>   avoids adding a new custom m4 file
> - use if-then tests instead of calling the macro various times 
> - remove undocumented changes to .travis.yml 
> 
> patch 2: 
> - use llvm-3.3 when building with g++-4.4 since llvm-3.6 actually
> sets the -std=c++11 flag resulting in build failure with g++4.4 that
> doesn't support this flag. 
> 
> Regarding adding yet anouther build configuration to travis: 
> I propose to add this test, because mesa is supposed to support
> compilers  gcc/g++ 4.2, and -std=c++11 was not supported before g++-
> 4.7. Given that g++ >= 6 is now the standard in Debian stable and
> derivatives, and defaults to c++14, developers using these distros
> might not be aware when they add c++11 (or c++14) code.
> 
> Changes w.r.t. v2:
> - complete rewrite
> 
> best regards, 
> Gert 
> 
> Gert Wollny (2):
>   configure+mesa/st: unify check for -std=c++11 support and enable
> accordingly
>   travis: Add test for gcc-4.4 compiler tool chain
> 
>  .travis.yml   | 31
> +++
>  configure.ac  | 18 ++--
>  src/gallium/drivers/swr/Makefile.am   |  4 ++--
>  src/gallium/state_trackers/clover/Makefile.am |  6 +++---
>  src/mesa/state_tracker/tests/Makefile.am  |  7 +-
>  5 files changed, 54 insertions(+), 12 deletions(-)
> 
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Re: [Mesa-dev] [PATCH 1/2] etnaviv: skip unused vertex attributes when assigning VS inputs

2017-10-14 Thread Wladimir J. van der Laan

On Thu, Oct 12, 2017 at 04:07:47PM +0200, Lucas Stach wrote:
> When not all of the vertex attributes are actually used in the shader,
> we end up with some inputs without an assigned reg. Those are marked
> as invalid and must be skipped when assigning the inputs, as those would
> overwrite other valid inputs otherwise.
> 
> Fixes piglit drawpixels and a bunch of other tests using the st_draw path.
> 
> Signed-off-by: Lucas Stach 

Reviewed-by: Wladimir J. van der Laan 
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Re: [Mesa-dev] [PATCH 2/2] etnaviv: rework TS enable to be a derived state

2017-10-14 Thread Wladimir J. van der Laan

On Thu, Oct 12, 2017 at 04:07:48PM +0200, Lucas Stach wrote:
> Draw operations should not use the TS if the TS buffer content is invalid,
> as this leads to wrong rendering or even GPU hangs. As the TS valid status
> can change between draws (clear operations changing it to valid,

> blits using the RS to the color or ZS buffer changing it to invalid), the
> TS_MEM_CONFIG must be updated before each draw if the status has changed.
> This fixes the remaining TS related piglit failures (regressions of a
> standard run against a piglit run with TS completely disabled).
> 
> Signed-off-by: Lucas Stach 

Keeping the TS memory config state up to date with our internal state is a good 
idea.

Reviewed-by: Wladimir J. van der Laan 


> ---
>  src/gallium/drivers/etnaviv/etnaviv_clear_blit.c |  5 +--
>  src/gallium/drivers/etnaviv/etnaviv_context.h|  1 +
>  src/gallium/drivers/etnaviv/etnaviv_state.c  | 42 
> ++--
>  3 files changed, 43 insertions(+), 5 deletions(-)
> 
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c 
> b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
> index c62287b1339a..7b3fc1822ba5 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
> @@ -130,7 +130,7 @@ etna_blit_clear_color(struct pipe_context *pctx, struct 
> pipe_surface *dst,
>}
>  
>surf->level->ts_valid = true;
> -  ctx->dirty |= ETNA_DIRTY_TS;
> +  ctx->dirty |= ETNA_DIRTY_TS | ETNA_DIRTY_DERIVE_TS;
> } else if (unlikely(new_clear_value != surf->level->clear_value)) { /* 
> Queue normal RS clear for non-TS surfaces */
>/* If clear color changed, re-generate stored command */
>etna_rs_gen_clear_surface(ctx, surf, new_clear_value);
> @@ -189,7 +189,7 @@ etna_blit_clear_zs(struct pipe_context *pctx, struct 
> pipe_surface *dst,
>}
>  
>surf->level->ts_valid = true;
> -  ctx->dirty |= ETNA_DIRTY_TS;
> +  ctx->dirty |= ETNA_DIRTY_TS | ETNA_DIRTY_DERIVE_TS;
> } else {
>if (unlikely(new_clear_value != surf->level->clear_value)) { /* Queue 
> normal RS clear for non-TS surfaces */
>   /* If clear depth value changed, re-generate stored command */
> @@ -612,6 +612,7 @@ etna_try_rs_blit(struct pipe_context *pctx,
> resource_written(ctx, &dst->base);
> dst->seqno++;
> dst->levels[blit_info->dst.level].ts_valid = false;
> +   ctx->dirty |= ETNA_DIRTY_DERIVE_TS;
>  
> return TRUE;
>  
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.h 
> b/src/gallium/drivers/etnaviv/etnaviv_context.h
> index 2c9b24dfd439..bf2b265f5ee4 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_context.h
> +++ b/src/gallium/drivers/etnaviv/etnaviv_context.h
> @@ -124,6 +124,7 @@ struct etna_context {
>ETNA_DIRTY_SHADER  = (1 << 16),
>ETNA_DIRTY_TS  = (1 << 17),
>ETNA_DIRTY_TEXTURE_CACHES  = (1 << 18),
> +  ETNA_DIRTY_DERIVE_TS   = (1 << 19),
> } dirty;
>  
> uint32_t prim_hwsupport;
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_state.c 
> b/src/gallium/drivers/etnaviv/etnaviv_state.c
> index fc3d9f108fac..34bcb1906991 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_state.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_state.c
> @@ -165,7 +165,6 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
>cs->PE_COLOR_STRIDE = cbuf->surf.stride;
>  
>if (cbuf->surf.ts_size) {
> - ts_mem_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
>   cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value;
>  
>   cs->TS_COLOR_STATUS_BASE = cbuf->ts_reloc;
> @@ -231,7 +230,6 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
>cs->PE_DEPTH_NORMALIZE = fui(exp2f(depth_bits) - 1.0f);
>  
>if (zsbuf->surf.ts_size) {
> - ts_mem_config |= VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
>   cs->TS_DEPTH_CLEAR_VALUE = zsbuf->level->clear_value;
>  
>   cs->TS_DEPTH_STATUS_BASE = zsbuf->ts_reloc;
> @@ -325,7 +323,7 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
> cs->PE_LOGIC_OP = VIVS_PE_LOGIC_OP_SINGLE_BUFFER(ctx->specs.single_buffer 
> ? 2 : 0);
>  
> ctx->framebuffer_s = *sv; /* keep copy of original structure */
> -   ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER;
> +   ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_DERIVE_TS;
>  }
>  
>  static void
> @@ -572,6 +570,41 @@ etna_vertex_elements_state_bind(struct pipe_context 
> *pctx, void *ve)
> ctx->dirty |= ETNA_DIRTY_VERTEX_ELEMENTS;
>  }
>  
> +static bool
> +etna_update_ts_config(struct etna_context *ctx)
> +{
> +   uint32_t new_ts_config = ctx->framebuffer.TS_MEM_CONFIG;
> +
> +   if (ctx->framebuffer_s.nr_cbufs > 0) {
> +  struct etna_surface *c_surf = 
> etna_surface(ctx->framebuffer_s.cbufs[0]);
> +
> +  if(c_surf->level->ts_size && c_surf->level->ts_valid) {
> + new_ts_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
> +  } else {
> + ne

Re: [Mesa-dev] [PATCH 1/2] etnaviv: skip unused vertex attributes when assigning VS inputs

2017-10-14 Thread Christian Gmeiner

2017-10-12 16:07 GMT+02:00 Lucas Stach :
> When not all of the vertex attributes are actually used in the shader,
> we end up with some inputs without an assigned reg. Those are marked
> as invalid and must be skipped when assigning the inputs, as those would
> overwrite other valid inputs otherwise.
>
> Fixes piglit drawpixels and a bunch of other tests using the st_draw path.
>
> Signed-off-by: Lucas Stach 

Reviewed-by: Christian Gmeiner 

> ---
>  src/gallium/drivers/etnaviv/etnaviv_compiler.c | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler.c 
> b/src/gallium/drivers/etnaviv/etnaviv_compiler.c
> index e2b906c2f6a5..41ab4031f6c5 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_compiler.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_compiler.c
> @@ -2126,6 +2126,10 @@ fill_in_vs_inputs(struct etna_shader_variant *sobj, 
> struct etna_compile *c)
> for (int idx = 0; idx < c->file[TGSI_FILE_INPUT].reg_size; ++idx) {
>struct etna_reg_desc *reg = &c->file[TGSI_FILE_INPUT].reg[idx];
>assert(sf->num_reg < ETNA_NUM_INPUTS);
> +
> +  if (!reg->native.valid)
> + continue;
> +
>/* XXX exclude inputs with special semantics such as gl_frontFacing */
>sf->reg[sf->num_reg].reg = reg->native.id;
>sf->reg[sf->num_reg].semantic = reg->semantic;
> --
> 2.11.0
>
> ___
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greets
--
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Re: [Mesa-dev] [PATCH 2/2] etnaviv: rework TS enable to be a derived state

2017-10-14 Thread Christian Gmeiner

2017-10-12 16:07 GMT+02:00 Lucas Stach :
> Draw operations should not use the TS if the TS buffer content is invalid,
> as this leads to wrong rendering or even GPU hangs. As the TS valid status
> can change between draws (clear operations changing it to valid, blits using
> the RS to the color or ZS buffer changing it to invalid), the TS_MEM_CONFIG
> must be updated before each draw if the status has changed.
>
> This fixes the remaining TS related piglit failures (regressions of a
> standard run against a piglit run with TS completely disabled).
>
> Signed-off-by: Lucas Stach 

Reviewed-by: Christian Gmeiner 

> ---
>  src/gallium/drivers/etnaviv/etnaviv_clear_blit.c |  5 +--
>  src/gallium/drivers/etnaviv/etnaviv_context.h|  1 +
>  src/gallium/drivers/etnaviv/etnaviv_state.c  | 42 
> ++--
>  3 files changed, 43 insertions(+), 5 deletions(-)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c 
> b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
> index c62287b1339a..7b3fc1822ba5 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
> @@ -130,7 +130,7 @@ etna_blit_clear_color(struct pipe_context *pctx, struct 
> pipe_surface *dst,
>}
>
>surf->level->ts_valid = true;
> -  ctx->dirty |= ETNA_DIRTY_TS;
> +  ctx->dirty |= ETNA_DIRTY_TS | ETNA_DIRTY_DERIVE_TS;
> } else if (unlikely(new_clear_value != surf->level->clear_value)) { /* 
> Queue normal RS clear for non-TS surfaces */
>/* If clear color changed, re-generate stored command */
>etna_rs_gen_clear_surface(ctx, surf, new_clear_value);
> @@ -189,7 +189,7 @@ etna_blit_clear_zs(struct pipe_context *pctx, struct 
> pipe_surface *dst,
>}
>
>surf->level->ts_valid = true;
> -  ctx->dirty |= ETNA_DIRTY_TS;
> +  ctx->dirty |= ETNA_DIRTY_TS | ETNA_DIRTY_DERIVE_TS;
> } else {
>if (unlikely(new_clear_value != surf->level->clear_value)) { /* Queue 
> normal RS clear for non-TS surfaces */
>   /* If clear depth value changed, re-generate stored command */
> @@ -612,6 +612,7 @@ etna_try_rs_blit(struct pipe_context *pctx,
> resource_written(ctx, &dst->base);
> dst->seqno++;
> dst->levels[blit_info->dst.level].ts_valid = false;
> +   ctx->dirty |= ETNA_DIRTY_DERIVE_TS;
>
> return TRUE;
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.h 
> b/src/gallium/drivers/etnaviv/etnaviv_context.h
> index 2c9b24dfd439..bf2b265f5ee4 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_context.h
> +++ b/src/gallium/drivers/etnaviv/etnaviv_context.h
> @@ -124,6 +124,7 @@ struct etna_context {
>ETNA_DIRTY_SHADER  = (1 << 16),
>ETNA_DIRTY_TS  = (1 << 17),
>ETNA_DIRTY_TEXTURE_CACHES  = (1 << 18),
> +  ETNA_DIRTY_DERIVE_TS   = (1 << 19),
> } dirty;
>
> uint32_t prim_hwsupport;
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_state.c 
> b/src/gallium/drivers/etnaviv/etnaviv_state.c
> index fc3d9f108fac..34bcb1906991 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_state.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_state.c
> @@ -165,7 +165,6 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
>cs->PE_COLOR_STRIDE = cbuf->surf.stride;
>
>if (cbuf->surf.ts_size) {
> - ts_mem_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
>   cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value;
>
>   cs->TS_COLOR_STATUS_BASE = cbuf->ts_reloc;
> @@ -231,7 +230,6 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
>cs->PE_DEPTH_NORMALIZE = fui(exp2f(depth_bits) - 1.0f);
>
>if (zsbuf->surf.ts_size) {
> - ts_mem_config |= VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
>   cs->TS_DEPTH_CLEAR_VALUE = zsbuf->level->clear_value;
>
>   cs->TS_DEPTH_STATUS_BASE = zsbuf->ts_reloc;
> @@ -325,7 +323,7 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
> cs->PE_LOGIC_OP = VIVS_PE_LOGIC_OP_SINGLE_BUFFER(ctx->specs.single_buffer 
> ? 2 : 0);
>
> ctx->framebuffer_s = *sv; /* keep copy of original structure */
> -   ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER;
> +   ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_DERIVE_TS;
>  }
>
>  static void
> @@ -572,6 +570,41 @@ etna_vertex_elements_state_bind(struct pipe_context 
> *pctx, void *ve)
> ctx->dirty |= ETNA_DIRTY_VERTEX_ELEMENTS;
>  }
>
> +static bool
> +etna_update_ts_config(struct etna_context *ctx)
> +{
> +   uint32_t new_ts_config = ctx->framebuffer.TS_MEM_CONFIG;
> +
> +   if (ctx->framebuffer_s.nr_cbufs > 0) {
> +  struct etna_surface *c_surf = 
> etna_surface(ctx->framebuffer_s.cbufs[0]);
> +
> +  if(c_surf->level->ts_size && c_surf->level->ts_valid) {
> + new_ts_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
> +  } else {
> + new_ts_config &= ~VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
> +  }
> +   }
> +
> +   if (ctx->framebuffer_s.zsbuf) {
> +  struct etna_surfac

Re: [Mesa-dev] [PATCH v3 16/43] i965/fs: Define new shader opcode to set rounding modes

2017-10-14 Thread Chema Casanova



On 14/10/17 09:49, Pohjolainen, Topi wrote:
> On Thu, Oct 12, 2017 at 08:38:05PM +0200, Jose Maria Casanova Crespo wrote:
>> From: Alejandro Piñeiro 
>>
>> Although it is possible to emit them directly as AND/OR on brw_fs_nir,
>> having a specific opcode makes it easier to remove duplicate settings
>> later.
>>
>> v2: (Curro)
>>   - Set thread control to 'switch' when using the control register
>>   - Use a single SHADER_OPCODE_RND_MODE opcode taking an immediate
>> with the rounding mode.
>>   - Avoid magic numbers setting rounding mode field at control register.
>> v3: (Curro)
>>   - Remove redundant and add missing whitespace lines.
>>   - Match printing instruction to IR opcode "rnd_mode"
>>
>> Signed-off-by:  Alejandro Piñeiro 
>> Signed-off-by:  Jose Maria Casanova Crespo 
>> Reviewed-by: Francisco Jerez 
>> ---
>>  src/intel/compiler/brw_eu.h |  4 
>>  src/intel/compiler/brw_eu_defines.h | 16 
>>  src/intel/compiler/brw_eu_emit.c| 33 
>> +
>>  src/intel/compiler/brw_fs_generator.cpp |  5 +
>>  src/intel/compiler/brw_shader.cpp   |  4 
>>  5 files changed, 62 insertions(+)
>>
>> diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
>> index 8e597b212a..145942a54f 100644
>> --- a/src/intel/compiler/brw_eu.h
>> +++ b/src/intel/compiler/brw_eu.h
>> @@ -500,6 +500,10 @@ brw_broadcast(struct brw_codegen *p,
>>struct brw_reg src,
>>struct brw_reg idx);
>>  
>> +void
>> +brw_rounding_mode(struct brw_codegen *p,
>> +  enum brw_rnd_mode mode);
>> +
>>  /***
>>   * brw_eu_util.c:
>>   */
>> diff --git a/src/intel/compiler/brw_eu_defines.h 
>> b/src/intel/compiler/brw_eu_defines.h
>> index da482b73c5..6687883bfb 100644
>> --- a/src/intel/compiler/brw_eu_defines.h
>> +++ b/src/intel/compiler/brw_eu_defines.h
>> @@ -388,6 +388,8 @@ enum opcode {
>> SHADER_OPCODE_TYPED_SURFACE_WRITE,
>> SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
>>  
>> +   SHADER_OPCODE_RND_MODE,
>> +
>> SHADER_OPCODE_MEMORY_FENCE,
>>  
>> SHADER_OPCODE_GEN4_SCRATCH_READ,
>> @@ -1214,4 +1216,18 @@ enum brw_message_target {
>>  /* R0 */
>>  # define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT  27
>>  
>> +/* CR0.0[5:4] Floating-Point Rounding Modes
>> + *  Skylake PRM, Volume 7 Part 1, "Control Register", page 756
>> + */
>> +
>> +#define BRW_CR0_RND_MODE_MASK 0x30
>> +#define BRW_CR0_RND_MODE_SHIFT4
>> +
>> +enum PACKED brw_rnd_mode {
>> +   BRW_RND_MODE_RTNE = 0,  /* Round to Nearest or Even */
>> +   BRW_RND_MODE_RU = 1,/* Round Up, toward +inf */
>> +   BRW_RND_MODE_RD = 2,/* Round Down, toward -inf */
>> +   BRW_RND_MODE_RTZ = 3,   /* Round Toward Zero */
>> +};
>> +
>>  #endif /* BRW_EU_DEFINES_H */
>> diff --git a/src/intel/compiler/brw_eu_emit.c 
>> b/src/intel/compiler/brw_eu_emit.c
>> index 2b38d959d1..8c1e4c5eae 100644
>> --- a/src/intel/compiler/brw_eu_emit.c
>> +++ b/src/intel/compiler/brw_eu_emit.c
>> @@ -3450,3 +3450,36 @@ brw_WAIT(struct brw_codegen *p)
>> brw_inst_set_exec_size(devinfo, insn, BRW_EXECUTE_1);
>> brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
>>  }
>> +
>> +/**
>> + * Changes the floating point rounding mode updating the control register
>> + * field defined at cr0.0[5-6] bits. This function supports the changes to
>> + * RTNE (00), RU (01), RD (10) and RTZ (11) rounding using bitwise 
>> operations.
>> + * Only RTNE and RTZ rounding are enabled at nir.
>> + */
>> +void
>> +brw_rounding_mode(struct brw_codegen *p,
>> +  enum brw_rnd_mode mode)
>> +{
>> +   const unsigned bits  = mode << BRW_CR0_RND_MODE_SHIFT;
> 
> Extra space before '='.
> 

Fixed locally

Thanks.
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Re: [Mesa-dev] [PATCH v3 14/43] i965/fs: Handle 32-bit to 16-bit conversions

2017-10-14 Thread Chema Casanova



On 14/10/17 09:55, Pohjolainen, Topi wrote:
> On Thu, Oct 12, 2017 at 08:38:03PM +0200, Jose Maria Casanova Crespo wrote:
>> From: Alejandro Piñeiro 
>>
>> Conversions to 16-bit need having aligment between the 16-bit
>> and 32-bit types. So the conversion operations unpack 16-bit types
>> to with an stride=2 and then applies a MOV with the conversion.
>>
>> v2 (Jason Ekstrand):
>>   - Avoid the general use of stride=2 for 16-bit register types.
>>
>> Signed-off-by: Eduardo Lima 
>> Signed-off-by: Alejandro Piñeiro 
>> Signed-off-by: Jose Maria Casanova Crespo 
>> ---
>>  src/intel/compiler/brw_fs_nir.cpp | 25 +
>>  1 file changed, 25 insertions(+)
>>
>> diff --git a/src/intel/compiler/brw_fs_nir.cpp 
>> b/src/intel/compiler/brw_fs_nir.cpp
>> index affe65d5e9..6908c7ea02 100644
>> --- a/src/intel/compiler/brw_fs_nir.cpp
>> +++ b/src/intel/compiler/brw_fs_nir.cpp
>> @@ -693,6 +693,31 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, 
>> nir_alu_instr *instr)
>>inst->saturate = instr->dest.saturate;
>>break;
>>  
>> +  /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
>> +   * on the HW gen, it is a special hw opcode or just a MOV, and
>> +   * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
>> +   *
>> +   * But if we want to use that opcode, we need to provide support on
>> +   * different optimizations and lowerings. As right now HF support is
>> +   * only for gen8+, it will be better to use directly the MOV, and use
>> +   * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
>> +   */
>> +
>> +   case nir_op_f2f16:
>> +   case nir_op_i2i16:
>> +   case nir_op_u2u16: {
>> +  /* TODO: Fixing aligment rules for conversions from 32-bits to
>> +   * 16-bit types should be moved to lower_conversions
>> +   */
>> +  fs_reg tmp = bld.vgrf(op[0].type, 1);
>> +  tmp = subscript(tmp, result.type, 0);
>> +  inst = bld.MOV(tmp, op[0]);
>> +  inst->saturate = instr->dest.saturate;
>> +  inst = bld.MOV(result ,tmp);
> 
> Move space after ','
> 

Fixed locally.

Thanks.

>> +  inst->saturate = instr->dest.saturate;
>> +  break;
>> +   }
>> +
>> case nir_op_f2f64:
>> case nir_op_i2f64:
>> case nir_op_u2f64:
>> -- 
>> 2.13.6
>>
>> ___
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>> mesa-dev@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> 
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Re: [Mesa-dev] [PATCH v3 19/43] i965/fs: Support push constants of 16-bit types

2017-10-14 Thread Chema Casanova



On 14/10/17 10:02, Pohjolainen, Topi wrote:
> On Thu, Oct 12, 2017 at 08:38:08PM +0200, Jose Maria Casanova Crespo wrote:
>> We enable the use of 16-bit values in push constants
>> modifying the assign_constant_locations function to work
>> with 16-bit types.
>>
>> The API to access buffers in Vulkan use multiples of 4-byte for
>> offsets and sizes. Current accountability of uniforms based on 4-byte
>> slots will work for 16-bit values if they are allowed to use 32-bit
>> slots. For that, we replace the division by 4 by a DIV_ROUND_UP, so
>> 2-byte elements will use 1 slot instead of 0.
>>
>> We aligns the 16-bit locations after assigning the 32-bit
> 
> s/aligns/align/
> 
Also fixed.

Thanks.

Chema
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[Mesa-dev] [PATCH] meson: build freedreno

2017-10-14 Thread Rob Clark

Signed-off-by: Rob Clark 
---
This applies on top of Dylan's wip/meson-radeonsi branch

 meson.build  |   6 +
 meson_options.txt|   2 +-
 src/gallium/drivers/freedreno/meson.build| 212 +++
 src/gallium/meson.build  |   3 +-
 src/gallium/winsys/freedreno/drm/meson.build |  30 
 5 files changed, 251 insertions(+), 2 deletions(-)
 create mode 100644 src/gallium/drivers/freedreno/meson.build
 create mode 100644 src/gallium/winsys/freedreno/drm/meson.build

diff --git a/meson.build b/meson.build
index bc3bbf41a65..a56fe98a951 100644
--- a/meson.build
+++ b/meson.build
@@ -93,12 +93,14 @@ endif
 with_gallium = false
 with_gallium_radeonsi = false
 with_gallium_nouveau = false
+with_gallium_freedreno = false
 with_gallium_softpipe = false
 _drivers = get_option('gallium-drivers')
 if _drivers != ''
   _split = _drivers.split(',')
   with_gallium_radeonsi = _split.contains('radeonsi')
   with_gallium_nouveau = _split.contains('nouveau')
+  with_gallium_freedreno = _split.contains('freedreno')
   with_gallium_softpipe = _split.contains('swrast')
   with_gallium = true
   with_dri = true
@@ -558,6 +560,7 @@ dep_m = cc.find_library('m', required : false)
 dep_libdrm_amdgpu = []
 dep_libdrm_radeon = []
 dep_libdrm_nouveau = []
+dep_libdrm_freedreno = []
 if with_amd_vk or with_gallium_radeonsi
   dep_libdrm_amdgpu = dependency('libdrm_amdgpu', version : '>= 2.4.84')
 endif
@@ -567,6 +570,9 @@ endif
 if with_gallium_nouveau
   dep_libdrm_nouveau = dependency('libdrm_nouveau', version : '>= 2.4.66')
 endif
+if with_gallium_freedreno
+  deb_libdrm_freedreno = dependency('libdrm_freedreno', version : '>= 2.4.74')
+endif
 
 llvm_modules = ['bitwriter', 'engine', 'mcdisassembler', 'mcjit']
 if with_amd_vk
diff --git a/meson_options.txt b/meson_options.txt
index 71e9ea63555..6b311ac2404 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -46,7 +46,7 @@ option(
 option(
   'gallium-drivers',
   type : 'string',
-  value : 'radeonsi,nouveau,swrast',
+  value : 'radeonsi,nouveau,freedreno,swrast',
   description : 'comma separated list of gallium drivers to build.'
 )
 option(
diff --git a/src/gallium/drivers/freedreno/meson.build 
b/src/gallium/drivers/freedreno/meson.build
new file mode 100644
index 000..2df97ca1f62
--- /dev/null
+++ b/src/gallium/drivers/freedreno/meson.build
@@ -0,0 +1,212 @@
+# Copyright © 2017 Dylan Baker
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+ir3_nir_trig_c = custom_target(
+  'ir3_nir_trig.c',
+  input : 'ir3/ir3_nir_trig.py',
+  output : 'ir3_nir_trig.c',
+  command : [prog_python2, '@INPUT@'],
+  capture : true,
+  depend_files : files('ir3/ir3_nir_trig.py'),
+)
+
+files_libfreedreno = files(
+  'adreno_common.xml.h',
+  'adreno_pm4.xml.h',
+  'disasm.h',
+  'freedreno_batch.c',
+  'freedreno_batch.h',
+  'freedreno_batch_cache.c',
+  'freedreno_batch_cache.h',
+  'freedreno_context.c',
+  'freedreno_context.h',
+  'freedreno_draw.c',
+  'freedreno_draw.h',
+  'freedreno_fence.c',
+  'freedreno_fence.h',
+  'freedreno_gmem.c',
+  'freedreno_gmem.h',
+  'freedreno_program.c',
+  'freedreno_program.h',
+  'freedreno_query.c',
+  'freedreno_query.h',
+  'freedreno_query_acc.c',
+  'freedreno_query_acc.h',
+  'freedreno_query_hw.c',
+  'freedreno_query_hw.h',
+  'freedreno_query_sw.c',
+  'freedreno_query_sw.h',
+  'freedreno_resource.c',
+  'freedreno_resource.h',
+  'freedreno_screen.c',
+  'freedreno_screen.h',
+  'freedreno_state.c',
+  'freedreno_state.h',
+  'freedreno_surface.c',
+  'freedreno_surface.h',
+  'freedreno_texture.c',
+  'freedreno_texture.h',
+  'freedreno_util.c',
+  'freedreno_util.h',
+  'a2xx/a2xx.xml.h',
+  'a2xx/disasm-a2xx.c',
+  'a2xx/fd2_blend.c',
+  'a2xx/fd2_blend.h',
+  'a2xx/fd2_compiler.c',
+  'a2xx/fd2_compiler.h',
+  'a2xx/fd2_context.c',
+  'a2xx/fd2_context.h',
+  'a2xx/fd2_draw.c',
+  'a2xx/fd2_draw.h',
+  'a2xx/fd2_emit.c',
+

[Mesa-dev] [PATCH] svga: fix format_conversion_table breakage

2017-10-14 Thread Brian Paul

The new A1B5G5R5_UNORM, X1B5G5R5_UNORM formats were added in the
wrong place in commit ef874ee450b18e "gallium: Add support for 5551
with the 1-bit field in the low bit."
---
 src/gallium/drivers/svga/svga_format.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_format.c 
b/src/gallium/drivers/svga/svga_format.c
index b6ca9c5..bcaff60 100644
--- a/src/gallium/drivers/svga/svga_format.c
+++ b/src/gallium/drivers/svga/svga_format.c
@@ -58,7 +58,6 @@ static const struct vgpu10_format_entry 
format_conversion_table[] =
{ PIPE_FORMAT_A8R8G8B8_UNORM,SVGA3D_FORMAT_INVALID,  
SVGA3D_FORMAT_INVALID,   0 },
{ PIPE_FORMAT_X8R8G8B8_UNORM,SVGA3D_FORMAT_INVALID,  
SVGA3D_FORMAT_INVALID,   0 },
{ PIPE_FORMAT_B5G5R5A1_UNORM,SVGA3D_FORMAT_INVALID,  
SVGA3D_B5G5R5A1_UNORM,   TF_GEN_MIPS },
-   { PIPE_FORMAT_A1B5G5R5_UNORM,SVGA3D_FORMAT_INVALID,  
SVGA3D_FORMAT_INVALID,   0 },
{ PIPE_FORMAT_B4G4R4A4_UNORM,SVGA3D_FORMAT_INVALID,  
SVGA3D_FORMAT_INVALID,   0 },
{ PIPE_FORMAT_B5G6R5_UNORM,  SVGA3D_FORMAT_INVALID,  
SVGA3D_B5G6R5_UNORM, TF_GEN_MIPS },
{ PIPE_FORMAT_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM,   
SVGA3D_R10G10B10A2_UNORM,TF_GEN_MIPS },
@@ -176,7 +175,6 @@ static const struct vgpu10_format_entry 
format_conversion_table[] =
{ PIPE_FORMAT_R5SG5SB6U_NORM,SVGA3D_FORMAT_INVALID,  
SVGA3D_FORMAT_INVALID,   0 },
{ PIPE_FORMAT_A8B8G8R8_UNORM,SVGA3D_FORMAT_INVALID,  
SVGA3D_FORMAT_INVALID,   0 },
{ PIPE_FORMAT_B5G5R5X1_UNORM,SVGA3D_FORMAT_INVALID,  
SVGA3D_FORMAT_INVALID,   0 },
-   { PIPE_FORMAT_X1B5G5R5_UNORM,SVGA3D_FORMAT_INVALID,  
SVGA3D_FORMAT_INVALID,   0 },
{ PIPE_FORMAT_R10G10B10A2_USCALED,   SVGA3D_R10G10B10A2_UNORM,   
SVGA3D_FORMAT_INVALID,   VF_PUINT_TO_USCALED },
{ PIPE_FORMAT_R11G11B10_FLOAT,   SVGA3D_FORMAT_INVALID,  
SVGA3D_R11G11B10_FLOAT,  TF_GEN_MIPS },
{ PIPE_FORMAT_R9G9B9E5_FLOAT,SVGA3D_FORMAT_INVALID,  
SVGA3D_R9G9B9E5_SHAREDEXP,   0 },
@@ -363,6 +361,8 @@ static const struct vgpu10_format_entry 
format_conversion_table[] =
{ PIPE_FORMAT_ASTC_12x12_SRGB,   SVGA3D_FORMAT_INVALID,  
SVGA3D_FORMAT_INVALID,   0 },
{ PIPE_FORMAT_P016,  SVGA3D_FORMAT_INVALID,  
SVGA3D_FORMAT_INVALID,   0 },
{ PIPE_FORMAT_R10G10B10X2_UNORM, SVGA3D_FORMAT_INVALID,  
SVGA3D_FORMAT_INVALID,   0 },
+   { PIPE_FORMAT_A1B5G5R5_UNORM,SVGA3D_FORMAT_INVALID,  
SVGA3D_FORMAT_INVALID,   0 },
+   { PIPE_FORMAT_X1B5G5R5_UNORM,SVGA3D_FORMAT_INVALID,  
SVGA3D_FORMAT_INVALID,   0 },
 };
 
 
-- 
1.9.1

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[Mesa-dev] [PATCH v2 1/2] freedreno/ir3: use a flag instead of setting PYTHONPATH

2017-10-14 Thread Rob Clark

Similar to 848da662224326ccfbe6647bc82f4f89ca22c762, pass an arg to
ir3_nir_trig.py to add to python path, rather than using $PYTHONPATH,
to prep for meson build support.

Signed-off-by: Rob Clark 
---
 src/gallium/drivers/freedreno/Makefile.am |  2 +-
 src/gallium/drivers/freedreno/ir3/ir3_nir_trig.py | 25 +++
 2 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/freedreno/Makefile.am 
b/src/gallium/drivers/freedreno/Makefile.am
index 128c7fb5990..5cb4c74cb68 100644
--- a/src/gallium/drivers/freedreno/Makefile.am
+++ b/src/gallium/drivers/freedreno/Makefile.am
@@ -12,7 +12,7 @@ AM_CFLAGS = \
 MKDIR_GEN = $(AM_V_at)$(MKDIR_P) $(@D)
 ir3/ir3_nir_trig.c: ir3/ir3_nir_trig.py 
$(top_srcdir)/src/compiler/nir/nir_algebraic.py
$(MKDIR_GEN)
-   $(AM_V_GEN) PYTHONPATH=$(top_srcdir)/src/compiler/nir $(PYTHON2) 
$(PYTHON_FLAGS) $(srcdir)/ir3/ir3_nir_trig.py > $@ || ($(RM) $@; false)
+   $(AM_V_GEN) $(PYTHON2) $(PYTHON_FLAGS) $(srcdir)/ir3/ir3_nir_trig.py -p 
$(top_srcdir)/src/compiler/nir > $@ || ($(RM) $@; false)
 
 noinst_LTLIBRARIES = libfreedreno.la
 
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_nir_trig.py 
b/src/gallium/drivers/freedreno/ir3/ir3_nir_trig.py
index f358f4d6bc4..a0ab9d01903 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_nir_trig.py
+++ b/src/gallium/drivers/freedreno/ir3/ir3_nir_trig.py
@@ -20,13 +20,30 @@
 # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 # IN THE SOFTWARE.
 
-import nir_algebraic
+import argparse
+import sys
 
 trig_workarounds = [
(('fsin', 'x'), ('fsin', ('fsub', ('fmul', 6.283185, ('ffract', ('fadd', 
('fmul', 0.159155, 'x'), 0.5))), 3.141593))),
(('fcos', 'x'), ('fcos', ('fsub', ('fmul', 6.283185, ('ffract', ('fadd', 
('fmul', 0.159155, 'x'), 0.5))), 3.141593))),
 ]
 
-print '#include "ir3_nir.h"'
-print nir_algebraic.AlgebraicPass("ir3_nir_apply_trig_workarounds",
-  trig_workarounds).render()
+
+def main():
+parser = argparse.ArgumentParser()
+parser.add_argument('-p', '--import-path', required=True)
+args = parser.parse_args()
+sys.path.insert(0, args.import_path)
+run()
+
+
+def run():
+import nir_algebraic  # pylint: disable=import-error
+
+print '#include "ir3_nir.h"'
+print nir_algebraic.AlgebraicPass("ir3_nir_apply_trig_workarounds",
+  trig_workarounds).render()
+
+
+if __name__ == '__main__':
+main()
-- 
2.13.6

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[Mesa-dev] [PATCH v2 2/2] meson: build freedreno

2017-10-14 Thread Rob Clark

Signed-off-by: Rob Clark 
---
As before, applies on top of of Dylan's wip/meson-radeonsi branch.  But
now it actually builds freedreno (and fixes some mistakes in v1 that I
hadn't noticed because freedreno wasn't actually getting added to the
build)

 meson.build  |   6 +
 meson_options.txt|   2 +-
 src/gallium/drivers/freedreno/meson.build| 221 +++
 src/gallium/meson.build  |   3 +-
 src/gallium/targets/dri/meson.build  |   5 +
 src/gallium/winsys/freedreno/drm/meson.build |  30 
 6 files changed, 265 insertions(+), 2 deletions(-)
 create mode 100644 src/gallium/drivers/freedreno/meson.build
 create mode 100644 src/gallium/winsys/freedreno/drm/meson.build

diff --git a/meson.build b/meson.build
index bc3bbf41a65..2554f7166cb 100644
--- a/meson.build
+++ b/meson.build
@@ -93,12 +93,14 @@ endif
 with_gallium = false
 with_gallium_radeonsi = false
 with_gallium_nouveau = false
+with_gallium_freedreno = false
 with_gallium_softpipe = false
 _drivers = get_option('gallium-drivers')
 if _drivers != ''
   _split = _drivers.split(',')
   with_gallium_radeonsi = _split.contains('radeonsi')
   with_gallium_nouveau = _split.contains('nouveau')
+  with_gallium_freedreno = _split.contains('freedreno')
   with_gallium_softpipe = _split.contains('swrast')
   with_gallium = true
   with_dri = true
@@ -558,6 +560,7 @@ dep_m = cc.find_library('m', required : false)
 dep_libdrm_amdgpu = []
 dep_libdrm_radeon = []
 dep_libdrm_nouveau = []
+dep_libdrm_freedreno = []
 if with_amd_vk or with_gallium_radeonsi
   dep_libdrm_amdgpu = dependency('libdrm_amdgpu', version : '>= 2.4.84')
 endif
@@ -567,6 +570,9 @@ endif
 if with_gallium_nouveau
   dep_libdrm_nouveau = dependency('libdrm_nouveau', version : '>= 2.4.66')
 endif
+if with_gallium_freedreno
+  dep_libdrm_freedreno = dependency('libdrm_freedreno', version : '>= 2.4.74')
+endif
 
 llvm_modules = ['bitwriter', 'engine', 'mcdisassembler', 'mcjit']
 if with_amd_vk
diff --git a/meson_options.txt b/meson_options.txt
index 71e9ea63555..6b311ac2404 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -46,7 +46,7 @@ option(
 option(
   'gallium-drivers',
   type : 'string',
-  value : 'radeonsi,nouveau,swrast',
+  value : 'radeonsi,nouveau,freedreno,swrast',
   description : 'comma separated list of gallium drivers to build.'
 )
 option(
diff --git a/src/gallium/drivers/freedreno/meson.build 
b/src/gallium/drivers/freedreno/meson.build
new file mode 100644
index 000..191fcffe80c
--- /dev/null
+++ b/src/gallium/drivers/freedreno/meson.build
@@ -0,0 +1,221 @@
+# Copyright © 2017 Dylan Baker
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+ir3_nir_trig_c = custom_target(
+  'ir3_nir_trig.c',
+  input : 'ir3/ir3_nir_trig.py',
+  output : 'ir3_nir_trig.c',
+  command : [prog_python2, '@INPUT@', '-p',
+ join_paths(meson.source_root(), 'src/compiler/nir/')],
+  capture : true,
+  depend_files : files(
+'ir3/ir3_nir_trig.py',
+join_paths(meson.source_root(), 'src/compiler/nir/nir_algebraic.py'),
+  ),
+)
+
+files_libfreedreno = files(
+  'adreno_common.xml.h',
+  'adreno_pm4.xml.h',
+  'disasm.h',
+  'freedreno_batch.c',
+  'freedreno_batch.h',
+  'freedreno_batch_cache.c',
+  'freedreno_batch_cache.h',
+  'freedreno_context.c',
+  'freedreno_context.h',
+  'freedreno_draw.c',
+  'freedreno_draw.h',
+  'freedreno_fence.c',
+  'freedreno_fence.h',
+  'freedreno_gmem.c',
+  'freedreno_gmem.h',
+  'freedreno_program.c',
+  'freedreno_program.h',
+  'freedreno_query.c',
+  'freedreno_query.h',
+  'freedreno_query_acc.c',
+  'freedreno_query_acc.h',
+  'freedreno_query_hw.c',
+  'freedreno_query_hw.h',
+  'freedreno_query_sw.c',
+  'freedreno_query_sw.h',
+  'freedreno_resource.c',
+  'freedreno_resource.h',
+  'freedreno_screen.c',
+  'freedreno_screen.h',
+  'freedreno_state.c',
+  'freedreno_state.h',
+  'freedreno_surface.c',
+  'freed

[Mesa-dev] [PATCH v3 2/2] meson: build freedreno

2017-10-14 Thread Rob Clark

Signed-off-by: Rob Clark 
---
v1: actually build freedreno
v2: corrected installed ${driver}_dri.so name

 meson.build  |   6 +
 meson_options.txt|   2 +-
 src/gallium/drivers/freedreno/meson.build| 221 +++
 src/gallium/meson.build  |   3 +-
 src/gallium/targets/dri/meson.build  |   6 +
 src/gallium/winsys/freedreno/drm/meson.build |  30 
 6 files changed, 266 insertions(+), 2 deletions(-)
 create mode 100644 src/gallium/drivers/freedreno/meson.build
 create mode 100644 src/gallium/winsys/freedreno/drm/meson.build

diff --git a/meson.build b/meson.build
index bc3bbf41a65..2554f7166cb 100644
--- a/meson.build
+++ b/meson.build
@@ -93,12 +93,14 @@ endif
 with_gallium = false
 with_gallium_radeonsi = false
 with_gallium_nouveau = false
+with_gallium_freedreno = false
 with_gallium_softpipe = false
 _drivers = get_option('gallium-drivers')
 if _drivers != ''
   _split = _drivers.split(',')
   with_gallium_radeonsi = _split.contains('radeonsi')
   with_gallium_nouveau = _split.contains('nouveau')
+  with_gallium_freedreno = _split.contains('freedreno')
   with_gallium_softpipe = _split.contains('swrast')
   with_gallium = true
   with_dri = true
@@ -558,6 +560,7 @@ dep_m = cc.find_library('m', required : false)
 dep_libdrm_amdgpu = []
 dep_libdrm_radeon = []
 dep_libdrm_nouveau = []
+dep_libdrm_freedreno = []
 if with_amd_vk or with_gallium_radeonsi
   dep_libdrm_amdgpu = dependency('libdrm_amdgpu', version : '>= 2.4.84')
 endif
@@ -567,6 +570,9 @@ endif
 if with_gallium_nouveau
   dep_libdrm_nouveau = dependency('libdrm_nouveau', version : '>= 2.4.66')
 endif
+if with_gallium_freedreno
+  dep_libdrm_freedreno = dependency('libdrm_freedreno', version : '>= 2.4.74')
+endif
 
 llvm_modules = ['bitwriter', 'engine', 'mcdisassembler', 'mcjit']
 if with_amd_vk
diff --git a/meson_options.txt b/meson_options.txt
index 71e9ea63555..6b311ac2404 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -46,7 +46,7 @@ option(
 option(
   'gallium-drivers',
   type : 'string',
-  value : 'radeonsi,nouveau,swrast',
+  value : 'radeonsi,nouveau,freedreno,swrast',
   description : 'comma separated list of gallium drivers to build.'
 )
 option(
diff --git a/src/gallium/drivers/freedreno/meson.build 
b/src/gallium/drivers/freedreno/meson.build
new file mode 100644
index 000..191fcffe80c
--- /dev/null
+++ b/src/gallium/drivers/freedreno/meson.build
@@ -0,0 +1,221 @@
+# Copyright © 2017 Dylan Baker
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+ir3_nir_trig_c = custom_target(
+  'ir3_nir_trig.c',
+  input : 'ir3/ir3_nir_trig.py',
+  output : 'ir3_nir_trig.c',
+  command : [prog_python2, '@INPUT@', '-p',
+ join_paths(meson.source_root(), 'src/compiler/nir/')],
+  capture : true,
+  depend_files : files(
+'ir3/ir3_nir_trig.py',
+join_paths(meson.source_root(), 'src/compiler/nir/nir_algebraic.py'),
+  ),
+)
+
+files_libfreedreno = files(
+  'adreno_common.xml.h',
+  'adreno_pm4.xml.h',
+  'disasm.h',
+  'freedreno_batch.c',
+  'freedreno_batch.h',
+  'freedreno_batch_cache.c',
+  'freedreno_batch_cache.h',
+  'freedreno_context.c',
+  'freedreno_context.h',
+  'freedreno_draw.c',
+  'freedreno_draw.h',
+  'freedreno_fence.c',
+  'freedreno_fence.h',
+  'freedreno_gmem.c',
+  'freedreno_gmem.h',
+  'freedreno_program.c',
+  'freedreno_program.h',
+  'freedreno_query.c',
+  'freedreno_query.h',
+  'freedreno_query_acc.c',
+  'freedreno_query_acc.h',
+  'freedreno_query_hw.c',
+  'freedreno_query_hw.h',
+  'freedreno_query_sw.c',
+  'freedreno_query_sw.h',
+  'freedreno_resource.c',
+  'freedreno_resource.h',
+  'freedreno_screen.c',
+  'freedreno_screen.h',
+  'freedreno_state.c',
+  'freedreno_state.h',
+  'freedreno_surface.c',
+  'freedreno_surface.h',
+  'freedreno_texture.c',
+  'freedreno_texture.h',
+  'freedreno_util.c',
+  'freedreno_util.h',
+  'a2xx/a2xx.xml.h',
+  'a2xx

Re: [Mesa-dev] [PATCH 1/2] meson: provide Makefile.sources variables to meson build

2017-10-14 Thread Jakob Bornecrantz

On Sat, Oct 14, 2017 at 1:36 AM, Dylan Baker  wrote:
> I'm not sure about this approach, we would need a way to add depends to meson,
> but I'm also worried that calling make adds another dependency that could be
> problematic for windows, and I really don't like the idea of having a
> half-and-half approach with the sources.
>
> Here's what I've been playing with:
> https://github.com/dcbaker/meson/tree/make-import-module
> https://github.com/dcbaker/mesa/tree/wip/meson-makefile-sources
>
> How would you feel about that?

Couldn't you just use the Makefile parser José wrote for the scons
build, that would avoid running make and waiting for a new version of
Meson. Or is there something it is lacking?

We could start out with our own Makefile parser and then move onto one
in Meson once it is upstreamed and that version of meson is commonly
available?

Cheers, Jakob.
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Re: [Mesa-dev] [PATCH] blob: Use intptr_t instead of ssize_t

2017-10-14 Thread Henri Verbeet

On 13 October 2017 at 19:44, Jason Ekstrand  wrote:
> ssize_t is a GNU extension and is not available on Windows or MacOS.

Not to argue against the patch in any way, but ssize_t is POSIX.
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[Mesa-dev] Build fail since configure.ac: rework llvm libs handling for 3.9+

2017-10-14 Thread Andy Furniss


Since

commit 13a53c4f5cdd664fd155c9e78fb46a4387af006c
Author: Emil Velikov 
Date:   Thu Oct 5 11:19:05 2017 +0100

configure.ac: rework llvm libs handling for 3.9+

I am getting 00s of

 /mesa/src/amd/common/. undefined reference to LLVM..

Using git llvm have tried with -DLLVM_APPEND_VC_REV=OFF

My llvm config =

cmake -DCMAKE_INSTALL_PREFIX=/usr -DCMAKE_BUILD_TYPE=Release 
-DLLVM_TARGETS_TO_BUILD="host;AMDGPU" -DLLVM_ENABLE_ASSERTIONS=ON 
-DLLVM_BUILD_LLVM_DYLIB=ON


Mesa config

./autogen.sh --prefix=/usr --sysconfdir=/etc --enable-texture-float 
--enable-opencl --with-egl-platforms=x11,drm,wayland 
--with-gallium-drivers=radeonsi,swrast --with-vulkan-drivers=radeon 
--enable-gbm --enable-shared-glapi --enable-glx-tls --with-dri-drivers=


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Re: [Mesa-dev] Build fail since configure.ac: rework llvm libs handling for 3.9+

2017-10-14 Thread Andy Furniss


Andy Furniss wrote:

Since

commit 13a53c4f5cdd664fd155c9e78fb46a4387af006c
Author: Emil Velikov 
Date:   Thu Oct 5 11:19:05 2017 +0100

 configure.ac: rework llvm libs handling for 3.9+

I am getting 00s of

 /mesa/src/amd/common/. undefined reference to LLVM..

Using git llvm have tried with -DLLVM_APPEND_VC_REV=OFF

My llvm config =

cmake -DCMAKE_INSTALL_PREFIX=/usr -DCMAKE_BUILD_TYPE=Release 
-DLLVM_TARGETS_TO_BUILD="host;AMDGPU" -DLLVM_ENABLE_ASSERTIONS=ON 
-DLLVM_BUILD_LLVM_DYLIB=ON


Build is OK with llvm built with -DLLVM_LINK_LLVM_DYLIB=ON

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[Mesa-dev] [PATCH 2/9] radv: Change cache datastructures for combined pipelines.

2017-10-14 Thread Timothy Arceri

From: Bas Nieuwenhuizen 

Signed-off-by: Timothy Arceri 
---
 src/amd/vulkan/radv_pipeline_cache.c | 102 ++-
 1 file changed, 64 insertions(+), 38 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline_cache.c 
b/src/amd/vulkan/radv_pipeline_cache.c
index fc99b43fff..fc34e07822 100644
--- a/src/amd/vulkan/radv_pipeline_cache.c
+++ b/src/amd/vulkan/radv_pipeline_cache.c
@@ -24,31 +24,34 @@
 #include "util/mesa-sha1.h"
 #include "util/debug.h"
 #include "util/disk_cache.h"
 #include "util/u_atomic.h"
 #include "radv_debug.h"
 #include "radv_private.h"
 #include "radv_shader.h"
 
 #include "ac_nir_to_llvm.h"
 
+struct cache_entry_variant_info {
+   struct ac_shader_variant_info variant_info;
+   struct ac_shader_config config;
+   uint32_t rsrc1, rsrc2;
+};
+
 struct cache_entry {
union {
unsigned char sha1[20];
uint32_t sha1_dw[5];
};
-   uint32_t code_size;
-   struct ac_shader_variant_info variant_info;
-   struct ac_shader_config config;
-   uint32_t rsrc1, rsrc2;
-   struct radv_shader_variant *variant;
-   uint32_t code[0];
+   uint32_t code_sizes[MESA_SHADER_STAGES];
+   struct radv_shader_variant *variants[MESA_SHADER_STAGES];
+   char code[0];
 };
 
 void
 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
 struct radv_device *device)
 {
cache->device = device;
pthread_mutex_init(&cache->mutex, NULL);
 
cache->modified = false;
@@ -65,33 +68,39 @@ radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
cache->table_size = 0;
else
memset(cache->hash_table, 0, byte_size);
 }
 
 void
 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache)
 {
for (unsigned i = 0; i < cache->table_size; ++i)
if (cache->hash_table[i]) {
-   if (cache->hash_table[i]->variant)
-   radv_shader_variant_destroy(cache->device,
-   
cache->hash_table[i]->variant);
+   for(int j = 0; j < MESA_SHADER_STAGES; ++j)  {
+   if (cache->hash_table[i]->variants[j])
+   
radv_shader_variant_destroy(cache->device,
+   
cache->hash_table[i]->variants[j]);
+   }
vk_free(&cache->alloc, cache->hash_table[i]);
}
pthread_mutex_destroy(&cache->mutex);
free(cache->hash_table);
 }
 
 static uint32_t
 entry_size(struct cache_entry *entry)
 {
-   return sizeof(*entry) + entry->code_size;
+   size_t ret = sizeof(*entry);
+   for (int i = 0; i < MESA_SHADER_STAGES; ++i)
+   if (entry->code_sizes[i])
+   ret += sizeof(struct cache_entry_variant_info) + 
entry->code_sizes[i];
+   return ret;
 }
 
 void
 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
 const char *entrypoint,
 const VkSpecializationInfo *spec_info,
 const struct radv_pipeline_layout *layout,
 const struct ac_shader_variant_key *key,
 uint32_t flags)
 {
@@ -172,42 +181,47 @@ radv_create_shader_variant_from_pipeline_cache(struct 
radv_device *device,
uint8_t disk_sha1[20];
disk_cache_compute_key(device->physical_device->disk_cache,
   sha1, 20, disk_sha1);
entry = (struct cache_entry *)
disk_cache_get(device->physical_device->disk_cache,
   disk_sha1, NULL);
if (!entry)
return NULL;
}
 
-   if (!entry->variant) {
+   if (!entry->variants[0]) {
struct radv_shader_variant *variant;
+   char *p = entry->code;
+   struct cache_entry_variant_info info;
 
variant = calloc(1, sizeof(struct radv_shader_variant));
if (!variant)
return NULL;
 
-   variant->code_size = entry->code_size;
-   variant->config = entry->config;
-   variant->info = entry->variant_info;
-   variant->rsrc1 = entry->rsrc1;
-   variant->rsrc2 = entry->rsrc2;
+   memcpy(&info, p, sizeof(struct cache_entry_variant_info));
+   p += sizeof(struct cache_entry_variant_info);
+
+   variant->code_size = entry->code_sizes[0];
+   variant->config = info.config;
+   variant->info = info.variant_info;
+   variant->rsrc1 = info.rsrc1;
+   variant->rsrc2 = info.rsrc2;
variant->ref_count = 1;
 
void *ptr = radv_alloc_shader_memory(device, variant);
-

[Mesa-dev] [PATCH 3/9] radv: Add multiple shader cache store & load functions.

2017-10-14 Thread Timothy Arceri

From: Bas Nieuwenhuizen 

Signed-off-by: Timothy Arceri 
---
 src/amd/vulkan/radv_pipeline_cache.c | 155 +++
 src/amd/vulkan/radv_private.h|  14 
 2 files changed, 169 insertions(+)

diff --git a/src/amd/vulkan/radv_pipeline_cache.c 
b/src/amd/vulkan/radv_pipeline_cache.c
index fc34e07822..15b159a698 100644
--- a/src/amd/vulkan/radv_pipeline_cache.c
+++ b/src/amd/vulkan/radv_pipeline_cache.c
@@ -210,20 +210,83 @@ radv_create_shader_variant_from_pipeline_cache(struct 
radv_device *device,
void *ptr = radv_alloc_shader_memory(device, variant);
memcpy(ptr, p, entry->code_sizes[0]);
 
entry->variants[0] = variant;
}
 
p_atomic_inc(&entry->variants[0]->ref_count);
return entry->variants[0];
 }
 
+bool
+radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
+   struct radv_pipeline_cache 
*cache,
+   const unsigned char *sha1,
+   struct radv_shader_variant 
**variants)
+{
+   struct cache_entry *entry;
+   if (cache)
+   entry = radv_pipeline_cache_search(cache, sha1);
+   else
+   entry = radv_pipeline_cache_search(device->mem_cache, sha1);
+
+   if (!entry) {
+   if (!device->physical_device->disk_cache)
+   return false;
+
+   uint8_t disk_sha1[20];
+   disk_cache_compute_key(device->physical_device->disk_cache,
+  sha1, 20, disk_sha1);
+   entry = (struct cache_entry *)
+   disk_cache_get(device->physical_device->disk_cache,
+  disk_sha1, NULL);
+   if (!entry)
+   return false;
+   }
+
+   char *p = entry->code;
+   for(int i = 0; i < MESA_SHADER_STAGES; ++i) {
+   if (!entry->variants[i] && entry->code_sizes[i]) {
+   struct radv_shader_variant *variant;
+   struct cache_entry_variant_info info;
+
+   variant = calloc(1, sizeof(struct radv_shader_variant));
+   if (!variant)
+   return false;
+
+   memcpy(&info, p, sizeof(struct 
cache_entry_variant_info));
+   p += sizeof(struct cache_entry_variant_info);
+
+   variant->config = info.config;
+   variant->info = info.variant_info;
+   variant->rsrc1 = info.rsrc1;
+   variant->rsrc2 = info.rsrc2;
+   variant->code_size = entry->code_sizes[i];
+   variant->ref_count = 1;
+
+   void *ptr = radv_alloc_shader_memory(device, variant);
+   memcpy(ptr, p, entry->code_sizes[i]);
+   p += entry->code_sizes[i];
+
+   entry->variants[i] = variant;
+   }
+
+   }
+
+   for (int i = 0; i < MESA_SHADER_STAGES; ++i)
+   if (entry->variants[i])
+   p_atomic_inc(&entry->variants[i]->ref_count);
+
+   memcpy(variants, entry->variants, sizeof(entry->variants));
+   return true;
+}
+
 
 static void
 radv_pipeline_cache_set_entry(struct radv_pipeline_cache *cache,
  struct cache_entry *entry)
 {
const uint32_t mask = cache->table_size - 1;
const uint32_t start = entry->sha1_dw[0];
 
/* We'll always be able to insert when we get here. */
assert(cache->kernel_count < cache->table_size / 2);
@@ -353,20 +416,112 @@ radv_pipeline_cache_insert_shader(struct radv_device 
*device,
entry->variants[0] = variant;
p_atomic_inc(&variant->ref_count);
 
radv_pipeline_cache_add_entry(cache, entry);
 
cache->modified = true;
pthread_mutex_unlock(&cache->mutex);
return variant;
 }
 
+void
+radv_pipeline_cache_insert_shaders(struct radv_device *device,
+  struct radv_pipeline_cache *cache,
+  const unsigned char *sha1,
+  struct radv_shader_variant **variants,
+  const void *const *codes,
+  const unsigned *code_sizes)
+{
+   if (!cache)
+   cache = device->mem_cache;
+
+   pthread_mutex_lock(&cache->mutex);
+   struct cache_entry *entry = radv_pipeline_cache_search_unlocked(cache, 
sha1);
+   if (entry) {
+   for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
+   if (entry->variants[i]) {
+   radv_shader_variant_destroy(cache->device, 
variants[i]);
+   variants[i] = entry->variants[i];
+

[Mesa-dev] [PATCH 5/9] radv: add radv_create_shaders() helper

2017-10-14 Thread Timothy Arceri

From: Bas Nieuwenhuizen 

This is a combined shader creation helper than will help us to
create the shaders for each stage at once. This will allow us to
do some link time optimisations.

Signed-off-by: Timothy Arceri 
---
 src/amd/vulkan/radv_pipeline.c   | 130 +++
 src/amd/vulkan/radv_pipeline_cache.c |   3 +-
 2 files changed, 132 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 415a6cd62b..f923027036 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1736,20 +1736,150 @@ static void calculate_ps_inputs(struct radv_pipeline 
*pipeline)
 
flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << 
ps_offset));
 
pipeline->graphics.ps_input_cntl[ps_offset] = 
offset_to_ps_input(vs_offset, flat_shade);
++ps_offset;
}
 
pipeline->graphics.ps_input_cntl_num = ps_offset;
 }
 
+static
+void radv_create_shaders(struct radv_pipeline *pipeline,
+ struct radv_device *device,
+ struct radv_pipeline_cache *cache,
+ struct ac_shader_variant_key *keys,
+ const VkPipelineShaderStageCreateInfo **pStages)
+{
+   struct radv_shader_module fs_m = {0};
+   struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
+   nir_shader *nir[MESA_SHADER_STAGES] = {0};
+   void *codes[MESA_SHADER_STAGES] = {0};
+   unsigned code_sizes[MESA_SHADER_STAGES] = {0};
+   unsigned char hash[20], gs_copy_hash[20];
+
+   for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
+   if (pStages[i]) {
+   modules[i] = 
radv_shader_module_from_handle(pStages[i]->module);
+   if (modules[i]->nir)
+   _mesa_sha1_compute(modules[i]->nir->info.name,
+  
strlen(modules[i]->nir->info.name),
+  modules[i]->sha1);
+   }
+   }
+
+   radv_hash_shaders(hash, pStages, pipeline->layout, keys, 
get_hash_flags(device));
+   memcpy(gs_copy_hash, hash, 20);
+   gs_copy_hash[0] ^= 1;
+
+   if (modules[MESA_SHADER_GEOMETRY]) {
+   pipeline->gs_copy_shader =
+   radv_create_shader_variant_from_pipeline_cache(
+   pipeline->device,
+   cache,
+   gs_copy_hash);
+   }
+
+   if (radv_create_shader_variants_from_pipeline_cache(device, cache, 
hash, pipeline->shaders) &&
+   (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader))
+   return;
+
+   if (!modules[MESA_SHADER_FRAGMENT]) {
+   nir_builder fs_b;
+   nir_builder_init_simple_shader(&fs_b, NULL, 
MESA_SHADER_FRAGMENT, NULL);
+   fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
+   fs_m.nir = fs_b.shader;
+   modules[MESA_SHADER_FRAGMENT] = &fs_m;
+   }
+
+   for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
+   const VkPipelineShaderStageCreateInfo *stage = pStages[i];
+
+   if (!modules[i])
+   continue;
+
+   nir[i] = radv_shader_compile_to_nir(device, modules[i],
+   stage ? stage->pName : 
"main", i,
+   stage ? 
stage->pSpecializationInfo : NULL);
+   pipeline->active_stages |= mesa_to_vk_shader_stage(i);
+   }
+
+   if (nir[MESA_SHADER_TESS_CTRL]) {
+   /* TODO: This is no longer used as a key we should refactor 
this */
+   if (keys)
+   keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = 
nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
+
+   nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], 
nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
+   }
+
+   if (nir[MESA_SHADER_FRAGMENT]) {
+   pipeline->shaders[MESA_SHADER_FRAGMENT] =
+   radv_shader_variant_create(device, 
modules[MESA_SHADER_FRAGMENT], nir[MESA_SHADER_FRAGMENT],
+  pipeline->layout, keys ? 
keys + MESA_SHADER_FRAGMENT : 0,
+  
&codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
+
+   /* TODO: These are no longer used as keys we should refactor 
this */
+   if (keys) {
+   keys[MESA_SHADER_VERTEX].vs.export_prim_id =
+   
pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
+   keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
+   
pipeline->shaders[MESA_SHADER_FRAGMENT]->info

[Mesa-dev] [PATCH 8/9] radv: reuse the multiple shader store & load functions for gs copy variant

2017-10-14 Thread Timothy Arceri

---
 src/amd/vulkan/radv_pipeline.c   |  27 +---
 src/amd/vulkan/radv_pipeline_cache.c | 127 ---
 src/amd/vulkan/radv_private.h|  12 +---
 3 files changed, 17 insertions(+), 149 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 4bb9fbb15b..e95925fda5 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1544,25 +1544,23 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
   
strlen(modules[i]->nir->info.name),
   modules[i]->sha1);
}
}
 
radv_hash_shaders(hash, pStages, pipeline->layout, keys, 
get_hash_flags(device));
memcpy(gs_copy_hash, hash, 20);
gs_copy_hash[0] ^= 1;
 
if (modules[MESA_SHADER_GEOMETRY]) {
-   pipeline->gs_copy_shader =
-   radv_create_shader_variant_from_pipeline_cache(
-   pipeline->device,
-   cache,
-   gs_copy_hash);
+   struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
+   radv_create_shader_variants_from_pipeline_cache(device, cache, 
gs_copy_hash, variants);
+   pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
}
 
if (radv_create_shader_variants_from_pipeline_cache(device, cache, 
hash, pipeline->shaders) &&
(!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader))
return;
 
if (!modules[MESA_SHADER_FRAGMENT]) {
nir_builder fs_b;
nir_builder_init_simple_shader(&fs_b, NULL, 
MESA_SHADER_FRAGMENT, NULL);
fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
@@ -1622,26 +1620,33 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
void *gs_copy_code = NULL;
unsigned gs_copy_code_size = 0;
if (!pipeline->gs_copy_shader) {
pipeline->gs_copy_shader = radv_create_gs_copy_shader(
device, nir[MESA_SHADER_GEOMETRY], 
&gs_copy_code,
&gs_copy_code_size,

keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
}
 
if (pipeline->gs_copy_shader) {
-   pipeline->gs_copy_shader =
-   radv_pipeline_cache_insert_shader(device, cache,
- gs_copy_hash,
- 
pipeline->gs_copy_shader,
- gs_copy_code,
- 
gs_copy_code_size);
+   void *code[MESA_SHADER_STAGES] = {0};
+   unsigned code_size[MESA_SHADER_STAGES] = {0};
+   struct radv_shader_variant 
*variants[MESA_SHADER_STAGES] = {0};
+
+   code[MESA_SHADER_GEOMETRY] = gs_copy_code;
+   code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
+   variants[MESA_SHADER_GEOMETRY] = 
pipeline->gs_copy_shader;
+
+   radv_pipeline_cache_insert_shaders(device, cache,
+  gs_copy_hash,
+  variants,
+  (const void**)code,
+  code_size);
}
free(gs_copy_code);
}
 
radv_pipeline_cache_insert_shaders(device, cache, hash, 
pipeline->shaders,
   (const void**)codes, code_sizes);
 
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
free(codes[i]);
if (modules[i] && !modules[i]->nir)
diff --git a/src/amd/vulkan/radv_pipeline_cache.c 
b/src/amd/vulkan/radv_pipeline_cache.c
index d29098eea0..1e8a703ce2 100644
--- a/src/amd/vulkan/radv_pipeline_cache.c
+++ b/src/amd/vulkan/radv_pipeline_cache.c
@@ -163,74 +163,20 @@ radv_pipeline_cache_search(struct radv_pipeline_cache 
*cache,
 
pthread_mutex_lock(&cache->mutex);
 
entry = radv_pipeline_cache_search_unlocked(cache, sha1);
 
pthread_mutex_unlock(&cache->mutex);
 
return entry;
 }
 
-struct radv_shader_variant *
-radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
-  struct radv_pipeline_cache 
*cache,
-  const unsigned char *sha1)
-{
-   struct cache_entry *entry = NULL;
-
-   if (cache)
-   entry = radv_p

[Mesa-dev] [PATCH 1/9] radv: reorder init function calls

2017-10-14 Thread Timothy Arceri

---
 src/amd/vulkan/radv_pipeline.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 5e409ce767..415a6cd62b 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1759,30 +1759,30 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
if (subpass->view_mask)
has_view_index = true;
if (alloc == NULL)
alloc = &device->alloc;
 
pipeline->device = device;
pipeline->layout = 
radv_pipeline_layout_from_handle(pCreateInfo->layout);
 
radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
+   radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
+
const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 
0, };
struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
pStages[stage] = &pCreateInfo->pStages[i];
modules[stage] = 
radv_shader_module_from_handle(pStages[stage]->module);
}
 
-   radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
-
if (!modules[MESA_SHADER_FRAGMENT]) {
nir_builder fs_b;
nir_builder_init_simple_shader(&fs_b, NULL, 
MESA_SHADER_FRAGMENT, NULL);
fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
fs_m.nir = fs_b.shader;
modules[MESA_SHADER_FRAGMENT] = &fs_m;
}
 
if (modules[MESA_SHADER_FRAGMENT]) {
struct ac_shader_variant_key key = {0};
-- 
2.13.6

___
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mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 6/9] radv: switch to using radv_create_shaders()

2017-10-14 Thread Timothy Arceri

---
 src/amd/vulkan/radv_pipeline.c | 114 +++--
 1 file changed, 29 insertions(+), 85 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index f923027036..446e14226f 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1354,31 +1354,30 @@ radv_pipeline_init_dynamic_state(struct radv_pipeline 
*pipeline,

pCreateInfo->pDepthStencilState->front.reference;
dynamic->stencil_reference.back =
pCreateInfo->pDepthStencilState->back.reference;
}
}
 
pipeline->dynamic_state_mask = states;
 }
 
 static struct ac_shader_variant_key
-radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool 
as_es, bool as_ls, bool export_prim_id)
+radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool 
as_es, bool as_ls)
 {
struct ac_shader_variant_key key;
const VkPipelineVertexInputStateCreateInfo *input_state =
 pCreateInfo->pVertexInputState;
 
memset(&key, 0, sizeof(key));
key.vs.instance_rate_inputs = 0;
key.vs.as_es = as_es;
key.vs.as_ls = as_ls;
-   key.vs.export_prim_id = export_prim_id;
 
for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; 
++i) {
unsigned binding;
binding = input_state->pVertexAttributeDescriptions[i].binding;
if (input_state->pVertexBindingDescriptions[binding].inputRate)
key.vs.instance_rate_inputs |= 1u << 
input_state->pVertexAttributeDescriptions[i].location;
}
return key;
 }
 
@@ -1874,131 +1873,80 @@ void radv_create_shaders(struct radv_pipeline 
*pipeline,
 }
 
 static VkResult
 radv_pipeline_init(struct radv_pipeline *pipeline,
   struct radv_device *device,
   struct radv_pipeline_cache *cache,
   const VkGraphicsPipelineCreateInfo *pCreateInfo,
   const struct radv_graphics_pipeline_create_info *extra,
   const VkAllocationCallbacks *alloc)
 {
-   struct radv_shader_module fs_m = {0};
VkResult result;
bool has_view_index = false;
 
RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
if (subpass->view_mask)
has_view_index = true;
if (alloc == NULL)
alloc = &device->alloc;
 
pipeline->device = device;
pipeline->layout = 
radv_pipeline_layout_from_handle(pCreateInfo->layout);
 
radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
 
const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 
0, };
-   struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
pStages[stage] = &pCreateInfo->pStages[i];
-   modules[stage] = 
radv_shader_module_from_handle(pStages[stage]->module);
}
 
-   if (!modules[MESA_SHADER_FRAGMENT]) {
-   nir_builder fs_b;
-   nir_builder_init_simple_shader(&fs_b, NULL, 
MESA_SHADER_FRAGMENT, NULL);
-   fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
-   fs_m.nir = fs_b.shader;
-   modules[MESA_SHADER_FRAGMENT] = &fs_m;
-   }
-
-   if (modules[MESA_SHADER_FRAGMENT]) {
-   struct ac_shader_variant_key key = {0};
-   key.fs.col_format = 
pipeline->graphics.blend.spi_shader_col_format;
-   if (pCreateInfo->pMultisampleState &&
-   pCreateInfo->pMultisampleState->rasterizationSamples > 1)
-   key.fs.multisample = true;
+   struct ac_shader_variant_key keys[MESA_SHADER_STAGES];
+   memset(keys, 0, sizeof(keys));
 
-   if (pipeline->device->physical_device->rad_info.chip_class < VI)
-   radv_pipeline_compute_get_int_clamp(pCreateInfo, 
&key.fs.is_int8, &key.fs.is_int10);
-
-   const VkPipelineShaderStageCreateInfo *stage = 
pStages[MESA_SHADER_FRAGMENT];
-
-   pipeline->shaders[MESA_SHADER_FRAGMENT] =
-radv_pipeline_compile(pipeline, cache, 
modules[MESA_SHADER_FRAGMENT],
-  stage ? stage->pName : "main",
-  MESA_SHADER_FRAGMENT,
-  stage ? 
stage->pSpecializationInfo : NULL,
-  pipeline->layout, &key);
-   pipeline->active_stages |= 
mesa_

[Mesa-dev] [PATCH 4/9] radv: add radv_hash_shaders() helper

2017-10-14 Thread Timothy Arceri

From: Bas Nieuwenhuizen 

This will be used to create a hash of the combined shaders in the
pipeline.

Signed-off-by: Timothy Arceri 
---
 src/amd/vulkan/radv_pipeline_cache.c | 33 +
 src/amd/vulkan/radv_private.h|  7 +++
 2 files changed, 40 insertions(+)

diff --git a/src/amd/vulkan/radv_pipeline_cache.c 
b/src/amd/vulkan/radv_pipeline_cache.c
index 15b159a698..feffb4e77b 100644
--- a/src/amd/vulkan/radv_pipeline_cache.c
+++ b/src/amd/vulkan/radv_pipeline_cache.c
@@ -115,20 +115,53 @@ radv_hash_shader(unsigned char *hash, struct 
radv_shader_module *module,
_mesa_sha1_update(&ctx, layout->sha1, sizeof(layout->sha1));
if (spec_info) {
_mesa_sha1_update(&ctx, spec_info->pMapEntries,
  spec_info->mapEntryCount * sizeof 
spec_info->pMapEntries[0]);
_mesa_sha1_update(&ctx, spec_info->pData, spec_info->dataSize);
}
_mesa_sha1_update(&ctx, &flags, 4);
_mesa_sha1_final(&ctx, hash);
 }
 
+void
+radv_hash_shaders(unsigned char *hash,
+ const VkPipelineShaderStageCreateInfo **stages,
+ const struct radv_pipeline_layout *layout,
+ const struct ac_shader_variant_key *keys,
+ uint32_t flags)
+{
+   struct mesa_sha1 ctx;
+
+   _mesa_sha1_init(&ctx);
+   if (keys)
+   _mesa_sha1_update(&ctx, keys, sizeof(*keys) * 
MESA_SHADER_STAGES);
+   if (layout)
+   _mesa_sha1_update(&ctx, layout->sha1, sizeof(layout->sha1));
+
+   for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
+   if (stages[i]) {
+   RADV_FROM_HANDLE(radv_shader_module, module, 
stages[i]->module);
+   const VkSpecializationInfo *spec_info = 
stages[i]->pSpecializationInfo;
+
+   _mesa_sha1_update(&ctx, module->sha1, 
sizeof(module->sha1));
+   _mesa_sha1_update(&ctx, stages[i]->pName, 
strlen(stages[i]->pName));
+   if (spec_info) {
+   _mesa_sha1_update(&ctx, spec_info->pMapEntries,
+ spec_info->mapEntryCount * 
sizeof spec_info->pMapEntries[0]);
+   _mesa_sha1_update(&ctx, spec_info->pData, 
spec_info->dataSize);
+   }
+   }
+   }
+   _mesa_sha1_update(&ctx, &flags, 4);
+   _mesa_sha1_final(&ctx, hash);
+}
+
 
 static struct cache_entry *
 radv_pipeline_cache_search_unlocked(struct radv_pipeline_cache *cache,
const unsigned char *sha1)
 {
const uint32_t mask = cache->table_size - 1;
const uint32_t start = (*(uint32_t *) sha1);
 
if (cache->table_size == 0)
return NULL;
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index b0cb8679fd..110d141085 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -980,20 +980,27 @@ struct ac_shader_variant_key;
 #define RADV_HASH_SHADER_SISCHED (1 << 1)
 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
 void
 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
 const char *entrypoint,
 const VkSpecializationInfo *spec_info,
 const struct radv_pipeline_layout *layout,
 const struct ac_shader_variant_key *key,
 uint32_t flags);
 
+void
+radv_hash_shaders(unsigned char *hash,
+ const VkPipelineShaderStageCreateInfo **stages,
+ const struct radv_pipeline_layout *layout,
+ const struct ac_shader_variant_key *keys,
+ uint32_t flags);
+
 static inline gl_shader_stage
 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
 {
assert(__builtin_popcount(vk_stage) == 1);
return ffs(vk_stage) - 1;
 }
 
 static inline VkShaderStageFlagBits
 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
 {
-- 
2.13.6

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[Mesa-dev] RADV initial NIR linking support

2017-10-14 Thread Timothy Arceri

This initial linking support removes unused varyings across
stages.

Future improvements include enabling removing unused varying
components [1], varying packing (in progress), and varying
array splitting.

I've tried to run the series on the public Vulkan CTS but I
seem to be hitting an existing issue that locks up my machine [2].

Sascha Willems demo results:

computecullandlod 39 -> 41 fps
pipelines ~6100 -> ~6200 fps

5 changed files with 375 additions and 406 deletions.

[1] https://patchwork.freedesktop.org/series/31781/
[2] 
dEQP-VK.pipeline.render_to_image.core.1d_array.huge.width_layers.r8g8b8a8_unorm_d32_sfloat_s8_uint
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[Mesa-dev] [PATCH 9/9] radv: Link shaders.

2017-10-14 Thread Timothy Arceri

From: Bas Nieuwenhuizen 

Here we make use of NIR the linking helpers to remove unused
varyings.

Sascha Willems demo results:

computecullandlod 39 -> 41 fps
pipelines ~6100 -> ~6200 fps

Signed-off-by: Bas Nieuwenhuizen 
Signed-off-by: Timothy Arceri 
---
 src/amd/vulkan/radv_pipeline.c | 42 ++
 src/amd/vulkan/radv_shader.c   |  2 +-
 src/amd/vulkan/radv_shader.h   |  3 +++
 3 files changed, 46 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index e95925fda5..9e0b494802 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1515,20 +1515,60 @@ static void calculate_ps_inputs(struct radv_pipeline 
*pipeline)
 
flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << 
ps_offset));
 
pipeline->graphics.ps_input_cntl[ps_offset] = 
offset_to_ps_input(vs_offset, flat_shade);
++ps_offset;
}
 
pipeline->graphics.ps_input_cntl_num = ps_offset;
 }
 
+static void
+radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
+{
+   nir_shader* ordered_shaders[MESA_SHADER_STAGES];
+   int shader_count = 0;
+
+   if(shaders[MESA_SHADER_FRAGMENT]) {
+   ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
+   }
+   if(shaders[MESA_SHADER_GEOMETRY]) {
+   ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
+   }
+   if(shaders[MESA_SHADER_TESS_EVAL]) {
+   ordered_shaders[shader_count++] = 
shaders[MESA_SHADER_TESS_EVAL];
+   }
+   if(shaders[MESA_SHADER_TESS_CTRL]) {
+   ordered_shaders[shader_count++] = 
shaders[MESA_SHADER_TESS_CTRL];
+   }
+   if(shaders[MESA_SHADER_VERTEX]) {
+   ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
+   }
+
+   for (int i = 1; i < shader_count; ++i)  {
+   nir_remove_dead_variables(ordered_shaders[i],
+ nir_var_shader_out);
+   nir_remove_dead_variables(ordered_shaders[i - 1],
+ nir_var_shader_in);
+
+   bool progress = nir_remove_unused_varyings(ordered_shaders[i],
+  ordered_shaders[i - 
1]);
+
+   if (progress) {
+   nir_lower_global_vars_to_local(ordered_shaders[i]);
+   radv_optimize_nir(ordered_shaders[i]);
+   nir_lower_global_vars_to_local(ordered_shaders[i - 1]);
+   radv_optimize_nir(ordered_shaders[i - 1]);
+   }
+   }
+}
+
 static
 void radv_create_shaders(struct radv_pipeline *pipeline,
  struct radv_device *device,
  struct radv_pipeline_cache *cache,
  struct ac_shader_variant_key *keys,
  const VkPipelineShaderStageCreateInfo **pStages)
 {
struct radv_shader_module fs_m = {0};
struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
nir_shader *nir[MESA_SHADER_STAGES] = {0};
@@ -1598,20 +1638,22 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
if (keys) {
keys[MESA_SHADER_VERTEX].vs.export_prim_id =

pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =

pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
}
 
pipeline->active_stages |= 
mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
}
 
+   radv_link_shaders(pipeline, nir);
+
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
if(modules[i] && !pipeline->shaders[i]) {
pipeline->shaders[i] = 
radv_shader_variant_create(device, modules[i], nir[i],
  
pipeline->layout,
  keys 
? keys + i : 0, &codes[i],
  
&code_sizes[i]);
 
pipeline->active_stages |= mesa_to_vk_shader_stage(i);
}
}
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index d4bef9792e..055787a705 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -103,21 +103,21 @@ void radv_DestroyShaderModule(
 {
RADV_FROM_HANDLE(radv_device, device, _device);
RADV_FROM_HANDLE(radv_shader_module, module, _module);
 
if (!module)
return;
 
vk_free2(&device->alloc, pAllocator, module);
 }
 
-static void
+void
 radv_optimize_nir(struct nir_shader *shader)
 {
 bool progress;

[Mesa-dev] [PATCH 7/9] radv: remove some now unused shader compile code

2017-10-14 Thread Timothy Arceri

---
 src/amd/vulkan/radv_pipeline.c   | 220 ---
 src/amd/vulkan/radv_pipeline_cache.c |  26 -
 src/amd/vulkan/radv_private.h|   8 --
 3 files changed, 254 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 446e14226f..4bb9fbb15b 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -92,240 +92,20 @@ static uint32_t get_hash_flags(struct radv_device *device)
 {
uint32_t hash_flags = 0;
 
if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
hash_flags |= RADV_HASH_SHADER_SISCHED;
return hash_flags;
 }
 
-static struct radv_shader_variant *
-radv_pipeline_compile(struct radv_pipeline *pipeline,
- struct radv_pipeline_cache *cache,
- struct radv_shader_module *module,
- const char *entrypoint,
- gl_shader_stage stage,
- const VkSpecializationInfo *spec_info,
- struct radv_pipeline_layout *layout,
- const struct ac_shader_variant_key *key)
-{
-   unsigned char sha1[20];
-   unsigned char gs_copy_sha1[20];
-   struct radv_shader_variant *variant;
-   nir_shader *nir;
-   void *code = NULL;
-   unsigned code_size = 0;
-   unsigned hash_flags = get_hash_flags(pipeline->device);
-   if (module->nir)
-   _mesa_sha1_compute(module->nir->info.name,
-  strlen(module->nir->info.name),
-  module->sha1);
-
-   radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 
hash_flags);
-   if (stage == MESA_SHADER_GEOMETRY)
-   radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
-layout, key, hash_flags | 
RADV_HASH_SHADER_IS_GEOM_COPY_SHADER);
-
-   variant = 
radv_create_shader_variant_from_pipeline_cache(pipeline->device,
-cache,
-sha1);
-
-   if (stage == MESA_SHADER_GEOMETRY) {
-   pipeline->gs_copy_shader =
-   radv_create_shader_variant_from_pipeline_cache(
-   pipeline->device,
-   cache,
-   gs_copy_sha1);
-   }
-
-   if (variant &&
-   (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
-   return variant;
-
-   nir = radv_shader_compile_to_nir(pipeline->device,
-module, entrypoint, stage,
-spec_info);
-   if (nir == NULL)
-   return NULL;
-
-   if (!variant) {
-   variant = radv_shader_variant_create(pipeline->device, module, 
nir,
-layout, key, &code,
-&code_size);
-   }
-
-   if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
-   void *gs_copy_code = NULL;
-   unsigned gs_copy_code_size = 0;
-   pipeline->gs_copy_shader = radv_create_gs_copy_shader(
-   pipeline->device, nir, &gs_copy_code,
-   &gs_copy_code_size, key->has_multiview_view_index);
-
-   if (pipeline->gs_copy_shader) {
-   pipeline->gs_copy_shader =
-   
radv_pipeline_cache_insert_shader(pipeline->device,
- cache,
- gs_copy_sha1,
- 
pipeline->gs_copy_shader,
- gs_copy_code,
- 
gs_copy_code_size);
-   }
-
-   free(gs_copy_code);
-   }
-   if (!module->nir && !pipeline->device->trace_bo)
-   ralloc_free(nir);
-
-   if (variant)
-   variant = radv_pipeline_cache_insert_shader(pipeline->device,
-   cache, sha1,
-   variant, code,
-   code_size);
-
-   if (code)
-   free(code);
-   return variant;
-}
-
-static struct ac_shader_variant_key
-radv_compute_tes_key(bool as_es, bool export_prim_id)
-{
-   struct ac_shader_variant_key key;
-   memset(&key, 0, sizeof(key));
-   key.tes.as_es = as_es;
-   /* export prim id only

Re: [Mesa-dev] [PATCH 5/9] radv: add radv_create_shaders() helper

2017-10-14 Thread Bas Nieuwenhuizen

On Sun, Oct 15, 2017 at 1:36 AM, Timothy Arceri  wrote:
> From: Bas Nieuwenhuizen 
>
> This is a combined shader creation helper than will help us to
> create the shaders for each stage at once. This will allow us to
> do some link time optimisations.
>
> Signed-off-by: Timothy Arceri 
> ---
>  src/amd/vulkan/radv_pipeline.c   | 130 
> +++
>  src/amd/vulkan/radv_pipeline_cache.c |   3 +-
>  2 files changed, 132 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
> index 415a6cd62b..f923027036 100644
> --- a/src/amd/vulkan/radv_pipeline.c
> +++ b/src/amd/vulkan/radv_pipeline.c
> @@ -1736,20 +1736,150 @@ static void calculate_ps_inputs(struct radv_pipeline 
> *pipeline)
>
> flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << 
> ps_offset));
>
> pipeline->graphics.ps_input_cntl[ps_offset] = 
> offset_to_ps_input(vs_offset, flat_shade);
> ++ps_offset;
> }
>
> pipeline->graphics.ps_input_cntl_num = ps_offset;
>  }
>
> +static
> +void radv_create_shaders(struct radv_pipeline *pipeline,
> + struct radv_device *device,
> + struct radv_pipeline_cache *cache,
> + struct ac_shader_variant_key *keys,
> + const VkPipelineShaderStageCreateInfo **pStages)
> +{
> +   struct radv_shader_module fs_m = {0};
> +   struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
> +   nir_shader *nir[MESA_SHADER_STAGES] = {0};
> +   void *codes[MESA_SHADER_STAGES] = {0};
> +   unsigned code_sizes[MESA_SHADER_STAGES] = {0};
> +   unsigned char hash[20], gs_copy_hash[20];
> +
> +   for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
> +   if (pStages[i]) {
> +   modules[i] = 
> radv_shader_module_from_handle(pStages[i]->module);
> +   if (modules[i]->nir)
> +   _mesa_sha1_compute(modules[i]->nir->info.name,
> +  
> strlen(modules[i]->nir->info.name),
> +  modules[i]->sha1);
> +   }
> +   }
> +
> +   radv_hash_shaders(hash, pStages, pipeline->layout, keys, 
> get_hash_flags(device));
> +   memcpy(gs_copy_hash, hash, 20);
> +   gs_copy_hash[0] ^= 1;
> +
> +   if (modules[MESA_SHADER_GEOMETRY]) {
> +   pipeline->gs_copy_shader =
> +   radv_create_shader_variant_from_pipeline_cache(
> +   pipeline->device,
> +   cache,
> +   gs_copy_hash);
> +   }
> +
> +   if (radv_create_shader_variants_from_pipeline_cache(device, cache, 
> hash, pipeline->shaders) &&
> +   (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader))
> +   return;
> +
> +   if (!modules[MESA_SHADER_FRAGMENT]) {
> +   nir_builder fs_b;
> +   nir_builder_init_simple_shader(&fs_b, NULL, 
> MESA_SHADER_FRAGMENT, NULL);
> +   fs_b.shader->info.name = ralloc_strdup(fs_b.shader, 
> "noop_fs");
> +   fs_m.nir = fs_b.shader;
> +   modules[MESA_SHADER_FRAGMENT] = &fs_m;
> +   }
> +
> +   for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
> +   const VkPipelineShaderStageCreateInfo *stage = pStages[i];
> +
> +   if (!modules[i])
> +   continue;
> +
> +   nir[i] = radv_shader_compile_to_nir(device, modules[i],
> +   stage ? stage->pName : 
> "main", i,
> +   stage ? 
> stage->pSpecializationInfo : NULL);
> +   pipeline->active_stages |= mesa_to_vk_shader_stage(i);
> +   }
> +
> +   if (nir[MESA_SHADER_TESS_CTRL]) {
> +   /* TODO: This is no longer used as a key we should refactor 
> this */
> +   if (keys)
> +   keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = 
> nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
> +
> +   nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], 
> nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
> +   }
> +
> +   if (nir[MESA_SHADER_FRAGMENT]) {
> +   pipeline->shaders[MESA_SHADER_FRAGMENT] =
> +   radv_shader_variant_create(device, 
> modules[MESA_SHADER_FRAGMENT], nir[MESA_SHADER_FRAGMENT],
> +  pipeline->layout, keys ? 
> keys + MESA_SHADER_FRAGMENT : 0,
> +  
> &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
> +
> +   /* TODO: These are no longer used as keys we should refactor 
> this */
> +   if (keys) {
> +

Re: [Mesa-dev] RADV initial NIR linking support

2017-10-14 Thread Bas Nieuwenhuizen

The series looks good to me, with the comment on patch 5 fixed.

Reviewed-by: Bas Nieuwenhuizen 

for the series. However, I'd be a lot more comfortable landing this if
it sees a CTS run. Will kick one off tonight and see what happens.

On Sun, Oct 15, 2017 at 1:36 AM, Timothy Arceri  wrote:
> This initial linking support removes unused varyings across
> stages.
>
> Future improvements include enabling removing unused varying
> components [1], varying packing (in progress), and varying
> array splitting.
>
> I've tried to run the series on the public Vulkan CTS but I
> seem to be hitting an existing issue that locks up my machine [2].
>
> Sascha Willems demo results:
>
> computecullandlod 39 -> 41 fps
> pipelines ~6100 -> ~6200 fps
>
> 5 changed files with 375 additions and 406 deletions.
>
> [1] https://patchwork.freedesktop.org/series/31781/
> [2] 
> dEQP-VK.pipeline.render_to_image.core.1d_array.huge.width_layers.r8g8b8a8_unorm_d32_sfloat_s8_uint
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Re: [Mesa-dev] [PATCH 1/2] meson: provide Makefile.sources variables to meson build

2017-10-14 Thread Dylan Baker

Quoting Jakob Bornecrantz (2017-10-14 13:03:14)
> On Sat, Oct 14, 2017 at 1:36 AM, Dylan Baker  wrote:
> > I'm not sure about this approach, we would need a way to add depends to 
> > meson,
> > but I'm also worried that calling make adds another dependency that could be
> > problematic for windows, and I really don't like the idea of having a
> > half-and-half approach with the sources.
> >
> > Here's what I've been playing with:
> > https://github.com/dcbaker/meson/tree/make-import-module
> > https://github.com/dcbaker/mesa/tree/wip/meson-makefile-sources
> >
> > How would you feel about that?
> 
> Couldn't you just use the Makefile parser José wrote for the scons
> build, that would avoid running make and waiting for a new version of
> Meson. Or is there something it is lacking?
> 
> We could start out with our own Makefile parser and then move onto one
> in Meson once it is upstreamed and that version of meson is commonly
> available?
> 
> Cheers, Jakob.

In the short term I don't know how much it really hurts to duplicate the sources
in meson vs reading the makefiles, I also haven't had a chance to look at what
Jose did in scons, but if upstreaming fails that is probably a good starting
point. I'd like to try to get something upstream rather than hacking around
meson, since that has been very successful in the past. I should also point out
that meson's LLVM handling is due for a pretty major overhaul (patches waiting
more review and merge), and that we really want that support anyway (among other
things meson's LLVM inserts -L/usr/lib into your linker args, and as of 0.43
lacks static/dynamic linking options. There are also some features that are in
0.43 (we currently support back to at least 0.42, I haven't tested further back
than that) that we will need to work on windows (our workarounds involve using
touch). There's also still a lot of work to do to get our meson build system up
to the quality of our autotools and scons build systems, so I think we have some
time before we need to worry really hard about it.

Dylan

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Re: [Mesa-dev] [PATCH v3 2/2] meson: build freedreno

2017-10-14 Thread Dylan Baker

Quoting Rob Clark (2017-10-14 11:41:49)
> Signed-off-by: Rob Clark 
> ---
> v1: actually build freedreno
> v2: corrected installed ${driver}_dri.so name
> 
>  meson.build  |   6 +
>  meson_options.txt|   2 +-
>  src/gallium/drivers/freedreno/meson.build| 221 
> +++
>  src/gallium/meson.build  |   3 +-
>  src/gallium/targets/dri/meson.build  |   6 +
>  src/gallium/winsys/freedreno/drm/meson.build |  30 
>  6 files changed, 266 insertions(+), 2 deletions(-)
>  create mode 100644 src/gallium/drivers/freedreno/meson.build
>  create mode 100644 src/gallium/winsys/freedreno/drm/meson.build
> 
> diff --git a/meson.build b/meson.build
> index bc3bbf41a65..2554f7166cb 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -93,12 +93,14 @@ endif
>  with_gallium = false
>  with_gallium_radeonsi = false
>  with_gallium_nouveau = false
> +with_gallium_freedreno = false
>  with_gallium_softpipe = false
>  _drivers = get_option('gallium-drivers')
>  if _drivers != ''
>_split = _drivers.split(',')
>with_gallium_radeonsi = _split.contains('radeonsi')
>with_gallium_nouveau = _split.contains('nouveau')
> +  with_gallium_freedreno = _split.contains('freedreno')
>with_gallium_softpipe = _split.contains('swrast')
>with_gallium = true
>with_dri = true
> @@ -558,6 +560,7 @@ dep_m = cc.find_library('m', required : false)
>  dep_libdrm_amdgpu = []
>  dep_libdrm_radeon = []
>  dep_libdrm_nouveau = []
> +dep_libdrm_freedreno = []
>  if with_amd_vk or with_gallium_radeonsi
>dep_libdrm_amdgpu = dependency('libdrm_amdgpu', version : '>= 2.4.84')
>  endif
> @@ -567,6 +570,9 @@ endif
>  if with_gallium_nouveau
>dep_libdrm_nouveau = dependency('libdrm_nouveau', version : '>= 2.4.66')
>  endif
> +if with_gallium_freedreno
> +  dep_libdrm_freedreno = dependency('libdrm_freedreno', version : '>= 
> 2.4.74')
> +endif
>  
>  llvm_modules = ['bitwriter', 'engine', 'mcdisassembler', 'mcjit']
>  if with_amd_vk
> diff --git a/meson_options.txt b/meson_options.txt
> index 71e9ea63555..6b311ac2404 100644
> --- a/meson_options.txt
> +++ b/meson_options.txt
> @@ -46,7 +46,7 @@ option(
>  option(
>'gallium-drivers',
>type : 'string',
> -  value : 'radeonsi,nouveau,swrast',
> +  value : 'radeonsi,nouveau,freedreno,swrast',
>description : 'comma separated list of gallium drivers to build.'
>  )
>  option(
> diff --git a/src/gallium/drivers/freedreno/meson.build 
> b/src/gallium/drivers/freedreno/meson.build
> new file mode 100644
> index 000..191fcffe80c
> --- /dev/null
> +++ b/src/gallium/drivers/freedreno/meson.build
> @@ -0,0 +1,221 @@
> +# Copyright © 2017 Dylan Baker

While I appreciate this gesture, you should probable change this ;)

> +
> +# Permission is hereby granted, free of charge, to any person obtaining a 
> copy
> +# of this software and associated documentation files (the "Software"), to 
> deal
> +# in the Software without restriction, including without limitation the 
> rights
> +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> +# copies of the Software, and to permit persons to whom the Software is
> +# furnished to do so, subject to the following conditions:
> +
> +# The above copyright notice and this permission notice shall be included in
> +# all copies or substantial portions of the Software.
> +
> +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
> +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
> FROM,
> +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 
> THE
> +# SOFTWARE.
> +
> +ir3_nir_trig_c = custom_target(
> +  'ir3_nir_trig.c',
> +  input : 'ir3/ir3_nir_trig.py',
> +  output : 'ir3_nir_trig.c',
> +  command : [prog_python2, '@INPUT@', '-p',
> + join_paths(meson.source_root(), 'src/compiler/nir/')],
> +  capture : true,
> +  depend_files : files(
> +'ir3/ir3_nir_trig.py',
> +join_paths(meson.source_root(), 'src/compiler/nir/nir_algebraic.py'),

Do we have a files() object for this? Since both freedreno and i965 need this,
why don't we add a files_nir_algebraic_py (or whatever) in nir and use that for
both drivers.

> +  ),
> +)
> +
> +files_libfreedreno = files(
> +  'adreno_common.xml.h',
> +  'adreno_pm4.xml.h',
> +  'disasm.h',
> +  'freedreno_batch.c',
> +  'freedreno_batch.h',
> +  'freedreno_batch_cache.c',
> +  'freedreno_batch_cache.h',
> +  'freedreno_context.c',
> +  'freedreno_context.h',
> +  'freedreno_draw.c',
> +  'freedreno_draw.h',
> +  'freedreno_fence.c',
> +  'freedreno_fence.h',
> +  'freedreno_gmem.c',
> +  'freedreno_gmem.h',
> +  'freedreno_program.c',
> +  'freedreno_prog

Re: [Mesa-dev] [PATCH v3 16/43] i965/fs: Define new shader opcode to set rounding modes

Re: [Mesa-dev] [PATCH v3 14/43] i965/fs: Handle 32-bit to 16-bit conversions

Re: [Mesa-dev] [PATCH v3 19/43] i965/fs: Support push constants of 16-bit types

Re: [Mesa-dev] [PATCH v4 0/2] build system: Unify c++11 detection and used [was: configure+mesa/st:check -std=c++11 support and enable tests accordingly]

Re: [Mesa-dev] [PATCH 1/2] etnaviv: skip unused vertex attributes when assigning VS inputs

Re: [Mesa-dev] [PATCH 2/2] etnaviv: rework TS enable to be a derived state

Re: [Mesa-dev] [PATCH 1/2] etnaviv: skip unused vertex attributes when assigning VS inputs

Re: [Mesa-dev] [PATCH 2/2] etnaviv: rework TS enable to be a derived state

Re: [Mesa-dev] [PATCH v3 16/43] i965/fs: Define new shader opcode to set rounding modes

Re: [Mesa-dev] [PATCH v3 14/43] i965/fs: Handle 32-bit to 16-bit conversions

Re: [Mesa-dev] [PATCH v3 19/43] i965/fs: Support push constants of 16-bit types

[Mesa-dev] [PATCH] meson: build freedreno

[Mesa-dev] [PATCH] svga: fix format_conversion_table breakage

[Mesa-dev] [PATCH v2 1/2] freedreno/ir3: use a flag instead of setting PYTHONPATH

[Mesa-dev] [PATCH v2 2/2] meson: build freedreno

[Mesa-dev] [PATCH v3 2/2] meson: build freedreno

Re: [Mesa-dev] [PATCH 1/2] meson: provide Makefile.sources variables to meson build

Re: [Mesa-dev] [PATCH] blob: Use intptr_t instead of ssize_t

[Mesa-dev] Build fail since configure.ac: rework llvm libs handling for 3.9+

Re: [Mesa-dev] Build fail since configure.ac: rework llvm libs handling for 3.9+

[Mesa-dev] [PATCH 2/9] radv: Change cache datastructures for combined pipelines.

[Mesa-dev] [PATCH 3/9] radv: Add multiple shader cache store & load functions.

[Mesa-dev] [PATCH 5/9] radv: add radv_create_shaders() helper

[Mesa-dev] [PATCH 8/9] radv: reuse the multiple shader store & load functions for gs copy variant

[Mesa-dev] [PATCH 1/9] radv: reorder init function calls

[Mesa-dev] [PATCH 6/9] radv: switch to using radv_create_shaders()

[Mesa-dev] [PATCH 4/9] radv: add radv_hash_shaders() helper

[Mesa-dev] RADV initial NIR linking support

[Mesa-dev] [PATCH 9/9] radv: Link shaders.

[Mesa-dev] [PATCH 7/9] radv: remove some now unused shader compile code

Re: [Mesa-dev] [PATCH 5/9] radv: add radv_create_shaders() helper

Re: [Mesa-dev] RADV initial NIR linking support

Re: [Mesa-dev] [PATCH 1/2] meson: provide Makefile.sources variables to meson build

Re: [Mesa-dev] [PATCH v3 2/2] meson: build freedreno

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