[Mesa-dev] [PATCH] [rfc] radv: optimise bo descriptor updates for non-local bos.

[Dave Airlie]

From: Dave Airlie 

This might be a bit over optimising.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_cmd_buffer.c |  9 +++---
 src/amd/vulkan/radv_descriptor_set.c | 55 +++-
 src/amd/vulkan/radv_private.h|  1 +
 3 files changed, 41 insertions(+), 24 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 62adbaced10..cd642dbf690 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2295,10 +2295,11 @@ radv_bind_descriptor_set(struct radv_cmd_buffer 
*cmd_buffer,
 
assert(!(set->layout->flags & 
VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
 
-   for (unsigned j = 0; j < set->layout->buffer_count; ++j)
-   if (set->descriptors[j])
-   radv_cs_add_buffer(ws, cmd_buffer->cs, 
set->descriptors[j], 7);
-
+   if (set->has_non_local_bo_descriptor) {
+   for (unsigned j = 0; j < set->layout->buffer_count; ++j)
+   if (set->descriptors[j])
+   radv_cs_add_buffer(ws, cmd_buffer->cs, 
set->descriptors[j], 7);
+   }
if(set->bo)
radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
 }
diff --git a/src/amd/vulkan/radv_descriptor_set.c 
b/src/amd/vulkan/radv_descriptor_set.c
index a98ff37ced6..2595ff5cdc5 100644
--- a/src/amd/vulkan/radv_descriptor_set.c
+++ b/src/amd/vulkan/radv_descriptor_set.c
@@ -555,23 +555,27 @@ VkResult radv_FreeDescriptorSets(
return VK_SUCCESS;
 }
 
-static void write_texel_buffer_descriptor(struct radv_device *device,
+static bool write_texel_buffer_descriptor(struct radv_device *device,
  struct radv_cmd_buffer *cmd_buffer,
  unsigned *dst,
  struct radeon_winsys_bo **buffer_list,
  const VkBufferView _buffer_view)
 {
RADV_FROM_HANDLE(radv_buffer_view, buffer_view, _buffer_view);
-
+   bool ret = false;
memcpy(dst, buffer_view->state, 4 * 4);
 
if (cmd_buffer)
radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer_view->bo, 
7);
-   else
+   else {
*buffer_list = buffer_view->bo;
+   if (buffer_view->bo->is_local)
+   ret = true;
+   }
+   return ret;
 }
 
-static void write_buffer_descriptor(struct radv_device *device,
+static bool write_buffer_descriptor(struct radv_device *device,
 struct radv_cmd_buffer *cmd_buffer,
 unsigned *dst,
 struct radeon_winsys_bo **buffer_list,
@@ -580,7 +584,7 @@ static void write_buffer_descriptor(struct radv_device 
*device,
RADV_FROM_HANDLE(radv_buffer, buffer, buffer_info->buffer);
uint64_t va = radv_buffer_get_va(buffer->bo);
uint32_t range = buffer_info->range;
-
+   bool is_local = true;
if (buffer_info->range == VK_WHOLE_SIZE)
range = buffer->size - buffer_info->offset;
 
@@ -597,11 +601,14 @@ static void write_buffer_descriptor(struct radv_device 
*device,
 
if (cmd_buffer)
radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer->bo, 7);
-   else
+   else {
*buffer_list = buffer->bo;
+   is_local = buffer->bo->is_local;
+   }
+   return is_local;
 }
 
-static void write_dynamic_buffer_descriptor(struct radv_device *device,
+static bool write_dynamic_buffer_descriptor(struct radv_device *device,
 struct radv_descriptor_range 
*range,
 struct radeon_winsys_bo 
**buffer_list,
 const VkDescriptorBufferInfo 
*buffer_info)
@@ -618,9 +625,10 @@ static void write_dynamic_buffer_descriptor(struct 
radv_device *device,
range->size = size;
 
*buffer_list = buffer->bo;
+   return buffer->bo->is_local;
 }
 
-static void
+static bool
 write_image_descriptor(struct radv_device *device,
   struct radv_cmd_buffer *cmd_buffer,
   unsigned *dst,
@@ -629,7 +637,7 @@ write_image_descriptor(struct radv_device *device,
   const VkDescriptorImageInfo *image_info)
 {
RADV_FROM_HANDLE(radv_image_view, iview, image_info->imageView);
-
+   bool ret = true;
if (descriptor_type == VK_DESCRIPTOR_TYPE_STORAGE_IMAGE) {
memcpy(dst, iview->storage_descriptor, 8 * 4);
memcpy(dst + 8, iview->storage_fmask_descriptor, 8 * 4);
@@ -640,11 +648,14 @@ write_image_descriptor(struct radv_device *device,
 
if (cmd_buffer)
radv_cs_add_buffer(device->ws, cmd_buffer->cs, iview->bo, 7);
-   else
+   else 

[Mesa-dev] [PATCH] radv: pre-calculate user_data_0 registers and store in pipeline

[Dave Airlie]

From: Dave Airlie 

There's no point recalculating these the whole time on descriptor
emission, just store them at pipeline creation.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_cmd_buffer.c | 14 ++--
 src/amd/vulkan/radv_pipeline.c   | 49 ++--
 src/amd/vulkan/radv_private.h|  1 +
 src/amd/vulkan/radv_shader.c | 39 
 src/amd/vulkan/radv_shader.h |  4 
 5 files changed, 55 insertions(+), 52 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 7357eadae39..62adbaced10 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -574,7 +574,7 @@ radv_emit_userdata_address(struct radv_cmd_buffer 
*cmd_buffer,
   int idx, uint64_t va)
 {
struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, 
idx);
-   uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, 
cmd_buffer->device->physical_device->rad_info.chip_class, 
radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
+   uint32_t base_reg = pipeline->user_data_0[stage];
if (loc->sgpr_idx == -1)
return;
assert(loc->num_sgprs == 2);
@@ -616,7 +616,7 @@ radv_update_multisample_state(struct radv_cmd_buffer 
*cmd_buffer,
if 
(pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
uint32_t offset;
struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, 
MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
-   uint32_t base_reg = 
radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, 
cmd_buffer->device->physical_device->rad_info.chip_class, 
radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
+   uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
if (loc->sgpr_idx == -1)
return;
assert(loc->num_sgprs == 1);
@@ -838,7 +838,7 @@ radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
 
loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, 
AC_UD_TCS_OFFCHIP_LAYOUT);
if (loc->sgpr_idx != -1) {
-   uint32_t base_reg = 
radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, 
cmd_buffer->device->physical_device->rad_info.chip_class, 
radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
+   uint32_t base_reg = 
pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
assert(loc->num_sgprs == 4);
assert(!loc->indirect);
radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx 
* 4, 4);
@@ -851,7 +851,7 @@ radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
 
loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, 
AC_UD_TES_OFFCHIP_LAYOUT);
if (loc->sgpr_idx != -1) {
-   uint32_t base_reg = 
radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, 
cmd_buffer->device->physical_device->rad_info.chip_class, 
radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
+   uint32_t base_reg = 
pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
assert(loc->num_sgprs == 1);
assert(!loc->indirect);
 
@@ -861,7 +861,7 @@ radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
 
loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, 
AC_UD_VS_LS_TCS_IN_LAYOUT);
if (loc->sgpr_idx != -1) {
-   uint32_t base_reg = 
radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, 
cmd_buffer->device->physical_device->rad_info.chip_class, 
radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
+   uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX];
assert(loc->num_sgprs == 1);
assert(!loc->indirect);
 
@@ -1577,7 +1577,7 @@ emit_stage_descriptor_set_userdata(struct radv_cmd_buffer 
*cmd_buffer,
   gl_shader_stage stage)
 {
struct ac_userdata_info *desc_set_loc = 
>shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
-   uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, 
cmd_buffer->device->physical_device->rad_info.chip_class, 
radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
+   uint32_t base_reg = pipeline->user_data_0[stage];
 
if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
return;
@@ -2938,7 +2938,7 @@ static void radv_emit_view_index(struct radv_cmd_buffer 
*cmd_buffer, unsigned in
struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, 
stage, AC_UD_VIEW_INDEX);
if (loc->sgpr_idx == -1)
continue;
-   uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, 
cmd_buffer->device->physical_device->rad_info.chip_class, 

Re: [Mesa-dev] [PATCH 2/2] glsl/linker: location aliasing requires types to have the same width

[Iago Toral]

On Fri, 2017-11-03 at 12:01 -0400, Ilia Mirkin wrote:
> On Fri, Nov 3, 2017 at 6:56 AM, Iago Toral Quiroga  > wrote:
> > Regarding location aliasing requirements, the OpenGL spec says:
> > 
> >   "Further, when location aliasing, the aliases sharing the
> > location
> >    must have the same underlying numerical type  (floating-point or
> >    integer)."
> > 
> > Khronos has further clarified that this also requires the
> > underlying
> > types to have the same width, so we can't put a float and a double
> > in the same location slot for example. Future versions of the spec
> > will
> > be corrected to make this clear.
> > 
> > This patch amends our implementation to account for this
> > restriction.
> > 
> > In the process of doing this, I also noticed that we would attempt
> > to check aliasing requirements for record variables (including the
> > test
> > for the numerical type) which is not allowed, instead, we should be
> > producing a linker error as soon as we see any attempt to do
> > location
> > aliasing on a record variable.
> 
> Is there a piglit for this? (Which fails without this patch?)
> 
> Oh, and you hit it because you stuck the unreachable in there?

No, there aren't any tests that catch this, I can add one though.

> 
> > ---
> >  src/compiler/glsl/link_varyings.cpp | 41
> > ++---
> >  1 file changed, 34 insertions(+), 7 deletions(-)
> > 
> > diff --git a/src/compiler/glsl/link_varyings.cpp
> > b/src/compiler/glsl/link_varyings.cpp
> > index af938611f4..1d17deaffe 100644
> > --- a/src/compiler/glsl/link_varyings.cpp
> > +++ b/src/compiler/glsl/link_varyings.cpp
> > @@ -413,7 +413,7 @@ struct explicit_location_info {
> >  };
> > 
> >  static inline unsigned
> > -get_numerical_type(const glsl_type *type)
> > +get_numerical_sized_type(const glsl_type *type)
> >  {
> > /* From the OpenGL 4.6 spec, section 4.4.1 Input Layout
> > Qualifiers, Page 68,
> >  * (Location aliasing):
> > @@ -421,10 +421,22 @@ get_numerical_type(const glsl_type *type)
> >  *"Further, when location aliasing, the aliases sharing the
> > location
> >  * must have the same underlying numerical type  (floating-
> > point or
> >  * integer)
> > +*
> > +* Khronos has further clarified that this also requires the
> > underlying
> > +* types to have the same width, so we can't put a float and a
> > double
> > +* in the same location slot for example. Future versions of
> > the spec will
> > +* be corrected to make this clear.
> >  */
> > -   if (type->is_float() || type->is_double())
> > +   if (type->is_float())
> >    return GLSL_TYPE_FLOAT;
> > -   return GLSL_TYPE_INT;
> > +   else if (type->is_integer())
> > +  return GLSL_TYPE_INT;
> > +   else if (type->is_double())
> > +  return GLSL_TYPE_DOUBLE;
> > +   else if (type->is_integer_64())
> > +  return GLSL_TYPE_INT64;
> 
> How does a (bindless) sampler/image come across? Do they come out as
> ->is_integer_64? (I don't think they do.)

Actually, this should not have an unreachable(). The types we see here
are provided by the user, so we should not assert on them, we should
handle them as linker errors if they are not numerical (and that should
also handle the case of structs without having to special-case them
below). I'll send a v2.

Iago

> > +
> > +   unreachable("Type is not numerical");
> >  }
> > 
> >  static bool
> > @@ -442,14 +454,17 @@ check_location_aliasing(struct
> > explicit_location_info explicit_locations[][4],
> >  gl_shader_stage stage)
> >  {
> > unsigned last_comp;
> > +   bool is_record;
> > if (type->without_array()->is_record()) {
> >    /* The component qualifier can't be used on structs so just
> > treat
> > * all component slots as used.
> > */
> >    last_comp = 4;
> > +  is_record = true;
> > } else {
> >    unsigned dmul = type->without_array()->is_64bit() ? 2 : 1;
> >    last_comp = component + type->without_array()-
> > >vector_elements * dmul;
> > +  is_record = false;
> > }
> > 
> > while (location < location_limit) {
> > @@ -459,8 +474,17 @@ check_location_aliasing(struct
> > explicit_location_info explicit_locations[][4],
> >  _locations[location][comp];
> > 
> >   if (info->var) {
> > -/* Component aliasing is not alloed */
> > -if (comp >= component && comp < last_comp) {
> > +if (is_record) {
> > +   /* Disallow location aliasing for record variables
> > */
> > +   linker_error(prog,
> > +"%s shader uses explicit location on
> > record "
> > +"variable %s that generates location
> > aliasing "
> > +"for location %u, component %u\n",
> > +_mesa_shader_stage_to_string(stage),
> > +var->name, location, comp);
> > +  

Re: [Mesa-dev] [PATCH] Android: update CleanSpec.mk

[Tapani Pälli]

On 11/06/2017 04:08 AM, Chih-Wei Huang wrote:

2017-11-03 19:02 GMT+08:00 Tapani Pälli :

On 11/03/2017 12:30 PM, Chih-Wei Huang wrote:

2017-11-03 15:47 GMT+08:00 Tapani Pälli :

Hi Chih-Wei;
This looks good to me. Only thing that causes a bit of headache is ...
what
is the difference between PRODUCT_OUT, OUT_DIR and TARGET_OUT?


OUT_DIR is also set to "out" if it's not already set.

PRODUCT_OUT is where all target files go.
(i.e., out/target/product/$device/)

TARGET_OUT is $PRODUCT_OUT/system

Please see the definitions in build/core/envsetup.mk.


OK, thanks. I'm not sure if TARGET_OUT is correct then, at least on
Android-IA these vendor files are under:

out/target/product/$device/vendor/lib

so, not under 'system'.


Yes. This patch is used to remove old files under 'system'.
Otherwise the image may contain duplicate libraries
that causes unexpected problems.



Right now I get it, thanks!

Reviewed-by: Tapani Pälli 

// Tapani
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Re: [Mesa-dev] [PATCH 1/9] gallium: add CAPs to support HW atomic counters. (v2)

[Dave Airlie]

On 4 November 2017 at 10:01, Marek Olšák  wrote:
> Not sure if the "HW" prefix everywhere makes sense since gallium
> doesn't imply there is a hardware driver behind it, but I don't really
> care much.

Well it's more that the atomic's aren't normal ssbo atomics, and there is
dedicated hardware for them. Really a software backing by definition is
unlikely to have any specific atomic counter hardware, so I think the HW
one still stands.

Dave.
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Re: [Mesa-dev] [PATCH 2/9] gallium/tgsi: start adding hw atomics (v2)

[Dave Airlie]

>> +Hardware Atomic Register File
>> +^
>> +
>> +Hardware atomics are declared as a 2D array with an optional array id.
>> +
>> +The first member of the dimension is the buffer resource the atomic
>> +is located in.
>> +The second member is a range into the buffer resource, either for
>> +one or multiple counters. If this is an array, the declaration will have
>> +an unique array id.
>> +
>> +Each counter is 4 bytes in size, and index and ranges are in counters not 
>> bytes.
>> +DCL BUFFER[0], ATOMIC
>> +DCL ATOMIC[0][0]
>> +DCL ATOMIC[0][1]
>> +
>> +This declares two atomics, one at the start of the buffer and one in the
>> +second 4 bytes.
>> +
>> +DCL BUFFER[0], ATOMIC
>> +DCL BUFFER[1], ATOMIC
>
> Why are there BUFFER declarations?

Good question I thought they had a use, guess not.

I'll drop them.

Dave.
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Re: [Mesa-dev] [PATCH 8/9] r600: add support for hw atomic counters. (v2)

[Dave Airlie]

 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
>> +   radeon_emit(cs, reloc);
>> +   }
>> +   ++rctx->append_fence_id;
>> +   reloc = radeon_add_to_buffer_list(>b, >b.gfx,
>> +
>> r600_resource(rctx->append_fence),
>> + RADEON_USAGE_READWRITE,
>> + RADEON_PRIO_SHADER_RW_BUFFER);
>> +   dst_offset = r600_resource(rctx->append_fence)->gpu_address;
>> +   radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
>> +   radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
>> +   radeon_emit(cs, dst_offset & 0x);
>> +   radeon_emit(cs, (2 << 29) | ((dst_offset >> 32) & 0xff));
>> +   radeon_emit(cs, rctx->append_fence_id);
>> +   radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
>> +   radeon_emit(cs, reloc);
>> +
>> +   radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0) | pkt_flags);
>> +   radeon_emit(cs, WAIT_REG_MEM_GEQUAL | WAIT_REG_MEM_MEMORY | (1 <<
>> 8));
>> +   radeon_emit(cs, dst_offset & 0x);
>> +   radeon_emit(cs, ((dst_offset >> 32) & 0xff));
>> +   radeon_emit(cs, rctx->append_fence_id);
>> +   radeon_emit(cs, 0x);
>> +   radeon_emit(cs, 0xa);
>> +   radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
>> +   radeon_emit(cs, reloc);
>
>
> This is pretty pessimistic, did you benchmark it?

I actually don't know of any app that uses atomic counters, do we have one?

Until I do I'd rather stay correct and simple, and if someone finds a workload
then I can care more.

>
> There's an ongoing discussion in the OpenGL WG about what exactly the
> semantics for ARB_shader_atomic_counters should be, because the original
> extension language and the language after inclusion into core seem a bit
> contradictory.
>
> Certainly, one of the CTS tests for ARB_shader_atomic_counters inserts
> glMemoryBarrier() calls between back-to-back draws involving counters...
>
> So it seems to me you should probably be able to get away with waiting for
> the append fence ID in pipe_context::memory_barrier and/or when the atomic
> counter buffers are unbound.
>
> The other thing is that the wait may have to be in PFP (or rather, the PFP
> may have to be synced with the ME) in order to get index buffer and indirect
> draw loads correct.
>
> Bottom line is, nobody seems to have good and definitive tests for the
> various read-after-write combinations that are possible with atomic
> counters.
>
> I guess it's fine for r600 to land this as-is, but I do want to implement
> GDS atomics in radeonsi as well, and then we may want to revisit :)
>
Yeah I've sort of followed it, I'm not sure the fglrx driver even got stuff
right, it fails a few of the piglit tests.

For radeonsi hopefully this code won't affect it too much.
Dave.
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[Mesa-dev] [PATCH] radv: keep a stage mask per pipeline. (v2)

[Dave Airlie]

From: Dave Airlie 

This should reduce some pointless loops.

v2: fix missing check which causes crashes with compute shaders

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_cmd_buffer.c | 53 +++-
 src/amd/vulkan/radv_pipeline.c   |  2 ++
 src/amd/vulkan/radv_private.h|  1 +
 3 files changed, 17 insertions(+), 39 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 833c3eb3f0d..7357eadae39 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -682,17 +682,10 @@ static void
 radv_emit_shaders_prefetch(struct radv_cmd_buffer *cmd_buffer,
   struct radv_pipeline *pipeline)
 {
-   radv_emit_shader_prefetch(cmd_buffer,
- pipeline->shaders[MESA_SHADER_VERTEX]);
-   radv_emit_shader_prefetch(cmd_buffer,
- pipeline->shaders[MESA_SHADER_TESS_CTRL]);
-   radv_emit_shader_prefetch(cmd_buffer,
- pipeline->shaders[MESA_SHADER_TESS_EVAL]);
-   radv_emit_shader_prefetch(cmd_buffer,
- pipeline->shaders[MESA_SHADER_GEOMETRY]);
+   radv_foreach_stage(stage, pipeline->stage_mask)
+   radv_emit_shader_prefetch(cmd_buffer,
+ pipeline->shaders[stage]);
radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
-   radv_emit_shader_prefetch(cmd_buffer,
- pipeline->shaders[MESA_SHADER_FRAGMENT]);
 }
 
 static void
@@ -1603,12 +1596,11 @@ radv_emit_descriptor_set_userdata(struct 
radv_cmd_buffer *cmd_buffer,
  struct radv_descriptor_set *set,
  unsigned idx)
 {
-   if (cmd_buffer->state.pipeline) {
+   if (cmd_buffer->state.pipeline && (stages & 
cmd_buffer->state.pipeline->stage_mask)) {
radv_foreach_stage(stage, stages) {
-   if (cmd_buffer->state.pipeline->shaders[stage])
-   emit_stage_descriptor_set_userdata(cmd_buffer, 
cmd_buffer->state.pipeline,
-  idx, set->va,
-  stage);
+   emit_stage_descriptor_set_userdata(cmd_buffer, 
cmd_buffer->state.pipeline,
+  idx, set->va,
+  stage);
}
}
 
@@ -1658,25 +1650,10 @@ radv_flush_indirect_descriptor_sets(struct 
radv_cmd_buffer *cmd_buffer)
va += offset;
 
if (cmd_buffer->state.pipeline) {
-   if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
-   radv_emit_userdata_address(cmd_buffer, 
cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
-  
AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
-
-   if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
-   radv_emit_userdata_address(cmd_buffer, 
cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
-  
AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
-
-   if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
-   radv_emit_userdata_address(cmd_buffer, 
cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
-  
AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
-
-   if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
-   radv_emit_userdata_address(cmd_buffer, 
cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
-  
AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
-
-   if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
-   radv_emit_userdata_address(cmd_buffer, 
cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
+   radv_foreach_stage(stage, 
cmd_buffer->state.pipeline->stage_mask) {
+   radv_emit_userdata_address(cmd_buffer, 
cmd_buffer->state.pipeline, stage,
   
AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
+   }
}
 
if (cmd_buffer->state.compute_pipeline)
@@ -1751,10 +1728,8 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
   cmd_buffer->cs, 
MESA_SHADER_STAGES * 4);
 
radv_foreach_stage(stage, stages) {
-   if (pipeline->shaders[stage]) {
-   radv_emit_userdata_address(cmd_buffer, pipeline, stage,
-  AC_UD_PUSH_CONSTANTS, va);
-   }
+   radv_emit_userdata_address(cmd_buffer, pipeline, 

[Mesa-dev] [PATCH] radv: keep a stage mask per pipeline.

[Dave Airlie]

From: Dave Airlie 

This should reduce some pointless loops.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_cmd_buffer.c | 51 ++--
 src/amd/vulkan/radv_pipeline.c   |  2 ++
 src/amd/vulkan/radv_private.h|  1 +
 3 files changed, 16 insertions(+), 38 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 833c3eb3f0d..7026d3d1fb6 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -682,17 +682,10 @@ static void
 radv_emit_shaders_prefetch(struct radv_cmd_buffer *cmd_buffer,
   struct radv_pipeline *pipeline)
 {
-   radv_emit_shader_prefetch(cmd_buffer,
- pipeline->shaders[MESA_SHADER_VERTEX]);
-   radv_emit_shader_prefetch(cmd_buffer,
- pipeline->shaders[MESA_SHADER_TESS_CTRL]);
-   radv_emit_shader_prefetch(cmd_buffer,
- pipeline->shaders[MESA_SHADER_TESS_EVAL]);
-   radv_emit_shader_prefetch(cmd_buffer,
- pipeline->shaders[MESA_SHADER_GEOMETRY]);
+   radv_foreach_stage(stage, pipeline->stage_mask)
+   radv_emit_shader_prefetch(cmd_buffer,
+ pipeline->shaders[stage]);
radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
-   radv_emit_shader_prefetch(cmd_buffer,
- pipeline->shaders[MESA_SHADER_FRAGMENT]);
 }
 
 static void
@@ -1605,10 +1598,9 @@ radv_emit_descriptor_set_userdata(struct radv_cmd_buffer 
*cmd_buffer,
 {
if (cmd_buffer->state.pipeline) {
radv_foreach_stage(stage, stages) {
-   if (cmd_buffer->state.pipeline->shaders[stage])
-   emit_stage_descriptor_set_userdata(cmd_buffer, 
cmd_buffer->state.pipeline,
-  idx, set->va,
-  stage);
+   emit_stage_descriptor_set_userdata(cmd_buffer, 
cmd_buffer->state.pipeline,
+  idx, set->va,
+  stage);
}
}
 
@@ -1658,25 +1650,10 @@ radv_flush_indirect_descriptor_sets(struct 
radv_cmd_buffer *cmd_buffer)
va += offset;
 
if (cmd_buffer->state.pipeline) {
-   if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
-   radv_emit_userdata_address(cmd_buffer, 
cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
-  
AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
-
-   if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
-   radv_emit_userdata_address(cmd_buffer, 
cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
-  
AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
-
-   if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
-   radv_emit_userdata_address(cmd_buffer, 
cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
-  
AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
-
-   if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
-   radv_emit_userdata_address(cmd_buffer, 
cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
-  
AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
-
-   if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
-   radv_emit_userdata_address(cmd_buffer, 
cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
+   radv_foreach_stage(stage, 
cmd_buffer->state.pipeline->stage_mask) {
+   radv_emit_userdata_address(cmd_buffer, 
cmd_buffer->state.pipeline, stage,
   
AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
+   }
}
 
if (cmd_buffer->state.compute_pipeline)
@@ -1751,10 +1728,8 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
   cmd_buffer->cs, 
MESA_SHADER_STAGES * 4);
 
radv_foreach_stage(stage, stages) {
-   if (pipeline->shaders[stage]) {
-   radv_emit_userdata_address(cmd_buffer, pipeline, stage,
-  AC_UD_PUSH_CONSTANTS, va);
-   }
+   radv_emit_userdata_address(cmd_buffer, pipeline, stage,
+  AC_UD_PUSH_CONSTANTS, va);
}
 
cmd_buffer->push_constant_stages &= ~stages;
@@ -1819,9 +1794,9 @@ radv_upload_graphics_shader_descriptors(struct 
radv_cmd_buffer *cmd_buffer, bool
if 

[Mesa-dev] [PATCH 1/2] nv50: make blending work so that zero wins in a multiplication

[Ilia Mirkin]

This matches nvc0 behavior, tested with the fbo-float-nan piglit.

Signed-off-by: Ilia Mirkin 
---
 src/gallium/drivers/nouveau/nv50/nv50_screen.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index 5ee5a26b652..47c70d74e94 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -771,6 +771,11 @@ nv50_screen_init_hwctx(struct nv50_screen *screen)
   PUSH_DATA (push, 0);
}
 
+   BEGIN_NV04(push, NV50_3D(UNK0FDC), 1);
+   PUSH_DATA (push, 1);
+   BEGIN_NV04(push, NV50_3D(UNK19C0), 1);
+   PUSH_DATA (push, 1);
+
PUSH_KICK (push);
 }
 
-- 
2.13.6

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[Mesa-dev] [PATCH 2/2] r600g: use SIMPLE_FLOAT for blending to avoid NaNs in RTs

[Ilia Mirkin]

Radeonsi also sets this flag.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103544
Signed-off-by: Ilia Mirkin 
---

This needs testing with the fbo-float-nan piglit that was recently added. Just
guessing that this is the right flag to set here.

 src/gallium/drivers/r600/evergreen_state.c | 1 +
 src/gallium/drivers/r600/r600_state.c  | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 96eb35a9818..131778dea9f 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1211,6 +1211,7 @@ static void evergreen_set_color_surface_common(struct 
r600_context *rctx,
S_028C70_COMP_SWAP(swap) |
S_028C70_BLEND_CLAMP(blend_clamp) |
S_028C70_BLEND_BYPASS(blend_bypass) |
+   S_028C70_SIMPLE_FLOAT(1) |
S_028C70_NUMBER_TYPE(ntype) |
S_028C70_ENDIAN(endian);
 
diff --git a/src/gallium/drivers/r600/r600_state.c 
b/src/gallium/drivers/r600/r600_state.c
index c21e8dabb1f..0c331537460 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -898,6 +898,7 @@ static void r600_init_color_surface(struct r600_context 
*rctx,
S_0280A0_COMP_SWAP(swap) |
S_0280A0_BLEND_BYPASS(blend_bypass) |
S_0280A0_BLEND_CLAMP(blend_clamp) |
+   S_0280A0_SIMPLE_FLOAT(1) |
S_0280A0_NUMBER_TYPE(ntype) |
S_0280A0_ENDIAN(endian);
 
-- 
2.13.6

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[Mesa-dev] [PATCH 1/2] radv: wrap cs_add_buffer in an inline.

[Dave Airlie]

From: Dave Airlie 

The next patch will try and avoid calling the indirect function.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_cmd_buffer.c | 40 ++--
 src/amd/vulkan/radv_descriptor_set.c |  6 +++---
 src/amd/vulkan/radv_device.c | 14 ++---
 src/amd/vulkan/radv_meta_buffer.c|  8 
 src/amd/vulkan/radv_query.c  | 10 -
 src/amd/vulkan/radv_radeon_winsys.h  |  8 
 6 files changed, 47 insertions(+), 39 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 590c41a7bf2..5fb9b479324 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -279,7 +279,7 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
cmd_buffer->sample_positions_needed = false;
 
if (cmd_buffer->upload.upload_bo)
-   cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
+   radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
  
cmd_buffer->upload.upload_bo, 8);
cmd_buffer->upload.offset = 0;
 
@@ -321,7 +321,7 @@ radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer 
*cmd_buffer,
return false;
}
 
-   device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
+   radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
if (cmd_buffer->upload.upload_bo) {
upload = malloc(sizeof(*upload));
 
@@ -415,7 +415,7 @@ void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer 
*cmd_buffer)
MAYBE_UNUSED unsigned cdw_max = 
radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
 
++cmd_buffer->state.trace_id;
-   device->ws->cs_add_buffer(cs, device->trace_bo, 8);
+   radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
radv_emit_write_data_packet(cs, va, 1, _buffer->state.trace_id);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
@@ -472,7 +472,7 @@ radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
data[0] = (uintptr_t)pipeline;
data[1] = (uintptr_t)pipeline >> 32;
 
-   device->ws->cs_add_buffer(cs, device->trace_bo, 8);
+   radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
radv_emit_write_data_packet(cs, va, 2, data);
 }
 
@@ -508,7 +508,7 @@ radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
data[i * 2 + 1] = (uintptr_t)set >> 32;
}
 
-   device->ws->cs_add_buffer(cs, device->trace_bo, 8);
+   radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
 }
 
@@ -1297,7 +1297,7 @@ radv_set_depth_clear_regs(struct radv_cmd_buffer 
*cmd_buffer,
if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
++reg_count;
 
-   cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
+   radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, image->bo, 
8);
 
radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
@@ -1358,7 +1358,7 @@ radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer 
*cmd_buffer,
if (!image->surface.dcc_size)
return;
 
-   cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
+   radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, image->bo, 
8);
 
radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
@@ -1382,7 +1382,7 @@ radv_set_color_clear_regs(struct radv_cmd_buffer 
*cmd_buffer,
if (!image->cmask.size && !image->surface.dcc_size)
return;
 
-   cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
+   radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, image->bo, 
8);
 
radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
@@ -1445,7 +1445,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer 
*cmd_buffer)
int idx = subpass->color_attachments[i].attachment;
struct radv_attachment_info *att = 
>attachments[idx];
 
-   cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, 
att->attachment->bo, 8);
+   radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, 
att->attachment->bo, 8);
 
assert(att->attachment->aspect_mask & 
VK_IMAGE_ASPECT_COLOR_BIT);
radv_emit_fb_color_state(cmd_buffer, i, >cb);
@@ -1458,7 +1458,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer 
*cmd_buffer)
VkImageLayout layout = subpass->depth_stencil_attachment.layout;
struct radv_attachment_info *att = 
>attachments[idx];

[Mesa-dev] [PATCH 2/2] radv: move is_local up to the winsys level.

[Dave Airlie]

From: Dave Airlie 

We can avoid adding the buffer in the non-local case, this will
avoid all the overhead of the indirect call.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_radeon_winsys.h   | 4 
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 2 +-
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.h | 1 -
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 2 +-
 4 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_radeon_winsys.h 
b/src/amd/vulkan/radv_radeon_winsys.h
index bab19a6233d..66a2bcccb4d 100644
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -147,6 +147,7 @@ struct radeon_winsys_fence;
 
 struct radeon_winsys_bo {
uint64_t va;
+   bool is_local;
 };
 struct radv_winsys_sem_counts {
uint32_t syncobj_count;
@@ -284,6 +285,9 @@ static inline void radv_cs_add_buffer(struct radeon_winsys 
*ws,
  struct radeon_winsys_bo *bo,
  uint8_t priority)
 {
+   if (bo->is_local)
+   return;
+
ws->cs_add_buffer(cs, bo, priority);
 }
 
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
index dac549a20ad..9ec4b4fb561 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
@@ -333,7 +333,7 @@ radv_amdgpu_winsys_bo_create(struct radeon_winsys *_ws,
if (!(flags & RADEON_FLAG_IMPLICIT_SYNC) && ws->info.drm_minor >= 22)
request.flags |= AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
if (flags & RADEON_FLAG_NO_INTERPROCESS_SHARING && ws->info.drm_minor 
>= 20) {
-   bo->is_local = true;
+   bo->base.is_local = true;
request.flags |= AMDGPU_GEM_CREATE_VM_ALWAYS_VALID;
}
 
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.h 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.h
index f9aac9451c0..f32e4308386 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.h
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.h
@@ -45,7 +45,6 @@ struct radv_amdgpu_winsys_bo {
uint64_t size;
struct radv_amdgpu_winsys *ws;
bool is_virtual;
-   bool is_local;
int ref_count;
 
union {
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index 939c221e0c8..c10bdd6c91e 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -473,7 +473,7 @@ static void radv_amdgpu_cs_add_buffer(struct 
radeon_winsys_cs *_cs,
return;
}
 
-   if (bo->is_local)
+   if (bo->base.is_local)
return;
 
radv_amdgpu_cs_add_buffer_internal(cs, bo->bo, priority);
-- 
2.14.2

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[Mesa-dev] [PATCH] radv: when loading regs no need to add buffer

[Dave Airlie]

From: Dave Airlie 

The function that calls us has just added the buffer to the
list already, no need to try and add it again.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_cmd_buffer.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 188b2fdafa3..590c41a7bf2 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1327,7 +1327,6 @@ radv_load_depth_clear_regs(struct radv_cmd_buffer 
*cmd_buffer,
if (!image->surface.htile_size)
return;
 
-   cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
 
radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
@@ -1411,7 +1410,6 @@ radv_load_color_clear_regs(struct radv_cmd_buffer 
*cmd_buffer,
return;
 
uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
-   cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
 
radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 
cmd_buffer->state.predicating));
radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
-- 
2.14.2

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[Mesa-dev] [PATCH 1/2] radv: move calculating vs out info regs into pipeline.

[Dave Airlie]

From: Dave Airlie 

This moves some calculations of register values into the pipeline
construction, it saves looking at outinfo in the cmd buffer emit.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_cmd_buffer.c | 29 -
 src/amd/vulkan/radv_pipeline.c   | 21 ++---
 src/amd/vulkan/radv_private.h|  9 -
 3 files changed, 34 insertions(+), 25 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 6f5d4441ef6..cbd3f25d08e 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -698,28 +698,15 @@ radv_emit_shaders_prefetch(struct radv_cmd_buffer 
*cmd_buffer,
 static void
 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
struct radv_pipeline *pipeline,
-   struct radv_shader_variant *shader,
-   struct ac_vs_output_info *outinfo)
+   struct radv_shader_variant *shader)
 {
uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
-   unsigned export_count;
 
-   export_count = MAX2(1, outinfo->param_exports);
radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
-  S_0286C4_VS_EXPORT_COUNT(export_count - 1));
+  pipeline->graphics.vs.spi_vs_out_config);
 
radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
-  
S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
-  S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports 
> 1 ?
-  
V_02870C_SPI_SHADER_4COMP :
-  
V_02870C_SPI_SHADER_NONE) |
-  S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports 
> 2 ?
-  
V_02870C_SPI_SHADER_4COMP :
-  
V_02870C_SPI_SHADER_NONE) |
-  S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports 
> 3 ?
-  
V_02870C_SPI_SHADER_4COMP :
-  
V_02870C_SPI_SHADER_NONE));
-
+  pipeline->graphics.vs.spi_shader_pos_format);
 
radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
radeon_emit(cmd_buffer->cs, va >> 8);
@@ -735,11 +722,11 @@ radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
 
 
radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
-  pipeline->graphics.pa_cl_vs_out_cntl);
+  pipeline->graphics.vs.pa_cl_vs_out_cntl);
 
if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
-  
S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
+  pipeline->graphics.vs.vgt_reuse_off);
 }
 
 static void
@@ -821,7 +808,7 @@ radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
else if (vs->info.vs.as_es)
radv_emit_hw_es(cmd_buffer, vs, >info.vs.es_info);
else
-   radv_emit_hw_vs(cmd_buffer, pipeline, vs, >info.vs.outinfo);
+   radv_emit_hw_vs(cmd_buffer, pipeline, vs);
 }
 
 
@@ -841,7 +828,7 @@ radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
if (tes->info.tes.as_es)
radv_emit_hw_es(cmd_buffer, tes, 
>info.tes.es_info);
else
-   radv_emit_hw_vs(cmd_buffer, pipeline, tes, 
>info.tes.outinfo);
+   radv_emit_hw_vs(cmd_buffer, pipeline, tes);
}
 
radv_emit_hw_hs(cmd_buffer, tcs);
@@ -951,7 +938,7 @@ radv_emit_geometry_shader(struct radv_cmd_buffer 
*cmd_buffer,
radeon_emit(cmd_buffer->cs, gs->rsrc2);
}
 
-   radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, 
>gs_copy_shader->info.vs.outinfo);
+   radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
 
struct ac_userdata_info *loc = 
radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
 
AC_UD_GS_VS_RING_STRIDE_ENTRIES);
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index c6d9debc7e4..4a70ab53eb3 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1545,7 +1545,7 @@ static void calculate_vgt_gs_mode(struct radv_pipeline 
*pipeline)
}
 }
 
-static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
+static void calculate_vs_outinfo(struct radv_pipeline *pipeline)
 {
struct ac_vs_output_info *outinfo = 

[Mesa-dev] [PATCH 2/2] radv: emit esgs ring size in one place.

[Dave Airlie]

From: Dave Airlie 

This register is the same on all gpus so far, so emit it in one
place and also for the pre-gfx9 gpus set the value in the pipeline
creation.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_cmd_buffer.c | 14 +++---
 src/amd/vulkan/radv_pipeline.c   |  1 +
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index cbd3f25d08e..188b2fdafa3 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -731,13 +731,11 @@ radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
 
 static void
 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
-   struct radv_shader_variant *shader,
-   struct ac_es_output_info *outinfo)
+   struct radv_pipeline *pipeline,
+   struct radv_shader_variant *shader)
 {
uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 
-   radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
-  outinfo->esgs_itemsize / 4);
radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
radeon_emit(cmd_buffer->cs, va >> 8);
radeon_emit(cmd_buffer->cs, va >> 40);
@@ -806,7 +804,7 @@ radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
if (vs->info.vs.as_ls)
radv_emit_hw_ls(cmd_buffer, vs);
else if (vs->info.vs.as_es)
-   radv_emit_hw_es(cmd_buffer, vs, >info.vs.es_info);
+   radv_emit_hw_es(cmd_buffer, pipeline, vs);
else
radv_emit_hw_vs(cmd_buffer, pipeline, vs);
 }
@@ -826,7 +824,7 @@ radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
 
if (tes) {
if (tes->info.tes.as_es)
-   radv_emit_hw_es(cmd_buffer, tes, 
>info.tes.es_info);
+   radv_emit_hw_es(cmd_buffer, pipeline, tes);
else
radv_emit_hw_vs(cmd_buffer, pipeline, tes);
}
@@ -915,6 +913,9 @@ radv_emit_geometry_shader(struct radv_cmd_buffer 
*cmd_buffer,
   S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
   S_028B90_ENABLE(gs_num_invocations > 0));
 
+   radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
+  pipeline->graphics.gs.vgt_esgs_ring_itemsize);
+
va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
 
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
@@ -929,7 +930,6 @@ radv_emit_geometry_shader(struct radv_cmd_buffer 
*cmd_buffer,
 
radeon_set_context_reg(cmd_buffer->cs, 
R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
radeon_set_context_reg(cmd_buffer->cs, 
R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, 
pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
-   radeon_set_context_reg(cmd_buffer->cs, 
R_028AAC_VGT_ESGS_RING_ITEMSIZE, pipeline->graphics.gs.vgt_esgs_ring_itemsize);
} else {
radeon_set_sh_reg_seq(cmd_buffer->cs, 
R_00B220_SPI_SHADER_PGM_LO_GS, 4);
radeon_emit(cmd_buffer->cs, va >> 8);
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 4a70ab53eb3..5895a76ff4b 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1290,6 +1290,7 @@ calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
if (pipeline->device->physical_device->rad_info.chip_class <= VI)
pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, 
min_esgs_ring_size, max_size);
 
+   pipeline->graphics.gs.vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 
4;
pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
 }
 
-- 
2.14.2

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Re: [Mesa-dev] [PATCH 3/4] radv: add helper for setting a descriptor.

[Bas Nieuwenhuizen]

On Mon, Nov 6, 2017 at 12:44 AM, Dave Airlie  wrote:
> From: Dave Airlie 
>
> This is just a simple refactor.
>
> Signed-off-by: Dave Airlie 
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 20 
>  src/amd/vulkan/radv_meta.c   |  3 +--
>  src/amd/vulkan/radv_private.h|  4 
>  3 files changed, 17 insertions(+), 10 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c 
> b/src/amd/vulkan/radv_cmd_buffer.c
> index 85d6b57e8ad..80dcf7fe088 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -476,6 +476,14 @@ radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
> radv_emit_write_data_packet(cs, va, 2, data);
>  }
>
> +void radv_set_descriptor(struct radv_cmd_buffer *cmd_buffer,
> +struct radv_descriptor_set *set,
> +unsigned idx)
> +{
> +   cmd_buffer->state.descriptors[idx] = set;
> +   cmd_buffer->state.descriptors_dirty |= (1u << idx);
> +}

radv_set_descriptor_set? We are binding a set, not a single descriptor.

> +
>  static void
>  radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
>  {
> @@ -2319,8 +2327,7 @@ radv_bind_descriptor_set(struct radv_cmd_buffer 
> *cmd_buffer,
>  {
> struct radeon_winsys *ws = cmd_buffer->device->ws;
>
> -   cmd_buffer->state.descriptors[idx] = set;
> -   cmd_buffer->state.descriptors_dirty |= (1u << idx);
> +   radv_set_descriptor(cmd_buffer, set, idx);
> if (!set)
> return;
>
> @@ -2432,8 +2439,7 @@ void radv_meta_push_descriptor_set(
> radv_descriptor_set_to_handle(push_set),
> descriptorWriteCount, pDescriptorWrites, 
> 0, NULL);
>
> -   cmd_buffer->state.descriptors[set] = push_set;
> -   cmd_buffer->state.descriptors_dirty |= (1u << set);
> +   radv_set_descriptor(cmd_buffer, push_set, set);
>  }
>
>  void radv_CmdPushDescriptorSetKHR(
> @@ -2457,8 +2463,7 @@ void radv_CmdPushDescriptorSetKHR(
> radv_descriptor_set_to_handle(push_set),
> descriptorWriteCount, pDescriptorWrites, 
> 0, NULL);
>
> -   cmd_buffer->state.descriptors[set] = push_set;
> -   cmd_buffer->state.descriptors_dirty |= (1u << set);
> +   radv_set_descriptor(cmd_buffer, push_set, set);
> cmd_buffer->state.push_descriptors_dirty = true;
>  }
>
> @@ -2481,8 +2486,7 @@ void radv_CmdPushDescriptorSetWithTemplateKHR(
> radv_update_descriptor_set_with_template(cmd_buffer->device, 
> cmd_buffer, push_set,
>  descriptorUpdateTemplate, 
> pData);
>
> -   cmd_buffer->state.descriptors[set] = push_set;
> -   cmd_buffer->state.descriptors_dirty |= (1u << set);
> +   radv_set_descriptor(cmd_buffer, push_set, set);
> cmd_buffer->state.push_descriptors_dirty = true;
>  }
>
> diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
> index 3f57618ad28..dce78cdbe03 100644
> --- a/src/amd/vulkan/radv_meta.c
> +++ b/src/amd/vulkan/radv_meta.c
> @@ -124,8 +124,7 @@ radv_meta_restore(const struct radv_meta_saved_state 
> *state,
> }
>
> if (state->flags & RADV_META_SAVE_DESCRIPTORS) {
> -   cmd_buffer->state.descriptors[0] = state->old_descriptor_set0;
> -   cmd_buffer->state.descriptors_dirty |= (1 << 0);
> +   radv_set_descriptor(cmd_buffer, state->old_descriptor_set0, 
> 0);
> }
>
> if (state->flags & RADV_META_SAVE_CONSTANTS) {
> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
> index d236588621a..df3e76feb8f 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -1552,6 +1552,10 @@ VkResult radv_alloc_sem_info(struct 
> radv_winsys_sem_info *sem_info,
>  const VkSemaphore *signal_sems);
>  void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
>
> +void radv_set_descriptor(struct radv_cmd_buffer *cmd_buffer,
> +struct radv_descriptor_set *set,
> +unsigned idx);
> +
>  void
>  radv_update_descriptor_sets(struct radv_device *device,
>  struct radv_cmd_buffer *cmd_buffer,
> --
> 2.14.2
>
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Re: [Mesa-dev] [PATCH] radv: free attachments on end command buffer.

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

On Mon, Nov 6, 2017 at 1:37 AM, Dave Airlie  wrote:
> From: Dave Airlie 
>
> If we allocate attachments in the begin command buffer due to the
> render pass continue bit, we were leaking them.
>
> Since renderpasses inside a cmd buffer malloc/free these properly,
> and set to NULL, we just need to call free at end.
>
> Fixes a memory leak with multithreading demo.
>
> Cc: "17.2 17.3" 
> Signed-off-by: Dave Airlie 
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c 
> b/src/amd/vulkan/radv_cmd_buffer.c
> index fa378423e00..5f8b1c3c989 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -2515,6 +2515,8 @@ VkResult radv_EndCommandBuffer(
> si_emit_cache_flush(cmd_buffer);
> }
>
> +   vk_free(_buffer->pool->alloc, cmd_buffer->state.attachments);
> +
> if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
> return VK_ERROR_OUT_OF_DEVICE_MEMORY;
>
> --
> 2.14.2
>
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[Mesa-dev] [PATCH] radv: free attachments on end command buffer.

[Dave Airlie]

From: Dave Airlie 

If we allocate attachments in the begin command buffer due to the
render pass continue bit, we were leaking them.

Since renderpasses inside a cmd buffer malloc/free these properly,
and set to NULL, we just need to call free at end.

Fixes a memory leak with multithreading demo.

Cc: "17.2 17.3" 
Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_cmd_buffer.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index fa378423e00..5f8b1c3c989 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2515,6 +2515,8 @@ VkResult radv_EndCommandBuffer(
si_emit_cache_flush(cmd_buffer);
}
 
+   vk_free(_buffer->pool->alloc, cmd_buffer->state.attachments);
+
if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
return VK_ERROR_OUT_OF_DEVICE_MEMORY;
 
-- 
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[Mesa-dev] [Bug 103586] OpenCL/Clover: AMD Turks: corrupt output buffer (depending on dimension order?)

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103586

Bug ID: 103586
   Summary: OpenCL/Clover: AMD Turks: corrupt output buffer
(depending on dimension order?)
   Product: Mesa
   Version: 17.2
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Other
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: freedesk...@treblig.org
QA Contact: mesa-dev@lists.freedesktop.org

I've got a trivial kernel that draws a sphere in a voxel cube; each voxel
should end up as 0 or 1; if I use global id 0 as z, 1 as y, 2 as x  I get
corruptions where some voxels have random junk in; if I reverse the order so
that global id 0 is x, 1 is y and 2 is z then it's happy.
(Confirmed the code is clean with oclgrind and happy on Intel.

Versions:

Number of devices 1
  Device Name AMD TURKS (DRM 2.50.0 /
4.13.0-1-amd64, LLVM 5.0.0)
  Device Vendor   AMD
  Device Vendor ID0x1002
  Device Version  OpenCL 1.1 Mesa 17.2.4
  Driver Version  17.2.4
  Device OpenCL C Version OpenCL C 1.1 

(on debian testing, was on stable, but same behaviour)

01:00.0 0300: 1002:6841
01:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI]
Thames [Radeon HD 7550M/7570M/7650M] (prog-if 00 [VGA controller])
Subsystem: Hewlett-Packard Company Thames [Radeon HD 7550M/7570M/7650M]
Flags: bus master, fast devsel, latency 0, IRQ 37
Memory at c000 (64-bit, prefetchable) [size=256M]
Memory at d430 (64-bit, non-prefetchable) [size=128K]
I/O ports at 4000 [size=256]
Expansion ROM at 000c [disabled] [size=128K]
Capabilities: 
Kernel driver in use: radeon
Kernel modules: radeon

in an HP Elitebook laptop.

Code that triggers this:
https://github.com/penguin42/opencl-play/commit/c98470685874769e4a59975791459180564b6f6e

build and run with:
g++ -O2 ocl.cpp -lOpenCL && ./a.out 2> z
then check output with:
tr '01' '  ' 

[Mesa-dev] [PATCH 3/4] radv: add helper for setting a descriptor.

[Dave Airlie]

From: Dave Airlie 

This is just a simple refactor.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_cmd_buffer.c | 20 
 src/amd/vulkan/radv_meta.c   |  3 +--
 src/amd/vulkan/radv_private.h|  4 
 3 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 85d6b57e8ad..80dcf7fe088 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -476,6 +476,14 @@ radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
radv_emit_write_data_packet(cs, va, 2, data);
 }
 
+void radv_set_descriptor(struct radv_cmd_buffer *cmd_buffer,
+struct radv_descriptor_set *set,
+unsigned idx)
+{
+   cmd_buffer->state.descriptors[idx] = set;
+   cmd_buffer->state.descriptors_dirty |= (1u << idx);
+}
+
 static void
 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
 {
@@ -2319,8 +2327,7 @@ radv_bind_descriptor_set(struct radv_cmd_buffer 
*cmd_buffer,
 {
struct radeon_winsys *ws = cmd_buffer->device->ws;
 
-   cmd_buffer->state.descriptors[idx] = set;
-   cmd_buffer->state.descriptors_dirty |= (1u << idx);
+   radv_set_descriptor(cmd_buffer, set, idx);
if (!set)
return;
 
@@ -2432,8 +2439,7 @@ void radv_meta_push_descriptor_set(
radv_descriptor_set_to_handle(push_set),
descriptorWriteCount, pDescriptorWrites, 0, 
NULL);
 
-   cmd_buffer->state.descriptors[set] = push_set;
-   cmd_buffer->state.descriptors_dirty |= (1u << set);
+   radv_set_descriptor(cmd_buffer, push_set, set);
 }
 
 void radv_CmdPushDescriptorSetKHR(
@@ -2457,8 +2463,7 @@ void radv_CmdPushDescriptorSetKHR(
radv_descriptor_set_to_handle(push_set),
descriptorWriteCount, pDescriptorWrites, 0, 
NULL);
 
-   cmd_buffer->state.descriptors[set] = push_set;
-   cmd_buffer->state.descriptors_dirty |= (1u << set);
+   radv_set_descriptor(cmd_buffer, push_set, set);
cmd_buffer->state.push_descriptors_dirty = true;
 }
 
@@ -2481,8 +2486,7 @@ void radv_CmdPushDescriptorSetWithTemplateKHR(
radv_update_descriptor_set_with_template(cmd_buffer->device, 
cmd_buffer, push_set,
 descriptorUpdateTemplate, 
pData);
 
-   cmd_buffer->state.descriptors[set] = push_set;
-   cmd_buffer->state.descriptors_dirty |= (1u << set);
+   radv_set_descriptor(cmd_buffer, push_set, set);
cmd_buffer->state.push_descriptors_dirty = true;
 }
 
diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
index 3f57618ad28..dce78cdbe03 100644
--- a/src/amd/vulkan/radv_meta.c
+++ b/src/amd/vulkan/radv_meta.c
@@ -124,8 +124,7 @@ radv_meta_restore(const struct radv_meta_saved_state *state,
}
 
if (state->flags & RADV_META_SAVE_DESCRIPTORS) {
-   cmd_buffer->state.descriptors[0] = state->old_descriptor_set0;
-   cmd_buffer->state.descriptors_dirty |= (1 << 0);
+   radv_set_descriptor(cmd_buffer, state->old_descriptor_set0, 0);
}
 
if (state->flags & RADV_META_SAVE_CONSTANTS) {
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index d236588621a..df3e76feb8f 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1552,6 +1552,10 @@ VkResult radv_alloc_sem_info(struct radv_winsys_sem_info 
*sem_info,
 const VkSemaphore *signal_sems);
 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
 
+void radv_set_descriptor(struct radv_cmd_buffer *cmd_buffer,
+struct radv_descriptor_set *set,
+unsigned idx);
+
 void
 radv_update_descriptor_sets(struct radv_device *device,
 struct radv_cmd_buffer *cmd_buffer,
-- 
2.14.2

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[Mesa-dev] [PATCH 1/4] radv: reorder cmd_state to remove a hole.

[Dave Airlie]

From: Dave Airlie 

This just removes a hole in the cmd_state and packs some bools
together.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_private.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 51bdde20323..15cd5eee7df 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -810,9 +810,9 @@ struct radv_attachment_state {
 
 struct radv_cmd_state {
bool  vb_dirty;
-   radv_cmd_dirty_mask_t dirty;
bool  push_descriptors_dirty;
bool predicating;
+   radv_cmd_dirty_mask_t dirty;
 
struct radv_pipeline *pipeline;
struct radv_pipeline *emitted_pipeline;
-- 
2.14.2

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[Mesa-dev] [PATCH 4/4] radv: move descriptor sets out of cmd_state.

[Dave Airlie]

From: Dave Airlie 

Instead of storing all the pointers and zeroing them all out,
just store a valid bitmask in the state. This also moves
the CmdBindPipeline path down the cpu usage path for the
multithreading demo as it no longer has to traverse MAX_SETS
to find the active descriptor sets.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_cmd_buffer.c | 29 ++---
 src/amd/vulkan/radv_meta.c   |  5 -
 src/amd/vulkan/radv_private.h|  3 ++-
 3 files changed, 20 insertions(+), 17 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 80dcf7fe088..fa378423e00 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -480,8 +480,13 @@ void radv_set_descriptor(struct radv_cmd_buffer 
*cmd_buffer,
 struct radv_descriptor_set *set,
 unsigned idx)
 {
-   cmd_buffer->state.descriptors[idx] = set;
+   cmd_buffer->descriptors[idx] = set;
+   if (set)
+   cmd_buffer->state.valid_descriptors |= (1u << idx);
+   else
+   cmd_buffer->state.valid_descriptors &= ~(1u << idx);
cmd_buffer->state.descriptors_dirty |= (1u << idx);
+
 }
 
 static void
@@ -491,17 +496,14 @@ radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
struct radeon_winsys_cs *cs = cmd_buffer->cs;
uint32_t data[MAX_SETS * 2] = {};
uint64_t va;
-
+   unsigned i;
va = radv_buffer_get_va(device->trace_bo) + 24;
 
MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
   cmd_buffer->cs, 4 + 
MAX_SETS * 2);
 
-   for (int i = 0; i < MAX_SETS; i++) {
-   struct radv_descriptor_set *set = 
cmd_buffer->state.descriptors[i];
-   if (!set)
-   continue;
-
+   for_each_bit(i, cmd_buffer->state.valid_descriptors) {
+   struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
data[i * 2] = (uintptr_t)set;
data[i * 2 + 1] = (uintptr_t)set >> 32;
}
@@ -1660,8 +1662,8 @@ radv_flush_indirect_descriptor_sets(struct 
radv_cmd_buffer *cmd_buffer)
for (unsigned i = 0; i < MAX_SETS; i++) {
uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
uint64_t set_va = 0;
-   struct radv_descriptor_set *set = 
cmd_buffer->state.descriptors[i];
-   if (set)
+   struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
+   if (cmd_buffer->state.valid_descriptors & (1u << i))
set_va = set->va;
uptr[0] = set_va & 0x;
uptr[1] = set_va >> 32;
@@ -1719,8 +1721,8 @@ radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
   MAX_SETS * 
MESA_SHADER_STAGES * 4);
 
for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
-   struct radv_descriptor_set *set = 
cmd_buffer->state.descriptors[i];
-   if (!set)
+   struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
+   if (!(cmd_buffer->state.valid_descriptors & (1u << i)))
continue;
 
radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
@@ -2569,10 +2571,7 @@ radv_emit_compute_pipeline(struct radv_cmd_buffer 
*cmd_buffer)
 
 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
 {
-   for (unsigned i = 0; i < MAX_SETS; i++) {
-   if (cmd_buffer->state.descriptors[i])
-   cmd_buffer->state.descriptors_dirty |= (1u << i);
-   }
+   cmd_buffer->state.descriptors_dirty |= 
cmd_buffer->state.valid_descriptors;
 }
 
 void radv_CmdBindPipeline(
diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
index dce78cdbe03..46c9384cd60 100644
--- a/src/amd/vulkan/radv_meta.c
+++ b/src/amd/vulkan/radv_meta.c
@@ -73,7 +73,10 @@ radv_meta_save(struct radv_meta_saved_state *state,
}
 
if (state->flags & RADV_META_SAVE_DESCRIPTORS) {
-   state->old_descriptor_set0 = cmd_buffer->state.descriptors[0];
+   if (cmd_buffer->state.valid_descriptors & (1 << 0))
+   state->old_descriptor_set0 = cmd_buffer->descriptors[0];
+   else
+   state->old_descriptor_set0 = NULL;
}
 
if (state->flags & RADV_META_SAVE_CONSTANTS) {
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index df3e76feb8f..8d632705453 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -822,7 +822,6 @@ struct radv_cmd_state {
struct radv_render_pass * pass;
const struct radv_subpass * subpass;
struct radv_dynamic_state

[Mesa-dev] [PATCH 2/4] radv: move vertex binding out of cmd state.

[Dave Airlie]

From: Dave Airlie 

This isn't required to be cleared, since buffers are only linked
by vertex elements, so if elements are clear then no buffers
should be referenced.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_cmd_buffer.c | 6 +++---
 src/amd/vulkan/radv_private.h| 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 43505a3372a..85d6b57e8ad 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1790,13 +1790,13 @@ radv_cmd_buffer_update_vertex_descriptors(struct 
radv_cmd_buffer *cmd_buffer, bo
uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
uint32_t offset;
int vb = velems->binding[i];
-   struct radv_buffer *buffer = 
cmd_buffer->state.vertex_bindings[vb].buffer;
+   struct radv_buffer *buffer = 
cmd_buffer->vertex_bindings[vb].buffer;
uint32_t stride = 
cmd_buffer->state.pipeline->binding_stride[vb];
 
device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 
8);
va = radv_buffer_get_va(buffer->bo);
 
-   offset = cmd_buffer->state.vertex_bindings[vb].offset + 
velems->offset[i];
+   offset = cmd_buffer->vertex_bindings[vb].offset + 
velems->offset[i];
va += offset + buffer->offset;
desc[0] = va;
desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | 
S_008F04_STRIDE(stride);
@@ -2256,7 +2256,7 @@ void radv_CmdBindVertexBuffers(
const VkDeviceSize* pOffsets)
 {
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
-   struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
+   struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
bool changed = false;
 
/* We have to defer setting up vertex buffer since we need the buffer
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 15cd5eee7df..d236588621a 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -822,7 +822,6 @@ struct radv_cmd_state {
struct radv_render_pass * pass;
const struct radv_subpass * subpass;
struct radv_dynamic_state dynamic;
-   struct radv_vertex_bindingvertex_bindings[MAX_VBS];
struct radv_descriptor_set *  descriptors[MAX_SETS];
struct radv_attachment_state *attachments;
VkRect2D render_area;
@@ -871,6 +870,7 @@ struct radv_cmd_buffer {
VkCommandBufferLevel level;
struct radeon_winsys_cs *cs;
struct radv_cmd_state state;
+   struct radv_vertex_binding   vertex_bindings[MAX_VBS];
uint32_t queue_family_index;
 
uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
-- 
2.14.2

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[Mesa-dev] [PATCH] i965: disable NIR linking on HSW and below

[Timothy Arceri]

Fixes: 379b24a40d3d "i965: make use of nir linking"

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103537
---

Jason's fixes referenced in the bug report help a little,
however there are still issues with the vector backend and
I don't have time to investigate right now so just disable it.

 src/mesa/drivers/dri/i965/brw_link.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
b/src/mesa/drivers/dri/i965/brw_link.cpp
index 9019db56aa0..5cbfd85c05f 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -272,8 +272,11 @@ brw_link_shader(struct gl_context *ctx, struct 
gl_shader_program *shProg)
 * ensures that inter-shader outputs written to in an earlier stage
 * are eliminated if they are (transitively) not used in a later
 * stage.
+*
+* TODO: Look into Shader of Mordor regressions on HSW and enable this for
+* all platforms. See: https://bugs.freedesktop.org/show_bug.cgi?id=103537
 */
-if (first != last) {
+if (first != last && brw->screen->devinfo.gen >= 8) {
int next = last;
for (int i = next - 1; i >= 0; i--) {
   if (shProg->_LinkedShaders[i] == NULL)
-- 
2.13.6

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Re: [Mesa-dev] [PATCH] nir: handle get_buffer_size in nir_lower_atomics_to_ssbo

[Kenneth Graunke]

On Sunday, November 5, 2017 11:17:06 AM PST Rob Clark wrote:
> Overlooked initially, be we need to remap the SSBO index for this as
> well.
> 
> Signed-off-by: Rob Clark 
> ---
>  src/compiler/nir/nir_lower_atomics_to_ssbo.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/src/compiler/nir/nir_lower_atomics_to_ssbo.c 
> b/src/compiler/nir/nir_lower_atomics_to_ssbo.c
> index 371eb0b9d15..934ae81d750 100644
> --- a/src/compiler/nir/nir_lower_atomics_to_ssbo.c
> +++ b/src/compiler/nir/nir_lower_atomics_to_ssbo.c
> @@ -59,6 +59,7 @@ lower_instr(nir_intrinsic_instr *instr, unsigned 
> ssbo_offset, nir_builder *b)
> case nir_intrinsic_ssbo_atomic_comp_swap:
> case nir_intrinsic_store_ssbo:
> case nir_intrinsic_load_ssbo:
> +   case nir_intrinsic_get_buffer_size:
>/* easy case, keep same opcode and just remap SSBO buffer index: */
>op = instr->intrinsic;
>idx_src = (op == nir_intrinsic_store_ssbo) ? 1 : 0;
> 

Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH] nir: handle get_buffer_size in nir_lower_atomics_to_ssbo

[Jason Ekstrand]

Rb


On November 5, 2017 11:17:18 Rob Clark  wrote:


Overlooked initially, be we need to remap the SSBO index for this as
well.

Signed-off-by: Rob Clark 
---
 src/compiler/nir/nir_lower_atomics_to_ssbo.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/compiler/nir/nir_lower_atomics_to_ssbo.c 
b/src/compiler/nir/nir_lower_atomics_to_ssbo.c

index 371eb0b9d15..934ae81d750 100644
--- a/src/compiler/nir/nir_lower_atomics_to_ssbo.c
+++ b/src/compiler/nir/nir_lower_atomics_to_ssbo.c
@@ -59,6 +59,7 @@ lower_instr(nir_intrinsic_instr *instr, unsigned 
ssbo_offset, nir_builder *b)

case nir_intrinsic_ssbo_atomic_comp_swap:
case nir_intrinsic_store_ssbo:
case nir_intrinsic_load_ssbo:
+   case nir_intrinsic_get_buffer_size:
   /* easy case, keep same opcode and just remap SSBO buffer index: */
   op = instr->intrinsic;
   idx_src = (op == nir_intrinsic_store_ssbo) ? 1 : 0;
--
2.13.6




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Re: [Mesa-dev] [PATCH] nv50,nvc0: enable using LOAD from constbuf

[Ilia Mirkin]

On Sun, Nov 5, 2017 at 1:13 PM, Tobias Klausmann
 wrote:
>
> On 11/5/17 4:48 PM, Ilia Mirkin wrote:
>> This enables std430-style packing for UBOs which aren't otherwise marked
>> as std140.
>>
>> There might be small register lifetime changes as a result of removed
>> duplicate loads in some cases, but this seems worth it overall.
>
>
> A before/after shader-db run would be nice to see.
>
> Reviewed-by: Tobias Klausmann 

Not great =/

total instructions in shared programs : 6583617 -> 6588798 (0.08%)
total gprs used in shared programs: 950832 -> 951158 (0.03%)
total shared used in shared programs  : 0 -> 0 (0.00%)
total local used in shared programs   : 15328 -> 15328 (0.00%)
total bytes used in shared programs   : 60366976 -> 60414152 (0.08%)

local sharedgpr   inst  bytes
helped   0   0   0  61  61
  hurt   0   0 186 742 742

But not horrible either. Pretty much all of these would be resolved if
we had instruction scheduling... the loads happen somewhere up top and
can't propagate into e.g. exports, etc.

  -ilia
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[Mesa-dev] [PATCH] nir: handle get_buffer_size in nir_lower_atomics_to_ssbo

[Rob Clark]

Overlooked initially, be we need to remap the SSBO index for this as
well.

Signed-off-by: Rob Clark 
---
 src/compiler/nir/nir_lower_atomics_to_ssbo.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/compiler/nir/nir_lower_atomics_to_ssbo.c 
b/src/compiler/nir/nir_lower_atomics_to_ssbo.c
index 371eb0b9d15..934ae81d750 100644
--- a/src/compiler/nir/nir_lower_atomics_to_ssbo.c
+++ b/src/compiler/nir/nir_lower_atomics_to_ssbo.c
@@ -59,6 +59,7 @@ lower_instr(nir_intrinsic_instr *instr, unsigned ssbo_offset, 
nir_builder *b)
case nir_intrinsic_ssbo_atomic_comp_swap:
case nir_intrinsic_store_ssbo:
case nir_intrinsic_load_ssbo:
+   case nir_intrinsic_get_buffer_size:
   /* easy case, keep same opcode and just remap SSBO buffer index: */
   op = instr->intrinsic;
   idx_src = (op == nir_intrinsic_store_ssbo) ? 1 : 0;
-- 
2.13.6

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Re: [Mesa-dev] [PATCH] nv50,nvc0: enable using LOAD from constbuf

[Tobias Klausmann]

On 11/5/17 4:48 PM, Ilia Mirkin wrote:
> This enables std430-style packing for UBOs which aren't otherwise marked
> as std140.
>
> There might be small register lifetime changes as a result of removed
> duplicate loads in some cases, but this seems worth it overall.


A before/after shader-db run would be nice to see.

Reviewed-by: Tobias Klausmann 


>
> Signed-off-by: Ilia Mirkin 
> ---
>  src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 2 ++
>  src/gallium/drivers/nouveau/nv50/nv50_screen.c| 2 +-
>  src/gallium/drivers/nouveau/nvc0/nvc0_screen.c| 2 +-
>  3 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> index 34351dab518..dfddffc89da 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> @@ -403,6 +403,7 @@ static nv50_ir::DataFile translateFile(uint file)
>  {
> switch (file) {
> case TGSI_FILE_CONSTANT:return nv50_ir::FILE_MEMORY_CONST;
> +   case TGSI_FILE_CONSTBUF:return nv50_ir::FILE_MEMORY_CONST;
> case TGSI_FILE_INPUT:   return nv50_ir::FILE_SHADER_INPUT;
> case TGSI_FILE_OUTPUT:  return nv50_ir::FILE_SHADER_OUTPUT;
> case TGSI_FILE_TEMPORARY:   return nv50_ir::FILE_GPR;
> @@ -2628,6 +2629,7 @@ Converter::handleLOAD(Value *dst0[4])
>  
> switch (tgsi.getSrc(0).getFile()) {
> case TGSI_FILE_BUFFER:
> +   case TGSI_FILE_CONSTBUF:
> case TGSI_FILE_MEMORY:
>for (c = 0; c < 4; ++c) {
>   if (!dst0[c])
> diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c 
> b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
> index 2066cf3f6e1..5ee5a26b652 100644
> --- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
> +++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
> @@ -202,6 +202,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum 
> pipe_cap param)
> case PIPE_CAP_TGSI_CLOCK:
> case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
> case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
> +   case PIPE_CAP_LOAD_CONSTBUF:
>return 1;
> case PIPE_CAP_SEAMLESS_CUBE_MAP:
>return 1; /* class_3d >= NVA0_3D_CLASS; */
> @@ -275,7 +276,6 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum 
> pipe_cap param)
> case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
> case PIPE_CAP_QUERY_SO_OVERFLOW:
> case PIPE_CAP_MEMOBJ:
> -   case PIPE_CAP_LOAD_CONSTBUF:
> case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
> case PIPE_CAP_TILE_RASTER_ORDER:
> case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c 
> b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> index d62a5552536..3544afe044b 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> @@ -257,6 +257,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum 
> pipe_cap param)
> case PIPE_CAP_COMPUTE:
> case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
> case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
> +   case PIPE_CAP_LOAD_CONSTBUF:
>return 1;
> case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
>return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
> @@ -304,7 +305,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum 
> pipe_cap param)
> case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
> case PIPE_CAP_QUERY_SO_OVERFLOW:
> case PIPE_CAP_MEMOBJ:
> -   case PIPE_CAP_LOAD_CONSTBUF:
> case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
> case PIPE_CAP_TILE_RASTER_ORDER:
> case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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Re: [Mesa-dev] [PATCH 19/19] etnaviv: GC7000: Split off current texture code

[Wladimir J. van der Laan]

On Sun, Nov 05, 2017 at 04:31:40PM +0100, Christian Gmeiner wrote:

> > +#ifndef H_ETNAVIV_TEXTURE_PLAIN
> > +#define H_ETNAVIV_TEXTURE_PLAIN
> > +
> > +#include 
> > +
> > +#include "pipe/p_context.h"
> > +#include "pipe/p_state.h"
> > +
> > +#include "hw/state_3d.xml.h"
> 
> Is this include needed?

Huh, no, I don't see why the states would need to be included in the header,
probably a leftover, I'll remove it.

Wladimir

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[Mesa-dev] [PATCH] nv50,nvc0: enable using LOAD from constbuf

[Ilia Mirkin]

This enables std430-style packing for UBOs which aren't otherwise marked
as std140.

There might be small register lifetime changes as a result of removed
duplicate loads in some cases, but this seems worth it overall.

Signed-off-by: Ilia Mirkin 
---
 src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 2 ++
 src/gallium/drivers/nouveau/nv50/nv50_screen.c| 2 +-
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c| 2 +-
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 34351dab518..dfddffc89da 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -403,6 +403,7 @@ static nv50_ir::DataFile translateFile(uint file)
 {
switch (file) {
case TGSI_FILE_CONSTANT:return nv50_ir::FILE_MEMORY_CONST;
+   case TGSI_FILE_CONSTBUF:return nv50_ir::FILE_MEMORY_CONST;
case TGSI_FILE_INPUT:   return nv50_ir::FILE_SHADER_INPUT;
case TGSI_FILE_OUTPUT:  return nv50_ir::FILE_SHADER_OUTPUT;
case TGSI_FILE_TEMPORARY:   return nv50_ir::FILE_GPR;
@@ -2628,6 +2629,7 @@ Converter::handleLOAD(Value *dst0[4])
 
switch (tgsi.getSrc(0).getFile()) {
case TGSI_FILE_BUFFER:
+   case TGSI_FILE_CONSTBUF:
case TGSI_FILE_MEMORY:
   for (c = 0; c < 4; ++c) {
  if (!dst0[c])
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index 2066cf3f6e1..5ee5a26b652 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -202,6 +202,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
case PIPE_CAP_TGSI_CLOCK:
case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
+   case PIPE_CAP_LOAD_CONSTBUF:
   return 1;
case PIPE_CAP_SEAMLESS_CUBE_MAP:
   return 1; /* class_3d >= NVA0_3D_CLASS; */
@@ -275,7 +276,6 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
case PIPE_CAP_QUERY_SO_OVERFLOW:
case PIPE_CAP_MEMOBJ:
-   case PIPE_CAP_LOAD_CONSTBUF:
case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
case PIPE_CAP_TILE_RASTER_ORDER:
case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index d62a5552536..3544afe044b 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -257,6 +257,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
case PIPE_CAP_COMPUTE:
case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
+   case PIPE_CAP_LOAD_CONSTBUF:
   return 1;
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
   return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
@@ -304,7 +305,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
case PIPE_CAP_QUERY_SO_OVERFLOW:
case PIPE_CAP_MEMOBJ:
-   case PIPE_CAP_LOAD_CONSTBUF:
case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
case PIPE_CAP_TILE_RASTER_ORDER:
case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
-- 
2.13.6

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Re: [Mesa-dev] [PATCH 16/19] etnaviv: GC7000: Factor out incompatible texture handling logic

[Christian Gmeiner]

2017-10-30 17:17 GMT+01:00 Wladimir J. van der Laan :
> This will be shared with the texture descriptor path.
>
> Signed-off-by: Wladimir J. van der Laan 

Reviewed-by: Christian Gmeiner 

> ---
>  src/gallium/drivers/etnaviv/etnaviv_texture.c | 40 
> +--
>  src/gallium/drivers/etnaviv/etnaviv_texture.h |  5 
>  2 files changed, 30 insertions(+), 15 deletions(-)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_texture.c 
> b/src/gallium/drivers/etnaviv/etnaviv_texture.c
> index 335a2df..55942a9 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_texture.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_texture.c
> @@ -164,22 +164,10 @@ etna_resource_sampler_compatible(struct etna_resource 
> *res)
> return true;
>  }
>
> -static struct pipe_sampler_view *
> -etna_create_sampler_view(struct pipe_context *pctx, struct pipe_resource 
> *prsc,
> - const struct pipe_sampler_view *so)
> +struct etna_resource *
> +etna_texture_handle_incompatible(struct pipe_context *pctx, struct 
> pipe_resource *prsc)
>  {
> -   struct etna_sampler_view *sv = CALLOC_STRUCT(etna_sampler_view);
> struct etna_resource *res = etna_resource(prsc);
> -   struct etna_context *ctx = etna_context(pctx);
> -   const uint32_t format = translate_texture_format(so->format);
> -   const bool ext = !!(format & EXT_FORMAT);
> -   const uint32_t swiz = get_texture_swiz(so->format, so->swizzle_r,
> -  so->swizzle_g, so->swizzle_b,
> -  so->swizzle_a);
> -
> -   if (!sv)
> -  return NULL;
> -
> if (!etna_resource_sampler_compatible(res)) {
>/* The original resource is not compatible with the sampler.
> * Allocate an appropriately tiled texture. */
> @@ -194,11 +182,33 @@ etna_create_sampler_view(struct pipe_context *pctx, 
> struct pipe_resource *prsc,
>}
>
>if (!res->texture) {
> - free(sv);
>   return NULL;
>}
>res = etna_resource(res->texture);
> }
> +   return res;
> +}
> +
> +static struct pipe_sampler_view *
> +etna_create_sampler_view(struct pipe_context *pctx, struct pipe_resource 
> *prsc,
> + const struct pipe_sampler_view *so)
> +{
> +   struct etna_sampler_view *sv = CALLOC_STRUCT(etna_sampler_view);
> +   struct etna_context *ctx = etna_context(pctx);
> +   const uint32_t format = translate_texture_format(so->format);
> +   const bool ext = !!(format & EXT_FORMAT);
> +   const uint32_t swiz = get_texture_swiz(so->format, so->swizzle_r,
> +  so->swizzle_g, so->swizzle_b,
> +  so->swizzle_a);
> +
> +   if (!sv)
> +  return NULL;
> +
> +   struct etna_resource *res = etna_texture_handle_incompatible(pctx, prsc);
> +   if (!res) {
> +  free(sv);
> +  return NULL;
> +   }
>
> sv->base = *so;
> pipe_reference_init(>base.reference, 1);
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_texture.h 
> b/src/gallium/drivers/etnaviv/etnaviv_texture.h
> index a7a67fc..9d1789e 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_texture.h
> +++ b/src/gallium/drivers/etnaviv/etnaviv_texture.h
> @@ -72,4 +72,9 @@ etna_sampler_view(struct pipe_sampler_view *view)
>  void
>  etna_texture_init(struct pipe_context *pctx);
>
> +/* If the original resource is not compatible with the sampler.  Allocate
> + * an appropriately tiled texture. */
> +struct etna_resource *
> +etna_texture_handle_incompatible(struct pipe_context *pctx, struct 
> pipe_resource *prsc);
> +
>  #endif
> --
> 2.7.4
>



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Re: [Mesa-dev] [PATCH 19/19] etnaviv: GC7000: Split off current texture code

[Christian Gmeiner]

2017-10-30 17:17 GMT+01:00 Wladimir J. van der Laan :
> Prepare for two texture handling paths, the descriptor-based
> path will be added in a future commit. These are structured
> so that the texture implementation handles its own state
> emission.
>
> Signed-off-by: Wladimir J. van der Laan 

Reviewed-by: Christian Gmeiner 

> ---
>  src/gallium/drivers/etnaviv/Makefile.sources   |   2 +
>  src/gallium/drivers/etnaviv/etnaviv_context.h  |   3 +
>  src/gallium/drivers/etnaviv/etnaviv_emit.c |  74 +-
>  src/gallium/drivers/etnaviv/etnaviv_texture.c  | 137 +-
>  src/gallium/drivers/etnaviv/etnaviv_texture.h  |  37 +--
>  .../drivers/etnaviv/etnaviv_texture_plain.c| 279 
> +
>  .../drivers/etnaviv/etnaviv_texture_plain.h|  77 ++
>  7 files changed, 367 insertions(+), 242 deletions(-)
>  create mode 100644 src/gallium/drivers/etnaviv/etnaviv_texture_plain.c
>  create mode 100644 src/gallium/drivers/etnaviv/etnaviv_texture_plain.h
>
> diff --git a/src/gallium/drivers/etnaviv/Makefile.sources 
> b/src/gallium/drivers/etnaviv/Makefile.sources
> index 56cc3b2..05ac073 100644
> --- a/src/gallium/drivers/etnaviv/Makefile.sources
> +++ b/src/gallium/drivers/etnaviv/Makefile.sources
> @@ -51,6 +51,8 @@ C_SOURCES :=  \
> etnaviv_surface.h \
> etnaviv_texture.c \
> etnaviv_texture.h \
> +   etnaviv_texture_plain.c \
> +   etnaviv_texture_plain.h \
> etnaviv_tiling.c \
> etnaviv_tiling.h \
> etnaviv_transfer.c \
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.h 
> b/src/gallium/drivers/etnaviv/etnaviv_context.h
> index 1ed38ce..6672a67 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_context.h
> +++ b/src/gallium/drivers/etnaviv/etnaviv_context.h
> @@ -100,6 +100,9 @@ struct etna_shader_uniform_info {
>  struct etna_context {
> struct pipe_context base;
>
> +   /* GPU-specific implementation to emit texture state */
> +   void (*emit_texture_state)(struct etna_context *pctx);
> +
> struct etna_specs specs;
> struct etna_screen *screen;
> struct etna_cmd_stream *stream;
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_emit.c 
> b/src/gallium/drivers/etnaviv/etnaviv_emit.c
> index b766005..3ad7467 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_emit.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_emit.c
> @@ -289,7 +289,6 @@ void
>  etna_emit_state(struct etna_context *ctx)
>  {
> struct etna_cmd_stream *stream = ctx->stream;
> -   uint32_t active_samplers = active_samplers_bits(ctx);
>
> /* Pre-reserve the command buffer space which we are likely to need.
>  * This must cover all the state emitted below, and the following
> @@ -625,77 +624,6 @@ etna_emit_state(struct etna_context *ctx)
>/*01668*/ EMIT_STATE_RELOC(TS_DEPTH_SURFACE_BASE, 
> >framebuffer.TS_DEPTH_SURFACE_BASE);
>/*0166C*/ EMIT_STATE(TS_DEPTH_CLEAR_VALUE, 
> ctx->framebuffer.TS_DEPTH_CLEAR_VALUE);
> }
> -
> -   if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
> -  for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
> - uint32_t val = 0; /* 0 == sampler inactive */
> -
> - /* set active samplers to their configuration value (determined by 
> both
> -  * the sampler state and sampler view) */
> - if ((1 << x) & active_samplers) {
> -struct etna_sampler_state *ss = 
> etna_sampler_state(ctx->sampler[x]);
> -struct etna_sampler_view *sv = 
> etna_sampler_view(ctx->sampler_view[x]);
> -
> -val = (ss->TE_SAMPLER_CONFIG0 & sv->TE_SAMPLER_CONFIG0_MASK) |
> -  sv->TE_SAMPLER_CONFIG0;
> - }
> -
> - /*02000*/ EMIT_STATE(TE_SAMPLER_CONFIG0(x), val);
> -  }
> -   }
> -   if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
> -  struct etna_sampler_view *sv;
> -
> -  for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
> - if ((1 << x) & active_samplers) {
> -sv = etna_sampler_view(ctx->sampler_view[x]);
> -/*02040*/ EMIT_STATE(TE_SAMPLER_SIZE(x), sv->TE_SAMPLER_SIZE);
> - }
> -  }
> -  for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
> - if ((1 << x) & active_samplers) {
> -sv = etna_sampler_view(ctx->sampler_view[x]);
> -/*02080*/ EMIT_STATE(TE_SAMPLER_LOG_SIZE(x), 
> sv->TE_SAMPLER_LOG_SIZE);
> - }
> -  }
> -   }
> -   if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
> -  struct etna_sampler_state *ss;
> -  struct etna_sampler_view *sv;
> -
> -  for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
> - if ((1 << x) & active_samplers) {
> -ss = etna_sampler_state(ctx->sampler[x]);
> -sv = etna_sampler_view(ctx->sampler_view[x]);
> -
> -/* min and max lod is determined both by the sampler and the 
> view */
> - 

Re: [Mesa-dev] [PATCH 18/19] etnaviv: GC7000: Move etna_coalesce to emit header file

[Christian Gmeiner]

2017-10-30 17:17 GMT+01:00 Wladimir J. van der Laan :
> Want to be able to emit state from the texture implementation.
>
> Signed-off-by: Wladimir J. van der Laan 

Reviewed-by: Christian Gmeiner 

> ---
>  src/gallium/drivers/etnaviv/etnaviv_emit.c | 83 
> --
>  src/gallium/drivers/etnaviv/etnaviv_emit.h | 83 
> ++
>  2 files changed, 83 insertions(+), 83 deletions(-)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_emit.c 
> b/src/gallium/drivers/etnaviv/etnaviv_emit.c
> index bc0f567..b766005 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_emit.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_emit.c
> @@ -44,12 +44,6 @@
>  #include "hw/state_blt.xml.h"
>  #include "util/u_math.h"
>
> -struct etna_coalesce {
> -   uint32_t start;
> -   uint32_t last_reg;
> -   uint32_t last_fixp;
> -};
> -
>  /* Queue a STALL command (queues 2 words) */
>  static inline void
>  CMD_STALL(struct etna_cmd_stream *stream, uint32_t from, uint32_t to)
> @@ -88,83 +82,6 @@ etna_stall(struct etna_cmd_stream *stream, uint32_t from, 
> uint32_t to)
> }
>  }
>
> -static void
> -etna_coalesce_start(struct etna_cmd_stream *stream,
> -struct etna_coalesce *coalesce)
> -{
> -   coalesce->start = etna_cmd_stream_offset(stream);
> -   coalesce->last_reg = 0;
> -   coalesce->last_fixp = 0;
> -}
> -
> -static void
> -etna_coalesce_end(struct etna_cmd_stream *stream,
> -  struct etna_coalesce *coalesce)
> -{
> -   uint32_t end = etna_cmd_stream_offset(stream);
> -   uint32_t size = end - coalesce->start;
> -
> -   if (size) {
> -  uint32_t offset = coalesce->start - 1;
> -  uint32_t value = etna_cmd_stream_get(stream, offset);
> -
> -  value |= VIV_FE_LOAD_STATE_HEADER_COUNT(size);
> -  etna_cmd_stream_set(stream, offset, value);
> -   }
> -
> -   /* append needed padding */
> -   if (end % 2 == 1)
> -  etna_cmd_stream_emit(stream, 0xdeadbeef);
> -}
> -
> -static void
> -check_coalsence(struct etna_cmd_stream *stream, struct etna_coalesce 
> *coalesce,
> -uint32_t reg, uint32_t fixp)
> -{
> -   if (coalesce->last_reg != 0) {
> -  if (((coalesce->last_reg + 4) != reg) || (coalesce->last_fixp != 
> fixp)) {
> - etna_coalesce_end(stream, coalesce);
> - etna_emit_load_state(stream, reg >> 2, 0, fixp);
> - coalesce->start = etna_cmd_stream_offset(stream);
> -  }
> -   } else {
> -  etna_emit_load_state(stream, reg >> 2, 0, fixp);
> -  coalesce->start = etna_cmd_stream_offset(stream);
> -   }
> -
> -   coalesce->last_reg = reg;
> -   coalesce->last_fixp = fixp;
> -}
> -
> -static inline void
> -etna_coalsence_emit(struct etna_cmd_stream *stream,
> -struct etna_coalesce *coalesce, uint32_t reg,
> -uint32_t value)
> -{
> -   check_coalsence(stream, coalesce, reg, 0);
> -   etna_cmd_stream_emit(stream, value);
> -}
> -
> -static inline void
> -etna_coalsence_emit_fixp(struct etna_cmd_stream *stream,
> - struct etna_coalesce *coalesce, uint32_t reg,
> - uint32_t value)
> -{
> -   check_coalsence(stream, coalesce, reg, 1);
> -   etna_cmd_stream_emit(stream, value);
> -}
> -
> -static inline void
> -etna_coalsence_emit_reloc(struct etna_cmd_stream *stream,
> -  struct etna_coalesce *coalesce, uint32_t reg,
> -  const struct etna_reloc *r)
> -{
> -   if (r->bo) {
> -  check_coalsence(stream, coalesce, reg, 0);
> -  etna_cmd_stream_reloc(stream, r);
> -   }
> -}
> -
>  #define EMIT_STATE(state_name, src_value) \
> etna_coalsence_emit(stream, , VIVS_##state_name, src_value)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_emit.h 
> b/src/gallium/drivers/etnaviv/etnaviv_emit.h
> index 3c3d129..dd90127 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_emit.h
> +++ b/src/gallium/drivers/etnaviv/etnaviv_emit.h
> @@ -34,6 +34,12 @@
>  struct etna_context;
>  struct compiled_rs_state;
>
> +struct etna_coalesce {
> +   uint32_t start;
> +   uint32_t last_reg;
> +   uint32_t last_fixp;
> +};
> +
>  static inline void
>  etna_emit_load_state(struct etna_cmd_stream *stream, const uint16_t offset,
>   const uint16_t count, const int fixp)
> @@ -138,6 +144,83 @@ etna_draw_instanced(struct etna_cmd_stream *stream,
> etna_cmd_stream_emit(stream, 0);
>  }
>
> +static inline void
> +etna_coalesce_start(struct etna_cmd_stream *stream,
> +struct etna_coalesce *coalesce)
> +{
> +   coalesce->start = etna_cmd_stream_offset(stream);
> +   coalesce->last_reg = 0;
> +   coalesce->last_fixp = 0;
> +}
> +
> +static inline void
> +etna_coalesce_end(struct etna_cmd_stream *stream,
> +  struct etna_coalesce *coalesce)
> +{
> +   uint32_t end = etna_cmd_stream_offset(stream);
> +   uint32_t size = end - coalesce->start;
> +
> +   if 

Re: [Mesa-dev] [PATCH 17/19] etnaviv: GC7000: Move active_samplers_bits to texture

[Christian Gmeiner]

2017-10-30 17:17 GMT+01:00 Wladimir J. van der Laan :
> This needs to be shared between texture_plain and texture_desc.
>
> Signed-off-by: Wladimir J. van der Laan 

Reviewed-by: Christian Gmeiner 

> ---
>  src/gallium/drivers/etnaviv/etnaviv_emit.c| 12 
>  src/gallium/drivers/etnaviv/etnaviv_texture.c |  6 ++
>  src/gallium/drivers/etnaviv/etnaviv_texture.h | 11 +++
>  3 files changed, 17 insertions(+), 12 deletions(-)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_emit.c 
> b/src/gallium/drivers/etnaviv/etnaviv_emit.c
> index 0990a37..bc0f567 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_emit.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_emit.c
> @@ -249,18 +249,6 @@ etna_submit_rs_state(struct etna_context *ctx,
> }
>  }
>
> -/* Create bit field that specifies which samplers are active and thus need 
> to be
> - * programmed
> - * 32 bits is enough for 32 samplers. As far as I know this is the upper 
> bound
> - * supported on any Vivante hw
> - * up to GC4000.
> - */
> -static uint32_t
> -active_samplers_bits(struct etna_context *ctx)
> -{
> -   return ctx->active_sampler_views & ctx->active_samplers;
> -}
> -
>  #define ETNA_3D_CONTEXT_SIZE  (400) /* keep this number above "Total state 
> updates (fixed)" from gen_weave_state tool */
>
>  static unsigned
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_texture.c 
> b/src/gallium/drivers/etnaviv/etnaviv_texture.c
> index 55942a9..d3fa109 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_texture.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_texture.c
> @@ -363,6 +363,12 @@ etna_texture_barrier(struct pipe_context *pctx, unsigned 
> flags)
> etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, 
> VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_TEXTURE);
>  }
>
> +uint32_t
> +active_samplers_bits(struct etna_context *ctx)
> +{
> +   return ctx->active_sampler_views & ctx->active_samplers;
> +}
> +
>  void
>  etna_texture_init(struct pipe_context *pctx)
>  {
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_texture.h 
> b/src/gallium/drivers/etnaviv/etnaviv_texture.h
> index 9d1789e..cc741a0 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_texture.h
> +++ b/src/gallium/drivers/etnaviv/etnaviv_texture.h
> @@ -34,6 +34,8 @@
>
>  #include "hw/state_3d.xml.h"
>
> +struct etna_context;
> +
>  struct etna_sampler_state {
> struct pipe_sampler_state base;
>
> @@ -77,4 +79,13 @@ etna_texture_init(struct pipe_context *pctx);
>  struct etna_resource *
>  etna_texture_handle_incompatible(struct pipe_context *pctx, struct 
> pipe_resource *prsc);
>
> +/* Create bit field that specifies which samplers are active and thus need 
> to be
> + * programmed
> + * 32 bits is enough for 32 samplers. As far as I know this is the upper 
> bound
> + * supported on any Vivante hw
> + * up to GC4000.
> + */
> +uint32_t
> +active_samplers_bits(struct etna_context *ctx);
> +
>  #endif
> --
> 2.7.4
>



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--
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Re: [Mesa-dev] [PATCH 10/19] etnaviv: GC7000: No RS align when using BLT

[Christian Gmeiner]

Reviewed-by: Christian Gmeiner 

2017-11-05 16:23 GMT+01:00 Christian Gmeiner :
> 2017-11-05 13:38 GMT+01:00 Wladimir :
 +  if (!ctx->specs.use_blt) {
 + /* This (ab)uses the RS as a plain buffer memset().
 +  * Currently uses a fixed row size of 64 bytes. Some 
 benchmarking with
 +  * different sizes may be in order. */
 + struct etna_bo *ts_bo = etna_resource(surf->base.texture)->ts_bo;
 + etna_compile_rs_state(ctx, >clear_command, &(struct 
 rs_state) {
 +.source_format = RS_FORMAT_A8R8G8B8,
 +.dest_format = RS_FORMAT_A8R8G8B8,
 +.dest = ts_bo,
 +.dest_offset = surf->surf.ts_offset,
 +.dest_stride = 0x40,
 +.dest_tiling = ETNA_LAYOUT_TILED,
 +.dither = {0x, 0x},
 +.width = 16,
 +.height = etna_align_up(surf->surf.ts_size / 0x40, 4),
 +.clear_value = {ctx->specs.ts_clear_value},
 +.clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
 +.clear_bits = 0x
 + });
 +  }
 } else {
 -  etna_rs_gen_clear_surface(ctx, surf, surf->level->clear_value);
 +  if (!ctx->specs.use_blt)
 + etna_rs_gen_clear_surface(ctx, surf, surf->level->clear_value);
 }

>>>
>>> if (!ctx->specs.use_blt) {
>>> } else {
>>>if (!ctx->specs.use_blt)
>>>   ..
>>> }
>>>
>>> Looks funny... btw. do you have a git branch somewhere to look at this 
>>> sereis?
>>
>> It looks somewhat funny but I don't think it's wrong.
>> There's an extra } there. Context is:
>>
>> if (surf->surf.ts_size) {
>>   if (!ctx->specs.use_blt) {
>> ...
>>   }
>> } else {
>> if (!ctx->specs.use_blt)
>> ..
>> }
>>
>> My current working tree can be found at
>> https://github.com/laanwj/mesa/tree/gc7000. It contains these patches
>> (but also some temporary local scaffolding, so be warned).
>
> Then it might not be as useful as I need it.
>
> --
> greets
> --
> Christian Gmeiner, MSc
>
> https://christian-gmeiner.info



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Re: [Mesa-dev] [PATCH 10/19] etnaviv: GC7000: No RS align when using BLT

[Christian Gmeiner]

2017-11-05 13:38 GMT+01:00 Wladimir :
>>> +  if (!ctx->specs.use_blt) {
>>> + /* This (ab)uses the RS as a plain buffer memset().
>>> +  * Currently uses a fixed row size of 64 bytes. Some benchmarking 
>>> with
>>> +  * different sizes may be in order. */
>>> + struct etna_bo *ts_bo = etna_resource(surf->base.texture)->ts_bo;
>>> + etna_compile_rs_state(ctx, >clear_command, &(struct 
>>> rs_state) {
>>> +.source_format = RS_FORMAT_A8R8G8B8,
>>> +.dest_format = RS_FORMAT_A8R8G8B8,
>>> +.dest = ts_bo,
>>> +.dest_offset = surf->surf.ts_offset,
>>> +.dest_stride = 0x40,
>>> +.dest_tiling = ETNA_LAYOUT_TILED,
>>> +.dither = {0x, 0x},
>>> +.width = 16,
>>> +.height = etna_align_up(surf->surf.ts_size / 0x40, 4),
>>> +.clear_value = {ctx->specs.ts_clear_value},
>>> +.clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
>>> +.clear_bits = 0x
>>> + });
>>> +  }
>>> } else {
>>> -  etna_rs_gen_clear_surface(ctx, surf, surf->level->clear_value);
>>> +  if (!ctx->specs.use_blt)
>>> + etna_rs_gen_clear_surface(ctx, surf, surf->level->clear_value);
>>> }
>>>
>>
>> if (!ctx->specs.use_blt) {
>> } else {
>>if (!ctx->specs.use_blt)
>>   ..
>> }
>>
>> Looks funny... btw. do you have a git branch somewhere to look at this 
>> sereis?
>
> It looks somewhat funny but I don't think it's wrong.
> There's an extra } there. Context is:
>
> if (surf->surf.ts_size) {
>   if (!ctx->specs.use_blt) {
> ...
>   }
> } else {
> if (!ctx->specs.use_blt)
> ..
> }
>
> My current working tree can be found at
> https://github.com/laanwj/mesa/tree/gc7000. It contains these patches
> (but also some temporary local scaffolding, so be warned).

Then it might not be as useful as I need it.

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Re: [Mesa-dev] [PATCH 15/19] etnaviv: GC7000: Track dirty sampler views

[Christian Gmeiner]

2017-10-30 17:17 GMT+01:00 Wladimir J. van der Laan :
> Need this to efficiently emit texture descriptor invalidations.
>
> Signed-off-by: Wladimir J. van der Laan 

Reviewed-by: Christian Gmeiner 

> ---
>  src/gallium/drivers/etnaviv/etnaviv_context.c | 1 +
>  src/gallium/drivers/etnaviv/etnaviv_context.h | 1 +
>  src/gallium/drivers/etnaviv/etnaviv_emit.c| 1 +
>  src/gallium/drivers/etnaviv/etnaviv_texture.c | 9 +++--
>  4 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.c 
> b/src/gallium/drivers/etnaviv/etnaviv_context.c
> index 7d54192..3038d21 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_context.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_context.c
> @@ -382,6 +382,7 @@ etna_cmd_stream_reset_notify(struct etna_cmd_stream 
> *stream, void *priv)
> }
>
> ctx->dirty = ~0L;
> +   ctx->dirty_sampler_views = ~0L;
>
> /* go through all the used resources and clear their status flag */
> LIST_FOR_EACH_ENTRY_SAFE(rsc, rsc_tmp, >used_resources, list)
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.h 
> b/src/gallium/drivers/etnaviv/etnaviv_context.h
> index 2903e09..1ed38ce 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_context.h
> +++ b/src/gallium/drivers/etnaviv/etnaviv_context.h
> @@ -156,6 +156,7 @@ struct etna_context {
> struct compiled_viewport_state viewport;
> unsigned num_fragment_sampler_views;
> uint32_t active_sampler_views;
> +   uint32_t dirty_sampler_views;
> struct pipe_sampler_view *sampler_view[PIPE_MAX_SAMPLERS];
> struct pipe_constant_buffer constant_buffer[PIPE_SHADER_TYPES];
> struct etna_vertexbuf_state vertex_buffer;
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_emit.c 
> b/src/gallium/drivers/etnaviv/etnaviv_emit.c
> index 692275a..0990a37 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_emit.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_emit.c
> @@ -970,4 +970,5 @@ etna_emit_state(struct etna_context *ctx)
>  #undef EMIT_STATE_FIXP
>  #undef EMIT_STATE_RELOC
> ctx->dirty = 0;
> +   ctx->dirty_sampler_views = 0;
>  }
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_texture.c 
> b/src/gallium/drivers/etnaviv/etnaviv_texture.c
> index 597390a..335a2df 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_texture.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_texture.c
> @@ -276,12 +276,14 @@ set_sampler_views(struct etna_context *ctx, unsigned 
> start, unsigned end,
>  {
> unsigned i, j;
> uint32_t mask = 1 << start;
> +   uint32_t prev_active_sampler_views = ctx->active_sampler_views;
>
> for (i = start, j = 0; j < nr; i++, j++, mask <<= 1) {
>pipe_sampler_view_reference(>sampler_view[i], views[j]);
> -  if (views[j])
> +  if (views[j]) {
>   ctx->active_sampler_views |= mask;
> -  else
> + ctx->dirty_sampler_views |= mask;
> +  } else
>   ctx->active_sampler_views &= ~mask;
> }
>
> @@ -289,6 +291,9 @@ set_sampler_views(struct etna_context *ctx, unsigned 
> start, unsigned end,
>pipe_sampler_view_reference(>sampler_view[i], NULL);
>ctx->active_sampler_views &= ~mask;
> }
> +
> +   /* sampler views that changed state (even to inactive) are also dirty */
> +   ctx->dirty_sampler_views |= ctx->active_sampler_views ^ 
> prev_active_sampler_views;
>  }
>
>  static inline void
> --
> 2.7.4
>



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Re: [Mesa-dev] [PATCH 14/19] etnaviv: GC7000: Make point sprites work on HALTI5

[Christian Gmeiner]

2017-10-30 17:17 GMT+01:00 Wladimir J. van der Laan :
> Track varying component offset of the point size output, as well as
> provide the offset of the point coord input.
>
> Signed-off-by: Wladimir J. van der Laan 

Reviewed-by: Christian Gmeiner 

> ---
>  src/gallium/drivers/etnaviv/etnaviv_compiler.c | 7 ++-
>  src/gallium/drivers/etnaviv/etnaviv_compiler.h | 1 +
>  src/gallium/drivers/etnaviv/etnaviv_shader.c   | 8 
>  3 files changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler.c 
> b/src/gallium/drivers/etnaviv/etnaviv_compiler.c
> index 3180646..4351175 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_compiler.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_compiler.c
> @@ -2550,12 +2550,14 @@ bool
>  etna_link_shader(struct etna_shader_link_info *info,
>   const struct etna_shader_variant *vs, const struct 
> etna_shader_variant *fs)
>  {
> +   int comp_ofs = 0;
> /* For each fragment input we need to find the associated vertex shader
>  * output, which can be found by matching on semantic name and index. A
>  * binary search could be used because the vs outputs are sorted by their
>  * semantic index and grouped by semantic type by fill_in_vs_outputs.
>  */
> assert(fs->infile.num_reg < ETNA_NUM_INPUTS);
> +   info->pcoord_varying_comp_ofs = -1;
>
> for (int idx = 0; idx < fs->infile.num_reg; ++idx) {
>const struct etna_shader_inout *fsio = >infile.reg[idx];
> @@ -2583,8 +2585,10 @@ etna_link_shader(struct etna_shader_link_info *info,
>
>
>/* point coord is position output from VS, so has no dedicated reg */
> -  if (fsio->semantic.Name == TGSI_SEMANTIC_PCOORD)
> +  if (fsio->semantic.Name == TGSI_SEMANTIC_PCOORD) {
> + info->pcoord_varying_comp_ofs = comp_ofs;
>   continue;
> +  }
>
>if (vsio == NULL) {
>   BUG("Semantic %d value %d not found in vertex shader outputs\n", 
> fsio->semantic.Name, fsio->semantic.Index);
> @@ -2592,6 +2596,7 @@ etna_link_shader(struct etna_shader_link_info *info,
>}
>
>varying->reg = vsio->reg;
> +  comp_ofs += varying->num_components;
> }
>
> assert(info->num_varyings == fs->infile.num_reg);
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler.h 
> b/src/gallium/drivers/etnaviv/etnaviv_compiler.h
> index f5c1689..48b1b21 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_compiler.h
> +++ b/src/gallium/drivers/etnaviv/etnaviv_compiler.h
> @@ -118,6 +118,7 @@ struct etna_shader_link_info {
> /* each PS input is annotated with the VS output reg */
> unsigned num_varyings;
> struct etna_varying varyings[ETNA_NUM_INPUTS];
> +   int pcoord_varying_comp_ofs;
>  };
>
>  bool
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_shader.c 
> b/src/gallium/drivers/etnaviv/etnaviv_shader.c
> index 6012680..04ababc 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_shader.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_shader.c
> @@ -179,6 +179,14 @@ etna_link_shaders(struct etna_context *ctx, struct 
> compiled_shader_state *cs,
> cs->GL_VARYING_COMPONENT_USE[0] = component_use[0];
> cs->GL_VARYING_COMPONENT_USE[1] = component_use[1];
>
> +   cs->GL_HALTI5_SH_SPECIALS =
> +  0x7f7f | /* unknown bits, probably other PS inputs */
> +  /* pointsize is last (see above) */
> +  VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT((vs->vs_pointsize_out_reg != 
> -1) ?
> +  cs->VS_OUTPUT_COUNT * 4 : 
> 0x00) |
> +  VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN((link.pcoord_varying_comp_ofs 
> != -1) ?
> +  link.pcoord_varying_comp_ofs : 
> 0x7f);
> +
> /* reference instruction memory */
> cs->vs_inst_mem_size = vs->code_size;
> cs->VS_INST_MEM = vs->code;
> --
> 2.7.4
>



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Re: [Mesa-dev] [PATCH 13/19] etnaviv: GC7000: State changes for HALTI3..5

[Christian Gmeiner]

2017-10-30 17:16 GMT+01:00 Wladimir J. van der Laan :
> Update state objects to add new state, and emit function to emit new
> state.
>
> Signed-off-by: Wladimir J. van der Laan 

Reviewed-by: Christian Gmeiner 

> ---
>  src/gallium/drivers/etnaviv/etnaviv_emit.c | 247 
> +++--
>  src/gallium/drivers/etnaviv/etnaviv_internal.h |   4 +
>  src/gallium/drivers/etnaviv/etnaviv_state.c|  35 +++-
>  src/gallium/drivers/etnaviv/etnaviv_zsa.c  |   3 +-
>  4 files changed, 217 insertions(+), 72 deletions(-)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_emit.c 
> b/src/gallium/drivers/etnaviv/etnaviv_emit.c
> index f388a89..692275a 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_emit.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_emit.c
> @@ -291,6 +291,91 @@ required_stream_size(struct etna_context *ctx)
> return size;
>  }
>
> +/* Emit state that only exists on HALTI5+ */
> +static void
> +emit_halti5_only_state(struct etna_context *ctx, int vs_output_count)
> +{
> +   struct etna_cmd_stream *stream = ctx->stream;
> +   uint32_t dirty = ctx->dirty;
> +   struct etna_coalesce coalesce;
> +
> +   etna_coalesce_start(stream, );
> +   if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
> +  /* Magic states (load balancing, inter-unit sync, buffers) */
> +  /*00870*/ EMIT_STATE(VS_HALTI5_OUTPUT_COUNT, vs_output_count | 
> ((vs_output_count * 0x10) << 8));
> +  /*008A0*/ EMIT_STATE(VS_HALTI5_UNK008A0, 0x0001000e | 
> ((0x110/vs_output_count) << 20));
> +  for (int x = 0; x < 4; ++x) {
> + /*008E0*/ EMIT_STATE(VS_HALTI5_OUTPUT(x), 
> ctx->shader_state.VS_OUTPUT[x]);
> +  }
> +   }
> +   if (unlikely(dirty & (ETNA_DIRTY_VERTEX_ELEMENTS | ETNA_DIRTY_SHADER))) {
> +  for (int x = 0; x < 4; ++x) {
> + /*008C0*/ EMIT_STATE(VS_HALTI5_INPUT(x), 
> ctx->shader_state.VS_INPUT[x]);
> +  }
> +   }
> +   if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
> +  /*00A90*/ EMIT_STATE(PA_VARYING_NUM_COMPONENTS(0), 
> ctx->shader_state.GL_VARYING_NUM_COMPONENTS);
> +  /*00AA8*/ EMIT_STATE(PA_VS_OUTPUT_COUNT, vs_output_count);
> +  /*01080*/ EMIT_STATE(PS_VARYING_NUM_COMPONENTS(0), 
> ctx->shader_state.GL_VARYING_NUM_COMPONENTS);
> +  /*03888*/ EMIT_STATE(GL_HALTI5_SH_SPECIALS, 
> ctx->shader_state.GL_HALTI5_SH_SPECIALS);
> +   }
> +   etna_coalesce_end(stream, );
> +}
> +
> +/* Emit state that no longer exists on HALTI5 */
> +static void
> +emit_pre_halti5_state(struct etna_context *ctx)
> +{
> +   struct etna_cmd_stream *stream = ctx->stream;
> +   uint32_t dirty = ctx->dirty;
> +   struct etna_coalesce coalesce;
> +
> +   etna_coalesce_start(stream, );
> +   if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
> +  /*00800*/ EMIT_STATE(VS_END_PC, ctx->shader_state.VS_END_PC);
> +   }
> +   if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
> +  for (int x = 0; x < 4; ++x) {
> +/*00810*/ EMIT_STATE(VS_OUTPUT(x), ctx->shader_state.VS_OUTPUT[x]);
> +  }
> +   }
> +   if (unlikely(dirty & (ETNA_DIRTY_VERTEX_ELEMENTS | ETNA_DIRTY_SHADER))) {
> +  for (int x = 0; x < 4; ++x) {
> +/*00820*/ EMIT_STATE(VS_INPUT(x), ctx->shader_state.VS_INPUT[x]);
> +  }
> +   }
> +   if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
> +  /*00838*/ EMIT_STATE(VS_START_PC, ctx->shader_state.VS_START_PC);
> +   }
> +   if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
> +  for (int x = 0; x < 10; ++x) {
> + /*00A40*/ EMIT_STATE(PA_SHADER_ATTRIBUTES(x), 
> ctx->shader_state.PA_SHADER_ATTRIBUTES[x]);
> +  }
> +   }
> +   if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) {
> +  /*00E04*/ EMIT_STATE(RA_MULTISAMPLE_UNK00E04, 
> ctx->framebuffer.RA_MULTISAMPLE_UNK00E04);
> +  for (int x = 0; x < 4; ++x) {
> + /*00E10*/ EMIT_STATE(RA_MULTISAMPLE_UNK00E10(x), 
> ctx->framebuffer.RA_MULTISAMPLE_UNK00E10[x]);
> +  }
> +  for (int x = 0; x < 16; ++x) {
> + /*00E40*/ EMIT_STATE(RA_CENTROID_TABLE(x), 
> ctx->framebuffer.RA_CENTROID_TABLE[x]);
> +  }
> +   }
> +   if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_FRAMEBUFFER))) {
> +  /*01000*/ EMIT_STATE(PS_END_PC, ctx->shader_state.PS_END_PC);
> +   }
> +   if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_FRAMEBUFFER))) {
> +  /*01018*/ EMIT_STATE(PS_START_PC, ctx->shader_state.PS_START_PC);
> +   }
> +   if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
> +  /*03820*/ EMIT_STATE(GL_VARYING_NUM_COMPONENTS, 
> ctx->shader_state.GL_VARYING_NUM_COMPONENTS);
> +  for (int x = 0; x < 2; ++x) {
> + /*03828*/ EMIT_STATE(GL_VARYING_COMPONENT_USE(x), 
> ctx->shader_state.GL_VARYING_COMPONENT_USE[x]);
> +  }
> +   }
> +   etna_coalesce_end(stream, );
> +}
> +
>  /* Weave state before draw operation. This function merges all the compiled
>   * state blocks under the context into one device register state. Parts of
>   * this state that are changed since last call (dirty) will be 

Re: [Mesa-dev] [PATCH 12/19] etnaviv: GC7000: Update screen specs for HALTI5

[Christian Gmeiner]

2017-10-30 17:16 GMT+01:00 Wladimir J. van der Laan :
> - This core must load shaders from memory (AFAIK)
> - Yet another new location for UNIFORMS
>
> Signed-off-by: Wladimir J. van der Laan 

Reviewed-by: Christian Gmeiner 

> ---
>  src/gallium/drivers/etnaviv/etnaviv_screen.c | 19 +++
>  1 file changed, 15 insertions(+), 4 deletions(-)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c 
> b/src/gallium/drivers/etnaviv/etnaviv_screen.c
> index e48b395..1db0743 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_screen.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c
> @@ -730,7 +730,13 @@ etna_get_specs(struct etna_screen *screen)
> screen->specs.has_halti2_instructions =
>VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
>
> -   if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
> +   if (screen->specs.halti >= 5) {
> +  /* GC7000 - this core must load shaders from memory. */
> +  screen->specs.vs_offset = 0;
> +  screen->specs.ps_offset = 0;
> +  screen->specs.max_instructions = 0; /* Do not program shaders manually 
> */
> +  screen->specs.has_icache = true;
> +   } else if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
>/* GC3000 - this core is capable of loading shaders from
> * memory. It can also run shaders from registers, as a fallback, but
> * "max_instructions" does not have the correct value. It has place for
> @@ -783,9 +789,14 @@ etna_get_specs(struct etna_screen *screen)
>screen->specs.max_vs_uniforms = 256;
>screen->specs.max_ps_uniforms = 256;
> }
> -   /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess
> -   */
> -   if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1)) {
> +
> +   if (screen->specs.halti >= 5) {
> +  screen->specs.has_unified_uniforms = true;
> +  screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0);
> +  screen->specs.ps_uniforms_offset = 
> VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4);
> +   } else if (screen->specs.halti >= 1) {
> +  /* unified uniform memory on GC3000 - HALTI1 feature bit is just a 
> guess
> +  */
>screen->specs.has_unified_uniforms = true;
>screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0);
>/* hardcode PS uniforms to start after end of VS uniforms -
> --
> 2.7.4
>



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Re: [Mesa-dev] [PATCH 11/19] etnaviv: GC7000: Update context reset for ..HALTI5

[Christian Gmeiner]

2017-10-30 17:16 GMT+01:00 Wladimir J. van der Laan :
> Update context reset for HALTI3..HALTI5, sorting states for the HALTI
> version that has them.
>
> Signed-off-by: Wladimir J. van der Laan 

Reviewed-by: Christian Gmeiner 

> ---
>  src/gallium/drivers/etnaviv/etnaviv_context.c | 37 
> +++
>  1 file changed, 32 insertions(+), 5 deletions(-)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.c 
> b/src/gallium/drivers/etnaviv/etnaviv_context.c
> index 56ab395..7d54192 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_context.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_context.c
> @@ -333,10 +333,11 @@ etna_cmd_stream_reset_notify(struct etna_cmd_stream 
> *stream, void *priv)
>
> etna_set_state(stream, VIVS_GL_API_MODE, VIVS_GL_API_MODE_OPENGL);
> etna_set_state(stream, VIVS_GL_VERTEX_ELEMENT_CONFIG, 0x0001);
> +   /* blob sets this to 0x4031 on GC7000, seems to make no difference,
> +* but keep it in mind if depth behaves strangely. */
> etna_set_state(stream, VIVS_RA_EARLY_DEPTH, 0x0031);
> etna_set_state(stream, VIVS_PA_W_CLIP_LIMIT, 0x3401);
> -   etna_set_state(stream, VIVS_PA_FLAGS, 0x); /* blob sets 
> ZCONVERT_BYPASS on GC3000, this messes up z for us */
> -   etna_set_state(stream, VIVS_RA_UNK00E0C, 0x);
> +   etna_set_state(stream, VIVS_PA_FLAGS, 0x); /* blob sets 
> ZCONVERT_BYPASS on GC3000+, this messes up z for us */
> etna_set_state(stream, VIVS_PA_VIEWPORT_UNK00A80, 0x38a01404);
> etna_set_state(stream, VIVS_PA_VIEWPORT_UNK00A84, fui(8192.0));
> etna_set_state(stream, VIVS_PA_ZFARCLIPPING, 0x);
> @@ -344,11 +345,37 @@ etna_cmd_stream_reset_notify(struct etna_cmd_stream 
> *stream, void *priv)
> etna_set_state(stream, VIVS_PE_ALPHA_COLOR_EXT1, 0x);
> etna_set_state(stream, VIVS_RA_HDEPTH_CONTROL, 0x7000);
> etna_set_state(stream, VIVS_PE_STENCIL_CONFIG_EXT2, 0x);
> -   etna_set_state(stream, VIVS_GL_UNK03834, 0x);
> -   etna_set_state(stream, VIVS_GL_UNK03838, 0x);
> -   etna_set_state(stream, VIVS_GL_UNK03854, 0x);
> etna_set_state(stream, VIVS_PS_CONTROL_EXT, 0x);
>
> +   /* There is no HALTI0 specific state */
> +   if (ctx->specs.halti >= 1) { /* Only on HALTI1+ */
> +  etna_set_state(stream, VIVS_VS_HALTI1_UNK00884, 0x0808);
> +   }
> +   if (ctx->specs.halti >= 2) { /* Only on HALTI2+ */
> +  etna_set_state(stream, VIVS_RA_UNK00E0C, 0x);
> +   }
> +   if (ctx->specs.halti >= 3) { /* Only on HALTI3+ */
> +  etna_set_state(stream, VIVS_PE_MEM_CONFIG, 0x); /* TODO: cache 
> modes */
> +  etna_set_state(stream, VIVS_PS_HALTI3_UNK0103C, 0x76543210);
> +   }
> +   if (ctx->specs.halti >= 4) { /* Only on HALTI4+ */
> +  etna_set_state(stream, VIVS_PS_MSAA_CONFIG, 0x6fff & 0xf70f & 
> 0xfff6 &
> +  0x6fff & 0xf6ff & 
> 0xff7f);
> +  etna_set_state(stream, VIVS_PE_HALTI4_UNK014C0, 0x);
> +   }
> +   if (ctx->specs.halti >= 5) { /* Only on HALTI5+ */
> +  etna_set_state(stream, VIVS_NTE_DESCRIPTOR_UNK14C40, 0x0001);
> +  etna_set_state(stream, VIVS_FE_HALTI5_UNK007D8, 0x0002);
> +  etna_set_state(stream, VIVS_FE_HALTI5_UNK007C4, 0x);
> +  etna_set_state(stream, VIVS_PS_SAMPLER_BASE, 0x);
> +  etna_set_state(stream, VIVS_VS_SAMPLER_BASE, 0x0020);
> +  etna_set_state(stream, VIVS_SH_CONFIG, VIVS_SH_CONFIG_RTNE_ROUNDING);
> +   } else { /* Only on pre-HALTI5 */
> +  etna_set_state(stream, VIVS_GL_UNK03834, 0x);
> +  etna_set_state(stream, VIVS_GL_UNK03838, 0x);
> +  etna_set_state(stream, VIVS_GL_UNK03854, 0x);
> +   }
> +
> if (!ctx->specs.use_blt) {
>/* Enable SINGLE_BUFFER for resolve, if supported */
>etna_set_state(stream, VIVS_RS_SINGLE_BUFFER, 
> COND(ctx->specs.single_buffer, VIVS_RS_SINGLE_BUFFER_ENABLE));
> --
> 2.7.4
>



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--
Christian Gmeiner, MSc

https://christian-gmeiner.info
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[Mesa-dev] [Bug 103579] Vertex shader causes compiler to crash in SPIRV-to-NIR

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103579

Bug ID: 103579
   Summary: Vertex shader causes compiler to crash in SPIRV-to-NIR
   Product: Mesa
   Version: git
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Vulkan/radeon
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: mais...@archlinux.us
QA Contact: mesa-dev@lists.freedesktop.org

Created attachment 135247
  --> https://bugs.freedesktop.org/attachment.cgi?id=135247=edit
Repro shader

The attached vertex shader crashes when trying to emit code for

 %23 = OpLoad %19 %22 (gl_InstanceIndex)

with backtrace:
#0  0x74a15f66 in vtn_pointer_to_offset (b=0x56fb88b0,
ptr=0x57023280, index_out=0x7fffb2d0, end_idx_out=0x7fffb2c8) at
spirv/vtn_variables.c:521
#1  0x74a16e91 in vtn_block_load (b=0x56fb88b0, src=0x57023280)
at spirv/vtn_variables.c:838
#2  0x74a17211 in vtn_variable_load (b=0x56fb88b0,
src=0x57023280) at spirv/vtn_variables.c:927
#3  0x74a18f3d in vtn_handle_variables (b=0x56fb88b0,
opcode=SpvOpLoad, w=0x570249c8, count=4) at spirv/vtn_variables.c:1841
#4  0x74a088fe in vtn_handle_body_instruction (b=0x56fb88b0,
opcode=SpvOpLoad, w=0x570249c8, count=4) at spirv/spirv_to_nir.c:3092
#5  0x74a00cb0 in vtn_foreach_instruction (b=0x56fb88b0,
start=0x57024764, end=0x57024a78, handler=0x74a08834
) at spirv/spirv_to_nir.c:244
#6  0x74a0e9e2 in vtn_emit_cf_list (b=0x56fb88b0,
cf_list=0x56fa9ef0, switch_fall_var=0x0, has_switch_break=0x0,
handler=0x74a08834 ) at spirv/vtn_cfg.c:600
#7  0x74a0f20e in vtn_function_emit (b=0x56fb88b0,
func=0x56fa9ed0, instruction_handler=0x74a08834
) at spirv/vtn_cfg.c:775
#8  0x74a08d9f in spirv_to_nir (words=0x57024748, word_count=608,
spec=0x0, num_spec=0, stage=MESA_SHADER_VERTEX, entry_point_name=0x55bdb9b8
"main", ext=0x7fffb820, options=0x74a4fd20 ) at
spirv/spirv_to_nir.c:3376
#9  0x7494e318 in radv_shader_compile_to_nir (device=0x56e2d400,
module=0x570240e0, entrypoint_name=0x55bdb9b8 "main",
stage=MESA_SHADER_VERTEX, spec_info=0x0) at radv_shader.c:209
#10 0x74948d80 in radv_create_shaders (pipeline=0x56fce9f0,
device=0x56e2d400, cache=0x56e354f0, key=..., pStages=0x7fffbc10)
at radv_pipeline.c:1821
#11 0x74949869 in radv_pipeline_init (pipeline=0x56fce9f0,
device=0x56e2d400, cache=0x56e354f0, pCreateInfo=0x56fb40c8,
extra=0x0, alloc=0x56e2d408) at radv_pipeline.c:1983
#12 0x7494a738 in radv_graphics_pipeline_create
(_device=0x56e2d400, _cache=0x56e354f0, pCreateInfo=0x56fb40c8,
extra=0x0, pAllocator=0x0, pPipeline=0x57047c70) at radv_pipeline.c:2260
#13 0x7494a7f6 in radv_CreateGraphicsPipelines (_device=0x56e2d400,
pipelineCache=0x56e354f0, count=1, pCreateInfos=0x56fb40c8,
pAllocator=0x0, pPipelines=0x57047c70) at radv_pipeline.c:2285

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Re: [Mesa-dev] [PATCH 10/19] etnaviv: GC7000: No RS align when using BLT

[Wladimir]

>> +  if (!ctx->specs.use_blt) {
>> + /* This (ab)uses the RS as a plain buffer memset().
>> +  * Currently uses a fixed row size of 64 bytes. Some benchmarking 
>> with
>> +  * different sizes may be in order. */
>> + struct etna_bo *ts_bo = etna_resource(surf->base.texture)->ts_bo;
>> + etna_compile_rs_state(ctx, >clear_command, &(struct 
>> rs_state) {
>> +.source_format = RS_FORMAT_A8R8G8B8,
>> +.dest_format = RS_FORMAT_A8R8G8B8,
>> +.dest = ts_bo,
>> +.dest_offset = surf->surf.ts_offset,
>> +.dest_stride = 0x40,
>> +.dest_tiling = ETNA_LAYOUT_TILED,
>> +.dither = {0x, 0x},
>> +.width = 16,
>> +.height = etna_align_up(surf->surf.ts_size / 0x40, 4),
>> +.clear_value = {ctx->specs.ts_clear_value},
>> +.clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
>> +.clear_bits = 0x
>> + });
>> +  }
>> } else {
>> -  etna_rs_gen_clear_surface(ctx, surf, surf->level->clear_value);
>> +  if (!ctx->specs.use_blt)
>> + etna_rs_gen_clear_surface(ctx, surf, surf->level->clear_value);
>> }
>>
>
> if (!ctx->specs.use_blt) {
> } else {
>if (!ctx->specs.use_blt)
>   ..
> }
>
> Looks funny... btw. do you have a git branch somewhere to look at this sereis?

It looks somewhat funny but I don't think it's wrong.
There's an extra } there. Context is:

if (surf->surf.ts_size) {
  if (!ctx->specs.use_blt) {
...
  }
} else {
if (!ctx->specs.use_blt)
..
}

My current working tree can be found at
https://github.com/laanwj/mesa/tree/gc7000. It contains these patches
(but also some temporary local scaffolding, so be warned).

Wladimir
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Re: [Mesa-dev] [PATCH 10/19] etnaviv: GC7000: No RS align when using BLT

[Christian Gmeiner]

2017-10-30 17:16 GMT+01:00 Wladimir J. van der Laan :
> RS align is not necessary and might even be harmful when using the BLT
> engine for blitting.
>
> Signed-off-by: Wladimir J. van der Laan 
> ---
>  src/gallium/drivers/etnaviv/etnaviv_resource.c | 15 +
>  src/gallium/drivers/etnaviv/etnaviv_surface.c  | 41 +
>  src/gallium/drivers/etnaviv/etnaviv_transfer.c | 42 
> ++
>  3 files changed, 53 insertions(+), 45 deletions(-)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.c 
> b/src/gallium/drivers/etnaviv/etnaviv_resource.c
> index d6cccd2..743a1c0 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_resource.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_resource.c
> @@ -211,9 +211,11 @@ etna_resource_alloc(struct pipe_screen *pscreen, 
> unsigned layout,
>
> /* If we have the TEXTURE_HALIGN feature, we can always align to the
>  * resolve engine's width.  If not, we must not align resources used
> -* only for textures. */
> -   bool rs_align = VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN) ||
> -   !etna_resource_sampler_only(templat);
> +* only for textures. If this GPU uses the BLT engine, never do RS align.
> +*/
> +   bool rs_align = screen->specs.use_blt ? false : (
> +  VIV_FEATURE(screen, chipMinorFeatures1, 
> TEXTURE_HALIGN) ||
> +  !etna_resource_sampler_only(templat));
>
> /* Determine needed padding (alignment of height/width) */
> unsigned paddingX = 0, paddingY = 0;
> @@ -222,7 +224,7 @@ etna_resource_alloc(struct pipe_screen *pscreen, unsigned 
> layout,
>  , );
> assert(paddingX && paddingY);
>
> -   if (templat->target != PIPE_BUFFER)
> +   if (!screen->specs.use_blt && templat->target != PIPE_BUFFER)
>etna_adjust_rs_align(screen->specs.pixel_pipes, NULL, );
>
> if (templat->bind & PIPE_BIND_SCANOUT) {
> @@ -231,7 +233,7 @@ etna_resource_alloc(struct pipe_screen *pscreen, unsigned 
> layout,
>struct winsys_handle handle;
>
>/* pad scanout buffer size to be compatible with the RS */
> -  if (modifier == DRM_FORMAT_MOD_LINEAR)
> +  if (!screen->specs.use_blt && modifier == DRM_FORMAT_MOD_LINEAR)
>   etna_adjust_rs_align(screen->specs.pixel_pipes, , 
> );
>
>scanout_templat.width0 = align(scanout_templat.width0, paddingX);
> @@ -514,7 +516,8 @@ etna_resource_from_handle(struct pipe_screen *pscreen,
>  VIV_FEATURE(screen, chipMinorFeatures1, 
> TEXTURE_HALIGN),
>  , , >halign);
>
> -   etna_adjust_rs_align(screen->specs.pixel_pipes, NULL, );
> +   if (!screen->specs.use_blt)
> +  etna_adjust_rs_align(screen->specs.pixel_pipes, NULL, );
> level->padded_width = align(level->width, paddingX);
> level->padded_height = align(level->height, paddingY);
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_surface.c 
> b/src/gallium/drivers/etnaviv/etnaviv_surface.c
> index 4b95f65..4429573 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_surface.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_surface.c
> @@ -116,26 +116,29 @@ etna_create_surface(struct pipe_context *pctx, struct 
> pipe_resource *prsc,
>surf->ts_reloc.offset = surf->surf.ts_offset;
>surf->ts_reloc.flags = 0;
>
> -  /* This (ab)uses the RS as a plain buffer memset().
> -   * Currently uses a fixed row size of 64 bytes. Some benchmarking with
> -   * different sizes may be in order. */
> -  struct etna_bo *ts_bo = etna_resource(surf->base.texture)->ts_bo;
> -  etna_compile_rs_state(ctx, >clear_command, &(struct rs_state) {
> - .source_format = RS_FORMAT_A8R8G8B8,
> - .dest_format = RS_FORMAT_A8R8G8B8,
> - .dest = ts_bo,
> - .dest_offset = surf->surf.ts_offset,
> - .dest_stride = 0x40,
> - .dest_tiling = ETNA_LAYOUT_TILED,
> - .dither = {0x, 0x},
> - .width = 16,
> - .height = etna_align_up(surf->surf.ts_size / 0x40, 4),
> - .clear_value = {ctx->specs.ts_clear_value},
> - .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
> - .clear_bits = 0x
> -  });
> +  if (!ctx->specs.use_blt) {
> + /* This (ab)uses the RS as a plain buffer memset().
> +  * Currently uses a fixed row size of 64 bytes. Some benchmarking 
> with
> +  * different sizes may be in order. */
> + struct etna_bo *ts_bo = etna_resource(surf->base.texture)->ts_bo;
> + etna_compile_rs_state(ctx, >clear_command, &(struct rs_state) 
> {
> +.source_format = RS_FORMAT_A8R8G8B8,
> +.dest_format = RS_FORMAT_A8R8G8B8,
> +.dest = ts_bo,
> +.dest_offset = surf->surf.ts_offset,
> +.dest_stride = 0x40,
> +.dest_tiling = ETNA_LAYOUT_TILED,
> +.dither = {0x, 

Re: [Mesa-dev] [PATCH 08/19] etnaviv: GC7000: Split off RS blit functions

[Wladimir]

On Sun, Nov 5, 2017 at 1:09 PM, Christian Gmeiner
 wrote:
> 2017-10-30 17:16 GMT+01:00 Wladimir J. van der Laan :
>> Prepare for BLT-based blitting path by moving RS-based
>> blitting to its own implementation file.
>>
>> Signed-off-by: Wladimir J. van der Laan 
>> ---
>>  src/gallium/drivers/etnaviv/Makefile.sources   |   1 +
>
> src/gallium/drivers/etnaviv/meson.build needs changed too.
>
>>  src/gallium/drivers/etnaviv/etnaviv_clear_blit.c   | 553 +--
>>  src/gallium/drivers/etnaviv/etnaviv_clear_blit.h   |   9 +
>>  .../drivers/etnaviv/etnaviv_clear_blit_rs.c| 595 
>> +
>
> Maybe we could move the rs specific stuff directly into
> etnaviv_rs.[ch]? So we end with
> etnaviv_blt.[ch] and etnaviv_rs.[ch]. (Just an idea I had during review).

I also thought about that, but kept the low/high level separation as
it was already there, as I didn't want to make it inconsistent between
RS and BLT. But I think it's a good idea in itself.

When that's done I also think we should move the RS emit code back
into etna_rs.c, that would make it self-contained.

Wladimir
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Re: [Mesa-dev] [PATCH 09/19] etnaviv: GC7000: BLT engine blitting support

[Christian Gmeiner]

2017-10-30 17:16 GMT+01:00 Wladimir J. van der Laan :
> Add an implemenation of key clear_blit functions using the BLT engine
> that replaced the RS on GC7000.
>
> Signed-off-by: Wladimir J. van der Laan 
> ---
>  src/gallium/drivers/etnaviv/Makefile.sources   |   1 +

src/gallium/drivers/etnaviv/meson.build needs changed too.

>  src/gallium/drivers/etnaviv/etnaviv_clear_blit.c   |   7 +-
>  src/gallium/drivers/etnaviv/etnaviv_clear_blit.h   |   3 +
>  .../drivers/etnaviv/etnaviv_clear_blit_blt.c   | 412 
> +
>  src/gallium/drivers/etnaviv/etnaviv_context.c  |   6 +-
>  src/gallium/drivers/etnaviv/etnaviv_internal.h |   2 +
>  src/gallium/drivers/etnaviv/etnaviv_screen.c   |   2 +
>  7 files changed, 430 insertions(+), 3 deletions(-)
>  create mode 100644 src/gallium/drivers/etnaviv/etnaviv_clear_blit_blt.c
>
> diff --git a/src/gallium/drivers/etnaviv/Makefile.sources 
> b/src/gallium/drivers/etnaviv/Makefile.sources
> index f4acaa2..56cc3b2 100644
> --- a/src/gallium/drivers/etnaviv/Makefile.sources
> +++ b/src/gallium/drivers/etnaviv/Makefile.sources
> @@ -13,6 +13,7 @@ C_SOURCES :=  \
> etnaviv_blt.h \
> etnaviv_clear_blit.c \
> etnaviv_clear_blit.h \
> +   etnaviv_clear_blit_blt.c \
> etnaviv_clear_blit_rs.c \
> etnaviv_compiler.c \
> etnaviv_compiler.h \
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c 
> b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
> index faf8f39..3b3ab00 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
> @@ -215,10 +215,15 @@ etna_copy_resource_box(struct pipe_context *pctx, 
> struct pipe_resource *dst,
>  void
>  etna_clear_blit_init(struct pipe_context *pctx)
>  {
> +   struct etna_context *ctx = etna_context(pctx);
> +
> pctx->clear_render_target = etna_clear_render_target;
> pctx->clear_depth_stencil = etna_clear_depth_stencil;
> pctx->resource_copy_region = etna_resource_copy_region;
> pctx->flush_resource = etna_flush_resource;
>
> -   etna_clear_blit_rs_init(pctx);
> +   if (ctx->specs.use_blt)
> +  etna_clear_blit_blt_init(pctx);
> +   else
> +  etna_clear_blit_rs_init(pctx);
>  }
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.h 
> b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.h
> index 7f84d2e..57b75e8 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.h
> +++ b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.h
> @@ -57,6 +57,9 @@ void
>  etna_clear_blit_init(struct pipe_context *pctx);
>
>  void
> +etna_clear_blit_blt_init(struct pipe_context *pctx);
> +
> +void
>  etna_clear_blit_rs_init(struct pipe_context *pctx);
>
>  #endif
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_clear_blit_blt.c 
> b/src/gallium/drivers/etnaviv/etnaviv_clear_blit_blt.c
> new file mode 100644
> index 000..e0c26cc
> --- /dev/null
> +++ b/src/gallium/drivers/etnaviv/etnaviv_clear_blit_blt.c
> @@ -0,0 +1,412 @@
> +/*
> + * Copyright (c) 2017 Etnaviv Project
> + * Copyright (C) 2017 Zodiac Inflight Innovations
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sub license,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the
> + * next paragraph) shall be included in all copies or substantial portions
> + * of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> + * DEALINGS IN THE SOFTWARE.
> + *
> + * Authors:
> + *Wladimir J. van der Laan 
> + */
> +
> +#include "etnaviv_clear_blit.h"
> +
> +#include "hw/common.xml.h"
> +
> +#include "etnaviv_blt.h"
> +#include "etnaviv_context.h"
> +#include "etnaviv_emit.h"
> +#include "etnaviv_format.h"
> +#include "etnaviv_resource.h"
> +#include "etnaviv_surface.h"
> +#include "etnaviv_translate.h"
> +
> +#include "pipe/p_defines.h"
> +#include "pipe/p_state.h"
> +#include "util/u_blitter.h"
> +#include "util/u_inlines.h"
> +#include "util/u_memory.h"
> +#include "util/u_surface.h"
> +
> +#define translate_blt_format translate_rs_format
> +
> +static void
> +etna_blit_clear_color_blt(struct 

Re: [Mesa-dev] [PATCH 08/19] etnaviv: GC7000: Split off RS blit functions

[Christian Gmeiner]

2017-10-30 17:16 GMT+01:00 Wladimir J. van der Laan :
> Prepare for BLT-based blitting path by moving RS-based
> blitting to its own implementation file.
>
> Signed-off-by: Wladimir J. van der Laan 
> ---
>  src/gallium/drivers/etnaviv/Makefile.sources   |   1 +

src/gallium/drivers/etnaviv/meson.build needs changed too.

>  src/gallium/drivers/etnaviv/etnaviv_clear_blit.c   | 553 +--
>  src/gallium/drivers/etnaviv/etnaviv_clear_blit.h   |   9 +
>  .../drivers/etnaviv/etnaviv_clear_blit_rs.c| 595 
> +

Maybe we could move the rs specific stuff directly into
etnaviv_rs.[ch]? So we end with
etnaviv_blt.[ch] and etnaviv_rs.[ch]. (Just an idea I had during review).

>  4 files changed, 610 insertions(+), 548 deletions(-)
>  create mode 100644 src/gallium/drivers/etnaviv/etnaviv_clear_blit_rs.c
>
> diff --git a/src/gallium/drivers/etnaviv/Makefile.sources 
> b/src/gallium/drivers/etnaviv/Makefile.sources
> index 3fab212..f4acaa2 100644
> --- a/src/gallium/drivers/etnaviv/Makefile.sources
> +++ b/src/gallium/drivers/etnaviv/Makefile.sources
> @@ -13,6 +13,7 @@ C_SOURCES :=  \
> etnaviv_blt.h \
> etnaviv_clear_blit.c \
> etnaviv_clear_blit.h \
> +   etnaviv_clear_blit_rs.c \
> etnaviv_compiler.c \
> etnaviv_compiler.h \
> etnaviv_context.c \
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c 
> b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
> index 878e3fd..faf8f39 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
> @@ -30,7 +30,6 @@
>
>  #include "etnaviv_context.h"
>  #include "etnaviv_emit.h"
> -#include "etnaviv_emit.h"
>  #include "etnaviv_format.h"
>  #include "etnaviv_resource.h"
>  #include "etnaviv_surface.h"
> @@ -44,7 +43,7 @@
>  #include "util/u_surface.h"
>
>  /* Save current state for blitter operation */
> -static void
> +void
>  etna_blit_save_state(struct etna_context *ctx)
>  {
> util_blitter_save_vertex_buffer_slot(ctx->blitter, ctx->vertex_buffer.vb);
> @@ -65,43 +64,8 @@ etna_blit_save_state(struct etna_context *ctx)
>   ctx->num_fragment_sampler_views, ctx->sampler_view);
>  }
>
> -/* Generate clear command for a surface (non-fast clear case) */
> -void
> -etna_rs_gen_clear_surface(struct etna_context *ctx, struct etna_surface 
> *surf,
> -  uint32_t clear_value)
> -{
> -   struct etna_resource *dst = etna_resource(surf->base.texture);
> -   uint32_t format = translate_rs_format(surf->base.format);
> -
> -   if (format == ETNA_NO_MATCH) {
> -  BUG("etna_rs_gen_clear_surface: Unhandled clear fmt %s", 
> util_format_name(surf->base.format));
> -  format = RS_FORMAT_A8R8G8B8;
> -  assert(0);
> -   }
> -
> -   /* use tiled clear if width is multiple of 16 */
> -   bool tiled_clear = (surf->surf.padded_width & ETNA_RS_WIDTH_MASK) == 0 &&
> -  (surf->surf.padded_height & ETNA_RS_HEIGHT_MASK) == 0;
> -
> -   etna_compile_rs_state( ctx, >clear_command, &(struct rs_state) {
> -  .source_format = format,
> -  .dest_format = format,
> -  .dest = dst->bo,
> -  .dest_offset = surf->surf.offset,
> -  .dest_stride = surf->surf.stride,
> -  .dest_padded_height = surf->surf.padded_height,
> -  .dest_tiling = tiled_clear ? dst->layout : ETNA_LAYOUT_LINEAR,
> -  .dither = {0x, 0x},
> -  .width = surf->surf.padded_width, /* These must be padded to 16x4 if 
> !LINEAR, otherwise RS will hang */
> -  .height = surf->surf.padded_height,
> -  .clear_value = {clear_value},
> -  .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
> -  .clear_bits = 0x
> -   });
> -}
> -
> -static inline uint32_t
> -pack_rgba(enum pipe_format format, const float *rgba)
> +uint32_t
> +etna_clear_blit_pack_rgba(enum pipe_format format, const float *rgba)
>  {
> union util_color uc;
> util_pack_color(rgba, format, );
> @@ -112,152 +76,6 @@ pack_rgba(enum pipe_format format, const float *rgba)
>  }
>
>  static void
> -etna_blit_clear_color(struct pipe_context *pctx, struct pipe_surface *dst,
> -  const union pipe_color_union *color)
> -{
> -   struct etna_context *ctx = etna_context(pctx);
> -   struct etna_surface *surf = etna_surface(dst);
> -   uint32_t new_clear_value = pack_rgba(surf->base.format, color->f);
> -
> -   if (surf->surf.ts_size) { /* TS: use precompiled clear command */
> -  ctx->framebuffer.TS_COLOR_CLEAR_VALUE = new_clear_value;
> -
> -  if (VIV_FEATURE(ctx->screen, chipMinorFeatures1, AUTO_DISABLE)) {
> - /* Set number of color tiles to be filled */
> - etna_set_state(ctx->stream, VIVS_TS_COLOR_AUTO_DISABLE_COUNT,
> -surf->surf.padded_width * surf->surf.padded_height / 
> 16);
> - ctx->framebuffer.TS_MEM_CONFIG |= 
> VIVS_TS_MEM_CONFIG_COLOR_AUTO_DISABLE;
> -  }
> -
> -  

Re: [Mesa-dev] [PATCH 07/19] etnaviv: GC7000: Add etnaviv_blt

[Christian Gmeiner]

2017-11-05 13:02 GMT+01:00 Christian Gmeiner :
> 2017-10-30 17:16 GMT+01:00 Wladimir J. van der Laan :
>> Add a low-level library for using the BLT engine from the etnaviv
>> driver.
>>
>
> As I have no HW to test it I am just looking at the code and write
> down what I think :)
>
> There are some code style issues: https://www.mesa3d.org/codingstyle.html
>
>> Signed-off-by: Wladimir J. van der Laan 
>> ---
>>  src/gallium/drivers/etnaviv/Makefile.sources |   2 +

src/gallium/drivers/etnaviv/meson.build needs changed too.

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--
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Re: [Mesa-dev] [PATCH 07/19] etnaviv: GC7000: Add etnaviv_blt

[Christian Gmeiner]

2017-10-30 17:16 GMT+01:00 Wladimir J. van der Laan :
> Add a low-level library for using the BLT engine from the etnaviv
> driver.
>

As I have no HW to test it I am just looking at the code and write
down what I think :)

There are some code style issues: https://www.mesa3d.org/codingstyle.html

> Signed-off-by: Wladimir J. van der Laan 
> ---
>  src/gallium/drivers/etnaviv/Makefile.sources |   2 +
>  src/gallium/drivers/etnaviv/etnaviv_blt.c| 219 
> +++
>  src/gallium/drivers/etnaviv/etnaviv_blt.h| 128 
>  3 files changed, 349 insertions(+)
>  create mode 100644 src/gallium/drivers/etnaviv/etnaviv_blt.c
>  create mode 100644 src/gallium/drivers/etnaviv/etnaviv_blt.h
>
> diff --git a/src/gallium/drivers/etnaviv/Makefile.sources 
> b/src/gallium/drivers/etnaviv/Makefile.sources
> index ea8df80..3fab212 100644
> --- a/src/gallium/drivers/etnaviv/Makefile.sources
> +++ b/src/gallium/drivers/etnaviv/Makefile.sources
> @@ -9,6 +9,8 @@ C_SOURCES :=  \
> etnaviv_asm.h \
> etnaviv_blend.c \
> etnaviv_blend.h \
> +   etnaviv_blt.c \
> +   etnaviv_blt.h \
> etnaviv_clear_blit.c \
> etnaviv_clear_blit.h \
> etnaviv_compiler.c \
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_blt.c 
> b/src/gallium/drivers/etnaviv/etnaviv_blt.c
> new file mode 100644
> index 000..c88bc1e
> --- /dev/null
> +++ b/src/gallium/drivers/etnaviv/etnaviv_blt.c
> @@ -0,0 +1,219 @@
> +/*
> + * Copyright (c) 2017 Etnaviv Project
> + * Copyright (C) 2017 Zodiac Inflight Innovations
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sub license,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the
> + * next paragraph) shall be included in all copies or substantial portions
> + * of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> + * DEALINGS IN THE SOFTWARE.
> + *
> + * Authors:
> + *Wladimir J. van der Laan 
> + */
> +#include "etnaviv_blt.h"
> +
> +#include "etnaviv_emit.h"
> +#include "util/u_math.h"
> +
> +#include "hw/common_3d.xml.h"
> +#include "hw/state_blt.xml.h"
> +
> +#include 
> +
> +static inline uint32_t blt_compute_stride_bits(const struct blt_imginfo *img)
> +{

should be:

static inline uint32_t
blt_compute_stride_bits(const struct blt_imginfo *img)
{

> +return VIVS_BLT_DEST_STRIDE_TILING(img->tiling == ETNA_LAYOUT_LINEAR ? 0 
> : 3) | /* 1/3? */
> +   VIVS_BLT_DEST_STRIDE_FORMAT(img->format) |
> +   VIVS_BLT_DEST_STRIDE_STRIDE(img->stride);
> +}
> +
> +static inline uint32_t blt_compute_img_config_bits(const struct blt_imginfo 
> *img, bool for_dest)
> +{
> +uint32_t tiling_bits = 0;
> +if (img->tiling == ETNA_LAYOUT_SUPER_TILED) {
> +tiling_bits |= for_dest ? BLT_IMAGE_CONFIG_TO_SUPER_TILED : 
> BLT_IMAGE_CONFIG_FROM_SUPER_TILED;
> +}
> +
> +return BLT_IMAGE_CONFIG_CACHE_MODE(img->cache_mode) |
> +   COND(img->use_ts, BLT_IMAGE_CONFIG_TS) |
> +   COND(img->compressed, BLT_IMAGE_CONFIG_COMPRESSION) |
> +   BLT_IMAGE_CONFIG_COMPRESSION_FORMAT(img->compress_fmt) |
> +   COND(for_dest, BLT_IMAGE_CONFIG_UNK22) |
> +   BLT_IMAGE_CONFIG_SWIZ_R(0) | /* not used? */
> +   BLT_IMAGE_CONFIG_SWIZ_G(1) |
> +   BLT_IMAGE_CONFIG_SWIZ_B(2) |
> +   BLT_IMAGE_CONFIG_SWIZ_A(3) |
> +   tiling_bits;
> +}
> +
> +static inline uint32_t blt_compute_swizzle_bits(const struct blt_imginfo 
> *img, bool for_dest)
> +{
> +uint32_t swiz = VIVS_BLT_SWIZZLE_SRC_R(img->swizzle[0]) |
> +VIVS_BLT_SWIZZLE_SRC_G(img->swizzle[1]) |
> +VIVS_BLT_SWIZZLE_SRC_B(img->swizzle[2]) |
> +VIVS_BLT_SWIZZLE_SRC_A(img->swizzle[3]);
> +return for_dest ? (swiz << 12) : swiz;
> +}
> +
> +void emit_blt_clearimage(struct etna_cmd_stream *stream, const struct 
> blt_clear_op *op)
> +{
> +etna_cmd_stream_reserve(stream, 64*2); /* Make sure BLT op doesn't get 
> broken up */
> +
> +etna_set_state(stream, VIVS_BLT_ENABLE, 0x0001);
> +

Re: [Mesa-dev] [PATCH 06/19] etnaviv: GC7000: Support BLT as recipient for etna_stall

[Christian Gmeiner]

2017-11-05 12:54 GMT+01:00 Wladimir :
> On Sun, Nov 5, 2017 at 12:47 PM, Christian Gmeiner
>  wrote:
>> 2017-10-30 17:16 GMT+01:00 Wladimir J. van der Laan :
>>> When the BLT is involved as source or target, add an extra BLT
>>> enable/disable sequence around the sync sequence.
>>>
>>
>> Does this mean we are doing lazy blit operations? Or why is this needed at 
>> all?
>
> How do you mean with "lazy blit"?
>
> This is required. Any syncing with the BLT will otherwise crash. The
> Vivante blob does it, also.
>

See comments for patch "[PATCH 07/19] etnaviv: GC7000: Add etnaviv_blt"

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--
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Re: [Mesa-dev] [PATCH 06/19] etnaviv: GC7000: Support BLT as recipient for etna_stall

[Wladimir]

On Sun, Nov 5, 2017 at 12:47 PM, Christian Gmeiner
 wrote:
> 2017-10-30 17:16 GMT+01:00 Wladimir J. van der Laan :
>> When the BLT is involved as source or target, add an extra BLT
>> enable/disable sequence around the sync sequence.
>>
>
> Does this mean we are doing lazy blit operations? Or why is this needed at 
> all?

How do you mean with "lazy blit"?

This is required. Any syncing with the BLT will otherwise crash. The
Vivante blob does it, also.

Wladimir
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Re: [Mesa-dev] [PATCH 06/19] etnaviv: GC7000: Support BLT as recipient for etna_stall

[Christian Gmeiner]

2017-10-30 17:16 GMT+01:00 Wladimir J. van der Laan :
> When the BLT is involved as source or target, add an extra BLT
> enable/disable sequence around the sync sequence.
>

Does this mean we are doing lazy blit operations? Or why is this needed at all?

> Signed-off-by: Wladimir J. van der Laan 
> ---
>  src/gallium/drivers/etnaviv/etnaviv_emit.c | 15 ++-
>  1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_emit.c 
> b/src/gallium/drivers/etnaviv/etnaviv_emit.c
> index 6f7ce68..f388a89 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_emit.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_emit.c
> @@ -41,6 +41,7 @@
>  #include "etnaviv_zsa.h"
>  #include "hw/common.xml.h"
>  #include "hw/state.xml.h"
> +#include "hw/state_blt.xml.h"
>  #include "util/u_math.h"
>
>  struct etna_coalesce {
> @@ -60,8 +61,15 @@ CMD_STALL(struct etna_cmd_stream *stream, uint32_t from, 
> uint32_t to)
>  void
>  etna_stall(struct etna_cmd_stream *stream, uint32_t from, uint32_t to)
>  {
> -   etna_cmd_stream_reserve(stream, 4);
> +   bool blt = (from == SYNC_RECIPIENT_BLT) || (to == SYNC_RECIPIENT_BLT);
> +   etna_cmd_stream_reserve(stream, blt ? 8 : 4);
>
> +   if (blt) {
> +  etna_emit_load_state(stream, VIVS_BLT_ENABLE >> 2, 1, 0);
> +  etna_cmd_stream_emit(stream, 1);
> +   }
> +
> +   /* TODO: set bit 28/29 of token after BLT COPY_BUFFER */
> etna_emit_load_state(stream, VIVS_GL_SEMAPHORE_TOKEN >> 2, 1, 0);
> etna_cmd_stream_emit(stream, VIVS_GL_SEMAPHORE_TOKEN_FROM(from) | 
> VIVS_GL_SEMAPHORE_TOKEN_TO(to));
>
> @@ -73,6 +81,11 @@ etna_stall(struct etna_cmd_stream *stream, uint32_t from, 
> uint32_t to)
>etna_emit_load_state(stream, VIVS_GL_STALL_TOKEN >> 2, 1, 0);
>etna_cmd_stream_emit(stream, VIVS_GL_STALL_TOKEN_FROM(from) | 
> VIVS_GL_STALL_TOKEN_TO(to));
> }
> +
> +   if (blt) {
> +  etna_emit_load_state(stream, VIVS_BLT_ENABLE >> 2, 1, 0);
> +  etna_cmd_stream_emit(stream, 0);
> +   }
>  }
>
>  static void
> --
> 2.7.4
>



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--
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Re: [Mesa-dev] [PATCH 04/19] etnaviv: Emit SCALE for vertex attributes

[Christian Gmeiner]

2017-10-30 17:16 GMT+01:00 Wladimir J. van der Laan :
> This is used by HALTI2+ (GC3000+) when drawing with DRAW_INSTANCED.
>
> It is also necessary when switching between integer and floating point
> vertex element formats.
>
> Signed-off-by: Wladimir J. van der Laan 

Reviewed-by: Christian Gmeiner 

> ---
>  src/gallium/drivers/etnaviv/etnaviv_emit.c | 5 +
>  src/gallium/drivers/etnaviv/etnaviv_internal.h | 1 +
>  src/gallium/drivers/etnaviv/etnaviv_state.c| 1 +
>  3 files changed, 7 insertions(+)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_emit.c 
> b/src/gallium/drivers/etnaviv/etnaviv_emit.c
> index 707b1e7..6f7ce68 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_emit.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_emit.c
> @@ -341,6 +341,11 @@ etna_emit_state(struct etna_context *ctx)
>/*00600*/ etna_set_state_multi(stream, 
> VIVS_FE_VERTEX_ELEMENT_CONFIG(0),
>   ctx->vertex_elements->num_elements,
>   ctx->vertex_elements->FE_VERTEX_ELEMENT_CONFIG);
> +  if (ctx->specs.halti >= 2) {
> + /*00780*/ etna_set_state_multi(stream, 
> VIVS_FE_GENERIC_ATTRIB_SCALE(0),
> +ctx->vertex_elements->num_elements,
> +ctx->vertex_elements->NFE_GENERIC_ATTRIB_SCALE);
> +  }
> }
>
> /* The following code is originally generated by gen_merge_state.py, to
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_internal.h 
> b/src/gallium/drivers/etnaviv/etnaviv_internal.h
> index 22264ec..92ae1bf 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_internal.h
> +++ b/src/gallium/drivers/etnaviv/etnaviv_internal.h
> @@ -214,6 +214,7 @@ struct compiled_framebuffer_state {
>  struct compiled_vertex_elements_state {
> unsigned num_elements;
> uint32_t FE_VERTEX_ELEMENT_CONFIG[VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN];
> +   uint32_t NFE_GENERIC_ATTRIB_SCALE[VIVS_NFE_GENERIC_ATTRIB__LEN];
>  };
>
>  /* Compiled context->set_vertex_buffer result */
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_state.c 
> b/src/gallium/drivers/etnaviv/etnaviv_state.c
> index a8b3141..b2feb32 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_state.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_state.c
> @@ -550,6 +550,7 @@ etna_vertex_elements_state_create(struct pipe_context 
> *pctx,
>   
> VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(elements[idx].vertex_buffer_index) |
>   VIVS_FE_VERTEX_ELEMENT_CONFIG_START(elements[idx].src_offset) |
>   VIVS_FE_VERTEX_ELEMENT_CONFIG_END(end_offset - start_offset);
> +  cs->NFE_GENERIC_ATTRIB_SCALE[idx] = 0x3f80; /* 1 for integer, 1.0 
> for float */
> }
>
> return cs;
> --
> 2.7.4
>



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Re: [Mesa-dev] [PATCH 03/19] etnaviv: Put HALTI level in specs

[Christian Gmeiner]

2017-10-30 17:16 GMT+01:00 Wladimir J. van der Laan :
> The HALTI level is an indication of the gross architecture of the GPU.
> It determines for significant part what feature level the GPU has, what
> state (especially frontend state) is there, and where it is located.
>
> Signed-off-by: Wladimir J. van der Laan 

Reviewed-by: Christian Gmeiner 

> ---
>  src/gallium/drivers/etnaviv/etnaviv_internal.h |  2 ++
>  src/gallium/drivers/etnaviv/etnaviv_screen.c   | 21 +
>  2 files changed, 23 insertions(+)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_internal.h 
> b/src/gallium/drivers/etnaviv/etnaviv_internal.h
> index 896bbf5..22264ec 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_internal.h
> +++ b/src/gallium/drivers/etnaviv/etnaviv_internal.h
> @@ -60,6 +60,8 @@
>
>  /* GPU chip 3D specs */
>  struct etna_specs {
> +   /* HALTI (gross architecture) level. -1 for pre-HALTI. */
> +   int halti : 8;
> /* supports SUPERTILE (64x64) tiling? */
> unsigned can_supertile : 1;
> /* needs z=(z+w)/2, for older GCxxx */
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c 
> b/src/gallium/drivers/etnaviv/etnaviv_screen.c
> index 1fb8751..9e9c590 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_screen.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c
> @@ -682,6 +682,27 @@ etna_get_specs(struct etna_screen *screen)
> }
> screen->specs.num_constants = val;
>
> +   /* Figure out gross GPU architecture. See rnndb/common.xml for a specific
> +* description of the differences. */
> +   if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5))
> +  screen->specs.halti = 5; /* New GC7000/GC8x00  */
> +   else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI4))
> +  screen->specs.halti = 4; /* Old GC7000/GC7400 */
> +   else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI3))
> +  screen->specs.halti = 3; /* None? */
> +   else if (VIV_FEATURE(screen, chipMinorFeatures4, HALTI2))
> +  screen->specs.halti = 2; /* GC2500/GC3000/GC5000/GC6400 */
> +   else if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1))
> +  screen->specs.halti = 1; /* GC900/GC4000/GC7000UL */
> +   else if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0))
> +  screen->specs.halti = 0; /* GC880/GC2000/GC7000TM */
> +   else
> +  screen->specs.halti = -1; /* GC7000nanolite / pre-GC2000 except GC880 
> */
> +   if (screen->specs.halti >= 0)
> +  DBG("etnaviv: GPU arch: HALTI%d\n", screen->specs.halti);
> +   else
> +  DBG("etnaviv: GPU arch: pre-HALTI\n");
> +
> screen->specs.can_supertile =
>VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
> screen->specs.bits_per_tile =
> --
> 2.7.4
>

I really like the idea!

-- 
greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info
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Re: [Mesa-dev] [PATCH 02/19] etnaviv: Const-correctness etnaviv_emit.h

[Christian Gmeiner]

2017-10-30 17:16 GMT+01:00 Wladimir J. van der Laan :
> The relocation structure is never changed by submitting it.
>
> Signed-off-by: Wladimir J. van der Laan 

Reviewed-by: Christian Gmeiner 

> ---
>  src/gallium/drivers/etnaviv/etnaviv_emit.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_emit.h 
> b/src/gallium/drivers/etnaviv/etnaviv_emit.h
> index 6a3c772..e0c0eda 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_emit.h
> +++ b/src/gallium/drivers/etnaviv/etnaviv_emit.h
> @@ -59,7 +59,7 @@ etna_set_state(struct etna_cmd_stream *stream, uint32_t 
> address, uint32_t value)
>
>  static inline void
>  etna_set_state_reloc(struct etna_cmd_stream *stream, uint32_t address,
> - struct etna_reloc *reloc)
> + const struct etna_reloc *reloc)
>  {
> etna_cmd_stream_reserve(stream, 2);
> etna_emit_load_state(stream, address >> 2, 1, 0);
> --
> 2.7.4
>



-- 
greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info
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