[Mesa-dev] [AppVeyor] mesa master #7685 failed

[AppVeyor]

Build mesa 7685 failed


Commit 5c33e8c772 by Timothy Arceri on 5/9/2018 3:28 AM:

st/nir: use NIR for asm programs\n\nReviewed-by: Eric Anholt 


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[Mesa-dev] [PATCH v2 2/3] glsl: allow built-in variables to be explicitly declared

[Timothy Arceri]

Mesa seems to be the only implementation that doesn't allow builtins
to be explicitly declared. The GLSL 1.30 spec seems to imply that
buitins may be explicitly declared.

This this allows the game "Full Bore" the be playable (when using
MESA_GL_VERSION_OVERRIDE=3.3COMPAT). It will also allow us to
remove the allow_glsl_builtin_variable_redeclaration dri override.

From the GLSL 1.30 spec Section 7.2 (Fragment Shader Special
Variables):

"Both gl_FragColor and gl_FragData are deprecated; the preferred
usage is to explicitly declare these outputs in the fragment
shader using the out storage qualifier."

To avoid some GLSL ES tests failing we add a check to make sure
precision matches on the redeclared builtin.
---
 src/compiler/glsl/ast_to_hir.cpp | 32 ++--
 1 file changed, 22 insertions(+), 10 deletions(-)

diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index a7a9ac80769..54d0816a986 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -4390,14 +4390,8 @@ get_variable_being_redeclared(ir_variable **var_ptr, 
YYLTYPE loc,
   earlier->data.precision = var->data.precision;
   earlier->data.memory_coherent = var->data.memory_coherent;
 
-   } else if (earlier->data.how_declared == ir_var_declared_implicitly &&
-  state->allow_builtin_variable_redeclaration) {
-  /* Allow verbatim redeclarations of built-in variables. Not explicitly
-   * valid, but some applications do it.
-   */
-  if (earlier->data.mode != var->data.mode &&
-  !(earlier->data.mode == ir_var_system_value &&
-var->data.mode == ir_var_shader_in)) {
+   } else if (allow_all_redeclarations) {
+  if (earlier->data.mode != var->data.mode) {
  _mesa_glsl_error(, state,
   "redeclaration of `%s' with incorrect qualifiers",
   var->name);
@@ -4406,8 +4400,22 @@ get_variable_being_redeclared(ir_variable **var_ptr, 
YYLTYPE loc,
   "redeclaration of `%s' has incorrect type",
   var->name);
   }
-   } else if (allow_all_redeclarations) {
-  if (earlier->data.mode != var->data.mode) {
+   } else if (earlier->data.how_declared == ir_var_declared_implicitly) {
+  /* Allow verbatim redeclarations of built-in variables. The GLSL 1.30
+   * spec seems to imply that buitins may be explicitly declared.
+   *
+   * From the GLSL 1.30 spec Section 7.2 (Fragment Shader Special
+   * Variables):
+   *
+   *"Both gl_FragColor and gl_FragData are deprecated; the preferred
+   *usage is to explicitly declare these outputs in the fragment
+   *shader using the out storage qualifier."
+   */
+  enum ir_variable_mode builtin_mode =
+ glsl_external_mode((ir_variable_mode) earlier->data.mode,
+state->stage, earlier->data.location);
+
+  if (builtin_mode != var->data.mode) {
  _mesa_glsl_error(, state,
   "redeclaration of `%s' with incorrect qualifiers",
   var->name);
@@ -4415,6 +4423,10 @@ get_variable_being_redeclared(ir_variable **var_ptr, 
YYLTYPE loc,
  _mesa_glsl_error(, state,
   "redeclaration of `%s' has incorrect type",
   var->name);
+  } else if (earlier->data.precision != var->data.precision) {
+ _mesa_glsl_error(, state,
+  "redeclaration of `%s' has incorrect precision",
+  var->name);
   }
} else {
   _mesa_glsl_error(, state, "`%s' redeclared", var->name);
-- 
2.17.0

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[Mesa-dev] [PATCH v2 1/3] glsl: add glsl_external_mode() helper

[Timothy Arceri]

This allows us to get the variable mode as specified by the GLSL
spec. We will use this in the following patch.
---
 src/compiler/glsl/ast_to_hir.cpp | 73 
 1 file changed, 73 insertions(+)

diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index 3bf581571e2..a7a9ac80769 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -4175,6 +4175,79 @@ apply_type_qualifier_to_variable(const struct 
ast_type_qualifier *qual,
apply_image_qualifier_to_variable(qual, var, state, loc);
 }
 
+/**
+ * Get the GLSL mode specified in for system values (if any).
+ */
+static enum ir_variable_mode
+glsl_external_mode(enum ir_variable_mode internal_mode, gl_shader_stage stage,
+   unsigned slot) {
+   if (internal_mode == ir_var_system_value) {
+  switch (slot) {
+  case SYSTEM_VALUE_SUBGROUP_SIZE:
+ return ir_var_uniform;
+  case SYSTEM_VALUE_PRIMITIVE_ID:
+ if (stage == MESA_SHADER_GEOMETRY) {
+return ir_var_shader_out;
+ } else {
+return ir_var_shader_in;
+ }
+  case SYSTEM_VALUE_TESS_LEVEL_OUTER:
+  case SYSTEM_VALUE_TESS_LEVEL_INNER:
+ if (stage == MESA_SHADER_TESS_CTRL) {
+return ir_var_shader_out;
+ } else {
+assert(stage == MESA_SHADER_TESS_EVAL);
+return ir_var_shader_in;
+ }
+  case SYSTEM_VALUE_SUBGROUP_INVOCATION:
+  case SYSTEM_VALUE_SUBGROUP_EQ_MASK:
+  case SYSTEM_VALUE_SUBGROUP_GE_MASK:
+  case SYSTEM_VALUE_SUBGROUP_GT_MASK:
+  case SYSTEM_VALUE_SUBGROUP_LE_MASK:
+  case SYSTEM_VALUE_SUBGROUP_LT_MASK:
+  case SYSTEM_VALUE_INSTANCE_ID:
+  case SYSTEM_VALUE_VERTEX_ID:
+  case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
+  case SYSTEM_VALUE_BASE_VERTEX:
+  case SYSTEM_VALUE_BASE_INSTANCE:
+  case SYSTEM_VALUE_DRAW_ID:
+  case SYSTEM_VALUE_INVOCATION_ID:
+  case SYSTEM_VALUE_FRAG_COORD:
+  case SYSTEM_VALUE_FRONT_FACE:
+  case SYSTEM_VALUE_SAMPLE_ID:
+  case SYSTEM_VALUE_SAMPLE_POS:
+  case SYSTEM_VALUE_SAMPLE_MASK_IN:
+  case SYSTEM_VALUE_HELPER_INVOCATION:
+  case SYSTEM_VALUE_TESS_COORD:
+  case SYSTEM_VALUE_VERTICES_IN:
+  case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
+  case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX:
+  case SYSTEM_VALUE_GLOBAL_INVOCATION_ID:
+  case SYSTEM_VALUE_WORK_GROUP_ID:
+  case SYSTEM_VALUE_NUM_WORK_GROUPS:
+  case SYSTEM_VALUE_LOCAL_GROUP_SIZE:
+ return ir_var_shader_in;
+  case SYSTEM_VALUE_NUM_SUBGROUPS:
+  case SYSTEM_VALUE_SUBGROUP_ID:
+  case SYSTEM_VALUE_INSTANCE_INDEX:
+  case SYSTEM_VALUE_FIRST_VERTEX:
+  case SYSTEM_VALUE_IS_INDEXED_DRAW:
+  case SYSTEM_VALUE_DEVICE_INDEX:
+  case SYSTEM_VALUE_VIEW_INDEX:
+  case SYSTEM_VALUE_VERTEX_CNT:
+ /* These system values have no GLSL facing equal */
+ return internal_mode;
+  case SYSTEM_VALUE_MAX:
+ unreachable("Invalid system value slot SYSTEM_VALUE_MAX");
+ break;
+  default:
+ unreachable("Unhandled system value in glsl_external_mode()");
+  }
+   }
+
+   return internal_mode;
+}
+
 /**
  * Get the variable that is being redeclared by this declaration or if it
  * does not exist, the current declared variable.
-- 
2.17.0

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[Mesa-dev] [PATCH v2 3/3] mesa/st/i965: remove the allow_glsl_builtin_variable_redeclaration dri option

[Timothy Arceri]

The previous patch changes the compiler to behave this way always so
we no longer need it.
---
 src/compiler/glsl/glsl_parser_extras.cpp|  2 --
 src/compiler/glsl/glsl_parser_extras.h  |  1 -
 src/gallium/auxiliary/pipe-loader/driinfo_gallium.h |  1 -
 src/gallium/include/state_tracker/st_api.h  |  1 -
 src/gallium/state_trackers/dri/dri_screen.c |  2 --
 src/mesa/drivers/dri/i965/brw_context.c |  3 ---
 src/mesa/drivers/dri/i965/intel_screen.c|  1 -
 src/mesa/main/mtypes.h  |  5 -
 src/mesa/state_tracker/st_extensions.c  |  2 --
 src/util/drirc  | 11 ---
 src/util/xmlpool/t_options.h|  5 -
 11 files changed, 34 deletions(-)

diff --git a/src/compiler/glsl/glsl_parser_extras.cpp 
b/src/compiler/glsl/glsl_parser_extras.cpp
index 25003eeccce..c6ffdcc588c 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -304,8 +304,6 @@ _mesa_glsl_parse_state::_mesa_glsl_parse_state(struct 
gl_context *_ctx,
   sizeof(this->atomic_counter_offsets));
this->allow_extension_directive_midshader =
   ctx->Const.AllowGLSLExtensionDirectiveMidShader;
-   this->allow_builtin_variable_redeclaration =
-  ctx->Const.AllowGLSLBuiltinVariableRedeclaration;
 
this->cs_input_local_size_variable_specified = false;
 
diff --git a/src/compiler/glsl/glsl_parser_extras.h 
b/src/compiler/glsl/glsl_parser_extras.h
index 5b9b6cc8621..794aa5dc2fd 100644
--- a/src/compiler/glsl/glsl_parser_extras.h
+++ b/src/compiler/glsl/glsl_parser_extras.h
@@ -848,7 +848,6 @@ struct _mesa_glsl_parse_state {
unsigned atomic_counter_offsets[MAX_COMBINED_ATOMIC_BUFFERS];
 
bool allow_extension_directive_midshader;
-   bool allow_builtin_variable_redeclaration;
 
/**
 * Known subroutine type declarations.
diff --git a/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h 
b/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
index 21dc599dc26..85e3b699964 100644
--- a/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
+++ b/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
@@ -23,7 +23,6 @@ DRI_CONF_SECTION_DEBUG
DRI_CONF_DISABLE_SHADER_BIT_ENCODING("false")
DRI_CONF_FORCE_GLSL_VERSION(0)
DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
-   DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false")
DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
diff --git a/src/gallium/include/state_tracker/st_api.h 
b/src/gallium/include/state_tracker/st_api.h
index ec6e7844b87..b8fc833b356 100644
--- a/src/gallium/include/state_tracker/st_api.h
+++ b/src/gallium/include/state_tracker/st_api.h
@@ -222,7 +222,6 @@ struct st_config_options
boolean force_glsl_extensions_warn;
unsigned force_glsl_version;
boolean allow_glsl_extension_directive_midshader;
-   boolean allow_glsl_builtin_variable_redeclaration;
boolean allow_higher_compat_version;
boolean glsl_zero_init;
boolean force_glsl_abs_sqrt;
diff --git a/src/gallium/state_trackers/dri/dri_screen.c 
b/src/gallium/state_trackers/dri/dri_screen.c
index aaee9870776..c0df65aa5a6 100644
--- a/src/gallium/state_trackers/dri/dri_screen.c
+++ b/src/gallium/state_trackers/dri/dri_screen.c
@@ -74,8 +74,6 @@ dri_fill_st_options(struct dri_screen *screen)
   driQueryOptioni(optionCache, "force_glsl_version");
options->allow_glsl_extension_directive_midshader =
   driQueryOptionb(optionCache, "allow_glsl_extension_directive_midshader");
-   options->allow_glsl_builtin_variable_redeclaration =
-  driQueryOptionb(optionCache, 
"allow_glsl_builtin_variable_redeclaration");
options->allow_higher_compat_version =
   driQueryOptionb(optionCache, "allow_higher_compat_version");
options->glsl_zero_init = driQueryOptionb(optionCache, "glsl_zero_init");
diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index bd1e20845f0..c338dd4c29b 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -836,9 +836,6 @@ brw_process_driconf_options(struct brw_context *brw)
ctx->Const.AllowGLSLExtensionDirectiveMidShader =
   driQueryOptionb(options, "allow_glsl_extension_directive_midshader");
 
-   ctx->Const.AllowGLSLBuiltinVariableRedeclaration =
-  driQueryOptionb(options, "allow_glsl_builtin_variable_redeclaration");
-
ctx->Const.AllowHigherCompatVersion =
   driQueryOptionb(options, "allow_higher_compat_version");
 
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 409f763b640..ef7efdeba24 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -84,7 +84,6 @@ DRI_CONF_BEGIN
   

[Mesa-dev] [Bug 106480] A2B10G10R10_SNORM vertex attribute doesn't work.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106480

--- Comment #4 from Roland Scheidegger  ---
radeonsi has workarounds for all signed r10g10b10a2 formats for everything
before Vega (except Stoney Ridge), with the code explicitly saying the A2 is
read as unsigned by the hw.
At a quick glance I don't see any such workarounds for radv, but I have zero
idea about that driver.

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Re: [Mesa-dev] [PATCH 3/4] i965: Handle non-zero texture buffer offsets in buffer object range calculation.

[Francisco Jerez]

Hey Nanley,

Nanley Chery  writes:

> On Mon, Mar 19, 2018 at 11:26:58AM -0700, Francisco Jerez wrote:
>> Otherwise the specified surface state will allow the GPU to access
>> memory up to BufferOffset bytes past the end of the buffer.  Found by
>> inspection.
>> 
>> Cc: mesa-sta...@lists.freedesktop.org
>> ---
>>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>> 
>> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
>> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
>> index ed4def9046e..2ab15af793a 100644
>> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
>> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
>> @@ -654,7 +654,8 @@ buffer_texture_range_size(struct brw_context *brw,
>>  * so that when ISL divides by stride to obtain the number of texels, 
>> that
>>  * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
>>  */
>> -   return MIN3((unsigned)obj->BufferSize, buffer_size,
>> +   return MIN3((unsigned)obj->BufferSize,
>> +   buffer_size - obj->BufferOffset,
>> brw->ctx.Const.MaxTextureBufferSize * texel_size);
>
> I don't understand this change. Previously we took the minimum between:
> 1) The TextureBuffer size specified by glTexBufferRange().
> 2) The size of the buffer object specified by glTexBuffer().
> 3) The maximum allowed texture buffer size.
>
> This patch modifies case 2 to be subtracted by the offset which will
> always be 0 for glTexBuffer().
>

The second argument of the MIN3 function is calculating the size of the
buffer object range accessible to the GPU.  The correct offset interval
that is supposed to be mapped to the GPU is [obj->BufferOffset,
obj->BufferObject->Size[, from where the expression above follows.

>>  }
>>  
>> -- 
>> 2.16.1
>> 


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[Mesa-dev] [Bug 106480] A2B10G10R10_SNORM vertex attribute doesn't work.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106480

--- Comment #3 from Bas Nieuwenhuizen  ---
Created attachment 139509
  --> https://bugs.freedesktop.org/attachment.cgi?id=139509=edit
renderdoc screenshot of non-reproduction

Not sure I can reproduce. If I go to the corner A is a proper 1.0 here (and 0.0
in the other corners).

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Re: [Mesa-dev] docs: Intel Mesa Drivers infographic

[Jason Ekstrand]

Couple of edits:

i915:  I'd leave the bit about "embedded" out.  I don't think it's used for
any new deployments at this point.

1965: How about "Implements intel-specific parts of OpenGL entrypoints"

ISL isn't really for converting between surface formats.  A better
one-sentence description would be "A library for computing image sizes and
memory layouts"

BLORP: How about "blit, clear, and resolve functionality" rather than
"driver functionality"

NIR: Not really a "front-end" more of an "optimizing middle compiler"

Looks snazzy though. :-)

On Thu, May 10, 2018 at 6:19 PM, Laura Ekstrand 
wrote:

> Hi All,
>
> I developed the following infographic to inform readers about the various
> parts that make up the Intel Mesa drivers.  It is intended to help groups
> inside Intel better understand the open source community, and at the same
> time, it helps train newcomers to Mesa in driver architecture.
>
> I haven't put this in a tree yet since it is a combination of a
> LibreOffice Draw document and a binary image file.
>
> Thanks.
>
> Laura
>
> https://drive.google.com/file/d/1D0k3-p88xEame5gepJQfIcCyZhG4CAsW/
> view?usp=sharing
>
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Re: [Mesa-dev] [PATCH 4/4] i965: Use intel_bufferobj_buffer() wrapper in image surface state setup.

[Nanley Chery]

On Mon, Mar 19, 2018 at 11:26:59AM -0700, Francisco Jerez wrote:
> Instead of directly using intel_obj->buffer.  Among other things
> intel_bufferobj_buffer() will update intel_buffer_object::
> gpu_active_start/end, which are used by glBufferSubData() to decide
> which path to take.  Fixes a failure in the Piglit
> ARB_shader_image_load_store-host-mem-barrier Buffer Update/WaW tests,
> which could be reproduced with a non-standard glGetTexSubImage
> implementation (see bug report).
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105351

What do you think about leaving the bug open until we create a piglit
test to reproduce it? We could create a new bug otherwise.

> Reported-by: Nanley Chery 
> Cc: mesa-sta...@lists.freedesktop.org
> ---
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 8 +---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index 2ab15af793a..5d4c84bb55a 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -1510,14 +1510,16 @@ update_image_surface(struct brw_context *brw,
>const unsigned format = get_image_format(brw, u->_ActualFormat, 
> access);
>  
>if (obj->Target == GL_TEXTURE_BUFFER) {
> - struct intel_buffer_object *intel_obj =
> -intel_buffer_object(obj->BufferObject);
>   const unsigned texel_size = (format == ISL_FORMAT_RAW ? 1 :
>
> _mesa_get_format_bytes(u->_ActualFormat));
>   const unsigned buffer_size = buffer_texture_range_size(brw, obj);
> + struct brw_bo *const bo = !obj->BufferObject ? NULL :

Interesting. Did the old code wrongly assume that
obj->BufferObject != NULL? Maybe we need a test that tries to do image
load/store on a texture buffer without a backing buffer object?

> +intel_bufferobj_buffer(brw, 
> intel_buffer_object(obj->BufferObject),
> +   obj->BufferOffset, buffer_size,
> +   access != GL_READ_ONLY);
>  

Looks right to me. The comment above the helper function says:
   [...]
   * Anywhere that uses buffer objects in the pipeline should be using this to
   * mark the range of the buffer that is being accessed by the pipeline.
   */
  
...and that is what we're doing here. This patch is
Reviewed-by: Nanley Chery 

>   brw_emit_buffer_surface_state(
> -brw, surf_offset, intel_obj->buffer, obj->BufferOffset,
> +brw, surf_offset, bo, obj->BufferOffset,
>  format, buffer_size, texel_size,
>  access != GL_READ_ONLY ? RELOC_WRITE : 0);
>  
> -- 
> 2.16.1
> 
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Re: [Mesa-dev] [PATCH v8 2/2] anv: enable VK_EXT_shader_stencil_export

[Jason Ekstrand]

Reviewed-by: Jason Ekstrand 

On Fri, May 11, 2018 at 4:35 PM, Caio Marcelo de Oliveira Filho <
caio.olive...@intel.com> wrote:

> From: Gustavo Lima Chaves 
>
> ---
>  src/intel/vulkan/anv_extensions.py | 1 +
>  src/intel/vulkan/anv_pipeline.c| 1 +
>  src/intel/vulkan/genX_pipeline.c   | 1 +
>  3 files changed, 3 insertions(+)
>
> diff --git a/src/intel/vulkan/anv_extensions.py b/src/intel/vulkan/anv_
> extensions.py
> index b5bee0881ce..8160864685f 100644
> --- a/src/intel/vulkan/anv_extensions.py
> +++ b/src/intel/vulkan/anv_extensions.py
> @@ -112,6 +112,7 @@ EXTENSIONS = [
>  Extension('VK_EXT_global_priority',   1,
>'device->has_context_priority'),
>  Extension('VK_EXT_shader_viewport_index_layer',   1, True),
> +Extension('VK_EXT_shader_stencil_export', 1,
> 'device->info.gen >= 9'),
>  ]
>
>  class VkVersion:
> diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_
> pipeline.c
> index 8f30136b100..240bde036d6 100644
> --- a/src/intel/vulkan/anv_pipeline.c
> +++ b/src/intel/vulkan/anv_pipeline.c
> @@ -152,6 +152,7 @@ anv_shader_compile_to_nir(struct anv_pipeline
> *pipeline,
>   .subgroup_quad = true,
>   .subgroup_shuffle = true,
>   .subgroup_vote = true,
> + .stencil_export = device->instance->physicalDevice.info.gen >=
> 9,
>},
> };
>
> diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_
> pipeline.c
> index 6016d257584..462c59451cc 100644
> --- a/src/intel/vulkan/genX_pipeline.c
> +++ b/src/intel/vulkan/genX_pipeline.c
> @@ -1600,6 +1600,7 @@ emit_3dstate_ps_extra(struct anv_pipeline *pipeline,
>   ps.PixelShaderHasUAV = true;
>
>  #if GEN_GEN >= 9
> +  ps.PixelShaderComputesStencil = wm_prog_data->computed_stencil;
>ps.PixelShaderPullsBary= wm_prog_data->pulls_bary;
>ps.InputCoverageMaskState  = wm_prog_data->uses_sample_mask ?
> ICMS_INNER_CONSERVATIVE : ICMS_NONE;
> --
> 2.17.0
>
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Re: [Mesa-dev] [PATCH v8 1/2] spirv: add/hookup SpvCapabilityStencilExportEXT

[Jason Ekstrand]

Reviewed-by: Jason Ekstrand 

On Fri, May 11, 2018 at 4:35 PM, Caio Marcelo de Oliveira Filho <
caio.olive...@intel.com> wrote:

> From: Gustavo Lima Chaves 
>
> v2:
> An attempt to support SpvExecutionModeStencilRefReplacingEXT's behavior
> also follows, with the interpretation to said mode being we prevent
> writes to the built-in FragStencilRefEXT variable when the execution
> mode isn't set.
>
> v3:
> A more cautious reading of 1db44252d01bf7539452ccc2b5210c74b8dcd573 led
> me to a missing change that would stop (what I later discovered were)
> GPU hangs on the CTS test written to exercise this.
>
> v4:
> Turn FragStencilRefEXT decoration usage without StencilRefReplacingEXT
> mode into a warning, instead of trying to make the variable read-only.
> If we are to follow the originating extension on GL, the built-in
> variable in question should never be readable anyway.
>
> v5/v6: rebases.
>
> v7:
> Fix check for gen9 lost in rebase. (Ilia)
> Reduce the scope of the bool used to track whether
> SpvExecutionModeStencilRefReplacingEXT was used. Was in shader_info,
> moved to vtn_builder. (Jason)
>
> v8:
> Assert for fragment shader handling StencilRefReplacingEXT execution
> mode. (Caio)
> Remove warning logic, since an entry point might not have
> StencilRefReplacingEXT execution mode, but the global output variable
> might still exist for another entry point in the module. (Jason)
> ---
>  src/compiler/shader_info.h | 1 +
>  src/compiler/spirv/spirv_to_nir.c  | 8 
>  src/compiler/spirv/vtn_variables.c | 4 
>  3 files changed, 13 insertions(+)
>
> diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
> index afc53a88405..81f844d36ae 100644
> --- a/src/compiler/shader_info.h
> +++ b/src/compiler/shader_info.h
> @@ -56,6 +56,7 @@ struct spirv_supported_capabilities {
> bool trinary_minmax;
> bool descriptor_array_dynamic_indexing;
> bool runtime_descriptor_array;
> +   bool stencil_export;
>  };
>
>  typedef struct shader_info {
> diff --git a/src/compiler/spirv/spirv_to_nir.c
> b/src/compiler/spirv/spirv_to_nir.c
> index 78437428aa7..3c3ef4658d6 100644
> --- a/src/compiler/spirv/spirv_to_nir.c
> +++ b/src/compiler/spirv/spirv_to_nir.c
> @@ -3396,6 +3396,10 @@ vtn_handle_preamble_instruction(struct vtn_builder
> *b, SpvOp opcode,
>   spv_check_supported(runtime_descriptor_array, cap);
>   break;
>
> +  case SpvCapabilityStencilExportEXT:
> + spv_check_supported(stencil_export, cap);
> + break;
> +
>default:
>   vtn_fail("Unhandled capability");
>}
> @@ -3573,6 +3577,10 @@ vtn_handle_execution_mode(struct vtn_builder *b,
> struct vtn_value *entry_point,
> case SpvExecutionModeContractionOff:
>break; /* OpenCL */
>
> +   case SpvExecutionModeStencilRefReplacingEXT:
> +  vtn_assert(b->shader->info.stage == MESA_SHADER_FRAGMENT);
> +  break;
> +
> default:
>vtn_fail("Unhandled execution mode");
> }
> diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_
> variables.c
> index fd8ab7f247a..53bee1b9288 100644
> --- a/src/compiler/spirv/vtn_variables.c
> +++ b/src/compiler/spirv/vtn_variables.c
> @@ -1354,6 +1354,10 @@ vtn_get_builtin_location(struct vtn_builder *b,
>*location = SYSTEM_VALUE_SUBGROUP_LT_MASK,
>set_mode_system_value(b, mode);
>break;
> +   case SpvBuiltInFragStencilRefEXT:
> +  *location = FRAG_RESULT_STENCIL;
> +  vtn_assert(*mode == nir_var_shader_out);
> +  break;
> default:
>vtn_fail("unsupported builtin");
> }
> --
> 2.17.0
>
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[Mesa-dev] [PATCH 09/10] i965/miptree: Move the access_raw call to the individual map functions

[Jason Ekstrand]

The only function that doesn't need to call access_raw is map_blit.  If
it takes the blitter path, it will happen as part of intel_miptree_copy.
If map_blit takes the blorp path, no brw_blorp_copy_miptrees will handle
doing whatever resolves are needed.  This should save us resolves in
quite a few cases and will probably help performance a bit.
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 16 +---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 7c5e6f6..0bfc426 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -3109,6 +3109,9 @@ intel_miptree_map_gtt(struct brw_context *brw,
y /= bh;
x /= bw;
 
+   intel_miptree_access_raw(brw, mt, level, slice,
+map->mode & GL_MAP_WRITE_BIT);
+
base = intel_miptree_map_raw(brw, mt, map->mode);
 
if (base == NULL)
@@ -3247,6 +3250,8 @@ intel_miptree_map_movntdqa(struct brw_context *brw,
assert(map->mode & GL_MAP_READ_BIT);
assert(!(map->mode & GL_MAP_WRITE_BIT));
 
+   intel_miptree_access_raw(brw, mt, level, slice, false);
+
DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__,
map->x, map->y, map->w, map->h,
mt, _mesa_get_format_name(mt->format),
@@ -3341,6 +3346,9 @@ intel_miptree_map_s8(struct brw_context *brw,
if (!map->buffer)
   return;
 
+   intel_miptree_access_raw(brw, mt, level, slice,
+map->mode & GL_MAP_WRITE_BIT);
+
/* One of either READ_BIT or WRITE_BIT or both is set.  READ_BIT implies no
 * INVALIDATE_RANGE_BIT.  WRITE_BIT needs the original values read in unless
 * invalidate is set, since we'll be writing the whole rectangle from our
@@ -3423,6 +3431,8 @@ intel_miptree_map_etc(struct brw_context *brw,
assert(map->mode & GL_MAP_WRITE_BIT);
assert(map->mode & GL_MAP_INVALIDATE_RANGE_BIT);
 
+   intel_miptree_access_raw(brw, mt, level, slice, true);
+
map->stride = _mesa_format_row_stride(mt->etc_format, map->w);
map->buffer = malloc(_mesa_format_image_size(mt->etc_format,
 map->w, map->h, 1));
@@ -3516,6 +3526,9 @@ intel_miptree_map_depthstencil(struct brw_context *brw,
if (!map->buffer)
   return;
 
+   intel_miptree_access_raw(brw, mt, level, slice,
+map->mode & GL_MAP_WRITE_BIT);
+
/* One of either READ_BIT or WRITE_BIT or both is set.  READ_BIT implies no
 * INVALIDATE_RANGE_BIT.  WRITE_BIT needs the original values read in unless
 * invalidate is set, since we'll be writing the whole rectangle from our
@@ -3697,9 +3710,6 @@ intel_miptree_map(struct brw_context *brw,
   return;
}
 
-   intel_miptree_access_raw(brw, mt, level, slice,
-map->mode & GL_MAP_WRITE_BIT);
-
if (mt->format == MESA_FORMAT_S_UINT8) {
   intel_miptree_map_s8(brw, mt, map, level, slice);
} else if (mt->etc_format != MESA_FORMAT_NONE &&
-- 
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[Mesa-dev] [PATCH 08/10] i965: Remove support for the BLT ring

[Jason Ekstrand]

We still support the blitter on gen4-5 but it's on the same ring as 3D.
---
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 12 +++-
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 8c5fd50..b9ea922 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -771,18 +771,12 @@ submit_batch(struct brw_context *brw, int in_fence_fd, 
int *out_fence_fd)
*   To avoid stalling, execobject.offset should match the current
*   address of that object within the active context.
*/
-  int flags = I915_EXEC_NO_RELOC;
+  assert(devinfo->gen < 6 || batch->ring == RENDER_RING);
+  int flags = I915_EXEC_NO_RELOC | I915_EXEC_RENDER;
 
-  if (devinfo->gen >= 6 && batch->ring == BLT_RING) {
- flags |= I915_EXEC_BLT;
-  } else {
- flags |= I915_EXEC_RENDER;
-  }
   if (batch->needs_sol_reset)
  flags |= I915_EXEC_GEN7_SOL_RESET;
 
-  uint32_t hw_ctx = batch->ring == RENDER_RING ? brw->hw_ctx : 0;
-
   /* Set statebuffer relocations */
   const unsigned state_index = batch->state.bo->index;
   if (state_index < batch->exec_count &&
@@ -812,7 +806,7 @@ submit_batch(struct brw_context *brw, int in_fence_fd, int 
*out_fence_fd)
  batch->validation_list[index] = tmp;
   }
 
-  ret = execbuffer(dri_screen->fd, batch, hw_ctx,
+  ret = execbuffer(dri_screen->fd, batch, brw->hw_ctx,
4 * USED_BATCH(*batch),
in_fence_fd, out_fence_fd, flags);
 
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 10/10] intel/blorp: Use linear formats for CCS_E clear colors in copies

[Jason Ekstrand]

It's clear that the original code meant to do this and there is even a
10-line comment explaining why.  Originally, we had a simple function
for packing the clear colors which was unaware of sRGB.  However, in
a6b66a7b26ae1, when we started using ISL to do the packing, the wrong
format was used.

Fixes: a6b66a7b26 "intel/blorp: Use ISL instead of bitcast_color..."
---
 src/intel/blorp/blorp_blit.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index e825862..26bf442 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -2562,7 +2562,7 @@ blorp_copy(struct blorp_batch *batch,
   params.src.view.format));
   uint32_t packed[4];
   isl_color_value_pack(_color,
-   params.src.surf.format, packed);
+   linear_src_format, packed);
   isl_color_value_unpack(_color,
  params.src.view.format, packed);
}
@@ -2576,7 +2576,7 @@ blorp_copy(struct blorp_batch *batch,
   params.dst.view.format));
   uint32_t packed[4];
   isl_color_value_pack(_color,
-   params.dst.surf.format, packed);
+   linear_dst_format, packed);
   isl_color_value_unpack(_color,
  params.dst.view.format, packed);
}
-- 
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[Mesa-dev] [PATCH 06/10] i965/miptree: Use blorp for validation tex copies on gen6+

[Jason Ekstrand]

It's faster than the blitter and can handle things like stencil properly
so it doesn't require software fallbacks.
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 40 +++
 1 file changed, 29 insertions(+), 11 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 67086ee..47a8e8e 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1557,6 +1557,7 @@ intel_miptree_copy_slice(struct brw_context *brw,
  unsigned dst_level, unsigned dst_layer)
 
 {
+   const struct gen_device_info *devinfo = >screen->devinfo;
mesa_format format = src_mt->format;
unsigned width = minify(src_mt->surf.phys_level0_sa.width,
src_level - src_mt->first_level);
@@ -1569,6 +1570,32 @@ intel_miptree_copy_slice(struct brw_context *brw,
assert(_mesa_get_srgb_format_linear(src_mt->format) ==
   _mesa_get_srgb_format_linear(dst_mt->format));
 
+   DBG("validate blit mt %s %p %d,%d -> mt %s %p %d,%d (%dx%d)\n",
+   _mesa_get_format_name(src_mt->format),
+   src_mt, src_level, src_layer,
+   _mesa_get_format_name(dst_mt->format),
+   dst_mt, dst_level, dst_layer,
+   width, height);
+
+   if (devinfo->gen >= 6) {
+  /* On gen6 and above, we just use blorp.  It's faster than the blitter
+   * and can handle everything without software fallbacks.
+   */
+  brw_blorp_copy_miptrees(brw,
+  src_mt, src_level, src_layer,
+  dst_mt, dst_level, dst_layer,
+  0, 0, 0, 0, width, height);
+
+  if (src_mt->stencil_mt) {
+ assert(dst_mt->stencil_mt);
+ brw_blorp_copy_miptrees(brw,
+ src_mt->stencil_mt, src_level, src_layer,
+ dst_mt->stencil_mt, dst_level, dst_layer,
+ 0, 0, 0, 0, width, height);
+  }
+  return;
+   }
+
if (dst_mt->compressed) {
   unsigned int i, j;
   _mesa_get_format_block_size(dst_mt->format, , );
@@ -1576,17 +1603,8 @@ intel_miptree_copy_slice(struct brw_context *brw,
   width = ALIGN_NPOT(width, i) / i;
}
 
-   /* If it's a packed depth/stencil buffer with separate stencil, the blit
-* below won't apply since we can't do the depth's Y tiling or the
-* stencil's W tiling in the blitter.
-*/
-   if (src_mt->stencil_mt) {
-  intel_miptree_copy_slice_sw(brw,
-  src_mt, src_level, src_layer,
-  dst_mt, dst_level, dst_layer,
-  width, height);
-  return;
-   }
+   /* Gen4-5 doesn't support separate stencil */
+   assert(!src_mt->stencil_mt);
 
uint32_t dst_x, dst_y, src_x, src_y;
intel_miptree_get_image_offset(dst_mt, dst_level, dst_layer,
-- 
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[Mesa-dev] [PATCH 07/10] i965/miptree: Use blorp for blit maps on gen6+

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 36 +++
 1 file changed, 25 insertions(+), 11 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 47a8e8e..7c5e6f6 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -3143,16 +3143,23 @@ intel_miptree_unmap_blit(struct brw_context *brw,
 unsigned int level,
 unsigned int slice)
 {
+   const struct gen_device_info *devinfo = >screen->devinfo;
struct gl_context *ctx = >ctx;
 
intel_miptree_unmap_raw(map->linear_mt);
 
if (map->mode & GL_MAP_WRITE_BIT) {
-  bool ok = intel_miptree_copy(brw,
-   map->linear_mt, 0, 0, 0, 0,
-   mt, level, slice, map->x, map->y,
-   map->w, map->h);
-  WARN_ONCE(!ok, "Failed to blit from linear temporary mapping");
+  if (devinfo->gen >= 6) {
+ brw_blorp_copy_miptrees(brw, map->linear_mt, 0, 0,
+ mt, level, slice,
+ 0, 0, map->x, map->y, map->w, map->h);
+  } else {
+ bool ok = intel_miptree_copy(brw,
+  map->linear_mt, 0, 0, 0, 0,
+  mt, level, slice, map->x, map->y,
+  map->w, map->h);
+ WARN_ONCE(!ok, "Failed to blit from linear temporary mapping");
+  }
}
 
intel_miptree_release(>linear_mt);
@@ -3164,6 +3171,7 @@ intel_miptree_map_blit(struct brw_context *brw,
   struct intel_miptree_map *map,
   unsigned int level, unsigned int slice)
 {
+   const struct gen_device_info *devinfo = >screen->devinfo;
map->linear_mt = intel_miptree_create(brw, GL_TEXTURE_2D, mt->format,
  /* first_level */ 0,
  /* last_level */ 0,
@@ -3183,12 +3191,18 @@ intel_miptree_map_blit(struct brw_context *brw,
 * temporary buffer back out.
 */
if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) {
-  if (!intel_miptree_copy(brw,
-  mt, level, slice, map->x, map->y,
-  map->linear_mt, 0, 0, 0, 0,
-  map->w, map->h)) {
- fprintf(stderr, "Failed to blit\n");
- goto fail;
+  if (devinfo->gen >= 6) {
+ brw_blorp_copy_miptrees(brw, mt, level, slice,
+ map->linear_mt, 0, 0,
+ map->x, map->y, 0, 0, map->w, map->h);
+  } else {
+ if (!intel_miptree_copy(brw,
+ mt, level, slice, map->x, map->y,
+ map->linear_mt, 0, 0, 0, 0,
+ map->w, map->h)) {
+fprintf(stderr, "Failed to blit\n");
+goto fail;
+ }
   }
}
 
-- 
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[Mesa-dev] [PATCH 03/10] i965: Remove some unused includes of intel_blit.h

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_clear.c  | 1 -
 src/mesa/drivers/dri/i965/intel_pixel_read.c   | 1 -
 src/mesa/drivers/dri/i965/intel_tex_image.c| 1 -
 src/mesa/drivers/dri/i965/intel_tex_validate.c | 1 -
 4 files changed, 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c 
b/src/mesa/drivers/dri/i965/brw_clear.c
index 3d540d6..7eb0cbf 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -30,7 +30,6 @@
 #include "drivers/common/meta.h"
 
 #include "intel_batchbuffer.h"
-#include "intel_blit.h"
 #include "intel_fbo.h"
 #include "intel_mipmap_tree.h"
 
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c 
b/src/mesa/drivers/dri/i965/intel_pixel_read.c
index cf95737..6ed7895 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c
@@ -39,7 +39,6 @@
 #include "brw_blorp.h"
 #include "intel_screen.h"
 #include "intel_batchbuffer.h"
-#include "intel_blit.h"
 #include "intel_buffers.h"
 #include "intel_fbo.h"
 #include "intel_mipmap_tree.h"
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c 
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 856216e..fae1792 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -21,7 +21,6 @@
 #include "intel_buffer_objects.h"
 #include "intel_batchbuffer.h"
 #include "intel_tex.h"
-#include "intel_blit.h"
 #include "intel_fbo.h"
 #include "intel_image.h"
 #include "intel_tiled_memcpy.h"
diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c 
b/src/mesa/drivers/dri/i965/intel_tex_validate.c
index eaa60ba..72ce83c 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c
@@ -29,7 +29,6 @@
 
 #include "brw_context.h"
 #include "intel_mipmap_tree.h"
-#include "intel_blit.h"
 #include "intel_tex.h"
 
 #define FILE_DEBUG_FLAG DEBUG_TEXTURE
-- 
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[Mesa-dev] [PATCH 01/10] i965: Use meta for pixel ops on gen6+

[Jason Ekstrand]

Using meta for anything is fairly aweful and definitely has more CPU
overhead.  However, it also uses the 3D pipe and is therefore likely
faster in terms of GPU time than the blitter.  Also, the blitter code
has so many early returns that it's probably not buying us that much.
We may as well just use meta all the time instead of working over-time
to find the tiny case where we can use the blitter.  We keep gen4-5
using the old blit paths to avoid perturbing old hardware too much.
---
 src/mesa/drivers/dri/i965/intel_pixel_bitmap.c | 6 --
 src/mesa/drivers/dri/i965/intel_pixel_copy.c   | 5 -
 src/mesa/drivers/dri/i965/intel_pixel_draw.c   | 3 ++-
 3 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c 
b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
index 5bc341b..f9d4829 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
@@ -348,11 +348,13 @@ intelBitmap(struct gl_context * ctx,
const struct gl_pixelstore_attrib *unpack,
const GLubyte * pixels)
 {
+   struct brw_context *brw = brw_context(ctx);
+
if (!_mesa_check_conditional_render(ctx))
   return;
 
-   if (do_blit_bitmap(ctx, x, y, width, height,
-  unpack, pixels))
+   if (brw->screen->devinfo.gen < 6 &&
+   do_blit_bitmap(ctx, x, y, width, height, unpack, pixels))
   return;
 
_mesa_meta_Bitmap(ctx, x, y, width, height, unpack, pixels);
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_copy.c 
b/src/mesa/drivers/dri/i965/intel_pixel_copy.c
index 8029ffb..31838cc 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_copy.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_copy.c
@@ -196,12 +196,15 @@ intelCopyPixels(struct gl_context * ctx,
 GLsizei width, GLsizei height,
 GLint destx, GLint desty, GLenum type)
 {
+   struct brw_context *brw = brw_context(ctx);
+
DBG("%s\n", __func__);
 
if (!_mesa_check_conditional_render(ctx))
   return;
 
-   if (do_blit_copypixels(ctx, srcx, srcy, width, height, destx, desty, type))
+   if (brw->screen->devinfo.gen < 6 &&
+   do_blit_copypixels(ctx, srcx, srcy, width, height, destx, desty, type))
   return;
 
/* this will use swrast if needed */
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_draw.c 
b/src/mesa/drivers/dri/i965/intel_pixel_draw.c
index 82dca4a..d5d1b99e69 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_draw.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_draw.c
@@ -163,7 +163,8 @@ intelDrawPixels(struct gl_context * ctx,
   return;
}
 
-   if (_mesa_is_bufferobj(unpack->BufferObj)) {
+   if (brw->screen->devinfo.gen < 6 &&
+   _mesa_is_bufferobj(unpack->BufferObj)) {
   if (do_blit_drawpixels(ctx, x, y, width, height, format, type, unpack,
 pixels)) {
 return;
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 02/10] i965/blit: Delete intel_emit_linear_blit

[Jason Ekstrand]

This function is no longer used.
---
 src/mesa/drivers/dri/i965/intel_blit.c | 56 --
 src/mesa/drivers/dri/i965/intel_blit.h |  6 
 2 files changed, 62 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
b/src/mesa/drivers/dri/i965/intel_blit.c
index dcecab6..5ef7858 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -706,62 +706,6 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw,
return true;
 }
 
-/* We don't have a memmove-type blit like some other hardware, so we'll do a
- * rectangular blit covering a large space, then emit 1-scanline blit at the
- * end to cover the last if we need.
- */
-void
-intel_emit_linear_blit(struct brw_context *brw,
-  struct brw_bo *dst_bo,
-  unsigned int dst_offset,
-  struct brw_bo *src_bo,
-  unsigned int src_offset,
-  unsigned int size)
-{
-   struct gl_context *ctx = >ctx;
-   GLuint pitch, height;
-   int16_t src_x, dst_x;
-   bool ok;
-
-   do {
-  /* The pitch given to the GPU must be DWORD aligned, and
-   * we want width to match pitch. Max width is (1 << 15 - 1),
-   * rounding that down to the nearest DWORD is 1 << 15 - 4
-   */
-  pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 64), 4);
-  height = (size < pitch || pitch == 0) ? 1 : size / pitch;
-
-  src_x = src_offset % 64;
-  dst_x = dst_offset % 64;
-  pitch = ALIGN(MIN2(size, (1 << 15) - 64), 4);
-  assert(src_x + pitch < 1 << 15);
-  assert(dst_x + pitch < 1 << 15);
-
-  ok = emit_copy_blit(brw, 1,
-  pitch, src_bo, src_offset - src_x,
-  ISL_TILING_LINEAR,
-  pitch, dst_bo, dst_offset - dst_x,
-  ISL_TILING_LINEAR,
-  src_x, 0, /* src x/y */
-  dst_x, 0, /* dst x/y */
-  MIN2(size, pitch), height, /* w, h */
-  COLOR_LOGICOP_COPY);
-  if (!ok) {
- _mesa_problem(ctx, "Failed to linear blit %dx%d\n",
-   MIN2(size, pitch), height);
- return;
-  }
-
-  pitch *= height;
-  if (size <= pitch)
- return;
-
-  src_offset += pitch;
-  dst_offset += pitch;
-  size -= pitch;
-   } while (1);
-}
-
 /**
  * Used to initialize the alpha value of an ARGB miptree after copying
  * into it from an XRGB source.
diff --git a/src/mesa/drivers/dri/i965/intel_blit.h 
b/src/mesa/drivers/dri/i965/intel_blit.h
index f3ca7b0..babdfa4 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.h
+++ b/src/mesa/drivers/dri/i965/intel_blit.h
@@ -61,11 +61,5 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw,
  GLshort x, GLshort y,
  GLshort w, GLshort h,
  enum gl_logicop_mode logic_op);
-void intel_emit_linear_blit(struct brw_context *brw,
-   struct brw_bo *dst_bo,
-   unsigned int dst_offset,
-   struct brw_bo *src_bo,
-   unsigned int src_offset,
-   unsigned int size);
 
 #endif
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 05/10] i965: Delete the blitter path for CopyTexSubImage

[Jason Ekstrand]

The blorp path (called first) can do anything the blitter path can do so
it's just dead code.
---
 src/mesa/drivers/dri/i965/intel_tex_copy.c | 58 --
 1 file changed, 58 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_tex_copy.c 
b/src/mesa/drivers/dri/i965/intel_tex_copy.c
index 5a0e09f..bc209c6 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_copy.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_copy.c
@@ -37,61 +37,11 @@
 #include "intel_mipmap_tree.h"
 #include "intel_fbo.h"
 #include "intel_tex.h"
-#include "intel_blit.h"
 #include "brw_context.h"
 
 #define FILE_DEBUG_FLAG DEBUG_TEXTURE
 
 
-static bool
-intel_copy_texsubimage(struct brw_context *brw,
-   struct intel_texture_image *intelImage,
-   GLint dstx, GLint dsty, GLint slice,
-   struct intel_renderbuffer *irb,
-   GLint x, GLint y, GLsizei width, GLsizei height)
-{
-   const GLenum internalFormat = intelImage->base.Base.InternalFormat;
-
-   if (!intelImage->mt || !irb || !irb->mt) {
-  if (unlikely(INTEL_DEBUG & DEBUG_PERF))
-fprintf(stderr, "%s fail %p %p (0x%08x)\n",
-__func__, intelImage->mt, irb, internalFormat);
-  return false;
-   }
-
-   /* No pixel transfer operations (zoom, bias, mapping), just a blit */
-   if (brw->ctx._ImageTransferState)
-  return false;
-
-   intel_prepare_render(brw);
-
-   /* glCopyTexSubImage() can be called on a multisampled renderbuffer (if
-* that renderbuffer is associated with the window system framebuffer),
-* however the hardware blitter can't handle this case, so fall back to
-* meta (which can, since it uses ReadPixels).
-*/
-   if (irb->Base.Base.NumSamples != 0)
-  return false;
-
-   /* glCopyTexSubImage() can't be called on a multisampled texture. */
-   assert(intelImage->base.Base.NumSamples == 0);
-
-   /* account for view parameters and face index */
-   int dst_level = intelImage->base.Base.Level +
-   intelImage->base.Base.TexObject->MinLevel;
-   int dst_slice = slice + intelImage->base.Base.Face +
-   intelImage->base.Base.TexObject->MinLayer;
-
-   /* blit from src buffer to texture */
-   return intel_miptree_blit(brw,
- irb->mt, irb->mt_level, irb->mt_layer,
- x, y, irb->Base.Base.Name == 0,
- intelImage->mt, dst_level, dst_slice,
- dstx, dsty, false,
- width, height, COLOR_LOGICOP_COPY);
-}
-
-
 static void
 intelCopyTexSubImage(struct gl_context *ctx, GLuint dims,
  struct gl_texture_image *texImage,
@@ -107,14 +57,6 @@ intelCopyTexSubImage(struct gl_context *ctx, GLuint dims,
  xoffset, yoffset, width, height))
   return;
 
-   /* Next, try the BLT engine. */
-   if (intel_copy_texsubimage(brw,
-  intel_texture_image(texImage),
-  xoffset, yoffset, slice,
-  intel_renderbuffer(rb), x, y, width, height)) {
-  return;
-   }
-
/* Finally, fall back to meta.  This will likely be slow. */
perf_debug("%s - fallback to swrast\n", __func__);
_mesa_meta_CopyTexSubImage(ctx, dims, texImage,
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 04/10] i965: Don't fall back to the blitter in BlitFramebuffer

[Jason Ekstrand]

On gen4-5, we try the blitter before we even try blorp.  On newer
platforms, blorp can do everything the blitter can so there's no point
in even having the blitter fall-back path.
---
 src/mesa/drivers/dri/i965/intel_fbo.c | 8 
 1 file changed, 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c 
b/src/mesa/drivers/dri/i965/intel_fbo.c
index ca4008f..fb84b73 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -915,14 +915,6 @@ intel_blit_framebuffer(struct gl_context *ctx,
   assert(!"Invalid blit");
}
 
-   /* Try using the BLT engine. */
-   mask = intel_blit_framebuffer_with_blitter(ctx, readFb, drawFb,
-  srcX0, srcY0, srcX1, srcY1,
-  dstX0, dstY0, dstX1, dstY1,
-  mask);
-   if (mask == 0x0)
-  return;
-
_swrast_BlitFramebuffer(ctx, readFb, drawFb,
srcX0, srcY0, srcX1, srcY1,
dstX0, dstY0, dstX1, dstY1,
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 00/10] Die, blitter, die!

[Jason Ekstrand]

This patch series completely kills off our usage of the hardware blitter
for Sandy Bridge and later.  On Sandy Bridge, the blitter was moved to
another ring and so using it incurs noticable synchronization overhead and,
at the same time, that synchronization is an endless source of GPU hangs on
SNB.  Some time around the Ivy Bridge time frame, we suspect that the
blitter ended up with somewhat slower paths to memory than the 3D engine so
it's slower in general.

To make matters worse, the blitter does not understand any sort of
compression at all and so using it frequently means having to do some sort
of resolve operation.  This is especially bad on gen9 where we have CCS
compression enabled on almost everything.  By using blorp for things like
miptree mapping, we can avoid decompressing and even get free compression
on unmap as-needed.

Jason Ekstrand (10):
  i965: Use meta for pixel ops on gen6+
  i965/blit: Delete intel_emit_linear_blit
  i965: Remove some unused includes of intel_blit.h
  i965: Don't fall back to the blitter in BlitFramebuffer
  i965: Delete the blitter path for CopyTexSubImage
  i965/miptree: Use blorp for validation tex copies on gen6+
  i965/miptree: Use blorp for blit maps on gen6+
  i965: Remove support for the BLT ring
  i965/miptree: Move the access_raw call to the individual map functions
  intel/blorp: Use linear formats for CCS_E clear colors in copies

 src/intel/blorp/blorp_blit.c   |  4 +-
 src/mesa/drivers/dri/i965/brw_clear.c  |  1 -
 src/mesa/drivers/dri/i965/intel_batchbuffer.c  | 12 +---
 src/mesa/drivers/dri/i965/intel_blit.c | 56 
 src/mesa/drivers/dri/i965/intel_blit.h |  6 --
 src/mesa/drivers/dri/i965/intel_fbo.c  |  8 ---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c  | 92 +++---
 src/mesa/drivers/dri/i965/intel_pixel_bitmap.c |  6 +-
 src/mesa/drivers/dri/i965/intel_pixel_copy.c   |  5 +-
 src/mesa/drivers/dri/i965/intel_pixel_draw.c   |  3 +-
 src/mesa/drivers/dri/i965/intel_pixel_read.c   |  1 -
 src/mesa/drivers/dri/i965/intel_tex_copy.c | 58 
 src/mesa/drivers/dri/i965/intel_tex_image.c|  1 -
 src/mesa/drivers/dri/i965/intel_tex_validate.c |  1 -
 14 files changed, 82 insertions(+), 172 deletions(-)

-- 
2.5.0.400.gff86faf

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[Mesa-dev] [ANNOUNCE] mesa 18.1.0-rc4

[dylan]

Hello List,

Mesa 18.1.0-rc4 is now available.

We have changes all over the place with this one, core mesa, gallium, the glsl
compiler, r600, radv, radeonsi, i965, anv, and dri3 all got fixes in this 
release.

I wanted to note that all bugs in the 18.1 release tracker and the 18.0 to 18.1
regression tracker have been closed, unless there are critical bugs opened in 
the
mean time this will be the last RC before the 18.1.0 release. That release is
scheduled for next Friday.

The 4th (and final) release candidate for 18.1.0 is now available. Currently we 
have:
 - 25 queued
 - 0 nominated (outstanding)
 - and 0 rejected patches

There were no merge conflicts of any kind.


Mesa stable queue
-

Nominated (NUMBER)
==

Bas Nieuwenhuizen (1):
  vulkan/wsi: Only use LINEAR modifier for prime if supported.

Brian Paul (3):
  glsl: change ast_type_qualifier bitset size to work around GCC 5.4 bug
  mesa: fix glGetInteger/Float/etc queries for vertex arrays attribs
  mesa: revert GL_[SECONDARY_]COLOR_ARRAY_SIZE glGet type to TYPE_INT

Dave Airlie (1):
  r600: fix constant buffer bounds.

Dylan Baker (1):
  Bump version to rc4

Ian Romanick (1):
  mesa: Add missing support for glFogiv(GL_FOG_DISTANCE_MODE_NV)

Jan Vesely (7):
  r600: Cleanup constant buffers on context destruction
  eg/compute: Drop reference on code_bo in destructor.
  eg/compute: Drop reference to kernel_param bo in destructor
  pipe-loader: Free driver_name in error path
  gallium/auxiliary: Add helper function to count the number of entries in 
hash table
  winsys/radeon: Destroy fd_hash table when the last winsys is removed.
  winsys/amdgpu: Destroy dev_hash table when the last winsys is removed.

Jason Ekstrand (1):
  i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL

Kenneth Graunke (1):
  i965: Don't leak blorp on Gen4-5.

Lionel Landwerlin (4):
  intel: devinfo: fix assertion on devices with odd number of EUs
  i965: silence unused variable
  i965: require pixel scoreboard stall prior to ISP disable
  anv: emit pixel scoreboard stall before ISP disable

Marek Olšák (1):
  radeonsi/gfx9: work around a GPU hang due to broken indirect indexing in 
LLVM

Matt Turner (1):
  gallium/tests: Fix assignment of EXTRA_DIST

Michel Dänzer (1):
  dri3: Only update number of back buffers in loader_dri3_get_buffers

Rhys Perry (1):
  mesa: fix error handling in get_framebuffer_parameteriv

Ross Burton (1):
  src/intel/Makefile.vulkan.am: add missing MKDIR_GEN



tag: mesa-18.1.0-rc4

https://mesa.freedesktop.org/archive/mesa-18.1.0-rc4.tar.gz
MD5:  cb9f222bc6e71314b2787112ea894eb8  mesa-18.1.0-rc4.tar.gz
SHA1: efdddcd5d5715a44cb6fdd5f693cc1d7ac3792ef  mesa-18.1.0-rc4.tar.gz
SHA256: 51b988a37968a858b12c411f52e66657f579c207e88eacd8cee8d8d137e7  
mesa-18.1.0-rc4.tar.gz
SHA512: 
5d3e94083b5750405c3f4cb5205008d30055bdfbd3cceb33283d2f15c69f90bd617ba85bb704c625aa5f0ebb05c87ab3705b39fac5a43c74d8f23dcb5c33d251
  mesa-18.1.0-rc4.tar.gz
PGP:  https://mesa.freedesktop.org/archive/mesa-18.1.0-rc4.tar.gz.sig

https://mesa.freedesktop.org/archive/mesa-18.1.0-rc4.tar.xz
MD5:  6e25463779e157302b10fb98146fca1e  mesa-18.1.0-rc4.tar.xz
SHA1: b98423c9f23221d69e17f4c3ba979185a8251240  mesa-18.1.0-rc4.tar.xz
SHA256: 8207155b822af999d621aa4e9013dff8b78dd46be8abc385e33ca8389e6dce6b  
mesa-18.1.0-rc4.tar.xz
SHA512: 
5a00e12cf588a7ea165b096d67d36d53899d6fea9922e6c09eb6fc3acc99a004e0baf3af06277c920e14f4c9685af7d5e4ee6096d9a8c1bc3a6456775af57d23
  mesa-18.1.0-rc4.tar.xz
PGP:  https://mesa.freedesktop.org/archive/mesa-18.1.0-rc4.tar.xz.sig


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[Mesa-dev] [PATCH v8 2/2] anv: enable VK_EXT_shader_stencil_export

[Caio Marcelo de Oliveira Filho]

From: Gustavo Lima Chaves 

---
 src/intel/vulkan/anv_extensions.py | 1 +
 src/intel/vulkan/anv_pipeline.c| 1 +
 src/intel/vulkan/genX_pipeline.c   | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index b5bee0881ce..8160864685f 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -112,6 +112,7 @@ EXTENSIONS = [
 Extension('VK_EXT_global_priority',   1,
   'device->has_context_priority'),
 Extension('VK_EXT_shader_viewport_index_layer',   1, True),
+Extension('VK_EXT_shader_stencil_export', 1, 'device->info.gen 
>= 9'),
 ]
 
 class VkVersion:
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 8f30136b100..240bde036d6 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -152,6 +152,7 @@ anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
  .subgroup_quad = true,
  .subgroup_shuffle = true,
  .subgroup_vote = true,
+ .stencil_export = device->instance->physicalDevice.info.gen >= 9,
   },
};
 
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 6016d257584..462c59451cc 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1600,6 +1600,7 @@ emit_3dstate_ps_extra(struct anv_pipeline *pipeline,
  ps.PixelShaderHasUAV = true;
 
 #if GEN_GEN >= 9
+  ps.PixelShaderComputesStencil = wm_prog_data->computed_stencil;
   ps.PixelShaderPullsBary= wm_prog_data->pulls_bary;
   ps.InputCoverageMaskState  = wm_prog_data->uses_sample_mask ?
ICMS_INNER_CONSERVATIVE : ICMS_NONE;
-- 
2.17.0

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[Mesa-dev] [PATCH v8 1/2] spirv: add/hookup SpvCapabilityStencilExportEXT

[Caio Marcelo de Oliveira Filho]

From: Gustavo Lima Chaves 

v2:
An attempt to support SpvExecutionModeStencilRefReplacingEXT's behavior
also follows, with the interpretation to said mode being we prevent
writes to the built-in FragStencilRefEXT variable when the execution
mode isn't set.

v3:
A more cautious reading of 1db44252d01bf7539452ccc2b5210c74b8dcd573 led
me to a missing change that would stop (what I later discovered were)
GPU hangs on the CTS test written to exercise this.

v4:
Turn FragStencilRefEXT decoration usage without StencilRefReplacingEXT
mode into a warning, instead of trying to make the variable read-only.
If we are to follow the originating extension on GL, the built-in
variable in question should never be readable anyway.

v5/v6: rebases.

v7:
Fix check for gen9 lost in rebase. (Ilia)
Reduce the scope of the bool used to track whether
SpvExecutionModeStencilRefReplacingEXT was used. Was in shader_info,
moved to vtn_builder. (Jason)

v8:
Assert for fragment shader handling StencilRefReplacingEXT execution
mode. (Caio)
Remove warning logic, since an entry point might not have
StencilRefReplacingEXT execution mode, but the global output variable
might still exist for another entry point in the module. (Jason)
---
 src/compiler/shader_info.h | 1 +
 src/compiler/spirv/spirv_to_nir.c  | 8 
 src/compiler/spirv/vtn_variables.c | 4 
 3 files changed, 13 insertions(+)

diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index afc53a88405..81f844d36ae 100644
--- a/src/compiler/shader_info.h
+++ b/src/compiler/shader_info.h
@@ -56,6 +56,7 @@ struct spirv_supported_capabilities {
bool trinary_minmax;
bool descriptor_array_dynamic_indexing;
bool runtime_descriptor_array;
+   bool stencil_export;
 };
 
 typedef struct shader_info {
diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 78437428aa7..3c3ef4658d6 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -3396,6 +3396,10 @@ vtn_handle_preamble_instruction(struct vtn_builder *b, 
SpvOp opcode,
  spv_check_supported(runtime_descriptor_array, cap);
  break;
 
+  case SpvCapabilityStencilExportEXT:
+ spv_check_supported(stencil_export, cap);
+ break;
+
   default:
  vtn_fail("Unhandled capability");
   }
@@ -3573,6 +3577,10 @@ vtn_handle_execution_mode(struct vtn_builder *b, struct 
vtn_value *entry_point,
case SpvExecutionModeContractionOff:
   break; /* OpenCL */
 
+   case SpvExecutionModeStencilRefReplacingEXT:
+  vtn_assert(b->shader->info.stage == MESA_SHADER_FRAGMENT);
+  break;
+
default:
   vtn_fail("Unhandled execution mode");
}
diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index fd8ab7f247a..53bee1b9288 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1354,6 +1354,10 @@ vtn_get_builtin_location(struct vtn_builder *b,
   *location = SYSTEM_VALUE_SUBGROUP_LT_MASK,
   set_mode_system_value(b, mode);
   break;
+   case SpvBuiltInFragStencilRefEXT:
+  *location = FRAG_RESULT_STENCIL;
+  vtn_assert(*mode == nir_var_shader_out);
+  break;
default:
   vtn_fail("unsupported builtin");
}
-- 
2.17.0

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Re: [Mesa-dev] [PATCH 3/4] i965: Handle non-zero texture buffer offsets in buffer object range calculation.

[Nanley Chery]

On Mon, Mar 19, 2018 at 11:26:58AM -0700, Francisco Jerez wrote:
> Otherwise the specified surface state will allow the GPU to access
> memory up to BufferOffset bytes past the end of the buffer.  Found by
> inspection.
> 
> Cc: mesa-sta...@lists.freedesktop.org
> ---
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index ed4def9046e..2ab15af793a 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -654,7 +654,8 @@ buffer_texture_range_size(struct brw_context *brw,
>  * so that when ISL divides by stride to obtain the number of texels, that
>  * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
>  */
> -   return MIN3((unsigned)obj->BufferSize, buffer_size,
> +   return MIN3((unsigned)obj->BufferSize,
> +   buffer_size - obj->BufferOffset,
> brw->ctx.Const.MaxTextureBufferSize * texel_size);

I don't understand this change. Previously we took the minimum between:
1) The TextureBuffer size specified by glTexBufferRange().
2) The size of the buffer object specified by glTexBuffer().
3) The maximum allowed texture buffer size.

This patch modifies case 2 to be subtracted by the offset which will
always be 0 for glTexBuffer().

>  }
>  
> -- 
> 2.16.1
> 
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Re: [Mesa-dev] [PATCH 2/4] i965: Move buffer texture size calculation into a common helper function.

[Nanley Chery]

On Mon, Mar 19, 2018 at 11:26:57AM -0700, Francisco Jerez wrote:
> The buffer texture size calculations (should be easy enough, right?)
> are repeated in three different places, each of them subtly broken in
> a different way.  E.g. the image load/store path was never fixed to
> clamp to MaxTextureBufferSize, and none of them are taking into
> account the buffer offset correctly.  It's easier to fix it all in one
> place.
> 
> Cc: mesa-sta...@lists.freedesktop.org

I created a bug so that we remember to add test coverage for this issue:
https://bugs.freedesktop.org/show_bug.cgi?id=106481

> ---
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 54 
> ++--
>  1 file changed, 32 insertions(+), 22 deletions(-)

This patch is
Reviewed-by: Nanley Chery 

> 
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index caa92d7d878..ed4def9046e 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -629,26 +629,14 @@ brw_emit_buffer_surface_state(struct brw_context *brw,
>   .mocs = brw_get_bo_mocs(devinfo, bo));
>  }
>  
> -void
> -brw_update_buffer_texture_surface(struct gl_context *ctx,
> -  unsigned unit,
> -  uint32_t *surf_offset)
> +static unsigned
> +buffer_texture_range_size(struct brw_context *brw,
> +  struct gl_texture_object *obj)
>  {
> -   struct brw_context *brw = brw_context(ctx);
> -   struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
> -   struct intel_buffer_object *intel_obj =
> -  intel_buffer_object(tObj->BufferObject);
> -   uint32_t size = tObj->BufferSize;
> -   struct brw_bo *bo = NULL;
> -   mesa_format format = tObj->_BufferObjectFormat;
> -   const enum isl_format isl_format = brw_isl_format_for_mesa_format(format);
> -   int texel_size = _mesa_get_format_bytes(format);
> -
> -   if (intel_obj) {
> -  size = MIN2(size, intel_obj->Base.Size);
> -  bo = intel_bufferobj_buffer(brw, intel_obj, tObj->BufferOffset, size,
> -  false);
> -   }
> +   assert(obj->Target == GL_TEXTURE_BUFFER);
> +   const unsigned texel_size = 
> _mesa_get_format_bytes(obj->_BufferObjectFormat);
> +   const unsigned buffer_size = (!obj->BufferObject ? 0 :
> + obj->BufferObject->Size);
>  
> /* The ARB_texture_buffer_specification says:
>  *
> @@ -666,7 +654,28 @@ brw_update_buffer_texture_surface(struct gl_context *ctx,
>  * so that when ISL divides by stride to obtain the number of texels, that
>  * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
>  */
> -   size = MIN2(size, ctx->Const.MaxTextureBufferSize * (unsigned) 
> texel_size);
> +   return MIN3((unsigned)obj->BufferSize, buffer_size,
> +   brw->ctx.Const.MaxTextureBufferSize * texel_size);
> +}
> +
> +void
> +brw_update_buffer_texture_surface(struct gl_context *ctx,
> +  unsigned unit,
> +  uint32_t *surf_offset)
> +{
> +   struct brw_context *brw = brw_context(ctx);
> +   struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
> +   struct intel_buffer_object *intel_obj =
> +  intel_buffer_object(tObj->BufferObject);
> +   const unsigned size = buffer_texture_range_size(brw, tObj);
> +   struct brw_bo *bo = NULL;
> +   mesa_format format = tObj->_BufferObjectFormat;
> +   const enum isl_format isl_format = brw_isl_format_for_mesa_format(format);
> +   int texel_size = _mesa_get_format_bytes(format);
> +
> +   if (intel_obj)
> +  bo = intel_bufferobj_buffer(brw, intel_obj, tObj->BufferOffset, size,
> +  false);
>  
> if (isl_format == ISL_FORMAT_UNSUPPORTED) {
>_mesa_problem(NULL, "bad format %s for texture buffer\n",
> @@ -1468,7 +1477,7 @@ update_buffer_image_param(struct brw_context *brw,
>struct brw_image_param *param)
>  {
> struct gl_buffer_object *obj = u->TexObj->BufferObject;
> -   const uint32_t size = MIN2((uint32_t)u->TexObj->BufferSize, obj->Size);
> +   const unsigned size = buffer_texture_range_size(brw, u->TexObj);
> update_default_image_param(brw, u, surface_idx, param);
>  
> param->size[0] = size / _mesa_get_format_bytes(u->_ActualFormat);
> @@ -1504,10 +1513,11 @@ update_image_surface(struct brw_context *brw,
>  intel_buffer_object(obj->BufferObject);
>   const unsigned texel_size = (format == ISL_FORMAT_RAW ? 1 :
>
> _mesa_get_format_bytes(u->_ActualFormat));
> + const unsigned buffer_size = buffer_texture_range_size(brw, obj);
>  
>   brw_emit_buffer_surface_state(
>  brw, surf_offset, intel_obj->buffer, obj->BufferOffset,
> -format, 

[Mesa-dev] [Bug 106480] A2B10G10R10_SNORM vertex attribute doesn't work.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106480

--- Comment #2 from mais...@archlinux.us ---
If you're using RenderDoc to inspect the vertex buffer input, you need the very
latest as there was a bug with A2BGR10_SNORM.

The vertex buffer input is (1.0, -1.0, -1.0, -1.0), (-1.0, 1.0, -1.0, -1.0) and
so on, for each component, frag shader does vColor * 0.5 + 0.5, so expected
output should land in [0, 1] range for each component.

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[Mesa-dev] [Bug 106480] A2B10G10R10_SNORM vertex attribute doesn't work.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106480

--- Comment #1 from mais...@archlinux.us ---
Created attachment 139507
  --> https://bugs.freedesktop.org/attachment.cgi?id=139507=edit
RenderDoc Capture

The color for each component should be 1.0 for one corner, and interpolate
towards 0.0 in the other corners, but A is ~0.8 where it should be 0.0, and
~0.6 where it should be 1.0. This seems very similar to SNORM being treated as
UNORM.

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[Mesa-dev] [Bug 106480] A2B10G10R10_SNORM vertex attribute doesn't work.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106480

Bug ID: 106480
   Summary: A2B10G10R10_SNORM vertex attribute doesn't work.
   Product: Mesa
   Version: git
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Vulkan/radeon
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: mais...@archlinux.us
QA Contact: mesa-dev@lists.freedesktop.org

Created attachment 139506
  --> https://bugs.freedesktop.org/attachment.cgi?id=139506=edit
Pipelines

I've tried to make a vertex shader which uses this vertex format, but it does
not work on RADV.

It is almost as if the format becomes SNORM for RGB, but UNORM for A.

To replay the pipeline creation:
git clone git://github.com/Themaister/Fossilize
cd Fossilize
git submodule update --init
mkdir build
cd build
cmake ..
make -j16
./cli/fossilize-replay /tmp/pipelines.json --filter-graphics 0

The ISA generated in VK_AMD_shader_info is:
.cli/fossilize-disasm /tmp/pipelines.json --target amd --graphics-pipeline 0
--stage vert

s_load_dwordx4 s[8:11], s[2:3], 0x0 ; C00A0201 
s_load_dwordx4 s[0:3], s[2:3], 0x10 ; C00A0001 0010
v_add_u32_e32 v0, vcc, s4, v0   ; 3204
v_mov_b32_e32 v6, 1.0   ; 7E0C02F2
v_mov_b32_e32 v7, 0 ; 7E0E0280
s_waitcnt lgkmcnt(0); BF8C007F
buffer_load_format_xy v[4:5], v0, s[8:11], 0 idxen  ; E0042000 80020400
buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 idxen ; E00C2000 8000
s_waitcnt vmcnt(1)  ; BF8C0F71
exp pos0 v4, v5, v7, v6 done; C40008CF 06070504
s_waitcnt vmcnt(0)  ; BF8C0F70
exp param0 v0, v1, v2, v3   ; C400020F 03020100
s_endpgm; BF81

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Re: [Mesa-dev] [PATCH v7 1/2] spirv: add/hookup SpvCapabilityStencilExportEXT

[Jason Ekstrand]

On Fri, May 11, 2018 at 3:06 PM, Caio Marcelo de Oliveira Filho <
caio.olive...@intel.com> wrote:

> From: Gustavo Lima Chaves 
>
> v2:
> An attempt to support SpvExecutionModeStencilRefReplacingEXT's behavior
> also follows, with the interpretation to said mode being we prevent
> writes to the built-in FragStencilRefEXT variable when the execution
> mode isn't set.
>
> v3:
> A more cautious reading of 1db44252d01bf7539452ccc2b5210c74b8dcd573 led
> me to a missing change that would stop (what I later discovered were)
> GPU hangs on the CTS test written to exercise this.
>
> v4:
> Turn FragStencilRefEXT decoration usage without StencilRefReplacingEXT
> mode into a warning, instead of trying to make the variable read-only.
> If we are to follow the originating extension on GL, the built-in
> variable in question should never be readable anyway.
>
> v5/v6: rebases.
>
> v7:
> Fix check for gen9 lost in rebase. (Ilia)
> Reduce the scope of the bool used to track whether
> SpvExecutionModeStencilRefReplacingEXT was used. Was in shader_info,
> moved to vtn_builder. (Jason)
> ---
>
> Moved the history and some of the code from the other patch. Keeping
> the patch in Gustavo name since the only real change I made was
> trivial (moving a boolean between structs).
>
>  src/compiler/shader_info.h |  1 +
>  src/compiler/spirv/spirv_to_nir.c  |  8 
>  src/compiler/spirv/vtn_private.h   |  1 +
>  src/compiler/spirv/vtn_variables.c | 10 ++
>  4 files changed, 20 insertions(+)
>
> diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
> index afc53a88405..81f844d36ae 100644
> --- a/src/compiler/shader_info.h
> +++ b/src/compiler/shader_info.h
> @@ -56,6 +56,7 @@ struct spirv_supported_capabilities {
> bool trinary_minmax;
> bool descriptor_array_dynamic_indexing;
> bool runtime_descriptor_array;
> +   bool stencil_export;
>  };
>
>  typedef struct shader_info {
> diff --git a/src/compiler/spirv/spirv_to_nir.c
> b/src/compiler/spirv/spirv_to_nir.c
> index 78437428aa7..bc8e77c35c3 100644
> --- a/src/compiler/spirv/spirv_to_nir.c
> +++ b/src/compiler/spirv/spirv_to_nir.c
> @@ -3396,6 +3396,10 @@ vtn_handle_preamble_instruction(struct vtn_builder
> *b, SpvOp opcode,
>   spv_check_supported(runtime_descriptor_array, cap);
>   break;
>
> +  case SpvCapabilityStencilExportEXT:
> + spv_check_supported(stencil_export, cap);
> + break;
> +
>default:
>   vtn_fail("Unhandled capability");
>}
> @@ -3573,6 +3577,10 @@ vtn_handle_execution_mode(struct vtn_builder *b,
> struct vtn_value *entry_point,
> case SpvExecutionModeContractionOff:
>break; /* OpenCL */
>
> +   case SpvExecutionModeStencilRefReplacingEXT:
> +  b->outputs_stencil_ref = true;
> +  break;
> +
> default:
>vtn_fail("Unhandled execution mode");
> }
> diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_
> private.h
> index b501bbf9b4a..75f78363b46 100644
> --- a/src/compiler/spirv/vtn_private.h
> +++ b/src/compiler/spirv/vtn_private.h
> @@ -574,6 +574,7 @@ struct vtn_builder {
> struct vtn_value *entry_point;
> bool origin_upper_left;
> bool pixel_center_integer;
> +   bool outputs_stencil_ref;
>
> struct vtn_function *func;
> struct exec_list functions;
> diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_
> variables.c
> index fd8ab7f247a..2bc8b5e9003 100644
> --- a/src/compiler/spirv/vtn_variables.c
> +++ b/src/compiler/spirv/vtn_variables.c
> @@ -1354,6 +1354,10 @@ vtn_get_builtin_location(struct vtn_builder *b,
>*location = SYSTEM_VALUE_SUBGROUP_LT_MASK,
>set_mode_system_value(b, mode);
>break;
> +   case SpvBuiltInFragStencilRefEXT:
> +  *location = FRAG_RESULT_STENCIL;
> +  vtn_assert(*mode == nir_var_shader_out);
> +  break;
> default:
>vtn_fail("unsupported builtin");
> }
> @@ -1425,6 +1429,12 @@ apply_var_decoration(struct vtn_builder *b,
> nir_variable *nir_var,
>case SpvBuiltInSamplePosition:
>   nir_var->data.origin_upper_left = b->origin_upper_left;
>   break;
> +  case SpvBuiltInFragStencilRefEXT:
> + if (!b->outputs_stencil_ref) {
> +vtn_warn("The StencilRefReplacingEXT mode should be declared
> when"
> + " the decoration FragStencilRefEXT is used on a
> variable");
> + }
> + break;
>

I like this check but, unfortunately, I'm not sure it's actually viable.
The problem is that execution modes (which is what this is checking) are
applied to a shader entrypoint.  Since you can have multiple entrypoints
per module and this variable may not be used for the primary entrypoint,
I'm not sure it makes sense.  Maybe best to just drop it and hope they do
the right thing.


>default:
>   break;
>}
> --
> 2.17.0
>
> ___
> mesa-dev 

[Mesa-dev] [PATCH v7 1/2] spirv: add/hookup SpvCapabilityStencilExportEXT

[Caio Marcelo de Oliveira Filho]

From: Gustavo Lima Chaves 

v2:
An attempt to support SpvExecutionModeStencilRefReplacingEXT's behavior
also follows, with the interpretation to said mode being we prevent
writes to the built-in FragStencilRefEXT variable when the execution
mode isn't set.

v3:
A more cautious reading of 1db44252d01bf7539452ccc2b5210c74b8dcd573 led
me to a missing change that would stop (what I later discovered were)
GPU hangs on the CTS test written to exercise this.

v4:
Turn FragStencilRefEXT decoration usage without StencilRefReplacingEXT
mode into a warning, instead of trying to make the variable read-only.
If we are to follow the originating extension on GL, the built-in
variable in question should never be readable anyway.

v5/v6: rebases.

v7:
Fix check for gen9 lost in rebase. (Ilia)
Reduce the scope of the bool used to track whether
SpvExecutionModeStencilRefReplacingEXT was used. Was in shader_info,
moved to vtn_builder. (Jason)
---

Moved the history and some of the code from the other patch. Keeping
the patch in Gustavo name since the only real change I made was
trivial (moving a boolean between structs).

 src/compiler/shader_info.h |  1 +
 src/compiler/spirv/spirv_to_nir.c  |  8 
 src/compiler/spirv/vtn_private.h   |  1 +
 src/compiler/spirv/vtn_variables.c | 10 ++
 4 files changed, 20 insertions(+)

diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index afc53a88405..81f844d36ae 100644
--- a/src/compiler/shader_info.h
+++ b/src/compiler/shader_info.h
@@ -56,6 +56,7 @@ struct spirv_supported_capabilities {
bool trinary_minmax;
bool descriptor_array_dynamic_indexing;
bool runtime_descriptor_array;
+   bool stencil_export;
 };
 
 typedef struct shader_info {
diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 78437428aa7..bc8e77c35c3 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -3396,6 +3396,10 @@ vtn_handle_preamble_instruction(struct vtn_builder *b, 
SpvOp opcode,
  spv_check_supported(runtime_descriptor_array, cap);
  break;
 
+  case SpvCapabilityStencilExportEXT:
+ spv_check_supported(stencil_export, cap);
+ break;
+
   default:
  vtn_fail("Unhandled capability");
   }
@@ -3573,6 +3577,10 @@ vtn_handle_execution_mode(struct vtn_builder *b, struct 
vtn_value *entry_point,
case SpvExecutionModeContractionOff:
   break; /* OpenCL */
 
+   case SpvExecutionModeStencilRefReplacingEXT:
+  b->outputs_stencil_ref = true;
+  break;
+
default:
   vtn_fail("Unhandled execution mode");
}
diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h
index b501bbf9b4a..75f78363b46 100644
--- a/src/compiler/spirv/vtn_private.h
+++ b/src/compiler/spirv/vtn_private.h
@@ -574,6 +574,7 @@ struct vtn_builder {
struct vtn_value *entry_point;
bool origin_upper_left;
bool pixel_center_integer;
+   bool outputs_stencil_ref;
 
struct vtn_function *func;
struct exec_list functions;
diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index fd8ab7f247a..2bc8b5e9003 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1354,6 +1354,10 @@ vtn_get_builtin_location(struct vtn_builder *b,
   *location = SYSTEM_VALUE_SUBGROUP_LT_MASK,
   set_mode_system_value(b, mode);
   break;
+   case SpvBuiltInFragStencilRefEXT:
+  *location = FRAG_RESULT_STENCIL;
+  vtn_assert(*mode == nir_var_shader_out);
+  break;
default:
   vtn_fail("unsupported builtin");
}
@@ -1425,6 +1429,12 @@ apply_var_decoration(struct vtn_builder *b, nir_variable 
*nir_var,
   case SpvBuiltInSamplePosition:
  nir_var->data.origin_upper_left = b->origin_upper_left;
  break;
+  case SpvBuiltInFragStencilRefEXT:
+ if (!b->outputs_stencil_ref) {
+vtn_warn("The StencilRefReplacingEXT mode should be declared when"
+ " the decoration FragStencilRefEXT is used on a 
variable");
+ }
+ break;
   default:
  break;
   }
-- 
2.17.0

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[Mesa-dev] [PATCH v7 2/2] anv: enable VK_EXT_shader_stencil_export

[Caio Marcelo de Oliveira Filho]

From: Gustavo Lima Chaves 

---
 src/intel/vulkan/anv_extensions.py | 1 +
 src/intel/vulkan/anv_pipeline.c| 1 +
 src/intel/vulkan/genX_pipeline.c   | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index b5bee0881ce..8160864685f 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -112,6 +112,7 @@ EXTENSIONS = [
 Extension('VK_EXT_global_priority',   1,
   'device->has_context_priority'),
 Extension('VK_EXT_shader_viewport_index_layer',   1, True),
+Extension('VK_EXT_shader_stencil_export', 1, 'device->info.gen 
>= 9'),
 ]
 
 class VkVersion:
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 8f30136b100..240bde036d6 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -152,6 +152,7 @@ anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
  .subgroup_quad = true,
  .subgroup_shuffle = true,
  .subgroup_vote = true,
+ .stencil_export = device->instance->physicalDevice.info.gen >= 9,
   },
};
 
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 6016d257584..462c59451cc 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1600,6 +1600,7 @@ emit_3dstate_ps_extra(struct anv_pipeline *pipeline,
  ps.PixelShaderHasUAV = true;
 
 #if GEN_GEN >= 9
+  ps.PixelShaderComputesStencil = wm_prog_data->computed_stencil;
   ps.PixelShaderPullsBary= wm_prog_data->pulls_bary;
   ps.InputCoverageMaskState  = wm_prog_data->uses_sample_mask ?
ICMS_INNER_CONSERVATIVE : ICMS_NONE;
-- 
2.17.0

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Re: [Mesa-dev] [PATCH v6 2/2] anv: enable VK_EXT_shader_stencil_export

[Jason Ekstrand]

On Fri, May 11, 2018 at 12:15 PM, Caio Marcelo de Oliveira Filho <
caio.olive...@intel.com> wrote:

> From: Gustavo Lima Chaves 
>
> v2:
> An attempt to support SpvExecutionModeStencilRefReplacingEXT's behavior
> also follows, with the interpretation to said mode being we prevent
> writes to the built-in FragStencilRefEXT variable when the execution
> mode isn't set.
>
> v3:
> A more cautious reading of 1db44252d01bf7539452ccc2b5210c74b8dcd573 led
> me to a missing change that would stop (what I later discovered were)
> GPU hangs on the CTS test written to exercize this.
>
> v4:
> Turn FragStencilRefEXT decoration usage without StencilRefReplacingEXT
> mode into a warning, instead of trying to make the variable read-only.
> If we are to follow the originating extension on GL, the built-in
> variable in question should never be readable anyway.
> ---
>
> This is the original patch from Gustavo Lima Chaves (v5 was another
> rebase), with some trivial changes to rebase.
>
> I'm updating the test on Vulkan CTS to make sure we have some coverage
> of this feature; so this should only land once that gets accepted, but
> is ready for review.
>
>  src/compiler/shader_info.h | 2 ++
>  src/compiler/spirv/spirv_to_nir.c  | 4 
>  src/compiler/spirv/vtn_variables.c | 5 +
>  src/intel/vulkan/anv_extensions.py | 1 +
>  src/intel/vulkan/anv_pipeline.c| 1 +
>  src/intel/vulkan/genX_pipeline.c   | 1 +
>  6 files changed, 14 insertions(+)
>
> diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
> index 81f844d36ae..e9141261e8b 100644
> --- a/src/compiler/shader_info.h
> +++ b/src/compiler/shader_info.h
> @@ -180,6 +180,8 @@ typedef struct shader_info {
>
>   bool pixel_center_integer;
>
> + bool outputs_stencil;
>

This isn't used by anything outside of spirv_to_nir so I don't think it
makes sense in shader_info.  If user wants to know if the output is
written, they can look at outputs_written.  If you want to have the warning
below (which seems good to me), maybe a boolean in vtn_builder instead?


> +
>   /** gl_FragDepth layout for ARB_conservative_depth. */
>   enum gl_frag_depth_layout depth_layout;
>} fs;
> diff --git a/src/compiler/spirv/spirv_to_nir.c
> b/src/compiler/spirv/spirv_to_nir.c
> index 6c0551603ea..81c5e890071 100644
> --- a/src/compiler/spirv/spirv_to_nir.c
> +++ b/src/compiler/spirv/spirv_to_nir.c
> @@ -3577,6 +3577,10 @@ vtn_handle_execution_mode(struct vtn_builder *b,
> struct vtn_value *entry_point,
> case SpvExecutionModeContractionOff:
>break; /* OpenCL */
>
> +   case SpvExecutionModeStencilRefReplacingEXT:
> +  b->shader->info.fs.outputs_stencil = true;
> +  break;
> +
> default:
>vtn_fail("Unhandled execution mode");
> }
> diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_
> variables.c
> index 53bee1b9288..0a3108bdc43 100644
> --- a/src/compiler/spirv/vtn_variables.c
> +++ b/src/compiler/spirv/vtn_variables.c
> @@ -1429,6 +1429,11 @@ apply_var_decoration(struct vtn_builder *b,
> nir_variable *nir_var,
>case SpvBuiltInSamplePosition:
>   nir_var->data.origin_upper_left = b->origin_upper_left;
>   break;
> +  case SpvBuiltInFragStencilRefEXT:
> + if (!b->shader->info.fs.outputs_stencil)
> +vtn_warn("The StencilRefReplacingEXT mode should be declared
> when"
> + " the decoration FragStencilRefEXT is used on a
> variable");
> + break;
>

This stuff should go in the previous patch.


>default:
>   break;
>}
> diff --git a/src/intel/vulkan/anv_extensions.py b/src/intel/vulkan/anv_
> extensions.py
> index b5bee0881ce..8160864685f 100644
> --- a/src/intel/vulkan/anv_extensions.py
> +++ b/src/intel/vulkan/anv_extensions.py
> @@ -112,6 +112,7 @@ EXTENSIONS = [
>  Extension('VK_EXT_global_priority',   1,
>'device->has_context_priority'),
>  Extension('VK_EXT_shader_viewport_index_layer',   1, True),
> +Extension('VK_EXT_shader_stencil_export', 1,
> 'device->info.gen >= 9'),
>  ]
>
>  class VkVersion:
> diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_
> pipeline.c
> index 8f30136b100..c37b9b96e11 100644
> --- a/src/intel/vulkan/anv_pipeline.c
> +++ b/src/intel/vulkan/anv_pipeline.c
> @@ -152,6 +152,7 @@ anv_shader_compile_to_nir(struct anv_pipeline
> *pipeline,
>   .subgroup_quad = true,
>   .subgroup_shuffle = true,
>   .subgroup_vote = true,
> + .stencil_export = true,
>},
> };
>
> diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_
> pipeline.c
> index 6016d257584..462c59451cc 100644
> --- a/src/intel/vulkan/genX_pipeline.c
> +++ b/src/intel/vulkan/genX_pipeline.c
> @@ -1600,6 +1600,7 @@ emit_3dstate_ps_extra(struct anv_pipeline *pipeline,
>   ps.PixelShaderHasUAV = true;
>
>  #if GEN_GEN >= 9

Re: [Mesa-dev] [PATCH v6 2/2] anv: enable VK_EXT_shader_stencil_export

[Caio Marcelo de Oliveira Filho]

> > [please wait for someone who knows what they're doing to actually
> > review before sending a new version]
> 
> Sorry, I wanted to have some recent on the list for folks doing CTS
> review to apply. I will avoid this in the future.

After a second read, I probably misunderstood what you meant there --
I thought you were unhappy that I sent this series at all, but it
seems you meant 'wait for more reviews before sending a fix for the
issue just pointed out'.


Thanks,
Caio
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Re: [Mesa-dev] [PATCH v6 2/2] anv: enable VK_EXT_shader_stencil_export

[Ilia Mirkin]

On Fri, May 11, 2018 at 3:49 PM, Caio Marcelo de Oliveira Filho
 wrote:
> On Fri, May 11, 2018 at 03:31:31PM -0400, Ilia Mirkin wrote:
>> > diff --git a/src/intel/vulkan/anv_pipeline.c 
>> > b/src/intel/vulkan/anv_pipeline.c
>> > index 8f30136b100..c37b9b96e11 100644
>> > --- a/src/intel/vulkan/anv_pipeline.c
>> > +++ b/src/intel/vulkan/anv_pipeline.c
>> > @@ -152,6 +152,7 @@ anv_shader_compile_to_nir(struct anv_pipeline 
>> > *pipeline,
>> >   .subgroup_quad = true,
>> >   .subgroup_shuffle = true,
>> >   .subgroup_vote = true,
>> > + .stencil_export = true,
>>
>> gen9+, no?
>
> You are correct, I messed up on this one since Gustavo's latest
> version is correct. Thanks for pointing out.
>
>
>> [please wait for someone who knows what they're doing to actually
>> review before sending a new version]
>
> Sorry, I wanted to have some recent on the list for folks doing CTS
> review to apply. I will avoid this in the future.

I meant don't send an update just with the above fix without someone
other than me reviewing :) I'm the one who doesn't know what they're
doing.
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Re: [Mesa-dev] [PATCH v6 2/2] anv: enable VK_EXT_shader_stencil_export

[Caio Marcelo de Oliveira Filho]

On Fri, May 11, 2018 at 03:31:31PM -0400, Ilia Mirkin wrote:
> > diff --git a/src/intel/vulkan/anv_pipeline.c 
> > b/src/intel/vulkan/anv_pipeline.c
> > index 8f30136b100..c37b9b96e11 100644
> > --- a/src/intel/vulkan/anv_pipeline.c
> > +++ b/src/intel/vulkan/anv_pipeline.c
> > @@ -152,6 +152,7 @@ anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
> >   .subgroup_quad = true,
> >   .subgroup_shuffle = true,
> >   .subgroup_vote = true,
> > + .stencil_export = true,
> 
> gen9+, no?

You are correct, I messed up on this one since Gustavo's latest
version is correct. Thanks for pointing out.


> [please wait for someone who knows what they're doing to actually
> review before sending a new version]

Sorry, I wanted to have some recent on the list for folks doing CTS
review to apply. I will avoid this in the future.


Thanks,
Caio
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Re: [Mesa-dev] [PATCH v6 2/2] anv: enable VK_EXT_shader_stencil_export

[Ilia Mirkin]

On Fri, May 11, 2018 at 3:15 PM, Caio Marcelo de Oliveira Filho
 wrote:
> From: Gustavo Lima Chaves 
>
> v2:
> An attempt to support SpvExecutionModeStencilRefReplacingEXT's behavior
> also follows, with the interpretation to said mode being we prevent
> writes to the built-in FragStencilRefEXT variable when the execution
> mode isn't set.
>
> v3:
> A more cautious reading of 1db44252d01bf7539452ccc2b5210c74b8dcd573 led
> me to a missing change that would stop (what I later discovered were)
> GPU hangs on the CTS test written to exercize this.
>
> v4:
> Turn FragStencilRefEXT decoration usage without StencilRefReplacingEXT
> mode into a warning, instead of trying to make the variable read-only.
> If we are to follow the originating extension on GL, the built-in
> variable in question should never be readable anyway.
> ---
>
> This is the original patch from Gustavo Lima Chaves (v5 was another
> rebase), with some trivial changes to rebase.
>
> I'm updating the test on Vulkan CTS to make sure we have some coverage
> of this feature; so this should only land once that gets accepted, but
> is ready for review.
>
>  src/compiler/shader_info.h | 2 ++
>  src/compiler/spirv/spirv_to_nir.c  | 4 
>  src/compiler/spirv/vtn_variables.c | 5 +
>  src/intel/vulkan/anv_extensions.py | 1 +
>  src/intel/vulkan/anv_pipeline.c| 1 +
>  src/intel/vulkan/genX_pipeline.c   | 1 +
>  6 files changed, 14 insertions(+)
>
> diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
> index 81f844d36ae..e9141261e8b 100644
> --- a/src/compiler/shader_info.h
> +++ b/src/compiler/shader_info.h
> @@ -180,6 +180,8 @@ typedef struct shader_info {
>
>   bool pixel_center_integer;
>
> + bool outputs_stencil;
> +
>   /** gl_FragDepth layout for ARB_conservative_depth. */
>   enum gl_frag_depth_layout depth_layout;
>} fs;
> diff --git a/src/compiler/spirv/spirv_to_nir.c 
> b/src/compiler/spirv/spirv_to_nir.c
> index 6c0551603ea..81c5e890071 100644
> --- a/src/compiler/spirv/spirv_to_nir.c
> +++ b/src/compiler/spirv/spirv_to_nir.c
> @@ -3577,6 +3577,10 @@ vtn_handle_execution_mode(struct vtn_builder *b, 
> struct vtn_value *entry_point,
> case SpvExecutionModeContractionOff:
>break; /* OpenCL */
>
> +   case SpvExecutionModeStencilRefReplacingEXT:
> +  b->shader->info.fs.outputs_stencil = true;
> +  break;
> +
> default:
>vtn_fail("Unhandled execution mode");
> }
> diff --git a/src/compiler/spirv/vtn_variables.c 
> b/src/compiler/spirv/vtn_variables.c
> index 53bee1b9288..0a3108bdc43 100644
> --- a/src/compiler/spirv/vtn_variables.c
> +++ b/src/compiler/spirv/vtn_variables.c
> @@ -1429,6 +1429,11 @@ apply_var_decoration(struct vtn_builder *b, 
> nir_variable *nir_var,
>case SpvBuiltInSamplePosition:
>   nir_var->data.origin_upper_left = b->origin_upper_left;
>   break;
> +  case SpvBuiltInFragStencilRefEXT:
> + if (!b->shader->info.fs.outputs_stencil)
> +vtn_warn("The StencilRefReplacingEXT mode should be declared 
> when"
> + " the decoration FragStencilRefEXT is used on a 
> variable");
> + break;
>default:
>   break;
>}
> diff --git a/src/intel/vulkan/anv_extensions.py 
> b/src/intel/vulkan/anv_extensions.py
> index b5bee0881ce..8160864685f 100644
> --- a/src/intel/vulkan/anv_extensions.py
> +++ b/src/intel/vulkan/anv_extensions.py
> @@ -112,6 +112,7 @@ EXTENSIONS = [
>  Extension('VK_EXT_global_priority',   1,
>'device->has_context_priority'),
>  Extension('VK_EXT_shader_viewport_index_layer',   1, True),
> +Extension('VK_EXT_shader_stencil_export', 1, 
> 'device->info.gen >= 9'),
>  ]
>
>  class VkVersion:
> diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
> index 8f30136b100..c37b9b96e11 100644
> --- a/src/intel/vulkan/anv_pipeline.c
> +++ b/src/intel/vulkan/anv_pipeline.c
> @@ -152,6 +152,7 @@ anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
>   .subgroup_quad = true,
>   .subgroup_shuffle = true,
>   .subgroup_vote = true,
> + .stencil_export = true,

gen9+, no? [please wait for someone who knows what they're doing to
actually review before sending a new version]

>},
> };
>
> diff --git a/src/intel/vulkan/genX_pipeline.c 
> b/src/intel/vulkan/genX_pipeline.c
> index 6016d257584..462c59451cc 100644
> --- a/src/intel/vulkan/genX_pipeline.c
> +++ b/src/intel/vulkan/genX_pipeline.c
> @@ -1600,6 +1600,7 @@ emit_3dstate_ps_extra(struct anv_pipeline *pipeline,
>   ps.PixelShaderHasUAV = true;
>
>  #if GEN_GEN >= 9
> +  ps.PixelShaderComputesStencil = wm_prog_data->computed_stencil;
>ps.PixelShaderPullsBary= wm_prog_data->pulls_bary;
>ps.InputCoverageMaskState  = wm_prog_data->uses_sample_mask ?
>

[Mesa-dev] [PATCH v6 1/2] spirv: add/hookup SpvCapabilityStencilExportEXT

[Caio Marcelo de Oliveira Filho]

From: Gustavo Lima Chaves 

Reviewed-by: Jason Ekstrand 
Reviewed-by: Iago Toral Quiroga 
---

This is the original patch from Gustavo Lima Chaves rebased and
with the added R-b's.

 src/compiler/shader_info.h | 1 +
 src/compiler/spirv/spirv_to_nir.c  | 4 
 src/compiler/spirv/vtn_variables.c | 4 
 3 files changed, 9 insertions(+)

diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index afc53a88405..81f844d36ae 100644
--- a/src/compiler/shader_info.h
+++ b/src/compiler/shader_info.h
@@ -56,6 +56,7 @@ struct spirv_supported_capabilities {
bool trinary_minmax;
bool descriptor_array_dynamic_indexing;
bool runtime_descriptor_array;
+   bool stencil_export;
 };
 
 typedef struct shader_info {
diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 78437428aa7..6c0551603ea 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -3396,6 +3396,10 @@ vtn_handle_preamble_instruction(struct vtn_builder *b, 
SpvOp opcode,
  spv_check_supported(runtime_descriptor_array, cap);
  break;
 
+  case SpvCapabilityStencilExportEXT:
+ spv_check_supported(stencil_export, cap);
+ break;
+
   default:
  vtn_fail("Unhandled capability");
   }
diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index fd8ab7f247a..53bee1b9288 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1354,6 +1354,10 @@ vtn_get_builtin_location(struct vtn_builder *b,
   *location = SYSTEM_VALUE_SUBGROUP_LT_MASK,
   set_mode_system_value(b, mode);
   break;
+   case SpvBuiltInFragStencilRefEXT:
+  *location = FRAG_RESULT_STENCIL;
+  vtn_assert(*mode == nir_var_shader_out);
+  break;
default:
   vtn_fail("unsupported builtin");
}
-- 
2.17.0

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[Mesa-dev] [PATCH v6 2/2] anv: enable VK_EXT_shader_stencil_export

[Caio Marcelo de Oliveira Filho]

From: Gustavo Lima Chaves 

v2:
An attempt to support SpvExecutionModeStencilRefReplacingEXT's behavior
also follows, with the interpretation to said mode being we prevent
writes to the built-in FragStencilRefEXT variable when the execution
mode isn't set.

v3:
A more cautious reading of 1db44252d01bf7539452ccc2b5210c74b8dcd573 led
me to a missing change that would stop (what I later discovered were)
GPU hangs on the CTS test written to exercize this.

v4:
Turn FragStencilRefEXT decoration usage without StencilRefReplacingEXT
mode into a warning, instead of trying to make the variable read-only.
If we are to follow the originating extension on GL, the built-in
variable in question should never be readable anyway.
---

This is the original patch from Gustavo Lima Chaves (v5 was another
rebase), with some trivial changes to rebase.

I'm updating the test on Vulkan CTS to make sure we have some coverage
of this feature; so this should only land once that gets accepted, but
is ready for review.

 src/compiler/shader_info.h | 2 ++
 src/compiler/spirv/spirv_to_nir.c  | 4 
 src/compiler/spirv/vtn_variables.c | 5 +
 src/intel/vulkan/anv_extensions.py | 1 +
 src/intel/vulkan/anv_pipeline.c| 1 +
 src/intel/vulkan/genX_pipeline.c   | 1 +
 6 files changed, 14 insertions(+)

diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index 81f844d36ae..e9141261e8b 100644
--- a/src/compiler/shader_info.h
+++ b/src/compiler/shader_info.h
@@ -180,6 +180,8 @@ typedef struct shader_info {
 
  bool pixel_center_integer;
 
+ bool outputs_stencil;
+
  /** gl_FragDepth layout for ARB_conservative_depth. */
  enum gl_frag_depth_layout depth_layout;
   } fs;
diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 6c0551603ea..81c5e890071 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -3577,6 +3577,10 @@ vtn_handle_execution_mode(struct vtn_builder *b, struct 
vtn_value *entry_point,
case SpvExecutionModeContractionOff:
   break; /* OpenCL */
 
+   case SpvExecutionModeStencilRefReplacingEXT:
+  b->shader->info.fs.outputs_stencil = true;
+  break;
+
default:
   vtn_fail("Unhandled execution mode");
}
diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index 53bee1b9288..0a3108bdc43 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1429,6 +1429,11 @@ apply_var_decoration(struct vtn_builder *b, nir_variable 
*nir_var,
   case SpvBuiltInSamplePosition:
  nir_var->data.origin_upper_left = b->origin_upper_left;
  break;
+  case SpvBuiltInFragStencilRefEXT:
+ if (!b->shader->info.fs.outputs_stencil)
+vtn_warn("The StencilRefReplacingEXT mode should be declared when"
+ " the decoration FragStencilRefEXT is used on a 
variable");
+ break;
   default:
  break;
   }
diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index b5bee0881ce..8160864685f 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -112,6 +112,7 @@ EXTENSIONS = [
 Extension('VK_EXT_global_priority',   1,
   'device->has_context_priority'),
 Extension('VK_EXT_shader_viewport_index_layer',   1, True),
+Extension('VK_EXT_shader_stencil_export', 1, 'device->info.gen 
>= 9'),
 ]
 
 class VkVersion:
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 8f30136b100..c37b9b96e11 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -152,6 +152,7 @@ anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
  .subgroup_quad = true,
  .subgroup_shuffle = true,
  .subgroup_vote = true,
+ .stencil_export = true,
   },
};
 
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 6016d257584..462c59451cc 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1600,6 +1600,7 @@ emit_3dstate_ps_extra(struct anv_pipeline *pipeline,
  ps.PixelShaderHasUAV = true;
 
 #if GEN_GEN >= 9
+  ps.PixelShaderComputesStencil = wm_prog_data->computed_stencil;
   ps.PixelShaderPullsBary= wm_prog_data->pulls_bary;
   ps.InputCoverageMaskState  = wm_prog_data->uses_sample_mask ?
ICMS_INNER_CONSERVATIVE : ICMS_NONE;
-- 
2.17.0

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[Mesa-dev] [Bug 106479] NDEBUG not defined for libamdgpu_addrlib

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106479

Bug ID: 106479
   Summary: NDEBUG not defined for libamdgpu_addrlib
   Product: Mesa
   Version: git
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Mesa core
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: valentin.da...@gmail.com
QA Contact: mesa-dev@lists.freedesktop.org

Created attachment 139503
  --> https://bugs.freedesktop.org/attachment.cgi?id=139503=edit
Patch

I got crashes with Vulkan applications using Unity and SteamVR. Among them the
SteamVR room setup.

Here is the assertion that breaks.

../../../src/amd/addrlib/core/addrlib2.h:732: VOID
Addr::V2::Lib::VerifyMipLevelInfo(const ADDR2_COMPUTE_SURFACE_INFO_INPUT*)
const: Assertion `actualMipLevels >= pIn->numMipLevels' failed.

And this breaks even when disabling debug. I suppose the was an oversight when
writing the Makefile.

The provided patch solves my issue.

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Re: [Mesa-dev] Mesa (18.1): Bump version to rc4

[Dylan Baker]

Quoting Michel Dänzer (2018-05-11 09:55:23)
> 
> Hi Dylan,
> 
> 
> any reason for not picking 6f81e07ecb8c0793dc482307d5d96fd3df95b7d2
> "dri3: Only update number of back buffers in loader_dri3_get_buffers"
> for rc4?

Hi Michel,

That patch is present in rc4 as 312c2f047e5ce7fe277d34d7d99b9945c60f4e60.

Dylan


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Re: [Mesa-dev] Mesa (18.1): Bump version to rc4

[Michel Dänzer]

Hi Dylan,


any reason for not picking 6f81e07ecb8c0793dc482307d5d96fd3df95b7d2
"dri3: Only update number of back buffers in loader_dri3_get_buffers"
for rc4?


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Re: [Mesa-dev] [PATCH] etnaviv: remove pipe_fence_handle::ctx

[Christian Gmeiner]

Am Mi., 9. Mai 2018 um 03:00 Uhr schrieb Rob Clark :

> A fence can outlive the ctx it was created from (see glmark2).. etnaviv
> doesn't actually need fence->ctx so lets remove it before someone makes
> the mistake of assuming it is a valid pointer.

> Signed-off-by: Rob Clark 

Reviewed-by: Christian Gmeiner 

> ---
> I assume this was just copy-pasta from freedreno.. where since eed9685d
> (for ctx priority) we actually do need the ctx to wait on a fence..

> fixing this for freedreno will require a libdrm version bump (to add
> refcnt'ing to fd_pipe) so we don't have to refcnt the entire ctx (so if
> anyone needs a libdrm release, please hold off for a day or so)

>   src/gallium/drivers/etnaviv/etnaviv_fence.c | 2 --
>   1 file changed, 2 deletions(-)

> diff --git a/src/gallium/drivers/etnaviv/etnaviv_fence.c
b/src/gallium/drivers/etnaviv/etnaviv_fence.c
> index 22a964ad282..cf3e67766ba 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_fence.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_fence.c
> @@ -36,7 +36,6 @@

>   struct pipe_fence_handle {
>  struct pipe_reference reference;
> -   struct etna_context *ctx;
>  struct etna_screen *screen;
>  int fence_fd;
>  uint32_t timestamp;
> @@ -111,7 +110,6 @@ etna_fence_create(struct pipe_context *pctx, int
fence_fd)

>  pipe_reference_init(>reference, 1);

> -   fence->ctx = ctx;
>  fence->screen = ctx->screen;
>  fence->timestamp = etna_cmd_stream_timestamp(ctx->stream);
>  fence->fence_fd = fence_fd;
> --
> 2.17.0

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-- 
greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info
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Re: [Mesa-dev] [PATCH 3/4] i965/drm: Searching for a cached buffer for reuse

[James Xiong]

On Fri, 11 May 2018 16:57:22 +0100
Chris Wilson  wrote:

> Quoting James Xiong (2018-05-11 16:35:04)
> > On Thu, 10 May 2018 13:56:12 -0700
> > Kenneth Graunke  wrote:
> > 
> > > On Friday, May 4, 2018 5:56:04 PM PDT James Xiong wrote:
> > > > From: "Xiong, James" 
> > > > 
> > > > Now that a bucket contains cached buffers with different sizes,
> > > > go through its list and search for a cached buffer with enough
> > > > size.
> > > > 
> > > > Signed-off-by: Xiong, James 
<...>
> > > > pos, member);   \ 
> > > 
> > > Hi James,
> > > 
> > > I don't particularly like the idea of introducing linear linked
> > > list walks to find a buffer.  It's a really nice property to have
> > > every buffer in the bucket be suitable and be able to grab one
> > > immediately. It sounds like purging things more often in patch 4
> > > reduces the cost of this new list walk, but...it'd be nice to not
> > > add it in the first place.
> > Yes, the purge, as well as the cleanup routine which kicks in from
> > time
> 
> It should not be time to time, it should be whenever the cache is
> older than a 1s (use a timer thread if you are concerned) as it being
> checked everytime something is put into the cache (and so before the
> lists grow). 
That's exactly how it works, the cleanup gets called before a buffer is
going to be put in the bucket, there is also a check if the an earlier
cleaned up has been performed within 1s BTW.

Sorry for the misleading. 
> If it is overallocating such that you are running out of
> memory and not reusing buffers, the cache is barely functioning. Now
> that's the information you want to present, where/when/why/how the
> cache is not working. What is being put into the cache that is never
> reused? -Chris
I tried to cleanup cached buffers more aggressively, every single time
when a buffer is unreferenced, and measure the memory usage, it didn't
help much. I believe that cached-but-not-get-reused might contribute to
the overhead too but mostly it is from the bucket size roundup.

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Re: [Mesa-dev] [PATCH 2/2] st/nir: use NIR for asm programs

[Eric Anholt]

Timothy Arceri  writes:

> On 10/05/18 02:46, Eric Anholt wrote:
>> Timothy Arceri  writes:
>> 
>>> ---
>>>   src/mesa/state_tracker/st_program.c | 65 +
>>>   1 file changed, 58 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/src/mesa/state_tracker/st_program.c 
>>> b/src/mesa/state_tracker/st_program.c
>>> index fe72ddaf2c0..4e2476a26ef 100644
>>> --- a/src/mesa/state_tracker/st_program.c
>>> +++ b/src/mesa/state_tracker/st_program.c
>>> @@ -37,6 +37,7 @@
>>>   #include "main/mtypes.h"
>>>   #include "program/prog_parameter.h"
>>>   #include "program/prog_print.h"
>>> +#include "program/prog_to_nir.h"
>>>   #include "program/programopt.h"
>>>   
>>>   #include "compiler/nir/nir.h"
>>> @@ -377,6 +378,28 @@ st_release_cp_variants(struct st_context *st, struct 
>>> st_compute_program *stcp)
>>>  }
>>>   }
>>>   
>>> +/**
>>> + * Translate ARB (asm) program to NIR
>>> + */
>>> +static nir_shader *
>>> +st_translate_prog_to_nir(struct st_context *st, struct gl_program *prog,
>>> + gl_shader_stage stage)
>>> +{
>>> +   const struct gl_shader_compiler_options *options =
>>> +  >ctx->Const.ShaderCompilerOptions[stage];
>>> +
>>> +   /* Translate to NIR */
>>> +   nir_shader *nir = prog_to_nir(prog, options->NirOptions);
>>> +   NIR_PASS_V(nir, nir_lower_regs_to_ssa); /* turn registers into SSA */
>>> +   nir_validate_shader(nir);
>>> +
>>> +   /* Optimise NIR */
>>> +   st_nir_opts(nir);
>>> +   nir_validate_shader(nir);
>>> +
>>> +   return nir;
>>> +}
>>> +
>>>   /**
>>>* Translate a vertex program.
>>>*/
>>> @@ -458,15 +481,28 @@ st_translate_vertex_program(struct st_context *st,
>>> /* No samplers are allowed in ARB_vp. */
>>>  }
>>>   
>>> -   if (stvp->shader_program) {
>>> -  struct gl_program *prog = stvp->shader_program->last_vert_prog;
>>> -  if (prog) {
>>> - st_translate_stream_output_info2(prog->sh.LinkedTransformFeedback,
>>> -  stvp->result_to_output,
>>> -  >tgsi.stream_output);
>>> +   enum pipe_shader_ir preferred_ir = (enum pipe_shader_ir)
>>> +  st->pipe->screen->get_shader_param(st->pipe->screen, 
>>> PIPE_SHADER_VERTEX,
>>> + PIPE_SHADER_CAP_PREFERRED_IR);
>>> +
>>> +   if (preferred_ir == PIPE_SHADER_IR_NIR) {
>>> +  if (stvp->shader_program) {
>>> + struct gl_program *prog = stvp->shader_program->last_vert_prog;
>>> + if (prog) {
>>> +
>>> st_translate_stream_output_info2(prog->sh.LinkedTransformFeedback,
>>> + stvp->result_to_output,
>>> + >tgsi.stream_output);
>>> + }
>>> +
>>> + st_store_ir_in_disk_cache(st, >Base, true);
>> 
>> Doesn't this block want to be run in the shader_program &&
>> !PIPE_SHADER_IR_NIR case?
>
> There is no such case. stvp->shader_program is equal to 
> PIPE_SHADER_IR_NIR for GLSL shaders.

This code is so twisty.  You're right.  For both:

Reviewed-by: Eric Anholt 


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Re: [Mesa-dev] [PATCH 3/4] i965/drm: Searching for a cached buffer for reuse

[Chris Wilson]

Quoting James Xiong (2018-05-11 16:35:04)
> On Thu, 10 May 2018 13:56:12 -0700
> Kenneth Graunke  wrote:
> 
> > On Friday, May 4, 2018 5:56:04 PM PDT James Xiong wrote:
> > > From: "Xiong, James" 
> > > 
> > > Now that a bucket contains cached buffers with different sizes, go
> > > through its list and search for a cached buffer with enough size.
> > > 
> > > Signed-off-by: Xiong, James 
> > > ---
> > >  src/mesa/drivers/dri/i965/brw_bufmgr.c | 21 +++--
> > >  src/util/list.h|  5 +
> > >  2 files changed, 20 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
> > > b/src/mesa/drivers/dri/i965/brw_bufmgr.c index 6a9b005..5235aa6
> > > 100644 --- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
> > > +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
> > > @@ -281,7 +281,7 @@ cached_bo_for_size(struct brw_bufmgr *bufmgr,
> > > assert(!(busy && zeroed));
> > >  
> > > if(bucket != NULL && !list_empty(>head)) {
> > > -  struct brw_bo *bo;
> > > +  struct brw_bo *bo, *temp_bo;
> > >  retry:
> > >bo = NULL;
> > >  
> > > @@ -292,8 +292,13 @@ retry:
> > >* asked us to zero the buffer, we don't want this
> > >* because we are going to mmap it.
> > >*/
> > > - bo = LIST_ENTRY(struct brw_bo, bucket->head.prev, head);
> > > - list_del(>head);
> > > + LIST_FOR_EACH_ENTRY_REV(temp_bo, >head, head) {
> > > +if (temp_bo->size >= size) {
> > > +   bo = temp_bo;
> > > +   list_del(>head);
> > > +   break;
> > > +}
> > > + }
> > >} else {
> > >   /* For non-render-target BOs (where we're probably
> > >* going to map it first thing in order to fill it
> > > @@ -302,9 +307,13 @@ retry:
> > >* allocating a new buffer is probably faster than
> > >* waiting for the GPU to finish.
> > >*/
> > > - bo = LIST_ENTRY(struct brw_bo, bucket->head.next, head);
> > > - if (!brw_bo_busy(bo)) {
> > > -list_del(>head);
> > > + LIST_FOR_EACH_ENTRY(temp_bo, >head, head) {
> > > +if (temp_bo->size >= size &&
> > > +!brw_bo_busy(temp_bo)) {
> > > +   bo = temp_bo;
> > > +   list_del(>head);
> > > +   break;
> > > +}
> > >   }
> > >}
> > >  
> > > diff --git a/src/util/list.h b/src/util/list.h
> > > index 6edb750..9362072 100644
> > > --- a/src/util/list.h
> > > +++ b/src/util/list.h
> > > @@ -189,6 +189,11 @@ static inline void list_validate(struct
> > > list_head *list) >member !=
> > > (head); \ pos =
> > > container_of(pos->member.next, pos, member)) 
> > > +#define LIST_FOR_EACH_ENTRY_REV(pos, head,
> > > member)  \
> > > +   for (pos = NULL, pos = container_of((head)->prev, pos,
> > > member);  \
> > > +>member !=
> > > (head); \
> > > +pos = container_of(pos->member.prev, pos, member))
> > > +
> > >  #define LIST_FOR_EACH_ENTRY_SAFE(pos, storage, head,
> > > member) \ for (pos = NULL, pos = container_of((head)->next,
> > > pos, member),   \ storage = container_of(pos->member.next,
> > > pos, member);   \ 
> > 
> > Hi James,
> > 
> > I don't particularly like the idea of introducing linear linked list
> > walks to find a buffer.  It's a really nice property to have every
> > buffer in the bucket be suitable and be able to grab one immediately.
> > It sounds like purging things more often in patch 4 reduces the cost
> > of this new list walk, but...it'd be nice to not add it in the first
> > place.
> Yes, the purge, as well as the cleanup routine which kicks in from time

It should not be time to time, it should be whenever the cache is older
than a 1s (use a timer thread if you are concerned) as it being checked
everytime something is put into the cache (and so before the lists grow).
If it is overallocating such that you are running out of memory and not
reusing buffers, the cache is barely functioning. Now that's the
information you want to present, where/when/why/how the cache is not
working. What is being put into the cache that is never reused?
-Chris
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Re: [Mesa-dev] [PATCH mesa 4/5] meson: fix platforms=[]

[Dylan Baker]

Quoting Eric Engestrom (2018-05-11 07:12:29)
> Fixes: 5608d0a2cee47c7d037f ("meson: use array type options")
> Signed-off-by: Eric Engestrom 
> ---
>  meson.build | 26 +++---
>  1 file changed, 11 insertions(+), 15 deletions(-)
> 
> diff --git a/meson.build b/meson.build
> index a8999f37bd06a84cf7c0..5dd5168eb95dc823bbbe 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -231,12 +231,6 @@ else
>with_dri_platform = 'none'
>  endif
>  
> -with_platform_android = false
> -with_platform_wayland = false
> -with_platform_x11 = false
> -with_platform_drm = false
> -with_platform_surfaceless = false
> -egl_native_platform = ''
>  _platforms = get_option('platforms')
>  if _platforms.contains('auto')
>if system_has_kms_drm
> @@ -249,13 +243,15 @@ if _platforms.contains('auto')
>  error('Unknown OS. Please pass -Dplatforms to set platforms. Patches 
> gladly accepted to fix this.')
>endif
>  endif
> -if _platforms != ['']
> -  with_platform_android = _platforms.contains('android')
> -  with_platform_x11 = _platforms.contains('x11')
> -  with_platform_wayland = _platforms.contains('wayland')
> -  with_platform_drm = _platforms.contains('drm')
> -  with_platform_haiku = _platforms.contains('haiku')
> -  with_platform_surfaceless = _platforms.contains('surfaceless')
> +
> +with_platform_android = _platforms.contains('android')
> +with_platform_x11 = _platforms.contains('x11')
> +with_platform_wayland = _platforms.contains('wayland')
> +with_platform_drm = _platforms.contains('drm')
> +with_platform_haiku = _platforms.contains('haiku')
> +with_platform_surfaceless = _platforms.contains('surfaceless')
> +

> +if _platforms.length() != 0
>egl_native_platform = _platforms[0]
>  endif

This isn't going to work, since if you set -Dplatforms=, then _platforms will ==
['']

>  
> @@ -298,13 +294,13 @@ endif
>  
>  _egl = get_option('egl')
>  if _egl == 'auto'
> -  with_egl = with_dri and with_shared_glapi and egl_native_platform != ''
> +  with_egl = with_dri and with_shared_glapi and _platforms.length() != 0
>  elif _egl == 'true'
>if not with_dri
>  error('EGL requires dri')
>elif not with_shared_glapi
>  error('EGL requires shared-glapi')
> -  elif egl_native_platform == ''
> +  elif _platforms.length() == 0
>  error('No platforms specified, consider -Dplatforms=drm,x11 at least')
>elif not ['disabled', 'dri'].contains(with_glx)
>  error('EGL requires dri, but a GLX is being built without dri')

Same for all of these.

Dylan

> -- 
> Cheers,
>   Eric
> 


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Re: [Mesa-dev] [PATCH mesa 3/5] meson: fix vulkan-drivers=[]

[Dylan Baker]

Quoting Eric Engestrom (2018-05-11 07:12:28)
> Fixes: 5608d0a2cee47c7d037f ("meson: use array type options")
> Signed-off-by: Eric Engestrom 
> ---
>  meson.build | 12 
>  1 file changed, 4 insertions(+), 8 deletions(-)
> 
> diff --git a/meson.build b/meson.build
> index 6b069ae5dfc52adba1b7..a8999f37bd06a84cf7c0 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -180,9 +180,6 @@ if with_gallium and system_has_kms_drm
>endif
>  endif
>  
> -with_intel_vk = false
> -with_amd_vk = false
> -with_any_vk = false
>  _vulkan_drivers = get_option('vulkan-drivers')
>  if _vulkan_drivers.contains('auto')
>if system_has_kms_drm
> @@ -198,11 +195,10 @@ if _vulkan_drivers.contains('auto')
>  error('Unknown OS. Please pass -Dvulkan-drivers to set driver options. 
> Patches gladly accepted to fix this.')
>endif
>  endif
> -if _vulkan_drivers != ['']
> -  with_intel_vk = _vulkan_drivers.contains('intel')
> -  with_amd_vk = _vulkan_drivers.contains('amd')
> -  with_any_vk = true
> -endif
> +
> +with_intel_vk = _vulkan_drivers.contains('intel')
> +with_amd_vk = _vulkan_drivers.contains('amd')
> +with_any_vk = with_intel_vk or with_amd_vk

Same comment as the last patch.

>  
>  if with_dri_swrast and (with_gallium_softpipe or with_gallium_swr)
>error('Only one swrast provider can be built')
> -- 
> Cheers,
>   Eric
> 


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Re: [Mesa-dev] [PATCH mesa 2/5] meson: fix gallium-drivers=[]

[Dylan Baker]

Quoting Eric Engestrom (2018-05-11 07:12:27)
> Fixes: 5608d0a2cee47c7d037f ("meson: use array type options")
> Signed-off-by: Eric Engestrom 
> ---
>  meson.build | 73 +++--
>  1 file changed, 32 insertions(+), 41 deletions(-)
> 
> diff --git a/meson.build b/meson.build
> index afebfd2c65fdb22dae29..6b069ae5dfc52adba1b7 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -123,23 +123,6 @@ with_dri = (with_dri_i915 or with_dri_i965 or
> with_dri_r100 or with_dri_r200 or
> with_dri_nouveau or with_dri_swrast)
>  
> -with_gallium = false
> -with_gallium_pl111 = false
> -with_gallium_radeonsi = false
> -with_gallium_r300 = false
> -with_gallium_r600 = false
> -with_gallium_nouveau = false
> -with_gallium_freedreno = false
> -with_gallium_softpipe = false
> -with_gallium_vc4 = false
> -with_gallium_vc5 = false
> -with_gallium_etnaviv = false
> -with_gallium_imx = false
> -with_gallium_tegra = false
> -with_gallium_i915 = false
> -with_gallium_svga = false
> -with_gallium_virgl = false
> -with_gallium_swr = false
>  _drivers = get_option('gallium-drivers')
>  if _drivers.contains('auto')
>if system_has_kms_drm
> @@ -162,30 +145,38 @@ if _drivers.contains('auto')
>  error('Unknown OS. Please pass -Dgallium-drivers to set driver options. 
> Patches gladly accepted to fix this.')
>endif
>  endif
> -if _drivers != ['']
> -  with_gallium_pl111 = _drivers.contains('pl111')
> -  with_gallium_radeonsi = _drivers.contains('radeonsi')
> -  with_gallium_r300 = _drivers.contains('r300')
> -  with_gallium_r600 = _drivers.contains('r600')
> -  with_gallium_nouveau = _drivers.contains('nouveau')
> -  with_gallium_freedreno = _drivers.contains('freedreno')
> -  with_gallium_softpipe = _drivers.contains('swrast')
> -  with_gallium_vc4 = _drivers.contains('vc4')
> -  with_gallium_vc5 = _drivers.contains('vc5')
> -  with_gallium_etnaviv = _drivers.contains('etnaviv')
> -  with_gallium_imx = _drivers.contains('imx')
> -  with_gallium_tegra = _drivers.contains('tegra')
> -  with_gallium_i915 = _drivers.contains('i915')
> -  with_gallium_svga = _drivers.contains('svga')
> -  with_gallium_virgl = _drivers.contains('virgl')
> -  with_gallium_swr = _drivers.contains('swr')
> -  with_gallium = true
> -  if system_has_kms_drm
> -_glx = get_option('glx')
> -_egl = get_option('egl')
> -if _glx == 'dri' or _egl == 'true' or (_glx == 'disabled' and _egl != 
> 'false')
> -  with_dri = true
> -endif
> +
> +with_gallium_pl111 = _drivers.contains('pl111')
> +with_gallium_radeonsi = _drivers.contains('radeonsi')
> +with_gallium_r300 = _drivers.contains('r300')
> +with_gallium_r600 = _drivers.contains('r600')
> +with_gallium_nouveau = _drivers.contains('nouveau')
> +with_gallium_freedreno = _drivers.contains('freedreno')
> +with_gallium_softpipe = _drivers.contains('swrast')
> +with_gallium_vc4 = _drivers.contains('vc4')
> +with_gallium_vc5 = _drivers.contains('vc5')
> +with_gallium_etnaviv = _drivers.contains('etnaviv')
> +with_gallium_imx = _drivers.contains('imx')
> +with_gallium_tegra = _drivers.contains('tegra')
> +with_gallium_i915 = _drivers.contains('i915')
> +with_gallium_svga = _drivers.contains('svga')
> +with_gallium_virgl = _drivers.contains('virgl')
> +with_gallium_swr = _drivers.contains('swr')
> +
> +with_gallium = (with_gallium_pl111 or with_gallium_radeonsi or
> +with_gallium_r300 or with_gallium_r600 or
> +with_gallium_nouveau or with_gallium_freedreno or
> +with_gallium_softpipe or with_gallium_vc4 or
> +with_gallium_vc5 or with_gallium_etnaviv or
> +with_gallium_imx or with_gallium_tegra or
> +with_gallium_i915 or with_gallium_svga or
> +with_gallium_virgl or with_gallium_swr)

This could be simplified to this, right?
with_gallium = _drivers != ['']

Dylan


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Re: [Mesa-dev] [PATCH mesa] meson: remove dependency antipattern

[Dylan Baker]

Reviewed-by: Dylan Baker 

Quoting Eric Engestrom (2018-05-11 06:56:13)
> `dep_valgrind != []` now (0.45) produces a warning that is quite explicit:
>   WARNING: Trying to compare values of different types (DependencyHolder, 
> list) using !=.
>   The result of this is undefined and will become a hard error in a future 
> Meson release.
> 
> `dep_valgrind = []` used to be the recommended way to deal with
> non-existant dependency, but these don't work with `.found()`, so now
> the recommended way is to declare a impossible dependency, which
> null_dep does for us in Mesa.
> 
> In short, we don't need and shouldn't check for `!= []` anywhere anymore.
> 
> Signed-off-by: Eric Engestrom 
> ---
>  src/compiler/glsl/glcpp/meson.build | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/compiler/glsl/glcpp/meson.build 
> b/src/compiler/glsl/glcpp/meson.build
> index e6a3dc86753d9485c450..09d44ddd68777bca8029 100644
> --- a/src/compiler/glsl/glcpp/meson.build
> +++ b/src/compiler/glsl/glcpp/meson.build
> @@ -57,7 +57,7 @@ glcpp = executable(
>  
>  if with_tests
>modes = ['unix', 'windows', 'oldmac', 'bizarro']
> -  if dep_valgrind != [] and dep_valgrind.found()
> +  if dep_valgrind.found()
>  modes += ['valgrind']
>endif
>  
> -- 
> Cheers,
>   Eric
> 


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Re: [Mesa-dev] [PATCH 3/4] i965/drm: Searching for a cached buffer for reuse

[James Xiong]

On Thu, 10 May 2018 13:56:12 -0700
Kenneth Graunke  wrote:

> On Friday, May 4, 2018 5:56:04 PM PDT James Xiong wrote:
> > From: "Xiong, James" 
> > 
> > Now that a bucket contains cached buffers with different sizes, go
> > through its list and search for a cached buffer with enough size.
> > 
> > Signed-off-by: Xiong, James 
> > ---
> >  src/mesa/drivers/dri/i965/brw_bufmgr.c | 21 +++--
> >  src/util/list.h|  5 +
> >  2 files changed, 20 insertions(+), 6 deletions(-)
> > 
> > diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
> > b/src/mesa/drivers/dri/i965/brw_bufmgr.c index 6a9b005..5235aa6
> > 100644 --- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
> > +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
> > @@ -281,7 +281,7 @@ cached_bo_for_size(struct brw_bufmgr *bufmgr,
> > assert(!(busy && zeroed));
> >  
> > if(bucket != NULL && !list_empty(>head)) {
> > -  struct brw_bo *bo;
> > +  struct brw_bo *bo, *temp_bo;
> >  retry:
> >bo = NULL;
> >  
> > @@ -292,8 +292,13 @@ retry:
> >* asked us to zero the buffer, we don't want this
> >* because we are going to mmap it.
> >*/
> > - bo = LIST_ENTRY(struct brw_bo, bucket->head.prev, head);
> > - list_del(>head);
> > + LIST_FOR_EACH_ENTRY_REV(temp_bo, >head, head) {
> > +if (temp_bo->size >= size) {
> > +   bo = temp_bo;
> > +   list_del(>head);
> > +   break;
> > +}
> > + }
> >} else {
> >   /* For non-render-target BOs (where we're probably
> >* going to map it first thing in order to fill it
> > @@ -302,9 +307,13 @@ retry:
> >* allocating a new buffer is probably faster than
> >* waiting for the GPU to finish.
> >*/
> > - bo = LIST_ENTRY(struct brw_bo, bucket->head.next, head);
> > - if (!brw_bo_busy(bo)) {
> > -list_del(>head);
> > + LIST_FOR_EACH_ENTRY(temp_bo, >head, head) {
> > +if (temp_bo->size >= size &&
> > +!brw_bo_busy(temp_bo)) {
> > +   bo = temp_bo;
> > +   list_del(>head);
> > +   break;
> > +}
> >   }
> >}
> >  
> > diff --git a/src/util/list.h b/src/util/list.h
> > index 6edb750..9362072 100644
> > --- a/src/util/list.h
> > +++ b/src/util/list.h
> > @@ -189,6 +189,11 @@ static inline void list_validate(struct
> > list_head *list) >member !=
> > (head); \ pos =
> > container_of(pos->member.next, pos, member)) 
> > +#define LIST_FOR_EACH_ENTRY_REV(pos, head,
> > member)  \
> > +   for (pos = NULL, pos = container_of((head)->prev, pos,
> > member);  \
> > +>member !=
> > (head); \
> > +pos = container_of(pos->member.prev, pos, member))
> > +
> >  #define LIST_FOR_EACH_ENTRY_SAFE(pos, storage, head,
> > member) \ for (pos = NULL, pos = container_of((head)->next,
> > pos, member),   \ storage = container_of(pos->member.next,
> > pos, member);   \ 
> 
> Hi James,
> 
> I don't particularly like the idea of introducing linear linked list
> walks to find a buffer.  It's a really nice property to have every
> buffer in the bucket be suitable and be able to grab one immediately.
> It sounds like purging things more often in patch 4 reduces the cost
> of this new list walk, but...it'd be nice to not add it in the first
> place.
Yes, the purge, as well as the cleanup routine which kicks in from time
to time and removes any cached buffers freed 1+ second ago, keeps the
list short. One thing I could think of is to have a fixed size cached
buffer array so that we could use a binary search instead of walks of
the double-linked list.
> 
> This also conflicts with my new VMA allocator approach a lot, which
> assumes that all buffers in a bucket are the same size...
Yes.
> 
> Still, you've shown some pretty nice memory savings.  Scott and I were
> wondering if it would be possible to achieve a similar effect by
> tuning the bucket sizes - either adding more, or adjusting some.  The
> sizes we have are pretty arbitrary - we started with powers of two,
> and then added more intermediate sizes back in 2010 to reduce memory
> waste.
I think it will work, the memory saving will be somewhere between
depends on how many buckets we have, the more buckets the less size
gap between buckets and more memory saving, the thing is we will have to
walk the bucket list now.
> 
> For example, 1920x1080 RGBA Y-tiled buffers are going to be really
> common, and should be 8,355,840 bytes...but the nearest bucket size is
> 8,388,608, so we waste 32KB.  We might want to make sure there's a
> bucket at that exact size.
Yes, but the tiling, pitch and height alignments might change for
example a new 

Re: [Mesa-dev] [Intel-gfx] [PATCH] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk

[Michel Thierry]

On 5/11/2018 5:43 AM, Mika Kuoppala wrote:

Chris Wilson  writes:


Quoting Mika Kuoppala (2018-05-11 10:56:49)

Michel Thierry  writes:


Factor in clear values wherever required while updating destination
min/max.

References: HSDES#160184
Signed-off-by: Michel Thierry 
Cc: mesa-dev@lists.freedesktop.org
Cc: Mika Kuoppala 
Cc: Oscar Mateo 


Reviewed-by: Mika Kuoppala 


Cc: stable?


Yes, we should.



I think so too, although stable doesn't have the workaround refactoring 
yet, the change will be in intel_engine_cs.c instead.



-Mika


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Re: [Mesa-dev] [Intel-gfx] [PATCH] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk

[Mika Kuoppala]

Chris Wilson  writes:

> Quoting Mika Kuoppala (2018-05-11 10:56:49)
>> Michel Thierry  writes:
>> 
>> > Factor in clear values wherever required while updating destination
>> > min/max.
>> >
>> > References: HSDES#160184
>> > Signed-off-by: Michel Thierry 
>> > Cc: mesa-dev@lists.freedesktop.org
>> > Cc: Mika Kuoppala 
>> > Cc: Oscar Mateo 
>> 
>> Reviewed-by: Mika Kuoppala 
>
> Cc: stable?

Yes, we should.

-Mika

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Re: [Mesa-dev] meson: Fix build for egl platform_x11 with dri3

[Ville Syrjälä]

On Fri, May 11, 2018 at 03:26:57PM +0100, Eric Engestrom wrote:
> On Monday, 2018-05-07 20:05:40 +0300, Ville Syrjälä wrote:
> > From: Ville Syrjälä 
> > 
> > platform_x11 with dri3 needs inc_loader.
> > 
> > In file included from ../src/egl/drivers/dri2/platform_x11_dri3.c:35:0:
> > ../src/egl/drivers/dri2/egl_dri2.h:41:32: fatal error: 
> > loader_dri3_helper.h: No such file or directory
> > In file included from ../src/egl/drivers/dri2/platform_x11.c:46:0:
> > ../src/egl/drivers/dri2/egl_dri2.h:41:32: fatal error: 
> > loader_dri3_helper.h: No such file or directory
> > In file included from ../src/egl/drivers/dri2/egl_dri2.c:61:0:
> > ../src/egl/drivers/dri2/egl_dri2.h:41:32: fatal error: 
> > loader_dri3_helper.h: No such file or directory
> > 
> > Cc: Dylan Baker 
> > Signed-off-by: Ville Syrjälä 
> 
> Reviewed-by: Eric Engestrom 

Thanks. Pushed to master.

> 
> > ---
> >  src/egl/meson.build | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/src/egl/meson.build b/src/egl/meson.build
> > index 6537e4bdee61..9050d763a6cd 100644
> > --- a/src/egl/meson.build
> > +++ b/src/egl/meson.build
> > @@ -102,6 +102,7 @@ if with_platform_x11
> >if with_dri3
> >  files_egl += files('drivers/dri2/platform_x11_dri3.c')
> >  link_for_egl += libloader_dri3_helper
> > +incs_for_egl += inc_loader
> >endif
> >deps_for_egl += [dep_x11_xcb, dep_xcb_dri2, dep_xcb_xfixes]
> >  endif

-- 
Ville Syrjälä
Intel
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[Mesa-dev] [PATCH 1/2] radv: allow to dump the GS copy shader with RADV_DEBUG="shaders"

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_pipeline.c | 2 +-
 src/amd/vulkan/radv_shader.c   | 2 +-
 src/amd/vulkan/radv_shader.h   | 9 ++---
 3 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index b4e4f3211e2..4a2b16fdf68 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1976,7 +1976,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
radv_link_shaders(pipeline, nir);
 
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
-   if (modules[i] && radv_can_dump_shader(device, modules[i]))
+   if (modules[i] && radv_can_dump_shader(device, modules[i], 
false))
nir_print_shader(nir[i], stderr);
}
 
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index cdd4142f291..24ece0974a7 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -488,7 +488,7 @@ shader_variant_create(struct radv_device *device,
 
options->family = chip_family;
options->chip_class = device->physical_device->rad_info.chip_class;
-   options->dump_shader = radv_can_dump_shader(device, module);
+   options->dump_shader = radv_can_dump_shader(device, module, 
gs_copy_shader);
options->dump_preoptir = options->dump_shader &&
 device->instance->debug_flags & 
RADV_DEBUG_PREOPTIR;
options->record_llvm_ir = device->keep_shader_info;
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index c7e261c5ca7..7c9aed64378 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -350,11 +350,14 @@ radv_shader_dump_stats(struct radv_device *device,
 
 static inline bool
 radv_can_dump_shader(struct radv_device *device,
-struct radv_shader_module *module)
+struct radv_shader_module *module,
+bool is_gs_copy_shader)
 {
+   if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
+   return false;
+
/* Only dump non-meta shaders, useful for debugging purposes. */
-   return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS &&
-  module && !module->nir;
+   return (module && !module->nir) || is_gs_copy_shader;
 }
 
 static inline bool
-- 
2.17.0

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[Mesa-dev] [PATCH 2/2] radv: remove useless check in radv_create_shaders()

[Samuel Pitoiset]

radv_can_dump_shader() already handles if module is NULL.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_pipeline.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 4a2b16fdf68..c48a552ae4c 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1976,7 +1976,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
radv_link_shaders(pipeline, nir);
 
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
-   if (modules[i] && radv_can_dump_shader(device, modules[i], 
false))
+   if (radv_can_dump_shader(device, modules[i], false))
nir_print_shader(nir[i], stderr);
}
 
-- 
2.17.0

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[Mesa-dev] [PATCH mesa 4/5] meson: fix platforms=[]

[Eric Engestrom]

Fixes: 5608d0a2cee47c7d037f ("meson: use array type options")
Signed-off-by: Eric Engestrom 
---
 meson.build | 26 +++---
 1 file changed, 11 insertions(+), 15 deletions(-)

diff --git a/meson.build b/meson.build
index a8999f37bd06a84cf7c0..5dd5168eb95dc823bbbe 100644
--- a/meson.build
+++ b/meson.build
@@ -231,12 +231,6 @@ else
   with_dri_platform = 'none'
 endif
 
-with_platform_android = false
-with_platform_wayland = false
-with_platform_x11 = false
-with_platform_drm = false
-with_platform_surfaceless = false
-egl_native_platform = ''
 _platforms = get_option('platforms')
 if _platforms.contains('auto')
   if system_has_kms_drm
@@ -249,13 +243,15 @@ if _platforms.contains('auto')
 error('Unknown OS. Please pass -Dplatforms to set platforms. Patches 
gladly accepted to fix this.')
   endif
 endif
-if _platforms != ['']
-  with_platform_android = _platforms.contains('android')
-  with_platform_x11 = _platforms.contains('x11')
-  with_platform_wayland = _platforms.contains('wayland')
-  with_platform_drm = _platforms.contains('drm')
-  with_platform_haiku = _platforms.contains('haiku')
-  with_platform_surfaceless = _platforms.contains('surfaceless')
+
+with_platform_android = _platforms.contains('android')
+with_platform_x11 = _platforms.contains('x11')
+with_platform_wayland = _platforms.contains('wayland')
+with_platform_drm = _platforms.contains('drm')
+with_platform_haiku = _platforms.contains('haiku')
+with_platform_surfaceless = _platforms.contains('surfaceless')
+
+if _platforms.length() != 0
   egl_native_platform = _platforms[0]
 endif
 
@@ -298,13 +294,13 @@ endif
 
 _egl = get_option('egl')
 if _egl == 'auto'
-  with_egl = with_dri and with_shared_glapi and egl_native_platform != ''
+  with_egl = with_dri and with_shared_glapi and _platforms.length() != 0
 elif _egl == 'true'
   if not with_dri
 error('EGL requires dri')
   elif not with_shared_glapi
 error('EGL requires shared-glapi')
-  elif egl_native_platform == ''
+  elif _platforms.length() == 0
 error('No platforms specified, consider -Dplatforms=drm,x11 at least')
   elif not ['disabled', 'dri'].contains(with_glx)
 error('EGL requires dri, but a GLX is being built without dri')
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa 3/5] meson: fix vulkan-drivers=[]

[Eric Engestrom]

Fixes: 5608d0a2cee47c7d037f ("meson: use array type options")
Signed-off-by: Eric Engestrom 
---
 meson.build | 12 
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/meson.build b/meson.build
index 6b069ae5dfc52adba1b7..a8999f37bd06a84cf7c0 100644
--- a/meson.build
+++ b/meson.build
@@ -180,9 +180,6 @@ if with_gallium and system_has_kms_drm
   endif
 endif
 
-with_intel_vk = false
-with_amd_vk = false
-with_any_vk = false
 _vulkan_drivers = get_option('vulkan-drivers')
 if _vulkan_drivers.contains('auto')
   if system_has_kms_drm
@@ -198,11 +195,10 @@ if _vulkan_drivers.contains('auto')
 error('Unknown OS. Please pass -Dvulkan-drivers to set driver options. 
Patches gladly accepted to fix this.')
   endif
 endif
-if _vulkan_drivers != ['']
-  with_intel_vk = _vulkan_drivers.contains('intel')
-  with_amd_vk = _vulkan_drivers.contains('amd')
-  with_any_vk = true
-endif
+
+with_intel_vk = _vulkan_drivers.contains('intel')
+with_amd_vk = _vulkan_drivers.contains('amd')
+with_any_vk = with_intel_vk or with_amd_vk
 
 if with_dri_swrast and (with_gallium_softpipe or with_gallium_swr)
   error('Only one swrast provider can be built')
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa 5/5] meson: drop unused empty string array element

[Eric Engestrom]

Signed-off-by: Eric Engestrom 
---
 meson.build | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/meson.build b/meson.build
index 5dd5168eb95dc823bbbe..bd48e343d30c1024c104 100644
--- a/meson.build
+++ b/meson.build
@@ -100,13 +100,13 @@ if _drivers.contains('auto')
 if ['x86', 'x86_64'].contains(host_machine.cpu_family())
   _drivers = ['i915', 'i965', 'r100', 'r200', 'nouveau']
 elif ['arm', 'aarch64'].contains(host_machine.cpu_family())
-  _drivers = ['']
+  _drivers = []
 else
   error('Unknown architecture. Please pass -Ddri-drivers to set driver 
options. Patches gladly accepted to fix this.')
 endif
   elif ['darwin', 'windows', 'cygwin', 'haiku'].contains(host_machine.system())
 # only swrast would make sense here, but gallium swrast is a much better 
default
-_drivers = ['']
+_drivers = []
   else
 error('Unknown OS. Please pass -Ddri-drivers to set driver options. 
Patches gladly accepted to fix this.')
   endif
@@ -190,7 +190,7 @@ if _vulkan_drivers.contains('auto')
 endif
   elif ['darwin', 'windows', 'cygwin', 'haiku'].contains(host_machine.system())
 # No vulkan driver supports windows or macOS currently
-_vulkan_drivers = ['']
+_vulkan_drivers = []
   else
 error('Unknown OS. Please pass -Dvulkan-drivers to set driver options. 
Patches gladly accepted to fix this.')
   endif
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa 2/5] meson: fix gallium-drivers=[]

[Eric Engestrom]

Fixes: 5608d0a2cee47c7d037f ("meson: use array type options")
Signed-off-by: Eric Engestrom 
---
 meson.build | 73 +++--
 1 file changed, 32 insertions(+), 41 deletions(-)

diff --git a/meson.build b/meson.build
index afebfd2c65fdb22dae29..6b069ae5dfc52adba1b7 100644
--- a/meson.build
+++ b/meson.build
@@ -123,23 +123,6 @@ with_dri = (with_dri_i915 or with_dri_i965 or
with_dri_r100 or with_dri_r200 or
with_dri_nouveau or with_dri_swrast)
 
-with_gallium = false
-with_gallium_pl111 = false
-with_gallium_radeonsi = false
-with_gallium_r300 = false
-with_gallium_r600 = false
-with_gallium_nouveau = false
-with_gallium_freedreno = false
-with_gallium_softpipe = false
-with_gallium_vc4 = false
-with_gallium_vc5 = false
-with_gallium_etnaviv = false
-with_gallium_imx = false
-with_gallium_tegra = false
-with_gallium_i915 = false
-with_gallium_svga = false
-with_gallium_virgl = false
-with_gallium_swr = false
 _drivers = get_option('gallium-drivers')
 if _drivers.contains('auto')
   if system_has_kms_drm
@@ -162,30 +145,38 @@ if _drivers.contains('auto')
 error('Unknown OS. Please pass -Dgallium-drivers to set driver options. 
Patches gladly accepted to fix this.')
   endif
 endif
-if _drivers != ['']
-  with_gallium_pl111 = _drivers.contains('pl111')
-  with_gallium_radeonsi = _drivers.contains('radeonsi')
-  with_gallium_r300 = _drivers.contains('r300')
-  with_gallium_r600 = _drivers.contains('r600')
-  with_gallium_nouveau = _drivers.contains('nouveau')
-  with_gallium_freedreno = _drivers.contains('freedreno')
-  with_gallium_softpipe = _drivers.contains('swrast')
-  with_gallium_vc4 = _drivers.contains('vc4')
-  with_gallium_vc5 = _drivers.contains('vc5')
-  with_gallium_etnaviv = _drivers.contains('etnaviv')
-  with_gallium_imx = _drivers.contains('imx')
-  with_gallium_tegra = _drivers.contains('tegra')
-  with_gallium_i915 = _drivers.contains('i915')
-  with_gallium_svga = _drivers.contains('svga')
-  with_gallium_virgl = _drivers.contains('virgl')
-  with_gallium_swr = _drivers.contains('swr')
-  with_gallium = true
-  if system_has_kms_drm
-_glx = get_option('glx')
-_egl = get_option('egl')
-if _glx == 'dri' or _egl == 'true' or (_glx == 'disabled' and _egl != 
'false')
-  with_dri = true
-endif
+
+with_gallium_pl111 = _drivers.contains('pl111')
+with_gallium_radeonsi = _drivers.contains('radeonsi')
+with_gallium_r300 = _drivers.contains('r300')
+with_gallium_r600 = _drivers.contains('r600')
+with_gallium_nouveau = _drivers.contains('nouveau')
+with_gallium_freedreno = _drivers.contains('freedreno')
+with_gallium_softpipe = _drivers.contains('swrast')
+with_gallium_vc4 = _drivers.contains('vc4')
+with_gallium_vc5 = _drivers.contains('vc5')
+with_gallium_etnaviv = _drivers.contains('etnaviv')
+with_gallium_imx = _drivers.contains('imx')
+with_gallium_tegra = _drivers.contains('tegra')
+with_gallium_i915 = _drivers.contains('i915')
+with_gallium_svga = _drivers.contains('svga')
+with_gallium_virgl = _drivers.contains('virgl')
+with_gallium_swr = _drivers.contains('swr')
+
+with_gallium = (with_gallium_pl111 or with_gallium_radeonsi or
+with_gallium_r300 or with_gallium_r600 or
+with_gallium_nouveau or with_gallium_freedreno or
+with_gallium_softpipe or with_gallium_vc4 or
+with_gallium_vc5 or with_gallium_etnaviv or
+with_gallium_imx or with_gallium_tegra or
+with_gallium_i915 or with_gallium_svga or
+with_gallium_virgl or with_gallium_swr)
+
+if with_gallium and system_has_kms_drm
+  _glx = get_option('glx')
+  _egl = get_option('egl')
+  if _glx == 'dri' or _egl == 'true' or (_glx == 'disabled' and _egl != 
'false')
+with_dri = true
   endif
 endif
 
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa 0/5] meson: fix empty array options

[Eric Engestrom]

I'm guessing these were tested using `-D platforms=`, which actually sets
the array to contain 1 element, an empty string.

Rework the code to handle both that, and emptying the array (`-D platforms=[]`).


Eric Engestrom (5):
  meson: fix dri-drivers=[]
  meson: fix gallium-drivers=[]
  meson: fix vulkan-drivers=[]
  meson: fix platforms=[]
  meson: drop unused empty string array element

 meson.build | 144 ++--
 1 file changed, 61 insertions(+), 83 deletions(-)

-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa 1/5] meson: fix dri-drivers=[]

[Eric Engestrom]

Fixes: 5608d0a2cee47c7d037f ("meson: use array type options")
Signed-off-by: Eric Engestrom 
---
 meson.build | 27 +++
 1 file changed, 11 insertions(+), 16 deletions(-)

diff --git a/meson.build b/meson.build
index e52b4a51093247bef95a..afebfd2c65fdb22dae29 100644
--- a/meson.build
+++ b/meson.build
@@ -93,13 +93,6 @@ endif
 
 system_has_kms_drm = ['openbsd', 'netbsd', 'freebsd', 'dragonfly', 
'linux'].contains(host_machine.system())
 
-with_dri = false
-with_dri_i915 = false
-with_dri_i965 = false
-with_dri_r100 = false
-with_dri_r200 = false
-with_dri_nouveau = false
-with_dri_swrast = false
 _drivers = get_option('dri-drivers')
 if _drivers.contains('auto')
   if system_has_kms_drm
@@ -118,15 +111,17 @@ if _drivers.contains('auto')
 error('Unknown OS. Please pass -Ddri-drivers to set driver options. 
Patches gladly accepted to fix this.')
   endif
 endif
-if _drivers != ['']
-  with_dri_i915 = _drivers.contains('i915')
-  with_dri_i965 = _drivers.contains('i965')
-  with_dri_r100 = _drivers.contains('r100')
-  with_dri_r200 = _drivers.contains('r200')
-  with_dri_nouveau = _drivers.contains('nouveau')
-  with_dri_swrast = _drivers.contains('swrast')
-  with_dri = true
-endif
+
+with_dri_i915 = _drivers.contains('i915')
+with_dri_i965 = _drivers.contains('i965')
+with_dri_r100 = _drivers.contains('r100')
+with_dri_r200 = _drivers.contains('r200')
+with_dri_nouveau = _drivers.contains('nouveau')
+with_dri_swrast = _drivers.contains('swrast')
+
+with_dri = (with_dri_i915 or with_dri_i965 or
+   with_dri_r100 or with_dri_r200 or
+   with_dri_nouveau or with_dri_swrast)
 
 with_gallium = false
 with_gallium_pl111 = false
-- 
Cheers,
  Eric

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Re: [Mesa-dev] meson: Fix build for egl platform_x11 with dri3

[Eric Engestrom]

On Monday, 2018-05-07 20:05:40 +0300, Ville Syrjälä wrote:
> From: Ville Syrjälä 
> 
> platform_x11 with dri3 needs inc_loader.
> 
> In file included from ../src/egl/drivers/dri2/platform_x11_dri3.c:35:0:
> ../src/egl/drivers/dri2/egl_dri2.h:41:32: fatal error: loader_dri3_helper.h: 
> No such file or directory
> In file included from ../src/egl/drivers/dri2/platform_x11.c:46:0:
> ../src/egl/drivers/dri2/egl_dri2.h:41:32: fatal error: loader_dri3_helper.h: 
> No such file or directory
> In file included from ../src/egl/drivers/dri2/egl_dri2.c:61:0:
> ../src/egl/drivers/dri2/egl_dri2.h:41:32: fatal error: loader_dri3_helper.h: 
> No such file or directory
> 
> Cc: Dylan Baker 
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Eric Engestrom 

> ---
>  src/egl/meson.build | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/src/egl/meson.build b/src/egl/meson.build
> index 6537e4bdee61..9050d763a6cd 100644
> --- a/src/egl/meson.build
> +++ b/src/egl/meson.build
> @@ -102,6 +102,7 @@ if with_platform_x11
>if with_dri3
>  files_egl += files('drivers/dri2/platform_x11_dri3.c')
>  link_for_egl += libloader_dri3_helper
> +incs_for_egl += inc_loader
>endif
>deps_for_egl += [dep_x11_xcb, dep_xcb_dri2, dep_xcb_xfixes]
>  endif
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[Mesa-dev] [PATCH mesa] meson: remove dependency antipattern

[Eric Engestrom]

`dep_valgrind != []` now (0.45) produces a warning that is quite explicit:
  WARNING: Trying to compare values of different types (DependencyHolder, list) 
using !=.
  The result of this is undefined and will become a hard error in a future 
Meson release.

`dep_valgrind = []` used to be the recommended way to deal with
non-existant dependency, but these don't work with `.found()`, so now
the recommended way is to declare a impossible dependency, which
null_dep does for us in Mesa.

In short, we don't need and shouldn't check for `!= []` anywhere anymore.

Signed-off-by: Eric Engestrom 
---
 src/compiler/glsl/glcpp/meson.build | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/glsl/glcpp/meson.build 
b/src/compiler/glsl/glcpp/meson.build
index e6a3dc86753d9485c450..09d44ddd68777bca8029 100644
--- a/src/compiler/glsl/glcpp/meson.build
+++ b/src/compiler/glsl/glcpp/meson.build
@@ -57,7 +57,7 @@ glcpp = executable(
 
 if with_tests
   modes = ['unix', 'windows', 'oldmac', 'bizarro']
-  if dep_valgrind != [] and dep_valgrind.found()
+  if dep_valgrind.found()
 modes += ['valgrind']
   endif
 
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH 0/3] egl/android: Remove dependencies on specific grallocs

[Robert Foss]

This series replaces the dependency on
GRALLOC_MODULE_PERFORM_GET_DRM_FD with DRM node
probing and disables the support for drm_gralloc.

The series has been tested on Qemu+AOSP, where a
virtio gpu was successfully probed for and
opened.

This however required adding support in libdrm
for virtio gpus, and virtio buses. An initial
patch for this can be found here:

https://gitlab.collabora.com/robertfoss/libdrm/tree/virtio_rfc

Changes since v1:
 - Added fix for build issue
 - Do not rely on libdrm for probing
 - Distinguish between errors and when no drm devices are found

Changes since RFC:
 - Rebased work on the libdrm patch [2].
 - Included patch from Rob Herring disabling drm_gralloc/flink
   support by default.
 - Added device handler driver probing.


Rob Herring (1):
  egl/android: #ifdef out flink name support

Robert Foss (2):
  gallium/util: Fix build error due to cast to different size
  egl/android: Add DRM node probing and filtering

 src/egl/Android.mk|   6 +-
 src/egl/drivers/dri2/egl_dri2.h   |   2 -
 src/egl/drivers/dri2/platform_android.c   | 206 ++
 .../auxiliary/util/u_debug_stack_android.cpp  |   4 +-
 4 files changed, 174 insertions(+), 44 deletions(-)

-- 
2.17.0

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[Mesa-dev] [PATCH 2/3] egl/android: #ifdef out flink name support

[Robert Foss]

From: Rob Herring 

Maintaining both flink names and prime fd support which are provided by
2 different gralloc implementations is problematic because we have a
dependency on a specific gralloc implementation header.

This mostly disables the dependency on the gralloc implementation and
headers. The dependency on GRALLOC_MODULE_PERFORM_GET_DRM_FD remains for
now, but the definition is added locally to remove the header
dependency.

drm_gralloc support can be enabled by setting
BOARD_USES_DRM_GRALLOC=true in BoardConfig.mk.

Signed-off-by: Rob Herring 
Signed-off-by: Robert Foss 
---
Changes since RFC:
 - Instead of removing code, #ifdef it out.

 src/egl/Android.mk  |  6 ++-
 src/egl/drivers/dri2/egl_dri2.h |  2 -
 src/egl/drivers/dri2/platform_android.c | 56 +++--
 3 files changed, 49 insertions(+), 15 deletions(-)

diff --git a/src/egl/Android.mk b/src/egl/Android.mk
index 11818694f4..8412aeb798 100644
--- a/src/egl/Android.mk
+++ b/src/egl/Android.mk
@@ -57,9 +57,13 @@ LOCAL_SHARED_LIBRARIES := \
libhardware \
liblog \
libcutils \
-   libgralloc_drm \
libsync
 
+ifeq ($(BOARD_USES_DRM_GRALLOC),true)
+   LOCAL_CFLAGS += -DHAVE_DRM_GRALLOC
+   LOCAL_SHARED_LIBRARIES += libgralloc_drm
+endif
+
 ifeq ($(filter $(MESA_ANDROID_MAJOR_VERSION), 4 5 6 7),)
 LOCAL_SHARED_LIBRARIES += libnativewindow
 endif
diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
index adabc527f8..5d8fbfa235 100644
--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -67,8 +67,6 @@ struct zwp_linux_dmabuf_v1;
 
 #include 
 #include 
-#include 
-
 #endif /* HAVE_ANDROID_PLATFORM */
 
 #include "eglconfig.h"
diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index 1d6ed92bd6..4ba96aad90 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -37,7 +37,11 @@
 #include "loader.h"
 #include "egl_dri2.h"
 #include "egl_dri2_fallbacks.h"
+
+#ifdef HAVE_DRM_GRALLOC
+#include 
 #include "gralloc_drm.h"
+#endif /* HAVE_DRM_GRALLOC */
 
 #define ALIGN(val, align)  (((val) + (align) - 1) & ~((align) - 1))
 
@@ -164,11 +168,13 @@ get_native_buffer_fd(struct ANativeWindowBuffer *buf)
return (handle && handle->numFds) ? handle->data[0] : -1;
 }
 
+#ifdef HAVE_DRM_GRALLOC
 static int
 get_native_buffer_name(struct ANativeWindowBuffer *buf)
 {
return gralloc_drm_get_gem_handle(buf->handle);
 }
+#endif /* HAVE_DRM_GRALLOC */
 
 static EGLBoolean
 droid_window_dequeue_buffer(struct dri2_egl_surface *dri2_surf)
@@ -838,6 +844,7 @@ droid_create_image_from_prime_fd(_EGLDisplay *disp, 
_EGLContext *ctx,
return dri2_create_image_dma_buf(disp, ctx, NULL, attr_list);
 }
 
+#ifdef HAVE_DRM_GRALLOC
 static _EGLImage *
 droid_create_image_from_name(_EGLDisplay *disp, _EGLContext *ctx,
  struct ANativeWindowBuffer *buf)
@@ -881,6 +888,7 @@ droid_create_image_from_name(_EGLDisplay *disp, _EGLContext 
*ctx,
 
return _img->base;
 }
+#endif /* HAVE_DRM_GRALLOC */
 
 static EGLBoolean
 droid_query_surface(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSurface *surf,
@@ -937,7 +945,11 @@ dri2_create_image_android_native_buffer(_EGLDisplay *disp,
if (fd >= 0)
   return droid_create_image_from_prime_fd(disp, ctx, buf, fd);
 
+#ifdef HAVE_DRM_GRALLOC
return droid_create_image_from_name(disp, ctx, buf);
+#else
+   return NULL;
+#endif
 }
 
 static _EGLImage *
@@ -959,6 +971,7 @@ droid_flush_front_buffer(__DRIdrawable * driDrawable, void 
*loaderPrivate)
 {
 }
 
+#ifdef HAVE_DRM_GRALLOC
 static int
 droid_get_buffers_parse_attachments(struct dri2_egl_surface *dri2_surf,
 unsigned int *attachments, int count)
@@ -1034,6 +1047,7 @@ droid_get_buffers_with_format(__DRIdrawable * driDrawable,
 
return dri2_surf->buffers;
 }
+#endif /* HAVE_DRM_GRALLOC */
 
 static unsigned
 droid_get_capability(void *loaderPrivate, enum dri_loader_cap cap)
@@ -1116,6 +1130,14 @@ droid_add_configs_for_visuals(_EGLDriver *drv, 
_EGLDisplay *dpy)
return (config_count != 0);
 }
 
+enum {
+/* perform(const struct gralloc_module_t *mod,
+ * int op,
+ * int *fd);
+ */
+GRALLOC_MODULE_PERFORM_GET_DRM_FD = 0x4002,
+};
+
 static int
 droid_open_device(struct dri2_egl_display *dri2_dpy)
 {
@@ -1158,6 +1180,7 @@ static const struct dri2_egl_display_vtbl 
droid_display_vtbl = {
.get_dri_drawable = dri2_surface_get_dri_drawable,
 };
 
+#ifdef HAVE_DRM_GRALLOC
 static const __DRIdri2LoaderExtension droid_dri2_loader_extension = {
.base = { __DRI_DRI2_LOADER, 4 },
 
@@ -1166,6 +1189,7 @@ static const __DRIdri2LoaderExtension 
droid_dri2_loader_extension = {
.getBuffersWithFormat = droid_get_buffers_with_format,
.getCapability= 

[Mesa-dev] [PATCH 3/3] egl/android: Add DRM node probing and filtering

[Robert Foss]

This patch both adds support for probing & filtering DRM nodes
and switches away from using the GRALLOC_MODULE_PERFORM_GET_DRM_FD
gralloc call.

Currently the filtering is based just on the driver name,
and the desired name is supplied using the "drm.gpu.vendor_name"
Android property.

The filtering itself is done using the newly introduced
libdrm drmHandleMatch() call.

Signed-off-by: Robert Foss 
---
Changes since v1:
 - Do not rely on libdrm for probing
 - Distinguish between errors and when no drm devices are found

Changes since RFC:
 - Rebased on newer libdrm drmHandleMatch patch
 - Added support for driver probing

 src/egl/drivers/dri2/platform_android.c | 202 +---
 1 file changed, 149 insertions(+), 53 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index 4ba96aad90..76e5474e48 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -27,6 +27,7 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -1130,31 +1131,6 @@ droid_add_configs_for_visuals(_EGLDriver *drv, 
_EGLDisplay *dpy)
return (config_count != 0);
 }
 
-enum {
-/* perform(const struct gralloc_module_t *mod,
- * int op,
- * int *fd);
- */
-GRALLOC_MODULE_PERFORM_GET_DRM_FD = 0x4002,
-};
-
-static int
-droid_open_device(struct dri2_egl_display *dri2_dpy)
-{
-   int fd = -1, err = -EINVAL;
-
-   if (dri2_dpy->gralloc->perform)
- err = dri2_dpy->gralloc->perform(dri2_dpy->gralloc,
-  GRALLOC_MODULE_PERFORM_GET_DRM_FD,
-  );
-   if (err || fd < 0) {
-  _eglLog(_EGL_WARNING, "fail to get drm fd");
-  fd = -1;
-   }
-
-   return (fd >= 0) ? fcntl(fd, F_DUPFD_CLOEXEC, 3) : -1;
-}
-
 static const struct dri2_egl_display_vtbl droid_display_vtbl = {
.authenticate = NULL,
.create_window_surface = droid_create_window_surface,
@@ -1215,6 +1191,151 @@ static const __DRIextension 
*droid_image_loader_extensions[] = {
NULL,
 };
 
+EGLBoolean
+droid_load_driver(_EGLDisplay *disp)
+{
+   struct dri2_egl_display *dri2_dpy = disp->DriverData;
+   const char *err;
+
+   dri2_dpy->driver_name = loader_get_driver_for_fd(dri2_dpy->fd);
+   if (dri2_dpy->driver_name == NULL) {
+  err = "DRI2: failed to get driver name";
+  goto error;
+   }
+
+   dri2_dpy->is_render_node = drmGetNodeTypeFromFd(dri2_dpy->fd) == 
DRM_NODE_RENDER;
+
+   if (!dri2_dpy->is_render_node) {
+   #ifdef HAVE_DRM_GRALLOC
+   /* Handle control nodes using __DRI_DRI2_LOADER extension and GEM names
+* for backwards compatibility with drm_gralloc. (Do not use on new
+* systems.) */
+   dri2_dpy->loader_extensions = droid_dri2_loader_extensions;
+   if (!dri2_load_driver(disp)) {
+  err = "DRI2: failed to load driver";
+  goto error;
+   }
+   #else
+   err = "DRI2: handle is not for a render node";
+   goto error;
+   #endif
+   } else {
+   dri2_dpy->loader_extensions = droid_image_loader_extensions;
+   if (!dri2_load_driver_dri3(disp)) {
+  err = "DRI3: failed to load driver";
+  goto error;
+   }
+}
+
+   return EGL_TRUE;
+
+error:
+   free(dri2_dpy->driver_name);
+   dri2_dpy->driver_name = NULL;
+   return _eglError(EGL_NOT_INITIALIZED, err);
+}
+
+static int
+droid_probe_driver(_EGLDisplay *disp, int fd)
+{
+   struct dri2_egl_display *dri2_dpy = disp->DriverData;
+   dri2_dpy->fd = fd;
+
+   if (!droid_load_driver(disp))
+  return false;
+
+   /* Since this probe can succeed, but another filter may fail,
+  this string needs to be deallocated either way.
+  Once an FD has been found, this string will be set a second time. */
+   free(dri2_dpy->driver_name);
+   dri2_dpy->driver_name = NULL;
+   return true;
+}
+
+static int
+droid_probe_device(_EGLDisplay *disp, int fd, drmDevicePtr dev, char *vendor)
+{
+   drmVersionPtr ver = drmGetVersion(fd);
+   if (!ver)
+   goto fail;
+
+   size_t vendor_len = strlen(vendor);
+   if (vendor_len != 0 && strncmp(vendor, ver->name, vendor_len))
+  goto fail;
+
+   if (!droid_probe_driver(disp, fd))
+  goto fail;
+
+   drmFreeVersion(ver);
+   return true;
+
+fail:
+   drmFreeVersion(ver);
+   return false;
+}
+
+static int
+droid_open_device(_EGLDisplay *disp)
+{
+   const int MAX_DRM_DEVICES = 32;
+   int prop_set, num_devices, ret;
+   int fd = -1, fallback_fd = -1;
+
+   char vendor_name[PROPERTY_VALUE_MAX];
+   property_get("drm.gpu.vendor_name", vendor_name, NULL);
+
+   drmDevicePtr devices[MAX_DRM_DEVICES];
+   num_devices = drmGetDevices2(0, devices, MAX_DRM_DEVICES);
+
+   if (num_devices < 0) {
+  _eglLog(_EGL_WARNING, "Unable to find DRM devices, error %d", 
num_devices);
+  return -1;
+   }
+
+   if (num_devices == 0) {
+  

[Mesa-dev] [PATCH 1/3] gallium/util: Fix build error due to cast to different size

[Robert Foss]

Signed-off-by: Robert Foss 
---
 src/gallium/auxiliary/util/u_debug_stack_android.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_debug_stack_android.cpp 
b/src/gallium/auxiliary/util/u_debug_stack_android.cpp
index b3d56aebe6..395a1fe911 100644
--- a/src/gallium/auxiliary/util/u_debug_stack_android.cpp
+++ b/src/gallium/auxiliary/util/u_debug_stack_android.cpp
@@ -49,10 +49,10 @@ debug_backtrace_capture(debug_stack_frame *mesa_backtrace,
   backtrace_table = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 _mesa_key_pointer_equal);
 
-   backtrace_entry = _mesa_hash_table_search(backtrace_table, (void*) tid);
+   backtrace_entry = _mesa_hash_table_search(backtrace_table, (void*) 
(uintptr_t)tid);
if (!backtrace_entry) {
   backtrace = Backtrace::Create(getpid(), tid);
-  _mesa_hash_table_insert(backtrace_table, (void*) tid, backtrace);
+  _mesa_hash_table_insert(backtrace_table, (void*) (uintptr_t)tid, 
backtrace);
} else {
   backtrace = (Backtrace *) backtrace_entry->data;
}
-- 
2.17.0

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[Mesa-dev] [Bug 106315] The witness + dxvk suffers flickering garbage

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106315

--- Comment #3 from vercammenth...@gmail.com ---
AMDVLK has the same artifacts while amdgpu-pro renders fine. I posted
comparison screenshots in the dxvk github issue:
https://github.com/doitsujin/dxvk/issues/10#issuecomment-388349740

World of Warcraft has similar artifacts on radv and also renders fine with
amdgpu-pro: https://github.com/doitsujin/dxvk/issues/343

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Re: [Mesa-dev] [Mesa-stable] [PATCH] mesa: fix glGetInteger/Float/etc queries for vertex arrays attribs

[Brian Paul]

On 05/11/2018 03:51 AM, Juan A. Suarez Romero wrote:

On Wed, 2018-05-09 at 19:51 -0600, Brian Paul wrote:

The vertex array Size and Stride attributes are now ubyte and short,
respectively.  The glGet code needed to be updated to handle those
types, but wasn't.

Fixes the new piglit test gl-1.5-get-array-attribs test.

Bugzilla: 
https://urldefense.proofpoint.com/v2/url?u=https-3A__bugs.freedesktop.org_show-5Fbug.cgi-3Fid-3D106450=DwICaQ=uilaK90D4TOVoH58JNXRgQ=Ie7_encNUsqxbSRbqbNgofw0ITcfE8JKfaUjIQhncGA=UiMSw582Jyda8hb5bMjFvA5YnjycFZvNEg-XV3XkgR8=xrYXXcUiUfyIya8IE0wGTxl0FQoLbLKk-BKwePoIDRg=
Fixes: d5f42f96e16 ("mesa: shrink size of gl_array_attributes (v2)")
Cc: mesa-sta...@lists.freedesktop.org



This commit was nominated for inclusion to stable, but at the same time it has
the "Fixes" tag.

My understanding is that this patch does not make sense if the branch doesn't
include the commit it fixes.

In the case of 18.0 stable branch, commit d5f42f96e16 is not there, so I
understand this nominated patch shouldn't be included neither. Thus, I'll reject
it for 18.0.

If you think it should be included anyway, just sent a new patch that can be
applied in 18.0.

Thank you.


OK, no problem.  I was assuming the 18.0 branch was created after Jan 
19, but evidently it was made before.


-Brian


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Re: [Mesa-dev] [Intel-gfx] [PATCH] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk

[Chris Wilson]

Quoting Mika Kuoppala (2018-05-11 10:56:49)
> Michel Thierry  writes:
> 
> > Factor in clear values wherever required while updating destination
> > min/max.
> >
> > References: HSDES#160184
> > Signed-off-by: Michel Thierry 
> > Cc: mesa-dev@lists.freedesktop.org
> > Cc: Mika Kuoppala 
> > Cc: Oscar Mateo 
> 
> Reviewed-by: Mika Kuoppala 

Cc: stable?
-Chris
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[Mesa-dev] [PATCH] anv,nir: add generated files to .gitignore(s)

[Rhys Perry]

---
 src/compiler/nir/.gitignore | 2 ++
 src/intel/vulkan/.gitignore | 1 +
 2 files changed, 3 insertions(+)

diff --git a/src/compiler/nir/.gitignore b/src/compiler/nir/.gitignore
index 64828eba6d..8faf93f0b2 100644
--- a/src/compiler/nir/.gitignore
+++ b/src/compiler/nir/.gitignore
@@ -3,3 +3,5 @@ nir_opt_algebraic.c
 nir_opcodes.c
 nir_opcodes.h
 nir_constant_expressions.c
+nir_intrinsics.c
+nir_intrinsics.h
diff --git a/src/intel/vulkan/.gitignore b/src/intel/vulkan/.gitignore
index 4ea978d6e4..b84b17134f 100644
--- a/src/intel/vulkan/.gitignore
+++ b/src/intel/vulkan/.gitignore
@@ -1,5 +1,6 @@
 # Generated source files
 /anv_extensions.c
+/anv_extensions.h
 /anv_entrypoints.c
 /anv_entrypoints.h
 /anv_timestamp.h
-- 
2.14.3

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[Mesa-dev] [Bug 34259] gallium: transfers should use z/depth and not y/height for 1d array textures as layer parameter

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=34259

Roland Scheidegger  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #2 from Roland Scheidegger  ---
I am quite sure this was fixed ages ago (I think when mesa core stopped using
height for slice when mapping etc. 1d arrays).

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Re: [Mesa-dev] [PATCH] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk

[Mika Kuoppala]

Michel Thierry  writes:

> Factor in clear values wherever required while updating destination
> min/max.
>
> References: HSDES#160184
> Signed-off-by: Michel Thierry 
> Cc: mesa-dev@lists.freedesktop.org
> Cc: Mika Kuoppala 
> Cc: Oscar Mateo 

Reviewed-by: Mika Kuoppala 
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[Mesa-dev] [PATCH] nvc0: fix setting of subpixel precision during conservative rasterization

[Rhys Perry]

Signed-off-by: Rhys Perry 
---
 src/gallium/drivers/nouveau/nvc0/mme/com9097.mme   | 2 +-
 src/gallium/drivers/nouveau/nvc0/mme/com9097.mme.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nvc0/mme/com9097.mme 
b/src/gallium/drivers/nouveau/nvc0/mme/com9097.mme
index ecf9960667..38c2e86843 100644
--- a/src/gallium/drivers/nouveau/nvc0/mme/com9097.mme
+++ b/src/gallium/drivers/nouveau/nvc0/mme/com9097.mme
@@ -569,7 +569,7 @@ qbw_done:
mov $r2 0x831
send (extrinsrt 0x0 $r2 0 12 11) /* sends 0x418800 */
/* Subpixel precision */
-   mov $r2 (extrinsrt 0x0 $r1 0 3 0)
+   mov $r2 (extrinsrt 0x0 $r1 0 4 0)
mov $r2 (extrinsrt $r2 $r1 4 4 8)
maddr 0x8287 /* SUBPIXEL_PRECISION[0] (incrementing by 8 methods) */
mov $r3 16 /* loop counter */
diff --git a/src/gallium/drivers/nouveau/nvc0/mme/com9097.mme.h 
b/src/gallium/drivers/nouveau/nvc0/mme/com9097.mme.h
index 3eacda9a27..49c0891114 100644
--- a/src/gallium/drivers/nouveau/nvc0/mme/com9097.mme.h
+++ b/src/gallium/drivers/nouveau/nvc0/mme/com9097.mme.h
@@ -384,7 +384,7 @@ uint32_t mme9097_conservative_raster_state[] = {
0x06310021,
0x020c4211,
0x5b008042,
-   0x00c04212,
+   0x01004212,
0x41085212,
0x20a1c021,
0x00040311,
-- 
2.14.3

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Re: [Mesa-dev] [PATCH 1/2] mesa: changes to expose OES_texture_view extension

[Tapani Pälli]

On 05/11/2018 02:44 PM, Ilia Mirkin wrote:

On Fri, May 11, 2018 at 6:21 AM, Tapani Pälli  wrote:

I've sent couple of patch to piglit mailing list that add 6 more test cases.
There are some tests left, some of them are problematic not because of API
but formats being used. Let me know if there are some particular tests/API
in addition to which I converted you might be worried about.


There wasn't anything in particular. I just saw you were relying on
existing piglit coverage for your testing of the extension, and wanted
to ensure it was known that this was incomplete -- I had started
working on it and never finished, probably due to seeing something
shiny. Probably worth checking if something has materialized in dEQP
or CTS -- there was nothing at the time.



Thanks for pointing it out. For dEQP there is some small usage of 
TextureView in couple of tests (in CopyImage, TextureBorderClamp) but 
does not have dedicated test for it, Desktop CTS has one.


Thanks;

// Tapani
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Re: [Mesa-dev] [PATCH 1/2] mesa: changes to expose OES_texture_view extension

[Ilia Mirkin]

On Fri, May 11, 2018 at 6:21 AM, Tapani Pälli  wrote:
> I've sent couple of patch to piglit mailing list that add 6 more test cases.
> There are some tests left, some of them are problematic not because of API
> but formats being used. Let me know if there are some particular tests/API
> in addition to which I converted you might be worried about.

There wasn't anything in particular. I just saw you were relying on
existing piglit coverage for your testing of the extension, and wanted
to ensure it was known that this was incomplete -- I had started
working on it and never finished, probably due to seeing something
shiny. Probably worth checking if something has materialized in dEQP
or CTS -- there was nothing at the time.

Cheers,

  -ilia
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[Mesa-dev] [PATCH 1/2] glsl: allow built-in variables to be explicitly declared

[Timothy Arceri]

Mesa seems to be the only implementation that doesn't allow builtins
to be explicitly declared. The GLSL 1.30 spec seems to imply that
buitins may be explicitly declared.

This this allows the game "Full Bore" the be playable (when using
MESA_GL_VERSION_OVERRIDE=3.3COMPAT). It will also allow us to
remove the allow_glsl_builtin_variable_redeclaration dri override.

From the GLSL 1.30 spec Section 7.2 (Fragment Shader Special
Variables):

"Both gl_FragColor and gl_FragData are deprecated; the preferred
usage is to explicitly declare these outputs in the fragment
shader using the out storage qualifier."

To avoid some GLSL ES tests failing we add a check to make sure
precision matches on the redeclared builtin.

precission
---
 src/compiler/glsl/ast_to_hir.cpp | 30 --
 1 file changed, 20 insertions(+), 10 deletions(-)

diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index 3bf581571e2..178004bb5d4 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -4317,14 +4317,8 @@ get_variable_being_redeclared(ir_variable **var_ptr, 
YYLTYPE loc,
   earlier->data.precision = var->data.precision;
   earlier->data.memory_coherent = var->data.memory_coherent;
 
-   } else if (earlier->data.how_declared == ir_var_declared_implicitly &&
-  state->allow_builtin_variable_redeclaration) {
-  /* Allow verbatim redeclarations of built-in variables. Not explicitly
-   * valid, but some applications do it.
-   */
-  if (earlier->data.mode != var->data.mode &&
-  !(earlier->data.mode == ir_var_system_value &&
-var->data.mode == ir_var_shader_in)) {
+   } else if (allow_all_redeclarations) {
+  if (earlier->data.mode != var->data.mode) {
  _mesa_glsl_error(, state,
   "redeclaration of `%s' with incorrect qualifiers",
   var->name);
@@ -4333,8 +4327,20 @@ get_variable_being_redeclared(ir_variable **var_ptr, 
YYLTYPE loc,
   "redeclaration of `%s' has incorrect type",
   var->name);
   }
-   } else if (allow_all_redeclarations) {
-  if (earlier->data.mode != var->data.mode) {
+   } else if (earlier->data.how_declared == ir_var_declared_implicitly) {
+  /* Allow verbatim redeclarations of built-in variables. The GLSL 1.30
+   * spec seems to imply that buitins may be explicitly declared.
+   *
+   * From the GLSL 1.30 spec Section 7.2 (Fragment Shader Special
+   * Variables):
+   *
+   *"Both gl_FragColor and gl_FragData are deprecated; the preferred
+   *usage is to explicitly declare these outputs in the fragment
+   *shader using the out storage qualifier."
+   */
+  if (earlier->data.mode != var->data.mode &&
+  !(earlier->data.mode == ir_var_system_value &&
+var->data.mode == ir_var_shader_in)) {
  _mesa_glsl_error(, state,
   "redeclaration of `%s' with incorrect qualifiers",
   var->name);
@@ -4342,6 +4348,10 @@ get_variable_being_redeclared(ir_variable **var_ptr, 
YYLTYPE loc,
  _mesa_glsl_error(, state,
   "redeclaration of `%s' has incorrect type",
   var->name);
+  } else if (earlier->data.precision != var->data.precision) {
+ _mesa_glsl_error(, state,
+  "redeclaration of `%s' has incorrect precision",
+  var->name);
   }
} else {
   _mesa_glsl_error(, state, "`%s' redeclared", var->name);
-- 
2.17.0

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[Mesa-dev] [PATCH 2/2] mesa/st/i965: remove the allow_glsl_builtin_variable_redeclaration dri option

[Timothy Arceri]

The previous patch changes the compiler to behave this way always so
we no longer need it.
---
 src/compiler/glsl/glsl_parser_extras.cpp  |  2 --
 src/compiler/glsl/glsl_parser_extras.h|  1 -
 .../auxiliary/pipe-loader/driinfo_gallium.h   |  1 -
 src/gallium/include/state_tracker/st_api.h|  1 -
 src/gallium/state_trackers/dri/dri_screen.c   |  2 --
 src/mesa/drivers/dri/i965/brw_context.c   |  3 ---
 src/mesa/drivers/dri/i965/intel_screen.c  |  1 -
 src/mesa/main/mtypes.h|  5 -
 src/mesa/state_tracker/st_extensions.c|  2 --
 src/util/drirc| 15 ---
 src/util/xmlpool/t_options.h  |  5 -
 11 files changed, 38 deletions(-)

diff --git a/src/compiler/glsl/glsl_parser_extras.cpp 
b/src/compiler/glsl/glsl_parser_extras.cpp
index 25003eeccce..c6ffdcc588c 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -304,8 +304,6 @@ _mesa_glsl_parse_state::_mesa_glsl_parse_state(struct 
gl_context *_ctx,
   sizeof(this->atomic_counter_offsets));
this->allow_extension_directive_midshader =
   ctx->Const.AllowGLSLExtensionDirectiveMidShader;
-   this->allow_builtin_variable_redeclaration =
-  ctx->Const.AllowGLSLBuiltinVariableRedeclaration;
 
this->cs_input_local_size_variable_specified = false;
 
diff --git a/src/compiler/glsl/glsl_parser_extras.h 
b/src/compiler/glsl/glsl_parser_extras.h
index 5b9b6cc8621..794aa5dc2fd 100644
--- a/src/compiler/glsl/glsl_parser_extras.h
+++ b/src/compiler/glsl/glsl_parser_extras.h
@@ -848,7 +848,6 @@ struct _mesa_glsl_parse_state {
unsigned atomic_counter_offsets[MAX_COMBINED_ATOMIC_BUFFERS];
 
bool allow_extension_directive_midshader;
-   bool allow_builtin_variable_redeclaration;
 
/**
 * Known subroutine type declarations.
diff --git a/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h 
b/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
index 21dc599dc26..85e3b699964 100644
--- a/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
+++ b/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
@@ -23,7 +23,6 @@ DRI_CONF_SECTION_DEBUG
DRI_CONF_DISABLE_SHADER_BIT_ENCODING("false")
DRI_CONF_FORCE_GLSL_VERSION(0)
DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
-   DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false")
DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
diff --git a/src/gallium/include/state_tracker/st_api.h 
b/src/gallium/include/state_tracker/st_api.h
index ec6e7844b87..b8fc833b356 100644
--- a/src/gallium/include/state_tracker/st_api.h
+++ b/src/gallium/include/state_tracker/st_api.h
@@ -222,7 +222,6 @@ struct st_config_options
boolean force_glsl_extensions_warn;
unsigned force_glsl_version;
boolean allow_glsl_extension_directive_midshader;
-   boolean allow_glsl_builtin_variable_redeclaration;
boolean allow_higher_compat_version;
boolean glsl_zero_init;
boolean force_glsl_abs_sqrt;
diff --git a/src/gallium/state_trackers/dri/dri_screen.c 
b/src/gallium/state_trackers/dri/dri_screen.c
index aaee9870776..c0df65aa5a6 100644
--- a/src/gallium/state_trackers/dri/dri_screen.c
+++ b/src/gallium/state_trackers/dri/dri_screen.c
@@ -74,8 +74,6 @@ dri_fill_st_options(struct dri_screen *screen)
   driQueryOptioni(optionCache, "force_glsl_version");
options->allow_glsl_extension_directive_midshader =
   driQueryOptionb(optionCache, "allow_glsl_extension_directive_midshader");
-   options->allow_glsl_builtin_variable_redeclaration =
-  driQueryOptionb(optionCache, 
"allow_glsl_builtin_variable_redeclaration");
options->allow_higher_compat_version =
   driQueryOptionb(optionCache, "allow_higher_compat_version");
options->glsl_zero_init = driQueryOptionb(optionCache, "glsl_zero_init");
diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index bd1e20845f0..c338dd4c29b 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -836,9 +836,6 @@ brw_process_driconf_options(struct brw_context *brw)
ctx->Const.AllowGLSLExtensionDirectiveMidShader =
   driQueryOptionb(options, "allow_glsl_extension_directive_midshader");
 
-   ctx->Const.AllowGLSLBuiltinVariableRedeclaration =
-  driQueryOptionb(options, "allow_glsl_builtin_variable_redeclaration");
-
ctx->Const.AllowHigherCompatVersion =
   driQueryOptionb(options, "allow_higher_compat_version");
 
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 409f763b640..ef7efdeba24 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -84,7 +84,6 @@ DRI_CONF_BEGIN
   

Re: [Mesa-dev] [PATCH 3/3] radv: use compute path for multi-layer images.

[Bas Nieuwenhuizen]

Series is

Reviewed-by: Bas Nieuwenhuizen 

CC to stable?

On Fri, May 11, 2018 at 6:56 AM, Dave Airlie  wrote:
> From: Dave Airlie 
>
> I don't think the hw resolve path can't handle multi-layer images.
>
> This fixes all the:
> dEQP-VK.renderpass.multisample_resolve.layers_*
> tests on my VI card.
> ---
>  src/amd/vulkan/radv_meta_resolve.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/src/amd/vulkan/radv_meta_resolve.c 
> b/src/amd/vulkan/radv_meta_resolve.c
> index 75916713c00..d4d3552f317 100644
> --- a/src/amd/vulkan/radv_meta_resolve.c
> +++ b/src/amd/vulkan/radv_meta_resolve.c
> @@ -358,6 +358,8 @@ static void radv_pick_resolve_method_images(struct 
> radv_image *src_image,
> *method = RESOLVE_COMPUTE;
> else if (vk_format_is_int(src_image->vk_format))
> *method = RESOLVE_COMPUTE;
> +   else if (src_image->info.array_size > 1)
> +   *method = RESOLVE_COMPUTE;
>
> if (radv_layout_dcc_compressed(dest_image, dest_image_layout, 
> queue_mask)) {
> *method = RESOLVE_FRAGMENT;
> --
> 2.14.3
>
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Re: [Mesa-dev] [Mesa-stable] [PATCH] mesa: revert GL_[SECONDARY_]COLOR_ARRAY_SIZE glGet type to TYPE_INT

[Juan A. Suarez Romero]

On Thu, 2018-05-10 at 09:27 -0600, Brian Paul wrote:
> Since size can be 3, 4 or GL_BGRA we need to keep these glGet types
> as TYPE_INT, not TYPE_UBYTE.
> 
> Fixes: d07466fe18522 ("mesa: fix glGetInteger/Float/etc queries for
> vertex arrays attribs")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106462
> cc: mesa-sta...@lists.freedesktop.org

Hi!

This commit was nominated for stable, but at the same time with Fixes. My
understanding is that this should be included in stable release only if the
commit it fixes was also included.

For the specific case of 18.0 release, d07466fe18522 is not part of the release.
 Thus, I will reject this patch too.

If you think this patch should be included anyway, please, submit a version that
can be applied cleanly.


Thank you!


J.A.

> ---
>  src/mesa/main/get_hash_params.py | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/src/mesa/main/get_hash_params.py 
> b/src/mesa/main/get_hash_params.py
> index bb7d23a..a97b948 100644
> --- a/src/mesa/main/get_hash_params.py
> +++ b/src/mesa/main/get_hash_params.py
> @@ -219,7 +219,7 @@ descriptor=[
>[ "NORMAL_ARRAY_TYPE", 
> "ARRAY_ENUM16(VertexAttrib[VERT_ATTRIB_NORMAL].Type), NO_EXTRA" ],
>[ "NORMAL_ARRAY_STRIDE", 
> "ARRAY_SHORT(VertexAttrib[VERT_ATTRIB_NORMAL].Stride), NO_EXTRA" ],
>[ "COLOR_ARRAY", "ARRAY_BOOL(VertexAttrib[VERT_ATTRIB_COLOR0].Enabled), 
> NO_EXTRA" ],
> -  [ "COLOR_ARRAY_SIZE", "LOC_CUSTOM, TYPE_UBYTE, 0, NO_EXTRA" ],
> +  [ "COLOR_ARRAY_SIZE", "LOC_CUSTOM, TYPE_INT, 0, NO_EXTRA" ],
>[ "COLOR_ARRAY_TYPE", 
> "ARRAY_ENUM16(VertexAttrib[VERT_ATTRIB_COLOR0].Type), NO_EXTRA" ],
>[ "COLOR_ARRAY_STRIDE", 
> "ARRAY_SHORT(VertexAttrib[VERT_ATTRIB_COLOR0].Stride), NO_EXTRA" ],
>[ "TEXTURE_COORD_ARRAY", "LOC_CUSTOM, TYPE_BOOLEAN, offsetof(struct 
> gl_array_attributes, Enabled), NO_EXTRA" ],
> @@ -825,7 +825,7 @@ descriptor=[
>[ "SECONDARY_COLOR_ARRAY", 
> "ARRAY_BOOL(VertexAttrib[VERT_ATTRIB_COLOR1].Enabled), NO_EXTRA" ],
>[ "SECONDARY_COLOR_ARRAY_TYPE", 
> "ARRAY_ENUM16(VertexAttrib[VERT_ATTRIB_COLOR1].Type), NO_EXTRA" ],
>[ "SECONDARY_COLOR_ARRAY_STRIDE", 
> "ARRAY_SHORT(VertexAttrib[VERT_ATTRIB_COLOR1].Stride), NO_EXTRA" ],
> -  [ "SECONDARY_COLOR_ARRAY_SIZE", "LOC_CUSTOM, TYPE_UBYTE, 0, NO_EXTRA" ],
> +  [ "SECONDARY_COLOR_ARRAY_SIZE", "LOC_CUSTOM, TYPE_INT, 0, NO_EXTRA" ],
>  
>  # GL_EXT_fog_coord
>[ "CURRENT_FOG_COORDINATE", 
> "CONTEXT_FLOAT(Current.Attrib[VERT_ATTRIB_FOG][0]), extra_flush_current" ],
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Re: [Mesa-dev] [PATCH 1/2] mesa: changes to expose OES_texture_view extension

[Tapani Pälli]

Hi Ilia;

On 05/09/2018 04:05 PM, Tapani Pälli wrote:



On 09.05.2018 14:39, Ilia Mirkin wrote:
On Wed, May 9, 2018 at 2:12 AM, Tapani Pälli  
wrote:

Functionality already covered by ARB_texture_view, patch also
adds missing 'gles guard' for enums (added in f1563e6392).

Tested via arb_texture_view.*_gles3 tests and individual app
utilizing texture view with ETC2.


I only converted a few of the tests to work with GLES3 (it was nearly
2 years ago, so my recollection is hazy, but I think the remainder
required a lot more work). I think all or most of the tests in
arb_texture_view need GLES3 equivalents before we can be sure the
functionality is good to go. At the very least, someone should audit
the tests that were not converted to see what functionality is not
being tested. I definitely didn't feel like I was finished enough to
push the implementation in mesa at the time.



I took a look at some of them, one issue is that piglit-utils 'probe 
texel' functions are not compatible with ES because they use 
glGetTexImage, to have more test coverage I think we would need to have 
ES compatible equivalent for those functions. Will check how it would work.


I've sent couple of patch to piglit mailing list that add 6 more test 
cases. There are some tests left, some of them are problematic not 
because of API but formats being used. Let me know if there are some 
particular tests/API in addition to which I converted you might be 
worried about.


Thanks;

// Tapani
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Re: [Mesa-dev] [PATCH] glx/dri: Take an extra reference on our own GLX drawables

[Michel Dänzer]

On 2018-05-11 10:23 AM, Michel Dänzer wrote:
> On 2018-05-10 05:09 PM, Adam Jackson wrote:
>> On Wed, 2018-05-09 at 18:17 +0200, Michel Dänzer wrote:
>>
>>> How about the idea I described before, saving the loader_dri3_drawable
>>> values in a hash table in dri3_screen? Maybe we could simply save a
>>> pointer to the whole struct, after only freeing the renderbuffers.
>>
>> That would also leak, less in absolute terms but the same big-O, for
>> the same reasons.
> 
> Sure, but with the same number x of leaked objects, there's a difference
> between leaking x times tens of bytes, or x times potentially megabytes.

Also, if we wanted to get fancy, we could periodically (in a thread?)
iterate over the hash table entries and check if the windows still exist.


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Re: [Mesa-dev] [Mesa-stable] [PATCH] mesa: fix glGetInteger/Float/etc queries for vertex arrays attribs

[Juan A. Suarez Romero]

On Wed, 2018-05-09 at 19:51 -0600, Brian Paul wrote:
> The vertex array Size and Stride attributes are now ubyte and short,
> respectively.  The glGet code needed to be updated to handle those
> types, but wasn't.
> 
> Fixes the new piglit test gl-1.5-get-array-attribs test.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106450
> Fixes: d5f42f96e16 ("mesa: shrink size of gl_array_attributes (v2)")
> Cc: mesa-sta...@lists.freedesktop.org


This commit was nominated for inclusion to stable, but at the same time it has
the "Fixes" tag.

My understanding is that this patch does not make sense if the branch doesn't
include the commit it fixes.

In the case of 18.0 stable branch, commit d5f42f96e16 is not there, so I
understand this nominated patch shouldn't be included neither. Thus, I'll reject
it for 18.0.

If you think it should be included anyway, just sent a new patch that can be
applied in 18.0.

Thank you.


J.A.



> ---
>  src/mesa/main/get.c  | 77 
> ++--
>  src/mesa/main/get_hash_params.py | 24 ++---
>  2 files changed, 86 insertions(+), 15 deletions(-)
> 
> diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
> index 44b7b83..441eac4 100644
> --- a/src/mesa/main/get.c
> +++ b/src/mesa/main/get.c
> @@ -105,6 +105,8 @@ enum value_type {
> TYPE_ENUM,
> TYPE_ENUM_2,
> TYPE_BOOLEAN,
> +   TYPE_UBYTE,
> +   TYPE_SHORT,
> TYPE_BIT_0,
> TYPE_BIT_1,
> TYPE_BIT_2,
> @@ -188,6 +190,8 @@ union value {
> GLint value_int_4[4];
> GLint64 value_int64;
> GLenum value_enum;
> +   GLubyte value_ubyte;
> +   GLshort value_short;
>  
> /* Sigh, see GL_COMPRESSED_TEXTURE_FORMATS_ARB handling */
> struct {
> @@ -235,10 +239,13 @@ union value {
>  #define CONTEXT_MATRIX(field) CONTEXT_FIELD(field, TYPE_MATRIX)
>  #define CONTEXT_MATRIX_T(field) CONTEXT_FIELD(field, TYPE_MATRIX_T)
>  
> +/* Vertex array fields */
>  #define ARRAY_INT(field) ARRAY_FIELD(field, TYPE_INT)
>  #define ARRAY_ENUM(field) ARRAY_FIELD(field, TYPE_ENUM)
>  #define ARRAY_ENUM16(field) ARRAY_FIELD(field, TYPE_ENUM16)
>  #define ARRAY_BOOL(field) ARRAY_FIELD(field, TYPE_BOOLEAN)
> +#define ARRAY_UBYTE(field) ARRAY_FIELD(field, TYPE_UBYTE)
> +#define ARRAY_SHORT(field) ARRAY_FIELD(field, TYPE_SHORT)
>  
>  #define EXT(f)   \
> offsetof(struct gl_extensions, f)
> @@ -1520,6 +1527,10 @@ get_value_size(enum value_type type, const union value 
> *v)
>return sizeof(GLenum) * 2;
> case TYPE_BOOLEAN:
>return sizeof(GLboolean);
> +   case TYPE_UBYTE:
> +  return sizeof(GLubyte);
> +   case TYPE_SHORT:
> +  return sizeof(GLshort);
> case TYPE_BIT_0:
> case TYPE_BIT_1:
> case TYPE_BIT_2:
> @@ -1628,7 +1639,15 @@ _mesa_GetBooleanv(GLenum pname, GLboolean *params)
>break;
>  
> case TYPE_BOOLEAN:
> -  params[0] = ((GLboolean*) p)[0];
> +  params[0] = ((GLboolean *) p)[0];
> +  break;
> +
> +   case TYPE_UBYTE:
> +  params[0] = ((GLubyte *) p)[0] != 0;
> +  break;
> +
> +   case TYPE_SHORT:
> +  params[0] = ((GLshort *) p)[0] != 0;
>break;
>  
> case TYPE_MATRIX:
> @@ -1735,7 +1754,15 @@ _mesa_GetFloatv(GLenum pname, GLfloat *params)
>break;
>  
> case TYPE_BOOLEAN:
> -  params[0] = BOOLEAN_TO_FLOAT(*(GLboolean*) p);
> +  params[0] = BOOLEAN_TO_FLOAT(*(GLboolean *) p);
> +  break;
> +
> +   case TYPE_UBYTE:
> +  params[0] = (GLfloat) ((GLubyte *) p)[0];
> +  break;
> +
> +   case TYPE_SHORT:
> +  params[0] = (GLfloat) ((GLshort *) p)[0];
>break;
>  
> case TYPE_MATRIX:
> @@ -1845,6 +1872,14 @@ _mesa_GetIntegerv(GLenum pname, GLint *params)
>params[0] = BOOLEAN_TO_INT(*(GLboolean*) p);
>break;
>  
> +   case TYPE_UBYTE:
> +  params[0] = ((GLubyte *) p)[0];
> +  break;
> +
> +   case TYPE_SHORT:
> +  params[0] = ((GLshort *) p)[0];
> +  break;
> +
> case TYPE_MATRIX:
>m = *(GLmatrix **) p;
>for (i = 0; i < 16; i++)
> @@ -2065,6 +2100,14 @@ _mesa_GetDoublev(GLenum pname, GLdouble *params)
>params[0] = *(GLboolean*) p;
>break;
>  
> +   case TYPE_UBYTE:
> +  params[0] = ((GLubyte *) p)[0];
> +  break;
> +
> +   case TYPE_SHORT:
> +  params[0] = ((GLshort *) p)[0];
> +  break;
> +
> case TYPE_MATRIX:
>m = *(GLmatrix **) p;
>for (i = 0; i < 16; i++)
> @@ -2144,6 +2187,8 @@ _mesa_GetUnsignedBytevEXT(GLenum pname, GLubyte *data)
> case TYPE_ENUM:
> case TYPE_ENUM_2:
> case TYPE_BOOLEAN:
> +   case TYPE_UBYTE:
> +   case TYPE_SHORT:
> case TYPE_FLOAT:
> case TYPE_FLOATN:
> case TYPE_FLOAT_2:
> @@ -2793,6 +2838,14 @@ _mesa_GetFloati_v(GLenum pname, GLuint index, GLfloat 
> *params)
>params[0] = BOOLEAN_TO_FLOAT(v.value_bool);
>break;
>  
> +   case TYPE_UBYTE:
> +  params[0] = (GLfloat) v.value_ubyte;
> +  break;
> +
> +   case 

Re: [Mesa-dev] [PATCH] radv: minor cleanups in radv_fill_shader_variant()

[Timothy Arceri]

Reviewed-by: Timothy Arceri 

On 11/05/18 17:46, Samuel Pitoiset wrote:

Signed-off-by: Samuel Pitoiset 
---
  src/amd/vulkan/radv_shader.c | 29 +++--
  1 file changed, 15 insertions(+), 14 deletions(-)

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 27b3fbed16d..07634870d4f 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -371,6 +371,7 @@ radv_fill_shader_variant(struct radv_device *device,
 gl_shader_stage stage)
  {
bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
+   struct radv_shader_info *info = >info.info;
unsigned vgpr_comp_cnt = 0;
  
  	if (scratch_enabled && !device->llvm_supports_spill)

@@ -378,9 +379,9 @@ radv_fill_shader_variant(struct radv_device *device,
  
  	variant->code_size = binary->code_size;

variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
-   S_00B12C_SCRATCH_EN(scratch_enabled);
+S_00B12C_SCRATCH_EN(scratch_enabled);
  
-	variant->rsrc1 =  S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |

+   variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
S_00B848_DX10_CLAMP(1) |
S_00B848_FLOAT_MODE(variant->config.float_mode);
@@ -391,10 +392,11 @@ radv_fill_shader_variant(struct radv_device *device,
variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
break;
case MESA_SHADER_TESS_CTRL:
-   if (device->physical_device->rad_info.chip_class >= GFX9)
+   if (device->physical_device->rad_info.chip_class >= GFX9) {
vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
-   else
+   } else {
variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
+   }
break;
case MESA_SHADER_VERTEX:
case MESA_SHADER_GEOMETRY:
@@ -402,8 +404,7 @@ radv_fill_shader_variant(struct radv_device *device,
break;
case MESA_SHADER_FRAGMENT:
break;
-   case MESA_SHADER_COMPUTE: {
-   struct radv_shader_info *info = >info.info;
+   case MESA_SHADER_COMPUTE:
variant->rsrc2 |=
S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
@@ -413,7 +414,6 @@ radv_fill_shader_variant(struct radv_device *device,
S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) 
|
S_00B84C_LDS_SIZE(variant->config.lds_size);
break;
-   }
default:
unreachable("unsupported shader type");
break;
@@ -421,7 +421,6 @@ radv_fill_shader_variant(struct radv_device *device,
  
  	if (device->physical_device->rad_info.chip_class >= GFX9 &&

stage == MESA_SHADER_GEOMETRY) {
-   struct radv_shader_info *info = >info.info;
unsigned es_type = variant->info.gs.es_type;
unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
  
@@ -436,23 +435,25 @@ radv_fill_shader_variant(struct radv_device *device,

/* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
 * VGPR[0:4] are always loaded.
 */
-   if (info->uses_invocation_id)
+   if (info->uses_invocation_id) {
gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
-   else if (info->uses_prim_id)
+   } else if (info->uses_prim_id) {
gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
-   else if (variant->info.gs.vertices_in >= 3)
+   } else if (variant->info.gs.vertices_in >= 3) {
gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
-   else
+   } else {
gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
+   }
  
  		variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);

variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
  S_00B22C_OC_LDS_EN(es_type == 
MESA_SHADER_TESS_EVAL);
} else if (device->physical_device->rad_info.chip_class >= GFX9 &&
-   stage == MESA_SHADER_TESS_CTRL)
+  stage == MESA_SHADER_TESS_CTRL) {
variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
-   else
+   } else {
variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
+   }
  
  	void *ptr = radv_alloc_shader_memory(device, variant);

memcpy(ptr, binary->code, binary->code_size);


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Re: [Mesa-dev] [PATCH] radv: move ac_build_if_state on top of radv_nir_to_llvm.c

[Timothy Arceri]

Reviewed-by: Timothy Arceri 

On 11/05/18 17:38, Samuel Pitoiset wrote:

These helpers will be needed for future work.

Signed-off-by: Samuel Pitoiset 
---
  src/amd/vulkan/radv_nir_to_llvm.c | 183 +++---
  1 file changed, 92 insertions(+), 91 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index cee3558215d..725fdb07a4d 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -130,6 +130,98 @@ radv_shader_context_from_abi(struct ac_shader_abi *abi)
return container_of(abi, ctx, abi);
  }
  
+struct ac_build_if_state

+{
+   struct radv_shader_context *ctx;
+   LLVMValueRef condition;
+   LLVMBasicBlockRef entry_block;
+   LLVMBasicBlockRef true_block;
+   LLVMBasicBlockRef false_block;
+   LLVMBasicBlockRef merge_block;
+};
+
+static LLVMBasicBlockRef
+ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
+{
+   LLVMBasicBlockRef current_block;
+   LLVMBasicBlockRef next_block;
+   LLVMBasicBlockRef new_block;
+
+   /* get current basic block */
+   current_block = LLVMGetInsertBlock(ctx->ac.builder);
+
+   /* chqeck if there's another block after this one */
+   next_block = LLVMGetNextBasicBlock(current_block);
+   if (next_block) {
+   /* insert the new block before the next block */
+   new_block = LLVMInsertBasicBlockInContext(ctx->context, 
next_block, name);
+   }
+   else {
+   /* append new block after current block */
+   LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
+   new_block = LLVMAppendBasicBlockInContext(ctx->context, 
function, name);
+   }
+   return new_block;
+}
+
+static void
+ac_nir_build_if(struct ac_build_if_state *ifthen,
+   struct radv_shader_context *ctx,
+   LLVMValueRef condition)
+{
+   LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
+
+   memset(ifthen, 0, sizeof *ifthen);
+   ifthen->ctx = ctx;
+   ifthen->condition = condition;
+   ifthen->entry_block = block;
+
+   /* create endif/merge basic block for the phi functions */
+   ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
+
+   /* create/insert true_block before merge_block */
+   ifthen->true_block =
+   LLVMInsertBasicBlockInContext(ctx->context,
+ ifthen->merge_block,
+ "if-true-block");
+
+   /* successive code goes into the true block */
+   LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
+}
+
+/**
+ * End a conditional.
+ */
+static void
+ac_nir_build_endif(struct ac_build_if_state *ifthen)
+{
+   LLVMBuilderRef builder = ifthen->ctx->ac.builder;
+
+   /* Insert branch to the merge block from current block */
+   LLVMBuildBr(builder, ifthen->merge_block);
+
+   /*
+* Now patch in the various branch instructions.
+*/
+
+   /* Insert the conditional branch instruction at the end of entry_block 
*/
+   LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
+   if (ifthen->false_block) {
+   /* we have an else clause */
+   LLVMBuildCondBr(builder, ifthen->condition,
+   ifthen->true_block, ifthen->false_block);
+   }
+   else {
+   /* no else clause */
+   LLVMBuildCondBr(builder, ifthen->condition,
+   ifthen->true_block, ifthen->merge_block);
+   }
+
+   /* Resume building code at end of the ifthen->merge_block */
+   LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
+}
+
+
  static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
  {
switch (ctx->stage) {
@@ -2555,97 +2647,6 @@ handle_ls_outputs_post(struct radv_shader_context *ctx)
}
  }
  
-struct ac_build_if_state

-{
-   struct radv_shader_context *ctx;
-   LLVMValueRef condition;
-   LLVMBasicBlockRef entry_block;
-   LLVMBasicBlockRef true_block;
-   LLVMBasicBlockRef false_block;
-   LLVMBasicBlockRef merge_block;
-};
-
-static LLVMBasicBlockRef
-ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
-{
-   LLVMBasicBlockRef current_block;
-   LLVMBasicBlockRef next_block;
-   LLVMBasicBlockRef new_block;
-
-   /* get current basic block */
-   current_block = LLVMGetInsertBlock(ctx->ac.builder);
-
-   /* chqeck if there's another block after this one */
-   next_block = LLVMGetNextBasicBlock(current_block);
-   if (next_block) {
-   /* insert the new block before the next block */
-   new_block = LLVMInsertBasicBlockInContext(ctx->context, 
next_block, name);
-   }
-   else {
-   /* 

Re: [Mesa-dev] [PATCH 2/2] loader_dri3: Variant 2: Wait for pending swaps to complete before drawable_fini.

[Michel Dänzer]

On 2018-05-09 07:32 PM, Adam Jackson wrote:
> On Tue, 2018-05-08 at 11:42 +0200, Michel Dänzer wrote:
> 
>> Idle notify events shouldn't need special treatment, since the pixmap
>> XIDs of the buffers will be different between loader_dri3_drawable
>> incarnations, aren't they?
> 
> We're destroying loader_dri3_drawable structs at MakeCurrent time, but
> not destroying actual drawables, so I don't think the XIDs will change.

I'm talking about loader_dri3_buffer::pixmap, which are destroyed in
loader_dri3_drawable_fini -> dri3_free_render_buffer.


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Re: [Mesa-dev] [PATCH] glx/dri: Take an extra reference on our own GLX drawables

[Michel Dänzer]

On 2018-05-10 05:09 PM, Adam Jackson wrote:
> On Wed, 2018-05-09 at 18:17 +0200, Michel Dänzer wrote:
> 
>> How about the idea I described before, saving the loader_dri3_drawable
>> values in a hash table in dri3_screen? Maybe we could simply save a
>> pointer to the whole struct, after only freeing the renderbuffers.
> 
> That would also leak, less in absolute terms but the same big-O, for
> the same reasons.

Sure, but with the same number x of leaked objects, there's a difference
between leaking x times tens of bytes, or x times potentially megabytes.


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[Mesa-dev] [PATCH] radv: minor cleanups in radv_fill_shader_variant()

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_shader.c | 29 +++--
 1 file changed, 15 insertions(+), 14 deletions(-)

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 27b3fbed16d..07634870d4f 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -371,6 +371,7 @@ radv_fill_shader_variant(struct radv_device *device,
 gl_shader_stage stage)
 {
bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
+   struct radv_shader_info *info = >info.info;
unsigned vgpr_comp_cnt = 0;
 
if (scratch_enabled && !device->llvm_supports_spill)
@@ -378,9 +379,9 @@ radv_fill_shader_variant(struct radv_device *device,
 
variant->code_size = binary->code_size;
variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
-   S_00B12C_SCRATCH_EN(scratch_enabled);
+S_00B12C_SCRATCH_EN(scratch_enabled);
 
-   variant->rsrc1 =  S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
+   variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
S_00B848_DX10_CLAMP(1) |
S_00B848_FLOAT_MODE(variant->config.float_mode);
@@ -391,10 +392,11 @@ radv_fill_shader_variant(struct radv_device *device,
variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
break;
case MESA_SHADER_TESS_CTRL:
-   if (device->physical_device->rad_info.chip_class >= GFX9)
+   if (device->physical_device->rad_info.chip_class >= GFX9) {
vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
-   else
+   } else {
variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
+   }
break;
case MESA_SHADER_VERTEX:
case MESA_SHADER_GEOMETRY:
@@ -402,8 +404,7 @@ radv_fill_shader_variant(struct radv_device *device,
break;
case MESA_SHADER_FRAGMENT:
break;
-   case MESA_SHADER_COMPUTE: {
-   struct radv_shader_info *info = >info.info;
+   case MESA_SHADER_COMPUTE:
variant->rsrc2 |=
S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
@@ -413,7 +414,6 @@ radv_fill_shader_variant(struct radv_device *device,
S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) 
|
S_00B84C_LDS_SIZE(variant->config.lds_size);
break;
-   }
default:
unreachable("unsupported shader type");
break;
@@ -421,7 +421,6 @@ radv_fill_shader_variant(struct radv_device *device,
 
if (device->physical_device->rad_info.chip_class >= GFX9 &&
stage == MESA_SHADER_GEOMETRY) {
-   struct radv_shader_info *info = >info.info;
unsigned es_type = variant->info.gs.es_type;
unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
 
@@ -436,23 +435,25 @@ radv_fill_shader_variant(struct radv_device *device,
/* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
 * VGPR[0:4] are always loaded.
 */
-   if (info->uses_invocation_id)
+   if (info->uses_invocation_id) {
gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
-   else if (info->uses_prim_id)
+   } else if (info->uses_prim_id) {
gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
-   else if (variant->info.gs.vertices_in >= 3)
+   } else if (variant->info.gs.vertices_in >= 3) {
gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
-   else
+   } else {
gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
+   }
 
variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
  S_00B22C_OC_LDS_EN(es_type == 
MESA_SHADER_TESS_EVAL);
} else if (device->physical_device->rad_info.chip_class >= GFX9 &&
-   stage == MESA_SHADER_TESS_CTRL)
+  stage == MESA_SHADER_TESS_CTRL) {
variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
-   else
+   } else {
variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
+   }
 
void *ptr = radv_alloc_shader_memory(device, variant);
memcpy(ptr, binary->code, binary->code_size);
-- 
2.17.0

___
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mesa-dev@lists.freedesktop.org

[Mesa-dev] [PATCH] radv: move ac_build_if_state on top of radv_nir_to_llvm.c

[Samuel Pitoiset]

These helpers will be needed for future work.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_nir_to_llvm.c | 183 +++---
 1 file changed, 92 insertions(+), 91 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index cee3558215d..725fdb07a4d 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -130,6 +130,98 @@ radv_shader_context_from_abi(struct ac_shader_abi *abi)
return container_of(abi, ctx, abi);
 }
 
+struct ac_build_if_state
+{
+   struct radv_shader_context *ctx;
+   LLVMValueRef condition;
+   LLVMBasicBlockRef entry_block;
+   LLVMBasicBlockRef true_block;
+   LLVMBasicBlockRef false_block;
+   LLVMBasicBlockRef merge_block;
+};
+
+static LLVMBasicBlockRef
+ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
+{
+   LLVMBasicBlockRef current_block;
+   LLVMBasicBlockRef next_block;
+   LLVMBasicBlockRef new_block;
+
+   /* get current basic block */
+   current_block = LLVMGetInsertBlock(ctx->ac.builder);
+
+   /* chqeck if there's another block after this one */
+   next_block = LLVMGetNextBasicBlock(current_block);
+   if (next_block) {
+   /* insert the new block before the next block */
+   new_block = LLVMInsertBasicBlockInContext(ctx->context, 
next_block, name);
+   }
+   else {
+   /* append new block after current block */
+   LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
+   new_block = LLVMAppendBasicBlockInContext(ctx->context, 
function, name);
+   }
+   return new_block;
+}
+
+static void
+ac_nir_build_if(struct ac_build_if_state *ifthen,
+   struct radv_shader_context *ctx,
+   LLVMValueRef condition)
+{
+   LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
+
+   memset(ifthen, 0, sizeof *ifthen);
+   ifthen->ctx = ctx;
+   ifthen->condition = condition;
+   ifthen->entry_block = block;
+
+   /* create endif/merge basic block for the phi functions */
+   ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
+
+   /* create/insert true_block before merge_block */
+   ifthen->true_block =
+   LLVMInsertBasicBlockInContext(ctx->context,
+ ifthen->merge_block,
+ "if-true-block");
+
+   /* successive code goes into the true block */
+   LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
+}
+
+/**
+ * End a conditional.
+ */
+static void
+ac_nir_build_endif(struct ac_build_if_state *ifthen)
+{
+   LLVMBuilderRef builder = ifthen->ctx->ac.builder;
+
+   /* Insert branch to the merge block from current block */
+   LLVMBuildBr(builder, ifthen->merge_block);
+
+   /*
+* Now patch in the various branch instructions.
+*/
+
+   /* Insert the conditional branch instruction at the end of entry_block 
*/
+   LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
+   if (ifthen->false_block) {
+   /* we have an else clause */
+   LLVMBuildCondBr(builder, ifthen->condition,
+   ifthen->true_block, ifthen->false_block);
+   }
+   else {
+   /* no else clause */
+   LLVMBuildCondBr(builder, ifthen->condition,
+   ifthen->true_block, ifthen->merge_block);
+   }
+
+   /* Resume building code at end of the ifthen->merge_block */
+   LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
+}
+
+
 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
 {
switch (ctx->stage) {
@@ -2555,97 +2647,6 @@ handle_ls_outputs_post(struct radv_shader_context *ctx)
}
 }
 
-struct ac_build_if_state
-{
-   struct radv_shader_context *ctx;
-   LLVMValueRef condition;
-   LLVMBasicBlockRef entry_block;
-   LLVMBasicBlockRef true_block;
-   LLVMBasicBlockRef false_block;
-   LLVMBasicBlockRef merge_block;
-};
-
-static LLVMBasicBlockRef
-ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
-{
-   LLVMBasicBlockRef current_block;
-   LLVMBasicBlockRef next_block;
-   LLVMBasicBlockRef new_block;
-
-   /* get current basic block */
-   current_block = LLVMGetInsertBlock(ctx->ac.builder);
-
-   /* chqeck if there's another block after this one */
-   next_block = LLVMGetNextBasicBlock(current_block);
-   if (next_block) {
-   /* insert the new block before the next block */
-   new_block = LLVMInsertBasicBlockInContext(ctx->context, 
next_block, name);
-   }
-   else {
-   /* append new block after current block */
-   LLVMValueRef function =