Re: [Mesa-dev] [PATCH] gallivm: Detect VSX separately from Altivec

[Roland Scheidegger]

u_cpu_detect should detect what's really available, not what is used
(though indeed we actually disable u_cpu bits explicitly in gallivm for
some sse features, but this is a hack).
So I think it would be better if u_cpu_detect sets the has_vsx bit
regardless what the env var is and then enable it based on this bit and
the env var.
Otherwise looks good to me.

Roland

Am 19.08.2018 um 23:17 schrieb Vicki Pfau:
> Previously gallivm would attempt to use VSX instructions on all systems
> where it detected that Altivec is supported; however, VSX was added to
> POWER long after Altivec, causing lots of crashes on older POWER/PPC
> hardware, e.g. PPC Macs. By detecting VSX separately from Altivec we can
> automatically disable it on hardware that supports Altivec but not VSX
> 
> Signed-off-by: Vicki Pfau 
> ---
>  src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 21 +++
>  src/gallium/auxiliary/util/u_cpu_detect.c | 14 -
>  src/gallium/auxiliary/util/u_cpu_detect.h |  1 +
>  3 files changed, 17 insertions(+), 19 deletions(-)
> 
> diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp 
> b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
> index 79dbedbb56..fcbdd5050f 100644
> --- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
> +++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
> @@ -650,26 +650,11 @@ 
> lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
>  * which are fixed in LLVM 4.0.
>  *
>  * With LLVM 4.0 or higher:
> -* Make sure VSX instructions are ENABLED, unless
> -* a) the entire -mattr option is overridden via GALLIVM_MATTRS, or
> -* b) VSX instructions are explicitly enabled/disabled via GALLIVM_VSX=1 
> or 0.
> +* Make sure VSX instructions are ENABLED (if supported), unless
> +* VSX instructions are explicitly enabled/disabled via GALLIVM_VSX=1 or 
> 0.
>  */
> if (util_cpu_caps.has_altivec) {
> -  char *env_mattrs = getenv("GALLIVM_MATTRS");
> -  if (env_mattrs) {
> - MAttrs.push_back(env_mattrs);
> -  }
> -  else {
> - boolean enable_vsx = true;
> - char *env_vsx = getenv("GALLIVM_VSX");
> - if (env_vsx && env_vsx[0] == '0') {
> -enable_vsx = false;
> - }
> - if (enable_vsx)
> -MAttrs.push_back("+vsx");
> - else
> -MAttrs.push_back("-vsx");
> -  }
> +  MAttrs.push_back(util_cpu_caps.has_vsx ? "+vsx" : "-vsx");
> }
>  #endif
>  #endif
> diff --git a/src/gallium/auxiliary/util/u_cpu_detect.c 
> b/src/gallium/auxiliary/util/u_cpu_detect.c
> index 3c6ae4ea1a..14003aa769 100644
> --- a/src/gallium/auxiliary/util/u_cpu_detect.c
> +++ b/src/gallium/auxiliary/util/u_cpu_detect.c
> @@ -133,6 +133,7 @@ check_os_altivec_support(void)
>signal(SIGILL, SIG_DFL);
> } else {
>boolean enable_altivec = TRUE;/* Default: enable  if available, 
> and if not overridden */
> +  boolean enable_vsx = TRUE;
>  #ifdef DEBUG
>/* Disabling Altivec code generation is not the same as disabling VSX 
> code generation,
> * which can be done simply by passing -mattr=-vsx to the LLVM 
> compiler; cf.
> @@ -144,6 +145,11 @@ check_os_altivec_support(void)
>   enable_altivec = FALSE;
>}
>  #endif
> +  /* VSX instructions can be explicitly enabled/disabled via 
> GALLIVM_VSX=1 or 0 */
> +  char *env_vsx = getenv("GALLIVM_VSX");
> +  if (env_vsx && env_vsx[0] == '0') {
> + enable_vsx = FALSE;
> +  }
>if (enable_altivec) {
>   __lv_powerpc_canjump = 1;
>  
> @@ -153,8 +159,13 @@ check_os_altivec_support(void)
>   :
>   : "r" (-1));
>  
> - signal(SIGILL, SIG_DFL);
>   util_cpu_caps.has_altivec = 1;
> +
> + if (enable_vsx) {
> +__asm __volatile("xxland %vs0, %vs0, %vs0");
> +util_cpu_caps.has_vsx = 1;
> + }
> + signal(SIGILL, SIG_DFL);
>} else {
>   util_cpu_caps.has_altivec = 0;
>}
> @@ -536,6 +547,7 @@ util_cpu_detect(void)
>debug_printf("util_cpu_caps.has_3dnow_ext = %u\n", 
> util_cpu_caps.has_3dnow_ext);
>debug_printf("util_cpu_caps.has_xop = %u\n", util_cpu_caps.has_xop);
>debug_printf("util_cpu_caps.has_altivec = %u\n", 
> util_cpu_caps.has_altivec);
> +  debug_printf("util_cpu_caps.has_vsx = %u\n", util_cpu_caps.has_vsx);
>debug_printf("util_cpu_caps.has_neon = %u\n", util_cpu_caps.has_neon);
>debug_printf("util_cpu_caps.has_daz = %u\n", util_cpu_caps.has_daz);
>debug_printf("util_cpu_caps.has_avx512f = %u\n", 
> util_cpu_caps.has_avx512f);
> diff --git a/src/gallium/auxiliary/util/u_cpu_detect.h 
> b/src/gallium/auxiliary/util/u_cpu_detect.h
> index 7a63d55028..19f5567ca7 100644
> --- a/src/gallium/auxiliary/util/u_cpu_detect.h
> +++ b/src/gallium/auxiliary/util/u_cpu_detect.h
> @@ -71,6 +71,7 @@ struct util_cpu_caps {
> unsigned has_3dnow_ext:1;
>  

Re: [Mesa-dev] [PATCH 1/5] anv/lower_ycbcr: Use the binding array size for bounds checks

[Dylan Baker]

Quoting Jason Ekstrand (2018-08-08 01:12:49)
> Because lower_ycbcr gets called before apply_pipeline_layout, the
> indices are all logical and the binding layout HW size is actually too
> big for the bounds check.  We should just use the regular logical array
> size instead.
> 
> Fixes: f3e91e78a33 "anv: add nir lowering pass for ycbcr textures"
> ---
>  src/intel/vulkan/anv_nir_lower_ycbcr_textures.c | 10 --
>  1 file changed, 4 insertions(+), 6 deletions(-)
> 
> diff --git a/src/intel/vulkan/anv_nir_lower_ycbcr_textures.c 
> b/src/intel/vulkan/anv_nir_lower_ycbcr_textures.c
> index 5a971d9be39..71e511f34b7 100644
> --- a/src/intel/vulkan/anv_nir_lower_ycbcr_textures.c
> +++ b/src/intel/vulkan/anv_nir_lower_ycbcr_textures.c
> @@ -340,18 +340,16 @@ try_lower_tex_ycbcr(struct anv_pipeline_layout *layout,
> if (binding->immutable_samplers == NULL)
>return false;
>  
> -   unsigned texture_index = tex->texture_index;
> +   assert(tex->texture_index == 0);
> +   unsigned array_index = 0;
> if (deref->deref_type != nir_deref_type_var) {
>assert(deref->deref_type == nir_deref_type_array);
>nir_const_value *const_index = 
> nir_src_as_const_value(deref->arr.index);
>if (!const_index)
>   return false;
> -  size_t hw_binding_size =
> - anv_descriptor_set_binding_layout_get_hw_size(binding);
> -  texture_index += MIN2(const_index->u32[0], hw_binding_size - 1);
> +  array_index = MIN2(const_index->u32[0], binding->array_size - 1);
> }
> -   const struct anv_sampler *sampler =
> -  binding->immutable_samplers[texture_index];
> +   const struct anv_sampler *sampler = 
> binding->immutable_samplers[array_index];
>  
> if (sampler->conversion == NULL)
>return false;
> -- 
> 2.17.1
> 

Hi Jason,

f3e91e78a33 is present in 18.1, but this patch doesn't apply cleanly due to (I
think) your rework of how derefs work in NIR. Do you want to backport this patch
to 18.1, or just drop it?

Thanks,
Dylan


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[Mesa-dev] [PATCH] gallivm: Detect VSX separately from Altivec

[Vicki Pfau]

Previously gallivm would attempt to use VSX instructions on all systems
where it detected that Altivec is supported; however, VSX was added to
POWER long after Altivec, causing lots of crashes on older POWER/PPC
hardware, e.g. PPC Macs. By detecting VSX separately from Altivec we can
automatically disable it on hardware that supports Altivec but not VSX

Signed-off-by: Vicki Pfau 
---
 src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 21 +++
 src/gallium/auxiliary/util/u_cpu_detect.c | 14 -
 src/gallium/auxiliary/util/u_cpu_detect.h |  1 +
 3 files changed, 17 insertions(+), 19 deletions(-)

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp 
b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
index 79dbedbb56..fcbdd5050f 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
+++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
@@ -650,26 +650,11 @@ 
lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
 * which are fixed in LLVM 4.0.
 *
 * With LLVM 4.0 or higher:
-* Make sure VSX instructions are ENABLED, unless
-* a) the entire -mattr option is overridden via GALLIVM_MATTRS, or
-* b) VSX instructions are explicitly enabled/disabled via GALLIVM_VSX=1 or 
0.
+* Make sure VSX instructions are ENABLED (if supported), unless
+* VSX instructions are explicitly enabled/disabled via GALLIVM_VSX=1 or 0.
 */
if (util_cpu_caps.has_altivec) {
-  char *env_mattrs = getenv("GALLIVM_MATTRS");
-  if (env_mattrs) {
- MAttrs.push_back(env_mattrs);
-  }
-  else {
- boolean enable_vsx = true;
- char *env_vsx = getenv("GALLIVM_VSX");
- if (env_vsx && env_vsx[0] == '0') {
-enable_vsx = false;
- }
- if (enable_vsx)
-MAttrs.push_back("+vsx");
- else
-MAttrs.push_back("-vsx");
-  }
+  MAttrs.push_back(util_cpu_caps.has_vsx ? "+vsx" : "-vsx");
}
 #endif
 #endif
diff --git a/src/gallium/auxiliary/util/u_cpu_detect.c 
b/src/gallium/auxiliary/util/u_cpu_detect.c
index 3c6ae4ea1a..14003aa769 100644
--- a/src/gallium/auxiliary/util/u_cpu_detect.c
+++ b/src/gallium/auxiliary/util/u_cpu_detect.c
@@ -133,6 +133,7 @@ check_os_altivec_support(void)
   signal(SIGILL, SIG_DFL);
} else {
   boolean enable_altivec = TRUE;/* Default: enable  if available, and 
if not overridden */
+  boolean enable_vsx = TRUE;
 #ifdef DEBUG
   /* Disabling Altivec code generation is not the same as disabling VSX 
code generation,
* which can be done simply by passing -mattr=-vsx to the LLVM compiler; 
cf.
@@ -144,6 +145,11 @@ check_os_altivec_support(void)
  enable_altivec = FALSE;
   }
 #endif
+  /* VSX instructions can be explicitly enabled/disabled via GALLIVM_VSX=1 
or 0 */
+  char *env_vsx = getenv("GALLIVM_VSX");
+  if (env_vsx && env_vsx[0] == '0') {
+ enable_vsx = FALSE;
+  }
   if (enable_altivec) {
  __lv_powerpc_canjump = 1;
 
@@ -153,8 +159,13 @@ check_os_altivec_support(void)
  :
  : "r" (-1));
 
- signal(SIGILL, SIG_DFL);
  util_cpu_caps.has_altivec = 1;
+
+ if (enable_vsx) {
+__asm __volatile("xxland %vs0, %vs0, %vs0");
+util_cpu_caps.has_vsx = 1;
+ }
+ signal(SIGILL, SIG_DFL);
   } else {
  util_cpu_caps.has_altivec = 0;
   }
@@ -536,6 +547,7 @@ util_cpu_detect(void)
   debug_printf("util_cpu_caps.has_3dnow_ext = %u\n", 
util_cpu_caps.has_3dnow_ext);
   debug_printf("util_cpu_caps.has_xop = %u\n", util_cpu_caps.has_xop);
   debug_printf("util_cpu_caps.has_altivec = %u\n", 
util_cpu_caps.has_altivec);
+  debug_printf("util_cpu_caps.has_vsx = %u\n", util_cpu_caps.has_vsx);
   debug_printf("util_cpu_caps.has_neon = %u\n", util_cpu_caps.has_neon);
   debug_printf("util_cpu_caps.has_daz = %u\n", util_cpu_caps.has_daz);
   debug_printf("util_cpu_caps.has_avx512f = %u\n", 
util_cpu_caps.has_avx512f);
diff --git a/src/gallium/auxiliary/util/u_cpu_detect.h 
b/src/gallium/auxiliary/util/u_cpu_detect.h
index 7a63d55028..19f5567ca7 100644
--- a/src/gallium/auxiliary/util/u_cpu_detect.h
+++ b/src/gallium/auxiliary/util/u_cpu_detect.h
@@ -71,6 +71,7 @@ struct util_cpu_caps {
unsigned has_3dnow_ext:1;
unsigned has_xop:1;
unsigned has_altivec:1;
+   unsigned has_vsx:1;
unsigned has_daz:1;
unsigned has_neon:1;
 
-- 
2.18.0

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Re: [Mesa-dev] [PATCH] travis: make drivers explicit in Meson targets

[Juan A. Suarez Romero]

On Mon, 2018-08-20 at 12:06 +0200, Juan A. Suarez Romero wrote:
> On Tue, 2018-08-14 at 11:00 +0100, Emil Velikov wrote:
> > On 8 August 2018 at 15:36, Juan A. Suarez Romero  
> > wrote:
> > > Like in the autotools target, make the list of drivers to be built in
> > > each of the Meson targets explicit.
> > > 
> > > This will help to identify missing dependencies and other issues more
> > > easily.
> > > 
> > > CC: Emil Velikov 
> > 
> > Thanks Juan! Sorry for missing this :-(
> > 
> > Do you know, which meson version got the ability to have the driver
> > list, without the square brackets?
> 
> 
> I think from the very beginning
> 

Emil, is this patch R-b for you?

J.A.

> 
> > -Emil
> > 
> 
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[Mesa-dev] [PATCH] i965/batch: don't ignore the 'brw_new_batch' call for a 'new batch'

[asimiklit . work]

From: Andrii Simiklit 

If we restore the 'new batch' using 'intel_batchbuffer_reset_to_saved'
function we must restore the default state of the batch using
'brw_new_batch' function because the 'intel_batchbuffer_flush'
function will not do it for the 'new batch' again.
At least the following fields of the batch
'state_base_address_emitted','aperture_space', 'state_used'
should be restored to default values to avoid:
1. the aperture_space overflow
2. the missed STATE_BASE_ADDRESS commad in the batch
3. the memory overconsumption of the 'statebuffer'
   due to uncleared 'state_used' field.
etc.

Signed-off-by: Andrii Simiklit 
---
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 104 +++---
 1 file changed, 59 insertions(+), 45 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 65d2c64..b8c5fb4 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -219,7 +219,7 @@ add_exec_bo(struct intel_batchbuffer *batch, struct brw_bo 
*bo)
bo->index = batch->exec_count;
batch->exec_bos[batch->exec_count] = bo;
batch->aperture_space += bo->size;
-
+   assert((batch->aperture_space >= 0) && "error 'batch->aperture_space' field 
is overflown!");
return batch->exec_count++;
 }
 
@@ -290,6 +290,51 @@ intel_batchbuffer_reset_and_clear_render_cache(struct 
brw_context *brw)
brw_cache_sets_clear(brw);
 }
 
+/**
+ * Called when starting a new batch buffer.
+ */
+static void
+brw_new_batch(struct brw_context *brw)
+{
+   /* Unreference any BOs held by the previous batch, and reset counts. */
+   for (int i = 0; i < brw->batch.exec_count; i++) {
+  brw_bo_unreference(brw->batch.exec_bos[i]);
+  brw->batch.exec_bos[i] = NULL;
+   }
+   brw->batch.batch_relocs.reloc_count = 0;
+   brw->batch.state_relocs.reloc_count = 0;
+   brw->batch.exec_count = 0;
+   brw->batch.aperture_space = 0;
+
+   brw_bo_unreference(brw->batch.state.bo);
+
+   /* Create a new batchbuffer and reset the associated state: */
+   intel_batchbuffer_reset_and_clear_render_cache(brw);
+
+   /* If the kernel supports hardware contexts, then most hardware state is
+* preserved between batches; we only need to re-emit state that is required
+* to be in every batch.  Otherwise we need to re-emit all the state that
+* would otherwise be stored in the context (which for all intents and
+* purposes means everything).
+*/
+   if (brw->hw_ctx == 0) {
+  brw->ctx.NewDriverState |= BRW_NEW_CONTEXT;
+  brw_upload_invariant_state(brw);
+   }
+
+   brw->ctx.NewDriverState |= BRW_NEW_BATCH;
+
+   brw->ib.index_size = -1;
+
+   /* We need to periodically reap the shader time results, because rollover
+* happens every few seconds.  We also want to see results every once in a
+* while, because many programs won't cleanly destroy our context, so the
+* end-of-run printout may not happen.
+*/
+   if (INTEL_DEBUG & DEBUG_SHADER_TIME)
+  brw_collect_and_report_shader_time(brw);
+}
+
 void
 intel_batchbuffer_save_state(struct brw_context *brw)
 {
@@ -311,6 +356,19 @@ intel_batchbuffer_reset_to_saved(struct brw_context *brw)
brw->batch.exec_count = brw->batch.saved.exec_count;
 
brw->batch.map_next = brw->batch.saved.map_next;
+   if (USED_BATCH(brw->batch) == 0)
+   {
+  /**
+   * The 'intel_batchbuffer_flush' function will not call
+   * the 'brw_new_batch' function when the USED_BATCH returns 0.
+   * It may leads to the few following issue:
+   * The 'aperture_space' field can be overflown
+   * The 'statebuffer' buffer contains the big unused space
+   * The STATE_BASE_ADDRESS message is missed
+   * etc
+   **/
+  brw_new_batch(brw);
+   }
 }
 
 void
@@ -529,50 +587,6 @@ intel_batchbuffer_require_space(struct brw_context *brw, 
GLuint sz)
}
 }
 
-/**
- * Called when starting a new batch buffer.
- */
-static void
-brw_new_batch(struct brw_context *brw)
-{
-   /* Unreference any BOs held by the previous batch, and reset counts. */
-   for (int i = 0; i < brw->batch.exec_count; i++) {
-  brw_bo_unreference(brw->batch.exec_bos[i]);
-  brw->batch.exec_bos[i] = NULL;
-   }
-   brw->batch.batch_relocs.reloc_count = 0;
-   brw->batch.state_relocs.reloc_count = 0;
-   brw->batch.exec_count = 0;
-   brw->batch.aperture_space = 0;
-
-   brw_bo_unreference(brw->batch.state.bo);
-
-   /* Create a new batchbuffer and reset the associated state: */
-   intel_batchbuffer_reset_and_clear_render_cache(brw);
-
-   /* If the kernel supports hardware contexts, then most hardware state is
-* preserved between batches; we only need to re-emit state that is required
-* to be in every batch.  Otherwise we need to re-emit all the state that
-* would otherwise be stored in the context (which for all intents and
-* purposes means everything).
-*/
-   if (brw->hw_ctx == 0) {
-  

[Mesa-dev] [PATCH] i965/batch: don't ignore the 'brw_new_batch' call for a 'new batch'

[asimiklit . work]

From: Andrii Simiklit 

If we restore the 'new batch' using 'intel_batchbuffer_reset_to_saved'
function we must restore the default state of the batch using
'brw_new_batch' function because the 'intel_batchbuffer_flush'
function will not do it for the 'new batch' again.
At least the following fields of the batch
'state_base_address_emitted','aperture_space', 'state_used'
should be restored to default values to avoid:
1. the aperture_space overflow
2. the missed STATE_BASE_ADDRESS commad in the batch
3. the memory overconsumption of the 'statebuffer'
   due to uncleared 'state_used' field.
etc.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107626
Signed-off-by: Andrii Simiklit 
---
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 104 +++---
 1 file changed, 59 insertions(+), 45 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 65d2c64..b8c5fb4 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -219,7 +219,7 @@ add_exec_bo(struct intel_batchbuffer *batch, struct brw_bo 
*bo)
bo->index = batch->exec_count;
batch->exec_bos[batch->exec_count] = bo;
batch->aperture_space += bo->size;
-
+   assert((batch->aperture_space >= 0) && "error 'batch->aperture_space' field 
is overflown!");
return batch->exec_count++;
 }
 
@@ -290,6 +290,51 @@ intel_batchbuffer_reset_and_clear_render_cache(struct 
brw_context *brw)
brw_cache_sets_clear(brw);
 }
 
+/**
+ * Called when starting a new batch buffer.
+ */
+static void
+brw_new_batch(struct brw_context *brw)
+{
+   /* Unreference any BOs held by the previous batch, and reset counts. */
+   for (int i = 0; i < brw->batch.exec_count; i++) {
+  brw_bo_unreference(brw->batch.exec_bos[i]);
+  brw->batch.exec_bos[i] = NULL;
+   }
+   brw->batch.batch_relocs.reloc_count = 0;
+   brw->batch.state_relocs.reloc_count = 0;
+   brw->batch.exec_count = 0;
+   brw->batch.aperture_space = 0;
+
+   brw_bo_unreference(brw->batch.state.bo);
+
+   /* Create a new batchbuffer and reset the associated state: */
+   intel_batchbuffer_reset_and_clear_render_cache(brw);
+
+   /* If the kernel supports hardware contexts, then most hardware state is
+* preserved between batches; we only need to re-emit state that is required
+* to be in every batch.  Otherwise we need to re-emit all the state that
+* would otherwise be stored in the context (which for all intents and
+* purposes means everything).
+*/
+   if (brw->hw_ctx == 0) {
+  brw->ctx.NewDriverState |= BRW_NEW_CONTEXT;
+  brw_upload_invariant_state(brw);
+   }
+
+   brw->ctx.NewDriverState |= BRW_NEW_BATCH;
+
+   brw->ib.index_size = -1;
+
+   /* We need to periodically reap the shader time results, because rollover
+* happens every few seconds.  We also want to see results every once in a
+* while, because many programs won't cleanly destroy our context, so the
+* end-of-run printout may not happen.
+*/
+   if (INTEL_DEBUG & DEBUG_SHADER_TIME)
+  brw_collect_and_report_shader_time(brw);
+}
+
 void
 intel_batchbuffer_save_state(struct brw_context *brw)
 {
@@ -311,6 +356,19 @@ intel_batchbuffer_reset_to_saved(struct brw_context *brw)
brw->batch.exec_count = brw->batch.saved.exec_count;
 
brw->batch.map_next = brw->batch.saved.map_next;
+   if (USED_BATCH(brw->batch) == 0)
+   {
+  /**
+   * The 'intel_batchbuffer_flush' function will not call
+   * the 'brw_new_batch' function when the USED_BATCH returns 0.
+   * It may leads to the few following issue:
+   * The 'aperture_space' field can be overflown
+   * The 'statebuffer' buffer contains the big unused space
+   * The STATE_BASE_ADDRESS message is missed
+   * etc
+   **/
+  brw_new_batch(brw);
+   }
 }
 
 void
@@ -529,50 +587,6 @@ intel_batchbuffer_require_space(struct brw_context *brw, 
GLuint sz)
}
 }
 
-/**
- * Called when starting a new batch buffer.
- */
-static void
-brw_new_batch(struct brw_context *brw)
-{
-   /* Unreference any BOs held by the previous batch, and reset counts. */
-   for (int i = 0; i < brw->batch.exec_count; i++) {
-  brw_bo_unreference(brw->batch.exec_bos[i]);
-  brw->batch.exec_bos[i] = NULL;
-   }
-   brw->batch.batch_relocs.reloc_count = 0;
-   brw->batch.state_relocs.reloc_count = 0;
-   brw->batch.exec_count = 0;
-   brw->batch.aperture_space = 0;
-
-   brw_bo_unreference(brw->batch.state.bo);
-
-   /* Create a new batchbuffer and reset the associated state: */
-   intel_batchbuffer_reset_and_clear_render_cache(brw);
-
-   /* If the kernel supports hardware contexts, then most hardware state is
-* preserved between batches; we only need to re-emit state that is required
-* to be in every batch.  Otherwise we need to re-emit all the state that
-* would otherwise be stored in the context (which for all intents and
-* purposes means everything).

Re: [Mesa-dev] [Mesa-stable] [PATCH v4 1/2] wayland/egl: initialize window surface size to window size

[Juan A. Suarez Romero]

On Thu, 2018-08-09 at 09:03 -0700, Dylan Baker wrote:
> Quoting Juan A. Suarez Romero (2018-08-07 08:49:36)
> > When creating a windows surface with eglCreateWindowSurface(), the
> > width and height returned by eglQuerySurface(EGL_{WIDTH,HEIGHT}) is
> > invalid until buffers are updated (like calling glClear()).
> > 
> > But according to EGL 1.5 spec, section 3.5.6 ("Surface Attributes"):
> > 
> >   "Querying EGL_WIDTH and EGL_HEIGHT returns respectively the width and
> >height, in pixels, of the surface. For a window or pixmap surface,
> >these values are initially equal to the width and height of the
> >native window or pixmap with respect to which the surface was
> >created"
> > 
> > This fixes dEQP-EGL.functional.color_clears.* CTS tests
> > 
> > v2:
> > - Do not modify attached_{width,height} (Daniel)
> > - Do not update size on resizing window (Brendan)
> > 
> > CC: Daniel Stone 
> > CC: Brendan King 
> > CC: mesa-sta...@lists.freedesktop.org
> > Tested-by: Eric Engestrom 
> > ---
> >  src/egl/drivers/dri2/platform_wayland.c | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/src/egl/drivers/dri2/platform_wayland.c 
> > b/src/egl/drivers/dri2/platform_wayland.c
> > index dca099500a8..a5d43094cf3 100644
> > --- a/src/egl/drivers/dri2/platform_wayland.c
> > +++ b/src/egl/drivers/dri2/platform_wayland.c
> > @@ -258,6 +258,9 @@ dri2_wl_create_window_surface(_EGLDriver *drv, 
> > _EGLDisplay *disp,
> >goto cleanup_surf;
> > }
> >  
> > +   dri2_surf->base.Width = window->width;
> > +   dri2_surf->base.Height = window->height;
> > +
> > visual_idx = dri2_wl_visual_idx_from_config(dri2_dpy, config);
> > assert(visual_idx != -1);
> >  
> > -- 
> > 2.17.1
> > 
> 
> Hi Juan,
> 
> There was a minor conflict when I pulled this into staging/18.1, I'm pretty
> confident that I resolved it correctly, but if you wouldn't mind taking a look
> I'd appreciate it.
> 

Sorry for answering late. The patch seems good for me. Thanks!


J.A.

> Thanks,
> Dylan

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[Mesa-dev] [PATCH] autotools: include git_sha1.h in dist tarball

[Juan A. Suarez Romero]

This fixes `make distcheck`.

Fixes: 471f708ed6 ("git_sha1: simplify logic")
CC: Eric Engestrom 
---
 src/Makefile.am | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/Makefile.am b/src/Makefile.am
index 396865cbe55..412510f435b 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -26,7 +26,7 @@ git_sha1.h:
 
 BUILT_SOURCES = git_sha1.h
 CLEANFILES = $(BUILT_SOURCES)
-EXTRA_DIST = git_sha1.h.in meson.build
+EXTRA_DIST = git_sha1.h meson.build
 
 SUBDIRS = . gtest util mapi/glapi/gen mapi
 
-- 
2.17.1

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[Mesa-dev] [Bug 107224] Incorrect Rendering in Deus Ex: Mankind Divided in-game menu

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107224

--- Comment #10 from Alex Smith  ---
We've just released a game data update that should fix this issue for both AMD
and Intel, as well as a shader compilation failure on 18.2. It should be
applied next time you launch the game (it's handled outside of Steam, will be
automatically downloaded at startup).

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Re: [Mesa-dev] [PATCH] Add NV_fragment_shader_interlock support.

[Kevin Rogovin]

Hi Plamena,

 Thankyou for the fast review. Can you push it or have someone push it? (I
do not have push rights)

-Keviv

On Mon, Aug 20, 2018, 2:50 PM Manolova, Plamena 
wrote:

> Hi Kevin,
> This looks good to me :)
>
> Reviewed-by: Plamena Manolova 
>
> On Wed, Aug 15, 2018 at 2:29 PM,  wrote:
>
>> From: Kevin Rogovin 
>>
>> The main purpose for having NV_fragment_shader_interlock
>> extension is because that extension is also for GLES31 while
>> the ARB extension is for GL only.
>> ---
>>  src/compiler/glsl/builtin_functions.cpp  | 18 ++
>>  src/compiler/glsl/glsl_parser.yy |  6 --
>>  src/compiler/glsl/glsl_parser_extras.cpp |  1 +
>>  src/compiler/glsl/glsl_parser_extras.h   |  2 ++
>>  src/mesa/main/extensions_table.h |  1 +
>>  5 files changed, 26 insertions(+), 2 deletions(-)
>>
>> diff --git a/src/compiler/glsl/builtin_functions.cpp
>> b/src/compiler/glsl/builtin_functions.cpp
>> index 7119903795..e7b78c0158 100644
>> --- a/src/compiler/glsl/builtin_functions.cpp
>> +++ b/src/compiler/glsl/builtin_functions.cpp
>> @@ -519,6 +519,12 @@ supports_arb_fragment_shader_interlock(const
>> _mesa_glsl_parse_state *state)
>> return state->ARB_fragment_shader_interlock_enable;
>>  }
>>
>> +static bool
>> +supports_nv_fragment_shader_interlock(const _mesa_glsl_parse_state
>> *state)
>> +{
>> +   return state->NV_fragment_shader_interlock_enable;
>> +}
>> +
>>  static bool
>>  shader_clock(const _mesa_glsl_parse_state *state)
>>  {
>> @@ -3331,6 +3337,18 @@ builtin_builder::create_builtins()
>> supports_arb_fragment_shader_interlock),
>>  NULL);
>>
>> +   add_function("beginInvocationInterlockNV",
>> +_invocation_interlock(
>> +   "__intrinsic_begin_invocation_interlock",
>> +   supports_nv_fragment_shader_interlock),
>> +NULL);
>> +
>> +   add_function("endInvocationInterlockNV",
>> +_invocation_interlock(
>> +   "__intrinsic_end_invocation_interlock",
>> +   supports_nv_fragment_shader_interlock),
>> +NULL);
>> +
>> add_function("anyInvocationARB",
>>  _vote("__intrinsic_vote_any", vote),
>>  NULL);
>> diff --git a/src/compiler/glsl/glsl_parser.yy
>> b/src/compiler/glsl/glsl_parser.yy
>> index cb7376995d..bc2571b684 100644
>> --- a/src/compiler/glsl/glsl_parser.yy
>> +++ b/src/compiler/glsl/glsl_parser.yy
>> @@ -1450,10 +1450,12 @@ layout_qualifier_id:
>>"only valid in fragment shader input layout
>> declaration.");
>>} else if (pixel_interlock_ordered + pixel_interlock_unordered +
>>   sample_interlock_ordered + sample_interlock_unordered >
>> 0 &&
>> - !state->ARB_fragment_shader_interlock_enable) {
>> + !state->ARB_fragment_shader_interlock_enable &&
>> + !state->NV_fragment_shader_interlock_enable) {
>>   _mesa_glsl_error(& @1, state,
>>"interlock layout qualifier present, but the "
>> -  "GL_ARB_fragment_shader_interlock extension is
>> not "
>> +  "GL_ARB_fragment_shader_interlock or "
>> +  "GL_NV_fragment_shader_interlock extension is
>> not "
>>"enabled.");
>>} else {
>>   $$.flags.q.pixel_interlock_ordered = pixel_interlock_ordered;
>> diff --git a/src/compiler/glsl/glsl_parser_extras.cpp
>> b/src/compiler/glsl/glsl_parser_extras.cpp
>> index 6d92f24ea2..393942b62c 100644
>> --- a/src/compiler/glsl/glsl_parser_extras.cpp
>> +++ b/src/compiler/glsl/glsl_parser_extras.cpp
>> @@ -724,6 +724,7 @@ static const _mesa_glsl_extension
>> _mesa_glsl_supported_extensions[] = {
>> EXT_AEP(EXT_texture_cube_map_array),
>> EXT(INTEL_conservative_rasterization),
>> EXT(MESA_shader_integer_functions),
>> +   EXT(NV_fragment_shader_interlock),
>> EXT(NV_image_formats),
>>  };
>>
>> diff --git a/src/compiler/glsl/glsl_parser_extras.h
>> b/src/compiler/glsl/glsl_parser_extras.h
>> index 59a173418b..3b17b54f0a 100644
>> --- a/src/compiler/glsl/glsl_parser_extras.h
>> +++ b/src/compiler/glsl/glsl_parser_extras.h
>> @@ -810,6 +810,8 @@ struct _mesa_glsl_parse_state {
>> bool INTEL_conservative_rasterization_warn;
>> bool MESA_shader_integer_functions_enable;
>> bool MESA_shader_integer_functions_warn;
>> +   bool NV_fragment_shader_interlock_enable;
>> +   bool NV_fragment_shader_interlock_warn;
>> bool NV_image_formats_enable;
>> bool NV_image_formats_warn;
>> /*@}*/
>> diff --git a/src/mesa/main/extensions_table.h
>> b/src/mesa/main/extensions_table.h
>> index af5ce118da..746e821886 100644
>> --- a/src/mesa/main/extensions_table.h
>> +++ b/src/mesa/main/extensions_table.h
>> @@ -346,6 +346,7 @@ EXT(NV_draw_buffers ,
>> dummy_true
>>  EXT(NV_fbo_color_attachments   

Re: [Mesa-dev] i915/swrast vertex array regression

[Ville Syrjälä]

On Fri, Aug 10, 2018 at 01:13:31PM +0200, Mathias Fröhlich wrote:
> Hi Ville,
> 
> > Looks like
> > "vid_gl20" "0"
> > is needed to reproduce the issue.
> 
> Thanks! Now I can observe the problem!
> And the attached patch seems to fix what I can observe here.
> Does the attached patch also fix the problem with the
> older intel chip you originally reported?

Seems to. Thanks for tracking it down.

Tested-by: Ville Syrjälä 

> 
> Thanks!
> 
> Mathias

> From 68e921478c8c38a13b7258e0d3f1f235709dcfe9 Mon Sep 17 00:00:00 2001
> From: =?UTF-8?q?Mathias=20Fr=C3=B6hlich?= 
> Date: Fri, 10 Aug 2018 11:37:43 +0200
> Subject: [PATCH] tnl: Fix green gun regression in xonotic.
> MIME-Version: 1.0
> Content-Type: text/plain; charset=UTF-8
> Content-Transfer-Encoding: 8bit
> 
> Signed-off-by: Mathias Fröhlich 
> ---
>  src/mesa/tnl/t_split_copy.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/mesa/tnl/t_split_copy.c b/src/mesa/tnl/t_split_copy.c
> index cbb7eb409f..085ae9a28c 100644
> --- a/src/mesa/tnl/t_split_copy.c
> +++ b/src/mesa/tnl/t_split_copy.c
> @@ -531,7 +531,7 @@ replay_init(struct copy_context *copy)
> for (offset = 0, i = 0; i < copy->nr_varying; i++) {
>const struct tnl_vertex_array *src = copy->varying[i].array;
>const struct gl_array_attributes *srcattr = src->VertexAttrib;
> -  struct tnl_vertex_array *dst = >dstarray[i];
> +  struct tnl_vertex_array *dst = >dstarray[copy->varying[i].attr];
>struct gl_vertex_buffer_binding *dstbind = 
> >varying[i].dstbinding;
>struct gl_array_attributes *dstattr = >varying[i].dstattribs;
>  
> -- 
> 2.17.1
> 


-- 
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Intel
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Re: [Mesa-dev] [PATCH 3/5] egl/android: remove droid_probe_driver()

[Emil Velikov]

On 13 August 2018 at 17:18, Tomasz Figa  wrote:
> On Tue, Aug 14, 2018 at 1:09 AM Emil Velikov  wrote:
>>
>> On 13 August 2018 at 16:43, Tomasz Figa  wrote:
>> > On Tue, Aug 14, 2018 at 12:35 AM Emil Velikov  
>> > wrote:
>> >>
>> >> On 13 August 2018 at 16:16, Tomasz Figa  wrote:
>> >> > Hi Emil,
>> >> >
>> >> > On Mon, Aug 13, 2018 at 11:48 PM Emil Velikov 
>> >> >  wrote:
>> >> >>
>> >> >> From: Emil Velikov 
>> >> >>
>> >> >> The function name is misleading - it effectively checks if
>> >> >> loader_get_driver_for_fd fails. Which can happen only only on strdup
>> >> >> error - a close to impossible scenario.
>> >> >
>> >> > How about a DRI node which doesn't have a driver in Mesa?
>> >> >
>> >> Can you elaborate a bit - are you thinking of any of the following or
>> >> something else:
>> >>  - no support for vendor X
>> >>  - supported vendor, missing vendor/device pci id for device X
>> >>  - supported vendor, built w/o it
>> >>
>> >> All these are fairly different cases, with somewhat different solution
>> >> for each one.
>> >
>> > Let's say "no support for vendor X", but supported vendor Y GPU next
>> > to it. We want this code to skip vendor X DRI node and choose vendor Y
>> > DRI node.
>> >
>> >>
>> >> Fwiw the function loader_get_driver_for_fd does:
>> >>  - gets the vendor/device pci id and maps that to a driver_name
>> >>  - if device not a pci device (or query fails) - fallback to the name
>> >> as returned in drmGetVersion
>> >
>> > Good catch. Looks like I misunderstood what it does when reviewing
>> > Rob's series and existing code doesn't work as I expected. I think it
>> > would just error out in the case above, right?
>> >
>> Determining if a device is "supported" is fairly subtle:
>> For example, even if you open the foo_dri.so the driver can fail due
>> to old kernel module, LLVM version, etc.
>> One solution is to continue loading up-to dri2_create_screen() - if it
>> fails fall-back to the next device.
>>
>> Any objections if I do that as follow-up patch, if you agree of course?
>
> Our downstream patch [1] actually loaded until
> dri2_load_driver(_dri3)() in probe, but if you think
> dri2_create_screen() could make more sense, I'm okay with it. Thanks.
>
Right, patch that does that can be seen here (copy in your inbox)
https://patchwork.freedesktop.org/patch/244276/

Can you Ack/R-b/T-b the series - I think all your concerns have been addressed.

https://patchwork.freedesktop.org/patch/244366/
https://patchwork.freedesktop.org/patch/244243/
https://patchwork.freedesktop.org/patch/244244/
https://patchwork.freedesktop.org/patch/244240/
https://patchwork.freedesktop.org/patch/244242/


Thanks
Emil
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[Mesa-dev] [PATCH] glsl/linker: Allow unused in blocks which are not declated on previous stage

[vadym.shovkoplias]

From Section 4.3.4 (Inputs) of the GLSL 1.50 spec:

"Only the input variables that are actually read need to be written
 by the previous stage; it is allowed to have superfluous
 declarations of input variables."

Fixes:
* interstage-multiple-shader-objects.shader_test

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101247
Signed-off-by: Vadym Shovkoplias 
---
 src/compiler/glsl/link_interface_blocks.cpp | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/compiler/glsl/link_interface_blocks.cpp 
b/src/compiler/glsl/link_interface_blocks.cpp
index e5eca9460e..801fbcd5d9 100644
--- a/src/compiler/glsl/link_interface_blocks.cpp
+++ b/src/compiler/glsl/link_interface_blocks.cpp
@@ -417,9 +417,15 @@ validate_interstage_inout_blocks(struct gl_shader_program 
*prog,
* write to any of the pre-defined outputs (e.g. if the vertex shader
* does not write to gl_Position, etc), which is allowed and results in
* undefined behavior.
+   *
+   * From Section 4.3.4 (Inputs) of the GLSL 1.50 spec:
+   *
+   *"Only the input variables that are actually read need to be written
+   * by the previous stage; it is allowed to have superfluous
+   * declarations of input variables."
*/
   if (producer_def == NULL &&
-  !is_builtin_gl_in_block(var, consumer->Stage)) {
+  !is_builtin_gl_in_block(var, consumer->Stage) && var->data.used) {
  linker_error(prog, "Input block `%s' is not an output of "
   "the previous stage\n", var->get_interface_type()->name);
  return;
-- 
2.18.0

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Re: [Mesa-dev] [PATCH] i965: Advertise 8 bits subpixel precision for viewport bounds on gen6+

[Danylo Piliaiev]

On 8/20/18 4:28 PM, Lionel Landwerlin wrote:

Reviewed-by: Lionel Landwerlin 

Thanks!


Do you need me to push it?

Yes


Thanks,

-
Lionel

On 08/08/18 16:03, Danylo Piliaiev wrote:

Hi,

Since the exact value is not important for users,  Roland offered 
compelling explanation

and the value is also 8 on Windows - could the patch be reviewed/pushed?

- Danil

On 06/19/2018 03:44 PM, Roland Scheidegger wrote:

My guess would be 8 because that's what the rasterization subpixel
precision is, so precision beyond that doesn't really do much, even if
this actually is a float.
Plus, with maximum sized fb (16kx16k dimension) you don't actually
really get a lot more than 8 fixed points bits anyway (near those 16k).
So imho 8 makes most sense.

Roland


Am 19.06.2018 um 10:35 schrieb danylo:

Hi Lionel,

Indeed the value 8 here is questionable. I picked it because other
drivers advertise the same value e.g. in Mesa radeon returns 8 for gl
and vulkan or on Windows Intel's driver returns 8. But why 8? It's 
some

kind of mystery.


"If the implementation truely has floating point viewport bounds, it
may report a sufficiently high value to indicate this. "
8 seems to be a sufficiently high value (it seems if someone even 
checks

the value it's going like 'precision > 0' - it is used as a flag). But
still it's probably not good enough argument...

Floating point (IEEE 754) has 24 bits of significand precision, in 
other
way - 6 to 9 significant decimal digits. And drivers return 8, the 
only

8 in float-point is 8 exponent bits.

Unless someone knows why 8, there two paths:

   * Left it to be 8 - be the same as other drivers
   * Make 24 - to reflect 24 bits of significand precision of float


- Danil


On 18.06.18 17:27, Lionel Landwerlin wrote:

Hey Danylo,

Thanks for this patch.
I'm not really an expert here but my understanding is that it should
reflect the number of bits in fixed point precision.
We use 32bits floats in the packets sent to the hardware.
Quoting the spec :

"If the implementation truely has floating point viewport bounds, it
may report a sufficiently high value to indicate this. "

Maybe we should use something a bit bigger than 8?

Cheers,

-
Lionel

On 18/06/18 13:50, Danylo Piliaiev wrote:

We use floating-points for viewport bounds so VIEWPORT_SUBPIXEL_BITS
should reflect this.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105975

Signed-off-by: Danylo Piliaiev 
---
  src/mesa/drivers/dri/i965/brw_context.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c

index 9ced230..eacf326 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -688,7 +688,7 @@ brw_initialize_context_constants(struct 
brw_context *brw)

 /* ARB_viewport_array, OES_viewport_array */
 if (devinfo->gen >= 6) {
    ctx->Const.MaxViewports = GEN6_NUM_VIEWPORTS;
-  ctx->Const.ViewportSubpixelBits = 0;
+  ctx->Const.ViewportSubpixelBits = 8;
      /* Cast to float before negating because 
MaxViewportWidth is unsigned.

 */





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Re: [Mesa-dev] [PATCH] i965: Advertise 8 bits subpixel precision for viewport bounds on gen6+

[Lionel Landwerlin]

Reviewed-by: Lionel Landwerlin 

Do you need me to push it?

Thanks,

-
Lionel

On 08/08/18 16:03, Danylo Piliaiev wrote:

Hi,

Since the exact value is not important for users,  Roland offered 
compelling explanation

and the value is also 8 on Windows - could the patch be reviewed/pushed?

- Danil

On 06/19/2018 03:44 PM, Roland Scheidegger wrote:

My guess would be 8 because that's what the rasterization subpixel
precision is, so precision beyond that doesn't really do much, even if
this actually is a float.
Plus, with maximum sized fb (16kx16k dimension) you don't actually
really get a lot more than 8 fixed points bits anyway (near those 16k).
So imho 8 makes most sense.

Roland


Am 19.06.2018 um 10:35 schrieb danylo:

Hi Lionel,

Indeed the value 8 here is questionable. I picked it because other
drivers advertise the same value e.g. in Mesa radeon returns 8 for gl
and vulkan or on Windows Intel's driver returns 8. But why 8? It's some
kind of mystery.


"If the implementation truely has floating point viewport bounds, it
may report a sufficiently high value to indicate this. "
8 seems to be a sufficiently high value (it seems if someone even 
checks

the value it's going like 'precision > 0' - it is used as a flag). But
still it's probably not good enough argument...

Floating point (IEEE 754) has 24 bits of significand precision, in 
other

way - 6 to 9 significant decimal digits. And drivers return 8, the only
8 in float-point is 8 exponent bits.

Unless someone knows why 8, there two paths:

   * Left it to be 8 - be the same as other drivers
   * Make 24 - to reflect 24 bits of significand precision of float


- Danil


On 18.06.18 17:27, Lionel Landwerlin wrote:

Hey Danylo,

Thanks for this patch.
I'm not really an expert here but my understanding is that it should
reflect the number of bits in fixed point precision.
We use 32bits floats in the packets sent to the hardware.
Quoting the spec :

"If the implementation truely has floating point viewport bounds, it
may report a sufficiently high value to indicate this. "

Maybe we should use something a bit bigger than 8?

Cheers,

-
Lionel

On 18/06/18 13:50, Danylo Piliaiev wrote:

We use floating-points for viewport bounds so VIEWPORT_SUBPIXEL_BITS
should reflect this.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105975

Signed-off-by: Danylo Piliaiev 
---
  src/mesa/drivers/dri/i965/brw_context.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c

index 9ced230..eacf326 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -688,7 +688,7 @@ brw_initialize_context_constants(struct 
brw_context *brw)

 /* ARB_viewport_array, OES_viewport_array */
 if (devinfo->gen >= 6) {
    ctx->Const.MaxViewports = GEN6_NUM_VIEWPORTS;
-  ctx->Const.ViewportSubpixelBits = 0;
+  ctx->Const.ViewportSubpixelBits = 8;
      /* Cast to float before negating because 
MaxViewportWidth is unsigned.

 */





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[Mesa-dev] [Bug 106630] radv: LLVM ERROR: Pointer address space out of range (bisected)

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106630

Samuel Pitoiset  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

--- Comment #3 from Samuel Pitoiset  ---
Fixed with https://llvm.org/viewvc/llvm-project?view=revision=340171

I will request a backport for LLVM 7.

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Re: [Mesa-dev] [PATCH 1/2] intel/fs: New method for register_byte_use_pattern for fs_inst

[Chema Casanova]

El 29/07/18 a las 19:47, Chema Casanova escribió:
> El 28/07/18 a las 01:45, Francisco Jerez escribió:
>> Chema Casanova  writes:

[...]

> If we have a partial write/read:
>
> I understood that you my initial patter proposal would only be ok for
> the first GRF of src[i]/dst (reg_offset == 0)
>
> periodic_mask(this->exec_size,   /* count */
>this->src[i].stride * type_sz(this->src[i].type), /*step */
>type_sz(this->src[i].type),   /* bits */
>this->src[i].offset % REG_SIZE);  /* offset */
>
> In the case we manage only reg_offset == 0 we get a huge improvement
> reducing all problems many of the register_pressure we have now on all
> SIMD8 shaders with 8/16bits test cases.
>
> I understood that you didn't agree that for cases where src/destination
> use more than 1 GRF (reg_offset == 1) we can not guarantee that we can
> apply the same internal offset (this->src[i].offset % REG_SIZE) as the
> base register to calculate a patter. So It would be better to return ~0u
> on reads or 0u in writes.
>
>>>
 Yes, but you could easily determine whether the mask is going to be
 invariant with respect to reg_offset (where reg_offset is within bounds)
 and in that case return the periodic_mask() expression above, otherwise
 return 0/~0u depending on whether reg_offset is within bounds.
>>>
>>> Ok, so we are within bounds, we don't have a predicated write, we are
>>> not a send message. Then we have an ALU opcode and we return the
>>> periodic_mask.
>>>
>>
>> Those are all necessary but not sufficient conditions for the
>> periodic_mask() expression above to give you the correct answer for any
>> in-bounds reg_offset > 0, you should check that byte_offset < type_size
>> * stride in addition.
> 
> That's true. Fixed in v5.
> 
> If we don't satisfy the condition then we return 0 on writes and ~0u on
> reads.

Could you have a look at the v5 to check if I can count with your R-b ?

https://patchwork.freedesktop.org/patch/241482/

I suppose you didn't have time to have a look at the other patch of the
series.

"[v2,2/2] intel/fs: Improve liveness range calculation for partial writes"
https://patchwork.freedesktop.org/patch/239839/

Thanks in advance,

Chema

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[Mesa-dev] [PATCH 4/4] virgl: add debug-switch to output TGSI

[Erik Faye-Lund]

This is quite useful for debugging shader-transpiling issues in
virglrenderer.

Signed-off-by: Erik Faye-Lund 
---
 src/gallium/drivers/virgl/virgl_encode.c | 3 +++
 src/gallium/drivers/virgl/virgl_screen.c | 1 +
 src/gallium/drivers/virgl/virgl_screen.h | 1 +
 3 files changed, 5 insertions(+)

diff --git a/src/gallium/drivers/virgl/virgl_encode.c 
b/src/gallium/drivers/virgl/virgl_encode.c
index ea544fe5cd..4e99dda0f7 100644
--- a/src/gallium/drivers/virgl/virgl_encode.c
+++ b/src/gallium/drivers/virgl/virgl_encode.c
@@ -274,6 +274,9 @@ int virgl_encode_shader_state(struct virgl_context *ctx,
if (bret == false)
   return -1;
 
+   if (virgl_debug & VIRGL_DEBUG_TGSI)
+  debug_printf("TGSI:\n---8<---\n%s\n---8<---\n", str);
+
shader_len = strlen(str) + 1;
 
left_bytes = shader_len;
diff --git a/src/gallium/drivers/virgl/virgl_screen.c 
b/src/gallium/drivers/virgl/virgl_screen.c
index 61147c423c..d9b50c9cca 100644
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -39,6 +39,7 @@
 int virgl_debug = 0;
 static const struct debug_named_value debug_options[] = {
{ "verbose", VIRGL_DEBUG_VERBOSE, NULL },
+   { "tgsi", VIRGL_DEBUG_TGSI, NULL },
DEBUG_NAMED_VALUE_END
 };
 DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug, "VIRGL_DEBUG", debug_options, 0)
diff --git a/src/gallium/drivers/virgl/virgl_screen.h 
b/src/gallium/drivers/virgl/virgl_screen.h
index 8334d16242..719f5166d7 100644
--- a/src/gallium/drivers/virgl/virgl_screen.h
+++ b/src/gallium/drivers/virgl/virgl_screen.h
@@ -28,6 +28,7 @@
 #include "virgl_winsys.h"
 
 #define VIRGL_DEBUG_VERBOSE 1
+#define VIRGL_DEBUG_TGSI2
 extern int virgl_debug;
 
 struct virgl_screen {
-- 
2.17.1

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[Mesa-dev] [PATCH 3/4] virgl: introduce $VIRGL_DEBUG=verbose

[Erik Faye-Lund]

This adds an environment-varaible that can be used for driver-specific
flags, as well as a flag for it to enable verbose output.

While we're at it, quiet some overly chatty debug-output by default.

Signed-off-by: Erik Faye-Lund 
---
 src/gallium/drivers/virgl/virgl_context.c | 6 --
 src/gallium/drivers/virgl/virgl_encode.c  | 3 ++-
 src/gallium/drivers/virgl/virgl_screen.c  | 9 +
 src/gallium/drivers/virgl/virgl_screen.h  | 3 +++
 4 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_context.c 
b/src/gallium/drivers/virgl/virgl_context.c
index dc1dd2d3c2..edc03f5dcf 100644
--- a/src/gallium/drivers/virgl/virgl_context.c
+++ b/src/gallium/drivers/virgl/virgl_context.c
@@ -1115,8 +1115,10 @@ static void virgl_get_sample_position(struct 
pipe_context *ctx,
}
out_value[0] = ((bits >> 4) & 0xf) / 16.0f;
out_value[1] = (bits & 0xf) / 16.0f;
-   debug_printf("VIRGL: sample postion [%2d/%2d] = (%f, %f)\n",
-   index, sample_count, out_value[0], out_value[1]);
+
+   if (virgl_debug & VIRGL_DEBUG_VERBOSE)
+  debug_printf("VIRGL: sample postion [%2d/%2d] = (%f, %f)\n",
+   index, sample_count, out_value[0], out_value[1]);
 }
 
 struct pipe_context *virgl_context_create(struct pipe_screen *pscreen,
diff --git a/src/gallium/drivers/virgl/virgl_encode.c 
b/src/gallium/drivers/virgl/virgl_encode.c
index 6b0077ac0c..ea544fe5cd 100644
--- a/src/gallium/drivers/virgl/virgl_encode.c
+++ b/src/gallium/drivers/virgl/virgl_encode.c
@@ -261,7 +261,8 @@ int virgl_encode_shader_state(struct virgl_context *ctx,
 
   bret = tgsi_dump_str(tokens, TGSI_DUMP_FLOAT_AS_HEX, str, 
str_total_size);
   if (bret == false) {
- debug_printf("Failed to translate shader in available space - trying 
again\n");
+ if (virgl_debug & VIRGL_DEBUG_VERBOSE)
+debug_printf("Failed to translate shader in available space - 
trying again\n");
  old_size = str_total_size;
  str_total_size = 65536 * ++retry_size;
  str = REALLOC(str, old_size, str_total_size);
diff --git a/src/gallium/drivers/virgl/virgl_screen.c 
b/src/gallium/drivers/virgl/virgl_screen.c
index 86063c66aa..61147c423c 100644
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -36,6 +36,13 @@
 #include "virgl_public.h"
 #include "virgl_context.h"
 
+int virgl_debug = 0;
+static const struct debug_named_value debug_options[] = {
+   { "verbose", VIRGL_DEBUG_VERBOSE, NULL },
+   DEBUG_NAMED_VALUE_END
+};
+DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug, "VIRGL_DEBUG", debug_options, 0)
+
 static const char *
 virgl_get_vendor(struct pipe_screen *screen)
 {
@@ -724,6 +731,8 @@ virgl_create_screen(struct virgl_winsys *vws)
if (!screen)
   return NULL;
 
+   virgl_debug = debug_get_option_virgl_debug();
+
screen->vws = vws;
screen->base.get_name = virgl_get_name;
screen->base.get_vendor = virgl_get_vendor;
diff --git a/src/gallium/drivers/virgl/virgl_screen.h 
b/src/gallium/drivers/virgl/virgl_screen.h
index dcf5816d60..8334d16242 100644
--- a/src/gallium/drivers/virgl/virgl_screen.h
+++ b/src/gallium/drivers/virgl/virgl_screen.h
@@ -27,6 +27,9 @@
 #include "util/slab.h"
 #include "virgl_winsys.h"
 
+#define VIRGL_DEBUG_VERBOSE 1
+extern int virgl_debug;
+
 struct virgl_screen {
struct pipe_screen base;
 
-- 
2.17.1

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[Mesa-dev] [PATCH 2/4] virgl: replace fprintf-call with debug_printf

[Erik Faye-Lund]

This is the only direct call-site for fprintf in virgl; all other
call-sites call debug_printf instead. So let's follow in style here.

Signed-off-by: Erik Faye-Lund 
---
 src/gallium/drivers/virgl/virgl_encode.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/virgl/virgl_encode.c 
b/src/gallium/drivers/virgl/virgl_encode.c
index 190c338f45..6b0077ac0c 100644
--- a/src/gallium/drivers/virgl/virgl_encode.c
+++ b/src/gallium/drivers/virgl/virgl_encode.c
@@ -261,7 +261,7 @@ int virgl_encode_shader_state(struct virgl_context *ctx,
 
   bret = tgsi_dump_str(tokens, TGSI_DUMP_FLOAT_AS_HEX, str, 
str_total_size);
   if (bret == false) {
- fprintf(stderr, "Failed to translate shader in available space - 
trying again\n");
+ debug_printf("Failed to translate shader in available space - trying 
again\n");
  old_size = str_total_size;
  str_total_size = 65536 * ++retry_size;
  str = REALLOC(str, old_size, str_total_size);
-- 
2.17.1

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[Mesa-dev] [PATCH 0/4] virgl: debug printing cleanups

[Erik Faye-Lund]

Here's some patches that cleans up debug-printing in virgl a bit, by
using the existing debug environment-variable infrastructure so things
can be turned on and off explicitly.

This version introduce two flags:
- verbose: enables verbose output. This is useful to get information on
  some internal details, which would usually be overly chatty.
- tgsi: outputs the textual TGSI representation. This is useful for
  debugging virglrenderer when it's often useful to see what TGSI
  triggered for instance a malformed shader.

Both of these are flags for the VIRGL_DEBUG environement variable.

Erik Faye-Lund (4):
  virgl: delete commented out fprintf-call
  virgl: replace fprintf-call with debug_printf
  virgl: introduce $VIRGL_DEBUG=verbose
  virgl: add debug-switch to output TGSI

 src/gallium/drivers/virgl/virgl_context.c |  6 --
 src/gallium/drivers/virgl/virgl_encode.c  |  6 +-
 src/gallium/drivers/virgl/virgl_encode.h  |  1 -
 src/gallium/drivers/virgl/virgl_screen.c  | 10 ++
 src/gallium/drivers/virgl/virgl_screen.h  |  4 
 5 files changed, 23 insertions(+), 4 deletions(-)

-- 
2.17.1

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[Mesa-dev] [PATCH 1/4] virgl: delete commented out fprintf-call

[Erik Faye-Lund]

This is just debug-cruft left over. Let's just get rid of it.

Signed-off-by: Erik Faye-Lund 
---
 src/gallium/drivers/virgl/virgl_encode.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/gallium/drivers/virgl/virgl_encode.h 
b/src/gallium/drivers/virgl/virgl_encode.h
index 749cd33012..999123f426 100644
--- a/src/gallium/drivers/virgl/virgl_encode.h
+++ b/src/gallium/drivers/virgl/virgl_encode.h
@@ -70,7 +70,6 @@ static inline void virgl_encoder_write_block(struct 
virgl_cmd_buf *state,
int x;
memcpy(state->buf + state->cdw, ptr, len);
x = (len % 4);
-//   fprintf(stderr, "[%d] block %d x is %d\n", state->cdw, len, x);
if (x) {
   uint8_t *mp = (uint8_t *)(state->buf + state->cdw);
   mp += len;
-- 
2.17.1

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Re: [Mesa-dev] [PATCH 3/4] virgl: introduce $VIRGL_DEBUG=verbose

[Erik Faye-Lund]

Sorry, made a mistake when sending this series out. I'll resend 
properly soon.


On Mon, Aug 20, 2018 at 2:03 PM, Erik Faye-Lund 
 wrote:

This adds an environment-varaible that can be used for driver-specific
flags, as well as a flag for it to enable verbose output.

While we're at it, quiet some overly chatty debug-output by default.

Signed-off-by: Erik Faye-Lund 
---
 src/gallium/drivers/virgl/virgl_context.c | 6 --
 src/gallium/drivers/virgl/virgl_encode.c  | 3 ++-
 src/gallium/drivers/virgl/virgl_screen.c  | 9 +
 src/gallium/drivers/virgl/virgl_screen.h  | 3 +++
 4 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_context.c 
b/src/gallium/drivers/virgl/virgl_context.c

index dc1dd2d3c2..edc03f5dcf 100644
--- a/src/gallium/drivers/virgl/virgl_context.c
+++ b/src/gallium/drivers/virgl/virgl_context.c
@@ -1115,8 +1115,10 @@ static void virgl_get_sample_position(struct 
pipe_context *ctx,

}
out_value[0] = ((bits >> 4) & 0xf) / 16.0f;
out_value[1] = (bits & 0xf) / 16.0f;
-   debug_printf("VIRGL: sample postion [%2d/%2d] = (%f, %f)\n",
-   index, sample_count, out_value[0], out_value[1]);
+
+   if (virgl_debug & VIRGL_DEBUG_VERBOSE)
+  debug_printf("VIRGL: sample postion [%2d/%2d] = (%f, %f)\n",
+   index, sample_count, out_value[0], out_value[1]);
 }

 struct pipe_context *virgl_context_create(struct pipe_screen 
*pscreen,
diff --git a/src/gallium/drivers/virgl/virgl_encode.c 
b/src/gallium/drivers/virgl/virgl_encode.c

index 6b0077ac0c..ea544fe5cd 100644
--- a/src/gallium/drivers/virgl/virgl_encode.c
+++ b/src/gallium/drivers/virgl/virgl_encode.c
@@ -261,7 +261,8 @@ int virgl_encode_shader_state(struct 
virgl_context *ctx,


   bret = tgsi_dump_str(tokens, TGSI_DUMP_FLOAT_AS_HEX, str, 
str_total_size);

   if (bret == false) {
- debug_printf("Failed to translate shader in available space 
- trying again\n");

+ if (virgl_debug & VIRGL_DEBUG_VERBOSE)
+debug_printf("Failed to translate shader in available 
space - trying again\n");

  old_size = str_total_size;
  str_total_size = 65536 * ++retry_size;
  str = REALLOC(str, old_size, str_total_size);
diff --git a/src/gallium/drivers/virgl/virgl_screen.c 
b/src/gallium/drivers/virgl/virgl_screen.c

index 86063c66aa..61147c423c 100644
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -36,6 +36,13 @@
 #include "virgl_public.h"
 #include "virgl_context.h"

+int virgl_debug = 0;
+static const struct debug_named_value debug_options[] = {
+   { "verbose", VIRGL_DEBUG_VERBOSE, NULL },
+   DEBUG_NAMED_VALUE_END
+};
+DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug, "VIRGL_DEBUG", 
debug_options, 0)

+
 static const char *
 virgl_get_vendor(struct pipe_screen *screen)
 {
@@ -724,6 +731,8 @@ virgl_create_screen(struct virgl_winsys *vws)
if (!screen)
   return NULL;

+   virgl_debug = debug_get_option_virgl_debug();
+
screen->vws = vws;
screen->base.get_name = virgl_get_name;
screen->base.get_vendor = virgl_get_vendor;
diff --git a/src/gallium/drivers/virgl/virgl_screen.h 
b/src/gallium/drivers/virgl/virgl_screen.h

index dcf5816d60..8334d16242 100644
--- a/src/gallium/drivers/virgl/virgl_screen.h
+++ b/src/gallium/drivers/virgl/virgl_screen.h
@@ -27,6 +27,9 @@
 #include "util/slab.h"
 #include "virgl_winsys.h"

+#define VIRGL_DEBUG_VERBOSE 1
+extern int virgl_debug;
+
 struct virgl_screen {
struct pipe_screen base;

--
2.17.1

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[Mesa-dev] [PATCH 1/4] virgl: delete commented out fprintf-call

[Erik Faye-Lund]

This is just debug-cruft left over. Let's just get rid of it.

Signed-off-by: Erik Faye-Lund 
---
 src/gallium/drivers/virgl/virgl_encode.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/gallium/drivers/virgl/virgl_encode.h 
b/src/gallium/drivers/virgl/virgl_encode.h
index 749cd33012..999123f426 100644
--- a/src/gallium/drivers/virgl/virgl_encode.h
+++ b/src/gallium/drivers/virgl/virgl_encode.h
@@ -70,7 +70,6 @@ static inline void virgl_encoder_write_block(struct 
virgl_cmd_buf *state,
int x;
memcpy(state->buf + state->cdw, ptr, len);
x = (len % 4);
-//   fprintf(stderr, "[%d] block %d x is %d\n", state->cdw, len, x);
if (x) {
   uint8_t *mp = (uint8_t *)(state->buf + state->cdw);
   mp += len;
-- 
2.17.1

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[Mesa-dev] [PATCH 2/4] virgl: replace fprintf-call with debug_printf

[Erik Faye-Lund]

This is the only direct call-site for fprintf in virgl; all other
call-sites call debug_printf instead. So let's follow in style here.

Signed-off-by: Erik Faye-Lund 
---
 src/gallium/drivers/virgl/virgl_encode.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/virgl/virgl_encode.c 
b/src/gallium/drivers/virgl/virgl_encode.c
index 190c338f45..6b0077ac0c 100644
--- a/src/gallium/drivers/virgl/virgl_encode.c
+++ b/src/gallium/drivers/virgl/virgl_encode.c
@@ -261,7 +261,7 @@ int virgl_encode_shader_state(struct virgl_context *ctx,
 
   bret = tgsi_dump_str(tokens, TGSI_DUMP_FLOAT_AS_HEX, str, 
str_total_size);
   if (bret == false) {
- fprintf(stderr, "Failed to translate shader in available space - 
trying again\n");
+ debug_printf("Failed to translate shader in available space - trying 
again\n");
  old_size = str_total_size;
  str_total_size = 65536 * ++retry_size;
  str = REALLOC(str, old_size, str_total_size);
-- 
2.17.1

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[Mesa-dev] [PATCH 3/4] virgl: introduce $VIRGL_DEBUG=verbose

[Erik Faye-Lund]

This adds an environment-varaible that can be used for driver-specific
flags, as well as a flag for it to enable verbose output.

While we're at it, quiet some overly chatty debug-output by default.

Signed-off-by: Erik Faye-Lund 
---
 src/gallium/drivers/virgl/virgl_context.c | 6 --
 src/gallium/drivers/virgl/virgl_encode.c  | 3 ++-
 src/gallium/drivers/virgl/virgl_screen.c  | 9 +
 src/gallium/drivers/virgl/virgl_screen.h  | 3 +++
 4 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_context.c 
b/src/gallium/drivers/virgl/virgl_context.c
index dc1dd2d3c2..edc03f5dcf 100644
--- a/src/gallium/drivers/virgl/virgl_context.c
+++ b/src/gallium/drivers/virgl/virgl_context.c
@@ -1115,8 +1115,10 @@ static void virgl_get_sample_position(struct 
pipe_context *ctx,
}
out_value[0] = ((bits >> 4) & 0xf) / 16.0f;
out_value[1] = (bits & 0xf) / 16.0f;
-   debug_printf("VIRGL: sample postion [%2d/%2d] = (%f, %f)\n",
-   index, sample_count, out_value[0], out_value[1]);
+
+   if (virgl_debug & VIRGL_DEBUG_VERBOSE)
+  debug_printf("VIRGL: sample postion [%2d/%2d] = (%f, %f)\n",
+   index, sample_count, out_value[0], out_value[1]);
 }
 
 struct pipe_context *virgl_context_create(struct pipe_screen *pscreen,
diff --git a/src/gallium/drivers/virgl/virgl_encode.c 
b/src/gallium/drivers/virgl/virgl_encode.c
index 6b0077ac0c..ea544fe5cd 100644
--- a/src/gallium/drivers/virgl/virgl_encode.c
+++ b/src/gallium/drivers/virgl/virgl_encode.c
@@ -261,7 +261,8 @@ int virgl_encode_shader_state(struct virgl_context *ctx,
 
   bret = tgsi_dump_str(tokens, TGSI_DUMP_FLOAT_AS_HEX, str, 
str_total_size);
   if (bret == false) {
- debug_printf("Failed to translate shader in available space - trying 
again\n");
+ if (virgl_debug & VIRGL_DEBUG_VERBOSE)
+debug_printf("Failed to translate shader in available space - 
trying again\n");
  old_size = str_total_size;
  str_total_size = 65536 * ++retry_size;
  str = REALLOC(str, old_size, str_total_size);
diff --git a/src/gallium/drivers/virgl/virgl_screen.c 
b/src/gallium/drivers/virgl/virgl_screen.c
index 86063c66aa..61147c423c 100644
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -36,6 +36,13 @@
 #include "virgl_public.h"
 #include "virgl_context.h"
 
+int virgl_debug = 0;
+static const struct debug_named_value debug_options[] = {
+   { "verbose", VIRGL_DEBUG_VERBOSE, NULL },
+   DEBUG_NAMED_VALUE_END
+};
+DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug, "VIRGL_DEBUG", debug_options, 0)
+
 static const char *
 virgl_get_vendor(struct pipe_screen *screen)
 {
@@ -724,6 +731,8 @@ virgl_create_screen(struct virgl_winsys *vws)
if (!screen)
   return NULL;
 
+   virgl_debug = debug_get_option_virgl_debug();
+
screen->vws = vws;
screen->base.get_name = virgl_get_name;
screen->base.get_vendor = virgl_get_vendor;
diff --git a/src/gallium/drivers/virgl/virgl_screen.h 
b/src/gallium/drivers/virgl/virgl_screen.h
index dcf5816d60..8334d16242 100644
--- a/src/gallium/drivers/virgl/virgl_screen.h
+++ b/src/gallium/drivers/virgl/virgl_screen.h
@@ -27,6 +27,9 @@
 #include "util/slab.h"
 #include "virgl_winsys.h"
 
+#define VIRGL_DEBUG_VERBOSE 1
+extern int virgl_debug;
+
 struct virgl_screen {
struct pipe_screen base;
 
-- 
2.17.1

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[Mesa-dev] [PATCH v1] configure/vulkan: linking issue of Vulkan

[Sergii Romantsov]

Installing of Vulkan on Ubuntu 16.04 fails during relinking.
Seems caught libtool-issue.
Library-dependicies GL_LIB_DEPS moved upper.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107624
Signed-off-by: Sergii Romantsov 
---
 src/glx/Makefile.am | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/glx/Makefile.am b/src/glx/Makefile.am
index 8f9d80c..bb30a85 100644
--- a/src/glx/Makefile.am
+++ b/src/glx/Makefile.am
@@ -176,10 +176,10 @@ endif
 # against the system one.
 GL_LIBS = \
$(LIBDRM_LIBS) \
+   $(GL_LIB_DEPS) \
libglx.la \
$(top_builddir)/src/mapi/glapi/libglapi.la \
-   $(top_builddir)/src/mapi/shared-glapi/libglapi.la \
-   $(GL_LIB_DEPS)
+   $(top_builddir)/src/mapi/shared-glapi/libglapi.la
 
 GL_LDFLAGS = \
-no-undefined \
-- 
2.7.4

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Re: [Mesa-dev] [PATCH] Add NV_fragment_shader_interlock support.

[Manolova, Plamena]

Hi Kevin,
This looks good to me :)

Reviewed-by: Plamena Manolova 

On Wed, Aug 15, 2018 at 2:29 PM,  wrote:

> From: Kevin Rogovin 
>
> The main purpose for having NV_fragment_shader_interlock
> extension is because that extension is also for GLES31 while
> the ARB extension is for GL only.
> ---
>  src/compiler/glsl/builtin_functions.cpp  | 18 ++
>  src/compiler/glsl/glsl_parser.yy |  6 --
>  src/compiler/glsl/glsl_parser_extras.cpp |  1 +
>  src/compiler/glsl/glsl_parser_extras.h   |  2 ++
>  src/mesa/main/extensions_table.h |  1 +
>  5 files changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/src/compiler/glsl/builtin_functions.cpp
> b/src/compiler/glsl/builtin_functions.cpp
> index 7119903795..e7b78c0158 100644
> --- a/src/compiler/glsl/builtin_functions.cpp
> +++ b/src/compiler/glsl/builtin_functions.cpp
> @@ -519,6 +519,12 @@ supports_arb_fragment_shader_interlock(const
> _mesa_glsl_parse_state *state)
> return state->ARB_fragment_shader_interlock_enable;
>  }
>
> +static bool
> +supports_nv_fragment_shader_interlock(const _mesa_glsl_parse_state
> *state)
> +{
> +   return state->NV_fragment_shader_interlock_enable;
> +}
> +
>  static bool
>  shader_clock(const _mesa_glsl_parse_state *state)
>  {
> @@ -3331,6 +3337,18 @@ builtin_builder::create_builtins()
> supports_arb_fragment_shader_interlock),
>  NULL);
>
> +   add_function("beginInvocationInterlockNV",
> +_invocation_interlock(
> +   "__intrinsic_begin_invocation_interlock",
> +   supports_nv_fragment_shader_interlock),
> +NULL);
> +
> +   add_function("endInvocationInterlockNV",
> +_invocation_interlock(
> +   "__intrinsic_end_invocation_interlock",
> +   supports_nv_fragment_shader_interlock),
> +NULL);
> +
> add_function("anyInvocationARB",
>  _vote("__intrinsic_vote_any", vote),
>  NULL);
> diff --git a/src/compiler/glsl/glsl_parser.yy
> b/src/compiler/glsl/glsl_parser.yy
> index cb7376995d..bc2571b684 100644
> --- a/src/compiler/glsl/glsl_parser.yy
> +++ b/src/compiler/glsl/glsl_parser.yy
> @@ -1450,10 +1450,12 @@ layout_qualifier_id:
>"only valid in fragment shader input layout
> declaration.");
>} else if (pixel_interlock_ordered + pixel_interlock_unordered +
>   sample_interlock_ordered + sample_interlock_unordered >
> 0 &&
> - !state->ARB_fragment_shader_interlock_enable) {
> + !state->ARB_fragment_shader_interlock_enable &&
> + !state->NV_fragment_shader_interlock_enable) {
>   _mesa_glsl_error(& @1, state,
>"interlock layout qualifier present, but the "
> -  "GL_ARB_fragment_shader_interlock extension is
> not "
> +  "GL_ARB_fragment_shader_interlock or "
> +  "GL_NV_fragment_shader_interlock extension is
> not "
>"enabled.");
>} else {
>   $$.flags.q.pixel_interlock_ordered = pixel_interlock_ordered;
> diff --git a/src/compiler/glsl/glsl_parser_extras.cpp
> b/src/compiler/glsl/glsl_parser_extras.cpp
> index 6d92f24ea2..393942b62c 100644
> --- a/src/compiler/glsl/glsl_parser_extras.cpp
> +++ b/src/compiler/glsl/glsl_parser_extras.cpp
> @@ -724,6 +724,7 @@ static const _mesa_glsl_extension
> _mesa_glsl_supported_extensions[] = {
> EXT_AEP(EXT_texture_cube_map_array),
> EXT(INTEL_conservative_rasterization),
> EXT(MESA_shader_integer_functions),
> +   EXT(NV_fragment_shader_interlock),
> EXT(NV_image_formats),
>  };
>
> diff --git a/src/compiler/glsl/glsl_parser_extras.h
> b/src/compiler/glsl/glsl_parser_extras.h
> index 59a173418b..3b17b54f0a 100644
> --- a/src/compiler/glsl/glsl_parser_extras.h
> +++ b/src/compiler/glsl/glsl_parser_extras.h
> @@ -810,6 +810,8 @@ struct _mesa_glsl_parse_state {
> bool INTEL_conservative_rasterization_warn;
> bool MESA_shader_integer_functions_enable;
> bool MESA_shader_integer_functions_warn;
> +   bool NV_fragment_shader_interlock_enable;
> +   bool NV_fragment_shader_interlock_warn;
> bool NV_image_formats_enable;
> bool NV_image_formats_warn;
> /*@}*/
> diff --git a/src/mesa/main/extensions_table.h
> b/src/mesa/main/extensions_table.h
> index af5ce118da..746e821886 100644
> --- a/src/mesa/main/extensions_table.h
> +++ b/src/mesa/main/extensions_table.h
> @@ -346,6 +346,7 @@ EXT(NV_draw_buffers ,
> dummy_true
>  EXT(NV_fbo_color_attachments, dummy_true
>,  x ,  x ,  x , ES2, 2010)
>  EXT(NV_fill_rectangle   , NV_fill_rectangle
> , GLL, GLC,  x ,  x , 2015)
>  EXT(NV_fog_distance , NV_fog_distance
> , GLL,  x ,  x ,  x , 2001)
> 

[Mesa-dev] [Bug 106590] Wrong line numbers expanded while compiling shaders

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106590

--- Comment #6 from Kenneth Graunke  ---
(In reply to Mark Janes from comment #5)
> This seems like a duplicate of 
> 
>  https://bugs.freedesktop.org/show_bug.cgi?id=106807
> 
> My faint recollection is that the specification of the __LINE__ macro is
> inconsistent.  If, as Ken says, this has been removed from the
> specification, why are we looking at patches to change the implementation?

No, __LINE__ is perfectly well defined and not going away.  #line directives to
alter the current line using expressions is going away.  I'm pretty sure
Zhaowei Yuan's patch fixes a real bug we've had for a long time.

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[Mesa-dev] [PATCH] appveyor: Set git core.autocrlf setting to true.

[Jose Fonseca]

The git core.autocrlf setting defaults to true (ie, all text files get
checked out as CRLF on Windows), except on Appveyor where's set to
"input" (ie, all text files get checked out with the upstream
repository's line endings, which for us typically means LF.)

And this was masking on Appveyor a regression in gen_xmlpool.py
processing t_options.h with CRLF line endings.

This change makes core.autocrlf to be true, which would have enabled to
immediately catch the issue, as seen in
https://ci.appveyor.com/project/jrfonseca/mesa/build/51
---
 appveyor.yml | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/appveyor.yml b/appveyor.yml
index 86440f0d76a..73be3c57df8 100644
--- a/appveyor.yml
+++ b/appveyor.yml
@@ -39,11 +39,18 @@ cache:
 
 os: Visual Studio 2015
 
+init:
+# Appveyor defaults core.autocrlf to input instead of the default (true), but
+# that can hide problems processing CRLF text on Windows
+- git config --global core.autocrlf true
+
 environment:
   WINFLEXBISON_ARCHIVE: win_flex_bison-2.5.9.zip
   LLVM_ARCHIVE: llvm-5.0.1-msvc2015-mtd.7z
 
 install:
+# Check git config
+- git config core.autocrlf
 # Check pip
 - python --version
 - python -m pip --version
-- 
2.17.1

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Re: [Mesa-dev] [PATCH v4] anv: add VK_EXT_sampler_filter_minmax support

[Lionel Landwerlin]

On 17/08/18 17:57, Yunchao He wrote:

This extension can be supported on SKL+. With this patch,
all corresponding tests (6K+) in CTS can pass. No test fails.

I verified CTS with the command below:
deqp-vk --deqp-case=dEQP-VK.pipeline.sampler.view_type.*reduce*

v2: 1) support all depth formats, not depth-only formats, 2) fix
a wrong indention (Jason).

v3: fix a few nits (Lionel).

v4: fix failures in CI: disable sampler reduction mode when compare
mode in sampler state is enabled (Lionel).
---
  src/intel/vulkan/anv_device.c  |  8 
  src/intel/vulkan/anv_extensions.py |  1 +
  src/intel/vulkan/anv_formats.c |  6 ++
  src/intel/vulkan/genX_state.c  | 26 ++
  4 files changed, 41 insertions(+)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 04fd6a829e..e45ba4b3af 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1116,6 +1116,14 @@ void anv_GetPhysicalDeviceProperties2(
   break;
}
  
+  case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {

+ VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
+(VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
+ properties->filterMinmaxImageComponentMapping = pdevice->info.gen >= 
9;
+ properties->filterMinmaxSingleComponentFormats = true;
+ break;
+  }
+
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
   VkPhysicalDeviceSubgroupProperties *properties = (void *)ext;
  
diff --git a/src/intel/vulkan/anv_extensions.py b/src/intel/vulkan/anv_extensions.py

index ea837744b4..e165bd371d 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -125,6 +125,7 @@ EXTENSIONS = [
  Extension('VK_EXT_shader_stencil_export', 1, 'device->info.gen 
>= 9'),
  Extension('VK_EXT_vertex_attribute_divisor',  2, True),
  Extension('VK_EXT_post_depth_coverage',   1, 'device->info.gen 
>= 9'),
+Extension('VK_EXT_sampler_filter_minmax', 1, 'device->info.gen 
>= 9'),
  ]
  
  class VkVersion:

diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 815b320a82..33faf7cc37 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -489,6 +489,9 @@ get_image_format_features(const struct gen_device_info 
*devinfo,
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT || devinfo->gen >= 8)
   flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;
  
+  if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && devinfo->gen >= 9)

+ flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT;
+
flags |= VK_FORMAT_FEATURE_BLIT_SRC_BIT |
 VK_FORMAT_FEATURE_BLIT_DST_BIT |
 VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR |
@@ -521,6 +524,9 @@ get_image_format_features(const struct gen_device_info 
*devinfo,
 if (isl_format_supports_sampling(devinfo, plane_format.isl_format)) {
flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;
  
+  if (devinfo->gen >= 9)

+ flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT;
+
if (isl_format_supports_filtering(devinfo, plane_format.isl_format))
   flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_LINEAR_BIT;
 }
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index b1014d9e79..cc64fe6d4a 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -245,6 +245,14 @@ static const uint32_t vk_to_gen_shadow_compare_op[] = {
 [VK_COMPARE_OP_ALWAYS]   = PREFILTEROPNEVER,
  };
  
+#if GEN_GEN >= 9

+static const uint32_t vk_to_gen_sampler_reduction_mode[] = {
+   [VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT] = STD_FILTER,
+   [VK_SAMPLER_REDUCTION_MODE_MIN_EXT]  = MINIMUM,
+   [VK_SAMPLER_REDUCTION_MODE_MAX_EXT]  = MAXIMUM,
+};
+#endif
+
  VkResult genX(CreateSampler)(
  VkDevice_device,
  const VkSamplerCreateInfo*  pCreateInfo,
@@ -266,6 +274,10 @@ VkResult genX(CreateSampler)(
 uint32_t border_color_offset = device->border_colors.offset +
pCreateInfo->borderColor * 64;
  
+#if GEN_GEN >= 9

+   unsigned sampler_reduction_mode = STD_FILTER;
+#endif
+
 vk_foreach_struct(ext, pCreateInfo->pNext) {
switch (ext->sType) {
case VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_INFO: {
@@ -281,6 +293,15 @@ VkResult genX(CreateSampler)(
   sampler->conversion = conversion;
   break;
}
+#if GEN_GEN >= 9
+  case VK_STRUCTURE_TYPE_SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT: {
+ struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
+(struct VkSamplerReductionModeCreateInfoEXT *) ext;
+ sampler_reduction_mode =
+

Re: [Mesa-dev] [RFC 5/7] anv/android: add ahardwarebuffer external memory properties

[Tapani Pälli]

On 08/17/2018 12:15 PM, Tapani Pälli wrote:

Signed-off-by: Tapani Pälli 
---
  src/intel/vulkan/anv_formats.c | 19 ++-
  1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index dc398306a70..f1506b8acbe 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -929,9 +929,11 @@ static const VkExternalMemoryProperties prime_fd_props = {
 .exportFromImportedHandleTypes =
VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT |
VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT,
+  VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID,
 .compatibleHandleTypes =
VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT |
-  VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT,
+  VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT |
+  VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID,
  };
  
  VkResult anv_GetPhysicalDeviceImageFormatProperties2(

@@ -943,6 +945,7 @@ VkResult anv_GetPhysicalDeviceImageFormatProperties2(
 const VkPhysicalDeviceExternalImageFormatInfo *external_info = NULL;
 VkExternalImageFormatPropertiesKHR *external_props = NULL;
 VkSamplerYcbcrConversionImageFormatProperties *ycbcr_props = NULL;
+   struct VkAndroidHardwareBufferUsageANDROID *android_usage = NULL;
 VkResult result;
  
 /* Extract input structs */

@@ -966,6 +969,9 @@ VkResult anv_GetPhysicalDeviceImageFormatProperties2(
case VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_IMAGE_FORMAT_PROPERTIES:
   ycbcr_props = (void *) s;
   break;
+  case VK_STRUCTURE_TYPE_ANDROID_HARDWARE_BUFFER_USAGE_ANDROID:
+ android_usage = (void *) s;
+ break;
default:
   anv_debug_ignored_stype(s->sType);
   break;
@@ -977,6 +983,14 @@ VkResult anv_GetPhysicalDeviceImageFormatProperties2(
 if (result != VK_SUCCESS)
goto fail;
  
+#ifdef ANDROID

+   if (android_usage) {
+  android_usage->androidHardwareBufferUsage =
+ AHARDWAREBUFFER_USAGE_GPU_SAMPLED_IMAGE |
+ AHARDWAREBUFFER_USAGE_GPU_COLOR_OUTPUT;
+   }
+#endif
+
 /* From the Vulkan 1.0.42 spec:
  *
  *If handleType is 0, vkGetPhysicalDeviceImageFormatProperties2 will
@@ -987,6 +1001,7 @@ VkResult anv_GetPhysicalDeviceImageFormatProperties2(
switch (external_info->handleType) {
case VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT:
case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
+  case VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID:
   if (external_props)
  external_props->externalMemoryProperties = prime_fd_props;
   break;
@@ -1070,6 +1085,8 @@ void anv_GetPhysicalDeviceExternalBufferProperties(
 switch (pExternalBufferInfo->handleType) {
 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT:
 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
+   case VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID:
+  /* TODO - for android, should we set 
VK_EXTERNAL_MEMORY_FEATURE_DEDICATED_ONLY_BIT for non-image buffers here? */


No we should not ... we should actually set it for images in 
GetPhysicalDeviceImageFormatProperties2 as specified in the spec.




pExternalBufferProperties->externalMemoryProperties = prime_fd_props;
return;
 default:



// Tapani
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[Mesa-dev] [Bug 103122] 17.1 and 17.2 glsl/tests/cache-test regression. 17.0.6 works.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103122

Timothy Arceri  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

--- Comment #2 from Timothy Arceri  ---
I believe we fixed the issues reported on gentoo. If not please reopen and link
to the downstream gentoo bug report. Thanks.

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Re: [Mesa-dev] [PATCH 06/22] nir/format_convert: Add vec mask and sign-extend helpers

[Kenneth Graunke]

On Friday, August 17, 2018 1:06:12 PM PDT Jason Ekstrand wrote:
> ---
>  src/compiler/nir/nir_format_convert.h | 35 +--
>  1 file changed, 27 insertions(+), 8 deletions(-)
> 
> diff --git a/src/compiler/nir/nir_format_convert.h 
> b/src/compiler/nir/nir_format_convert.h
> index b1345f7263b..305273cdfdd 100644
> --- a/src/compiler/nir/nir_format_convert.h
> +++ b/src/compiler/nir/nir_format_convert.h
> @@ -50,6 +50,32 @@ nir_mask_shift_or(struct nir_builder *b, nir_ssa_def *dst, 
> nir_ssa_def *src,
> return nir_ior(b, nir_mask_shift(b, src, src_mask, src_left_shift), dst);
>  }
>  
> +static inline nir_ssa_def *
> +nir_format_mask_uvec(nir_builder *b, nir_ssa_def *src,
> + const unsigned *bits)
> +{
> +   nir_const_value mask;
> +   for (unsigned i = 0; i < src->num_components; i++) {
> +  assert(bits[i] < 32);
> +  mask.u32[i] = (1u << bits[i]) - 1;
> +   }
> +   return nir_iand(b, src, nir_build_imm(b, src->num_components, 32, mask));
> +}
> +
> +static inline nir_ssa_def *
> +nir_format_sign_extend_ivec(nir_builder *b, nir_ssa_def *src,
> +const unsigned *bits)
> +{
> +   assert(src->num_components <= 4);
> +   nir_ssa_def *comps[4];
> +   for (unsigned i = 0; i < src->num_components; i++) {
> +  nir_ssa_def *shift = nir_imm_int(b, src->bit_size - bits[i]);
> +  comps[i] = nir_ishr(b, nir_ishl(b, nir_channel(b, src, i), shift), 
> shift);
> +   }
> +   return nir_vec(b, comps, src->num_components);
> +}
> +
> +
>  static inline nir_ssa_def *
>  nir_format_unpack_int(nir_builder *b, nir_ssa_def *packed,
>const unsigned *bits, unsigned num_components,
> @@ -117,14 +143,7 @@ static inline nir_ssa_def *
>  nir_format_pack_uint(nir_builder *b, nir_ssa_def *color,
>   const unsigned *bits, unsigned num_components)
>  {
> -   nir_const_value mask;
> -   for (unsigned i = 0; i < num_components; i++) {

This used to operate on the num_components parameter to
nir_format_pack_uint, but now it operates on color->num_components
instead.  That's probably OK...do we even need the parameter?

Nothing actually uses this function in master today AFAICT...

Patches 1-3 (with Bas's fixes) and 5-7 are:
Reviewed-by: Kenneth Graunke 

> -  assert(bits[i] < 32);
> -  mask.u32[i] = (1u << bits[i]) - 1;
> -   }
> -   nir_ssa_def *mask_imm = nir_build_imm(b, num_components, 32, mask);
> -
> -   return nir_format_pack_uint_unmasked(b, nir_iand(b, color, mask_imm),
> +   return nir_format_pack_uint_unmasked(b, nir_format_mask_uvec(b, color, 
> bits),
>  bits, num_components);
>  }
>  
> 



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[Mesa-dev] v2 Tidy up dri config options

[Timothy Arceri]

v2:
- moved TCL dri config options to old radeon drivers instead
  of replacing with env var.
- some reviewed patches from previous series pushed

This series removes some unused options, replaces some legacy
debug options with env vars instead and moves a bunch of old
radeon dri driver options directly into the drivers.

I haven't bothered copying all the radeon dri translations
as I didn't want to waste my time as it seems unlikely anyone
will even use those config options these days (I was tempted to
just remove them altogether).

The motivation behind the series is to prep dri conf to be more
modular and eventually use it with the radv driver.


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[Mesa-dev] [PATCH v2 06/14] mesa: move legacy TCL dri config options

[Timothy Arceri]

---
 src/mesa/drivers/dri/radeon/radeon_screen.c | 10 +
 src/mesa/drivers/dri/radeon/radeon_screen.h |  5 +
 src/util/xmlpool/ca.po  | 23 -
 src/util/xmlpool/de.po  | 23 -
 src/util/xmlpool/es.po  | 23 -
 src/util/xmlpool/fr.po  | 23 -
 src/util/xmlpool/nl.po  | 23 -
 src/util/xmlpool/sv.po  | 22 
 src/util/xmlpool/t_options.h| 14 -
 9 files changed, 15 insertions(+), 151 deletions(-)

diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c 
b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 4c93404607d..fe484abf73f 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -80,6 +80,16 @@ DRI_CONF_OPT_BEGIN_B(hyperz, def) \
 DRI_CONF_DESC(en,"Use HyperZ to boost performance") \
 DRI_CONF_OPT_END
 
+#define DRI_CONF_TCL_MODE(def) \
+DRI_CONF_OPT_BEGIN_V(tcl_mode,enum,def,"0:3") \
+DRI_CONF_DESC_BEGIN(en,"TCL mode (Transformation, Clipping, 
Lighting)") \
+DRI_CONF_ENUM(0,"Use software TCL pipeline") \
+DRI_CONF_ENUM(1,"Use hardware TCL as first TCL pipeline 
stage") \
+DRI_CONF_ENUM(2,"Bypass the TCL pipeline") \
+DRI_CONF_ENUM(3,"Bypass the TCL pipeline with state-based 
machine code generated on-the-fly") \
+DRI_CONF_DESC_END \
+DRI_CONF_OPT_END
+
 #if defined(RADEON_R100)   /* R100 */
 static const __DRIconfigOptionsExtension radeon_config_options = {
.base = { __DRI_CONFIG_OPTIONS, 1 },
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h 
b/src/mesa/drivers/dri/radeon/radeon_screen.h
index efb2e6016b7..9d69dcd4785 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -48,6 +48,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 
SOFTWARE.
 #include "util/xmlconfig.h"
 
 
+#define DRI_CONF_TCL_SW 0
+#define DRI_CONF_TCL_PIPELINED 1
+#define DRI_CONF_TCL_VTXFMT 2
+#define DRI_CONF_TCL_CODEGEN 3
+
 typedef struct {
drm_handle_t handle;/* Handle to the DRM region */
drmSize size;   /* Size of the DRM region */
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index 2c663d25027..15c5fa0f133 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -193,29 +193,6 @@ msgstr ""
 msgid "Performance"
 msgstr "Rendiment"
 
-#: t_options.h:238
-msgid "TCL mode (Transformation, Clipping, Lighting)"
-msgstr "Mode TCL (Transformació, Retall, Il·luminació)"
-
-#: t_options.h:239
-msgid "Use software TCL pipeline"
-msgstr "Utilitza la canonada TCL de programari"
-
-#: t_options.h:240
-msgid "Use hardware TCL as first TCL pipeline stage"
-msgstr "Utilitza el TCL de maquinari com a la primera fase de la canonada TCL"
-
-#: t_options.h:241
-msgid "Bypass the TCL pipeline"
-msgstr "Passa per alt la canonada TCL"
-
-#: t_options.h:242
-msgid ""
-"Bypass the TCL pipeline with state-based machine code generated on-the-fly"
-msgstr ""
-"Passa per alt la canonada TCL amb codi de màquina basat en estats, generat "
-"sobre la marxa"
-
 #: t_options.h:251
 msgid "Method to limit rendering latency"
 msgstr "Mètode per a limitar la latència de renderització"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index 40095df3c40..683d33d4bc6 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -167,29 +167,6 @@ msgstr ""
 msgid "Performance"
 msgstr "Leistung"
 
-#: t_options.h:238
-msgid "TCL mode (Transformation, Clipping, Lighting)"
-msgstr "TCL-Modus (Transformation, Clipping, Licht)"
-
-#: t_options.h:239
-msgid "Use software TCL pipeline"
-msgstr "Benutze die Software-TCL-Pipeline"
-
-#: t_options.h:240
-msgid "Use hardware TCL as first TCL pipeline stage"
-msgstr "Benutze Hardware TCL als erste Stufe der TCL-Pipeline"
-
-#: t_options.h:241
-msgid "Bypass the TCL pipeline"
-msgstr "Umgehe die TCL-Pipeline"
-
-#: t_options.h:242
-msgid ""
-"Bypass the TCL pipeline with state-based machine code generated on-the-fly"
-msgstr ""
-"Umgehe die TCL-Pipeline mit zur Laufzeit erzeugtem, zustandsbasiertem "
-"Maschinencode"
-
 #: t_options.h:251
 msgid "Method to limit rendering latency"
 msgstr "Methode zur Begrenzung der Bildverzögerung"
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index b1cfdd6e146..8b841c682fe 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -174,29 +174,6 @@ msgstr ""
 msgid "Performance"
 msgstr "Rendimiento"
 
-#: t_options.h:238
-msgid "TCL mode (Transformation, Clipping, Lighting)"
-msgstr "Modo TCL (Transformación, Recorte, Iluminación)"
-
-#: t_options.h:239
-msgid "Use software TCL pipeline"
-msgstr "Usar tubería TCL por software"
-
-#: t_options.h:240
-msgid "Use hardware TCL as first TCL 

[Mesa-dev] [Bug 107563] [RADV] Broken rendering in Unity demos

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107563

--- Comment #9 from Samuel Pitoiset  ---
The rendering issue is fixed with
https://cgit.freedesktop.org/mesa/mesa/commit/?id=0aacb5eab6120aa1410966d23101e16eea3fbcd7

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[Mesa-dev] [PATCH v2 09/14] mesa: remove unused dri option float_depth

[Timothy Arceri]

This seems to have only been used by DRI1 drivers which were
removed with e4344161bde2.
---
 src/util/xmlpool/ca.po   | 4 
 src/util/xmlpool/de.po   | 4 
 src/util/xmlpool/es.po   | 4 
 src/util/xmlpool/fr.po   | 4 
 src/util/xmlpool/nl.po   | 4 
 src/util/xmlpool/sv.po   | 4 
 src/util/xmlpool/t_options.h | 5 -
 7 files changed, 29 deletions(-)

diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index 5f78915b544..c588832b5d9 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -124,10 +124,6 @@ msgstr "Arrodoneix els components de color a baix"
 msgid "Round to nearest color"
 msgstr "Arrodoneix al color més proper"
 
-#: t_options.h:190
-msgid "Floating point depth buffer"
-msgstr "Buffer de profunditat de punt flotant"
-
 #: t_options.h:195
 msgid "A post-processing filter to cel-shade the output"
 msgstr "Un filtre de postprocessament per a aplicar cel shading a la sortida"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index 2ef0607cbb2..f40a39fff59 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -99,10 +99,6 @@ msgstr "Farbkomponenten abrunden"
 msgid "Round to nearest color"
 msgstr "Zur ähnlichsten Farbe runden"
 
-#: t_options.h:190
-msgid "Floating point depth buffer"
-msgstr "Fließkomma z-Puffer"
-
 #: t_options.h:195
 msgid "A post-processing filter to cel-shade the output"
 msgstr "Nachbearbeitungsfilter für Cell Shading"
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index cfb6c0eb18d..e371834070b 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -106,10 +106,6 @@ msgstr "Redondear hacia abajo los componentes de color"
 msgid "Round to nearest color"
 msgstr "Redondear al color más cercano"
 
-#: t_options.h:190
-msgid "Floating point depth buffer"
-msgstr "Búfer de profundidad en coma flotante"
-
 #: t_options.h:195
 msgid "A post-processing filter to cel-shade the output"
 msgstr "Un filtro de postprocesamiento para aplicar cel shading a la salida"
diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index 94a248069a0..b898e3423dd 100644
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -98,10 +98,6 @@ msgstr "Arrondi à l'inférieur"
 msgid "Round to nearest color"
 msgstr "Arrondi au plus proche"
 
-#: t_options.h:190
-msgid "Floating point depth buffer"
-msgstr "Z-buffer en virgule flottante"
-
 #: t_options.h:195
 msgid "A post-processing filter to cel-shade the output"
 msgstr ""
diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
index 9beafb42224..21845ce879c 100644
--- a/src/util/xmlpool/nl.po
+++ b/src/util/xmlpool/nl.po
@@ -98,10 +98,6 @@ msgstr "Horizontale foutdiffusie, zet fout bij lijnbegin 
terug"
 msgid "Ordered 2D color dithering"
 msgstr "Geordende 2D kleurrasterisering"
 
-#: t_options.h:190
-msgid "Floating point depth buffer"
-msgstr "Dieptebuffer als commagetal"
-
 #: t_options.h:195
 msgid "A post-processing filter to cel-shade the output"
 msgstr ""
diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
index d952d5d8388..e340ed5df60 100644
--- a/src/util/xmlpool/sv.po
+++ b/src/util/xmlpool/sv.po
@@ -114,10 +114,6 @@ msgstr "Horisontell felspridning, återställ fel vid 
radbörjan"
 msgid "Ordered 2D color dithering"
 msgstr "Ordnad 2D-färgutjämning"
 
-#: t_options.h:190
-msgid "Floating point depth buffer"
-msgstr "Buffert för flytande punktdjup"
-
 #: t_options.h:195
 msgid "A post-processing filter to cel-shade the output"
 msgstr ""
diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
index 8aad0070adf..170425d9f4a 100644
--- a/src/util/xmlpool/t_options.h
+++ b/src/util/xmlpool/t_options.h
@@ -181,11 +181,6 @@ DRI_CONF_OPT_BEGIN_V(round_mode,enum,def,"0:1") \
 DRI_CONF_DESC_END \
 DRI_CONF_OPT_END
 
-#define DRI_CONF_FLOAT_DEPTH(def) \
-DRI_CONF_OPT_BEGIN_B(float_depth, def) \
-DRI_CONF_DESC(en,gettext("Floating point depth buffer")) \
-DRI_CONF_OPT_END
-
 #define DRI_CONF_PP_CELSHADE(def) \
 DRI_CONF_OPT_BEGIN_V(pp_celshade,enum,def,"0:1") \
 DRI_CONF_DESC(en,gettext("A post-processing filter to cel-shade the 
output")) \
-- 
2.17.1

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Re: [Mesa-dev] [PATCH 00/12] Compiler warning fixes, round 2

[Kai Wasserbäch]

Hey Linoel,
Lionel Landwerlin wrote on 20.08.2018 11:19:
> On 20/08/18 09:16, Kai Wasserbäch wrote:
>> Lionel Landwerlin wrote on 19.08.2018 11:05:
>>> Patches 6, 7, 10 & 11 are :
>>>
>>> Reviewed-by: Lionel Landwerlin 
>> thanks! Feel free to push, I don't have commit access (see cover letter).
> 
> Will do.

thanks!

>>> There are 2 existing series touching the same code, in patches 8, 9 & 12, I
>>> think should land before the warnings are fixed.
>> Hm, I can see why you might want to hold off on 8 and 9 then, but 12 
>> shouldn't
>> break anything, should it? It might even work as a fixup for your other 
>> series?
>> Anyway, I can carry those three over to the next series, once I get most of 
>> this
>> into master. 
> 
> It clashes with this one : https://patchwork.freedesktop.org/series/48139/

Ah, I see. Patch 12 from this series wouldn't be needed at all afterwards, since
result would be the return value then. Let's abandon this one then. 

Cheers,
Kai



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Re: [Mesa-dev] [PATCH 11/22] nir: Make image load/store intrinsics variable-width

[Kenneth Graunke]

On Friday, August 17, 2018 1:06:17 PM PDT Jason Ekstrand wrote:
> Instead of requiring 4 components, this allows them to potentially use
> fewer.  Both the SPIR-V and GLSL paths still generate vec4 intrinsics so
> drivers which assume 4 components should be safe.  However, we want to
> be able to shrink them for i965.
> ---
>  src/compiler/glsl/glsl_to_nir.cpp  | 9 +++--
>  src/compiler/nir/nir_intrinsics.py | 4 ++--
>  src/compiler/spirv/spirv_to_nir.c  | 2 ++
>  3 files changed, 11 insertions(+), 4 deletions(-)

Patches 10-13 are:
Reviewed-by: Kenneth Graunke 


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[Mesa-dev] [PATCH v2 07/14] mesa: move legacy dri config option color_reduction

[Timothy Arceri]

---
 src/mesa/drivers/dri/radeon/radeon_screen.h | 10 ++
 src/util/xmlpool/ca.po  | 12 
 src/util/xmlpool/de.po  | 12 
 src/util/xmlpool/es.po  | 12 
 src/util/xmlpool/fr.po  | 12 
 src/util/xmlpool/nl.po  | 12 
 src/util/xmlpool/sv.po  | 12 
 src/util/xmlpool/t_options.h| 10 --
 8 files changed, 10 insertions(+), 82 deletions(-)

diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h 
b/src/mesa/drivers/dri/radeon/radeon_screen.h
index 9d69dcd4785..35a20996f82 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -47,6 +47,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 
SOFTWARE.
 #include "radeon_reg.h"
 #include "util/xmlconfig.h"
 
+#define DRI_CONF_COLOR_REDUCTION_ROUND 0
+#define DRI_CONF_COLOR_REDUCTION_DITHER 1
+#define DRI_CONF_COLOR_REDUCTION(def) \
+DRI_CONF_OPT_BEGIN_V(color_reduction,enum,def,"0:1") \
+DRI_CONF_DESC_BEGIN(en,"Initial color reduction method") \
+DRI_CONF_ENUM(0,"Round colors") \
+DRI_CONF_ENUM(1,"Dither colors") \
+DRI_CONF_DESC_END \
+DRI_CONF_OPT_END
+
 
 #define DRI_CONF_TCL_SW 0
 #define DRI_CONF_TCL_PIPELINED 1
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index 15c5fa0f133..cab901ae194 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -112,18 +112,6 @@ msgstr ""
 "Prohibeix una parcialitat negativa del Nivell de Detalle (LOD) de les "
 "textures"
 
-#: t_options.h:160
-msgid "Initial color reduction method"
-msgstr "Mètode inicial de reducció de color"
-
-#: t_options.h:161
-msgid "Round colors"
-msgstr "Colors arrodonits"
-
-#: t_options.h:162
-msgid "Dither colors"
-msgstr "Colors tramats"
-
 #: t_options.h:170
 msgid "Color rounding method"
 msgstr "Mètode d'arrodoniment de color"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index 683d33d4bc6..421078441db 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -87,18 +87,6 @@ msgstr "Initialer Maximalwert für anisotropische 
Texturfilterung"
 msgid "Forbid negative texture LOD bias"
 msgstr "Verbiete negative Textur-Detailgradverschiebung"
 
-#: t_options.h:160
-msgid "Initial color reduction method"
-msgstr "Initiale Farbreduktionsmethode"
-
-#: t_options.h:161
-msgid "Round colors"
-msgstr "Farben runden"
-
-#: t_options.h:162
-msgid "Dither colors"
-msgstr "Farben rastern"
-
 #: t_options.h:170
 msgid "Color rounding method"
 msgstr "Farbrundungsmethode"
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index 8b841c682fe..fe9bce1bbba 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -94,18 +94,6 @@ msgstr "Valor máximo inicial para filtrado anisotrópico de 
textura"
 msgid "Forbid negative texture LOD bias"
 msgstr "Prohibir valores negativos de Nivel De Detalle (LOD) de texturas"
 
-#: t_options.h:160
-msgid "Initial color reduction method"
-msgstr "Método inicial de reducción de color"
-
-#: t_options.h:161
-msgid "Round colors"
-msgstr "Colores redondeados"
-
-#: t_options.h:162
-msgid "Dither colors"
-msgstr "Colores suavizados"
-
 #: t_options.h:170
 msgid "Color rounding method"
 msgstr "Método de redondeo de colores"
diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index d8bab1a2139..609c6041e34 100644
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -86,18 +86,6 @@ msgstr "Valeur maximale initiale pour le filtrage 
anisotropique de texture"
 msgid "Forbid negative texture LOD bias"
 msgstr "Interdire le LOD bias negatif"
 
-#: t_options.h:160
-msgid "Initial color reduction method"
-msgstr "Technique de réduction de couleurs"
-
-#: t_options.h:161
-msgid "Round colors"
-msgstr "Arrondir les valeurs de couleur"
-
-#: t_options.h:162
-msgid "Dither colors"
-msgstr "Tramer les couleurs"
-
 #: t_options.h:170
 msgid "Color rounding method"
 msgstr "Méthode d'arrondi des couleurs"
diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
index e6fb5d1f9d7..65071e57451 100644
--- a/src/util/xmlpool/nl.po
+++ b/src/util/xmlpool/nl.po
@@ -86,18 +86,6 @@ msgstr "Initïele maximum waarde voor anisotrophische textuur 
filtering"
 msgid "Forbid negative texture LOD bias"
 msgstr "Verbied negatief niveau detailonderscheid (LOD) van texturen"
 
-#: t_options.h:160
-msgid "Initial color reduction method"
-msgstr "Initïele kleurreductie methode"
-
-#: t_options.h:161
-msgid "Round colors"
-msgstr "Rond kleuren af"
-
-#: t_options.h:162
-msgid "Dither colors"
-msgstr "Rasteriseer kleuren"
-
 #: t_options.h:170
 msgid "Color rounding method"
 msgstr "Kleurafrondingmethode"
diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
index 89072e66f22..d952d5d8388 100644
--- a/src/util/xmlpool/sv.po
+++ b/src/util/xmlpool/sv.po
@@ -86,18 +86,6 @@ msgstr "Initialt maximalt 

Re: [Mesa-dev] [PATCH 00/12] Compiler warning fixes, round 2

[Lionel Landwerlin]

On 20/08/18 09:16, Kai Wasserbäch wrote:

Hey Lionel,
Lionel Landwerlin wrote on 19.08.2018 11:05:

Patches 6, 7, 10 & 11 are :

Reviewed-by: Lionel Landwerlin 

thanks! Feel free to push, I don't have commit access (see cover letter).


Will do.




There are 2 existing series touching the same code, in patches 8, 9 & 12, I
think should land before the warnings are fixed.

Hm, I can see why you might want to hold off on 8 and 9 then, but 12 shouldn't
break anything, should it? It might even work as a fixup for your other series?
Anyway, I can carry those three over to the next series, once I get most of this
into master. 


It clashes with this one : https://patchwork.freedesktop.org/series/48139/



Cheers,
Kai



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Re: [Mesa-dev] [PATCH 08/22] nir/format_convert: Add [us]norm conversion helpers

[Kenneth Graunke]

On Friday, August 17, 2018 1:06:14 PM PDT Jason Ekstrand wrote:
> ---
>  src/compiler/nir/nir_format_convert.h | 56 +++
>  1 file changed, 56 insertions(+)
> 
> diff --git a/src/compiler/nir/nir_format_convert.h 
> b/src/compiler/nir/nir_format_convert.h
> index f2eafcbf5b4..75793733ea6 100644
> --- a/src/compiler/nir/nir_format_convert.h
> +++ b/src/compiler/nir/nir_format_convert.h
> @@ -201,6 +201,62 @@ nir_format_bitcast_uvec_unmasked(nir_builder *b, 
> nir_ssa_def *src,
> return nir_vec(b, dst_chan, dst_components);
>  }
>  
> +static inline nir_ssa_def *
> +_nir_format_norm_factor(nir_builder *b, unsigned *bits,
> +unsigned num_components,
> +bool is_signed)
> +{
> +   nir_const_value factor;
> +   for (unsigned i = 0; i < num_components; i++) {
> +  assert(bits[i] < 32);
> +  factor.f32[i] = (1ul << (bits[i] - is_signed)) - 1;
> +   }
> +   return nir_build_imm(b, num_components, 32, factor);
> +}
> +
> +static inline nir_ssa_def *
> +nir_format_unorm_to_float(nir_builder *b, nir_ssa_def *u, unsigned *bits)
> +{
> +   nir_ssa_def *factor =
> +  _nir_format_norm_factor(b, bits, u->num_components, false);
> +
> +   return nir_fdiv(b, nir_u2f32(b, u), factor);
> +}
> +
> +static inline nir_ssa_def *
> +nir_format_snorm_to_float(nir_builder *b, nir_ssa_def *s, unsigned *bits)
> +{
> +   nir_ssa_def *factor =
> +  _nir_format_norm_factor(b, bits, s->num_components, true);
> +
> +   return nir_fmax(b, nir_fdiv(b, nir_i2f32(b, s), factor),
> +  nir_imm_float(b, -1.0f));
> +}
> +
> +static inline nir_ssa_def *
> +nir_format_float_to_unorm(nir_builder *b, nir_ssa_def *f, unsigned *bits)
> +{
> +   nir_ssa_def *factor =
> +  _nir_format_norm_factor(b, bits, f->num_components, false);
> +
> +   /* Clamp to the range [0, 1] */
> +   f = nir_fsat(b, f);
> +
> +   return nir_f2u32(b, nir_fround_even(b, nir_fmul(b, f, factor)));
> +}
> +
> +static inline nir_ssa_def *
> +nir_format_float_to_snorm(nir_builder *b, nir_ssa_def *f, unsigned *bits)
> +{
> +   nir_ssa_def *factor =
> +  _nir_format_norm_factor(b, bits, f->num_components, true);
> +
> +   /* Clamp to the range [0, 1] */

Should be [-1, 1] here.

Could always move nir_fclamp from nir_builtin_builder.h to nir_builder.h
and then use that here, too.  Would be ever so slightly simpler.

With the comment fixed,
Reviewed-by: Kenneth Graunke 

> +   f = nir_fmin(b, nir_fmax(b, f, nir_imm_float(b, -1)), nir_imm_float(b, 
> 1));
> +
> +   return nir_f2i32(b, nir_fround_even(b, nir_fmul(b, f, factor)));
> +}
> +
>  static inline nir_ssa_def *
>  nir_format_linear_to_srgb(nir_builder *b, nir_ssa_def *c)
>  {
> 



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Re: [Mesa-dev] [PATCH] travis: make drivers explicit in Meson targets

[Juan A. Suarez Romero]

On Tue, 2018-08-14 at 11:00 +0100, Emil Velikov wrote:
> On 8 August 2018 at 15:36, Juan A. Suarez Romero  wrote:
> > Like in the autotools target, make the list of drivers to be built in
> > each of the Meson targets explicit.
> > 
> > This will help to identify missing dependencies and other issues more
> > easily.
> > 
> > CC: Emil Velikov 
> 
> Thanks Juan! Sorry for missing this :-(
> 
> Do you know, which meson version got the ability to have the driver
> list, without the square brackets?


I think from the very beginning


> -Emil
> 

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Re: [Mesa-dev] [PATCH v2] intel/decoder: fix the possible out of bounds group_iter

[Lionel Landwerlin]

On 15/08/18 10:45, andrey simiklit wrote:

Hi all,

Thanks for your reply.

We shouldn't even get to use the iterator if it's an unknown
instruction.
The decoder should just advance dword by dword until it finds
something that
makes sense again.


Got it)
So this is an expected behavior there:

return iter_group_offset_bits(iter, iter->group_iter + 1) <
  (gen_group_get_length(iter->group, iter->p) * 32);


when we convert a negative *int* to *uint* to return true to continue 
our loop.


return iter_group_offset_bits(iter, iter->group_iter + 1) <
  (*0xFFE0U*);


Do you think it is good idea to add comment or something like this 
into the "iter_more_groups" function:


int *length* = gen_group_get_length(iter->group, iter->p);

return *length < 0 ||*
   iter_group_offset_bits(iter, iter->group_iter + 1) <
    (*length* * 32);

to show more explicitly here that we want to return true to continue 
our loop

when the -1 is returned from the "gen_group_get_length" function
because at the moment it is a bit implicit)
Please let me know if I am incorrect.


Sorry for the late answer :(

This implies an unknown size for the inspected instruction/struct.
I think this shouldn't happen because the caller even try to initialize 
the iterator to decode it.


I would add an assert, because the iterator doesn't really deal with 
that case.
I'm not sure whether there is such case in the genxml files, but if it 
happens we should probably look into it.


Cheers,

-
Lionel



Regards,
Andrii.

On Tue, Aug 14, 2018 at 7:08 PM, Lionel Landwerlin 
mailto:lionel.g.landwer...@intel.com>> 
wrote:


On 14/08/18 16:16, Rafael Antognolli wrote:

On Tue, Aug 14, 2018 at 03:36:18PM +0100, Lionel Landwerlin wrote:

On 14/08/18 12:55, asimiklit.work 
wrote:

Hi Lionel,

Hi Andrii,

Again sorry, I don't think this is the right fix.
I'm sending another patch to fix the parsing of
MI_BATCH_BUFFER_START which seems to be the actual
issue.

Thanks for working on this,

Thanks for your fast reply.
I agree that it is not correct patch for this issue
but anyway
"iter_more_groups" function will still work incorrectly
for unknown instructions when the
"iter->group->variable" field is true.
I guess that this case should be fixed.
Please let me know if I am incorrect.

Hey Andrii,

We shouldn't even get to use the iterator if it's an
unknown instruction.
The decoder should just advance dword by dword until it
finds something that
makes sense again.

If we run into that problem, I think we should fix the caller.

In that case, would an unreachable() or assert be a good thing
to do?


Yep, I guess assert in gen_field_iterator_init() should be a good
thing.


Regards,
Andrii.

On 2018-08-14 1:26 PM, Lionel Landwerlin wrote:

Hi Andrii,

Again sorry, I don't think this is the right fix.
I'm sending another patch to fix the parsing of
MI_BATCH_BUFFER_START which seems to be the actual
issue.

Thanks for working on this,

-
Lionel

On 14/08/18 10:04, asimiklit.w...@gmail.com
 wrote:

From: Andrii Simiklit
mailto:asimiklit.w...@gmail.com>>

The "gen_group_get_length" function can return
a negative value
and it can lead to the out of bounds group_iter.

v2: printing of "unknown command type" was added
Bugzilla:
https://bugs.freedesktop.org/show_bug.cgi?id=107544

Signed-off-by: Andrii Simiklit
mailto:andrii.simik...@globallogic.com>>
---
   src/intel/common/gen_decoder.c | 13
+++--
   1 file changed, 11 insertions(+), 2
deletions(-)

diff --git a/src/intel/common/gen_decoder.c
b/src/intel/common/gen_decoder.c
index ec0a486..b36facf 100644
--- a/src/intel/common/gen_decoder.c
+++ 

Re: [Mesa-dev] [PATCH] i965/icl: Allow headerless sampler messages for pre-emptable contexts

[Kenneth Graunke]

On Friday, August 17, 2018 5:13:25 PM PDT Anuj Phogat wrote:
> It fixes simulator warnings in piglit tests complaining about missing
> support for headerless sampler messages for pre-emptable contexts.
> Bit 5 in SAMPLER MODE register is newly introduced for ICLLP.
> 
> Signed-off-by: Anuj Phogat 
> ---
>  src/mesa/drivers/dri/i965/brw_defines.h  |  4 
>  src/mesa/drivers/dri/i965/brw_state_upload.c | 11 +++
>  2 files changed, 15 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index 855f1c7d744..433314115b1 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -1673,4 +1673,8 @@ enum brw_pixel_shader_coverage_mask_mode {
>  # define GLK_SCEC_BARRIER_MODE_3D_HULL (1 << 7)
>  # define GLK_SCEC_BARRIER_MODE_MASKREG_MASK(1 << 7)
>  
> +#define GEN11_SAMPLER_MODE  0xE18C
> +# define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS(1 << 5)
> +# define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK   REG_MASK(1 << 5)
> +
>  #endif
> diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
> b/src/mesa/drivers/dri/i965/brw_state_upload.c
> index 757426407c3..5a334b48892 100644
> --- a/src/mesa/drivers/dri/i965/brw_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
> @@ -63,6 +63,17 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
>  
> brw_upload_invariant_state(brw);
>  
> +   if (devinfo->gen == 11) {
> +  /*  The default behavior of bit 5 "Headerless Message for Pre-emptable
> +   *  Contexts" in SAMPLER MODE register is set to 0, which means
> +   *  headerless sampler messages are not allowed for pre-emptable
> +   *  contexts. Set the bit 5 to 1 to allow them.

Bonus space after the stars.  Can we also change this to:

   * contexts.  Set bit 5 to allow them.

Same for the anv patch.  Either way, both are:
Reviewed-by: Kenneth Graunke 

I don't know if people are trying to enable pre-emption during GPGPU
work on pre-Gen11.  If so, that probably will not work, and we'd either
need to avoid headerless messages (gross) or disable preemption (maybe
also bad...)

> +   */
> +  brw_load_register_imm32(brw, GEN11_SAMPLER_MODE,
> +  
> HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK |
> +  HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS);
> +   }
> +
> if (devinfo->gen == 10 || devinfo->gen == 11) {
>/* From gen10 workaround table in h/w specs:
> *
> 



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[Mesa-dev] [PATCH v2 14/14] mesa: move legacy dri config option texture_depth

[Timothy Arceri]

---
 src/mesa/drivers/dri/radeon/radeon_screen.h | 13 +
 src/util/xmlpool/ca.po  | 20 
 src/util/xmlpool/de.po  | 20 
 src/util/xmlpool/es.po  | 20 
 src/util/xmlpool/fr.po  | 20 
 src/util/xmlpool/nl.po  | 20 
 src/util/xmlpool/sv.po  | 20 
 src/util/xmlpool/t_options.h| 14 --
 8 files changed, 13 insertions(+), 134 deletions(-)

diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h 
b/src/mesa/drivers/dri/radeon/radeon_screen.h
index 30202aec8b0..af1b9454e10 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -91,6 +91,19 @@ DRI_CONF_OPT_BEGIN_V(fthrottle_mode,enum,def,"0:2") \
 DRI_CONF_DESC_END \
 DRI_CONF_OPT_END
 
+#define DRI_CONF_TEXTURE_DEPTH_FB   0
+#define DRI_CONF_TEXTURE_DEPTH_32   1
+#define DRI_CONF_TEXTURE_DEPTH_16   2
+#define DRI_CONF_TEXTURE_DEPTH_FORCE_16 3
+#define DRI_CONF_TEXTURE_DEPTH(def) \
+DRI_CONF_OPT_BEGIN_V(texture_depth,enum,def,"0:3") \
+   DRI_CONF_DESC_BEGIN(en,"Texture color depth") \
+DRI_CONF_ENUM(0,"Prefer frame buffer color depth") \
+DRI_CONF_ENUM(1,"Prefer 32 bits per texel") \
+DRI_CONF_ENUM(2,"Prefer 16 bits per texel") \
+DRI_CONF_ENUM(3,"Force 16 bits per texel") \
+DRI_CONF_DESC_END \
+DRI_CONF_OPT_END
 
 #define DRI_CONF_TCL_SW 0
 #define DRI_CONF_TCL_PIPELINED 1
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index ddb37b6dd8f..91621f2831d 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -82,26 +82,6 @@ msgstr "Permet les directives #extension GLSL en el mitjà 
dels shaders"
 msgid "Image Quality"
 msgstr "Qualitat d'imatge"
 
-#: t_options.h:133
-msgid "Texture color depth"
-msgstr "Profunditat de color de textura"
-
-#: t_options.h:134
-msgid "Prefer frame buffer color depth"
-msgstr "Prefereix profunditat de color del framebuffer"
-
-#: t_options.h:135
-msgid "Prefer 32 bits per texel"
-msgstr "Prefereix 32 bits per texel"
-
-#: t_options.h:136
-msgid "Prefer 16 bits per texel"
-msgstr "Prefereix 16 bits per texel"
-
-#: t_options.h:137
-msgid "Force 16 bits per texel"
-msgstr "Força 16 bits per texel"
-
 #: t_options.h:195
 msgid "A post-processing filter to cel-shade the output"
 msgstr "Un filtre de postprocessament per a aplicar cel shading a la sortida"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index 7b5b9510cfc..8c1d3df3f11 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -59,26 +59,6 @@ msgstr ""
 msgid "Image Quality"
 msgstr "Bildqualität"
 
-#: t_options.h:133
-msgid "Texture color depth"
-msgstr "Texturfarbtiefe"
-
-#: t_options.h:134
-msgid "Prefer frame buffer color depth"
-msgstr "Bevorzuge Farbtiefe des Framebuffers"
-
-#: t_options.h:135
-msgid "Prefer 32 bits per texel"
-msgstr "Bevorzuge 32 bits pro Texel"
-
-#: t_options.h:136
-msgid "Prefer 16 bits per texel"
-msgstr "Bevorzuge 16 bits pro Texel"
-
-#: t_options.h:137
-msgid "Force 16 bits per texel"
-msgstr "Erzwinge 16 bits pro Texel"
-
 #: t_options.h:195
 msgid "A post-processing filter to cel-shade the output"
 msgstr "Nachbearbeitungsfilter für Cell Shading"
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index 81106ae7139..e5f44c8efc5 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -66,26 +66,6 @@ msgstr "Permite directivas #extension GLSL en medio de los 
shaders"
 msgid "Image Quality"
 msgstr "Calidad de imagen"
 
-#: t_options.h:133
-msgid "Texture color depth"
-msgstr "Profundidad de color de textura"
-
-#: t_options.h:134
-msgid "Prefer frame buffer color depth"
-msgstr "Preferir profundidad de color del framebuffer"
-
-#: t_options.h:135
-msgid "Prefer 32 bits per texel"
-msgstr "Preferir 32 bits por texel"
-
-#: t_options.h:136
-msgid "Prefer 16 bits per texel"
-msgstr "Preferir 16 bits por texel"
-
-#: t_options.h:137
-msgid "Force 16 bits per texel"
-msgstr "Forzar a 16 bits por texel"
-
 #: t_options.h:195
 msgid "A post-processing filter to cel-shade the output"
 msgstr "Un filtro de postprocesamiento para aplicar cel shading a la salida"
diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index f1a2ce0748e..aa8706cbb1c 100644
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -58,26 +58,6 @@ msgstr ""
 msgid "Image Quality"
 msgstr "Qualité d'image"
 
-#: t_options.h:133
-msgid "Texture color depth"
-msgstr "Profondeur de texture"
-
-#: t_options.h:134
-msgid "Prefer frame buffer color depth"
-msgstr "Profondeur de couleur"
-
-#: t_options.h:135
-msgid "Prefer 32 bits per texel"
-msgstr "Préférer 32 bits par texel"
-
-#: t_options.h:136
-msgid "Prefer 16 bits per texel"
-msgstr "Prérérer 16 bits par texel"
-
-#: 

Re: [Mesa-dev] Tidy up dri config options

[Kenneth Graunke]

On Wednesday, August 15, 2018 3:13:09 AM PDT Timothy Arceri wrote:
> This series removes some unused options, replaces some legacy
> debug options with env vars instead and moves a bunch of old
> radeon dri driver options directly into the drivers.
> 
> I haven't bothered copying all the radeon dri translations
> as I didn't want to waste my time as it seems unlikely anyone
> will even use those config options these days (I was tempted to
> just remove them altogether).
> 
> The motivation behind the series is to prep dri conf to be more
> modular and eventually use it with the radv driver.

Patches 1-8 are
Reviewed-by: Kenneth Graunke 


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[Mesa-dev] [PATCH] loader: decouple USE_DRICONF from HAVE_LIBDRM

[Qiang Yu]

For user can use dri_driver drirc option even on
environment without libdrm.

Tested on build with and without libdrm.

Signed-off-by: Qiang Yu 
---
 src/loader/loader.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/loader/loader.c b/src/loader/loader.c
index 2e37d11..22cf320 100644
--- a/src/loader/loader.c
+++ b/src/loader/loader.c
@@ -45,11 +45,12 @@
 
 #ifdef HAVE_LIBDRM
 #include 
+#endif
+
 #ifdef USE_DRICONF
 #include "util/xmlconfig.h"
 #include "util/xmlpool.h"
 #endif
-#endif
 
 #define __IS_LOADER
 #include "pci_id_driver_map.h"
@@ -102,7 +103,6 @@ static char *loader_get_kernel_driver_name(int fd)
 #endif
 }
 
-#if defined(HAVE_LIBDRM)
 #ifdef USE_DRICONF
 static const char __driConfigOptionsLoader[] =
 DRI_CONF_BEGIN
@@ -134,7 +134,10 @@ static char *loader_get_dri_config_driver(int fd)
free(kernel_driver);
return dri_driver;
 }
+#endif
 
+#if defined(HAVE_LIBDRM)
+#ifdef USE_DRICONF
 static char *loader_get_dri_config_device_id(void)
 {
driOptionCache defaultInitOptions;
@@ -382,7 +385,7 @@ loader_get_driver_for_fd(int fd)
  return strdup(driver);
}
 
-#if defined(HAVE_LIBDRM) && defined(USE_DRICONF)
+#ifdef USE_DRICONF
driver = loader_get_dri_config_driver(fd);
if (driver)
   return driver;
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 10/22] nir/format_convert: Fix a bitmask in unpack_11f11f10f

[Kenneth Graunke]

On Friday, August 17, 2018 1:06:16 PM PDT Jason Ekstrand wrote:
> Fixes: 4e337b42f9a2 "nir/format_convert: Add pack/unpack for R11F_G11F_B10F"
> ---
>  src/compiler/nir/nir_format_convert.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/compiler/nir/nir_format_convert.h 
> b/src/compiler/nir/nir_format_convert.h
> index c79001a50aa..27a8ac08d49 100644
> --- a/src/compiler/nir/nir_format_convert.h
> +++ b/src/compiler/nir/nir_format_convert.h
> @@ -288,7 +288,7 @@ nir_format_unpack_11f11f10f(nir_builder *b, nir_ssa_def 
> *packed)
>  {
> nir_ssa_def *chans[3];
> chans[0] = nir_mask_shift(b, packed, 0x07ff, 4);
> -   chans[1] = nir_mask_shift(b, packed, 0x003ff100, -7);
> +   chans[1] = nir_mask_shift(b, packed, 0x003ff800, -7);
> chans[2] = nir_mask_shift(b, packed, 0xffc0, -17);
>  
> for (unsigned i = 0; i < 3; i++)
> 

Patches 9-10 are:
Reviewed-by: Kenneth Graunke 


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[Mesa-dev] [Bug 107610] Dolphin emulator mis-renders shadow overlay in Super Mario Sunshine

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107610

--- Comment #1 from Samuel Pitoiset  ---
Can you record a renderdoc trace instead please?

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[Mesa-dev] [Bug 91889] Planetary Anihilation: Titans display content of other processes buffers

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=91889

Timothy Arceri  changed:

   What|Removed |Added

 Resolution|--- |NOTOURBUG
 Status|NEW |RESOLVED

--- Comment #30 from Timothy Arceri  ---
Closing as not our bug as per:
https://bugs.freedesktop.org/show_bug.cgi?id=65968#c12

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[Mesa-dev] [PATCH v2 10/14] mesa: move legacy dri config option round_mode

[Timothy Arceri]

---
 src/mesa/drivers/dri/radeon/radeon_screen.h | 10 ++
 src/util/xmlpool/ca.po  | 12 
 src/util/xmlpool/de.po  | 12 
 src/util/xmlpool/es.po  | 12 
 src/util/xmlpool/fr.po  | 12 
 src/util/xmlpool/sv.po  | 12 
 src/util/xmlpool/t_options.h| 10 --
 7 files changed, 10 insertions(+), 70 deletions(-)

diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h 
b/src/mesa/drivers/dri/radeon/radeon_screen.h
index c5b8023d9d1..e36e438e295 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -69,6 +69,16 @@ DRI_CONF_OPT_BEGIN_V(dither_mode,enum,def,"0:2") \
 DRI_CONF_DESC_END \
 DRI_CONF_OPT_END
 
+#define DRI_CONF_ROUND_TRUNC 0
+#define DRI_CONF_ROUND_ROUND 1
+#define DRI_CONF_ROUND_MODE(def) \
+DRI_CONF_OPT_BEGIN_V(round_mode,enum,def,"0:1") \
+   DRI_CONF_DESC_BEGIN(en,"Color rounding method") \
+DRI_CONF_ENUM(0,"Round color components downward") \
+DRI_CONF_ENUM(1,"Round to nearest color") \
+DRI_CONF_DESC_END \
+DRI_CONF_OPT_END
+
 
 #define DRI_CONF_TCL_SW 0
 #define DRI_CONF_TCL_PIPELINED 1
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index c588832b5d9..1710a2ce199 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -112,18 +112,6 @@ msgstr ""
 "Prohibeix una parcialitat negativa del Nivell de Detalle (LOD) de les "
 "textures"
 
-#: t_options.h:170
-msgid "Color rounding method"
-msgstr "Mètode d'arrodoniment de color"
-
-#: t_options.h:171
-msgid "Round color components downward"
-msgstr "Arrodoneix els components de color a baix"
-
-#: t_options.h:172
-msgid "Round to nearest color"
-msgstr "Arrodoneix al color més proper"
-
 #: t_options.h:195
 msgid "A post-processing filter to cel-shade the output"
 msgstr "Un filtre de postprocessament per a aplicar cel shading a la sortida"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index f40a39fff59..5581725a251 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -87,18 +87,6 @@ msgstr "Initialer Maximalwert für anisotropische 
Texturfilterung"
 msgid "Forbid negative texture LOD bias"
 msgstr "Verbiete negative Textur-Detailgradverschiebung"
 
-#: t_options.h:170
-msgid "Color rounding method"
-msgstr "Farbrundungsmethode"
-
-#: t_options.h:171
-msgid "Round color components downward"
-msgstr "Farbkomponenten abrunden"
-
-#: t_options.h:172
-msgid "Round to nearest color"
-msgstr "Zur ähnlichsten Farbe runden"
-
 #: t_options.h:195
 msgid "A post-processing filter to cel-shade the output"
 msgstr "Nachbearbeitungsfilter für Cell Shading"
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index e371834070b..85288bfbe8a 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -94,18 +94,6 @@ msgstr "Valor máximo inicial para filtrado anisotrópico de 
textura"
 msgid "Forbid negative texture LOD bias"
 msgstr "Prohibir valores negativos de Nivel De Detalle (LOD) de texturas"
 
-#: t_options.h:170
-msgid "Color rounding method"
-msgstr "Método de redondeo de colores"
-
-#: t_options.h:171
-msgid "Round color components downward"
-msgstr "Redondear hacia abajo los componentes de color"
-
-#: t_options.h:172
-msgid "Round to nearest color"
-msgstr "Redondear al color más cercano"
-
 #: t_options.h:195
 msgid "A post-processing filter to cel-shade the output"
 msgstr "Un filtro de postprocesamiento para aplicar cel shading a la salida"
diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index b898e3423dd..1f2d04cd396 100644
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -86,18 +86,6 @@ msgstr "Valeur maximale initiale pour le filtrage 
anisotropique de texture"
 msgid "Forbid negative texture LOD bias"
 msgstr "Interdire le LOD bias negatif"
 
-#: t_options.h:170
-msgid "Color rounding method"
-msgstr "Méthode d'arrondi des couleurs"
-
-#: t_options.h:171
-msgid "Round color components downward"
-msgstr "Arrondi à l'inférieur"
-
-#: t_options.h:172
-msgid "Round to nearest color"
-msgstr "Arrondi au plus proche"
-
 #: t_options.h:195
 msgid "A post-processing filter to cel-shade the output"
 msgstr ""
diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
index e340ed5df60..61d735b86c1 100644
--- a/src/util/xmlpool/sv.po
+++ b/src/util/xmlpool/sv.po
@@ -86,18 +86,6 @@ msgstr "Initialt maximalt värde för anisotropisk 
texturfiltrering"
 msgid "Forbid negative texture LOD bias"
 msgstr "Förbjud negativ LOD-kompensation för texturer"
 
-#: t_options.h:170
-msgid "Color rounding method"
-msgstr "Färgavrundningsmetod"
-
-#: t_options.h:171
-msgid "Round color components downward"
-msgstr "Avrunda färdkomponenter nedåt"
-
-#: t_options.h:172
-msgid "Round to nearest color"
-msgstr "Avrunda till närmsta färg"
-
 #: t_options.h:181
 msgid "Color dithering method"
 

[Mesa-dev] [Bug 107169] [regression] Upgrade from 18.0.4 to 18.1.0 causes severe stuttering in games

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107169

Timothy Arceri  changed:

   What|Removed |Added

   Assignee|mesa-dev@lists.freedesktop. |dri-devel@lists.freedesktop
   |org |.org
  Component|Mesa core   |Drivers/Gallium/r600
 QA Contact|mesa-dev@lists.freedesktop. |dri-devel@lists.freedesktop
   |org |.org

--- Comment #6 from Timothy Arceri  ---
Reassigning to r600 as it looks like this is probably a driver specific issue.

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[Mesa-dev] [PATCH v2 01/14] i915: remove early_z dri option

[Timothy Arceri]

This driver is in maintenance mode so lets remove this hidden
unsafe option.
---
 src/mesa/drivers/dri/i915/i915_vtbl.c | 8 
 src/mesa/drivers/dri/i915/intel_context.c | 2 --
 src/mesa/drivers/dri/i915/intel_context.h | 2 --
 src/mesa/drivers/dri/i915/intel_screen.c  | 4 
 4 files changed, 16 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c 
b/src/mesa/drivers/dri/i915/i915_vtbl.c
index 6a0a121856d..562c83a665f 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -609,14 +609,6 @@ i915_set_draw_region(struct intel_context *intel,
   value |= DV_PF_;
}
 
-   /* This isn't quite safe, thus being hidden behind an option.  When changing
-* the value of this bit, the pipeline needs to be MI_FLUSHed.  And it
-* can only be set when a depth buffer is already defined.
-*/
-   if (intel->is_945 && intel->use_early_z &&
-   depth_region->tiling != I915_TILING_NONE)
-  value |= CLASSIC_EARLY_DEPTH;
-
if (depth_region && depth_region->cpp == 4) {
   value |= DEPTH_FRMT_24_FIXED_8_OTHER;
}
diff --git a/src/mesa/drivers/dri/i915/intel_context.c 
b/src/mesa/drivers/dri/i915/intel_context.c
index 9a6e49dd827..728d6d58699 100644
--- a/src/mesa/drivers/dri/i915/intel_context.c
+++ b/src/mesa/drivers/dri/i915/intel_context.c
@@ -532,8 +532,6 @@ intelInitContext(struct intel_context *intel,
 
intel_fbo_init(intel);
 
-   intel->use_early_z = driQueryOptionb(>optionCache, "early_z");
-
intel->prim.primitive = ~0;
 
/* Force all software fallbacks */
diff --git a/src/mesa/drivers/dri/i915/intel_context.h 
b/src/mesa/drivers/dri/i915/intel_context.h
index a8339896f65..580af53f956 100644
--- a/src/mesa/drivers/dri/i915/intel_context.h
+++ b/src/mesa/drivers/dri/i915/intel_context.h
@@ -238,8 +238,6 @@ struct intel_context
 */
bool front_buffer_dirty;
 
-   bool use_early_z;
-
__DRIcontext *driContext;
struct intel_screen *intelScreen;
 
diff --git a/src/mesa/drivers/dri/i915/intel_screen.c 
b/src/mesa/drivers/dri/i915/intel_screen.c
index 27be9219e47..3d4f7ae94aa 100644
--- a/src/mesa/drivers/dri/i915/intel_screen.c
+++ b/src/mesa/drivers/dri/i915/intel_screen.c
@@ -57,10 +57,6 @@ DRI_CONF_BEGIN
 DRI_CONF_DESC_END
   DRI_CONF_OPT_END
 
-  DRI_CONF_OPT_BEGIN_B(early_z, "false")
-DRI_CONF_DESC(en, "Enable early Z in classic mode (unstable, 
945-only).")
-  DRI_CONF_OPT_END
-
   DRI_CONF_OPT_BEGIN_B(fragment_shader, "true")
 DRI_CONF_DESC(en, "Enable limited ARB_fragment_shader support on 
915/945.")
   DRI_CONF_OPT_END
-- 
2.17.1

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Re: [Mesa-dev] [PATCH 00/12] Compiler warning fixes, round 2

[Kai Wasserbäch]

Hey Lionel,
Lionel Landwerlin wrote on 19.08.2018 11:05:
> Patches 6, 7, 10 & 11 are :
> 
> Reviewed-by: Lionel Landwerlin 

thanks! Feel free to push, I don't have commit access (see cover letter).

> There are 2 existing series touching the same code, in patches 8, 9 & 12, I
> think should land before the warnings are fixed.

Hm, I can see why you might want to hold off on 8 and 9 then, but 12 shouldn't
break anything, should it? It might even work as a fixup for your other series?
Anyway, I can carry those three over to the next series, once I get most of this
into master. 

Cheers,
Kai



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[Mesa-dev] [PATCH v2 08/14] mesa: move legacy dri config option dither_mode

[Timothy Arceri]

---
 src/mesa/drivers/dri/radeon/radeon_screen.h | 12 
 src/util/xmlpool/ca.po  | 16 
 src/util/xmlpool/de.po  | 16 
 src/util/xmlpool/es.po  | 16 
 src/util/xmlpool/fr.po  | 16 
 src/util/xmlpool/nl.po  | 16 
 src/util/xmlpool/t_options.h| 12 
 7 files changed, 12 insertions(+), 92 deletions(-)

diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h 
b/src/mesa/drivers/dri/radeon/radeon_screen.h
index 35a20996f82..c5b8023d9d1 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -57,6 +57,18 @@ DRI_CONF_OPT_BEGIN_V(color_reduction,enum,def,"0:1") \
 DRI_CONF_DESC_END \
 DRI_CONF_OPT_END
 
+#define DRI_CONF_DITHER_XERRORDIFF 0
+#define DRI_CONF_DITHER_XERRORDIFFRESET 1
+#define DRI_CONF_DITHER_ORDERED 2
+#define DRI_CONF_DITHER_MODE(def) \
+DRI_CONF_OPT_BEGIN_V(dither_mode,enum,def,"0:2") \
+   DRI_CONF_DESC_BEGIN(en,"Color dithering method") \
+DRI_CONF_ENUM(0,"Horizontal error diffusion") \
+DRI_CONF_ENUM(1,"Horizontal error diffusion, reset error at 
line start") \
+DRI_CONF_ENUM(2,"Ordered 2D color dithering") \
+DRI_CONF_DESC_END \
+DRI_CONF_OPT_END
+
 
 #define DRI_CONF_TCL_SW 0
 #define DRI_CONF_TCL_PIPELINED 1
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index cab901ae194..5f78915b544 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -124,22 +124,6 @@ msgstr "Arrodoneix els components de color a baix"
 msgid "Round to nearest color"
 msgstr "Arrodoneix al color més proper"
 
-#: t_options.h:181
-msgid "Color dithering method"
-msgstr "Mètode de tramat de color"
-
-#: t_options.h:182
-msgid "Horizontal error diffusion"
-msgstr "Difusió d'error horitzontal"
-
-#: t_options.h:183
-msgid "Horizontal error diffusion, reset error at line start"
-msgstr "Difusió d'error horitzontal, reinicia l'error a l'inici de la línia"
-
-#: t_options.h:184
-msgid "Ordered 2D color dithering"
-msgstr "Tramat de color 2D ordenat"
-
 #: t_options.h:190
 msgid "Floating point depth buffer"
 msgstr "Buffer de profunditat de punt flotant"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index 421078441db..2ef0607cbb2 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -99,22 +99,6 @@ msgstr "Farbkomponenten abrunden"
 msgid "Round to nearest color"
 msgstr "Zur ähnlichsten Farbe runden"
 
-#: t_options.h:181
-msgid "Color dithering method"
-msgstr "Farbrasterungsmethode"
-
-#: t_options.h:182
-msgid "Horizontal error diffusion"
-msgstr "Horizontale Fehlerstreuung"
-
-#: t_options.h:183
-msgid "Horizontal error diffusion, reset error at line start"
-msgstr "Horizontale Fehlerstreuung, Fehler am Zeilenanfang zurücksetzen"
-
-#: t_options.h:184
-msgid "Ordered 2D color dithering"
-msgstr "Geordnete 2D Farbrasterung"
-
 #: t_options.h:190
 msgid "Floating point depth buffer"
 msgstr "Fließkomma z-Puffer"
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index fe9bce1bbba..cfb6c0eb18d 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -106,22 +106,6 @@ msgstr "Redondear hacia abajo los componentes de color"
 msgid "Round to nearest color"
 msgstr "Redondear al color más cercano"
 
-#: t_options.h:181
-msgid "Color dithering method"
-msgstr "Método de suavizado de color"
-
-#: t_options.h:182
-msgid "Horizontal error diffusion"
-msgstr "Difusión de error horizontal"
-
-#: t_options.h:183
-msgid "Horizontal error diffusion, reset error at line start"
-msgstr "Difusión de error horizontal, reiniciar error al comienzo de línea"
-
-#: t_options.h:184
-msgid "Ordered 2D color dithering"
-msgstr "Suavizado de color 2D ordenado"
-
 #: t_options.h:190
 msgid "Floating point depth buffer"
 msgstr "Búfer de profundidad en coma flotante"
diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index 609c6041e34..94a248069a0 100644
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -98,22 +98,6 @@ msgstr "Arrondi à l'inférieur"
 msgid "Round to nearest color"
 msgstr "Arrondi au plus proche"
 
-#: t_options.h:181
-msgid "Color dithering method"
-msgstr "Méthode de tramage"
-
-#: t_options.h:182
-msgid "Horizontal error diffusion"
-msgstr "Diffusion d'erreur horizontale"
-
-#: t_options.h:183
-msgid "Horizontal error diffusion, reset error at line start"
-msgstr "Diffusion d'erreur horizontale, réinitialisé pour chaque ligne"
-
-#: t_options.h:184
-msgid "Ordered 2D color dithering"
-msgstr "Tramage ordonné des couleurs"
-
 #: t_options.h:190
 msgid "Floating point depth buffer"
 msgstr "Z-buffer en virgule flottante"
diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
index 65071e57451..9beafb42224 100644
--- a/src/util/xmlpool/nl.po
+++ b/src/util/xmlpool/nl.po
@@ -86,22 +86,6 @@ msgstr 

[Mesa-dev] [PATCH v2 12/14] mesa: move legacy dri config option def_max_anisotropy

[Timothy Arceri]

---
 src/mesa/drivers/dri/radeon/radeon_screen.c | 5 +
 src/util/xmlpool/ca.po  | 4 
 src/util/xmlpool/de.po  | 4 
 src/util/xmlpool/es.po  | 4 
 src/util/xmlpool/fr.po  | 4 
 src/util/xmlpool/nl.po  | 4 
 src/util/xmlpool/sv.po  | 4 
 src/util/xmlpool/t_options.h| 5 -
 8 files changed, 5 insertions(+), 29 deletions(-)

diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c 
b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 6475e2f22c0..6345f2ce661 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -95,6 +95,11 @@ DRI_CONF_OPT_BEGIN_B(no_neg_lod_bias, def) \
 DRI_CONF_DESC(en,"Forbid negative texture LOD bias") \
 DRI_CONF_OPT_END
 
+#define DRI_CONF_DEF_MAX_ANISOTROPY(def,range) \
+DRI_CONF_OPT_BEGIN_V(def_max_anisotropy,float,def,range) \
+DRI_CONF_DESC(en,"Initial maximum value for anisotropic texture 
filtering") \
+DRI_CONF_OPT_END
+
 #if defined(RADEON_R100)   /* R100 */
 static const __DRIconfigOptionsExtension radeon_config_options = {
.base = { __DRI_CONFIG_OPTIONS, 1 },
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index 7760da13ac2..e8ff8af1bb4 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -102,10 +102,6 @@ msgstr "Prefereix 16 bits per texel"
 msgid "Force 16 bits per texel"
 msgstr "Força 16 bits per texel"
 
-#: t_options.h:143
-msgid "Initial maximum value for anisotropic texture filtering"
-msgstr "Valor màxim inicial per a la filtració de textura anisòtropa"
-
 #: t_options.h:195
 msgid "A post-processing filter to cel-shade the output"
 msgstr "Un filtre de postprocessament per a aplicar cel shading a la sortida"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index 9e466f7620a..8d5804f4433 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -79,10 +79,6 @@ msgstr "Bevorzuge 16 bits pro Texel"
 msgid "Force 16 bits per texel"
 msgstr "Erzwinge 16 bits pro Texel"
 
-#: t_options.h:143
-msgid "Initial maximum value for anisotropic texture filtering"
-msgstr "Initialer Maximalwert für anisotropische Texturfilterung"
-
 #: t_options.h:195
 msgid "A post-processing filter to cel-shade the output"
 msgstr "Nachbearbeitungsfilter für Cell Shading"
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index cd76fa39b4a..c79191f6c8b 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -86,10 +86,6 @@ msgstr "Preferir 16 bits por texel"
 msgid "Force 16 bits per texel"
 msgstr "Forzar a 16 bits por texel"
 
-#: t_options.h:143
-msgid "Initial maximum value for anisotropic texture filtering"
-msgstr "Valor máximo inicial para filtrado anisotrópico de textura"
-
 #: t_options.h:195
 msgid "A post-processing filter to cel-shade the output"
 msgstr "Un filtro de postprocesamiento para aplicar cel shading a la salida"
diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index d086b44a4b0..c1856aa0fd3 100644
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -78,10 +78,6 @@ msgstr "Prérérer 16 bits par texel"
 msgid "Force 16 bits per texel"
 msgstr "Forcer 16 bits par texel"
 
-#: t_options.h:143
-msgid "Initial maximum value for anisotropic texture filtering"
-msgstr "Valeur maximale initiale pour le filtrage anisotropique de texture"
-
 #: t_options.h:195
 msgid "A post-processing filter to cel-shade the output"
 msgstr ""
diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
index 38473fdc2de..50fb346 100644
--- a/src/util/xmlpool/nl.po
+++ b/src/util/xmlpool/nl.po
@@ -78,10 +78,6 @@ msgstr "Prefereer 16 bits per texel"
 msgid "Force 16 bits per texel"
 msgstr "Dwing 16 bits per texel af"
 
-#: t_options.h:143
-msgid "Initial maximum value for anisotropic texture filtering"
-msgstr "Initïele maximum waarde voor anisotrophische textuur filtering"
-
 #: t_options.h:182
 msgid "Horizontal error diffusion"
 msgstr "Horizontale foutdiffusie"
diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
index 8c3bca72e68..3e11072ea89 100644
--- a/src/util/xmlpool/sv.po
+++ b/src/util/xmlpool/sv.po
@@ -78,10 +78,6 @@ msgstr "Föredra 16 bitar per texel"
 msgid "Force 16 bits per texel"
 msgstr "Tvinga 16 bitar per texel"
 
-#: t_options.h:143
-msgid "Initial maximum value for anisotropic texture filtering"
-msgstr "Initialt maximalt värde för anisotropisk texturfiltrering"
-
 #: t_options.h:181
 msgid "Color dithering method"
 msgstr "Färgutjämningsmetod"
diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
index 4207280dcf9..47f35f1564f 100644
--- a/src/util/xmlpool/t_options.h
+++ b/src/util/xmlpool/t_options.h
@@ -156,11 +156,6 @@ DRI_CONF_OPT_BEGIN_V(texture_depth,enum,def,"0:3") \
 DRI_CONF_DESC_END \
 DRI_CONF_OPT_END
 
-#define DRI_CONF_DEF_MAX_ANISOTROPY(def,range) \

[Mesa-dev] [PATCH v2 05/14] mesa: move legacy hyperz option from dri config

[Timothy Arceri]

---
 src/mesa/drivers/dri/radeon/radeon_screen.c | 5 +
 src/util/xmlpool/ca.po  | 4 
 src/util/xmlpool/de.po  | 4 
 src/util/xmlpool/es.po  | 4 
 src/util/xmlpool/fr.po  | 4 
 src/util/xmlpool/nl.po  | 4 
 src/util/xmlpool/sv.po  | 4 
 src/util/xmlpool/t_options.h| 7 ---
 8 files changed, 5 insertions(+), 31 deletions(-)

diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c 
b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 5637361a916..4c93404607d 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -75,6 +75,11 @@ DRI_CONF_OPT_BEGIN_V(texture_units,int,def, # min ":" # max 
) \
 DRI_CONF_DESC(en,"Number of texture units used") \
 DRI_CONF_OPT_END
 
+#define DRI_CONF_HYPERZ(def) \
+DRI_CONF_OPT_BEGIN_B(hyperz, def) \
+DRI_CONF_DESC(en,"Use HyperZ to boost performance") \
+DRI_CONF_OPT_END
+
 #if defined(RADEON_R100)   /* R100 */
 static const __DRIconfigOptionsExtension radeon_config_options = {
.base = { __DRI_CONFIG_OPTIONS, 1 },
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index 6cfd8699a80..2c663d25027 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -258,10 +258,6 @@ msgstr ""
 "Sempre sincronitza amb el refresc vertical, l'aplicació tria l'interval "
 "mínim d'intercanvi"
 
-#: t_options.h:276
-msgid "Use HyperZ to boost performance"
-msgstr "Utilitza el HyperZ per a augmentar el rendiment"
-
 #: t_options.h:323
 msgid "Miscellaneous"
 msgstr "Miscel·lània"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index 90a35e70dcf..40095df3c40 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -233,10 +233,6 @@ msgstr ""
 "Immer mit der Bildwiederholung synchronisieren, Anwendung wählt das minimale "
 "Bildintervall"
 
-#: t_options.h:276
-msgid "Use HyperZ to boost performance"
-msgstr "HyperZ zur Leistungssteigerung verwenden"
-
 #: t_options.h:323
 msgid "Miscellaneous"
 msgstr ""
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index a087c0e1689..b1cfdd6e146 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -242,10 +242,6 @@ msgstr ""
 "Sincronizar siempre con el refresco vertical, la aplicación elige el "
 "intervalo de intercambio mínimo"
 
-#: t_options.h:276
-msgid "Use HyperZ to boost performance"
-msgstr "Usar HyperZ para potenciar rendimiento"
-
 #: t_options.h:323
 msgid "Miscellaneous"
 msgstr "Misceláneos"
diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index 8bcd08f9bf4..39bb6035823 100644
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -231,10 +231,6 @@ msgstr ""
 "Toujours synchroniser avec le balayage vertical, l'application choisit "
 "l'intervalle minimal"
 
-#: t_options.h:276
-msgid "Use HyperZ to boost performance"
-msgstr "Utiliser le HyperZ pour améliorer les performances"
-
 #: t_options.h:323
 msgid "Miscellaneous"
 msgstr ""
diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
index 303d45517ff..8dd73ca5dfe 100644
--- a/src/util/xmlpool/nl.po
+++ b/src/util/xmlpool/nl.po
@@ -230,10 +230,6 @@ msgstr ""
 "Synchroniseer altijd met verticale verversing, de applicatie kiest het "
 "minimum omwisselingsinterval"
 
-#: t_options.h:276
-msgid "Use HyperZ to boost performance"
-msgstr "Gebruik HyperZ om de prestaties te verbeteren"
-
 #: t_options.h:323
 msgid "Miscellaneous"
 msgstr ""
diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
index c60d1aaf226..319caa73876 100644
--- a/src/util/xmlpool/sv.po
+++ b/src/util/xmlpool/sv.po
@@ -224,10 +224,6 @@ msgstr ""
 "Synkronisera alltid med vertikal uppdatering, programmet väljer den minsta "
 "växlingsintervallen"
 
-#: t_options.h:276
-msgid "Use HyperZ to boost performance"
-msgstr "Använd HyperZ för att maximera prestandan"
-
 #: t_options.h:323
 msgid "Miscellaneous"
 msgstr ""
diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
index f8623bd9f6d..a946a5d363a 100644
--- a/src/util/xmlpool/t_options.h
+++ b/src/util/xmlpool/t_options.h
@@ -287,13 +287,6 @@ DRI_CONF_OPT_BEGIN_V(vblank_mode,enum,def,"0:3") \
 DRI_CONF_DESC_END \
 DRI_CONF_OPT_END
 
-#define DRI_CONF_HYPERZ_DISABLED 0
-#define DRI_CONF_HYPERZ_ENABLED 1
-#define DRI_CONF_HYPERZ(def) \
-DRI_CONF_OPT_BEGIN_B(hyperz, def) \
-DRI_CONF_DESC(en,gettext("Use HyperZ to boost performance")) \
-DRI_CONF_OPT_END
-
 #define DRI_CONF_MESA_GLTHREAD(def) \
 DRI_CONF_OPT_BEGIN_B(mesa_glthread, def) \
 DRI_CONF_DESC(en,gettext("Enable offloading GL driver work to a 
separate thread")) \
-- 
2.17.1

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[Mesa-dev] [PATCH v2 02/14] i965: remove unused no_rast bool

[Timothy Arceri]

Forcing software fallbacks for i965 hasn't been an option since
5e3c093ff866.
---
 src/mesa/drivers/dri/i965/brw_context.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 72be8f2a4d0..c32def7c3d7 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -814,7 +814,6 @@ struct brw_context
 * drirc options:
 * @{
 */
-   bool no_rast;
bool always_flush_batch;
bool always_flush_cache;
bool disable_throttling;
-- 
2.17.1

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[Mesa-dev] [PATCH v2 13/14] mesa: move legacy dri config option fthrottle_mode

[Timothy Arceri]

---
 src/mesa/drivers/dri/radeon/radeon_screen.h | 12 
 src/util/xmlpool/ca.po  | 17 -
 src/util/xmlpool/de.po  | 17 -
 src/util/xmlpool/es.po  | 17 -
 src/util/xmlpool/fr.po  | 16 
 src/util/xmlpool/nl.po  | 19 ---
 src/util/xmlpool/sv.po  | 16 
 src/util/xmlpool/t_options.h| 12 
 8 files changed, 12 insertions(+), 114 deletions(-)

diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h 
b/src/mesa/drivers/dri/radeon/radeon_screen.h
index e36e438e295..30202aec8b0 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -79,6 +79,18 @@ DRI_CONF_OPT_BEGIN_V(round_mode,enum,def,"0:1") \
 DRI_CONF_DESC_END \
 DRI_CONF_OPT_END
 
+#define DRI_CONF_FTHROTTLE_BUSY 0
+#define DRI_CONF_FTHROTTLE_USLEEPS 1
+#define DRI_CONF_FTHROTTLE_IRQS 2
+#define DRI_CONF_FTHROTTLE_MODE(def) \
+DRI_CONF_OPT_BEGIN_V(fthrottle_mode,enum,def,"0:2") \
+DRI_CONF_DESC_BEGIN(en,"Method to limit rendering latency") \
+DRI_CONF_ENUM(0,"Busy waiting for the graphics hardware") \
+DRI_CONF_ENUM(1,"Sleep for brief intervals while waiting for 
the graphics hardware") \
+DRI_CONF_ENUM(2,"Let the graphics hardware emit a software 
interrupt and sleep") \
+DRI_CONF_DESC_END \
+DRI_CONF_OPT_END
+
 
 #define DRI_CONF_TCL_SW 0
 #define DRI_CONF_TCL_PIPELINED 1
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index e8ff8af1bb4..ddb37b6dd8f 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -139,23 +139,6 @@ msgstr ""
 msgid "Performance"
 msgstr "Rendiment"
 
-#: t_options.h:251
-msgid "Method to limit rendering latency"
-msgstr "Mètode per a limitar la latència de renderització"
-
-#: t_options.h:252
-msgid "Busy waiting for the graphics hardware"
-msgstr "Espera activa pel maquinari de gràfics"
-
-#: t_options.h:253
-msgid "Sleep for brief intervals while waiting for the graphics hardware"
-msgstr "Dorm per intervals breus mentre s'espera al maquinari de gràfics"
-
-#: t_options.h:254
-msgid "Let the graphics hardware emit a software interrupt and sleep"
-msgstr ""
-"Deixa que el maquinari de gràfics emeti una interrupció de programari i dormi"
-
 #: t_options.h:264
 msgid "Synchronization with vertical refresh (swap intervals)"
 msgstr "Sincronització amb refresc vertical (intervals d'intercanvi)"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index 8d5804f4433..7b5b9510cfc 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -115,23 +115,6 @@ msgstr ""
 msgid "Performance"
 msgstr "Leistung"
 
-#: t_options.h:251
-msgid "Method to limit rendering latency"
-msgstr "Methode zur Begrenzung der Bildverzögerung"
-
-#: t_options.h:252
-msgid "Busy waiting for the graphics hardware"
-msgstr "Aktives Warten auf die Grafikhardware"
-
-#: t_options.h:253
-msgid "Sleep for brief intervals while waiting for the graphics hardware"
-msgstr "Kurze Schlafintervalle beim Warten auf die Grafikhardware"
-
-#: t_options.h:254
-msgid "Let the graphics hardware emit a software interrupt and sleep"
-msgstr ""
-"Die Grafikhardware eine Softwareunterbrechnung erzeugen lassen und schlafen"
-
 #: t_options.h:264
 msgid "Synchronization with vertical refresh (swap intervals)"
 msgstr "Synchronisation mit der vertikalen Bildwiederholung"
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index c79191f6c8b..81106ae7139 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -122,23 +122,6 @@ msgstr ""
 msgid "Performance"
 msgstr "Rendimiento"
 
-#: t_options.h:251
-msgid "Method to limit rendering latency"
-msgstr "Método para limitar la latencia de renderización"
-
-#: t_options.h:252
-msgid "Busy waiting for the graphics hardware"
-msgstr "Esperar activamente al hardware gráfico"
-
-#: t_options.h:253
-msgid "Sleep for brief intervals while waiting for the graphics hardware"
-msgstr "Dormir en intervalos cortos mientras se espera al hardware gráfico"
-
-#: t_options.h:254
-msgid "Let the graphics hardware emit a software interrupt and sleep"
-msgstr ""
-"Permitir que el hardware gráfico emita una interrupción de software y duerma"
-
 #: t_options.h:264
 msgid "Synchronization with vertical refresh (swap intervals)"
 msgstr "Sincronización con el refresco vertical (intervalos de intercambio)"
diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index c1856aa0fd3..f1a2ce0748e 100644
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -110,22 +110,6 @@ msgstr ""
 msgid "Performance"
 msgstr "Performance"
 
-#: t_options.h:251
-msgid "Method to limit rendering latency"
-msgstr "Méthode d'attente de la carte graphique"
-
-#: t_options.h:252
-msgid "Busy waiting for the graphics hardware"
-msgstr "Attente 

[Mesa-dev] [PATCH v3 4/7] nir: add complex_loop bool to loop info

[Timothy Arceri]

In order to be sure loop_terminator_list is an accurate
representation of all the jumps in the loop we need to be sure we
didn't encounter any other complex behaviour such as continues,
nested breaks, etc during analysis.

This will be used in the following patch.

Reviewed-by: Jason Ekstrand 
---
 src/compiler/nir/nir.h  | 6 ++
 src/compiler/nir/nir_loop_analyze.c | 8 ++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index d0fa693884b..7b9d174e1fc 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1794,6 +1794,12 @@ typedef struct {
/* Unroll the loop regardless of its size */
bool force_unroll;
 
+   /* Does the loop contain complex loop terminators, continues or other
+* complex behaviours? If this is true we can't rely on
+* loop_terminator_list to be complete or accurate.
+*/
+   bool complex_loop;
+
nir_loop_terminator *limiting_terminator;
 
/* A list of loop_terminators terminating this loop. */
diff --git a/src/compiler/nir/nir_loop_analyze.c 
b/src/compiler/nir/nir_loop_analyze.c
index 5454b7691ba..9c3fd2f286f 100644
--- a/src/compiler/nir/nir_loop_analyze.c
+++ b/src/compiler/nir/nir_loop_analyze.c
@@ -317,15 +317,19 @@ find_loop_terminators(loop_info_state *state)
   * not find a loop terminator, but there is a break-statement then
   * we should return false so that we do not try to find trip-count
   */
- if (!nir_is_trivial_loop_if(nif, break_blk))
+ if (!nir_is_trivial_loop_if(nif, break_blk)) {
+state->loop->info->complex_loop = true;
 return false;
+ }
 
  /* Continue if the if contained no jumps at all */
  if (!break_blk)
 continue;
 
- if (nif->condition.ssa->parent_instr->type == nir_instr_type_phi)
+ if (nif->condition.ssa->parent_instr->type == nir_instr_type_phi) {
+state->loop->info->complex_loop = true;
 return false;
+ }
 
  nir_loop_terminator *terminator =
 rzalloc(state->loop->info, nir_loop_terminator);
-- 
2.17.1

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[Mesa-dev] [PATCH v3 7/7] nir: add loop unroll support for complex wrapper loops

[Timothy Arceri]

In GLSL IR we cheat with switch statements and simply convert them
into loops with a single iteration. This allowed us to make use of
the existing jump instruction handling provided by the loop handing
code, it also allows dead code to be cleaned up once we have
wrapped the code in a loop.

However using loops in this way created previously unrollable loops
which limits further optimisations. Here we provide a way to unroll
loops that end in a break and have multiple other exits.

All shader-db changes are from the dolphin uber shaders. There is a
small amount of HURT shaders but in general the improvements far
exceed the HURT.

shader-db results IVB:

total instructions in shared programs: 10018187 -> 10016468 (-0.02%)
instructions in affected programs: 104080 -> 102361 (-1.65%)
helped: 36
HURT: 15

total cycles in shared programs: 220065064 -> 154529655 (-29.78%)
cycles in affected programs: 126063017 -> 60527608 (-51.99%)
helped: 51
HURT: 0

total loops in shared programs: 2515 -> 2308 (-8.23%)
loops in affected programs: 903 -> 696 (-22.92%)
helped: 51
HURT: 0

total spills in shared programs: 4370 -> 4124 (-5.63%)
spills in affected programs: 1397 -> 1151 (-17.61%)
helped: 9
HURT: 12

total fills in shared programs: 4581 -> 4419 (-3.54%)
fills in affected programs: 2201 -> 2039 (-7.36%)
helped: 9
HURT: 15
---
 src/compiler/nir/nir_opt_loop_unroll.c | 113 +
 1 file changed, 76 insertions(+), 37 deletions(-)

diff --git a/src/compiler/nir/nir_opt_loop_unroll.c 
b/src/compiler/nir/nir_opt_loop_unroll.c
index 9c33267cb72..fa60523aac7 100644
--- a/src/compiler/nir/nir_opt_loop_unroll.c
+++ b/src/compiler/nir/nir_opt_loop_unroll.c
@@ -67,7 +67,6 @@ loop_prepare_for_unroll(nir_loop *loop)
/* Remove continue if its the last instruction in the loop */
nir_instr *last_instr = nir_block_last_instr(nir_loop_last_block(loop));
if (last_instr && last_instr->type == nir_instr_type_jump) {
-  assert(nir_instr_as_jump(last_instr)->type == nir_jump_continue);
   nir_instr_remove(last_instr);
}
 }
@@ -474,54 +473,91 @@ complex_unroll(nir_loop *loop, nir_loop_terminator 
*unlimit_term,
 static bool
 wrapper_unroll(nir_loop *loop)
 {
-   bool progress = false;
-
-   nir_block *blk_after_loop =
-  nir_cursor_current_block(nir_after_cf_node(>cf_node));
-
-   /* There may still be some single src phis following the loop that
-* have not yet been cleaned up by another pass. Tidy those up before
-* unrolling the loop.
-*/
-   nir_foreach_instr_safe(instr, blk_after_loop) {
-  if (instr->type != nir_instr_type_phi)
- break;
+   if (!list_empty(>info->loop_terminator_list)) {
 
-  nir_phi_instr *phi = nir_instr_as_phi(instr);
-  assert(exec_list_length(>srcs) == 1);
+  /* Unrolling a loop with a large number of exits can result in a
+   * large inrease in register pressure. For now we just skip
+   * unrolling if we have more than 3 exits (not including the break
+   * at the end of the loop).
+   *
+   * TODO: Most loops that fit this pattern are simply switch
+   * statements that are converted to a loop to take advantage of
+   * exiting jump instruction handling. In this case we could make
+   * use of a binary seach pattern like we do in
+   * nir_lower_indirect_derefs(), this should allow us to unroll the
+   * loops in an optimal way and should also avoid some of the
+   * register pressure that comes from simply nesting the
+   * terminators one after the other.
+   */
+  if (list_length(>info->loop_terminator_list) > 3)
+ return false;
+
+  loop_prepare_for_unroll(loop);
+
+  nir_cursor cursor = nir_after_block(nir_loop_last_block(loop));
+  list_for_each_entry(nir_loop_terminator, terminator,
+  >info->loop_terminator_list,
+  loop_terminator_link) {
+
+ /* Remove break from the terminator */
+ nir_instr *break_instr =
+nir_block_last_instr(terminator->break_block);
+ nir_instr_remove(break_instr);
+
+ /* Pluck out the loop body. */
+ nir_cf_list loop_body;
+ nir_cf_extract(_body,
+nir_after_cf_node(>nif->cf_node),
+cursor);
+
+ /* Reinsert loop body into continue from block */
+ nir_cf_reinsert(_body,
+ nir_after_block(terminator->continue_from_block));
+
+ cursor = terminator->continue_from_then ?
+   nir_after_block(nir_if_last_then_block(terminator->nif)) :
+   nir_after_block(nir_if_last_else_block(terminator->nif));
+  }
+   } else {
+  nir_block *blk_after_loop =
+ nir_cursor_current_block(nir_after_cf_node(>cf_node));
 
-  nir_phi_src *phi_src = exec_node_data(nir_phi_src,
-exec_list_get_head(>srcs),
-node);
+  /* There may 

[Mesa-dev] [PATCH v3 3/7] nir: always attempt to find loop terminators

[Timothy Arceri]

This will help later patches with unrolling loops that end with a
break i.e. loops the always exit on their first interation.

Reviewed-by: Jason Ekstrand 
---
 src/compiler/nir/nir_loop_analyze.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/compiler/nir/nir_loop_analyze.c 
b/src/compiler/nir/nir_loop_analyze.c
index d564296aa67..5454b7691ba 100644
--- a/src/compiler/nir/nir_loop_analyze.c
+++ b/src/compiler/nir/nir_loop_analyze.c
@@ -717,13 +717,6 @@ get_loop_info(loop_info_state *state, nir_function_impl 
*impl)
   }
}
 
-   /* Induction analysis needs invariance information so get that first */
-   compute_invariance_information(state);
-
-   /* We have invariance information so try to find induction variables */
-   if (!compute_induction_information(state))
-  return;
-
/* Try to find all simple terminators of the loop. If we can't find any,
 * or we find possible terminators that have side effects then bail.
 */
@@ -737,6 +730,13 @@ get_loop_info(loop_info_state *state, nir_function_impl 
*impl)
   return;
}
 
+   /* Induction analysis needs invariance information so get that first */
+   compute_invariance_information(state);
+
+   /* We have invariance information so try to find induction variables */
+   if (!compute_induction_information(state))
+  return;
+
/* Run through each of the terminators and try to compute a trip-count */
find_trip_count(state);
 
-- 
2.17.1

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Re: [Mesa-dev] [PATCH] anv/icl: Disable binding table prefetching

[Kenneth Graunke]

On Friday, August 17, 2018 5:14:52 PM PDT Anuj Phogat wrote:
> Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to
> disable prefetching of binding tables for ICLLP A0 and B0
> steppings. We have a similar patch for i965 driver in  Mesa
> commit a5889d70.
> 
> Signed-off-by: Anuj Phogat 
> ---
>  src/intel/vulkan/genX_pipeline.c | 21 +++--
>  1 file changed, 15 insertions(+), 6 deletions(-)

Looks reasonable, we can always revert it later.

Reviewed-by: Kenneth Graunke 


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[Mesa-dev] [PATCH v3 2/7] nir: propagates if condition evaluation down some alu chains

[Timothy Arceri]

shader-db IVB results:

total instructions in shared programs: 9993483 -> 9993472 (-0.00%)
instructions in affected programs: 1300 -> 1289 (-0.85%)
helped: 11
HURT: 0

total cycles in shared programs: 219476091 -> 219476059 (-0.00%)
cycles in affected programs: 7675 -> 7643 (-0.42%)
helped: 10
HURT: 1
---
 src/compiler/nir/nir_opt_if.c | 155 --
 1 file changed, 149 insertions(+), 6 deletions(-)

diff --git a/src/compiler/nir/nir_opt_if.c b/src/compiler/nir/nir_opt_if.c
index 8c886041708..95c6dbb136a 100644
--- a/src/compiler/nir/nir_opt_if.c
+++ b/src/compiler/nir/nir_opt_if.c
@@ -405,9 +405,134 @@ replace_if_condition_use_with_const(nir_src *use, 
unsigned nir_boolean,
   nir_instr_rewrite_src(use->parent_instr, use, new_src);
 }
 
+/*
+ * This propagates if condition evaluation down the chain of some alu
+ * instructions. For example by checking the use of some of the following alu
+ * instruction we can eventually replace ssa_107 with NIR_TRUE.
+ *
+ *   loop {
+ *  block block_1:
+ *  vec1 32 ssa_85 = load_const (0x0002)
+ *  vec1 32 ssa_86 = ieq ssa_48, ssa_85
+ *  vec1 32 ssa_87 = load_const (0x0001)
+ *  vec1 32 ssa_88 = ieq ssa_48, ssa_87
+ *  vec1 32 ssa_89 = ior ssa_86, ssa_88
+ *  vec1 32 ssa_90 = ieq ssa_48, ssa_0
+ *  vec1 32 ssa_91 = ior ssa_89, ssa_90
+ *  if ssa_86 {
+ * block block_2:
+ * ...
+ *break
+ *  } else {
+ *block block_3:
+ *  }
+ *  block block_4:
+ *  if ssa_88 {
+ *block block_5:
+ * ...
+ *break
+ *  } else {
+ *block block_6:
+ *  }
+ *  block block_7:
+ *  if ssa_90 {
+ *block block_8:
+ * ...
+ *break
+ *  } else {
+ *block block_9:
+ *  }
+ *  block block_10:
+ *  vec1 32 ssa_107 = inot ssa_91
+ *  if ssa_107 {
+ *block block_11:
+ *break
+ *  } else {
+ *block block_12:
+ *  }
+ *   }
+ */
 static bool
-evaluate_condition_use(nir_if *nif, nir_src *use_src, void *mem_ctx,
-   bool if_condition)
+propagate_condition_eval(nir_builder *b, nir_if *nif, nir_src *use_src,
+ nir_src *alu_use, nir_alu_instr *alu, void *mem_ctx,
+ bool if_condition)
+{
+   bool progress = false;
+
+   nir_block *use_block;
+   if (if_condition) {
+  use_block =
+ nir_cf_node_as_block(nir_cf_node_prev(_use->parent_if->cf_node));
+   } else {
+  use_block = alu_use->parent_instr->block;
+   }
+
+   if (nir_op_infos[alu->op].num_inputs == 1) {
+  if (nir_block_dominates(nir_if_first_then_block(nif), use_block)) {
+ replace_if_condition_use_with_const(alu_use, NIR_TRUE, mem_ctx,
+ if_condition);
+ progress = true;
+  } else if (nir_block_dominates(nir_if_first_else_block(nif),
+ use_block)) {
+ replace_if_condition_use_with_const(alu_use, NIR_FALSE, mem_ctx,
+ if_condition);
+ progress = true;
+  }
+   } else {
+  assert(alu->op == nir_op_ior || alu->op == nir_op_iand);
+
+  bool found = false;
+  unsigned nir_boolean = 0;
+  if (nir_block_dominates(nir_if_first_then_block(nif), use_block)) {
+ nir_boolean = NIR_TRUE;
+ found = true;
+  } else if (nir_block_dominates(nir_if_first_else_block(nif),
+ use_block)) {
+ nir_boolean = NIR_FALSE;
+ found = true;
+  }
+
+  if (found) {
+ nir_ssa_def *def[2];
+ for (unsigned i = 0; i < 2; i++) {
+if (alu->src[i].src.ssa == use_src->ssa) {
+   if (if_condition) {
+  b->cursor =
+ nir_before_cf_node(_use->parent_if->cf_node);
+   } else {
+  b->cursor = nir_before_instr(alu_use->parent_instr);
+   }
+
+   nir_const_value value;
+   value.u32[0] = nir_boolean;
+
+   def[i] = nir_build_imm(b, 1, 32, value);
+} else {
+   def[i] = alu->src[i].src.ssa;
+}
+ }
+
+ nir_ssa_def *nalu =
+nir_build_alu(b, alu->op, def[0], def[1], NULL, NULL);
+
+ /* Rewrite use to use new alu instruction */
+ nir_src new_src = nir_src_for_ssa(nalu);
+
+ if (if_condition)
+nir_if_rewrite_condition(alu_use->parent_if, new_src);
+ else
+nir_instr_rewrite_src(alu_use->parent_instr, alu_use, new_src);
+
+ progress = true;
+  }
+   }
+
+   return progress;
+}
+
+static bool
+evaluate_condition_use(nir_builder *b, nir_if *nif, nir_src *use_src,
+   void *mem_ctx, bool if_condition)
 {
bool progress = false;
 
@@ -439,23 +564,41 @@ 

Re: [Mesa-dev] [RFC][PATCH 3/5] mesa: Add support for AMD_depth_clamp_separate

[Sagar Ghuge]

On 08/13/2018 03:52 PM, Ian Romanick wrote:
> On 08/09/2018 01:09 PM, Marek Olšák wrote:
>> On Wed, Aug 1, 2018 at 11:31 PM, Sagar Ghuge  wrote:
>>> enable _mesa_PushAttrib() and _mesa_PopAttrib()
>>> to handle GL_DEPTH_CLAMP_NEAR_AMD and
>>> GL_DEPTH_CLAMP_FAR_AMD tokens.
>>>
>>> Signed-off-by: Sagar Ghuge 
>>> ---
>>>  src/mesa/main/attrib.c | 16 
>>>  1 file changed, 16 insertions(+)
>>>
>>> diff --git a/src/mesa/main/attrib.c b/src/mesa/main/attrib.c
>>> index cbe93ab6fa..d9f165b428 100644
>>> --- a/src/mesa/main/attrib.c
>>> +++ b/src/mesa/main/attrib.c
>>> @@ -73,6 +73,8 @@ struct gl_enable_attrib
>>> GLboolean ColorMaterial;
>>> GLboolean CullFace;
>>> GLboolean DepthClamp;
>>> +   GLboolean DepthClampNear;
>>> +   GLboolean DepthClampFar;
>>
>> The first patch uses this. Also, DepthClamp can be removed, because
>> DepthClampNear+Far replace it, right?
> 
> Based on your comment on patch 4 and my comments on patch 0, maybe we
> should:
> 
> - Remove DepthClamp.  Add _DepthClamp, DepthClampNear, and DepthClampFar.

I might be missing some pieces. But DepthClampNear + far can replaces 
DepthClamp. so why do we need _DepthClamp ? (Adding _DepthClamp means 
it will be derived from DepthClampNear+far, correct ? removing DepthClamp
here means, need to completely get rid of every reference of 
DepthClamp in source code? ) 

> 
> - If GL_DEPTH_CLAMP is set, set all three.  If GL_DEPTH_CLAMP is
> cleared, clear all three.
> 
> - If either of GL_DEPTH_CLAMP_FAR_AMD or GL_DEPTH_CLAMP_NEAR_AMD
> changes, change _DepthClamp to DepthClampNear || DepthClampFar.
> 

We only need to handle this case - "Querying DEPTH_CLAMP will return TRUE if 
DEPTH_CLAMP_NEAR_AMD _or_
DEPTH_CLAMP_FAR_AMD is enabled." 
I think we don't have to keep changing _DepthClamp, because if we do it
then it will enable depth clamping for both the planes and will get different 
behavior.
Please correct me if I am wrong or missing anything. 

> - Drivers that enable AMD_depth_clamp_separate will only ever look at
> DepthClampNear and DepthClampFar.
> 
> I think that gets all the cases correct with the minimum fuss.  Marek,
> what do you think?
> 
>> Marek
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>> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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[Mesa-dev] [PATCH v2 11/14] mesa: move legacy dri config option no_neg_lod_bias

[Timothy Arceri]

---
 src/mesa/drivers/dri/radeon/radeon_screen.c | 5 +
 src/util/xmlpool/ca.po  | 6 --
 src/util/xmlpool/de.po  | 4 
 src/util/xmlpool/es.po  | 4 
 src/util/xmlpool/fr.po  | 4 
 src/util/xmlpool/nl.po  | 4 
 src/util/xmlpool/sv.po  | 4 
 src/util/xmlpool/t_options.h| 5 -
 8 files changed, 5 insertions(+), 31 deletions(-)

diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c 
b/src/mesa/drivers/dri/radeon/radeon_screen.c
index fe484abf73f..6475e2f22c0 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -90,6 +90,11 @@ DRI_CONF_OPT_BEGIN_V(tcl_mode,enum,def,"0:3") \
 DRI_CONF_DESC_END \
 DRI_CONF_OPT_END
 
+#define DRI_CONF_NO_NEG_LOD_BIAS(def) \
+DRI_CONF_OPT_BEGIN_B(no_neg_lod_bias, def) \
+DRI_CONF_DESC(en,"Forbid negative texture LOD bias") \
+DRI_CONF_OPT_END
+
 #if defined(RADEON_R100)   /* R100 */
 static const __DRIconfigOptionsExtension radeon_config_options = {
.base = { __DRI_CONFIG_OPTIONS, 1 },
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index 1710a2ce199..7760da13ac2 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -106,12 +106,6 @@ msgstr "Força 16 bits per texel"
 msgid "Initial maximum value for anisotropic texture filtering"
 msgstr "Valor màxim inicial per a la filtració de textura anisòtropa"
 
-#: t_options.h:148
-msgid "Forbid negative texture LOD bias"
-msgstr ""
-"Prohibeix una parcialitat negativa del Nivell de Detalle (LOD) de les "
-"textures"
-
 #: t_options.h:195
 msgid "A post-processing filter to cel-shade the output"
 msgstr "Un filtre de postprocessament per a aplicar cel shading a la sortida"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index 5581725a251..9e466f7620a 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -83,10 +83,6 @@ msgstr "Erzwinge 16 bits pro Texel"
 msgid "Initial maximum value for anisotropic texture filtering"
 msgstr "Initialer Maximalwert für anisotropische Texturfilterung"
 
-#: t_options.h:148
-msgid "Forbid negative texture LOD bias"
-msgstr "Verbiete negative Textur-Detailgradverschiebung"
-
 #: t_options.h:195
 msgid "A post-processing filter to cel-shade the output"
 msgstr "Nachbearbeitungsfilter für Cell Shading"
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index 85288bfbe8a..cd76fa39b4a 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -90,10 +90,6 @@ msgstr "Forzar a 16 bits por texel"
 msgid "Initial maximum value for anisotropic texture filtering"
 msgstr "Valor máximo inicial para filtrado anisotrópico de textura"
 
-#: t_options.h:148
-msgid "Forbid negative texture LOD bias"
-msgstr "Prohibir valores negativos de Nivel De Detalle (LOD) de texturas"
-
 #: t_options.h:195
 msgid "A post-processing filter to cel-shade the output"
 msgstr "Un filtro de postprocesamiento para aplicar cel shading a la salida"
diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index 1f2d04cd396..d086b44a4b0 100644
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -82,10 +82,6 @@ msgstr "Forcer 16 bits par texel"
 msgid "Initial maximum value for anisotropic texture filtering"
 msgstr "Valeur maximale initiale pour le filtrage anisotropique de texture"
 
-#: t_options.h:148
-msgid "Forbid negative texture LOD bias"
-msgstr "Interdire le LOD bias negatif"
-
 #: t_options.h:195
 msgid "A post-processing filter to cel-shade the output"
 msgstr ""
diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
index 21845ce879c..38473fdc2de 100644
--- a/src/util/xmlpool/nl.po
+++ b/src/util/xmlpool/nl.po
@@ -82,10 +82,6 @@ msgstr "Dwing 16 bits per texel af"
 msgid "Initial maximum value for anisotropic texture filtering"
 msgstr "Initïele maximum waarde voor anisotrophische textuur filtering"
 
-#: t_options.h:148
-msgid "Forbid negative texture LOD bias"
-msgstr "Verbied negatief niveau detailonderscheid (LOD) van texturen"
-
 #: t_options.h:182
 msgid "Horizontal error diffusion"
 msgstr "Horizontale foutdiffusie"
diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
index 61d735b86c1..8c3bca72e68 100644
--- a/src/util/xmlpool/sv.po
+++ b/src/util/xmlpool/sv.po
@@ -82,10 +82,6 @@ msgstr "Tvinga 16 bitar per texel"
 msgid "Initial maximum value for anisotropic texture filtering"
 msgstr "Initialt maximalt värde för anisotropisk texturfiltrering"
 
-#: t_options.h:148
-msgid "Forbid negative texture LOD bias"
-msgstr "Förbjud negativ LOD-kompensation för texturer"
-
 #: t_options.h:181
 msgid "Color dithering method"
 msgstr "Färgutjämningsmetod"
diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
index 9d7dca54a94..4207280dcf9 100644
--- a/src/util/xmlpool/t_options.h
+++ b/src/util/xmlpool/t_options.h
@@ -161,11 +161,6 @@ 

[Mesa-dev] [PATCH v2 04/14] mesa: remove unused dri config option disable_shader_bit_encoding

[Timothy Arceri]

This was added as a workaround for Heaven 3.0 but was later removed
by 5ead448719f3 to allow Heaven 4.0 to work correctly.
---
 src/gallium/auxiliary/pipe-loader/driinfo_gallium.h | 1 -
 src/gallium/include/state_tracker/st_api.h  | 1 -
 src/gallium/state_trackers/dri/dri_screen.c | 2 --
 src/gallium/state_trackers/osmesa/osmesa.c  | 1 -
 src/mesa/state_tracker/st_extensions.c  | 4 +---
 src/util/xmlpool/ca.po  | 4 
 src/util/xmlpool/de.po  | 4 
 src/util/xmlpool/es.po  | 4 
 src/util/xmlpool/fr.po  | 4 
 src/util/xmlpool/nl.po  | 4 
 src/util/xmlpool/sv.po  | 4 
 src/util/xmlpool/t_options.h| 5 -
 12 files changed, 1 insertion(+), 37 deletions(-)

diff --git a/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h 
b/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
index 90dbf658a6d..b8f0fe64098 100644
--- a/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
+++ b/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
@@ -20,7 +20,6 @@ DRI_CONF_SECTION_DEBUG
DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
-   DRI_CONF_DISABLE_SHADER_BIT_ENCODING("false")
DRI_CONF_FORCE_GLSL_VERSION(0)
DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
DRI_CONF_ALLOW_GLSL_BUILTIN_CONST_EXPRESSION("false")
diff --git a/src/gallium/include/state_tracker/st_api.h 
b/src/gallium/include/state_tracker/st_api.h
index 5b72c0afc99..8d386a82a63 100644
--- a/src/gallium/include/state_tracker/st_api.h
+++ b/src/gallium/include/state_tracker/st_api.h
@@ -218,7 +218,6 @@ struct st_config_options
 {
boolean disable_blend_func_extended;
boolean disable_glsl_line_continuations;
-   boolean disable_shader_bit_encoding;
boolean force_glsl_extensions_warn;
unsigned force_glsl_version;
boolean allow_glsl_extension_directive_midshader;
diff --git a/src/gallium/state_trackers/dri/dri_screen.c 
b/src/gallium/state_trackers/dri/dri_screen.c
index e5bc47391e7..3e4de59a433 100644
--- a/src/gallium/state_trackers/dri/dri_screen.c
+++ b/src/gallium/state_trackers/dri/dri_screen.c
@@ -66,8 +66,6 @@ dri_fill_st_options(struct dri_screen *screen)
   driQueryOptionb(optionCache, "disable_blend_func_extended");
options->disable_glsl_line_continuations =
   driQueryOptionb(optionCache, "disable_glsl_line_continuations");
-   options->disable_shader_bit_encoding =
-  driQueryOptionb(optionCache, "disable_shader_bit_encoding");
options->force_glsl_extensions_warn =
   driQueryOptionb(optionCache, "force_glsl_extensions_warn");
options->force_glsl_version =
diff --git a/src/gallium/state_trackers/osmesa/osmesa.c 
b/src/gallium/state_trackers/osmesa/osmesa.c
index 8baec0a0e44..e7e0ab13acb 100644
--- a/src/gallium/state_trackers/osmesa/osmesa.c
+++ b/src/gallium/state_trackers/osmesa/osmesa.c
@@ -689,7 +689,6 @@ OSMesaCreateContextAttribs(const int *attribList, 
OSMesaContext sharelist)
attribs.options.force_glsl_extensions_warn = FALSE;
attribs.options.disable_blend_func_extended = FALSE;
attribs.options.disable_glsl_line_continuations = FALSE;
-   attribs.options.disable_shader_bit_encoding = FALSE;
attribs.options.force_glsl_version = 0;
 
osmesa_init_st_visual(,
diff --git a/src/mesa/state_tracker/st_extensions.c 
b/src/mesa/state_tracker/st_extensions.c
index db08d5169af..a81c68dd53a 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -1020,9 +1020,7 @@ void st_init_extensions(struct pipe_screen *screen,
   extensions->ARB_shading_language_420pack = GL_TRUE;
   extensions->ARB_texture_query_levels = GL_TRUE;
 
-  if (!options->disable_shader_bit_encoding) {
- extensions->ARB_shader_bit_encoding = GL_TRUE;
-  }
+  extensions->ARB_shader_bit_encoding = GL_TRUE;
 
   extensions->EXT_shader_integer_mix = GL_TRUE;
   extensions->ARB_arrays_of_arrays = GL_TRUE;
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index 8a338c0e33c..6cfd8699a80 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -67,10 +67,6 @@ msgstr ""
 "Deshabilita les continuacions de línia basades en barra invertida en la font "
 "GLSL"
 
-#: t_options.h:100
-msgid "Disable GL_ARB_shader_bit_encoding"
-msgstr "Deshabilita el GL_ARB_shader_bit_encoding"
-
 #: t_options.h:105
 msgid ""
 "Force a default GLSL version for shaders that lack an explicit #version line"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index 9b7059ba8ad..90a35e70dcf 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -46,10 +46,6 @@ msgstr ""
 msgid "Disable backslash-based line continuations in GLSL source"
 msgstr ""
 
-#: t_options.h:100

[Mesa-dev] [Bug 100708] Trine 2 doesn't start on radeonsi on mesa 17

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=100708

Timothy Arceri  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |NOTOURBUG

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[Mesa-dev] [Bug 106590] Wrong line numbers expanded while compiling shaders

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106590

--- Comment #5 from Mark Janes  ---
This seems like a duplicate of 

 https://bugs.freedesktop.org/show_bug.cgi?id=106807

My faint recollection is that the specification of the __LINE__ macro is
inconsistent.  If, as Ken says, this has been removed from the specification,
why are we looking at patches to change the implementation?

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[Mesa-dev] [Bug 105859] mesa update gnome-terminal crashes on editing preferences

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=105859

Timothy Arceri  changed:

   What|Removed |Added

 Resolution|--- |WORKSFORME
 Status|NEW |RESOLVED

--- Comment #3 from Timothy Arceri  ---
No further info provided, and can't reproduce the issue so closing.

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[Mesa-dev] [Bug 99388] RHEL 7.3, Matlab 2016a Segmentation fault - glEnable

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99388

Timothy Arceri  changed:

   What|Removed |Added

  Component|Mesa core   |Drivers/OSMesa
 Status|NEW |NEEDINFO

--- Comment #1 from Timothy Arceri  ---
Is this still and issue with a more recent Mesa build?

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[Mesa-dev] [PATCH v3 1/7] nir: evaluate if condition uses inside the if branches

[Timothy Arceri]

Since we know what side of the branch we ended up on we can just
replace the use with a constant.

All the spill changes in shader-db are from Dolphin uber shaders,
despite some small regressions the change is clearly positive.

V2: insert new constant after any phis in the
use->parent_instr->type == nir_instr_type_phi path.

v3:
 - use nir_after_block_before_jump() for inserting const
 - check dominance of phi uses correctly

shader-db results IVB:

total instructions in shared programs: 201 -> 9993483 (-0.06%)
instructions in affected programs: 163235 -> 157517 (-3.50%)
helped: 132
HURT: 2

total cycles in shared programs: 231670754 -> 219476091 (-5.26%)
cycles in affected programs: 143424120 -> 131229457 (-8.50%)
helped: 115
HURT: 24

total spills in shared programs: 4383 -> 4370 (-0.30%)
spills in affected programs: 1656 -> 1643 (-0.79%)
helped: 9
HURT: 18

total fills in shared programs: 4610 -> 4581 (-0.63%)
fills in affected programs: 374 -> 345 (-7.75%)
helped: 6
HURT: 0
---
 src/compiler/nir/nir_opt_if.c | 135 ++
 1 file changed, 135 insertions(+)

diff --git a/src/compiler/nir/nir_opt_if.c b/src/compiler/nir/nir_opt_if.c
index dacf2d6c667..8c886041708 100644
--- a/src/compiler/nir/nir_opt_if.c
+++ b/src/compiler/nir/nir_opt_if.c
@@ -369,6 +369,98 @@ opt_if_loop_terminator(nir_if *nif)
return true;
 }
 
+static void
+replace_if_condition_use_with_const(nir_src *use, unsigned nir_boolean,
+void *mem_ctx, bool if_condition)
+{
+   /* Create const */
+   nir_load_const_instr *load = nir_load_const_instr_create(mem_ctx, 1, 32);
+   load->value.u32[0] = nir_boolean;
+
+   if (if_condition) {
+  nir_instr_insert_before_cf(>parent_if->cf_node,  >instr);
+   } else if (use->parent_instr->type == nir_instr_type_phi) {
+  nir_phi_instr *cond_phi = nir_instr_as_phi(use->parent_instr);
+
+  bool UNUSED found = false;
+  nir_foreach_phi_src(phi_src, cond_phi) {
+ if (phi_src->src.ssa == use->ssa) {
+nir_instr_insert(nir_after_block_before_jump(phi_src->pred),
+ >instr);
+found = true;
+break;
+ }
+  }
+  assert(found);
+   } else {
+  nir_instr_insert_before(use->parent_instr,  >instr);
+   }
+
+   /* Rewrite use to use const */
+   nir_src new_src = nir_src_for_ssa(>def);
+
+   if (if_condition)
+  nir_if_rewrite_condition(use->parent_if, new_src);
+   else
+  nir_instr_rewrite_src(use->parent_instr, use, new_src);
+}
+
+static bool
+evaluate_condition_use(nir_if *nif, nir_src *use_src, void *mem_ctx,
+   bool if_condition)
+{
+   bool progress = false;
+
+   nir_block *use_block = NULL;
+   if (if_condition) {
+  use_block =
+ nir_cf_node_as_block(nir_cf_node_prev(_src->parent_if->cf_node));
+   } else if (use_src->parent_instr->type == nir_instr_type_phi) {
+  nir_phi_instr *cond_phi = nir_instr_as_phi(use_src->parent_instr);
+
+  nir_foreach_phi_src(phi_src, cond_phi) {
+ if (phi_src->src.ssa == use_src->ssa) {
+use_block = phi_src->pred;
+break;
+ }
+  }
+  assert(use_block);
+   } else {
+  use_block = use_src->parent_instr->block;
+   }
+
+   if (nir_block_dominates(nir_if_first_then_block(nif), use_block)) {
+  replace_if_condition_use_with_const(use_src, NIR_TRUE, mem_ctx,
+  if_condition);
+  progress = true;
+   } else if (nir_block_dominates(nir_if_first_else_block(nif), use_block)) {
+  replace_if_condition_use_with_const(use_src, NIR_FALSE, mem_ctx,
+  if_condition);
+  progress = true;
+   }
+
+   return progress;
+}
+
+static bool
+opt_if_evaluate_condition_use(nir_if *nif, void *mem_ctx)
+{
+   bool progress = false;
+
+   /* Evaluate any uses of the if condition inside the if branches */
+   assert(nif->condition.is_ssa);
+   nir_foreach_use_safe(use_src, nif->condition.ssa) {
+  progress |= evaluate_condition_use(nif, use_src, mem_ctx, false);
+   }
+
+   nir_foreach_if_use_safe(use_src, nif->condition.ssa) {
+  if (use_src->parent_if != nif)
+ progress |= evaluate_condition_use(nif, use_src, mem_ctx, true);
+   }
+
+   return progress;
+}
+
 static bool
 opt_if_cf_list(nir_builder *b, struct exec_list *cf_list)
 {
@@ -402,6 +494,41 @@ opt_if_cf_list(nir_builder *b, struct exec_list *cf_list)
return progress;
 }
 
+/**
+ * These optimisations depend on nir_metadata_block_index and therefore must
+ * not do anything to cause the metadata to become invalid.
+ */
+static bool
+opt_if_safe_cf_list(nir_builder *b, struct exec_list *cf_list, void *mem_ctx)
+{
+   bool progress = false;
+   foreach_list_typed(nir_cf_node, cf_node, node, cf_list) {
+  switch (cf_node->type) {
+  case nir_cf_node_block:
+ break;
+
+  case nir_cf_node_if: {
+ nir_if *nif = 

[Mesa-dev] [PATCH v2 03/14] mesa: drop legacy no_rast dri option

[Timothy Arceri]

Add enviroment var overrides to legacy drivers instead.
---
 src/mesa/drivers/dri/i915/intel_context.c| 2 +-
 src/mesa/drivers/dri/i915/intel_screen.c | 1 -
 src/mesa/drivers/dri/i965/intel_screen.c | 1 -
 src/mesa/drivers/dri/r200/r200_context.c | 2 +-
 src/mesa/drivers/dri/radeon/radeon_context.c | 2 +-
 src/mesa/drivers/dri/radeon/radeon_screen.c  | 6 --
 src/util/xmlpool/ca.po   | 4 
 src/util/xmlpool/de.po   | 4 
 src/util/xmlpool/es.po   | 4 
 src/util/xmlpool/fr.po   | 4 
 src/util/xmlpool/nl.po   | 4 
 src/util/xmlpool/sv.po   | 4 
 src/util/xmlpool/t_options.h | 5 -
 13 files changed, 3 insertions(+), 40 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/intel_context.c 
b/src/mesa/drivers/dri/i915/intel_context.c
index 728d6d58699..abc16d47491 100644
--- a/src/mesa/drivers/dri/i915/intel_context.c
+++ b/src/mesa/drivers/dri/i915/intel_context.c
@@ -535,7 +535,7 @@ intelInitContext(struct intel_context *intel,
intel->prim.primitive = ~0;
 
/* Force all software fallbacks */
-   if (driQueryOptionb(>optionCache, "no_rast")) {
+   if (getenv("INTEL_NO_RAST")) {
   fprintf(stderr, "disabling 3D rasterization\n");
   intel->no_rast = 1;
}
diff --git a/src/mesa/drivers/dri/i915/intel_screen.c 
b/src/mesa/drivers/dri/i915/intel_screen.c
index 3d4f7ae94aa..50934c10c48 100644
--- a/src/mesa/drivers/dri/i915/intel_screen.c
+++ b/src/mesa/drivers/dri/i915/intel_screen.c
@@ -65,7 +65,6 @@ DRI_CONF_BEGIN
DRI_CONF_SECTION_QUALITY
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
-  DRI_CONF_NO_RAST("false")
   DRI_CONF_ALWAYS_FLUSH_BATCH("false")
   DRI_CONF_ALWAYS_FLUSH_CACHE("false")
   DRI_CONF_DISABLE_THROTTLING("false")
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index e57bbf4..923f9be3fbb 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -74,7 +74,6 @@ DRI_CONF_BEGIN
DRI_CONF_SECTION_END
 
DRI_CONF_SECTION_DEBUG
-  DRI_CONF_NO_RAST("false")
   DRI_CONF_ALWAYS_FLUSH_BATCH("false")
   DRI_CONF_ALWAYS_FLUSH_CACHE("false")
   DRI_CONF_DISABLE_THROTTLING("false")
diff --git a/src/mesa/drivers/dri/r200/r200_context.c 
b/src/mesa/drivers/dri/r200/r200_context.c
index cfdc9b84e87..392c10fb74d 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -383,7 +383,7 @@ GLboolean r200CreateContext( gl_api api,
   (getenv("R200_GART_CLIENT_TEXTURES") != 0);
 
tcl_mode = driQueryOptioni(>radeon.optionCache, "tcl_mode");
-   if (driQueryOptionb(>radeon.optionCache, "no_rast")) {
+   if (getenv("R200_NO_RAST")) {
   fprintf(stderr, "disabling 3D acceleration\n");
   FALLBACK(rmesa, R200_FALLBACK_DISABLE, 1);
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c 
b/src/mesa/drivers/dri/radeon/radeon_context.c
index e1e87640ef0..db1cc7274db 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -332,7 +332,7 @@ r100CreateContext( gl_api api,
rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
 
tcl_mode = driQueryOptioni(>radeon.optionCache, "tcl_mode");
-   if (driQueryOptionb(>radeon.optionCache, "no_rast")) {
+   if (getenv("RADEON_NO_RAST")) {
   fprintf(stderr, "disabling 3D acceleration\n");
   FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
} else if (tcl_mode == DRI_CONF_TCL_SW ||
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c 
b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 009d7953a24..5637361a916 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -95,9 +95,6 @@ DRI_CONF_BEGIN
 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
 DRI_CONF_SECTION_END
-DRI_CONF_SECTION_DEBUG
-DRI_CONF_NO_RAST("false")
-DRI_CONF_SECTION_END
 DRI_CONF_END
 };
 
@@ -128,9 +125,6 @@ DRI_CONF_BEGIN
 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
 DRI_CONF_SECTION_END
-DRI_CONF_SECTION_DEBUG
-DRI_CONF_NO_RAST("false")
-DRI_CONF_SECTION_END
 DRI_CONF_END
 };
 #endif
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index 55d83f903fb..8a338c0e33c 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -39,10 +39,6 @@ msgstr ""
 msgid "Debugging"
 msgstr "Depuració"
 
-#: t_options.h:60
-msgid "Disable 3D acceleration"
-msgstr "Deshabilita l'acceleració 3D"
-
 #: t_options.h:70
 msgid "Enable flushing batchbuffer after each draw call"
 msgstr "Habilita el buidatge del batchbuffer després de cada trucada de dibuix"
diff --git a/src/util/xmlpool/de.po 

[Mesa-dev] [PATCH v3 5/7] nir/opt_loop_unroll: Remove unneeded phis if we make progress

[Timothy Arceri]

Now that SSA values can be derefs and they have special rules, we have
to be a bit more careful about our LCSSA phis.  In particular, we need
to clean up in case LCSSA ended up creating a phi node for a deref.
This avoids validation issues with some CTS tests with the following
patch, but its possible this we could also see the same problem with
the existing unrolling passes.
---
 src/compiler/nir/nir_opt_loop_unroll.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/compiler/nir/nir_opt_loop_unroll.c 
b/src/compiler/nir/nir_opt_loop_unroll.c
index a1ad0e59814..e0e0b754716 100644
--- a/src/compiler/nir/nir_opt_loop_unroll.c
+++ b/src/compiler/nir/nir_opt_loop_unroll.c
@@ -575,9 +575,17 @@ nir_opt_loop_unroll_impl(nir_function_impl *impl,
 _nested_loop);
}
 
-   if (progress)
+   if (progress) {
   nir_lower_regs_to_ssa_impl(impl);
 
+  /* Calling nir_convert_loop_to_lcssa() adds extra phi nodes which may
+   * not be valid if they're used for something such as a deref.
+   *  Remove any unneeded phis.
+   */
+  nir_copy_prop(impl->function->shader);
+  nir_opt_remove_phis_impl(impl);
+   }
+
return progress;
 }
 
-- 
2.17.1

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[Mesa-dev] [PATCH v3 6/7] nir: add loop unroll support for wrapper loops

[Timothy Arceri]

This adds support for unrolling the classic

do {
// ...
} while (false)

that is used to wrap multi-line macros. GLSL IR also wraps switch
statements in a loop like this.

shader-db results IVB:

total loops in shared programs: 2515 -> 2512 (-0.12%)
loops in affected programs: 33 -> 30 (-9.09%)
helped: 3
HURT: 0
---
 src/compiler/nir/nir_opt_loop_unroll.c | 77 ++
 1 file changed, 77 insertions(+)

diff --git a/src/compiler/nir/nir_opt_loop_unroll.c 
b/src/compiler/nir/nir_opt_loop_unroll.c
index e0e0b754716..9c33267cb72 100644
--- a/src/compiler/nir/nir_opt_loop_unroll.c
+++ b/src/compiler/nir/nir_opt_loop_unroll.c
@@ -465,6 +465,65 @@ complex_unroll(nir_loop *loop, nir_loop_terminator 
*unlimit_term,
_mesa_hash_table_destroy(remap_table, NULL);
 }
 
+/* Unrolls the classic wrapper loops e.g
+ *
+ *do {
+ *// ...
+ *} while (false)
+ */
+static bool
+wrapper_unroll(nir_loop *loop)
+{
+   bool progress = false;
+
+   nir_block *blk_after_loop =
+  nir_cursor_current_block(nir_after_cf_node(>cf_node));
+
+   /* There may still be some single src phis following the loop that
+* have not yet been cleaned up by another pass. Tidy those up before
+* unrolling the loop.
+*/
+   nir_foreach_instr_safe(instr, blk_after_loop) {
+  if (instr->type != nir_instr_type_phi)
+ break;
+
+  nir_phi_instr *phi = nir_instr_as_phi(instr);
+  assert(exec_list_length(>srcs) == 1);
+
+  nir_phi_src *phi_src = exec_node_data(nir_phi_src,
+exec_list_get_head(>srcs),
+node);
+
+  nir_ssa_def_rewrite_uses(>dest.ssa, phi_src->src);
+  nir_instr_remove(instr);
+
+  progress = true;
+   }
+
+   nir_block *last_loop_blk = nir_loop_last_block(loop);
+   if (nir_block_ends_in_break(last_loop_blk)) {
+
+  /* Remove break at end of the loop */
+  nir_instr *break_instr = nir_block_last_instr(last_loop_blk);
+  nir_instr_remove(break_instr);
+
+  /* Pluck out the loop body. */
+  nir_cf_list loop_body;
+  nir_cf_extract(_body, nir_before_block(nir_loop_first_block(loop)),
+ nir_after_block(nir_loop_last_block(loop)));
+
+  /* Reinsert loop body after the loop */
+  nir_cf_reinsert(_body, nir_after_cf_node(>cf_node));
+
+  /* The loop has been unrolled so remove it. */
+  nir_cf_node_remove(>cf_node);
+
+  progress = true;
+   }
+
+   return progress;
+}
+
 static bool
 is_loop_small_enough_to_unroll(nir_shader *shader, nir_loop_info *li)
 {
@@ -516,6 +575,24 @@ process_loops(nir_shader *sh, nir_cf_node *cf_node, bool 
*has_nested_loop_out)
 */
if (!progress) {
 
+  /* Check for the classic
+   *
+   *do {
+   *// ...
+   *} while (false)
+   *
+   * that is used to wrap multi-line macros. GLSL IR also wraps switch
+   * statements in a loop like this.
+   */
+  if (loop->info->limiting_terminator == NULL &&
+  list_empty(>info->loop_terminator_list) &&
+  !loop->info->complex_loop) {
+
+ progress = wrapper_unroll(loop);
+
+ goto exit;
+  }
+
   if (has_nested_loop || loop->info->limiting_terminator == NULL)
  goto exit;
 
-- 
2.17.1

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[Mesa-dev] [Bug 107224] Incorrect Rendering in Deus Ex: Mankind Divided in-game menu

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107224

Timothy Arceri  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |NOTOURBUG

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[Mesa-dev] Vulkan specialization constants

[Michal Babej]

Hello,

Does any of the mesa driver's Vulkan implementations support
specialization constants as array sizes ? In particular, the constants
clspv generates for local variable array size.

Thanks,
  -- mb
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Re: [Mesa-dev] [PATCH 00/12] Compiler warning fixes, round 2

[Lionel Landwerlin]

Hi Kai,

Patches 6, 7, 10 & 11 are :

Reviewed-by: Lionel Landwerlin 

There are 2 existing series touching the same code, in patches 8, 9 & 
12, I think should land before the warnings are fixed.


Thanks,

-
Lionel

On 18/08/18 12:16, Kai Wasserbäch wrote:

Hey,
thanks to Bas and Timothy for reviewing and pushing most of my previous
warning fixes series ()!

I just continued down the build log and fixed the next eleven warnings.
These changes are, again, compile-tested in a clean chroot (pbuilder) on
amd64 and i386.

You can find the signed commits on the FDO GitLab at
.

Note: the first patch is a resend of patch four of the previous series,
as it hasn't been reviewed/accepted so far and I thought it would be
easier to keep only one series active.

Please review and, if you should accept these patches, please commit
them for me, as I do not have commit access for Mesa.

Cheers,
Kai


Kai Wasserbäch (12):
   amd/addrlib: mark returnCode as MAYBE_UNUSED in ElemGetExportNorm
   amd/addrlib: mark microBlockDim as MAYBE_UNUSED in
 Addr::V2::Gfx9Lib::HwlComputeBlock256Equation
   amd/addrlib: mark *pEqToCheck as MAYBE_UNUSED in
 Addr::V2::Gfx9Lib::ComputeStereoInfo
   amd/addrlib: mark numPipes as MAYBE_UNUSED in
 Addr::V1::EgBasedLib::SanityCheckMacroTiled
   amd/addrlib: mark physicalSliceSize as MAYBE_UNUSED in
 Addr::V1::EgBasedLib::HwlGetSizeAdjustmentMicroTiled
   intel/aubinator_error_decode: mark ret as MAYBE_UNUSED in main
   intel: aubinator: mark ftruncate_res as MAYBE_UNUSED in
 ensure_phys_mem
   intel: aubinator: mark *res as MAYBE_UNUSED in get_ggtt_batch_bo
   intel: aubinator: mark *res as MAYBE_UNUSED in get_ppgtt_batch_bo
   intel/tools: initialise bo_addr to 0 in main
   intel/decoder: mark total_length as MAYBE_UNUSED in gen_spec_load
   intel/decoder: mark result as MAYBE_UNUSED in gen_field_iterator_next

  src/amd/Makefile.addrlib.am  |  1 +
  src/amd/addrlib/addrinterface.cpp|  4 +++-
  src/amd/addrlib/gfx9/gfx9addrlib.cpp | 16 +---
  src/amd/addrlib/r800/egbaddrlib.cpp  |  8 +---
  src/intel/common/gen_decoder.c   |  5 +++--
  src/intel/tools/aubinator.c  | 12 +++-
  src/intel/tools/aubinator_error_decode.c |  2 +-
  src/intel/tools/error2aub.c  |  2 +-
  8 files changed, 30 insertions(+), 20 deletions(-)



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