Re: [Mesa-dev] [PATCH] radv: fix sample_mask_in loading. (v3)

2018-01-25 Thread Emil Velikov 
On 23 January 2018 at 23:00, Dave Airlie  wrote:
> From: Dave Airlie 
>
> This is ported from radeonsi and fixes:
> dEQP-VK.pipeline.multisample_shader_builtin.sample_mask.bit_*
>
> v2: don't call this path for radeonsi, it does it in the epilog.
> use the radeonsi code path.
> v3: handle NULL pCreateInfo->pMultisampleState properly (Samuel)
>
> Signed-off-by: Dave Airlie 
> ---
Hi Dave,

The patch seems to depend on the pipeline key introduction [49d035122ee] et al.
Can you please send a backport for 17.3 to mesa-stable - ideally with
--subject-prefix="BACKPORT 17.3".

Thanks
Emil
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Re: [Mesa-dev] [PATCH] radv: fix sample_mask_in loading. (v3)

2018-01-23 Thread Bas Nieuwenhuizen 
On Wed, Jan 24, 2018 at 12:00 AM, Dave Airlie  wrote:
> From: Dave Airlie 
>
> This is ported from radeonsi and fixes:
> dEQP-VK.pipeline.multisample_shader_builtin.sample_mask.bit_*
>
> v2: don't call this path for radeonsi, it does it in the epilog.
> use the radeonsi code path.
> v3: handle NULL pCreateInfo->pMultisampleState properly (Samuel)
>
> Signed-off-by: Dave Airlie 
> ---
>  src/amd/common/ac_nir_to_llvm.c | 29 -
>  src/amd/common/ac_nir_to_llvm.h |  2 ++
>  src/amd/vulkan/radv_pipeline.c  | 29 -
>  src/amd/vulkan/radv_private.h   |  2 ++
>  4 files changed, 56 insertions(+), 6 deletions(-)
>
> diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
> index cc3af77..8ae8650 100644
> --- a/src/amd/common/ac_nir_to_llvm.c
> +++ b/src/amd/common/ac_nir_to_llvm.c
> @@ -4049,6 +4049,30 @@ static LLVMValueRef load_sample_pos(struct 
> ac_nir_context *ctx)
> return ac_build_gather_values(>ac, values, 2);
>  }
>
> +static LLVMValueRef load_sample_mask_in(struct ac_nir_context *ctx)
> +{
> +   uint8_t log2_ps_iter_samples = 
> ctx->nctx->shader_info->info.ps.force_persample ? 
> ctx->nctx->options->key.fs.log2_num_samples : 
> ctx->nctx->options->key.fs.log2_ps_iter_samples;
> +
> +   /* The bit pattern matches that used by fixed function fragment
> +* processing. */
> +   static const uint16_t ps_iter_masks[] = {
> +   0x, /* not used */
> +   0x,
> +   0x,
> +   0x0101,
> +   0x0001,
> +   };
> +   assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
> +
> +   uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
> +
> +   LLVMValueRef result, sample_id;
> +   sample_id = unpack_param(>ac, ctx->abi->ancillary, 8, 4);
> +   sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 
> ps_iter_mask, false), sample_id, "");
> +   result = LLVMBuildAnd(ctx->ac.builder, sample_id, 
> ctx->abi->sample_coverage, "");
> +   return result;
> +}
> +
>  static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
>  const nir_intrinsic_instr *instr)
>  {
> @@ -4353,7 +4377,10 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
> result = load_sample_pos(ctx);
> break;
> case nir_intrinsic_load_sample_mask_in:
> -   result = ctx->abi->sample_coverage;
> +   if (ctx->nctx)
> +   result = load_sample_mask_in(ctx);
> +   else
> +   result = ctx->abi->sample_coverage;
> break;
> case nir_intrinsic_load_frag_coord: {
> LLVMValueRef values[4] = {
> diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
> index 62ea38b..1656289 100644
> --- a/src/amd/common/ac_nir_to_llvm.h
> +++ b/src/amd/common/ac_nir_to_llvm.h
> @@ -60,6 +60,8 @@ struct ac_tcs_variant_key {
>
>  struct ac_fs_variant_key {
> uint32_t col_format;
> +   uint8_t log2_ps_iter_samples;
> +   uint8_t log2_num_samples;
> uint32_t is_int8;
> uint32_t is_int10;
> uint32_t multisample : 1;
> diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
> index a49fe05..416b80f 100644
> --- a/src/amd/vulkan/radv_pipeline.c
> +++ b/src/amd/vulkan/radv_pipeline.c
> @@ -798,6 +798,18 @@ radv_pipeline_init_raster_state(struct radv_pipeline 
> *pipeline,
>
>  }
>
> +static uint8_t radv_pipeline_get_ps_iter_samples(const 
> VkPipelineMultisampleStateCreateInfo *vkms)
> +{
> +   uint32_t num_samples = vkms->rasterizationSamples;
> +   uint32_t ps_iter_samples = num_samples;

I think ps_iter_samples should default to 1 without
vkm->sampleShadingEnable. (It will be overridden anyway when forcing
per sample shading).

With that:

Reviewed-by: Bas Nieuwenhuizen 

> +
> +   if (vkms->sampleShadingEnable) {
> +   ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
> +   ps_iter_samples = util_next_power_of_two(ps_iter_samples);
> +   }
> +   return ps_iter_samples;
> +}
> +
>  static void
>  radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
>  const VkGraphicsPipelineCreateInfo 
> *pCreateInfo)
> @@ -813,9 +825,9 @@ radv_pipeline_init_multisample_state(struct radv_pipeline 
> *pipeline,
> else
> ms->num_samples = 1;
>
> -   if (vkms && vkms->sampleShadingEnable) {
> -   ps_iter_samples = ceil(vkms->minSampleShading * 
> ms->num_samples);
> -   } else if 
> (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
> +   if (vkms)
> +   ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
> +   if

[Mesa-dev] [PATCH] radv: fix sample_mask_in loading. (v3)

2018-01-23 Thread Dave Airlie 
From: Dave Airlie 

This is ported from radeonsi and fixes:
dEQP-VK.pipeline.multisample_shader_builtin.sample_mask.bit_*

v2: don't call this path for radeonsi, it does it in the epilog.
use the radeonsi code path.
v3: handle NULL pCreateInfo->pMultisampleState properly (Samuel)

Signed-off-by: Dave Airlie 
---
 src/amd/common/ac_nir_to_llvm.c | 29 -
 src/amd/common/ac_nir_to_llvm.h |  2 ++
 src/amd/vulkan/radv_pipeline.c  | 29 -
 src/amd/vulkan/radv_private.h   |  2 ++
 4 files changed, 56 insertions(+), 6 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index cc3af77..8ae8650 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4049,6 +4049,30 @@ static LLVMValueRef load_sample_pos(struct 
ac_nir_context *ctx)
return ac_build_gather_values(>ac, values, 2);
 }
 
+static LLVMValueRef load_sample_mask_in(struct ac_nir_context *ctx)
+{
+   uint8_t log2_ps_iter_samples = 
ctx->nctx->shader_info->info.ps.force_persample ? 
ctx->nctx->options->key.fs.log2_num_samples : 
ctx->nctx->options->key.fs.log2_ps_iter_samples;
+
+   /* The bit pattern matches that used by fixed function fragment
+* processing. */
+   static const uint16_t ps_iter_masks[] = {
+   0x, /* not used */
+   0x,
+   0x,
+   0x0101,
+   0x0001,
+   };
+   assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
+
+   uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
+
+   LLVMValueRef result, sample_id;
+   sample_id = unpack_param(>ac, ctx->abi->ancillary, 8, 4);
+   sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 
ps_iter_mask, false), sample_id, "");
+   result = LLVMBuildAnd(ctx->ac.builder, sample_id, 
ctx->abi->sample_coverage, "");
+   return result;
+}
+
 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
 const nir_intrinsic_instr *instr)
 {
@@ -4353,7 +4377,10 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
result = load_sample_pos(ctx);
break;
case nir_intrinsic_load_sample_mask_in:
-   result = ctx->abi->sample_coverage;
+   if (ctx->nctx)
+   result = load_sample_mask_in(ctx);
+   else
+   result = ctx->abi->sample_coverage;
break;
case nir_intrinsic_load_frag_coord: {
LLVMValueRef values[4] = {
diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index 62ea38b..1656289 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -60,6 +60,8 @@ struct ac_tcs_variant_key {
 
 struct ac_fs_variant_key {
uint32_t col_format;
+   uint8_t log2_ps_iter_samples;
+   uint8_t log2_num_samples;
uint32_t is_int8;
uint32_t is_int10;
uint32_t multisample : 1;
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index a49fe05..416b80f 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -798,6 +798,18 @@ radv_pipeline_init_raster_state(struct radv_pipeline 
*pipeline,
 
 }
 
+static uint8_t radv_pipeline_get_ps_iter_samples(const 
VkPipelineMultisampleStateCreateInfo *vkms)
+{
+   uint32_t num_samples = vkms->rasterizationSamples;
+   uint32_t ps_iter_samples = num_samples;
+
+   if (vkms->sampleShadingEnable) {
+   ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
+   ps_iter_samples = util_next_power_of_two(ps_iter_samples);
+   }
+   return ps_iter_samples;
+}
+
 static void
 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
 const VkGraphicsPipelineCreateInfo 
*pCreateInfo)
@@ -813,9 +825,9 @@ radv_pipeline_init_multisample_state(struct radv_pipeline 
*pipeline,
else
ms->num_samples = 1;
 
-   if (vkms && vkms->sampleShadingEnable) {
-   ps_iter_samples = ceil(vkms->minSampleShading * 
ms->num_samples);
-   } else if 
(pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
+   if (vkms)
+   ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
+   if (vkms && !vkms->sampleShadingEnable && 
pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
ps_iter_samples = ms->num_samples;
}
 
@@ -838,7 +850,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline 
*pipeline,
 
if (ms->num_samples > 1) {
unsigned log_samples = util_logbase2(ms->num_samples);
-   unsigned log_ps_iter_samples = 
util_logbase2(util_next_power_of_two(ps_iter_samples));
+   unsigned

Re: [Mesa-dev] [PATCH] radv: fix sample_mask_in loading. (v2)

2018-01-23 Thread Samuel Pitoiset 



On 01/23/2018 04:00 AM, Dave Airlie wrote:

From: Dave Airlie 

This is ported from radeonsi and fixes:
dEQP-VK.pipeline.multisample_shader_builtin.sample_mask.bit_*

v2: don't call this path for radeonsi, it does it in the epilog.
use the radeonsi code path.

Signed-off-by: Dave Airlie 
---
  src/amd/common/ac_nir_to_llvm.c | 29 -
  src/amd/common/ac_nir_to_llvm.h |  2 ++
  src/amd/vulkan/radv_pipeline.c  | 28 +++-
  src/amd/vulkan/radv_private.h   |  2 ++
  4 files changed, 55 insertions(+), 6 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 214fb14..668cd50 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4046,6 +4046,30 @@ static LLVMValueRef load_sample_pos(struct 
ac_nir_context *ctx)
return ac_build_gather_values(>ac, values, 2);
  }
  
+static LLVMValueRef load_sample_mask_in(struct ac_nir_context *ctx)

+{
+   uint8_t log2_ps_iter_samples = ctx->nctx->shader_info->info.ps.force_persample ? 
ctx->nctx->options->key.fs.log2_num_samples : 
ctx->nctx->options->key.fs.log2_ps_iter_samples;
+
+   /* The bit pattern matches that used by fixed function fragment
+* processing. */
+   static const uint16_t ps_iter_masks[] = {
+   0x, /* not used */
+   0x,
+   0x,
+   0x0101,
+   0x0001,
+   };
+   assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
+
+   uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
+
+   LLVMValueRef result, sample_id;
+   sample_id = unpack_param(>ac, ctx->abi->ancillary, 8, 4);
+   sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, 
false), sample_id, "");
+   result = LLVMBuildAnd(ctx->ac.builder, sample_id, ctx->abi->sample_coverage, 
"");
+   return result;
+}
+
  static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
 const nir_intrinsic_instr *instr)
  {
@@ -4350,7 +4374,10 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
result = load_sample_pos(ctx);
break;
case nir_intrinsic_load_sample_mask_in:
-   result = ctx->abi->sample_coverage;
+   if (ctx->nctx)
+   result = load_sample_mask_in(ctx);
+   else
+   result = ctx->abi->sample_coverage;
break;
case nir_intrinsic_load_frag_coord: {
LLVMValueRef values[4] = {
diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index 62ea38b..1656289 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -60,6 +60,8 @@ struct ac_tcs_variant_key {
  
  struct ac_fs_variant_key {

uint32_t col_format;
+   uint8_t log2_ps_iter_samples;
+   uint8_t log2_num_samples;
uint32_t is_int8;
uint32_t is_int10;
uint32_t multisample : 1;
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index f29c88e..98d1eca 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -798,6 +798,18 @@ radv_pipeline_init_raster_state(struct radv_pipeline 
*pipeline,
  
  }
  
+static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)

+{
+   uint32_t num_samples = 
pCreateInfo->pMultisampleState->rasterizationSamples;


I guess pMultisampleState might be NULL, no?


+   uint32_t ps_iter_samples = num_samples;
+
+   if (pCreateInfo->pMultisampleState->sampleShadingEnable) {
+   ps_iter_samples = 
ceil(pCreateInfo->pMultisampleState->minSampleShading * num_samples);
+   ps_iter_samples = util_next_power_of_two(ps_iter_samples);
+   }
+   return ps_iter_samples;
+}
+
  static void
  radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
 const VkGraphicsPipelineCreateInfo 
*pCreateInfo)
@@ -813,9 +825,8 @@ radv_pipeline_init_multisample_state(struct radv_pipeline 
*pipeline,
else
ms->num_samples = 1;
  
-	if (vkms && vkms->sampleShadingEnable) {

-   ps_iter_samples = ceil(vkms->minSampleShading * 
ms->num_samples);
-   } else if 
(pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
+   ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
+   if (vkms && !vkms->sampleShadingEnable && 
pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
ps_iter_samples = ms->num_samples;
}
  
@@ -838,7 +849,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
  
  	if (ms->num_samples > 1) {

unsigned log_samples = util_logbase2(ms->num_samples);
-   unsigned log_ps_iter_samples =

[Mesa-dev] [PATCH] radv: fix sample_mask_in loading. (v2)

2018-01-22 Thread Dave Airlie 
From: Dave Airlie 

This is ported from radeonsi and fixes:
dEQP-VK.pipeline.multisample_shader_builtin.sample_mask.bit_*

v2: don't call this path for radeonsi, it does it in the epilog.
use the radeonsi code path.

Signed-off-by: Dave Airlie 
---
 src/amd/common/ac_nir_to_llvm.c | 29 -
 src/amd/common/ac_nir_to_llvm.h |  2 ++
 src/amd/vulkan/radv_pipeline.c  | 28 +++-
 src/amd/vulkan/radv_private.h   |  2 ++
 4 files changed, 55 insertions(+), 6 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 214fb14..668cd50 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4046,6 +4046,30 @@ static LLVMValueRef load_sample_pos(struct 
ac_nir_context *ctx)
return ac_build_gather_values(>ac, values, 2);
 }
 
+static LLVMValueRef load_sample_mask_in(struct ac_nir_context *ctx)
+{
+   uint8_t log2_ps_iter_samples = 
ctx->nctx->shader_info->info.ps.force_persample ? 
ctx->nctx->options->key.fs.log2_num_samples : 
ctx->nctx->options->key.fs.log2_ps_iter_samples;
+
+   /* The bit pattern matches that used by fixed function fragment
+* processing. */
+   static const uint16_t ps_iter_masks[] = {
+   0x, /* not used */
+   0x,
+   0x,
+   0x0101,
+   0x0001,
+   };
+   assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
+
+   uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
+
+   LLVMValueRef result, sample_id;
+   sample_id = unpack_param(>ac, ctx->abi->ancillary, 8, 4);
+   sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 
ps_iter_mask, false), sample_id, "");
+   result = LLVMBuildAnd(ctx->ac.builder, sample_id, 
ctx->abi->sample_coverage, "");
+   return result;
+}
+
 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
 const nir_intrinsic_instr *instr)
 {
@@ -4350,7 +4374,10 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
result = load_sample_pos(ctx);
break;
case nir_intrinsic_load_sample_mask_in:
-   result = ctx->abi->sample_coverage;
+   if (ctx->nctx)
+   result = load_sample_mask_in(ctx);
+   else
+   result = ctx->abi->sample_coverage;
break;
case nir_intrinsic_load_frag_coord: {
LLVMValueRef values[4] = {
diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index 62ea38b..1656289 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -60,6 +60,8 @@ struct ac_tcs_variant_key {
 
 struct ac_fs_variant_key {
uint32_t col_format;
+   uint8_t log2_ps_iter_samples;
+   uint8_t log2_num_samples;
uint32_t is_int8;
uint32_t is_int10;
uint32_t multisample : 1;
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index f29c88e..98d1eca 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -798,6 +798,18 @@ radv_pipeline_init_raster_state(struct radv_pipeline 
*pipeline,
 
 }
 
+static uint8_t radv_pipeline_get_ps_iter_samples(const 
VkGraphicsPipelineCreateInfo *pCreateInfo)
+{
+   uint32_t num_samples = 
pCreateInfo->pMultisampleState->rasterizationSamples;
+   uint32_t ps_iter_samples = num_samples;
+
+   if (pCreateInfo->pMultisampleState->sampleShadingEnable) {
+   ps_iter_samples = 
ceil(pCreateInfo->pMultisampleState->minSampleShading * num_samples);
+   ps_iter_samples = util_next_power_of_two(ps_iter_samples);
+   }
+   return ps_iter_samples;
+}
+
 static void
 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
 const VkGraphicsPipelineCreateInfo 
*pCreateInfo)
@@ -813,9 +825,8 @@ radv_pipeline_init_multisample_state(struct radv_pipeline 
*pipeline,
else
ms->num_samples = 1;
 
-   if (vkms && vkms->sampleShadingEnable) {
-   ps_iter_samples = ceil(vkms->minSampleShading * 
ms->num_samples);
-   } else if 
(pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
+   ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
+   if (vkms && !vkms->sampleShadingEnable && 
pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
ps_iter_samples = ms->num_samples;
}
 
@@ -838,7 +849,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline 
*pipeline,
 
if (ms->num_samples > 1) {
unsigned log_samples = util_logbase2(ms->num_samples);
-   unsigned log_ps_iter_samples = 
util_logbase2(util_next_power_of_two(ps_iter_samples));
+   unsigned log_ps_iter_samples =

Re: [Mesa-dev] [PATCH] radv: fix sample_mask_in loading.

2018-01-22 Thread Timothy Arceri 

This breaks some piglit tests on radeonsi e.g.

R600_DEBUG=nir ./bin/arb_sample_shading-samplemask 2 all all -auto -fbo

On 23/01/18 12:08, Dave Airlie wrote:

From: Dave Airlie 

This is ported from amdvlk, and fixes:
dEQP-VK.pipeline.multisample_shader_builtin.sample_mask.bit_*

Signed-off-by: Dave Airlie 
---
  src/amd/common/ac_nir_to_llvm.c | 12 +++-
  1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 214fb14..876c7ce 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4046,6 +4046,16 @@ static LLVMValueRef load_sample_pos(struct 
ac_nir_context *ctx)
return ac_build_gather_values(>ac, values, 2);
  }
  
+static LLVMValueRef load_sample_mask_in(struct ac_nir_context *ctx)

+{
+   LLVMValueRef result, sample_id;
+   sample_id = unpack_param(>ac, ctx->abi->ancillary, 8, 4);
+
+   sample_id = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1, sample_id, "");
+   result = LLVMBuildAnd(ctx->ac.builder, sample_id, ctx->abi->sample_coverage, 
"");
+   return result;
+}
+
  static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
 const nir_intrinsic_instr *instr)
  {
@@ -4350,7 +4360,7 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
result = load_sample_pos(ctx);
break;
case nir_intrinsic_load_sample_mask_in:
-   result = ctx->abi->sample_coverage;
+   result = load_sample_mask_in(ctx);
break;
case nir_intrinsic_load_frag_coord: {
LLVMValueRef values[4] = {


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[Mesa-dev] [PATCH] radv: fix sample_mask_in loading.

2018-01-22 Thread Dave Airlie 
From: Dave Airlie 

This is ported from amdvlk, and fixes:
dEQP-VK.pipeline.multisample_shader_builtin.sample_mask.bit_*

Signed-off-by: Dave Airlie 
---
 src/amd/common/ac_nir_to_llvm.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 214fb14..876c7ce 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4046,6 +4046,16 @@ static LLVMValueRef load_sample_pos(struct 
ac_nir_context *ctx)
return ac_build_gather_values(>ac, values, 2);
 }
 
+static LLVMValueRef load_sample_mask_in(struct ac_nir_context *ctx)
+{
+   LLVMValueRef result, sample_id;
+   sample_id = unpack_param(>ac, ctx->abi->ancillary, 8, 4);
+
+   sample_id = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1, sample_id, "");
+   result = LLVMBuildAnd(ctx->ac.builder, sample_id, 
ctx->abi->sample_coverage, "");
+   return result;
+}
+
 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
 const nir_intrinsic_instr *instr)
 {
@@ -4350,7 +4360,7 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
result = load_sample_pos(ctx);
break;
case nir_intrinsic_load_sample_mask_in:
-   result = ctx->abi->sample_coverage;
+   result = load_sample_mask_in(ctx);
break;
case nir_intrinsic_load_frag_coord: {
LLVMValueRef values[4] = {
-- 
2.9.5

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