Re: [Mesa-dev] [PATCH 1/4] gallium/ttn: add support for texture offsets
Rob Clark writes: > On Tue, Apr 14, 2015 at 1:04 PM, Eric Anholt wrote: >> Rob Clark writes: >> >>> From: Rob Clark >>> >>> Signed-off-by: Rob Clark >> >> 1-3 (with the fix to 1 that you posted in irc) are: >> >> Reviewed-by: Eric Anholt >> >> I don't like the mismatch on bytes vs vec4s in the load_ubo_indirect >> arguments for patch 4, and will be interested in seeing the version you >> were working on to fix that. > > so, if I pull out the addressing-modes patch, then for the ubo patch > we are back to 'index *= 16' vec4->byte conversion. Which is funny > looking, but at the moment my best definition of "correct" is "what > glsl_to_nir and intel driver do", and by that definition, this is the > correct thing to do. OK. But we should be doing the SHL here, too (also gets us consistency with glsl_to_nir). signature.asc Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/4] gallium/ttn: add support for texture offsets
On Tue, Apr 14, 2015 at 1:04 PM, Eric Anholt wrote: > Rob Clark writes: > >> From: Rob Clark >> >> Signed-off-by: Rob Clark > > 1-3 (with the fix to 1 that you posted in irc) are: > > Reviewed-by: Eric Anholt > > I don't like the mismatch on bytes vs vec4s in the load_ubo_indirect > arguments for patch 4, and will be interested in seeing the version you > were working on to fix that. so, if I pull out the addressing-modes patch, then for the ubo patch we are back to 'index *= 16' vec4->byte conversion. Which is funny looking, but at the moment my best definition of "correct" is "what glsl_to_nir and intel driver do", and by that definition, this is the correct thing to do. BR, -R ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/4] gallium/ttn: add support for texture offsets
Rob Clark writes: > From: Rob Clark > > Signed-off-by: Rob Clark 1-3 (with the fix to 1 that you posted in irc) are: Reviewed-by: Eric Anholt I don't like the mismatch on bytes vs vec4s in the load_ubo_indirect arguments for patch 4, and will be interested in seeing the version you were working on to fix that. signature.asc Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/4] gallium/ttn: add support for texture offsets
On Mon, Apr 13, 2015 at 1:34 PM, Eric Anholt wrote:
> Rob Clark writes:
>
>> From: Rob Clark
>>
>> Signed-off-by: Rob Clark
>> ---
>> src/gallium/auxiliary/nir/tgsi_to_nir.c | 30 +-
>> 1 file changed, 29 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c
>> b/src/gallium/auxiliary/nir/tgsi_to_nir.c
>> index 9d988b06..c9f9e03 100644
>> --- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
>> +++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
>> @@ -982,7 +982,7 @@ ttn_tex(struct ttn_compile *c, nir_alu_dest dest,
>> nir_ssa_def **src)
>> struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
>> nir_tex_instr *instr;
>> nir_texop op;
>> - unsigned num_srcs, samp = 1;
>> + unsigned num_srcs, samp = 1, i;
>>
>> switch (tgsi_inst->Instruction.Opcode) {
>> case TGSI_OPCODE_TEX:
>> @@ -1026,6 +1026,8 @@ ttn_tex(struct ttn_compile *c, nir_alu_dest dest,
>> nir_ssa_def **src)
>>num_srcs++;
>> }
>>
>> + num_srcs += tgsi_inst->Texture.NumOffsets;
>> +
>> instr = nir_tex_instr_create(b->shader, num_srcs);
>> instr->op = op;
>>
>> @@ -1103,6 +1105,32 @@ ttn_tex(struct ttn_compile *c, nir_alu_dest dest,
>> nir_ssa_def **src)
>>src_number++;
>> }
>>
>> + for (i = 0; i < tgsi_inst->Texture.NumOffsets; i++) {
>> + struct tgsi_texture_offset *tex_offset = &tgsi_inst->TexOffsets[i];
>> + /* since TexOffset ins't using tgsi_full_src_register we get to
>> + * do some extra gymnastics:
>> + */
>> + nir_alu_src src;
>> +
>> + memset(&src, 0, sizeof(src));
>> +
>> + src.src = ttn_src_for_file_and_index(c,
>> + tex_offset->File,
>> + tex_offset->Index,
>> + NULL);
>> +
>> + src.swizzle[0] = tex_offset->SwizzleX;
>> + src.swizzle[1] = tex_offset->SwizzleY;
>> + src.swizzle[2] = tex_offset->SwizzleZ;
>> + src.swizzle[3] = TGSI_SWIZZLE_W;
>> +
>> + nir_ssa_def *off = nir_fmov_alu(b, src, instr->coord_components);
>
> For a cubemap array, won't coord_components be 4, but you only want a
> 3-component value as the offset? I'm suspicious of this fixed SWIZZLE_W
> here. If you move the .src_type setting above this, you could use
> nir_tex_instr_src_size(instr, src_number) to get the right number of
> components.
hmm, yeah I suppose offsets don't apply to array index..
BR,
-R
>
>> +
>> + instr->src[src_number].src = nir_src_for_ssa(off);
>> + instr->src[src_number].src_type = nir_tex_src_offset;
>> + src_number++;
>> + }
>> +
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Re: [Mesa-dev] [PATCH 1/4] gallium/ttn: add support for texture offsets
On Mon, Apr 13, 2015 at 1:34 PM, Eric Anholt wrote:
> Rob Clark writes:
>
>> From: Rob Clark
>>
>> Signed-off-by: Rob Clark
>> ---
>> src/gallium/auxiliary/nir/tgsi_to_nir.c | 30 +-
>> 1 file changed, 29 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c
>> b/src/gallium/auxiliary/nir/tgsi_to_nir.c
>> index 9d988b06..c9f9e03 100644
>> --- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
>> +++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
>> @@ -982,7 +982,7 @@ ttn_tex(struct ttn_compile *c, nir_alu_dest dest,
>> nir_ssa_def **src)
>> struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
>> nir_tex_instr *instr;
>> nir_texop op;
>> - unsigned num_srcs, samp = 1;
>> + unsigned num_srcs, samp = 1, i;
>>
>> switch (tgsi_inst->Instruction.Opcode) {
>> case TGSI_OPCODE_TEX:
>> @@ -1026,6 +1026,8 @@ ttn_tex(struct ttn_compile *c, nir_alu_dest dest,
>> nir_ssa_def **src)
>>num_srcs++;
>> }
>>
>> + num_srcs += tgsi_inst->Texture.NumOffsets;
>> +
>> instr = nir_tex_instr_create(b->shader, num_srcs);
>> instr->op = op;
>>
>> @@ -1103,6 +1105,32 @@ ttn_tex(struct ttn_compile *c, nir_alu_dest dest,
>> nir_ssa_def **src)
>>src_number++;
>> }
>>
>> + for (i = 0; i < tgsi_inst->Texture.NumOffsets; i++) {
>> + struct tgsi_texture_offset *tex_offset = &tgsi_inst->TexOffsets[i];
>> + /* since TexOffset ins't using tgsi_full_src_register we get to
>> + * do some extra gymnastics:
>> + */
>> + nir_alu_src src;
>> +
>> + memset(&src, 0, sizeof(src));
>> +
>> + src.src = ttn_src_for_file_and_index(c,
>> + tex_offset->File,
>> + tex_offset->Index,
>> + NULL);
>> +
>> + src.swizzle[0] = tex_offset->SwizzleX;
>> + src.swizzle[1] = tex_offset->SwizzleY;
>> + src.swizzle[2] = tex_offset->SwizzleZ;
>> + src.swizzle[3] = TGSI_SWIZZLE_W;
>> +
>> + nir_ssa_def *off = nir_fmov_alu(b, src, instr->coord_components);
>
> For a cubemap array, won't coord_components be 4, but you only want a
> 3-component value as the offset? I'm suspicious of this fixed SWIZZLE_W
> here. If you move the .src_type setting above this, you could use
> nir_tex_instr_src_size(instr, src_number) to get the right number of
> components.
When are offsets on cubemaps supported? The real question is what will
coord_components be for a 2darray -- if it's 2, then this is fine, if
it's 3, then it needs fixing.
-ilia
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Re: [Mesa-dev] [PATCH 1/4] gallium/ttn: add support for texture offsets
Rob Clark writes:
> From: Rob Clark
>
> Signed-off-by: Rob Clark
> ---
> src/gallium/auxiliary/nir/tgsi_to_nir.c | 30 +-
> 1 file changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c
> b/src/gallium/auxiliary/nir/tgsi_to_nir.c
> index 9d988b06..c9f9e03 100644
> --- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
> +++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
> @@ -982,7 +982,7 @@ ttn_tex(struct ttn_compile *c, nir_alu_dest dest,
> nir_ssa_def **src)
> struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
> nir_tex_instr *instr;
> nir_texop op;
> - unsigned num_srcs, samp = 1;
> + unsigned num_srcs, samp = 1, i;
>
> switch (tgsi_inst->Instruction.Opcode) {
> case TGSI_OPCODE_TEX:
> @@ -1026,6 +1026,8 @@ ttn_tex(struct ttn_compile *c, nir_alu_dest dest,
> nir_ssa_def **src)
>num_srcs++;
> }
>
> + num_srcs += tgsi_inst->Texture.NumOffsets;
> +
> instr = nir_tex_instr_create(b->shader, num_srcs);
> instr->op = op;
>
> @@ -1103,6 +1105,32 @@ ttn_tex(struct ttn_compile *c, nir_alu_dest dest,
> nir_ssa_def **src)
>src_number++;
> }
>
> + for (i = 0; i < tgsi_inst->Texture.NumOffsets; i++) {
> + struct tgsi_texture_offset *tex_offset = &tgsi_inst->TexOffsets[i];
> + /* since TexOffset ins't using tgsi_full_src_register we get to
> + * do some extra gymnastics:
> + */
> + nir_alu_src src;
> +
> + memset(&src, 0, sizeof(src));
> +
> + src.src = ttn_src_for_file_and_index(c,
> + tex_offset->File,
> + tex_offset->Index,
> + NULL);
> +
> + src.swizzle[0] = tex_offset->SwizzleX;
> + src.swizzle[1] = tex_offset->SwizzleY;
> + src.swizzle[2] = tex_offset->SwizzleZ;
> + src.swizzle[3] = TGSI_SWIZZLE_W;
> +
> + nir_ssa_def *off = nir_fmov_alu(b, src, instr->coord_components);
For a cubemap array, won't coord_components be 4, but you only want a
3-component value as the offset? I'm suspicious of this fixed SWIZZLE_W
here. If you move the .src_type setting above this, you could use
nir_tex_instr_src_size(instr, src_number) to get the right number of
components.
> +
> + instr->src[src_number].src = nir_src_for_ssa(off);
> + instr->src[src_number].src_type = nir_tex_src_offset;
> + src_number++;
> + }
> +
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[Mesa-dev] [PATCH 1/4] gallium/ttn: add support for texture offsets
From: Rob Clark
Signed-off-by: Rob Clark
---
src/gallium/auxiliary/nir/tgsi_to_nir.c | 30 +-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c
b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index 9d988b06..c9f9e03 100644
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -982,7 +982,7 @@ ttn_tex(struct ttn_compile *c, nir_alu_dest dest,
nir_ssa_def **src)
struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
nir_tex_instr *instr;
nir_texop op;
- unsigned num_srcs, samp = 1;
+ unsigned num_srcs, samp = 1, i;
switch (tgsi_inst->Instruction.Opcode) {
case TGSI_OPCODE_TEX:
@@ -1026,6 +1026,8 @@ ttn_tex(struct ttn_compile *c, nir_alu_dest dest,
nir_ssa_def **src)
num_srcs++;
}
+ num_srcs += tgsi_inst->Texture.NumOffsets;
+
instr = nir_tex_instr_create(b->shader, num_srcs);
instr->op = op;
@@ -1103,6 +1105,32 @@ ttn_tex(struct ttn_compile *c, nir_alu_dest dest,
nir_ssa_def **src)
src_number++;
}
+ for (i = 0; i < tgsi_inst->Texture.NumOffsets; i++) {
+ struct tgsi_texture_offset *tex_offset = &tgsi_inst->TexOffsets[i];
+ /* since TexOffset ins't using tgsi_full_src_register we get to
+ * do some extra gymnastics:
+ */
+ nir_alu_src src;
+
+ memset(&src, 0, sizeof(src));
+
+ src.src = ttn_src_for_file_and_index(c,
+ tex_offset->File,
+ tex_offset->Index,
+ NULL);
+
+ src.swizzle[0] = tex_offset->SwizzleX;
+ src.swizzle[1] = tex_offset->SwizzleY;
+ src.swizzle[2] = tex_offset->SwizzleZ;
+ src.swizzle[3] = TGSI_SWIZZLE_W;
+
+ nir_ssa_def *off = nir_fmov_alu(b, src, instr->coord_components);
+
+ instr->src[src_number].src = nir_src_for_ssa(off);
+ instr->src[src_number].src_type = nir_tex_src_offset;
+ src_number++;
+ }
+
assert(src_number == num_srcs);
nir_ssa_dest_init(&instr->instr, &instr->dest, 4, NULL);
--
2.1.0
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