Re: [Mesa-dev] [PATCH] glsl: Add an optimization pass to flatten simple nested if blocks.
On Wed, Apr 3, 2013 at 11:56 PM, Kenneth Graunke kenn...@whitecape.orgwrote:
GLBenchmark 2.7's shaders contain conditional blocks like:
if (x) {
if (y) {
...
}
}
where the outer conditional's then clause contains exactly one statement
(the nested if) and there are no else clauses. This can easily be
optimized into:
if (x y) {
...
}
This saves a few instructions in GLBenchmark 2.7:
total instructions in shared programs: 11833 - 11649 (-1.55%)
instructions in affected programs: 8234 - 8050 (-2.23%)
It also helps CS:GO slightly (-0.05%/-0.22%). More importantly,
however, it simplifies the control flow graph, which could enable other
optimizations.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Matt Turner matts...@gmail.com
Any measurable performance improvement?
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Re: [Mesa-dev] [PATCH 2/2] i965/vs: Use GRFs for pull constant offsets on gen7.
Reviewed-by: Matt Turner matts...@gmail.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] remove mfeatures.h, take two
Ready to commit? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] mesa: Update comments to match newer specs.
Old GL 1.x specs used 'b' but newer specs use 'p'. The line immediately
above the second hunk also uses 'p'.
---
src/mesa/main/mtypes.h |2 +-
src/mesa/main/texobj.c |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 008f68b..3d8f359 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -1171,7 +1171,7 @@ struct gl_texture_object
GLint MaxLevel; /** max mipmap level, OpenGL 1.2 */
GLint ImmutableLevels; /** ES 3.0 / ARB_texture_view */
GLint _MaxLevel;/** actual max mipmap level (q in the spec) */
- GLfloat _MaxLambda; /** = _MaxLevel - BaseLevel (q - b in spec) */
+ GLfloat _MaxLambda; /** = _MaxLevel - BaseLevel (q - p in spec) */
GLint CropRect[4]; /** GL_OES_draw_texture */
GLenum Swizzle[4]; /** GL_EXT_texture_swizzle */
GLuint _Swizzle; /** same as Swizzle, but SWIZZLE_* format */
diff --git a/src/mesa/main/texobj.c b/src/mesa/main/texobj.c
index 66377c8..d0fcb12 100644
--- a/src/mesa/main/texobj.c
+++ b/src/mesa/main/texobj.c
@@ -553,7 +553,7 @@ _mesa_test_texobj_completeness( const struct gl_context
*ctx,
t-_MaxLevel = MIN2(t-_MaxLevel, t-MaxLevel);
t-_MaxLevel = MIN2(t-_MaxLevel, maxLevels - 1); /* 'q' in the GL spec */
- /* Compute _MaxLambda = q - b (see the 1.2 spec) used during mipmapping */
+ /* Compute _MaxLambda = q - p in the spec used during mipmapping */
t-_MaxLambda = (GLfloat) (t-_MaxLevel - baseLevel);
if (t-Immutable) {
--
1.7.8.6
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[Mesa-dev] [PATCH 2/2] mesa: Use MIN3 instead of two MIN2s.
--- src/mesa/main/texobj.c |9 + 1 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/mesa/main/texobj.c b/src/mesa/main/texobj.c index d0fcb12..28b8130 100644 --- a/src/mesa/main/texobj.c +++ b/src/mesa/main/texobj.c @@ -548,10 +548,11 @@ _mesa_test_texobj_completeness( const struct gl_context *ctx, ASSERT(maxLevels 0); - t-_MaxLevel = - baseLevel + baseImage-MaxNumLevels - 1; /* 'p' in the GL spec */ - t-_MaxLevel = MIN2(t-_MaxLevel, t-MaxLevel); - t-_MaxLevel = MIN2(t-_MaxLevel, maxLevels - 1); /* 'q' in the GL spec */ + t-_MaxLevel = MIN3(t-MaxLevel, + /* 'p' in the GL spec */ + baseLevel + baseImage-MaxNumLevels - 1, + /* 'q' in the GL spec */ + maxLevels - 1); /* Compute _MaxLambda = q - p in the spec used during mipmapping */ t-_MaxLambda = (GLfloat) (t-_MaxLevel - baseLevel); -- 1.7.8.6 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 3/3] i965: Prefer Y-tiling on Gen6+.
On Mon, Apr 8, 2013 at 7:27 PM, Kenneth Graunke kenn...@whitecape.org wrote: In the past, we preferred X-tiling for color buffers because our BLT code couldn't handle Y-tiling. However, the BLT paths have been largely replaced by BLORP on Gen6+, which can handle any kind of tiling. We hadn't measured any performance improvement in the past, but that's probably because compressed textures were all uncompressed anyway. s/uncompressed/untiled/ Series is Reviewed-by: Matt Turner matts...@gmail.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] i965/fs/gen7: Allow reads from MRFs.
Since they're actually GRFs, we can read from them.
total instructions in shared programs: 852751 - 851371 (-0.16%)
instructions in affected programs: 227286 - 225906 (-0.61%)
(no regressions)
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 22 --
1 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index c12ba45..57be319 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2121,16 +2121,18 @@ fs_visitor::compute_to_mrf()
/* You can't read from an MRF, so if someone else reads our
* MRF's source GRF that we wanted to rewrite, that stops us.
*/
-bool interfered = false;
-for (int i = 0; i 3; i++) {
- if (scan_inst-src[i].file == GRF
- scan_inst-src[i].reg == inst-src[0].reg
- scan_inst-src[i].reg_offset == inst-src[0].reg_offset) {
- interfered = true;
- }
-}
-if (interfered)
- break;
+ if (intel-gen 7) {
+bool interfered = false;
+for (int i = 0; i 3; i++) {
+ if (scan_inst-src[i].file == GRF
+ scan_inst-src[i].reg == inst-src[0].reg
+ scan_inst-src[i].reg_offset == inst-src[0].reg_offset) {
+ interfered = true;
+ }
+}
+if (interfered)
+ break;
+ }
if (scan_inst-dst.file == MRF) {
/* If somebody else writes our MRF here, we can't
--
1.7.8.6
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[Mesa-dev] [PATCH 2/2] i965/vs/gen7: Allow reads from MRFs.
Since they're actually GRFs, we can read from them.
total instructions in shared programs: 344973 - 342483 (-0.72%)
instructions in affected programs: 245602 - 243112 (-1.01%)
(no regressions)
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 23 +--
1 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index c58fb44..e337738 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -927,16 +927,18 @@ vec4_visitor::opt_register_coalesce()
* GRF we're trying to coalesce to, we don't actually handle
* rewriting sources so bail in that case as well.
*/
-bool interfered = false;
-for (int i = 0; i 3; i++) {
- if (scan_inst-src[i].file == GRF
- scan_inst-src[i].reg == inst-src[0].reg
- scan_inst-src[i].reg_offset == inst-src[0].reg_offset) {
- interfered = true;
- }
-}
-if (interfered)
- break;
+ if (intel-gen 7) {
+bool interfered = false;
+for (int i = 0; i 3; i++) {
+ if (scan_inst-src[i].file == GRF
+ scan_inst-src[i].reg == inst-src[0].reg
+ scan_inst-src[i].reg_offset == inst-src[0].reg_offset) {
+ interfered = true;
+ }
+}
+if (interfered)
+ break;
+ }
/* If somebody else writes our destination here, we can't coalesce
* before that.
@@ -956,6 +958,7 @@ vec4_visitor::opt_register_coalesce()
break;
}
} else {
+bool interfered = false;
for (int i = 0; i 3; i++) {
if (scan_inst-src[i].file == inst-dst.file
scan_inst-src[i].reg == inst-dst.reg
--
1.7.8.6
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Re: [Mesa-dev] [PATCH] gallium/opencl: Fix out-of-tree build
On Tue, Apr 9, 2013 at 2:28 AM, Niels Ole Salscheider niels_...@salscheider-online.de wrote: Am Dienstag, 9. April 2013, 11:17:39 schrieb Michel Dänzer: From: Michel Dänzer michel.daen...@amd.com Signed-off-by: Michel Dänzer michel.daen...@amd.com --- src/gallium/targets/opencl/Makefile.am | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/targets/opencl/Makefile.am b/src/gallium/targets/opencl/Makefile.am index 389eecc..810f9bb 100644 --- a/src/gallium/targets/opencl/Makefile.am +++ b/src/gallium/targets/opencl/Makefile.am @@ -32,11 +32,11 @@ libOpenCL_la_SOURCES = # Force usage of a C++ linker nodist_EXTRA_libOpenCL_la_SOURCES = dummy.cpp -PIPE_SRC_DIR = $(top_srcdir)/src/gallium/targets/pipe-loader +PIPE_BUILD_DIR = $(top_builddir)/src/gallium/targets/pipe-loader # Provide compatibility with scripts for the old Mesa build system for # a while by putting a link to the driver into /lib of the build tree. all-local: libOpenCL.la - @$(MAKE) -C $(PIPE_SRC_DIR) + @$(MAKE) -C $(PIPE_BUILD_DIR) $(MKDIR_P) $(top_builddir)/$(LIB_DIR) ln -f .libs/libOpenCL.so* $(top_builddir)/$(LIB_DIR)/ -- 1.8.2 I sent that patch to the list on 24.02.2013, but Matt Turner said that he has a better solution that does not involve calling make... Sorry for not handling it sooner. I really don't enjoy doing automake stuff -- it's hard to find the motivation to push through a big series that has even a small chance of breaking anything. I expected to get to finishing that series sooner when I emailed you. Michel, if you want to commit Niels' patch I'd be grateful. Whenever I get back to my series, I can easily enough rebase it. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] i965: NULL check prog on compilation failure.
I believe that prog can only be NULL for ARB programs. Neither
brw_fs_fp.cpp nor brw_vec4_vp.cpp call fail(), but not NULL checking
prog is obviously fragile.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 8 +---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 8 +---
src/mesa/drivers/dri/i965/brw_vs.c | 2 +-
src/mesa/drivers/dri/i965/brw_wm.c | 2 +-
4 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index c12ba45..2086af8 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2886,7 +2886,7 @@ brw_wm_fs_emit(struct brw_context *brw, struct
brw_wm_compile *c,
if (unlikely(INTEL_DEBUG DEBUG_WM)) {
if (shader) {
- printf(GLSL IR for native fragment shader %d:\n, prog-Name);
+ printf(GLSL IR for native fragment shader %d:\n, prog ? prog-Name
: -1);
_mesa_print_ir(shader-ir, NULL);
printf(\n\n);
} else {
@@ -2900,8 +2900,10 @@ brw_wm_fs_emit(struct brw_context *brw, struct
brw_wm_compile *c,
*/
fs_visitor v(brw, c, prog, fp, 8);
if (!v.run()) {
- prog-LinkStatus = false;
- ralloc_strcat(prog-InfoLog, v.fail_msg);
+ if (prog) {
+ prog-LinkStatus = false;
+ ralloc_strcat(prog-InfoLog, v.fail_msg);
+ }
_mesa_problem(NULL, Failed to compile fragment shader: %s\n,
v.fail_msg);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index c58fb44..446b4cf 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1506,7 +1506,7 @@ brw_vs_emit(struct brw_context *brw,
if (unlikely(INTEL_DEBUG DEBUG_VS)) {
if (shader) {
- printf(GLSL IR for native vertex shader %d:\n, prog-Name);
+ printf(GLSL IR for native vertex shader %d:\n, prog ? prog-Name :
-1);
_mesa_print_ir(shader-ir, NULL);
printf(\n\n);
} else {
@@ -1518,8 +1518,10 @@ brw_vs_emit(struct brw_context *brw,
vec4_visitor v(brw, c, prog, shader, mem_ctx);
if (!v.run()) {
- prog-LinkStatus = false;
- ralloc_strcat(prog-InfoLog, v.fail_msg);
+ if (prog) {
+ prog-LinkStatus = false;
+ ralloc_strcat(prog-InfoLog, v.fail_msg);
+ }
return NULL;
}
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c
b/src/mesa/drivers/dri/i965/brw_vs.c
index 6d2c0fd..f7a5e41 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -351,7 +351,7 @@ brw_vs_debug_recompile(struct brw_context *brw,
const struct brw_vs_prog_key *old_key = NULL;
bool found = false;
- perf_debug(Recompiling vertex shader for program %d\n, prog-Name);
+ perf_debug(Recompiling vertex shader for program %d\n, prog ? prog-Name
: -1);
for (unsigned int i = 0; i brw-cache.size; i++) {
for (c = brw-cache.items[i]; c; c = c-next) {
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c
b/src/mesa/drivers/dri/i965/brw_wm.c
index 9b30ba1..6bd95b4 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -248,7 +248,7 @@ brw_wm_debug_recompile(struct brw_context *brw,
const struct brw_wm_prog_key *old_key = NULL;
bool found = false;
- perf_debug(Recompiling fragment shader for program %d\n, prog-Name);
+ perf_debug(Recompiling fragment shader for program %d\n, prog ?
prog-Name : -1);
for (unsigned int i = 0; i brw-cache.size; i++) {
for (c = brw-cache.items[i]; c; c = c-next) {
--
1.8.1.5
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[Mesa-dev] [PATCH 2/2] i965/vs: Print error if vertex shader fails to compile.
--- src/mesa/drivers/dri/i965/brw_vec4.cpp | 4 1 file changed, 4 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 446b4cf..e129816 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -1522,6 +1522,10 @@ brw_vs_emit(struct brw_context *brw, prog-LinkStatus = false; ralloc_strcat(prog-InfoLog, v.fail_msg); } + + _mesa_problem(NULL, Failed to compile vertex shader: %s\n, +v.fail_msg); + return NULL; } -- 1.8.1.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] i965: NULL check prog on compilation failure.
On Tue, Apr 9, 2013 at 3:55 PM, Eric Anholt e...@anholt.net wrote: Matt Turner matts...@gmail.com writes: I believe that prog can only be NULL for ARB programs. Neither brw_fs_fp.cpp nor brw_vec4_vp.cpp call fail(), but not NULL checking prog is obviously fragile. (shader != NULL) = (prog != NULL), so if you want consistency I'd rather see the if (shader) changed to if (prog). Ah, that's better. A bunch of these changes are not about compilation failure, anyway. The changes to brw_vs.c and brw_wm.c? They actually are -- brw_vs_debug_recompile and brw_wm_debug_recompile are called below the modified hunks in brw_vec4.cpp and brw_fs.cpp. But they're called from inside if (shader) tests, so never mind. So, this patch is crap. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 3/5] i965/fs: Add a helper function for checking for partial register updates.
On Wed, Apr 10, 2013 at 11:54 AM, Eric Anholt e...@anholt.net wrote:
These checks were all over, and every time I wrote one I had to try to
decide again what the cases were for partial updates.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 35
+++-
src/mesa/drivers/dri/i965/brw_fs.h |1 +
.../drivers/dri/i965/brw_fs_copy_propagation.cpp |4 +--
src/mesa/drivers/dri/i965/brw_fs_cse.cpp |3 +-
.../drivers/dri/i965/brw_fs_live_variables.cpp |4 +--
5 files changed, 24 insertions(+), 23 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index c12ba45..331e1ea 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -711,6 +711,22 @@ fs_visitor::pop_force_sechalf()
}
/**
+ * Returns true if the instruction has a flag that means it won't
+ * update an entire destination register.
+ *
+ * For example, dead code elimination and live variable analysis want to know
+ * when a write to a variable screens off any preceding values that were in
+ * it.
+ */
+bool
+fs_inst::is_partial_write()
+{
+ return (this-predicate ||
+ this-force_uncompressed ||
+ this-force_sechalf);
+}
+
+/**
* Returns how many MRFs an FS opcode will write over.
*
* Note that this is not the 0 or 1 implied writes in an actual gen
@@ -2065,22 +2081,14 @@ fs_visitor::compute_to_mrf()
* into a compute-to-MRF.
*/
- /* If it's predicated, it (probably) didn't populate all
-* the channels. We might be able to rewrite everything
+ /* If this one instruction didn't populate all the
+* channels, bail. We might be able to rewrite everything
* that writes that reg, but it would require smarter
* tracking to delay the rewriting until complete success.
*/
- if (scan_inst-predicate)
+ if (scan_inst-is_partial_write())
break;
- /* If it's half of register setup and not the same half as
-* our MOV we're trying to remove, bail for now.
-*/
- if (scan_inst-force_uncompressed != inst-force_uncompressed ||
- scan_inst-force_sechalf != inst-force_sechalf) {
- break;
- }
-
/* Things returning more than one register would need us to
* understand coalescing out more than one MOV at a time.
*/
@@ -2662,10 +2670,7 @@ fs_visitor::get_instruction_generating_reg(fs_inst
*start,
fs_reg reg)
{
if (end == start ||
- end-predicate ||
- end-force_uncompressed ||
- end-force_sechalf ||
- reg.reladdr ||
Is the removal of reg.reladdr intentional?
+ end-is_partial_write() ||
!reg.equals(end-dst)) {
return NULL;
} else {
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 60e3e0a..f0901e7 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -179,6 +179,7 @@ public:
bool is_math();
bool is_control_flow();
bool is_send_from_grf();
+ bool is_partial_write();
fs_reg dst;
fs_reg src[3];
diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
index 36df759..234f8bd 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
@@ -414,9 +414,7 @@ fs_visitor::opt_copy_propagate_local(void *mem_ctx,
bblock_t *block,
inst-src[0].file == IMM)
inst-src[0].type == inst-dst.type
!inst-saturate
- !inst-predicate
- !inst-force_uncompressed
- !inst-force_sechalf) {
+ !inst-is_partial_write()) {
acp_entry *entry = ralloc(mem_ctx, acp_entry);
entry-dst = inst-dst;
entry-src = inst-src[0];
diff --git a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
index 2a8fd0b..b5c2200 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
@@ -97,8 +97,7 @@ fs_visitor::opt_cse_local(bblock_t *block, exec_list *aeb)
inst = (fs_inst *) inst-next) {
/* Skip some cases. */
- if (is_expression(inst) !inst-predicate
- !inst-force_uncompressed !inst-force_sechalf
+ if (is_expression(inst) !inst-is_partial_write()
!inst-conditional_mod)
{
bool found = false;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
b/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
index ca60aa2..fdcfac6 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
+++
Re: [Mesa-dev] [PATCH 4/5] i965/fs: Remove incorrect note of writing attr in centroid workaround.
On Wed, Apr 10, 2013 at 11:54 AM, Eric Anholt e...@anholt.net wrote: This instruction doesn't update its IR destination, it just moves from payload to f0. This caused the dead code elimination pass I'm adding to dead-code-eliminate the first step of interpolation. This was because it had a destination that was never read? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 5/5] i965/fs: Add basic-block-level dead code elimination.
On Wed, Apr 10, 2013 at 11:54 AM, Eric Anholt e...@anholt.net wrote:
This is a poor substitute for proper global dead code elimination that
could replace both our current paths, but it was very easy to write. It
particularly helps with Valve's shaders that are translated out of DX
assembly, which has been register allocated and thus have a bunch of
unrelated uses of the same variable (some of which get copy-propagated
from and then left for dead).
shader-db results:
total instructions in shared programs: 1735753 - 1731698 (-0.23%)
instructions in affected programs: 492620 - 488565 (-0.82%)
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 160
++
src/mesa/drivers/dri/i965/brw_fs.h |1 +
2 files changed, 161 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 3917dba..96e8a99 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -32,6 +32,7 @@ extern C {
#include sys/types.h
+#include main/hash_table.h
#include main/macros.h
#include main/shaderobj.h
#include main/uniforms.h
@@ -1823,6 +1824,164 @@ fs_visitor::dead_code_eliminate()
return progress;
}
+struct dead_code_hash_key
+{
+ int vgrf;
+ int reg_offset;
+};
+
+static bool
+dead_code_hash_compare(const void *a, const void *b)
+{
+ return memcmp(a, b, sizeof(struct dead_code_hash_key)) == 0;
+}
+
+static void
+clear_dead_code_hash(struct hash_table *ht)
+{
+ struct hash_entry *entry;
+
+ hash_table_foreach(ht, entry) {
+ _mesa_hash_table_remove(ht, entry);
+ }
+}
+
+static void
+insert_dead_code_hash(struct hash_table *ht,
+ int vgrf, int reg_offset, fs_inst *inst)
+{
+ /* We don't bother freeing keys, because they'll be GCed with the ht. */
+ struct dead_code_hash_key *key = ralloc(ht, struct dead_code_hash_key);
+
+ key-vgrf = vgrf;
+ key-reg_offset = reg_offset;
+
+ _mesa_hash_table_insert(ht, _mesa_hash_data(key, sizeof(*key)), key,
inst);
+}
+
+static struct hash_entry *
+get_dead_code_hash_entry(struct hash_table *ht, int vgrf, int reg_offset)
+{
+ struct dead_code_hash_key key;
+
+ key.vgrf = vgrf;
+ key.reg_offset = reg_offset;
+
+ return _mesa_hash_table_search(ht, _mesa_hash_data(key, sizeof(key)),
key);
+}
+
+static void
+remove_dead_code_hash(struct hash_table *ht,
+ int vgrf, int reg_offset)
+{
+ struct hash_entry *entry = get_dead_code_hash_entry(ht, vgrf, reg_offset);
+ if (!entry)
+ return;
+
+ _mesa_hash_table_remove(ht, entry);
+}
+
+/**
+ * Walks basic blocks, removing any regs that are written but not read before
+ * being redefined.
+ *
+ * The dead_code_eliminate() function implements a global dead code
+ * elimination, but it only handles the removing the last write to a register
+ * if it's never read. This one can handle intermediate writes, but only
+ * within a basic block.
+ */
+bool
+fs_visitor::dead_code_eliminate_local()
+{
+ struct hash_table *ht;
+ bool progress = false;
+
+ ht = _mesa_hash_table_create(mem_ctx, dead_code_hash_compare);
+
+ foreach_list_safe(node, this-instructions) {
+ fs_inst *inst = (fs_inst *)node;
+
+ /* At a basic block, empty the HT since we don't understand dataflow
+ * here.
+ */
+ if (inst-is_control_flow()) {
+ clear_dead_code_hash(ht);
+ continue;
+ }
+
+ /* Clear the HT of any instructions that got read. */
+ for (int i = 0; i 3; i++) {
+ fs_reg src = inst-src[i];
+ if (src.file != GRF)
+continue;
+
+ int read = 1;
+ if (inst-is_send_from_grf())
+read = virtual_grf_sizes[src.reg] - src.reg_offset;
+
+ for (int reg_offset = src.reg_offset;
+ reg_offset src.reg_offset + read;
+ reg_offset++) {
+remove_dead_code_hash(ht, src.reg, reg_offset);
+ }
+ }
+
+ /* Add any update of a GRF to the HT, removing a previous write if it's
s/it's/it/
+ * wasn't read.
+ */
+ if (inst-dst.file == GRF) {
+ if (inst-regs_written 1) {
+/* We don't know how to trim channels from an instruction's
+ * writes, so we can't incrementally remove unread channels from
+ * it. Just remove whatever it overwrites from the table
+ */
+for (int i = 0; i inst-regs_written; i++) {
+ remove_dead_code_hash(ht,
+ inst-dst.reg,
+ inst-dst.reg_offset + i);
+}
+ } else {
+struct hash_entry *entry =
+ get_dead_code_hash_entry(ht, inst-dst.reg,
+inst-dst.reg_offset);
+
+if
Re: [Mesa-dev] i965: more dead code elimination
On Wed, Apr 10, 2013 at 11:54 AM, Eric Anholt e...@anholt.net wrote: Motivated by some troubles in register allocation on Valve's shaders, I found a cheap (runtime and development time) way to cut some dead code. This looked like failure due to losing 16-wide programs, until I updated more apps in shader-db to use shader_tests (which provide more accurate simulation, since your FS attributes are no longer demoted to undefined temporary values). shader-db results: total instructions in shared programs: 1735753 - 1731698 (-0.23%) instructions in affected programs: 492620 - 488565 (-0.82%) There are also a few cleanup patches attached that have been kicking around several optimization branches I have. This series is on the local-dce branch of my tree. Assuming the comment in #3 is addressed and my understanding of #4 is correct, the series is Reviewed-by: Matt Turner matts...@gmail.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 1/2] i965: NULL check prog on shader compilation failure.
Also change if (shader) to if (prog) for consistency.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 12 +++-
src/mesa/drivers/dri/i965/brw_vec4.cpp |8 +---
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 4338ae6..2b6208c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2885,7 +2885,7 @@ brw_wm_fs_emit(struct brw_context *brw, struct
brw_wm_compile *c,
shader = (brw_shader *) prog-_LinkedShaders[MESA_SHADER_FRAGMENT];
if (unlikely(INTEL_DEBUG DEBUG_WM)) {
- if (shader) {
+ if (prog) {
printf(GLSL IR for native fragment shader %d:\n, prog-Name);
_mesa_print_ir(shader-ir, NULL);
printf(\n\n);
@@ -2900,11 +2900,13 @@ brw_wm_fs_emit(struct brw_context *brw, struct
brw_wm_compile *c,
*/
fs_visitor v(brw, c, prog, fp, 8);
if (!v.run()) {
- prog-LinkStatus = false;
- ralloc_strcat(prog-InfoLog, v.fail_msg);
+ if (prog) {
+ prog-LinkStatus = false;
+ ralloc_strcat(prog-InfoLog, v.fail_msg);
- _mesa_problem(NULL, Failed to compile fragment shader: %s\n,
- v.fail_msg);
+ _mesa_problem(NULL, Failed to compile fragment shader: %s\n,
+ v.fail_msg);
+ }
return NULL;
}
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index b6d454f..4f7b8c0 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1531,7 +1531,7 @@ brw_vs_emit(struct brw_context *brw,
shader = (brw_shader *) prog-_LinkedShaders[MESA_SHADER_VERTEX];
if (unlikely(INTEL_DEBUG DEBUG_VS)) {
- if (shader) {
+ if (prog) {
printf(GLSL IR for native vertex shader %d:\n, prog-Name);
_mesa_print_ir(shader-ir, NULL);
printf(\n\n);
@@ -1544,8 +1544,10 @@ brw_vs_emit(struct brw_context *brw,
vec4_vs_visitor v(brw, c, prog_data, prog, shader, mem_ctx);
if (!v.run()) {
- prog-LinkStatus = false;
- ralloc_strcat(prog-InfoLog, v.fail_msg);
+ if (prog) {
+ prog-LinkStatus = false;
+ ralloc_strcat(prog-InfoLog, v.fail_msg);
+ }
return NULL;
}
--
1.7.8.6
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 2/2] i965/vs: Print error if vertex shader fails to compile.
---
src/mesa/drivers/dri/i965/brw_vec4.cpp |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 4f7b8c0..6a2ce35 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1547,6 +1547,9 @@ brw_vs_emit(struct brw_context *brw,
if (prog) {
prog-LinkStatus = false;
ralloc_strcat(prog-InfoLog, v.fail_msg);
+
+ _mesa_problem(NULL, Failed to compile vertex shader: %s\n,
+ v.fail_msg);
}
return NULL;
}
--
1.7.8.6
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] intel: release build compile warnings cleanups
On Thu, Apr 11, 2013 at 11:06 AM, Eric Anholt e...@anholt.net wrote: I got tired of freaking out a little every time I built my release tree because of compile warnings. All but the last 2 seemed like pretty clean fixes to me. And then there's the first patch, which is unrelated but I found while trying to figure out why register_coalesce() does something that opt_copy_propagate() doesn't. Available at compile-warnings of my tree. Series is Reviewed-by: Matt Turner matts...@gmail.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] mesa: Add core support for the GL_AMD_performance_monitor extension.
On Thu, Apr 11, 2013 at 2:00 PM, Kenneth Graunke kenn...@whitecape.org wrote:
This provides an interface for applications (and OpenGL-based tools) to
access GPU performance counters. Since the exact performance counters
available vary between vendors and hardware generations, the extension
provides an API the application can use to get the names, types, and
minimum/maximum values of all available counters. Counters are also
organized into groups.
Applications create performance monitor objects, select the counters
they want to track, and Begin/End monitoring, much like OpenGL's query
API. Multiple monitors can be in flight simultaneously.
We chose not to implement the similar GL_INTEL_performance_queries
extension because Intel has not bothered to publish a specification in
the OpenGL registry.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mapi/glapi/gen/Makefile.am | 1 +
src/mapi/glapi/gen/gl_API.xml| 2 +
src/mapi/glapi/gen/gl_genexec.py | 1 +
src/mesa/SConscript | 1 +
src/mesa/main/context.c | 2 +
src/mesa/main/dd.h | 22 +++
src/mesa/main/extensions.c | 1 +
src/mesa/main/mtypes.h | 84
src/mesa/sources.mak | 1 +
9 files changed, 115 insertions(+)
diff --git a/src/mapi/glapi/gen/Makefile.am b/src/mapi/glapi/gen/Makefile.am
index 36e47e2..baf8afc 100644
--- a/src/mapi/glapi/gen/Makefile.am
+++ b/src/mapi/glapi/gen/Makefile.am
@@ -115,6 +115,7 @@ API_XML = \
ARB_texture_storage.xml \
ARB_vertex_array_object.xml \
AMD_draw_buffers_blend.xml \
+ AMD_performance_monitor.xml \
ARB_vertex_type_2_10_10_10_rev.xml \
I was going to ask if you could alphabetize this, but the whole list is hosed.
APPLE_object_purgeable.xml \
APPLE_vertex_array_object.xml \
diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml
index df95924..afc7673 100644
--- a/src/mapi/glapi/gen/gl_API.xml
+++ b/src/mapi/glapi/gen/gl_API.xml
@@ -12743,6 +12743,8 @@
enum name=FRAMEBUFFER_SRGB_CAPABLE_EXT value=0x8DBA/
/category
+xi:include href=AMD_performance_monitor.xml
xmlns:xi=http://www.w3.org/2001/XInclude/
+
category name=GL_APPLE_texture_range number=367
enum name=TEXTURE_STORAGE_HINT_APPLE count=1 value=0x85BC
size name=TexParameteriv/
diff --git a/src/mapi/glapi/gen/gl_genexec.py
b/src/mapi/glapi/gen/gl_genexec.py
index a85b447..e1233c4 100644
--- a/src/mapi/glapi/gen/gl_genexec.py
+++ b/src/mapi/glapi/gen/gl_genexec.py
@@ -82,6 +82,7 @@ header = /**
#include main/lines.h
#include main/matrix.h
#include main/multisample.h
+#include main/performance_monitor.h
#include main/pixel.h
#include main/pixelstore.h
#include main/points.h
diff --git a/src/mesa/SConscript b/src/mesa/SConscript
index ca9b70b..9726c95 100644
--- a/src/mesa/SConscript
+++ b/src/mesa/SConscript
@@ -97,6 +97,7 @@ main_sources = [
'main/multisample.c',
'main/pack.c',
'main/pbo.c',
+'main/performance_monitor.c',
'main/pixel.c',
'main/pixelstore.c',
'main/pixeltransfer.c',
diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index 0539934..960239a 100644
--- a/src/mesa/main/context.c
+++ b/src/mesa/main/context.c
@@ -106,6 +106,7 @@
#include macros.h
#include matrix.h
#include multisample.h
+#include performance_monitor.h
#include pixel.h
#include pixelstore.h
#include points.h
@@ -762,6 +763,7 @@ init_attrib_groups(struct gl_context *ctx)
_mesa_init_lighting( ctx );
_mesa_init_matrix( ctx );
_mesa_init_multisample( ctx );
+ _mesa_init_performance_monitors( ctx );
_mesa_init_pixel( ctx );
_mesa_init_pixelstore( ctx );
_mesa_init_point( ctx );
diff --git a/src/mesa/main/dd.h b/src/mesa/main/dd.h
index 8f3cd3d..60e7653 100644
--- a/src/mesa/main/dd.h
+++ b/src/mesa/main/dd.h
@@ -646,6 +646,28 @@ struct dd_function_table {
void (*WaitQuery)(struct gl_context *ctx, struct gl_query_object *q);
/*@}*/
+ /**
+* \name Performance monitors
+*/
+ /*@{*/
+ struct gl_perf_monitor_object * (*NewPerfMonitor)(void);
+ void (*DeletePerfMonitor)(struct gl_perf_monitor_object *m);
+ void (*BeginPerfMonitor)(struct gl_context *ctx,
+struct gl_perf_monitor_object *m);
+
+ /** Stop an active performance monitor, discarding results. */
+ void (*ResetPerfMonitor)(struct gl_context *ctx,
+struct gl_perf_monitor_object *m);
+ void (*EndPerfMonitor)(struct gl_context *ctx,
+ struct gl_perf_monitor_object *m);
+ GLboolean (*IsPerfMonitorResultAvailable)(struct gl_perf_monitor_object
*m);
+ void (*GetPerfMonitorResult)(struct gl_context *ctx,
+struct gl_perf_monitor_object *m,
+
[Mesa-dev] [PATCH 01/12] build: Rename sources.mak - Makefile.sources
For the sake of consistency. Tested-by: Emil Velikov emil.l.veli...@gmail.com Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com --- src/glx/apple/Makefile | 2 +- src/mapi/glapi/Makefile.am | 4 +- src/mapi/glapi/Makefile.sources | 19 ++ src/mapi/glapi/sources.mak | 19 -- src/mapi/mapi/Makefile.sources | 36 src/mapi/mapi/sources.mak | 36 src/mapi/shared-glapi/Makefile.am | 2 +- src/mapi/vgapi/Makefile.am | 2 +- src/mesa/Android.libmesa_dricore.mk | 2 +- src/mesa/Android.libmesa_st_mesa.mk | 2 +- src/mesa/Makefile.am| 2 +- src/mesa/Makefile.sources | 350 src/mesa/libdricore/Makefile.am | 2 +- src/mesa/program/Android.mk | 4 +- src/mesa/program/Makefile.am| 2 +- src/mesa/sources.mak| 350 16 files changed, 417 insertions(+), 417 deletions(-) create mode 100644 src/mapi/glapi/Makefile.sources delete mode 100644 src/mapi/glapi/sources.mak create mode 100644 src/mapi/mapi/Makefile.sources delete mode 100644 src/mapi/mapi/sources.mak create mode 100644 src/mesa/Makefile.sources delete mode 100644 src/mesa/sources.mak diff --git a/src/glx/apple/Makefile b/src/glx/apple/Makefile index f6faa1e..7dab068 100644 --- a/src/glx/apple/Makefile +++ b/src/glx/apple/Makefile @@ -58,7 +58,7 @@ SOURCES = \ ../xfont.c \ ../applegl_glx.c -include $(TOP)/src/mesa/sources.mak +include $(TOP)/src/mesa/Makefile.sources # override GLAPI_LIB GLAPI_LIB = $(TOP)/src/mapi/glapi/libglapi.a diff --git a/src/mapi/glapi/Makefile.am b/src/mapi/glapi/Makefile.am index bdb527d..cf2602a 100644 --- a/src/mapi/glapi/Makefile.am +++ b/src/mapi/glapi/Makefile.am @@ -20,8 +20,8 @@ # IN THE SOFTWARE. TOP = $(top_srcdir) -include sources.mak -include ../mapi/sources.mak +include Makefile.sources +include ../mapi/Makefile.sources AM_CPPFLAGS = \ $(DEFINES) \ diff --git a/src/mapi/glapi/Makefile.sources b/src/mapi/glapi/Makefile.sources new file mode 100644 index 000..58d28c5 --- /dev/null +++ b/src/mapi/glapi/Makefile.sources @@ -0,0 +1,19 @@ +# src/mapi/glapi/Makefile.sources + +GLAPI_SOURCES = \ + glapi_dispatch.c \ + glapi_entrypoint.c \ + glapi_gentable.c \ + glapi_getproc.c \ + glapi_nop.c \ + glthread.c \ + glapi.c + +X86_API = \ + glapi_x86.S + +X86_64_API = \ + glapi_x86-64.S + +SPARC_API =\ + glapi_sparc.S diff --git a/src/mapi/glapi/sources.mak b/src/mapi/glapi/sources.mak deleted file mode 100644 index aa8a4d4..000 --- a/src/mapi/glapi/sources.mak +++ /dev/null @@ -1,19 +0,0 @@ -# src/mapi/glapi/sources.mak - -GLAPI_SOURCES = \ - glapi_dispatch.c \ - glapi_entrypoint.c \ - glapi_gentable.c \ - glapi_getproc.c \ - glapi_nop.c \ - glthread.c \ - glapi.c - -X86_API = \ - glapi_x86.S - -X86_64_API = \ - glapi_x86-64.S - -SPARC_API =\ - glapi_sparc.S diff --git a/src/mapi/mapi/Makefile.sources b/src/mapi/mapi/Makefile.sources new file mode 100644 index 000..a2f6c71 --- /dev/null +++ b/src/mapi/mapi/Makefile.sources @@ -0,0 +1,36 @@ +# src/mapi/mapi/Makefile.sources +# +# mapi may be used in several ways +# +# - In default mode, mapi implements the interface defined by mapi.h. To use +#this mode, compile MAPI_FILES. +# +# - In util mode, mapi provides utility functions for use with glapi. To use +#this mode, compile MAPI_UTIL_FILES with MAPI_MODE_UTIL defined. +# +# - In glapi mode, mapi implements the interface defined by glapi.h. To use +#this mode, compile MAPI_GLAPI_FILES with MAPI_MODE_GLAPI defined. +# +# - In bridge mode, mapi provides entry points calling into glapi. To use +#this mode, compile MAPI_BRIDGE_FILES with MAPI_MODE_BRIDGE defined. + +MAPI_UTIL_FILES = \ + $(TOP)/src/mapi/mapi/u_current.c \ + $(TOP)/src/mapi/mapi/u_execmem.c + +MAPI_FILES = \ + $(TOP)/src/mapi/mapi/entry.c \ + $(TOP)/src/mapi/mapi/mapi.c \ + $(TOP)/src/mapi/mapi/stub.c \ + $(TOP)/src/mapi/mapi/table.c \ + $(MAPI_UTIL_FILES) + +MAPI_GLAPI_FILES = \ + $(TOP)/src/mapi/mapi/entry.c \ + $(TOP)/src/mapi/mapi/mapi_glapi.c \ + $(TOP)/src/mapi/mapi/stub.c \ + $(TOP)/src/mapi/mapi/table.c \ + $(MAPI_UTIL_FILES) + +MAPI_BRIDGE_FILES = \ + $(TOP)/src/mapi/mapi/entry.c diff --git a/src/mapi/mapi/sources.mak b/src/mapi/mapi/sources.mak deleted file mode 100644 index 56f4afd..000 --- a/src/mapi/mapi/sources.mak +++ /dev/null @@ -1,36 +0,0 @@ -# src/mapi/mapi/sources.mak -# -# mapi may be used in several ways -# -# - In default mode, mapi implements the interface defined by mapi.h. To use -#this mode, compile MAPI_FILES.
[Mesa-dev] [PATCH 03/12] build: Get rid of CORE_DIRS
A step toward working make dist/distcheck. Tested-by: Emil Velikov emil.l.veli...@gmail.com Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com --- configure.ac | 37 - src/Makefile.am | 30 +++--- src/mapi/Makefile.am | 42 ++ 3 files changed, 77 insertions(+), 32 deletions(-) create mode 100644 src/mapi/Makefile.am diff --git a/configure.ac b/configure.ac index 55ebb07..c658047 100644 --- a/configure.ac +++ b/configure.ac @@ -690,6 +690,13 @@ if test x$enable_gles2 = xyes; then fi AC_SUBST([API_DEFINES]) +AM_CONDITIONAL(HAVE_OPENGL, test x$enable_opengl = xyes) +AM_CONDITIONAL(HAVE_OPENGL_ES1, test x$enable_gles1 = xyes) +AM_CONDITIONAL(HAVE_OPENGL_ES2, test x$enable_gles2 = xyes) +AM_CONDITIONAL(NEED_OPENGL_COMMON, test x$enable_opengl = xyes -o \ +x$enable_gles1 = xyes -o \ +x$enable_gles2 = xyes) + if test x$enable_glx = xno; then AC_MSG_WARN([GLX disabled, disabling Xlib-GLX]) enable_xlib_glx=no @@ -737,7 +744,6 @@ if test x$enable_shared_glapi = xyes; then # libGL will use libglapi for function lookups (IN_DRI_DRIVER means to use # the remap table) DEFINES=$DEFINES -DIN_DRI_DRIVER -CORE_DIRS=mapi/shared-glapi fi AM_CONDITIONAL(HAVE_SHARED_GLAPI, test x$enable_shared_glapi = xyes) @@ -750,28 +756,6 @@ GALLIUM_WINSYS_DIRS=sw GALLIUM_DRIVERS_DIRS=galahad trace rbug noop identity GALLIUM_STATE_TRACKERS_DIRS= -# build glapi if OpenGL is enabled -if test x$enable_opengl = xyes; then -CORE_DIRS=$CORE_DIRS mapi/glapi -fi - -# build es1api if OpenGL ES 1.x is enabled -if test x$enable_gles1 = xyes; then -CORE_DIRS=$CORE_DIRS mapi/es1api -fi - -# build es2api if OpenGL ES 2.x is enabled -if test x$enable_gles2 = xyes; then -CORE_DIRS=$CORE_DIRS mapi/es2api -fi - -# build glsl and mesa if OpenGL or OpenGL ES is enabled -case x$enable_opengl$enable_gles1$enable_gles2 in -x*yes*) -CORE_DIRS=mapi/glapi/gen $CORE_DIRS gtest glsl mesa -;; -esac - case x$enable_glx$enable_xlib_glx in xyesyes) DRIVER_DIRS=$DRIVER_DIRS x11 @@ -1341,7 +1325,6 @@ if test x$enable_openvg = xyes; then EGL_CLIENT_APIS=$EGL_CLIENT_APIS '$(VG_LIB)' VG_LIB_DEPS=$VG_LIB_DEPS $SELINUX_LIBS $PTHREAD_LIBS -CORE_DIRS=$CORE_DIRS mapi/vgapi GALLIUM_STATE_TRACKERS_DIRS=vega $GALLIUM_STATE_TRACKERS_DIRS HAVE_ST_VEGA=yes VG_PC_LIB_PRIV=-lm $CLOCK_LIB $PTHREAD_LIBS $DLOPEN_LIBS @@ -1455,10 +1438,8 @@ AC_SUBST([CLANG_RESOURCE_DIR]) case x$enable_opengl$enable_gles1$enable_gles2 in x*yes*) EGL_CLIENT_APIS=$EGL_CLIENT_APIS '$(GL_LIB)' -HAVE_OPENGL=yes ;; esac -AM_CONDITIONAL(HAVE_OPENGL, test x$HAVE_OPENGL = xyes) AC_SUBST([VG_LIB_DEPS]) AC_SUBST([EGL_CLIENT_APIS]) @@ -2022,9 +2003,6 @@ AC_SUBST([XA_MINOR], 0) AC_SUBST([XA_TINY], 0) AC_SUBST([XA_VERSION], $XA_MAJOR.$XA_MINOR.$XA_TINY) -dnl prepend CORE_DIRS to SRC_DIRS -SRC_DIRS=$CORE_DIRS $SRC_DIRS - dnl Restore LDFLAGS and CPPFLAGS LDFLAGS=$_SAVE_LDFLAGS CPPFLAGS=$_SAVE_CPPFLAGS @@ -2132,6 +2110,7 @@ AC_CONFIG_FILES([Makefile src/glx/Makefile src/glx/tests/Makefile src/gtest/Makefile + src/mapi/Makefile src/mapi/es1api/Makefile src/mapi/es1api/glesv1_cm.pc src/mapi/es2api/Makefile diff --git a/src/Makefile.am b/src/Makefile.am index d6a7946..d096f29 100644 --- a/src/Makefile.am +++ b/src/Makefile.am @@ -1,4 +1,28 @@ -SUBDIRS=$(SRC_DIRS) +# Copyright © 2013 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the Software), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. -all-local: - $(MKDIR_P) $(top_builddir)/$(LIB_DIR) +SUBDIRS = gtest mapi + +if NEED_OPENGL_COMMON +SUBDIRS += glsl mesa +endif + +SUBDIRS += $(SRC_DIRS) diff --git a/src/mapi/Makefile.am
[Mesa-dev] [PATCH 04/12] build: Get rid of SRC_DIRS
Tested-by: Emil Velikov emil.l.veli...@gmail.com Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com --- Since last time: - Stop building src/glx for xlib-glx, as noticed out by Eric and Andreas. (Relies on the fact that $enable_dri and $enable_xlib_glx are mutually exclusive) configure.ac| 21 +++-- src/Makefile.am | 25 - 2 files changed, 31 insertions(+), 15 deletions(-) diff --git a/configure.ac b/configure.ac index c658047..8537de1 100644 --- a/configure.ac +++ b/configure.ac @@ -724,6 +724,8 @@ if test x$enable_glx = xyes -a \ enable_glx=no fi +AM_CONDITIONAL(HAVE_DRI_GLX, test x$enable_glx = xyes -a \ + x$enable_dri = xyes) AM_CONDITIONAL(HAVE_DRI, test x$enable_dri = xyes) AM_CONDITIONAL(NEED_LIBMESA, test x$enable_xlib_glx = xyes -o \ x$enable_osmesa = xyes) @@ -764,10 +766,6 @@ xyesyes) GALLIUM_STATE_TRACKERS_DIRS=glx $GALLIUM_STATE_TRACKERS_DIRS HAVE_WINSYS_XLIB=yes ;; -xyesno) -# DRI-based GLX -SRC_DIRS=$SRC_DIRS glx -;; esac if test x$enable_dri = xyes; then @@ -784,7 +782,6 @@ if test x$enable_osmesa = xyes; then GALLIUM_TARGET_DIRS=$GALLIUM_TARGET_DIRS osmesa fi -AC_SUBST([SRC_DIRS]) AC_SUBST([DRIVER_DIRS]) AC_SUBST([GALLIUM_DIRS]) AC_SUBST([GALLIUM_TARGET_DIRS]) @@ -1181,8 +1178,6 @@ if test x$enable_gbm = xauto; then esac fi if test x$enable_gbm = xyes; then -SRC_DIRS=$SRC_DIRS gbm - PKG_CHECK_MODULES([LIBUDEV], [libudev], [], AC_MSG_ERROR([gbm needs udev])) @@ -1193,6 +1188,7 @@ if test x$enable_gbm = xyes; then fi fi fi +AM_CONDITIONAL(HAVE_GBM, test x$enable_gbm = xyes) GBM_PC_REQ_PRIV=libudev GBM_PC_LIB_PRIV=$DLOPEN_LIBS AC_SUBST([GBM_PC_REQ_PRIV]) @@ -1204,7 +1200,6 @@ dnl EGL_CLIENT_APIS= if test x$enable_egl = xyes; then -SRC_DIRS=$SRC_DIRS egl EGL_LIB_DEPS=$DLOPEN_LIBS $SELINUX_LIBS $PTHREAD_LIBS AC_CHECK_FUNC(mincore, [DEFINES=$DEFINES -DHAVE_MINCORE]) @@ -1223,6 +1218,7 @@ if test x$enable_egl = xyes; then fi fi +AM_CONDITIONAL(HAVE_EGL, test x$enable_egl = xyes) AC_SUBST([EGL_LIB_DEPS]) dnl @@ -1419,10 +1415,7 @@ fi dnl dnl Gallium configuration dnl -if test x$with_gallium_drivers != x; then -SRC_DIRS=$SRC_DIRS gallium gallium/winsys gallium/targets -fi -AM_CONDITIONAL(HAVE_GALLIUM, test x$with_gallium_drivers != x) +AM_CONDITIONAL(HAVE_GALLIUM, test -n $with_gallium_drivers) AC_SUBST([LLVM_BINDIR]) AC_SUBST([LLVM_CFLAGS]) @@ -1680,9 +1673,9 @@ dnl dnl Gallium Tests dnl if test x$enable_gallium_tests = xyes; then -SRC_DIRS=$SRC_DIRS gallium/tests/trivial gallium/tests/unit enable_gallium_loader=yes fi +AM_CONDITIONAL(HAVE_GALLIUM_TESTS, test x$enable_gallium_tests = xyes) dnl Directory for VDPAU libs AC_ARG_WITH([vdpau-libdir], @@ -2231,7 +2224,7 @@ else fi echo -if echo $SRC_DIRS | grep 'gallium' /dev/null 21; then +if test -n $with_gallium_drivers; then echo Gallium: yes echo Gallium dirs:$GALLIUM_DIRS echo Target dirs: $GALLIUM_TARGET_DIRS diff --git a/src/Makefile.am b/src/Makefile.am index d096f29..b6449b9 100644 --- a/src/Makefile.am +++ b/src/Makefile.am @@ -25,4 +25,27 @@ if NEED_OPENGL_COMMON SUBDIRS += glsl mesa endif -SUBDIRS += $(SRC_DIRS) +if HAVE_DRI_GLX +SUBDIRS += glx +endif + +if HAVE_GBM +SUBDIRS += gbm +endif + +if HAVE_EGL +SUBDIRS += egl +endif + +if HAVE_GALLIUM +SUBDIRS += \ + gallium \ + gallium/winsys \ + gallium/targets + +if HAVE_GALLIUM_TESTS +SUBDIRS += \ + gallium/tests/trivial \ + gallium/tests/unit +endif +endif -- 1.8.1.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 05/12] build: Remove GALLIUM_DIRS
It's always constant anyway. Tested-by: Emil Velikov emil.l.veli...@gmail.com Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com --- configure.ac| 4 src/Makefile.am | 4 +++- src/gallium/Makefile.am | 22 -- 3 files changed, 3 insertions(+), 27 deletions(-) delete mode 100644 src/gallium/Makefile.am diff --git a/configure.ac b/configure.ac index 8537de1..299007d 100644 --- a/configure.ac +++ b/configure.ac @@ -752,7 +752,6 @@ AM_CONDITIONAL(HAVE_SHARED_GLAPI, test x$enable_shared_glapi = xyes) dnl dnl Driver specific build directories dnl -GALLIUM_DIRS=auxiliary drivers state_trackers GALLIUM_TARGET_DIRS= GALLIUM_WINSYS_DIRS=sw GALLIUM_DRIVERS_DIRS=galahad trace rbug noop identity @@ -783,7 +782,6 @@ if test x$enable_osmesa = xyes; then fi AC_SUBST([DRIVER_DIRS]) -AC_SUBST([GALLIUM_DIRS]) AC_SUBST([GALLIUM_TARGET_DIRS]) AC_SUBST([GALLIUM_WINSYS_DIRS]) AC_SUBST([GALLIUM_DRIVERS_DIRS]) @@ -2017,7 +2015,6 @@ AC_CONFIG_FILES([Makefile src/egl/wayland/wayland-drm/Makefile src/egl/wayland/wayland-egl/Makefile src/egl/wayland/wayland-egl/wayland-egl.pc - src/gallium/Makefile src/gallium/auxiliary/Makefile src/gallium/auxiliary/pipe-loader/Makefile src/gallium/drivers/Makefile @@ -2226,7 +2223,6 @@ fi echo if test -n $with_gallium_drivers; then echo Gallium: yes -echo Gallium dirs:$GALLIUM_DIRS echo Target dirs: $GALLIUM_TARGET_DIRS echo Winsys dirs: $GALLIUM_WINSYS_DIRS echo Driver dirs: $GALLIUM_DRIVERS_DIRS diff --git a/src/Makefile.am b/src/Makefile.am index b6449b9..b3dc44d 100644 --- a/src/Makefile.am +++ b/src/Makefile.am @@ -39,7 +39,9 @@ endif if HAVE_GALLIUM SUBDIRS += \ - gallium \ + gallium/auxiliary \ + gallium/drivers \ + gallium/state_trackers \ gallium/winsys \ gallium/targets diff --git a/src/gallium/Makefile.am b/src/gallium/Makefile.am deleted file mode 100644 index e7cff89..000 --- a/src/gallium/Makefile.am +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright © 2012 Intel Corporation -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the Software), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. - -SUBDIRS = $(GALLIUM_DIRS) -- 1.8.1.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 06/12] build: Stop AC_SUBST'ing DRI_DIRS and GALLIUM_DRIVERS_DIRS
Neither are used in Makefile.ams. Tested-by: Emil Velikov emil.l.veli...@gmail.com Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com --- configure.ac | 2 -- 1 file changed, 2 deletions(-) diff --git a/configure.ac b/configure.ac index 299007d..9eec334 100644 --- a/configure.ac +++ b/configure.ac @@ -784,7 +784,6 @@ fi AC_SUBST([DRIVER_DIRS]) AC_SUBST([GALLIUM_TARGET_DIRS]) AC_SUBST([GALLIUM_WINSYS_DIRS]) -AC_SUBST([GALLIUM_DRIVERS_DIRS]) AC_SUBST([GALLIUM_STATE_TRACKERS_DIRS]) AC_SUBST([MESA_LLVM]) @@ -1065,7 +1064,6 @@ if test x$enable_dri = xyes; then GALLIUM_DRI_LIB_DEPS=$GALLIUM_DRI_LIB_DEPS $SELINUX_LIBS $LIBDRM_LIBS $EXPAT_LIB -lm $CLOCK_LIB $PTHREAD_LIBS $DLOPEN_LIBS fi AM_CONDITIONAL(NEED_LIBDRICORE, test -n $DRI_DIRS) -AC_SUBST([DRI_DIRS]) AC_SUBST([EXPAT_INCLUDES]) AC_SUBST([DRI_LIB_DEPS]) AC_SUBST([GALLIUM_DRI_LIB_DEPS]) -- 1.8.1.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 07/12] build: Get rid of DRIVER_DIRS
Tested-by: Emil Velikov emil.l.veli...@gmail.com Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com --- configure.ac | 9 ++--- src/mesa/Makefile.am | 14 +- src/mesa/drivers/Makefile.am | 22 -- 3 files changed, 15 insertions(+), 30 deletions(-) delete mode 100644 src/mesa/drivers/Makefile.am diff --git a/configure.ac b/configure.ac index 9eec334..4421895 100644 --- a/configure.ac +++ b/configure.ac @@ -759,7 +759,6 @@ GALLIUM_STATE_TRACKERS_DIRS= case x$enable_glx$enable_xlib_glx in xyesyes) -DRIVER_DIRS=$DRIVER_DIRS x11 GALLIUM_WINSYS_DIRS=$GALLIUM_WINSYS_DIRS sw/xlib GALLIUM_TARGET_DIRS=$GALLIUM_TARGET_DIRS libgl-xlib GALLIUM_STATE_TRACKERS_DIRS=glx $GALLIUM_STATE_TRACKERS_DIRS @@ -768,20 +767,16 @@ xyesyes) esac if test x$enable_dri = xyes; then -DRIVER_DIRS=$DRIVER_DIRS dri - GALLIUM_WINSYS_DIRS=$GALLIUM_WINSYS_DIRS sw/dri GALLIUM_STATE_TRACKERS_DIRS=dri $GALLIUM_STATE_TRACKERS_DIRS HAVE_ST_DRI=yes fi if test x$enable_osmesa = xyes; then -DRIVER_DIRS=$DRIVER_DIRS osmesa GALLIUM_STATE_TRACKERS_DIRS=osmesa $GALLIUM_STATE_TRACKERS_DIRS GALLIUM_TARGET_DIRS=$GALLIUM_TARGET_DIRS osmesa fi -AC_SUBST([DRIVER_DIRS]) AC_SUBST([GALLIUM_TARGET_DIRS]) AC_SUBST([GALLIUM_WINSYS_DIRS]) AC_SUBST([GALLIUM_STATE_TRACKERS_DIRS]) @@ -1973,7 +1968,8 @@ AC_SUBST([GALLIUM_MAKE_DIRS]) AM_CONDITIONAL(NEED_LIBPROGRAM, test x$with_gallium_drivers != x -o \ x$enable_xlib_glx = xyes -o \ x$enable_osmesa = xyes) -AM_CONDITIONAL(HAVE_X11_DRIVER, echo $DRIVER_DIRS | grep 'x11' /dev/null 21) +AM_CONDITIONAL(HAVE_X11_DRIVER, test x$enable_xlib_glx = xyes) +AM_CONDITIONAL(HAVE_OSMESA, test x$enable_osmesa = xyes) AM_CONDITIONAL(HAVE_X86_ASM, echo $DEFINES | grep 'X86_ASM' /dev/null 21) AM_CONDITIONAL(HAVE_X86_64_ASM, echo $DEFINES | grep 'X86_64_ASM' /dev/null 21) @@ -2112,7 +2108,6 @@ AC_CONFIG_FILES([Makefile src/mapi/vgapi/vg.pc src/mesa/Makefile src/mesa/gl.pc - src/mesa/drivers/Makefile src/mesa/drivers/dri/dri.pc src/mesa/drivers/dri/common/Makefile src/mesa/drivers/dri/common/xmlpool/Makefile diff --git a/src/mesa/Makefile.am b/src/mesa/Makefile.am index 14685e7..5850412 100644 --- a/src/mesa/Makefile.am +++ b/src/mesa/Makefile.am @@ -23,7 +23,19 @@ if NEED_LIBDRICORE DRICORE_SUBDIR = libdricore endif -SUBDIRS = program x86 x86-64 . $(DRICORE_SUBDIR) drivers +SUBDIRS = program x86 x86-64 . $(DRICORE_SUBDIR) + +if HAVE_X11_DRIVER +SUBDIRS += drivers/x11 +endif + +if HAVE_DRI +SUBDIRS += drivers/dri +endif + +if HAVE_OSMESA +SUBDIRS += drivers/osmesa +endif gldir = $(includedir)/GL gl_HEADERS = $(top_srcdir)/include/GL/*.h diff --git a/src/mesa/drivers/Makefile.am b/src/mesa/drivers/Makefile.am deleted file mode 100644 index 1bc74ea..000 --- a/src/mesa/drivers/Makefile.am +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright © 2012 Intel Corporation -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the Software), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. - -SUBDIRS = $(DRIVER_DIRS) -- 1.8.1.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 08/12] build: Stop using GALLIUM_STATE_TRACKERS_DIRS for SUBDIRS
configure still uses it to print the enabled state trackers.
Tested-by: Emil Velikov emil.l.veli...@gmail.com
Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com
---
configure.ac | 45 +++
src/gallium/state_trackers/Makefile.am | 65 --
2 files changed, 75 insertions(+), 35 deletions(-)
diff --git a/configure.ac b/configure.ac
index 4421895..80d6eaa 100644
--- a/configure.ac
+++ b/configure.ac
@@ -769,7 +769,6 @@ esac
if test x$enable_dri = xyes; then
GALLIUM_WINSYS_DIRS=$GALLIUM_WINSYS_DIRS sw/dri
GALLIUM_STATE_TRACKERS_DIRS=dri $GALLIUM_STATE_TRACKERS_DIRS
-HAVE_ST_DRI=yes
fi
if test x$enable_osmesa = xyes; then
@@ -779,7 +778,6 @@ fi
AC_SUBST([GALLIUM_TARGET_DIRS])
AC_SUBST([GALLIUM_WINSYS_DIRS])
-AC_SUBST([GALLIUM_STATE_TRACKERS_DIRS])
AC_SUBST([MESA_LLVM])
# Check for libdrm
@@ -1228,14 +1226,14 @@ if test x$enable_gallium_egl = xyes; then
GALLIUM_STATE_TRACKERS_DIRS=egl $GALLIUM_STATE_TRACKERS_DIRS
GALLIUM_TARGET_DIRS=$GALLIUM_TARGET_DIRS egl-static
-HAVE_ST_EGL=yes
fi
+AM_CONDITIONAL(HAVE_GALLIUM_EGL, test x$enable_gallium_egl = xyes)
dnl
dnl gbm Gallium configuration
dnl
if test x$enable_gallium_gbm = xauto; then
-case $enable_gbm$HAVE_ST_EGL$enable_dri$with_egl_platforms in
+case $enable_gbm$enable_gallium_egl$enable_dri$with_egl_platforms in
yesyesyes*drm*)
enable_gallium_gbm=yes ;;
*)
@@ -1256,9 +1254,9 @@ if test x$enable_gallium_gbm = xyes; then
GALLIUM_STATE_TRACKERS_DIRS=gbm $GALLIUM_STATE_TRACKERS_DIRS
GALLIUM_TARGET_DIRS=$GALLIUM_TARGET_DIRS gbm
-HAVE_ST_GBM=yes
enable_gallium_loader=yes
fi
+AM_CONDITIONAL(HAVE_GALLIUM_GBM, test x$enable_gallium_gbm = xyes)
dnl
dnl X.Org DDX configuration
@@ -1271,8 +1269,8 @@ if test x$enable_xorg = xyes; then
HAVE_XEXTPROTO_71=yes; DEFINES=$DEFINES -DHAVE_XEXTPROTO_71,
HAVE_XEXTPROTO_71=no)
GALLIUM_STATE_TRACKERS_DIRS=xorg $GALLIUM_STATE_TRACKERS_DIRS
-HAVE_ST_XORG=yes
fi
+AM_CONDITIONAL(HAVE_ST_XORG, test x$enable_xorg = xyes)
dnl
dnl XA configuration
@@ -1288,11 +1286,11 @@ fi
fi
if test x$enable_xa = xyes; then
GALLIUM_STATE_TRACKERS_DIRS=xa $GALLIUM_STATE_TRACKERS_DIRS
-HAVE_ST_XA=yes
AC_SUBST(AWK)
AC_SUBST(GREP)
AC_SUBST(NM)
fi
+AM_CONDITIONAL(HAVE_ST_XA, test x$enable_xa = xyes)
dnl
dnl OpenVG configuration
@@ -1313,7 +1311,6 @@ if test x$enable_openvg = xyes; then
EGL_CLIENT_APIS=$EGL_CLIENT_APIS '$(VG_LIB)'
VG_LIB_DEPS=$VG_LIB_DEPS $SELINUX_LIBS $PTHREAD_LIBS
GALLIUM_STATE_TRACKERS_DIRS=vega $GALLIUM_STATE_TRACKERS_DIRS
-HAVE_ST_VEGA=yes
VG_PC_LIB_PRIV=-lm $CLOCK_LIB $PTHREAD_LIBS $DLOPEN_LIBS
AC_SUBST([VG_PC_LIB_PRIV])
fi
@@ -1344,14 +1341,14 @@ fi
if test x$enable_xvmc = xyes; then
PKG_CHECK_MODULES([XVMC], [xvmc = 1.0.6 x11-xcb xcb-dri2 = 1.8])
GALLIUM_STATE_TRACKERS_DIRS=$GALLIUM_STATE_TRACKERS_DIRS xvmc
-HAVE_ST_XVMC=yes
fi
+AM_CONDITIONAL(HAVE_ST_XVMC, test x$enable_xvmc = xyes)
if test x$enable_vdpau = xyes; then
PKG_CHECK_MODULES([VDPAU], [vdpau = 0.4.1 x11-xcb xcb-dri2 = 1.8])
GALLIUM_STATE_TRACKERS_DIRS=$GALLIUM_STATE_TRACKERS_DIRS vdpau
-HAVE_ST_VDPAU=yes
fi
+AM_CONDITIONAL(HAVE_ST_VDPAU, test x$enable_vdpau = xyes)
dnl
dnl OpenCL configuration
@@ -1398,6 +1395,7 @@ if test x$enable_opencl = xyes; then
GALLIUM_TARGET_DIRS=$GALLIUM_TARGET_DIRS opencl
enable_gallium_loader=yes
fi
+AM_CONDITIONAL(HAVE_CLOVER, test x$enable_opencl = xyes)
if test x$enable_gallium_gbm = xyes || test x$enable_opencl = xyes; then
GALLIUM_TARGET_DIRS=$GALLIUM_TARGET_DIRS pipe-loader
@@ -1688,28 +1686,28 @@ dnl
dnl Gallium helper functions
dnl
gallium_check_st() {
-if test x$HAVE_ST_DRI = xyes || test x$HAVE_ST_XORG = xyes ||
-test x$HAVE_ST_XA = xyes || test x$HAVE_ST_XVMC = xyes ||
-test x$HAVE_ST_VDPAU = xyes; then
+if test x$enable_dri = xyes -o x$enable_xorg = xyes -o \
+x$enable_xa = xyes -o x$enable_xvmc = xyes -o \
+x$enable_vdpau = xyes; then
if test x$have_libdrm != xyes; then
AC_MSG_ERROR([DRI or Xorg DDX requires libdrm = $LIBDRM_REQUIRED])
fi
GALLIUM_WINSYS_DIRS=$GALLIUM_WINSYS_DIRS $1
fi
-if test x$HAVE_ST_DRI = xyes test x$2 != x; then
+if test x$enable_dri = xyes test x$2 != x; then
GALLIUM_TARGET_DIRS=$GALLIUM_TARGET_DIRS $2
HAVE_COMMON_DRI=yes
fi
-if test x$HAVE_ST_XORG = xyes test x$3 != x; then
+if test x$enable_xorg = xyes test x$3 != x; then
GALLIUM_TARGET_DIRS=$GALLIUM_TARGET_DIRS $3
fi
-if test x$HAVE_ST_XA = xyes test x$4 != x; then
+if test x$enable_xa = xyes test x$4 != x; then
GALLIUM_TARGET_DIRS=$GALLIUM_TARGET_DIRS $4
fi
-if test x$HAVE_ST_XVMC = xyes test x$5 != x; then
+if test
[Mesa-dev] [PATCH 09/12] build: Get rid of GALLIUM_MAKE_DIRS
Tested-by: Emil Velikov emil.l.veli...@gmail.com Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com --- Since last time: - Rebase and add freedreno. configure.ac| 31 +++ src/gallium/drivers/Makefile.am | 84 - src/gallium/targets/pipe-loader/Makefile.am | 6 +-- 3 files changed, 78 insertions(+), 43 deletions(-) diff --git a/configure.ac b/configure.ac index 80d6eaa..588aab5 100644 --- a/configure.ac +++ b/configure.ac @@ -1897,6 +1897,13 @@ AM_CONDITIONAL(HAVE_GALLIUM_FREEDRENO, test x$HAVE_GALLIUM_FREEDRENO = xyes) AM_CONDITIONAL(HAVE_GALLIUM_SOFTPIPE, test x$HAVE_GALLIUM_SOFTPIPE = xyes) AM_CONDITIONAL(HAVE_GALLIUM_LLVMPIPE, test x$HAVE_GALLIUM_LLVMPIPE = xyes) +AM_CONDITIONAL(NEED_GALLIUM_SOFTPIPE_DRIVER, test x$HAVE_GALLIUM_SVGA = xyes -o \ + x$HAVE_GALLIUM_I915 = xyes -o \ + x$HAVE_GALLIUM_SOFTPIPE = xyes) +AM_CONDITIONAL(NEED_GALLIUM_LLVMPIPE_DRIVER, test x$HAVE_GALLIUM_I915 = xyes -o \ + x$HAVE_GALLIUM_SOFTPIPE = xyes -a \ + x$MESA_LLVM = x1) + if test x$enable_gallium_loader = xyes; then GALLIUM_WINSYS_DIRS=$GALLIUM_WINSYS_DIRS sw/null GALLIUM_PIPE_LOADER_DEFINES=-DHAVE_PIPE_LOADER_SW @@ -1922,24 +1929,6 @@ if test x$enable_gallium_loader = xyes; then AC_SUBST([GALLIUM_PIPE_LOADER_LIBS]) fi -dnl Tell Automake which drivers to build -for driver in $GALLIUM_DRIVERS_DIRS; do -case x$driver in -xgalahad) -HAVE_GALAHAD_GALLIUM=yes; - ;; - xidentity) - HAVE_IDENTITY_GALLIUM=yes; - ;; - xnoop) - HAVE_NOOP_GALLIUM=yes; - ;; -*) -GALLIUM_MAKE_DIRS=$GALLIUM_MAKE_DIRS $driver - ;; -esac -done - AM_CONDITIONAL(HAVE_I915_DRI, test x$HAVE_I915_DRI = xyes) AM_CONDITIONAL(HAVE_I965_DRI, test x$HAVE_I965_DRI = xyes) AM_CONDITIONAL(HAVE_NOUVEAU_DRI, test x$HAVE_NOUVEAU_DRI = xyes) @@ -1948,9 +1937,6 @@ AM_CONDITIONAL(HAVE_RADEON_DRI, test x$HAVE_RADEON_DRI = xyes) AM_CONDITIONAL(HAVE_SWRAST_DRI, test x$HAVE_SWRAST_DRI = xyes) AM_CONDITIONAL(HAVE_COMMON_DRI, test x$HAVE_COMMON_DRI = xyes) -AM_CONDITIONAL(HAVE_GALAHAD_GALLIUM, test x$HAVE_GALAHAD_GALLIUM = xyes) -AM_CONDITIONAL(HAVE_IDENTITY_GALLIUM, test x$HAVE_IDENTITY_GALLIUM = xyes) -AM_CONDITIONAL(HAVE_NOOP_GALLIUM, test x$HAVE_NOOP_GALLIUM = xyes) AM_CONDITIONAL(NEED_RADEON_LLVM, test x$NEED_RADEON_LLVM = xyes) AM_CONDITIONAL(R600_NEED_RADEON_GALLIUM, test x$R600_NEED_RADEON_GALLIUM = xyes) AM_CONDITIONAL(USE_R600_LLVM_COMPILER, test x$USE_R600_LLVM_COMPILER = xyes) @@ -1960,8 +1946,6 @@ AM_CONDITIONAL(HAVE_GALLIUM_COMPUTE, test x$enable_opencl = xyes) AM_CONDITIONAL(HAVE_MESA_LLVM, test x$MESA_LLVM = x1) AM_CONDITIONAL(LLVM_NEEDS_FNORTTI, test $LLVM_VERSION_INT -ge 302) -AC_SUBST([GALLIUM_MAKE_DIRS]) - AM_CONDITIONAL(NEED_LIBPROGRAM, test x$with_gallium_drivers != x -o \ x$enable_xlib_glx = xyes -o \ x$enable_osmesa = xyes) @@ -2129,7 +2113,6 @@ dnl Sort the dirs alphabetically GALLIUM_TARGET_DIRS=`echo $GALLIUM_TARGET_DIRS|tr \n|sort -u|tr \n ` GALLIUM_WINSYS_DIRS=`echo $GALLIUM_WINSYS_DIRS|tr \n|sort -u|tr \n ` GALLIUM_DRIVERS_DIRS=`echo $GALLIUM_DRIVERS_DIRS|tr \n|sort -u|tr \n ` -GALLIUM_MAKE_DIRS=`echo $GALLIUM_MAKE_DIRS|tr \n|sort -u|tr \n ` GALLIUM_STATE_TRACKERS_DIRS=`echo $GALLIUM_STATE_TRACKERS_DIRS|tr \n|sort -u|tr \n ` AC_OUTPUT diff --git a/src/gallium/drivers/Makefile.am b/src/gallium/drivers/Makefile.am index c4dc6bf..25c680a 100644 --- a/src/gallium/drivers/Makefile.am +++ b/src/gallium/drivers/Makefile.am @@ -11,12 +11,10 @@ AM_CFLAGS = $(VISIBILITY_CFLAGS) noinst_LTLIBRARIES = -SUBDIRS = . +SUBDIRS = . trace rbug -if HAVE_GALAHAD_GALLIUM - noinst_LTLIBRARIES += galahad/libgalahad.la galahad_libgalahad_la_SOURCES = \ @@ -24,12 +22,8 @@ galahad_libgalahad_la_SOURCES = \ galahad/glhd_context.c \ galahad/glhd_screen.c -endif - -if HAVE_IDENTITY_GALLIUM - noinst_LTLIBRARIES += identity/libidentity.la identity_libidentity_la_SOURCES = \ @@ -37,12 +31,8 @@ identity_libidentity_la_SOURCES = \ identity/id_context.c \ identity/id_screen.c -endif - -if HAVE_NOOP_GALLIUM - # Meta-driver which combines whichever software rasterizers have been # built into a single convenience library. @@ -52,8 +42,6 @@ noop_libnoop_la_SOURCES = \ noop/noop_pipe.c \ noop/noop_state.c -endif -
[Mesa-dev] [PATCH 10/12] build: Build pipe-loader before gallium tests
And don't build it from other Makefiles. That's awful, and breaks distclean. Tested-by: Emil Velikov emil.l.veli...@gmail.com Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com --- configure.ac | 8 src/gallium/targets/opencl/Makefile.am | 3 --- src/gallium/tests/trivial/Makefile.am | 4 3 files changed, 4 insertions(+), 11 deletions(-) diff --git a/configure.ac b/configure.ac index 588aab5..8c9ca58 100644 --- a/configure.ac +++ b/configure.ac @@ -1397,10 +1397,6 @@ if test x$enable_opencl = xyes; then fi AM_CONDITIONAL(HAVE_CLOVER, test x$enable_opencl = xyes) -if test x$enable_gallium_gbm = xyes || test x$enable_opencl = xyes; then -GALLIUM_TARGET_DIRS=$GALLIUM_TARGET_DIRS pipe-loader -fi - dnl dnl Gallium configuration dnl @@ -1666,6 +1662,10 @@ if test x$enable_gallium_tests = xyes; then fi AM_CONDITIONAL(HAVE_GALLIUM_TESTS, test x$enable_gallium_tests = xyes) +if test x$enable_gallium_loader = xyes; then +GALLIUM_TARGET_DIRS=$GALLIUM_TARGET_DIRS pipe-loader +fi + dnl Directory for VDPAU libs AC_ARG_WITH([vdpau-libdir], [AS_HELP_STRING([--with-vdpau-libdir=DIR], diff --git a/src/gallium/targets/opencl/Makefile.am b/src/gallium/targets/opencl/Makefile.am index 810f9bb..4b77d0a 100644 --- a/src/gallium/targets/opencl/Makefile.am +++ b/src/gallium/targets/opencl/Makefile.am @@ -32,11 +32,8 @@ libOpenCL_la_SOURCES = # Force usage of a C++ linker nodist_EXTRA_libOpenCL_la_SOURCES = dummy.cpp -PIPE_BUILD_DIR = $(top_builddir)/src/gallium/targets/pipe-loader - # Provide compatibility with scripts for the old Mesa build system for # a while by putting a link to the driver into /lib of the build tree. all-local: libOpenCL.la - @$(MAKE) -C $(PIPE_BUILD_DIR) $(MKDIR_P) $(top_builddir)/$(LIB_DIR) ln -f .libs/libOpenCL.so* $(top_builddir)/$(LIB_DIR)/ diff --git a/src/gallium/tests/trivial/Makefile.am b/src/gallium/tests/trivial/Makefile.am index e6e9ae7..705a878 100644 --- a/src/gallium/tests/trivial/Makefile.am +++ b/src/gallium/tests/trivial/Makefile.am @@ -26,9 +26,5 @@ tri_SOURCES = tri.c quad_tex_SOURCES = quad-tex.c -all-local: - @$(MAKE) -C $(PIPE_SRC_DIR) - clean-local: - @$(MAKE) -C $(PIPE_SRC_DIR) clean -rm -f result.bmp -- 1.8.1.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 11/12] build: Get rid of GALLIUM_TARGET_DIRS
configure still uses it to print the enabled targets. Tested-by: Emil Velikov emil.l.veli...@gmail.com Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com --- Since last time: - Rebase and add freedreno. configure.ac| 2 +- src/gallium/targets/Makefile.am | 152 +++- 2 files changed, 152 insertions(+), 2 deletions(-) diff --git a/configure.ac b/configure.ac index 8c9ca58..c17d191 100644 --- a/configure.ac +++ b/configure.ac @@ -776,7 +776,6 @@ if test x$enable_osmesa = xyes; then GALLIUM_TARGET_DIRS=$GALLIUM_TARGET_DIRS osmesa fi -AC_SUBST([GALLIUM_TARGET_DIRS]) AC_SUBST([GALLIUM_WINSYS_DIRS]) AC_SUBST([MESA_LLVM]) @@ -1665,6 +1664,7 @@ AM_CONDITIONAL(HAVE_GALLIUM_TESTS, test x$enable_gallium_tests = xyes) if test x$enable_gallium_loader = xyes; then GALLIUM_TARGET_DIRS=$GALLIUM_TARGET_DIRS pipe-loader fi +AM_CONDITIONAL(NEED_GALLIUM_LOADER, test x$enable_gallium_loader = xyes) dnl Directory for VDPAU libs AC_ARG_WITH([vdpau-libdir], diff --git a/src/gallium/targets/Makefile.am b/src/gallium/targets/Makefile.am index deeefbe..b3e9cbc 100644 --- a/src/gallium/targets/Makefile.am +++ b/src/gallium/targets/Makefile.am @@ -1 +1,151 @@ -SUBDIRS = $(GALLIUM_TARGET_DIRS) +# Copyright © 2013 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the Software), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, +# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +# HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +SUBDIRS = + +if HAVE_X11_DRIVER +SUBDIRS += libgl-xlib +endif + +if HAVE_OSMESA +SUBDIRS += osmesa +endif + +if HAVE_GALLIUM_GBM +SUBDIRS += gbm +endif + +if HAVE_CLOVER +SUBDIRS += opencl +endif + +if HAVE_GALLIUM_SVGA +if HAVE_DRI +SUBDIRS += dri-vmwgfx +endif + +if HAVE_ST_XA +SUBDIRS += xa-vmwgfx +endif +endif + +if HAVE_GALLIUM_FREEDRENO +if HAVE_DRI +SUBDIRS += dri-freedreno +endif +endif + +if HAVE_GALLIUM_I915 +if HAVE_DRI +SUBDIRS += dri-i915 +endif + +if HAVE_ST_XORG +SUBDIRS += xorg-i915 +endif +endif + +if HAVE_GALLIUM_R300 +if HAVE_DRI +SUBDIRS += dri-r300 +endif + +if HAVE_ST_XVMC +SUBDIRS += xvmc-r300 +endif + +if HAVE_ST_VDPAU +SUBDIRS += vdpau-r300 +endif +endif + +if HAVE_GALLIUM_R600 +if HAVE_DRI +SUBDIRS += dri-r600 +endif + +if HAVE_ST_XORG +SUBDIRS += xorg-r600 +endif + +if HAVE_ST_XVMC +SUBDIRS += xvmc-r600 +endif + +if HAVE_ST_VDPAU +SUBDIRS += vdpau-r600 +endif +endif + +if HAVE_GALLIUM_RADEONSI +if HAVE_DRI +SUBDIRS += dri-radeonsi +endif + +if HAVE_ST_XORG +SUBDIRS += xorg-radeonsi +endif + +if HAVE_ST_VDPAU +SUBDIRS += vdpau-radeonsi +endif +endif + +if HAVE_GALLIUM_NOUVEAU +if HAVE_DRI +SUBDIRS += dri-nouveau +endif + +if HAVE_ST_XORG +SUBDIRS += xorg-nouveau +endif + +if HAVE_ST_XVMC +SUBDIRS += xvmc-nouveau +endif + +if HAVE_ST_VDPAU +SUBDIRS += vdpau-nouveau +endif +endif + +if HAVE_GALLIUM_SOFTPIPE +if HAVE_DRI +SUBDIRS += dri-swrast +endif + +if HAVE_ST_XVMC +SUBDIRS += xvmc-softpipe +endif + +if HAVE_ST_VDPAU +SUBDIRS += vdpau-softpipe +endif +endif + +if NEED_GALLIUM_LOADER +SUBDIRS += pipe-loader +endif + +if HAVE_GALLIUM_EGL +SUBDIRS += egl-static +endif -- 1.8.1.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 12/12] build: Get rid of GALLIUM_WINSYS_DIRS
configure still uses it to print the enabled winsys.
Tested-by: Emil Velikov emil.l.veli...@gmail.com
Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com
---
Since last time:
- Rebase and add freedreno.
configure.ac | 38 +-
src/gallium/winsys/Makefile.am| 66 ++-
src/gallium/winsys/sw/Makefile.am | 37 --
3 files changed, 88 insertions(+), 53 deletions(-)
delete mode 100644 src/gallium/winsys/sw/Makefile.am
diff --git a/configure.ac b/configure.ac
index c17d191..518edbb 100644
--- a/configure.ac
+++ b/configure.ac
@@ -762,7 +762,7 @@ xyesyes)
GALLIUM_WINSYS_DIRS=$GALLIUM_WINSYS_DIRS sw/xlib
GALLIUM_TARGET_DIRS=$GALLIUM_TARGET_DIRS libgl-xlib
GALLIUM_STATE_TRACKERS_DIRS=glx $GALLIUM_STATE_TRACKERS_DIRS
-HAVE_WINSYS_XLIB=yes
+NEED_WINSYS_XLIB=yes
;;
esac
@@ -776,7 +776,6 @@ if test x$enable_osmesa = xyes; then
GALLIUM_TARGET_DIRS=$GALLIUM_TARGET_DIRS osmesa
fi
-AC_SUBST([GALLIUM_WINSYS_DIRS])
AC_SUBST([MESA_LLVM])
# Check for libdrm
@@ -1445,10 +1444,6 @@ fi
egl_platforms=`IFS=', '; echo $with_egl_platforms`
for plat in $egl_platforms; do
case $plat in
- fbdev|null)
- GALLIUM_WINSYS_DIRS=$GALLIUM_WINSYS_DIRS sw/$plat
- ;;
-
wayland)
PKG_CHECK_MODULES([WAYLAND], [wayland-client = 1.0.2
wayland-server = 1.0.2])
GALLIUM_WINSYS_DIRS=$GALLIUM_WINSYS_DIRS sw/wayland
@@ -1471,7 +1466,7 @@ for plat in $egl_platforms; do
AC_MSG_ERROR([EGL platform drm needs gbm])
;;
- android|gdi)
+ android|fbdev|gdi|null)
;;
*)
@@ -1496,6 +1491,9 @@ fi
EGL_PLATFORMS=$egl_platforms
+if echo $egl_platforms | grep 'x11' /dev/null 21; then
+NEED_WINSYS_XLIB=yes
+fi
AM_CONDITIONAL(HAVE_EGL_PLATFORM_X11, echo $egl_platforms | grep 'x11'
/dev/null 21)
AM_CONDITIONAL(HAVE_EGL_PLATFORM_WAYLAND, echo $egl_platforms | grep
'wayland' /dev/null 21)
AM_CONDITIONAL(HAVE_EGL_PLATFORM_DRM, echo $egl_platforms | grep 'drm'
/dev/null 21)
@@ -1686,9 +1684,7 @@ dnl
dnl Gallium helper functions
dnl
gallium_check_st() {
-if test x$enable_dri = xyes -o x$enable_xorg = xyes -o \
-x$enable_xa = xyes -o x$enable_xvmc = xyes -o \
-x$enable_vdpau = xyes; then
+if test x$NEED_NONNULL_WINSYS = xyes; then
if test x$have_libdrm != xyes; then
AC_MSG_ERROR([DRI or Xorg DDX requires libdrm = $LIBDRM_REQUIRED])
fi
@@ -1747,6 +1743,13 @@ radeon_llvm_check() {
}
dnl Gallium drivers
+if test x$enable_dri = xyes -o x$enable_xorg = xyes -o \
+x$enable_xa = xyes -o x$enable_xvmc = xyes -o \
+x$enable_vdpau = xyes; then
+NEED_NONNULL_WINSYS=yes
+fi
+AM_CONDITIONAL(NEED_NONNULL_WINSYS, test x$NEED_NONNULL_WINSYS = xyes)
+
dnl Duplicates in GALLIUM_DRIVERS_DIRS are removed by sorting it after this
block
if test x$with_gallium_drivers != x; then
gallium_drivers=`IFS=', '; echo $with_gallium_drivers`
@@ -1832,9 +1835,8 @@ if test x$with_gallium_drivers != x; then
GALLIUM_TARGET_DIRS=$GALLIUM_TARGET_DIRS xvmc-softpipe
fi
if test x$enable_vdpau = xyes -o x$enable_xvmc = xyes; then
- if test x$HAVE_WINSYS_XLIB != xyes; then
- GALLIUM_WINSYS_DIRS=$GALLIUM_WINSYS_DIRS sw/xlib
- fi
+NEED_WINSYS_XLIB=yes
+GALLIUM_WINSYS_DIRS=$GALLIUM_WINSYS_DIRS sw/xlib
fi
;;
*)
@@ -1910,7 +1912,7 @@ if test x$enable_gallium_loader = xyes; then
GALLIUM_PIPE_LOADER_LIBS=\$(top_builddir)/src/gallium/auxiliary/pipe-loader/libpipe_loader.la
GALLIUM_PIPE_LOADER_LIBS=$GALLIUM_PIPE_LOADER_LIBS
\$(top_builddir)/src/gallium/winsys/sw/null/libws_null.la
-if test x$HAVE_WINSYS_XLIB = xyes; then
+if test x$NEED_WINSYS_XLIB = xyes; then
GALLIUM_PIPE_LOADER_DEFINES=$GALLIUM_PIPE_LOADER_DEFINES
-DHAVE_PIPE_LOADER_XLIB
GALLIUM_PIPE_LOADER_LIBS=$GALLIUM_PIPE_LOADER_LIBS
\$(top_builddir)/src/gallium/winsys/sw/xlib/libws_xlib.la
fi
@@ -1937,6 +1939,13 @@ AM_CONDITIONAL(HAVE_RADEON_DRI, test x$HAVE_RADEON_DRI =
xyes)
AM_CONDITIONAL(HAVE_SWRAST_DRI, test x$HAVE_SWRAST_DRI = xyes)
AM_CONDITIONAL(HAVE_COMMON_DRI, test x$HAVE_COMMON_DRI = xyes)
+AM_CONDITIONAL(NEED_RADEON_DRM_WINSYS, test x$NEED_NONNULL_WINSYS = xyes -a \
+x$HAVE_GALLIUM_R300 = xyes -o \
+x$HAVE_GALLIUM_R600 = xyes -o \
+x$HAVE_GALLIUM_RADEONSI = xyes)
+AM_CONDITIONAL(NEED_WINSYS_WRAPPER, test x$HAVE_GALLIUM_I915 = xyes -o \
+ x$HAVE_GALLIUM_SVGA = xyes)
+AM_CONDITIONAL(NEED_WINSYS_XLIB, test x$NEED_WINSYS_XLIB = xyes)
Re: [Mesa-dev] [PATCH 01/12] build: Rename sources.mak - Makefile.sources
On Thu, Apr 11, 2013 at 11:35 PM, Jordan Justen jljus...@gmail.com wrote: Assuming this matched your make-dist-1 branch, It does. Series Reviewed-by: Jordan Justen jordan.l.jus...@intel.com Thanks! ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 01/12] build: Rename sources.mak - Makefile.sources
On Thu, Apr 11, 2013 at 4:29 PM, Matt Turner matts...@gmail.com wrote: For the sake of consistency. Tested-by: Emil Velikov emil.l.veli...@gmail.com Reviewed-and-Tested-by: Andreas Boll andreas.boll@gmail.com --- Chad Jose, Could you test the first two patches of this series with the Android and scons build systems? I've tried to make the proper changes to both build systems. Branch available at git://people.freedesktop.org/~mattst88/mesa make-dist-1 Thanks, Matt ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] i965: Implement work-around for CMP with null dest on Haswell.
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 2578bf8..704f219 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -1653,6 +1653,7 @@ void brw_CMP(struct brw_compile *p,
struct brw_reg src0,
struct brw_reg src1)
{
+ struct intel_context *intel = p-brw-intel;
struct brw_instruction *insn = next_insn(p, BRW_OPCODE_CMP);
insn-header.destreg__conditionalmod = conditional;
@@ -1672,6 +1673,17 @@ void brw_CMP(struct brw_compile *p,
p-current-header.predicate_control = BRW_PREDICATE_NORMAL;
p-flag_value = 0xff;
}
+
+ /* Item WaCMPInstNullDstForcesThreadSwitch in the Haswell Bspec workarounds
+* page says:
+*Any CMP instruction with a null destination must use a {switch}.
+*/
+ if (intel-is_haswell) {
+ if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE
+ dest.nr == BRW_ARF_NULL) {
+ insn-header.thread_control = BRW_THREAD_SWITCH;
+ }
+ }
}
/* Issue 'wait' instruction for n1, host could program MMIO
--
1.7.8.6
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[Mesa-dev] [PATCH 2/2] i965: Check reg.nr for BRW_ARF_NULL instead of reg.file.
--- src/mesa/drivers/dri/i965/brw_eu_emit.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 704f219..a98892b 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -182,7 +182,7 @@ validate_reg(struct brw_instruction *insn, struct brw_reg reg) } if (reg.file == BRW_ARCHITECTURE_REGISTER_FILE - reg.file == BRW_ARF_NULL) + reg.nr == BRW_ARF_NULL) return; assert(reg.hstride = 0 reg.hstride Elements(hstride_for_reg)); -- 1.7.8.6 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] Small build issue with libdrm under home since uvd commit.
On Tue, Apr 16, 2013 at 2:54 AM, Andy Furniss andy...@ukfsn.org wrote: On one of my builds I have libdrm/mesa/xorg living under my home, normally I can build mesa by setting LDFLAGS and --prefix= but since the uvd commit I get - Making all in radeon make[3]: Entering directory `/mnt/sdb1/Src/Mesa-git/mesa/src/gallium/drivers/radeon' CC radeon_uvd.lo In file included from radeon_uvd.c:48:0: ../../winsys/radeon/drm/radeon_winsys.h:44:35: fatal error: libdrm/radeon_surface.h: No such file or directory compilation terminated. I can work around by setting CPPFLAGS but in the (distant) past this has proven to be problematic if some internal header gets updated as the now too old installed header gets used. Looks like it's simply because LIBDRM_CFLAGS or RADEON_CFLAGS aren't in AM_CFLAGS. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] new i965g pipe driver for Intel GEN6 (and later)
On Tue, Apr 16, 2013 at 9:45 AM, Chia-I Wu olva...@gmail.com wrote: If there is no objection, I'd like to merge it in a day or two. My only objection is over adding a driver that is explicitly a toy, the confusion it will cause users, and the developer time it will waste. It wasn't uncommon for a user to waste a nontrivial amount of someone's time in #intel-gfx only to discover that they were trying to use the (old) i965g driver that no one maintained. I think everything Marek said was correct. If you could extend Gallium to consume GLSL IR it might actually be an interesting project. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] new i965g pipe driver for Intel GEN6 (and later)
On Tue, Apr 16, 2013 at 10:18 AM, Kenneth Graunke kenn...@whitecape.org wrote: On 04/16/2013 09:58 AM, Matt Turner wrote: On Tue, Apr 16, 2013 at 9:45 AM, Chia-I Wu olva...@gmail.com wrote: If there is no objection, I'd like to merge it in a day or two. My only objection is over adding a driver that is explicitly a toy, the confusion it will cause users, and the developer time it will waste. It wasn't uncommon for a user to waste a nontrivial amount of someone's time in #intel-gfx only to discover that they were trying to use the (old) i965g driver that no one maintained. That's very true. I wonder, should i965g be built by default? Or should you have to explicitly request it via --with-gallium-drivers=i965? The thinking is that the default should be to build the drivers most people want to use. The old i965g driver wasn't built by default. It still caused confusion and wasted time. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] new i965g pipe driver for Intel GEN6 (and later)
On Tue, Apr 16, 2013 at 10:35 AM, Michael Karcher michael.karc...@fu-berlin.de wrote: I suspect there might be a comparable need for a i965g driver, as that chip has no vertex shader hardware. This isn't true. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] intel: Add a null pointer check before dereferencing the pointer
On Tue, Apr 16, 2013 at 11:11 AM, Anuj Phogat anuj.pho...@gmail.com wrote:
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/intel/intel_screen.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c
b/src/mesa/drivers/dri/intel/intel_screen.c
index 16750f2..27b992c 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -707,6 +707,9 @@ intel_from_planar(__DRIimage *parent, int plane, void
*loaderPrivate)
stride = parent-strides[index];
image = intel_allocate_image(dri_format, loaderPrivate);
+if (image == NULL)
+ return NULL;
+
if (offset + height * stride parent-region-bo-size) {
_mesa_warning(NULL, intel_create_sub_image: subimage out of bounds);
free(image);
--
1.8.1.4
There is another place in the same file that the return value of
intel_allocate_image isn't checked. Should probably add a check there
while you're fixing this.
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Re: [Mesa-dev] [PATCH V2] intel: Add a null pointer check before dereferencing the pointer
On Tue, Apr 16, 2013 at 4:13 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/intel/intel_screen.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c
b/src/mesa/drivers/dri/intel/intel_screen.c
index 16750f2..00e7bc6 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -368,6 +368,9 @@ intel_create_image_from_name(__DRIscreen *screen,
int cpp;
image = intel_allocate_image(format, loaderPrivate);
+if (image == NULL)
+ return NULL;
+
if (image-format == MESA_FORMAT_NONE)
cpp = 1;
else
@@ -504,6 +507,9 @@ intel_create_image(__DRIscreen *screen,
}
image = intel_allocate_image(format, loaderPrivate);
+ if (image == NULL)
+ return NULL;
+
cpp = _mesa_get_format_bytes(image-format);
image-region =
intel_region_alloc(intelScreen, tiling, cpp, width, height, true);
@@ -707,6 +713,9 @@ intel_from_planar(__DRIimage *parent, int plane, void
*loaderPrivate)
stride = parent-strides[index];
image = intel_allocate_image(dri_format, loaderPrivate);
+if (image == NULL)
+ return NULL;
+
if (offset + height * stride parent-region-bo-size) {
_mesa_warning(NULL, intel_create_sub_image: subimage out of bounds);
free(image);
--
1.8.1.4
Reviewed-by: Matt Turner matts...@gmail.com
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Re: [Mesa-dev] [PATCH] docs: update release notes for 9.2
On Wed, Apr 17, 2013 at 8:27 AM, Andreas Boll andreas.boll@gmail.com wrote: --- docs/relnotes/9.2.html | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/docs/relnotes/9.2.html b/docs/relnotes/9.2.html index ec9cc47..0dcc960 100644 --- a/docs/relnotes/9.2.html +++ b/docs/relnotes/9.2.html @@ -44,8 +44,13 @@ Note: some of the new features are only available with certain drivers. /p ul -liOSMesa interface for gallium llvmpipe/softpipe drivers -liGallium Heads-Up Display (HUD) feature for performance monitoring +liGL_ARB_texture_buffer_range/li +liGL_ARB_texture_multisample/li +liGL_ARB_texture_storage_multisample/li +liGL_ARB_texture_query_lod/li +liAdded new freedreno gallium driver/li +liOSMesa interface for gallium llvmpipe/softpipe drivers/li +liGallium Heads-Up Display (HUD) feature for performance monitoring/li /ul @@ -57,7 +62,7 @@ Note: some of the new features are only available with certain drivers. h2Changes/h2 ul -tbd +liRemoved d3d1x state tracker (unused, unmaintained and broken)/li /ul /div -- 1.7.10.4 Reviewed-by: Matt Turner matts...@gmail.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] autoconf: enable detection of vdpau and xvmc by default
On Wed, Apr 17, 2013 at 6:07 PM, Emil Velikov emil.l.veli...@gmail.com wrote: On 18/04/13 01:55, Emil Velikov wrote: On 18/04/13 01:21, Paul Berry wrote: On 12 April 2013 01:26, Christian König deathsim...@vodafone.de wrote: From: Christian König christian.koe...@amd.com Since we now have UVD support we should enable them by default. Signed-off-by: Christian König christian.koe...@amd.com Those of us who don't build Gallium now need to add --disable-gallium-g3dvl to our configure parameters, or the build fails with the error message configure: error: cannot enable G3DVL without Gallium. Is it possible to change this so that the default is if building gallium, enable g3dvl, else disable g3dvl? The attached patch should change the behaviour from always enable to enable if building gallium. Please review/test Btw, I do not have commit access, so feel free to commit Emil Pardon, the patch had a stray -a. Corrected and tested version is attached Emil Thanks. I removed the $ from the beginning of the assignment to enable_gallium_g3dvl and committed it. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] configure.ac: Remove gallium-g3dvl flag.
It's next to useless, since it just allows you to turn off VDPAU and XvMC with a single switch. Just check whether Gallium drivers are enabled instead. --- configure.ac | 17 + 1 files changed, 1 insertions(+), 16 deletions(-) diff --git a/configure.ac b/configure.ac index 70c598e..8266cb7 100644 --- a/configure.ac +++ b/configure.ac @@ -1317,22 +1317,7 @@ AM_CONDITIONAL(HAVE_OPENVG, test x$enable_openvg = xyes) dnl dnl Gallium G3DVL configuration dnl -AC_ARG_ENABLE([gallium-g3dvl], -[AS_HELP_STRING([--disable-gallium-g3dvl], -[build gallium g3dvl @:@default=auto@:@])], -[enable_gallium_g3dvl=$enableval], -[enable_gallium_g3dvl=auto]) -if test x$enable_gallium_g3dvl = xauto; then -if test x$with_gallium_drivers != x; then -enable_gallium_g3dvl=yes -fi -fi - -if test x$enable_gallium_g3dvl = xyes; then -if test x$with_gallium_drivers = x; then -AC_MSG_ERROR([cannot enable G3DVL without Gallium]) -fi - +if test -n $with_gallium_drivers; then if test x$enable_xvmc = xauto; then PKG_CHECK_EXISTS([xvmc], [enable_xvmc=yes], [enable_xvmc=no]) fi -- 1.7.8.6 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 6/6] build: remove unused API_DEFINES
$(top_builddir)/src/mapi \ -I$(top_srcdir)/src/mesa/ \ - $(DEFINES) \ - $(API_DEFINES) + $(DEFINES) AM_CFLAGS = $(PTHREAD_CFLAGS) \ $(VISIBILITY_CFLAGS) AM_CXXFLAGS = $(PTHREAD_CFLAGS) \ diff --git a/src/mesa/drivers/x11/Makefile.am b/src/mesa/drivers/x11/Makefile.am index 2b0a163..32bd385 100644 --- a/src/mesa/drivers/x11/Makefile.am +++ b/src/mesa/drivers/x11/Makefile.am @@ -29,7 +29,6 @@ AM_CPPFLAGS = \ -I$(top_srcdir)/src/mesa \ -I$(top_srcdir)/src/mesa/main \ $(X11_INCLUDES) \ - $(API_DEFINES) \ $(DEFINES) if HAVE_X11_DRIVER diff --git a/src/mesa/libdricore/Makefile.am b/src/mesa/libdricore/Makefile.am index dce5170..56ceeb7 100644 --- a/src/mesa/libdricore/Makefile.am +++ b/src/mesa/libdricore/Makefile.am @@ -28,7 +28,6 @@ noinst_PROGRAMS = AM_CPPFLAGS = \ $(INCLUDE_DIRS) \ - $(API_DEFINES) \ $(DEFINES) \ -DUSE_DRICORE diff --git a/src/mesa/main/tests/Makefile.am b/src/mesa/main/tests/Makefile.am index 4acc815..87262d5 100644 --- a/src/mesa/main/tests/Makefile.am +++ b/src/mesa/main/tests/Makefile.am @@ -8,7 +8,7 @@ AM_CPPFLAGS = \ -I$(top_srcdir)/src/mapi \ -I$(top_srcdir)/src/mesa \ -I$(top_srcdir)/include \ - $(API_DEFINES) $(DEFINES) $(INCLUDE_DIRS) + $(DEFINES) $(INCLUDE_DIRS) TESTS = main-test check_PROGRAMS = main-test diff --git a/src/mesa/main/tests/hash_table/Makefile.am b/src/mesa/main/tests/hash_table/Makefile.am index f63841d..0330ebb 100644 --- a/src/mesa/main/tests/hash_table/Makefile.am +++ b/src/mesa/main/tests/hash_table/Makefile.am @@ -21,7 +21,7 @@ AM_CPPFLAGS = \ -I$(top_srcdir)/include \ -I$(top_srcdir)/src/mesa/main \ - $(API_DEFINES) $(DEFINES) $(INCLUDE_DIRS) + $(DEFINES) $(INCLUDE_DIRS) LDADD = \ $(top_builddir)/src/mesa/libmesa.la \ diff --git a/src/mesa/program/Makefile.am b/src/mesa/program/Makefile.am index b0e9eff..ab565e2 100644 --- a/src/mesa/program/Makefile.am +++ b/src/mesa/program/Makefile.am @@ -21,7 +21,7 @@ include ../Makefile.sources -AM_CPPFLAGS = $(API_DEFINES) $(DEFINES) $(INCLUDE_DIRS) +AM_CPPFLAGS = $(DEFINES) $(INCLUDE_DIRS) AM_CFLAGS = $(VISIBILITY_CFLAGS) AM_CXXFLAGS = $(VISIBILITY_CXXFLAGS) libdricore_program_la_CFLAGS = $(NOVISIBILITY_CFLAGS) diff --git a/src/mesa/x86-64/Makefile.am b/src/mesa/x86-64/Makefile.am index baeb4b6..80e7917 100644 --- a/src/mesa/x86-64/Makefile.am +++ b/src/mesa/x86-64/Makefile.am @@ -25,7 +25,6 @@ AM_CPPFLAGS = \ -I$(top_srcdir)/include \ -I$(top_srcdir)/src/mesa \ -I$(top_srcdir)/src/mapi \ - $(API_DEFINES) \ $(DEFINES) noinst_PROGRAMS = gen_matypes diff --git a/src/mesa/x86/Makefile.am b/src/mesa/x86/Makefile.am index 5976bb4..21ce360 100644 --- a/src/mesa/x86/Makefile.am +++ b/src/mesa/x86/Makefile.am @@ -25,7 +25,6 @@ AM_CPPFLAGS = \ -I$(top_srcdir)/include \ -I$(top_srcdir)/src/mesa \ -I$(top_srcdir)/src/mapi \ - $(API_DEFINES) \ $(DEFINES) noinst_PROGRAMS = gen_matypes -- 1.7.10.4 Series is Reviewed-by: Matt Turner matts...@gmail.com There's an instance of IN_DRI_DRIVER in a scons file that I didn't see removed. May want to remove it too. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] i965/fs: Don't save value returned by emit() if it's not used.
Probably a copy-n-paste mistake. --- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 422816d..f1539d5 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -521,7 +521,7 @@ fs_visitor::visit(ir_expression *ir) break; case ir_unop_b2i: - inst = emit(AND(this-result, op[0], fs_reg(1))); + emit(AND(this-result, op[0], fs_reg(1))); break; case ir_unop_b2f: temp = fs_reg(this, glsl_type::int_type); @@ -541,14 +541,14 @@ fs_visitor::visit(ir_expression *ir) break; case ir_unop_ceil: op[0].negate = !op[0].negate; - inst = emit(RNDD(this-result, op[0])); + emit(RNDD(this-result, op[0])); this-result.negate = true; break; case ir_unop_floor: - inst = emit(RNDD(this-result, op[0])); + emit(RNDD(this-result, op[0])); break; case ir_unop_fract: - inst = emit(FRC(this-result, op[0])); + emit(FRC(this-result, op[0])); break; case ir_unop_round_even: emit(RNDE(this-result, op[0])); @@ -585,27 +585,27 @@ fs_visitor::visit(ir_expression *ir) break; case ir_unop_bit_not: - inst = emit(NOT(this-result, op[0])); + emit(NOT(this-result, op[0])); break; case ir_binop_bit_and: - inst = emit(AND(this-result, op[0], op[1])); + emit(AND(this-result, op[0], op[1])); break; case ir_binop_bit_xor: - inst = emit(XOR(this-result, op[0], op[1])); + emit(XOR(this-result, op[0], op[1])); break; case ir_binop_bit_or: - inst = emit(OR(this-result, op[0], op[1])); + emit(OR(this-result, op[0], op[1])); break; case ir_binop_lshift: - inst = emit(SHL(this-result, op[0], op[1])); + emit(SHL(this-result, op[0], op[1])); break; case ir_binop_rshift: if (ir-type-base_type == GLSL_TYPE_INT) -inst = emit(ASR(this-result, op[0], op[1])); +emit(ASR(this-result, op[0], op[1])); else -inst = emit(SHR(this-result, op[0], op[1])); +emit(SHR(this-result, op[0], op[1])); break; case ir_binop_pack_half_2x16_split: emit(FS_OPCODE_PACK_HALF_2x16_SPLIT, this-result, op[0], op[1]); -- 1.8.1.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] i965: Apply CMP NULL {Switch} work-around to other Gen7s.
Listed in the restrictions section of CMP, but not on the work-arounds
page.
---
src/mesa/drivers/dri/i965/brw_eu_emit.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 704f219..f379263 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -1677,8 +1677,11 @@ void brw_CMP(struct brw_compile *p,
/* Item WaCMPInstNullDstForcesThreadSwitch in the Haswell Bspec workarounds
* page says:
*Any CMP instruction with a null destination must use a {switch}.
+*
+* It also applies to other Gen7 platforms (IVB, VLV) even though it isn't
+* mentioned on their work-arounds pages.
*/
- if (intel-is_haswell) {
+ if (intel-gen == 7) {
if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE
dest.nr == BRW_ARF_NULL) {
insn-header.thread_control = BRW_THREAD_SWITCH;
--
1.7.8.6
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[Mesa-dev] [PATCH 01/16] mesa: Add infrastructure for ARB_gpu_shader5.
---
src/glsl/builtins/tools/generate_builtins.py |1 +
src/glsl/glcpp/glcpp-parse.y |3 +++
src/glsl/glsl_parser_extras.cpp |1 +
src/glsl/glsl_parser_extras.h|2 ++
src/glsl/standalone_scaffolding.cpp |1 +
src/mesa/main/extensions.c |1 +
src/mesa/main/mtypes.h |1 +
7 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/src/glsl/builtins/tools/generate_builtins.py
b/src/glsl/builtins/tools/generate_builtins.py
index 75d3c21..85bd5dd 100755
--- a/src/glsl/builtins/tools/generate_builtins.py
+++ b/src/glsl/builtins/tools/generate_builtins.py
@@ -192,6 +192,7 @@ read_builtins(GLenum target, const char *protos, const char
**functions, unsigne
st-ARB_shading_language_packing_enable = true;
st-ARB_texture_multisample_enable = true;
st-ARB_texture_query_lod_enable = true;
+ st-ARB_gpu_shader5_enable = true;
_mesa_glsl_initialize_types(st);
sh-ir = new(sh) exec_list;
diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/glsl/glcpp/glcpp-parse.y
index 00edbbf..f0d2ab0 100644
--- a/src/glsl/glcpp/glcpp-parse.y
+++ b/src/glsl/glcpp/glcpp-parse.y
@@ -1236,6 +1236,9 @@ glcpp_parser_create (const struct gl_extensions
*extensions, int api)
if (extensions-ARB_texture_query_lod)
add_builtin_define(parser, GL_ARB_texture_query_lod, 1);
+
+ if (extensions-ARB_gpu_shader5)
+add_builtin_define(parser, GL_ARB_gpu_shader5, 1);
}
}
diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp
index 0992294..e4636f8 100644
--- a/src/glsl/glsl_parser_extras.cpp
+++ b/src/glsl/glsl_parser_extras.cpp
@@ -468,6 +468,7 @@ static const _mesa_glsl_extension
_mesa_glsl_supported_extensions[] = {
EXT(ARB_shading_language_packing, true, false, true, true, false,
ARB_shading_language_packing),
EXT(ARB_texture_multisample,true, false, true, true, false,
ARB_texture_multisample),
EXT(ARB_texture_query_lod, false, false, true, true, false,
ARB_texture_query_lod),
+ EXT(ARB_gpu_shader5,true, true, true, true, false,
ARB_gpu_shader5),
};
#undef EXT
diff --git a/src/glsl/glsl_parser_extras.h b/src/glsl/glsl_parser_extras.h
index 95891b5..c77dda8 100644
--- a/src/glsl/glsl_parser_extras.h
+++ b/src/glsl/glsl_parser_extras.h
@@ -284,6 +284,8 @@ struct _mesa_glsl_parse_state {
bool ARB_texture_multisample_warn;
bool ARB_texture_query_lod_enable;
bool ARB_texture_query_lod_warn;
+ bool ARB_gpu_shader5_enable;
+ bool ARB_gpu_shader5_warn;
/*@}*/
/** Extensions supported by the OpenGL implementation. */
diff --git a/src/glsl/standalone_scaffolding.cpp
b/src/glsl/standalone_scaffolding.cpp
index 0c1f52f..3c8f70f 100644
--- a/src/glsl/standalone_scaffolding.cpp
+++ b/src/glsl/standalone_scaffolding.cpp
@@ -104,6 +104,7 @@ void initialize_context_to_defaults(struct gl_context *ctx,
gl_api api)
ctx-Extensions.ARB_texture_cube_map_array = true;
ctx-Extensions.ARB_texture_multisample = true;
ctx-Extensions.ARB_texture_query_lod = true;
+ ctx-Extensions.ARB_gpu_shader5 = true;
ctx-Const.GLSLVersion = 120;
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index 64473b9..c56ba15 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa/main/extensions.c
@@ -101,6 +101,7 @@ static const struct extension extension_table[] = {
{ GL_ARB_framebuffer_object, o(ARB_framebuffer_object),
GL, 2005 },
{ GL_ARB_framebuffer_sRGB,o(EXT_framebuffer_sRGB),
GL, 1998 },
{ GL_ARB_get_program_binary, o(ARB_shader_objects),
GL, 2010 },
+ { GL_ARB_gpu_shader5, o(ARB_gpu_shader5),
GL, 2010 },
{ GL_ARB_half_float_pixel,o(ARB_half_float_pixel),
GL, 2003 },
{ GL_ARB_half_float_vertex, o(ARB_half_float_vertex),
GL, 2008 },
{ GL_ARB_instanced_arrays,o(ARB_instanced_arrays),
GL, 2008 },
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 6108a35..ef646ce 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2965,6 +2965,7 @@ struct gl_extensions
GLboolean ARB_framebuffer_object;
GLboolean ARB_explicit_attrib_location;
GLboolean ARB_geometry_shader4;
+ GLboolean ARB_gpu_shader5;
GLboolean ARB_half_float_pixel;
GLboolean ARB_half_float_vertex;
GLboolean ARB_instanced_arrays;
--
1.7.8.6
___
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[Mesa-dev] [PATCH 03/16] glsl: Add new bit built-ins IR and prototypes from ARB_gpu_shader5.
--- src/glsl/builtins/ir/bitCount.ir| 41 ++ src/glsl/builtins/ir/bitfieldExtract.ir | 57 src/glsl/builtins/ir/bitfieldInsert.ir | 65 +++ src/glsl/builtins/ir/bitfieldReverse.ir | 41 ++ src/glsl/builtins/ir/findLSB.ir | 41 ++ src/glsl/builtins/ir/findMSB.ir | 41 ++ src/glsl/builtins/profiles/ARB_gpu_shader5.glsl | 56 +++ 7 files changed, 342 insertions(+), 0 deletions(-) create mode 100644 src/glsl/builtins/ir/bitCount.ir create mode 100644 src/glsl/builtins/ir/bitfieldExtract.ir create mode 100644 src/glsl/builtins/ir/bitfieldInsert.ir create mode 100644 src/glsl/builtins/ir/bitfieldReverse.ir create mode 100644 src/glsl/builtins/ir/findLSB.ir create mode 100644 src/glsl/builtins/ir/findMSB.ir create mode 100644 src/glsl/builtins/profiles/ARB_gpu_shader5.glsl diff --git a/src/glsl/builtins/ir/bitCount.ir b/src/glsl/builtins/ir/bitCount.ir new file mode 100644 index 000..71fcae2 --- /dev/null +++ b/src/glsl/builtins/ir/bitCount.ir @@ -0,0 +1,41 @@ +((function bitCount + (signature int + (parameters + (declare (in) int value)) + ((return (expression int bit_count (var_ref value) + + (signature ivec2 + (parameters + (declare (in) ivec2 value)) + ((return (expression ivec2 bit_count (var_ref value) + + (signature ivec3 + (parameters + (declare (in) ivec3 value)) + ((return (expression ivec3 bit_count (var_ref value) + + (signature ivec4 + (parameters + (declare (in) ivec4 value)) + ((return (expression ivec4 bit_count (var_ref value) + + (signature int + (parameters + (declare (in) uint value)) + ((return (expression int bit_count (var_ref value) + + (signature ivec2 + (parameters + (declare (in) uvec2 value)) + ((return (expression ivec2 bit_count (var_ref value) + + (signature ivec3 + (parameters + (declare (in) uvec3 value)) + ((return (expression ivec3 bit_count (var_ref value) + + (signature ivec4 + (parameters + (declare (in) uvec4 value)) + ((return (expression ivec4 bit_count (var_ref value) +)) diff --git a/src/glsl/builtins/ir/bitfieldExtract.ir b/src/glsl/builtins/ir/bitfieldExtract.ir new file mode 100644 index 000..0491c82 --- /dev/null +++ b/src/glsl/builtins/ir/bitfieldExtract.ir @@ -0,0 +1,57 @@ +((function bitfieldExtract + (signature int + (parameters + (declare (in) int value) + (declare (in) int offset) + (declare (in) int bits)) + ((return (expression int bitfield_extract (var_ref value) (var_ref offset) (var_ref bits) + + (signature ivec2 + (parameters + (declare (in) ivec2 value) + (declare (in) int offset) + (declare (in) int bits)) + ((return (expression ivec2 bitfield_extract (var_ref value) (var_ref offset) (var_ref bits) + + (signature ivec3 + (parameters + (declare (in) ivec3 value) + (declare (in) int offset) + (declare (in) int bits)) + ((return (expression ivec3 bitfield_extract (var_ref value) (var_ref offset) (var_ref bits) + + (signature ivec4 + (parameters + (declare (in) ivec4 value) + (declare (in) int offset) + (declare (in) int bits)) + ((return (expression ivec4 bitfield_extract (var_ref value) (var_ref offset) (var_ref bits) + + (signature uint + (parameters + (declare (in) uint value) + (declare (in) int offset) + (declare (in) int bits)) + ((return (expression uint bitfield_extract (var_ref value) (var_ref offset) (var_ref bits) + + (signature uvec2 + (parameters + (declare (in) uvec2 value) + (declare (in) int offset) + (declare (in) int bits)) + ((return (expression uvec2 bitfield_extract (var_ref value) (var_ref offset) (var_ref bits) + + (signature uvec3 + (parameters + (declare (in) uvec3 value) + (declare (in) int offset) + (declare (in) int bits)) + ((return (expression uvec3 bitfield_extract (var_ref value) (var_ref offset) (var_ref bits) + + (signature uvec4 + (parameters + (declare (in) uvec4 value) + (declare (in) int offset) + (declare (in) int bits)) + ((return (expression uvec4 bitfield_extract (var_ref value) (var_ref offset) (var_ref bits) +)) diff --git a/src/glsl/builtins/ir/bitfieldInsert.ir b/src/glsl/builtins/ir/bitfieldInsert.ir new file mode 100644 index 000..2bb4442 --- /dev/null +++ b/src/glsl/builtins/ir/bitfieldInsert.ir @@ -0,0 +1,65 @@ +((function bitfieldInsert + (signature int + (parameters + (declare (in) int base) + (declare (in) int insert) + (declare (in) int offset) + (declare (in) int bits)) + ((return (expression int bitfield_insert (var_ref base) (var_ref
[Mesa-dev] [PATCH 04/16] glsl: Add support for new bit built-ins in ARB_gpu_shader5.
---
src/glsl/ir.cpp|8 +++-
src/glsl/ir.h | 21 -
src/glsl/ir_validate.cpp | 26 ++
src/glsl/opt_algebraic.cpp |6 +++---
src/mesa/program/ir_to_mesa.cpp|9 +
src/mesa/state_tracker/st_glsl_to_tgsi.cpp |8
6 files changed, 73 insertions(+), 5 deletions(-)
diff --git a/src/glsl/ir.cpp b/src/glsl/ir.cpp
index 05b77da..2c989c9 100644
--- a/src/glsl/ir.cpp
+++ b/src/glsl/ir.cpp
@@ -419,7 +419,7 @@ ir_expression::get_num_operands(ir_expression_operation op)
if (op = ir_last_triop)
return 3;
- if (op == ir_quadop_vector)
+ if (op = ir_last_quadop)
return 4;
assert(false);
@@ -477,6 +477,10 @@ static const char *const operator_strs[] = {
unpackHalf2x16,
unpackHalf2x16_split_x,
unpackHalf2x16_split_y,
+ bitfield_reverse,
+ bit_count,
+ find_msb,
+ find_lsb,
noise,
+,
-,
@@ -506,6 +510,8 @@ static const char *const operator_strs[] = {
packHalf2x16_split,
ubo_load,
lrp,
+ bitfield_extract,
+ bitfield_insert,
vector,
};
diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index 3018e0f..277b815 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -1032,6 +1032,16 @@ enum ir_expression_operation {
ir_unop_unpack_half_2x16_split_y,
/*@}*/
+ /**
+* \name Bit operations, part of ARB_gpu_shader5.
+*/
+ /*@{*/
+ ir_unop_bitfield_reverse,
+ ir_unop_bit_count,
+ ir_unop_find_msb,
+ ir_unop_find_lsb,
+ /*@}*/
+
ir_unop_noise,
/**
@@ -1122,14 +1132,23 @@ enum ir_expression_operation {
ir_triop_lrp,
+ ir_triop_bitfield_extract,
+
/**
* A sentinel marking the last of the ternary operations.
*/
- ir_last_triop = ir_triop_lrp,
+ ir_last_triop = ir_triop_bitfield_extract,
+
+ ir_quadop_bitfield_insert,
ir_quadop_vector,
/**
+* A sentinel marking the last of the ternary operations.
+*/
+ ir_last_quadop = ir_quadop_vector,
+
+ /**
* A sentinel marking the last of all operations.
*/
ir_last_opcode = ir_quadop_vector
diff --git a/src/glsl/ir_validate.cpp b/src/glsl/ir_validate.cpp
index 699c192..4a8df69 100644
--- a/src/glsl/ir_validate.cpp
+++ b/src/glsl/ir_validate.cpp
@@ -361,6 +361,19 @@ ir_validate::visit_leave(ir_expression *ir)
assert(ir-operands[0]-type == glsl_type::uint_type);
break;
+ case ir_unop_bitfield_reverse:
+ assert(ir-operands[0]-type == ir-type);
+ assert(ir-type-is_integer());
+ break;
+
+ case ir_unop_bit_count:
+ case ir_unop_find_msb:
+ case ir_unop_find_lsb:
+ assert(ir-operands[0]-type-vector_elements ==
ir-type-vector_elements);
+ assert(ir-operands[0]-type-is_integer());
+ assert(ir-type-base_type == GLSL_TYPE_INT);
+ break;
+
case ir_unop_noise:
/* XXX what can we assert here? */
break;
@@ -474,6 +487,19 @@ ir_validate::visit_leave(ir_expression *ir)
assert(ir-operands[2]-type == ir-operands[0]-type ||
ir-operands[2]-type == glsl_type::float_type);
break;
+ case ir_triop_bitfield_extract:
+ assert(ir-operands[0]-type == ir-type);
+ assert(ir-operands[1]-type == glsl_type::int_type);
+ assert(ir-operands[2]-type == glsl_type::int_type);
+ break;
+
+ case ir_quadop_bitfield_insert:
+ assert(ir-operands[0]-type == ir-type);
+ assert(ir-operands[1]-type == ir-type);
+ assert(ir-operands[2]-type == glsl_type::int_type);
+ assert(ir-operands[3]-type == glsl_type::int_type);
+ break;
+
case ir_quadop_vector:
/* The vector operator collects some number of scalars and generates a
* vector from them.
diff --git a/src/glsl/opt_algebraic.cpp b/src/glsl/opt_algebraic.cpp
index 70e016d..d706a6a 100644
--- a/src/glsl/opt_algebraic.cpp
+++ b/src/glsl/opt_algebraic.cpp
@@ -186,12 +186,12 @@ ir_algebraic_visitor::swizzle_if_required(ir_expression
*expr,
ir_rvalue *
ir_algebraic_visitor::handle_expression(ir_expression *ir)
{
- ir_constant *op_const[3] = {NULL, NULL, NULL};
- ir_expression *op_expr[3] = {NULL, NULL, NULL};
+ ir_constant *op_const[4] = {NULL, NULL, NULL, NULL};
+ ir_expression *op_expr[4] = {NULL, NULL, NULL, NULL};
ir_expression *temp;
unsigned int i;
- assert(ir-get_num_operands() = 3);
+ assert(ir-get_num_operands() = 4);
for (i = 0; i ir-get_num_operands(); i++) {
if (ir-operands[i]-type-is_matrix())
return ir;
diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp
index 14cf5ba..c6f6bf4 100644
--- a/src/mesa/program/ir_to_mesa.cpp
+++ b/src/mesa/program/ir_to_mesa.cpp
@@ -1444,6 +1444,10 @@ ir_to_mesa_visitor::visit(ir_expression *ir)
case ir_unop_unpack_half_2x16_split_x:
case ir_unop_unpack_half_2x16_split_y:
case ir_binop_pack_half_2x16_split:
+ case ir_unop_bitfield_reverse:
+ case
[Mesa-dev] [PATCH 00/16] Bit built-ins for ARB_gpu_shader5
This series, available at git://people.freedesktop.org/~mattst88/mesa arb_gpu_shader5 adds support for the bit built-ins for ARB_gpu_shader5 to the GLSL compiler and the i965 driver. Interesting parts of the series - - New IR operations for each built-in, plus two operations that match i965 and Radeon hardware. - 3x new lowering passes, for bitfieldInsert to BFM/BFI instructions, bitfieldInsert to BFM/bitops (for i965 VS), and bitfieldExtract to bitops (for i965 VS). - Addition of 3-src destination and shared-source fields and types on i965 to accommodate the BFE and BFI2 instructions. - Don't bother scalarizing the BFI1 (BFM) instruction in the i965 FS, since a single BFM generated from bitfieldInsert() feeds multiple scalarized BFI2 (BFI) instructions. Potential improvements: - Make 3-source instructions work in the i965 VS, and simply use BFE and BFI2 (and remove two of the lowering passes). - Alternatively, optimize the code generated by the lowering passes - Emit 3-src instructions if working on scalar data. - Do a slightly more efficient lowering if the data type is unsigned. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 05/16] glsl: Add constant evaluation of bit built-ins.
---
src/glsl/ir_constant_expression.cpp | 123 +++
1 files changed, 123 insertions(+), 0 deletions(-)
diff --git a/src/glsl/ir_constant_expression.cpp
b/src/glsl/ir_constant_expression.cpp
index c09e56a..119fe59 100644
--- a/src/glsl/ir_constant_expression.cpp
+++ b/src/glsl/ir_constant_expression.cpp
@@ -1248,6 +1248,102 @@ ir_expression::constant_expression_value(struct
hash_table *variable_context)
}
break;
+ case ir_unop_bitfield_reverse:
+ /* http://graphics.stanford.edu/~seander/bithacks.html#BitReverseObvious
*/
+ for (unsigned c = 0; c components; c++) {
+ unsigned int v = op[0]-value.u[c]; // input bits to be reversed
+ unsigned int r = v; // r will be reversed bits of v; first get LSB of
v
+ int s = sizeof(v) * CHAR_BIT - 1; // extra shift needed at end
+
+ for (v = 1; v; v = 1) {
+r = 1;
+r |= v 1;
+s--;
+ }
+ r = s; // shift when v's highest bits are zero
+
+ data.u[c] = r;
+ }
+ break;
+
+ case ir_unop_bit_count:
+ for (unsigned c = 0; c components; c++) {
+ unsigned count = 0;
+ unsigned v = op[0]-value.u[c];
+
+ for (; v; count++) {
+v = v - 1;
+ }
+ data.u[c] = count;
+ }
+ break;
+
+ case ir_unop_find_msb:
+ for (unsigned c = 0; c components; c++) {
+ int v = op[0]-value.i[c];
+
+ if (v == 0 || (op[0]-type-base_type == GLSL_TYPE_INT v == -1))
+data.i[c] = -1;
+ else {
+int count = 0;
+int top_bit = op[0]-type-base_type == GLSL_TYPE_UINT
+ ? 0 : v (1 31);
+
+while (((v (1 31)) == top_bit) count != 32) {
+ count++;
+ v = 1;
+}
+
+data.i[c] = count;
+ }
+ }
+ break;
+
+ case ir_unop_find_lsb:
+ for (unsigned c = 0; c components; c++) {
+ if (op[0]-value.i[c] == 0)
+data.i[c] = -1;
+ else {
+unsigned pos = 0;
+unsigned v = op[0]-value.u[c];
+
+for (; !(v 1); v = 1) {
+ pos++;
+}
+data.u[c] = pos;
+ }
+ }
+ break;
+
+ case ir_triop_bitfield_extract: {
+ int offset = op[1]-value.i[0];
+ int bits = op[2]-value.i[0];
+
+ for (unsigned c = 0; c components; c++) {
+ if (bits == 0)
+data.u[c] = 0;
+ else if (offset 0 || bits 0)
+data.u[c] = 0; /* Undefined, per spec. */
+ else if (offset + bits 32)
+data.u[c] = 0; /* Undefined, per spec. */
+ else {
+if (op[0]-type-base_type == GLSL_TYPE_INT) {
+ /* int so that the right shift will sign-extend. */
+ int value = op[0]-value.i[c];
+ value = 32 - bits - offset;
+ value = 32 - bits;
+ data.i[c] = value;
+} else {
+ unsigned value = op[0]-value.u[c];
+ value = 32 - bits - offset;
+ value = 32 - bits;
+ data.u[c] = value;
+}
+ }
+ }
+ break;
+ }
+
case ir_triop_lrp: {
assert(op[0]-type-base_type == GLSL_TYPE_FLOAT);
assert(op[1]-type-base_type == GLSL_TYPE_FLOAT);
@@ -1261,6 +1357,33 @@ ir_expression::constant_expression_value(struct
hash_table *variable_context)
break;
}
+ case ir_quadop_bitfield_insert: {
+ int offset = op[2]-value.i[0];
+ int bits = op[3]-value.i[0];
+
+ for (unsigned c = 0; c components; c++) {
+ if (bits == 0)
+data.u[c] = op[0]-value.u[c];
+ else if (offset 0 || bits 0)
+data.u[c] = 0; /* Undefined, per spec. */
+ else if (offset + bits 32)
+data.u[c] = 0; /* Undefined, per spec. */
+ else {
+unsigned insert_mask = ((1 bits) - 1) offset;
+
+unsigned insert = op[1]-value.u[c];
+insert = offset;
+insert = insert_mask;
+
+unsigned base = op[0]-value.u[c];
+base = ~insert_mask;
+
+data.u[c] = base | insert;
+ }
+ }
+ break;
+ }
+
case ir_quadop_vector:
for (unsigned c = 0; c this-type-vector_elements; c++) {
switch (this-type-base_type) {
--
1.7.8.6
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[Mesa-dev] [PATCH 06/16] glsl: Add a pass to lower bitfield-insert into bfm+bfi.
i965/Gen7+ and Radeon/Evergreen+ have bfm/bfi instructions to implement
bitfieldInsert() from ARB_gpu_shader5.
---
src/glsl/ir.cpp |2 +
src/glsl/ir.h | 18
src/glsl/ir_optimization.h |1 +
src/glsl/ir_validate.cpp| 12 +++
src/glsl/lower_instructions.cpp | 42 +++
src/mesa/program/ir_to_mesa.cpp |2 +
6 files changed, 77 insertions(+), 0 deletions(-)
diff --git a/src/glsl/ir.cpp b/src/glsl/ir.cpp
index 2c989c9..2c54525 100644
--- a/src/glsl/ir.cpp
+++ b/src/glsl/ir.cpp
@@ -508,8 +508,10 @@ static const char *const operator_strs[] = {
max,
pow,
packHalf2x16_split,
+ bfm,
ubo_load,
lrp,
+ bfi,
bitfield_extract,
bitfield_insert,
vector,
diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index 277b815..f23dc19 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -1118,6 +1118,15 @@ enum ir_expression_operation {
/*@}*/
/**
+* \name First half of a lowered bitfieldInsert() operation.
+*
+* \see lower_instructions::bitfield_insert_to_bfm_bfi
+*/
+ /*@{*/
+ ir_binop_bfm,
+ /*@}*/
+
+ /**
* Load a value the size of a given GLSL type from a uniform block.
*
* operand0 is the ir_constant uniform block index in the linked shader.
@@ -1132,6 +1141,15 @@ enum ir_expression_operation {
ir_triop_lrp,
+ /**
+* \name Second half of a lowered bitfieldInsert() operation.
+*
+* \see lower_instructions::bitfield_insert_to_bfm_bfi
+*/
+ /*@{*/
+ ir_triop_bfi,
+ /*@}*/
+
ir_triop_bitfield_extract,
/**
diff --git a/src/glsl/ir_optimization.h b/src/glsl/ir_optimization.h
index a8885d7..49b1475 100644
--- a/src/glsl/ir_optimization.h
+++ b/src/glsl/ir_optimization.h
@@ -37,6 +37,7 @@
#define MOD_TO_FRACT 0x20
#define INT_DIV_TO_MUL_RCP 0x40
#define LRP_TO_ARITH 0x80
+#define BITFIELD_INSERT_TO_BFM_BFI 0x100
/**
* \see class lower_packing_builtins_visitor
diff --git a/src/glsl/ir_validate.cpp b/src/glsl/ir_validate.cpp
index 4a8df69..26f09c7 100644
--- a/src/glsl/ir_validate.cpp
+++ b/src/glsl/ir_validate.cpp
@@ -474,6 +474,12 @@ ir_validate::visit_leave(ir_expression *ir)
assert(ir-operands[1]-type == glsl_type::float_type);
break;
+ case ir_binop_bfm:
+ assert(ir-type-is_integer());
+ assert(ir-operands[0]-type-is_integer());
+ assert(ir-operands[1]-type-is_integer());
+ break;
+
case ir_binop_ubo_load:
assert(ir-operands[0]-as_constant());
assert(ir-operands[0]-type == glsl_type::uint_type);
@@ -487,6 +493,12 @@ ir_validate::visit_leave(ir_expression *ir)
assert(ir-operands[2]-type == ir-operands[0]-type ||
ir-operands[2]-type == glsl_type::float_type);
break;
+ case ir_triop_bfi:
+ assert(ir-operands[0]-type-is_integer());
+ assert(ir-operands[1]-type == ir-operands[2]-type);
+ assert(ir-operands[1]-type == ir-type);
+ break;
+
case ir_triop_bitfield_extract:
assert(ir-operands[0]-type == ir-type);
assert(ir-operands[1]-type == glsl_type::int_type);
diff --git a/src/glsl/lower_instructions.cpp b/src/glsl/lower_instructions.cpp
index 1ce7b7c..ff9715d 100644
--- a/src/glsl/lower_instructions.cpp
+++ b/src/glsl/lower_instructions.cpp
@@ -38,6 +38,7 @@
* - LOG_TO_LOG2
* - MOD_TO_FRACT
* - LRP_TO_ARITH
+ * - BITFIELD_INSERT_TO_BFM_BFI
*
* SUB_TO_ADD_NEG:
* ---
@@ -84,6 +85,15 @@
* LRP_TO_ARITH:
* -
* Converts ir_triop_lrp to (op0 * (1.0f - op2)) + (op1 * op2).
+ *
+ * BITFIELD_INSERT_TO_BFM_BFI:
+ * ---
+ * Breaks ir_quadop_bitfield_insert into ir_binop_bfm (bitfield mask) and
+ * ir_triop_bfi (bitfield insert).
+ *
+ * Many GPUs implement the bitfieldInsert() built-in from ARB_gpu_shader_5
+ * with a pair of instructions.
+ *
*/
#include main/core.h /* for M_LOG2E */
@@ -114,6 +124,7 @@ private:
void pow_to_exp2(ir_expression *);
void log_to_log2(ir_expression *);
void lrp_to_arith(ir_expression *);
+ void bitfield_insert_to_bfm_bfi(ir_expression *);
};
/**
@@ -298,6 +309,32 @@ lower_instructions_visitor::lrp_to_arith(ir_expression *ir)
this-progress = true;
}
+void
+lower_instructions_visitor::bitfield_insert_to_bfm_bfi(ir_expression *ir)
+{
+ /* Translates
+*ir_quadop_bitfield_insert base insert offset bits
+* into
+*ir_triop_bfi (ir_binop_bfm bits offset) insert base
+*/
+
+ /* Save op0 */
+ ir_variable *temp = new(ir) ir_variable(ir-operands[0]-type, bfi_base,
+ ir_var_temporary);
+ this-base_ir-insert_before(temp);
+ this-base_ir-insert_before(assign(temp, ir-operands[0]));
+
+ ir-operation = ir_triop_bfi;
+ ir-operands[0] = new(ir) ir_expression(ir_binop_bfm, ir-type,
+ swizzle_(ir-operands[3]),
+
[Mesa-dev] [PATCH 07/16] glsl: Add bitfieldInsert-to-bfm/bitops lowering pass.
---
src/glsl/ir_optimization.h |1 +
src/glsl/lower_instructions.cpp | 61 +++
2 files changed, 62 insertions(+), 0 deletions(-)
diff --git a/src/glsl/ir_optimization.h b/src/glsl/ir_optimization.h
index 49b1475..445dc49 100644
--- a/src/glsl/ir_optimization.h
+++ b/src/glsl/ir_optimization.h
@@ -38,6 +38,7 @@
#define INT_DIV_TO_MUL_RCP 0x40
#define LRP_TO_ARITH 0x80
#define BITFIELD_INSERT_TO_BFM_BFI 0x100
+#define BITFIELD_INSERT_TO_BFM_BITOPS 0x200
/**
* \see class lower_packing_builtins_visitor
diff --git a/src/glsl/lower_instructions.cpp b/src/glsl/lower_instructions.cpp
index ff9715d..1c1cad8 100644
--- a/src/glsl/lower_instructions.cpp
+++ b/src/glsl/lower_instructions.cpp
@@ -39,6 +39,7 @@
* - MOD_TO_FRACT
* - LRP_TO_ARITH
* - BITFIELD_INSERT_TO_BFM_BFI
+ * - BITFIELD_INSERT_TO_BFM_BITOPS
*
* SUB_TO_ADD_NEG:
* ---
@@ -91,9 +92,20 @@
* Breaks ir_quadop_bitfield_insert into ir_binop_bfm (bitfield mask) and
* ir_triop_bfi (bitfield insert).
*
+ * Mutually exclusive with BITFIELD_INSERT_TO_BFM_BITOPS.
+ *
* Many GPUs implement the bitfieldInsert() built-in from ARB_gpu_shader_5
* with a pair of instructions.
*
+ * BITFIELD_INSERT_TO_BFM_BITOPS:
+ * --
+ * Breaks ir_quadop_bitfield_insert into ir_binop_bfm (bitfield mask) and
+ * bit operations simulating ir_triop_bfi (bitfield insert).
+ *
+ * Mutually exclusive with BITFIELD_INSERT_TO_BFM_BITOPS.
+ *
+ * It's difficult to use vector three-source instructions in i965's vertex
+ * shader, so don't emit ir_triop_bfi, but rather bit operations.
*/
#include main/core.h /* for M_LOG2E */
@@ -125,6 +137,7 @@ private:
void log_to_log2(ir_expression *);
void lrp_to_arith(ir_expression *);
void bitfield_insert_to_bfm_bfi(ir_expression *);
+ void bitfield_insert_to_bfm_bitops(ir_expression *ir);
};
/**
@@ -335,6 +348,52 @@
lower_instructions_visitor::bitfield_insert_to_bfm_bfi(ir_expression *ir)
this-progress = true;
}
+void lower_instructions_visitor::bitfield_insert_to_bfm_bitops(ir_expression
*ir)
+{
+ /* Translates
+*ir_quadop_bitfield_insert base insert offset bits
+* into
+*(or (and base (not insert_mask))
+*(and ( insert offset) insert_mask))
+* where insert_mask is
+*(bfm bits offset)
+*/
+ ir_variable *base = new(ir) ir_variable(ir-operands[0]-type, bfi_base,
+ ir_var_temporary);
+ this-base_ir-insert_before(base);
+ this-base_ir-insert_before(assign(base, ir-operands[0]));
+
+ ir_variable *insert = new(ir) ir_variable(ir-operands[1]-type,
bfi_insert,
+ ir_var_temporary);
+ this-base_ir-insert_before(insert);
+ this-base_ir-insert_before(assign(insert, ir-operands[1]));
+
+ ir_variable *offset = new(ir) ir_variable(ir-operands[2]-type,
bfi_offset,
+ ir_var_temporary);
+ this-base_ir-insert_before(offset);
+ this-base_ir-insert_before(assign(offset, ir-operands[2]));
+
+ ir_variable *bits = new(ir) ir_variable(ir-operands[3]-type, bfi_bits,
+ ir_var_temporary);
+ this-base_ir-insert_before(bits);
+ this-base_ir-insert_before(assign(bits, ir-operands[3]));
+
+ ir_variable *insert_mask = new(ir) ir_variable(glsl_type::int_type,
+ insert_mask,
+ ir_var_temporary);
+ this-base_ir-insert_before(insert_mask);
+ this-base_ir-insert_before(assign(insert_mask,
+ new(ir) ir_expression(ir_binop_bfm,
ir-type,
+
swizzle_(bits),
+
swizzle_(offset;
+
+ ir-operation = ir_binop_bit_or;
+ ir-operands[0] = bit_and(base, bit_not(insert_mask));
+ ir-operands[1] = bit_and(lshift(insert, offset), insert_mask);
+ ir-operands[2] = NULL;
+ ir-operands[3] = NULL;
+}
+
ir_visitor_status
lower_instructions_visitor::visit_leave(ir_expression *ir)
{
@@ -379,6 +438,8 @@ lower_instructions_visitor::visit_leave(ir_expression *ir)
case ir_quadop_bitfield_insert:
if (lowering(BITFIELD_INSERT_TO_BFM_BFI))
bitfield_insert_to_bfm_bfi(ir);
+ else if (lowering(BITFIELD_INSERT_TO_BFM_BITOPS))
+ bitfield_insert_to_bfm_bitops(ir);
break;
default:
--
1.7.8.6
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 08/16] glsl: Add BFE-to-bitops lowering pass.
---
src/glsl/ir_optimization.h |1 +
src/glsl/lower_instructions.cpp | 82 +++
2 files changed, 83 insertions(+), 0 deletions(-)
diff --git a/src/glsl/ir_optimization.h b/src/glsl/ir_optimization.h
index 445dc49..c5405e5 100644
--- a/src/glsl/ir_optimization.h
+++ b/src/glsl/ir_optimization.h
@@ -39,6 +39,7 @@
#define LRP_TO_ARITH 0x80
#define BITFIELD_INSERT_TO_BFM_BFI 0x100
#define BITFIELD_INSERT_TO_BFM_BITOPS 0x200
+#define BFE_TO_BITOPS 0x400
/**
* \see class lower_packing_builtins_visitor
diff --git a/src/glsl/lower_instructions.cpp b/src/glsl/lower_instructions.cpp
index 1c1cad8..d49c419 100644
--- a/src/glsl/lower_instructions.cpp
+++ b/src/glsl/lower_instructions.cpp
@@ -40,6 +40,7 @@
* - LRP_TO_ARITH
* - BITFIELD_INSERT_TO_BFM_BFI
* - BITFIELD_INSERT_TO_BFM_BITOPS
+ * - BFE_TO_BITOPS
*
* SUB_TO_ADD_NEG:
* ---
@@ -106,6 +107,10 @@
*
* It's difficult to use vector three-source instructions in i965's vertex
* shader, so don't emit ir_triop_bfi, but rather bit operations.
+ *
+ * BFE_TO_BITOPS:
+ * --
+ * Breaks ir_triop_bitfield_extract into bit operations (and, or, shift).
*/
#include main/core.h /* for M_LOG2E */
@@ -138,6 +143,7 @@ private:
void lrp_to_arith(ir_expression *);
void bitfield_insert_to_bfm_bfi(ir_expression *);
void bitfield_insert_to_bfm_bitops(ir_expression *ir);
+ void bfe_to_bitops(ir_expression *);
};
/**
@@ -394,6 +400,77 @@ void
lower_instructions_visitor::bitfield_insert_to_bfm_bitops(ir_expression *ir
ir-operands[3] = NULL;
}
+void
+lower_instructions_visitor::bfe_to_bitops(ir_expression *ir)
+{
+ /* Translates
+*(bfe value offset bits)
+* into
+*(asr (shl value (- (- 32 bits) offset)) (- 32 bits))
+*
+* which more simply is
+*value = 32 - bits - offset;
+*value = 32 - bits; // = is ASR.
+*
+* but some hardware (like i965) can only shift by 0-31, so the corner case
+* of bits == 0 leads to shifting by 0 instead of 32. Instead, do
+*if (bits == 0)
+* result = 0;
+*else {
+* value = 32 - bits - offset;
+* value = 32 - bits; // = is ASR.
+* result = value;
+*}
+*/
+
+ /* TODO:
+*- Allow hardware that can shift by 32 to avoid the branch.
+*- Allow skipping the lowering pass if type of value is scalar.
+*- Emit (value offset) (1 bits) - 1) for unsigned values.
+*/
+
+ ir_variable *value = new(ir) ir_variable(ir-operands[0]-type, bfe_value,
+ir_var_temporary);
+ this-base_ir-insert_before(value);
+ this-base_ir-insert_before(assign(value, ir-operands[0]));
+
+ ir_variable *offset = new(ir) ir_variable(ir-operands[1]-type,
bfe_offset,
+ ir_var_temporary);
+ this-base_ir-insert_before(offset);
+ this-base_ir-insert_before(assign(offset, ir-operands[1]));
+
+ ir_variable *bits = new(ir) ir_variable(ir-operands[2]-type, bfe_bits,
+ ir_var_temporary);
+ this-base_ir-insert_before(bits);
+ this-base_ir-insert_before(assign(bits, ir-operands[2]));
+
+ ir_constant *immed_32 = new(ir) ir_constant(32);
+ ir_variable *width_minus_bits = new(ir) ir_variable(glsl_type::int_type,
+ width_minus_bits,
+ ir_var_temporary);
+ this-base_ir-insert_before(width_minus_bits);
+ this-base_ir-insert_before(assign(width_minus_bits, sub(immed_32, bits)));
+
+ ir_variable *result = new(ir) ir_variable(ir-type, bfe_result,
+ ir_var_temporary);
+ this-base_ir-insert_before(result);
+
+ ir_if *bits_zero_if = if_tree(equal(bits, new(ir) ir_constant(0)),
+ assign(result, new(ir) ir_constant(0)),
+ assign(result,
+rshift(lshift(value,
swizzle_(sub(width_minus_bits, offset))),
+
swizzle_(width_minus_bits;
+ this-base_ir-insert_before(bits_zero_if);
+
+ /* XXX: Seems like there should be a better way of doing this. */
+ ir-operation = ir_binop_add;
+ ir-operands[0] = new(ir) ir_dereference_variable(result);
+ ir-operands[1] = new(ir) ir_constant(0);
+ ir-operands[2] = NULL;
+
+ this-progress = true;
+}
+
ir_visitor_status
lower_instructions_visitor::visit_leave(ir_expression *ir)
{
@@ -442,6 +519,11 @@ lower_instructions_visitor::visit_leave(ir_expression *ir)
bitfield_insert_to_bfm_bitops(ir);
break;
+ case ir_triop_bitfield_extract:
+ if (lowering(BFE_TO_BITOPS))
+ bfe_to_bitops(ir);
+ break;
+
default:
return visit_continue;
}
--
1.7.8.6
[Mesa-dev] [PATCH 09/16] i965: Add Gen7+ fields to brw_instruction and add comments.
---
src/mesa/drivers/dri/i965/brw_structs.h | 31 +++
1 files changed, 19 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h
b/src/mesa/drivers/dri/i965/brw_structs.h
index 75365e0..c322edf 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -824,7 +824,7 @@ struct brw_instruction
GLuint access_mode:1;
GLuint mask_control:1;
GLuint dependency_control:2;
- GLuint compression_control:2; /* gen6: quater control */
+ GLuint compression_control:2; /* gen6: quarter control */
GLuint thread_control:2;
GLuint predicate_control:4;
GLuint predicate_inverse:1;
@@ -849,7 +849,7 @@ struct brw_instruction
GLuint src0_reg_type:3;
GLuint src1_reg_file:2;
GLuint src1_reg_type:3;
-GLuint pad:1;
+ GLuint nibctrl:1; /* gen7+ */
GLuint dest_subreg_nr:5;
GLuint dest_reg_nr:8;
GLuint dest_horiz_stride:2;
@@ -864,7 +864,7 @@ struct brw_instruction
GLuint src0_reg_type:3;
GLuint src1_reg_file:2;/* 0x0c00 */
GLuint src1_reg_type:3;/* 0x7000 */
-GLuint pad:1;
+ GLuint nibctrl:1; /* gen7+ */
GLint dest_indirect_offset:10; /* offset against the deref'd address
reg */
GLuint dest_subreg_nr:3; /* subnr for the address reg a0.x */
GLuint dest_horiz_stride:2;
@@ -879,7 +879,7 @@ struct brw_instruction
GLuint src0_reg_type:3;
GLuint src1_reg_file:2;
GLuint src1_reg_type:3;
-GLuint pad:1;
+ GLuint nibctrl:1; /* gen7+ */
GLuint dest_writemask:4;
GLuint dest_subreg_nr:1;
GLuint dest_reg_nr:8;
@@ -893,7 +893,9 @@ struct brw_instruction
GLuint dest_reg_type:3;
GLuint src0_reg_file:2;
GLuint src0_reg_type:3;
-GLuint pad0:6;
+ GLuint src1_reg_file:2;
+ GLuint src1_reg_type:3;
+ GLuint nibctrl:1; /* gen7+ */
GLuint dest_writemask:4;
GLint dest_indirect_offset:6;
GLuint dest_subreg_nr:3;
@@ -914,16 +916,21 @@ struct brw_instruction
} branch_gen6;
struct {
-GLuint dest_reg_file:1;
+ GLuint dest_reg_file:1; /* gen6, not gen7+ */
GLuint flag_subreg_num:1;
-GLuint pad0:2;
+ GLuint flag_reg_nr:1; /* gen7+ */
+ GLuint pad0:1;
GLuint src0_abs:1;
GLuint src0_negate:1;
GLuint src1_abs:1;
GLuint src1_negate:1;
GLuint src2_abs:1;
GLuint src2_negate:1;
-GLuint pad1:7;
+ GLuint src_type:2; /* gen7+ */
+ GLuint dst_type:2; /* gen7+ */
+ GLuint pad1:1;
+ GLuint nibctrl:1; /* gen7+ */
+ GLuint pad2:1;
GLuint dest_writemask:4;
GLuint dest_subreg_nr:3;
GLuint dest_reg_nr:8;
@@ -945,7 +952,7 @@ struct brw_instruction
GLuint src0_width:3;
GLuint src0_vert_stride:4;
GLuint flag_subreg_nr:1;
-GLuint flag_reg_nr:1;
+ GLuint flag_reg_nr:1; /* gen7+ */
GLuint pad:5;
} da1;
@@ -960,7 +967,7 @@ struct brw_instruction
GLuint src0_width:3;
GLuint src0_vert_stride:4;
GLuint flag_subreg_nr:1;
-GLuint flag_reg_nr:1;
+ GLuint flag_reg_nr:1; /* gen7+ */
GLuint pad:5;
} ia1;
@@ -978,7 +985,7 @@ struct brw_instruction
GLuint pad0:1;
GLuint src0_vert_stride:4;
GLuint flag_subreg_nr:1;
-GLuint flag_reg_nr:1;
+ GLuint flag_reg_nr:1; /* gen7+ */
GLuint pad1:5;
} da16;
@@ -996,7 +1003,7 @@ struct brw_instruction
GLuint pad0:1;
GLuint src0_vert_stride:4;
GLuint flag_subreg_nr:1;
-GLuint flag_reg_nr:1;
+ GLuint flag_reg_nr:1; /* gen7+ */
GLuint pad1:5;
} ia16;
--
1.7.8.6
___
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http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 10/16] i965: Add 3-src destination and shared-source type macros.
---
src/mesa/drivers/dri/i965/brw_defines.h | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 38f0356..a5d9452 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -777,6 +777,17 @@ enum opcode {
#define BRW_REGISTER_TYPE_V 6/* packed int vector, immediates only,
uword dest only */
#define BRW_REGISTER_TYPE_F 7
+/* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so
+ * the types were implied. IVB adds BFE and BFI2 that operate on doublewords
+ * and unsigned doublewords, so a new field is also available in the da3src
+ * struct (part of struct brw_instruction.bits1 in brw_structs.h) to select
+ * dst and shared-src types. The values are different from BRW_REGISTER_TYPE_*.
+ */
+#define BRW_3SRC_TYPE_F 0
+#define BRW_3SRC_TYPE_D 1
+#define BRW_3SRC_TYPE_UD 2
+#define BRW_3SRC_TYPE_DF 3
+
#define BRW_ARF_NULL 0x00
#define BRW_ARF_ADDRESS 0x10
#define BRW_ARF_ACCUMULATOR 0x20
--
1.7.8.6
___
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[Mesa-dev] [PATCH 11/16] i965/gen7: Set src/dst types for 3-src instructions.
Also update asserts to allow BFE and BFI2, which take (unsigned)
doubleword arguments.
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 34 +++---
1 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index dda562f..f6dd2e2 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -788,6 +788,7 @@ static struct brw_instruction *brw_alu3(struct brw_compile
*p,
struct brw_reg src1,
struct brw_reg src2)
{
+ struct intel_context *intel = p-brw-intel;
struct brw_instruction *insn = next_insn(p, opcode);
gen7_convert_mrf_to_grf(p, dest);
@@ -798,7 +799,9 @@ static struct brw_instruction *brw_alu3(struct brw_compile
*p,
dest.file == BRW_MESSAGE_REGISTER_FILE);
assert(dest.nr 128);
assert(dest.address_mode == BRW_ADDRESS_DIRECT);
- assert(dest.type == BRW_REGISTER_TYPE_F);
+ assert(dest.type == BRW_REGISTER_TYPE_F ||
+ dest.type == BRW_REGISTER_TYPE_D ||
+ dest.type == BRW_REGISTER_TYPE_UD);
insn-bits1.da3src.dest_reg_file = (dest.file == BRW_MESSAGE_REGISTER_FILE);
insn-bits1.da3src.dest_reg_nr = dest.nr;
insn-bits1.da3src.dest_subreg_nr = dest.subnr / 16;
@@ -808,7 +811,9 @@ static struct brw_instruction *brw_alu3(struct brw_compile
*p,
assert(src0.file == BRW_GENERAL_REGISTER_FILE);
assert(src0.address_mode == BRW_ADDRESS_DIRECT);
assert(src0.nr 128);
- assert(src0.type == BRW_REGISTER_TYPE_F);
+ assert(src0.type == BRW_REGISTER_TYPE_F ||
+ src0.type == BRW_REGISTER_TYPE_D ||
+ src0.type == BRW_REGISTER_TYPE_UD);
insn-bits2.da3src.src0_swizzle = src0.dw1.bits.swizzle;
insn-bits2.da3src.src0_subreg_nr = get_3src_subreg_nr(src0);
insn-bits2.da3src.src0_reg_nr = src0.nr;
@@ -819,7 +824,8 @@ static struct brw_instruction *brw_alu3(struct brw_compile
*p,
assert(src1.file == BRW_GENERAL_REGISTER_FILE);
assert(src1.address_mode == BRW_ADDRESS_DIRECT);
assert(src1.nr 128);
- assert(src1.type == BRW_REGISTER_TYPE_F);
+ assert(src1.type == BRW_REGISTER_TYPE_F ||
+ src1.type == BRW_REGISTER_TYPE_D);
insn-bits2.da3src.src1_swizzle = src1.dw1.bits.swizzle;
insn-bits2.da3src.src1_subreg_nr_low = get_3src_subreg_nr(src1) 0x3;
insn-bits3.da3src.src1_subreg_nr_high = get_3src_subreg_nr(src1) 2;
@@ -831,7 +837,8 @@ static struct brw_instruction *brw_alu3(struct brw_compile
*p,
assert(src2.file == BRW_GENERAL_REGISTER_FILE);
assert(src2.address_mode == BRW_ADDRESS_DIRECT);
assert(src2.nr 128);
- assert(src2.type == BRW_REGISTER_TYPE_F);
+ assert(src2.type == BRW_REGISTER_TYPE_F ||
+ src2.type == BRW_REGISTER_TYPE_D);
insn-bits3.da3src.src2_swizzle = src2.dw1.bits.swizzle;
insn-bits3.da3src.src2_subreg_nr = get_3src_subreg_nr(src2);
insn-bits3.da3src.src2_rep_ctrl = src2.vstride == BRW_VERTICAL_STRIDE_0;
@@ -839,6 +846,25 @@ static struct brw_instruction *brw_alu3(struct brw_compile
*p,
insn-bits1.da3src.src2_abs = src2.abs;
insn-bits1.da3src.src2_negate = src2.negate;
+ if (intel-gen = 7) {
+ assert(dest.type == src0.type);
+
+ switch (dest.type) {
+ case BRW_REGISTER_TYPE_F:
+ insn-bits1.da3src.src_type = BRW_3SRC_TYPE_F;
+ insn-bits1.da3src.dst_type = BRW_3SRC_TYPE_F;
+ break;
+ case BRW_REGISTER_TYPE_D:
+ insn-bits1.da3src.src_type = BRW_3SRC_TYPE_D;
+ insn-bits1.da3src.dst_type = BRW_3SRC_TYPE_D;
+ break;
+ case BRW_REGISTER_TYPE_UD:
+ insn-bits1.da3src.src_type = BRW_3SRC_TYPE_UD;
+ insn-bits1.da3src.dst_type = BRW_3SRC_TYPE_UD;
+ break;
+ }
+ }
+
return insn;
}
--
1.7.8.6
___
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[Mesa-dev] [PATCH 12/16] i965: Add support for emitting and disassembling bit instructions.
Specifically
bfe - for bitfieldExtract()
bfi1 and bfi2 - for bitfieldInsert()
bfrev - for bitfieldReverse()
cbit - for bitCount()
fbh - for findMSB()
fbl - for findLSB()
---
src/mesa/drivers/dri/i965/brw_defines.h |7 +++
src/mesa/drivers/dri/i965/brw_disasm.c |7 +++
src/mesa/drivers/dri/i965/brw_eu.h |7 +++
src/mesa/drivers/dri/i965/brw_eu_emit.c |7 +++
4 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index a5d9452..62a79d6 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -647,6 +647,10 @@ enum opcode {
BRW_OPCODE_CMPN = 17,
BRW_OPCODE_F32TO16 = 19,
BRW_OPCODE_F16TO32 = 20,
+ BRW_OPCODE_BFREV = 23,
+ BRW_OPCODE_BFE =24,
+ BRW_OPCODE_BFI1 = 25,
+ BRW_OPCODE_BFI2 = 26,
BRW_OPCODE_JMPI = 32,
BRW_OPCODE_IF = 34,
BRW_OPCODE_IFF =35,
@@ -676,6 +680,9 @@ enum opcode {
BRW_OPCODE_MAC =72,
BRW_OPCODE_MACH = 73,
BRW_OPCODE_LZD =74,
+ BRW_OPCODE_FBH =75,
+ BRW_OPCODE_FBL =76,
+ BRW_OPCODE_CBIT = 77,
BRW_OPCODE_SAD2 = 80,
BRW_OPCODE_SADA2 = 81,
BRW_OPCODE_DP4 =84,
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c
b/src/mesa/drivers/dri/i965/brw_disasm.c
index 8736764..0b881b7 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -43,6 +43,10 @@ const struct opcode_desc opcode_descs[128] = {
[BRW_OPCODE_LZD] = { .name = lzd, .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_F32TO16] = { .name = f32to16, .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_F16TO32] = { .name = f16to32, .nsrc = 1, .ndst = 1 },
+[BRW_OPCODE_BFREV] = { .name = bfrev, .nsrc = 1, .ndst = 1},
+[BRW_OPCODE_FBH] = { .name = fbh, .nsrc = 1, .ndst = 1},
+[BRW_OPCODE_FBL] = { .name = fbl, .nsrc = 1, .ndst = 1},
+[BRW_OPCODE_CBIT] = { .name = cbit, .nsrc = 1, .ndst = 1},
[BRW_OPCODE_MUL] = { .name = mul, .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_MAC] = { .name = mac, .nsrc = 2, .ndst = 1 },
@@ -70,6 +74,9 @@ const struct opcode_desc opcode_descs[128] = {
[BRW_OPCODE_ASR] = { .name = asr, .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_CMP] = { .name = cmp, .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_CMPN] = { .name = cmpn, .nsrc = 2, .ndst = 1 },
+[BRW_OPCODE_BFE] = { .name = bfe, .nsrc = 3, .ndst = 1},
+[BRW_OPCODE_BFI1] = { .name = bfe1, .nsrc = 2, .ndst = 1},
+[BRW_OPCODE_BFI2] = { .name = bfe2, .nsrc = 3, .ndst = 1},
[BRW_OPCODE_SEND] = { .name = send, .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_SENDC] = { .name = sendc, .nsrc = 1, .ndst = 1 },
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
b/src/mesa/drivers/dri/i965/brw_eu.h
index 9683b13..ce8843d 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -176,6 +176,13 @@ ALU2(LINE)
ALU2(PLN)
ALU3(MAD)
ALU3(LRP)
+ALU1(BFREV)
+ALU3(BFE)
+ALU2(BFI1)
+ALU3(BFI2)
+ALU1(FBH)
+ALU1(FBL)
+ALU1(CBIT)
ROUND(RNDZ)
ROUND(RNDE)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index f6dd2e2..d2f8fe6 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -951,6 +951,13 @@ ALU2(LINE)
ALU2(PLN)
ALU3(MAD)
ALU3(LRP)
+ALU1(BFREV)
+ALU3(BFE)
+ALU2(BFI1)
+ALU3(BFI2)
+ALU1(FBH)
+ALU1(FBL)
+ALU1(CBIT)
ROUND(RNDZ)
ROUND(RNDE)
--
1.7.8.6
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[Mesa-dev] [PATCH 13/16] i965/fs: Add support for bit instructions.
Don't bother scalarizing ir_binop_bfm, since its results are
identical for all channels.
---
src/mesa/drivers/dri/i965/brw_fs.cpp |7 +++
src/mesa/drivers/dri/i965/brw_fs.h |7 +++
.../dri/i965/brw_fs_channel_expressions.cpp| 37 +++
src/mesa/drivers/dri/i965/brw_fs_emit.cpp | 48
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 29
5 files changed, 128 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 5f659b1..f060a7c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -173,6 +173,13 @@ ALU2(SHL)
ALU2(SHR)
ALU2(ASR)
ALU3(LRP)
+ALU1(BFREV)
+ALU3(BFE)
+ALU2(BFI1)
+ALU3(BFI2)
+ALU1(FBH)
+ALU1(FBL)
+ALU1(CBIT)
/** Gen4 predicated IF. */
fs_inst *
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 86a9ec5..fe7eddc 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -288,6 +288,13 @@ public:
uint32_t condition);
fs_inst *LRP(fs_reg dst, fs_reg a, fs_reg y, fs_reg x);
fs_inst *DEP_RESOLVE_MOV(int grf);
+ fs_inst *BFREV(fs_reg dst, fs_reg value);
+ fs_inst *BFE(fs_reg dst, fs_reg bits, fs_reg offset, fs_reg value);
+ fs_inst *BFI1(fs_reg dst, fs_reg bits, fs_reg offset);
+ fs_inst *BFI2(fs_reg dst, fs_reg bfi1_dst, fs_reg insert, fs_reg base);
+ fs_inst *FBH(fs_reg dst, fs_reg value);
+ fs_inst *FBL(fs_reg dst, fs_reg value);
+ fs_inst *CBIT(fs_reg dst, fs_reg value);
int type_size(const struct glsl_type *type);
fs_inst *get_instruction_generating_reg(fs_inst *start,
diff --git a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
index 30d8d9b..ee362e3 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
@@ -216,6 +216,10 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment
*ir)
case ir_unop_cos_reduced:
case ir_unop_dFdx:
case ir_unop_dFdy:
+ case ir_unop_bitfield_reverse:
+ case ir_unop_bit_count:
+ case ir_unop_find_msb:
+ case ir_unop_find_lsb:
for (i = 0; i vector_elements; i++) {
ir_rvalue *op0 = get_element(op_var[0], i);
@@ -338,11 +342,26 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment
*ir)
assert(!noise should have been broken down to function call);
break;
+ case ir_binop_bfm: {
+ /* Does not need to be scalarized, since its result will be identical
+ * for all channels.
+ */
+ ir_rvalue *op0 = get_element(op_var[0], 0);
+ ir_rvalue *op1 = get_element(op_var[1], 0);
+
+ assign(ir, 0, new(mem_ctx) ir_expression(expr-operation,
+ element_type,
+ op0,
+ op1));
+ break;
+ }
+
case ir_binop_ubo_load:
assert(!not yet supported);
break;
case ir_triop_lrp:
+ case ir_triop_bitfield_extract:
for (i = 0; i vector_elements; i++) {
ir_rvalue *op0 = get_element(op_var[0], i);
ir_rvalue *op1 = get_element(op_var[1], i);
@@ -356,6 +375,23 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment
*ir)
}
break;
+ case ir_triop_bfi: {
+ /* Only a single BFM is needed for multiple BFIs. */
+ ir_rvalue *op0 = get_element(op_var[0], 0);
+
+ for (i = 0; i vector_elements; i++) {
+ ir_rvalue *op1 = get_element(op_var[1], i);
+ ir_rvalue *op2 = get_element(op_var[2], i);
+
+ assign(ir, i, new(mem_ctx) ir_expression(expr-operation,
+ element_type,
+ op0,
+ op1,
+ op2));
+ }
+ break;
+ }
+
case ir_unop_pack_snorm_2x16:
case ir_unop_pack_snorm_4x8:
case ir_unop_pack_unorm_2x16:
@@ -366,6 +402,7 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment
*ir)
case ir_unop_unpack_unorm_2x16:
case ir_unop_unpack_unorm_4x8:
case ir_unop_unpack_half_2x16:
+ case ir_quadop_bitfield_insert:
case ir_quadop_vector:
assert(!should have been lowered);
break;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
index 0f6b715..b7c85ef 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
@@ -1209,6 +1209,54 @@ fs_generator::generate_code(exec_list *instructions)
case BRW_OPCODE_SEL:
brw_SEL(p, dst, src[0], src[1]);
break;
+ case BRW_OPCODE_BFREV:
+ /* BFREV only supports UD type for src and
[Mesa-dev] [PATCH 14/16] i965/vs: Add support for bit instructions.
---
src/mesa/drivers/dri/i965/brw_vec4.h |7 +++
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp| 29 ++
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 48
3 files changed, 84 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 697ab86..45c1f7a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -386,6 +386,13 @@ public:
vec4_instruction *PULL_CONSTANT_LOAD(dst_reg dst, src_reg index);
vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
+ vec4_instruction *BFREV(dst_reg dst, src_reg value);
+ vec4_instruction *BFE(dst_reg dst, src_reg bits, src_reg offset, src_reg
value);
+ vec4_instruction *BFI1(dst_reg dst, src_reg bits, src_reg offset);
+ vec4_instruction *BFI2(dst_reg dst, src_reg bfi1_dst, src_reg insert,
src_reg base);
+ vec4_instruction *FBH(dst_reg dst, src_reg value);
+ vec4_instruction *FBL(dst_reg dst, src_reg value);
+ vec4_instruction *CBIT(dst_reg dst, src_reg value);
int implied_mrf_writes(vec4_instruction *inst);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index c9963bf..6916bd8 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -838,6 +838,35 @@ vec4_generator::generate_code(exec_list *instructions)
brw_F16TO32(p, dst, src[0]);
break;
+ case BRW_OPCODE_BFREV:
+ /* BFREV only supports UD type for src and dst. */
+ brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
+ retype(src[0], BRW_REGISTER_TYPE_UD));
+ break;
+ case BRW_OPCODE_FBH:
+ /* FBH only supports UD type for dst. */
+ brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
+ break;
+ case BRW_OPCODE_FBL:
+ /* FBL only supports UD type for dst. */
+ brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
+ break;
+ case BRW_OPCODE_CBIT:
+ /* CBIT only supports UD type for dst. */
+ brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
+ break;
+
+ case BRW_OPCODE_BFE:
+ brw_BFE(p, dst, src[0], src[1], src[2]);
+ break;
+
+ case BRW_OPCODE_BFI1:
+ brw_BFI1(p, dst, src[0], src[1]);
+ break;
+ case BRW_OPCODE_BFI2:
+ brw_BFI2(p, dst, src[0], src[1], src[2]);
+ break;
+
case BRW_OPCODE_IF:
if (inst-src[0].file != BAD_FILE) {
/* The instruction has an embedded compare (only allowed on gen6) */
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 2fb8482..d46c3f7 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -107,6 +107,14 @@ vec4_visitor::emit(enum opcode opcode)
src0, src1); \
}
+#define ALU3(op) \
+ vec4_instruction * \
+ vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1, src_reg src2)\
+ { \
+ return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
+ src0, src1, src2); \
+ }
+
ALU1(NOT)
ALU1(MOV)
ALU1(FRC)
@@ -127,6 +135,13 @@ ALU2(DPH)
ALU2(SHL)
ALU2(SHR)
ALU2(ASR)
+ALU1(BFREV)
+ALU3(BFE)
+ALU2(BFI1)
+ALU3(BFI2)
+ALU1(FBH)
+ALU1(FBL)
+ALU1(CBIT)
/** Gen4 predicated IF. */
vec4_instruction *
@@ -1350,6 +1365,19 @@ vec4_visitor::visit(ir_expression *ir)
assert(!derivatives not valid in vertex shader);
break;
+ case ir_unop_bitfield_reverse:
+ emit(BFREV(result_dst, op[0]));
+ break;
+ case ir_unop_bit_count:
+ emit(CBIT(result_dst, op[0]));
+ break;
+ case ir_unop_find_msb:
+ emit(FBH(result_dst, op[0]));
+ break;
+ case ir_unop_find_lsb:
+ emit(FBL(result_dst, op[0]));
+ break;
+
case ir_unop_noise:
assert(!not reached: should be handled by lower_noise);
break;
@@ -1550,6 +1578,10 @@ vec4_visitor::visit(ir_expression *ir)
inst = emit(SHR(result_dst, op[0], op[1]));
break;
+ case ir_binop_bfm:
+ emit(BFI1(result_dst, op[0], op[1]));
+ break;
+
case ir_binop_ubo_load: {
ir_constant *uniform_block = ir-operands[0]-as_constant();
ir_constant *const_offset_ir = ir-operands[1]-as_constant();
@@ -1599,6 +1631,22 @@ vec4_visitor::visit(ir_expression *ir)
assert(!not reached: should be handled by lrp_to_arith);
break;
+ case ir_triop_bfi:
+ emit(BFI2(result_dst, op[0], op[1], op[2]));
+
[Mesa-dev] [PATCH 15/16] i965: Lower bitfieldExtract and bitfieldInsert.
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 14 ++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index b3bd1b9..15a0440 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -151,6 +151,20 @@ brw_link_shader(struct gl_context *ctx, struct
gl_shader_program *shProg)
* must precede lower_instructions().
*/
brw_lower_packing_builtins(brw, (gl_shader_type) stage, shader-ir);
+
+ /* bitfield lowering passes insert subtraction instructions which need
+ * to be lowered, so it must precede lower_instructions(SUB_TO_ADD_NEG).
+ */
+ int bfe_to_bitops = 0, bitfield_insert = 0;
+ if (intel-gen = 7) {
+ bfe_to_bitops = stage != MESA_SHADER_FRAGMENT
+ ? BFE_TO_BITOPS : 0;
+ bitfield_insert = stage != MESA_SHADER_FRAGMENT
+ ? BITFIELD_INSERT_TO_BFM_BITOPS
+ : BITFIELD_INSERT_TO_BFM_BFI;
+ }
+ lower_instructions(shader-ir, bfe_to_bitops | bitfield_insert);
+
do_mat_op_to_vec(shader-ir);
const int lrp_to_arith = (intel-gen 6 || stage !=
MESA_SHADER_FRAGMENT)
? LRP_TO_ARITH : 0;
--
1.7.8.6
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[Mesa-dev] [PATCH 16/16] i965: Print the correct dst and shared-src types for 3-src instructions.
---
src/mesa/drivers/dri/i965/brw_disasm.c | 26 ++
1 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c
b/src/mesa/drivers/dri/i965/brw_disasm.c
index 0b881b7..556e63a 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -468,6 +468,19 @@ static int print_opcode (FILE *file, int id)
return 0;
}
+static int three_source_type_to_reg_type(int three_source_type)
+{
+ switch (three_source_type) {
+ case BRW_3SRC_TYPE_F:
+ return BRW_REGISTER_TYPE_F;
+ case BRW_3SRC_TYPE_D:
+ return BRW_REGISTER_TYPE_D;
+ case BRW_3SRC_TYPE_UD:
+ return BRW_REGISTER_TYPE_UD;
+ }
+ return -1;
+}
+
static int reg (FILE *file, GLuint _reg_file, GLuint _reg_nr)
{
interr = 0;
@@ -594,7 +607,9 @@ static int dest_3src (FILE *file, struct brw_instruction
*inst)
format (file, .%d, inst-bits1.da3src.dest_subreg_nr);
string (file, 1);
err |= control (file, writemask, writemask,
inst-bits1.da3src.dest_writemask, NULL);
-err |= control (file, dest reg encoding, reg_encoding,
BRW_REGISTER_TYPE_F, NULL);
+err |= control (file, dest reg encoding, reg_encoding,
+three_source_type_to_reg_type(inst-bits1.da3src.dst_type),
+NULL);
return 0;
}
@@ -733,7 +748,8 @@ static int src0_3src (FILE *file, struct brw_instruction
*inst)
format (file, .%d, inst-bits2.da3src.src0_subreg_nr);
string (file, 4,1,1);
err |= control (file, src da16 reg type, reg_encoding,
- BRW_REGISTER_TYPE_F, NULL);
+three_source_type_to_reg_type(inst-bits1.da3src.src_type),
+NULL);
/*
* Three kinds of swizzle display:
* identity - nothing printed
@@ -785,7 +801,8 @@ static int src1_3src (FILE *file, struct brw_instruction
*inst)
format (file, .%d, src1_subreg_nr);
string (file, 4,1,1);
err |= control (file, src da16 reg type, reg_encoding,
- BRW_REGISTER_TYPE_F, NULL);
+three_source_type_to_reg_type(inst-bits1.da3src.src_type),
+NULL);
/*
* Three kinds of swizzle display:
* identity - nothing printed
@@ -836,7 +853,8 @@ static int src2_3src (FILE *file, struct brw_instruction
*inst)
format (file, .%d, inst-bits3.da3src.src2_subreg_nr);
string (file, 4,1,1);
err |= control (file, src da16 reg type, reg_encoding,
- BRW_REGISTER_TYPE_F, NULL);
+three_source_type_to_reg_type(inst-bits1.da3src.src_type),
+NULL);
/*
* Three kinds of swizzle display:
* identity - nothing printed
--
1.7.8.6
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[Mesa-dev] [PATCH 2/2] i965: Remove strange comments about math functions.
---
Do these comments make sense to anyone else?
src/mesa/drivers/dri/i965/brw_defines.h |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index ea5d2af..6517f24 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1034,9 +1034,9 @@ enum brw_message_target {
#define BRW_MATH_FUNCTION_EXP 3
#define BRW_MATH_FUNCTION_SQRT 4
#define BRW_MATH_FUNCTION_RSQ 5
-#define BRW_MATH_FUNCTION_SIN 6 /* was 7 */
-#define BRW_MATH_FUNCTION_COS 7 /* was 8 */
-#define BRW_MATH_FUNCTION_SINCOS 8 /* was 6 */
+#define BRW_MATH_FUNCTION_SIN 6
+#define BRW_MATH_FUNCTION_COS 7
+#define BRW_MATH_FUNCTION_SINCOS 8 /* gen4, gen5 */
#define BRW_MATH_FUNCTION_FDIV 9 /* gen6+ */
#define BRW_MATH_FUNCTION_POW 10
#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11
--
1.7.8.6
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Re: [Mesa-dev] [PATCH 2/2] glsl: Teach basic block analysis about break/continue/discard.
On Tue, Apr 23, 2013 at 10:25 AM, Paul Berry stereotype...@gmail.com wrote:
Previously, the only kind of ir_jump that would terminate a basic
block was return. However, the other possible types of ir_jump
(break, continue, and discard) should terminate a basic block
too. This patch modifies basic block analysis so that it terminates a
basic block on any type of ir_jump, not just ir_return.
Fixes piglit test dead-code-break-interaction.shader_test.
---
src/glsl/ir_basic_block.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/glsl/ir_basic_block.cpp b/src/glsl/ir_basic_block.cpp
index 86e0cf7..2cbc682 100644
--- a/src/glsl/ir_basic_block.cpp
+++ b/src/glsl/ir_basic_block.cpp
@@ -77,7 +77,7 @@ void call_for_basic_blocks(exec_list *instructions,
callback(leader, ir, data);
leader = NULL;
call_for_basic_blocks(ir_loop-body_instructions, callback, data);
- } else if (ir-as_return() || ir-as_call()) {
+ } else if (ir-as_jump() || ir-as_call()) {
callback(leader, ir, data);
leader = NULL;
} else if ((ir_function = ir-as_function())) {
--
1.8.2.1
Series is Reviewed-by: Matt Turner matts...@gmail.com
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Re: [Mesa-dev] [PATCH 04/16] glsl: Add support for new bit built-ins in ARB_gpu_shader5.
On Mon, Apr 22, 2013 at 6:33 PM, Chris Forbes chr...@ijw.co.nz wrote: In the last hunk: + case ir_binop_bfm: + case ir_triop_bfi: These look like leftovers? -- Chris Yes, good call. I've moved them to later in the series where they're actually added (glsl: Add a pass to lower bitfield-insert into bfm+bfi.) ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 06/16] glsl: Add a pass to lower bitfield-insert into bfm+bfi.
On Tue, Apr 23, 2013 at 2:23 AM, Chris Forbes chr...@ijw.co.nz wrote: + /* Save op0 */ + ir_variable *temp = new(ir) ir_variable(ir-operands[0]- type, bfi_base, + ir_var_temporary); + this-base_ir-insert_before(temp); + this-base_ir-insert_before(assign(temp, ir-operands[0])); + + ir-operation = ir_triop_bfi; + ir-operands[0] = new(ir) ir_expression(ir_binop_bfm, ir-type, + swizzle_(ir-operands[3]), + swizzle_(ir-operands[2])); + /* ir-operands[1] is still the value to insert. */ + ir-operands[2] = new(ir) ir_dereference_variable(temp); + ir-operands[3] = NULL; Emitting the temp and assignment to it into the IR seems spurious -- is there a reason something like this doesn't work:? ir_rvalue *base_expr = ir-operands[0]; ir-operation = ir_triop_bfi; ir-operands[0] = new(ir) ir_expression(ir_binop_bfm, ir-type, swizzle_(ir-operands[3]), swizzle_(ir-operands[2])); /* ir-operands[1] is still the value to insert. */ ir-operands[2] = base_expr; ir-operands[3] = NULL; I might have missed something :) -- Chris Yes, that is much simpler. I'd just copied the lrp_to_arith function to begin with, but it actually has a reason to create a temporary and do the assignment: it uses the temporary multiple times. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] i965/vs: Add a function to fix-up uniform arguments for 3-src insts.
Three-source instructions have a vertical stride overloaded to 4, which
prevents directly using vec4 uniforms as arguments. Instead we need to
insert a MOV instruction to do the replication for the three-source
instruction.
With this in place, we can use three-source instructions in the vertex
shader. While some thought needs to go into deciding whether its better
to use a three-source instruction rather than a sequence of equivalent
instructions (when one or more sources are uniforms or immediates), this
will allow us to skip a lot of ugly lowering code and use the BFE and
BFI2 instructions directly.
---
These patches should go before my ARB_gpu_shader5 series, and allow me to
drop
[PATCH 07/16] glsl: Add bitfieldInsert-to-bfm/bitops lowering pass.
[PATCH 08/16] glsl: Add BFE-to-bitops lowering pass.
src/mesa/drivers/dri/i965/brw_vec4.h | 2 ++
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 23 +++
2 files changed, 25 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 697ab86..c280922 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -430,6 +430,8 @@ public:
void emit_scs(ir_instruction *ir, enum prog_opcode op,
dst_reg dst, const src_reg src);
+ src_reg fix_3src_operand(src_reg src);
+
void emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src);
void emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src);
void emit_math(enum opcode opcode, dst_reg dst, src_reg src);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 2fb8482..69e805d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -224,6 +224,29 @@ vec4_visitor::emit_dp(dst_reg dst, src_reg src0, src_reg
src1, unsigned elements
}
src_reg
+vec4_visitor::fix_3src_operand(src_reg src)
+{
+ /* Using vec4 uniforms in SIMD4x2 programs is difficult. You'd like to be
+* able to use vertical stride of zero to replicate the vec4 uniform, like
+*
+*g30;4,1:f - [0, 4][1, 5][2, 6][3, 7]
+*
+* But you can't, since vertical stride is always four in three-source
+* instructions. Instead, insert a MOV instruction to do the replication so
+* that the three-source instruction can consume it.
+*/
+
+ /* The MOV is only needed if the source is a uniform or immediate. */
+ if (src.file != UNIFORM src.file != IMM)
+ return src;
+
+ dst_reg expanded = dst_reg(this, glsl_type::vec4_type);
+ expanded.type = src.type;
+ emit(MOV(expanded, src));
+ return src_reg(expanded);
+}
+
+src_reg
vec4_visitor::fix_math_operand(src_reg src)
{
/* The gen6 math instruction ignores the source modifiers --
--
1.8.1.5
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[Mesa-dev] [PATCH 2/2] i965/vs: Add support for LRP instruction.
Only 13 affected programs in shader-db, but they were all helped.
total instructions in shared programs: 368877 - 368851 (-0.01%)
instructions in affected programs: 1576 - 1550 (-1.65%)
---
src/mesa/drivers/dri/i965/brw_shader.cpp| 3 +--
src/mesa/drivers/dri/i965/brw_vec4.h| 1 +
src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp | 3 +++
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp | 4
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 14 +-
5 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index b3bd1b9..5addff6 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -152,8 +152,7 @@ brw_link_shader(struct gl_context *ctx, struct
gl_shader_program *shProg)
*/
brw_lower_packing_builtins(brw, (gl_shader_type) stage, shader-ir);
do_mat_op_to_vec(shader-ir);
- const int lrp_to_arith = (intel-gen 6 || stage !=
MESA_SHADER_FRAGMENT)
-? LRP_TO_ARITH : 0;
+ const int lrp_to_arith = intel-gen 6 ? LRP_TO_ARITH : 0;
lower_instructions(shader-ir,
MOD_TO_FRACT |
DIV_TO_MUL_RCP |
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index c280922..d34ed35 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -386,6 +386,7 @@ public:
vec4_instruction *PULL_CONSTANT_LOAD(dst_reg dst, src_reg index);
vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
+ vec4_instruction *LRP(dst_reg dst, src_reg a, src_reg y, src_reg x);
int implied_mrf_writes(vec4_instruction *inst);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
index 51ee475..f2c6cd6 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
@@ -215,6 +215,9 @@ vec4_visitor::try_copy_propagation(struct intel_context
*intel,
if (has_source_modifiers !can_do_source_mods(inst))
return false;
+ if (inst-opcode == BRW_OPCODE_LRP value.file == UNIFORM)
+ return false;
+
/* We can't copy-propagate a UD negation into a condmod
* instruction, because the condmod ends up looking at the 33-bit
* signed accumulator value instead of the 32-bit value we wanted
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index c9963bf..96b4965 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -838,6 +838,10 @@ vec4_generator::generate_code(exec_list *instructions)
brw_F16TO32(p, dst, src[0]);
break;
+ case BRW_OPCODE_LRP:
+ brw_LRP(p, dst, src[0], src[1], src[2]);
+ break;
+
case BRW_OPCODE_IF:
if (inst-src[0].file != BAD_FILE) {
/* The instruction has an embedded compare (only allowed on gen6) */
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 69e805d..88c435c 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -107,6 +107,14 @@ vec4_visitor::emit(enum opcode opcode)
src0, src1); \
}
+#define ALU3(op) \
+ vec4_instruction * \
+ vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1, src_reg src2)\
+ { \
+ return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
+ src0, src1, src2); \
+ }
+
ALU1(NOT)
ALU1(MOV)
ALU1(FRC)
@@ -127,6 +135,7 @@ ALU2(DPH)
ALU2(SHL)
ALU2(SHR)
ALU2(ASR)
+ALU3(LRP)
/** Gen4 predicated IF. */
vec4_instruction *
@@ -1619,7 +1628,10 @@ vec4_visitor::visit(ir_expression *ir)
}
case ir_triop_lrp:
- assert(!not reached: should be handled by lrp_to_arith);
+ op[0] = fix_3src_operand(op[0]);
+ op[1] = fix_3src_operand(op[1]);
+ op[2] = fix_3src_operand(op[2]);
+ emit(LRP(result_dst, op[0], op[1], op[2]));
break;
case ir_quadop_vector:
--
1.8.1.5
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Re: [Mesa-dev] [PATCH 16/16] i965: Print the correct dst and shared-src types for 3-src instructions.
On Tue, Apr 23, 2013 at 3:42 AM, Chris Forbes chr...@ijw.co.nz wrote: Would it make more sense to move this patch just before or after patch 11, so the disassembly is correct from the moment you start emitting these? Yes, good idea. I've moved it immediately after patch 11, i965/gen7: Set src/dst types for 3-src instructions. With that change, do I get a R-b? :) ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/6] configure.ac: Remove unused HAVE_PIPE_LOADER_XLIB macro.
Added in e1364530 but never used. --- configure.ac |1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/configure.ac b/configure.ac index 50e60f6..55ea13d 100644 --- a/configure.ac +++ b/configure.ac @@ -1899,7 +1899,6 @@ if test x$enable_gallium_loader = xyes; then GALLIUM_PIPE_LOADER_LIBS=$GALLIUM_PIPE_LOADER_LIBS \$(top_builddir)/src/gallium/winsys/sw/null/libws_null.la if test x$NEED_WINSYS_XLIB = xyes; then -GALLIUM_PIPE_LOADER_DEFINES=$GALLIUM_PIPE_LOADER_DEFINES -DHAVE_PIPE_LOADER_XLIB GALLIUM_PIPE_LOADER_LIBS=$GALLIUM_PIPE_LOADER_LIBS \$(top_builddir)/src/gallium/winsys/sw/xlib/libws_xlib.la fi -- 1.7.8.6 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/6] build: Rename PIPE_LOADER_HAVE_XCB to HAVE_PIPE_LOADER_XCB.
For consistency, since we already have HAVE_PIPE_LOADER_{SW,DRM}.
---
configure.ac |2 +-
.../auxiliary/pipe-loader/pipe_loader_drm.c|4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/configure.ac b/configure.ac
index 55ea13d..25e6518 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1907,7 +1907,7 @@ if test x$enable_gallium_loader = xyes; then
PKG_CHECK_MODULES([GALLIUM_PIPE_LOADER_XCB], [xcb xcb-dri2],
pipe_loader_have_xcb=yes, pipe_loader_have_xcb=no)
if test x$pipe_loader_have_xcb = xyes; then
-GALLIUM_PIPE_LOADER_DEFINES=$GALLIUM_PIPE_LOADER_DEFINES
-DPIPE_LOADER_HAVE_XCB
+GALLIUM_PIPE_LOADER_DEFINES=$GALLIUM_PIPE_LOADER_DEFINES
-DHAVE_PIPE_LOADER_XCB
GALLIUM_PIPE_LOADER_LIBS=$GALLIUM_PIPE_LOADER_LIBS
$GALLIUM_PIPE_LOADER_XCB_LIBS $LIBDRM_LIBS
fi
fi
diff --git a/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
b/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
index 6dedc41..339d7bf 100644
--- a/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
+++ b/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
@@ -35,7 +35,7 @@
#include libudev.h
#include xf86drm.h
-#ifdef PIPE_LOADER_HAVE_XCB
+#ifdef HAVE_PIPE_LOADER_XCB
#include xcb/dri2.h
@@ -133,7 +133,7 @@ static struct pipe_loader_ops pipe_loader_drm_ops;
static void
pipe_loader_drm_x_auth(int fd)
{
-#if PIPE_LOADER_HAVE_XCB
+#if HAVE_PIPE_LOADER_XCB
/* Try authenticate with the X server to give us access to devices that X
* is running on. */
xcb_connection_t *xcb_conn;
--
1.7.8.6
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[Mesa-dev] [PATCH 3/6] build: Remove libws_null.la from GALLIUM_PIPE_LOADER_LIBS.
--- configure.ac |1 - src/gallium/targets/gbm/Makefile.am|1 + src/gallium/targets/opencl/Makefile.am |1 + src/gallium/tests/trivial/Makefile.am |1 + 4 files changed, 3 insertions(+), 1 deletions(-) diff --git a/configure.ac b/configure.ac index 25e6518..7b37279 100644 --- a/configure.ac +++ b/configure.ac @@ -1896,7 +1896,6 @@ if test x$enable_gallium_loader = xyes; then GALLIUM_WINSYS_DIRS=$GALLIUM_WINSYS_DIRS sw/null GALLIUM_PIPE_LOADER_DEFINES=-DHAVE_PIPE_LOADER_SW GALLIUM_PIPE_LOADER_LIBS=\$(top_builddir)/src/gallium/auxiliary/pipe-loader/libpipe_loader.la -GALLIUM_PIPE_LOADER_LIBS=$GALLIUM_PIPE_LOADER_LIBS \$(top_builddir)/src/gallium/winsys/sw/null/libws_null.la if test x$NEED_WINSYS_XLIB = xyes; then GALLIUM_PIPE_LOADER_LIBS=$GALLIUM_PIPE_LOADER_LIBS \$(top_builddir)/src/gallium/winsys/sw/xlib/libws_xlib.la diff --git a/src/gallium/targets/gbm/Makefile.am b/src/gallium/targets/gbm/Makefile.am index 278e4fa..ee66f9d 100644 --- a/src/gallium/targets/gbm/Makefile.am +++ b/src/gallium/targets/gbm/Makefile.am @@ -43,6 +43,7 @@ gbm_gallium_drm_la_SOURCES = gbm.c gbm_gallium_drm_la_LIBADD = \ $(GALLIUM_PIPE_LOADER_LIBS) \ + $(top_builddir)/src/gallium/winsys/sw/null/libws_null.la \ $(top_builddir)/src/gallium/state_trackers/gbm/libgbm.la \ $(top_builddir)/src/gallium/auxiliary/libgallium.la \ $(LIBUDEV_LIBS) \ diff --git a/src/gallium/targets/opencl/Makefile.am b/src/gallium/targets/opencl/Makefile.am index 4b77d0a..9947aec 100644 --- a/src/gallium/targets/opencl/Makefile.am +++ b/src/gallium/targets/opencl/Makefile.am @@ -7,6 +7,7 @@ libOpenCL_la_LDFLAGS = \ -version-number 1:0 libOpenCL_la_LIBADD = \ + $(top_builddir)/src/gallium/winsys/sw/null/libws_null.la \ $(top_builddir)/src/gallium/state_trackers/clover/libclover.la \ $(top_builddir)/src/gallium/auxiliary/libgallium.la \ $(GALLIUM_PIPE_LOADER_LIBS) $(LIBUDEV_LIBS) \ diff --git a/src/gallium/tests/trivial/Makefile.am b/src/gallium/tests/trivial/Makefile.am index 705a878..6f34d3b 100644 --- a/src/gallium/tests/trivial/Makefile.am +++ b/src/gallium/tests/trivial/Makefile.am @@ -12,6 +12,7 @@ AM_CPPFLAGS = \ $(GALLIUM_PIPE_LOADER_DEFINES) LDADD = $(GALLIUM_PIPE_LOADER_LIBS) \ + $(top_builddir)/src/gallium/winsys/sw/null/libws_null.la \ $(top_builddir)/src/gallium/auxiliary/libgallium.la \ $(LIBUDEV_LIBS) \ $(DLOPEN_LIBS) \ -- 1.7.8.6 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 4/6] build: Remove HAVE_PIPE_LOADER_SW.
It guarded the function prototype of pipe_loader_sw_probe, whose use (in pipe_loader.c) and definition (in pipe_loader_sw.c) were not guarded. Both are built into libpipe_loader.la if HAVE_LOADER_GALLIUM, which is enable_gallium_loader in configure.ac. --- configure.ac|1 - src/gallium/auxiliary/pipe-loader/pipe_loader.h |4 2 files changed, 0 insertions(+), 5 deletions(-) diff --git a/configure.ac b/configure.ac index 7b37279..ad6dc24 100644 --- a/configure.ac +++ b/configure.ac @@ -1894,7 +1894,6 @@ AM_CONDITIONAL(NEED_GALLIUM_LLVMPIPE_DRIVER, test x$HAVE_GALLIUM_I915 = xyes - if test x$enable_gallium_loader = xyes; then GALLIUM_WINSYS_DIRS=$GALLIUM_WINSYS_DIRS sw/null -GALLIUM_PIPE_LOADER_DEFINES=-DHAVE_PIPE_LOADER_SW GALLIUM_PIPE_LOADER_LIBS=\$(top_builddir)/src/gallium/auxiliary/pipe-loader/libpipe_loader.la if test x$NEED_WINSYS_XLIB = xyes; then diff --git a/src/gallium/auxiliary/pipe-loader/pipe_loader.h b/src/gallium/auxiliary/pipe-loader/pipe_loader.h index 21a609f..444bdf1 100644 --- a/src/gallium/auxiliary/pipe-loader/pipe_loader.h +++ b/src/gallium/auxiliary/pipe-loader/pipe_loader.h @@ -99,8 +99,6 @@ pipe_loader_create_screen(struct pipe_loader_device *dev, void pipe_loader_release(struct pipe_loader_device **devs, int ndev); -#ifdef HAVE_PIPE_LOADER_SW - /** * Get a list of known software devices. * @@ -111,8 +109,6 @@ pipe_loader_release(struct pipe_loader_device **devs, int ndev); int pipe_loader_sw_probe(struct pipe_loader_device **devs, int ndev); -#endif - #ifdef HAVE_PIPE_LOADER_DRM /** -- 1.7.8.6 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 5/6] build: Remove libpipe_loader.la from GALLIUM_PIPE_LOADER_LIBS.
--- configure.ac |1 - src/gallium/targets/gbm/Makefile.am|1 + src/gallium/targets/opencl/Makefile.am |1 + src/gallium/tests/trivial/Makefile.am |1 + 4 files changed, 3 insertions(+), 1 deletions(-) diff --git a/configure.ac b/configure.ac index ad6dc24..0d79c32 100644 --- a/configure.ac +++ b/configure.ac @@ -1894,7 +1894,6 @@ AM_CONDITIONAL(NEED_GALLIUM_LLVMPIPE_DRIVER, test x$HAVE_GALLIUM_I915 = xyes - if test x$enable_gallium_loader = xyes; then GALLIUM_WINSYS_DIRS=$GALLIUM_WINSYS_DIRS sw/null - GALLIUM_PIPE_LOADER_LIBS=\$(top_builddir)/src/gallium/auxiliary/pipe-loader/libpipe_loader.la if test x$NEED_WINSYS_XLIB = xyes; then GALLIUM_PIPE_LOADER_LIBS=$GALLIUM_PIPE_LOADER_LIBS \$(top_builddir)/src/gallium/winsys/sw/xlib/libws_xlib.la diff --git a/src/gallium/targets/gbm/Makefile.am b/src/gallium/targets/gbm/Makefile.am index ee66f9d..4299d07 100644 --- a/src/gallium/targets/gbm/Makefile.am +++ b/src/gallium/targets/gbm/Makefile.am @@ -43,6 +43,7 @@ gbm_gallium_drm_la_SOURCES = gbm.c gbm_gallium_drm_la_LIBADD = \ $(GALLIUM_PIPE_LOADER_LIBS) \ + $(top_builddir)/src/gallium/auxiliary/pipe-loader/libpipe_loader.la \ $(top_builddir)/src/gallium/winsys/sw/null/libws_null.la \ $(top_builddir)/src/gallium/state_trackers/gbm/libgbm.la \ $(top_builddir)/src/gallium/auxiliary/libgallium.la \ diff --git a/src/gallium/targets/opencl/Makefile.am b/src/gallium/targets/opencl/Makefile.am index 9947aec..46bb29f 100644 --- a/src/gallium/targets/opencl/Makefile.am +++ b/src/gallium/targets/opencl/Makefile.am @@ -7,6 +7,7 @@ libOpenCL_la_LDFLAGS = \ -version-number 1:0 libOpenCL_la_LIBADD = \ + $(top_builddir)/src/gallium/auxiliary/pipe-loader/libpipe_loader.la \ $(top_builddir)/src/gallium/winsys/sw/null/libws_null.la \ $(top_builddir)/src/gallium/state_trackers/clover/libclover.la \ $(top_builddir)/src/gallium/auxiliary/libgallium.la \ diff --git a/src/gallium/tests/trivial/Makefile.am b/src/gallium/tests/trivial/Makefile.am index 6f34d3b..d65eb86 100644 --- a/src/gallium/tests/trivial/Makefile.am +++ b/src/gallium/tests/trivial/Makefile.am @@ -12,6 +12,7 @@ AM_CPPFLAGS = \ $(GALLIUM_PIPE_LOADER_DEFINES) LDADD = $(GALLIUM_PIPE_LOADER_LIBS) \ + $(top_builddir)/src/gallium/auxiliary/pipe-loader/libpipe_loader.la \ $(top_builddir)/src/gallium/winsys/sw/null/libws_null.la \ $(top_builddir)/src/gallium/auxiliary/libgallium.la \ $(LIBUDEV_LIBS) \ -- 1.7.8.6 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 6/6] build: Remove libws_xlib.la from GALLIUM_PIPE_LOADER_LIBS.
The three users of GALLIUM_PIPE_LOADER_LIBS (OpenCL, gallium-gbm, gallium tests) don't appear to need libws_xlib.la. --- Seems weird that this wasn't actually needed, but I tested by adding -Wl,--no-undefined to each Makefile.am that uses GALLIUM_PIPE_LOADER_LIBS (opencl, tests, and gallium-gbm). Maybe I'm wrong? configure.ac |4 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/configure.ac b/configure.ac index 0d79c32..d22901e 100644 --- a/configure.ac +++ b/configure.ac @@ -1895,10 +1895,6 @@ AM_CONDITIONAL(NEED_GALLIUM_LLVMPIPE_DRIVER, test x$HAVE_GALLIUM_I915 = xyes - if test x$enable_gallium_loader = xyes; then GALLIUM_WINSYS_DIRS=$GALLIUM_WINSYS_DIRS sw/null -if test x$NEED_WINSYS_XLIB = xyes; then -GALLIUM_PIPE_LOADER_LIBS=$GALLIUM_PIPE_LOADER_LIBS \$(top_builddir)/src/gallium/winsys/sw/xlib/libws_xlib.la -fi - if test x$enable_gallium_drm_loader = xyes; then GALLIUM_PIPE_LOADER_DEFINES=$GALLIUM_PIPE_LOADER_DEFINES -DHAVE_PIPE_LOADER_DRM PKG_CHECK_MODULES([GALLIUM_PIPE_LOADER_XCB], [xcb xcb-dri2], -- 1.7.8.6 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/fs: Allow LRPs with uniform registers.
On Thu, Apr 25, 2013 at 9:06 PM, Eric Anholt e...@anholt.net wrote:
Improves GLB2.7 performance on my HSW by 0.671455% +/- 0.225037% (n=62).
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index f1539d5..8aae516 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -198,10 +198,19 @@ fs_visitor::visit(ir_dereference_array *ir)
this-result = src;
}
+static bool
+is_valid_3src(fs_reg reg)
+{
+ return reg.file == GRF || reg.file == UNIFORM;
+}
+
void
fs_visitor::emit_lrp(fs_reg dst, fs_reg x, fs_reg y, fs_reg a)
{
- if (intel-gen 6 || x.file != GRF || y.file != GRF || a.file != GRF) {
+ if (intel-gen 6 ||
+ !is_valid_3src(x) ||
+ !is_valid_3src(y) ||
+ !is_valid_3src(a)) {
/* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
fs_reg y_times_a = fs_reg(this, glsl_type::float_type);
fs_reg one_minus_a = fs_reg(this, glsl_type::float_type);
--
1.7.10.4
Reviewed-by: Matt Turner matts...@gmail.com
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[Mesa-dev] [PATCH 04/14] glsl: Add support for new bit built-ins in ARB_gpu_shader5.
v2: Move use of ir_binop_bfm and ir_triop_bfi to a later patch.
---
src/glsl/ir.cpp| 8 +++-
src/glsl/ir.h | 21 -
src/glsl/ir_validate.cpp | 26 ++
src/glsl/opt_algebraic.cpp | 6 +++---
src/mesa/program/ir_to_mesa.cpp| 9 +
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 6 ++
6 files changed, 71 insertions(+), 5 deletions(-)
diff --git a/src/glsl/ir.cpp b/src/glsl/ir.cpp
index 05b77da..2c989c9 100644
--- a/src/glsl/ir.cpp
+++ b/src/glsl/ir.cpp
@@ -419,7 +419,7 @@ ir_expression::get_num_operands(ir_expression_operation op)
if (op = ir_last_triop)
return 3;
- if (op == ir_quadop_vector)
+ if (op = ir_last_quadop)
return 4;
assert(false);
@@ -477,6 +477,10 @@ static const char *const operator_strs[] = {
unpackHalf2x16,
unpackHalf2x16_split_x,
unpackHalf2x16_split_y,
+ bitfield_reverse,
+ bit_count,
+ find_msb,
+ find_lsb,
noise,
+,
-,
@@ -506,6 +510,8 @@ static const char *const operator_strs[] = {
packHalf2x16_split,
ubo_load,
lrp,
+ bitfield_extract,
+ bitfield_insert,
vector,
};
diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index 878a946..470c08c 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -1033,6 +1033,16 @@ enum ir_expression_operation {
ir_unop_unpack_half_2x16_split_y,
/*@}*/
+ /**
+* \name Bit operations, part of ARB_gpu_shader5.
+*/
+ /*@{*/
+ ir_unop_bitfield_reverse,
+ ir_unop_bit_count,
+ ir_unop_find_msb,
+ ir_unop_find_lsb,
+ /*@}*/
+
ir_unop_noise,
/**
@@ -1123,14 +1133,23 @@ enum ir_expression_operation {
ir_triop_lrp,
+ ir_triop_bitfield_extract,
+
/**
* A sentinel marking the last of the ternary operations.
*/
- ir_last_triop = ir_triop_lrp,
+ ir_last_triop = ir_triop_bitfield_extract,
+
+ ir_quadop_bitfield_insert,
ir_quadop_vector,
/**
+* A sentinel marking the last of the ternary operations.
+*/
+ ir_last_quadop = ir_quadop_vector,
+
+ /**
* A sentinel marking the last of all operations.
*/
ir_last_opcode = ir_quadop_vector
diff --git a/src/glsl/ir_validate.cpp b/src/glsl/ir_validate.cpp
index 699c192..4a8df69 100644
--- a/src/glsl/ir_validate.cpp
+++ b/src/glsl/ir_validate.cpp
@@ -361,6 +361,19 @@ ir_validate::visit_leave(ir_expression *ir)
assert(ir-operands[0]-type == glsl_type::uint_type);
break;
+ case ir_unop_bitfield_reverse:
+ assert(ir-operands[0]-type == ir-type);
+ assert(ir-type-is_integer());
+ break;
+
+ case ir_unop_bit_count:
+ case ir_unop_find_msb:
+ case ir_unop_find_lsb:
+ assert(ir-operands[0]-type-vector_elements ==
ir-type-vector_elements);
+ assert(ir-operands[0]-type-is_integer());
+ assert(ir-type-base_type == GLSL_TYPE_INT);
+ break;
+
case ir_unop_noise:
/* XXX what can we assert here? */
break;
@@ -474,6 +487,19 @@ ir_validate::visit_leave(ir_expression *ir)
assert(ir-operands[2]-type == ir-operands[0]-type ||
ir-operands[2]-type == glsl_type::float_type);
break;
+ case ir_triop_bitfield_extract:
+ assert(ir-operands[0]-type == ir-type);
+ assert(ir-operands[1]-type == glsl_type::int_type);
+ assert(ir-operands[2]-type == glsl_type::int_type);
+ break;
+
+ case ir_quadop_bitfield_insert:
+ assert(ir-operands[0]-type == ir-type);
+ assert(ir-operands[1]-type == ir-type);
+ assert(ir-operands[2]-type == glsl_type::int_type);
+ assert(ir-operands[3]-type == glsl_type::int_type);
+ break;
+
case ir_quadop_vector:
/* The vector operator collects some number of scalars and generates a
* vector from them.
diff --git a/src/glsl/opt_algebraic.cpp b/src/glsl/opt_algebraic.cpp
index 70e016d..d706a6a 100644
--- a/src/glsl/opt_algebraic.cpp
+++ b/src/glsl/opt_algebraic.cpp
@@ -186,12 +186,12 @@ ir_algebraic_visitor::swizzle_if_required(ir_expression
*expr,
ir_rvalue *
ir_algebraic_visitor::handle_expression(ir_expression *ir)
{
- ir_constant *op_const[3] = {NULL, NULL, NULL};
- ir_expression *op_expr[3] = {NULL, NULL, NULL};
+ ir_constant *op_const[4] = {NULL, NULL, NULL, NULL};
+ ir_expression *op_expr[4] = {NULL, NULL, NULL, NULL};
ir_expression *temp;
unsigned int i;
- assert(ir-get_num_operands() = 3);
+ assert(ir-get_num_operands() = 4);
for (i = 0; i ir-get_num_operands(); i++) {
if (ir-operands[i]-type-is_matrix())
return ir;
diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp
index 14cf5ba..c6f6bf4 100644
--- a/src/mesa/program/ir_to_mesa.cpp
+++ b/src/mesa/program/ir_to_mesa.cpp
@@ -1444,6 +1444,10 @@ ir_to_mesa_visitor::visit(ir_expression *ir)
case ir_unop_unpack_half_2x16_split_x:
case ir_unop_unpack_half_2x16_split_y:
case ir_binop_pack_half_2x16_split:
+
[Mesa-dev] [PATCH 05/14] glsl: Add constant evaluation of bit built-ins.
v2: Order bits from LSB end (31 - count) for ir_unop_find_msb.
---
src/glsl/ir_constant_expression.cpp | 123
1 file changed, 123 insertions(+)
diff --git a/src/glsl/ir_constant_expression.cpp
b/src/glsl/ir_constant_expression.cpp
index c09e56a..66b0a64 100644
--- a/src/glsl/ir_constant_expression.cpp
+++ b/src/glsl/ir_constant_expression.cpp
@@ -1248,6 +1248,102 @@ ir_expression::constant_expression_value(struct
hash_table *variable_context)
}
break;
+ case ir_unop_bitfield_reverse:
+ /* http://graphics.stanford.edu/~seander/bithacks.html#BitReverseObvious
*/
+ for (unsigned c = 0; c components; c++) {
+ unsigned int v = op[0]-value.u[c]; // input bits to be reversed
+ unsigned int r = v; // r will be reversed bits of v; first get LSB of
v
+ int s = sizeof(v) * CHAR_BIT - 1; // extra shift needed at end
+
+ for (v = 1; v; v = 1) {
+r = 1;
+r |= v 1;
+s--;
+ }
+ r = s; // shift when v's highest bits are zero
+
+ data.u[c] = r;
+ }
+ break;
+
+ case ir_unop_bit_count:
+ for (unsigned c = 0; c components; c++) {
+ unsigned count = 0;
+ unsigned v = op[0]-value.u[c];
+
+ for (; v; count++) {
+v = v - 1;
+ }
+ data.u[c] = count;
+ }
+ break;
+
+ case ir_unop_find_msb:
+ for (unsigned c = 0; c components; c++) {
+ int v = op[0]-value.i[c];
+
+ if (v == 0 || (op[0]-type-base_type == GLSL_TYPE_INT v == -1))
+data.i[c] = -1;
+ else {
+int count = 0;
+int top_bit = op[0]-type-base_type == GLSL_TYPE_UINT
+ ? 0 : v (1 31);
+
+while (((v (1 31)) == top_bit) count != 32) {
+ count++;
+ v = 1;
+}
+
+data.i[c] = 31 - count;
+ }
+ }
+ break;
+
+ case ir_unop_find_lsb:
+ for (unsigned c = 0; c components; c++) {
+ if (op[0]-value.i[c] == 0)
+data.i[c] = -1;
+ else {
+unsigned pos = 0;
+unsigned v = op[0]-value.u[c];
+
+for (; !(v 1); v = 1) {
+ pos++;
+}
+data.u[c] = pos;
+ }
+ }
+ break;
+
+ case ir_triop_bitfield_extract: {
+ int offset = op[1]-value.i[0];
+ int bits = op[2]-value.i[0];
+
+ for (unsigned c = 0; c components; c++) {
+ if (bits == 0)
+data.u[c] = 0;
+ else if (offset 0 || bits 0)
+data.u[c] = 0; /* Undefined, per spec. */
+ else if (offset + bits 32)
+data.u[c] = 0; /* Undefined, per spec. */
+ else {
+if (op[0]-type-base_type == GLSL_TYPE_INT) {
+ /* int so that the right shift will sign-extend. */
+ int value = op[0]-value.i[c];
+ value = 32 - bits - offset;
+ value = 32 - bits;
+ data.i[c] = value;
+} else {
+ unsigned value = op[0]-value.u[c];
+ value = 32 - bits - offset;
+ value = 32 - bits;
+ data.u[c] = value;
+}
+ }
+ }
+ break;
+ }
+
case ir_triop_lrp: {
assert(op[0]-type-base_type == GLSL_TYPE_FLOAT);
assert(op[1]-type-base_type == GLSL_TYPE_FLOAT);
@@ -1261,6 +1357,33 @@ ir_expression::constant_expression_value(struct
hash_table *variable_context)
break;
}
+ case ir_quadop_bitfield_insert: {
+ int offset = op[2]-value.i[0];
+ int bits = op[3]-value.i[0];
+
+ for (unsigned c = 0; c components; c++) {
+ if (bits == 0)
+data.u[c] = op[0]-value.u[c];
+ else if (offset 0 || bits 0)
+data.u[c] = 0; /* Undefined, per spec. */
+ else if (offset + bits 32)
+data.u[c] = 0; /* Undefined, per spec. */
+ else {
+unsigned insert_mask = ((1 bits) - 1) offset;
+
+unsigned insert = op[1]-value.u[c];
+insert = offset;
+insert = insert_mask;
+
+unsigned base = op[0]-value.u[c];
+base = ~insert_mask;
+
+data.u[c] = base | insert;
+ }
+ }
+ break;
+ }
+
case ir_quadop_vector:
for (unsigned c = 0; c this-type-vector_elements; c++) {
switch (this-type-base_type) {
--
1.8.1.5
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[Mesa-dev] [PATCH 06/14] glsl: Add a pass to lower bitfield-insert into bfm+bfi.
i965/Gen7+ and Radeon/Evergreen+ have bfm/bfi instructions to implement
bitfieldInsert() from ARB_gpu_shader5.
v2: Add ir_binop_bfm and ir_triop_bfi to st_glsl_to_tgsi.cpp.
Remove spurious temporary assignment and dereference.
---
src/glsl/ir.cpp| 2 ++
src/glsl/ir.h | 18 ++
src/glsl/ir_optimization.h | 1 +
src/glsl/ir_validate.cpp | 12 ++
src/glsl/lower_instructions.cpp| 38 ++
src/mesa/program/ir_to_mesa.cpp| 2 ++
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 ++
7 files changed, 75 insertions(+)
diff --git a/src/glsl/ir.cpp b/src/glsl/ir.cpp
index 2c989c9..2c54525 100644
--- a/src/glsl/ir.cpp
+++ b/src/glsl/ir.cpp
@@ -508,8 +508,10 @@ static const char *const operator_strs[] = {
max,
pow,
packHalf2x16_split,
+ bfm,
ubo_load,
lrp,
+ bfi,
bitfield_extract,
bitfield_insert,
vector,
diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index 470c08c..6783eca 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -1119,6 +1119,15 @@ enum ir_expression_operation {
/*@}*/
/**
+* \name First half of a lowered bitfieldInsert() operation.
+*
+* \see lower_instructions::bitfield_insert_to_bfm_bfi
+*/
+ /*@{*/
+ ir_binop_bfm,
+ /*@}*/
+
+ /**
* Load a value the size of a given GLSL type from a uniform block.
*
* operand0 is the ir_constant uniform block index in the linked shader.
@@ -1133,6 +1142,15 @@ enum ir_expression_operation {
ir_triop_lrp,
+ /**
+* \name Second half of a lowered bitfieldInsert() operation.
+*
+* \see lower_instructions::bitfield_insert_to_bfm_bfi
+*/
+ /*@{*/
+ ir_triop_bfi,
+ /*@}*/
+
ir_triop_bitfield_extract,
/**
diff --git a/src/glsl/ir_optimization.h b/src/glsl/ir_optimization.h
index a8885d7..49b1475 100644
--- a/src/glsl/ir_optimization.h
+++ b/src/glsl/ir_optimization.h
@@ -37,6 +37,7 @@
#define MOD_TO_FRACT 0x20
#define INT_DIV_TO_MUL_RCP 0x40
#define LRP_TO_ARITH 0x80
+#define BITFIELD_INSERT_TO_BFM_BFI 0x100
/**
* \see class lower_packing_builtins_visitor
diff --git a/src/glsl/ir_validate.cpp b/src/glsl/ir_validate.cpp
index 4a8df69..26f09c7 100644
--- a/src/glsl/ir_validate.cpp
+++ b/src/glsl/ir_validate.cpp
@@ -474,6 +474,12 @@ ir_validate::visit_leave(ir_expression *ir)
assert(ir-operands[1]-type == glsl_type::float_type);
break;
+ case ir_binop_bfm:
+ assert(ir-type-is_integer());
+ assert(ir-operands[0]-type-is_integer());
+ assert(ir-operands[1]-type-is_integer());
+ break;
+
case ir_binop_ubo_load:
assert(ir-operands[0]-as_constant());
assert(ir-operands[0]-type == glsl_type::uint_type);
@@ -487,6 +493,12 @@ ir_validate::visit_leave(ir_expression *ir)
assert(ir-operands[2]-type == ir-operands[0]-type ||
ir-operands[2]-type == glsl_type::float_type);
break;
+ case ir_triop_bfi:
+ assert(ir-operands[0]-type-is_integer());
+ assert(ir-operands[1]-type == ir-operands[2]-type);
+ assert(ir-operands[1]-type == ir-type);
+ break;
+
case ir_triop_bitfield_extract:
assert(ir-operands[0]-type == ir-type);
assert(ir-operands[1]-type == glsl_type::int_type);
diff --git a/src/glsl/lower_instructions.cpp b/src/glsl/lower_instructions.cpp
index 1ce7b7c..6c70a4a 100644
--- a/src/glsl/lower_instructions.cpp
+++ b/src/glsl/lower_instructions.cpp
@@ -38,6 +38,7 @@
* - LOG_TO_LOG2
* - MOD_TO_FRACT
* - LRP_TO_ARITH
+ * - BITFIELD_INSERT_TO_BFM_BFI
*
* SUB_TO_ADD_NEG:
* ---
@@ -84,6 +85,15 @@
* LRP_TO_ARITH:
* -
* Converts ir_triop_lrp to (op0 * (1.0f - op2)) + (op1 * op2).
+ *
+ * BITFIELD_INSERT_TO_BFM_BFI:
+ * ---
+ * Breaks ir_quadop_bitfield_insert into ir_binop_bfm (bitfield mask) and
+ * ir_triop_bfi (bitfield insert).
+ *
+ * Many GPUs implement the bitfieldInsert() built-in from ARB_gpu_shader_5
+ * with a pair of instructions.
+ *
*/
#include main/core.h /* for M_LOG2E */
@@ -114,6 +124,7 @@ private:
void pow_to_exp2(ir_expression *);
void log_to_log2(ir_expression *);
void lrp_to_arith(ir_expression *);
+ void bitfield_insert_to_bfm_bfi(ir_expression *);
};
/**
@@ -298,6 +309,28 @@ lower_instructions_visitor::lrp_to_arith(ir_expression *ir)
this-progress = true;
}
+void
+lower_instructions_visitor::bitfield_insert_to_bfm_bfi(ir_expression *ir)
+{
+ /* Translates
+*ir_quadop_bitfield_insert base insert offset bits
+* into
+*ir_triop_bfi (ir_binop_bfm bits offset) insert base
+*/
+
+ ir_rvalue *base_expr = ir-operands[0];
+
+ ir-operation = ir_triop_bfi;
+ ir-operands[0] = new(ir) ir_expression(ir_binop_bfm, ir-type,
+ swizzle_(ir-operands[3]),
+
[Mesa-dev] [PATCH 12/14] i965/fs: Add support for bit instructions.
Don't bother scalarizing ir_binop_bfm, since its results are
identical for all channels.
v2: Subtract result of FBH from 31 (unless an error) to convert
MSB counts to LSB counts.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 7
src/mesa/drivers/dri/i965/brw_fs.h | 7
.../dri/i965/brw_fs_channel_expressions.cpp| 37 +
src/mesa/drivers/dri/i965/brw_fs_emit.cpp | 48 ++
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 43 +++
5 files changed, 142 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 66e78d0..cac898d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -173,6 +173,13 @@ ALU2(SHL)
ALU2(SHR)
ALU2(ASR)
ALU3(LRP)
+ALU1(BFREV)
+ALU3(BFE)
+ALU2(BFI1)
+ALU3(BFI2)
+ALU1(FBH)
+ALU1(FBL)
+ALU1(CBIT)
/** Gen4 predicated IF. */
fs_inst *
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 86a9ec5..fe7eddc 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -288,6 +288,13 @@ public:
uint32_t condition);
fs_inst *LRP(fs_reg dst, fs_reg a, fs_reg y, fs_reg x);
fs_inst *DEP_RESOLVE_MOV(int grf);
+ fs_inst *BFREV(fs_reg dst, fs_reg value);
+ fs_inst *BFE(fs_reg dst, fs_reg bits, fs_reg offset, fs_reg value);
+ fs_inst *BFI1(fs_reg dst, fs_reg bits, fs_reg offset);
+ fs_inst *BFI2(fs_reg dst, fs_reg bfi1_dst, fs_reg insert, fs_reg base);
+ fs_inst *FBH(fs_reg dst, fs_reg value);
+ fs_inst *FBL(fs_reg dst, fs_reg value);
+ fs_inst *CBIT(fs_reg dst, fs_reg value);
int type_size(const struct glsl_type *type);
fs_inst *get_instruction_generating_reg(fs_inst *start,
diff --git a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
index 30d8d9b..ee362e3 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
@@ -216,6 +216,10 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment
*ir)
case ir_unop_cos_reduced:
case ir_unop_dFdx:
case ir_unop_dFdy:
+ case ir_unop_bitfield_reverse:
+ case ir_unop_bit_count:
+ case ir_unop_find_msb:
+ case ir_unop_find_lsb:
for (i = 0; i vector_elements; i++) {
ir_rvalue *op0 = get_element(op_var[0], i);
@@ -338,11 +342,26 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment
*ir)
assert(!noise should have been broken down to function call);
break;
+ case ir_binop_bfm: {
+ /* Does not need to be scalarized, since its result will be identical
+ * for all channels.
+ */
+ ir_rvalue *op0 = get_element(op_var[0], 0);
+ ir_rvalue *op1 = get_element(op_var[1], 0);
+
+ assign(ir, 0, new(mem_ctx) ir_expression(expr-operation,
+ element_type,
+ op0,
+ op1));
+ break;
+ }
+
case ir_binop_ubo_load:
assert(!not yet supported);
break;
case ir_triop_lrp:
+ case ir_triop_bitfield_extract:
for (i = 0; i vector_elements; i++) {
ir_rvalue *op0 = get_element(op_var[0], i);
ir_rvalue *op1 = get_element(op_var[1], i);
@@ -356,6 +375,23 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment
*ir)
}
break;
+ case ir_triop_bfi: {
+ /* Only a single BFM is needed for multiple BFIs. */
+ ir_rvalue *op0 = get_element(op_var[0], 0);
+
+ for (i = 0; i vector_elements; i++) {
+ ir_rvalue *op1 = get_element(op_var[1], i);
+ ir_rvalue *op2 = get_element(op_var[2], i);
+
+ assign(ir, i, new(mem_ctx) ir_expression(expr-operation,
+ element_type,
+ op0,
+ op1,
+ op2));
+ }
+ break;
+ }
+
case ir_unop_pack_snorm_2x16:
case ir_unop_pack_snorm_4x8:
case ir_unop_pack_unorm_2x16:
@@ -366,6 +402,7 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment
*ir)
case ir_unop_unpack_unorm_2x16:
case ir_unop_unpack_unorm_4x8:
case ir_unop_unpack_half_2x16:
+ case ir_quadop_bitfield_insert:
case ir_quadop_vector:
assert(!should have been lowered);
break;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
index 0f6b715..b7c85ef 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
@@ -1209,6 +1209,54 @@ fs_generator::generate_code(exec_list *instructions)
case BRW_OPCODE_SEL:
brw_SEL(p, dst, src[0], src[1]);
break;
+
[Mesa-dev] [PATCH 13/14] i965/vs: Add support for bit instructions.
v2: Rebase on LRP addition.
Use fix_3src_operand() when emitting BFE and BFI2.
Add BFE and BFI2 to is_3src_inst check in
brw_vec4_copy_propagation.cpp.
Subtract result of FBH from 31 (unless an error) to convert
MSB counts to LSB counts
---
src/mesa/drivers/dri/i965/brw_vec4.h | 7 +++
.../drivers/dri/i965/brw_vec4_copy_propagation.cpp | 5 +-
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp| 29 ++
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 66 ++
4 files changed, 106 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index d34ed35..5cef891 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -387,6 +387,13 @@ public:
vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
vec4_instruction *LRP(dst_reg dst, src_reg a, src_reg y, src_reg x);
+ vec4_instruction *BFREV(dst_reg dst, src_reg value);
+ vec4_instruction *BFE(dst_reg dst, src_reg bits, src_reg offset, src_reg
value);
+ vec4_instruction *BFI1(dst_reg dst, src_reg bits, src_reg offset);
+ vec4_instruction *BFI2(dst_reg dst, src_reg bfi1_dst, src_reg insert,
src_reg base);
+ vec4_instruction *FBH(dst_reg dst, src_reg value);
+ vec4_instruction *FBL(dst_reg dst, src_reg value);
+ vec4_instruction *CBIT(dst_reg dst, src_reg value);
int implied_mrf_writes(vec4_instruction *inst);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
index f2c6cd6..39eef4b 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
@@ -215,7 +215,10 @@ vec4_visitor::try_copy_propagation(struct intel_context
*intel,
if (has_source_modifiers !can_do_source_mods(inst))
return false;
- if (inst-opcode == BRW_OPCODE_LRP value.file == UNIFORM)
+ bool is_3src_inst = (inst-opcode == BRW_OPCODE_LRP ||
+inst-opcode == BRW_OPCODE_BFE ||
+inst-opcode == BRW_OPCODE_BFI2);
+ if (is_3src_inst value.file == UNIFORM)
return false;
/* We can't copy-propagate a UD negation into a condmod
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index 96b4965..91101f2 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -842,6 +842,35 @@ vec4_generator::generate_code(exec_list *instructions)
brw_LRP(p, dst, src[0], src[1], src[2]);
break;
+ case BRW_OPCODE_BFREV:
+ /* BFREV only supports UD type for src and dst. */
+ brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
+ retype(src[0], BRW_REGISTER_TYPE_UD));
+ break;
+ case BRW_OPCODE_FBH:
+ /* FBH only supports UD type for dst. */
+ brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
+ break;
+ case BRW_OPCODE_FBL:
+ /* FBL only supports UD type for dst. */
+ brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
+ break;
+ case BRW_OPCODE_CBIT:
+ /* CBIT only supports UD type for dst. */
+ brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
+ break;
+
+ case BRW_OPCODE_BFE:
+ brw_BFE(p, dst, src[0], src[1], src[2]);
+ break;
+
+ case BRW_OPCODE_BFI1:
+ brw_BFI1(p, dst, src[0], src[1]);
+ break;
+ case BRW_OPCODE_BFI2:
+ brw_BFI2(p, dst, src[0], src[1], src[2]);
+ break;
+
case BRW_OPCODE_IF:
if (inst-src[0].file != BAD_FILE) {
/* The instruction has an embedded compare (only allowed on gen6) */
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 31da01f..96830c3 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -136,6 +136,13 @@ ALU2(SHL)
ALU2(SHR)
ALU2(ASR)
ALU3(LRP)
+ALU1(BFREV)
+ALU3(BFE)
+ALU2(BFI1)
+ALU3(BFI2)
+ALU1(FBH)
+ALU1(FBL)
+ALU1(CBIT)
/** Gen4 predicated IF. */
vec4_instruction *
@@ -1382,6 +1389,39 @@ vec4_visitor::visit(ir_expression *ir)
assert(!derivatives not valid in vertex shader);
break;
+ case ir_unop_bitfield_reverse:
+ emit(BFREV(result_dst, op[0]));
+ break;
+ case ir_unop_bit_count:
+ emit(CBIT(result_dst, op[0]));
+ break;
+ case ir_unop_find_msb: {
+ src_reg temp = src_reg(this, glsl_type::uint_type);
+
+ inst = emit(FBH(dst_reg(temp), op[0]));
+ inst-dst.writemask = WRITEMASK_XYZW;
+
+ /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
+ * from the LSB side. If FBH didn't return an error (0x), then
+
[Mesa-dev] [PATCH 14/14] i965: Lower bitfieldInsert.
v2: Only lower bitfieldInsert to BFM+BFI (and don't lower bitfieldExtract at all) since three-source instructions are now usable in the vertex shader. --- src/mesa/drivers/dri/i965/brw_shader.cpp | 9 + 1 file changed, 9 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 5addff6..efe7151 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -151,6 +151,15 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg) * must precede lower_instructions(). */ brw_lower_packing_builtins(brw, (gl_shader_type) stage, shader-ir); + + /* bitfield lowering passes insert subtraction instructions which need + * to be lowered, so it must precede lower_instructions(SUB_TO_ADD_NEG). + */ + int bitfield_insert = intel-gen = 7 +? BITFIELD_INSERT_TO_BFM_BFI +: 0; + lower_instructions(shader-ir, bitfield_insert); + do_mat_op_to_vec(shader-ir); const int lrp_to_arith = intel-gen 6 ? LRP_TO_ARITH : 0; lower_instructions(shader-ir, -- 1.8.1.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] fixup! glsl: Add a pass to lower bitfield-insert into bfm+bfi.
--- Does this squashed in seem okay, Eric? src/glsl/lower_instructions.cpp | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/glsl/lower_instructions.cpp b/src/glsl/lower_instructions.cpp index 6c70a4a..d32ec80 100644 --- a/src/glsl/lower_instructions.cpp +++ b/src/glsl/lower_instructions.cpp @@ -321,9 +321,10 @@ lower_instructions_visitor::bitfield_insert_to_bfm_bfi(ir_expression *ir) ir_rvalue *base_expr = ir-operands[0]; ir-operation = ir_triop_bfi; - ir-operands[0] = new(ir) ir_expression(ir_binop_bfm, ir-type, - swizzle_(ir-operands[3]), - swizzle_(ir-operands[2])); + ir-operands[0] = new(ir) ir_expression(ir_binop_bfm, + ir-type-get_base_type(), + ir-operands[3], + ir-operands[2]); /* ir-operands[1] is still the value to insert. */ ir-operands[2] = base_expr; ir-operands[3] = NULL; -- 1.8.1.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 7/6] scons: remove IN_DRI_DRIVER
On Wed, May 1, 2013 at 11:54 AM, Andreas Boll
andreas.boll@gmail.com wrote:
ping
2013/4/19 Andreas Boll andreas.boll@gmail.com
Not used anymore.
---
Note: Untested
src/mesa/SConscript |1 -
1 file changed, 1 deletion(-)
diff --git a/src/mesa/SConscript b/src/mesa/SConscript
index 3cd0f87..b87e40d 100644
--- a/src/mesa/SConscript
+++ b/src/mesa/SConscript
@@ -31,7 +31,6 @@ if env['platform'] == 'windows':
env.Append(CPPDEFINES = ['_GLAPI_NO_EXPORTS'])
else:
env.Append(CPPDEFINES = [
-'IN_DRI_DRIVER', # enable the remap table (for DRI drivers)
('HAVE_DLOPEN', '1'),
])
--
1.7.10.4
It's been on the list for a while and seems harmless and I haven't had
much success getting anyone to test scons changes. So, just commit it.
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Re: [Mesa-dev] [PATCH 2/3] intel: Add multisample scaled blitting in blorp engine
On Wed, May 1, 2013 at 2:10 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
@@ -1063,22 +1176,21 @@ brw_blorp_blit_program::translate_tiling(bool
old_tiled_w, bool new_tiled_w)
* X' = (X ~0b1011) 1 | (Y 0b1) 2 | X 0b1 (4)
* Y' = (Y ~0b1) 1 | (X 0b1000) 2 | (X 0b10) 1
*/
- brw_AND(func, t1, X, brw_imm_uw(0xfff4)); /* X ~0b1011 */
- brw_SHR(func, t1, t1, brw_imm_uw(1)); /* (X ~0b1011) 1 */
- brw_AND(func, t2, Y, brw_imm_uw(1)); /* Y 0b1 */
- brw_SHL(func, t2, t2, brw_imm_uw(2)); /* (Y 0b1) 2 */
- brw_OR(func, t1, t1, t2); /* (X ~0b1011) 1 | (Y 0b1) 2 */
- brw_AND(func, t2, X, brw_imm_uw(1)); /* X 0b1 */
- brw_OR(func, Xp, t1, t2);
- brw_AND(func, t1, Y, brw_imm_uw(0xfffe)); /* Y ~0b1 */
- brw_SHL(func, t1, t1, brw_imm_uw(1)); /* (Y ~0b1) 1 */
- brw_AND(func, t2, X, brw_imm_uw(8)); /* X 0b1000 */
- brw_SHR(func, t2, t2, brw_imm_uw(2)); /* (X 0b1000) 2 */
- brw_OR(func, t1, t1, t2); /* (Y ~0b1) 1 | (X 0b1000) 2 */
- brw_AND(func, t2, X, brw_imm_uw(2)); /* X 0b10 */
- brw_SHR(func, t2, t2, brw_imm_uw(1)); /* (X 0b10) 1 */
- brw_OR(func, Yp, t1, t2);
- SWAP_XY_AND_XPYP();
+ brw_AND(func, rt1, rX, brw_imm_uw(0xfff4)); /* X ~0b1011 */
+ brw_SHR(func, rt1, rt1, brw_imm_uw(1)); /* (X ~0b1011) 1 */
+ brw_AND(func, rt2, rY, brw_imm_uw(1)); /* Y 0b1 */
+ brw_SHL(func, rt2, rt2, brw_imm_uw(2)); /* (Y 0b1) 2 */
+ brw_OR(func, rt1, rt1, rt2); /* (X ~0b1011) 1 | (Y 0b1) 2 */
+ brw_AND(func, rt2, rX, brw_imm_uw(1)); /* X 0b1 */
+ brw_OR(func, rXp, rt1, rt2);
+ brw_AND(func, rt1, rY, brw_imm_uw(0xfffe)); /* Y ~0b1 */
+ brw_SHL(func, rt1, rt1, brw_imm_uw(1)); /* (Y ~0b1) 1 */
+ brw_AND(func, rt2, rX, brw_imm_uw(8)); /* X 0b1000 */
+ brw_SHR(func, rt2, rt2, brw_imm_uw(2)); /* (X 0b1000) 2 */
+ brw_OR(func, rt1, rt1, rt2); /* (Y ~0b1) 1 | (X 0b1000) 2 */
+ brw_AND(func, rt2, rX, brw_imm_uw(2)); /* X 0b10 */
+ brw_SHR(func, rt2, rt2, brw_imm_uw(1)); /* (X 0b10) 1 */
+ brw_OR(func, rYp, rt1, rt2);
} else {
/* Applying the same logic as above, but in reverse, we obtain the
* formulas:
In hunks like these I'm having a difficult time determining if there
are differences other than the changing the variables t1 - rt1; t2 -
rt2, X - rX, etc. Are there other functional differences, and if so
is there a way we could separate the two?
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Re: [Mesa-dev] [PATCH 2/3] glsl: add AMD_vertex_shader_layer support
On Wed, May 1, 2013 at 8:41 PM, Jordan Justen jljus...@gmail.com wrote: On Tue, Apr 30, 2013 at 10:01 AM, Jordan Justen jljus...@gmail.com wrote: On Tue, Apr 30, 2013 at 9:57 AM, Ian Romanick i...@freedesktop.org wrote: On 04/27/2013 04:32 PM, Jordan Justen wrote: This GLSL extension requires that AMD_vertex_shader_layer be enabled by the driver. Most (all?) extensions also add a preprocessor define. Can you poke at AMD's driver to see if GL_AMD_vertex_shader_layer is defined? If so, then we need to add it too. Unfortunately, I don't have an AMD card. Anuj tried my piglit test with his AMD card, and found the extension wasn't available. Anuj updated his driver, and now the extension is available. Is this series r-b you pending resolution of the define issue? His question about the preprocessor definition is still unanswered, as far as I can tell. e.g., In http://www.opengl.org/registry/specs/ARB/gpu_shader5.txt it says Including the following line in a shader can be used to control the language features described in this extension: #extension GL_ARB_gpu_shader5 : behavior where behavior is as specified in section 3.3. New preprocessor #defines are added to the OpenGL Shading Language: #define GL_ARB_gpu_shader51 This extension spec doesn't say anything about that, but it seems probable that AMD's driver actually adds the preprocessor stuff, since it's kind of mean to add a built-in variable to GLSL without a macro to tell if it's available. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [v2 08/10] egl: definitions for EXT_image_dma_buf_import
On Mon, Apr 29, 2013 at 4:08 AM, Topi Pohjolainen topi.pohjolai...@intel.com wrote: As specified in: http://www.khronos.org/registry/egl/extensions/EXT/EGL_EXT_image_dma_buf_import.txt Checking for the valid fourcc values is left for drivers avoiding dependency to drm header files here. v2: - enforce EGL_NO_CONTEXT Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com --- include/EGL/eglext.h | 33 src/egl/main/eglapi.c | 7 - src/egl/main/egldisplay.h | 1 + src/egl/main/eglimage.c| 76 ++ src/egl/main/eglimage.h| 15 + src/mesa/main/extensions.c | 1 + src/mesa/main/mtypes.h | 1 + 7 files changed, 133 insertions(+), 1 deletion(-) diff --git a/include/EGL/eglext.h b/include/EGL/eglext.h index b2b5a80..9b9be8f 100644 --- a/include/EGL/eglext.h +++ b/include/EGL/eglext.h @@ -532,6 +532,39 @@ typedef EGLint (EGLAPIENTRYP PFNEGLDUPNATIVEFENCEFDANDROIDPROC)(EGLDisplay dpy, #define EGL_BUFFER_AGE_EXT 0x313D #endif +#define EGL_LINUX_DMA_BUF_EXT 0x3270 /* eglCreateImageKHR target */ + +/* Attributes for eglCreateImageKHR. */ +#define EGL_LINUX_DRM_FOURCC_EXT 0x3271 +#define EGL_DMA_BUF_PLANE0_FD_EXT 0x3272 +#define EGL_DMA_BUF_PLANE0_OFFSET_EXT 0x3273 +#define EGL_DMA_BUF_PLANE0_PITCH_EXT 0x3274 +#define EGL_DMA_BUF_PLANE1_FD_EXT 0x3275 +#define EGL_DMA_BUF_PLANE1_OFFSET_EXT 0x3276 +#define EGL_DMA_BUF_PLANE1_PITCH_EXT 0x3277 +#define EGL_DMA_BUF_PLANE2_FD_EXT 0x3278 +#define EGL_DMA_BUF_PLANE2_OFFSET_EXT 0x3279 +#define EGL_DMA_BUF_PLANE2_PITCH_EXT 0x327A +#define EGL_YUV_COLOR_SPACE_HINT_EXT 0x327B +#define EGL_SAMPLE_RANGE_HINT_EXT 0x327C +#define EGL_YUV_CHROMA_HORIZONTAL_SITING_HINT_EXT 0x327D +#define EGL_YUV_CHROMA_VERTICAL_SITING_HINT_EXT0x327E + +/* Accepted values for EGL_YUV_COLOR_SPACE_HINT_EXT attribute */ +#define EGL_ITU_REC601_EXT 0x327F +#define EGL_ITU_REC709_EXT 0x3280 +#define EGL_ITU_REC2020_EXT 0x3281 + +/* Accepted values for EGL_SAMPLE_RANGE_HINT_EXT attribute */ +#define EGL_YUV_FULL_RANGE_EXT0x3282 +#define EGL_YUV_NARROW_RANGE_EXT 0x3283 + +/* Accepted values for attributes EGL_YUV_CHROMA_HORIZONTAL_SITING_HINT_EXT + * and EGL_YUV_CHROMA_VERTICAL_SITING_HINT_EXT + */ +#define EGL_YUV_CHROMA_SITING_0_EXT0x3284 +#define EGL_YUV_CHROMA_SITING_0_5_EXT 0x3285 + #include EGL/eglmesaext.h #ifdef __cplusplus eglext.h is imported from Khronos (http://www.khronos.org/registry/egl/api/EGL/eglext.h), with the single modification to #include EGL/eglmesaext.h at the bottom of the file. The new version contains all the definitions for this extension. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/3] glsl: add AMD_vertex_shader_layer support
On Wed, May 1, 2013 at 9:25 PM, Jordan Justen jljus...@gmail.com wrote: pending resolution meant I'd figure out what the AMD driver is doing, and follow that. Indeed, sorry -- reading comprehension fail. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [v4 08/10] egl: update eglext.h from khronos
On Thu, May 2, 2013 at 12:08 AM, Topi Pohjolainen topi.pohjolai...@intel.com wrote: Provides definitions for dma buffer import extension. Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com --- Reviewed-by: Matt Turner matts...@gmail.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] st/xvmc/tests: Fix build failure
On Wed, May 1, 2013 at 12:17 PM, Lauri Kasanen c...@gmx.com wrote: Without this, the X lib path was not properly passed for tests/: /usr/bin/ld: cannot find -lXvMCW /usr/bin/ld: cannot find -lXvMC /usr/bin/ld: cannot find -lXv /usr/bin/ld: cannot find -lX11 collect2: ld returned 1 exit status Signed-off-by: Lauri Kasanen c...@gmx.com --- src/gallium/state_trackers/xvmc/Makefile.am |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/gallium/state_trackers/xvmc/Makefile.am b/src/gallium/state_trackers/xvmc/Makefile.am index 8ac7406..83a568b 100644 --- a/src/gallium/state_trackers/xvmc/Makefile.am +++ b/src/gallium/state_trackers/xvmc/Makefile.am @@ -44,7 +44,7 @@ check_PROGRAMS = \ TESTS = $(check_PROGRAMS) noinst_PROGRAMS = tests/xvmc_bench -TEST_LIBS = -lXvMCW -lXvMC -lXv -lX11 +TEST_LIBS = $(XVMC_LIBS) -lXvMCW -lXvMC -lXv -lX11 Doesn't XVMC_LIBS include all of those other libraries? I think they're now redundant and should be removed. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] st/xvmc/tests: Fix build failure
On Thu, May 2, 2013 at 11:52 AM, Lauri Kasanen c...@gmx.com wrote: On Thu, 2 May 2013 07:58:30 -0700 Matt Turner matts...@gmail.com wrote: -TEST_LIBS = -lXvMCW -lXvMC -lXv -lX11 +TEST_LIBS = $(XVMC_LIBS) -lXvMCW -lXvMC -lXv -lX11 Doesn't XVMC_LIBS include all of those other libraries? I think they're now redundant and should be removed. It doesn't here: XVMC_LIBS = -L/usr/X11R7/lib -lXvMC -lXv -lX11-xcb -lX11 -lxcb-dri2 -lxcb libXvMCW is not there. Okay, so you should remove at all but -lXvMCW. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 05/14] glsl: Add constant evaluation of bit built-ins.
v2: Order bits from LSB end (31 - count) for ir_unop_find_msb.
v3: Add ir_triop_bitfield_extract as an exception to the op[0]-type ==
op[1]-type assertion in ir_constant_expression.cpp.
Reviewed-by: Chris Forbes chr...@ijw.co.nz [v2]
---
src/glsl/ir_constant_expression.cpp | 126 +++-
1 file changed, 125 insertions(+), 1 deletion(-)
diff --git a/src/glsl/ir_constant_expression.cpp
b/src/glsl/ir_constant_expression.cpp
index c09e56a..a4a117e 100644
--- a/src/glsl/ir_constant_expression.cpp
+++ b/src/glsl/ir_constant_expression.cpp
@@ -393,7 +393,8 @@ ir_expression::constant_expression_value(struct hash_table
*variable_context)
if (op[1] != NULL)
assert(op[0]-type-base_type == op[1]-type-base_type ||
this-operation == ir_binop_lshift ||
-this-operation == ir_binop_rshift);
+ this-operation == ir_binop_rshift ||
+ this-operation == ir_triop_bitfield_extract);
bool op0_scalar = op[0]-type-is_scalar();
bool op1_scalar = op[1] != NULL op[1]-type-is_scalar();
@@ -1248,6 +1249,102 @@ ir_expression::constant_expression_value(struct
hash_table *variable_context)
}
break;
+ case ir_unop_bitfield_reverse:
+ /* http://graphics.stanford.edu/~seander/bithacks.html#BitReverseObvious
*/
+ for (unsigned c = 0; c components; c++) {
+ unsigned int v = op[0]-value.u[c]; // input bits to be reversed
+ unsigned int r = v; // r will be reversed bits of v; first get LSB of
v
+ int s = sizeof(v) * CHAR_BIT - 1; // extra shift needed at end
+
+ for (v = 1; v; v = 1) {
+r = 1;
+r |= v 1;
+s--;
+ }
+ r = s; // shift when v's highest bits are zero
+
+ data.u[c] = r;
+ }
+ break;
+
+ case ir_unop_bit_count:
+ for (unsigned c = 0; c components; c++) {
+ unsigned count = 0;
+ unsigned v = op[0]-value.u[c];
+
+ for (; v; count++) {
+v = v - 1;
+ }
+ data.u[c] = count;
+ }
+ break;
+
+ case ir_unop_find_msb:
+ for (unsigned c = 0; c components; c++) {
+ int v = op[0]-value.i[c];
+
+ if (v == 0 || (op[0]-type-base_type == GLSL_TYPE_INT v == -1))
+data.i[c] = -1;
+ else {
+int count = 0;
+int top_bit = op[0]-type-base_type == GLSL_TYPE_UINT
+ ? 0 : v (1 31);
+
+while (((v (1 31)) == top_bit) count != 32) {
+ count++;
+ v = 1;
+}
+
+data.i[c] = 31 - count;
+ }
+ }
+ break;
+
+ case ir_unop_find_lsb:
+ for (unsigned c = 0; c components; c++) {
+ if (op[0]-value.i[c] == 0)
+data.i[c] = -1;
+ else {
+unsigned pos = 0;
+unsigned v = op[0]-value.u[c];
+
+for (; !(v 1); v = 1) {
+ pos++;
+}
+data.u[c] = pos;
+ }
+ }
+ break;
+
+ case ir_triop_bitfield_extract: {
+ int offset = op[1]-value.i[0];
+ int bits = op[2]-value.i[0];
+
+ for (unsigned c = 0; c components; c++) {
+ if (bits == 0)
+data.u[c] = 0;
+ else if (offset 0 || bits 0)
+data.u[c] = 0; /* Undefined, per spec. */
+ else if (offset + bits 32)
+data.u[c] = 0; /* Undefined, per spec. */
+ else {
+if (op[0]-type-base_type == GLSL_TYPE_INT) {
+ /* int so that the right shift will sign-extend. */
+ int value = op[0]-value.i[c];
+ value = 32 - bits - offset;
+ value = 32 - bits;
+ data.i[c] = value;
+} else {
+ unsigned value = op[0]-value.u[c];
+ value = 32 - bits - offset;
+ value = 32 - bits;
+ data.u[c] = value;
+}
+ }
+ }
+ break;
+ }
+
case ir_triop_lrp: {
assert(op[0]-type-base_type == GLSL_TYPE_FLOAT);
assert(op[1]-type-base_type == GLSL_TYPE_FLOAT);
@@ -1261,6 +1358,33 @@ ir_expression::constant_expression_value(struct
hash_table *variable_context)
break;
}
+ case ir_quadop_bitfield_insert: {
+ int offset = op[2]-value.i[0];
+ int bits = op[3]-value.i[0];
+
+ for (unsigned c = 0; c components; c++) {
+ if (bits == 0)
+data.u[c] = op[0]-value.u[c];
+ else if (offset 0 || bits 0)
+data.u[c] = 0; /* Undefined, per spec. */
+ else if (offset + bits 32)
+data.u[c] = 0; /* Undefined, per spec. */
+ else {
+unsigned insert_mask = ((1 bits) - 1) offset;
+
+unsigned insert = op[1]-value.u[c];
+insert = offset;
+insert = insert_mask;
+
+unsigned base = op[0]-value.u[c];
+base = ~insert_mask;
+
+data.u[c] = base
[Mesa-dev] [PATCH] i965/gen7: Set src/dst types for 3-src instructions.
Also update asserts to allow BFE and BFI2, which take (unsigned)
doubleword arguments.
v2: Allow BRW_REGISTER_TYPE_UD for src1 and src2 as well.
Assert that src2.type (instead of src0.type) matches dest.type since
it's the primary argument and src0 and src1 might correctly have
different types.
Reviewed-by: Chris Forbes chr...@ijw.co.nz [v1]
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 40 +
1 file changed, 36 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index dda562f..bd02270 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -788,6 +788,7 @@ static struct brw_instruction *brw_alu3(struct brw_compile
*p,
struct brw_reg src1,
struct brw_reg src2)
{
+ struct intel_context *intel = p-brw-intel;
struct brw_instruction *insn = next_insn(p, opcode);
gen7_convert_mrf_to_grf(p, dest);
@@ -798,7 +799,9 @@ static struct brw_instruction *brw_alu3(struct brw_compile
*p,
dest.file == BRW_MESSAGE_REGISTER_FILE);
assert(dest.nr 128);
assert(dest.address_mode == BRW_ADDRESS_DIRECT);
- assert(dest.type == BRW_REGISTER_TYPE_F);
+ assert(dest.type == BRW_REGISTER_TYPE_F ||
+ dest.type == BRW_REGISTER_TYPE_D ||
+ dest.type == BRW_REGISTER_TYPE_UD);
insn-bits1.da3src.dest_reg_file = (dest.file == BRW_MESSAGE_REGISTER_FILE);
insn-bits1.da3src.dest_reg_nr = dest.nr;
insn-bits1.da3src.dest_subreg_nr = dest.subnr / 16;
@@ -808,7 +811,9 @@ static struct brw_instruction *brw_alu3(struct brw_compile
*p,
assert(src0.file == BRW_GENERAL_REGISTER_FILE);
assert(src0.address_mode == BRW_ADDRESS_DIRECT);
assert(src0.nr 128);
- assert(src0.type == BRW_REGISTER_TYPE_F);
+ assert(src0.type == BRW_REGISTER_TYPE_F ||
+ src0.type == BRW_REGISTER_TYPE_D ||
+ src0.type == BRW_REGISTER_TYPE_UD);
insn-bits2.da3src.src0_swizzle = src0.dw1.bits.swizzle;
insn-bits2.da3src.src0_subreg_nr = get_3src_subreg_nr(src0);
insn-bits2.da3src.src0_reg_nr = src0.nr;
@@ -819,7 +824,9 @@ static struct brw_instruction *brw_alu3(struct brw_compile
*p,
assert(src1.file == BRW_GENERAL_REGISTER_FILE);
assert(src1.address_mode == BRW_ADDRESS_DIRECT);
assert(src1.nr 128);
- assert(src1.type == BRW_REGISTER_TYPE_F);
+ assert(src1.type == BRW_REGISTER_TYPE_F ||
+ src0.type == BRW_REGISTER_TYPE_D ||
+ src0.type == BRW_REGISTER_TYPE_UD);
insn-bits2.da3src.src1_swizzle = src1.dw1.bits.swizzle;
insn-bits2.da3src.src1_subreg_nr_low = get_3src_subreg_nr(src1) 0x3;
insn-bits3.da3src.src1_subreg_nr_high = get_3src_subreg_nr(src1) 2;
@@ -831,7 +838,9 @@ static struct brw_instruction *brw_alu3(struct brw_compile
*p,
assert(src2.file == BRW_GENERAL_REGISTER_FILE);
assert(src2.address_mode == BRW_ADDRESS_DIRECT);
assert(src2.nr 128);
- assert(src2.type == BRW_REGISTER_TYPE_F);
+ assert(src2.type == BRW_REGISTER_TYPE_F ||
+ src0.type == BRW_REGISTER_TYPE_D ||
+ src0.type == BRW_REGISTER_TYPE_UD);
insn-bits3.da3src.src2_swizzle = src2.dw1.bits.swizzle;
insn-bits3.da3src.src2_subreg_nr = get_3src_subreg_nr(src2);
insn-bits3.da3src.src2_rep_ctrl = src2.vstride == BRW_VERTICAL_STRIDE_0;
@@ -839,6 +848,29 @@ static struct brw_instruction *brw_alu3(struct brw_compile
*p,
insn-bits1.da3src.src2_abs = src2.abs;
insn-bits1.da3src.src2_negate = src2.negate;
+ if (intel-gen = 7) {
+ /* For MAD and LRP, all incoming src types are float, but for BFE and
+ * BFI2, the three source types might not all be the same. src2, the
+ * primary argument, should match the type of the destination.
+ */
+ assert(dest.type == src2.type);
+
+ switch (dest.type) {
+ case BRW_REGISTER_TYPE_F:
+ insn-bits1.da3src.src_type = BRW_3SRC_TYPE_F;
+ insn-bits1.da3src.dst_type = BRW_3SRC_TYPE_F;
+ break;
+ case BRW_REGISTER_TYPE_D:
+ insn-bits1.da3src.src_type = BRW_3SRC_TYPE_D;
+ insn-bits1.da3src.dst_type = BRW_3SRC_TYPE_D;
+ break;
+ case BRW_REGISTER_TYPE_UD:
+ insn-bits1.da3src.src_type = BRW_3SRC_TYPE_UD;
+ insn-bits1.da3src.dst_type = BRW_3SRC_TYPE_UD;
+ break;
+ }
+ }
+
return insn;
}
--
1.8.1.5
___
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mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 12/14] i965/fs: Add support for bit instructions.
Don't bother scalarizing ir_binop_bfm, since its results are
identical for all channels.
v2: Subtract result of FBH from 31 (unless an error) to convert
MSB counts to LSB counts.
v3: Use op0-clone() in ir_triop_bfi to prevent (var_ref
channel_expressions) from appearing multiple times in the IR.
Reviewed-by: Chris Forbes chr...@ijw.co.nz [v2]
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 7
src/mesa/drivers/dri/i965/brw_fs.h | 7
.../dri/i965/brw_fs_channel_expressions.cpp| 37 +
src/mesa/drivers/dri/i965/brw_fs_emit.cpp | 48 ++
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 43 +++
5 files changed, 142 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 66e78d0..cac898d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -173,6 +173,13 @@ ALU2(SHL)
ALU2(SHR)
ALU2(ASR)
ALU3(LRP)
+ALU1(BFREV)
+ALU3(BFE)
+ALU2(BFI1)
+ALU3(BFI2)
+ALU1(FBH)
+ALU1(FBL)
+ALU1(CBIT)
/** Gen4 predicated IF. */
fs_inst *
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 86a9ec5..fe7eddc 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -288,6 +288,13 @@ public:
uint32_t condition);
fs_inst *LRP(fs_reg dst, fs_reg a, fs_reg y, fs_reg x);
fs_inst *DEP_RESOLVE_MOV(int grf);
+ fs_inst *BFREV(fs_reg dst, fs_reg value);
+ fs_inst *BFE(fs_reg dst, fs_reg bits, fs_reg offset, fs_reg value);
+ fs_inst *BFI1(fs_reg dst, fs_reg bits, fs_reg offset);
+ fs_inst *BFI2(fs_reg dst, fs_reg bfi1_dst, fs_reg insert, fs_reg base);
+ fs_inst *FBH(fs_reg dst, fs_reg value);
+ fs_inst *FBL(fs_reg dst, fs_reg value);
+ fs_inst *CBIT(fs_reg dst, fs_reg value);
int type_size(const struct glsl_type *type);
fs_inst *get_instruction_generating_reg(fs_inst *start,
diff --git a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
index 30d8d9b..0f3d4ab 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
@@ -216,6 +216,10 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment
*ir)
case ir_unop_cos_reduced:
case ir_unop_dFdx:
case ir_unop_dFdy:
+ case ir_unop_bitfield_reverse:
+ case ir_unop_bit_count:
+ case ir_unop_find_msb:
+ case ir_unop_find_lsb:
for (i = 0; i vector_elements; i++) {
ir_rvalue *op0 = get_element(op_var[0], i);
@@ -338,11 +342,26 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment
*ir)
assert(!noise should have been broken down to function call);
break;
+ case ir_binop_bfm: {
+ /* Does not need to be scalarized, since its result will be identical
+ * for all channels.
+ */
+ ir_rvalue *op0 = get_element(op_var[0], 0);
+ ir_rvalue *op1 = get_element(op_var[1], 0);
+
+ assign(ir, 0, new(mem_ctx) ir_expression(expr-operation,
+ element_type,
+ op0,
+ op1));
+ break;
+ }
+
case ir_binop_ubo_load:
assert(!not yet supported);
break;
case ir_triop_lrp:
+ case ir_triop_bitfield_extract:
for (i = 0; i vector_elements; i++) {
ir_rvalue *op0 = get_element(op_var[0], i);
ir_rvalue *op1 = get_element(op_var[1], i);
@@ -356,6 +375,23 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment
*ir)
}
break;
+ case ir_triop_bfi: {
+ /* Only a single BFM is needed for multiple BFIs. */
+ ir_rvalue *op0 = get_element(op_var[0], 0);
+
+ for (i = 0; i vector_elements; i++) {
+ ir_rvalue *op1 = get_element(op_var[1], i);
+ ir_rvalue *op2 = get_element(op_var[2], i);
+
+ assign(ir, i, new(mem_ctx) ir_expression(expr-operation,
+ element_type,
+ op0-clone(mem_ctx, NULL),
+ op1,
+ op2));
+ }
+ break;
+ }
+
case ir_unop_pack_snorm_2x16:
case ir_unop_pack_snorm_4x8:
case ir_unop_pack_unorm_2x16:
@@ -366,6 +402,7 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment
*ir)
case ir_unop_unpack_unorm_2x16:
case ir_unop_unpack_unorm_4x8:
case ir_unop_unpack_half_2x16:
+ case ir_quadop_bitfield_insert:
case ir_quadop_vector:
assert(!should have been lowered);
break;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
index 0f6b715..b7c85ef 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
+++
[Mesa-dev] [PATCH 14/14] i965: Lower bitfieldInsert.
v2: Only lower bitfieldInsert to BFM+BFI (and don't lower bitfieldExtract at all) since three-source instructions are now usable in the vertex shader. v3: Lower bitfield_insert in the same pass with everything else, since it doesn't produce any instructions to be lowered (the other two lowering passes that were in a previous iteration of this series emitted subtractions which needed to be lowered). Reviewed-by: Chris Forbes chr...@ijw.co.nz [v2] --- src/mesa/drivers/dri/i965/brw_shader.cpp | 4 1 file changed, 4 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 5addff6..283e4a8 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -152,6 +152,9 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg) */ brw_lower_packing_builtins(brw, (gl_shader_type) stage, shader-ir); do_mat_op_to_vec(shader-ir); + const int bitfield_insert = intel-gen = 7 + ? BITFIELD_INSERT_TO_BFM_BFI + : 0; const int lrp_to_arith = intel-gen 6 ? LRP_TO_ARITH : 0; lower_instructions(shader-ir, MOD_TO_FRACT | @@ -159,6 +162,7 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg) SUB_TO_ADD_NEG | EXP_TO_EXP2 | LOG_TO_LOG2 | + bitfield_insert | lrp_to_arith); /* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this, -- 1.8.1.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 15/14] i965/fs: Don't emit 16-wide BFI1 instructions.
The Haswell Bspec says A SIMD16 instruction is not allowed. (but
16-wide BFI1 works for me so far). Since GLSL's bitfieldInsert()
function takes int parameters BFI1 produces the same results in all
channels, so there's never any reason to emit a 16-wide BFI1.
---
src/mesa/drivers/dri/i965/brw_fs_emit.cpp| 5 -
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 7 ++-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
index b7c85ef..d35438c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
@@ -1250,7 +1250,10 @@ fs_generator::generate_code(exec_list *instructions)
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_BFI2(p, dst, src[0], src[1], src[2]);
brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
-brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]),
sechalf(src[2]));
+/* We don't emit 16-wide BFI1 instructions, so don't use sechalf()
+ * on src[0] (which comes from BFI1).
+ */
+brw_BFI2(p, sechalf(dst), src[0], sechalf(src[1]),
sechalf(src[2]));
brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
} else {
brw_BFI2(p, dst, src[0], src[1], src[2]);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 417e8a8..b62f996 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -617,7 +617,12 @@ fs_visitor::visit(ir_expression *ir)
emit(BFE(this-result, op[2], op[1], op[0]));
break;
case ir_binop_bfm:
- emit(BFI1(this-result, op[0], op[1]));
+ inst = emit(BFI1(this-result, op[0], op[1]));
+ /* Haswell doesn't allow 16-wide for this instruction, and since it only
+ * takes int parameters from GLSL it produces the same result in all
+ * channels, so there's no reason to ever do 16-wide.
+ */
+ inst-force_uncompressed = true;
break;
case ir_triop_bfi:
emit(BFI2(this-result, op[0], op[1], op[2]));
--
1.8.1.5
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[Mesa-dev] [PATCH] i965/fs: Prefer picking texture ops when instruction scheduling.
Texture operations have very long (hundreds of cycles) latencies. If a
texture operation is ready to be scheduled, prefer it over other types
of instructions.
Typically this will mean the other instructions execute to completion
during the time it takes the texturing operation to return results, so
they're effectively free. It also helps to pipeline multiple texture
operations and overlap their latencies.
---
Mostly untested, and probably not useful until Eric's texture-grf branch
is completed.
src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
b/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
index 7567123..d81a386 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
@@ -726,15 +726,21 @@ instruction_scheduler::schedule_instructions(fs_inst
*next_block_header)
int chosen_time = 0;
if (post_reg_alloc) {
+ bool chosen_is_texture_op = false;
+
/* Of the instructions closest ready to execute or the closest to
- * being ready, choose the oldest one.
+ * being ready, choose the oldest one. Pick a texturing operation
+ * if it's available, since its latency is very high.
*/
foreach_list(node, instructions) {
schedule_node *n = (schedule_node *)node;
-if (!chosen || n-unblocked_time chosen_time) {
+if (!chosen ||
+(n-unblocked_time chosen_time
+ (chosen_is_texture_op == n-inst-is_tex( {
chosen = n;
chosen_time = n-unblocked_time;
+ chosen_is_texture_op = n-inst-is_tex();
}
}
} else {
--
1.8.1.5
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Re: [Mesa-dev] [PATCH 1/7] i965/vs: Do round-robin register allocation on gen6+ like we do in the FS.
On Tue, Apr 30, 2013 at 9:15 AM, Eric Anholt e...@anholt.net wrote: This will free instruction scheduling to make better choices. No statistically significant performance difference on GLB2.7 (n=93). --- Series is: Reviewed-by: Matt Turner matts...@gmail.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] st/xvmc/tests: Fix build failure, v2
On Fri, May 3, 2013 at 1:48 AM, Lauri Kasanen c...@gmx.com wrote: v2: Removed extra libs as requested by Matt Turner. Signed-off-by: Lauri Kasanen c...@gmx.com --- src/gallium/state_trackers/xvmc/Makefile.am |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/gallium/state_trackers/xvmc/Makefile.am b/src/gallium/state_trackers/xvmc/Makefile.am index 8ac7406..184432e 100644 --- a/src/gallium/state_trackers/xvmc/Makefile.am +++ b/src/gallium/state_trackers/xvmc/Makefile.am @@ -44,7 +44,7 @@ check_PROGRAMS = \ TESTS = $(check_PROGRAMS) noinst_PROGRAMS = tests/xvmc_bench -TEST_LIBS = -lXvMCW -lXvMC -lXv -lX11 +TEST_LIBS = $(XVMC_LIBS) -lXvMCW tests_test_context_SOURCES = tests/test_context.c tests/testlib.c tests_test_context_LDADD = $(TEST_LIBS) tests_test_surface_SOURCES = tests/test_surface.c tests/testlib.c -- 1.7.2.1 Reviewed-by: Matt Turner matts...@gmail.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
