Re: [PATCH 3/5] ARM: sun8i: dt: Add DT bindings documentation for Allwinner sun8i-emac
Le 06/06/2016 16:14, Rob Herring a écrit : > On Fri, Jun 03, 2016 at 11:56:28AM +0200, LABBE Corentin wrote: >> This patch adds documentation for Device-Tree bindings for the >> Allwinner sun8i-emac driver. >> >> Signed-off-by: LABBE Corentin >> --- >> .../bindings/net/allwinner,sun8i-emac.txt | 64 >> ++ >> 1 file changed, 64 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt >> >> diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt >> b/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt >> new file mode 100644 >> index 000..cf71a71 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt >> @@ -0,0 +1,64 @@ >> +* Allwinner sun8i EMAC ethernet controller >> + >> +Required properties: >> +- compatible: "allwinner,sun8i-a83t-emac", "allwinner,sun8i-h3-emac", >> +or "allwinner,sun50i-a64-emac" >> +- reg: address and length of the register sets for the device. >> +- reg-names: should be "emac" and "syscon", matching the register sets > > Is syscon shared with other devices? Your example only has 1 reg > address. > The example is bad, emac and syscon are two distinct regspaces. I will correct the example. >> +- interrupts: interrupt for the device >> +- clocks: A phandle to the reference clock for this device >> +- clock-names: should be "ahb" >> +- resets: A phandle to the reset control for this device >> +- reset-names: should be "ahb" >> +- phy-mode: See ethernet.txt >> +- phy or phy-handle: See ethernet.txt >> +- #address-cells: shall be 1 >> +- #size-cells: shall be 0 >> + >> +"allwinner,sun8i-h3-emac" also requires: >> +- clocks: an extra phandle to the reference clock for the EPHY >> +- clock-names: an extra "ephy" entry matching the clocks property >> +- resets: an extra phandle to the reset control for the EPHY >> +- resets-names: an extra "ephy" entry matching the resets property >> + >> +See ethernet.txt in the same directory for generic bindings for ethernet >> +controllers. >> + >> +The device node referenced by "phy" or "phy-handle" should be a child node >> +of this node. See phy.txt for the generic PHY bindings. >> + >> +Optional properties: >> +- phy-supply: phandle to a regulator if the PHY needs one >> +- phy-io-supply: phandle to a regulator if the PHY needs a another one for >> I/O. >> + This is sometimes found with RGMII PHYs, which use a second >> + regulator for the lower I/O voltage. > > These should go in the phy's node. > In fact, I forgot to remove them, since for the moment, the driver sent do not have any regulator support. Thanks
[PATCH] net: ethernet: i40e: remove i40e_fcoe files
i40e_fcoe support was removed via commit 9eed69a9147c ("i40e: Drop FCoE code
from core driver files")
But this left files in place but uncompilable.
Let's finish the cleaning.
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/intel/i40e/i40e_fcoe.c | 1571 ---
drivers/net/ethernet/intel/i40e/i40e_fcoe.h | 127 ---
2 files changed, 1698 deletions(-)
delete mode 100644 drivers/net/ethernet/intel/i40e/i40e_fcoe.c
delete mode 100644 drivers/net/ethernet/intel/i40e/i40e_fcoe.h
diff --git a/drivers/net/ethernet/intel/i40e/i40e_fcoe.c
b/drivers/net/ethernet/intel/i40e/i40e_fcoe.c
deleted file mode 100644
index 2d1253c5b7a1..
--- a/drivers/net/ethernet/intel/i40e/i40e_fcoe.c
+++ /dev/null
@@ -1,1571 +0,0 @@
-/***
- *
- * Intel Ethernet Controller XL710 Family Linux Driver
- * Copyright(c) 2013 - 2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program. If not, see <http://www.gnu.org/licenses/>.
- *
- * The full GNU General Public License is included in this distribution in
- * the file called "COPYING".
- *
- * Contact Information:
- * e1000-devel Mailing List
- * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
- *
-
**/
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include "i40e.h"
-#include "i40e_fcoe.h"
-
-/**
- * i40e_fcoe_sof_is_class2 - returns true if this is a FC Class 2 SOF
- * @sof: the FCoE start of frame delimiter
- **/
-static inline bool i40e_fcoe_sof_is_class2(u8 sof)
-{
- return (sof == FC_SOF_I2) || (sof == FC_SOF_N2);
-}
-
-/**
- * i40e_fcoe_sof_is_class3 - returns true if this is a FC Class 3 SOF
- * @sof: the FCoE start of frame delimiter
- **/
-static inline bool i40e_fcoe_sof_is_class3(u8 sof)
-{
- return (sof == FC_SOF_I3) || (sof == FC_SOF_N3);
-}
-
-/**
- * i40e_fcoe_sof_is_supported - returns true if the FC SOF is supported by HW
- * @sof: the input SOF value from the frame
- **/
-static inline bool i40e_fcoe_sof_is_supported(u8 sof)
-{
- return i40e_fcoe_sof_is_class2(sof) ||
- i40e_fcoe_sof_is_class3(sof);
-}
-
-/**
- * i40e_fcoe_fc_sof - pull the SOF from FCoE header in the frame
- * @skb: the frame whose EOF is to be pulled from
- **/
-static inline int i40e_fcoe_fc_sof(struct sk_buff *skb, u8 *sof)
-{
- *sof = ((struct fcoe_hdr *)skb_network_header(skb))->fcoe_sof;
-
- if (!i40e_fcoe_sof_is_supported(*sof))
- return -EINVAL;
- return 0;
-}
-
-/**
- * i40e_fcoe_eof_is_supported - returns true if the EOF is supported by HW
- * @eof: the input EOF value from the frame
- **/
-static inline bool i40e_fcoe_eof_is_supported(u8 eof)
-{
- return (eof == FC_EOF_N) || (eof == FC_EOF_T) ||
- (eof == FC_EOF_NI) || (eof == FC_EOF_A);
-}
-
-/**
- * i40e_fcoe_fc_eof - pull EOF from FCoE trailer in the frame
- * @skb: the frame whose EOF is to be pulled from
- **/
-static inline int i40e_fcoe_fc_eof(struct sk_buff *skb, u8 *eof)
-{
- /* the first byte of the last dword is EOF */
- skb_copy_bits(skb, skb->len - 4, eof, 1);
-
- if (!i40e_fcoe_eof_is_supported(*eof))
- return -EINVAL;
- return 0;
-}
-
-/**
- * i40e_fcoe_ctxt_eof - convert input FC EOF for descriptor programming
- * @eof: the input eof value from the frame
- *
- * The FC EOF is converted to the value understood by HW for descriptor
- * programming. Never call this w/o calling i40e_fcoe_eof_is_supported()
- * first and that already checks for all supported valid eof values.
- **/
-static inline u32 i40e_fcoe_ctxt_eof(u8 eof)
-{
- switch (eof) {
- case FC_EOF_N:
- return I40E_TX_DESC_CMD_L4T_EOFT_EOF_N;
- case FC_EOF_T:
- return I40E_TX_DESC_CMD_L4T_EOFT_EOF_T;
- case FC_EOF_NI:
- return I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI;
- case FC_EOF_A:
- return I40E_TX_DESC_CMD_L4T_EOFT_EOF_A;
- default:
- /* Supported valid eof shall be already checked by
-* calling i40e_fcoe_eof_is_supported() first,
-* therefore this default case shall never hit.
-*/
- WARN_ON(1);
- return -EINVAL;
-
Re: [linux-sunxi] [PATCH 4/5] arm64: allwinner: h6: add EMAC device nodes
On Sun, Jul 22, 2018 at 01:39:54PM +0800, Icenowy Zheng wrote:
> Allwinner H6 SoC has an EMAC like the one in A64.
>
> Add device tree nodes for the H6 DTSI file.
>
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 30
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> index 3ab6cf0256ca..c65311de301a 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -149,6 +149,14 @@
> interrupt-controller;
> #interrupt-cells = <3>;
>
> + ext_rgmii_pins: rgmii_pins {
> + pins = "PD0", "PD1", "PD2", "PD3", "PD4",
> +"PD5", "PD7", "PD8", "PD9", "PD10",
> +"PD11", "PD12", "PD13", "PD19", "PD20";
> + function = "emac";
> + drive-strength = <40>;
> + };
> +
> mmc0_pins: mmc0-pins {
> pins = "PF0", "PF1", "PF2", "PF3",
> "PF4", "PF5";
> @@ -258,6 +266,28 @@
> status = "disabled";
> };
>
> + emac: ethernet@502 {
> + compatible = "allwinner,sun50i-a64-emac",
> + "allwinner,sun50i-h6-emac";
> + syscon = <&syscon>;
> + reg = <0x0502 0x1>;
> + interrupts = ;
> + interrupt-names = "macirq";
> + resets = <&ccu RST_BUS_EMAC>;
> + reset-names = "stmmaceth";
> + clocks = <&ccu CLK_BUS_EMAC>;
> + clock-names = "stmmaceth";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
#address-cells and #size-cells is unnecessary in emac node.
Regards
[BUG] net: stmmac: dwmac-sun8i broken in linux-next
Hello
The dwmac-sun8i driver is broken in next-20180515, symptom are no RX and TX
errors as shown by ifconfig:
eth0: flags=4163 mtu 1500
inet 192.168.1.204 netmask 255.255.255.0 broadcast 192.168.1.255
ether 96:75:ff:0d:f6:d8 txqueuelen 1000 (Ethernet)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 0 bytes 4956 (4.8 KiB)
TX errors 118 dropped 0 overruns 0 carrier 0 collisions 0
Reverting the following commit made the driver working:
4dbbe8dde8485b89bce8bbbe7564337fd7eed69f ("net: stmmac: Add support for U32 TC
filter using Flexible RX Parser")
5f0456b43140af9413397cc11d03d18b9f2fc2fc ("net: stmmac: Implement logic to
automatically select HW Interface")
Note that reverting only 4dbbe8dde8485b89bce8bbbe7564337fd7eed69f lead to crash:
[ 31.385110] Backtrace:
[ 31.387576] [] (stmmac_open) from []
(__dev_open+0xe4/0x180)
[ 31.394972] r10:ed447d04 r9:edc5d010 r8:ef02002c r7:c08670a4 r6:
r5:c0c08488
[ 31.402793] r4:ef02
[ 31.405335] [] (__dev_open) from []
(__dev_change_flags+0x190/0x1e8)
[ 31.413421] r8:1002 r7:c0c08488 r6:1003 r5:0001 r4:ef02
[ 31.420122] [] (__dev_change_flags) from []
(dev_change_flags+0x20/0x50)
[ 31.428555] r9:edc5d010 r8:ed447c18 r7:ef020134 r6: r5:1002
r4:ef02
[ 31.436300] [] (dev_change_flags) from []
(do_setlink+0x28c/0xbdc)
[ 31.444213] r9:edc5d010 r8:ed447c18 r7: r6:c0c08488 r5:ed447b50
r4:ef02
[ 31.451955] [] (do_setlink) from []
(rtnl_newlink+0x54c/0x7a8)
[ 31.459522] r10:ed447d04 r9: r8: r7: r6:
r5:
[ 31.467343] r4:ef02
[ 31.469885] [] (rtnl_newlink) from []
(rtnetlink_rcv_msg+0x38c/0x544)
[ 31.478058] r10:ed447d04 r9: r8:ee242840 r7: r6:edc5d000
r5:c0c08488
[ 31.485879] r4:
[ 31.488422] [] (rtnetlink_rcv_msg) from []
(netlink_rcv_skb+0xc0/0x118)
[ 31.496768] r10:c0c08488 r9: r8:0020 r7:edc5d000 r6:c064466c
r5:c0c08488
[ 31.504589] r4:ee242840
[ 31.507129] [] (netlink_rcv_skb) from []
(rtnetlink_rcv+0x18/0x1c)
[ 31.515042] r8:ed447d60 r7:ee242840 r6:0020 r5:ee37d800 r4:ee5fac00
[ 31.521742] [] (rtnetlink_rcv) from []
(netlink_unicast+0x190/0x1fc)
[ 31.529829] [] (netlink_unicast) from []
(netlink_sendmsg+0x3cc/0x410)
[ 31.538089] r10: r9:0020 r8:014000c0 r7:ee242840 r6:ee37d800
r5:c0c08488
[ 31.545910] r4:ed447f44
[ 31.548452] [] (netlink_sendmsg) from []
(sock_sendmsg+0x1c/0x2c)
[ 31.556279] r10: r9:ed447edc r8: r7:eefce640 r6:
r5:c0c08488
[ 31.564100] r4:ed447f44
[ 31.566640] [] (sock_sendmsg) from []
(___sys_sendmsg+0x250/0x264)
[ 31.574555] [] (___sys_sendmsg) from []
(__sys_sendmsg+0x58/0x94)
[ 31.582382] r10: r9:ed446000 r8:c01011c4 r7:eefce640 r6:
r5:bec25150
[ 31.590203] r4:c0c08488
[ 31.592743] [] (__sys_sendmsg) from []
(sys_sendmsg+0x14/0x18)
[ 31.600307] r7:0128 r6:bec2d17c r5:bec25144 r4:00093ee0
[ 31.605969] [] (sys_sendmsg) from []
(ret_fast_syscall+0x0/0x28)
[ 31.613704] Exception stack(0xed447fa8 to 0xed447ff0)
[ 31.618756] 7fa0: 00093ee0 bec25144 0003 bec25150
85ce
[ 31.626929] 7fc0: 00093ee0 bec25144 bec2d17c 0128 000942a8 5afc783a
00094000 bec25150
[ 31.635099] 7fe0: bec250f0 012c b6e10b5c
[ 31.640152] Code: e59a261c e59a013c e50b306c e592300c (e593300c)
[ 31.646632] ---[ end trace 407964b7deb937bf ]---
For the moment, I stil didnt find the issue.
What to we do now ? do you want that I send revert patchs ?
Regards
Re: [PATCH v3 net-next 00/12] net: stmmac: Clean-up and tune-up
On Fri, May 18, 2018 at 02:55:57PM +0100, Jose Abreu wrote:
> This targets to uniformize the handling of the different GMAC versions in
> stmmac_main.c file and also tune-up the HW.
>
> Currently there are some if/else conditions in the main source file which
> calls different callbacks depending on the ID of GMAC.
>
> With the introducion of a generic HW interface handling which automatically
> selects the GMAC callbacks to be used, it is now unpleasant to see if
> conditions in the main code because this should be completely agnostic of the
> GMAC version.
>
> This series removes most of these conditions. There are some if conditions
> that remain untouched but the callbacks handling are now uniformized.
>
> Tested in GMAC5, hope I didn't break any previous versions.
>
> Please check [1] for performance analisys of patches 3-12.
>
> ---
> David,
>
> This will probably generate a merge conflict with [2] (which was not merged
> yet). I'm waiting for Corentin input and then, if this series is merged
> before, I will rebase [2]. Or the other way around if you prefer :D
>
> Thanks
> ---
>
> Cc: David S. Miller
> Cc: Joao Pinto
> Cc: Vitor Soares
> Cc: Giuseppe Cavallaro
> Cc: Alexandre Torgue
>
> [1] https://marc.info/?l=linux-netdev&m=152656352607905&w=2
> [2] https://patchwork.ozlabs.org/patch/915286/
>
> Jose Abreu (12):
> net: stmmac: Enable OSP for GMAC4
> net: stmmac: Do not keep rearming the coalesce timer in stmmac_xmit
> net: stmmac: Let descriptor code set skbuff address
> net: stmmac: Let descriptor code clear the descriptor
> net: stmmac: Uniformize the use of dma_{rx/tx}_mode callbacks
> net: stmmac: Remove uneeded checks for GMAC version
> net: stmmac: Move PTP and MMC base address calculation to hwif.c
> net: stmmac: Uniformize the use of dma_init_* callbacks
> net: stmmac: Remove uneeded check for GMAC version in stmmac_xmit
> net: stmmac: Uniformize set_rx_owner()
> net: stmmac: Let descriptor code get skbuff address
> net: stmmac: Remove if condition by taking advantage of hwif return
> code
>
> drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 82 +---
> .../net/ethernet/stmicro/stmmac/dwmac1000_dma.c| 92 ++
> drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c | 35 +++--
> drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c | 34 +++-
> drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c |7 +-
> drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h |1 -
> drivers/net/ethernet/stmicro/stmmac/enh_desc.c | 20 ++-
> drivers/net/ethernet/stmicro/stmmac/hwif.c | 34
> drivers/net/ethernet/stmicro/stmmac/hwif.h | 27 ++-
> drivers/net/ethernet/stmicro/stmmac/norm_desc.c| 20 ++-
> drivers/net/ethernet/stmicro/stmmac/stmmac.h |1 +
> drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 198
> +++-
> 12 files changed, 323 insertions(+), 228 deletions(-)
>
>
Hello
You didnt have put in CC linux-ker...@vger.kernel.org as required by
get_maintener.pl letting more people to see this series.
Since this series touch dwmac-sun8i.c you should have also added Chen-Yu
Tsai/Maxime Ripard (as also asked by get_maintainer).
Regards
Re: [PATCH net-next] net: stmmac: Populate missing callbacks in HWIF initialization
On Thu, May 17, 2018 at 10:57:28AM +0100, Jose Abreu wrote:
> Some HW specific setusp, like sun8i, do not populate all the necessary
> callbacks, which is what HWIF helpers were expecting.
>
> Fix this by always trying to get the generic helpers and populate them
> if they were not previously populated by HW specific setup.
>
> Signed-off-by: Jose Abreu
> Fixes: 5f0456b43140 ("net: stmmac: Implement logic to automatically
> select HW Interface")
> Reported-by: Corentin Labbe
> Cc: Corentin Labbe
> Cc: David S. Miller
> Cc: Joao Pinto
> Cc: Giuseppe Cavallaro
> Cc: Alexandre Torgue
> ---
> Hi Corentin,
>
> Please check if this patch makes sun8i work again.
>
> Thanks and Best Regards,
> Jose Miguel Abreu
> ---
Hello
Tested-by: Corentin Labbe
Thanks for the quick fix.
Note that this patch conflict with your next v3 serie
Regards
Re: [PATCH v3 net-next 00/12] net: stmmac: Clean-up and tune-up
On Fri, May 18, 2018 at 03:23:44PM +0100, Jose Abreu wrote:
> Hi Corentin,
>
> On 18-05-2018 15:12, Corentin Labbe wrote:
> > On Fri, May 18, 2018 at 02:55:57PM +0100, Jose Abreu wrote:
> >> This targets to uniformize the handling of the different GMAC versions in
> >> stmmac_main.c file and also tune-up the HW.
> >>
> >> Currently there are some if/else conditions in the main source file which
> >> calls different callbacks depending on the ID of GMAC.
> >>
> >> With the introducion of a generic HW interface handling which automatically
> >> selects the GMAC callbacks to be used, it is now unpleasant to see if
> >> conditions in the main code because this should be completely agnostic of
> >> the
> >> GMAC version.
> >>
> >> This series removes most of these conditions. There are some if conditions
> >> that remain untouched but the callbacks handling are now uniformized.
> >>
> >> Tested in GMAC5, hope I didn't break any previous versions.
> >>
> >> Please check [1] for performance analisys of patches 3-12.
> >>
> >> ---
> >> David,
> >>
> >> This will probably generate a merge conflict with [2] (which was not merged
> >> yet). I'm waiting for Corentin input and then, if this series is merged
> >> before, I will rebase [2]. Or the other way around if you prefer :D
> >>
> >> Thanks
> >> ---
> >>
> >> Cc: David S. Miller
> >> Cc: Joao Pinto
> >> Cc: Vitor Soares
> >> Cc: Giuseppe Cavallaro
> >> Cc: Alexandre Torgue
> >>
> >> [1]
> >> https://urldefense.proofpoint.com/v2/url?u=https-3A__marc.info_-3Fl-3Dlinux-2Dnetdev-26m-3D152656352607905-26w-3D2&d=DwIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw&m=a7bgrSQpisaMSa5fT-je94smZ_TM7QTxNFKqkvI5Nns&s=Tr23Xj_UCR_PaJp8AYiy18hfhbILnsaCsKDT5_4m2z4&e=
> >> [2]
> >> https://urldefense.proofpoint.com/v2/url?u=https-3A__patchwork.ozlabs.org_patch_915286_&d=DwIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw&m=a7bgrSQpisaMSa5fT-je94smZ_TM7QTxNFKqkvI5Nns&s=Q0SV-ZR35zIJWjiaLNXqlOWchppQ2CsO-Fh-BFCjCB8&e=
> >>
> >> Jose Abreu (12):
> >> net: stmmac: Enable OSP for GMAC4
> >> net: stmmac: Do not keep rearming the coalesce timer in stmmac_xmit
> >> net: stmmac: Let descriptor code set skbuff address
> >> net: stmmac: Let descriptor code clear the descriptor
> >> net: stmmac: Uniformize the use of dma_{rx/tx}_mode callbacks
> >> net: stmmac: Remove uneeded checks for GMAC version
> >> net: stmmac: Move PTP and MMC base address calculation to hwif.c
> >> net: stmmac: Uniformize the use of dma_init_* callbacks
> >> net: stmmac: Remove uneeded check for GMAC version in stmmac_xmit
> >> net: stmmac: Uniformize set_rx_owner()
> >> net: stmmac: Let descriptor code get skbuff address
> >> net: stmmac: Remove if condition by taking advantage of hwif return
> >> code
> >>
> >> drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 82 +---
> >> .../net/ethernet/stmicro/stmmac/dwmac1000_dma.c| 92 ++
> >> drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c | 35 +++--
> >> drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c | 34 +++-
> >> drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c |7 +-
> >> drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h |1 -
> >> drivers/net/ethernet/stmicro/stmmac/enh_desc.c | 20 ++-
> >> drivers/net/ethernet/stmicro/stmmac/hwif.c | 34
> >> drivers/net/ethernet/stmicro/stmmac/hwif.h | 27 ++-
> >> drivers/net/ethernet/stmicro/stmmac/norm_desc.c| 20 ++-
> >> drivers/net/ethernet/stmicro/stmmac/stmmac.h |1 +
> >> drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 198
> >> +++-
> >> 12 files changed, 323 insertions(+), 228 deletions(-)
> >>
> >>
> > Hello
> >
> > You didnt have put in CC linux-ker...@vger.kernel.org as required by
> > get_maintener.pl letting more people to see this series.
> > Since this series touch dwmac-sun8i.c you should have also added Chen-Yu
> > Tsai/Maxime Ripard (as also asked by get_maintainer).
>
> Usually I just cc according to MAINTAINERS file but thanks for
> noticing. Added in cc now.
>
./scripts/get_maintainer.pl does this for you (and it use MAINTAINERS).
You have to use it at least, since it handle regex that could be easily unseen
like for dwmac-sun8i.
[PATCH v3 7/9] ARM: dts: sun8i: Enable sun8i-emac on the Orange PI One
From: Hans de Goede
The sun8i-emac hardware is present on the Orange PI One.
It uses the internal PHY.
This patch create the needed emac and phy nodes.
Signed-off-by: Hans de Goede
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index 0adf932..0bc3867 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -94,6 +94,16 @@
status = "okay";
};
+&emac {
+ phy = <&phy1>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
--
2.7.3
[PATCH v3 4/9] ARM: dts: sun8i-h3: Add dt node for the syscon control module
This patch add the dt node for the syscon register present on the
Allwinner H3.
Only two register are present in this syscon and the only one useful is
the one dedicated to EMAC clock.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index fdf9fdb..a39da6f 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -140,6 +140,11 @@
#size-cells = <1>;
ranges;
+ syscon: syscon@01c0 {
+ compatible = "syscon";
+ reg = <0x01c0 0x34>;
+ };
+
dma: dma-controller@01c02000 {
compatible = "allwinner,sun8i-h3-dma";
reg = <0x01c02000 0x1000>;
--
2.7.3
[PATCH v3 5/9] ARM: dts: sun8i-h3: add sun8i-emac ethernet driver
The sun8i-emac is an ethernet MAC hardware that support 10/100/1000
speed.
This patch enable the sun8i-emac on the Allwinner H3 SoC Device-tree.
The SoC H3 have an internal PHY, so optionals syscon and ephy are set.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index a39da6f..a3ac476 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -50,6 +50,10 @@
/ {
interrupt-parent = <&gic>;
+ aliases {
+ ethernet0 = &emac;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -446,6 +450,21 @@
status = "disabled";
};
+ emac: ethernet@1c3 {
+ compatible = "allwinner,sun8i-h3-emac";
+ syscon = <&syscon>;
+ reg = <0x01c3 0x104>;
+ reg-names = "emac";
+ interrupts = ;
+ resets = <&ccu RST_BUS_EMAC>, <&ccu RST_BUS_EPHY>;
+ reset-names = "ahb", "ephy";
+ clocks = <&ccu CLK_BUS_EMAC>, <&ccu CLK_BUS_EPHY>;
+ clock-names = "ahb", "ephy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
--
2.7.3
[PATCH v3 0/9] net-next: ethernet: add sun8i-emac driver
Hello This patch series add the driver for sun8i-emac which handle the Ethernet MAC present on Allwinner H3/A83T/A64 SoCs. It supports 10/100/1000 Mbit/s speed with half/full duplex. It can use an internal PHY (MII 10/100) or an external PHY via RGMII/RMII. This patch series enable the driver only for the H3 SoC since A83T and A64 doesn't have the necessary clocks present in mainline. This patch series enable the driver only for OrangePiPC and OrangePIOne boards since other board with H3 use external PHY which need optional regulators that will be supported later. The driver have been tested on the following boards: - H3 Orange PI PC, Orange PI Plus, BananaPI-M2+ - A64 Pine64 - A83T BananaPI-M3 I would like to thanks Chen-Yu Tsai for his help on developing this driver. Regards Changes since v2 - Added patch to support Orange PI One - Added a patch to enable SUN8I_EMAC in sunxi_defconfig - Added a patch to enable pm_runtime - The Emac clock is now used standard syscon/regmap - Added netdev_sent_queue/netdev_completed_queue - Added lots of documentation on working (locks, memory barrier, etc...) - Cleaned DT bindings documentation - Added ethernet0 aliases as suggested by Hans de Goede - Change prefix of all DEFINE to EMAC_ - The driver is now endian safe - Reworked the internal PHY mechanism - Removed dma_set_mask_and_coherent(32) since it is the default for of_platform_driver Changes since v1 - Implement NAPI - Sorted and reworded all define - Reworked ethtools stats strings - Removed all unneeded __packked and __aligned - Added tuning of RX/TX ring size via ethtool - Corrected use of sk/skb naming - Added some wmb when needed - Moved irq claim/free to emac_open/close - Lots of code refactoring Corentin Labbe (8): ethernet: sun8i-emac: add pm_runtime support ethernet: add sun8i-emac driver MAINTAINERS: Add myself as maintainer of sun8i-emac ARM: sun8i: dt: Add DT bindings documentation for Allwinner sun8i-emac ARM: dts: sun8i-h3: Add dt node for the syscon control module ARM: dts: sun8i-h3: add sun8i-emac ethernet driver ARM: dts: sun8i: Enable sun8i-emac on the Orange PI PC ARM: sunxi: Enable sun8i-emac driver on sunxi_defconfig Hans de Goede (1): ARM: dts: sun8i: Enable sun8i-emac on the Orange PI One .../bindings/net/allwinner,sun8i-emac.txt | 64 + MAINTAINERS|6 + arch/arm/boot/dts/sun8i-h3-orangepi-one.dts| 10 + arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 10 + arch/arm/boot/dts/sun8i-h3.dtsi| 24 + arch/arm/configs/sunxi_defconfig |1 + drivers/net/ethernet/allwinner/Kconfig | 13 + drivers/net/ethernet/allwinner/Makefile|1 + drivers/net/ethernet/allwinner/sun8i-emac.c| 2313 9 files changed, 2442 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt create mode 100644 drivers/net/ethernet/allwinner/sun8i-emac.c -- 2.7.3
[PATCH v3 3/9] ARM: sun8i: dt: Add DT bindings documentation for Allwinner sun8i-emac
This patch adds documentation for Device-Tree bindings for the
Allwinner sun8i-emac driver.
Signed-off-by: Corentin Labbe
---
.../bindings/net/allwinner,sun8i-emac.txt | 64 ++
1 file changed, 64 insertions(+)
create mode 100644
Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt
diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt
b/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt
new file mode 100644
index 000..4968ee3
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt
@@ -0,0 +1,64 @@
+* Allwinner sun8i EMAC ethernet controller
+
+Required properties:
+- compatible: should be one of the following string:
+ "allwinner,sun8i-a83t-emac"
+ "allwinner,sun8i-h3-emac"
+ "allwinner,sun50i-a64-emac"
+- reg: address and length of the register for the device.
+- reg-names: should be "emac"
+- syscon: A phandle to the syscon of the SoC
+- interrupts: interrupt for the device
+- clocks: A phandle to the reference clock for this device
+- clock-names: should be "ahb"
+- resets: A phandle to the reset control for this device
+- reset-names: should be "ahb"
+- phy-mode: See ethernet.txt
+- phy or phy-handle: See ethernet.txt
+- #address-cells: shall be 1
+- #size-cells: shall be 0
+
+"allwinner,sun8i-h3-emac" also requires:
+- clocks: an extra phandle to the reference clock for the EPHY
+- clock-names: an extra "ephy" entry matching the clocks property
+- resets: an extra phandle to the reset control for the EPHY
+- resets-names: an extra "ephy" entry matching the resets property
+
+See ethernet.txt in the same directory for generic bindings for ethernet
+controllers.
+
+The device node referenced by "phy" or "phy-handle" should be a child node
+of this node. See phy.txt for the generic PHY bindings.
+
+Optional properties:
+- allwinner,tx-delay: TX clock delay chain value. Range value is 0-0x07.
Default is 0)
+- allwinner,rx-delay: RX clock delay chain value. Range value is 0-0x1F.
Default is 0)
+
+The TX/RX clock delay chain settings are board specific.
+
+Optional properties for "allwinner,sun8i-h3-emac":
+- allwinner,leds-active-low: EPHY LEDs are active low
+
+Example:
+
+emac: ethernet@01c0b000 {
+ compatible = "allwinner,sun8i-h3-emac";
+ syscon = <&syscon>;
+ reg = <0x01c0b000 0x104>;
+ reg-names = "emac";
+ interrupts = ;
+ resets = <&ccu RST_BUS_EMAC>, <<&ccu RST_BUS_EPHY>;
+ reset-names = "ahb", "ephy";
+ clocks = <&ccu CLK_BUS_EMAC>, <&ccu CLK_BUS_EPHY>;
+ clock-names = "ahb", "ephy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy = <&phy1>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
--
2.7.3
[PATCH v3 6/9] ARM: dts: sun8i: Enable sun8i-emac on the Orange PI PC
The sun8i-emac hardware is present on the Orange PI PC.
It uses the internal PHY.
This patch create the needed emac and phy nodes.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index daf50b9a6..24f8e97 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -165,3 +165,13 @@
/* USB VBUS is always on */
status = "okay";
};
+
+&emac {
+ phy = <&phy1>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
--
2.7.3
[PATCH v3 1/9] ethernet: add sun8i-emac driver
This patch add support for sun8i-emac ethernet MAC hardware. It could be found in Allwinner H3/A83T/A64 SoCs. It supports 10/100/1000 Mbit/s speed with half/full duplex. It can use an internal PHY (MII 10/100) or an external PHY via RGMII/RMII. Signed-off-by: Corentin Labbe --- drivers/net/ethernet/allwinner/Kconfig | 13 + drivers/net/ethernet/allwinner/Makefile |1 + drivers/net/ethernet/allwinner/sun8i-emac.c | 2255 +++ 3 files changed, 2269 insertions(+) create mode 100644 drivers/net/ethernet/allwinner/sun8i-emac.c diff --git a/drivers/net/ethernet/allwinner/Kconfig b/drivers/net/ethernet/allwinner/Kconfig index 47da7e7..060569c 100644 --- a/drivers/net/ethernet/allwinner/Kconfig +++ b/drivers/net/ethernet/allwinner/Kconfig @@ -33,4 +33,17 @@ config SUN4I_EMAC To compile this driver as a module, choose M here. The module will be called sun4i-emac. +config SUN8I_EMAC + tristate "Allwinner sun8i EMAC support" + depends on ARCH_SUNXI || COMPILE_TEST + depends on OF + select MII + select PHYLIB +---help--- + This driver support the sun8i EMAC ethernet driver present on + H3/A83T/A64 Allwinner SoCs. + + To compile this driver as a module, choose M here. The module + will be called sun8i-emac. + endif # NET_VENDOR_ALLWINNER diff --git a/drivers/net/ethernet/allwinner/Makefile b/drivers/net/ethernet/allwinner/Makefile index 03129f7..8bd1693c 100644 --- a/drivers/net/ethernet/allwinner/Makefile +++ b/drivers/net/ethernet/allwinner/Makefile @@ -3,3 +3,4 @@ # obj-$(CONFIG_SUN4I_EMAC) += sun4i-emac.o +obj-$(CONFIG_SUN8I_EMAC) += sun8i-emac.o diff --git a/drivers/net/ethernet/allwinner/sun8i-emac.c b/drivers/net/ethernet/allwinner/sun8i-emac.c new file mode 100644 index 000..1c4bc80 --- /dev/null +++ b/drivers/net/ethernet/allwinner/sun8i-emac.c @@ -0,0 +1,2255 @@ +/* + * sun8i-emac driver + * + * Copyright (C) 2015-2016 Corentin LABBE + * + * This is the driver for Allwinner Ethernet MAC found in H3/A83T/A64 SoC + * + * TODO: + * - MAC filtering + * - Jumbo frame + * - features rx-all (NETIF_F_RXALL_BIT) + * - PM runtime + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EMAC_BASIC_CTL00x00 +#define EMAC_BASIC_CTL10x04 +#define EMAC_INT_STA 0x08 +#define EMAC_INT_EN0x0C +#define EMAC_TX_CTL0 0x10 +#define EMAC_TX_CTL1 0x14 +#define EMAC_TX_FLOW_CTL 0x1C +#define EMAC_RX_CTL0 0x24 +#define EMAC_RX_CTL1 0x28 +#define EMAC_RX_FRM_FLT0x38 +#define EMAC_MDIO_CMD 0x48 +#define EMAC_MDIO_DATA 0x4C +#define EMAC_TX_DMA_STA0xB0 +#define EMAC_TX_CUR_DESC 0xB4 +#define EMAC_TX_CUR_BUF0xB8 +#define EMAC_RX_DMA_STA0xC0 + +#define MDIO_CMD_MII_BUSY BIT(0) +#define MDIO_CMD_MII_WRITE BIT(1) +#define MDIO_CMD_MII_PHY_REG_ADDR_MASK GENMASK(8, 4) +#define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT4 +#define MDIO_CMD_MII_PHY_ADDR_MASK GENMASK(16, 12) +#define MDIO_CMD_MII_PHY_ADDR_SHIFT12 + +#define EMAC_MACADDR_HI0x50 +#define EMAC_MACADDR_LO0x54 + +#define EMAC_RX_DESC_LIST 0x34 +#define EMAC_TX_DESC_LIST 0x20 + +#define EMAC_RX_DO_CRC BIT(27) +#define EMAC_RX_STRIP_FCS BIT(28) + +#define LE32_BIT(x) (cpu_to_le32(BIT(x))) + +#define EMAC_COULD_BE_USED_BY_DMA LE32_BIT(31) + +/* Used in RX_CTL1*/ +#define EMAC_RX_DMA_EN BIT(30) +#define EMAC_RX_DMA_START BIT(31) +/* Used in TX_CTL1*/ +#define EMAC_TX_DMA_EN BIT(30) +#define EMAC_TX_DMA_START BIT(31) + +/* Used in RX_CTL0 */ +#define EMAC_RX_RECEIVER_ENBIT(31) +/* Used in TX_CTL0 */ +#define EMAC_TX_TRANSMITTER_EN BIT(31) + +/* Basic CTL0 */ +#define EMAC_BCTL0_FD BIT(0) +#define EMAC_BCTL0_SPEED_102 +#define EMAC_BCTL0_SPEED_100 3 +#define EMAC_BCTL0_SPEED_MASK GENMASK(3, 2) +#define EMAC_BCTL0_SPEED_SHIFT 2 + +#define EMAC_FLOW_RX 1 +#define EMAC_FLOW_TX 2 + +#define EMAC_TX_INTBIT(0) +#define EMAC_TX_DMA_STOP_INT BIT(1) +#define EMAC_TX_BUF_UA_INT BIT(2) +#define EMAC_TX_TIMEOUT_INTBIT(3) +#define EMAC_TX_UNDERFLOW_INT BIT(4) +#define EMAC_TX_EARLY_INT BIT(5) +#define EMAC_RX_INTBIT(8) +#define EMAC_RX_BUF_UA_INT BIT(9) +#define EMAC_RX_DMA_STOP_INT BIT(10) +#define EMAC_RX_TIMEOUT_INTBIT(11) +#define EMAC_RX_OVERFLOW_INT BIT(12) +#define EMAC_RX_EARLY_INT BIT(13) +#define EMAC_RGMII_STA_INT BIT(16) + +/* Bits used in frame RX status */ +#define EMAC_DSC_RX_FIRST BIT(9) +#define EMAC_DSC_RX_LAST BIT(8) + +/* Bits used in frame TX ctl */ +#define EMAC_MAGIC_TX_BIT LE32_BIT(24) +#define EMAC_TX_DO_CRC (LE32_BIT(27) | LE32_BIT(28)) +#define EMAC_DSC_TX_FIRST
[RFC PATCH 9/9] ethernet: sun8i-emac: add pm_runtime support
This patch add pm_runtime support to sun8i-emac.
For the moment, only basic support is added, (the device is marked as
used when net/open)
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/allwinner/sun8i-emac.c | 62 -
1 file changed, 60 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/allwinner/sun8i-emac.c
b/drivers/net/ethernet/allwinner/sun8i-emac.c
index 1c4bc80..cce886e 100644
--- a/drivers/net/ethernet/allwinner/sun8i-emac.c
+++ b/drivers/net/ethernet/allwinner/sun8i-emac.c
@@ -9,7 +9,6 @@
* - MAC filtering
* - Jumbo frame
* - features rx-all (NETIF_F_RXALL_BIT)
- * - PM runtime
*/
#include
#include
@@ -27,6 +26,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1301,11 +1301,18 @@ static int sun8i_emac_open(struct net_device *ndev)
int err;
u32 v;
+ err = pm_runtime_get_sync(priv->dev);
+ if (err) {
+ pm_runtime_put_noidle(priv->dev);
+ dev_err(priv->dev, "pm_runtime error: %d\n", err);
+ return err;
+ }
+
err = request_irq(priv->irq, sun8i_emac_dma_interrupt, 0,
dev_name(priv->dev), ndev);
if (err) {
dev_err(priv->dev, "Cannot request IRQ: %d\n", err);
- return err;
+ goto err_runtime;
}
/* Set interface mode (and configure internal PHY on H3) */
@@ -1395,6 +1402,8 @@ err_syscon:
sun8i_emac_unset_syscon(ndev);
err_irq:
free_irq(priv->irq, ndev);
+err_runtime:
+ pm_runtime_put(priv->dev);
return err;
}
@@ -1483,6 +1492,8 @@ static int sun8i_emac_stop(struct net_device *ndev)
dma_free_coherent(priv->dev, priv->nbdesc_tx * sizeof(struct dma_desc),
priv->dd_tx, priv->dd_tx_phy);
+ pm_runtime_put(priv->dev);
+
return 0;
}
@@ -2210,6 +2221,8 @@ static int sun8i_emac_probe(struct platform_device *pdev)
goto probe_err;
}
+ pm_runtime_enable(priv->dev);
+
return 0;
probe_err:
@@ -2221,6 +2234,8 @@ static int sun8i_emac_remove(struct platform_device *pdev)
{
struct net_device *ndev = platform_get_drvdata(pdev);
+ pm_runtime_disable(&pdev->dev);
+
unregister_netdev(ndev);
platform_set_drvdata(pdev, NULL);
free_netdev(ndev);
@@ -2228,6 +2243,47 @@ static int sun8i_emac_remove(struct platform_device
*pdev)
return 0;
}
+static int __maybe_unused sun8i_emac_suspend(struct platform_device *pdev,
pm_message_t state)
+{
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct sun8i_emac_priv *priv = netdev_priv(ndev);
+
+ napi_disable(&priv->napi);
+
+ if (netif_running(ndev))
+ netif_device_detach(ndev);
+
+ sun8i_emac_stop_tx(ndev);
+ sun8i_emac_stop_rx(ndev);
+
+ sun8i_emac_rx_clean(ndev);
+ sun8i_emac_tx_clean(ndev);
+
+ phy_stop(ndev->phydev);
+
+ return 0;
+}
+
+static int __maybe_unused sun8i_emac_resume(struct platform_device *pdev)
+{
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct sun8i_emac_priv *priv = netdev_priv(ndev);
+
+ phy_start(ndev->phydev);
+
+ sun8i_emac_start_tx(ndev);
+ sun8i_emac_start_rx(ndev);
+
+ if (netif_running(ndev))
+ netif_device_attach(ndev);
+
+ netif_start_queue(ndev);
+
+ napi_enable(&priv->napi);
+
+ return 0;
+}
+
static const struct of_device_id sun8i_emac_of_match_table[] = {
{ .compatible = "allwinner,sun8i-a83t-emac",
.data = &emac_variant_a83t },
@@ -2246,6 +2302,8 @@ static struct platform_driver sun8i_emac_driver = {
.name = "sun8i-emac",
.of_match_table = sun8i_emac_of_match_table,
},
+ .suspend= sun8i_emac_suspend,
+ .resume = sun8i_emac_resume,
};
module_platform_driver(sun8i_emac_driver);
--
2.7.3
[PATCH v3 2/9] MAINTAINERS: Add myself as maintainer of sun8i-emac
This patch add myself as maintainer of the sun8i-emac driver. Signed-off-by: Corentin Labbe --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 6781a3f..43f5be3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -582,6 +582,12 @@ S: Maintained F: Documentation/i2c/busses/i2c-ali1563 F: drivers/i2c/busses/i2c-ali1563.c +ALLWINNER SUN8I-EMAC ETHERNET DRIVER +M: Corentin Labbe +L: netdev@vger.kernel.org +S: Maintained +F: drivers/net/ethernet/allwinner/sun8i-emac.c + ALLWINNER SECURITY SYSTEM M: Corentin Labbe L: linux-cry...@vger.kernel.org -- 2.7.3
[PATCH v3 8/9] ARM: sunxi: Enable sun8i-emac driver on sunxi_defconfig
Enable the sun8i-emac driver in the sunxi default configuration Signed-off-by: Corentin Labbe --- arch/arm/configs/sunxi_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig index 714da33..153707a 100644 --- a/arch/arm/configs/sunxi_defconfig +++ b/arch/arm/configs/sunxi_defconfig @@ -40,6 +40,7 @@ CONFIG_ATA=y CONFIG_AHCI_SUNXI=y CONFIG_NETDEVICES=y CONFIG_SUN4I_EMAC=y +CONFIG_SUN8I_EMAC=y # CONFIG_NET_VENDOR_ARC is not set # CONFIG_NET_CADENCE is not set # CONFIG_NET_VENDOR_BROADCOM is not set -- 2.7.3
[PATCH v4 00/10] net-next: ethernet: add sun8i-emac driver
Hello This patch series add the driver for sun8i-emac which handle the Ethernet MAC present on Allwinner H3/A83T/A64 SoCs. It supports 10/100/1000 Mbit/s speed with half/full duplex. It can use an internal PHY (MII 10/100) or an external PHY via RGMII/RMII. This patch series enable the driver only for the H3 SoC since A83T and A64 doesn't have the necessary clocks present in mainline. This patch series enable the driver only for OrangePiPC and OrangePIOne boards since other board with H3 use external PHY which need optional regulators that will be supported later. The driver have been tested on the following boards: - H3 Orange PI PC, Orange PI Plus, BananaPI-M2+ - A64 Pine64 - A83T BananaPI-M3 I would like to thanks Chen-Yu Tsai for his help on developing this driver. Regards Changes since v3 - sun8i-emac require a DT mdio node - moved sun8i_emac_power() so that no clock/reset/regulator is used until netdev/open is called - Removed PM patch until proper tests are done - DT use phy-handle instead of phy - Moved DT aliases ethernet to subnodes - Renamed PHY nodes to [int|ext]_[r|g]mii_phy - Moved clock/reset for internal PHY to PHY node. Changes since v2 - Added patch to support Orange PI One - Added a patch to enable SUN8I_EMAC in sunxi_defconfig - Added a patch to enable pm_runtime - The Emac clock is now used standard syscon/regmap - Added netdev_sent_queue/netdev_completed_queue - Added lots of documentation on working (locks, memory barrier, etc...) - Cleaned DT bindings documentation - Added ethernet0 aliases as suggested by Hans de Goede - Change prefix of all DEFINE to EMAC_ - The driver is now endian safe - Reworked the internal PHY mechanism - Removed dma_set_mask_and_coherent(32) since it is the default for of_platform_driver Changes since v1 - Implement NAPI - Sorted and reworded all define - Reworked ethtools stats strings - Removed all unneeded __packked and __aligned - Added tuning of RX/TX ring size via ethtool - Corrected use of sk/skb naming - Added some wmb when needed - Moved irq claim/free to emac_open/close - Lots of code refactoring Corentin Labbe (9): ethernet: add sun8i-emac driver MAINTAINERS: Add myself as maintainer of sun8i-emac ARM: sun8i: dt: Add DT bindings documentation for Allwinner sun8i-emac ARM: dts: sun8i-h3: Add dt node for the syscon control module ARM: dts: sun8i-h3: add sun8i-emac ethernet driver ARM: dts: sun8i: Enable sun8i-emac on the Orange PI PC ARM: dts: sun8i: Enable sun8i-emac on the Orange Pi 2 ARM: sunxi: Enable sun8i-emac driver on multi_v7_defconfig ARM: sunxi: Enable sun8i-emac driver on sunxi_defconfig Hans de Goede (1): ARM: dts: sun8i: Enable sun8i-emac on the Orange PI One .../bindings/net/allwinner,sun8i-emac.txt | 70 + MAINTAINERS|6 + arch/arm/boot/dts/sun8i-h3-orangepi-2.dts |8 + arch/arm/boot/dts/sun8i-h3-orangepi-one.dts|8 + arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts |8 + arch/arm/boot/dts/sun8i-h3.dtsi| 29 + arch/arm/configs/multi_v7_defconfig|1 + arch/arm/configs/sunxi_defconfig |1 + drivers/net/ethernet/allwinner/Kconfig | 13 + drivers/net/ethernet/allwinner/Makefile|1 + drivers/net/ethernet/allwinner/sun8i-emac.c| 2266 11 files changed, 2411 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt create mode 100644 drivers/net/ethernet/allwinner/sun8i-emac.c -- 2.7.3
[PATCH v4 02/10] MAINTAINERS: Add myself as maintainer of sun8i-emac
This patch add myself as maintainer of the sun8i-emac driver. Signed-off-by: Corentin Labbe --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 40f4629..e197d82 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -582,6 +582,12 @@ S: Maintained F: Documentation/i2c/busses/i2c-ali1563 F: drivers/i2c/busses/i2c-ali1563.c +ALLWINNER SUN8I-EMAC ETHERNET DRIVER +M: Corentin Labbe +L: netdev@vger.kernel.org +S: Maintained +F: drivers/net/ethernet/allwinner/sun8i-emac.c + ALLWINNER SECURITY SYSTEM M: Corentin Labbe L: linux-cry...@vger.kernel.org -- 2.7.3
[PATCH v4 03/10] ARM: sun8i: dt: Add DT bindings documentation for Allwinner sun8i-emac
This patch adds documentation for Device-Tree bindings for the
Allwinner sun8i-emac driver.
Signed-off-by: Corentin Labbe
---
.../bindings/net/allwinner,sun8i-emac.txt | 70 ++
1 file changed, 70 insertions(+)
create mode 100644
Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt
diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt
b/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt
new file mode 100644
index 000..92e4ef3b
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-emac.txt
@@ -0,0 +1,70 @@
+* Allwinner sun8i EMAC ethernet controller
+
+Required properties:
+- compatible: should be one of the following string:
+ "allwinner,sun8i-a83t-emac"
+ "allwinner,sun8i-h3-emac"
+ "allwinner,sun50i-a64-emac"
+- reg: address and length of the register for the device.
+- syscon: A phandle to the syscon of the SoC
+- interrupts: interrupt for the device
+- clocks: A phandle to the reference clock for this device
+- clock-names: should be "ahb"
+- resets: A phandle to the reset control for this device
+- reset-names: should be "ahb"
+- phy-mode: See ethernet.txt
+- phy-handle: See ethernet.txt
+- #address-cells: shall be 1
+- #size-cells: shall be 0
+
+Optional properties:
+- allwinner,tx-delay: TX clock delay chain value. Range value is 0-0x07.
Default is 0)
+- allwinner,rx-delay: RX clock delay chain value. Range value is 0-0x1F.
Default is 0)
+Both delay properties does not have units, there are arbitrary value.
+The TX/RX clock delay chain settings are board specific and could be found
+in vendor FEX files.
+
+Optional properties for "allwinner,sun8i-h3-emac":
+- allwinner,leds-active-low: EPHY LEDs are active low
+
+Required child node of emac:
+- mdio bus node: should be named mdio
+
+Required properties of the mdio node:
+- #address-cells: shall be 1
+- #size-cells: shall be 0
+
+The device node referenced by "phy" or "phy-handle" should be a child node
+of the mdio node. See phy.txt for the generic PHY bindings.
+
+Required properties of the phy node with "allwinner,sun8i-h3-emac":
+- clocks: an extra phandle to the reference clock for the EPHY
+- resets: an extra phandle to the reset control for the EPHY
+
+Example:
+
+emac: ethernet@01c0b000 {
+ compatible = "allwinner,sun8i-h3-emac";
+ syscon = <&syscon>;
+ reg = <0x01c0b000 0x104>;
+ interrupts = ;
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "ahb";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "ahb";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ };
+ };
+};
--
2.7.3
[PATCH v4 09/10] ARM: sunxi: Enable sun8i-emac driver on sunxi_defconfig
Enable the sun8i-emac driver in the sunxi default configuration Signed-off-by: Corentin Labbe --- arch/arm/configs/sunxi_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig index 714da33..153707a 100644 --- a/arch/arm/configs/sunxi_defconfig +++ b/arch/arm/configs/sunxi_defconfig @@ -40,6 +40,7 @@ CONFIG_ATA=y CONFIG_AHCI_SUNXI=y CONFIG_NETDEVICES=y CONFIG_SUN4I_EMAC=y +CONFIG_SUN8I_EMAC=y # CONFIG_NET_VENDOR_ARC is not set # CONFIG_NET_CADENCE is not set # CONFIG_NET_VENDOR_BROADCOM is not set -- 2.7.3
[PATCH v4 01/10] ethernet: add sun8i-emac driver
This patch add support for sun8i-emac ethernet MAC hardware. It could be found in Allwinner H3/A83T/A64 SoCs. It supports 10/100/1000 Mbit/s speed with half/full duplex. It can use an internal PHY (MII 10/100) or an external PHY via RGMII/RMII. Signed-off-by: Corentin Labbe --- drivers/net/ethernet/allwinner/Kconfig | 13 + drivers/net/ethernet/allwinner/Makefile |1 + drivers/net/ethernet/allwinner/sun8i-emac.c | 2266 +++ 3 files changed, 2280 insertions(+) create mode 100644 drivers/net/ethernet/allwinner/sun8i-emac.c diff --git a/drivers/net/ethernet/allwinner/Kconfig b/drivers/net/ethernet/allwinner/Kconfig index 47da7e7..060569c 100644 --- a/drivers/net/ethernet/allwinner/Kconfig +++ b/drivers/net/ethernet/allwinner/Kconfig @@ -33,4 +33,17 @@ config SUN4I_EMAC To compile this driver as a module, choose M here. The module will be called sun4i-emac. +config SUN8I_EMAC + tristate "Allwinner sun8i EMAC support" + depends on ARCH_SUNXI || COMPILE_TEST + depends on OF + select MII + select PHYLIB +---help--- + This driver support the sun8i EMAC ethernet driver present on + H3/A83T/A64 Allwinner SoCs. + + To compile this driver as a module, choose M here. The module + will be called sun8i-emac. + endif # NET_VENDOR_ALLWINNER diff --git a/drivers/net/ethernet/allwinner/Makefile b/drivers/net/ethernet/allwinner/Makefile index 03129f7..8bd1693c 100644 --- a/drivers/net/ethernet/allwinner/Makefile +++ b/drivers/net/ethernet/allwinner/Makefile @@ -3,3 +3,4 @@ # obj-$(CONFIG_SUN4I_EMAC) += sun4i-emac.o +obj-$(CONFIG_SUN8I_EMAC) += sun8i-emac.o diff --git a/drivers/net/ethernet/allwinner/sun8i-emac.c b/drivers/net/ethernet/allwinner/sun8i-emac.c new file mode 100644 index 000..aa525d7 --- /dev/null +++ b/drivers/net/ethernet/allwinner/sun8i-emac.c @@ -0,0 +1,2266 @@ +/* + * sun8i-emac driver + * + * Copyright (C) 2015-2016 Corentin LABBE + * + * This is the driver for Allwinner Ethernet MAC found in H3/A83T/A64 SoC + * + * TODO: + * - MAC filtering + * - Jumbo frame + * - features rx-all (NETIF_F_RXALL_BIT) + * - PM runtime + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EMAC_BASIC_CTL00x00 +#define EMAC_BASIC_CTL10x04 +#define EMAC_INT_STA 0x08 +#define EMAC_INT_EN0x0C +#define EMAC_TX_CTL0 0x10 +#define EMAC_TX_CTL1 0x14 +#define EMAC_TX_FLOW_CTL 0x1C +#define EMAC_RX_CTL0 0x24 +#define EMAC_RX_CTL1 0x28 +#define EMAC_RX_FRM_FLT0x38 +#define EMAC_MDIO_CMD 0x48 +#define EMAC_MDIO_DATA 0x4C +#define EMAC_TX_DMA_STA0xB0 +#define EMAC_TX_CUR_DESC 0xB4 +#define EMAC_TX_CUR_BUF0xB8 +#define EMAC_RX_DMA_STA0xC0 + +#define MDIO_CMD_MII_BUSY BIT(0) +#define MDIO_CMD_MII_WRITE BIT(1) +#define MDIO_CMD_MII_PHY_REG_ADDR_MASK GENMASK(8, 4) +#define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT4 +#define MDIO_CMD_MII_PHY_ADDR_MASK GENMASK(16, 12) +#define MDIO_CMD_MII_PHY_ADDR_SHIFT12 + +#define EMAC_MACADDR_HI0x50 +#define EMAC_MACADDR_LO0x54 + +#define EMAC_RX_DESC_LIST 0x34 +#define EMAC_TX_DESC_LIST 0x20 + +#define EMAC_RX_DO_CRC BIT(27) +#define EMAC_RX_STRIP_FCS BIT(28) + +#define LE32_BIT(x) (cpu_to_le32(BIT(x))) + +#define EMAC_COULD_BE_USED_BY_DMA LE32_BIT(31) + +/* Used in RX_CTL1*/ +#define EMAC_RX_DMA_EN BIT(30) +#define EMAC_RX_DMA_START BIT(31) +/* Used in TX_CTL1*/ +#define EMAC_TX_DMA_EN BIT(30) +#define EMAC_TX_DMA_START BIT(31) + +/* Used in RX_CTL0 */ +#define EMAC_RX_RECEIVER_ENBIT(31) +/* Used in TX_CTL0 */ +#define EMAC_TX_TRANSMITTER_EN BIT(31) + +/* Basic CTL0 */ +#define EMAC_BCTL0_FD BIT(0) +#define EMAC_BCTL0_SPEED_102 +#define EMAC_BCTL0_SPEED_100 3 +#define EMAC_BCTL0_SPEED_MASK GENMASK(3, 2) +#define EMAC_BCTL0_SPEED_SHIFT 2 + +#define EMAC_FLOW_RX 1 +#define EMAC_FLOW_TX 2 + +#define EMAC_TX_INTBIT(0) +#define EMAC_TX_DMA_STOP_INT BIT(1) +#define EMAC_TX_BUF_UA_INT BIT(2) +#define EMAC_TX_TIMEOUT_INTBIT(3) +#define EMAC_TX_UNDERFLOW_INT BIT(4) +#define EMAC_TX_EARLY_INT BIT(5) +#define EMAC_RX_INTBIT(8) +#define EMAC_RX_BUF_UA_INT BIT(9) +#define EMAC_RX_DMA_STOP_INT BIT(10) +#define EMAC_RX_TIMEOUT_INTBIT(11) +#define EMAC_RX_OVERFLOW_INT BIT(12) +#define EMAC_RX_EARLY_INT BIT(13) +#define EMAC_RGMII_STA_INT BIT(16) + +/* Bits used in frame RX status */ +#define EMAC_DSC_RX_FIRST BIT(9) +#define EMAC_DSC_RX_LAST BIT(8) + +/* Bits used in frame TX ctl */ +#define EMAC_MAGIC_TX_BIT LE32_BIT(24) +#define EMAC_TX_DO_CRC (LE32_BIT(27) | LE32_BIT(28)) +#define EMAC_DSC_TX_FIRST
[PATCH v4 05/10] ARM: dts: sun8i-h3: add sun8i-emac ethernet driver
The sun8i-emac is an ethernet MAC hardware that support 10/100/1000
speed.
This patch enable the sun8i-emac on the Allwinner H3 SoC Device-tree.
The SoC H3 have an internal PHY, so optionals syscon and ephy are set.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 1101d2f..d218154 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -446,6 +446,30 @@
status = "disabled";
};
+ emac: ethernet@1c3 {
+ compatible = "allwinner,sun8i-h3-emac";
+ syscon = <&syscon>;
+ reg = <0x01c3 0x104>;
+ interrupts = ;
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "ahb";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "ahb";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ };
+ };
+ };
+
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
--
2.7.3
[PATCH v4 06/10] ARM: dts: sun8i: Enable sun8i-emac on the Orange PI PC
The sun8i-emac hardware is present on the Orange PI PC.
It uses the internal PHY.
This patch create the needed emac node.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index daf50b9a6..71717cc 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -54,6 +54,7 @@
aliases {
serial0 = &uart0;
+ ethernet0 = &emac;
};
chosen {
@@ -165,3 +166,10 @@
/* USB VBUS is always on */
status = "okay";
};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
--
2.7.3
[PATCH v4 04/10] ARM: dts: sun8i-h3: Add dt node for the syscon control module
This patch add the dt node for the syscon register present on the
Allwinner H3.
Only two register are present in this syscon and the only one useful is
the one dedicated to EMAC clock.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 8a95e36..1101d2f 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -140,6 +140,11 @@
#size-cells = <1>;
ranges;
+ syscon: syscon@01c0 {
+ compatible = "syscon";
+ reg = <0x01c0 0x1000>;
+ };
+
dma: dma-controller@01c02000 {
compatible = "allwinner,sun8i-h3-dma";
reg = <0x01c02000 0x1000>;
--
2.7.3
[PATCH v4 07/10] ARM: dts: sun8i: Enable sun8i-emac on the Orange PI One
From: Hans de Goede
The sun8i-emac hardware is present on the Orange PI One.
It uses the internal PHY.
This patch create the needed emac node.
Signed-off-by: Hans de Goede
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index 0adf932..25f2455 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -54,6 +54,7 @@
aliases {
serial0 = &uart0;
+ ethernet0 = &emac;
};
chosen {
@@ -94,6 +95,13 @@
status = "okay";
};
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
--
2.7.3
[PATCH v4 08/10] ARM: dts: sun8i: Enable sun8i-emac on the Orange Pi 2
The sun8i-emac hardware is present on the Orange PI 2.
It uses the internal PHY.
This patch create the needed emac node.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index f93f5d1..5608eb4 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -54,6 +54,7 @@
aliases {
serial0 = &uart0;
+ ethernet0 = &emac;
};
chosen {
@@ -184,3 +185,10 @@
usb1_vbus-supply = <®_usb1_vbus>;
status = "okay";
};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
--
2.7.3
[PATCH v4 10/10] ARM: sunxi: Enable sun8i-emac driver on multi_v7_defconfig
Enable the sun8i-emac driver in the multi_v7 default configuration Signed-off-by: Corentin Labbe --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 5845910..f44d633 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -229,6 +229,7 @@ CONFIG_NETDEVICES=y CONFIG_VIRTIO_NET=y CONFIG_HIX5HD2_GMAC=y CONFIG_SUN4I_EMAC=y +CONFIG_SUN8I_EMAC=y CONFIG_MACB=y CONFIG_BCMGENET=m CONFIG_SYSTEMPORT=m -- 2.7.3
[PATCH 1/2] net: stmmac: avoid Camelcase naming
This patch simply rename regValue to value, like it was named in other mdio functions. Signed-off-by: Corentin Labbe --- drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c index e3216e5..6796c28 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c @@ -83,14 +83,14 @@ static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) unsigned int mii_data = priv->hw->mii.data; int data; - u16 regValue = (((phyaddr << 11) & (0xF800)) | + u16 value = (((phyaddr << 11) & (0xF800)) | ((phyreg << 6) & (0x07C0))); - regValue |= MII_BUSY | ((priv->clk_csr & 0xF) << 2); + value |= MII_BUSY | ((priv->clk_csr & 0xF) << 2); if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address)) return -EBUSY; - writel(regValue, priv->ioaddr + mii_address); + writel(value, priv->ioaddr + mii_address); if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address)) return -EBUSY; -- 2.7.3
[PATCH 2/2] net: stmmac: unify mdio functions
stmmac_mdio_{read|write} and stmmac_mdio_{read|write}_gmac4 are not
enought different for being split.
The only differences between thoses two functions are shift/mask for
addr/reg/clk_csr.
This patch introduce a per platform set of variable for setting thoses
shift/mask and unify mdio read and write functions.
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/common.h | 6 +
.../net/ethernet/stmicro/stmmac/dwmac1000_core.c | 6 +
.../net/ethernet/stmicro/stmmac/dwmac100_core.c| 7 ++
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 6 +
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 121 -
5 files changed, 48 insertions(+), 98 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h
b/drivers/net/ethernet/stmicro/stmmac/common.h
index 5bd4c05..3ced2e1 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -507,6 +507,12 @@ struct mac_link {
struct mii_regs {
unsigned int addr; /* MII Address */
unsigned int data; /* MII Data */
+ unsigned int addr_shift;/* MII address shift */
+ unsigned int reg_shift; /* MII reg shift */
+ unsigned int addr_mask; /* MII address mask */
+ unsigned int reg_mask; /* MII reg mask */
+ unsigned int clk_csr_shift;
+ unsigned int clk_csr_mask;
};
/* Helpers to manage the descriptors for chain and ring modes */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
index 7df4ff1..b21d03f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
@@ -534,6 +534,12 @@ struct mac_device_info *dwmac1000_setup(void __iomem
*ioaddr, int mcbins,
mac->link.speed = GMAC_CONTROL_FES;
mac->mii.addr = GMAC_MII_ADDR;
mac->mii.data = GMAC_MII_DATA;
+ mac->mii.addr_shift = 11;
+ mac->mii.addr_mask = 0xF800;
+ mac->mii.reg_shift = 6;
+ mac->mii.reg_mask = 0x07C0;
+ mac->mii.clk_csr_shift = 2;
+ mac->mii.clk_csr_mask = 0xF;
/* Get and dump the chip ID */
*synopsys_id = stmmac_get_synopsys_id(hwid);
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
index 6418b2e..a1d582f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
@@ -192,6 +192,13 @@ struct mac_device_info *dwmac100_setup(void __iomem
*ioaddr, int *synopsys_id)
mac->link.speed = 0;
mac->mii.addr = MAC_MII_ADDR;
mac->mii.data = MAC_MII_DATA;
+ mac->mii.addr_shift = 11;
+ mac->mii.addr_mask = 0xF800;
+ mac->mii.reg_shift = 6;
+ mac->mii.reg_mask = 0x07C0;
+ mac->mii.clk_csr_shift = 2;
+ mac->mii.clk_csr_mask = 0xF;
+
/* Synopsys Id is not available on old chips */
*synopsys_id = 0;
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
index 51019b7..eaed7cb 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
@@ -430,6 +430,12 @@ struct mac_device_info *dwmac4_setup(void __iomem *ioaddr,
int mcbins,
mac->link.speed = GMAC_CONFIG_FES;
mac->mii.addr = GMAC_MDIO_ADDR;
mac->mii.data = GMAC_MDIO_DATA;
+ mac->mii.addr_shift = 21;
+ mac->mii.addr_mask = GENMASK(25, 21);
+ mac->mii.reg_shift = 16;
+ mac->mii.reg_mask = GENMASK(20, 16);
+ mac->mii.clk_csr_shift = 8;
+ mac->mii.clk_csr_mask = GENMASK(11, 8);
/* Get and dump the chip ID */
*synopsys_id = stmmac_get_synopsys_id(hwid);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
index 6796c28..23322fd 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
@@ -42,13 +42,6 @@
#define MII_GMAC4_WRITE(1 << MII_GMAC4_GOC_SHIFT)
#define MII_GMAC4_READ (3 << MII_GMAC4_GOC_SHIFT)
-#define MII_PHY_ADDR_GMAC4_SHIFT 21
-#define MII_PHY_ADDR_GMAC4_MASKGENMASK(25, 21)
-#define MII_PHY_REG_GMAC4_SHIFT16
-#define MII_PHY_REG_GMAC4_MASK GENMASK(20, 16)
-#define MII_CSR_CLK_GMAC4_SHIFT8
-#define MII_CSR_CLK_GMAC4_MASK GENMASK(11, 8)
-
static int stmmac_mdio_busy_wait(void __iomem *ioaddr, unsigned int mii_addr)
{
unsigned long curr;
@@ -68,8 +61,8 @@ static int stmmac_mdio_busy_wait(void __iomem *ioaddr,
unsigned int mii_addr)
/**
* stmmac_mdio_read
* @bus: points to th
Re: [PATCH 1/2] net: stmmac: avoid Camelcase naming
On Fri, Dec 02, 2016 at 09:44:48AM +0100, Giuseppe CAVALLARO wrote: > Hello Corentin > > patches look ok, I just wonder if you tested it in case of > the stmmac is connected to a transceiver. Let me consider it > a critical part of the driver to properly work. > > Regards > Peppe > I tested it on a Cubieboard 2 (dwmac-sunxi). What do you mean by "connected to a transceiver" ? an external PHY ? Regards
[PATCH 1/5] irda: irproc.c: Remove unneeded linux/miscdevice.h include
irproc.c does not use any miscdevice so this patch remove this unnecessary inclusion. Signed-off-by: Corentin Labbe --- net/irda/irproc.c | 1 - 1 file changed, 1 deletion(-) diff --git a/net/irda/irproc.c b/net/irda/irproc.c index b9ac598..77cfdde 100644 --- a/net/irda/irproc.c +++ b/net/irda/irproc.c @@ -23,7 +23,6 @@ * / -#include #include #include #include -- 2.10.2
[PATCH 3/5] irnet: ppp: move IRNET_MINOR to include/linux/miscdevice.h
This patch move the define for IRNET_MINOR to include/linux/miscdevice.h It is better that all minor number definitions are in the same place. Signed-off-by: Corentin Labbe --- include/linux/miscdevice.h | 1 + net/irda/irnet/irnet_ppp.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/miscdevice.h b/include/linux/miscdevice.h index 18b2e3b..5ea0a65 100644 --- a/include/linux/miscdevice.h +++ b/include/linux/miscdevice.h @@ -37,6 +37,7 @@ #define HWRNG_MINOR183 #define MICROCODE_MINOR184 #define KEYPAD_MINOR 185 +#define IRNET_MINOR187 #define D7S_MINOR 193 #define VFIO_MINOR 196 #define TUN_MINOR 200 diff --git a/net/irda/irnet/irnet_ppp.h b/net/irda/irnet/irnet_ppp.h index 693ebc0..18fcead 100644 --- a/net/irda/irnet/irnet_ppp.h +++ b/net/irda/irnet/irnet_ppp.h @@ -21,7 +21,6 @@ /* /dev/irnet file constants */ #define IRNET_MAJOR10 /* Misc range */ -#define IRNET_MINOR187 /* Official allocation */ /* IrNET control channel stuff */ #define IRNET_MAX_COMMAND 256 /* Max length of a command line */ -- 2.10.2
[PATCH 5/5] irda: irnet: add member name to the miscdevice declaration
Since the struct miscdevice have many members, it is dangerous to init
it without members name relying only on member order.
This patch add member name to the init declaration.
Signed-off-by: Corentin Labbe
---
net/irda/irnet/irnet_ppp.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/net/irda/irnet/irnet_ppp.h b/net/irda/irnet/irnet_ppp.h
index ec092c9..1ed17f9 100644
--- a/net/irda/irnet/irnet_ppp.h
+++ b/net/irda/irnet/irnet_ppp.h
@@ -108,9 +108,9 @@ static const struct file_operations irnet_device_fops =
/* Structure so that the misc major (drivers/char/misc.c) take care of us... */
static struct miscdevice irnet_misc_device =
{
- IRNET_MINOR,
- "irnet",
- &irnet_device_fops
+ .minor = IRNET_MINOR,
+ .name = "irnet",
+ .file_operations = &irnet_device_fops
};
#endif /* IRNET_PPP_H */
--
2.10.2
[PATCH 4/5] irda: irnet: Remove unused IRNET_MAJOR define
The IRNET_MAJOR define is not used, so this patch remove it. Signed-off-by: Corentin Labbe --- net/irda/irnet/irnet_ppp.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/net/irda/irnet/irnet_ppp.h b/net/irda/irnet/irnet_ppp.h index 18fcead..ec092c9 100644 --- a/net/irda/irnet/irnet_ppp.h +++ b/net/irda/irnet/irnet_ppp.h @@ -19,9 +19,6 @@ / CONSTANTS & MACROS / -/* /dev/irnet file constants */ -#define IRNET_MAJOR10 /* Misc range */ - /* IrNET control channel stuff */ #define IRNET_MAX_COMMAND 256 /* Max length of a command line */ -- 2.10.2
[PATCH 2/5] irda: irnet: Move linux/miscdevice.h include
The only use of miscdevice is irda_ppp so no need to include linux/miscdevice.h for all irda files. This patch move the linux/miscdevice.h include to irnet_ppp.h Signed-off-by: Corentin Labbe --- net/irda/irnet/irnet.h | 1 - net/irda/irnet/irnet_ppp.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/net/irda/irnet/irnet.h b/net/irda/irnet/irnet.h index 8d65bb9..c69f0f3 100644 --- a/net/irda/irnet/irnet.h +++ b/net/irda/irnet/irnet.h @@ -245,7 +245,6 @@ #include #include #include -#include #include #include #include/* isspace() */ diff --git a/net/irda/irnet/irnet_ppp.h b/net/irda/irnet/irnet_ppp.h index 9402258..693ebc0 100644 --- a/net/irda/irnet/irnet_ppp.h +++ b/net/irda/irnet/irnet_ppp.h @@ -15,6 +15,7 @@ /* INCLUDES */ #include "irnet.h" /* Module global include */ +#include / CONSTANTS & MACROS / -- 2.10.2
Re: [PATCH 3/5] net: thunderx: Fix configuration of L3/L4 length checking
On Mon, Nov 14, 2016 at 04:24:44PM +0530, sunil.kovv...@gmail.com wrote:
> From: Sunil Goutham
>
> This patch fixes enabling of HW verification of L3/L4 length and
> TCP/UDP checksum which is currently being cleared. Also fixed VLAN
> stripping config which is being cleared when multiqset is enabled.
>
> Signed-off-by: Sunil Goutham
> ---
> drivers/net/ethernet/cavium/thunder/nicvf_queues.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_queues.c
> b/drivers/net/ethernet/cavium/thunder/nicvf_queues.c
> index f0e0ca6..3050177 100644
> --- a/drivers/net/ethernet/cavium/thunder/nicvf_queues.c
> +++ b/drivers/net/ethernet/cavium/thunder/nicvf_queues.c
> @@ -538,9 +538,12 @@ static void nicvf_rcv_queue_config(struct nicvf *nic,
> struct queue_set *qs,
> mbx.rq.cfg = (1ULL << 62) | (RQ_CQ_DROP << 8);
> nicvf_send_msg_to_pf(nic, &mbx);
>
> - nicvf_queue_reg_write(nic, NIC_QSET_RQ_GEN_CFG, 0, 0x00);
> - if (!nic->sqs_mode)
> + if (!nic->sqs_mode && (qidx == 0)) {
> + /* Enable checking L3/L4 length and TCP/UDP checksums */
> + nicvf_queue_reg_write(nic, NIC_QSET_RQ_GEN_CFG, 0,
> + ((1 << 24) | (1 << 23) | (1 << 21)));
Hello
You could use the BIT() macro here
Regards
[PATCH 2/3] net: stmmac: replace hardcoded function name by __func__
From: LABBE Corentin Some printing have the function name hardcoded. It is better to use __func__ instead. Signed-off-by: Corentin Labbe --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 791daf4..d160bdb 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -849,7 +849,7 @@ static int stmmac_init_phy(struct net_device *dev) snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, priv->plat->phy_addr); - netdev_dbg(priv->dev, "stmmac_init_phy: trying to attach to %s\n", + netdev_dbg(priv->dev, "%s: trying to attach to %s\n", __func__, phy_id_fmt); phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, @@ -890,9 +890,8 @@ static int stmmac_init_phy(struct net_device *dev) if (phydev->is_pseudo_fixed_link) phydev->irq = PHY_POLL; - netdev_dbg(priv->dev, - "stmmac_init_phy: attached to PHY (UID 0x%x) Link = %d\n", - phydev->phy_id, phydev->link); + netdev_dbg(priv->dev, "%s: attached to PHY (UID 0x%x) Link = %d\n", + __func__, phydev->phy_id, phydev->link); return 0; } -- 2.7.3
[PATCH 1/3] net: stmmac: replace all pr_xxx by their netdev_xxx counterpart
From: LABBE Corentin
The stmmac driver use lots of pr_xxx functions to print information.
This is bad since we cannot know which device logs the information.
(moreover if two stmmac device are present)
Furthermore, it seems that it assumes wrongly that all logs will always
be subsequent by using a dev_xxx then some indented pr_xxx like this:
kernel: sun7i-dwmac 1c5.ethernet: no reset control found
kernel: Ring mode enabled
kernel: No HW DMA feature register supported
kernel: Normal descriptors
kernel: TX Checksum insertion supported
So this patch replace all pr_xxx by their netdev_xxx counterpart.
Excepts for some printing where netdev "cause" unpretty output like:
sun7i-dwmac 1c5.ethernet (unnamed net_device) (uninitialized): no reset
control found
In those case, I keep dev_xxx.
In the same time I remove some "stmmac:" print since
this will be a duplicate with that dev_xxx displays.
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 204 --
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 14 +-
2 files changed, 123 insertions(+), 95 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 8eb12353..791daf4 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -305,7 +305,7 @@ bool stmmac_eee_init(struct stmmac_priv *priv)
*/
spin_lock_irqsave(&priv->lock, flags);
if (priv->eee_active) {
- pr_debug("stmmac: disable EEE\n");
+ netdev_dbg(priv->dev, "disable EEE\n");
del_timer_sync(&priv->eee_ctrl_timer);
priv->hw->mac->set_eee_timer(priv->hw, 0,
tx_lpi_timer);
@@ -334,7 +334,7 @@ bool stmmac_eee_init(struct stmmac_priv *priv)
ret = true;
spin_unlock_irqrestore(&priv->lock, flags);
- pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
+ netdev_dbg(priv->dev, "Energy-Efficient Ethernet
initialized\n");
}
out:
return ret;
@@ -456,8 +456,8 @@ static int stmmac_hwtstamp_ioctl(struct net_device *dev,
struct ifreq *ifr)
sizeof(struct hwtstamp_config)))
return -EFAULT;
- pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
-__func__, config.flags, config.tx_type, config.rx_filter);
+ netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x,
rx_filter:0x%x\n",
+ __func__, config.flags, config.tx_type, config.rx_filter);
/* reserved for future extensions */
if (config.flags)
@@ -756,8 +756,9 @@ static void stmmac_adjust_link(struct net_device *dev)
break;
default:
if (netif_msg_link(priv))
- pr_warn("%s: Speed (%d) not 10/100\n",
- dev->name, phydev->speed);
+ netdev_warn(priv->dev,
+ "Speed (%d) not 10/100\n",
+ phydev->speed);
break;
}
@@ -810,10 +811,10 @@ static void stmmac_check_pcs_mode(struct stmmac_priv
*priv)
(interface == PHY_INTERFACE_MODE_RGMII_ID) ||
(interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
(interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
- pr_debug("STMMAC: PCS RGMII support enable\n");
+ netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
priv->hw->pcs = STMMAC_PCS_RGMII;
} else if (interface == PHY_INTERFACE_MODE_SGMII) {
- pr_debug("STMMAC: PCS SGMII support enable\n");
+ netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
priv->hw->pcs = STMMAC_PCS_SGMII;
}
}
@@ -848,15 +849,15 @@ static int stmmac_init_phy(struct net_device *dev)
snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
priv->plat->phy_addr);
- pr_debug("stmmac_init_phy: trying to attach to %s\n",
-phy_id_fmt);
+ netdev_dbg(priv->dev, "stmmac_init_phy: trying to attach to
%s\n",
+
[PATCH 3/3] net: stmmac: replace if (netif_msg_type) by their netif_xxx counterpart
From: LABBE Corentin
As sugested by Joe Perches, we could replace all
if (netif_msg_type(priv)) dev_xxx(priv->devices, ...)
by the simpler macro netif_xxx(priv, hw, priv->dev, ...)
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 49 ++-
1 file changed, 21 insertions(+), 28 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index d160bdb..fbd1cd7 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -755,10 +755,9 @@ static void stmmac_adjust_link(struct net_device *dev)
stmmac_hw_fix_mac_speed(priv);
break;
default:
- if (netif_msg_link(priv))
- netdev_warn(priv->dev,
- "Speed (%d) not 10/100\n",
- phydev->speed);
+ netif_warn(priv, link, priv->dev,
+ "Speed (%d) not 10/100\n",
+ phydev->speed);
break;
}
@@ -1036,14 +1035,14 @@ static int init_dma_desc_rings(struct net_device *dev,
gfp_t flags)
priv->dma_buf_sz = bfsize;
- if (netif_msg_probe(priv)) {
- netdev_dbg(priv->dev, "(%s) dma_rx_phy=0x%08x
dma_tx_phy=0x%08x\n",
- __func__, (u32)priv->dma_rx_phy,
- (u32)priv->dma_tx_phy);
+ netif_dbg(priv, probe, priv->dev,
+ "(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n",
+ __func__, (u32)priv->dma_rx_phy, (u32)priv->dma_tx_phy);
+
+ /* RX INITIALIZATION */
+ netif_dbg(priv, probe, priv->dev,
+ "SKB addresses:\nskb\t\tskb data\tdma data\n");
- /* RX INITIALIZATION */
- netdev_dbg(priv->dev, "SKB addresses:\nskb\t\tskb data\tdma
data\n");
- }
for (i = 0; i < DMA_RX_SIZE; i++) {
struct dma_desc *p;
if (priv->extend_desc)
@@ -1055,11 +1054,9 @@ static int init_dma_desc_rings(struct net_device *dev,
gfp_t flags)
if (ret)
goto err_init_rx_buffers;
- if (netif_msg_probe(priv))
- netdev_dbg(priv->dev, "[%p]\t[%p]\t[%x]\n",
- priv->rx_skbuff[i],
-priv->rx_skbuff[i]->data,
-(unsigned int)priv->rx_skbuff_dma[i]);
+ netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n",
+ priv->rx_skbuff[i], priv->rx_skbuff[i]->data,
+ (unsigned int)priv->rx_skbuff_dma[i]);
}
priv->cur_rx = 0;
priv->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
@@ -1389,9 +1386,8 @@ static void stmmac_tx_clean(struct stmmac_priv *priv)
netif_tx_lock(priv->dev);
if (netif_queue_stopped(priv->dev) &&
stmmac_tx_avail(priv) > STMMAC_TX_THRESH) {
- if (netif_msg_tx_done(priv))
- netdev_dbg(priv->dev, "%s: restart transmit\n",
- __func__);
+ netif_dbg(priv, tx_done, priv->dev,
+ "%s: restart transmit\n", __func__);
netif_wake_queue(priv->dev);
}
netif_tx_unlock(priv->dev);
@@ -2096,9 +2092,8 @@ static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb,
struct net_device *dev)
priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
- if (netif_msg_hw(priv))
- netdev_dbg(priv->dev, "%s: stop transmitted packets\n",
- __func__);
+ netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
+ __func__);
netif_stop_queue(dev);
}
@@ -2298,9 +2293,8 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb,
struct net_device *dev)
}
if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
- if (netif_msg_hw(priv))
- netdev_dbg(priv->dev,
- "%s: stop transmitted packets\n", __func__);
+ netif_dbg(priv, hw, priv
Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY
On Thu, Sep 28, 2017 at 09:37:08AM +0200, Corentin Labbe wrote: > On Wed, Sep 27, 2017 at 04:02:10PM +0200, Andrew Lunn wrote: > > Hi Corentin > > > > > +Required properties for the mdio-mux node: > > > + - compatible = "mdio-mux" > > > > This is too generic. Please add a more specific compatible for this > > particular mux. You can keep "mdio-mux", since that is what the MDIO > > subsystem will look for. > > > > I will add allwinner,sun8i-h3-mdio-mux > > > > +Required properties of the integrated phy node: > > > - clocks: a phandle to the reference clock for the EPHY > > > - resets: a phandle to the reset control for the EPHY > > > +- phy-is-integrated > > > > So the last thing you said is that the mux is not the problem > > here. Something else is locking up. Did you discover what? > > > > I really would like phy-is-integrated to go away. > > > > I have found the problem: by enabling ephy clk/reset the timeout does not > occur anymore. > So we could remove phy-is-integrated by: > Moving internal phy clk/reset handling in mdio_mux_syscon_switch_fn() > But this means: > - getting internalphy node always by manually get internal_mdio/internal_phy > (and not by the given phyhandle) > - doing some unnecessary tasks (enable/scan/disable) when external_phy is > needed > Hello I have get rid of phy-is-integrated, but mdio_mux_syscon_switch_fn need to enable/disable ephy clk/reset. And so access to internal PHY node. But current DT made this ugly: (need to find mdio-mux then internalmdio then internal PHY) Since MAC cannot reset/choose internal MDIO without ephy clk/rst, could we interpret this as thoses clk/rst must be set in emac node. This will simplify a lot the code. Regards
Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY
On Thu, Sep 28, 2017 at 09:37:08AM +0200, Corentin Labbe wrote:
> On Wed, Sep 27, 2017 at 04:02:10PM +0200, Andrew Lunn wrote:
> > Hi Corentin
> >
> > > +Required properties for the mdio-mux node:
> > > + - compatible = "mdio-mux"
> >
> > This is too generic. Please add a more specific compatible for this
> > particular mux. You can keep "mdio-mux", since that is what the MDIO
> > subsystem will look for.
> >
>
> I will add allwinner,sun8i-h3-mdio-mux
>
> > > +Required properties of the integrated phy node:
> > > - clocks: a phandle to the reference clock for the EPHY
> > > - resets: a phandle to the reset control for the EPHY
> > > +- phy-is-integrated
> >
> > So the last thing you said is that the mux is not the problem
> > here. Something else is locking up. Did you discover what?
> >
> > I really would like phy-is-integrated to go away.
> >
>
> I have found the problem: by enabling ephy clk/reset the timeout does not
> occur anymore.
> So we could remove phy-is-integrated by:
> Moving internal phy clk/reset handling in mdio_mux_syscon_switch_fn()
> But this means:
> - getting internalphy node always by manually get internal_mdio/internal_phy
> (and not by the given phyhandle)
> - doing some unnecessary tasks (enable/scan/disable) when external_phy is
> needed
>
> Regards
Hello all
Below is the current patch, as you can read, it does not use anymore the
phy-is-integrated property.
So now, the mdio-mux must always enable the internal mdio when switch_fn ask
for it and so reset MAC and so need to enable ephy clk/reset.
But for this I need a reference to thoses clock and reset. (this is done in
get_ephy_nodes)
The current version set those clock in mdio-mux node, and as you can see it is
already ugly (lots of get next node),
if the clk/rst nodes were as it should be, in phy nodes, it will be more bad.
So, since the MAC have a dependency on thoses clk/rst nodes for doing reset(),
I seek a proper way to get references on it.
OR do you agree that putting ephy clk/rst in emac is acceptable ?
thanks
regards
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -41,14 +42,14 @@
* This value is used for disabling properly EMAC
* and used as a good starting value in case of the
* boot process(uboot) leave some stuff.
- * @internal_phy: Does the MAC embed an internal PHY
+ * @soc_has_internal_phy: Does the MAC embed an internal PHY
* @support_mii: Does the MAC handle MII
* @support_rmii: Does the MAC handle RMII
* @support_rgmii: Does the MAC handle RGMII
*/
struct emac_variant {
u32 default_syscon_value;
- int internal_phy;
+ bool soc_has_internal_phy;
bool support_mii;
bool support_rmii;
bool support_rgmii;
@@ -61,7 +62,7 @@ struct emac_variant {
* @rst_ephy: reference to the optional EPHY reset for the internal PHY
* @variant: reference to the current board variant
* @regmap:regmap for using the syscon
- * @use_internal_phy: Does the current PHY choice imply using the internal PHY
+ * @internal_phy_powered: Does the internal PHY is enabled
*/
struct sunxi_priv_data {
struct clk *tx_clk;
@@ -70,12 +71,13 @@ struct sunxi_priv_data {
struct reset_control *rst_ephy;
const struct emac_variant *variant;
struct regmap *regmap;
- bool use_internal_phy;
+ bool internal_phy_powered;
+ void *mux_handle;
};
static const struct emac_variant emac_variant_h3 = {
.default_syscon_value = 0x58000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -83,20 +85,20 @@ static const struct emac_variant emac_variant_h3 = {
static const struct emac_variant emac_variant_v3s = {
.default_syscon_value = 0x38000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true
};
static const struct emac_variant emac_variant_a83t = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rgmii = true
};
static const struct emac_variant emac_variant_a64 = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -195,6 +197,9 @@ static const struct emac_variant emac_variant_a6
[PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs
The Allwinner H3 SoC have two distinct MDIO bus, only one could be
active at the same time.
The selection of the active MDIO bus are done via some bits in the EMAC
register of the system controller.
This patch implement this MDIO switch via a custom MDIO-mux.
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 116 +++---
2 files changed, 104 insertions(+), 13 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig
b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index 97035766c291..e28c0d2c58e9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -159,6 +159,7 @@ config DWMAC_SUN8I
tristate "Allwinner sun8i GMAC support"
default ARCH_SUNXI
depends on OF && (ARCH_SUNXI || COMPILE_TEST)
+ select MDIO_BUS_MUX
---help---
Support for Allwinner H3 A83T A64 EMAC ethernet controllers.
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 672553b652bd..ddd5695886ac 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -71,6 +72,7 @@ struct sunxi_priv_data {
const struct emac_variant *variant;
struct regmap *regmap;
bool use_internal_phy;
+ void *mux_handle;
};
static const struct emac_variant emac_variant_h3 = {
@@ -195,6 +197,9 @@ static const struct emac_variant emac_variant_a64 = {
#define H3_EPHY_LED_POLBIT(17) /* 1: active low, 0: active
high */
#define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
#define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
+#define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT)
+#define DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID 0
+#define DWMAC_sUN8I_MDIO_MUX_EXTERNAL_ID 1
/* H3/A64 specific bits */
#define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */
@@ -634,6 +639,76 @@ static int sun8i_dwmac_reset(struct stmmac_priv *priv)
return 0;
}
+/* MDIO multiplexing switch function
+ * This function is called by the mdio-mux layer when it thinks the mdio bus
+ * multiplexer needs to switch.
+ * 'current_child' is the current value of the mux register
+ * 'desired_child' is the value of the 'reg' property of the target child MDIO
+ * node.
+ * The first time this function is called, current_child == -1.
+ * If current_child == desired_child, then the mux is already set to the
+ * correct bus.
+ *
+ * Note that we do not use reg/mask like mdio-mux-mmioreg because we need to
+ * know easily which bus is used (reset must be done only for desired bus).
+ */
+static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,
+void *data)
+{
+ struct stmmac_priv *priv = data;
+ struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
+ u32 reg, val;
+ int ret = 0;
+ bool need_reset = false;
+
+ if (current_child ^ desired_child) {
+ regmap_read(gmac->regmap, SYSCON_EMAC_REG, ®);
+ switch (desired_child) {
+ case DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID:
+ dev_info(priv->device, "Switch mux to internal PHY");
+ val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;
+ if (gmac->use_internal_phy)
+ need_reset = true;
+ break;
+ case DWMAC_sUN8I_MDIO_MUX_EXTERNAL_ID:
+ dev_info(priv->device, "Switch mux to external PHY");
+ val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN;
+ if (!gmac->use_internal_phy)
+ need_reset = true;
+ break;
+ default:
+ dev_err(priv->device, "Invalid child id %x\n",
desired_child);
+ return -EINVAL;
+ }
+ regmap_write(gmac->regmap, SYSCON_EMAC_REG, val);
+ /* After changing syscon value, the MAC need reset or it will
use
+* the last value (and so the last PHY set).
+* Reset is necessary only when we reach the needed MDIO,
+* it timeout in other case.
+*/
+ if (need_reset)
+ ret = sun8i_dwmac_reset(priv);
+ else
+ dev_dbg(priv->device, "skipped reset\n");
+ }
+ return ret;
+}
+
+static int sun8i_dwmac_register_mdio_mux(struct stmmac_pri
[PATCH v5 09/10] net: stmmac: snps,dwmac-mdio MDIOs are automatically registered
stmmac bindings docs said that its mdio node must have
compatible = "snps,dwmac-mdio";
Since dwmac-sun8i does not have any good reasons to not doing it, all
their MDIO node must have it.
Since these compatible is automatically registered, dwmac-sun8i compatible
does not need to be in need_mdio_ids.
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index a366b3747eeb..3de5501e34fe 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -311,10 +311,6 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat,
bool mdio = true;
static const struct of_device_id need_mdio_ids[] = {
{ .compatible = "snps,dwc-qos-ethernet-4.10" },
- { .compatible = "allwinner,sun8i-a83t-emac" },
- { .compatible = "allwinner,sun8i-h3-emac" },
- { .compatible = "allwinner,sun8i-v3s-emac" },
- { .compatible = "allwinner,sun50i-a64-emac" },
};
/* If phy-handle property is passed from DT, use it as the PHY */
--
2.13.5
[PATCH v5 08/10] net: stmmac: dwmac-sun8i: choose internal PHY via phy-is-integrated
The current way to find if the phy is internal is to compare DT phy-mode
and emac_variant/internal_phy.
But it will negate a possible future SoC where an external PHY use the
same phy mode than the internal one.
This patch adds a new way to find if the PHY is internal, via
the phy-is-integrated property.
Since the internal_phy variable does not need anymore to contain the xMII mode
used by the internal PHY, it is still used for knowing the presence of an
internal PHY, so it is modified to a boolean soc_has_internal_phy.
Signed-off-by: Corentin Labbe
Acked-by: Chen-Yu Tsai
Reviewed-by: Florian Fainelli
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index fffd6d5fc907..672553b652bd 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -41,14 +41,14 @@
* This value is used for disabling properly EMAC
* and used as a good starting value in case of the
* boot process(uboot) leave some stuff.
- * @internal_phy: Does the MAC embed an internal PHY
+ * @soc_has_internal_phy: Does the MAC embed an internal PHY
* @support_mii: Does the MAC handle MII
* @support_rmii: Does the MAC handle RMII
* @support_rgmii: Does the MAC handle RGMII
*/
struct emac_variant {
u32 default_syscon_value;
- int internal_phy;
+ bool soc_has_internal_phy;
bool support_mii;
bool support_rmii;
bool support_rgmii;
@@ -75,7 +75,7 @@ struct sunxi_priv_data {
static const struct emac_variant emac_variant_h3 = {
.default_syscon_value = 0x58000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -83,20 +83,20 @@ static const struct emac_variant emac_variant_h3 = {
static const struct emac_variant emac_variant_v3s = {
.default_syscon_value = 0x38000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true
};
static const struct emac_variant emac_variant_a83t = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rgmii = true
};
static const struct emac_variant emac_variant_a64 = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -648,7 +648,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
"Current syscon value is not the default %x (expect
%x)\n",
val, reg);
- if (gmac->variant->internal_phy) {
+ if (gmac->variant->soc_has_internal_phy) {
if (!gmac->use_internal_phy) {
/* switch to external PHY interface */
reg &= ~H3_EPHY_SELECT;
@@ -932,7 +932,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
}
plat_dat->interface = of_get_phy_mode(dev->of_node);
- if (plat_dat->interface == gmac->variant->internal_phy) {
+ if (of_property_read_bool(plat_dat->phy_node, "phy-is-integrated")) {
dev_info(&pdev->dev, "Will use internal PHY\n");
gmac->use_internal_phy = true;
gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0);
--
2.13.5
[PATCH v5 07/10] arm64: dts: allwinner: add snps,dwmac-mdio compatible to emac/mdio
stmmac bindings docs said that its mdio node must have
compatible = "snps,dwmac-mdio";
Since dwmac-sun8i does not have any good reasons to not doing it, all
their MDIO node must have it.
Signed-off-by: Corentin Labbe
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 4dd9ffef0d80..5dceebd81f09 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -476,6 +476,7 @@
#size-cells = <0>;
mdio: mdio {
+ compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
--
2.13.5
[PATCH v5 06/10] ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac
Since dwmac-sun8i could use either an integrated PHY or an external PHY
(which could be at same MDIO address), we need to represent this selection
by a MDIO switch.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 30 +-
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 4b599b5d26f6..e137377b312d 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -417,14 +417,34 @@
#size-cells = <0>;
status = "disabled";
- mdio: mdio {
+ mdio0: mdio {
#address-cells = <1>;
#size-cells = <0>;
- int_mii_phy: ethernet-phy@1 {
- compatible =
"ethernet-phy-ieee802.3-c22";
+ compatible = "snps,dwmac-mdio";
+ };
+
+ mdio-mux {
+ compatible = "mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Only one MDIO is usable at the time */
+ internal_mdio: mdio@1 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ compatible =
"ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ phy-is-integrated;
+ };
+ };
+ mdio: mdio@0 {
reg = <1>;
- clocks = <&ccu CLK_BUS_EPHY>;
- resets = <&ccu RST_BUS_EPHY>;
+ #address-cells = <1>;
+ #size-cells = <0>;
};
};
};
--
2.13.5
[PATCH v5 05/10] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY
This patch add documentation about the MDIO switch used on sun8i-h3-emac
for integrated PHY.
Signed-off-by: Corentin Labbe
---
.../devicetree/bindings/net/dwmac-sun8i.txt| 127 +++--
1 file changed, 120 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
index 725f3b187886..3fa0e54825ea 100644
--- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
+++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
@@ -39,7 +39,7 @@ Optional properties for the following compatibles:
- allwinner,leds-active-low: EPHY LEDs are active low
Required child node of emac:
-- mdio bus node: should be named mdio
+- mdio bus node: should be labelled mdio
Required properties of the mdio node:
- #address-cells: shall be 1
@@ -48,14 +48,28 @@ Required properties of the mdio node:
The device node referenced by "phy" or "phy-handle" should be a child node
of the mdio node. See phy.txt for the generic PHY bindings.
-Required properties of the phy node with the following compatibles:
+The following compatibles require an mdio-mux node called "mdio-mux":
+ - "allwinner,sun8i-h3-emac"
+ - "allwinner,sun8i-v3s-emac":
+Required properties for the mdio-mux node:
+ - compatible = "mdio-mux"
+ - one child mdio for the integrated mdio
+ - one child mdio for the external mdio if present (V3s have none)
+Required properties for the mdio-mux children node:
+ - reg: 0 for internal MDIO bus, 1 for external MDIO bus
+
+The following compatibles require a PHY node representing the integrated
+PHY, under the integrated MDIO bus node if an mdio-mux node is used:
- "allwinner,sun8i-h3-emac",
- "allwinner,sun8i-v3s-emac":
+
+Required properties of the integrated phy node:
- clocks: a phandle to the reference clock for the EPHY
- resets: a phandle to the reset control for the EPHY
+- phy-is-integrated
+- Should be a child of the integrated mdio
-Example:
-
+Example with integrated PHY:
emac: ethernet@1c0b000 {
compatible = "allwinner,sun8i-h3-emac";
syscon = <&syscon>;
@@ -72,13 +86,112 @@ emac: ethernet@1c0b000 {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
+
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+
+ mdio-mux {
+ compatible = "mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ int_mdio: mdio@1 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ phy-is-integrated
+ };
+ };
+ ext_mdio: mdio@0 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+Example with external PHY:
+emac: ethernet@1c0b000 {
+ compatible = "allwinner,sun8i-h3-emac";
+ syscon = <&syscon>;
+ reg = <0x01c0b000 0x104>;
+ interrupts = ;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+ allwinner,leds-active-low;
+
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+
+ mdio-mux {
+ compatible = "mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ int_mdio: mdio@1 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ phy-is-integrated
+ };
+ };
+ ext_mdio: mdio@0
[PATCH v5 02/10] dt-bindings: net: Restore sun8i dwmac binding
This patch restore dt-bindings documentation about dwmac-sun8i
This reverts commit 8aa33ec2f481 ("dt-bindings: net: Revert sun8i dwmac
binding")
Signed-off-by: Corentin Labbe
---
.../devicetree/bindings/net/dwmac-sun8i.txt| 84 ++
1 file changed, 84 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt
diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
new file mode 100644
index ..725f3b187886
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
@@ -0,0 +1,84 @@
+* Allwinner sun8i GMAC ethernet controller
+
+This device is a platform glue layer for stmmac.
+Please see stmmac.txt for the other unchanged properties.
+
+Required properties:
+- compatible: should be one of the following string:
+ "allwinner,sun8i-a83t-emac"
+ "allwinner,sun8i-h3-emac"
+ "allwinner,sun8i-v3s-emac"
+ "allwinner,sun50i-a64-emac"
+- reg: address and length of the register for the device.
+- interrupts: interrupt for the device
+- interrupt-names: should be "macirq"
+- clocks: A phandle to the reference clock for this device
+- clock-names: should be "stmmaceth"
+- resets: A phandle to the reset control for this device
+- reset-names: should be "stmmaceth"
+- phy-mode: See ethernet.txt
+- phy-handle: See ethernet.txt
+- #address-cells: shall be 1
+- #size-cells: shall be 0
+- syscon: A phandle to the syscon of the SoC with one of the following
+ compatible string:
+ - allwinner,sun8i-h3-system-controller
+ - allwinner,sun8i-v3s-system-controller
+ - allwinner,sun50i-a64-system-controller
+ - allwinner,sun8i-a83t-system-controller
+
+Optional properties:
+- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is
0-700. Default is 0)
+- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is
0-3100. Default is 0)
+Both delay properties need to be a multiple of 100. They control the delay for
+external PHY.
+
+Optional properties for the following compatibles:
+ - "allwinner,sun8i-h3-emac",
+ - "allwinner,sun8i-v3s-emac":
+- allwinner,leds-active-low: EPHY LEDs are active low
+
+Required child node of emac:
+- mdio bus node: should be named mdio
+
+Required properties of the mdio node:
+- #address-cells: shall be 1
+- #size-cells: shall be 0
+
+The device node referenced by "phy" or "phy-handle" should be a child node
+of the mdio node. See phy.txt for the generic PHY bindings.
+
+Required properties of the phy node with the following compatibles:
+ - "allwinner,sun8i-h3-emac",
+ - "allwinner,sun8i-v3s-emac":
+- clocks: a phandle to the reference clock for the EPHY
+- resets: a phandle to the reset control for the EPHY
+
+Example:
+
+emac: ethernet@1c0b000 {
+ compatible = "allwinner,sun8i-h3-emac";
+ syscon = <&syscon>;
+ reg = <0x01c0b000 0x104>;
+ interrupts = ;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ };
+ };
+};
--
2.13.5
[PATCH v5 03/10] arm: dts: sunxi: Restore EMAC changes
This patch restore arm DT about dwmac-sun8i
This reverts commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes")
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 19 +
arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 ++
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 +++
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 8 +++
arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 5 +
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts| 8 +++
arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22 +++
arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts| 16 ++
arch/arm/boot/dts/sunxi-h3-h5.dtsi| 26 +++
10 files changed, 128 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
index b1502df7b509..6713d0f2b3f4 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -56,6 +56,8 @@
aliases {
serial0 = &uart0;
+ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+ ethernet0 = &emac;
ethernet1 = &xr819;
};
@@ -102,6 +104,13 @@
status = "okay";
};
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index a337af1de322..d756ff825116 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -52,6 +52,7 @@
compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
};
@@ -114,12 +115,30 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <®_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
status = "okay";
};
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
index 8d2cc6e9a03f..78f6c24952dd 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
@@ -46,3 +46,10 @@
model = "FriendlyARM NanoPi NEO";
compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index 8ff71b1bb45b..17cdeae19c6f 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -54,6 +54,7 @@
aliases {
serial0 = &uart0;
/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+ ethernet0 = &emac;
ethernet1 = &rtl8189;
};
@@ -117,6 +118,13 @@
status = "okay";
};
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index 5fea430e0eb1..6880268e8b87 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -52,6 +52,7 @@
compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
@@ -97,6 +98,13 @@
status = "okay";
};
+&emac {
+ phy-handle
[PATCH v5 04/10] net: stmmac: sun8i: Restore the compatibles
This patch restore compatibles about dwmac-sun8i
This reverts commit ad4540cc5aa3 ("net: stmmac: sun8i: Remove the compatibles")
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 39c2122a4f26..fffd6d5fc907 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -979,6 +979,14 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
}
static const struct of_device_id sun8i_dwmac_match[] = {
+ { .compatible = "allwinner,sun8i-h3-emac",
+ .data = &emac_variant_h3 },
+ { .compatible = "allwinner,sun8i-v3s-emac",
+ .data = &emac_variant_v3s },
+ { .compatible = "allwinner,sun8i-a83t-emac",
+ .data = &emac_variant_a83t },
+ { .compatible = "allwinner,sun50i-a64-emac",
+ .data = &emac_variant_a64 },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
--
2.13.5
[PATCH v5 00/10] net: stmmac: dwmac-sun8i: Handle integrated PHY
Hello The current way to find if the PHY is internal is to compare DT phy-mode and emac_variant/internal_phy. But it will negate a possible future SoC where an external PHY use the same phy mode than the integrated one. This patchs series adds a new way to find if the PHY is integrated, via the phy-is-integrated DT property. Since it exists both integrated and external ethernet-phy@1, they are merged in the final DTB and so share all properties. For avoiding this, and better represent the reality, we use a MDIO mux. The first try was to create a new MDIO mux "mdio-mux-syscon". mdio-mux-syscon working the same way than mdio-mux-mmioreg with the exception that the register is used via syscon/regmap. But this solution does not work for two reason: - changing the MDIO selection need the reset of MAC which cannot be done by the mdio-mux-syscon driver - There were driver loading order problem: - mdio-mux-syscon needing that stmmac register the parent MDIO - stmmac needing that child MDIO was registered just after registering parent MDIO So we cannot use any external MDIO-mux. The final solution was to represent a mdio-mux and let the MAC handle all things. Note that phy-is-integrated is still needed (even if we use a MDIO mux) since some properties apply only on integrated PHY and we need to know the final MDIO bus in mdio_mux_syscon_switch_fn(). Since DT bits was reverted in 4.13, this patch series include the revert of the revert. So - the first four patchs bring back DT/stmmac stuff that was in 4.13 (and reverted) - fifth patch document how DT MDIO mux is implemented - patch 6 and 7 modify DT - patch 8, 9, 10 Modify stmmac according to the new bindings I have let patch splited for easy review. (for seeing what's new) But the final serie could have some patch squashed if someone want. Like squashing patch and 2 and 5 (documentation) Since DT worked well in 4.13, could it be targeted for 4.14 ? If necessary I could split this serie in two: - bring back A64/A83T (patchs 1, 2, 4, 7, 9) - add MXIO-mux and H3 (patchs 3, 4, 5, 6, 8, 10) Regards Changes since v4: - Update documentation for new bindings - Added 4 patchs for bring back reverted stuff of 4.13 - dwmac-sun8i now handle mdio-mux - MDIO use now compatible = "snps,dwmac-mdio"; Changes since v3: - Added a patch for handling fixed-link - Updated documentation Changes since v2: - Add a MDIO mux for creating distinction between integrated and external MDIO. - phy-is-integrated is not set in dtsi. Changes since v1: - Dropped phy-is-integrated documentation patch since another same patch was already merged - Moved phy-is-integrated from SoC dtsi to final board DT. Corentin Labbe (10): arm64: dts: allwinner: Restore EMAC changes dt-bindings: net: Restore sun8i dwmac binding arm: dts: sunxi: Restore EMAC changes net: stmmac: sun8i: Restore the compatibles dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac arm64: dts: allwinner: add snps,dwmac-mdio compatible to emac/mdio net: stmmac: dwmac-sun8i: choose internal PHY via phy-is-integrated net: stmmac: snps,dwmac-mdio MDIOs are automatically registered net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs .../devicetree/bindings/net/dwmac-sun8i.txt| 197 + arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9 + arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts| 19 ++ arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 + arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 + arch/arm/boot/dts/sun8i-h3-orangepi-one.dts| 8 + arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts| 5 + arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 8 + arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22 +++ arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 16 ++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 46 + .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 16 ++ .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 15 ++ .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 17 ++ .../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 16 ++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 21 +++ .../boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 17 ++ .../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 17 ++ .../dts/allwinner/sun50i-h5-orangepi-prime.dts | 17 ++ drivers/net/ethernet/stmicro/stmmac/Kconfig| 1 + drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 140 --- .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 4 - 22 files changed, 601 insertions(+), 25 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt -- 2.13.5
[PATCH v5 01/10] arm64: dts: allwinner: Restore EMAC changes
This patch restore arm64 DT about dwmac-sun8i
This reverts commit 87e1f5e8bb4b ("arm64: dts: allwinner: Revert EMAC changes")
Signed-off-by: Corentin Labbe
---
.../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 16
.../boot/dts/allwinner/sun50i-a64-pine64-plus.dts| 15 +++
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 17 +
.../dts/allwinner/sun50i-a64-sopine-baseboard.dts| 16
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi| 20
.../boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 17 +
.../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts| 17 +
.../boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 17 +
8 files changed, 135 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index d347f52e27f6..45bdbfb96126 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -51,6 +51,7 @@
compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
};
@@ -69,6 +70,14 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ status = "okay";
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@@ -79,6 +88,13 @@
bias-pull-up;
};
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
index f82ccf332c0f..24f1aac366d6 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
@@ -48,3 +48,18 @@
/* TODO: Camera, touchscreen, etc. */
};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index caf8b6fbe5e3..6f209bb10a2f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -51,6 +51,7 @@
compatible = "pine64,pine64", "allwinner,sun50i-a64";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -78,6 +79,15 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rmii_pins>;
+ phy-mode = "rmii";
+ phy-handle = <&ext_rmii_phy1>;
+ status = "okay";
+
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@@ -88,6 +98,13 @@
bias-pull-up;
};
+&mdio {
+ ext_rmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
index 17ccc12b58df..0eb2acedf8c3 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
@@ -53,6 +53,7 @@
"allwinner,sun50i-a64";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
@@ -76,6 +77,21 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-
Re: [PATCH v5 01/10] arm64: dts: allwinner: Restore EMAC changes
On Fri, Sep 08, 2017 at 09:19:54AM +0200, Maxime Ripard wrote:
> On Fri, Sep 08, 2017 at 09:11:47AM +0200, Corentin Labbe wrote:
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
> > b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
> > index 1c2387bd5df6..968908761194 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
> > @@ -50,6 +50,7 @@
> > compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5";
> >
> > aliases {
> > + ethernet0 = &emac;
> > serial0 = &uart0;
> > };
> >
> > @@ -108,6 +109,22 @@
> > status = "okay";
> > };
> >
> > +&emac {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&emac_rgmii_pins>;
> > + phy-supply = <®_gmac_3v3>;
> > + phy-handle = <&ext_rgmii_phy>;
> > + phy-mode = "rgmii";
> > + status = "okay";
> > +};
> > +
> > +&mdio {
> > + ext_rgmii_phy: ethernet-phy@7 {
> > + compatible = "ethernet-phy-ieee802.3-c22";
> > + reg = <7>;
> > + };
> > +};
> > +
>
> This won't compile, you don't have that node in the H5 DTSI.
>
Since H5 DTSI include arm/sunxi-h3-h5.dtsi it compiles.
Furthermore, I restested just now and confirm, it compiles fine.
Regards
Re: [PATCH v5 05/10] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY
On Fri, Sep 08, 2017 at 09:25:38AM +0200, Maxime Ripard wrote:
> On Fri, Sep 08, 2017 at 09:11:51AM +0200, Corentin Labbe wrote:
> > This patch add documentation about the MDIO switch used on sun8i-h3-emac
> > for integrated PHY.
> >
> > Signed-off-by: Corentin Labbe
> > ---
> > .../devicetree/bindings/net/dwmac-sun8i.txt| 127
> > +++--
> > 1 file changed, 120 insertions(+), 7 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > index 725f3b187886..3fa0e54825ea 100644
> > --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > @@ -39,7 +39,7 @@ Optional properties for the following compatibles:
> > - allwinner,leds-active-low: EPHY LEDs are active low
> >
> > Required child node of emac:
> > -- mdio bus node: should be named mdio
> > +- mdio bus node: should be labelled mdio
>
> labels do not end up in the final DT (while the names do) so why are
> you making this change?
>
I misunderstood label/name.
Anyway, this contrainst should leave due to "snps,dwmac-mdio MDIOs are
automatically registered"
> >
> > Required properties of the mdio node:
> > - #address-cells: shall be 1
> > @@ -48,14 +48,28 @@ Required properties of the mdio node:
> > The device node referenced by "phy" or "phy-handle" should be a child node
> > of the mdio node. See phy.txt for the generic PHY bindings.
> >
> > -Required properties of the phy node with the following compatibles:
> > +The following compatibles require an mdio-mux node called "mdio-mux":
> > + - "allwinner,sun8i-h3-emac"
> > + - "allwinner,sun8i-v3s-emac":
> > +Required properties for the mdio-mux node:
> > + - compatible = "mdio-mux"
> > + - one child mdio for the integrated mdio
> > + - one child mdio for the external mdio if present (V3s have none)
> > +Required properties for the mdio-mux children node:
> > + - reg: 0 for internal MDIO bus, 1 for external MDIO bus
> > +
> > +The following compatibles require a PHY node representing the integrated
> > +PHY, under the integrated MDIO bus node if an mdio-mux node is used:
> >- "allwinner,sun8i-h3-emac",
> >- "allwinner,sun8i-v3s-emac":
> > +
> > +Required properties of the integrated phy node:
> > - clocks: a phandle to the reference clock for the EPHY
> > - resets: a phandle to the reset control for the EPHY
> > +- phy-is-integrated
> > +- Should be a child of the integrated mdio
>
> I'm not sure what you mean by that, you ask that it should (so not
> required?) be a child of the integrated mdio...
>
I will change words to "must"
> >
> > -Example:
> > -
> > +Example with integrated PHY:
> > emac: ethernet@1c0b000 {
> > compatible = "allwinner,sun8i-h3-emac";
> > syscon = <&syscon>;
> > @@ -72,13 +86,112 @@ emac: ethernet@1c0b000 {
> > phy-handle = <&int_mii_phy>;
> > phy-mode = "mii";
> > allwinner,leds-active-low;
> > +
> > + mdio0: mdio {
>
> (You don't label it mdio here, unlike what was asked before)
>
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "snps,dwmac-mdio";
> > + };
>
> I think Rob wanted that node gone?
>
MDIO mux does not work without a parent MDIO, either gived by "parent-bus" or
directly via mdio_mux_init() (like it is the case in dwmac-sun8i)
> > + mdio-mux {
> > + compatible = "mdio-mux";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + int_mdio: mdio@1 {
> > + reg = <0>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + int_mii_phy: ethernet-phy@1 {
> > + reg = <1>;
> > + clocks = <&ccu CLK_BUS_EPHY>;
> > + resets = <&ccu RST_BUS_EPHY>;
> > + phy-is-integrated
> > + };
> > + };
>
> ... And in your example it's a child of the mdio mux?
>
So I confirm, integrated PHY must be a child of integrated MDIO (that mus
Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs
On Fri, Sep 08, 2017 at 03:05:20PM +0200, Andrew Lunn wrote:
> > +#define DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID 0
> > +#define DWMAC_sUN8I_MDIO_MUX_EXTERNAL_ID 1
> >
> > /* H3/A64 specific bits */
> > #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides
> > EPIT) */
> > @@ -634,6 +639,76 @@ static int sun8i_dwmac_reset(struct stmmac_priv *priv)
> > return 0;
> > }
> >
> > +/* MDIO multiplexing switch function
> > + * This function is called by the mdio-mux layer when it thinks the mdio
> > bus
> > + * multiplexer needs to switch.
> > + * 'current_child' is the current value of the mux register
> > + * 'desired_child' is the value of the 'reg' property of the target child
> > MDIO
> > + * node.
> > + * The first time this function is called, current_child == -1.
> > + * If current_child == desired_child, then the mux is already set to the
> > + * correct bus.
> > + *
> > + * Note that we do not use reg/mask like mdio-mux-mmioreg because we need
> > to
> > + * know easily which bus is used (reset must be done only for desired bus).
> > + */
> > +static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,
> > +void *data)
> > +{
> > + struct stmmac_priv *priv = data;
> > + struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
> > + u32 reg, val;
> > + int ret = 0;
> > + bool need_reset = false;
> > +
> > + if (current_child ^ desired_child) {
> > + regmap_read(gmac->regmap, SYSCON_EMAC_REG, ®);
> > + switch (desired_child) {
> > + case DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID:
> > + dev_info(priv->device, "Switch mux to internal PHY");
> > + val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;
> > + if (gmac->use_internal_phy)
> > + need_reset = true;
> > + break;
>
> This i don't get. Why do you need use_internal_phy? Isn't that
> implicit from DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID? Is it even possible to
> use an external PHY on the internal MDIO bus?
>
On my H3 box with external PHY, the MDIO mux library first select (for scan ?)
the internal MDIO.
Without use_internal_phy usage, this board will launch a reset to use the
internal MDIO... and this reset timeout/fail.
After the MDIO mux select the external MDIO.
> > + case DWMAC_sUN8I_MDIO_MUX_EXTERNAL_ID:
> > + dev_info(priv->device, "Switch mux to external PHY");
> > + val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN;
> > + if (!gmac->use_internal_phy)
> > + need_reset = true;
> > + break;
>
> And is it possible to use the internal PHY on the external bus?
>
I need to check that.
Regards
Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs
On Fri, Sep 08, 2017 at 04:00:20PM +0200, Andrew Lunn wrote:
> > > > +static int mdio_mux_syscon_switch_fn(int current_child, int
> > > > desired_child,
> > > > +void *data)
> > > > +{
> > > > + struct stmmac_priv *priv = data;
> > > > + struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
> > > > + u32 reg, val;
> > > > + int ret = 0;
> > > > + bool need_reset = false;
> > > > +
> > > > + if (current_child ^ desired_child) {
> > > > + regmap_read(gmac->regmap, SYSCON_EMAC_REG, ®);
> > > > + switch (desired_child) {
> > > > + case DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID:
> > > > + dev_info(priv->device, "Switch mux to internal
> > > > PHY");
> > > > + val = (reg & ~H3_EPHY_MUX_MASK) |
> > > > H3_EPHY_SELECT;
> > > > + if (gmac->use_internal_phy)
> > > > + need_reset = true;
> > > > + break;
> > >
> > > This i don't get. Why do you need use_internal_phy? Isn't that
> > > implicit from DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID? Is it even possible to
> > > use an external PHY on the internal MDIO bus?
> > >
> >
> > On my H3 box with external PHY, the MDIO mux library first select (for scan
> > ?) the internal MDIO.
> > Without use_internal_phy usage, this board will launch a reset to use the
> > internal MDIO... and this reset timeout/fail.
>
> Do you know why the reset times out/fails?
>
Because there are nothing connected to it.
I got also reset timeout on integrated MDIO when the integrated PHY is not
powered.
Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs
On Fri, Sep 08, 2017 at 04:17:36PM +0200, Andrew Lunn wrote: > > > Do you know why the reset times out/fails? > > > > > > > Because there are nothing connected to it. > > That should not be an issue. A read should just return 0x. And it > should return 0x fast. The timing of the MDIO protocol is fixed. A > read or a write takes a fixed number of cycles, independent of if > there is a device there or not. The bus data line has a pullup, so if > you try to access a missing device, you automatically read 0x. > Perhaps, but the reality is that with nothing connected to it, the reset of the MAC timeout. Certainly, the MAC does not support finding no PHY. So, to prevent an error message, and a "freeze" of the net process, the need_reset trick is necessary. Regards Corentin Labbe
Re: [PATCH v5 01/10] arm64: dts: allwinner: Restore EMAC changes
On Fri, Sep 08, 2017 at 03:39:04PM +0800, Chen-Yu Tsai wrote:
> On Fri, Sep 8, 2017 at 3:36 PM, Corentin Labbe
> wrote:
> > On Fri, Sep 08, 2017 at 09:19:54AM +0200, Maxime Ripard wrote:
> >> On Fri, Sep 08, 2017 at 09:11:47AM +0200, Corentin Labbe wrote:
> >> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
> >> > b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
> >> > index 1c2387bd5df6..968908761194 100644
> >> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
> >> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
> >> > @@ -50,6 +50,7 @@
> >> > compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5";
> >> >
> >> > aliases {
> >> > + ethernet0 = &emac;
> >> > serial0 = &uart0;
> >> > };
> >> >
> >> > @@ -108,6 +109,22 @@
> >> > status = "okay";
> >> > };
> >> >
> >> > +&emac {
> >> > + pinctrl-names = "default";
> >> > + pinctrl-0 = <&emac_rgmii_pins>;
> >> > + phy-supply = <®_gmac_3v3>;
> >> > + phy-handle = <&ext_rgmii_phy>;
> >> > + phy-mode = "rgmii";
> >> > + status = "okay";
> >> > +};
> >> > +
> >> > +&mdio {
> >> > + ext_rgmii_phy: ethernet-phy@7 {
> >> > + compatible = "ethernet-phy-ieee802.3-c22";
> >> > + reg = <7>;
> >> > + };
> >> > +};
> >> > +
> >>
> >> This won't compile, you don't have that node in the H5 DTSI.
> >>
> >
> > Since H5 DTSI include arm/sunxi-h3-h5.dtsi it compiles.
> > Furthermore, I restested just now and confirm, it compiles fine.
>
> The order of your patches are wrong. No individual patch should
> introduce build failures, not just the whole patch series.
>
Yes, I just miss-understood the reason of build failure.
I will fix the order in the next serie.
Thanks
Corentin Labbe
Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs
On Mon, Sep 11, 2017 at 06:11:24PM +0200, Andrew Lunn wrote:
> On Fri, Sep 08, 2017 at 04:28:25PM +0200, Corentin Labbe wrote:
> > On Fri, Sep 08, 2017 at 04:17:36PM +0200, Andrew Lunn wrote:
> > > > > Do you know why the reset times out/fails?
> > > > >
> > > >
> > > > Because there are nothing connected to it.
> > >
> > > That should not be an issue. A read should just return 0x. And it
> > > should return 0x fast. The timing of the MDIO protocol is fixed. A
> > > read or a write takes a fixed number of cycles, independent of if
> > > there is a device there or not. The bus data line has a pullup, so if
> > > you try to access a missing device, you automatically read 0x.
> > >
> >
> > Perhaps, but the reality is that with nothing connected to it, the reset of
> > the MAC timeout.
> > Certainly, the MAC does not support finding no PHY.
>
> Are you sure this is not because of the clock and reset?
>
> + #address-cells = <1>;
> + #size-cells = <0>;
> + int_mii_phy: ethernet-phy@1 {
> + compatible =
> "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + clocks = <&ccu CLK_BUS_EPHY>;
> + resets = <&ccu RST_BUS_EPHY>;
>
> The way you describe it here, the clock and reset are for the PHY. But
> maybe it is actually for the bus? I can understand a bus timing out if
> it has no clock, or it is held in reset. Try enabling the clock and
> reset when the internal bus is selected, not when the PHY on the bus
> is selected.
>
Even with CLK_BUS_EPHY/RST_BUS_EPHY enabled, the MAC reset timeout.
So no the CLK/RST are really for the PHY.
Regards
PS: patch and result with "integrated CLK/RST always on"
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -659,7 +659,7 @@ static int mdio_mux_syscon_switch_fn(int current_child, int
desired_child,
struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
u32 reg, val;
int ret = 0;
- bool need_reset = false;
+ bool need_reset = true;
if (current_child ^ desired_child) {
regmap_read(gmac->regmap, SYSCON_EMAC_REG, ®);
@@ -824,7 +824,7 @@ static int sun8i_dwmac_power_internal_phy(struct
stmmac_priv *priv)
int ret;
if (!gmac->use_internal_phy)
- return 0;
+ dev_info(priv->device, "IPHY BYPASS\n");
ret = clk_prepare_enable(gmac->ephy_clk);
if (ret) {
[ 18.057162] dwmac-sun8i 1c3.ethernet: Will use external PHY
[ 18.183789] dwmac-sun8i 1c3.ethernet: IPHY BYPASS
[ 18.184136] dwmac-sun8i 1c3.ethernet: Chain mode enabled
[ 18.184158] dwmac-sun8i 1c3.ethernet: No HW DMA feature register
supported
[ 18.184175] dwmac-sun8i 1c3.ethernet: Normal descriptors
[ 18.184192] dwmac-sun8i 1c3.ethernet: RX Checksum Offload Engine
supported
[ 18.184214] dwmac-sun8i 1c3.ethernet: COE Type 2
[ 18.184231] dwmac-sun8i 1c3.ethernet: TX Checksum insertion supported
[ 18.185491] libphy: stmmac: probed
[ 18.188481] libphy: mdio_mux: probed
[ 18.188831] dwmac-sun8i 1c3.ethernet: Switch mux to internal PHY
[ 18.288981] dwmac-sun8i 1c3.ethernet: EMAC reset timeout
[ 18.289559] libphy: mdio_mux: probed
[ 18.289629] dwmac-sun8i 1c3.ethernet: Switch mux to external PHY
[ 20.578316] EXT4-fs (mmcblk0p1): re-mounted. Opts: (null)
[ 31.240650] RTL8211E Gigabit Ethernet 0.1:00: attached PHY driver [RTL8211E
Gigabit Ethernet] (mii_bus:phy_addr=0.1:00, irq=POLL)
Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs
On Mon, Sep 11, 2017 at 10:19:20PM +0200, Andrew Lunn wrote: > > Even with CLK_BUS_EPHY/RST_BUS_EPHY enabled, the MAC reset timeout. > > So no the CLK/RST are really for the PHY. > > Thanks for trying that. > > You said it was probably during scanning of the bus it times out. What > address is causing the timeout? 0 or 1? If the internal bus can only > have one PHY on it, maybe we need to set bus->phy_mask to 0x1? > I have added a trace in begin and end of stmmac_mdio_read() [ 18.145451] libphy: stmmac: probed [ 18.148398] libphy: mdio_mux: probed [ 18.148650] dwmac-sun8i 1c3.ethernet: Switch mux to internal PHY [ 18.248751] dwmac-sun8i 1c3.ethernet: EMAC reset timeout [ 18.249297] libphy: mdio_mux: probed [ 18.249362] dwmac-sun8i 1c3.ethernet: Switch mux to external PHY [ 18.249391] stmmac_mdio_read 0 2 [ 18.249598] stmmac_mdio_read 0 2 1c [ 18.249623] stmmac_mdio_read 0 3 [ 18.249811] stmmac_mdio_read 0 3 c915 [ 20.737271] EXT4-fs (mmcblk0p1): re-mounted. Opts: (null) [ 31.294868] stmmac_mdio_read 0 0 [ 31.295311] stmmac_mdio_read 0 0 1140 It seems that the timeout is unrelated to MDIO bus. Regards
Re: [PATCH v5 02/10] dt-bindings: net: Restore sun8i dwmac binding
On Wed, Sep 13, 2017 at 01:07:34PM -0500, Rob Herring wrote:
> On Fri, Sep 08, 2017 at 09:11:48AM +0200, Corentin Labbe wrote:
> > This patch restore dt-bindings documentation about dwmac-sun8i
> > This reverts commit 8aa33ec2f481 ("dt-bindings: net: Revert sun8i dwmac
> > binding")
>
> Why?
>
I have put the reason in cover-letter and forget to put it in here also.
I fix that in next series.
Thanks
Re: [PATCH v5 05/10] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY
On Wed, Sep 13, 2017 at 01:20:04PM -0500, Rob Herring wrote:
> On Fri, Sep 08, 2017 at 09:43:25AM +0200, Corentin Labbe wrote:
> > On Fri, Sep 08, 2017 at 09:25:38AM +0200, Maxime Ripard wrote:
> > > On Fri, Sep 08, 2017 at 09:11:51AM +0200, Corentin Labbe wrote:
> > > > This patch add documentation about the MDIO switch used on sun8i-h3-emac
> > > > for integrated PHY.
> > > >
> > > > Signed-off-by: Corentin Labbe
> > > > ---
> > > > .../devicetree/bindings/net/dwmac-sun8i.txt| 127
> > > > +++--
> > > > 1 file changed, 120 insertions(+), 7 deletions(-)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > > > b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > > > index 725f3b187886..3fa0e54825ea 100644
> > > > --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > > > +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > > > @@ -39,7 +39,7 @@ Optional properties for the following compatibles:
> > > > - allwinner,leds-active-low: EPHY LEDs are active low
> > > >
> > > > Required child node of emac:
> > > > -- mdio bus node: should be named mdio
> > > > +- mdio bus node: should be labelled mdio
> > >
> > > labels do not end up in the final DT (while the names do) so why are
> > > you making this change?
> > >
> >
> > I misunderstood label/name.
> > Anyway, this contrainst should leave due to "snps,dwmac-mdio MDIOs are
> > automatically registered"
> >
> > > >
> > > > Required properties of the mdio node:
> > > > - #address-cells: shall be 1
> > > > @@ -48,14 +48,28 @@ Required properties of the mdio node:
> > > > The device node referenced by "phy" or "phy-handle" should be a child
> > > > node
> > > > of the mdio node. See phy.txt for the generic PHY bindings.
> > > >
> > > > -Required properties of the phy node with the following compatibles:
> > > > +The following compatibles require an mdio-mux node called "mdio-mux":
> > > > + - "allwinner,sun8i-h3-emac"
> > > > + - "allwinner,sun8i-v3s-emac":
> > > > +Required properties for the mdio-mux node:
> > > > + - compatible = "mdio-mux"
> > > > + - one child mdio for the integrated mdio
> > > > + - one child mdio for the external mdio if present (V3s have none)
> > > > +Required properties for the mdio-mux children node:
> > > > + - reg: 0 for internal MDIO bus, 1 for external MDIO bus
> > > > +
> > > > +The following compatibles require a PHY node representing the
> > > > integrated
> > > > +PHY, under the integrated MDIO bus node if an mdio-mux node is used:
> > > >- "allwinner,sun8i-h3-emac",
> > > >- "allwinner,sun8i-v3s-emac":
> > > > +
> > > > +Required properties of the integrated phy node:
> > > > - clocks: a phandle to the reference clock for the EPHY
> > > > - resets: a phandle to the reset control for the EPHY
> > > > +- phy-is-integrated
> > > > +- Should be a child of the integrated mdio
> > >
> > > I'm not sure what you mean by that, you ask that it should (so not
> > > required?) be a child of the integrated mdio...
> > >
> >
> > I will change words to "must"
> >
> > > >
> > > > -Example:
> > > > -
> > > > +Example with integrated PHY:
> > > > emac: ethernet@1c0b000 {
> > > > compatible = "allwinner,sun8i-h3-emac";
> > > > syscon = <&syscon>;
> > > > @@ -72,13 +86,112 @@ emac: ethernet@1c0b000 {
> > > > phy-handle = <&int_mii_phy>;
> > > > phy-mode = "mii";
> > > > allwinner,leds-active-low;
> > > > +
> > > > + mdio0: mdio {
> > >
> > > (You don't label it mdio here, unlike what was asked before)
> > >
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + compatible = "snps,dwmac-mdio";
> > > > + };
> > >
> > > I think Rob wanted that node gone?
> > >
[PATCH] vhost: remove unneeded linux/miscdevice.h include
drivers/vhost/vhost.c does not use any miscdevice, so this patch remove this unnecessary inclusion. Signed-off-by: Corentin Labbe --- drivers/vhost/vhost.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c index 33ac2b186b85..33ab839696f9 100644 --- a/drivers/vhost/vhost.c +++ b/drivers/vhost/vhost.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include -- 2.13.5
[PATCH] vsock: vmci: Remove unneeded linux/miscdevice.h include
net/vmw_vsock/vmci_transport.c does not use any miscdevice so this patch remove this unnecessary inclusion. Signed-off-by: Corentin Labbe --- net/vmw_vsock/vmci_transport.c | 1 - 1 file changed, 1 deletion(-) diff --git a/net/vmw_vsock/vmci_transport.c b/net/vmw_vsock/vmci_transport.c index 10ae7823a19d..0206155bff53 100644 --- a/net/vmw_vsock/vmci_transport.c +++ b/net/vmw_vsock/vmci_transport.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include -- 2.13.5
[PATCH v2] net: stmmac: dwmac-sun8i: Use reset exclusive
The current dwmac_sun8i module cannot be rmmod/modprobe due to that
the reset controller was not released when removed.
This patch remove ambiguity, by using of_reset_control_get_exclusive and
add the missing reset_control_put().
Note that we cannot use devm_reset_control_get, since the reset is not
in the device node.
Signed-off-by: Corentin Labbe
---
Changes since v1:
- added a note about devm_reset_control_get in commit message
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 57bb6dd7b401..1736d7cb0d96 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -854,6 +854,7 @@ static int sun8i_dwmac_unpower_internal_phy(struct
sunxi_priv_data *gmac)
clk_disable_unprepare(gmac->ephy_clk);
reset_control_assert(gmac->rst_ephy);
+ reset_control_put(gmac->rst_ephy);
return 0;
}
@@ -1010,7 +1011,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
return -EINVAL;
}
- gmac->rst_ephy = of_reset_control_get(plat_dat->phy_node, NULL);
+ gmac->rst_ephy =
of_reset_control_get_exclusive(plat_dat->phy_node, NULL);
if (IS_ERR(gmac->rst_ephy)) {
ret = PTR_ERR(gmac->rst_ephy);
if (ret == -EPROBE_DEFER)
--
2.13.5
Re: [PATCH v5 05/10] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY
On Thu, Sep 14, 2017 at 09:19:49PM +0200, Andrew Lunn wrote: > > > Is the MDIO controller "allwinner,sun8i-h3-emac" or "snps,dwmac-mdio"? > > > If the latter, then I think the node is fine, but then the mux should be > > > a child node of it. IOW, the child of an MDIO controller should either > > > be a mux node or slave devices. > > Hi Rob > > Up until now, children of an MDIO bus have been MDIO devices. Those > MDIO devices are either Ethernet PHYs, Ethernet Switches, or the > oddball devices that Broadcom iProc has, like generic PHYs. > > We have never had MDIO-muxes as MDIO children. A Mux is not an MDIO > device, and does not have the properties of an MDIO device. It is not > addressable on the MDIO bus. The current MUXes are addressed via GPIOs > or MMIO. > > There other similar cases. i2c-mux-gpio is not a child of an i2c bus, > nor i2c-mux-reg or gpio-mux. nxp,pca9548 is however a child of the i2c > bus, because it is an i2c device itself... > > If the MDIO mux was an MDIO device, i would agree with you. Bit it is > not, so lets not make it a child. > > Andrew Hello Rob, could you anwser/confirm please. I wait on this for sending the next version. Thanks Regards Corentin Labbe
Re: [PATCH v5 05/10] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY
On Tue, Sep 19, 2017 at 09:49:52PM -0500, Rob Herring wrote: > On Thu, Sep 14, 2017 at 2:19 PM, Andrew Lunn wrote: > >> > Is the MDIO controller "allwinner,sun8i-h3-emac" or "snps,dwmac-mdio"? > >> > If the latter, then I think the node is fine, but then the mux should be > >> > a child node of it. IOW, the child of an MDIO controller should either > >> > be a mux node or slave devices. > > > > Hi Rob > > > > Up until now, children of an MDIO bus have been MDIO devices. Those > > MDIO devices are either Ethernet PHYs, Ethernet Switches, or the > > oddball devices that Broadcom iProc has, like generic PHYs. > > > > We have never had MDIO-muxes as MDIO children. A Mux is not an MDIO > > device, and does not have the properties of an MDIO device. It is not > > addressable on the MDIO bus. The current MUXes are addressed via GPIOs > > or MMIO. > > The DT parent/child relationship defines the bus topology. We describe > MDIO buses in that way and if a mux is sitting between the controller > and the devices, then the DT hierarchy should reflect that. Now > sometimes we have 2 options for what interface has the parent/child > relationship (e.g. an I2C controlled USB hub chip), but in this case > we don't. > Putting mdio-mux as a child of it (the mdio node) give me: [ 18.175338] libphy: stmmac: probed [ 18.175379] mdio_bus stmmac-0: /soc/ethernet@1c3/mdio/mdio-mux has invalid PHY address [ 18.175408] mdio_bus stmmac-0: scan phy mdio-mux at address 0 [ 18.175450] mdio_bus stmmac-0: scan phy mdio-mux at address 1 [ 18.175482] mdio_bus stmmac-0: scan phy mdio-mux at address 2 [ 18.175513] mdio_bus stmmac-0: scan phy mdio-mux at address 3 [ 18.175544] mdio_bus stmmac-0: scan phy mdio-mux at address 4 [ 18.175575] mdio_bus stmmac-0: scan phy mdio-mux at address 5 [ 18.175607] mdio_bus stmmac-0: scan phy mdio-mux at address 6 [ 18.175638] mdio_bus stmmac-0: scan phy mdio-mux at address 7 [ 18.175669] mdio_bus stmmac-0: scan phy mdio-mux at address 8 [ 18.175700] mdio_bus stmmac-0: scan phy mdio-mux at address 9 [ 18.175731] mdio_bus stmmac-0: scan phy mdio-mux at address 10 [ 18.175762] mdio_bus stmmac-0: scan phy mdio-mux at address 11 [ 18.175795] mdio_bus stmmac-0: scan phy mdio-mux at address 12 [ 18.175827] mdio_bus stmmac-0: scan phy mdio-mux at address 13 [ 18.175858] mdio_bus stmmac-0: scan phy mdio-mux at address 14 [ 18.175889] mdio_bus stmmac-0: scan phy mdio-mux at address 15 [ 18.175919] mdio_bus stmmac-0: scan phy mdio-mux at address 16 [ 18.175951] mdio_bus stmmac-0: scan phy mdio-mux at address 17 [ 18.175982] mdio_bus stmmac-0: scan phy mdio-mux at address 18 [ 18.176014] mdio_bus stmmac-0: scan phy mdio-mux at address 19 [ 18.176045] mdio_bus stmmac-0: scan phy mdio-mux at address 20 [ 18.176076] mdio_bus stmmac-0: scan phy mdio-mux at address 21 [ 18.176107] mdio_bus stmmac-0: scan phy mdio-mux at address 22 [ 18.176139] mdio_bus stmmac-0: scan phy mdio-mux at address 23 [ 18.176170] mdio_bus stmmac-0: scan phy mdio-mux at address 24 [ 18.176202] mdio_bus stmmac-0: scan phy mdio-mux at address 25 [ 18.176233] mdio_bus stmmac-0: scan phy mdio-mux at address 26 [ 18.176271] mdio_bus stmmac-0: scan phy mdio-mux at address 27 [ 18.176320] mdio_bus stmmac-0: scan phy mdio-mux at address 28 [ 18.176371] mdio_bus stmmac-0: scan phy mdio-mux at address 29 [ 18.176420] mdio_bus stmmac-0: scan phy mdio-mux at address 30 [ 18.176452] mdio_bus stmmac-0: scan phy mdio-mux at address 31 Adding a fake to mdio-mux remove it, but I found that a bit ugly. Or perhaps patching of_mdiobus_register() to not scan node with compatible "mdio-mux". What do you think ? Regards
[PATCH v6 11/11] of: mdio: Prevent of_mdiobus_register from scanning mdio-mux nodes
Each child node of an MDIO node is scanned as a PHY when calling
of_mdiobus_register() givint the following result:
[ 18.175379] mdio_bus stmmac-0: /soc/ethernet@1c3/mdio/mdio-mux has
invalid PHY address
[ 18.175408] mdio_bus stmmac-0: scan phy mdio-mux at address 0
[ 18.175450] mdio_bus stmmac-0: scan phy mdio-mux at address 1
[...]
[ 18.176420] mdio_bus stmmac-0: scan phy mdio-mux at address 30
[ 18.176452] mdio_bus stmmac-0: scan phy mdio-mux at address 31
Since mdio-mux nodes are not PHY, this patch a way to to not scan
them.
Signed-off-by: Corentin Labbe
---
drivers/of/of_mdio.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c
index d94dd8b77abd..d90ddb0d90f2 100644
--- a/drivers/of/of_mdio.c
+++ b/drivers/of/of_mdio.c
@@ -190,6 +190,10 @@ int of_mdiobus_register(struct mii_bus *mdio, struct
device_node *np)
struct device_node *child;
bool scanphys = false;
int addr, rc;
+ static const struct of_device_id do_not_scan[] = {
+ { .compatible = "mdio-mux" },
+ {}
+ };
/* Do not continue if the node is disabled */
if (!of_device_is_available(np))
@@ -212,6 +216,9 @@ int of_mdiobus_register(struct mii_bus *mdio, struct
device_node *np)
/* Loop over the child nodes and register a phy_device for each phy */
for_each_available_child_of_node(np, child) {
+ if (of_match_node(do_not_scan, child))
+ continue;
+
addr = of_mdio_parse_addr(&mdio->dev, child);
if (addr < 0) {
scanphys = true;
@@ -229,6 +236,9 @@ int of_mdiobus_register(struct mii_bus *mdio, struct
device_node *np)
/* auto scan for PHYs with empty reg property */
for_each_available_child_of_node(np, child) {
+ if (of_match_node(do_not_scan, child))
+ continue;
+
/* Skip PHYs with reg property set */
if (of_find_property(child, "reg", NULL))
continue;
--
2.13.5
[PATCH v6 10/11] net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs
The Allwinner H3 SoC have two distinct MDIO bus, only one could be
active at the same time.
The selection of the active MDIO bus are done via some bits in the EMAC
register of the system controller.
This patch implement this MDIO switch via a custom MDIO-mux.
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 116 +++---
2 files changed, 104 insertions(+), 13 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig
b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index 97035766c291..e28c0d2c58e9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -159,6 +159,7 @@ config DWMAC_SUN8I
tristate "Allwinner sun8i GMAC support"
default ARCH_SUNXI
depends on OF && (ARCH_SUNXI || COMPILE_TEST)
+ select MDIO_BUS_MUX
---help---
Support for Allwinner H3 A83T A64 EMAC ethernet controllers.
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 672553b652bd..8bd500c351b4 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -71,6 +72,7 @@ struct sunxi_priv_data {
const struct emac_variant *variant;
struct regmap *regmap;
bool use_internal_phy;
+ void *mux_handle;
};
static const struct emac_variant emac_variant_h3 = {
@@ -195,6 +197,9 @@ static const struct emac_variant emac_variant_a64 = {
#define H3_EPHY_LED_POLBIT(17) /* 1: active low, 0: active
high */
#define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
#define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
+#define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT)
+#define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1
+#define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2
/* H3/A64 specific bits */
#define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */
@@ -634,6 +639,76 @@ static int sun8i_dwmac_reset(struct stmmac_priv *priv)
return 0;
}
+/* MDIO multiplexing switch function
+ * This function is called by the mdio-mux layer when it thinks the mdio bus
+ * multiplexer needs to switch.
+ * 'current_child' is the current value of the mux register
+ * 'desired_child' is the value of the 'reg' property of the target child MDIO
+ * node.
+ * The first time this function is called, current_child == -1.
+ * If current_child == desired_child, then the mux is already set to the
+ * correct bus.
+ *
+ * Note that we do not use reg/mask like mdio-mux-mmioreg because we need to
+ * know easily which bus is used (reset must be done only for desired bus).
+ */
+static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,
+void *data)
+{
+ struct stmmac_priv *priv = data;
+ struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
+ u32 reg, val;
+ int ret = 0;
+ bool need_reset = false;
+
+ if (current_child ^ desired_child) {
+ regmap_read(gmac->regmap, SYSCON_EMAC_REG, ®);
+ switch (desired_child) {
+ case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID:
+ dev_info(priv->device, "Switch mux to internal PHY");
+ val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;
+ if (gmac->use_internal_phy)
+ need_reset = true;
+ break;
+ case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID:
+ dev_info(priv->device, "Switch mux to external PHY");
+ val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN;
+ if (!gmac->use_internal_phy)
+ need_reset = true;
+ break;
+ default:
+ dev_err(priv->device, "Invalid child id %x\n",
desired_child);
+ return -EINVAL;
+ }
+ regmap_write(gmac->regmap, SYSCON_EMAC_REG, val);
+ /* After changing syscon value, the MAC need reset or it will
use
+* the last value (and so the last PHY set).
+* Reset is necessary only when we reach the needed MDIO,
+* it timeout in other case.
+*/
+ if (need_reset)
+ ret = sun8i_dwmac_reset(priv);
+ else
+ dev_dbg(priv->device, "skipped reset\n");
+ }
+ return ret;
+}
+
+static int sun8i_dwmac_register_mdio_mux(struct stmmac_pri
[PATCH v6 09/11] net: stmmac: dwmac-sun8i: choose internal PHY via phy-is-integrated
The current way to find if the phy is internal is to compare DT phy-mode
and emac_variant/internal_phy.
But it will negate a possible future SoC where an external PHY use the
same phy mode than the internal one.
This patch adds a new way to find if the PHY is internal, via
the phy-is-integrated property.
Since the internal_phy variable does not need anymore to contain the xMII mode
used by the internal PHY, it is still used for knowing the presence of an
internal PHY, so it is modified to a boolean soc_has_internal_phy.
Signed-off-by: Corentin Labbe
Acked-by: Chen-Yu Tsai
Reviewed-by: Florian Fainelli
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index fffd6d5fc907..672553b652bd 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -41,14 +41,14 @@
* This value is used for disabling properly EMAC
* and used as a good starting value in case of the
* boot process(uboot) leave some stuff.
- * @internal_phy: Does the MAC embed an internal PHY
+ * @soc_has_internal_phy: Does the MAC embed an internal PHY
* @support_mii: Does the MAC handle MII
* @support_rmii: Does the MAC handle RMII
* @support_rgmii: Does the MAC handle RGMII
*/
struct emac_variant {
u32 default_syscon_value;
- int internal_phy;
+ bool soc_has_internal_phy;
bool support_mii;
bool support_rmii;
bool support_rgmii;
@@ -75,7 +75,7 @@ struct sunxi_priv_data {
static const struct emac_variant emac_variant_h3 = {
.default_syscon_value = 0x58000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -83,20 +83,20 @@ static const struct emac_variant emac_variant_h3 = {
static const struct emac_variant emac_variant_v3s = {
.default_syscon_value = 0x38000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true
};
static const struct emac_variant emac_variant_a83t = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rgmii = true
};
static const struct emac_variant emac_variant_a64 = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -648,7 +648,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
"Current syscon value is not the default %x (expect
%x)\n",
val, reg);
- if (gmac->variant->internal_phy) {
+ if (gmac->variant->soc_has_internal_phy) {
if (!gmac->use_internal_phy) {
/* switch to external PHY interface */
reg &= ~H3_EPHY_SELECT;
@@ -932,7 +932,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
}
plat_dat->interface = of_get_phy_mode(dev->of_node);
- if (plat_dat->interface == gmac->variant->internal_phy) {
+ if (of_property_read_bool(plat_dat->phy_node, "phy-is-integrated")) {
dev_info(&pdev->dev, "Will use internal PHY\n");
gmac->use_internal_phy = true;
gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0);
--
2.13.5
[PATCH v6 07/11] arm64: dts: allwinner: add snps,dwmac-mdio compatible to emac/mdio
stmmac bindings docs said that its mdio node must have
compatible = "snps,dwmac-mdio";
Since dwmac-sun8i does not have any good reasons to not doing it, all
their MDIO node must have it.
Signed-off-by: Corentin Labbe
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 75494cd90e40..e30476f05802 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -517,6 +517,7 @@
#size-cells = <0>;
mdio: mdio {
+ compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
--
2.13.5
[PATCH v6 06/11] ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac
Since dwmac-sun8i could use either an integrated PHY or an external PHY
(which could be at same MDIO address), we need to represent this selection
by a MDIO switch.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 31 +--
1 file changed, 25 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 3b7d953429a6..a8e9b8f378ba 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -422,14 +422,33 @@
#size-cells = <0>;
status = "disabled";
- mdio: mdio {
+ mdio0: mdio {
#address-cells = <1>;
#size-cells = <0>;
- int_mii_phy: ethernet-phy@1 {
- compatible =
"ethernet-phy-ieee802.3-c22";
- reg = <1>;
- clocks = <&ccu CLK_BUS_EPHY>;
- resets = <&ccu RST_BUS_EPHY>;
+ compatible = "snps,dwmac-mdio";
+
+ mdio-mux {
+ compatible = "mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* Only one MDIO is usable at the time
*/
+ internal_mdio: mdio@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ compatible =
"ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ clocks = <&ccu
CLK_BUS_EPHY>;
+ resets = <&ccu
RST_BUS_EPHY>;
+ phy-is-integrated;
+ };
+ };
+ mdio: mdio@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
};
};
--
2.13.5
[PATCH v6 08/11] net: stmmac: snps,dwmac-mdio MDIOs are automatically registered
stmmac bindings docs said that its mdio node must have
compatible = "snps,dwmac-mdio";
Since dwmac-sun8i does not have any good reasons to not doing it, all
their MDIO node must have it.
Since these compatible is automatically registered, dwmac-sun8i compatible
does not need to be in need_mdio_ids.
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 8a280b48e3a9..9e616da0745d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -311,10 +311,6 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat,
bool mdio = true;
static const struct of_device_id need_mdio_ids[] = {
{ .compatible = "snps,dwc-qos-ethernet-4.10" },
- { .compatible = "allwinner,sun8i-a83t-emac" },
- { .compatible = "allwinner,sun8i-h3-emac" },
- { .compatible = "allwinner,sun8i-v3s-emac" },
- { .compatible = "allwinner,sun50i-a64-emac" },
{},
};
--
2.13.5
[PATCH v6 03/11] arm64: dts: allwinner: Restore EMAC changes
This patch restore arm64 DT about dwmac-sun8i
This reverts commit 87e1f5e8bb4b ("arm64: dts: allwinner: Revert EMAC changes")
Signed-off-by: Corentin Labbe
---
.../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 16
.../boot/dts/allwinner/sun50i-a64-pine64-plus.dts| 15 +++
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 17 +
.../dts/allwinner/sun50i-a64-sopine-baseboard.dts| 16
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi| 20
.../boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 17 +
.../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts| 17 +
.../boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 17 +
8 files changed, 135 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index d347f52e27f6..45bdbfb96126 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -51,6 +51,7 @@
compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
};
@@ -69,6 +70,14 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ status = "okay";
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@@ -79,6 +88,13 @@
bias-pull-up;
};
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
index f82ccf332c0f..24f1aac366d6 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
@@ -48,3 +48,18 @@
/* TODO: Camera, touchscreen, etc. */
};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index d06e34b5d192..806442d3e846 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -51,6 +51,7 @@
compatible = "pine64,pine64", "allwinner,sun50i-a64";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -71,6 +72,15 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rmii_pins>;
+ phy-mode = "rmii";
+ phy-handle = <&ext_rmii_phy1>;
+ status = "okay";
+
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@@ -81,6 +91,13 @@
bias-pull-up;
};
+&mdio {
+ ext_rmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
index 17ccc12b58df..0eb2acedf8c3 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
@@ -53,6 +53,7 @@
"allwinner,sun50i-a64";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
@@ -76,6 +77,21 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-
[PATCH v6 02/11] arm: dts: sunxi: Restore EMAC changes
This patch restore arm DT about dwmac-sun8i
This reverts commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes")
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 19 +
arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 ++
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 +++
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 8 +++
arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 5 +
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts| 8 +++
arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22 +++
arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts| 16 ++
arch/arm/boot/dts/sunxi-h3-h5.dtsi| 26 +++
10 files changed, 128 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
index b1502df7b509..6713d0f2b3f4 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -56,6 +56,8 @@
aliases {
serial0 = &uart0;
+ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+ ethernet0 = &emac;
ethernet1 = &xr819;
};
@@ -102,6 +104,13 @@
status = "okay";
};
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index e1dba9ffa94b..cc20d676a642 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -52,6 +52,7 @@
compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
};
@@ -111,12 +112,30 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <®_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
status = "okay";
};
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
index 8d2cc6e9a03f..78f6c24952dd 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
@@ -46,3 +46,10 @@
model = "FriendlyARM NanoPi NEO";
compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index 8ff71b1bb45b..17cdeae19c6f 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -54,6 +54,7 @@
aliases {
serial0 = &uart0;
/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+ ethernet0 = &emac;
ethernet1 = &rtl8189;
};
@@ -117,6 +118,13 @@
status = "okay";
};
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index 5fea430e0eb1..6880268e8b87 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -52,6 +52,7 @@
compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
@@ -97,6 +98,13 @@
status = "okay";
};
+&emac {
+ phy-handle
[PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY
This patch add documentation about the MDIO switch used on sun8i-h3-emac
for integrated PHY.
Signed-off-by: Corentin Labbe
---
.../devicetree/bindings/net/dwmac-sun8i.txt| 138 +++--
1 file changed, 126 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
index 725f3b187886..e2ef4683df08 100644
--- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
+++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
@@ -4,18 +4,18 @@ This device is a platform glue layer for stmmac.
Please see stmmac.txt for the other unchanged properties.
Required properties:
-- compatible: should be one of the following string:
+- compatible: must be one of the following string:
"allwinner,sun8i-a83t-emac"
"allwinner,sun8i-h3-emac"
"allwinner,sun8i-v3s-emac"
"allwinner,sun50i-a64-emac"
- reg: address and length of the register for the device.
- interrupts: interrupt for the device
-- interrupt-names: should be "macirq"
+- interrupt-names: must be "macirq"
- clocks: A phandle to the reference clock for this device
-- clock-names: should be "stmmaceth"
+- clock-names: must be "stmmaceth"
- resets: A phandle to the reset control for this device
-- reset-names: should be "stmmaceth"
+- reset-names: must be "stmmaceth"
- phy-mode: See ethernet.txt
- phy-handle: See ethernet.txt
- #address-cells: shall be 1
@@ -39,23 +39,38 @@ Optional properties for the following compatibles:
- allwinner,leds-active-low: EPHY LEDs are active low
Required child node of emac:
-- mdio bus node: should be named mdio
+- mdio bus node: with compatible "snps,dwmac-mdio"
Required properties of the mdio node:
- #address-cells: shall be 1
- #size-cells: shall be 0
-The device node referenced by "phy" or "phy-handle" should be a child node
+The device node referenced by "phy" or "phy-handle" must be a child node
of the mdio node. See phy.txt for the generic PHY bindings.
-Required properties of the phy node with the following compatibles:
+The following compatibles require that the mdio node have a mdio-mux child
+node called "mdio-mux":
+ - "allwinner,sun8i-h3-emac"
+ - "allwinner,sun8i-v3s-emac":
+Required properties for the mdio-mux node:
+ - compatible = "mdio-mux"
+ - one child mdio for the integrated mdio
+ - one child mdio for the external mdio if present (V3s have none)
+Required properties for the mdio-mux children node:
+ - reg: 1 for internal MDIO bus, 2 for external MDIO bus
+
+The following compatibles require a PHY node representing the integrated
+PHY, under the integrated MDIO bus node if an mdio-mux node is used:
- "allwinner,sun8i-h3-emac",
- "allwinner,sun8i-v3s-emac":
+
+Required properties of the integrated phy node:
- clocks: a phandle to the reference clock for the EPHY
- resets: a phandle to the reset control for the EPHY
+- phy-is-integrated
+- Must be a child of the integrated mdio
-Example:
-
+Example with integrated PHY:
emac: ethernet@1c0b000 {
compatible = "allwinner,sun8i-h3-emac";
syscon = <&syscon>;
@@ -72,13 +87,112 @@ emac: ethernet@1c0b000 {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
+
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ mdio-mux {
+ compatible = "mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ int_mdio: mdio@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ phy-is-integrated;
+ };
+ };
+ ext_mdio: mdio@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+};
+
+Example with external PHY:
+emac: ethernet@1c0b000 {
+ compatible = "allwinner,sun8i-h3-emac";
+ syscon = <&syscon>;
+ reg = <0x01
[PATCH v6 04/11] net: stmmac: sun8i: Restore the compatibles
This patch restore compatibles about dwmac-sun8i
This reverts commit ad4540cc5aa3 ("net: stmmac: sun8i: Remove the compatibles")
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 39c2122a4f26..fffd6d5fc907 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -979,6 +979,14 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
}
static const struct of_device_id sun8i_dwmac_match[] = {
+ { .compatible = "allwinner,sun8i-h3-emac",
+ .data = &emac_variant_h3 },
+ { .compatible = "allwinner,sun8i-v3s-emac",
+ .data = &emac_variant_v3s },
+ { .compatible = "allwinner,sun8i-a83t-emac",
+ .data = &emac_variant_a83t },
+ { .compatible = "allwinner,sun50i-a64-emac",
+ .data = &emac_variant_a64 },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
--
2.13.5
[PATCH v6 00/11] net: stmmac: dwmac-sun8i: Handle integrated PHY
Hello The current way to find if the PHY is internal is to compare DT phy-mode and emac_variant/internal_phy. But it will negate a possible future SoC where an external PHY use the same phy mode than the integrated one. This patchs series adds a new way to find if the PHY is integrated, via the phy-is-integrated DT property. Since it exists both integrated and external ethernet-phy@1, they are merged in the final DTB and so share all properties. For avoiding this, and better represent the reality, we use a MDIO mux. The first try was to create a new MDIO mux "mdio-mux-syscon". mdio-mux-syscon working the same way than mdio-mux-mmioreg with the exception that the register is used via syscon/regmap. But this solution does not work for two reason: - changing the MDIO selection need the reset of MAC which cannot be done by the mdio-mux-syscon driver - There were driver loading order problem: - mdio-mux-syscon needing that stmmac register the parent MDIO - stmmac needing that child MDIO was registered just after registering parent MDIO So we cannot use any external MDIO-mux. The final solution was to represent a mdio-mux and let the MAC handle all things. Note that phy-is-integrated is still needed (even if we use a MDIO mux) since some properties apply only on integrated PHY and we need to know the final MDIO bus in mdio_mux_syscon_switch_fn(). Since DT bits was reverted in 4.13, this patch series include the revert of the revert. So - the first four patchs bring back DT/stmmac stuff that was in 4.13 (and reverted) - fifth patch document how DT MDIO mux is implemented - patch 6 and 7 modify DT - patch 8, 9, 10 Modify stmmac according to the new bindings I have let patch splited for easy review. (for seeing what's new) But the final serie could have some patch squashed if someone want. Like squashing patch and 2 and 5 (documentation) Since DT worked well in 4.13, could it be targeted for 4.14 ? If necessary I could split this serie in two: - bring back A64/A83T (patchs 1, 2, 4, 7, 9) - add MXIO-mux and H3 (patchs 3, 4, 5, 6, 8, 10) Regards Changes since v5: - reordered patch 1 and 2 - mdio-mux node is now a mdio's child - added patch 11 for removing unnecessary scan of mdio-mux Changes since v4: - Update documentation for new bindings - Added 4 patchs for bring back reverted stuff of 4.13 - dwmac-sun8i now handle mdio-mux - MDIO use now compatible = "snps,dwmac-mdio"; Changes since v3: - Added a patch for handling fixed-link - Updated documentation Changes since v2: - Add a MDIO mux for creating distinction between integrated and external MDIO. - phy-is-integrated is not set in dtsi. Changes since v1: - Dropped phy-is-integrated documentation patch since another same patch was already merged - Moved phy-is-integrated from SoC dtsi to final board DT. Corentin Labbe (11): dt-bindings: net: Restore sun8i dwmac binding arm: dts: sunxi: Restore EMAC changes arm64: dts: allwinner: Restore EMAC changes net: stmmac: sun8i: Restore the compatibles dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac arm64: dts: allwinner: add snps,dwmac-mdio compatible to emac/mdio net: stmmac: snps,dwmac-mdio MDIOs are automatically registered net: stmmac: dwmac-sun8i: choose internal PHY via phy-is-integrated net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs of: mdio: Prevent of_mdiobus_register from scanning mdio-mux nodes .../devicetree/bindings/net/dwmac-sun8i.txt| 198 + arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9 + arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts| 19 ++ arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 + arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 + arch/arm/boot/dts/sun8i-h3-orangepi-one.dts| 8 + arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts| 5 + arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 8 + arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22 +++ arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 16 ++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 + .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 16 ++ .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 15 ++ .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 17 ++ .../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 16 ++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 21 +++ .../boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 17 ++ .../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 17 ++ .../dts/allwinner/sun50i-h5-orangepi-prime.dts | 17 ++ drivers/net/ethernet/stmicro/stmmac/Kconfig| 1 + drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 140 --- .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 4 - drivers/of/of_mdio.c |
[PATCH v6 01/11] dt-bindings: net: Restore sun8i dwmac binding
This patch restore dt-bindings documentation about dwmac-sun8i
This reverts commit 8aa33ec2f481 ("dt-bindings: net: Revert sun8i dwmac
binding")
Signed-off-by: Corentin Labbe
---
.../devicetree/bindings/net/dwmac-sun8i.txt| 84 ++
1 file changed, 84 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt
diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
new file mode 100644
index ..725f3b187886
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
@@ -0,0 +1,84 @@
+* Allwinner sun8i GMAC ethernet controller
+
+This device is a platform glue layer for stmmac.
+Please see stmmac.txt for the other unchanged properties.
+
+Required properties:
+- compatible: should be one of the following string:
+ "allwinner,sun8i-a83t-emac"
+ "allwinner,sun8i-h3-emac"
+ "allwinner,sun8i-v3s-emac"
+ "allwinner,sun50i-a64-emac"
+- reg: address and length of the register for the device.
+- interrupts: interrupt for the device
+- interrupt-names: should be "macirq"
+- clocks: A phandle to the reference clock for this device
+- clock-names: should be "stmmaceth"
+- resets: A phandle to the reset control for this device
+- reset-names: should be "stmmaceth"
+- phy-mode: See ethernet.txt
+- phy-handle: See ethernet.txt
+- #address-cells: shall be 1
+- #size-cells: shall be 0
+- syscon: A phandle to the syscon of the SoC with one of the following
+ compatible string:
+ - allwinner,sun8i-h3-system-controller
+ - allwinner,sun8i-v3s-system-controller
+ - allwinner,sun50i-a64-system-controller
+ - allwinner,sun8i-a83t-system-controller
+
+Optional properties:
+- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is
0-700. Default is 0)
+- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is
0-3100. Default is 0)
+Both delay properties need to be a multiple of 100. They control the delay for
+external PHY.
+
+Optional properties for the following compatibles:
+ - "allwinner,sun8i-h3-emac",
+ - "allwinner,sun8i-v3s-emac":
+- allwinner,leds-active-low: EPHY LEDs are active low
+
+Required child node of emac:
+- mdio bus node: should be named mdio
+
+Required properties of the mdio node:
+- #address-cells: shall be 1
+- #size-cells: shall be 0
+
+The device node referenced by "phy" or "phy-handle" should be a child node
+of the mdio node. See phy.txt for the generic PHY bindings.
+
+Required properties of the phy node with the following compatibles:
+ - "allwinner,sun8i-h3-emac",
+ - "allwinner,sun8i-v3s-emac":
+- clocks: a phandle to the reference clock for the EPHY
+- resets: a phandle to the reset control for the EPHY
+
+Example:
+
+emac: ethernet@1c0b000 {
+ compatible = "allwinner,sun8i-h3-emac";
+ syscon = <&syscon>;
+ reg = <0x01c0b000 0x104>;
+ interrupts = ;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ };
+ };
+};
--
2.13.5
Re: [PATCH v6 06/11] ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac
On Wed, Sep 27, 2017 at 12:16:22PM +0200, Maxime Ripard wrote:
> On Wed, Sep 27, 2017 at 07:34:09AM +0000, Corentin Labbe wrote:
> > Since dwmac-sun8i could use either an integrated PHY or an external PHY
> > (which could be at same MDIO address), we need to represent this selection
> > by a MDIO switch.
> >
> > Signed-off-by: Corentin Labbe
> > ---
> > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 31 +--
> > 1 file changed, 25 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> > b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> > index 3b7d953429a6..a8e9b8f378ba 100644
> > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> > @@ -422,14 +422,33 @@
> > #size-cells = <0>;
> > status = "disabled";
> >
> > - mdio: mdio {
> > + mdio0: mdio {
> > #address-cells = <1>;
> > #size-cells = <0>;
> > - int_mii_phy: ethernet-phy@1 {
> > - compatible =
> > "ethernet-phy-ieee802.3-c22";
> > - reg = <1>;
> > - clocks = <&ccu CLK_BUS_EPHY>;
> > - resets = <&ccu RST_BUS_EPHY>;
> > + compatible = "snps,dwmac-mdio";
> > +
> > + mdio-mux {
> > + compatible = "mdio-mux";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
>
> Newline
>
> > + /* Only one MDIO is usable at the time
> > */
> > + internal_mdio: mdio@1 {
> > + reg = <1>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
>
> Newline
>
> > + int_mii_phy: ethernet-phy@1 {
> > + compatible =
> > "ethernet-phy-ieee802.3-c22";
> > + reg = <1>;
> > + clocks = <&ccu
> > CLK_BUS_EPHY>;
> > + resets = <&ccu
> > RST_BUS_EPHY>;
> > + phy-is-integrated;
> > + };
> > + };
>
> Newline
>
> > + mdio: mdio@2 {
>
> This is quite confusing. Why not call the label external_mdio?
>
I will do it. (at origin I was not changing it for limiting changes on board
with external PHY, but now all DT are reverted, it will be easy)
Regards
Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY
On Wed, Sep 27, 2017 at 09:53:15PM -0700, Florian Fainelli wrote:
>
>
> On 09/27/2017 12:34 AM, Corentin Labbe wrote:
> > This patch add documentation about the MDIO switch used on sun8i-h3-emac
> > for integrated PHY.
> >
> > Signed-off-by: Corentin Labbe
> > ---
> > .../devicetree/bindings/net/dwmac-sun8i.txt| 138
> > +++--
> > 1 file changed, 126 insertions(+), 12 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > index 725f3b187886..e2ef4683df08 100644
> > --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > @@ -4,18 +4,18 @@ This device is a platform glue layer for stmmac.
> > Please see stmmac.txt for the other unchanged properties.
> >
> > Required properties:
> > -- compatible: should be one of the following string:
> > +- compatible: must be one of the following string:
> > "allwinner,sun8i-a83t-emac"
> > "allwinner,sun8i-h3-emac"
> > "allwinner,sun8i-v3s-emac"
> > "allwinner,sun50i-a64-emac"
> > - reg: address and length of the register for the device.
> > - interrupts: interrupt for the device
> > -- interrupt-names: should be "macirq"
> > +- interrupt-names: must be "macirq"
> > - clocks: A phandle to the reference clock for this device
> > -- clock-names: should be "stmmaceth"
> > +- clock-names: must be "stmmaceth"
> > - resets: A phandle to the reset control for this device
> > -- reset-names: should be "stmmaceth"
> > +- reset-names: must be "stmmaceth"
> > - phy-mode: See ethernet.txt
> > - phy-handle: See ethernet.txt
> > - #address-cells: shall be 1
> > @@ -39,23 +39,38 @@ Optional properties for the following compatibles:
> > - allwinner,leds-active-low: EPHY LEDs are active low
> >
> > Required child node of emac:
> > -- mdio bus node: should be named mdio
> > +- mdio bus node: with compatible "snps,dwmac-mdio"
> >
> > Required properties of the mdio node:
> > - #address-cells: shall be 1
> > - #size-cells: shall be 0
> >
> > -The device node referenced by "phy" or "phy-handle" should be a child node
> > +The device node referenced by "phy" or "phy-handle" must be a child node
> > of the mdio node. See phy.txt for the generic PHY bindings.
> >
> > -Required properties of the phy node with the following compatibles:
> > +The following compatibles require that the mdio node have a mdio-mux child
> > +node called "mdio-mux":
> > + - "allwinner,sun8i-h3-emac"
> > + - "allwinner,sun8i-v3s-emac":
> > +Required properties for the mdio-mux node:
> > + - compatible = "mdio-mux"
> > + - one child mdio for the integrated mdio
> > + - one child mdio for the external mdio if present (V3s have none)
> > +Required properties for the mdio-mux children node:
> > + - reg: 1 for internal MDIO bus, 2 for external MDIO bus
> > +
> > +The following compatibles require a PHY node representing the integrated
> > +PHY, under the integrated MDIO bus node if an mdio-mux node is used:
> >- "allwinner,sun8i-h3-emac",
> >- "allwinner,sun8i-v3s-emac":
> > +
> > +Required properties of the integrated phy node:
> > - clocks: a phandle to the reference clock for the EPHY
> > - resets: a phandle to the reset control for the EPHY
> > +- phy-is-integrated
> > +- Must be a child of the integrated mdio
> >
> > -Example:
> > -
> > +Example with integrated PHY:
> > emac: ethernet@1c0b000 {
> > compatible = "allwinner,sun8i-h3-emac";
> > syscon = <&syscon>;
> > @@ -72,13 +87,112 @@ emac: ethernet@1c0b000 {
> > phy-handle = <&int_mii_phy>;
> > phy-mode = "mii";
> > allwinner,leds-active-low;
> > +
> > + mdio0: mdio {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "snps,dwmac-mdio";
> > +
> > + mdio-mux {
> > + compatible = "mdio-mux";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
>
> Sorry for chiming in so late, but why don't we have the mdio-mux be the
> root node here in the mdio bus hierarchy? I understand that with this
> binding proposed here, we need to have patch 11 included (which btw,
> should come before any DTS change), but this does not seem to accurately
> model the HW.
>
> The mux itself is not a child node of the MDIO bus controller, it does
> not really belong in that address space although it does mangle the MDIO
> bus controller address space between the two ends of the mux.
>
> If this has been debated before, apologies for missing that part of the
> discussion.
>
I have done it as asked by Rob.
https://lkml.org/lkml/2017/9/13/422
https://lkml.org/lkml/2017/9/19/849
Regards
Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY
On Wed, Sep 27, 2017 at 04:02:10PM +0200, Andrew Lunn wrote: > Hi Corentin > > > +Required properties for the mdio-mux node: > > + - compatible = "mdio-mux" > > This is too generic. Please add a more specific compatible for this > particular mux. You can keep "mdio-mux", since that is what the MDIO > subsystem will look for. > I will add allwinner,sun8i-h3-mdio-mux > > +Required properties of the integrated phy node: > > - clocks: a phandle to the reference clock for the EPHY > > - resets: a phandle to the reset control for the EPHY > > +- phy-is-integrated > > So the last thing you said is that the mux is not the problem > here. Something else is locking up. Did you discover what? > > I really would like phy-is-integrated to go away. > I have found the problem: by enabling ephy clk/reset the timeout does not occur anymore. So we could remove phy-is-integrated by: Moving internal phy clk/reset handling in mdio_mux_syscon_switch_fn() But this means: - getting internalphy node always by manually get internal_mdio/internal_phy (and not by the given phyhandle) - doing some unnecessary tasks (enable/scan/disable) when external_phy is needed Regards
Re: [PATCH v3 05/11] net: stmmac: dwmac-rk: Add internal phy support
On Thu, Aug 03, 2017 at 07:06:33PM +0800, Chen-Yu Tsai wrote:
> On Thu, Aug 3, 2017 at 1:38 AM, Florian Fainelli wrote:
> > On 08/01/2017 11:21 PM, David Wu wrote:
> >> To make internal phy work, need to configure the phy_clock,
> >> phy cru_reset and related registers.
> >>
> >> Signed-off-by: David Wu
> >> ---
> >> .../devicetree/bindings/net/rockchip-dwmac.txt | 6 +-
> >> drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 81
> >> ++
> >> 2 files changed, 86 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> >> b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> >> index 8f42755..ec39b31 100644
> >> --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> >> +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> >> @@ -25,7 +25,8 @@ Required properties:
> >> - clock-names: One name for each entry in the clocks property.
> >> - phy-mode: See ethernet.txt file in the same directory.
> >> - pinctrl-names: Names corresponding to the numbered pinctrl states.
> >> - - pinctrl-0: pin-control mode. can be <&rgmii_pins> or <&rmii_pins>.
> >> + - pinctrl-0: pin-control mode. can be <&rgmii_pins>, <&rmii_pins> or led
> >> pins
> >> + for internal phy mode.
> >> - clock_in_out: For RGMII, it must be "input", means main clock(125MHz)
> >> is not sourced from SoC's PLL, but input from PHY; For RMII, "input"
> >> means
> >> PHY provides the reference clock(50MHz), "output" means GMAC provides
> >> the
> >> @@ -40,6 +41,9 @@ Optional properties:
> >> - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as
> >> default.
> >> - rx_delay: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as
> >> default.
> >> - phy-supply: phandle to a regulator if the PHY needs one
> >> + - clocks: <&cru MAC_PHY>: Clock selector for internal macphy
> >> + - phy-is-internal: A boolean property allows us to know that MAC will
> >> connect to
> >> + internal phy.
> >
> > This is incorrect in two ways:
> >
> > - this is a property of the PHY, so it should be documented as such in
> > Documentation/devicetree/bindings/net/phy.txt so other bindings can
> > re-use it
> >
> > - if it was specific to your MAC you would expect a vendor prefix to
> > this property, which is not there
> >
> > An alternative way to implement the external/internal logic selection
> > would be mandate that your Ethernet PHY node have a compatible string
> > like this:
> >
> > phy@0 {
> > compatible = "ethernet-phy-id1234.d400", "ethernet-phy-802.3-c22";
> > };
> >
> > Then you don't need this phy-is-internal property, because you can
> > locate the PHY node by the phy-handle (see more about that in a reply to
> > patch 10) and you can determine ahead of time whether this PHY is
> > internal or not based on its compatible string.
>
> This doesn't really work for us (sunxi). The "internal" PHY of the H3
> is also available in the X-Powers AC200 combo chip, which would be
> external. Same ID. So if someone were to be stupid and put the two
> together, you wouldn't know which one it actually is. Generically
> it doesn't make sense to match against the ID either. The PHY is
> only integrated or inlined into the SoC, meaning it could be moved
> elsewhere or even be a discreet part.
>
> The way I see it is more like a reversed pinmux. The system should
> select either the internal set or external set of xMII pins to use.
>
> A phy-is-internal property in the PHY node would work for us. We
> already need a PHY node to describe its clocks and resets.
>
> A side note to this solution is that, since the internal PHY is defined
> at the .dtsi level, any external PHYs at the same address would need to
> make sure to delete the property, which is kind of counterintuitive, but
> it is how device tree works. One would want to put the internal PHY's
> address, assuming it is configurable, on something that is rarely used.
>
Hello David, Florian, Andrew
Could someone ack this ? or nack if you think that the chance for having two
PHY id both internal and external is too low.
Anyway, we need a choice.
Regards
[PATCH 1/3] Documentation: bindings: Add documentation for phy-is-integrated
This patch adds documentation for phy-is-integrated, a boolean property
for PHY which permit to know if the PHY is integrated in the SoC.
For example, Allwinner H3 embeds an internal PHY but still permit to
connect an external PHY.
Since it is possible in theory to have the same PHY model both internal
and external, the only way to detect the location of the PHY is via this
property.
Signed-off-by: Corentin Labbe
---
Documentation/devicetree/bindings/net/phy.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/phy.txt
b/Documentation/devicetree/bindings/net/phy.txt
index b55857696fc3..6fabc14da432 100644
--- a/Documentation/devicetree/bindings/net/phy.txt
+++ b/Documentation/devicetree/bindings/net/phy.txt
@@ -52,6 +52,10 @@ Optional Properties:
Mark the corresponding energy efficient ethernet mode as broken and
request the ethernet to stop advertising it.
+- phy-is-integrated: If set, indicates that the PHY is integrated in the SoC
+ and so is not an external PHY. (Some SoC embeds a PHY and still provide
+ support for an optional external PHY)
+
Example:
ethernet-phy@0 {
--
2.13.0
[PATCH 3/3] net: stmmac: dwmac-sun8i: choose internal PHY via phy-is-integrated
The current way to find if the phy is internal is to compare DT phy-mode
and emac_variant/internal_phy.
But it will negate a possible future SoC where an external PHY use the
same phy mode than the internal one.
This patch adds a new way to find if the PHY is internal, via
the phy-is-integrated property.
Since the internal_phy variable does not need anymore to contain the xMII mode
used by the internal PHY, it is still used for knowing the presence of an
internal PHY, so it is modified to a boolean soc_has_internal_phy.
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index fffd6d5fc907..672553b652bd 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -41,14 +41,14 @@
* This value is used for disabling properly EMAC
* and used as a good starting value in case of the
* boot process(uboot) leave some stuff.
- * @internal_phy: Does the MAC embed an internal PHY
+ * @soc_has_internal_phy: Does the MAC embed an internal PHY
* @support_mii: Does the MAC handle MII
* @support_rmii: Does the MAC handle RMII
* @support_rgmii: Does the MAC handle RGMII
*/
struct emac_variant {
u32 default_syscon_value;
- int internal_phy;
+ bool soc_has_internal_phy;
bool support_mii;
bool support_rmii;
bool support_rgmii;
@@ -75,7 +75,7 @@ struct sunxi_priv_data {
static const struct emac_variant emac_variant_h3 = {
.default_syscon_value = 0x58000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -83,20 +83,20 @@ static const struct emac_variant emac_variant_h3 = {
static const struct emac_variant emac_variant_v3s = {
.default_syscon_value = 0x38000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true
};
static const struct emac_variant emac_variant_a83t = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rgmii = true
};
static const struct emac_variant emac_variant_a64 = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -648,7 +648,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
"Current syscon value is not the default %x (expect
%x)\n",
val, reg);
- if (gmac->variant->internal_phy) {
+ if (gmac->variant->soc_has_internal_phy) {
if (!gmac->use_internal_phy) {
/* switch to external PHY interface */
reg &= ~H3_EPHY_SELECT;
@@ -932,7 +932,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
}
plat_dat->interface = of_get_phy_mode(dev->of_node);
- if (plat_dat->interface == gmac->variant->internal_phy) {
+ if (of_property_read_bool(plat_dat->phy_node, "phy-is-integrated")) {
dev_info(&pdev->dev, "Will use internal PHY\n");
gmac->use_internal_phy = true;
gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0);
--
2.13.0
[PATCH 2/3] ARM: sun8i: sunxi-h3-h5: add phy-is-integrated property to internal PHY
This patch add the new phy-is-integrated property to the internal PHY node. Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 4b599b5d26f6..54fc24e4c569 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -425,6 +425,7 @@ reg = <1>; clocks = <&ccu CLK_BUS_EPHY>; resets = <&ccu RST_BUS_EPHY>; + phy-is-integrated; }; }; }; -- 2.13.0
[PATCH 0/3] net: stmmac: Detect PHY location with phy-is-integrated
Hello The current way to find if the phy is internal is to compare DT phy-mode and emac_variant/internal_phy. But it will negate a possible future SoC where an external PHY use the same phy mode than the internal one. This patchs series adds a new way to find if the PHY is internal, via the phy-is-integrated DT property. The first and third patch should go via the net tree. the second via the sunxi tree. Thanks Regards Corentin Labbe (3): Documentation: bindings: Add documentation for phy-is-integrated ARM: sun8i: sunxi-h3-h5: add phy-is-integrated property to internal PHY net: stmmac: dwmac-sun8i: choose internal PHY via phy-is-integrated Documentation/devicetree/bindings/net/phy.txt | 4 arch/arm/boot/dts/sunxi-h3-h5.dtsi| 1 + drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 16 3 files changed, 13 insertions(+), 8 deletions(-) -- 2.13.0
Re: [PATCH 2/3] ARM: sun8i: sunxi-h3-h5: add phy-is-integrated property to internal PHY
On Fri, Aug 11, 2017 at 10:42:51AM +0800, Chen-Yu Tsai wrote: > Hi, > > On Thu, Aug 10, 2017 at 4:51 PM, Corentin Labbe > wrote: > > This patch add the new phy-is-integrated property to the internal PHY > > node. > > > > Signed-off-by: Corentin Labbe > > --- > > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi > > b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > > index 4b599b5d26f6..54fc24e4c569 100644 > > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi > > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > > @@ -425,6 +425,7 @@ > > reg = <1>; > > clocks = <&ccu CLK_BUS_EPHY>; > > resets = <&ccu RST_BUS_EPHY>; > > + phy-is-integrated; > > You also need to "delete" this property at the board level for > any board that has the external PHY at address <1>. Otherwise > they will stop working. This is due to the internal and external > PHYs having the same path and node name in the device tree, so > they are effectively the same node. > > ChenYu > They have not the same name, ext_rgmii_phy vs int_mii_phy.
Re: [PATCH 2/3] ARM: sun8i: sunxi-h3-h5: add phy-is-integrated property to internal PHY
On Fri, Aug 11, 2017 at 04:11:13PM +0800, Chen-Yu Tsai wrote: > On Fri, Aug 11, 2017 at 4:05 PM, Corentin Labbe > wrote: > > On Fri, Aug 11, 2017 at 10:42:51AM +0800, Chen-Yu Tsai wrote: > >> Hi, > >> > >> On Thu, Aug 10, 2017 at 4:51 PM, Corentin Labbe > >> wrote: > >> > This patch add the new phy-is-integrated property to the internal PHY > >> > node. > >> > > >> > Signed-off-by: Corentin Labbe > >> > --- > >> > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 1 + > >> > 1 file changed, 1 insertion(+) > >> > > >> > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi > >> > b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > >> > index 4b599b5d26f6..54fc24e4c569 100644 > >> > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi > >> > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > >> > @@ -425,6 +425,7 @@ > >> > reg = <1>; > >> > clocks = <&ccu CLK_BUS_EPHY>; > >> > resets = <&ccu RST_BUS_EPHY>; > >> > + phy-is-integrated; > >> > >> You also need to "delete" this property at the board level for > >> any board that has the external PHY at address <1>. Otherwise > >> they will stop working. This is due to the internal and external > >> PHYs having the same path and node name in the device tree, so > >> they are effectively the same node. > >> > >> ChenYu > >> > > > > They have not the same name, ext_rgmii_phy vs int_mii_phy. > > That is just the label. The label plays no part in device tree merging. The > path > > /soc/ethernet@1c3/mdio/ethernet-phy@1 > > is the same. You can look under > > /proc/device-tree/soc/ethernet@1c3/mdio > > on the OrangePI Plus 2E or any other H3 board that uses an > external PHY at address 1. > > ChenYu Since we get the phy node by phy-handle and not by path, I think all should be good.
Re: [PATCH 2/3] ARM: sun8i: sunxi-h3-h5: add phy-is-integrated property to internal PHY
On Fri, Aug 11, 2017 at 04:22:11PM +0800, Chen-Yu Tsai wrote: > On Fri, Aug 11, 2017 at 4:19 PM, Corentin Labbe > wrote: > > On Fri, Aug 11, 2017 at 04:11:13PM +0800, Chen-Yu Tsai wrote: > >> On Fri, Aug 11, 2017 at 4:05 PM, Corentin Labbe > >> wrote: > >> > On Fri, Aug 11, 2017 at 10:42:51AM +0800, Chen-Yu Tsai wrote: > >> >> Hi, > >> >> > >> >> On Thu, Aug 10, 2017 at 4:51 PM, Corentin Labbe > >> >> wrote: > >> >> > This patch add the new phy-is-integrated property to the internal PHY > >> >> > node. > >> >> > > >> >> > Signed-off-by: Corentin Labbe > >> >> > --- > >> >> > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 1 + > >> >> > 1 file changed, 1 insertion(+) > >> >> > > >> >> > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi > >> >> > b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > >> >> > index 4b599b5d26f6..54fc24e4c569 100644 > >> >> > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi > >> >> > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > >> >> > @@ -425,6 +425,7 @@ > >> >> > reg = <1>; > >> >> > clocks = <&ccu CLK_BUS_EPHY>; > >> >> > resets = <&ccu RST_BUS_EPHY>; > >> >> > + phy-is-integrated; > >> >> > >> >> You also need to "delete" this property at the board level for > >> >> any board that has the external PHY at address <1>. Otherwise > >> >> they will stop working. This is due to the internal and external > >> >> PHYs having the same path and node name in the device tree, so > >> >> they are effectively the same node. > >> >> > >> >> ChenYu > >> >> > >> > > >> > They have not the same name, ext_rgmii_phy vs int_mii_phy. > >> > >> That is just the label. The label plays no part in device tree merging. > >> The path > >> > >> /soc/ethernet@1c3/mdio/ethernet-phy@1 > >> > >> is the same. You can look under > >> > >> /proc/device-tree/soc/ethernet@1c3/mdio > >> > >> on the OrangePI Plus 2E or any other H3 board that uses an > >> external PHY at address 1. > >> > >> ChenYu > > > > Since we get the phy node by phy-handle and not by path, I think all should > > be good. > > You are not getting me. The fact that the two seemingly separate > nodes are merged together means, whatever properties you put in > the internal PHY node, also affect the external PHY node. Once > compiled, they are the SAME node. So why not changing the internal node name from ethernet-phy to integrated-phy ?
Re: [PATCH 2/3] ARM: sun8i: sunxi-h3-h5: add phy-is-integrated property to internal PHY
On Fri, Aug 11, 2017 at 04:22:11PM +0800, Chen-Yu Tsai wrote:
> On Fri, Aug 11, 2017 at 4:19 PM, Corentin Labbe
> wrote:
> > On Fri, Aug 11, 2017 at 04:11:13PM +0800, Chen-Yu Tsai wrote:
> >> On Fri, Aug 11, 2017 at 4:05 PM, Corentin Labbe
> >> wrote:
> >> > On Fri, Aug 11, 2017 at 10:42:51AM +0800, Chen-Yu Tsai wrote:
> >> >> Hi,
> >> >>
> >> >> On Thu, Aug 10, 2017 at 4:51 PM, Corentin Labbe
> >> >> wrote:
> >> >> > This patch add the new phy-is-integrated property to the internal PHY
> >> >> > node.
> >> >> >
> >> >> > Signed-off-by: Corentin Labbe
> >> >> > ---
> >> >> > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 1 +
> >> >> > 1 file changed, 1 insertion(+)
> >> >> >
> >> >> > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> >> >> > b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> >> >> > index 4b599b5d26f6..54fc24e4c569 100644
> >> >> > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> >> >> > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> >> >> > @@ -425,6 +425,7 @@
> >> >> > reg = <1>;
> >> >> > clocks = <&ccu CLK_BUS_EPHY>;
> >> >> > resets = <&ccu RST_BUS_EPHY>;
> >> >> > + phy-is-integrated;
> >> >>
> >> >> You also need to "delete" this property at the board level for
> >> >> any board that has the external PHY at address <1>. Otherwise
> >> >> they will stop working. This is due to the internal and external
> >> >> PHYs having the same path and node name in the device tree, so
> >> >> they are effectively the same node.
> >> >>
> >> >> ChenYu
> >> >>
> >> >
> >> > They have not the same name, ext_rgmii_phy vs int_mii_phy.
> >>
> >> That is just the label. The label plays no part in device tree merging.
> >> The path
> >>
> >> /soc/ethernet@1c3/mdio/ethernet-phy@1
> >>
> >> is the same. You can look under
> >>
> >> /proc/device-tree/soc/ethernet@1c3/mdio
> >>
> >> on the OrangePI Plus 2E or any other H3 board that uses an
> >> external PHY at address 1.
> >>
> >> ChenYu
> >
> > Since we get the phy node by phy-handle and not by path, I think all should
> > be good.
>
> You are not getting me. The fact that the two seemingly separate
> nodes are merged together means, whatever properties you put in
> the internal PHY node, also affect the external PHY node. Once
> compiled, they are the SAME node.
Hello Rob, florian, mark
Adding a delete property on all external ethernet-phy@1 is a bit overkill, and
I dont like the idea that nodes are merged.
What do you think about other possible solutions:
- Using integrated-phy@1 for the integrated PHY node name
- Using a fake address like 31 (see patch below)
If you have any other solution...
Regards
>From fe39183946f7f4a6e21bce38fd8e4c1413012d68 Mon Sep 17 00:00:00 2001
From: Corentin Labbe
Date: Fri, 11 Aug 2017 14:49:54 +0200
Subject: [PATCH] ARM: sun8i: sunxi-h3-h5: Prevent merge of external and
integrated PHY
Actually, some external and integrated PHY are merged due to same dtnode
name "ethernet-phy@1".
This is problematic when we will want to use the phy-is-integrated
property. (Need to delete it on all external PHY node)
An easy solution is to set integrated PHY nodeaddresss at a fake one
that would never be used.
Since board makers currently only provides PHY at addresses 1 and 7,
we will use 31.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 54fc24e4c569..2110b0069e33 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -420,7 +420,15 @@
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
- int_mii_phy: ethernet-phy@1 {
+ /*
+* Using 31 permits to make a separation between
+* this integrated PHY and external ones.
+* Without it, external "ethernet-phy@1" will be
+* merged with it (due to same dtnode name).
+* Board makers currently only provides PHY at
+* addresses 1 and 7.
+*/
+ int_mii_phy: ethernet-phy@31 {
compatible =
"ethernet-phy-ieee802.3-c22";
reg = <1>;
clocks = <&ccu CLK_BUS_EPHY>;
--
2.13.0
Re: [PATCH 2/3] ARM: sun8i: sunxi-h3-h5: add phy-is-integrated property to internal PHY
On Fri, Aug 11, 2017 at 08:03:29AM -0700, Florian Fainelli wrote: > On August 11, 2017 6:25:26 AM PDT, Corentin Labbe > wrote: > >On Fri, Aug 11, 2017 at 04:22:11PM +0800, Chen-Yu Tsai wrote: > >> On Fri, Aug 11, 2017 at 4:19 PM, Corentin Labbe > >> wrote: > >> > On Fri, Aug 11, 2017 at 04:11:13PM +0800, Chen-Yu Tsai wrote: > >> >> On Fri, Aug 11, 2017 at 4:05 PM, Corentin Labbe > >> >> wrote: > >> >> > On Fri, Aug 11, 2017 at 10:42:51AM +0800, Chen-Yu Tsai wrote: > >> >> >> Hi, > >> >> >> > >> >> >> On Thu, Aug 10, 2017 at 4:51 PM, Corentin Labbe > >> >> >> wrote: > >> >> >> > This patch add the new phy-is-integrated property to the > >internal PHY > >> >> >> > node. > >> >> >> > > >> >> >> > Signed-off-by: Corentin Labbe > >> >> >> > --- > >> >> >> > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 1 + > >> >> >> > 1 file changed, 1 insertion(+) > >> >> >> > > >> >> >> > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi > >b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > >> >> >> > index 4b599b5d26f6..54fc24e4c569 100644 > >> >> >> > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi > >> >> >> > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > >> >> >> > @@ -425,6 +425,7 @@ > >> >> >> > reg = <1>; > >> >> >> > clocks = <&ccu > >CLK_BUS_EPHY>; > >> >> >> > resets = <&ccu > >RST_BUS_EPHY>; > >> >> >> > + phy-is-integrated; > >> >> >> > >> >> >> You also need to "delete" this property at the board level for > >> >> >> any board that has the external PHY at address <1>. Otherwise > >> >> >> they will stop working. This is due to the internal and > >external > >> >> >> PHYs having the same path and node name in the device tree, so > >> >> >> they are effectively the same node. > >> >> >> > >> >> >> ChenYu > >> >> >> > >> >> > > >> >> > They have not the same name, ext_rgmii_phy vs int_mii_phy. > >> >> > >> >> That is just the label. The label plays no part in device tree > >merging. The path > >> >> > >> >> /soc/ethernet@1c3/mdio/ethernet-phy@1 > >> >> > >> >> is the same. You can look under > >> >> > >> >> /proc/device-tree/soc/ethernet@1c3/mdio > >> >> > >> >> on the OrangePI Plus 2E or any other H3 board that uses an > >> >> external PHY at address 1. > >> >> > >> >> ChenYu > >> > > >> > Since we get the phy node by phy-handle and not by path, I think > >all should be good. > >> > >> You are not getting me. The fact that the two seemingly separate > >> nodes are merged together means, whatever properties you put in > >> the internal PHY node, also affect the external PHY node. Once > >> compiled, they are the SAME node. > > > >Hello Rob, florian, mark > > > >Adding a delete property on all external ethernet-phy@1 is a bit > >overkill, and I dont like the idea that nodes are merged. > > This is not exactly up to you that's just how DTC works. > > >What do you think about other possible solutions: > >- Using integrated-phy@1 for the integrated PHY node name > > That might be okay although you are using now a seemingly non-standard unit > name. > > >- Using a fake address like 31 (see patch below) > > You could also drop the address part in the unit name although we'd probably > get a DTC warning for that. > > I suspect both of your solutions and what I mentioned above will be producing > DTC warnings to some extent... Rob what do you think? > I think I found an easier solution, putting phy-is-integrated on board DT nodes only. I will send an updated serie. Regards
[PATCH v2 6/6] net: stmmac: dwmac-sun8i: choose internal PHY via phy-is-integrated
The current way to find if the phy is internal is to compare DT phy-mode
and emac_variant/internal_phy.
But it will negate a possible future SoC where an external PHY use the
same phy mode than the internal one.
This patch adds a new way to find if the PHY is internal, via
the phy-is-integrated property.
Since the internal_phy variable does not need anymore to contain the xMII mode
used by the internal PHY, it is still used for knowing the presence of an
internal PHY, so it is modified to a boolean soc_has_internal_phy.
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index fffd6d5fc907..672553b652bd 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -41,14 +41,14 @@
* This value is used for disabling properly EMAC
* and used as a good starting value in case of the
* boot process(uboot) leave some stuff.
- * @internal_phy: Does the MAC embed an internal PHY
+ * @soc_has_internal_phy: Does the MAC embed an internal PHY
* @support_mii: Does the MAC handle MII
* @support_rmii: Does the MAC handle RMII
* @support_rgmii: Does the MAC handle RGMII
*/
struct emac_variant {
u32 default_syscon_value;
- int internal_phy;
+ bool soc_has_internal_phy;
bool support_mii;
bool support_rmii;
bool support_rgmii;
@@ -75,7 +75,7 @@ struct sunxi_priv_data {
static const struct emac_variant emac_variant_h3 = {
.default_syscon_value = 0x58000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -83,20 +83,20 @@ static const struct emac_variant emac_variant_h3 = {
static const struct emac_variant emac_variant_v3s = {
.default_syscon_value = 0x38000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true
};
static const struct emac_variant emac_variant_a83t = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rgmii = true
};
static const struct emac_variant emac_variant_a64 = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -648,7 +648,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
"Current syscon value is not the default %x (expect
%x)\n",
val, reg);
- if (gmac->variant->internal_phy) {
+ if (gmac->variant->soc_has_internal_phy) {
if (!gmac->use_internal_phy) {
/* switch to external PHY interface */
reg &= ~H3_EPHY_SELECT;
@@ -932,7 +932,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
}
plat_dat->interface = of_get_phy_mode(dev->of_node);
- if (plat_dat->interface == gmac->variant->internal_phy) {
+ if (of_property_read_bool(plat_dat->phy_node, "phy-is-integrated")) {
dev_info(&pdev->dev, "Will use internal PHY\n");
gmac->use_internal_phy = true;
gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0);
--
2.13.0
[PATCH v2 5/6] ARM: sun8i: orangepi-one: Set phy-is-integrated to the internal phy node
This patch add the new phy-is-integrated property to the internal PHY node.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index 6880268e8b87..22c471473909 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -105,6 +105,10 @@
status = "okay";
};
+&int_mii_phy {
+ phy-is-integrated;
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
--
2.13.0
[PATCH v2 4/6] ARM: sun8i: orangepi-2: Set phy-is-integrated to the internal phy node
This patch add the new phy-is-integrated property to the internal PHY node.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index 17cdeae19c6f..0801c808c5e5 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -131,6 +131,10 @@
status = "okay";
};
+&int_mii_phy {
+ phy-is-integrated;
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
--
2.13.0
[PATCH v2 1/6] ARM: sun8i: orangepipc: Set phy-is-integrated to the internal phy node
This patch add the new phy-is-integrated property to the internal PHY
node.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index f5f0f15a2088..68a618b5f18c 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -131,6 +131,10 @@
status = "okay";
};
+&int_mii_phy {
+ phy-is-integrated;
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
--
2.13.0
[PATCH v2 3/6] ARM: sun8i: nanopi-neo: Set phy-is-integrated to the internal phy node
This patch add the new phy-is-integrated property to the internal PHY node.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
index 78f6c24952dd..e77b51c98374 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
@@ -53,3 +53,7 @@
allwinner,leds-active-low;
status = "okay";
};
+
+&int_mii_phy {
+ phy-is-integrated;
+};
--
2.13.0
[PATCH v2 0/6] net: stmmac: Detect PHY location with phy-is-integrated
Hello The current way to find if the phy is internal is to compare DT phy-mode and emac_variant/internal_phy. But it will negate a possible future SoC where an external PHY use the same phy mode than the integrated one. This patchs series adds a new way to find if the PHY is integrated, via the phy-is-integrated DT property. Since it exists both integrated and external ethernet-phy@1, they are merged in the final DTB and so share all properties. For avoiding this, the phy-is-integrated is added only to board DT. The first five patchs should go via the sunxi tree. the last one should go via the net tree. Note that this serie will need backporting the patch "Documentation: net: phy: Add phy-is-integrated binding" which is in net-next Thanks Regards Changes since v1: - Dropped phy-is-integrated documentation patch since another same patch was already merged - Moved phy-is-integrated from SoC dtsi to final board DT. Corentin Labbe (6): ARM: sun8i: orangepipc: Set phy-is-integrated to the internal phy node ARM: sun8i: beelink-x2: Set phy-is-integrated to the internal phy node ARM: sun8i: nanopi-neo: Set phy-is-integrated to the internal phy node ARM: sun8i: orangepi-2: Set phy-is-integrated to the internal phy node ARM: sun8i: orangepi-one: Set phy-is-integrated to the internal phy node net: stmmac: dwmac-sun8i: choose internal PHY via phy-is-integrated arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 4 arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 4 arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 4 arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 4 arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts| 4 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 16 6 files changed, 28 insertions(+), 8 deletions(-) -- 2.13.0
[PATCH v2 2/6] ARM: sun8i: beelink-x2: Set phy-is-integrated to the internal phy node
This patch add the new phy-is-integrated property to the internal PHY node.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
index 546837ccd8af..d0517240d5e3 100644
--- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
@@ -121,6 +121,10 @@
status = "okay";
};
+&int_mii_phy {
+ phy-is-integrated;
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
--
2.13.0
