Re: [PATCH] net: marvell: mvneta: fix DMA debug warning
Hi Russell, On ven., févr. 15 2019, Russell King wrote: > Booting 4.20 on SolidRun Clearfog issues this warning with DMA API > debug enabled: > > WARNING: CPU: 0 PID: 555 at kernel/dma/debug.c:1230 check_sync+0x514/0x5bc > mvneta f107.ethernet: DMA-API: device driver tries to sync DMA memory it > has not allocated [device address=0x2dd7dc00] [size=240 bytes] > Modules linked in: ahci mv88e6xxx dsa_core xhci_plat_hcd xhci_hcd devlink > armada_thermal marvell_cesa des_generic ehci_orion phy_armada38x_comphy > mcp3021 spi_orion evbug sfp mdio_i2c ip_tables x_tables > CPU: 0 PID: 555 Comm: bridge-network- Not tainted 4.20.0+ #291 > Hardware name: Marvell Armada 380/385 (Device Tree) > [] (unwind_backtrace) from [] (show_stack+0x10/0x14) > [] (show_stack) from [] (dump_stack+0x9c/0xd4) > [] (dump_stack) from [] (__warn+0xf8/0x124) > [] (__warn) from [] (warn_slowpath_fmt+0x38/0x48) > [] (warn_slowpath_fmt) from [] (check_sync+0x514/0x5bc) > [] (check_sync) from [] > (debug_dma_sync_single_range_for_cpu+0x6c/0x74) > [] (debug_dma_sync_single_range_for_cpu) from [] > (mvneta_poll+0x298/0xf58) > [] (mvneta_poll) from [] (net_rx_action+0x128/0x424) > [] (net_rx_action) from [] (__do_softirq+0xf0/0x540) > [] (__do_softirq) from [] (irq_exit+0x124/0x144) > [] (irq_exit) from [] (__handle_domain_irq+0x58/0xb0) > [] (__handle_domain_irq) from [] > (gic_handle_irq+0x48/0x98) > [] (gic_handle_irq) from [] (__irq_svc+0x70/0x98) > ... > > This appears to be caused by mvneta_rx_hwbm() calling > dma_sync_single_range_for_cpu() with the wrong struct device pointer, > as the buffer manager device pointer is used to map and unmap the > buffer. Fix this. > For me it makes sens to associate the DMA buffer to the HWBM, so this fixes looks good for me. Reviwed-by: Gregory CLEMENT Thanks, Gregory > Signed-off-by: Russell King > --- > Please check that this is the correct fix. > > drivers/net/ethernet/marvell/mvneta.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/marvell/mvneta.c > b/drivers/net/ethernet/marvell/mvneta.c > index ef0a85bbc586..0e1f87fca952 100644 > --- a/drivers/net/ethernet/marvell/mvneta.c > +++ b/drivers/net/ethernet/marvell/mvneta.c > @@ -2086,7 +2086,7 @@ static int mvneta_rx_hwbm(struct napi_struct *napi, > if (unlikely(!skb)) > goto err_drop_frame_ret_pool; > > - dma_sync_single_range_for_cpu(dev->dev.parent, > + dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev, > rx_desc->buf_phys_addr, > MVNETA_MH_SIZE + > NET_SKB_PAD, > rx_bytes, > -- > 2.7.4 > -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com
Re: [PATCH RFC RFT net-next 00/10] Modernize mv88e6060 and remove legacy probe
Hi Andrew, On mer., janv. 30 2019, Andrew Lunn wrote: > The mv88e6060 is the last device using the legacy method of probing an > DSA Ethernet switch. This patchset applies some cleanups to the > driver, and then adds support for probing the device as an MDIO bus > device. The legacy probe is then removed from the driver, and then > from DSA as a whole. > > This is compile tested only. Comment and testing welcome. > > It should not be merged yet, and one of the patches should go via > arm-soc. > > Andrew Lunn (10): > net: dsa: mv88e6xxx: Remove legacy probe support > net: dsa: mv88e6060: Replace ds with priv > net: dsa: mv88e6060: Replace REG_WRITE macro > net: dsa: mv88e6060: Replace REG_READ macro > net: dsa: mv88e6060: Support probing as an mdio device > net: dsa: mv88e6060: Remove support for legacy probing > net: dsa: mv88e6060: Add SPDX header > net: dsa: Remove legacy probing support > arch: arm: dts: Remove disabled marvell,dsa properties > bt-bindings: net: DSA: Remove legacy binding I saw there was some test already done on this series, but unless I am wrong it was not applied yet. Do you plan to send a new iteration soon? I am asking because this week the dt part can be applied to be merged in v5.1, whereas next week, it will be doable but as rc6 will be released there will be less chance to be accepted. Thanks, Gregory > > .../devicetree/bindings/net/dsa/dsa.txt | 155 > arch/arm/boot/dts/armada-370-rd.dts | 42 - > arch/arm/boot/dts/armada-388-clearfog.dts | 58 -- > arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 47 -- > arch/arm/boot/dts/kirkwood-dir665.dts | 47 -- > arch/arm/boot/dts/kirkwood-linksys-viper.dts | 47 -- > .../arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts | 47 -- > arch/arm/boot/dts/kirkwood-rd88f6281.dtsi | 41 - > drivers/net/dsa/Kconfig | 2 +- > drivers/net/dsa/mv88e6060.c | 217 ++--- > drivers/net/dsa/mv88e6060.h | 1 + > drivers/net/dsa/mv88e6xxx/chip.c | 71 +- > include/net/dsa.h | 23 - > net/dsa/Kconfig | 9 - > net/dsa/Makefile | 1 - > net/dsa/dsa.c | 5 - > net/dsa/dsa_priv.h| 12 - > net/dsa/legacy.c | 745 -- > 18 files changed, 121 insertions(+), 1449 deletions(-) > > -- > 2.20.1 > -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com
Re: [PATCH 2/2] arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal
Hi Baruch,
On mar., oct. 16 2018, Baruch Siach wrote:
> This reset signal controls the Marvell 1512 1G PHY.
>
> Note that current implementation queries the PHY over the MDIO bus
> (get_phy_device() call from of_mdiobus_register_phy()) before reset
> signal deassert. If the PHY reset signal is asserted at boot time, PHY
> registration fails. So current code relies on the bootloader to deassert
> the reset signal.
Applied on mvebu/dt64
Thanks,
Gregory
>
> Signed-off-by: Baruch Siach
> ---
> arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> index af1310c53bc8..73df0ef5e0c4 100644
> --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> @@ -337,6 +337,10 @@
>*/
> marvell,reg-init = <3 16 0 0x1017>;
> reg = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&cp0_copper_eth_phy_reset>;
> + reset-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <1>;
> };
>
> switch0: switch0@4 {
> --
> 2.19.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
Re: [PATCH 1/2] arm64: dts: clearfog-gt-8k: fix USB regulator gpio polarity
Hi Baruch,
On mar., oct. 16 2018, Baruch Siach wrote:
> The fixed regulator driver ignores the gpio flags, so this change has
> no practical effect in the current implementation. Fix it anyway to
> correct the hardware description.
>
Applied on mvebu/dt64
Thanks,
Gregory
> Signed-off-by: Baruch Siach
> ---
> arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> index aea9c220ae6a..af1310c53bc8 100644
> --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> @@ -42,7 +42,7 @@
>
> v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
> compatible = "regulator-fixed";
> - gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
> + gpio = <&cp0_gpio2 15 GPIO_ACTIVE_LOW>;
> pinctrl-names = "default";
> pinctrl-0 = <&cp0_xhci_vbus_pins>;
> regulator-name = "v_5v0_usb3_hst_vbus";
> --
> 2.19.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
Re: [PATCH net-next v3 00/10] net: mvpp2: phylink conversion
Hi Antoine, On jeu., mai 17 2018, Antoine Tenart wrote: > Hi Dave, Russell, > > This series convert the Marvell PPv2 driver to phylink (models the MAC > to PHY link). > > One important point is the PPv2 driver supports two probe modes: device > tree and ACPI. This series only brings phylink support for the device > tree mode, as the ACPI one will need further work. Still, the driver > should be working as before when using ACPI. This split should be > temporary, and was discussed with Marcin (in Cc.) who added ACPI support > to the driver. > > Also as the SFP cages on both DB boards can be considered as non-wired. > We thus chose not to describe those SFP cages and we use fixed-link. > > The rest of the series uses phylink to add support for 1000BaseX and > 2500BaseX modes in the PPv2 driver. To do this, two patches are needed > in the common PHY framework (patches 3 and 4). The last 4 patches modify > the device tree to use the new PPv2 functionalities. > > The series has been tested for the device tree mode on the 7040-db, > 8040-db and 8040-mcbin boards, to ensure all the interface where working > as expected. > > @Dave: patches 7 to 10 should go through the mvebu tree (Gregory in > Cc.) to avoid any conflict with the other mvebu dt patches taken during > this cycle. Patches 7 to 10 have been applied on mvebu/dt64. Thanks, Gregory > > The series is based on today's net-next. > > Thanks! > Antoine > > Since v2: > - Removed the SFP description from the DB boards, as their SFP cages > are wired properly. We now use fixed-link. > - Because of this rework, split the series in two, so that the SFP > part is reviewed separately. > - Small fixes in the phylink patch. > - Rebased on the latest net-next branch. > > Since v1: > - Chose a different approach to the SFP changes, as the previous ones > weren't valid and reworked both BD boards device trees. > - Misc fixes. > - Added Kishon's acked-by on one patch. > - Rebaed on latest net-next branch. > > Antoine Tenart (9): > net: mvpp2: align the ethtool ops definition > net: mvpp2: phylink support > phy: add 2.5G SGMII mode to the phy_mode enum > phy: cp110-comphy: 2.5G SGMII mode > net: mvpp2: 1000baseX support > net: mvpp2: 2500baseX support > arm64: dts: marvell: mcbin: enable the fourth network interface > arm64: dts: marvell: 8040-db: describe the 10G interfaces as > fixed-link > arm64: dts: marvell: 7040-db: describe the 10G interface as fixed-link > > Russell King (1): > arm64: dts: marvell: mcbin: add 10G SFP support > > .../arm64/boot/dts/marvell/armada-7040-db.dts | 5 + > .../arm64/boot/dts/marvell/armada-8040-db.dts | 10 + > .../boot/dts/marvell/armada-8040-mcbin.dts| 70 ++ > drivers/net/ethernet/marvell/Kconfig | 1 + > drivers/net/ethernet/marvell/mvpp2.c | 931 +++++++--- > drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 17 +- > include/linux/phy/phy.h | 1 + > 7 files changed, 680 insertions(+), 355 deletions(-) > > -- > 2.17.0 > -- Gregory Clement, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering http://bootlin.com
Re: [PATCH net 3/3] ARM64: dts: marvell: armada-cp110: Add clocks for the xmdio node
Hi agin,
On mer., avril 25 2018, Gregory CLEMENT wrote:
> Hi Maxime,
>
> On mer., avril 25 2018, Maxime Chevallier
> wrote:
>
>> The Marvell XSMI controller needs 3 clocks to operate correctly :
>> - The MG clock (clk 5)
>> - The MG Core clock (clk 6)
>> - The GOP clock (clk 18)
>>
>> This commit adds them, to avoid system hangs when using these
>> interfaces.
>>
>> Fixes: c7e92def1ef4 ("clk: mvebu: cp110: Fix clock tree representation")
>> Signed-off-by: Maxime Chevallier
>
> This patch should not have been sent with the net prefix and should not
> be merge through the net subsystem.
>
> I will take care of it to avoid conflict in the devei tree file during
> the merge windows.
So, applied on mvebu/fixes
Thanks,
Gregory
>
> Thanks,
>
> Gregory
>
>> ---
>> arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
>> b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
>> index 6c137ac656e9..ed2f1237ea1e 100644
>> --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
>> +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
>> @@ -142,6 +142,8 @@
>> #size-cells = <0>;
>> compatible = "marvell,xmdio";
>> reg = <0x12a600 0x10>;
>> + clocks = <&CP110_LABEL(clk) 1 5>,
>> + <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1
>> 18>;
>> status = "disabled";
>> };
>>
>> --
>> 2.11.0
>>
>
> --
> Gregory Clement, Bootlin (formerly Free Electrons)
> Embedded Linux and Kernel engineering
> http://bootlin.com
--
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
Re: [PATCH net 1/3] net: mvpp2: Fix clk error path in mvpp2_probe
Hi Maxime,
On mer., avril 25 2018, Maxime Chevallier
wrote:
> When clk_prepare_enable fails for the axi_clk, the mg_clk isn't properly
> cleaned up. Add another jump label to handle that case, and make sure we
> jump to it in the later error cases.
>
> Fixes: 4792ea04bcd0 ("net: mvpp2: Fix clock resource by adding an optional
> bus clock")
> Signed-off-by: Maxime Chevallier
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> drivers/net/ethernet/marvell/mvpp2.c | 15 ---
> 1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/net/ethernet/marvell/mvpp2.c
> b/drivers/net/ethernet/marvell/mvpp2.c
> index 4202f9b5b966..0c2f04813d42 100644
> --- a/drivers/net/ethernet/marvell/mvpp2.c
> +++ b/drivers/net/ethernet/marvell/mvpp2.c
> @@ -8774,12 +8774,12 @@ static int mvpp2_probe(struct platform_device *pdev)
> if (IS_ERR(priv->axi_clk)) {
> err = PTR_ERR(priv->axi_clk);
> if (err == -EPROBE_DEFER)
> - goto err_gop_clk;
> + goto err_mg_clk;
> priv->axi_clk = NULL;
> } else {
> err = clk_prepare_enable(priv->axi_clk);
> if (err < 0)
> - goto err_gop_clk;
> + goto err_mg_clk;
> }
>
> /* Get system's tclk rate */
> @@ -8793,7 +8793,7 @@ static int mvpp2_probe(struct platform_device *pdev)
> if (priv->hw_version == MVPP22) {
> err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
> if (err)
> - goto err_mg_clk;
> + goto err_axi_clk;
> /* Sadly, the BM pools all share the same register to
>* store the high 32 bits of their address. So they
>* must all have the same high 32 bits, which forces
> @@ -8801,14 +8801,14 @@ static int mvpp2_probe(struct platform_device *pdev)
>*/
> err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
> if (err)
> - goto err_mg_clk;
> + goto err_axi_clk;
> }
>
> /* Initialize network controller */
> err = mvpp2_init(pdev, priv);
> if (err < 0) {
> dev_err(&pdev->dev, "failed to initialize controller\n");
> - goto err_mg_clk;
> + goto err_axi_clk;
> }
>
> /* Initialize ports */
> @@ -8821,7 +8821,7 @@ static int mvpp2_probe(struct platform_device *pdev)
> if (priv->port_count == 0) {
> dev_err(&pdev->dev, "no ports enabled\n");
> err = -ENODEV;
> - goto err_mg_clk;
> + goto err_axi_clk;
> }
>
> /* Statistics must be gathered regularly because some of them (like
> @@ -8849,8 +8849,9 @@ static int mvpp2_probe(struct platform_device *pdev)
> mvpp2_port_remove(priv->port_list[i]);
> i++;
> }
> -err_mg_clk:
> +err_axi_clk:
> clk_disable_unprepare(priv->axi_clk);
> +err_mg_clk:
> if (priv->hw_version == MVPP22)
> clk_disable_unprepare(priv->mg_clk);
> err_gop_clk:
> --
> 2.11.0
>
--
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
Re: [PATCH net 2/3] net: mvpp2: Fix clock resource by adding missing mg_core_clk
g_core_clk");
> + if (IS_ERR(priv->mg_core_clk)) {
> + err = PTR_ERR(priv->mg_core_clk);
> + goto err_mg_clk;
> + }
> +
> + err = clk_prepare_enable(priv->mg_core_clk);
> + if (err < 0)
> + goto err_mg_clk;
> }
>
> priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk");
> if (IS_ERR(priv->axi_clk)) {
> err = PTR_ERR(priv->axi_clk);
> if (err == -EPROBE_DEFER)
> - goto err_mg_clk;
> + goto err_mg_core_clk;
> priv->axi_clk = NULL;
> } else {
> err = clk_prepare_enable(priv->axi_clk);
> if (err < 0)
> - goto err_mg_clk;
> + goto err_mg_core_clk;
> }
>
> /* Get system's tclk rate */
> @@ -8851,6 +8862,10 @@ static int mvpp2_probe(struct platform_device *pdev)
> }
> err_axi_clk:
> clk_disable_unprepare(priv->axi_clk);
> +
> +err_mg_core_clk:
> + if (priv->hw_version == MVPP22)
> + clk_disable_unprepare(priv->mg_core_clk);
> err_mg_clk:
> if (priv->hw_version == MVPP22)
> clk_disable_unprepare(priv->mg_clk);
> @@ -8898,6 +8913,7 @@ static int mvpp2_remove(struct platform_device *pdev)
> return 0;
>
> clk_disable_unprepare(priv->axi_clk);
> + clk_disable_unprepare(priv->mg_core_clk);
> clk_disable_unprepare(priv->mg_clk);
> clk_disable_unprepare(priv->pp_clk);
> clk_disable_unprepare(priv->gop_clk);
> --
> 2.11.0
>
--
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
Re: [PATCH net 3/3] ARM64: dts: marvell: armada-cp110: Add clocks for the xmdio node
Hi Maxime,
On mer., avril 25 2018, Maxime Chevallier
wrote:
> The Marvell XSMI controller needs 3 clocks to operate correctly :
> - The MG clock (clk 5)
> - The MG Core clock (clk 6)
> - The GOP clock (clk 18)
>
> This commit adds them, to avoid system hangs when using these
> interfaces.
>
> Fixes: c7e92def1ef4 ("clk: mvebu: cp110: Fix clock tree representation")
> Signed-off-by: Maxime Chevallier
This patch should not have been sent with the net prefix and should not
be merge through the net subsystem.
I will take care of it to avoid conflict in the devei tree file during
the merge windows.
Thanks,
Gregory
> ---
> arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
> b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
> index 6c137ac656e9..ed2f1237ea1e 100644
> --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
> @@ -142,6 +142,8 @@
> #size-cells = <0>;
> compatible = "marvell,xmdio";
> reg = <0x12a600 0x10>;
> + clocks = <&CP110_LABEL(clk) 1 5>,
> + <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1
> 18>;
> status = "disabled";
> };
>
> --
> 2.11.0
>
--
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
[PATCH] net: mvneta: fix enable of all initialized RXQs
From: Yelena Krivosheev
In mvneta_port_up() we enable relevant RX and TX port queues by write
queues bit map to an appropriate register.
q_map must be ZERO in the beginning of this process.
Signed-off-by: Yelena Krivosheev
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 25e9a551cc8c..3f6fb635738c 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -1132,6 +1132,7 @@ static void mvneta_port_up(struct mvneta_port *pp)
}
mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
+ q_map = 0;
/* Enable all initialized RXQs. */
for (queue = 0; queue < rxq_number; queue++) {
struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
--
2.16.2
Re: [PATCH 0/2] mv88e6xxx: Poll when no interrupt defined
Hi Andrew, On mar., févr. 27 2018, Andrew Lunn wrote: > On Tue, Feb 27, 2018 at 11:24:02AM +0100, Gregory CLEMENT wrote: >> Hi Andrew, >> >> On jeu., févr. 22 2018, Andrew Lunn wrote: >> >> > Not all boards using the mv88e6xxx switches have the interrupt output >> > connected to a GPIO. On these boards phylib has to poll the PHYs, >> > rather than use interrupts. Have the driver poll the interrupt status >> > register, which is more efficient than having phylib do it. And it >> > enables other switch interrupts to be services. >> > >> > The Armada 370RD is such a board without a interrupt GPIO. Now that >> > interrupts work, wire up the PHYs to make use if them. >> > >> > Gregory: Are you O.K. for the second patch to go through netdev? >> >> Why do you need that the second patch to go through netdev. Is there any >> dependency between the 2 patches? >> >> If it is the case does it means that an new kernel won't work with an >> old device tree? > > Hi Gregory > > There is a runtime dependency between the two. A new device tree blob > will not run on an old kernel. So if you take the second patch alone > via mvebu, the PHYs will stop working, no link up reported. > > But an old blob will run on a new kernel. Backwards compatibility is > maintained. Ok so you wanted to keep the kernel bisctable. So I'm fine with having this patch in netdev (and I think it is alrdeay the case). Gregory > > Andrew -- Gregory Clement, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering http://bootlin.com
Re: [PATCH 0/2] mv88e6xxx: Poll when no interrupt defined
Hi Andrew, On jeu., févr. 22 2018, Andrew Lunn wrote: > Not all boards using the mv88e6xxx switches have the interrupt output > connected to a GPIO. On these boards phylib has to poll the PHYs, > rather than use interrupts. Have the driver poll the interrupt status > register, which is more efficient than having phylib do it. And it > enables other switch interrupts to be services. > > The Armada 370RD is such a board without a interrupt GPIO. Now that > interrupts work, wire up the PHYs to make use if them. > > Gregory: Are you O.K. for the second patch to go through netdev? Why do you need that the second patch to go through netdev. Is there any dependency between the 2 patches? If it is the case does it means that an new kernel won't work with an old device tree? Gregory > > Andrew Lunn (2): > net: dsa: mv88e6xxx: Poll when no interrupt defined > arm: mvebu: 370-rd: Enable PHY interrupt handling > > arch/arm/boot/dts/armada-370-rd.dts | 32 > drivers/net/dsa/mv88e6xxx/chip.c| 146 > +--- > drivers/net/dsa/mv88e6xxx/chip.h| 3 + > 3 files changed, 138 insertions(+), 43 deletions(-) > > -- > 2.15.1 > -- Gregory Clement, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering http://bootlin.com
[PATCH net 0/3] Few mvneta fixes
Hello, here it is a small series of fixes found on the mvneta driver. They had been already used in the vendor kernel and are now ported to mainline. Thanks, Gregory Yelena Krivosheev (3): net: mvneta: clear interface link status on port disable net: mvneta: use proper rxq_number in loop on rx queues net: mvneta: eliminate wrong call to handle rx descriptor error drivers/net/ethernet/marvell/mvneta.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.15.1
[PATCH net 1/3] net: mvneta: clear interface link status on port disable
From: Yelena Krivosheev
When port connect to PHY in polling mode (with poll interval 1 sec),
port and phy link status must be synchronize in order don't loss link
change event.
[gregory.clem...@free-electrons.com: add fixes tag]
Cc:
Fixes: c5aff18204da ("net: mvneta: driver for Marvell Armada 370/XP network
unit")
Signed-off-by: Yelena Krivosheev
Tested-by: Dmitri Epshtein
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index bc93b69cfd1e..16b2bfb2cf51 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -1214,6 +1214,10 @@ static void mvneta_port_disable(struct mvneta_port *pp)
val &= ~MVNETA_GMAC0_PORT_ENABLE;
mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
+ pp->link = 0;
+ pp->duplex = -1;
+ pp->speed = 0;
+
udelay(200);
}
--
2.15.1
[PATCH net 3/3] net: mvneta: eliminate wrong call to handle rx descriptor error
From: Yelena Krivosheev
There are few reasons in mvneta_rx_swbm() function when received packet
is dropped. mvneta_rx_error() should be called only if error bit [16]
is set in rx descriptor.
[gregory.clem...@free-electrons.com: add fixes tag]
Cc: sta...@vger.kernel.org
Fixes: dc35a10f68d3 ("net: mvneta: bm: add support for hardware buffer
management")
Signed-off-by: Yelena Krivosheev
Tested-by: Dmitri Epshtein
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 1e0835655c93..a539263cd79c 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -1962,9 +1962,9 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int
rx_todo,
if (!mvneta_rxq_desc_is_first_last(rx_status) ||
(rx_status & MVNETA_RXD_ERR_SUMMARY)) {
+ mvneta_rx_error(pp, rx_desc);
err_drop_frame:
dev->stats.rx_errors++;
- mvneta_rx_error(pp, rx_desc);
/* leave the descriptor untouched */
continue;
}
--
2.15.1
[PATCH net 2/3] net: mvneta: use proper rxq_number in loop on rx queues
From: Yelena Krivosheev
When adding the RX queue association with each CPU, a typo was made in
the mvneta_cleanup_rxqs() function. This patch fixes it.
[gregory.clem...@free-electrons.com: add commit log and fixes tag]
Cc: sta...@vger.kernel.org
Fixes: 2dcf75e2793c ("net: mvneta: Associate RX queues with each CPU")
Signed-off-by: Yelena Krivosheev
Tested-by: Dmitri Epshtein
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 16b2bfb2cf51..1e0835655c93 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -3015,7 +3015,7 @@ static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
{
int queue;
- for (queue = 0; queue < txq_number; queue++)
+ for (queue = 0; queue < rxq_number; queue++)
mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
}
--
2.15.1
[PATCH v2 net] net: mvpp2: Fix clock resource by adding an optional bus clock
On Armada 7K/8K we need to explicitly enable the bus clock. The bus clock
is optional because not all the SoCs need them but at least for Armada
7K/8K it is actually mandatory.
The binding documentation is updating accordingly.
Signed-off-by: Gregory CLEMENT
---
Changelog:
v1 -> v2:
- manage the -EPROBE_DEFER case
- fix typos in documentation
- remove useless test before clk_disable_unprepare()
Documentation/devicetree/bindings/net/marvell-pp2.txt | 10 ++
drivers/net/ethernet/marvell/mvpp2.c | 15 +++
2 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/marvell-pp2.txt
b/Documentation/devicetree/bindings/net/marvell-pp2.txt
index 7e2dad08a12e..1814fa13f6ab 100644
--- a/Documentation/devicetree/bindings/net/marvell-pp2.txt
+++ b/Documentation/devicetree/bindings/net/marvell-pp2.txt
@@ -21,8 +21,9 @@ Required properties:
- main controller clock (for both armada-375-pp2 and armada-7k-pp2)
- GOP clock (for both armada-375-pp2 and armada-7k-pp2)
- MG clock (only for armada-7k-pp2)
-- clock-names: names of used clocks, must be "pp_clk", "gop_clk" and
- "mg_clk" (the latter only for armada-7k-pp2).
+ - AXI clock (only for armada-7k-pp2)
+- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk"
+ and "axi_clk" (the 2 latter only for armada-7k-pp2).
The ethernet ports are represented by subnodes. At least one port is
required.
@@ -78,8 +79,9 @@ Example for marvell,armada-7k-pp2:
cpm_ethernet: ethernet@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x10>, <0x129000 0xb000>;
- clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>;
- clock-names = "pp_clk", "gop_clk", "gp_clk";
+ clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>,
+<&cpm_syscon0 1 5>, <&cpm_syscon0 1 18>;
+ clock-names = "pp_clk", "gop_clk", "gp_clk", "axi_clk";
eth0: eth0 {
interrupts = ,
diff --git a/drivers/net/ethernet/marvell/mvpp2.c
b/drivers/net/ethernet/marvell/mvpp2.c
index dd0ee2691c86..f2656112986b 100644
--- a/drivers/net/ethernet/marvell/mvpp2.c
+++ b/drivers/net/ethernet/marvell/mvpp2.c
@@ -792,6 +792,7 @@ struct mvpp2 {
struct clk *pp_clk;
struct clk *gop_clk;
struct clk *mg_clk;
+ struct clk *axi_clk;
/* List of pointers to port structures */
struct mvpp2_port **port_list;
@@ -7963,6 +7964,18 @@ static int mvpp2_probe(struct platform_device *pdev)
err = clk_prepare_enable(priv->mg_clk);
if (err < 0)
goto err_gop_clk;
+
+ priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk");
+ if (IS_ERR(priv->axi_clk)) {
+ err = PTR_ERR(priv->axi_clk);
+ if (err == -EPROBE_DEFER)
+ goto err_gop_clk;
+ priv->axi_clk = NULL;
+ } else {
+ err = clk_prepare_enable(priv->axi_clk);
+ if (err < 0)
+ goto err_gop_clk;
+ }
}
/* Get system's tclk rate */
@@ -8015,6 +8028,7 @@ static int mvpp2_probe(struct platform_device *pdev)
return 0;
err_mg_clk:
+ clk_disable_unprepare(priv->axi_clk);
if (priv->hw_version == MVPP22)
clk_disable_unprepare(priv->mg_clk);
err_gop_clk:
@@ -8052,6 +8066,7 @@ static int mvpp2_remove(struct platform_device *pdev)
aggr_txq->descs_dma);
}
+ clk_disable_unprepare(priv->axi_clk);
clk_disable_unprepare(priv->mg_clk);
clk_disable_unprepare(priv->pp_clk);
clk_disable_unprepare(priv->gop_clk);
--
2.14.1
Re: [PATCH net] net: mvpp2: Fix clock resource by adding an optional bus clock
Hi Thomas,
On jeu., sept. 28 2017, Thomas Petazzoni
wrote:
>> /* List of pointers to port structures */
>> struct mvpp2_port **port_list;
>> @@ -7963,6 +7964,16 @@ static int mvpp2_probe(struct platform_device *pdev)
>> err = clk_prepare_enable(priv->mg_clk);
>> if (err < 0)
>> goto err_gop_clk;
>> +
>> +priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk");
>> +if (IS_ERR(priv->axi_clk)) {
>> +err = PTR_ERR(priv->axi_clk);
>> +priv->axi_clk = NULL;
>
> You should handle -EPROBE_DEFER here. Indeed, if we have -EPROBE_DEFER,
> we shouldn't treat it as "the clock doesn't exist, so let's skip it and
> continue", but rather as "the clock exists, but isn't ready to use yet,
> let's try later".
You're totally right, I will send a v2 (I will also fix the other issue
you spotted).
Thanks,
Gregory
>
> Thanks!
>
> Thomas
> --
> Thomas Petazzoni, CTO, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
>
> ___
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
[PATCH net] net: mvpp2: Fix clock resource by adding an optional bus clock
On Armada 7K/8K we need to explicitly enable the bus clock. The bus clock
is optional because not all the SoCs need them but at least for Armada
7K/8K it is actually mandatory.
The binding documentation is updating accordingly.
Signed-off-by: Gregory CLEMENT
---
Documentation/devicetree/bindings/net/marvell-pp2.txt | 10 ++
drivers/net/ethernet/marvell/mvpp2.c | 15 +++
2 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/marvell-pp2.txt
b/Documentation/devicetree/bindings/net/marvell-pp2.txt
index 7e2dad08a12e..49e1be6bb6ba 100644
--- a/Documentation/devicetree/bindings/net/marvell-pp2.txt
+++ b/Documentation/devicetree/bindings/net/marvell-pp2.txt
@@ -21,8 +21,9 @@ Required properties:
- main controller clock (for both armada-375-pp2 and armada-7k-pp2)
- GOP clock (for both armada-375-pp2 and armada-7k-pp2)
- MG clock (only for armada-7k-pp2)
-- clock-names: names of used clocks, must be "pp_clk", "gop_clk" and
- "mg_clk" (the latter only for armada-7k-pp2).
+ - AXI clock (only for armada-7k-pp2)
+- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk"
+ and "axi"(the 2 latter only for armada-7k-pp2).
The ethernet ports are represented by subnodes. At least one port is
required.
@@ -78,8 +79,9 @@ Example for marvell,armada-7k-pp2:
cpm_ethernet: ethernet@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x10>, <0x129000 0xb000>;
- clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>;
- clock-names = "pp_clk", "gop_clk", "gp_clk";
+ clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>,
+ <&cpm_syscon0 1 5>, <&cpm_syscon0 1 18>;
+ clock-names = "pp_clk", "gop_clk", "gp_clk", "axi_clk";
eth0: eth0 {
interrupts = ,
diff --git a/drivers/net/ethernet/marvell/mvpp2.c
b/drivers/net/ethernet/marvell/mvpp2.c
index dd0ee2691c86..33b6791df2bb 100644
--- a/drivers/net/ethernet/marvell/mvpp2.c
+++ b/drivers/net/ethernet/marvell/mvpp2.c
@@ -792,6 +792,7 @@ struct mvpp2 {
struct clk *pp_clk;
struct clk *gop_clk;
struct clk *mg_clk;
+ struct clk *axi_clk;
/* List of pointers to port structures */
struct mvpp2_port **port_list;
@@ -7963,6 +7964,16 @@ static int mvpp2_probe(struct platform_device *pdev)
err = clk_prepare_enable(priv->mg_clk);
if (err < 0)
goto err_gop_clk;
+
+ priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk");
+ if (IS_ERR(priv->axi_clk)) {
+ err = PTR_ERR(priv->axi_clk);
+ priv->axi_clk = NULL;
+ } else {
+ err = clk_prepare_enable(priv->axi_clk);
+ if (err < 0)
+ goto err_gop_clk;
+ }
}
/* Get system's tclk rate */
@@ -8015,6 +8026,8 @@ static int mvpp2_probe(struct platform_device *pdev)
return 0;
err_mg_clk:
+ if (priv->axi_clk)
+ clk_disable_unprepare(priv->axi_clk);
if (priv->hw_version == MVPP22)
clk_disable_unprepare(priv->mg_clk);
err_gop_clk:
@@ -8052,6 +8065,8 @@ static int mvpp2_remove(struct platform_device *pdev)
aggr_txq->descs_dma);
}
+ if (priv->axi_clk)
+ clk_disable_unprepare(priv->axi_clk);
clk_disable_unprepare(priv->mg_clk);
clk_disable_unprepare(priv->pp_clk);
clk_disable_unprepare(priv->gop_clk);
--
2.14.1
Re: [PATCH 1/2] net: mvneta: remove bogus use of
Hi Rob,
On jeu., juil. 20 2017, Rob Herring wrote:
> On Thu, Jul 20, 2017 at 10:06 AM, Gregory CLEMENT
> wrote:
>> Hi Rob,
>>
>> On jeu., juil. 20 2017, Rob Herring wrote:
>>
>> (Adding Marcin in CC who wrote this part of code)
>>
>>> Nothing sets ever sets data, so it is always NULL. Remove it as this is
>>> the only user of data ptr in the whole kernel, and it is going to be
>>> removed from struct device_node.
>>
>> Actually the use of device_node.data ptr is not bogus and it is set in
>> mvneta_bm_probe:
>> http://elixir.free-electrons.com/linux/latest/source/drivers/net/ethernet/marvell/mvneta_bm.c#L433
>
> Indeed. Looks like some complicated kconfig logic, so I'd not been
> able to trigger a build failure nor did 0-day (so far).
>
>> Your patch will break the BM support on this driver. So if you need to
>> remove this data ptr, then you have to offer an alternative for it.
>
> How about something like this (WS damaged) patch:
I finally took time to test your patch. There was some missing part
which prevented it to be build, like including linux/of_platform.h, or
providing tub function when CONFIG_MVNETA_BM was not enable.
Also the fact that you still call mvneta_bm_port_init() even if bm_priv
was NULL was not really nice. So I proposed the following patch, that I
tested on a clearfog with and without CONFIG_MVNETA_BM enabled.
>From 03c4028bc1f52d3d214e8506d9f0f0d3985d Mon Sep 17 00:00:00 2001
From: Gregory CLEMENT
Date: Fri, 4 Aug 2017 17:18:38 +0200
Subject: [PATCH] net: mvneta: remove data pointer usage from device_node
structure
In order to be able to remove the data pointer from the device_node
structure. We have to modify the way the BM resources are shared between
the mvneta port.
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c| 18 --
drivers/net/ethernet/marvell/mvneta_bm.c | 13 +
drivers/net/ethernet/marvell/mvneta_bm.h | 8 ++--
3 files changed, 31 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 63b6147753fe..fd84447582f7 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -4295,12 +4295,16 @@ static int mvneta_probe(struct platform_device *pdev)
/* Obtain access to BM resources if enabled and already initialized */
bm_node = of_parse_phandle(dn, "buffer-manager", 0);
- if (bm_node && bm_node->data) {
- pp->bm_priv = bm_node->data;
- err = mvneta_bm_port_init(pdev, pp);
- if (err < 0) {
- dev_info(&pdev->dev, "use SW buffer management\n");
- pp->bm_priv = NULL;
+ if (bm_node) {
+ pp->bm_priv = mvneta_bm_get(bm_node);
+ if (pp->bm_priv) {
+ err = mvneta_bm_port_init(pdev, pp);
+ if (err < 0) {
+ dev_info(&pdev->dev,
+"use SW buffer management\n");
+ mvneta_bm_put(pp->bm_priv);
+ pp->bm_priv = NULL;
+ }
}
}
of_node_put(bm_node);
@@ -4369,6 +4373,7 @@ static int mvneta_probe(struct platform_device *pdev)
mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
1 << pp->id);
+ mvneta_bm_put(pp->bm_priv);
}
err_free_stats:
free_percpu(pp->stats);
@@ -4410,6 +4415,7 @@ static int mvneta_remove(struct platform_device *pdev)
mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
1 << pp->id);
+ mvneta_bm_put(pp->bm_priv);
}
return 0;
diff --git a/drivers/net/ethernet/marvell/mvneta_bm.c
b/drivers/net/ethernet/marvell/mvneta_bm.c
index 466939f8f0cf..01e3152e76c8 100644
--- a/drivers/net/ethernet/marvell/mvneta_bm.c
+++ b/drivers/net/ethernet/marvell/mvneta_bm.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -392,6 +393,18 @@ static void mvneta_bm_put_sram(struct mvneta_bm *priv)
MVNETA_BM_BPPI_SIZE);
}
+struct mvneta_bm *mvneta_bm_get(struct device_node *node)
+{
+ struct platform_device *pdev = of_find_device_by_node(node);
+
+ return pdev ? platform_get_drvdata(pdev) : NULL;
+}
+
+void mvneta_bm_put(struct mvneta_bm *priv)
+{
+ platfo
Re: [PATCH 1/2] net: mvneta: remove bogus use of
Hi Rob,
On jeu., juil. 20 2017, Rob Herring wrote:
(Adding Marcin in CC who wrote this part of code)
> Nothing sets ever sets data, so it is always NULL. Remove it as this is
> the only user of data ptr in the whole kernel, and it is going to be
> removed from struct device_node.
Actually the use of device_node.data ptr is not bogus and it is set in
mvneta_bm_probe:
http://elixir.free-electrons.com/linux/latest/source/drivers/net/ethernet/marvell/mvneta_bm.c#L433
Your patch will break the BM support on this driver. So if you need to
remove this data ptr, then you have to offer an alternative for it.
Thanks,
Gregory
>
> Cc: Thomas Petazzoni
> Signed-off-by: Rob Herring
> ---
> Probably there's a better fix here to actually enable the h/w buffer
> manager.
>
> I intend to take this thru the DT tree as patch 2 is dependent on this.
>
> Rob
>
> drivers/net/ethernet/marvell/mvneta.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/ethernet/marvell/mvneta.c
> b/drivers/net/ethernet/marvell/mvneta.c
> index 0aab74c2a209..5624f4b49f9d 100644
> --- a/drivers/net/ethernet/marvell/mvneta.c
> +++ b/drivers/net/ethernet/marvell/mvneta.c
> @@ -4296,8 +4296,8 @@ static int mvneta_probe(struct platform_device *pdev)
>
> /* Obtain access to BM resources if enabled and already initialized */
> bm_node = of_parse_phandle(dn, "buffer-manager", 0);
> - if (bm_node && bm_node->data) {
> - pp->bm_priv = bm_node->data;
> + if (bm_node) {
> + pp->bm_priv = NULL;
> err = mvneta_bm_port_init(pdev, pp);
> if (err < 0) {
> dev_info(&pdev->dev, "use SW buffer management\n");
> --
> 2.11.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH net-next v5 11/11] arm64: marvell: dts: add xmdio nodes for 7k/8k
Hi Antoine,
On jeu., juin 15 2017, Antoine Tenart
wrote:
> Add the description of the xMDIO bus for the Marvell Armada 7k and
> Marvell Armada 8k; for both CP110 slave and master. This bus is found
> on Marvell Ethernet controllers and provides an interface with the
> xMDIO bus.
>
> Signed-off-by: Antoine Tenart
Applied on mvebu/dt64
Thanks,
Gregory
> ---
>
> @Dave: this patch should go through the mvebu tree as asked by Gregory,
> thanks!
>
> arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 8
> arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 8
> 2 files changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> index 576e825585c9..8b512b75aea9 100644
> --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> @@ -97,6 +97,14 @@
> clocks = <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>;
> };
>
> + cpm_xmdio: mdio@12a600 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "marvell,xmdio";
> + reg = <0x12a600 0x10>;
> + status = "disabled";
> + };
> +
> cpm_syscon0: system-controller@44 {
> compatible = "marvell,cp110-system-controller0",
>"syscon";
> diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> index 797208a11f9d..bd0c0e03edd2 100644
> --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> @@ -104,6 +104,14 @@
> clocks = <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
> };
>
> + cps_xmdio: mdio@12a600 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "marvell,xmdio";
> + reg = <0x12a600 0x10>;
> + status = "disabled";
> + };
> +
> cps_syscon0: system-controller@44 {
> compatible = "marvell,cp110-system-controller0",
>"syscon";
> --
> 2.9.4
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH 9/9] arm64: marvell: dts: add xmdio nodes for 7k/8k
Hi Antoine,
On jeu., juin 08 2017, Antoine Tenart
wrote:
> Hi Gregory,
>
> On Wed, Jun 07, 2017 at 10:38:10AM +0200, Antoine Tenart wrote:
>> diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
>> b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
>> index 2a99ff8fca2a..594356243ddb 100644
>> --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
>> +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
>> @@ -103,6 +103,13 @@
>> clocks = <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
>> };
>>
>> +cps_xmdio: mdio@12a600 {
>> +#address-cells = <1>;
>> +#size-cells = <0>;
>> +compatible = "marvell,xmdio";
>> +reg = <0x12a600 0x10>;
>> +};
>> +
>
> Russell pointed out on IRC the mdio/xmdio interfaces aren't wired to
> anything on the mcbin. We could either disable these interfaces by
> default, or add explicit disables in the mcbin device tree.
>
> What's your thoughts on this?
I prefer that we disable it by default and only enable it on the boards
using it.
Thanks,
Gregory
>
> Thanks!
> Antoine
>
> --
> Antoine Ténart, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH 9/9] arm64: marvell: dts: add xmdio nodes for 7k/8k
Hi Dave,
On mer., juin 07 2017, Antoine Tenart
wrote:
> Add the description of the xMDIO bus for the Marvell Armada 7k and
> Marvell Armada 8k; for both CP110 slave and master. This bus is found
> on Marvell Ethernet controllers and provides an interface with the
> xMDIO bus.
>
If you agrees with this series please don't apply this patch. I will
take care of it. We have many changes in the dt directory for the next
release and I want that all the change are in the same place to take
care of the merge conflict.
Thanks,
Gregory
> Signed-off-by: Antoine Tenart
> ---
> arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 7 +++
> arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 7 +++
> 2 files changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> index 037ed30d75a7..95953743455e 100644
> --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> @@ -98,6 +98,13 @@
> clocks = <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>;
> };
>
> + cpm_xmdio: mdio@12a600 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "marvell,xmdio";
> + reg = <0x12a600 0x10>;
> + };
> +
> cpm_icu: interrupt-controller@1e {
> compatible = "marvell,cp110-icu";
> reg = <0x1e 0x10>;
> diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> index 2a99ff8fca2a..594356243ddb 100644
> --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> @@ -103,6 +103,13 @@
> clocks = <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
> };
>
> + cps_xmdio: mdio@12a600 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "marvell,xmdio";
> + reg = <0x12a600 0x10>;
> + };
> +
> cps_icu: interrupt-controller@1e {
> compatible = "marvell,cp110-icu";
> reg = <0x1e 0x10>;
> --
> 2.9.4
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v2 0/6] Updates for Marvell Switch SoCs
Hi Chris, On jeu., févr. 16 2017, Chris Packham wrote: > Shortly after I posted my last series I got access to a more recent > Marvell SDK which had some device tree support for the switch SoCs I'd > been wanting. It was still based on an older kernel but it was a huge > improvement over what came before. > > Patch 1/6 is a typo I noticed after my initial series was applied. > > Patch 2/6 is a bit of a cleanup. I did initially struggle with how to > access individual parts of the DFX block as well as retaining a handle on > the entire thing for the switch driver to use. > > Patch 3/6 is a re-jig of the dtsi files which is needed by 5/6. This is > required because I need to use the coreclk label on a different node. It > also means I don't have to disable nodes for blocks that only exist on > the Armada-XP. > > Patch 4/6, 5/6 are split from the previous versions. > > Patch 6/6 is the device tree portion of a change already in clk-next. I applied patches 2, 3 and 6 on mvebu/dt with the acked-by from Rob when he gave it. Patch 1 is already part of 4.11-rc1. For patch 4 and 5 I understand that either we don't need it or it should be a updated version so I skipped them. Thanks, Gregory > > Chris Packham (6): > ARM: dts: Fix typo in armada-xp-98dx4251 > Changes in v2 > - new > Changes in v3: > - none > ARM: dts: armada-xp-98dx3236: combine dfx server nodes > Changes in v2: > - none > Changes in v3: > - none > ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236 > Changes in v2: > - Update root compatible strings in armada-xp-98dx3336.dtsi, > armada-xp-98dx4251.dtsi, armada-xp-db-dxbc2.dts and > armada-xp-db-xc3-24g4xg.dts > Changes in v3: > - none > ARM: dts: mvebu: Add binding for mv98dx3236-soc-id > Changes in v3: > - new, split from driver > ARM: mvebu: Add driver for mv98dx3236-soc-id > Changes in v2: > - none > Changes in v3: > - split from dts changes > ARM: dts: mvebu: Move mv98dx3236 clock bindings > Changes in v2: > - New. Split out from "clk: mvebu: Expand mv98dx3236-core-clock support" > Changes in v3: > - Clarify why the old location was wrong (but worked). > > > .../bindings/arm/marvell/mv98dx3236-soc-id.txt | 14 ++ > .../devicetree/bindings/clock/mvebu-core-clock.txt | 7 + > .../bindings/clock/mvebu-gated-clock.txt | 11 ++ > .../devicetree/bindings/net/marvell,prestera.txt | 13 +- > arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 213 > - > arch/arm/boot/dts/armada-xp-98dx3336.dtsi | 2 +- > arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 2 +- > arch/arm/boot/dts/armada-xp-db-dxbc2.dts | 2 +- > arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 2 +- > arch/arm/mach-mvebu/mvebu-soc-id.c | 43 - > 10 files changed, 242 insertions(+), 67 deletions(-) > create mode 100644 > Documentation/devicetree/bindings/arm/marvell/mv98dx3236-soc-id.txt > > -- > 2.11.0.24.ge6920cf -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH net-next v3 0/4] net: mvneta: improve rx/tx performance
Hi Jisheng, On lun., févr. 20 2017, Jisheng Zhang wrote: > In hot code path such as mvneta_rx_swbm(), we access fields of rx_desc > and tx_desc. These DMA descs are allocated by dma_alloc_coherent, they > are uncacheable if the device isn't cache coherent, reading from > uncached memory is fairly slow. > > patch1 reuses the read out status to getting status field of rx_desc > again. > > patch2 avoids getting buf_phys_addr from rx_desc again in > mvneta_rx_hwbm by reusing the phys_addr variable. > > patch3 avoids reading from tx_desc as much as possible by store what > we need in local variable. > > We get the following performance data on Marvell BG4CT Platforms > (tested with iperf): > > before the patch: > sending 1GB in mvneta_tx()(disabled TSO) costs 793553760ns > > after the patch: > sending 1GB in mvneta_tx()(disabled TSO) costs 719953800ns > > we saved 9.2% time. > > patch4 uses cacheable memory to store the rx buffer DMA address. > > We get the following performance data on Marvell BG4CT Platforms > (tested with iperf): > > before the patch: > recving 1GB in mvneta_rx_swbm() costs 1492659600 ns > > after the patch: > recving 1GB in mvneta_rx_swbm() costs 1421565640 ns Could you explain who you get this number? receiving 1GB in 1.42 second means having a bandwidth of 8/1.42=5.63 Gb/s, that means that you are using at least a 10Gb interface. When I used iperf I didn't have this kind of granularity: iperf -c 192.168.10.1 -n 1024M Client connecting to 192.168.10.19, TCP port 5001 TCP window size: 43.8 KByte (default) [ 3] local 192.168.10.28 port 53086 connected with 192.168.10.1 port 5001 [ ID] Interval Transfer Bandwidth [ 3] 0.0- 9.1 sec 1.00 GBytes 942 Mbits/sec Also without HWBM enabled (so with the same configuration of your test), I didn't noticed any improvement with the patch set applied. But at least I didn't see any regression with or without HWBM. Gregory > > We saved 4.76% time. > > Basically, patch1 and patch4 do what Arnd mentioned in [1]. > > Hi Arnd, > > I added "Suggested-by you" tag, I hope you don't mind ;) > > Thanks > > [1] https://www.spinics.net/lists/netdev/msg405889.html > > Since v2: > - add Gregory's ack to patch1 > - only get rx buffer DMA address from cacheable memory for mvneta_rx_swbm() > - add patch 2 to read rx_desc->buf_phys_addr once in mvneta_rx_hwbm() > - add patch 3 to avoid reading from tx_desc as much as possible > > Since v1: > - correct the performance data typo > > > Jisheng Zhang (4): > net: mvneta: avoid getting status from rx_desc as much as possible > net: mvneta: avoid getting buf_phys_addr from rx_desc again > net: mvneta: avoid reading from tx_desc as much as possible > net: mvneta: Use cacheable memory to store the rx buffer DMA address > > drivers/net/ethernet/marvell/mvneta.c | 80 > +++ > 1 file changed, 43 insertions(+), 37 deletions(-) > > -- > 2.11.0 > -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH net-next v2 2/2] net: mvneta: Use cacheable memory to store the rx buffer DMA address
Hi Thomas, On ven., févr. 17 2017, Thomas Petazzoni wrote: > Does not make sense, because it's not the SW that refills the RX > descriptors with the address of the RX buffers. It's done by the HW. > > With HWBM, I believe you have no choice but to read the physical > address from the RX descriptor. But you can probably optimize things a > little bit by reading it only once, and then storing it into a > cacheable variable. > > So maybe: > > - For SWBM, use the strategy proposed by Jisheng > - For HWBM, at the beginning of the RX completion path, read once the >rx_desc->buf_phys_addr, and store it in rxq->buf_dma_addr[index] For the HWBM path storing rx_desc->buf_phys_addr in rxq->buf_dma_addr[index] is not useful as we only use it in a single function. But a quick improvement could be to use the phys_addr variable. Indeed we store the value of rx_desc->buf_phys_addr in it and we never used it, instead we always use rx_desc->buf_phys_addr. Gregory > > Of course that's just a very rough proposal. I've been looking mainly > at mvpp2 lately, and I'm not sure I still remember how mvneta works in > the details. > > Best regards, > > Thomas > -- > Thomas Petazzoni, CTO, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH net-next v2 1/2] net: mvneta: avoid getting status from rx_desc as much as possible
Hi Jisheng,
On ven., févr. 17 2017, Jisheng Zhang wrote:
> In hot code path mvneta_rx_hwbm(), the rx_desc->status is read twice.
> The rx_desc is allocated by dma_alloc_coherent, it's uncacheable if
> the device isn't cache-coherent, reading from uncached memory is
> fairly slow. So reuse the read out rx_status to avoid the second
> reading from uncached memory.
>
> Signed-off-by: Jisheng Zhang
> Suggested-by: Arnd Bergmann
This one is OK and I didn't see a regression:
Tested-by: Gregory CLEMENT
Gregory
> ---
> drivers/net/ethernet/marvell/mvneta.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/net/ethernet/marvell/mvneta.c
> b/drivers/net/ethernet/marvell/mvneta.c
> index 61dd4462411c..06df72b8da85 100644
> --- a/drivers/net/ethernet/marvell/mvneta.c
> +++ b/drivers/net/ethernet/marvell/mvneta.c
> @@ -313,8 +313,8 @@
> ((addr >= txq->tso_hdrs_phys) && \
>(addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
>
> -#define MVNETA_RX_GET_BM_POOL_ID(rxd) \
> - (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
> +#define MVNETA_RX_GET_BM_POOL_ID(status) \
> + (((status) & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
>
> struct mvneta_statistic {
> unsigned short offset;
> @@ -1900,7 +1900,7 @@ static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
> for (i = 0; i < rx_done; i++) {
> struct mvneta_rx_desc *rx_desc =
> mvneta_rxq_next_desc_get(rxq);
> - u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
> + u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc->status);
> struct mvneta_bm_pool *bm_pool;
>
> bm_pool = &pp->bm_priv->bm_pools[pool_id];
> @@ -2075,7 +2075,7 @@ static int mvneta_rx_hwbm(struct mvneta_port *pp, int
> rx_todo,
> rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
> data = (u8 *)(uintptr_t)rx_desc->buf_cookie;
> phys_addr = rx_desc->buf_phys_addr;
> - pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
> + pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_status);
> bm_pool = &pp->bm_priv->bm_pools[pool_id];
>
> if (!mvneta_rxq_desc_is_first_last(rx_status) ||
> --
> 2.11.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH net-next v2 2/2] net: mvneta: Use cacheable memory to store the rx buffer DMA address
@@ -2082,8 +2087,7 @@ static int mvneta_rx_hwbm(struct mvneta_port *pp, int
> rx_todo,
> (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
> err_drop_frame_ret_pool:
> /* Return the buffer to the pool */
> - mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
> - rx_desc->buf_phys_addr);
> + mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, phys_addr);
> err_drop_frame:
> dev->stats.rx_errors++;
> mvneta_rx_error(pp, rx_desc);
> @@ -2098,7 +2102,7 @@ static int mvneta_rx_hwbm(struct mvneta_port *pp, int
> rx_todo,
> goto err_drop_frame_ret_pool;
>
> dma_sync_single_range_for_cpu(dev->dev.parent,
> - rx_desc->buf_phys_addr,
> + phys_addr,
> MVNETA_MH_SIZE +
> NET_SKB_PAD,
> rx_bytes,
> DMA_FROM_DEVICE);
> @@ -2114,8 +2118,7 @@ static int mvneta_rx_hwbm(struct mvneta_port *pp, int
> rx_todo,
> rcvd_bytes += rx_bytes;
>
> /* Return the buffer to the pool */
> - mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
> - rx_desc->buf_phys_addr);
> + mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, phys_addr);
>
> /* leave the descriptor and buffer untouched */
> continue;
> @@ -4019,7 +4022,10 @@ static int mvneta_init(struct device *dev, struct
> mvneta_port *pp)
> rxq->buf_virt_addr = devm_kmalloc(pp->dev->dev.parent,
> rxq->size * sizeof(void *),
> GFP_KERNEL);
> - if (!rxq->buf_virt_addr)
> + rxq->buf_dma_addr = devm_kmalloc(pp->dev->dev.parent,
> + rxq->size * sizeof(dma_addr_t),
> + GFP_KERNEL);
> + if (!rxq->buf_virt_addr || !rxq->buf_dma_addr)
> return -ENOMEM;
> }
>
> --
> 2.11.0
>
>
> ___
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH net-next v2 0/2] net: mvneta: improve rx performance
Hi Jisheng, On ven., févr. 17 2017, Jisheng Zhang wrote: > In hot code path such as mvneta_rx_hwbm() and mvneta_rx_swbm(), we may > access fields of rx_desc. The rx_desc is allocated by > dma_alloc_coherent, it's uncacheable if the device isn't cache > coherent, reading from uncached memory is fairly slow. Did you test it with HWBM support? I am not sure ti will work in this case. Gregory > > patch1 reuses the read out status to getting status field of rx_desc > again. > > patch2 uses cacheable memory to store the rx buffer DMA address. > > We get the following performance data on Marvell BG4CT Platforms > (tested with iperf): > > before the patch: > recving 1GB in mvneta_rx_swbm() costs 149265960 ns > > after the patch: > recving 1GB in mvneta_rx_swbm() costs 1421565640 ns > > We saved 4.76% time. > > RFC: can we do similar modification for tx? If yes, I can prepare a v2. > > > Basically, these two patches do what Arnd mentioned in [1]. > > Hi Arnd, > > I added "Suggested-by you" tag, I hope you don't mind ;) > > Thanks > > [1] https://www.spinics.net/lists/netdev/msg405889.html > > Since v1: > - correct the performance data typo > > Jisheng Zhang (2): > net: mvneta: avoid getting status from rx_desc as much as possible > net: mvneta: Use cacheable memory to store the rx buffer DMA address > > drivers/net/ethernet/marvell/mvneta.c | 36 > --- > 1 file changed, 21 insertions(+), 15 deletions(-) > > -- > 2.11.0 > > > _______ > linux-arm-kernel mailing list > linux-arm-ker...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
[PATCH net-next v7 0/3] Add support for the ethernet switch on the ESPRESSObin
Hi, This set of patches adds support for the Marvell Ethernet Topaz switch family (88E6141/88E6341) which is found on the ESPRESSObin. With this series the network is usable on this board. As usual, I rebased the series on the very last net-next/master. In this series there is no temperature support which need some patches form Andrew Lunn. As soon as Andrew Lunn will post the needed patch I will send a patch to enable the temperature support. Thanks, Gregory Changelog: v6 -> v7: - rebased on net-next/master (5b8784aaf29b) - Fixed the wrong age time coeff from 15s to 3.75s. - Remove support for temperature sensor v5 -> v6: - rebased on net-next/master (d140199af510) - Fix the redundant check on mv88e6xxx_6341_family (reported by Julia Lawall) - Add support for the 88E6141 - Move support for temperature sensor in the phy part Gregory CLEMENT (2): net: dsa: mv88e6xxx: Add support for ethernet switch 88E6341 net: dsa: mv88e6xxx: Add support for ethernet switch 88E6141 Romain Perier (1): net: dsa: mv88e6xxx: Don't forbid MDIO I/Os for PHY addr >= num_of_ports drivers/net/dsa/mv88e6xxx/chip.c | 102 --- drivers/net/dsa/mv88e6xxx/mv88e6xxx.h | 21 +- 2 files changed, 113 insertions(+), 10 deletions(-) base-commit: 334c367fd5cea7a9493c3026f7e6195ebab3d7b9 -- git-series 0.9.1
[PATCH net-next v7 2/3] net: dsa: mv88e6xxx: Add support for ethernet switch 88E6341
The Marvell 88E6341 device is single-chip, 6-port Ethernet switch with
four integrated 10/100/1000Mbps Ethernet transceivers and one high speed
SerDes interfaces. It is partially compatible with switches of family
88E6352 and switches of family 88E6390.
This commit adds an initial support for this switch by describing its
capabilities to the driver and introducing a new family.
Signed-off-by: Gregory CLEMENT
---
drivers/net/dsa/mv88e6xxx/chip.c | 54 ++--
drivers/net/dsa/mv88e6xxx/mv88e6xxx.h | 19 +-
2 files changed, 69 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 1344dad21f46..6a583527917d 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -702,6 +702,11 @@ static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip
*chip)
return chip->info->family == MV88E6XXX_FAMILY_6320;
}
+static bool mv88e6xxx_6341_family(struct mv88e6xxx_chip *chip)
+{
+ return chip->info->family == MV88E6XXX_FAMILY_6341;
+}
+
static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
{
return chip->info->family == MV88E6XXX_FAMILY_6351;
@@ -1726,7 +1731,8 @@ static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip
*chip, u16 vid,
: GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
- mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
+ mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip) ||
+ mv88e6xxx_6341_family(chip)) {
struct mv88e6xxx_vtu_entry vstp;
/* Adding a VTU entry requires a valid STU entry. As VSTP is not
@@ -2577,7 +2583,7 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip
*chip, int port)
if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
- mv88e6xxx_6185_family(chip))
+ mv88e6xxx_6185_family(chip) || mv88e6xxx_6341_family(chip))
reg = PORT_CONTROL_2_MAP_DA;
if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
@@ -2631,7 +2637,7 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip
*chip, int port)
if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
- mv88e6xxx_6320_family(chip)) {
+ mv88e6xxx_6320_family(chip) || mv88e6xxx_6341_family(chip)) {
/* Port ATU control: disable limiting the number of
* address database entries that this port is allowed
* to use.
@@ -3650,6 +3656,34 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
.reset = mv88e6352_g1_reset,
};
+static const struct mv88e6xxx_ops mv88e6341_ops = {
+ /* MV88E6XXX_FAMILY_6341 */
+ .get_eeprom = mv88e6xxx_g2_get_eeprom8,
+ .set_eeprom = mv88e6xxx_g2_set_eeprom8,
+ .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
+ .phy_read = mv88e6xxx_g2_smi_phy_read,
+ .phy_write = mv88e6xxx_g2_smi_phy_write,
+ .port_set_link = mv88e6xxx_port_set_link,
+ .port_set_duplex = mv88e6xxx_port_set_duplex,
+ .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
+ .port_set_speed = mv88e6390_port_set_speed,
+ .port_tag_remap = mv88e6095_port_tag_remap,
+ .port_set_frame_mode = mv88e6351_port_set_frame_mode,
+ .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
+ .port_set_ether_type = mv88e6351_port_set_ether_type,
+ .port_jumbo_config = mv88e6165_port_jumbo_config,
+ .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_pause_config = mv88e6097_port_pause_config,
+ .stats_snapshot = mv88e6390_g1_stats_snapshot,
+ .stats_get_sset_count = mv88e6320_stats_get_sset_count,
+ .stats_get_strings = mv88e6320_stats_get_strings,
+ .stats_get_stats = mv88e6390_stats_get_stats,
+ .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
+ .g1_set_egress_port = mv88e6390_g1_set_egress_port,
+ .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
+ .reset = mv88e6352_g1_reset,
+};
+
static const struct mv88e6xxx_ops mv88e6390_ops = {
/* MV88E6XXX_FAMILY_6390 */
.get_eeprom = mv88e6xxx_g2_get_eeprom8,
@@ -4037,6 +4071,20 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
.ops = &mv88e6321_ops,
},
+ [MV88E6341] = {
+ .prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
+ .family = MV88E6XXX_FAMILY_6341,
+ .name = "Marvell 88E6341",
+ .num_databases = 4096,
+ .num_ports = 6,
+ .port_base_addr = 0x10,
+
[PATCH net-next v7 3/3] net: dsa: mv88e6xxx: Add support for ethernet switch 88E6141
The Marvell 88E6341 device is single-chip, 6-port Ethernet switch with
four integrated 10/100/1000Mbps Ethernet transceivers and one high speed
SerDes interfaces.
It belongs to the Topaz family and unlike the 88E6341 it does not have
a TCAM.
Signed-off-by: Gregory CLEMENT
---
drivers/net/dsa/mv88e6xxx/chip.c | 42 -
drivers/net/dsa/mv88e6xxx/mv88e6xxx.h | 2 +-
2 files changed, 44 insertions(+)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 6a583527917d..bf385377a461 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -3656,6 +3656,34 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
.reset = mv88e6352_g1_reset,
};
+static const struct mv88e6xxx_ops mv88e6141_ops = {
+ /* MV88E6XXX_FAMILY_6341 */
+ .get_eeprom = mv88e6xxx_g2_get_eeprom8,
+ .set_eeprom = mv88e6xxx_g2_set_eeprom8,
+ .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
+ .phy_read = mv88e6xxx_g2_smi_phy_read,
+ .phy_write = mv88e6xxx_g2_smi_phy_write,
+ .port_set_link = mv88e6xxx_port_set_link,
+ .port_set_duplex = mv88e6xxx_port_set_duplex,
+ .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
+ .port_set_speed = mv88e6390_port_set_speed,
+ .port_tag_remap = mv88e6095_port_tag_remap,
+ .port_set_frame_mode = mv88e6351_port_set_frame_mode,
+ .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
+ .port_set_ether_type = mv88e6351_port_set_ether_type,
+ .port_jumbo_config = mv88e6165_port_jumbo_config,
+ .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_pause_config = mv88e6097_port_pause_config,
+ .stats_snapshot = mv88e6390_g1_stats_snapshot,
+ .stats_get_sset_count = mv88e6320_stats_get_sset_count,
+ .stats_get_strings = mv88e6320_stats_get_strings,
+ .stats_get_stats = mv88e6390_stats_get_stats,
+ .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
+ .g1_set_egress_port = mv88e6390_g1_set_egress_port,
+ .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
+ .reset = mv88e6352_g1_reset,
+};
+
static const struct mv88e6xxx_ops mv88e6341_ops = {
/* MV88E6XXX_FAMILY_6341 */
.get_eeprom = mv88e6xxx_g2_get_eeprom8,
@@ -4071,6 +4099,20 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
.ops = &mv88e6321_ops,
},
+ [MV88E6141] = {
+ .prod_num = PORT_SWITCH_ID_PROD_NUM_6141,
+ .family = MV88E6XXX_FAMILY_6341,
+ .name = "Marvell 88E6341",
+ .num_databases = 4096,
+ .num_ports = 6,
+ .port_base_addr = 0x10,
+ .global1_addr = 0x1b,
+ .age_time_coeff = 3750,
+ .tag_protocol = DSA_TAG_PROTO_EDSA,
+ .flags = MV88E6XXX_FLAGS_FAMILY_6341,
+ .ops = &mv88e6141_ops,
+ },
+
[MV88E6341] = {
.prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
.family = MV88E6XXX_FAMILY_6341,
diff --git a/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h
b/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h
index 76837d2022bb..9c5c0472b211 100644
--- a/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h
+++ b/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h
@@ -87,6 +87,7 @@
#define PORT_SWITCH_ID_PROD_NUM_6131 0x106
#define PORT_SWITCH_ID_PROD_NUM_6320 0x115
#define PORT_SWITCH_ID_PROD_NUM_6123 0x121
+#define PORT_SWITCH_ID_PROD_NUM_6141 0x340
#define PORT_SWITCH_ID_PROD_NUM_6161 0x161
#define PORT_SWITCH_ID_PROD_NUM_6165 0x165
#define PORT_SWITCH_ID_PROD_NUM_6171 0x171
@@ -421,6 +422,7 @@ enum mv88e6xxx_model {
MV88E6097,
MV88E6123,
MV88E6131,
+ MV88E6141,
MV88E6161,
MV88E6165,
MV88E6171,
--
git-series 0.9.1
[PATCH net-next v7 1/3] net: dsa: mv88e6xxx: Don't forbid MDIO I/Os for PHY addr >= num_of_ports
From: Romain Perier Some Marvell ethernet switches have internal ethernet transceivers with hardcoded phy addresses. These addresses can be greater than the number of ports or its value might be different than the associated port number. This is for example the case for MV88E6341 that has 6 ports and internal Port 1 to Port4 PHYs mapped at SMI addresses from 0x11 to 0x14. This commits fixes the issue by removing the condition in MDIO callbacks. Signed-off-by: Romain Perier Reviewed-by: Andrew Lunn Reviewed-by: Vivien Didelot Signed-off-by: Gregory CLEMENT --- drivers/net/dsa/mv88e6xxx/chip.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 84cba32443de..1344dad21f46 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -2917,9 +2917,6 @@ static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) u16 val; int err; - if (phy >= mv88e6xxx_num_ports(chip)) - return 0x; - if (!chip->info->ops->phy_read) return -EOPNOTSUPP; @@ -2936,9 +2933,6 @@ static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) struct mv88e6xxx_chip *chip = mdio_bus->chip; int err; - if (phy >= mv88e6xxx_num_ports(chip)) - return 0x; - if (!chip->info->ops->phy_write) return -EOPNOTSUPP; -- git-series 0.9.1
Re: [PATCH v6 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs
include "armada-xp-98dx3236.dtsi"
> +
> +/ {
> + model = "Marvell 98DX3336 SoC";
> + compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236",
> "marvell,armadaxp", "marvell,armada-370-xp";
> +
> + cpus {
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "marvell,sheeva-v7";
> + reg = <1>;
> + clocks = <&cpuclk 1>;
> + clock-latency = <100>;
> + };
> + };
> +
> + soc {
> + internal-regs {
> + resume@20980 {
> + compatible = "marvell,98dx3336-resume-ctrl";
> + reg = <0x20980 0x10>;
> + };
> + };
> + };
> +};
> +
> +&pp0 {
> + compatible = "marvell,prestera-98dx3336";
> +};
> diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
> b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
> new file mode 100644
> index ..4b0533a4ccb7
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
> @@ -0,0 +1,90 @@
> +/*
> + * Device Tree Include file for Marvell 98dx4521 family SoC
> + *
> + * Copyright (C) 2016 Allied Telesis Labs
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Contains definitions specific to the 98dx4521 SoC that are not
> + * common to all Armada XP SoCs.
> + */
> +
> +#include "armada-xp-98dx3236.dtsi"
> +
> +/ {
> + model = "Marvell 98DX4251 SoC";
> + compatible = "marvell,armadaxp-98dx4521", "marvell,armadaxp-98dx3236",
> "marvell,armadaxp", "marvell,armada-370-xp";
> +
> + cpus {
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "marvell,sheeva-v7";
> + reg = <1>;
> + clocks = <&cpuclk 1>;
> + clock-latency = <100>;
> + };
> + };
> +
> + soc {
> + internal-regs {
> + resume@20980 {
> + compatible = "marvell,98dx3336-resume-ctrl";
> + reg = <0x20980 0x10>;
> + };
> + };
> + };
> +};
> +
> +&sdio {
> + status = "okay";
> +};
> +
> +&pinctrl {
> + compatible = "marvell,98dx4251-pinctrl";
> +
> + sdio_pins: sdio-pins {
> + marvell,pins = "mpp5", "mpp6", "mpp7",
> +"mpp8", "mpp9", "mpp10";
> + marvell,function = "sd0";
> + };
> +};
> +
> +&pp0 {
> + compatible = "marvell,prestera-98dx4251";
> +};
> --
> 2.11.0.24.ge6920cf
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH net-next 0/2] Work around missing PHY prodcut ID in mv88e6390
Hi Andrew, On mer., janv. 25 2017, David Miller wrote: > From: Andrew Lunn > Date: Wed, 25 Jan 2017 02:55:12 +0100 > >> The internal PHYs of the MV88E6390 have a Marvell OUI, but the product >> ID is zero. Work around this by trapping reads to the ID, and if it is >> zero, return the MV88E6390 family ID. > > Because of the ID masking issue, I am expecting a respin of this. Do you think you will send a new version soon? It is the last missing part to send my v7 for the Topaz support on the EspressoBin. Thanks, Gregory -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCHv3 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs
tware, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Contains definitions specific to the 98dx3336 SoC that are not
> + * common to all Armada XP SoCs.
> + */
> +
> +#include "armada-xp-98dx3236.dtsi"
> +
> +/ {
> + model = "Marvell 98DX3336 SoC";
> + compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236",
> "marvell,armadaxp", "marvell,armada-370-xp";
> +
> + cpus {
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "marvell,sheeva-v7";
> + reg = <1>;
> + clocks = <&cpuclk 1>;
> + clock-latency = <100>;
> + };
> + };
> +
> + soc {
> + internal-regs {
Why the following node is not part of the dtsi?
Gregory
> + resume@20980 {
> + compatible = "marvell,98dx3336-resume-ctrl";
> + reg = <0x20980 0x10>;
> + };
> + };
> + };
> +};
> +
> +&pp0 {
> + compatible = "marvell,prestera-98dx3336";
> +};
> diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
> b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
> new file mode 100644
> index ..446e6e65ec59
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
> @@ -0,0 +1,90 @@
> +/*
> + * Device Tree Include file for Marvell 98dx4521 family SoC
> + *
> + * Copyright (C) 2016 Allied Telesis Labs
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Contains definitions specific to the 98dx4521 SoC that are not
> + * common to all Armada XP SoCs.
> + */
> +
> +#include "armada-xp-98dx3236.dtsi"
> +
> +/ {
> + model = "Marvell 98DX4251 SoC";
> + compatible = "marvell,armadaxp-98dx4521", "marvell,armadaxp-98dx3236",
> "marvell,armadaxp", "marvell,armada-370-xp";
> +
> + cpus {
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "marvell,sheeva-v7";
> + reg = <1>;
> + clocks = <&cpuclk 1>;
> + clock-latency = <100>;
> + };
> + };
> +
> + soc {
> + internal-regs {
> + resume@20980 {
> + compatible = "marvell,98dx3336-resume-ctrl";
> + reg = <0x20980 0x10>;
> + };
> + };
> + };
> +};
> +
> +&sdio {
> + status = "okay";
> +};
> +
> +&pinctrl {
> + compatible = "marvell,98dx4251-pinctrl";
> +
> + sdio_pins: sdio-pins {
> + marvell,pins = "mpp5", "mpp6", "mpp7",
> +"mpp8", "mpp9", "mpp10";
> + marvell,function = "sd0";
> + };
> +};
> +
> +&pp0 {
> + compatible = "marvell,prestera-98dx4251";
> +};
> --
> 2.11.0.24.ge6920cf
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH net-next 1/2] net: dsa: mv88e6xxx: Workaround missing PHY ID on mv88e6390
Hi Andrew,
> - return mv88e6xxx_g2_read(chip, GLOBAL2_SMI_PHY_DATA, val);
> + err = mv88e6xxx_g2_read(chip, GLOBAL2_SMI_PHY_DATA, val);
> + if (err)
> + return err;
> +
> + if (reg == MII_PHYSID2) {
> + /* The mv88e6390 internal PHYS don't have a model number.
> + * Use the switch family model number instead.
> + */
> + if (!(*val & 0x3ff)) {
> + if (chip->info->family == MV88E6XXX_FAMILY_6390)
I needed to test the MV88E6XXX_FAMILY_6341 flag too. But this one have
to be done in my series because before it the flag is not introduced.
As pointed in the other patch, we still need to decide to use the sale
PHY ID or to use a new one.
Thanks,
Gregory
> + *val |= PORT_SWITCH_ID_PROD_NUM_6390;
> + }
> + }
> +
> + return 0;
> }
>
> int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
> --
> 2.11.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH net-next 2/2] net: phy: Marvell: Add mv88e6390 internal PHY
Hi Andrew,
On mer., janv. 25 2017, Andrew Lunn wrote:
> diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
> index b5b73ff4329a..9debe1a4a6f6 100644
> --- a/drivers/net/phy/marvell.c
> +++ b/drivers/net/phy/marvell.c
> @@ -2140,6 +2140,25 @@ static struct phy_driver marvell_drivers[] = {
> .get_strings = marvell_get_strings,
> .get_stats = marvell_get_stats,
> },
> + {
> + .phy_id = MARVELL_PHY_ID_88E6390,
> + .phy_id_mask = MARVELL_PHY_ID_MASK,
> + .name = "Marvell 88E6390",
> + .features = PHY_GBIT_FEATURES,
> + .flags = PHY_HAS_INTERRUPT,
> + .probe = marvell_probe,
In order to get the temperature support I also had to modify the line
above by using m88e1510_probe instead of the marvell_probe. Indeed the
hwmon register was not done marvell_probe.
I think that you use marvell_probe because currently the value you get
are wrong for 6390. So either we have the 6390 which returns an
incorrect value for the temperature until you find the correct setting
or we introduce a new phy_id for the 6341 family with the hwmon support.
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH net-next 1/2] net: dsa: mv88e6xxx: Workaround missing PHY ID on mv88e6390
Hi Andrew,
On mer., janv. 25 2017, Andrew Lunn wrote:
> The internal PHYs of the mv88e6390 do not have a model ID. Trap any
> calls to the ID register, and if it is zero, return the ID for the
> mv88e6390. The Marvell PHY driver can then bind to this ID.
>
> Signed-off-by: Andrew Lunn
> Reviewed-by: Florian Fainelli
> ---
> drivers/net/dsa/mv88e6xxx/global2.c | 16 +++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/dsa/mv88e6xxx/global2.c
> b/drivers/net/dsa/mv88e6xxx/global2.c
> index 353e26bea3c3..521a5511bd5f 100644
> --- a/drivers/net/dsa/mv88e6xxx/global2.c
> +++ b/drivers/net/dsa/mv88e6xxx/global2.c
> @@ -520,7 +520,21 @@ int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip
> *chip,
> if (err)
> return err;
>
> - return mv88e6xxx_g2_read(chip, GLOBAL2_SMI_PHY_DATA, val);
> + err = mv88e6xxx_g2_read(chip, GLOBAL2_SMI_PHY_DATA, val);
> + if (err)
> + return err;
> +
> + if (reg == MII_PHYSID2) {
> + /* The mv88e6390 internal PHYS don't have a model number.
> + * Use the switch family model number instead.
> + */
> + if (!(*val & 0x3ff)) {
I tested this series on the Topaz switch but it failed because while I
said we read 0x1410C00 actually we read 0x01410C01. With the
MARVELL_PHY_ID_MASK we mask the 4 lower bits so that's why in my patch
"phy: marvell: Add support for the PHY embedded in the topaz switch" I
used the 0x01410C00 value for MARVELL_PHY_ID_88E6141.
However with the mask you use it doesn't work.
So this mask should be changed to 0x3f0 for the Topaz. Actually 0x3fe
would be enough but it seems more logical to use the same mask that for
MARVELL_PHY_ID_MASK.
We could either use the same mask for both family and still use 6390 as
they seem compatible or we use two different families based on the lower
bit.
Gregory
> + if (chip->info->family == MV88E6XXX_FAMILY_6390)
> + *val |= PORT_SWITCH_ID_PROD_NUM_6390;
> + }
> + }
> +
> + return 0;
> }
>
> int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
> --
> 2.11.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH net-next 5/5] net: dsa: mv88e6xxx: Implement the 6390 external MDIO bus
Hi Andrew, On mer., janv. 25 2017, Andrew Lunn wrote: >> diff --git a/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h >> b/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h >> index 7d24add45e74..572d585dc1e2 100644 >> --- a/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h >> +++ b/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h >> @@ -387,6 +387,7 @@ >> #define GLOBAL2_PTP_AVB_DATA0x17 >> #define GLOBAL2_SMI_PHY_CMD 0x18 >> #define GLOBAL2_SMI_PHY_CMD_BUSYBIT(15) >> +#define GLOBAL2_SMI_PHY_CMD_EXTERNALBIT(13) >> #define GLOBAL2_SMI_PHY_CMD_MODE_22 BIT(12) >> #define GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA((0x1 << 10) | \ > > Hi Gregory > > Please could you check if the 88E6341 has an external MDIO. Global 2, > register 0x18, bit 13. I confirm that 88E6341 has Global 2, register 0x18, bit 13 referred as "External access" Gregory > > Thanks > Andrew -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH net-next v6 2/4] net: dsa: mv88e6xxx: Add support for ethernet switch 88E6341
Hi Andrew,
On mer., janv. 25 2017, Andrew Lunn wrote:
>> +[MV88E6341] = {
>> +.prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
>> +.family = MV88E6XXX_FAMILY_6341,
>> +.name = "Marvell 88E6341",
>> +.num_databases = 4096,
>> +.num_ports = 6,
>> +.port_base_addr = 0x10,
>> +.global1_addr = 0x1b,
>> +.age_time_coeff = 15000,
>
> Hi Gregory
>
> Please could you check this timer in the datasheet. There is currently
> a bug in the mv88e6390 support code. I also set it to 15s. But in fact
> it is 3.75 seconds. The 6341 might also use 3.75 seconds.
When I read your series I also thought about it and indeed it is 3.75
seconds. I will fix it.
Thanks,
Gregory
>
>Thanks
> Andrew
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH net-next 5/8] net: dsa: mv88e6xxx: Workaround missing PHY ID on mv88e6390
Hi Vivien, On sam., janv. 21 2017, Vivien Didelot wrote: > Hi Andrew, > > Andrew Lunn writes: > >> The internal PHYs of the mv88e6390 do not have a model ID. Trap any >> calls to the ID register, and if it is zero, return the ID for the >> mv88e6390. The Marvell PHY driver can then bind to this ID. > > This, in addition to the temperature code not working (despite what the > datasheet says) makes me wonder if this is intentional from Marvell. Do > we have a revision number for the 88E6390X's on the ZII Dev Rev C board? > > It would be interesting to ask Gregory maybe about that. This looks not > "production-ready". What I can say is that with the 88E6341, which seems to have the same issue (ie incomplete PHY ID), reading the temperature worked. Gregory > > Other than that, I have no objection on the patch itself if that is > indeed expected from them... > > Thanks, > > Vivien -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH net-next v6 4/4] phy: marvell: Add support for the PHY embedded in the topaz switch
Hi Andrew, On mar., janv. 24 2017, Andrew Lunn wrote: > On Tue, Jan 24, 2017 at 09:10:26PM +0100, Gregory CLEMENT wrote: >> The PHY with the ID 0x1410C00 > > :-( > > I don't have a better reference, but > Linux/Documentation/devicetree/bindings/net/phy.txt says: > > 22 If the phy's identifier is known then the list may contain an entry > 23 of the form: "ethernet-phy-id." where > 24 - The value of the 16 bit Phy Identifier 1 register as > 25 4 hex digits. This is the chip vendor OUI bits 3:18 > 26 - The value of the 16 bit Phy Identifier 2 register as > 27 4 hex digits. This is the chip vendor OUI bits 19:24, > 28 followed by 10 bits of a vendor specific ID. > > So the lower 10 bits of 0x1410C00 are 0. So we know it is a Marvell > PHY from the OUI, but the vendor specific bits are all 0. In your previous email you mention a value of 0x0141, so when I saw the "C00" at the end I was happy and I didn't look for further. > > Please take a look at: > > https://marc.info/?l=linux-netdev&m=148495522620757&w=1 > > and > > https://marc.info/?l=linux-netdev&m=148495510320714&w=1 > > Maybe i should submit these two independently, so you can extend it > for the 88E6341 family. Please do it :) The feedback from Florian and Vivian was good about it so I see no reason to not apply them. Add me in CC so I will now when to rebase my series. Thanks, Gregory > > Andrew -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH net-next v6 1/4] net: dsa: mv88e6xxx: Don't forbid MDIO I/Os for PHY addr >= num_of_ports
Hi, On mar., janv. 24 2017, Gregory CLEMENT wrote: > From: Romain Perier > > Some Marvell ethernet switches have internal ethernet transceivers with > hardcoded phy addresses. These addresses can be greater than the number > of ports or its value might be different than the associated port number. > This is for example the case for MV88E6341 that has 6 ports and internal > Port 1 to Port4 PHYs mapped at SMI addresses from 0x11 to 0x14. > > This commits fixes the issue by removing the condition in MDIO callbacks. > > Signed-off-by: Romain Perier > Reviewed-by: Andrew Lunn This flag is missing: Reviewed-by: Vivien Didelot Actually I added during an interactive rebase, but I had to abort it and it was lost. Gregory > Signed-off-by: Gregory CLEMENT > --- > drivers/net/dsa/mv88e6xxx/chip.c | 6 -- > 1 file changed, 6 deletions(-) > > diff --git a/drivers/net/dsa/mv88e6xxx/chip.c > b/drivers/net/dsa/mv88e6xxx/chip.c > index c7e08e13bb54..7d942f8a42a7 100644 > --- a/drivers/net/dsa/mv88e6xxx/chip.c > +++ b/drivers/net/dsa/mv88e6xxx/chip.c > @@ -2882,9 +2882,6 @@ static int mv88e6xxx_mdio_read(struct mii_bus *bus, int > phy, int reg) > u16 val; > int err; > > - if (phy >= mv88e6xxx_num_ports(chip)) > - return 0x; > - > mutex_lock(&chip->reg_lock); > err = mv88e6xxx_phy_read(chip, phy, reg, &val); > mutex_unlock(&chip->reg_lock); > @@ -2897,9 +2894,6 @@ static int mv88e6xxx_mdio_write(struct mii_bus *bus, > int phy, int reg, u16 val) > struct mv88e6xxx_chip *chip = bus->priv; > int err; > > - if (phy >= mv88e6xxx_num_ports(chip)) > - return 0x; > - > mutex_lock(&chip->reg_lock); > err = mv88e6xxx_phy_write(chip, phy, reg, val); > mutex_unlock(&chip->reg_lock); > -- > git-series 0.9.1 -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
[PATCH net-next v6 3/4] net: dsa: mv88e6xxx: Add support for ethernet switch 88E6141
The Marvell 88E6341 device is single-chip, 6-port Ethernet switch with
four integrated 10/100/1000Mbps Ethernet transceivers and one high speed
SerDes interfaces.
It belongs to the Topaz family and unlike the 88E6341 it does not have
a TCAM.
Signed-off-by: Gregory CLEMENT
---
drivers/net/dsa/mv88e6xxx/chip.c | 42 -
drivers/net/dsa/mv88e6xxx/mv88e6xxx.h | 2 +-
2 files changed, 44 insertions(+)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 00db33ca1696..cdb8c7c4accd 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -3572,6 +3572,34 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
.reset = mv88e6352_g1_reset,
};
+static const struct mv88e6xxx_ops mv88e6141_ops = {
+ /* MV88E6XXX_FAMILY_6341 */
+ .get_eeprom = mv88e6xxx_g2_get_eeprom8,
+ .set_eeprom = mv88e6xxx_g2_set_eeprom8,
+ .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
+ .phy_read = mv88e6xxx_g2_smi_phy_read,
+ .phy_write = mv88e6xxx_g2_smi_phy_write,
+ .port_set_link = mv88e6xxx_port_set_link,
+ .port_set_duplex = mv88e6xxx_port_set_duplex,
+ .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
+ .port_set_speed = mv88e6390_port_set_speed,
+ .port_tag_remap = mv88e6095_port_tag_remap,
+ .port_set_frame_mode = mv88e6351_port_set_frame_mode,
+ .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
+ .port_set_ether_type = mv88e6351_port_set_ether_type,
+ .port_jumbo_config = mv88e6165_port_jumbo_config,
+ .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_pause_config = mv88e6097_port_pause_config,
+ .stats_snapshot = mv88e6390_g1_stats_snapshot,
+ .stats_get_sset_count = mv88e6320_stats_get_sset_count,
+ .stats_get_strings = mv88e6320_stats_get_strings,
+ .stats_get_stats = mv88e6390_stats_get_stats,
+ .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
+ .g1_set_egress_port = mv88e6390_g1_set_egress_port,
+ .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
+ .reset = mv88e6352_g1_reset,
+};
+
static const struct mv88e6xxx_ops mv88e6341_ops = {
/* MV88E6XXX_FAMILY_6341 */
.get_eeprom = mv88e6xxx_g2_get_eeprom8,
@@ -3987,6 +4015,20 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
.ops = &mv88e6321_ops,
},
+ [MV88E6141] = {
+ .prod_num = PORT_SWITCH_ID_PROD_NUM_6141,
+ .family = MV88E6XXX_FAMILY_6341,
+ .name = "Marvell 88E6341",
+ .num_databases = 4096,
+ .num_ports = 6,
+ .port_base_addr = 0x10,
+ .global1_addr = 0x1b,
+ .age_time_coeff = 15000,
+ .tag_protocol = DSA_TAG_PROTO_EDSA,
+ .flags = MV88E6XXX_FLAGS_FAMILY_6341,
+ .ops = &mv88e6141_ops,
+ },
+
[MV88E6341] = {
.prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
.family = MV88E6XXX_FAMILY_6341,
diff --git a/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h
b/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h
index e0527db0ef6e..94d1e98d4e2c 100644
--- a/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h
+++ b/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h
@@ -87,6 +87,7 @@
#define PORT_SWITCH_ID_PROD_NUM_6131 0x106
#define PORT_SWITCH_ID_PROD_NUM_6320 0x115
#define PORT_SWITCH_ID_PROD_NUM_6123 0x121
+#define PORT_SWITCH_ID_PROD_NUM_6141 0x340
#define PORT_SWITCH_ID_PROD_NUM_6161 0x161
#define PORT_SWITCH_ID_PROD_NUM_6165 0x165
#define PORT_SWITCH_ID_PROD_NUM_6171 0x171
@@ -420,6 +421,7 @@ enum mv88e6xxx_model {
MV88E6097,
MV88E6123,
MV88E6131,
+ MV88E6141,
MV88E6161,
MV88E6165,
MV88E6171,
--
git-series 0.9.1
[PATCH net-next v6 4/4] phy: marvell: Add support for the PHY embedded in the topaz switch
The PHY with the ID 0x1410C00 can be found embedded in the Marvell Topaz
switches (88E6141/88E6341). It is compatible with the 88E1510 (at least for
the temperature information), so add support for it, using the 88E1510
specific functions.
Signed-off-by: Gregory CLEMENT
---
drivers/net/phy/marvell.c | 21 +
include/linux/marvell_phy.h | 1 +
2 files changed, 22 insertions(+)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 64229976ace1..8b9338a746b8 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -2141,6 +2141,26 @@ static struct phy_driver marvell_drivers[] = {
.get_strings = marvell_get_strings,
.get_stats = marvell_get_stats,
},
+ {
+ .phy_id = MARVELL_PHY_ID_88E6141,
+ .phy_id_mask = MARVELL_PHY_ID_MASK,
+ .name = "Marvell 88E6141",
+ .probe = m88e1510_probe,
+ .remove = &marvell_remove,
+ .features = PHY_GBIT_FEATURES,
+ .flags = PHY_HAS_INTERRUPT,
+ .config_init = &marvell_config_init,
+ .config_aneg = &m88e1510_config_aneg,
+ .read_status = &marvell_read_status,
+ .ack_interrupt = &marvell_ack_interrupt,
+ .config_intr = &marvell_config_intr,
+ .did_interrupt = &m88e1121_did_interrupt,
+ .resume = &genphy_resume,
+ .suspend = &genphy_suspend,
+ .get_sset_count = marvell_get_sset_count,
+ .get_strings = marvell_get_strings,
+ .get_stats = marvell_get_stats,
+ },
};
module_phy_driver(marvell_drivers);
@@ -2159,6 +2179,7 @@ static struct mdio_device_id __maybe_unused marvell_tbl[]
= {
{ MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
{ MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
{ MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E6141, MARVELL_PHY_ID_MASK },
{ }
};
diff --git a/include/linux/marvell_phy.h b/include/linux/marvell_phy.h
index a57f0dfb6db7..6f33b73f2044 100644
--- a/include/linux/marvell_phy.h
+++ b/include/linux/marvell_phy.h
@@ -5,6 +5,7 @@
#define MARVELL_PHY_ID_MASK0xfff0
/* Known PHY IDs */
+#define MARVELL_PHY_ID_88E6141 0x01410c00
#define MARVELL_PHY_ID_88E1101 0x01410c60
#define MARVELL_PHY_ID_88E1112 0x01410c90
#define MARVELL_PHY_ID_88E 0x01410cc0
--
git-series 0.9.1
[PATCH net-next v6 1/4] net: dsa: mv88e6xxx: Don't forbid MDIO I/Os for PHY addr >= num_of_ports
From: Romain Perier Some Marvell ethernet switches have internal ethernet transceivers with hardcoded phy addresses. These addresses can be greater than the number of ports or its value might be different than the associated port number. This is for example the case for MV88E6341 that has 6 ports and internal Port 1 to Port4 PHYs mapped at SMI addresses from 0x11 to 0x14. This commits fixes the issue by removing the condition in MDIO callbacks. Signed-off-by: Romain Perier Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- drivers/net/dsa/mv88e6xxx/chip.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index c7e08e13bb54..7d942f8a42a7 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -2882,9 +2882,6 @@ static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) u16 val; int err; - if (phy >= mv88e6xxx_num_ports(chip)) - return 0x; - mutex_lock(&chip->reg_lock); err = mv88e6xxx_phy_read(chip, phy, reg, &val); mutex_unlock(&chip->reg_lock); @@ -2897,9 +2894,6 @@ static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) struct mv88e6xxx_chip *chip = bus->priv; int err; - if (phy >= mv88e6xxx_num_ports(chip)) - return 0x; - mutex_lock(&chip->reg_lock); err = mv88e6xxx_phy_write(chip, phy, reg, val); mutex_unlock(&chip->reg_lock); -- git-series 0.9.1
[PATCH net-next v6 0/4] Add support for the ethernet switch on the ESPRESSObin
Hi, This set of patches adds support for the Marvell Ethernet Topaz switch family (88E6141/88E6341) which is found on the ESPRESSObin. With this series the network is usable on this board. I rebased the series again on the very last net-next/master which allowed me this time to benefit to the temperature support introduced by Andrew Lunn. I still do not have a datasheet about the PHY embedded in the switch but thanks to the help of Andrew I was able to retrieve the PHY ID. Then, by using the 88E1510 operations I was able to get temperature with credible values. In this series I also added the support of the 88E6141 which is actually the switch on the boards I tested. The difference with the 88E6341, is the absence of the TCAM on the 88E6141, however I don't think this feature is used in the driver, so currently for Linux there is no difference except the switch ID. Thanks, Gregory Changelog: v5 -> v6: - rebased on net-next/master (d140199af510) - Fix the redundant check on mv88e6xxx_6341_family (reported by Julia Lawall) - Add support for the 88E6141 - Move support for temperature sensor in the phy part Gregory CLEMENT (3): net: dsa: mv88e6xxx: Add support for ethernet switch 88E6341 net: dsa: mv88e6xxx: Add support for ethernet switch 88E6141 phy: marvell: Add support for the PHY embedded in the topaz switch Romain Perier (1): net: dsa: mv88e6xxx: Don't forbid MDIO I/Os for PHY addr >= num_of_ports drivers/net/dsa/mv88e6xxx/chip.c | 102 --- drivers/net/dsa/mv88e6xxx/mv88e6xxx.h | 21 +- drivers/net/phy/marvell.c | 21 ++- include/linux/marvell_phy.h | 1 +- 4 files changed, 135 insertions(+), 10 deletions(-) base-commit: 1d0ec6626e558f9eb0043352745c02c42ff13a11 -- git-series 0.9.1
[PATCH net-next v6 2/4] net: dsa: mv88e6xxx: Add support for ethernet switch 88E6341
The Marvell 88E6341 device is single-chip, 6-port Ethernet switch with
four integrated 10/100/1000Mbps Ethernet transceivers and one high speed
SerDes interfaces. It is partially compatible with switches of family
88E6352 and switches of family 88E6390.
This commit adds an initial support for this switch by describing its
capabilities to the driver and introducing a new family.
Signed-off-by: Gregory CLEMENT
---
drivers/net/dsa/mv88e6xxx/chip.c | 54 ++--
drivers/net/dsa/mv88e6xxx/mv88e6xxx.h | 19 +-
2 files changed, 69 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 7d942f8a42a7..00db33ca1696 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -664,6 +664,11 @@ static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip
*chip)
return chip->info->family == MV88E6XXX_FAMILY_6320;
}
+static bool mv88e6xxx_6341_family(struct mv88e6xxx_chip *chip)
+{
+ return chip->info->family == MV88E6XXX_FAMILY_6341;
+}
+
static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
{
return chip->info->family == MV88E6XXX_FAMILY_6351;
@@ -1688,7 +1693,8 @@ static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip
*chip, u16 vid,
: GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
- mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
+ mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip) ||
+ mv88e6xxx_6341_family(chip)) {
struct mv88e6xxx_vtu_entry vstp;
/* Adding a VTU entry requires a valid STU entry. As VSTP is not
@@ -2543,7 +2549,7 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip
*chip, int port)
if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
- mv88e6xxx_6185_family(chip))
+ mv88e6xxx_6185_family(chip) || mv88e6xxx_6341_family(chip))
reg = PORT_CONTROL_2_MAP_DA;
if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
@@ -2597,7 +2603,7 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip
*chip, int port)
if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
- mv88e6xxx_6320_family(chip)) {
+ mv88e6xxx_6320_family(chip) || mv88e6xxx_6341_family(chip)) {
/* Port ATU control: disable limiting the number of
* address database entries that this port is allowed
* to use.
@@ -3566,6 +3572,34 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
.reset = mv88e6352_g1_reset,
};
+static const struct mv88e6xxx_ops mv88e6341_ops = {
+ /* MV88E6XXX_FAMILY_6341 */
+ .get_eeprom = mv88e6xxx_g2_get_eeprom8,
+ .set_eeprom = mv88e6xxx_g2_set_eeprom8,
+ .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
+ .phy_read = mv88e6xxx_g2_smi_phy_read,
+ .phy_write = mv88e6xxx_g2_smi_phy_write,
+ .port_set_link = mv88e6xxx_port_set_link,
+ .port_set_duplex = mv88e6xxx_port_set_duplex,
+ .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
+ .port_set_speed = mv88e6390_port_set_speed,
+ .port_tag_remap = mv88e6095_port_tag_remap,
+ .port_set_frame_mode = mv88e6351_port_set_frame_mode,
+ .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
+ .port_set_ether_type = mv88e6351_port_set_ether_type,
+ .port_jumbo_config = mv88e6165_port_jumbo_config,
+ .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_pause_config = mv88e6097_port_pause_config,
+ .stats_snapshot = mv88e6390_g1_stats_snapshot,
+ .stats_get_sset_count = mv88e6320_stats_get_sset_count,
+ .stats_get_strings = mv88e6320_stats_get_strings,
+ .stats_get_stats = mv88e6390_stats_get_stats,
+ .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
+ .g1_set_egress_port = mv88e6390_g1_set_egress_port,
+ .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
+ .reset = mv88e6352_g1_reset,
+};
+
static const struct mv88e6xxx_ops mv88e6390_ops = {
/* MV88E6XXX_FAMILY_6390 */
.get_eeprom = mv88e6xxx_g2_get_eeprom8,
@@ -3953,6 +3987,20 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
.ops = &mv88e6321_ops,
},
+ [MV88E6341] = {
+ .prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
+ .family = MV88E6XXX_FAMILY_6341,
+ .name = "Marvell 88E6341",
+ .num_databases = 4096,
+ .num_ports = 6,
+ .port_base_addr = 0x10,
+
Re: [PATCH v5 0/2] Add support for the ethernet switch on the ESPRESSObin
Hi David, On ven., janv. 20 2017, David Miller wrote: > From: Gregory CLEMENT > Date: Thu, 19 Jan 2017 22:49:32 +0100 > >> I created a new family for this switch and filled the ops structure >> by selecting which seems the more appropriate functions. I rebased >> the series on net-next/master which allowed me to benefit to the >> eeprom functions introduced for the 6390. > > It looks like there will be at least one more respin of this series, > specifically to remove the new family as Vivien seems to object to > this. I am about to send a new version. However about removing the new family, I thought that with the confirmation from Andrew we could keep it. Vivien could you confirm this? Thanks, Gregory -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH v5 2/2] net: dsa: mv88e6xxx: Add support for ethernet switch 88E6341
Hi Vvien and Andrew,
On ven., janv. 20 2017, Andrew Lunn wrote:
> On Thu, Jan 19, 2017 at 05:26:03PM -0500, Vivien Didelot wrote:
>> Gregory CLEMENT writes:
>>
>> > +static bool mv88e6xxx_6341_family(struct mv88e6xxx_chip *chip)
>> > +{
>> > + return chip->info->family == MV88E6XXX_FAMILY_6341;
>> > +}
>>
>> I don't want to see these erronous family checks anymore, but I cannot
>> blame you for adding it since not all the code is moved to ops yet ;)
If there a series about to be merged I can rebase my series on it. Else
I propose to keep it and convert the family check to ops when you will
send the series for it.
>>
>> >MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
>> >MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
>> >MV88E6XXX_FAMILY_6320, /* 6320 6321 */
>> > + MV88E6XXX_FAMILY_6341, /* 6141 6341 */
>>
>> Maybe I missed it, Andrew, can you confirm that 6341 is a proper Marvell
>> family of switch chips?
>
> My understand is that it is. Marvell have not added it to DSDT. There
> is a new SDK called UMSD, also GPLv2 and BSD. They call this family
> Topaz, and the 6390 is Peridot.
I confirm that 6141 and 6341 are called Topaz. Actually I can add the
support for the 6141 too, it is just a matter of adding an ID and maybe
removing some ops as 6141 is a subset of 6341.
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v5 0/2] Add support for the ethernet switch on the ESPRESSObin
Hi Andrew, On jeu., janv. 19 2017, Andrew Lunn wrote: >> While comparing the datasheet and the ops functions used, some >> question came to me. They should not prevent applying this series, >> but their answer would help me to have a better understanding of the >> dsa subsystem. >> >> - Are the temperature related operation still useful with dsa2 ? > > No. I'm in the process of moving the code into the Marvell PHY driver, > since the sensor is in the embedded PHYs. > > What ID does the embedded PHY use? The 6390 has a blank ID, where as > older device have a real ID. Actually I didn't find anything related to the temperature measurement in the datasheet I have. For the 6390 there is a dedicated datsheet for the PHY part for the 6352 it is part of the same datasheet. After a second look I think I don't have anything related to the PHY part in the datasheets. What I wanted to do was to test 6390 and 6352 temperature related functions and to see if one of them worked. That's how I realized it was not possible to do it with dsa2. > >> - Why the setup is done differently between the 6390 and the 6352 >> families when the have exactly the same register? > > EDSA on 6390 works differently to 6352, meaning it breaks. So we need > to run the 6390 with DSA tagging, not EDSA. Maybe this is the source > of the differences? > > It should also be noted that the 6390 support is not yet complete. I > have a few more patches in my tree to post. > >> - On the Port Controller 2, the bit PORT_CONTROL_2_MAP_DA is set for >> 6352 and not for 6390 whereas the same bit exists in 6360 and the >> description for this bit is the same for both datasheet. > > Humm, it does look like it is missing mv88e6xxx_6390_family(chip). > >> >> - Register PORT_ATU_CONTROL and PORT_PRI_OVERRIDE are reset on 6352 >> and not on 6390. While here again the registers description are >> the same. > > And the same here. I've mostly been working on where the 6390 is > different. Where it is the same i've mostly ignored it so far :-) > > There is also an ongoing effort to remove all these big if statements > with a list of families. Thanks for this answers I understand it a little better now. Gregory > > Andrew -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
[PATCH v5 1/2] net: dsa: mv88e6xxx: Don't forbid MDIO I/Os for PHY addr >= num_of_ports
From: Romain Perier Some Marvell ethernet switches have internal ethernet transceivers with hardcoded phy addresses. These addresses can be greater than the number of ports or its value might be different than the associated port number. This is for example the case for MV88E6341 that has 6 ports and internal Port 1 to Port4 PHYs mapped at SMI addresses from 0x11 to 0x14. This commits fixes the issue by removing the condition in MDIO callbacks. Signed-off-by: Romain Perier Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- drivers/net/dsa/mv88e6xxx/chip.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 987b2dbbd35a..d1960ae0a618 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -2882,9 +2882,6 @@ static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) u16 val; int err; - if (phy >= mv88e6xxx_num_ports(chip)) - return 0x; - mutex_lock(&chip->reg_lock); err = mv88e6xxx_phy_read(chip, phy, reg, &val); mutex_unlock(&chip->reg_lock); @@ -2897,9 +2894,6 @@ static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) struct mv88e6xxx_chip *chip = bus->priv; int err; - if (phy >= mv88e6xxx_num_ports(chip)) - return 0x; - mutex_lock(&chip->reg_lock); err = mv88e6xxx_phy_write(chip, phy, reg, val); mutex_unlock(&chip->reg_lock); -- 2.11.0
[PATCH v5 2/2] net: dsa: mv88e6xxx: Add support for ethernet switch 88E6341
The Marvell 88E6341 device is single-chip, 6-port Ethernet switch with
four integrated 10/100/1000Mbps Ethernet transceivers and one high speed
SerDes interfaces. It is partially compatible with switches of family
88E6352 and switches of family 88E6390.
This commit adds an initial support for this switch by describing its
capabilities to the driver and introducing a new family.
Signed-off-by: Gregory CLEMENT
---
drivers/net/dsa/mv88e6xxx/chip.c | 55 +--
drivers/net/dsa/mv88e6xxx/mv88e6xxx.h | 21 -
2 files changed, 72 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index d1960ae0a618..c73800e8105b 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -664,6 +664,11 @@ static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip
*chip)
return chip->info->family == MV88E6XXX_FAMILY_6320;
}
+static bool mv88e6xxx_6341_family(struct mv88e6xxx_chip *chip)
+{
+ return chip->info->family == MV88E6XXX_FAMILY_6341;
+}
+
static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
{
return chip->info->family == MV88E6XXX_FAMILY_6351;
@@ -1688,7 +1693,8 @@ static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip
*chip, u16 vid,
: GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
- mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
+ mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip) ||
+ mv88e6xxx_6341_family(chip)) {
struct mv88e6xxx_vtu_entry vstp;
/* Adding a VTU entry requires a valid STU entry. As VSTP is not
@@ -2543,7 +2549,7 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip
*chip, int port)
if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
- mv88e6xxx_6185_family(chip))
+ mv88e6xxx_6185_family(chip) || mv88e6xxx_6341_family(chip))
reg = PORT_CONTROL_2_MAP_DA;
if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
@@ -2597,7 +2603,8 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip
*chip, int port)
if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
- mv88e6xxx_6320_family(chip)) {
+ mv88e6xxx_6320_family(chip) || mv88e6xxx_6341_family(chip) ||
+ mv88e6xxx_6341_family(chip)) {
/* Port ATU control: disable limiting the number of
* address database entries that this port is allowed
* to use.
@@ -3714,6 +3721,34 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
.reset = mv88e6352_g1_reset,
};
+static const struct mv88e6xxx_ops mv88e6341_ops = {
+ /* MV88E6XXX_FAMILY_6341 */
+ .get_eeprom = mv88e6xxx_g2_get_eeprom8,
+ .set_eeprom = mv88e6xxx_g2_set_eeprom8,
+ .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
+ .phy_read = mv88e6xxx_g2_smi_phy_read,
+ .phy_write = mv88e6xxx_g2_smi_phy_write,
+ .port_set_link = mv88e6xxx_port_set_link,
+ .port_set_duplex = mv88e6xxx_port_set_duplex,
+ .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
+ .port_set_speed = mv88e6390_port_set_speed,
+ .port_tag_remap = mv88e6095_port_tag_remap,
+ .port_set_frame_mode = mv88e6351_port_set_frame_mode,
+ .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
+ .port_set_ether_type = mv88e6351_port_set_ether_type,
+ .port_jumbo_config = mv88e6165_port_jumbo_config,
+ .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_pause_config = mv88e6097_port_pause_config,
+ .stats_snapshot = mv88e6390_g1_stats_snapshot,
+ .stats_get_sset_count = mv88e6320_stats_get_sset_count,
+ .stats_get_strings = mv88e6320_stats_get_strings,
+ .stats_get_stats = mv88e6390_stats_get_stats,
+ .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
+ .g1_set_egress_port = mv88e6390_g1_set_egress_port,
+ .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
+ .reset = mv88e6352_g1_reset,
+};
+
static const struct mv88e6xxx_ops mv88e6390_ops = {
/* MV88E6XXX_FAMILY_6390 */
.get_eeprom = mv88e6xxx_g2_get_eeprom8,
@@ -4101,6 +4136,20 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
.ops = &mv88e6321_ops,
},
+ [MV88E6341] = {
+ .prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
+ .family = MV88E6XXX_FAMILY_6341,
+ .name = "Marvell 88E6341",
+ .num_databases = 4096,
+ .num_ports = 6,
+
[PATCH v5 0/2] Add support for the ethernet switch on the ESPRESSObin
Hi, This set of patches adds support for the Marvell Ethernet switch 88E6341 which is found on the ESPRESSObin. With this series the network is usable on this board. >From now on, I am taking care of this series. As Andrew Lunn pointed this switch is not fully compatible with the 6352. However it is neither fully compatible with the 6390. Actually it is more a mix between this two families. I created a new family for this switch and filled the ops structure by selecting which seems the more appropriate functions. I rebased the series on net-next/master which allowed me to benefit to the eeprom functions introduced for the 6390. While comparing the datasheet and the ops functions used, some question came to me. They should not prevent applying this series, but their answer would help me to have a better understanding of the dsa subsystem. - Are the temperature related operation still useful with dsa2 ? Indeed the hwmon initialization is only done from dsa_probe which is not called if we use dsa2. - Why the setup is done differently between the 6390 and the 6352 families when the have exactly the same register? - On the Port Controller 2, the bit PORT_CONTROL_2_MAP_DA is set for 6352 and not for 6390 whereas the same bit exists in 6360 and the description for this bit is the same for both datasheet. - Register PORT_ATU_CONTROL and PORT_PRI_OVERRIDE are reset on 6352 and not on 6390. While here again the registers description are the same. Thanks, Gregory Gregory CLEMENT (1): net: dsa: mv88e6xxx: Add support for ethernet switch 88E6341 Romain Perier (1): net: dsa: mv88e6xxx: Don't forbid MDIO I/Os for PHY addr >= num_of_ports drivers/net/dsa/mv88e6xxx/chip.c | 61 +-- drivers/net/dsa/mv88e6xxx/mv88e6xxx.h | 21 +++- 2 files changed, 72 insertions(+), 10 deletions(-) -- 2.11.0
Re: [PATCH net-next v4 0/2] Add support for the ethernet switch on the ESPRESSObin
Hi David, On mer., déc. 21 2016, Romain Perier wrote: > This set of patches adds support for the Marvell ethernet switch 88E6341. > It also add the devicetree definition of this switch to the DT board. The forth version of this series had been sent while the net-next merge window was closed so I think it was missed. Do you want that we send it again on the netdev mainling list? Thanks, Gregory > > Romain Perier (2): > net: dsa: mv88e6xxx: Don't forbid MDIO I/Os for PHY addr >= > num_of_ports > net: dsa: mv88e6xxx: Add support for ethernet switch 88E6341/88E6141 > > drivers/net/dsa/mv88e6xxx/chip.c | 48 > ++- > drivers/net/dsa/mv88e6xxx/mv88e6xxx.h | 4 ++- > 2 files changed, 45 insertions(+), 7 deletions(-) > > -- > > Note: As requested by Gregory, I have removed the patch for the DT (already > merged). > > 2.9.3 > -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH v3 net-next 3/3] arm64: dts: marvell: Add ethernet switch definition for the ESPRESSObin
Hi Romain,
On mer., déc. 21 2016, Romain Perier wrote:
> This defines and enables the Marvell ethernet switch MVE886341 on the
> Marvell ESPRESSObin board.
This patch looks OK now.
Applied on mvebu/dt64-4.11
So you can remove it from you next version because I don't want this
patch will be applied through the netdev branch. Indeed I expect more
changes in this file for v4.11 and it will be easier to have the change
in a single branch to avoid the merge conflict.
Thanks,
Gregory
>
> Signed-off-by: Romain Perier
> ---
>
> Changes in v3:
> - Changed the node switch0 to be at 1
> - Removed reg=<1> from the mdio node, finally that's not required
>
> Changes in v2:
> - EXPRESSObin -> ESPRESSObin
> - phy nodes definition must contain the internal bus address after the @
>
> .../boot/dts/marvell/armada-3720-espressobin.dts | 66
> ++
> 1 file changed, 66 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
> b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
> index 83178d9..12d9f65 100644
> --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
> +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
> @@ -80,3 +80,69 @@
> &usb3 {
> status = "okay";
> };
> +
> +&mdio {
> + switch0: switch0@1 {
> + compatible = "marvell,mv88e6085";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + dsa,member = <0 0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + label = "cpu";
> + ethernet = <ð0>;
> + };
> +
> + port@1 {
> + reg = <1>;
> + label = "wan";
> + phy-handle = <&switch0phy0>;
> + };
> +
> + port@2 {
> + reg = <2>;
> + label = "lan0";
> + phy-handle = <&switch0phy1>;
> + };
> +
> + port@3 {
> + reg = <3>;
> + label = "lan1";
> + phy-handle = <&switch0phy2>;
> + };
> +
> + };
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + switch0phy0: switch0phy0@11 {
> + reg = <0x11>;
> + };
> + switch0phy1: switch0phy1@12 {
> + reg = <0x12>;
> + };
> + switch0phy2: switch0phy2@13 {
> + reg = <0x13>;
> + };
> + };
> + };
> +};
> +
> +ð0 {
> + phy-mode = "rgmii-id";
> + status = "okay";
> +
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> +};
> --
> 2.9.3
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v3 net-next 1/3] net: dsa: mv88e6xxx: Don't forbid MDIO I/Os for PHY addr >= num_of_ports
Hi Romain, it seems there is a remaining typo :) On mer., déc. 21 2016, Romain Perier wrote: > Some Marvell ethernet switches have internal ethernet transceivers with > hardcoded phy addresses. These addresses can be grearer than the number greater > of ports or its value might be different than the associated port number. > This is for example the case for MV88E6341 that has 6 ports and internal > Port 1 to Port4 PHYs mapped at SMI addresses from 0x11 to 0x14. > > This commits fixes the issue by removing the condition in MDIO callbacks. > > Signed-off-by: Romain Perier > Reviewed-by: Andrew Lunn > --- > > Changes in v2: > - Added tag "Reviewed-by" by Andrew > - Fixed typo in the commit log > > drivers/net/dsa/mv88e6xxx/chip.c | 6 -- > 1 file changed, 6 deletions(-) > > diff --git a/drivers/net/dsa/mv88e6xxx/chip.c > b/drivers/net/dsa/mv88e6xxx/chip.c > index b5f0e1e..76d944e 100644 > --- a/drivers/net/dsa/mv88e6xxx/chip.c > +++ b/drivers/net/dsa/mv88e6xxx/chip.c > @@ -2881,9 +2881,6 @@ static int mv88e6xxx_mdio_read(struct mii_bus *bus, int > phy, int reg) > u16 val; > int err; > > - if (phy >= mv88e6xxx_num_ports(chip)) > - return 0x; > - > mutex_lock(&chip->reg_lock); > err = mv88e6xxx_phy_read(chip, phy, reg, &val); > mutex_unlock(&chip->reg_lock); > @@ -2896,9 +2893,6 @@ static int mv88e6xxx_mdio_write(struct mii_bus *bus, > int phy, int reg, u16 val) > struct mv88e6xxx_chip *chip = bus->priv; > int err; > > - if (phy >= mv88e6xxx_num_ports(chip)) > - return 0x; > - > mutex_lock(&chip->reg_lock); > err = mv88e6xxx_phy_write(chip, phy, reg, val); > mutex_unlock(&chip->reg_lock); > -- > 2.9.3 > -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH 3/3] Bluetooth: btusb: Configure Marvel to use one of the pins for oob wakeup
(0x3F, 0x59);
> + cmd[0] = opcode & 0xFF;
> + cmd[1] = opcode >> 8;
> + cmd[2] = 2; /* length of parameters that follow */
> + cmd[3] = pin;
> + cmd[4] = gap; /* time in ms, for which wakeup pin should be asserted */
> +
> + skb = bt_skb_alloc(sizeof(cmd), GFP_KERNEL);
> + if (!skb) {
> + bt_dev_err(hdev, "%s: No memory\n", __func__);
> + return -ENOMEM;
> + }
> +
> + memcpy(skb_put(skb, sizeof(cmd)), cmd, sizeof(cmd));
> + hci_skb_pkt_type(skb) = HCI_COMMAND_PKT;
> +
> + ret = btusb_send_frame(hdev, skb);
> + if (ret) {
> + bt_dev_err(hdev, "%s: configuration failed\n", __func__);
> + kfree_skb(skb);
> + return ret;
> + }
> +
> + return 0;
> +}
> +#endif
> +
> static int btusb_set_bdaddr_marvell(struct hci_dev *hdev,
> const bdaddr_t *bdaddr)
> {
> @@ -2917,6 +2969,13 @@ static int btusb_probe(struct usb_interface *intf,
> err = btusb_config_oob_wake(hdev);
> if (err)
> goto out_free_dev;
> +
> + /* Marvel devices may need a specific chip configuration */
> + if (id->driver_info & BTUSB_MARVELL && data->oob_wake_irq) {
> + err = marvell_config_oob_wake(hdev);
> + if (err)
> + goto out_free_dev;
> + }
> #endif
> if (id->driver_info & BTUSB_CW6622)
> set_bit(HCI_QUIRK_BROKEN_STORED_LINK_KEY, &hdev->quirks);
> --
> 2.8.0.rc3.226.g39d4020
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
[PATCH v6 net-next 2/7] net: mvneta: Do not allocate buffer in rxq init with HWBM
For HWBM all buffers are allocated in mvneta_bm_construct() and in runtime
they are put into descriptors by hardware. There is no need to fill them
at this point.
Suggested-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
Tested-by: Marcin Wojtas
---
drivers/net/ethernet/marvell/mvneta.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 1b84f746d748..f5319c50f8d9 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -2784,14 +2784,14 @@ static int mvneta_rxq_init(struct mvneta_port *pp,
mvneta_rxq_buf_size_set(pp, rxq,
MVNETA_RX_BUF_SIZE(pp->pkt_size));
mvneta_rxq_bm_disable(pp, rxq);
+ mvneta_rxq_fill(pp, rxq, rxq->size);
} else {
mvneta_rxq_bm_enable(pp, rxq);
mvneta_rxq_long_pool_set(pp, rxq);
mvneta_rxq_short_pool_set(pp, rxq);
+ mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size);
}
- mvneta_rxq_fill(pp, rxq, rxq->size);
-
return 0;
}
--
git-series 0.8.10
[PATCH v6 net-next 4/7] net: mvneta: Convert to be 64 bits compatible
From: Marcin Wojtas
Prepare the mvneta driver in order to be usable on the 64 bits platform
such as the Armada 3700.
[gregory.clem...@free-electrons.com]: this patch was extract from a larger
one to ease review and maintenance.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
Tested-by: Marcin Wojtas
---
drivers/net/ethernet/marvell/mvneta.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 92b9af14c352..8ef03fb69bcd 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -296,6 +296,12 @@
/* descriptor aligned size */
#define MVNETA_DESC_ALIGNED_SIZE 32
+/* Number of bytes to be taken into account by HW when putting incoming data
+ * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet
+ * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
+ */
+#define MVNETA_RX_PKT_OFFSET_CORRECTION64
+
#define MVNETA_RX_PKT_SIZE(mtu) \
ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
ETH_HLEN + ETH_FCS_LEN,\
@@ -416,6 +422,7 @@ struct mvneta_port {
u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
+ u16 rx_offset_correction;
};
/* The mvneta_tx_desc and mvneta_rx_desc structures describe the
@@ -1807,6 +1814,7 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
return -ENOMEM;
}
+ phys_addr += pp->rx_offset_correction;
mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
return 0;
}
@@ -2782,7 +2790,7 @@ static int mvneta_rxq_init(struct mvneta_port *pp,
mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
/* Set Offset */
- mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
+ mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD - pp->rx_offset_correction);
/* Set coalescing pkts and time */
mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
@@ -4033,6 +4041,13 @@ static int mvneta_probe(struct platform_device *pdev)
pp->rxq_def = rxq_def;
+ /* Set RX packet offset correction for platforms, whose
+* NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit
+* platforms and 0B for 32-bit ones.
+*/
+ pp->rx_offset_correction =
+ max(0, NET_SKB_PAD - MVNETA_RX_PKT_OFFSET_CORRECTION);
+
pp->indir[0] = rxq_def;
pp->clk = devm_clk_get(&pdev->dev, "core");
--
git-series 0.8.10
[PATCH v6 net-next 5/7] net: mvneta: Only disable mvneta_bm for 64-bits
Actually only the mvneta_bm support is not 64-bits compatible. The mvneta code itself can run on 64-bits architecture. Signed-off-by: Gregory CLEMENT Tested-by: Marcin Wojtas --- drivers/net/ethernet/marvell/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/Kconfig b/drivers/net/ethernet/marvell/Kconfig index 66fd9dbb2ca7..2ccea9dd9248 100644 --- a/drivers/net/ethernet/marvell/Kconfig +++ b/drivers/net/ethernet/marvell/Kconfig @@ -44,6 +44,7 @@ config MVMDIO config MVNETA_BM_ENABLE tristate "Marvell Armada 38x/XP network interface BM support" depends on MVNETA + depends on !64BIT ---help--- This driver supports auxiliary block of the network interface units in the Marvell ARMADA XP and ARMADA 38x SoC @@ -58,7 +59,6 @@ config MVNETA tristate "Marvell Armada 370/38x/XP network interface support" depends on PLAT_ORION || COMPILE_TEST depends on HAS_DMA - depends on !64BIT select MVMDIO select FIXED_PHY ---help--- @@ -71,6 +71,7 @@ config MVNETA config MVNETA_BM tristate + depends on !64BIT default y if MVNETA=y && MVNETA_BM_ENABLE!=n default MVNETA_BM_ENABLE select HWBM -- git-series 0.8.10
[PATCH v6 net-next 6/7] net: mvneta: Add network support for Armada 3700 SoC
From: Marcin Wojtas
Armada 3700 is a new ARMv8 SoC from Marvell using same network controller
as older Armada 370/38x/XP. There are however some differences that
needed taking into account when adding support for it:
* open default MBUS window to 4GB of DRAM - Armada 3700 SoC's Mbus
configuration for network controller has to be done on two levels:
global and per-port. The first one is inherited from the
bootloader. The latter can be opened in a default way, leaving
arbitration to the bus controller. Hence filled mbus_dram_target_info
structure is not needed
* make per-CPU operation optional - Recent patches adding RSS and XPS
support for Armada 38x/XP enabled per-CPU operation of the controller
by default. Contrary to older SoC's Armada 3700 SoC's network
controller is not capable of per-CPU processing due to interrupt lines'
connectivity. This patch restores non-per-CPU operation, which is now
optional and depends on neta_armada3700 flag value in mvneta_port
structure. In order not to complicate the code, separate interrupt
subroutine is implemented.
For now, on the Armada 3700, RSS is disabled as the current
implementation depend on the per cpu interrupts.
[gregory.clem...@free-electrons.com: extract from a larger patch, replace
some ifdef and port to net-next for v4.10]
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
Tested-by: Marcin Wojtas
---
Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 +-
drivers/net/ethernet/marvell/Kconfig | 7 +-
drivers/net/ethernet/marvell/mvneta.c | 287
+++-
3 files changed, 214 insertions(+), 87 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
index 73be8970815e..7aa840c8768d 100644
--- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
+++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
@@ -1,7 +1,10 @@
-* Marvell Armada 370 / Armada XP Ethernet Controller (NETA)
+* Marvell Armada 370 / Armada XP / Armada 3700 Ethernet Controller (NETA)
Required properties:
-- compatible: "marvell,armada-370-neta" or "marvell,armada-xp-neta".
+- compatible: could be one of the followings
+ "marvell,armada-370-neta"
+ "marvell,armada-xp-neta"
+ "marvell,armada-3700-neta"
- reg: address and length of the register set for the device.
- interrupts: interrupt for the device
- phy: See ethernet.txt file in the same directory.
diff --git a/drivers/net/ethernet/marvell/Kconfig
b/drivers/net/ethernet/marvell/Kconfig
index 2ccea9dd9248..3b8f11fe5e13 100644
--- a/drivers/net/ethernet/marvell/Kconfig
+++ b/drivers/net/ethernet/marvell/Kconfig
@@ -56,14 +56,15 @@ config MVNETA_BM_ENABLE
buffer management.
config MVNETA
- tristate "Marvell Armada 370/38x/XP network interface support"
- depends on PLAT_ORION || COMPILE_TEST
+ tristate "Marvell Armada 370/38x/XP/37xx network interface support"
+ depends on ARCH_MVEBU || COMPILE_TEST
depends on HAS_DMA
select MVMDIO
select FIXED_PHY
---help---
This driver supports the network interface units in the
- Marvell ARMADA XP, ARMADA 370 and ARMADA 38x SoC family.
+ Marvell ARMADA XP, ARMADA 370, ARMADA 38x and
+ ARMADA 37xx SoC family.
Note that this driver is distinct from the mv643xx_eth
driver, which should be used for the older Marvell SoCs
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 8ef03fb69bcd..ffc0c65068ea 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -397,6 +397,9 @@ struct mvneta_port {
spinlock_t lock;
bool is_stopped;
+ u32 cause_rx_tx;
+ struct napi_struct napi;
+
/* Core clock */
struct clk *clk;
/* AXI clock */
@@ -422,6 +425,9 @@ struct mvneta_port {
u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
+
+ /* Flags for special SoC configurations */
+ bool neta_armada3700;
u16 rx_offset_correction;
};
@@ -965,14 +971,9 @@ static int mvneta_mbus_io_win_set(struct mvneta_port *pp,
u32 base, u32 wsize,
return 0;
}
-/* Assign and initialize pools for port. In case of fail
- * buffer manager will remain disabled for current port.
- */
-static int mvneta_bm_port_init(struct platform_device *pdev,
- struct mvneta_port *pp)
+static int mvneta_bm_port_mbus_init(struct mvneta_port *pp)
{
- struct device_node *dn = pdev->dev.of_node;
- u32 long_pool_id, short_pool_id, wsize;
+
[PATCH v6 net-next 1/7] net: mvneta: Optimize rx path for small frame
For small frame reuse the phys_addr variable instead of accessing the uncacheable value in the rx descriptor. Signed-off-by: Gregory CLEMENT Tested-by: Marcin Wojtas --- drivers/net/ethernet/marvell/mvneta.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index 87274d4ab102..1b84f746d748 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c @@ -1918,7 +1918,7 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int rx_todo, goto err_drop_frame; dma_sync_single_range_for_cpu(dev->dev.parent, - rx_desc->buf_phys_addr, + phys_addr, MVNETA_MH_SIZE + NET_SKB_PAD, rx_bytes, DMA_FROM_DEVICE); -- git-series 0.8.10
[PATCH v6 net-next 0/7] Support Armada 37xx SoC (ARMv8 64-bits) in mvneta driver
Hi, The Armada 37xx is a new ARMv8 SoC from Marvell using same network controller as the older Armada 370/38x/XP SoCs. This series adapts the driver in order to be able to use it on this new SoC. The main changes are: - 64-bits support: the first patches allow using the driver on a 64-bit architecture. - MBUS support: the mbus configuration is different on Armada 37xx from the older SoCs. - per cpu interrupt: Armada 37xx do not support per cpu interrupt for the NETA IP, the non-per-CPU behavior was added back. The first patch is an optimization in the rx path in swbm mode. The second patch remove unnecessary allocation for HWBM. The first item is solved by patches 4 and 5. The 2 last items are solved by patch 6. In patch 7 the dt support is added. Beside Armada 37xx, this series have been again tested on Armada XP and Armada 38x (with Hardware Buffer Management and with Software Buffer Management). This is the 6th version of the series: - 1st version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/469588.html - 2nd version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/470476.html - 3rd version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/470901.html - 4th version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/471039.html - 5th version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/471478.html Changelog: v5 -> v6: - Added Tested-by from Marcin Wojtas on the series - Added Reviewed-by from Jisheng Zhang on patch 3 - Fix eth1 phy mode for Armada 3720 DB board on patch 7 v4 -> v5: - remove unnecessary cast in patch 3 v3 -> v4: - Adding new patch: "net: mvneta: do not allocate buffer in rxq init with HWBM" - Simplify the HWBM case in patch 3 as suggested by Marcin v2 -> v3: - Adding patch 1 "Optimize rx path for small frame" - Fix the kbuild error by moving the "phys_addr += pp->rx_offset_correction;" line from patch 2 to patch 3 where rx_offset_correction is introduced. - Move the memory allocation of the buf_virt_addr of the rxq to be called by the probe function in order to avoid a memory leak. Thanks, Gregory Gregory CLEMENT (5): net: mvneta: Optimize rx path for small frame net: mvneta: Do not allocate buffer in rxq init with HWBM net: mvneta: Use cacheable memory to store the rx buffer virtual address net: mvneta: Only disable mvneta_bm for 64-bits ARM64: dts: marvell: Add network support for Armada 3700 Marcin Wojtas (2): net: mvneta: Convert to be 64 bits compatible net: mvneta: Add network support for Armada 3700 SoC Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 +- arch/arm64/boot/dts/marvell/armada-3720-db.dts| 23 +- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 +- drivers/net/ethernet/marvell/Kconfig | 10 +- drivers/net/ethernet/marvell/mvneta.c | 344 +++- 5 files changed, 305 insertions(+), 102 deletions(-) base-commit: 436accebb53021ef7c63535f60bda410aa87c136 -- git-series 0.8.10
[PATCH v6 net-next 7/7] ARM64: dts: marvell: Add network support for Armada 3700
Add neta nodes for network support both in device tree for the SoC and
the board.
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 23 +++-
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 +++-
2 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 1372e9a6aaa4..a59d36cd6caf 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -81,3 +81,26 @@
&pcie0 {
status = "okay";
};
+
+&mdio {
+ status = "okay";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+ð0 {
+ phy-mode = "rgmii-id";
+ phy = <&phy0>;
+ status = "okay";
+};
+
+ð1 {
+ phy-mode = "sgmii";
+ phy = <&phy1>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index e9bd58793464..3b8eb45bdc76 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -140,6 +140,29 @@
};
};
+ eth0: ethernet@3 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x3 0x4000>;
+ interrupts = ;
+ clocks = <&sb_periph_clk 8>;
+ status = "disabled";
+ };
+
+ mdio: mdio@32004 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0x32004 0x4>;
+ };
+
+ eth1: ethernet@4 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x4 0x4000>;
+ interrupts = ;
+ clocks = <&sb_periph_clk 7>;
+ status = "disabled";
+ };
+
usb3: usb@58000 {
compatible = "marvell,armada3700-xhci",
"generic-xhci";
--
git-series 0.8.10
[PATCH v6 net-next 3/7] net: mvneta: Use cacheable memory to store the rx buffer virtual address
Until now the virtual address of the received buffer were stored in the
cookie field of the rx descriptor. However, this field is 32-bits only
which prevents to use the driver on a 64-bits architecture.
With this patch the virtual address is stored in an array not shared with
the hardware (no more need to use the DMA API). Thanks to this, it is
possible to use cache contrary to the access of the rx descriptor member.
The change is done in the swbm path only because the hwbm uses the cookie
field, this also means that currently the hwbm is not usable in 64-bits.
Signed-off-by: Gregory CLEMENT
Reviewed-by: Jisheng Zhang
Tested-by: Marcin Wojtas
---
drivers/net/ethernet/marvell/mvneta.c | 34 +++-
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index f5319c50f8d9..92b9af14c352 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -561,6 +561,9 @@ struct mvneta_rx_queue {
u32 pkts_coal;
u32 time_coal;
+ /* Virtual address of the RX buffer */
+ void **buf_virt_addr;
+
/* Virtual address of the RX DMA descriptors array */
struct mvneta_rx_desc *descs;
@@ -1573,10 +1576,14 @@ static void mvneta_tx_done_pkts_coal_set(struct
mvneta_port *pp,
/* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
- u32 phys_addr, u32 cookie)
+ u32 phys_addr, void *virt_addr,
+ struct mvneta_rx_queue *rxq)
{
- rx_desc->buf_cookie = cookie;
+ int i;
+
rx_desc->buf_phys_addr = phys_addr;
+ i = rx_desc - rxq->descs;
+ rxq->buf_virt_addr[i] = virt_addr;
}
/* Decrement sent descriptors counter */
@@ -1781,7 +1788,8 @@ EXPORT_SYMBOL_GPL(mvneta_frag_free);
/* Refill processing for SW buffer management */
static int mvneta_rx_refill(struct mvneta_port *pp,
- struct mvneta_rx_desc *rx_desc)
+ struct mvneta_rx_desc *rx_desc,
+ struct mvneta_rx_queue *rxq)
{
dma_addr_t phys_addr;
@@ -1799,7 +1807,7 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
return -ENOMEM;
}
- mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
+ mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
return 0;
}
@@ -1861,7 +1869,7 @@ static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
for (i = 0; i < rxq->size; i++) {
struct mvneta_rx_desc *rx_desc = rxq->descs + i;
- void *data = (void *)rx_desc->buf_cookie;
+ void *data = rxq->buf_virt_addr[i];
dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
MVNETA_RX_BUF_SIZE(pp->pkt_size),
DMA_FROM_DEVICE);
@@ -1894,12 +1902,13 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int
rx_todo,
unsigned char *data;
dma_addr_t phys_addr;
u32 rx_status, frag_size;
- int rx_bytes, err;
+ int rx_bytes, err, index;
rx_done++;
rx_status = rx_desc->status;
rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
- data = (unsigned char *)rx_desc->buf_cookie;
+ index = rx_desc - rxq->descs;
+ data = rxq->buf_virt_addr[index];
phys_addr = rx_desc->buf_phys_addr;
if (!mvneta_rxq_desc_is_first_last(rx_status) ||
@@ -1938,7 +1947,7 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int
rx_todo,
}
/* Refill processing */
- err = mvneta_rx_refill(pp, rx_desc);
+ err = mvneta_rx_refill(pp, rx_desc, rxq);
if (err) {
netdev_err(dev, "Linux processing - Can't refill\n");
rxq->missed++;
@@ -2020,7 +2029,7 @@ static int mvneta_rx_hwbm(struct mvneta_port *pp, int
rx_todo,
rx_done++;
rx_status = rx_desc->status;
rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
- data = (unsigned char *)rx_desc->buf_cookie;
+ data = (u8 *)(uintptr_t)rx_desc->buf_cookie;
phys_addr = rx_desc->buf_phys_addr;
pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
bm_pool = &pp->bm_priv->bm_pools[pool_id];
@@ -2716,7 +2725,7 @@ static int mvneta_rxq_fill(struct mvneta_port *pp, struct
mvneta_rx_queue *rxq,
for (i = 0; i < num; i++) {
memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
-
Re: [PATCH v5 net-next 0/7] Support Armada 37xx SoC (ARMv8 64-bits) in mvneta driver
Hi Marcin, On jeu., déc. 01 2016, Marcin Wojtas wrote: > Hi Gregory, > > Checked on a388-gp with and without HWBM, also both ports work on > a3700 (second one after changing to sgmii). > > Tested-by: Marcin Wojtas Thanks, I am going to send a new version with tour tested-by and the dts fix for the second port. Gregory > > Best regards, > Marcin > > 2016-11-30 22:42 GMT+01:00 Gregory CLEMENT > : >> Hi, >> >> The Armada 37xx is a new ARMv8 SoC from Marvell using same network >> controller as the older Armada 370/38x/XP SoCs. This series adapts the >> driver in order to be able to use it on this new SoC. The main changes >> are: >> >> - 64-bits support: the first patches allow using the driver on a 64-bit >> architecture. >> >> - MBUS support: the mbus configuration is different on Armada 37xx >> from the older SoCs. >> >> - per cpu interrupt: Armada 37xx do not support per cpu interrupt for >> the NETA IP, the non-per-CPU behavior was added back. >> >> The first patch is an optimization in the rx path in swbm mode. >> The second patch remove unnecessary allocation for HWBM. >> The first item is solved by patches 4 and 5. >> The 2 last items are solved by patch 6. >> In patch 7 the dt support is added. >> >> Beside Armada 37xx, this series have been again tested on Armada XP >> and Armada 38x (with Hardware Buffer Management and with Software >> Buffer Management). >> >> This is the 5th version of the series: >> - 1st version: >> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/469588.html >> >> - 2nd version: >> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/470476.html >> >> - 3rd version: >> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/470901.html >> >> - 4th version: >> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/471039.html >> >> Changelog: >> v4 -> v5: >> - remove unnecessary cast in patch 3 >> >> v3 -> v4: >> - Adding new patch: "net: mvneta: do not allocate buffer in rxq init >>with HWBM" >> >> - Simplify the HWBM case in patch 3 as suggested by Marcin >> >> v2 -> v3: >> - Adding patch 1 "Optimize rx path for small frame" >> >> - Fix the kbuild error by moving the "phys_addr += >> pp->rx_offset_correction;" >> line from patch 2 to patch 3 where rx_offset_correction is introduced. >> >> - Move the memory allocation of the buf_virt_addr of the rxq to be >>called by the probe function in order to avoid a memory leak. >> >> Thanks, >> >> Gregory >> >> Gregory CLEMENT (5): >> net: mvneta: Optimize rx path for small frame >> net: mvneta: Do not allocate buffer in rxq init with HWBM >> net: mvneta: Use cacheable memory to store the rx buffer virtual address >> net: mvneta: Only disable mvneta_bm for 64-bits >> ARM64: dts: marvell: Add network support for Armada 3700 >> >> Marcin Wojtas (2): >> net: mvneta: Convert to be 64 bits compatible >> net: mvneta: Add network support for Armada 3700 SoC >> >> Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 +- >> arch/arm64/boot/dts/marvell/armada-3720-db.dts| 23 >> +- >> arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 >> +- >> drivers/net/ethernet/marvell/Kconfig | 10 +- >> drivers/net/ethernet/marvell/mvneta.c | 344 >> +++- >> 5 files changed, 305 insertions(+), 102 deletions(-) >> >> base-commit: 436accebb53021ef7c63535f60bda410aa87c136 >> -- >> git-series 0.8.10 -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
[PATCH v5 net-next 5/7] net: mvneta: Only disable mvneta_bm for 64-bits
Actually only the mvneta_bm support is not 64-bits compatible. The mvneta code itself can run on 64-bits architecture. Signed-off-by: Gregory CLEMENT --- drivers/net/ethernet/marvell/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/Kconfig b/drivers/net/ethernet/marvell/Kconfig index 66fd9dbb2ca7..2ccea9dd9248 100644 --- a/drivers/net/ethernet/marvell/Kconfig +++ b/drivers/net/ethernet/marvell/Kconfig @@ -44,6 +44,7 @@ config MVMDIO config MVNETA_BM_ENABLE tristate "Marvell Armada 38x/XP network interface BM support" depends on MVNETA + depends on !64BIT ---help--- This driver supports auxiliary block of the network interface units in the Marvell ARMADA XP and ARMADA 38x SoC @@ -58,7 +59,6 @@ config MVNETA tristate "Marvell Armada 370/38x/XP network interface support" depends on PLAT_ORION || COMPILE_TEST depends on HAS_DMA - depends on !64BIT select MVMDIO select FIXED_PHY ---help--- @@ -71,6 +71,7 @@ config MVNETA config MVNETA_BM tristate + depends on !64BIT default y if MVNETA=y && MVNETA_BM_ENABLE!=n default MVNETA_BM_ENABLE select HWBM -- git-series 0.8.10
[PATCH v5 net-next 4/7] net: mvneta: Convert to be 64 bits compatible
From: Marcin Wojtas
Prepare the mvneta driver in order to be usable on the 64 bits platform
such as the Armada 3700.
[gregory.clem...@free-electrons.com]: this patch was extract from a larger
one to ease review and maintenance.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 92b9af14c352..8ef03fb69bcd 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -296,6 +296,12 @@
/* descriptor aligned size */
#define MVNETA_DESC_ALIGNED_SIZE 32
+/* Number of bytes to be taken into account by HW when putting incoming data
+ * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet
+ * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
+ */
+#define MVNETA_RX_PKT_OFFSET_CORRECTION64
+
#define MVNETA_RX_PKT_SIZE(mtu) \
ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
ETH_HLEN + ETH_FCS_LEN,\
@@ -416,6 +422,7 @@ struct mvneta_port {
u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
+ u16 rx_offset_correction;
};
/* The mvneta_tx_desc and mvneta_rx_desc structures describe the
@@ -1807,6 +1814,7 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
return -ENOMEM;
}
+ phys_addr += pp->rx_offset_correction;
mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
return 0;
}
@@ -2782,7 +2790,7 @@ static int mvneta_rxq_init(struct mvneta_port *pp,
mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
/* Set Offset */
- mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
+ mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD - pp->rx_offset_correction);
/* Set coalescing pkts and time */
mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
@@ -4033,6 +4041,13 @@ static int mvneta_probe(struct platform_device *pdev)
pp->rxq_def = rxq_def;
+ /* Set RX packet offset correction for platforms, whose
+* NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit
+* platforms and 0B for 32-bit ones.
+*/
+ pp->rx_offset_correction =
+ max(0, NET_SKB_PAD - MVNETA_RX_PKT_OFFSET_CORRECTION);
+
pp->indir[0] = rxq_def;
pp->clk = devm_clk_get(&pdev->dev, "core");
--
git-series 0.8.10
[PATCH v5 net-next 1/7] net: mvneta: Optimize rx path for small frame
For small frame reuse the phys_addr variable instead of accessing the uncacheable value in the rx descriptor. Signed-off-by: Gregory CLEMENT --- drivers/net/ethernet/marvell/mvneta.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index 87274d4ab102..1b84f746d748 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c @@ -1918,7 +1918,7 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int rx_todo, goto err_drop_frame; dma_sync_single_range_for_cpu(dev->dev.parent, - rx_desc->buf_phys_addr, + phys_addr, MVNETA_MH_SIZE + NET_SKB_PAD, rx_bytes, DMA_FROM_DEVICE); -- git-series 0.8.10
[PATCH v5 net-next 2/7] net: mvneta: Do not allocate buffer in rxq init with HWBM
For HWBM all buffers are allocated in mvneta_bm_construct() and in runtime
they are put into descriptors by hardware. There is no need to fill them
at this point.
Suggested-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 1b84f746d748..f5319c50f8d9 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -2784,14 +2784,14 @@ static int mvneta_rxq_init(struct mvneta_port *pp,
mvneta_rxq_buf_size_set(pp, rxq,
MVNETA_RX_BUF_SIZE(pp->pkt_size));
mvneta_rxq_bm_disable(pp, rxq);
+ mvneta_rxq_fill(pp, rxq, rxq->size);
} else {
mvneta_rxq_bm_enable(pp, rxq);
mvneta_rxq_long_pool_set(pp, rxq);
mvneta_rxq_short_pool_set(pp, rxq);
+ mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size);
}
- mvneta_rxq_fill(pp, rxq, rxq->size);
-
return 0;
}
--
git-series 0.8.10
[PATCH v5 net-next 3/7] net: mvneta: Use cacheable memory to store the rx buffer virtual address
Until now the virtual address of the received buffer were stored in the
cookie field of the rx descriptor. However, this field is 32-bits only
which prevents to use the driver on a 64-bits architecture.
With this patch the virtual address is stored in an array not shared with
the hardware (no more need to use the DMA API). Thanks to this, it is
possible to use cache contrary to the access of the rx descriptor member.
The change is done in the swbm path only because the hwbm uses the cookie
field, this also means that currently the hwbm is not usable in 64-bits.
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c | 34 +++-
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index f5319c50f8d9..92b9af14c352 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -561,6 +561,9 @@ struct mvneta_rx_queue {
u32 pkts_coal;
u32 time_coal;
+ /* Virtual address of the RX buffer */
+ void **buf_virt_addr;
+
/* Virtual address of the RX DMA descriptors array */
struct mvneta_rx_desc *descs;
@@ -1573,10 +1576,14 @@ static void mvneta_tx_done_pkts_coal_set(struct
mvneta_port *pp,
/* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
- u32 phys_addr, u32 cookie)
+ u32 phys_addr, void *virt_addr,
+ struct mvneta_rx_queue *rxq)
{
- rx_desc->buf_cookie = cookie;
+ int i;
+
rx_desc->buf_phys_addr = phys_addr;
+ i = rx_desc - rxq->descs;
+ rxq->buf_virt_addr[i] = virt_addr;
}
/* Decrement sent descriptors counter */
@@ -1781,7 +1788,8 @@ EXPORT_SYMBOL_GPL(mvneta_frag_free);
/* Refill processing for SW buffer management */
static int mvneta_rx_refill(struct mvneta_port *pp,
- struct mvneta_rx_desc *rx_desc)
+ struct mvneta_rx_desc *rx_desc,
+ struct mvneta_rx_queue *rxq)
{
dma_addr_t phys_addr;
@@ -1799,7 +1807,7 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
return -ENOMEM;
}
- mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
+ mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
return 0;
}
@@ -1861,7 +1869,7 @@ static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
for (i = 0; i < rxq->size; i++) {
struct mvneta_rx_desc *rx_desc = rxq->descs + i;
- void *data = (void *)rx_desc->buf_cookie;
+ void *data = rxq->buf_virt_addr[i];
dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
MVNETA_RX_BUF_SIZE(pp->pkt_size),
DMA_FROM_DEVICE);
@@ -1894,12 +1902,13 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int
rx_todo,
unsigned char *data;
dma_addr_t phys_addr;
u32 rx_status, frag_size;
- int rx_bytes, err;
+ int rx_bytes, err, index;
rx_done++;
rx_status = rx_desc->status;
rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
- data = (unsigned char *)rx_desc->buf_cookie;
+ index = rx_desc - rxq->descs;
+ data = rxq->buf_virt_addr[index];
phys_addr = rx_desc->buf_phys_addr;
if (!mvneta_rxq_desc_is_first_last(rx_status) ||
@@ -1938,7 +1947,7 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int
rx_todo,
}
/* Refill processing */
- err = mvneta_rx_refill(pp, rx_desc);
+ err = mvneta_rx_refill(pp, rx_desc, rxq);
if (err) {
netdev_err(dev, "Linux processing - Can't refill\n");
rxq->missed++;
@@ -2020,7 +2029,7 @@ static int mvneta_rx_hwbm(struct mvneta_port *pp, int
rx_todo,
rx_done++;
rx_status = rx_desc->status;
rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
- data = (unsigned char *)rx_desc->buf_cookie;
+ data = (u8 *)(uintptr_t)rx_desc->buf_cookie;
phys_addr = rx_desc->buf_phys_addr;
pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
bm_pool = &pp->bm_priv->bm_pools[pool_id];
@@ -2716,7 +2725,7 @@ static int mvneta_rxq_fill(struct mvneta_port *pp, struct
mvneta_rx_queue *rxq,
for (i = 0; i < num; i++) {
memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
- if (mvneta_rx_refill(pp, rxq->descs + i) !=
[PATCH v5 net-next 7/7] ARM64: dts: marvell: Add network support for Armada 3700
Add neta nodes for network support both in device tree for the SoC and
the board.
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 23 +++-
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 +++-
2 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 1372e9a6aaa4..c8b82e4145de 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -81,3 +81,26 @@
&pcie0 {
status = "okay";
};
+
+&mdio {
+ status = "okay";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+ð0 {
+ phy-mode = "rgmii-id";
+ phy = <&phy0>;
+ status = "okay";
+};
+
+ð1 {
+ phy-mode = "rgmii-id";
+ phy = <&phy1>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index e9bd58793464..3b8eb45bdc76 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -140,6 +140,29 @@
};
};
+ eth0: ethernet@3 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x3 0x4000>;
+ interrupts = ;
+ clocks = <&sb_periph_clk 8>;
+ status = "disabled";
+ };
+
+ mdio: mdio@32004 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0x32004 0x4>;
+ };
+
+ eth1: ethernet@4 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x4 0x4000>;
+ interrupts = ;
+ clocks = <&sb_periph_clk 7>;
+ status = "disabled";
+ };
+
usb3: usb@58000 {
compatible = "marvell,armada3700-xhci",
"generic-xhci";
--
git-series 0.8.10
[PATCH v5 net-next 0/7] Support Armada 37xx SoC (ARMv8 64-bits) in mvneta driver
Hi, The Armada 37xx is a new ARMv8 SoC from Marvell using same network controller as the older Armada 370/38x/XP SoCs. This series adapts the driver in order to be able to use it on this new SoC. The main changes are: - 64-bits support: the first patches allow using the driver on a 64-bit architecture. - MBUS support: the mbus configuration is different on Armada 37xx from the older SoCs. - per cpu interrupt: Armada 37xx do not support per cpu interrupt for the NETA IP, the non-per-CPU behavior was added back. The first patch is an optimization in the rx path in swbm mode. The second patch remove unnecessary allocation for HWBM. The first item is solved by patches 4 and 5. The 2 last items are solved by patch 6. In patch 7 the dt support is added. Beside Armada 37xx, this series have been again tested on Armada XP and Armada 38x (with Hardware Buffer Management and with Software Buffer Management). This is the 5th version of the series: - 1st version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/469588.html - 2nd version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/470476.html - 3rd version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/470901.html - 4th version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/471039.html Changelog: v4 -> v5: - remove unnecessary cast in patch 3 v3 -> v4: - Adding new patch: "net: mvneta: do not allocate buffer in rxq init with HWBM" - Simplify the HWBM case in patch 3 as suggested by Marcin v2 -> v3: - Adding patch 1 "Optimize rx path for small frame" - Fix the kbuild error by moving the "phys_addr += pp->rx_offset_correction;" line from patch 2 to patch 3 where rx_offset_correction is introduced. - Move the memory allocation of the buf_virt_addr of the rxq to be called by the probe function in order to avoid a memory leak. Thanks, Gregory Gregory CLEMENT (5): net: mvneta: Optimize rx path for small frame net: mvneta: Do not allocate buffer in rxq init with HWBM net: mvneta: Use cacheable memory to store the rx buffer virtual address net: mvneta: Only disable mvneta_bm for 64-bits ARM64: dts: marvell: Add network support for Armada 3700 Marcin Wojtas (2): net: mvneta: Convert to be 64 bits compatible net: mvneta: Add network support for Armada 3700 SoC Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 +- arch/arm64/boot/dts/marvell/armada-3720-db.dts| 23 +- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 +- drivers/net/ethernet/marvell/Kconfig | 10 +- drivers/net/ethernet/marvell/mvneta.c | 344 +++- 5 files changed, 305 insertions(+), 102 deletions(-) base-commit: 436accebb53021ef7c63535f60bda410aa87c136 -- git-series 0.8.10
[PATCH v5 net-next 6/7] net: mvneta: Add network support for Armada 3700 SoC
From: Marcin Wojtas
Armada 3700 is a new ARMv8 SoC from Marvell using same network controller
as older Armada 370/38x/XP. There are however some differences that
needed taking into account when adding support for it:
* open default MBUS window to 4GB of DRAM - Armada 3700 SoC's Mbus
configuration for network controller has to be done on two levels:
global and per-port. The first one is inherited from the
bootloader. The latter can be opened in a default way, leaving
arbitration to the bus controller. Hence filled mbus_dram_target_info
structure is not needed
* make per-CPU operation optional - Recent patches adding RSS and XPS
support for Armada 38x/XP enabled per-CPU operation of the controller
by default. Contrary to older SoC's Armada 3700 SoC's network
controller is not capable of per-CPU processing due to interrupt lines'
connectivity. This patch restores non-per-CPU operation, which is now
optional and depends on neta_armada3700 flag value in mvneta_port
structure. In order not to complicate the code, separate interrupt
subroutine is implemented.
For now, on the Armada 3700, RSS is disabled as the current
implementation depend on the per cpu interrupts.
[gregory.clem...@free-electrons.com: extract from a larger patch, replace
some ifdef and port to net-next for v4.10]
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 +-
drivers/net/ethernet/marvell/Kconfig | 7 +-
drivers/net/ethernet/marvell/mvneta.c | 287
+++-
3 files changed, 214 insertions(+), 87 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
index 73be8970815e..7aa840c8768d 100644
--- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
+++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
@@ -1,7 +1,10 @@
-* Marvell Armada 370 / Armada XP Ethernet Controller (NETA)
+* Marvell Armada 370 / Armada XP / Armada 3700 Ethernet Controller (NETA)
Required properties:
-- compatible: "marvell,armada-370-neta" or "marvell,armada-xp-neta".
+- compatible: could be one of the followings
+ "marvell,armada-370-neta"
+ "marvell,armada-xp-neta"
+ "marvell,armada-3700-neta"
- reg: address and length of the register set for the device.
- interrupts: interrupt for the device
- phy: See ethernet.txt file in the same directory.
diff --git a/drivers/net/ethernet/marvell/Kconfig
b/drivers/net/ethernet/marvell/Kconfig
index 2ccea9dd9248..3b8f11fe5e13 100644
--- a/drivers/net/ethernet/marvell/Kconfig
+++ b/drivers/net/ethernet/marvell/Kconfig
@@ -56,14 +56,15 @@ config MVNETA_BM_ENABLE
buffer management.
config MVNETA
- tristate "Marvell Armada 370/38x/XP network interface support"
- depends on PLAT_ORION || COMPILE_TEST
+ tristate "Marvell Armada 370/38x/XP/37xx network interface support"
+ depends on ARCH_MVEBU || COMPILE_TEST
depends on HAS_DMA
select MVMDIO
select FIXED_PHY
---help---
This driver supports the network interface units in the
- Marvell ARMADA XP, ARMADA 370 and ARMADA 38x SoC family.
+ Marvell ARMADA XP, ARMADA 370, ARMADA 38x and
+ ARMADA 37xx SoC family.
Note that this driver is distinct from the mv643xx_eth
driver, which should be used for the older Marvell SoCs
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 8ef03fb69bcd..ffc0c65068ea 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -397,6 +397,9 @@ struct mvneta_port {
spinlock_t lock;
bool is_stopped;
+ u32 cause_rx_tx;
+ struct napi_struct napi;
+
/* Core clock */
struct clk *clk;
/* AXI clock */
@@ -422,6 +425,9 @@ struct mvneta_port {
u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
+
+ /* Flags for special SoC configurations */
+ bool neta_armada3700;
u16 rx_offset_correction;
};
@@ -965,14 +971,9 @@ static int mvneta_mbus_io_win_set(struct mvneta_port *pp,
u32 base, u32 wsize,
return 0;
}
-/* Assign and initialize pools for port. In case of fail
- * buffer manager will remain disabled for current port.
- */
-static int mvneta_bm_port_init(struct platform_device *pdev,
- struct mvneta_port *pp)
+static int mvneta_bm_port_mbus_init(struct mvneta_port *pp)
{
- struct device_node *dn = pdev->dev.of_node;
- u32 long_pool_id, short_pool_id, wsize;
+ u32 wsize;
u
Re: [PATCH v4 net-next 3/7] net: mvneta: Use cacheable memory to store the rx buffer virtual address
Hi David, On mer., nov. 30 2016, David Miller wrote: > From: Gregory CLEMENT > Date: Tue, 29 Nov 2016 15:55:21 +0100 > >> +/* Virtual address of the RX buffer */ >> +void **buf_virt_addr; >> + >> /* Virtual address of the RX DMA descriptors array */ >> struct mvneta_rx_desc *descs; >> > ... >> +data = (unsigned char *)rxq->buf_virt_addr[index]; > > This cast is unnecessary, please remove it. OK I am doing it now. Thanks, Gregory -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
[PATCH v4 net-next 2/7] net: mvneta: Do not allocate buffer in rxq init with HWBM
For HWBM all buffers are allocated in mvneta_bm_construct() and in runtime
they are put into descriptors by hardware. There is no need to fill them
at this point.
Suggested-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 1b84f746d748..f5319c50f8d9 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -2784,14 +2784,14 @@ static int mvneta_rxq_init(struct mvneta_port *pp,
mvneta_rxq_buf_size_set(pp, rxq,
MVNETA_RX_BUF_SIZE(pp->pkt_size));
mvneta_rxq_bm_disable(pp, rxq);
+ mvneta_rxq_fill(pp, rxq, rxq->size);
} else {
mvneta_rxq_bm_enable(pp, rxq);
mvneta_rxq_long_pool_set(pp, rxq);
mvneta_rxq_short_pool_set(pp, rxq);
+ mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size);
}
- mvneta_rxq_fill(pp, rxq, rxq->size);
-
return 0;
}
--
git-series 0.8.10
[PATCH v4 net-next 1/7] net: mvneta: Optimize rx path for small frame
For small frame reuse the phys_addr variable instead of accessing the uncacheable value in the rx descriptor. Signed-off-by: Gregory CLEMENT --- drivers/net/ethernet/marvell/mvneta.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index 87274d4ab102..1b84f746d748 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c @@ -1918,7 +1918,7 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int rx_todo, goto err_drop_frame; dma_sync_single_range_for_cpu(dev->dev.parent, - rx_desc->buf_phys_addr, + phys_addr, MVNETA_MH_SIZE + NET_SKB_PAD, rx_bytes, DMA_FROM_DEVICE); -- git-series 0.8.10
[PATCH v4 net-next 3/7] net: mvneta: Use cacheable memory to store the rx buffer virtual address
Until now the virtual address of the received buffer were stored in the
cookie field of the rx descriptor. However, this field is 32-bits only
which prevents to use the driver on a 64-bits architecture.
With this patch the virtual address is stored in an array not shared with
the hardware (no more need to use the DMA API). Thanks to this, it is
possible to use cache contrary to the access of the rx descriptor member.
The change is done in the swbm path only because the hwbm uses the cookie
field, this also means that currently the hwbm is not usable in 64-bits.
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c | 34 +++-
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index f5319c50f8d9..b4810b0c0ffc 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -561,6 +561,9 @@ struct mvneta_rx_queue {
u32 pkts_coal;
u32 time_coal;
+ /* Virtual address of the RX buffer */
+ void **buf_virt_addr;
+
/* Virtual address of the RX DMA descriptors array */
struct mvneta_rx_desc *descs;
@@ -1573,10 +1576,14 @@ static void mvneta_tx_done_pkts_coal_set(struct
mvneta_port *pp,
/* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
- u32 phys_addr, u32 cookie)
+ u32 phys_addr, void *virt_addr,
+ struct mvneta_rx_queue *rxq)
{
- rx_desc->buf_cookie = cookie;
+ int i;
+
rx_desc->buf_phys_addr = phys_addr;
+ i = rx_desc - rxq->descs;
+ rxq->buf_virt_addr[i] = virt_addr;
}
/* Decrement sent descriptors counter */
@@ -1781,7 +1788,8 @@ EXPORT_SYMBOL_GPL(mvneta_frag_free);
/* Refill processing for SW buffer management */
static int mvneta_rx_refill(struct mvneta_port *pp,
- struct mvneta_rx_desc *rx_desc)
+ struct mvneta_rx_desc *rx_desc,
+ struct mvneta_rx_queue *rxq)
{
dma_addr_t phys_addr;
@@ -1799,7 +1807,7 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
return -ENOMEM;
}
- mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
+ mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
return 0;
}
@@ -1861,7 +1869,7 @@ static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
for (i = 0; i < rxq->size; i++) {
struct mvneta_rx_desc *rx_desc = rxq->descs + i;
- void *data = (void *)rx_desc->buf_cookie;
+ void *data = rxq->buf_virt_addr[i];
dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
MVNETA_RX_BUF_SIZE(pp->pkt_size),
DMA_FROM_DEVICE);
@@ -1894,12 +1902,13 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int
rx_todo,
unsigned char *data;
dma_addr_t phys_addr;
u32 rx_status, frag_size;
- int rx_bytes, err;
+ int rx_bytes, err, index;
rx_done++;
rx_status = rx_desc->status;
rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
- data = (unsigned char *)rx_desc->buf_cookie;
+ index = rx_desc - rxq->descs;
+ data = (unsigned char *)rxq->buf_virt_addr[index];
phys_addr = rx_desc->buf_phys_addr;
if (!mvneta_rxq_desc_is_first_last(rx_status) ||
@@ -1938,7 +1947,7 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int
rx_todo,
}
/* Refill processing */
- err = mvneta_rx_refill(pp, rx_desc);
+ err = mvneta_rx_refill(pp, rx_desc, rxq);
if (err) {
netdev_err(dev, "Linux processing - Can't refill\n");
rxq->missed++;
@@ -2020,7 +2029,7 @@ static int mvneta_rx_hwbm(struct mvneta_port *pp, int
rx_todo,
rx_done++;
rx_status = rx_desc->status;
rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
- data = (unsigned char *)rx_desc->buf_cookie;
+ data = (u8 *)(uintptr_t)rx_desc->buf_cookie;
phys_addr = rx_desc->buf_phys_addr;
pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
bm_pool = &pp->bm_priv->bm_pools[pool_id];
@@ -2716,7 +2725,7 @@ static int mvneta_rxq_fill(struct mvneta_port *pp, struct
mvneta_rx_queue *rxq,
for (i = 0; i < num; i++) {
memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
- if (mvnet
[PATCH v4 net-next 0/7] Support Armada 37xx SoC (ARMv8 64-bits) in mvneta driver
Hi, The Armada 37xx is a new ARMv8 SoC from Marvell using same network controller as the older Armada 370/38x/XP SoCs. This series adapts the driver in order to be able to use it on this new SoC. The main changes are: - 64-bits support: the first patches allow using the driver on a 64-bit architecture. - MBUS support: the mbus configuration is different on Armada 37xx from the older SoCs. - per cpu interrupt: Armada 37xx do not support per cpu interrupt for the NETA IP, the non-per-CPU behavior was added back. The first patch is an optimization in the rx path in swbm mode. The second patch remove unnecessary allocation for HWBM. The first item is solved by patches 4 and 5. The 2 last items are solved by patch 6. In patch 7 the dt support is added. Beside Armada 37xx, this series have been again tested on Armada XP and Armada 38x (with Hardware Buffer Management and with Software Buffer Management). This is the 4th version of the series: - 1st version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/469588.html - 2nd version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/470476.html -3rd version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/470901.html Changelog: v3 -> v4: - Adding new patch: "net: mvneta: do not allocate buffer in rxq init with HWBM" - Simplify the HWBM case in patch 3 as suggested by Marcin v2 -> v3: - Adding patch 1 "Optimize rx path for small frame" - Fix the kbuild error by moving the "phys_addr += pp->rx_offset_correction;" line from patch 2 to patch 3 where rx_offset_correction is introduced. - Move the memory allocation of the buf_virt_addr of the rxq to be called by the probe function in order to avoid a memory leak. Thanks, Gregory Gregory CLEMENT (5): net: mvneta: Optimize rx path for small frame net: mvneta: Do not allocate buffer in rxq init with HWBM net: mvneta: Use cacheable memory to store the rx buffer virtual address net: mvneta: Only disable mvneta_bm for 64-bits ARM64: dts: marvell: Add network support for Armada 3700 Marcin Wojtas (2): net: mvneta: Convert to be 64 bits compatible net: mvneta: Add network support for Armada 3700 SoC Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 +- arch/arm64/boot/dts/marvell/armada-3720-db.dts| 23 +- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 +- drivers/net/ethernet/marvell/Kconfig | 10 +- drivers/net/ethernet/marvell/mvneta.c | 344 +++- 5 files changed, 305 insertions(+), 102 deletions(-) base-commit: 436accebb53021ef7c63535f60bda410aa87c136 -- git-series 0.8.10
[PATCH v4 net-next 6/7] net: mvneta: Add network support for Armada 3700 SoC
From: Marcin Wojtas
Armada 3700 is a new ARMv8 SoC from Marvell using same network controller
as older Armada 370/38x/XP. There are however some differences that
needed taking into account when adding support for it:
* open default MBUS window to 4GB of DRAM - Armada 3700 SoC's Mbus
configuration for network controller has to be done on two levels:
global and per-port. The first one is inherited from the
bootloader. The latter can be opened in a default way, leaving
arbitration to the bus controller. Hence filled mbus_dram_target_info
structure is not needed
* make per-CPU operation optional - Recent patches adding RSS and XPS
support for Armada 38x/XP enabled per-CPU operation of the controller
by default. Contrary to older SoC's Armada 3700 SoC's network
controller is not capable of per-CPU processing due to interrupt lines'
connectivity. This patch restores non-per-CPU operation, which is now
optional and depends on neta_armada3700 flag value in mvneta_port
structure. In order not to complicate the code, separate interrupt
subroutine is implemented.
For now, on the Armada 3700, RSS is disabled as the current
implementation depend on the per cpu interrupts.
[gregory.clem...@free-electrons.com: extract from a larger patch, replace
some ifdef and port to net-next for v4.10]
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 +-
drivers/net/ethernet/marvell/Kconfig | 7 +-
drivers/net/ethernet/marvell/mvneta.c | 287
+++-
3 files changed, 214 insertions(+), 87 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
index 73be8970815e..7aa840c8768d 100644
--- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
+++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
@@ -1,7 +1,10 @@
-* Marvell Armada 370 / Armada XP Ethernet Controller (NETA)
+* Marvell Armada 370 / Armada XP / Armada 3700 Ethernet Controller (NETA)
Required properties:
-- compatible: "marvell,armada-370-neta" or "marvell,armada-xp-neta".
+- compatible: could be one of the followings
+ "marvell,armada-370-neta"
+ "marvell,armada-xp-neta"
+ "marvell,armada-3700-neta"
- reg: address and length of the register set for the device.
- interrupts: interrupt for the device
- phy: See ethernet.txt file in the same directory.
diff --git a/drivers/net/ethernet/marvell/Kconfig
b/drivers/net/ethernet/marvell/Kconfig
index 2ccea9dd9248..3b8f11fe5e13 100644
--- a/drivers/net/ethernet/marvell/Kconfig
+++ b/drivers/net/ethernet/marvell/Kconfig
@@ -56,14 +56,15 @@ config MVNETA_BM_ENABLE
buffer management.
config MVNETA
- tristate "Marvell Armada 370/38x/XP network interface support"
- depends on PLAT_ORION || COMPILE_TEST
+ tristate "Marvell Armada 370/38x/XP/37xx network interface support"
+ depends on ARCH_MVEBU || COMPILE_TEST
depends on HAS_DMA
select MVMDIO
select FIXED_PHY
---help---
This driver supports the network interface units in the
- Marvell ARMADA XP, ARMADA 370 and ARMADA 38x SoC family.
+ Marvell ARMADA XP, ARMADA 370, ARMADA 38x and
+ ARMADA 37xx SoC family.
Note that this driver is distinct from the mv643xx_eth
driver, which should be used for the older Marvell SoCs
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 6421402ef394..c12859201f5d 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -397,6 +397,9 @@ struct mvneta_port {
spinlock_t lock;
bool is_stopped;
+ u32 cause_rx_tx;
+ struct napi_struct napi;
+
/* Core clock */
struct clk *clk;
/* AXI clock */
@@ -422,6 +425,9 @@ struct mvneta_port {
u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
+
+ /* Flags for special SoC configurations */
+ bool neta_armada3700;
u16 rx_offset_correction;
};
@@ -965,14 +971,9 @@ static int mvneta_mbus_io_win_set(struct mvneta_port *pp,
u32 base, u32 wsize,
return 0;
}
-/* Assign and initialize pools for port. In case of fail
- * buffer manager will remain disabled for current port.
- */
-static int mvneta_bm_port_init(struct platform_device *pdev,
- struct mvneta_port *pp)
+static int mvneta_bm_port_mbus_init(struct mvneta_port *pp)
{
- struct device_node *dn = pdev->dev.of_node;
- u32 long_pool_id, short_pool_id, wsize;
+ u32 wsize;
u
[PATCH v4 net-next 7/7] ARM64: dts: marvell: Add network support for Armada 3700
Add neta nodes for network support both in device tree for the SoC and
the board.
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 23 +++-
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 +++-
2 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 1372e9a6aaa4..c8b82e4145de 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -81,3 +81,26 @@
&pcie0 {
status = "okay";
};
+
+&mdio {
+ status = "okay";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+ð0 {
+ phy-mode = "rgmii-id";
+ phy = <&phy0>;
+ status = "okay";
+};
+
+ð1 {
+ phy-mode = "rgmii-id";
+ phy = <&phy1>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index e9bd58793464..3b8eb45bdc76 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -140,6 +140,29 @@
};
};
+ eth0: ethernet@3 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x3 0x4000>;
+ interrupts = ;
+ clocks = <&sb_periph_clk 8>;
+ status = "disabled";
+ };
+
+ mdio: mdio@32004 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0x32004 0x4>;
+ };
+
+ eth1: ethernet@4 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x4 0x4000>;
+ interrupts = ;
+ clocks = <&sb_periph_clk 7>;
+ status = "disabled";
+ };
+
usb3: usb@58000 {
compatible = "marvell,armada3700-xhci",
"generic-xhci";
--
git-series 0.8.10
[PATCH v4 net-next 5/7] net: mvneta: Only disable mvneta_bm for 64-bits
Actually only the mvneta_bm support is not 64-bits compatible. The mvneta code itself can run on 64-bits architecture. Signed-off-by: Gregory CLEMENT --- drivers/net/ethernet/marvell/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/Kconfig b/drivers/net/ethernet/marvell/Kconfig index 66fd9dbb2ca7..2ccea9dd9248 100644 --- a/drivers/net/ethernet/marvell/Kconfig +++ b/drivers/net/ethernet/marvell/Kconfig @@ -44,6 +44,7 @@ config MVMDIO config MVNETA_BM_ENABLE tristate "Marvell Armada 38x/XP network interface BM support" depends on MVNETA + depends on !64BIT ---help--- This driver supports auxiliary block of the network interface units in the Marvell ARMADA XP and ARMADA 38x SoC @@ -58,7 +59,6 @@ config MVNETA tristate "Marvell Armada 370/38x/XP network interface support" depends on PLAT_ORION || COMPILE_TEST depends on HAS_DMA - depends on !64BIT select MVMDIO select FIXED_PHY ---help--- @@ -71,6 +71,7 @@ config MVNETA config MVNETA_BM tristate + depends on !64BIT default y if MVNETA=y && MVNETA_BM_ENABLE!=n default MVNETA_BM_ENABLE select HWBM -- git-series 0.8.10
[PATCH v4 net-next 4/7] net: mvneta: Convert to be 64 bits compatible
From: Marcin Wojtas
Prepare the mvneta driver in order to be usable on the 64 bits platform
such as the Armada 3700.
[gregory.clem...@free-electrons.com]: this patch was extract from a larger
one to ease review and maintenance.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index b4810b0c0ffc..6421402ef394 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -296,6 +296,12 @@
/* descriptor aligned size */
#define MVNETA_DESC_ALIGNED_SIZE 32
+/* Number of bytes to be taken into account by HW when putting incoming data
+ * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet
+ * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
+ */
+#define MVNETA_RX_PKT_OFFSET_CORRECTION64
+
#define MVNETA_RX_PKT_SIZE(mtu) \
ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
ETH_HLEN + ETH_FCS_LEN,\
@@ -416,6 +422,7 @@ struct mvneta_port {
u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
+ u16 rx_offset_correction;
};
/* The mvneta_tx_desc and mvneta_rx_desc structures describe the
@@ -1807,6 +1814,7 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
return -ENOMEM;
}
+ phys_addr += pp->rx_offset_correction;
mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
return 0;
}
@@ -2782,7 +2790,7 @@ static int mvneta_rxq_init(struct mvneta_port *pp,
mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
/* Set Offset */
- mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
+ mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD - pp->rx_offset_correction);
/* Set coalescing pkts and time */
mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
@@ -4033,6 +4041,13 @@ static int mvneta_probe(struct platform_device *pdev)
pp->rxq_def = rxq_def;
+ /* Set RX packet offset correction for platforms, whose
+* NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit
+* platforms and 0B for 32-bit ones.
+*/
+ pp->rx_offset_correction =
+ max(0, NET_SKB_PAD - MVNETA_RX_PKT_OFFSET_CORRECTION);
+
pp->indir[0] = rxq_def;
pp->clk = devm_clk_get(&pdev->dev, "core");
--
git-series 0.8.10
Re: [PATCH v3 net-next 2/6] net: mvneta: Use cacheable memory to store the rx buffer virtual address
Hi Marcin,
On mar., nov. 29 2016, Marcin Wojtas wrote:
> Gregory,
>
> 2016-11-29 11:19 GMT+01:00 Gregory CLEMENT
> :
>> Hi Marcin,
>>
>> On mar., nov. 29 2016, Marcin Wojtas wrote:
>>
>>> Hi Gregory,
>>>
>>> Another remark below, sorry for noise.
>>>
>>> 2016-11-29 10:37 GMT+01:00 Gregory CLEMENT
>>> :
>>>> Until now the virtual address of the received buffer were stored in the
>>>> cookie field of the rx descriptor. However, this field is 32-bits only
>>>> which prevents to use the driver on a 64-bits architecture.
>>>>
>>>> With this patch the virtual address is stored in an array not shared with
>>>> the hardware (no more need to use the DMA API). Thanks to this, it is
>>>> possible to use cache contrary to the access of the rx descriptor member.
>>>>
>>>> The change is done in the swbm path only because the hwbm uses the cookie
>>>> field, this also means that currently the hwbm is not usable in 64-bits.
>>>>
>>>> Signed-off-by: Gregory CLEMENT
>>>> ---
>>>> drivers/net/ethernet/marvell/mvneta.c | 93
>>>> 1 file changed, 81 insertions(+), 12 deletions(-)
>>>>
>>>> diff --git a/drivers/net/ethernet/marvell/mvneta.c
>>>> b/drivers/net/ethernet/marvell/mvneta.c
>>>> index 1b84f746d748..32b142d0e44e 100644
>>>> --- a/drivers/net/ethernet/marvell/mvneta.c
>>>> +++ b/drivers/net/ethernet/marvell/mvneta.c
>>>> @@ -561,6 +561,9 @@ struct mvneta_rx_queue {
>>>> u32 pkts_coal;
>>>> u32 time_coal;
>>>>
>>>> + /* Virtual address of the RX buffer */
>>>> + void **buf_virt_addr;
>>>> +
>>>> /* Virtual address of the RX DMA descriptors array */
>>>> struct mvneta_rx_desc *descs;
>>>>
>>>> @@ -1573,10 +1576,14 @@ static void mvneta_tx_done_pkts_coal_set(struct
>>>> mvneta_port *pp,
>>>>
>>>> /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
>>>> static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
>>>> - u32 phys_addr, u32 cookie)
>>>> + u32 phys_addr, void *virt_addr,
>>>> + struct mvneta_rx_queue *rxq)
>>>> {
>>>> - rx_desc->buf_cookie = cookie;
>>>> + int i;
>>>> +
>>>> rx_desc->buf_phys_addr = phys_addr;
>>>> + i = rx_desc - rxq->descs;
>>>> + rxq->buf_virt_addr[i] = virt_addr;
>>>> }
>>>>
>>>> /* Decrement sent descriptors counter */
>>>> @@ -1781,7 +1788,8 @@ EXPORT_SYMBOL_GPL(mvneta_frag_free);
>>>>
>>>> /* Refill processing for SW buffer management */
>>>> static int mvneta_rx_refill(struct mvneta_port *pp,
>>>> - struct mvneta_rx_desc *rx_desc)
>>>> + struct mvneta_rx_desc *rx_desc,
>>>> + struct mvneta_rx_queue *rxq)
>>>>
>>>> {
>>>> dma_addr_t phys_addr;
>>>> @@ -1799,7 +1807,7 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
>>>> return -ENOMEM;
>>>> }
>>>>
>>>> - mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
>>>> + mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
>>>> return 0;
>>>> }
>>>>
>>>> @@ -1861,7 +1869,12 @@ static void mvneta_rxq_drop_pkts(struct mvneta_port
>>>> *pp,
>>>>
>>>> for (i = 0; i < rxq->size; i++) {
>>>> struct mvneta_rx_desc *rx_desc = rxq->descs + i;
>>>> - void *data = (void *)rx_desc->buf_cookie;
>>>> + void *data;
>>>> +
>>>> + if (!pp->bm_priv)
>>>> + data = rxq->buf_virt_addr[i];
>>>> + else
>>>> + data = (void *)(uintptr_t)rx_desc->buf_cookie;
>>>
>>> Dropping packets for HWBM (in fact returning dropped buffers to the
>>> pool) is done a couple of lines above. This point will never be
>>
>> indeed I changed the code at every place the buf_cookie was used and
>> missed the fact that for HWBM this code was never reached.
>>
>>> reached with HWBM enabled (and it's also incorrect).
>>
>> What is incorrect?
>>
>
> Possible dma_unmapping + mvneta_frag_free for buffers in HWBM, when
> dropping packets.
Yes sure, but as you mentioned this code is never reached when HWBM is
enabled. I thought there was other part of the code to fix.
Thanks,
Gregory
>
> Thanks,
> Marcin
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v3 net-next 2/6] net: mvneta: Use cacheable memory to store the rx buffer virtual address
Hi Marcin,
On mar., nov. 29 2016, Marcin Wojtas wrote:
> Hi Gregory,
>
> Another remark below, sorry for noise.
>
> 2016-11-29 10:37 GMT+01:00 Gregory CLEMENT
> :
>> Until now the virtual address of the received buffer were stored in the
>> cookie field of the rx descriptor. However, this field is 32-bits only
>> which prevents to use the driver on a 64-bits architecture.
>>
>> With this patch the virtual address is stored in an array not shared with
>> the hardware (no more need to use the DMA API). Thanks to this, it is
>> possible to use cache contrary to the access of the rx descriptor member.
>>
>> The change is done in the swbm path only because the hwbm uses the cookie
>> field, this also means that currently the hwbm is not usable in 64-bits.
>>
>> Signed-off-by: Gregory CLEMENT
>> ---
>> drivers/net/ethernet/marvell/mvneta.c | 93
>> 1 file changed, 81 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/marvell/mvneta.c
>> b/drivers/net/ethernet/marvell/mvneta.c
>> index 1b84f746d748..32b142d0e44e 100644
>> --- a/drivers/net/ethernet/marvell/mvneta.c
>> +++ b/drivers/net/ethernet/marvell/mvneta.c
>> @@ -561,6 +561,9 @@ struct mvneta_rx_queue {
>> u32 pkts_coal;
>> u32 time_coal;
>>
>> + /* Virtual address of the RX buffer */
>> + void **buf_virt_addr;
>> +
>> /* Virtual address of the RX DMA descriptors array */
>> struct mvneta_rx_desc *descs;
>>
>> @@ -1573,10 +1576,14 @@ static void mvneta_tx_done_pkts_coal_set(struct
>> mvneta_port *pp,
>>
>> /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
>> static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
>> - u32 phys_addr, u32 cookie)
>> + u32 phys_addr, void *virt_addr,
>> + struct mvneta_rx_queue *rxq)
>> {
>> - rx_desc->buf_cookie = cookie;
>> + int i;
>> +
>> rx_desc->buf_phys_addr = phys_addr;
>> + i = rx_desc - rxq->descs;
>> + rxq->buf_virt_addr[i] = virt_addr;
>> }
>>
>> /* Decrement sent descriptors counter */
>> @@ -1781,7 +1788,8 @@ EXPORT_SYMBOL_GPL(mvneta_frag_free);
>>
>> /* Refill processing for SW buffer management */
>> static int mvneta_rx_refill(struct mvneta_port *pp,
>> - struct mvneta_rx_desc *rx_desc)
>> + struct mvneta_rx_desc *rx_desc,
>> + struct mvneta_rx_queue *rxq)
>>
>> {
>> dma_addr_t phys_addr;
>> @@ -1799,7 +1807,7 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
>> return -ENOMEM;
>> }
>>
>> - mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
>> + mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
>> return 0;
>> }
>>
>> @@ -1861,7 +1869,12 @@ static void mvneta_rxq_drop_pkts(struct mvneta_port
>> *pp,
>>
>> for (i = 0; i < rxq->size; i++) {
>> struct mvneta_rx_desc *rx_desc = rxq->descs + i;
>> - void *data = (void *)rx_desc->buf_cookie;
>> + void *data;
>> +
>> + if (!pp->bm_priv)
>> + data = rxq->buf_virt_addr[i];
>> + else
>> + data = (void *)(uintptr_t)rx_desc->buf_cookie;
>
> Dropping packets for HWBM (in fact returning dropped buffers to the
> pool) is done a couple of lines above. This point will never be
indeed I changed the code at every place the buf_cookie was used and
missed the fact that for HWBM this code was never reached.
> reached with HWBM enabled (and it's also incorrect).
What is incorrect?
Gregory
>
> Best regards,
> Marcin
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v3 net-next 2/6] net: mvneta: Use cacheable memory to store the rx buffer virtual address
Hi Marcin,
On mar., nov. 29 2016, Marcin Wojtas wrote:
> Hi Gregory,
>
> Apparently HWBM had a mistake in implementation, please see below.
>
> 2016-11-29 10:37 GMT+01:00 Gregory CLEMENT
> :
>> Until now the virtual address of the received buffer were stored in the
>> cookie field of the rx descriptor. However, this field is 32-bits only
>> which prevents to use the driver on a 64-bits architecture.
>>
>> With this patch the virtual address is stored in an array not shared with
>> the hardware (no more need to use the DMA API). Thanks to this, it is
>> possible to use cache contrary to the access of the rx descriptor member.
>>
>> The change is done in the swbm path only because the hwbm uses the cookie
>> field, this also means that currently the hwbm is not usable in 64-bits.
>>
>> Signed-off-by: Gregory CLEMENT
>> ---
>> drivers/net/ethernet/marvell/mvneta.c | 93
>> 1 file changed, 81 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/marvell/mvneta.c
>> b/drivers/net/ethernet/marvell/mvneta.c
>> index 1b84f746d748..32b142d0e44e 100644
>> --- a/drivers/net/ethernet/marvell/mvneta.c
>> +++ b/drivers/net/ethernet/marvell/mvneta.c
>> @@ -561,6 +561,9 @@ struct mvneta_rx_queue {
>> u32 pkts_coal;
>> u32 time_coal;
>>
>> + /* Virtual address of the RX buffer */
>> + void **buf_virt_addr;
>> +
>> /* Virtual address of the RX DMA descriptors array */
>> struct mvneta_rx_desc *descs;
>>
>> @@ -1573,10 +1576,14 @@ static void mvneta_tx_done_pkts_coal_set(struct
>> mvneta_port *pp,
>>
>> /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
>> static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
>> - u32 phys_addr, u32 cookie)
>> + u32 phys_addr, void *virt_addr,
>> + struct mvneta_rx_queue *rxq)
>> {
>> - rx_desc->buf_cookie = cookie;
>> + int i;
>> +
>> rx_desc->buf_phys_addr = phys_addr;
>> + i = rx_desc - rxq->descs;
>> + rxq->buf_virt_addr[i] = virt_addr;
>> }
>>
>> /* Decrement sent descriptors counter */
>> @@ -1781,7 +1788,8 @@ EXPORT_SYMBOL_GPL(mvneta_frag_free);
>>
>> /* Refill processing for SW buffer management */
>> static int mvneta_rx_refill(struct mvneta_port *pp,
>> - struct mvneta_rx_desc *rx_desc)
>> + struct mvneta_rx_desc *rx_desc,
>> + struct mvneta_rx_queue *rxq)
>>
>> {
>> dma_addr_t phys_addr;
>> @@ -1799,7 +1807,7 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
>> return -ENOMEM;
>> }
>>
>> - mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
>> + mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
>> return 0;
>> }
>>
>> @@ -1861,7 +1869,12 @@ static void mvneta_rxq_drop_pkts(struct mvneta_port
>> *pp,
>>
>> for (i = 0; i < rxq->size; i++) {
>> struct mvneta_rx_desc *rx_desc = rxq->descs + i;
>> - void *data = (void *)rx_desc->buf_cookie;
>> + void *data;
>> +
>> + if (!pp->bm_priv)
>> + data = rxq->buf_virt_addr[i];
>> + else
>> + data = (void *)(uintptr_t)rx_desc->buf_cookie;
>>
>> dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
>> MVNETA_RX_BUF_SIZE(pp->pkt_size),
>> DMA_FROM_DEVICE);
>> @@ -1894,12 +1907,13 @@ static int mvneta_rx_swbm(struct mvneta_port *pp,
>> int rx_todo,
>> unsigned char *data;
>> dma_addr_t phys_addr;
>> u32 rx_status, frag_size;
>> - int rx_bytes, err;
>> + int rx_bytes, err, index;
>>
>> rx_done++;
>> rx_status = rx_desc->status;
>> rx_bytes = rx_desc->data_size - (ETH_FCS_LEN +
>> MVNETA_MH_SIZE);
>> - data = (unsigned char *)rx_desc->buf_cookie;
>> + index = rx_desc - rxq->descs;
>> + data = (unsigned char *)rxq->buf_virt_addr[index];
>> phys_addr = rx_desc->buf_phys_addr;
>>
>> if (!mvneta_rxq_de
Re: [PATCH v3 net-next 0/6] Support Armada 37xx SoC (ARMv8 64-bits) in mvneta driver
Hi, On mar., nov. 29 2016, Gregory CLEMENT wrote: > Hi, > > The Armada 37xx is a new ARMv8 SoC from Marvell using same network > controller as the older Armada 370/38x/XP SoCs. This series adapts the > driver in order to be able to use it on this new SoC. The main changes > are: > > - 64-bits support: the first patches allow using the driver on a 64-bit > architecture. > > - MBUS support: the mbus configuration is different on Armada 37xx > from the older SoCs. > > - per cpu interrupt: Armada 37xx do not support per cpu interrupt for > the NETA IP, the non-per-CPU behavior was added back. > > The first item is solved by patches 1 to 3. > The 2 last items are solved by patch 4. > In patch 5 the dt support is added. > > Beside Armada 37xx, the series have been tested on Armada XP and > Armada 38x (with Hardware Buffer Management and with Software Buffer > Managment). > > Thanks, > I forgot to commit my cover with git series, so it was the old one. It should have been the following one: Hi, The Armada 37xx is a new ARMv8 SoC from Marvell using same network controller as the older Armada 370/38x/XP SoCs. This series adapts the driver in order to be able to use it on this new SoC. The main changes are: - 64-bits support: the first patches allow using the driver on a 64-bit architecture. - MBUS support: the mbus configuration is different on Armada 37xx from the older SoCs. - per cpu interrupt: Armada 37xx do not support per cpu interrupt for the NETA IP, the non-per-CPU behavior was added back. The first patch is an optimization in the rx path in swbm mode. The first item is solved by patches 2 to 3. The 2 last items are solved by patch 5. In patch 6 the dt support is added. Beside Armada 37xx, this new series have been again tested on Armada XP and Armada 38x (with Hardware Buffer Management and with Software Buffer Management). This is the 3th version of the series: - 1st version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/469588.html - 2nd version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/470476.html Changelog: v2 -> v3: - Adding patch 1 "Optimize rx path for small frame" - Fix the kbuild error by moving the "phys_addr += pp->rx_offset_correction;" line from patch 2 to patch 3 where rx_offset_correction is introduced. - Move the memory allocation of the buf_virt_addr of the rxq to be called by the probe function in order to avoid a memory leak. > Gregory > > Gregory CLEMENT (4): > net: mvneta: Optimize rx path for small frame > net: mvneta: Use cacheable memory to store the rx buffer virtual address > net: mvneta: Only disable mvneta_bm for 64-bits > ARM64: dts: marvell: Add network support for Armada 3700 > > Marcin Wojtas (2): > net: mvneta: Convert to be 64 bits compatible > net: mvneta: Add network support for Armada 3700 SoC > > Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 +- > arch/arm64/boot/dts/marvell/armada-3720-db.dts| 23 - > arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 - > drivers/net/ethernet/marvell/Kconfig | 10 +- > drivers/net/ethernet/marvell/mvneta.c | 400 > ++------ > 5 files changed, 361 insertions(+), 102 deletions(-) > > base-commit: 436accebb53021ef7c63535f60bda410aa87c136 > -- > git-series 0.8.10 -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
[PATCH v3 net-next 2/6] net: mvneta: Use cacheable memory to store the rx buffer virtual address
Until now the virtual address of the received buffer were stored in the
cookie field of the rx descriptor. However, this field is 32-bits only
which prevents to use the driver on a 64-bits architecture.
With this patch the virtual address is stored in an array not shared with
the hardware (no more need to use the DMA API). Thanks to this, it is
possible to use cache contrary to the access of the rx descriptor member.
The change is done in the swbm path only because the hwbm uses the cookie
field, this also means that currently the hwbm is not usable in 64-bits.
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c | 93
1 file changed, 81 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 1b84f746d748..32b142d0e44e 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -561,6 +561,9 @@ struct mvneta_rx_queue {
u32 pkts_coal;
u32 time_coal;
+ /* Virtual address of the RX buffer */
+ void **buf_virt_addr;
+
/* Virtual address of the RX DMA descriptors array */
struct mvneta_rx_desc *descs;
@@ -1573,10 +1576,14 @@ static void mvneta_tx_done_pkts_coal_set(struct
mvneta_port *pp,
/* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
- u32 phys_addr, u32 cookie)
+ u32 phys_addr, void *virt_addr,
+ struct mvneta_rx_queue *rxq)
{
- rx_desc->buf_cookie = cookie;
+ int i;
+
rx_desc->buf_phys_addr = phys_addr;
+ i = rx_desc - rxq->descs;
+ rxq->buf_virt_addr[i] = virt_addr;
}
/* Decrement sent descriptors counter */
@@ -1781,7 +1788,8 @@ EXPORT_SYMBOL_GPL(mvneta_frag_free);
/* Refill processing for SW buffer management */
static int mvneta_rx_refill(struct mvneta_port *pp,
- struct mvneta_rx_desc *rx_desc)
+ struct mvneta_rx_desc *rx_desc,
+ struct mvneta_rx_queue *rxq)
{
dma_addr_t phys_addr;
@@ -1799,7 +1807,7 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
return -ENOMEM;
}
- mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
+ mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
return 0;
}
@@ -1861,7 +1869,12 @@ static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
for (i = 0; i < rxq->size; i++) {
struct mvneta_rx_desc *rx_desc = rxq->descs + i;
- void *data = (void *)rx_desc->buf_cookie;
+ void *data;
+
+ if (!pp->bm_priv)
+ data = rxq->buf_virt_addr[i];
+ else
+ data = (void *)(uintptr_t)rx_desc->buf_cookie;
dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
MVNETA_RX_BUF_SIZE(pp->pkt_size),
DMA_FROM_DEVICE);
@@ -1894,12 +1907,13 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int
rx_todo,
unsigned char *data;
dma_addr_t phys_addr;
u32 rx_status, frag_size;
- int rx_bytes, err;
+ int rx_bytes, err, index;
rx_done++;
rx_status = rx_desc->status;
rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
- data = (unsigned char *)rx_desc->buf_cookie;
+ index = rx_desc - rxq->descs;
+ data = (unsigned char *)rxq->buf_virt_addr[index];
phys_addr = rx_desc->buf_phys_addr;
if (!mvneta_rxq_desc_is_first_last(rx_status) ||
@@ -1938,7 +1952,7 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int
rx_todo,
}
/* Refill processing */
- err = mvneta_rx_refill(pp, rx_desc);
+ err = mvneta_rx_refill(pp, rx_desc, rxq);
if (err) {
netdev_err(dev, "Linux processing - Can't refill\n");
rxq->missed++;
@@ -2020,7 +2034,7 @@ static int mvneta_rx_hwbm(struct mvneta_port *pp, int
rx_todo,
rx_done++;
rx_status = rx_desc->status;
rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
- data = (unsigned char *)rx_desc->buf_cookie;
+ data = (u8 *)(uintptr_t)rx_desc->buf_cookie;
phys_addr = rx_desc->buf_phys_addr;
pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
bm_pool = &pp->bm_priv->bm_pools[pool_id];
@@ -2708,6 +2722,56 @@ static int mvneta_poll(struct napi_struct *napi, int
budget)
retur
[PATCH v3 net-next 1/6] net: mvneta: Optimize rx path for small frame
For small frame reuse the phys_addr variable instead of accessing the uncacheable value in the rx descriptor. Signed-off-by: Gregory CLEMENT --- drivers/net/ethernet/marvell/mvneta.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index 87274d4ab102..1b84f746d748 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c @@ -1918,7 +1918,7 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int rx_todo, goto err_drop_frame; dma_sync_single_range_for_cpu(dev->dev.parent, - rx_desc->buf_phys_addr, + phys_addr, MVNETA_MH_SIZE + NET_SKB_PAD, rx_bytes, DMA_FROM_DEVICE); -- git-series 0.8.10
[PATCH v3 net-next 4/6] net: mvneta: Only disable mvneta_bm for 64-bits
Actually only the mvneta_bm support is not 64-bits compatible. The mvneta code itself can run on 64-bits architecture. Signed-off-by: Gregory CLEMENT --- drivers/net/ethernet/marvell/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/Kconfig b/drivers/net/ethernet/marvell/Kconfig index 66fd9dbb2ca7..2ccea9dd9248 100644 --- a/drivers/net/ethernet/marvell/Kconfig +++ b/drivers/net/ethernet/marvell/Kconfig @@ -44,6 +44,7 @@ config MVMDIO config MVNETA_BM_ENABLE tristate "Marvell Armada 38x/XP network interface BM support" depends on MVNETA + depends on !64BIT ---help--- This driver supports auxiliary block of the network interface units in the Marvell ARMADA XP and ARMADA 38x SoC @@ -58,7 +59,6 @@ config MVNETA tristate "Marvell Armada 370/38x/XP network interface support" depends on PLAT_ORION || COMPILE_TEST depends on HAS_DMA - depends on !64BIT select MVMDIO select FIXED_PHY ---help--- @@ -71,6 +71,7 @@ config MVNETA config MVNETA_BM tristate + depends on !64BIT default y if MVNETA=y && MVNETA_BM_ENABLE!=n default MVNETA_BM_ENABLE select HWBM -- git-series 0.8.10
[PATCH v3 net-next 5/6] net: mvneta: Add network support for Armada 3700 SoC
From: Marcin Wojtas
Armada 3700 is a new ARMv8 SoC from Marvell using same network controller
as older Armada 370/38x/XP. There are however some differences that
needed taking into account when adding support for it:
* open default MBUS window to 4GB of DRAM - Armada 3700 SoC's Mbus
configuration for network controller has to be done on two levels:
global and per-port. The first one is inherited from the
bootloader. The latter can be opened in a default way, leaving
arbitration to the bus controller. Hence filled mbus_dram_target_info
structure is not needed
* make per-CPU operation optional - Recent patches adding RSS and XPS
support for Armada 38x/XP enabled per-CPU operation of the controller
by default. Contrary to older SoC's Armada 3700 SoC's network
controller is not capable of per-CPU processing due to interrupt lines'
connectivity. This patch restores non-per-CPU operation, which is now
optional and depends on neta_armada3700 flag value in mvneta_port
structure. In order not to complicate the code, separate interrupt
subroutine is implemented.
For now, on the Armada 3700, RSS is disabled as the current
implementation depend on the per cpu interrupts.
[gregory.clem...@free-electrons.com: extract from a larger patch, replace
some ifdef and port to net-next for v4.10]
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 +-
drivers/net/ethernet/marvell/Kconfig | 7 +-
drivers/net/ethernet/marvell/mvneta.c | 287
+++-
3 files changed, 214 insertions(+), 87 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
index 73be8970815e..7aa840c8768d 100644
--- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
+++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
@@ -1,7 +1,10 @@
-* Marvell Armada 370 / Armada XP Ethernet Controller (NETA)
+* Marvell Armada 370 / Armada XP / Armada 3700 Ethernet Controller (NETA)
Required properties:
-- compatible: "marvell,armada-370-neta" or "marvell,armada-xp-neta".
+- compatible: could be one of the followings
+ "marvell,armada-370-neta"
+ "marvell,armada-xp-neta"
+ "marvell,armada-3700-neta"
- reg: address and length of the register set for the device.
- interrupts: interrupt for the device
- phy: See ethernet.txt file in the same directory.
diff --git a/drivers/net/ethernet/marvell/Kconfig
b/drivers/net/ethernet/marvell/Kconfig
index 2ccea9dd9248..3b8f11fe5e13 100644
--- a/drivers/net/ethernet/marvell/Kconfig
+++ b/drivers/net/ethernet/marvell/Kconfig
@@ -56,14 +56,15 @@ config MVNETA_BM_ENABLE
buffer management.
config MVNETA
- tristate "Marvell Armada 370/38x/XP network interface support"
- depends on PLAT_ORION || COMPILE_TEST
+ tristate "Marvell Armada 370/38x/XP/37xx network interface support"
+ depends on ARCH_MVEBU || COMPILE_TEST
depends on HAS_DMA
select MVMDIO
select FIXED_PHY
---help---
This driver supports the network interface units in the
- Marvell ARMADA XP, ARMADA 370 and ARMADA 38x SoC family.
+ Marvell ARMADA XP, ARMADA 370, ARMADA 38x and
+ ARMADA 37xx SoC family.
Note that this driver is distinct from the mv643xx_eth
driver, which should be used for the older Marvell SoCs
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index a8bd0d83028f..99cee88d5052 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -397,6 +397,9 @@ struct mvneta_port {
spinlock_t lock;
bool is_stopped;
+ u32 cause_rx_tx;
+ struct napi_struct napi;
+
/* Core clock */
struct clk *clk;
/* AXI clock */
@@ -422,6 +425,9 @@ struct mvneta_port {
u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
+
+ /* Flags for special SoC configurations */
+ bool neta_armada3700;
u16 rx_offset_correction;
};
@@ -965,14 +971,9 @@ static int mvneta_mbus_io_win_set(struct mvneta_port *pp,
u32 base, u32 wsize,
return 0;
}
-/* Assign and initialize pools for port. In case of fail
- * buffer manager will remain disabled for current port.
- */
-static int mvneta_bm_port_init(struct platform_device *pdev,
- struct mvneta_port *pp)
+static int mvneta_bm_port_mbus_init(struct mvneta_port *pp)
{
- struct device_node *dn = pdev->dev.of_node;
- u32 long_pool_id, short_pool_id, wsize;
+ u32 wsize;
u
[PATCH v3 net-next 3/6] net: mvneta: Convert to be 64 bits compatible
From: Marcin Wojtas
Prepare the mvneta driver in order to be usable on the 64 bits platform
such as the Armada 3700.
[gregory.clem...@free-electrons.com]: this patch was extract from a larger
one to ease review and maintenance.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 32b142d0e44e..a8bd0d83028f 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -296,6 +296,12 @@
/* descriptor aligned size */
#define MVNETA_DESC_ALIGNED_SIZE 32
+/* Number of bytes to be taken into account by HW when putting incoming data
+ * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet
+ * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
+ */
+#define MVNETA_RX_PKT_OFFSET_CORRECTION64
+
#define MVNETA_RX_PKT_SIZE(mtu) \
ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
ETH_HLEN + ETH_FCS_LEN,\
@@ -416,6 +422,7 @@ struct mvneta_port {
u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
+ u16 rx_offset_correction;
};
/* The mvneta_tx_desc and mvneta_rx_desc structures describe the
@@ -1807,6 +1814,7 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
return -ENOMEM;
}
+ phys_addr += pp->rx_offset_correction;
mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
return 0;
}
@@ -2742,6 +2750,7 @@ static int mvneta_rx_hwbm_refill(struct mvneta_port *pp,
return -ENOMEM;
}
+ phys_addr += pp->rx_offset_correction;
rx_desc->buf_phys_addr = phys_addr;
rx_desc->buf_cookie = (uintptr_t)data;
@@ -2837,7 +2846,7 @@ static int mvneta_rxq_init(struct mvneta_port *pp,
mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
/* Set Offset */
- mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
+ mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD - pp->rx_offset_correction);
/* Set coalescing pkts and time */
mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
@@ -4088,6 +4097,13 @@ static int mvneta_probe(struct platform_device *pdev)
pp->rxq_def = rxq_def;
+ /* Set RX packet offset correction for platforms, whose
+* NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit
+* platforms and 0B for 32-bit ones.
+*/
+ pp->rx_offset_correction =
+ max(0, NET_SKB_PAD - MVNETA_RX_PKT_OFFSET_CORRECTION);
+
pp->indir[0] = rxq_def;
pp->clk = devm_clk_get(&pdev->dev, "core");
--
git-series 0.8.10
[PATCH v3 net-next 6/6] ARM64: dts: marvell: Add network support for Armada 3700
Add neta nodes for network support both in device tree for the SoC and
the board.
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 23 +++-
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 +++-
2 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 1372e9a6aaa4..c8b82e4145de 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -81,3 +81,26 @@
&pcie0 {
status = "okay";
};
+
+&mdio {
+ status = "okay";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+ð0 {
+ phy-mode = "rgmii-id";
+ phy = <&phy0>;
+ status = "okay";
+};
+
+ð1 {
+ phy-mode = "rgmii-id";
+ phy = <&phy1>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index e9bd58793464..3b8eb45bdc76 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -140,6 +140,29 @@
};
};
+ eth0: ethernet@3 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x3 0x4000>;
+ interrupts = ;
+ clocks = <&sb_periph_clk 8>;
+ status = "disabled";
+ };
+
+ mdio: mdio@32004 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0x32004 0x4>;
+ };
+
+ eth1: ethernet@4 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x4 0x4000>;
+ interrupts = ;
+ clocks = <&sb_periph_clk 7>;
+ status = "disabled";
+ };
+
usb3: usb@58000 {
compatible = "marvell,armada3700-xhci",
"generic-xhci";
--
git-series 0.8.10
[PATCH v3 net-next 0/6] Support Armada 37xx SoC (ARMv8 64-bits) in mvneta driver
Hi, The Armada 37xx is a new ARMv8 SoC from Marvell using same network controller as the older Armada 370/38x/XP SoCs. This series adapts the driver in order to be able to use it on this new SoC. The main changes are: - 64-bits support: the first patches allow using the driver on a 64-bit architecture. - MBUS support: the mbus configuration is different on Armada 37xx from the older SoCs. - per cpu interrupt: Armada 37xx do not support per cpu interrupt for the NETA IP, the non-per-CPU behavior was added back. The first item is solved by patches 1 to 3. The 2 last items are solved by patch 4. In patch 5 the dt support is added. Beside Armada 37xx, the series have been tested on Armada XP and Armada 38x (with Hardware Buffer Management and with Software Buffer Managment). Thanks, Gregory Gregory CLEMENT (4): net: mvneta: Optimize rx path for small frame net: mvneta: Use cacheable memory to store the rx buffer virtual address net: mvneta: Only disable mvneta_bm for 64-bits ARM64: dts: marvell: Add network support for Armada 3700 Marcin Wojtas (2): net: mvneta: Convert to be 64 bits compatible net: mvneta: Add network support for Armada 3700 SoC Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 +- arch/arm64/boot/dts/marvell/armada-3720-db.dts| 23 - arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 - drivers/net/ethernet/marvell/Kconfig | 10 +- drivers/net/ethernet/marvell/mvneta.c | 400 ++-- 5 files changed, 361 insertions(+), 102 deletions(-) base-commit: 436accebb53021ef7c63535f60bda410aa87c136 -- git-series 0.8.10
Re: [PATCH net-next 1/5] net: mvneta: Use cacheable memory to store the rx buffer virtual address
Hi Jisheng,
On lun., nov. 28 2016, Jisheng Zhang wrote:
> Hi Gregory,
>
> On Fri, 25 Nov 2016 16:30:14 +0100 Gregory CLEMENT wrote:
>
>> Until now the virtual address of the received buffer were stored in the
>> cookie field of the rx descriptor. However, this field is 32-bits only
>> which prevents to use the driver on a 64-bits architecture.
>>
>> With this patch the virtual address is stored in an array not shared with
>> the hardware (no more need to use the DMA API). Thanks to this, it is
>> possible to use cache contrary to the access of the rx descriptor member.
>>
>> The change is done in the swbm path only because the hwbm uses the cookie
>> field, this also means that currently the hwbm is not usable in 64-bits.
>>
>> Signed-off-by: Gregory CLEMENT
>> ---
>> drivers/net/ethernet/marvell/mvneta.c | 96
>> 1 file changed, 84 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/marvell/mvneta.c
>> b/drivers/net/ethernet/marvell/mvneta.c
>> index 87274d4ab102..b6849f88cab7 100644
>> --- a/drivers/net/ethernet/marvell/mvneta.c
>> +++ b/drivers/net/ethernet/marvell/mvneta.c
>> @@ -561,6 +561,9 @@ struct mvneta_rx_queue {
>> u32 pkts_coal;
>> u32 time_coal;
>>
>> +/* Virtual address of the RX buffer */
>> +void **buf_virt_addr;
>
> can we store buf_phys_addr in cacheable memory as well?
Even if we store in in cacheable memory we will still need to store it
in the buffer descriptor as it is used by the hardware.
>
>> +
>> /* Virtual address of the RX DMA descriptors array */
>> struct mvneta_rx_desc *descs;
>>
>> @@ -1573,10 +1576,14 @@ static void mvneta_tx_done_pkts_coal_set(struct
>> mvneta_port *pp,
>>
>> /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
>> static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
>> -u32 phys_addr, u32 cookie)
>> +u32 phys_addr, void *virt_addr,
>> +struct mvneta_rx_queue *rxq)
>> {
>> -rx_desc->buf_cookie = cookie;
>> +int i;
>> +
>> rx_desc->buf_phys_addr = phys_addr;
>> +i = rx_desc - rxq->descs;
>> +rxq->buf_virt_addr[i] = virt_addr;
>> }
>>
>> /* Decrement sent descriptors counter */
>> @@ -1781,7 +1788,8 @@ EXPORT_SYMBOL_GPL(mvneta_frag_free);
>>
>> /* Refill processing for SW buffer management */
>> static int mvneta_rx_refill(struct mvneta_port *pp,
>> -struct mvneta_rx_desc *rx_desc)
>> +struct mvneta_rx_desc *rx_desc,
>> +struct mvneta_rx_queue *rxq)
>>
>> {
>> dma_addr_t phys_addr;
>> @@ -1799,7 +1807,7 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
>> return -ENOMEM;
>> }
>>
>> -mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
>> +mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
>> return 0;
>> }
>>
>> @@ -1861,7 +1869,12 @@ static void mvneta_rxq_drop_pkts(struct mvneta_port
>> *pp,
>>
>> for (i = 0; i < rxq->size; i++) {
>> struct mvneta_rx_desc *rx_desc = rxq->descs + i;
>> -void *data = (void *)rx_desc->buf_cookie;
>> +void *data;
>> +
>> +if (!pp->bm_priv)
>> +data = rxq->buf_virt_addr[i];
>> +else
>> +data = (void *)(uintptr_t)rx_desc->buf_cookie;
>>
>> dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
>> MVNETA_RX_BUF_SIZE(pp->pkt_size),
>> DMA_FROM_DEVICE);
>> @@ -1894,12 +1907,13 @@ static int mvneta_rx_swbm(struct mvneta_port *pp,
>> int rx_todo,
>> unsigned char *data;
>> dma_addr_t phys_addr;
>> u32 rx_status, frag_size;
>> -int rx_bytes, err;
>> +int rx_bytes, err, index;
>>
>> rx_done++;
>> rx_status = rx_desc->status;
>> rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
>> -data = (unsigned char *)rx_desc->buf_cookie;
>> +index = rx_desc - rxq->descs;
>> +data = (unsigned char *)rxq->buf_virt_addr[index];
>> phys_addr = rx_desc->buf_phys_addr;
>>
>>
[PATCH net-next 5/5] ARM64: dts: marvell: Add network support for Armada 3700
Add neta nodes for network support both in device tree for the SoC and
the board.
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 23 +++-
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 +++-
2 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 1372e9a6aaa4..c8b82e4145de 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -81,3 +81,26 @@
&pcie0 {
status = "okay";
};
+
+&mdio {
+ status = "okay";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+ð0 {
+ phy-mode = "rgmii-id";
+ phy = <&phy0>;
+ status = "okay";
+};
+
+ð1 {
+ phy-mode = "rgmii-id";
+ phy = <&phy1>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index e9bd58793464..3b8eb45bdc76 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -140,6 +140,29 @@
};
};
+ eth0: ethernet@3 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x3 0x4000>;
+ interrupts = ;
+ clocks = <&sb_periph_clk 8>;
+ status = "disabled";
+ };
+
+ mdio: mdio@32004 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0x32004 0x4>;
+ };
+
+ eth1: ethernet@4 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x4 0x4000>;
+ interrupts = ;
+ clocks = <&sb_periph_clk 7>;
+ status = "disabled";
+ };
+
usb3: usb@58000 {
compatible = "marvell,armada3700-xhci",
"generic-xhci";
--
git-series 0.8.10
[PATCH net-next 4/5] net: mvneta: Add network support for Armada 3700 SoC
From: Marcin Wojtas
Armada 3700 is a new ARMv8 SoC from Marvell using same network controller
as older Armada 370/38x/XP. There are however some differences that
needed taking into account when adding support for it:
* open default MBUS window to 4GB of DRAM - Armada 3700 SoC's Mbus
configuration for network controller has to be done on two levels:
global and per-port. The first one is inherited from the
bootloader. The latter can be opened in a default way, leaving
arbitration to the bus controller. Hence filled mbus_dram_target_info
structure is not needed
* make per-CPU operation optional - Recent patches adding RSS and XPS
support for Armada 38x/XP enabled per-CPU operation of the controller
by default. Contrary to older SoC's Armada 3700 SoC's network
controller is not capable of per-CPU processing due to interrupt lines'
connectivity. This patch restores non-per-CPU operation, which is now
optional and depends on neta_armada3700 flag value in mvneta_port
structure. In order not to complicate the code, separate interrupt
subroutine is implemented.
For now, on the Armada 3700, RSS is disabled as the current
implementation depend on the per cpu interrupts.
[gregory.clem...@free-electrons.com: extract from a larger patch, replace
some ifdef and port to net-next for v4.10]
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 +-
drivers/net/ethernet/marvell/Kconfig | 7 +-
drivers/net/ethernet/marvell/mvneta.c | 287
+++-
3 files changed, 214 insertions(+), 87 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
index 73be8970815e..7aa840c8768d 100644
--- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
+++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
@@ -1,7 +1,10 @@
-* Marvell Armada 370 / Armada XP Ethernet Controller (NETA)
+* Marvell Armada 370 / Armada XP / Armada 3700 Ethernet Controller (NETA)
Required properties:
-- compatible: "marvell,armada-370-neta" or "marvell,armada-xp-neta".
+- compatible: could be one of the followings
+ "marvell,armada-370-neta"
+ "marvell,armada-xp-neta"
+ "marvell,armada-3700-neta"
- reg: address and length of the register set for the device.
- interrupts: interrupt for the device
- phy: See ethernet.txt file in the same directory.
diff --git a/drivers/net/ethernet/marvell/Kconfig
b/drivers/net/ethernet/marvell/Kconfig
index 2ccea9dd9248..3b8f11fe5e13 100644
--- a/drivers/net/ethernet/marvell/Kconfig
+++ b/drivers/net/ethernet/marvell/Kconfig
@@ -56,14 +56,15 @@ config MVNETA_BM_ENABLE
buffer management.
config MVNETA
- tristate "Marvell Armada 370/38x/XP network interface support"
- depends on PLAT_ORION || COMPILE_TEST
+ tristate "Marvell Armada 370/38x/XP/37xx network interface support"
+ depends on ARCH_MVEBU || COMPILE_TEST
depends on HAS_DMA
select MVMDIO
select FIXED_PHY
---help---
This driver supports the network interface units in the
- Marvell ARMADA XP, ARMADA 370 and ARMADA 38x SoC family.
+ Marvell ARMADA XP, ARMADA 370, ARMADA 38x and
+ ARMADA 37xx SoC family.
Note that this driver is distinct from the mv643xx_eth
driver, which should be used for the older Marvell SoCs
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index ad3872e07a93..77cef5a9de7b 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -397,6 +397,9 @@ struct mvneta_port {
spinlock_t lock;
bool is_stopped;
+ u32 cause_rx_tx;
+ struct napi_struct napi;
+
/* Core clock */
struct clk *clk;
/* AXI clock */
@@ -422,6 +425,9 @@ struct mvneta_port {
u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
+
+ /* Flags for special SoC configurations */
+ bool neta_armada3700;
u16 rx_offset_correction;
};
@@ -965,14 +971,9 @@ static int mvneta_mbus_io_win_set(struct mvneta_port *pp,
u32 base, u32 wsize,
return 0;
}
-/* Assign and initialize pools for port. In case of fail
- * buffer manager will remain disabled for current port.
- */
-static int mvneta_bm_port_init(struct platform_device *pdev,
- struct mvneta_port *pp)
+static int mvneta_bm_port_mbus_init(struct mvneta_port *pp)
{
- struct device_node *dn = pdev->dev.of_node;
- u32 long_pool_id, short_pool_id, wsize;
+ u32 wsize;
u
