Re: [PATCH v12 01/10] dt-bindings: Add Cavium Octeon Common Ethernet Interface.

[Steven J. Hill]

On 06/28/2018 03:35 AM, Andrew Lunn wrote:
> 
>> +- cavium,rx-clk-delay-bypass: Set to <1> to bypass the rx clock delay 
>> setting.
>> +  Needed by the Micrel PHY.
> 
> Could you explain this some more. Is it anything to do with RGMII delays?
> 
Andrew,

One of my colleagues tracked this down for me. This device tree option is in 
place
because there are several different ways to do the clock and data with respect 
to
RGMII. This controls the delay introduced for the RX clock with respect to the 
data.
Without this, RX will not work with Micrel PHYs. Thanks.

Steve

[PATCH v12 01/10] dt-bindings: Add Cavium Octeon Common Ethernet Interface.

[Steven J. Hill]

From: Carlos Munoz 

Add bindings for Common Ethernet Interface (BGX) block.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
---
 .../devicetree/bindings/net/cavium-bgx.txt | 59 ++
 1 file changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/cavium-bgx.txt

diff --git a/Documentation/devicetree/bindings/net/cavium-bgx.txt 
b/Documentation/devicetree/bindings/net/cavium-bgx.txt
new file mode 100644
index 000..21c9606
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/cavium-bgx.txt
@@ -0,0 +1,59 @@
+* Common Ethernet Interface (BGX) block
+
+Properties:
+
+- compatible: "cavium,octeon-7890-bgx": Compatibility with all cn7xxx SOCs.
+
+- reg: The base address of the BGX block.
+
+- #address-cells: Must be <1>.
+
+- #size-cells: Must be <0>.  BGX addresses have no size component.
+
+Typically a BGX block has several children each representing a ethernet
+interface.
+
+Example:
+
+   ethernet-mac-nexus@11800e000 {
+   compatible = "cavium,octeon-7890-bgx";
+   reg = <0x00011800 0xe000 0x 0x0100>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ethernet-mac@0 {
+   ...
+   reg = <0>;
+   };
+   };
+
+
+* Ethernet Interface (BGX port) connects to PKI/PKO
+
+Properties:
+
+- compatible: "cavium,octeon-7890-bgx-port": Compatibility with all cn7xxx
+  SOCs.
+
+- reg: The index of the interface withing the BGX block.
+
+- local-mac-address: Mac address for the interface.
+
+- phy-handle: phandle to the phy node connected to the interface.
+
+
+* Ethernet Interface (BGX port) connects to XCV
+
+
+Properties:
+
+- compatible: "cavium,octeon-7360-xcv": Compatibility with cn73xx SOCs.
+
+- reg: The index of the interface withing the BGX block.
+
+- local-mac-address: Mac address for the interface.
+
+- phy-handle: phandle to the phy node connected to the interface.
+
+- cavium,rx-clk-delay-bypass: Set to <1> to bypass the rx clock delay setting.
+  Needed by the Micrel PHY.
-- 
2.1.4

[PATCH v12 02/10] netdev: cavium: octeon: Header for Octeon III BGX Ethernet

[Steven J. Hill]

From: Carlos Munoz 

Add the common header file used by the Octeon III BGX Ethernet
driver.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
---
 drivers/net/ethernet/cavium/octeon/octeon3-bgx.h | 150 +++
 drivers/net/ethernet/cavium/octeon/octeon3.h | 330 +++
 2 files changed, 480 insertions(+)
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx.h
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3.h

diff --git a/drivers/net/ethernet/cavium/octeon/octeon3-bgx.h 
b/drivers/net/ethernet/cavium/octeon/octeon3-bgx.h
new file mode 100644
index 000..df794f5
--- /dev/null
+++ b/drivers/net/ethernet/cavium/octeon/octeon3-bgx.h
@@ -0,0 +1,150 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Octeon III BGX Nexus Ethernet driver
+ *
+ * Copyright (C) 2018 Cavium, Inc.
+ */
+#ifndef _OCTEON3_BGX_H_
+#define _OCTEON3_BGX_H_
+
+#include 
+
+#define BGX_CMR_CHAN_MSK_MASK  GENMASK_ULL(15, 0)
+#define BGX_CMR_CHAN_MSK_SHIFT 16
+#define BGX_CMR_CONFIG_DATA_PKT_RX_EN  BIT(14)
+#define BGX_CMR_CONFIG_DATA_PKT_TX_EN  BIT(13)
+#define BGX_CMR_CONFIG_ENABLE  BIT(15)
+#define BGX_CMR_CONFIG_LMAC_TYPE_MASK  GENMASK_ULL(10, 8)
+#define BGX_CMR_CONFIG_LMAC_TYPE_SHIFT 8
+#define BGX_CMR_CONFIG_MIX_EN  BIT(11)
+#define BGX_CMR_GLOBAL_CONFIG_CMR_MIX0_RST BIT(3)
+#define BGX_CMR_GLOBAL_CONFIG_CMR_MIX1_RST BIT(4)
+#define BGX_CMR_RX_ADR_CTL_ACCEPT_ALL_MCST BIT(1)
+#define BGX_CMR_RX_ADR_CTL_BCST_ACCEPT BIT(0)
+#define BGX_CMR_RX_ADR_CTL_CAM_ACCEPT  BIT(3)
+#define BGX_CMR_RX_ADR_CTL_MCST_MODE_MASK  GENMASK_ULL(2, 1)
+#define BGX_CMR_RX_ADR_CTL_USE_CAM_FILTER  BIT(2)
+#define BGX_CMR_RX_ADRX_CAM_EN BIT(48)
+#define BGX_CMR_RX_ADRX_CAM_ID_SHIFT   52
+#define BGX_CMR_RX_FIFO_LEN_MASK   GENMASK_ULL(12, 0)
+#define BGX_CMR_RX_ID_MAP_PKND_MASKGENMASK_ULL(7, 0)
+#define BGX_CMR_RX_ID_MAP_RID_MASK GENMASK_ULL(14, 8)
+#define BGX_CMR_RX_ID_MAP_RID_SHIFT8
+#define BGX_CMR_TX_FIFO_LEN_LMAC_IDLE  BIT(13)
+#define BGX_CMR_TX_LMACS_MASK  GENMASK_ULL(2, 0)
+#define BGX_GMP_GMI_PRT_CFG_DUPLEX BIT(2)
+#define BGX_GMP_GMI_PRT_CFG_RX_IDLEBIT(12)
+#define BGX_GMP_GMI_PRT_CFG_SLOTTIME   BIT(3)
+#define BGX_GMP_GMI_PRT_CFG_SPEED  BIT(1)
+#define BGX_GMP_GMI_PRT_CFG_SPEED_MSB  BIT(8)
+#define BGX_GMP_GMI_PRT_CFG_TX_IDLEBIT(13)
+#define BGX_GMP_GMI_TX_APPEND_FCS  BIT(2)
+#define BGX_GMP_GMI_TX_APPEND_PAD  BIT(1)
+#define BGX_GMP_GMI_TX_APPEND_PREAMBLE BIT(0)
+#define BGX_GMP_GMI_TX_THRESH_DEFAULT  0x20
+#define BGX_GMP_PCS_AN_ADV_FULL_DUPLEX BIT(5)
+#define BGX_GMP_PCS_AN_ADV_HALF_DUPLEX BIT(6)
+#define BGX_GMP_PCS_AN_ADV_PAUSE_ASYMMETRIC2
+#define BGX_GMP_PCS_AN_ADV_PAUSE_BOTH  3
+#define BGX_GMP_PCS_AN_ADV_PAUSE_MASK  GENMASK_ULL(8, 7)
+#define BGX_GMP_PCS_AN_ADV_PAUSE_NONE  0
+#define BGX_GMP_PCS_AN_ADV_PAUSE_SHIFT 7
+#define BGX_GMP_PCS_AN_ADV_PAUSE_SYMMETRIC 1
+#define BGX_GMP_PCS_AN_ADV_REM_FLT_MASKGENMASK_ULL(13, 12)
+#define BGX_GMP_PCS_LINK_TIMER_COUNT_SHIFT 10
+#define BGX_GMP_PCS_MISC_CTL_GMXENOBIT(11)
+#define BGX_GMP_PCS_MISC_CTL_MAC_PHY   BIT(9)
+#define BGX_GMP_PCS_MISC_CTL_MODE  BIT(8)
+#define BGX_GMP_PCS_MISC_CTL_SAMP_PT_MASK  GENMASK_ULL(6, 0)
+#define BGX_GMP_PCS_MR_CONTROL_AN_EN   BIT(12)
+#define BGX_GMP_PCS_MR_CONTROL_PWR_DN  BIT(11)
+#define BGX_GMP_PCS_MR_CONTROL_RESET   BIT(15)
+#define BGX_GMP_PCS_MR_CONTROL_RST_AN  BIT(9)
+#define BGX_GMP_PCS_MR_CONTROL_SPDLSB  BIT(13)
+#define BGX_GMP_PCS_MR_CONTROL_SPDMSB  BIT(6)
+#define BGX_GMP_PCS_MR_STATUS_AN_CPT   BIT(5)
+#define BGX_GMP_PCS_SGM_AN_ADV_DUPLEX_FULL BIT(12)
+#define BGX_GMP_PCS_SGM_AN_ADV_SPEED_100
+#define BGX_GMP_PCS_SGM_AN_ADV_SPEED_1 3
+#define BGX_GMP_PCS_SGM_AN_ADV_SPEED_1000  2
+#define BGX_GMP_PCS_SGM_AN_ADV_SPEED_100   1
+#define BGX_GMP_PCS_SGM_AN_ADV_SPEED_MASK  GENMASK_ULL(11, 10)
+#define BGX_GMP_PCS_SGM_AN_ADV_SPEED_SHIFT 10
+#define BGX_SMU_CTRL_RX_IDLE   BIT(0)
+#define BGX_SMU_CTRL_TX_IDLE   BIT(1)
+#define BGX_SMU_RX_CTL_STATUS_MASK GENMASK_ULL(1, 0)
+#define BGX_SMU_TX_APPEND_FCS_CBIT(3)
+#define BGX_SMU_TX_APPEND_FCS_DBIT(2)
+#define BGX_SMU_TX_APPEND_PAD  BIT(1)
+#define BGX_SMU_TX_CTL_DIC_EN  BIT(0)
+#define BGX_SMU_TX_CTL_LS_MASK GENMASK_ULL(5, 4)
+#define BGX_SMU_TX_CTL_UNI_EN  BIT(1)
+#define BGX_SPU_AN_ADV_A100G_CR10  BIT(26)
+#define BGX_SPU_AN_ADV_A10G_KR BIT(23)
+#define BGX_SPU_AN_ADV_A10G_KX4BIT(22)
+#define BGX_SPU_AN_ADV_A1G_KX  BIT(21)
+#define BGX_SPU_AN_ADV_A40G_CR4BIT(25)
+#define BGX_SPU_AN_ADV_A40G_KR4BIT(24)
+#define BGX_SPU_AN_ADV_FEC_ABLEBIT(46)
+#define BGX_SPU_AN_ADV_FEC_REQ BIT(47)
+#define BGX_SPU_AN_ADV_RF  BIT(13)
+#define

[PATCH v12 04/10] netdev: cavium: octeon: Add Octeon III BGX Ports

[Steven J. Hill]

From: Carlos Munoz 

Add individual BGX nexus port support for Octeon III BGX Ethernet.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
---
 .../net/ethernet/cavium/octeon/octeon3-bgx-port.c  | 2192 
 1 file changed, 2192 insertions(+)
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-port.c

diff --git a/drivers/net/ethernet/cavium/octeon/octeon3-bgx-port.c 
b/drivers/net/ethernet/cavium/octeon/octeon3-bgx-port.c
new file mode 100644
index 000..eb5921b
--- /dev/null
+++ b/drivers/net/ethernet/cavium/octeon/octeon3-bgx-port.c
@@ -0,0 +1,2192 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Octeon III BGX Nexus Ethernet driver
+ *
+ * Copyright (C) 2018 Cavium, Inc.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "octeon3.h"
+
+struct bgx_port_priv {
+   int node;
+   int bgx;
+   int index; /* Port index on BGX block*/
+   enum port_mode mode;
+   int pknd;
+   int qlm;
+   const u8 *mac_addr;
+   struct phy_device *phydev;
+   struct device_node *phy_np;
+   bool mode_1000basex;
+   bool bgx_as_phy;
+   struct net_device *netdev;
+   struct mutex lock;  /* Serializes delayed work */
+   struct port_status (*get_link)(struct bgx_port_priv *priv);
+   int (*set_link)(struct bgx_port_priv *priv, struct port_status status);
+   struct port_status last_status;
+   struct delayed_work dwork;
+   bool work_queued;
+};
+
+/* lmac_pknd keeps track of the port kinds assigned to the lmacs */
+static int lmac_pknd[MAX_NODES][MAX_BGX_PER_NODE][MAX_LMAC_PER_BGX];
+
+static struct workqueue_struct *check_state_wq;
+static DEFINE_MUTEX(check_state_wq_mutex);
+
+int bgx_port_get_qlm(int node, int bgx, int index)
+{
+   int qlm = -1;
+   u64 data;
+
+   if (OCTEON_IS_MODEL(OCTEON_CN78XX)) {
+   if (bgx < 2) {
+   data = oct_csr_read(BGX_CMR_GLOBAL_CONFIG(node, bgx));
+   if (data & 1)
+   qlm = bgx + 2;
+   else
+   qlm = bgx;
+   } else {
+   qlm = bgx + 2;
+   }
+   } else if (OCTEON_IS_MODEL(OCTEON_CN73XX)) {
+   if (bgx < 2) {
+   qlm = bgx + 2;
+   } else {
+   /* Ports on bgx2 can be connected to qlm5 or qlm6 */
+   if (index < 2)
+   qlm = 5;
+   else
+   qlm = 6;
+   }
+   } else if (OCTEON_IS_MODEL(OCTEON_CNF75XX)) {
+   /* Ports on bgx0 can be connected to qlm4 or qlm5 */
+   if (index < 2)
+   qlm = 4;
+   else
+   qlm = 5;
+   }
+
+   return qlm;
+}
+EXPORT_SYMBOL(bgx_port_get_qlm);
+
+/* Returns the mode of the bgx port */
+enum port_mode bgx_port_get_mode(int node, int bgx, int index)
+{
+   enum port_mode mode;
+   u64 data;
+
+   data = oct_csr_read(BGX_CMR_CONFIG(node, bgx, index)) &
+   BGX_CMR_CONFIG_LMAC_TYPE_MASK;
+
+   switch (data  >> BGX_CMR_CONFIG_LMAC_TYPE_SHIFT) {
+   case 0:
+   mode = PORT_MODE_SGMII;
+   break;
+   case 1:
+   mode = PORT_MODE_XAUI;
+   break;
+   case 2:
+   mode = PORT_MODE_RXAUI;
+   break;
+   case 3:
+   data = oct_csr_read(BGX_SPU_BR_PMD_CONTROL(node, bgx, index));
+   /* The use of training differentiates 10G_KR from xfi */
+   if (data & BGX_SPU_BR_PMD_CONTROL_TRAIN_EN)
+   mode = PORT_MODE_10G_KR;
+   else
+   mode = PORT_MODE_XFI;
+   break;
+   case 4:
+   data = oct_csr_read(BGX_SPU_BR_PMD_CONTROL(node, bgx, index));
+   /* The use of training differentiates 40G_KR4 from xlaui */
+   if (data & BGX_SPU_BR_PMD_CONTROL_TRAIN_EN)
+   mode = PORT_MODE_40G_KR4;
+   else
+   mode = PORT_MODE_XLAUI;
+   break;
+   default:
+   mode = PORT_MODE_DISABLED;
+   break;
+   }
+
+   return mode;
+}
+EXPORT_SYMBOL(bgx_port_get_mode);
+
+int bgx_port_allocate_pknd(int node)
+{
+   struct global_resource_tag tag;
+   char buf[16];
+   int pknd;
+
+   strncpy((char *), "cvm_pknd", 8);
+   snprintf(buf, 16, "_%d..", node);
+   memcpy(, buf, 8);
+
+   res_mgr_create_resource(tag, 64);
+   pknd = res_mgr_alloc(tag, -1, false);
+   if (pknd < 0) {
+   pr_err("bgx-port: Failed to allocate pknd\n");
+   return -ENODEV;
+   }
+
+   return pknd;
+}
+EXPORT_SYMBOL(bgx_port_allocate_pknd);
+
+int bgx_port

[PATCH v12 08/10] netdev: cavium: octeon: Add Octeon III BGX Ethernet core

[Steven J. Hill]

From: Carlos Munoz 

This is the main core of the BGX Ethernet driver.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
---
 drivers/net/ethernet/cavium/octeon/octeon3-core.c | 2363 +
 1 file changed, 2363 insertions(+)
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-core.c

diff --git a/drivers/net/ethernet/cavium/octeon/octeon3-core.c 
b/drivers/net/ethernet/cavium/octeon/octeon3-core.c
new file mode 100644
index 000..b0dfacb
--- /dev/null
+++ b/drivers/net/ethernet/cavium/octeon/octeon3-core.c
@@ -0,0 +1,2363 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Octeon III BGX Nexus Ethernet driver core
+ *
+ * Copyright (C) 2018 Cavium, Inc.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "octeon3.h"
+
+/*  First buffer:
+ *
+ *+---SKB-+
+ *|   |
+ *|   |
+ * +--+--*data|
+ * |  |   |
+ * |  |   |
+ * |  +---+
+ * |   /|\
+ * ||
+ * ||
+ *\|/   |
+ * WQE - 128 -+-> +-+---+ -+-
+ *|   |*skb +   |  |
+ *|   | |  |
+ *|   | |  |
+ *  WQE_SKIP = 128| |  |
+ *|   | |  |
+ *|   | |  |
+ *|   | |  |
+ *|   | |  First Skip
+ * WQE   -+-> +-+  |
+ *|   word 0|  |
+ *|   word 1|  |
+ *|   word 2|  |
+ *|   word 3|  |
+ *|   word 4|  |
+ *+-+ -+-
+ *   ++- packet link|
+ *   ||  packet data|
+ *   || |
+ *   || |
+ *   || .   |
+ *   || .   |
+ *   || .   |
+ *   |+-+
+ *   |
+ *   |
+ * Later buffers:|
+ *   |
+ *   |
+ *   |
+ *   |
+ *   |
+ *   |+---SKB-+
+ *   ||   |
+ *   ||   |
+ *   | +--+--*data|
+ *   | |  |   |
+ *   | |  |   |
+ *   | |  +---+
+ *   | |   /|\
+ *   | ||
+ *   | ||
+ *   |\|/   |
+ * WQE - 128 +--> +-+---+ -+-
+ *   ||*skb +   |  |
+ *   || |  |
+ *   || |  |
+ *   || |  |
+ *   || |  LATER_SKIP = 128
+ *   || |  |
+ *   || |  |
+ *   || |  |
+ *   |+-+ -+-
+ *   ||  packet link|
+ *   +--> |  packet data|
+ *| |
+ *| |
+ *| .   |
+ *| .   |
+ *| .   |
+ *+-+
+ */
+
+#define FPA3_NUM_AURAS 1024
+#define MAX_TX_QUEUE_DEPTH 512
+#define MAX_RX_CONTEXTS32
+#define USE_ASYNC_IOBDMA   1   /* Always 1 */
+
+#define SKB_AURA_MAGIC 0xbadc0ffee4dad000ULL
+#define SKB_AURA_OFFSET1
+#define SKB_PTR_OFFSET 0
+
+/* PTP registers and bits */
+#define MIO_PTP_CLOCK_HI(n)(CVMX_MIO_PTP_CLOCK_HI + NODE_OFFSET(n))
+#define MIO_PTP_CLOCK_CFG(n)   (CVMX_MIO_PTP_CLOCK_CFG + NODE_OFFSET(n))
+#define MIO_PTP_CLOCK_COMP(n)  (CVMX_MIO_PTP_CLOCK_COMP + NODE_OFFSET(n))
+
+/* Misc. bitfields */
+#define MIO_PTP_CLOCK_CFG_PTP_EN   BIT(0)
+#define BGX_GMP_GMI_RX_FRM_CTL_PTP_MODEBIT(12)
+
+/* Up to 2 napis per core are supported */
+#define MAX_NAPI_PE

[PATCH v12 09/10] netdev: cavium: octeon: Add Octeon III BGX Ethernet building

[Steven J. Hill]

From: Carlos Munoz 

Add the build and configuration files for the BGX Ethernet.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
---
 drivers/net/ethernet/cavium/Kconfig | 22 +-
 drivers/net/ethernet/cavium/octeon/Makefile |  8 +++-
 2 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/cavium/Kconfig 
b/drivers/net/ethernet/cavium/Kconfig
index 043e3c1..3b9709d 100644
--- a/drivers/net/ethernet/cavium/Kconfig
+++ b/drivers/net/ethernet/cavium/Kconfig
@@ -4,7 +4,7 @@
 
 config NET_VENDOR_CAVIUM
bool "Cavium ethernet drivers"
-   depends on PCI
+   depends on PCI || CAVIUM_OCTEON_SOC
default y
---help---
  Select this option if you want enable Cavium network support.
@@ -100,4 +100,24 @@ config LIQUIDIO_VF
  will be called liquidio_vf. MSI-X interrupt support is required
  for this driver to work correctly
 
+config OCTEON3_BGX_PORT
+   tristate "Cavium Octeon III BGX port support"
+   depends on CAVIUM_OCTEON_SOC
+   ---help---
+ This driver adds support for Cavium Octeon III BGX ports. BGX ports
+ support sgmii, rgmii, xaui, rxaui, xlaui, xfi, 10KR and 40KR modes.
+
+ Say Y to use the management port on Octeon III boards or to use
+ any other ethernet port.
+
+config OCTEON3_ETHERNET
+   tristate "Cavium OCTEON III PKI/PKO Ethernet support"
+   depends on CAVIUM_OCTEON_SOC
+   select OCTEON_BGX_PORT
+   select OCTEON_FPA3
+   select FW_LOADER
+   ---help---
+ Support for 'BGX' Ethernet via PKI/PKO units. No support for
+ cn70xx chips, use OCTEON_ETHERNET instead.
+
 endif # NET_VENDOR_CAVIUM
diff --git a/drivers/net/ethernet/cavium/octeon/Makefile 
b/drivers/net/ethernet/cavium/octeon/Makefile
index efa41c1..1939c84 100644
--- a/drivers/net/ethernet/cavium/octeon/Makefile
+++ b/drivers/net/ethernet/cavium/octeon/Makefile
@@ -1,5 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0
 #
 # Makefile for the Cavium network device drivers.
 #
 
-obj-$(CONFIG_OCTEON_MGMT_ETHERNET) += octeon_mgmt.o
+obj-$(CONFIG_OCTEON_MGMT_ETHERNET) += octeon_mgmt.o
+obj-$(CONFIG_OCTEON3_BGX_PORT) += octeon3-bgx-nexus.o octeon3-bgx-port.o
+obj-$(CONFIG_OCTEON3_ETHERNET) += octeon3-ethernet.o
+
+octeon3-ethernet-objs += octeon3-core.o octeon3-pki.o octeon3-pko.o\
+octeon3-sso.o
-- 
2.1.4

[PATCH v12 06/10] netdev: cavium: octeon: Add Octeon III PKO Support

[Steven J. Hill]

From: Carlos Munoz 

Add support for Octeon III PKO logic block for BGX Ethernet.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
---
 drivers/net/ethernet/cavium/octeon/octeon3-pko.c | 1638 ++
 drivers/net/ethernet/cavium/octeon/octeon3-pko.h |  159 +++
 2 files changed, 1797 insertions(+)
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pko.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pko.h

diff --git a/drivers/net/ethernet/cavium/octeon/octeon3-pko.c 
b/drivers/net/ethernet/cavium/octeon/octeon3-pko.c
new file mode 100644
index 000..238bf51
--- /dev/null
+++ b/drivers/net/ethernet/cavium/octeon/octeon3-pko.c
@@ -0,0 +1,1638 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Octeon III Packet-Output Processing Unit (PKO)
+ *
+ * Copyright (C) 2018 Cavium, Inc.
+ */
+
+#include "octeon3.h"
+
+#define PKO_MAX_FIFO_GROUPS8
+#define PKO_MAX_OUTPUT_MACS28
+#define PKO_FIFO_SIZE  2560
+
+#define PKO_BASE   0x15400ull
+#define PKO_ADDR(n)(PKO_BASE + SET_XKPHYS + NODE_OFFSET(n))
+#define PKO_Q_ADDR(n, q)   (PKO_ADDR(n) + ((q) << 9))
+
+#define PKO_CHANNEL_LEVEL(n)   (PKO_ADDR(n) + 0x0800f0)
+#define PKO_DPFI_ENA(n)(PKO_ADDR(n) + 0xc00018)
+#define PKO_DPFI_FLUSH(n)  (PKO_ADDR(n) + 0xc8)
+#define PKO_DPFI_FPA_AURA(n)   (PKO_ADDR(n) + 0xc00010)
+#define PKO_DPFI_STATUS(n) (PKO_ADDR(n) + 0xc0)
+#define PKO_DQ_SCHEDULE(n, q)  (PKO_Q_ADDR(n, q) + 0x280008)
+#define PKO_DQ_SW_XOFF(n, q)   (PKO_Q_ADDR(n, q) + 0x2800e0)
+#define PKO_DQ_TOPOLOGY(n, q)  (PKO_Q_ADDR(n, q) + 0x30)
+#define PKO_DQ_WM_CTL(n, q)(PKO_Q_ADDR(n, q) + 0x40)
+#define PKO_ENABLE(n)  (PKO_ADDR(n) + 0xd8)
+#define PKO_L1_SQ_LINK(n, q)   (PKO_Q_ADDR(n, q) + 0x38)
+#define PKO_L1_SQ_SHAPE(n, q)  (PKO_Q_ADDR(n, q) + 0x10)
+#define PKO_L1_SQ_TOPOLOGY(n, q)   (PKO_Q_ADDR(n, q) + 0x08)
+#define PKO_L2_SQ_SCHEDULE(n, q)   (PKO_Q_ADDR(n, q) + 0x080008)
+#define PKO_L2_SQ_TOPOLOGY(n, q)   (PKO_Q_ADDR(n, q) + 0x10)
+#define PKO_L3_L2_SQ_CHANNEL(n, q) (PKO_Q_ADDR(n, q) + 0x080038)
+#define PKO_L3_SQ_SCHEDULE(n, q)   (PKO_Q_ADDR(n, q) + 0x18)
+#define PKO_L3_SQ_TOPOLOGY(n, q)   (PKO_Q_ADDR(n, q) + 0x18)
+#define PKO_L4_SQ_SCHEDULE(n, q)   (PKO_Q_ADDR(n, q) + 0x180008)
+#define PKO_L4_SQ_TOPOLOGY(n, q)   (PKO_Q_ADDR(n, q) + 0x20)
+#define PKO_L5_SQ_SCHEDULE(n, q)   (PKO_Q_ADDR(n, q) + 0x28)
+#define PKO_L5_SQ_TOPOLOGY(n, q)   (PKO_Q_ADDR(n, q) + 0x28)
+#define PKO_LUT(n, c)  (PKO_ADDR(n) + ((c) << 3) + 0xb0)
+#define PKO_MAC_CFG(n, m)  (PKO_ADDR(n) + ((m) << 3) + 0x90)
+#define PKO_MCI0_MAX_CRED(n, m)(PKO_ADDR(n) + ((m) << 3) + 
0xa0)
+#define PKO_MCI1_MAX_CRED(n, m)(PKO_ADDR(n) + ((m) << 3) + 
0xa8)
+#define PKO_PDM_CFG(n) (PKO_ADDR(n) + 0x80)
+#define PKO_PDM_DQ_MINPAD(n, q)(PKO_ADDR(n) + ((q) << 3) + 
0x8f)
+#define PKO_PTF_IOBP_CFG(n)(PKO_ADDR(n) + 0x900300)
+#define PKO_PTF_STATUS(n, f)   (PKO_ADDR(n) + ((f) << 3) + 0x900100)
+#define PKO_PTGF_CFG(n, g) (PKO_ADDR(n) + ((g) << 3) + 0x900200)
+#define PKO_SHAPER_CFG(n)  (PKO_ADDR(n) + 0x0800f8)
+#define PKO_STATUS(n)  (PKO_ADDR(n) + 0xd0)
+
+/* These levels mimic the PKO internal linked queue structure */
+enum queue_level {
+   PQ = 1,
+   L2_SQ = 2,
+   L3_SQ = 3,
+   L4_SQ = 4,
+   L5_SQ = 5,
+   DQ = 6
+};
+
+enum pko_dqop_e {
+   DQOP_SEND,
+   DQOP_OPEN,
+   DQOP_CLOSE,
+   DQOP_QUERY
+};
+
+enum pko_dqstatus_e {
+   PASS = 0,
+   BADSTATE = 0x8,
+   NOFPABUF = 0x9,
+   NOPKOBUF = 0xa,
+   FAILRTNPTR = 0xb,
+   ALREADY = 0xc,
+   NOTCREATED = 0xd,
+   NOTEMPTY = 0xe,
+   SENDPKTDROP = 0xf
+};
+
+struct mac_info {
+   int fifo_cnt;
+   int prio;
+   int speed;
+   int fifo;
+   int num_lmacs;
+};
+
+struct fifo_grp_info {
+   int speed;
+   int size;
+};
+
+static const int lut_index_78xx[] = {
+   0x200,
+   0x240,
+   0x280,
+   0x2c0,
+   0x300,
+   0x340
+};
+
+static const int lut_index_73xx[] = {
+   0x000,
+   0x040,
+   0x080
+};
+
+static enum queue_level max_sq_level(void)
+{
+   /* 73xx and 75xx only have 3 scheduler queue levels */
+   if (OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CNF75XX))
+   return L3_SQ;
+   return L5_SQ;
+}
+
+static int get_num_fifos(void)
+{
+   if (OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CNF75XX))
+   return 16;
+ 

[PATCH v12 10/10] MAINTAINERS: Add entry for drivers/net/ethernet/cavium/octeon/octeon3-*

[Steven J. Hill]

From: David Daney 

Signed-off-by: David Daney 
---
 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 99e5cef..378009c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3279,6 +3279,12 @@ W:   http://www.cavium.com
 S: Supported
 F: drivers/mmc/host/cavium*
 
+CAVIUM OCTEON-III NETWORK DRIVER
+M: Steven J. Hill 
+L: netdev@vger.kernel.org
+S: Supported
+F: drivers/net/ethernet/cavium/octeon/octeon3-*
+
 CAVIUM OCTEON-TX CRYPTO DRIVER
 M: George Cherian 
 L: linux-cry...@vger.kernel.org
-- 
2.1.4

[PATCH v12 05/10] netdev: cavium: octeon: Add Octeon III PKI Support

[Steven J. Hill]

From: Carlos Munoz 

Add support for Octeon III PKI logic block for BGX Ethernet.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
---
 drivers/net/ethernet/cavium/octeon/octeon3-pki.c | 789 +++
 drivers/net/ethernet/cavium/octeon/octeon3-pki.h | 113 
 2 files changed, 902 insertions(+)
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pki.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pki.h

diff --git a/drivers/net/ethernet/cavium/octeon/octeon3-pki.c 
b/drivers/net/ethernet/cavium/octeon/octeon3-pki.c
new file mode 100644
index 000..9782ba1
--- /dev/null
+++ b/drivers/net/ethernet/cavium/octeon/octeon3-pki.c
@@ -0,0 +1,789 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Octeon III Packet Input Unit (PKI)
+ *
+ * Copyright (C) 2018 Cavium, Inc.
+ */
+
+#include 
+
+#include "octeon3.h"
+#include "octeon3-pki.h"
+
+#define PKI_CLUSTER_FIRMWARE   "cavium/pki-cluster.bin"
+#define VERSION_LEN8
+
+#define PKI_MAX_PCAM_BANKS 2
+#define PKI_MAX_PCAM_BANK_ENTRIES  192
+#define PKI_MAX_PKNDS  64
+#define PKI_NUM_QPG_ENTRIES2048
+#define PKI_NUM_STYLES 256
+#define PKI_NUM_FINAL_STYLES   64
+
+#define PKI_BASE   0x118004400ull
+#define PKI_ADDR(n)(PKI_BASE + SET_XKPHYS + NODE_OFFSET(n))
+#define PKI_CL_ADDR(n, c)  (PKI_ADDR(n) + ((c) << 16))
+#define PKI_CL_PCAM(n, c, b, e)(PKI_CL_ADDR(n, c) + ((b) << 
12) + \
+((e) << 3))
+#define PKI_CL_PKIND(n, c, p)  (PKI_CL_ADDR(n, c) + ((p) << 8))
+#define PKI_CL_STYLE(n, c, s)  (PKI_CL_ADDR(n, c) + ((s) << 3))
+
+#define PKI_AURA_CFG(n, a) (PKI_ADDR(n) + 0x90 + ((a) << 3))
+#define PKI_BUF_CTL(n) (PKI_ADDR(n) + 0x000100)
+#define PKI_ICG_CFG(n) (PKI_ADDR(n) + 0x00a000)
+#define PKI_IMEM(n, i) (PKI_ADDR(n) + 0x10 + ((i) << 3))
+#define PKI_LTYPE_MAP(n, l)(PKI_ADDR(n) + 0x005000 + ((l) << 3))
+#define PKI_QPG_TBL(n, i)  (PKI_ADDR(n) + 0x80 + ((i) << 3))
+#define PKI_SFT_RST(n) (PKI_ADDR(n) + 0x10)
+#define PKI_STAT_CTL(n)(PKI_ADDR(n) + 0x000110)
+#define PKI_STAT_STAT0(n, p)   (PKI_ADDR(n) + 0xe00038 + ((p) << 8))
+#define PKI_STAT_STAT1(n, p)   (PKI_ADDR(n) + 0xe00040 + ((p) << 8))
+#define PKI_STAT_STAT3(n, p)   (PKI_ADDR(n) + 0xe00050 + ((p) << 8))
+#define PKI_STYLE_BUF(n, s)(PKI_ADDR(n) + 0x024000 + ((s) << 3))
+
+#define PKI_CL_ECC_CTL(n, c)   (PKI_CL_ADDR(n, c) + 0x00c020)
+#define PKI_CL_PCAM_TERM(n, c, b, e)   (PKI_CL_PCAM(n, c, b, e) + 0x70)
+#define PKI_CL_PCAM_MATCH(n, c, b, e)  (PKI_CL_PCAM(n, c, b, e) + 0x704000)
+#define PKI_CL_PCAM_ACTION(n, c, b, e) (PKI_CL_PCAM(n, c, b, e) + 0x708000)
+#define PKI_CL_PKIND_CFG(n, c, p)  (PKI_CL_PKIND(n, c, p) + 0x300040)
+#define PKI_CL_PKIND_STYLE(n, c, p)(PKI_CL_PKIND(n, c, p) + 0x300048)
+#define PKI_CL_PKIND_SKIP(n, c, p) (PKI_CL_PKIND(n, c, p) + 0x300050)
+#define PKI_CL_PKIND_L2_CUSTOM(n, c, p)(PKI_CL_PKIND(n, c, p) + 
0x300058)
+#define PKI_CL_PKIND_LG_CUSTOM(n, c, p)(PKI_CL_PKIND(n, c, p) + 
0x300060)
+#define PKI_CL_STYLE_CFG(n, c, s)  (PKI_CL_STYLE(n, c, s) + 0x50)
+#define PKI_CL_STYLE_CFG2(n, c, s) (PKI_CL_STYLE(n, c, s) + 0x500800)
+#define PKI_CL_STYLE_ALG(n, c, s)  (PKI_CL_STYLE(n, c, s) + 0x501000)
+
+enum pcam_term {
+   NONE,
+   L2_CUSTOM = 0x2,
+   HIGIGD = 0x4,
+   HIGIG = 0x5,
+   SMACH = 0x8,
+   SMACL = 0x9,
+   DMACH = 0xa,
+   DMACL = 0xb,
+   GLORT = 0x12,
+   DSA = 0x13,
+   ETHTYPE0 = 0x18,
+   ETHTYPE1 = 0x19,
+   ETHTYPE2 = 0x1a,
+   ETHTYPE3 = 0x1b,
+   MPLS0 = 0x1e,
+   L3_SIPHH = 0x1f,
+   L3_SIPMH = 0x20,
+   L3_SIPML = 0x21,
+   L3_SIPLL = 0x22,
+   L3_FLAGS = 0x23,
+   L3_DIPHH = 0x24,
+   L3_DIPMH = 0x25,
+   L3_DIPML = 0x26,
+   L3_DIPLL = 0x27,
+   LD_VNI = 0x28,
+   IL3_FLAGS = 0x2b,
+   LF_SPI = 0x2e,
+   L4_SPORT = 0x2f,
+   L4_PORT = 0x30,
+   LG_CUSTOM = 0x39
+};
+
+enum pki_ltype {
+   LTYPE_NONE,
+   LTYPE_ENET,
+   LTYPE_VLAN,
+   LTYPE_SNAP_PAYLD = 0x05,
+   LTYPE_ARP = 0x06,
+   LTYPE_RARP = 0x07,
+   LTYPE_IP4 = 0x08,
+   LTYPE_IP4_OPT = 0x09,
+   LTYPE_IP6 = 0x0a,
+   LTYPE_IP6_OPT = 0x0b,
+   LTYPE_IPSEC_ESP = 0x0c,
+   LTYPE_IPFRAG = 0x0d,
+   LTYPE_IPCOMP = 0x0e,
+   LTYPE_TCP = 0x10,
+   LTYPE_UDP = 0x11,
+   LTYPE_SCTP = 0x12,
+   LTYPE_UDP_VXLAN = 0x13,
+   LTYPE_GRE = 0x14,
+   LTYPE_NVGRE = 0x15,
+   LTYPE_GTP = 0x16,
+   LTYPE_UDP_GENEVE

[PATCH v12 07/10] netdev: cavium: octeon: Add Octeon III SSO Support

[Steven J. Hill]

From: Carlos Munoz 

Add support for Octeon III SSO logic block for BGX Ethernet.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
---
 drivers/net/ethernet/cavium/octeon/octeon3-sso.c | 221 +++
 drivers/net/ethernet/cavium/octeon/octeon3-sso.h |  89 +
 2 files changed, 310 insertions(+)
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-sso.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-sso.h

diff --git a/drivers/net/ethernet/cavium/octeon/octeon3-sso.c 
b/drivers/net/ethernet/cavium/octeon/octeon3-sso.c
new file mode 100644
index 000..73afad0
--- /dev/null
+++ b/drivers/net/ethernet/cavium/octeon/octeon3-sso.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Octeon III Schedule/Synchronize/Order Unit (SSO)
+ *
+ * Copyright (C) 2018 Cavium, Inc.
+ */
+
+#include "octeon3.h"
+
+static int octeon3_sso_get_num_groups(void)
+{
+   if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+   return 256;
+   if (OCTEON_IS_MODEL(OCTEON_CNF75XX) || OCTEON_IS_MODEL(OCTEON_CN73XX))
+   return 64;
+   return 0;
+}
+
+void octeon3_sso_irq_set(int node, int group, bool enable)
+{
+   if (enable)
+   oct_csr_write(1, SSO_GRP_INT_THR(node, group));
+   else
+   oct_csr_write(0, SSO_GRP_INT_THR(node, group));
+
+   oct_csr_write(SSO_GRP_INT_EXE_INT, SSO_GRP_INT(node, group));
+}
+EXPORT_SYMBOL(octeon3_sso_irq_set);
+
+/* octeon3_sso_alloc_groups - Allocate a range of SSO groups.
+ * @node: Node where SSO resides.
+ * @groups: Pointer to allocated groups.
+ * @cnt: Number of groups to allocate.
+ * @start: Group number to start sequential allocation from. -1 for don't care.
+ *
+ * Returns 0 if successful, error code otherwise..
+ */
+int octeon3_sso_alloc_groups(int node, int *groups, int cnt, int start)
+{
+   struct global_resource_tag tag;
+   int group, ret;
+   char buf[16];
+
+   strncpy((char *), "cvm_sso_", 8);
+   snprintf(buf, 16, "0%d..", node);
+   memcpy(, buf, 8);
+
+   res_mgr_create_resource(tag, octeon3_sso_get_num_groups());
+
+   if (!groups)
+   ret = res_mgr_alloc_range(tag, start, cnt, false, );
+   if (!ret)
+   ret = group;
+   else
+   ret = res_mgr_alloc_range(tag, start, cnt, false, groups);
+
+   return ret;
+}
+EXPORT_SYMBOL(octeon3_sso_alloc_groups);
+
+/* octeon3_sso_free_groups - Free SSO groups.
+ * @node: Node where SSO resides.
+ * @groups: Array of groups to free.
+ * @cnt: Number of groups to free.
+ */
+void octeon3_sso_free_groups(int node, int *groups, intcnt)
+{
+   struct global_resource_tag tag;
+   char buf[16];
+
+   /* Allocate the requested groups. */
+   strncpy((char *), "cvm_sso_", 8);
+   snprintf(buf, 16, "0%d..", node);
+   memcpy(, buf, 8);
+
+   res_mgr_free_range(tag, groups, cnt);
+}
+EXPORT_SYMBOL(octeon3_sso_free_groups);
+
+/* octeon3_sso_pass1_limit - When the Transitory Admission Queue (TAQ) is
+ *   almost full, it is possible for the SSo to hang. We work around this
+ *   by ensuring that the sum of SSO_GRP(0..255)_TAQ_THR[MAX_THR] of all
+ *   used groups is <= 1264. This may reduce single group performance when
+ *   many groups are in use.
+ * @node: Node to update.
+ * @grp: SSO group to update.
+ */
+void octeon3_sso_pass1_limit(int node, int group)
+{
+   u64 max_thr, rsvd_thr, taq_add, taq_thr;
+
+   /* Ideally we would like to divide the maximum number of TAQ buffers
+* (1264) among the SSO groups in use. However, since we do not know
+* how many SSO groups are used by code outside this driver, we take
+* the worst case approach.
+*/
+   max_thr = 1264 / octeon3_sso_get_num_groups();
+   if (max_thr < 4)
+   max_thr = 4;
+   rsvd_thr = max_thr - 1;
+
+   /* Changes to SSO_GRP_TAQ_THR[rsvd_thr] must also update
+* SSO_TAQ_ADD[RSVD_FREE].
+*/
+   taq_thr = oct_csr_read(SSO_GRP_TAQ_THR(node, group));
+   taq_add = (rsvd_thr - (taq_thr & SSO_GRP_TAQ_THR_RSVD_THR_MASK)) <<
+ SSO_TAQ_ADD_RSVD_FREE_SHIFT;
+
+   taq_thr &= ~(SSO_GRP_TAQ_THR_MAX_THR_MASK |
+SSO_GRP_TAQ_THR_RSVD_THR_MASK);
+   taq_thr |= max_thr << SSO_GRP_TAQ_THR_RSVD_THR_SHIFT;
+   taq_thr |= rsvd_thr;
+
+   oct_csr_write(taq_thr, SSO_GRP_TAQ_THR(node, group));
+   oct_csr_write(taq_add, SSO_TAQ_ADD(node));
+}
+EXPORT_SYMBOL(octeon3_sso_pass1_limit);
+
+/* octeon3_sso_shutdown - Shutdown the SSO.
+ * @node: Node where SSO to disable is.
+ * @aura: Aura used for the SSO buffers.
+ */
+void octeon3_sso_shutdown(int node, int aura)
+{
+   int i, max_grps, timeout;
+   u64 data, head, tail;
+   void *ptr;
+
+   /* Disable SSO. */
+   data = oct_csr_read(SSO_AW_CFG(node));
+ 

[PATCH v12 00/10] netdev: octeon-ethernet: Add Cavium Octeon III support.

[Steven J. Hill]

Add the Cavium OCTEON III network driver. There are some corresponding
MIPS architecture support changes which will be upstreamed separately.

Changes in v12:

o Complete reorganization of driver files and defined all bitfields
  used in the driver.
o Implemented suggested changes from Andrew Lunn.
o Ran checkpatch and did whitespace cleanups.

Carlos Munoz (9):
  dt-bindings: Add Cavium Octeon Common Ethernet Interface.
  netdev: cavium: octeon: Header for Octeon III BGX Ethernet
  netdev: cavium: octeon: Add Octeon III BGX Ethernet Nexus
  netdev: cavium: octeon: Add Octeon III BGX Ports
  netdev: cavium: octeon: Add Octeon III PKI Support
  netdev: cavium: octeon: Add Octeon III PKO Support
  netdev: cavium: octeon: Add Octeon III SSO Support
  netdev: cavium: octeon: Add Octeon III BGX Ethernet core
  netdev: cavium: octeon: Add Octeon III BGX Ethernet building

David Daney (1):
  MAINTAINERS: Add entry for
drivers/net/ethernet/cavium/octeon/octeon3-*

 .../devicetree/bindings/net/cavium-bgx.txt |   59 +
 MAINTAINERS|6 +
 drivers/net/ethernet/cavium/Kconfig|   22 +-
 drivers/net/ethernet/cavium/octeon/Makefile|8 +-
 .../net/ethernet/cavium/octeon/octeon3-bgx-nexus.c |  670 ++
 .../net/ethernet/cavium/octeon/octeon3-bgx-port.c  | 2192 ++
 drivers/net/ethernet/cavium/octeon/octeon3-bgx.h   |  191 ++
 drivers/net/ethernet/cavium/octeon/octeon3-core.c  | 2363 
 drivers/net/ethernet/cavium/octeon/octeon3-pki.c   |  789 +++
 drivers/net/ethernet/cavium/octeon/octeon3-pki.h   |  113 +
 drivers/net/ethernet/cavium/octeon/octeon3-pko.c   | 1638 ++
 drivers/net/ethernet/cavium/octeon/octeon3-pko.h   |  159 ++
 drivers/net/ethernet/cavium/octeon/octeon3-sso.c   |  221 ++
 drivers/net/ethernet/cavium/octeon/octeon3-sso.h   |   89 +
 drivers/net/ethernet/cavium/octeon/octeon3.h   |  330 +++
 15 files changed, 8848 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/cavium-bgx.txt
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-nexus.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-port.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx.h
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-core.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pki.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pki.h
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pko.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pko.h
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-sso.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-sso.h
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3.h

-- 
2.1.4

[PATCH v12 03/10] netdev: cavium: octeon: Add Octeon III BGX Ethernet Nexus

[Steven J. Hill]

From: Carlos Munoz 

Add the BGX nexus architeture for Octeon III BGX Ethernet.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
---
 .../net/ethernet/cavium/octeon/octeon3-bgx-nexus.c | 670 +
 drivers/net/ethernet/cavium/octeon/octeon3-bgx.h   | 281 +
 2 files changed, 831 insertions(+), 120 deletions(-)
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-nexus.c

diff --git a/drivers/net/ethernet/cavium/octeon/octeon3-bgx-nexus.c 
b/drivers/net/ethernet/cavium/octeon/octeon3-bgx-nexus.c
new file mode 100644
index 000..fced298
--- /dev/null
+++ b/drivers/net/ethernet/cavium/octeon/octeon3-bgx-nexus.c
@@ -0,0 +1,670 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Octeon III BGX Nexus Ethernet driver
+ *
+ * Copyright (C) 2018 Cavium, Inc.
+ */
+
+#include 
+#include 
+#include 
+
+#include "octeon3.h"
+
+static atomic_t request_mgmt_once;
+static atomic_t load_driver_once;
+static atomic_t pki_id;
+
+static char *mix_port;
+module_param(mix_port, charp, 0444);
+MODULE_PARM_DESC(mix_port, "Specifies which ports connect to MIX interfaces.");
+
+static char *pki_port;
+module_param(pki_port, charp, 0444);
+MODULE_PARM_DESC(pki_port, "Specifies which ports connect to the PKI.");
+
+#define MAX_MIX_PER_NODE   2
+#define MAX_MIX(MAX_NODES * MAX_MIX_PER_NODE)
+
+/* struct mix_port_lmac - Describes a lmac that connects to a mix port. The 
lmac
+ *   must be on the same node as the mix.
+ * @node: Node of the lmac.
+ * @bgx: Bgx of the lmac.
+ * @lmac: Lmac index.
+ */
+struct mix_port_lmac {
+   int node;
+   int bgx;
+   int lmac;
+};
+
+/* mix_ports_lmacs contains all the lmacs connected to mix ports */
+static struct mix_port_lmac mix_port_lmacs[MAX_MIX];
+
+/* pki_ports keeps track of the lmacs connected to the pki */
+static bool pki_ports[MAX_NODES][MAX_BGX_PER_NODE][MAX_LMAC_PER_BGX];
+
+/* Created platform devices get added to this list */
+static struct list_head pdev_list;
+static struct mutex pdev_list_lock;
+
+/* Created platform device use this structure to add themselves to the list */
+struct pdev_list_item {
+   struct list_head list;
+   struct platform_device *pdev;
+};
+
+/* is_lmac_to_mix - Search the list of lmacs connected to mix'es for a match.
+ * @node: Numa node of lmac to search for.
+ * @bgx: Bgx of lmac to search for.
+ * @lmac: Lmac index to search for.
+ *
+ * Returns true if the lmac is connected to a mix.
+ * Returns false if the lmac is not connected to a mix.
+ */
+static bool is_lmac_to_mix(int node, int bgx, int lmac)
+{
+   int i;
+
+   for (i = 0; i < MAX_MIX; i++) {
+   if (mix_port_lmacs[i].node == node &&
+   mix_port_lmacs[i].bgx == bgx &&
+   mix_port_lmacs[i].lmac == lmac)
+   return true;
+   }
+
+   return false;
+}
+
+/* is_lmac_to_pki - Search the list of lmacs connected to the pki for a match.
+ * @node: Numa node of lmac to search for.
+ * @bgx: Bgx of lmac to search for.
+ * @lmac: Lmac index to search for.
+ *
+ * Returns true if the lmac is connected to the pki.
+ * Returns false if the lmac is not connected to the pki.
+ */
+static bool is_lmac_to_pki(int node, int bgx, int lmac)
+{
+   return pki_ports[node][bgx][lmac];
+}
+
+/* is_lmac_to_xcv - Check if this lmac is connected to the xcv block (rgmii).
+ * @of_node: Device node to check.
+ *
+ * Returns true if the lmac is connected to the xcv port.
+ * Returns false if the lmac is not connected to the xcv port.
+ */
+static bool is_lmac_to_xcv(struct device_node *of_node)
+{
+   return of_device_is_compatible(of_node, "cavium,octeon-7360-xcv");
+}
+
+static int bgx_probe(struct platform_device *pdev)
+{
+   struct platform_device *new_dev, *pki_dev;
+   struct mac_platform_data platform_data;
+   int i, interface, numa_node, r = 0;
+   struct device_node *child;
+   const __be32 *reg;
+   u64 addr, data;
+   char id[64];
+   u32 port;
+
+   reg = of_get_property(pdev->dev.of_node, "reg", NULL);
+   addr = of_translate_address(pdev->dev.of_node, reg);
+   interface = (addr >> 24) & 0xf;
+   numa_node = (addr >> 36) & 0x7;
+
+   /* Assign 8 CAM entries per LMAC */
+   for (i = 0; i < 32; i++) {
+   data = i >> 3;
+   oct_csr_write(data,
+ BGX_CMR_RX_ADRX_CAM(numa_node, interface, i));
+   }
+
+   for_each_available_child_of_node(pdev->dev.of_node, child) {
+   struct pdev_list_item *pdev_item;
+   bool is_mix = false;
+   bool is_pki = false;
+   bool is_xcv = false;
+
+   if (!of_device_is_compatible(child, 
"cavium,octeon-7890-bgx-port") &&
+   !of_device_is_compat

[PATCH net-next v11 08/10] netdev: cavium: octeon: Add Octeon III BGX Ethernet core

[Steven J. Hill]

From: Carlos Munoz 

This is the main core of the BGX Ethernet driver.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
---
 drivers/net/ethernet/cavium/octeon/octeon3-core.c | 2380 +
 1 file changed, 2380 insertions(+)
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-core.c

diff --git a/drivers/net/ethernet/cavium/octeon/octeon3-core.c 
b/drivers/net/ethernet/cavium/octeon/octeon3-core.c
new file mode 100644
index 000..1e2f68d
--- /dev/null
+++ b/drivers/net/ethernet/cavium/octeon/octeon3-core.c
@@ -0,0 +1,2380 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Octeon III BGX Nexus Ethernet driver core
+ *
+ * Copyright (C) 2018 Cavium, Inc.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "octeon3.h"
+
+/*  First buffer:
+ *
+ *+---SKB-+
+ *|   |
+ *|   |
+ * +--+--*data|
+ * |  |   |
+ * |  |   |
+ * |  +---+
+ * |   /|\
+ * ||
+ * ||
+ *\|/   |
+ * WQE - 128 -+-> +-+---+ -+-
+ *|   |*skb +   |  |
+ *|   | |  |
+ *|   | |  |
+ *  WQE_SKIP = 128| |  |
+ *|   | |  |
+ *|   | |  |
+ *|   | |  |
+ *|   | |  First Skip
+ * WQE   -+-> +-+  |
+ *|   word 0|  |
+ *|   word 1|  |
+ *|   word 2|  |
+ *|   word 3|  |
+ *|   word 4|  |
+ *+-+ -+-
+ *   ++- packet link|
+ *   ||  packet data|
+ *   || |
+ *   || |
+ *   || .   |
+ *   || .   |
+ *   || .   |
+ *   |+-+
+ *   |
+ *   |
+ * Later buffers:|
+ *   |
+ *   |
+ *   |
+ *   |
+ *   |
+ *   |+---SKB-+
+ *   ||   |
+ *   ||   |
+ *   | +--+--*data|
+ *   | |  |   |
+ *   | |  |   |
+ *   | |  +---+
+ *   | |   /|\
+ *   | ||
+ *   | ||
+ *   |\|/   |
+ * WQE - 128 +--> +-+---+ -+-
+ *   ||*skb +   |  |
+ *   || |  |
+ *   || |  |
+ *   || |  |
+ *   || |  LATER_SKIP = 128
+ *   || |  |
+ *   || |  |
+ *   || |  |
+ *   |+-+ -+-
+ *   ||  packet link|
+ *   +--> |  packet data|
+ *| |
+ *| |
+ *| .   |
+ *| .   |
+ *| .   |
+ *+-+
+ */
+
+#define MAX_TX_QUEUE_DEPTH 512
+#define SSO_INTSN_EXE 0x61
+#define MAX_RX_CONTEXTS 32
+
+#define SKB_PTR_OFFSET 0
+#define SKB_AURA_OFFSET1
+#define SKB_AURA_MAGIC 0xbadc0ffee4dad000ULL
+
+#define MAX_CORES  48
+#define FPA3_NUM_AURAS 1024
+
+#define USE_ASYNC_IOBDMA   1
+#define SCR_SCRATCH0ull
+#define SSO_NO_WAIT0ull
+#define DID_TAG_SWTAG  0x60ull
+#define IOBDMA_SENDSINGLE  0xa200ull
+
+/* Values for the value of wqe word2 [ERRLEV] */
+#define PKI_ERRLEV_LA  0x01
+
+/* Values for the value of wqe word2 [OPCODE] */
+#define PKI_OPCODE_NONE0x00
+#define PKI_OPCODE_JABBER  0x02
+#define PKI_OPCODE_FCS 0x07
+
+/* Values for the

[PATCH net-next v11 09/10] netdev: cavium: octeon: Add Octeon III BGX Ethernet building

[Steven J. Hill]

From: Carlos Munoz 

Add the build and configuration files for the BGX Ethernet.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
---
 drivers/net/ethernet/cavium/Kconfig | 22 +-
 drivers/net/ethernet/cavium/octeon/Makefile |  8 +++-
 2 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/cavium/Kconfig 
b/drivers/net/ethernet/cavium/Kconfig
index 043e3c1..3b9709d 100644
--- a/drivers/net/ethernet/cavium/Kconfig
+++ b/drivers/net/ethernet/cavium/Kconfig
@@ -4,7 +4,7 @@
 
 config NET_VENDOR_CAVIUM
bool "Cavium ethernet drivers"
-   depends on PCI
+   depends on PCI || CAVIUM_OCTEON_SOC
default y
---help---
  Select this option if you want enable Cavium network support.
@@ -100,4 +100,24 @@ config LIQUIDIO_VF
  will be called liquidio_vf. MSI-X interrupt support is required
  for this driver to work correctly
 
+config OCTEON3_BGX_PORT
+   tristate "Cavium Octeon III BGX port support"
+   depends on CAVIUM_OCTEON_SOC
+   ---help---
+ This driver adds support for Cavium Octeon III BGX ports. BGX ports
+ support sgmii, rgmii, xaui, rxaui, xlaui, xfi, 10KR and 40KR modes.
+
+ Say Y to use the management port on Octeon III boards or to use
+ any other ethernet port.
+
+config OCTEON3_ETHERNET
+   tristate "Cavium OCTEON III PKI/PKO Ethernet support"
+   depends on CAVIUM_OCTEON_SOC
+   select OCTEON_BGX_PORT
+   select OCTEON_FPA3
+   select FW_LOADER
+   ---help---
+ Support for 'BGX' Ethernet via PKI/PKO units. No support for
+ cn70xx chips, use OCTEON_ETHERNET instead.
+
 endif # NET_VENDOR_CAVIUM
diff --git a/drivers/net/ethernet/cavium/octeon/Makefile 
b/drivers/net/ethernet/cavium/octeon/Makefile
index efa41c1..1939c84 100644
--- a/drivers/net/ethernet/cavium/octeon/Makefile
+++ b/drivers/net/ethernet/cavium/octeon/Makefile
@@ -1,5 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0
 #
 # Makefile for the Cavium network device drivers.
 #
 
-obj-$(CONFIG_OCTEON_MGMT_ETHERNET) += octeon_mgmt.o
+obj-$(CONFIG_OCTEON_MGMT_ETHERNET) += octeon_mgmt.o
+obj-$(CONFIG_OCTEON3_BGX_PORT) += octeon3-bgx-nexus.o octeon3-bgx-port.o
+obj-$(CONFIG_OCTEON3_ETHERNET) += octeon3-ethernet.o
+
+octeon3-ethernet-objs += octeon3-core.o octeon3-pki.o octeon3-pko.o\
+octeon3-sso.o
-- 
2.1.4

[PATCH net-next v11 06/10] netdev: cavium: octeon: Add Octeon III PKO Support

[Steven J. Hill]

From: Carlos Munoz 

Add support for Octeon III PKO logic block for BGX Ethernet.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
---
 drivers/net/ethernet/cavium/octeon/octeon3-pko.c | 1619 ++
 1 file changed, 1619 insertions(+)
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pko.c

diff --git a/drivers/net/ethernet/cavium/octeon/octeon3-pko.c 
b/drivers/net/ethernet/cavium/octeon/octeon3-pko.c
new file mode 100644
index 000..eb4c016
--- /dev/null
+++ b/drivers/net/ethernet/cavium/octeon/octeon3-pko.c
@@ -0,0 +1,1619 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Octeon III Packet-Output Processing Unit (PKO)
+ *
+ * Copyright (C) 2018 Cavium, Inc.
+ */
+
+#include "octeon3.h"
+
+#define MAX_OUTPUT_MAC 28
+#define MAX_FIFO_GRP   8
+
+#define FIFO_SIZE  2560
+
+/* Registers are accessed via xkphys */
+#define PKO_BASE   0x15400ull
+#define PKO_ADDR(node) (SET_XKPHYS + NODE_OFFSET(node) +  \
+PKO_BASE)
+
+#define PKO_L1_SQ_SHAPE(n, q)  (PKO_ADDR(n) + ((q) << 9)+ 0x10)
+#define PKO_L1_SQ_LINK(n, q)   (PKO_ADDR(n) + ((q) << 9)+ 0x38)
+#define PKO_DQ_WM_CTL(n, q)(PKO_ADDR(n) + ((q) << 9)+ 0x40)
+#define PKO_L1_SQ_TOPOLOGY(n, q)   (PKO_ADDR(n) + ((q) << 9)+ 0x08)
+#define PKO_L2_SQ_SCHEDULE(n, q)   (PKO_ADDR(n) + ((q) << 9)+ 0x080008)
+#define PKO_L3_L2_SQ_CHANNEL(n, q) (PKO_ADDR(n) + ((q) << 9)+ 0x080038)
+#define PKO_CHANNEL_LEVEL(n)   (PKO_ADDR(n) + 0x0800f0)
+#define PKO_SHAPER_CFG(n)  (PKO_ADDR(n) + 0x0800f8)
+#define PKO_L2_SQ_TOPOLOGY(n, q)   (PKO_ADDR(n) + ((q) << 9)+ 0x10)
+#define PKO_L3_SQ_SCHEDULE(n, q)   (PKO_ADDR(n) + ((q) << 9)+ 0x18)
+#define PKO_L3_SQ_TOPOLOGY(n, q)   (PKO_ADDR(n) + ((q) << 9)+ 0x18)
+#define PKO_L4_SQ_SCHEDULE(n, q)   (PKO_ADDR(n) + ((q) << 9)+ 0x180008)
+#define PKO_L4_SQ_TOPOLOGY(n, q)   (PKO_ADDR(n) + ((q) << 9)+ 0x20)
+#define PKO_L5_SQ_SCHEDULE(n, q)   (PKO_ADDR(n) + ((q) << 9)+ 0x28)
+#define PKO_L5_SQ_TOPOLOGY(n, q)   (PKO_ADDR(n) + ((q) << 9)+ 0x28)
+#define PKO_DQ_SCHEDULE(n, q)  (PKO_ADDR(n) + ((q) << 9)+ 0x280008)
+#define PKO_DQ_SW_XOFF(n, q)   (PKO_ADDR(n) + ((q) << 9)+ 0x2800e0)
+#define PKO_DQ_TOPOLOGY(n, q)  (PKO_ADDR(n) + ((q) << 9)+ 0x30)
+#define PKO_PDM_CFG(n) (PKO_ADDR(n) + 0x80)
+#define PKO_PDM_DQ_MINPAD(n, q)(PKO_ADDR(n) + ((q) << 3)+ 
0x8f)
+#define PKO_MAC_CFG(n, m)  (PKO_ADDR(n) + ((m) << 3)+ 0x90)
+#define PKO_PTF_STATUS(n, f)   (PKO_ADDR(n) + ((f) << 3)+ 0x900100)
+#define PKO_PTGF_CFG(n, g) (PKO_ADDR(n) + ((g) << 3)+ 0x900200)
+#define PKO_PTF_IOBP_CFG(n)(PKO_ADDR(n) + 0x900300)
+#define PKO_MCI0_MAX_CRED(n, m)(PKO_ADDR(n) + ((m) << 3)+ 
0xa0)
+#define PKO_MCI1_MAX_CRED(n, m)(PKO_ADDR(n) + ((m) << 3)+ 
0xa8)
+#define PKO_LUT(n, c)  (PKO_ADDR(n) + ((c) << 3)+ 0xb0)
+#define PKO_DPFI_STATUS(n) (PKO_ADDR(n) + 0xc0)
+#define PKO_DPFI_FLUSH(n)  (PKO_ADDR(n) + 0xc8)
+#define PKO_DPFI_FPA_AURA(n)   (PKO_ADDR(n) + 0xc00010)
+#define PKO_DPFI_ENA(n)(PKO_ADDR(n) + 
0xc00018)
+#define PKO_STATUS(n)  (PKO_ADDR(n) + 0xd0)
+#define PKO_ENABLE(n)  (PKO_ADDR(n) + 0xd8)
+
+/* These levels mimic the PKO internal linked queue structure */
+enum queue_level {
+   PQ = 1,
+   L2_SQ = 2,
+   L3_SQ = 3,
+   L4_SQ = 4,
+   L5_SQ = 5,
+   DQ = 6
+};
+
+enum pko_dqop_e {
+   DQOP_SEND,
+   DQOP_OPEN,
+   DQOP_CLOSE,
+   DQOP_QUERY
+};
+
+enum pko_dqstatus_e {
+   PASS = 0,
+   BADSTATE = 0x8,
+   NOFPABUF = 0x9,
+   NOPKOBUF = 0xa,
+   FAILRTNPTR = 0xb,
+   ALREADY = 0xc,
+   NOTCREATED = 0xd,
+   NOTEMPTY = 0xe,
+   SENDPKTDROP = 0xf
+};
+
+struct mac_info {
+   int fifo_cnt;
+   int prio;
+   int speed;
+   int fifo;
+   int num_lmacs;
+};
+
+struct fifo_grp_info {
+   int speed;
+   int size;
+};
+
+static const int lut_index_78xx[] = {
+   0x200,
+   0x240,
+   0x280,
+   0x2c0,
+   0x300,
+   0x340
+};
+
+static const int lut_index_73xx[] = {
+   0x000,
+   0x040,
+   0x080
+};
+
+static enum queue_level max_sq_level(void)
+{
+   /* 73xx and 75

[PATCH net-next v11 10/10] MAINTAINERS: Add entry for drivers/net/ethernet/cavium/octeon/octeon3-*

[Steven J. Hill]

From: David Daney 

Signed-off-by: David Daney 
---
 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 70d61c2..9ab8b69 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3249,6 +3249,12 @@ W:   http://www.cavium.com
 S: Supported
 F: drivers/mmc/host/cavium*
 
+CAVIUM OCTEON-III NETWORK DRIVER
+M: Steven J. Hill 
+L: netdev@vger.kernel.org
+S: Supported
+F: drivers/net/ethernet/cavium/octeon/octeon3-*
+
 CAVIUM OCTEON-TX CRYPTO DRIVER
 M: George Cherian 
 L: linux-cry...@vger.kernel.org
-- 
2.1.4

[PATCH net-next v11 03/10] netdev: cavium: octeon: Add Octeon III BGX Ethernet Nexus

[Steven J. Hill]

From: Carlos Munoz 

Add the BGX nexus architeture for Octeon III BGX Ethernet.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
---
 .../net/ethernet/cavium/octeon/octeon3-bgx-nexus.c | 673 +
 1 file changed, 673 insertions(+)
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-nexus.c

diff --git a/drivers/net/ethernet/cavium/octeon/octeon3-bgx-nexus.c 
b/drivers/net/ethernet/cavium/octeon/octeon3-bgx-nexus.c
new file mode 100644
index 000..f9c45d7
--- /dev/null
+++ b/drivers/net/ethernet/cavium/octeon/octeon3-bgx-nexus.c
@@ -0,0 +1,673 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Octeon III BGX Nexus Ethernet driver
+ *
+ * Copyright (C) 2018 Cavium, Inc.
+ */
+
+#include 
+#include 
+#include 
+
+#include "octeon3.h"
+
+static atomic_t request_mgmt_once;
+static atomic_t load_driver_once;
+static atomic_t pki_id;
+
+static char *mix_port;
+module_param(mix_port, charp, 0444);
+MODULE_PARM_DESC(mix_port, "Specifies which ports connect to MIX interfaces.");
+
+static char *pki_port;
+module_param(pki_port, charp, 0444);
+MODULE_PARM_DESC(pki_port, "Specifies which ports connect to the PKI.");
+
+#define MAX_MIX_PER_NODE   2
+#define MAX_MIX(MAX_NODES * MAX_MIX_PER_NODE)
+
+/* struct mix_port_lmac - Describes a lmac that connects to a mix port. The 
lmac
+ *   must be on the same node as the mix.
+ * @node: Node of the lmac.
+ * @bgx: Bgx of the lmac.
+ * @lmac: Lmac index.
+ */
+struct mix_port_lmac {
+   int node;
+   int bgx;
+   int lmac;
+};
+
+/* mix_ports_lmacs contains all the lmacs connected to mix ports */
+static struct mix_port_lmac mix_port_lmacs[MAX_MIX];
+
+/* pki_ports keeps track of the lmacs connected to the pki */
+static bool pki_ports[MAX_NODES][MAX_BGX_PER_NODE][MAX_LMAC_PER_BGX];
+
+/* Created platform devices get added to this list */
+static struct list_head pdev_list;
+static struct mutex pdev_list_lock;
+
+/* Created platform device use this structure to add themselves to the list */
+struct pdev_list_item {
+   struct list_head list;
+   struct platform_device *pdev;
+};
+
+/* is_lmac_to_mix - Search the list of lmacs connected to mix'es for a match.
+ * @node: Numa node of lmac to search for.
+ * @bgx: Bgx of lmac to search for.
+ * @lmac: Lmac index to search for.
+ *
+ * Returns true if the lmac is connected to a mix.
+ * Returns false if the lmac is not connected to a mix.
+ */
+static bool is_lmac_to_mix(int node, int bgx, int lmac)
+{
+   int i;
+
+   for (i = 0; i < MAX_MIX; i++) {
+   if (mix_port_lmacs[i].node == node &&
+   mix_port_lmacs[i].bgx == bgx &&
+   mix_port_lmacs[i].lmac == lmac)
+   return true;
+   }
+
+   return false;
+}
+
+/* is_lmac_to_pki - Search the list of lmacs connected to the pki for a match.
+ * @node: Numa node of lmac to search for.
+ * @bgx: Bgx of lmac to search for.
+ * @lmac: Lmac index to search for.
+ *
+ * Returns true if the lmac is connected to the pki.
+ * Returns false if the lmac is not connected to the pki.
+ */
+static bool is_lmac_to_pki(int node, int bgx, int lmac)
+{
+   return pki_ports[node][bgx][lmac];
+}
+
+/* is_lmac_to_xcv - Check if this lmac is connected to the xcv block (rgmii).
+ * @of_node: Device node to check.
+ *
+ * Returns true if the lmac is connected to the xcv port.
+ * Returns false if the lmac is not connected to the xcv port.
+ */
+static bool is_lmac_to_xcv(struct device_node *of_node)
+{
+   return of_device_is_compatible(of_node, "cavium,octeon-7360-xcv");
+}
+
+static int bgx_probe(struct platform_device *pdev)
+{
+   struct platform_device *new_dev, *pki_dev;
+   struct mac_platform_data platform_data;
+   int i, interface, numa_node, r = 0;
+   struct device_node *child;
+   const __be32 *reg;
+   u64 addr, data;
+   char id[64];
+   u32 port;
+
+   reg = of_get_property(pdev->dev.of_node, "reg", NULL);
+   addr = of_translate_address(pdev->dev.of_node, reg);
+   interface = (addr >> 24) & 0xf;
+   numa_node = (addr >> 36) & 0x7;
+
+   /* Assign 8 CAM entries per LMAC */
+   for (i = 0; i < 32; i++) {
+   data = i >> 3;
+   oct_csr_write(data,
+ BGX_CMR_RX_ADRX_CAM(numa_node, interface, i));
+   }
+
+   for_each_available_child_of_node(pdev->dev.of_node, child) {
+   struct pdev_list_item *pdev_item;
+   bool is_mix = false;
+   bool is_pki = false;
+   bool is_xcv = false;
+
+   if (!of_device_is_compatible(child, 
"cavium,octeon-7890-bgx-port") &&
+   !of_device_is_compatible(child, "cavium,octeon-7360-xcv"))
+   continue;
+   r = of_prop

[PATCH net-next v11 00/10] netdev: octeon-ethernet: Add Cavium Octeon III support.

[Steven J. Hill]

Add the Cavium OCTEON III network driver. There are some corresponding
MIPS architecture support changes which will be upstreamed separately.

Changes in v11:

o Massive clean-up of files, split big patch into smaller pieces,
  and some minor rework.

Carlos Munoz (9):
  dt-bindings: Add Cavium Octeon Common Ethernet Interface.
  netdev: cavium: octeon: Header for Octeon III BGX Ethernet
  netdev: cavium: octeon: Add Octeon III BGX Ethernet Nexus
  netdev: cavium: octeon: Add Octeon III BGX Ports
  netdev: cavium: octeon: Add Octeon III PKI Support
  netdev: cavium: octeon: Add Octeon III PKO Support
  netdev: cavium: octeon: Add Octeon III SSO Support
  netdev: cavium: octeon: Add Octeon III BGX Ethernet core
  netdev: cavium: octeon: Add Octeon III BGX Ethernet building

David Daney (1):
  MAINTAINERS: Add entry for
drivers/net/ethernet/cavium/octeon/octeon3-*

 .../devicetree/bindings/net/cavium-bgx.txt |   59 +
 MAINTAINERS|6 +
 drivers/net/ethernet/cavium/Kconfig|   22 +-
 drivers/net/ethernet/cavium/octeon/Makefile|8 +-
 .../net/ethernet/cavium/octeon/octeon3-bgx-nexus.c |  673 ++
 .../net/ethernet/cavium/octeon/octeon3-bgx-port.c  | 2196 ++
 drivers/net/ethernet/cavium/octeon/octeon3-core.c  | 2380 
 drivers/net/ethernet/cavium/octeon/octeon3-pki.c   |  781 +++
 drivers/net/ethernet/cavium/octeon/octeon3-pko.c   | 1619 +
 drivers/net/ethernet/cavium/octeon/octeon3-sso.c   |  244 ++
 drivers/net/ethernet/cavium/octeon/octeon3.h   |  409 
 11 files changed, 8395 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/cavium-bgx.txt
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-nexus.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-port.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-core.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pki.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pko.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-sso.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3.h

-- 
2.1.4

[PATCH net-next v11 02/10] netdev: cavium: octeon: Header for Octeon III BGX Ethernet

[Steven J. Hill]

From: Carlos Munoz 

Add the common header file used by the Octeon III BGX Ethernet
driver.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
---
 drivers/net/ethernet/cavium/octeon/octeon3.h | 409 +++
 1 file changed, 409 insertions(+)
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3.h

diff --git a/drivers/net/ethernet/cavium/octeon/octeon3.h 
b/drivers/net/ethernet/cavium/octeon/octeon3.h
new file mode 100644
index 000..2a64e1e
--- /dev/null
+++ b/drivers/net/ethernet/cavium/octeon/octeon3.h
@@ -0,0 +1,409 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Octeon III BGX Ethernet Driver 
+ *
+ * Copyright (C) 2018 Cavium, Inc.
+ */
+#ifndef _OCTEON3_H_
+#define _OCTEON3_H_
+
+#include 
+#include 
+#include 
+
+#include 
+
+#define MAX_NODES  2
+#define NODE_MASK  (MAX_NODES - 1)
+#define MAX_BGX_PER_NODE   6
+#define MAX_LMAC_PER_BGX   4
+
+#define IOBDMA_ORDERED_IO_ADDR 0xa200ull
+#define LMTDMA_ORDERED_IO_ADDR 0xa400ull
+
+#define SCRATCH_BASE   0x8000ull
+#define PKO_LMTLINE2ull
+#define LMTDMA_SCR_OFFSET  (PKO_LMTLINE * CVMX_CACHE_LINE_SIZE)
+
+/* Pko sub-command three bit codes (SUBDC3) */
+#define PKO_SENDSUBDC_GATHER   0x1
+
+/* Pko sub-command four bit codes (SUBDC4) */
+#define PKO_SENDSUBDC_TSO  0x8
+#define PKO_SENDSUBDC_FREE 0x9
+#define PKO_SENDSUBDC_WORK 0xa
+#define PKO_SENDSUBDC_MEM  0xc
+#define PKO_SENDSUBDC_EXT  0xd
+
+#define BGX_RX_FIFO_SIZE   (64 * 1024)
+#define BGX_TX_FIFO_SIZE   (32 * 1024)
+
+/* Registers are accessed via xkphys */
+#define SET_XKPHYS BIT_ULL(63)
+#define NODE_OFFSET(node)  ((node) * 0x10ull)
+
+/* Bgx register definitions */
+#define BGX_BASE   0x11800e000ull
+#define BGX_OFFSET(bgx)(BGX_BASE + ((bgx) << 24))
+#define INDEX_OFFSET(index)((index) << 20)
+#define INDEX_ADDR(n, b, i)(SET_XKPHYS + NODE_OFFSET(n) + \
+BGX_OFFSET(b) + INDEX_OFFSET(i))
+#define CAM_OFFSET(mac)((mac) << 3)
+#define CAM_ADDR(n, b, m)  (INDEX_ADDR(n, b, 0) + CAM_OFFSET(m))
+
+#define BGX_CMR_CONFIG(n, b, i)(INDEX_ADDR(n, b, i)  + 
0x0)
+#define BGX_CMR_GLOBAL_CONFIG(n, b)(INDEX_ADDR(n, b, 0)  + 0x8)
+#define BGX_CMR_RX_ID_MAP(n, b, i) (INDEX_ADDR(n, b, i)  + 0x00028)
+#define BGX_CMR_RX_BP_ON(n, b, i)  (INDEX_ADDR(n, b, i)  + 0x00088)
+#define BGX_CMR_RX_ADR_CTL(n, b, i)(INDEX_ADDR(n, b, i)  + 0x000a0)
+#define BGX_CMR_RX_FIFO_LEN(n, b, i)   (INDEX_ADDR(n, b, i)  + 0x000c0)
+#define BGX_CMR_RX_ADRX_CAM(n, b, m)   (CAM_ADDR(n, b, m)+ 0x00100)
+#define BGX_CMR_CHAN_MSK_AND(n, b) (INDEX_ADDR(n, b, 0)  + 0x00200)
+#define BGX_CMR_CHAN_MSK_OR(n, b)  (INDEX_ADDR(n, b, 0)  + 0x00208)
+#define BGX_CMR_TX_FIFO_LEN(n, b, i)   (INDEX_ADDR(n, b, i)  + 0x00418)
+#define BGX_CMR_TX_LMACS(n, b) (INDEX_ADDR(n, b, 0)  + 0x01000)
+
+#define BGX_SPU_CONTROL1(n, b, i)  (INDEX_ADDR(n, b, i)  + 0x1)
+#define BGX_SPU_STATUS1(n, b, i)   (INDEX_ADDR(n, b, i)  + 0x10008)
+#define BGX_SPU_STATUS2(n, b, i)   (INDEX_ADDR(n, b, i)  + 0x10020)
+#define BGX_SPU_BX_STATUS(n, b, i) (INDEX_ADDR(n, b, i)  + 0x10028)
+#define BGX_SPU_BR_STATUS1(n, b, i)(INDEX_ADDR(n, b, i)  + 0x10030)
+#define BGX_SPU_BR_STATUS2(n, b, i)(INDEX_ADDR(n, b, i)  + 0x10038)
+#define BGX_SPU_BR_BIP_ERR_CNT(n, b, i)(INDEX_ADDR(n, b, i)  + 
0x10058)
+#define BGX_SPU_BR_PMD_CONTROL(n, b, i)(INDEX_ADDR(n, b, i)  + 
0x10068)
+#define BGX_SPU_BR_PMD_LP_CUP(n, b, i) (INDEX_ADDR(n, b, i)  + 0x10078)
+#define BGX_SPU_BR_PMD_LD_CUP(n, b, i) (INDEX_ADDR(n, b, i)  + 0x10088)
+#define BGX_SPU_BR_PMD_LD_REP(n, b, i) (INDEX_ADDR(n, b, i)  + 0x10090)
+#define BGX_SPU_FEC_CONTROL(n, b, i)   (INDEX_ADDR(n, b, i)  + 0x100a0)
+#define BGX_SPU_AN_CONTROL(n, b, i)(INDEX_ADDR(n, b, i)  + 0x100c8)
+#define BGX_SPU_AN_STATUS(n, b, i) (INDEX_ADDR(n, b, i)  + 0x100d0)
+#define BGX_SPU_AN_ADV(n, b, i)(INDEX_ADDR(n, b, i)  + 
0x100d8)
+#define BGX_SPU_MISC_CONTROL(n, b, i)  (INDEX_ADDR(n, b, i)  + 0x10218)
+#define BGX_SPU_INT(n, b, i)   (INDEX_ADDR(n, b, i)  + 0x10220)
+#define BGX_SPU_DBG_CONTROL(n, b)  (INDEX_ADDR(n, b, 0)  + 0x10300)
+
+#define BGX_SMU_RX_INT(n, b, i)(INDEX_ADDR(n, b, i)  + 
0x2)
+#define BGX_SMU_RX_FRM_CTL(n, b, i)(INDEX_ADDR(n, b, i)  +

[PATCH net-next v11 05/10] netdev: cavium: octeon: Add Octeon III PKI Support

[Steven J. Hill]

From: Carlos Munoz 

Add support for Octeon III PKI logic block for BGX Ethernet.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
---
 drivers/net/ethernet/cavium/octeon/octeon3-pki.c | 781 +++
 1 file changed, 781 insertions(+)
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pki.c

diff --git a/drivers/net/ethernet/cavium/octeon/octeon3-pki.c 
b/drivers/net/ethernet/cavium/octeon/octeon3-pki.c
new file mode 100644
index 000..63e136b
--- /dev/null
+++ b/drivers/net/ethernet/cavium/octeon/octeon3-pki.c
@@ -0,0 +1,781 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Octeon III Packet Input Unit (PKI)
+ *
+ * Copyright (C) 2018 Cavium, Inc.
+ */
+
+#include 
+
+#include "octeon3.h"
+
+#define PKI_CLUSTER_FIRMWARE   "cavium/pki-cluster.bin"
+#define VERSION_LEN8
+
+#define MAX_CLUSTERS   4
+#define MAX_BANKS  2
+#define MAX_BANK_ENTRIES   192
+#define PKI_NUM_QPG_ENTRY  2048
+#define PKI_NUM_STYLE  256
+#define PKI_NUM_FINAL_STYLE64
+#define MAX_PKNDS  64
+
+/* Registers are accessed via xkphys */
+#define PKI_BASE   0x118004400ull
+#define PKI_ADDR(node) (SET_XKPHYS + NODE_OFFSET(node) +  \
+PKI_BASE)
+
+#define PKI_SFT_RST(n) (PKI_ADDR(n) + 0x10)
+#define PKI_BUF_CTL(n) (PKI_ADDR(n) + 0x000100)
+#define PKI_STAT_CTL(n)(PKI_ADDR(n) + 
0x000110)
+#define PKI_ICG_CFG(n) (PKI_ADDR(n) + 0x00a000)
+
+#define CLUSTER_OFFSET(c)  ((c) << 16)
+#define CL_ADDR(n, c)  (PKI_ADDR(n) + CLUSTER_OFFSET(c))
+#define PKI_CL_ECC_CTL(n, c)   (CL_ADDR(n, c)   + 0x00c020)
+
+#define PKI_STYLE_BUF(n, s)(PKI_ADDR(n) + ((s) << 3)+ 0x024000)
+
+#define PKI_LTYPE_MAP(n, l)(PKI_ADDR(n) + ((l) << 3)+ 0x005000)
+#define PKI_IMEM(n, i) (PKI_ADDR(n) + ((i) << 3)+ 0x10)
+
+#define PKI_CL_PKIND_CFG(n, c, p)  (CL_ADDR(n, c) + ((p) << 8)  + 0x300040)
+#define PKI_CL_PKIND_STYLE(n, c, p)(CL_ADDR(n, c) + ((p) << 8)  + 0x300048)
+#define PKI_CL_PKIND_SKIP(n, c, p) (CL_ADDR(n, c) + ((p) << 8)  + 0x300050)
+#define PKI_CL_PKIND_L2_CUSTOM(n, c, p)(CL_ADDR(n, c) + ((p) << 8)  + 
0x300058)
+#define PKI_CL_PKIND_LG_CUSTOM(n, c, p)(CL_ADDR(n, c) + ((p) << 8)  + 
0x300060)
+
+#define STYLE_OFFSET(s)((s) << 3)
+#define STYLE_ADDR(n, c, s)(PKI_ADDR(n) + CLUSTER_OFFSET(c) + \
+STYLE_OFFSET(s))
+#define PKI_CL_STYLE_CFG(n, c, s)  (STYLE_ADDR(n, c, s) + 0x50)
+#define PKI_CL_STYLE_CFG2(n, c, s) (STYLE_ADDR(n, c, s) + 0x500800)
+#define PKI_CLX_STYLEX_ALG(n, c, s)(STYLE_ADDR(n, c, s) + 0x501000)
+
+#define PCAM_OFFSET(bank)  ((bank) << 12)
+#define PCAM_ENTRY_OFFSET(entry)   ((entry) << 3)
+#define PCAM_ADDR(n, c, b, e)  (PKI_ADDR(n) + CLUSTER_OFFSET(c) + \
+PCAM_OFFSET(b) + PCAM_ENTRY_OFFSET(e))
+#define PKI_CL_PCAM_TERM(n, c, b, e)   (PCAM_ADDR(n, c, b, e)   + 0x70)
+#define PKI_CL_PCAM_MATCH(n, c, b, e)  (PCAM_ADDR(n, c, b, e)   + 0x704000)
+#define PKI_CL_PCAM_ACTION(n, c, b, e) (PCAM_ADDR(n, c, b, e)   + 0x708000)
+
+#define PKI_QPG_TBLX(n, i) (PKI_ADDR(n) + ((i) << 3)+ 0x80)
+#define PKI_AURAX_CFG(n, a)(PKI_ADDR(n) + ((a) << 3)+ 0x90)
+#define PKI_STATX_STAT0(n, p)  (PKI_ADDR(n) + ((p) << 8)+ 0xe00038)
+#define PKI_STATX_STAT1(n, p)  (PKI_ADDR(n) + ((p) << 8)+ 0xe00040)
+#define PKI_STATX_STAT3(n, p)  (PKI_ADDR(n) + ((p) << 8)+ 0xe00050)
+
+enum pcam_term {
+   NONE,
+   L2_CUSTOM = 0x2,
+   HIGIGD = 0x4,
+   HIGIG = 0x5,
+   SMACH = 0x8,
+   SMACL = 0x9,
+   DMACH = 0xa,
+   DMACL = 0xb,
+   GLORT = 0x12,
+   DSA = 0x13,
+   ETHTYPE0 = 0x18,
+   ETHTYPE1 = 0x19,
+   ETHTYPE2 = 0x1a,
+   ETHTYPE3 = 0x1b,
+   MPLS0 = 0x1e,
+   L3_SIPHH = 0x1f,
+   L3_SIPMH = 0x20,
+   L3_SIPML = 0x21,
+   L3_SIPLL = 0x22,
+   L3_FLAGS = 0x23,
+   L3_DIPHH = 0x24,
+   L3_DIPMH = 0x25,
+   L3_DIPML = 0x26,
+   L3_DIPLL = 0x27,
+   LD_VNI = 0x28,
+   IL3_FLAGS = 0x2b,
+   LF_SPI = 0x2e,
+   L4_SPORT = 0x2f,
+   L4_PORT = 0x30,
+   LG_CUSTOM = 0x39
+};
+
+enum pki_ltype {
+   LTYPE_NONE,
+   LTYPE_ENET,
+   LTYPE_VLAN,
+   LTYPE_SNAP_PAYLD = 0x05,
+   LTYPE_ARP = 0x06,
+   LTYPE_RARP = 0x07,
+   LTYPE_IP4 = 

[PATCH net-next v11 07/10] netdev: cavium: octeon: Add Octeon III SSO Support

[Steven J. Hill]

From: Carlos Munoz 

Add support for Octeon III SSO logic block for BGX Ethernet.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
---
 drivers/net/ethernet/cavium/octeon/octeon3-sso.c | 244 +++
 1 file changed, 244 insertions(+)
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-sso.c

diff --git a/drivers/net/ethernet/cavium/octeon/octeon3-sso.c 
b/drivers/net/ethernet/cavium/octeon/octeon3-sso.c
new file mode 100644
index 000..51d67a8
--- /dev/null
+++ b/drivers/net/ethernet/cavium/octeon/octeon3-sso.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Octeon III Schedule/Synchronize/Order Unit (SSO)
+ *
+ * Copyright (C) 2018 Cavium, Inc.
+ */
+
+#include "octeon3.h"
+
+/* Registers are accessed via xkphys. */
+#define SSO_BASE   0x16700ull
+#define SSO_ADDR(node) (SET_XKPHYS + NODE_OFFSET(node) + SSO_BASE)
+
+#define SSO_AW_STATUS(n)   (SSO_ADDR(n) + 0x10e0)
+#define SSO_AW_CFG(n)  (SSO_ADDR(n) + 0x10f0)
+#define SSO_ERR0(n)(SSO_ADDR(n) + 0x1240)
+#define SSO_TAQ_ADD(n) (SSO_ADDR(n) + 0x20e0)
+#define SSO_XAQ_AURA(n)(SSO_ADDR(n) + 0x2100)
+
+#define AQ_OFFSET(g)   ((g) << 3)
+#define AQ_ADDR(n, g)  (SSO_ADDR(n) + AQ_OFFSET(g))
+#define SSO_XAQ_HEAD_PTR(n, g) (AQ_ADDR(n, g) + 0x0008)
+#define SSO_XAQ_TAIL_PTR(n, g) (AQ_ADDR(n, g) + 0x0009)
+#define SSO_XAQ_HEAD_NEXT(n, g)(AQ_ADDR(n, g) + 0x000a)
+#define SSO_XAQ_TAIL_NEXT(n, g)(AQ_ADDR(n, g) + 0x000b)
+
+#define GRP_OFFSET(grp)((grp) << 16)
+#define GRP_ADDR(n, g) (SSO_ADDR(n)  + GRP_OFFSET(g))
+#define SSO_GRP_TAQ_THR(n, g)  (GRP_ADDR(n, g) + 0x2100)
+#define SSO_GRP_PRI(n, g)  (GRP_ADDR(n, g) + 0x2200)
+#define SSO_GRP_INT(n, g)  (GRP_ADDR(n, g) + 0x2400)
+#define SSO_GRP_INT_THR(n, g)  (GRP_ADDR(n, g) + 0x2500)
+#define SSO_GRP_AQ_CNT(n, g)   (GRP_ADDR(n, g) + 0x2700)
+
+static int octeon3_sso_get_num_groups(void)
+{
+   if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+   return 256;
+   if (OCTEON_IS_MODEL(OCTEON_CNF75XX) || OCTEON_IS_MODEL(OCTEON_CN73XX))
+   return 64;
+   return 0;
+}
+
+void octeon3_sso_irq_set(int node, int group, bool enable)
+{
+   if (enable)
+   oct_csr_write(1, SSO_GRP_INT_THR(node, group));
+   else
+   oct_csr_write(0, SSO_GRP_INT_THR(node, group));
+
+   oct_csr_write(BIT(1), SSO_GRP_INT(node, group));
+}
+EXPORT_SYMBOL(octeon3_sso_irq_set);
+
+/* octeon3_sso_alloc_groups - Allocate a range of SSO groups.
+ * @node: Node where SSO resides.
+ * @groups: Pointer to allocated groups.
+ * @cnt: Number of groups to allocate.
+ * @start: Group number to start sequential allocation from. -1 for don't care.
+ *
+ * Returns 0 if successful, error code otherwise..
+ */
+int octeon3_sso_alloc_groups(int node, int *groups, int cnt, int start)
+{
+   struct global_resource_tag tag;
+   int group, ret;
+   char buf[16];
+
+   strncpy((char *), "cvm_sso_", 8);
+   snprintf(buf, 16, "0%d..", node);
+   memcpy(, buf, 8);
+
+   res_mgr_create_resource(tag, octeon3_sso_get_num_groups());
+
+   if (!groups)
+   ret = res_mgr_alloc_range(tag, start, cnt, false, );
+   if (!ret)
+   ret = group;
+   else
+   ret = res_mgr_alloc_range(tag, start, cnt, false, groups);
+
+   return ret;
+}
+EXPORT_SYMBOL(octeon3_sso_alloc_groups);
+
+/* octeon3_sso_free_groups - Free SSO groups.
+ * @node: Node where SSO resides.
+ * @groups: Array of groups to free.
+ * @cnt: Number of groups to free.
+ */
+void octeon3_sso_free_groups(int node, int *groups, intcnt)
+{
+   struct global_resource_tag tag;
+   char buf[16];
+
+   /* Allocate the requested groups. */
+   strncpy((char *), "cvm_sso_", 8);
+   snprintf(buf, 16, "0%d..", node);
+   memcpy(, buf, 8);
+
+   res_mgr_free_range(tag, groups, cnt);
+}
+EXPORT_SYMBOL(octeon3_sso_free_groups);
+
+/* octeon3_sso_pass1_limit - When the Transitory Admission Queue (TAQ) is
+ *   almost full, it is possible for the SSo to hang. We work around this
+ *   by ensuring that the sum of SSO_GRP(0..255)_TAQ_THR[MAX_THR] of all
+ *   used groups is <= 1264. This may reduce single group performance when
+ *   many groups are in use.
+ * @node: Node to update.
+ * @grp: SSO group to update.
+ */
+void octeon3_sso_pass1_limit(int node, int group)
+{
+   u64 max_thr, rsvd_thr, taq_add, taq_thr;
+
+   /* Ideally we would like to divide the maximum number of TAQ buffers
+* (1264) among the SSO groups in use. However, since we do not know
+* how many SSO groups are used by code outside this driver, we take
+* the worst case approach.
+*/
+   max_thr = 1264 / octeon3_sso_g

[PATCH net-next v11 01/10] dt-bindings: Add Cavium Octeon Common Ethernet Interface.

[Steven J. Hill]

From: Carlos Munoz 

Add bindings for Common Ethernet Interface (BGX) block.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
---
 .../devicetree/bindings/net/cavium-bgx.txt | 59 ++
 1 file changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/cavium-bgx.txt

diff --git a/Documentation/devicetree/bindings/net/cavium-bgx.txt 
b/Documentation/devicetree/bindings/net/cavium-bgx.txt
new file mode 100644
index 000..21c9606
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/cavium-bgx.txt
@@ -0,0 +1,59 @@
+* Common Ethernet Interface (BGX) block
+
+Properties:
+
+- compatible: "cavium,octeon-7890-bgx": Compatibility with all cn7xxx SOCs.
+
+- reg: The base address of the BGX block.
+
+- #address-cells: Must be <1>.
+
+- #size-cells: Must be <0>.  BGX addresses have no size component.
+
+Typically a BGX block has several children each representing a ethernet
+interface.
+
+Example:
+
+   ethernet-mac-nexus@11800e000 {
+   compatible = "cavium,octeon-7890-bgx";
+   reg = <0x00011800 0xe000 0x 0x0100>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ethernet-mac@0 {
+   ...
+   reg = <0>;
+   };
+   };
+
+
+* Ethernet Interface (BGX port) connects to PKI/PKO
+
+Properties:
+
+- compatible: "cavium,octeon-7890-bgx-port": Compatibility with all cn7xxx
+  SOCs.
+
+- reg: The index of the interface withing the BGX block.
+
+- local-mac-address: Mac address for the interface.
+
+- phy-handle: phandle to the phy node connected to the interface.
+
+
+* Ethernet Interface (BGX port) connects to XCV
+
+
+Properties:
+
+- compatible: "cavium,octeon-7360-xcv": Compatibility with cn73xx SOCs.
+
+- reg: The index of the interface withing the BGX block.
+
+- local-mac-address: Mac address for the interface.
+
+- phy-handle: phandle to the phy node connected to the interface.
+
+- cavium,rx-clk-delay-bypass: Set to <1> to bypass the rx clock delay setting.
+  Needed by the Micrel PHY.
-- 
2.1.4

[PATCH net-next v11 04/10] netdev: cavium: octeon: Add Octeon III BGX Ports

[Steven J. Hill]

From: Carlos Munoz 

Add individual BGX nexus port support for Octeon III BGX Ethernet.

Signed-off-by: Carlos Munoz 
Signed-off-by: Steven J. Hill 
---
 .../net/ethernet/cavium/octeon/octeon3-bgx-port.c  | 2196 
 1 file changed, 2196 insertions(+)
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-port.c

diff --git a/drivers/net/ethernet/cavium/octeon/octeon3-bgx-port.c 
b/drivers/net/ethernet/cavium/octeon/octeon3-bgx-port.c
new file mode 100644
index 000..c96254f
--- /dev/null
+++ b/drivers/net/ethernet/cavium/octeon/octeon3-bgx-port.c
@@ -0,0 +1,2196 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Octeon III BGX Nexus Ethernet driver
+ *
+ * Copyright (C) 2018 Cavium, Inc.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "octeon3.h"
+
+struct bgx_port_priv {
+   int node;
+   int bgx;
+   int index; /* Port index on BGX block*/
+   enum port_mode mode;
+   int pknd;
+   int qlm;
+   const u8 *mac_addr;
+   struct phy_device *phydev;
+   struct device_node *phy_np;
+   bool mode_1000basex;
+   bool bgx_as_phy;
+   struct net_device *netdev;
+   struct mutex lock;  /* Serializes delayed work */
+   struct port_status (*get_link)(struct bgx_port_priv *priv);
+   int (*set_link)(struct bgx_port_priv *priv, struct port_status status);
+   struct port_status last_status;
+   struct delayed_work dwork;
+   bool work_queued;
+};
+
+/* lmac_pknd keeps track of the port kinds assigned to the lmacs */
+static int lmac_pknd[MAX_NODES][MAX_BGX_PER_NODE][MAX_LMAC_PER_BGX];
+
+static struct workqueue_struct *check_state_wq;
+static DEFINE_MUTEX(check_state_wq_mutex);
+
+int bgx_port_get_qlm(int node, int bgx, int index)
+{
+   int qlm = -1;
+   u64 data;
+
+   if (OCTEON_IS_MODEL(OCTEON_CN78XX)) {
+   if (bgx < 2) {
+   data = oct_csr_read(BGX_CMR_GLOBAL_CONFIG(node, bgx));
+   if (data & 1)
+   qlm = bgx + 2;
+   else
+   qlm = bgx;
+   } else {
+   qlm = bgx + 2;
+   }
+   } else if (OCTEON_IS_MODEL(OCTEON_CN73XX)) {
+   if (bgx < 2) {
+   qlm = bgx + 2;
+   } else {
+   /* Ports on bgx2 can be connected to qlm5 or qlm6 */
+   if (index < 2)
+   qlm = 5;
+   else
+   qlm = 6;
+   }
+   } else if (OCTEON_IS_MODEL(OCTEON_CNF75XX)) {
+   /* Ports on bgx0 can be connected to qlm4 or qlm5 */
+   if (index < 2)
+   qlm = 4;
+   else
+   qlm = 5;
+   }
+
+   return qlm;
+}
+EXPORT_SYMBOL(bgx_port_get_qlm);
+
+/* Returns the mode of the bgx port */
+enum port_mode bgx_port_get_mode(int node, int bgx, int index)
+{
+   enum port_mode mode;
+   u64 data;
+
+   data = oct_csr_read(BGX_CMR_CONFIG(node, bgx, index));
+
+   switch ((data >> 8) & 7) {
+   case 0:
+   mode = PORT_MODE_SGMII;
+   break;
+   case 1:
+   mode = PORT_MODE_XAUI;
+   break;
+   case 2:
+   mode = PORT_MODE_RXAUI;
+   break;
+   case 3:
+   data = oct_csr_read(BGX_SPU_BR_PMD_CONTROL(node, bgx, index));
+   /* The use of training differentiates 10G_KR from xfi */
+   if (data & BIT(1))
+   mode = PORT_MODE_10G_KR;
+   else
+   mode = PORT_MODE_XFI;
+   break;
+   case 4:
+   data = oct_csr_read(BGX_SPU_BR_PMD_CONTROL(node, bgx, index));
+   /* The use of training differentiates 40G_KR4 from xlaui */
+   if (data & BIT(1))
+   mode = PORT_MODE_40G_KR4;
+   else
+   mode = PORT_MODE_XLAUI;
+   break;
+   case 5:
+   mode = PORT_MODE_RGMII;
+   break;
+   default:
+   mode = PORT_MODE_DISABLED;
+   break;
+   }
+
+   return mode;
+}
+EXPORT_SYMBOL(bgx_port_get_mode);
+
+int bgx_port_allocate_pknd(int node)
+{
+   struct global_resource_tag tag;
+   char buf[16];
+   int pknd;
+
+   strncpy((char *), "cvm_pknd", 8);
+   snprintf(buf, 16, "_%d..", node);
+   memcpy(, buf, 8);
+
+   res_mgr_create_resource(tag, 64);
+   pknd = res_mgr_alloc(tag, -1, false);
+   if (pknd < 0) {
+   pr_err("bgx-port: Failed to allocate pknd\n");
+   return -ENODEV;
+   }
+
+   return pknd;
+}
+EXPORT_SYMBOL(bgx_port_allocate_pknd);
+
+int bgx_port_get_pknd(int node, int bgx, int index)
+{
+   return 

Re: [PATCH net-next v10 3/4] netdev: octeon-ethernet: Add Cavium Octeon III support.

[Steven J. Hill]

On 05/08/2018 09:28 PM, David Miller wrote:
> 
> That's all I have the stomache for at the moment.
> 
> This thing is really large, making it nearly impossible to review
> as one huge patch #3. Perhaps you can find a way to split it up
> logically somehow?
> 
Hey David.

This code was inherited by me, so there a lot of parts I personally
have not looked at. The third patch indeed needs to be broken up.
Let me devote some hours to cleaning, splitting and simplifying. My
apologies for the time you spent looking at it. The first patch,
however, only makes changes in the existing 'staging' directory. It
seems like that one could go in without trouble? Cheers.

Steve

[PATCH net-next v10 2/4] dt-bindings: Add Cavium Octeon Common Ethernet Interface.

[Steven J. Hill]

From: Carlos Munoz <cmu...@cavium.com>

Add bindings for Common Ethernet Interface (BGX) block.

Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Carlos Munoz <cmu...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 .../devicetree/bindings/net/cavium-bgx.txt | 61 ++
 1 file changed, 61 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/cavium-bgx.txt

diff --git a/Documentation/devicetree/bindings/net/cavium-bgx.txt 
b/Documentation/devicetree/bindings/net/cavium-bgx.txt
new file mode 100644
index 000..830c5f0
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/cavium-bgx.txt
@@ -0,0 +1,61 @@
+* Common Ethernet Interface (BGX) block
+
+Properties:
+
+- compatible: "cavium,octeon-7890-bgx": Compatibility with all cn7xxx SOCs.
+
+- reg: The base address of the BGX block.
+
+- #address-cells: Must be <1>.
+
+- #size-cells: Must be <0>.  BGX addresses have no size component.
+
+A BGX block has several children, each representing an Ethernet
+interface.
+
+
+* Ethernet Interface (BGX port) connects to PKI/PKO
+
+Properties:
+
+- compatible: "cavium,octeon-7890-bgx-port": Compatibility with all
+ cn7xxx SOCs.
+
+ "cavium,octeon-7360-xcv": Compatibility with cn73xx SOCs
+ for RGMII.
+
+- reg: The index of the interface within the BGX block.
+
+Optional properties:
+
+- local-mac-address: Mac address for the interface.
+
+- phy-handle: phandle to the phy node connected to the interface.
+
+- phy-mode: described in ethernet.txt.
+
+- fixed-link: described in fixed-link.txt.
+
+Example:
+
+   ethernet-mac-nexus@11800e000 {
+   compatible = "cavium,octeon-7890-bgx";
+   reg = <0x00011800 0xe000 0x 0x0100>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ethernet@0 {
+   compatible = "cavium,octeon-7360-xcv";
+   reg = <0>;
+   local-mac-address = [ 00 01 23 45 67 89 ];
+   phy-handle = <>;
+   phy-mode = "rgmii-rxid"
+   };
+   ethernet@1 {
+   compatible = "cavium,octeon-7890-bgx-port";
+   reg = <1>;
+   local-mac-address = [ 00 01 23 45 67 8a ];
+   phy-handle = <>;
+   phy-mode = "sgmii"
+   };
+   };
-- 
2.1.4

[PATCH net-next v10 0/4] netdev: octeon-ethernet: Add Cavium Octeon III support.

[Steven J. Hill]

Add the Cavium OCTEON III network driver. There are some corresponding
MIPS architecture support changes which will be upstreamed separately.

Changes in v10:

o Reorganization of patches to cleanly separate network and
  MIPS platform code.


Carlos Munoz (2):
  dt-bindings: Add Cavium Octeon Common Ethernet Interface.
  netdev: octeon-ethernet: Add Cavium Octeon III support.

David Daney (2):
  staging: octeon: Remove USE_ASYNC_IOBDMA macro.
  MAINTAINERS: Add entry for
drivers/net/ethernet/cavium/octeon/octeon3-*

 .../devicetree/bindings/net/cavium-bgx.txt |   61 +
 MAINTAINERS|6 +
 drivers/net/ethernet/cavium/Kconfig|   59 +-
 drivers/net/ethernet/cavium/octeon/Makefile|7 +
 .../net/ethernet/cavium/octeon/octeon3-bgx-nexus.c |  417 
 .../net/ethernet/cavium/octeon/octeon3-bgx-port.c  | 2003 +++
 drivers/net/ethernet/cavium/octeon/octeon3-core.c  | 2079 
 drivers/net/ethernet/cavium/octeon/octeon3-fpa.c   |  358 
 drivers/net/ethernet/cavium/octeon/octeon3-pki.c   |  823 
 drivers/net/ethernet/cavium/octeon/octeon3-pko.c   | 1688 
 drivers/net/ethernet/cavium/octeon/octeon3-sso.c   |  301 +++
 drivers/net/ethernet/cavium/octeon/octeon3.h   |  430 
 drivers/staging/octeon/ethernet-defines.h  |6 -
 drivers/staging/octeon/ethernet-rx.c   |   25 +-
 drivers/staging/octeon/ethernet-tx.c   |   85 +-
 15 files changed, 8259 insertions(+), 89 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/cavium-bgx.txt
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-nexus.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-port.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-core.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-fpa.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pki.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pko.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-sso.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3.h

-- 
2.1.4

[PATCH net-next v10 4/4] MAINTAINERS: Add entry for drivers/net/ethernet/cavium/octeon/octeon3-*

[Steven J. Hill]

From: David Daney <david.da...@cavium.com>

Signed-off-by: David Daney <david.da...@cavium.com>
---
 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index ebe0b9e..f066bda 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3252,6 +3252,12 @@ W:   http://www.cavium.com
 S: Supported
 F: drivers/mmc/host/cavium*
 
+CAVIUM OCTEON-III NETWORK DRIVER
+M:     Steven J. Hill <steven.h...@cavium.com>
+L: netdev@vger.kernel.org
+S: Supported
+F: drivers/net/ethernet/cavium/octeon/octeon3-*
+
 CAVIUM OCTEON-TX CRYPTO DRIVER
 M: George Cherian <george.cher...@cavium.com>
 L: linux-cry...@vger.kernel.org
-- 
2.1.4

[PATCH net-next v10 1/4] staging: octeon: Remove USE_ASYNC_IOBDMA macro.

[Steven J. Hill]

From: David Daney 

Previous patch sets USE_ASYNC_IOBDMA to 1 unconditionally. Remove
USE_ASYNC_IOBDMA from all if statements.  Remove dead code caused
by the change.

Acked-by: Greg Kroah-Hartman 
Signed-off-by: David Daney 
---
 drivers/staging/octeon/ethernet-defines.h |  6 ---
 drivers/staging/octeon/ethernet-rx.c  | 25 -
 drivers/staging/octeon/ethernet-tx.c  | 85 ++-
 3 files changed, 37 insertions(+), 79 deletions(-)

diff --git a/drivers/staging/octeon/ethernet-defines.h 
b/drivers/staging/octeon/ethernet-defines.h
index 1e11442..15db928 100644
--- a/drivers/staging/octeon/ethernet-defines.h
+++ b/drivers/staging/octeon/ethernet-defines.h
@@ -7,10 +7,6 @@
 
 /*
  * A few defines are used to control the operation of this driver:
- *  USE_ASYNC_IOBDMA
- *  Use asynchronous IO access to hardware. This uses Octeon's asynchronous
- *  IOBDMAs to issue IO accesses without stalling. Set this to zero
- *  to disable this. Note that IOBDMAs require CVMSEG.
  *  REUSE_SKBUFFS_WITHOUT_FREE
  *  Allows the TX path to free an skbuff into the FPA hardware pool. This
  *  can significantly improve performance for forwarding and bridging, but
@@ -29,8 +25,6 @@
 #define REUSE_SKBUFFS_WITHOUT_FREE  1
 #endif
 
-#define USE_ASYNC_IOBDMA(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0)
-
 /* Maximum number of SKBs to try to free per xmit packet. */
 #define MAX_OUT_QUEUE_DEPTH 1000
 
diff --git a/drivers/staging/octeon/ethernet-rx.c 
b/drivers/staging/octeon/ethernet-rx.c
index 5e27124..c1ae60c 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -198,11 +198,9 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
/* Prefetch cvm_oct_device since we know we need it soon */
prefetch(cvm_oct_device);
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Save scratch in case userspace is using it */
-   CVMX_SYNCIOBDMA;
-   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
-   }
+   /* Save scratch in case userspace is using it */
+   CVMX_SYNCIOBDMA;
+   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
 
/* Only allow work for our group (and preserve priorities) */
if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
@@ -217,10 +215,8 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
   BIT(rx_group->group));
}
 
-   if (USE_ASYNC_IOBDMA) {
-   cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
-   did_work_request = 1;
-   }
+   cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
+   did_work_request = 1;
 
while (rx_count < budget) {
struct sk_buff *skb = NULL;
@@ -229,7 +225,7 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
cvmx_wqe_t *work;
int port;
 
-   if (USE_ASYNC_IOBDMA && did_work_request)
+   if (did_work_request)
work = cvmx_pow_work_response_async(CVMX_SCR_SCRATCH);
else
work = cvmx_pow_work_request_sync(CVMX_POW_NO_WAIT);
@@ -257,7 +253,7 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
sizeof(void *));
prefetch(pskb);
 
-   if (USE_ASYNC_IOBDMA && rx_count < (budget - 1)) {
+   if (rx_count < (budget - 1)) {
cvmx_pow_work_request_async_nocheck(CVMX_SCR_SCRATCH,
CVMX_POW_NO_WAIT);
did_work_request = 1;
@@ -400,10 +396,9 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), old_group_mask);
}
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Restore the scratch area */
-   cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
-   }
+   /* Restore the scratch area */
+   cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
+
cvm_oct_rx_refill_pool(0);
 
return rx_count;
diff --git a/drivers/staging/octeon/ethernet-tx.c 
b/drivers/staging/octeon/ethernet-tx.c
index df3441b..2aa5fcb 100644
--- a/drivers/staging/octeon/ethernet-tx.c
+++ b/drivers/staging/octeon/ethernet-tx.c
@@ -176,23 +176,18 @@ int cvm_oct_xmit(struct sk_buff *skb, struct net_device 
*dev)
qos = 0;
}
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Save scratch in case userspace is using it */
-   CVMX_SYNCIOBDMA;
-   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
-   old_scratch2 = cvmx_scratch_read64(CVMX_SCR_SCRATCH + 8);
-
-   /*
-* Fetch and increment the number of packets to be

Re: [PATCH net-next v9 0/4] Prerequisites for Cavium OCTEON-III network driver.

[Steven J. Hill]

On 04/29/2018 07:33 PM, David Miller wrote:
> 
> I don't know if we really want all of these MIPS specific changes to
> go via the net-next tree.
> 
> The right way to do this is probably getting this series into the MIPS
> architecture tree.
> 
David,

Correct, and I should have been clearer about that. The MIPS-specific
changes are targeted for 4.18 and I will be working with James/Ralf
to get those in. The actual changes for adding the driver, however,
should be fine to go into net-next. The netdev list should have been
a CC: for those patches and the Linux/MIPS mailing list as the main
recipient. Mea culpa.

Steve

[PATCH net-next v9 3/3] MAINTAINERS: Add entry for drivers/net/ethernet/cavium/octeon/octeon3-*

[Steven J. Hill]

From: David Daney <david.da...@cavium.com>

Signed-off-by: David Daney <david.da...@cavium.com>
---
 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index a528008..57135f4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3250,6 +3250,12 @@ W:   http://www.cavium.com
 S: Supported
 F: drivers/mmc/host/cavium*
 
+CAVIUM OCTEON-III NETWORK DRIVER
+M:     Steven J. Hill <steven.h...@cavium.com>
+L: netdev@vger.kernel.org
+S: Supported
+F: drivers/net/ethernet/cavium/octeon/octeon3-*
+
 CAVIUM OCTEON-TX CRYPTO DRIVER
 M: George Cherian <george.cher...@cavium.com>
 L: linux-cry...@vger.kernel.org
-- 
2.1.4

[PATCH net-next v9 4/4] MIPS: Octeon: Add a global resource manager.

[Steven J. Hill]

From: Carlos Munoz <cmu...@cavium.com>

Add a global resource manager to manage tagged pointers within
bootmem allocated memory. This is used by various functional
blocks in the Octeon core like the FPA, Ethernet nexus, etc.

Acked-by: James Hogan <jho...@kernel.org>
Signed-off-by: Carlos Munoz <cmu...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 arch/mips/cavium-octeon/Makefile   |   1 +
 arch/mips/cavium-octeon/resource-mgr.c | 351 +
 arch/mips/include/asm/octeon/octeon.h  |  18 ++
 3 files changed, 370 insertions(+)
 create mode 100644 arch/mips/cavium-octeon/resource-mgr.c

diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 7c02e54..28c0bb7 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -10,6 +10,7 @@
 #
 
 obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o
+obj-y += resource-mgr.o
 obj-y += dma-octeon.o
 obj-y += octeon-memcpy.o
 obj-y += executive/
diff --git a/arch/mips/cavium-octeon/resource-mgr.c 
b/arch/mips/cavium-octeon/resource-mgr.c
new file mode 100644
index 000..74efda5
--- /dev/null
+++ b/arch/mips/cavium-octeon/resource-mgr.c
@@ -0,0 +1,351 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Resource manager for Octeon.
+ *
+ * Copyright (C) 2017 Cavium, Inc.
+ */
+#include 
+
+#include 
+#include 
+
+#define RESOURCE_MGR_BLOCK_NAME"cvmx-global-resources"
+#define MAX_RESOURCES  128
+#define INST_AVAILABLE -88
+#define OWNER  0xbadc0de
+
+struct global_resource_entry {
+   struct global_resource_tag tag;
+   u64 phys_addr;
+   u64 size;
+};
+
+struct global_resources {
+#ifdef __LITTLE_ENDIAN_BITFIELD
+   u32 rlock;
+   u32 pad;
+#else
+   u32 pad;
+   u32 rlock;
+#endif
+   u64 entry_cnt;
+   struct global_resource_entry resource_entry[];
+};
+
+static struct global_resources *res_mgr_info;
+
+
+/*
+ * The resource manager interacts with software running outside of the
+ * Linux kernel, which necessitates locking to maintain data structure
+ * consistency.  These custom locking functions implement the locking
+ * protocol, and cannot be replaced by kernel locking functions that
+ * may use different in-memory structures.
+ */
+
+static void res_mgr_lock(void)
+{
+   while (cmpxchg(_mgr_info->rlock, 0, 1))
+   ; /* Loop while not zero */
+   rmb();
+}
+
+static void res_mgr_unlock(void)
+{
+   /* Wait until all resource operations finish before unlocking. */
+   wmb();
+   WRITE_ONCE(res_mgr_info->rlock, 0);
+   /* Force a write buffer flush. */
+   wmb();
+}
+
+static int res_mgr_find_resource(struct global_resource_tag tag)
+{
+   struct global_resource_entry *res_entry;
+   int i;
+
+   for (i = 0; i < res_mgr_info->entry_cnt; i++) {
+   res_entry = _mgr_info->resource_entry[i];
+   if (res_entry->tag.lo == tag.lo && res_entry->tag.hi == tag.hi)
+   return i;
+   }
+   return -1;
+}
+
+/**
+ * res_mgr_create_resource() - Create a resource.
+ * @tag: Identifies the resource.
+ * @inst_cnt: Number of resource instances to create.
+ *
+ * Returns 0 if the source was created successfully.
+ * Returns < 0 for error codes.
+ */
+int res_mgr_create_resource(struct global_resource_tag tag, int inst_cnt)
+{
+   struct global_resource_entry *res_entry;
+   u64 size;
+   u64 *res_addr;
+   int res_index, i, rc = 0;
+
+   res_mgr_lock();
+
+   /* Make sure resource doesn't already exist. */
+   res_index = res_mgr_find_resource(tag);
+   if (res_index >= 0) {
+   rc = -EEXIST;
+   goto err;
+   }
+
+   if (res_mgr_info->entry_cnt >= MAX_RESOURCES) {
+   pr_err("Resource max limit reached, not created\n");
+   rc = -ENOSPC;
+   goto err;
+   }
+
+   /*
+* Each instance is kept in an array of u64s. The first array element
+* holds the number of allocated instances.
+*/
+   size = sizeof(u64) * (inst_cnt + 1);
+   res_addr = cvmx_bootmem_alloc_range(size, CVMX_CACHE_LINE_SIZE, 0, 0);
+   if (!res_addr) {
+   pr_err("Failed to allocate resource. not created\n");
+   rc = -ENOMEM;
+   goto err;
+   }
+
+   /* Initialize the newly created resource. */
+   *res_addr = inst_cnt;
+   for (i = 1; i <= inst_cnt; i++)
+   res_addr[i] = INST_AVAILABLE;
+
+   res_index = res_mgr_info->entry_cnt;
+   res_entry = _mgr_info->resource_entry[res_index];
+   res_entry->tag = tag;
+   res_entry->phys_addr = virt_to_phys(res_addr);
+   res_entry->s

[PATCH net-next v9 2/4] MIPS: Octeon: Automatically provision CVMSEG space.

[Steven J. Hill]

From: David Daney 

Remove CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE and automatically calculate
the amount of CVMSEG space needed.

1st 128-bytes: Use by IOBDMA
2nd 128-bytes: Reserved by kernel for scratch/TLS emulation.
3rd 128-bytes: OCTEON-III LMTLINE

New config variable CONFIG_CAVIUM_OCTEON_EXTRA_CVMSEG provisions
additional lines, defaults to zero.

Signed-off-by: David Daney 
Signed-off-by: Carlos Munoz 
---
 arch/mips/cavium-octeon/Kconfig| 27 +++
 arch/mips/cavium-octeon/setup.c| 16 ++-
 .../asm/mach-cavium-octeon/kernel-entry-init.h | 15 ---
 arch/mips/include/asm/octeon/octeon.h  |  2 ++
 arch/mips/include/asm/processor.h  |  2 +-
 arch/mips/kernel/octeon_switch.S   |  2 --
 arch/mips/mm/tlbex.c   | 31 +++---
 drivers/staging/octeon/ethernet-defines.h  |  2 +-
 8 files changed, 50 insertions(+), 47 deletions(-)

diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index b5eee1a..a283b73 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -11,21 +11,26 @@ config CAVIUM_CN63XXP1
  non-CN63XXP1 hardware, so it is recommended to select "n"
  unless it is known the workarounds are needed.
 
-config CAVIUM_OCTEON_CVMSEG_SIZE
-   int "Number of L1 cache lines reserved for CVMSEG memory"
-   range 0 54
-   default 1
-   help
- CVMSEG LM is a segment that accesses portions of the dcache as a
- local memory; the larger CVMSEG is, the smaller the cache is.
- This selects the size of CVMSEG LM, which is in cache blocks. The
- legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
- between zero and 6192 bytes).
-
 endif # CPU_CAVIUM_OCTEON
 
 if CAVIUM_OCTEON_SOC
 
+config CAVIUM_OCTEON_EXTRA_CVMSEG
+   int "Number of extra L1 cache lines reserved for CVMSEG memory"
+   range 0 50
+   default 0
+   help
+ CVMSEG LM is a segment that accesses portions of the dcache
+ as a local memory; the larger CVMSEG is, the smaller the
+ cache is.  The kernel uses two or three blocks (one for TLB
+ exception handlers, one for driver IOBDMA operations, and on
+ models that need it, one for LMTDMA operations). This
+ selects an optional extra number of CVMSEG lines for use by
+ other software.
+
+ Normally no extra lines are required, and this parameter
+ should be set to zero.
+
 config CAVIUM_OCTEON_LOCK_L2
bool "Lock often used kernel code in the L2"
default "y"
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 99e6a68..51c4d3c 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -68,6 +68,12 @@ extern void pci_console_init(const char *arg);
 static unsigned long long max_memory = ULLONG_MAX;
 static unsigned long long reserve_low_mem;
 
+/*
+ * modified in hernel-entry-init.h, must have an initial value to keep
+ * it from being clobbered when bss is zeroed.
+ */
+u32 octeon_cvmseg_lines = 2;
+
 DEFINE_SEMAPHORE(octeon_bootbus_sem);
 EXPORT_SYMBOL(octeon_bootbus_sem);
 
@@ -604,11 +610,7 @@ void octeon_user_io_init(void)
 
/* R/W If set, CVMSEG is available for loads/stores in
 * kernel/debug mode. */
-#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
cvmmemctl.s.cvmsegenak = 1;
-#else
-   cvmmemctl.s.cvmsegenak = 0;
-#endif
if (OCTEON_IS_OCTEON3()) {
/* Enable LMTDMA */
cvmmemctl.s.lmtena = 1;
@@ -626,9 +628,9 @@ void octeon_user_io_init(void)
 
/* Setup of CVMSEG is done in kernel-entry-init.h */
if (smp_processor_id() == 0)
-   pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
+   pr_notice("CVMSEG size: %u cache lines (%u bytes)\n",
+ octeon_cvmseg_lines,
+ octeon_cvmseg_lines * 128);
 
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
union cvmx_iob_fau_timeout fau_timeout;
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h 
b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index c38b38c..8322c9d 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -26,11 +26,18 @@
# a3 = address of boot descriptor block
.set push
.set arch=octeon
+   mfc0v1, CP0_PRID_REG
+   andiv1, 0xff00
+   li  v0, 0x9500  # cn78XX or later
+   subuv1, v1, v0
+   li  t2, 2 + CONFIG_CAVIUM_OCTEON_EXTRA_CVMSEG

[PATCH net-next v9 0/4] Prerequisites for Cavium OCTEON-III network driver.

[Steven J. Hill]

We want to add the Cavium OCTEON-III network driver.  But since
interacting with the input and output queues is done via special CPU
local memory, we also need to add support to the MIPS/Octeon
architecture code.  Aren't SoCs nice in this way?  These are the
prerequisite patches that are needed before the network driver can be
merged.

Changes in v9:

o Rebased to 'net-next'
o Revert code removal in kernel-entry-init.h
o Move CAVIUM_OCTEON_SCRATCH_OFFSET into tlbex.c

Changes in v8:

o Rebased to v4.16-rc2

Changes in v7:

o Splitting of the patch set only.  These 4 mips patches are unchanged
  from the previous posting.

Changes in v6:

o Added back cleanup patch for previous generation SoC "staging"
  driver, as Greg K-H acked it.

o Moved FPA driver to drivers/net/ethernet/cavium/octeon as it is
  currently only used by the octeon3-ethernet driver.

o Many code formatting fixes as noted by davem.

Changes in v5:

o Removed cleanup patch for previous generation SoC "staging" driver,
  as it will be sent as a follow-on.

o Fixed kernel doc formatting in all patches.

o Removed redundant licensing text boilerplate.

o Reviewed-by: header added to 2/7.

o Rewrote locking code in 3/7 to eliminate inline asm.

Changes in v4:

o Use phy_print_status() instead of open coding the equivalent.

o Print warning on phy mode mismatch.

o Improve dt-bindings and add Acked-by.

Changes in v3:

o Fix PKI (RX path) initialization to work with little endian kernel.

Changes in v2:

o Cleanup and use of standard bindings in the device tree bindings
  document.

o Added (hopefully) clarifying comments about several OCTEON
  architectural peculiarities.

o Removed unused testing code from the driver.

o Removed some module parameters that already default to the proper
  values.

o KConfig cleanup, including testing on x86_64, arm64 and mips.

o Fixed breakage to the driver for previous generation of OCTEON SoCs
  (in the staging directory still).

o Verified bisectability of the patch set.

Carlos Munoz (2):
  MIPS: Octeon: Enable LMTDMA/LMTST operations.
  MIPS: Octeon: Add a global resource manager.

David Daney (2):
  MIPS: Octeon: Automatically provision CVMSEG space.
  staging: octeon: Remove USE_ASYNC_IOBDMA macro.

 arch/mips/cavium-octeon/Kconfig|  27 +-
 arch/mips/cavium-octeon/Makefile   |   1 +
 arch/mips/cavium-octeon/resource-mgr.c | 351 +
 arch/mips/cavium-octeon/setup.c|  22 +-
 .../asm/mach-cavium-octeon/kernel-entry-init.h |  15 +-
 arch/mips/include/asm/octeon/octeon.h  |  32 +-
 arch/mips/include/asm/processor.h  |   2 +-
 arch/mips/kernel/octeon_switch.S   |   2 -
 arch/mips/mm/tlbex.c   |  31 +-
 drivers/staging/octeon/ethernet-defines.h  |   6 -
 drivers/staging/octeon/ethernet-rx.c   |  25 +-
 drivers/staging/octeon/ethernet-tx.c   |  85 ++---
 12 files changed, 472 insertions(+), 127 deletions(-)
 create mode 100644 arch/mips/cavium-octeon/resource-mgr.c

-- 
2.1.4

[PATCH net-next v9 1/3] dt-bindings: Add Cavium Octeon Common Ethernet Interface.

[Steven J. Hill]

From: Carlos Munoz <cmu...@cavium.com>

Add bindings for Common Ethernet Interface (BGX) block.

Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Carlos Munoz <cmu...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 .../devicetree/bindings/net/cavium-bgx.txt | 61 ++
 1 file changed, 61 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/cavium-bgx.txt

diff --git a/Documentation/devicetree/bindings/net/cavium-bgx.txt 
b/Documentation/devicetree/bindings/net/cavium-bgx.txt
new file mode 100644
index 000..830c5f0
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/cavium-bgx.txt
@@ -0,0 +1,61 @@
+* Common Ethernet Interface (BGX) block
+
+Properties:
+
+- compatible: "cavium,octeon-7890-bgx": Compatibility with all cn7xxx SOCs.
+
+- reg: The base address of the BGX block.
+
+- #address-cells: Must be <1>.
+
+- #size-cells: Must be <0>.  BGX addresses have no size component.
+
+A BGX block has several children, each representing an Ethernet
+interface.
+
+
+* Ethernet Interface (BGX port) connects to PKI/PKO
+
+Properties:
+
+- compatible: "cavium,octeon-7890-bgx-port": Compatibility with all
+ cn7xxx SOCs.
+
+ "cavium,octeon-7360-xcv": Compatibility with cn73xx SOCs
+ for RGMII.
+
+- reg: The index of the interface within the BGX block.
+
+Optional properties:
+
+- local-mac-address: Mac address for the interface.
+
+- phy-handle: phandle to the phy node connected to the interface.
+
+- phy-mode: described in ethernet.txt.
+
+- fixed-link: described in fixed-link.txt.
+
+Example:
+
+   ethernet-mac-nexus@11800e000 {
+   compatible = "cavium,octeon-7890-bgx";
+   reg = <0x00011800 0xe000 0x 0x0100>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ethernet@0 {
+   compatible = "cavium,octeon-7360-xcv";
+   reg = <0>;
+   local-mac-address = [ 00 01 23 45 67 89 ];
+   phy-handle = <>;
+   phy-mode = "rgmii-rxid"
+   };
+   ethernet@1 {
+   compatible = "cavium,octeon-7890-bgx-port";
+   reg = <1>;
+   local-mac-address = [ 00 01 23 45 67 8a ];
+   phy-handle = <>;
+   phy-mode = "sgmii"
+   };
+   };
-- 
2.1.4

[PATCH net-next v9 0/3] netdev: octeon-ethernet: Add Cavium Octeon III support.

[Steven J. Hill]

We are adding the Cavium OCTEON-III network driver.  Since interacting
with the input and output queues is done via special CPU local memory,
we also need to add support to the MIPS/Octeon architecture code.  The
four patch set to add this prerequisite code has been split out to a
seperate patch set sent to the mips-linux list.

A separate pull request was recently done by Steven Hill for the
firmware required by the driver.

Changes in v9:

o Rebased against 'net-next'

Changes in v8:

o Fixed locking in bgx port functions as noted by davem.

o Corrected SPDX-License-Identifier tags.

o Split driver from prerequisite patches.

Changes in v7:

o There was no v7, we go to v8 to synchronize version numbers with
prerequisites.

Changes in v6:

o Added back cleanup patch for previous generation SoC "staging"
  driver, as Greg K-H acked it.

o Moved FPA driver to drivers/net/ethernet/cavium/octeon as it is
  currently only used by the octeon3-ethernet driver.

o Many code formatting fixes as noted by davem.

Changes in v5:

o Removed cleanup patch for previous generation SoC "staging" driver,
  as it will be sent as a follow-on.

o Fixed kernel doc formatting in all patches.

o Removed redundant licensing text boilerplate.

o Reviewed-by: header added to 2/7.

o Rewrote locking code in 3/7 to eliminate inline asm.

Changes in v4:

o Use phy_print_status() instead of open coding the equivalent.

o Print warning on phy mode mismatch.

o Improve dt-bindings and add Acked-by.

Changes in v3:

o Fix PKI (RX path) initialization to work with little endian kernel.

Changes in v2:

o Cleanup and use of standard bindings in the device tree bindings
  document.

o Added (hopefully) clarifying comments about several OCTEON
  architectural peculiarities.

o Removed unused testing code from the driver.

o Removed some module parameters that already default to the proper
  values.

o KConfig cleanup, including testing on x86_64, arm64 and mips.

o Fixed breakage to the driver for previous generation of OCTEON SoCs (in
  the staging directory still).

o Verified bisectability of the patch set.

Carlos Munoz (2):
  dt-bindings: Add Cavium Octeon Common Ethernet Interface.
  netdev: octeon-ethernet: Add Cavium Octeon III support.

David Daney (1):
  MAINTAINERS: Add entry for
drivers/net/ethernet/cavium/octeon/octeon3-*

 .../devicetree/bindings/net/cavium-bgx.txt |   61 +
 MAINTAINERS|6 +
 drivers/net/ethernet/cavium/Kconfig|   59 +-
 drivers/net/ethernet/cavium/octeon/Makefile|7 +
 .../net/ethernet/cavium/octeon/octeon3-bgx-nexus.c |  417 
 .../net/ethernet/cavium/octeon/octeon3-bgx-port.c  | 2003 +++
 drivers/net/ethernet/cavium/octeon/octeon3-core.c  | 2079 
 drivers/net/ethernet/cavium/octeon/octeon3-fpa.c   |  358 
 drivers/net/ethernet/cavium/octeon/octeon3-pki.c   |  823 
 drivers/net/ethernet/cavium/octeon/octeon3-pko.c   | 1688 
 drivers/net/ethernet/cavium/octeon/octeon3-sso.c   |  301 +++
 drivers/net/ethernet/cavium/octeon/octeon3.h   |  430 
 12 files changed, 8222 insertions(+), 10 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/cavium-bgx.txt
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-nexus.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-port.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-core.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-fpa.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pki.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pko.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-sso.c
 create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3.h

-- 
2.1.4

[PATCH net-next v9 3/4] staging: octeon: Remove USE_ASYNC_IOBDMA macro.

[Steven J. Hill]

From: David Daney 

Previous patch sets USE_ASYNC_IOBDMA to 1 unconditionally.  Remove
USE_ASYNC_IOBDMA from all if statements.  Remove dead code caused by
the change.

Acked-by: Greg Kroah-Hartman 
Signed-off-by: David Daney 
---
 drivers/staging/octeon/ethernet-defines.h |  6 ---
 drivers/staging/octeon/ethernet-rx.c  | 25 -
 drivers/staging/octeon/ethernet-tx.c  | 85 ++-
 3 files changed, 37 insertions(+), 79 deletions(-)

diff --git a/drivers/staging/octeon/ethernet-defines.h 
b/drivers/staging/octeon/ethernet-defines.h
index 33c71f8..15db928 100644
--- a/drivers/staging/octeon/ethernet-defines.h
+++ b/drivers/staging/octeon/ethernet-defines.h
@@ -7,10 +7,6 @@
 
 /*
  * A few defines are used to control the operation of this driver:
- *  USE_ASYNC_IOBDMA
- *  Use asynchronous IO access to hardware. This uses Octeon's asynchronous
- *  IOBDMAs to issue IO accesses without stalling. Set this to zero
- *  to disable this. Note that IOBDMAs require CVMSEG.
  *  REUSE_SKBUFFS_WITHOUT_FREE
  *  Allows the TX path to free an skbuff into the FPA hardware pool. This
  *  can significantly improve performance for forwarding and bridging, but
@@ -29,8 +25,6 @@
 #define REUSE_SKBUFFS_WITHOUT_FREE  1
 #endif
 
-#define USE_ASYNC_IOBDMA   1
-
 /* Maximum number of SKBs to try to free per xmit packet. */
 #define MAX_OUT_QUEUE_DEPTH 1000
 
diff --git a/drivers/staging/octeon/ethernet-rx.c 
b/drivers/staging/octeon/ethernet-rx.c
index 5e27124..c1ae60c 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -198,11 +198,9 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
/* Prefetch cvm_oct_device since we know we need it soon */
prefetch(cvm_oct_device);
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Save scratch in case userspace is using it */
-   CVMX_SYNCIOBDMA;
-   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
-   }
+   /* Save scratch in case userspace is using it */
+   CVMX_SYNCIOBDMA;
+   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
 
/* Only allow work for our group (and preserve priorities) */
if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
@@ -217,10 +215,8 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
   BIT(rx_group->group));
}
 
-   if (USE_ASYNC_IOBDMA) {
-   cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
-   did_work_request = 1;
-   }
+   cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
+   did_work_request = 1;
 
while (rx_count < budget) {
struct sk_buff *skb = NULL;
@@ -229,7 +225,7 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
cvmx_wqe_t *work;
int port;
 
-   if (USE_ASYNC_IOBDMA && did_work_request)
+   if (did_work_request)
work = cvmx_pow_work_response_async(CVMX_SCR_SCRATCH);
else
work = cvmx_pow_work_request_sync(CVMX_POW_NO_WAIT);
@@ -257,7 +253,7 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
sizeof(void *));
prefetch(pskb);
 
-   if (USE_ASYNC_IOBDMA && rx_count < (budget - 1)) {
+   if (rx_count < (budget - 1)) {
cvmx_pow_work_request_async_nocheck(CVMX_SCR_SCRATCH,
CVMX_POW_NO_WAIT);
did_work_request = 1;
@@ -400,10 +396,9 @@ static int cvm_oct_poll(struct oct_rx_group *rx_group, int 
budget)
cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), old_group_mask);
}
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Restore the scratch area */
-   cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
-   }
+   /* Restore the scratch area */
+   cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
+
cvm_oct_rx_refill_pool(0);
 
return rx_count;
diff --git a/drivers/staging/octeon/ethernet-tx.c 
b/drivers/staging/octeon/ethernet-tx.c
index df3441b..2aa5fcb 100644
--- a/drivers/staging/octeon/ethernet-tx.c
+++ b/drivers/staging/octeon/ethernet-tx.c
@@ -176,23 +176,18 @@ int cvm_oct_xmit(struct sk_buff *skb, struct net_device 
*dev)
qos = 0;
}
 
-   if (USE_ASYNC_IOBDMA) {
-   /* Save scratch in case userspace is using it */
-   CVMX_SYNCIOBDMA;
-   old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
-   old_scratch2 = cvmx_scratch_read64(CVMX_SCR_SCRATCH + 8);
-
-   /*
-* Fetch and increment the number of packets to be
-* freed.
-  

[PATCH net-next v9 1/4] MIPS: Octeon: Enable LMTDMA/LMTST operations.

[Steven J. Hill]

From: Carlos Munoz <cmu...@cavium.com>

LMTDMA/LMTST operations move data between cores and I/O devices:

* LMTST operations can send an address and a variable length
  (up to 128 bytes) of data to an I/O device.
* LMTDMA operations can send an address and a variable length
  (up to 128) of data to the I/O device and then return a
  variable length (up to 128 bytes) response from the I/O device.

For both LMTST and LMTDMA, the data sent to the device is first stored
in the CVMSEG core local memory cache line indexed by
CVMMEMCTL[LMTLINE], the data is then atomically transmitted to the
device with a store to the CVMSEG LMTDMA trigger location.

Reviewed-by: James Hogan <jho...@kernel.org>
Signed-off-by: Carlos Munoz <cmu...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 arch/mips/cavium-octeon/setup.c   |  6 ++
 arch/mips/include/asm/octeon/octeon.h | 12 ++--
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index a8034d0..99e6a68 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -609,6 +609,12 @@ void octeon_user_io_init(void)
 #else
cvmmemctl.s.cvmsegenak = 0;
 #endif
+   if (OCTEON_IS_OCTEON3()) {
+   /* Enable LMTDMA */
+   cvmmemctl.s.lmtena = 1;
+   /* Scratch line to use for LMT operation */
+   cvmmemctl.s.lmtline = 2;
+   }
/* R/W If set, CVMSEG is available for loads/stores in
 * supervisor mode. */
cvmmemctl.s.cvmsegenas = 0;
diff --git a/arch/mips/include/asm/octeon/octeon.h 
b/arch/mips/include/asm/octeon/octeon.h
index c99c4b6..92a17d6 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -179,7 +179,15 @@ union octeon_cvmemctl {
/* RO 1 = BIST fail, 0 = BIST pass */
__BITFIELD_FIELD(uint64_t wbfbist:1,
/* Reserved */
-   __BITFIELD_FIELD(uint64_t reserved:17,
+   __BITFIELD_FIELD(uint64_t reserved_52_57:6,
+   /* When set, LMTDMA/LMTST operations are permitted */
+   __BITFIELD_FIELD(uint64_t lmtena:1,
+   /* Selects the CVMSEG LM cacheline used by LMTDMA
+* LMTST and wide atomic store operations.
+*/
+   __BITFIELD_FIELD(uint64_t lmtline:6,
+   /* Reserved */
+   __BITFIELD_FIELD(uint64_t reserved_41_44:4,
/* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU.
 * This field selects between the TLB replacement policies:
 * bitmask LRU or NLU. Bitmask LRU maintains a mask of
@@ -275,7 +283,7 @@ union octeon_cvmemctl {
/* R/W Size of local memory in cache blocks, 54 (6912
 * bytes) is max legal value. */
__BITFIELD_FIELD(uint64_t lmemsz:6,
-   ;)
+   ;
} s;
 };
 
-- 
2.1.4

Re: Cavium Octeon III network driver.

[Steven J. Hill]

On 04/14/2018 07:08 PM, Florian Fainelli wrote:
> 
> net-next tree is currently closed, but once it opens back up, you would
> likely want to resubmit those patches. Last I remember they were ready
> to go.
> 
The announcement appears on this list for when it is open, correct?

Cavium Octeon III network driver.

[Steven J. Hill]

Patches for Cavium's Octeon III network driver were submitted by
David Daney back on 20180222. David has since left the company and
I am now responsible for the upstreaming effort. When looking at
 they are marked as "Not Applicable". What
steps do I take next? Thanks.

Steve

Re: pull request: Cavium Octeon III firmware

[Steven J. Hill]

On 11/28/2017 11:30 AM, Ben Hutchings wrote:
> 
> The diffstat in your original pull request said that WHENCE wasn't
> updated.  Maybe you corrected that after sending the pull request.
> 
Ben,

The updated patch is ready for you to pull. Cheers.

Steve


git://git.linux-mips.org/pub/scm/sjhill/linux-firmware.git

Re: pull request: Cavium Octeon III firmware

[Steven J. Hill]

On 11/22/2017 07:40 PM, Ben Hutchings wrote:
> On Tue, 2017-10-31 at 17:05 -0500, Steven J. Hill wrote:
>> Hello.
>>
>> Would like to add firmware for our Octeon III PKI driver. Thanks.
> 
> Where is this driver?  I don't see any reference to the file in linux-
> next.
> 
> [...]
>>  cavium/pki-cluster.bin | Bin 0 -> 7488 bytes
>>  1 file changed, 0 insertions(+), 0 deletions(-)
>>  create mode 100644 cavium/pki-cluster.bin
> 
> When adding a file you also need to update WHENCE to include its
> copyright details.
> 
The WHENCE file was updated in the patch. I will assume you would like
to see two separate patches. One for the binary and one for the WHENCE.
I have done so and updated the git repo for you to pull from.


git://git.linux-mips.org/pub/scm/sjhill/linux-firmware.git

[PATCH] staging: octeon: Fix stopping of the interface.

[Steven J. Hill]

Before disconnecting the PHY when a port is being taken down,
a call to phy_stop() is necessary.

Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Acked-by: David Daney <david.da...@cavium.com>
---
 drivers/staging/octeon/ethernet-mdio.c | 4 +++-
 drivers/staging/octeon/ethernet.c  | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/octeon/ethernet-mdio.c 
b/drivers/staging/octeon/ethernet-mdio.c
index 691e4a5..b9d67c9 100644
--- a/drivers/staging/octeon/ethernet-mdio.c
+++ b/drivers/staging/octeon/ethernet-mdio.c
@@ -124,8 +124,10 @@ int cvm_oct_common_stop(struct net_device *dev)
 
priv->poll = NULL;
 
-   if (dev->phydev)
+   if (dev->phydev) {
+   phy_stop(dev->phydev);
phy_disconnect(dev->phydev);
+   }
 
if (priv->last_link) {
link_info.u64 = 0;
diff --git a/drivers/staging/octeon/ethernet.c 
b/drivers/staging/octeon/ethernet.c
index 429e24a..53d961d 100644
--- a/drivers/staging/octeon/ethernet.c
+++ b/drivers/staging/octeon/ethernet.c
@@ -463,8 +463,10 @@ int cvm_oct_common_init(struct net_device *dev)
 
 void cvm_oct_common_uninit(struct net_device *dev)
 {
-   if (dev->phydev)
+   if (dev->phydev) {
+   phy_stop(dev->phydev);
phy_disconnect(dev->phydev);
+   }
 }
 
 int cvm_oct_common_open(struct net_device *dev,
-- 
2.1.4

pull request: Cavium Octeon III firmware

[Steven J. Hill]

Hello.

Would like to add firmware for our Octeon III PKI driver. Thanks.

Steve


The following changes since commit bf04291309d3169c0ad3b8db52564235bbd08e30:

  WHENCE: Add new qed firmware (2017-10-09 18:03:26 +0100)

are available in the git repository at:

  git://git.linux-mips.org/pub/scm/sjhill/linux-firmware.git master

for you to fetch changes up to 4ba60409661aae0f53e2ade1e935252846cb7ee8:

  cavium: Add firmware for Octeon III PKI. (2017-10-31 16:31:11 -0500)


Steven J. Hill (1):
  cavium: Add firmware for Octeon III PKI.

 cavium/pki-cluster.bin | Bin 0 -> 7488 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 cavium/pki-cluster.bin

[PATCH v3] ethernet: cavium: octeon: Switch to using netdev_info().

[Steven J. Hill]

Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c | 24 +++-
 1 file changed, 11 insertions(+), 13 deletions(-)

diff --git a/drivers/net/ethernet/cavium/octeon/octeon_mgmt.c 
b/drivers/net/ethernet/cavium/octeon/octeon_mgmt.c
index 2887bca..3f6afb5 100644
--- a/drivers/net/ethernet/cavium/octeon/octeon_mgmt.c
+++ b/drivers/net/ethernet/cavium/octeon/octeon_mgmt.c
@@ -705,14 +705,15 @@ static int octeon_mgmt_ioctl_hwtstamp(struct net_device 
*netdev,
u64 clock_comp = (NSEC_PER_SEC << 32) / 
octeon_get_io_clock_rate();
if (!ptp.s.ptp_en)
cvmx_write_csr(CVMX_MIO_PTP_CLOCK_COMP, 
clock_comp);
-   pr_info("PTP Clock: Using sclk reference at %lld Hz\n",
-   (NSEC_PER_SEC << 32) / clock_comp);
+   netdev_info(netdev,
+   "PTP Clock using sclk reference @ %lldHz\n",
+   (NSEC_PER_SEC << 32) / clock_comp);
} else {
/* The clock is already programmed to use a GPIO */
u64 clock_comp = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_COMP);
-   pr_info("PTP Clock: Using GPIO %d at %lld Hz\n",
-   ptp.s.ext_clk_in,
-   (NSEC_PER_SEC << 32) / clock_comp);
+   netdev_info(netdev,
+   "PTP Clock using GPIO%d @ %lld Hz\n",
+   ptp.s.ext_clk_in, (NSEC_PER_SEC << 32) / 
clock_comp);
}
 
/* Enable the clock if it wasn't done already */
@@ -926,14 +927,11 @@ static void octeon_mgmt_adjust_link(struct net_device 
*netdev)
spin_unlock_irqrestore(>lock, flags);
 
if (link_changed != 0) {
-   if (link_changed > 0) {
-   pr_info("%s: Link is up - %d/%s\n", netdev->name,
-   phydev->speed,
-   phydev->duplex == DUPLEX_FULL ?
-   "Full" : "Half");
-   } else {
-   pr_info("%s: Link is down\n", netdev->name);
-   }
+   if (link_changed > 0)
+   netdev_info(netdev, "Link is up - %d/%s\n",
+   phydev->speed, phydev->duplex == 
DUPLEX_FULL ? "Full" : "Half");
+   else
+   netdev_info(netdev, "Link is down\n");
}
 }
 
-- 
2.1.4

[PATCH v2] ethernet: cavium: octeon: Switch to using netdev_info().

[Steven J. Hill]

Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c | 27 +++-
 1 file changed, 12 insertions(+), 15 deletions(-)

diff --git a/drivers/net/ethernet/cavium/octeon/octeon_mgmt.c 
b/drivers/net/ethernet/cavium/octeon/octeon_mgmt.c
index 2887bca..28e10dc 100644
--- a/drivers/net/ethernet/cavium/octeon/octeon_mgmt.c
+++ b/drivers/net/ethernet/cavium/octeon/octeon_mgmt.c
@@ -705,14 +705,15 @@ static int octeon_mgmt_ioctl_hwtstamp(struct net_device 
*netdev,
u64 clock_comp = (NSEC_PER_SEC << 32) / 
octeon_get_io_clock_rate();
if (!ptp.s.ptp_en)
cvmx_write_csr(CVMX_MIO_PTP_CLOCK_COMP, 
clock_comp);
-   pr_info("PTP Clock: Using sclk reference at %lld Hz\n",
-   (NSEC_PER_SEC << 32) / clock_comp);
+   netdev_info(netdev,
+   "PTP Clock using sclk reference @ %lldHz\n",
+   (NSEC_PER_SEC << 32) / clock_comp);
} else {
/* The clock is already programmed to use a GPIO */
u64 clock_comp = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_COMP);
-   pr_info("PTP Clock: Using GPIO %d at %lld Hz\n",
-   ptp.s.ext_clk_in,
-   (NSEC_PER_SEC << 32) / clock_comp);
+   netdev_info(netdev,
+   "PTP Clock using GPIO%d @ %lld Hz\n",
+   ptp.s.ext_clk_in, (NSEC_PER_SEC << 32) / 
clock_comp);
}
 
/* Enable the clock if it wasn't done already */
@@ -925,16 +926,12 @@ static void octeon_mgmt_adjust_link(struct net_device 
*netdev)
 
spin_unlock_irqrestore(>lock, flags);
 
-   if (link_changed != 0) {
-   if (link_changed > 0) {
-   pr_info("%s: Link is up - %d/%s\n", netdev->name,
-   phydev->speed,
-   phydev->duplex == DUPLEX_FULL ?
-   "Full" : "Half");
-   } else {
-   pr_info("%s: Link is down\n", netdev->name);
-   }
-   }
+   if (link_changed != 0)
+   if (link_changed > 0)
+   netdev_info(netdev, "Link is up - %d/%s\n",
+   phydev->speed, phydev->duplex == 
DUPLEX_FULL ? "Full" : "Half");
+   else
+   netdev_info(netdev, "Link is down\n");
 }
 
 static int octeon_mgmt_init_phy(struct net_device *netdev)
-- 
2.1.4

[PATCH v2] ethernet: cavium: octeon: Switch to using netdev_info().

[Steven J. Hill]

Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c | 27 +++-
 1 file changed, 12 insertions(+), 15 deletions(-)

diff --git a/drivers/net/ethernet/cavium/octeon/octeon_mgmt.c 
b/drivers/net/ethernet/cavium/octeon/octeon_mgmt.c
index 2887bca..28e10dc 100644
--- a/drivers/net/ethernet/cavium/octeon/octeon_mgmt.c
+++ b/drivers/net/ethernet/cavium/octeon/octeon_mgmt.c
@@ -705,14 +705,15 @@ static int octeon_mgmt_ioctl_hwtstamp(struct net_device 
*netdev,
u64 clock_comp = (NSEC_PER_SEC << 32) / 
octeon_get_io_clock_rate();
if (!ptp.s.ptp_en)
cvmx_write_csr(CVMX_MIO_PTP_CLOCK_COMP, 
clock_comp);
-   pr_info("PTP Clock: Using sclk reference at %lld Hz\n",
-   (NSEC_PER_SEC << 32) / clock_comp);
+   netdev_info(netdev,
+   "PTP Clock using sclk reference @ %lldHz\n",
+   (NSEC_PER_SEC << 32) / clock_comp);
} else {
/* The clock is already programmed to use a GPIO */
u64 clock_comp = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_COMP);
-   pr_info("PTP Clock: Using GPIO %d at %lld Hz\n",
-   ptp.s.ext_clk_in,
-   (NSEC_PER_SEC << 32) / clock_comp);
+   netdev_info(netdev,
+   "PTP Clock using GPIO%d @ %lld Hz\n",
+   ptp.s.ext_clk_in, (NSEC_PER_SEC << 32) / 
clock_comp);
}
 
/* Enable the clock if it wasn't done already */
@@ -925,16 +926,12 @@ static void octeon_mgmt_adjust_link(struct net_device 
*netdev)
 
spin_unlock_irqrestore(>lock, flags);
 
-   if (link_changed != 0) {
-   if (link_changed > 0) {
-   pr_info("%s: Link is up - %d/%s\n", netdev->name,
-   phydev->speed,
-   phydev->duplex == DUPLEX_FULL ?
-   "Full" : "Half");
-   } else {
-   pr_info("%s: Link is down\n", netdev->name);
-   }
-   }
+   if (link_changed != 0)
+   if (link_changed > 0)
+   netdev_info(netdev, "Link is up - %d/%s\n",
+   phydev->speed, phydev->duplex == 
DUPLEX_FULL ? "Full" : "Half");
+   else
+   netdev_info(netdev, "Link is down\n");
 }
 
 static int octeon_mgmt_init_phy(struct net_device *netdev)
-- 
2.1.4

[PATCH] ethernet: cavium: octeon: Switch to using netdev_info().

[Steven J. Hill]

Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
---
 drivers/net/ethernet/cavium/octeon/octeon_mgmt.c | 25 +++-
 1 file changed, 11 insertions(+), 14 deletions(-)

diff --git a/drivers/net/ethernet/cavium/octeon/octeon_mgmt.c 
b/drivers/net/ethernet/cavium/octeon/octeon_mgmt.c
index 2887bca..3bb8fbd 100644
--- a/drivers/net/ethernet/cavium/octeon/octeon_mgmt.c
+++ b/drivers/net/ethernet/cavium/octeon/octeon_mgmt.c
@@ -705,14 +705,15 @@ static int octeon_mgmt_ioctl_hwtstamp(struct net_device 
*netdev,
u64 clock_comp = (NSEC_PER_SEC << 32) / 
octeon_get_io_clock_rate();
if (!ptp.s.ptp_en)
cvmx_write_csr(CVMX_MIO_PTP_CLOCK_COMP, 
clock_comp);
-   pr_info("PTP Clock: Using sclk reference at %lld Hz\n",
+   netdev_info(netdev,
+   "PTP Clock: Using sclk reference at %lld Hz\n",
(NSEC_PER_SEC << 32) / clock_comp);
} else {
/* The clock is already programmed to use a GPIO */
u64 clock_comp = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_COMP);
-   pr_info("PTP Clock: Using GPIO %d at %lld Hz\n",
-   ptp.s.ext_clk_in,
-   (NSEC_PER_SEC << 32) / clock_comp);
+   netdev_info(netdev,
+   "PTP Clock: Using GPIO %d at %lld Hz\n",
+   ptp.s.ext_clk_in, (NSEC_PER_SEC << 32) / 
clock_comp);
}
 
/* Enable the clock if it wasn't done already */
@@ -925,16 +926,12 @@ static void octeon_mgmt_adjust_link(struct net_device 
*netdev)
 
spin_unlock_irqrestore(>lock, flags);
 
-   if (link_changed != 0) {
-   if (link_changed > 0) {
-   pr_info("%s: Link is up - %d/%s\n", netdev->name,
-   phydev->speed,
-   phydev->duplex == DUPLEX_FULL ?
-   "Full" : "Half");
-   } else {
-   pr_info("%s: Link is down\n", netdev->name);
-   }
-   }
+   if (link_changed != 0)
+   if (link_changed > 0)
+   netdev_info(netdev, "Link is up - %d/%s\n",
+   phydev->speed, phydev->duplex == DUPLEX_FULL ? 
"Full" : "Half");
+   else
+   netdev_info(netdev, "Link is down\n");
 }
 
 static int octeon_mgmt_init_phy(struct net_device *netdev)
-- 
2.1.4

Re: [PATCH] Merge GT/MV642xx Support into MV643xx Driver [7/8]

[Steven J. Hill]

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

Dale Farnsworth wrote:
 
 You have replaced the use of the global PHY spinlock with a per-port spinlock.
 However, the SMI register is shared by all ports.  The global lock is
 needed to prevent simultaneous updates of the register by drivers for
 multiple ports.
 
 NAK

Are you sure? Notice that a majority of the spinlocks were changed to disable
IRQs. Secondly, the lowest level mv_read/mv_write functions have to acquire
the big mv64x60_lock before they can read or write registers. I see the PHY
spinlock as being an additional and unnecessary lock to contend with. Am I
make an improper assumption?

- -Steve
-BEGIN PGP SIGNATURE-
Version: GnuPG v1.4.2.2 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

iD8DBQFGoBmSgyK5H2Ic36cRAj8JAKCfmg/T2FgOdYZ5YfnXJsiyn3RkaQCfadSk
GS8ICyW0+qNRHr5QqnY0PUQ=
=nvSB
-END PGP SIGNATURE-
-
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the body of a message to [EMAIL PROTECTED]
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[PATCH] Merge GT/MV642xx Support into MV643xx Driver [4/8]

[Steven J. Hill]

Add main 642xx support to 'drivers/net/mv643xx_eth.c' file.

Signed-off-by: Steven J. Hill [EMAIL PROTECTED]
---

--- linux-2.6.22.1/drivers/net/mv643xx_eth.c	2007-07-18 22:19:31.0 -0500
+++ linux-2.6.22.1-rci/drivers/net/mv643xx_eth.c	2007-07-18 22:22:04.0 -0500
@@ -13,8 +13,7 @@
  * Copyright (C) 2004-2006 MontaVista Software, Inc.
  *			   Dale Farnsworth [EMAIL PROTECTED]
  *
- * Copyright (C) 2004 Steven J. Hill [EMAIL PROTECTED]
- * [EMAIL PROTECTED]
+ * Copyright (C) 2004-2007 Steven J. Hill [EMAIL PROTECTED]
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -48,6 +47,11 @@
 #include asm/pgtable.h
 #include asm/system.h
 #include asm/delay.h
+#ifdef CONFIG_GT64260
+# include asm/cacheflush.h
+# include asm/tlbflush.h
+# include asm/mv64x60.h
+#endif
 #include mv643xx_eth.h
 
 /* Static function declarations */
@@ -83,6 +87,14 @@
 
 /* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
 static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
+#ifdef CONFIG_GT64260
+extern struct mv64x60_handle bh;
+static u32 eth_hash_table_size[3] = { 1, 1, 1 };
+static u32 eth_hash_table_hash_mode[3] = { 0, 0, 0 };
+static u32 eth_hash_table_default_mode[3] = { 0, 0, 0 };
+static u32 eth_hash_table_vbase_addr[3];
+static const u32 eth_hash_length[2] = { 0x8000, 0x800 };
+#endif
 
 static inline u32 mv_read(int offset)
 {
@@ -102,7 +114,7 @@
 }
 
 /*
- * Changes MTU (maximum transfer unit) of the gigabit ethenret port
+ * Changes MTU (maximum transfer unit) of the gigabit ethernet port
  *
  * Input :	pointer to ethernet interface network device structure
  *		new mtu size
@@ -113,6 +125,29 @@
 	if ((new_mtu  9500) || (new_mtu  64))
 		return -EINVAL;
 
+#ifdef CONFIG_GT64260
+	/*
+	 * The 642XX needs the frame length to be set for certain MTU
+	 * sizes to avoid length overrun errors.
+	 */
+	{
+		struct mv643xx_private *mp = netdev_priv(dev);
+		unsigned int reg;
+
+		reg = mv_read(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(mp-port_num));
+
+		if (new_mtu = 1528)
+			reg = ~(0x3  14);
+		else if (new_mtu = 1536)
+			reg |= (0x1  14);
+		else if (new_mtu = 2048)
+			reg |= (0x2  14);
+		else
+			reg |= (0x3  14);
+
+		mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(mp-port_num), reg);
+	}
+#endif
 	dev-mtu = new_mtu;
 	/*
 	 * Stop then re-open the interface. This will allocate RX skb's with
@@ -158,13 +193,18 @@
 		pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
 		pkt_info.buf_ptr = dma_map_single(NULL, skb-data,
 	ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
+#ifdef CONFIG_GT64260
+		invalidate_dcache_addr_size((u32) skb-data, dev-mtu);
+#endif
 		pkt_info.return_info = skb;
 		if (eth_rx_return_buff(mp, pkt_info) != ETH_OK) {
 			printk(KERN_ERR
 %s: Error allocating RX Ring\n, dev-name);
 			break;
 		}
+#ifndef CONFIG_GT64260
 		skb_reserve(skb, ETH_HW_IP_ALIGN);
+#endif
 	}
 	/*
 	 * If RX ring is empty of SKB, set a timer to try allocating
@@ -323,6 +361,10 @@
 
 		tx_index = mp-tx_used_desc_q;
 		desc = mp-p_tx_desc_area[tx_index];
+#ifdef CONFIG_GT64260
+		invalidate_dcache_addr_size((u32) desc, sizeof(struct eth_tx_desc));
+		mb();
+#endif
 		cmd_sts = desc-cmd_sts;
 
 		if (!force  (cmd_sts  ETH_BUFFER_OWNED_BY_DMA)) {
@@ -338,6 +380,10 @@
 		skb = mp-tx_skb[tx_index];
 		if (skb)
 			mp-tx_skb[tx_index] = NULL;
+#ifdef CONFIG_GT64260
+		flush_dcache_addr_size(skb, skb-len);
+		flush_dcache_addr_size((u32) desc, sizeof(struct eth_tx_desc));
+#endif
 
 		if (cmd_sts  ETH_ERROR_SUMMARY) {
 			printk(%s: Error in TX\n, dev-name);
@@ -381,7 +427,7 @@
  * queues toward kernel core or FastRoute them to another interface.
  *
  * Input :	dev - a pointer to the required interface
- *		max - maximum number to receive (0 means unlimted)
+ *		budget - maximum number to receive (0 means unlimited)
  *
  * Output :	number of served packets
  */
@@ -394,8 +440,10 @@
 	struct pkt_info pkt_info;
 
 	while (budget--  0  eth_port_receive(mp, pkt_info) == ETH_OK) {
+#ifndef CONFIG_GT64260
 		dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE,
 			DMA_FROM_DEVICE);
+#endif
 		mp-rx_desc_count--;
 		received_packets++;
 
@@ -429,6 +477,12 @@
 
 			dev_kfree_skb_irq(skb);
 		} else {
+#ifdef CONFIG_GT64260
+			skb_put(skb, pkt_info.byte_cnt);
+			skb-ip_summed = CHECKSUM_NONE;
+			skb-pkt_type = PACKET_HOST;
+			skb-dev = dev;
+#else
 			/*
 			 * The -4 is for the CRC in the trailer of the
 			 * received packet
@@ -440,6 +494,7 @@
 skb-csum = htons(
 	(pkt_info.cmd_sts  0x0007fff8)  3);
 			}
+#endif
 			skb-protocol = eth_type_trans(skb, dev);
 #ifdef MV643XX_NAPI
 			netif_receive_skb(skb);
@@ -460,6 +515,7 @@
 {
 	struct mv643xx_private *mp = netdev_priv(dev);
 	int port_num = mp-port_num;
+#ifndef CONFIG_GT64260
 	u32 o_pscr, n_pscr;
 	unsigned int queues;
 
@@ -502,6 +558,52 @@
 mv643xx_eth_port_enable_tx(port_num, queues);
 		}
 	}
+#else
+	u32 o_pcr, n_pcr;
+	u32 o_pcxr, n_pcxr;
+	unsigned int queues

[PATCH] Merge GT/MV642xx Support into MV643xx Driver [5/8]

[Steven J. Hill]

Fix 'mv643xx_eth_tx_timeout_task' function prototype.

Signed-off-by: Steven J. Hill [EMAIL PROTECTED]
---
--- linux-2.6.22.1/drivers/net/mv643xx_eth.c	2007-07-18 21:45:13.0 -0500
+++ linux-2.6.22.1-rci/drivers/net/mv643xx_eth.c	2007-07-18 21:44:07.0 -0500
@@ -317,11 +315,9 @@
  *
  * Actual routine to reset the adapter when a timeout on Tx has occurred
  */
-static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
+static void mv643xx_eth_tx_timeout_task(struct net_device *dev)
 {
-	struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private,
-		  tx_timeout_task);
-	struct net_device *dev = mp-mii.dev; /* yuck */
+	struct mv643xx_private *mp = netdev_priv(dev);
 
 	if (!netif_running(dev))
 		return;


signature.asc
Description: OpenPGP digital signature

[PATCH] Merge GT/MV642xx Support into MV643xx Driver [6/8]

[Steven J. Hill]

Fix the TX bytes statistics counter to, um, actually count.

Signed-off-by: Steven J. Hill [EMAIL PROTECTED]
---
--- linux-2.6.22.1/drivers/net/mv643xx_eth.c	2007-07-18 21:51:49.0 -0500
+++ linux-2.6.22.1-rci/drivers/net/mv643xx_eth.c	2007-07-18 21:44:07.0 -0500
@@ -1506,7 +1511,7 @@
 	spin_lock_irqsave(mp-lock, flags);
 
 	eth_tx_submit_descs_for_skb(mp, skb);
-	stats-tx_bytes = skb-len;
+	stats-tx_bytes += skb-len;
 	stats-tx_packets++;
 	dev-trans_start = jiffies;
 


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Description: OpenPGP digital signature

[PATCH] Merge GT/MV642xx Support into MV643xx Driver [7/8]

[Steven J. Hill]

Get rid of global PHY spinlock.

Signed-off-by: Steven J. Hill [EMAIL PROTECTED]
---
diff -ur linux-2.6.22.1/drivers/net/mv643xx_eth.c linux-2.6.22.1-rci/drivers/net/mv643xx_eth.c
--- linux-2.6.22.1/drivers/net/mv643xx_eth.c	2007-07-18 22:51:54.0 -0500
+++ linux-2.6.22.1-rci/drivers/net/mv643xx_eth.c	2007-07-18 22:39:37.0 -0500
@@ -74,7 +74,7 @@
 #endif
 static int ethernet_phy_get(unsigned int eth_port_num);
 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
-static int ethernet_phy_detect(unsigned int eth_port_num);
+static int ethernet_phy_detect(struct mv643xx_private *mp);
 static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location);
 static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val);
 static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
@@ -85,8 +85,6 @@
 
 static void __iomem *mv643xx_eth_shared_base;
 
-/* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
-static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
 #ifdef CONFIG_GT64260
 extern struct mv64x60_handle bh;
 static u32 eth_hash_table_size[3] = { 1, 1, 1 };
@@ -936,11 +927,12 @@
 static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 {
 	struct mv643xx_private *mp = netdev_priv(dev);
+	unsigned long flags;
 	int err;
 
-	spin_lock_irq(mp-lock);
+	spin_lock_irqsave(mp-lock, flags);
 	err = mii_ethtool_sset(mp-mii, cmd);
-	spin_unlock_irq(mp-lock);
+	spin_unlock_irqrestore(mp-lock, flags);
 
 	return err;
 }
@@ -948,11 +940,12 @@
 static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 {
 	struct mv643xx_private *mp = netdev_priv(dev);
+	unsigned long flags;
 	int err;
 
-	spin_lock_irq(mp-lock);
+	spin_lock_irqsave(mp-lock, flags);
 	err = mii_ethtool_gset(mp-mii, cmd);
-	spin_unlock_irq(mp-lock);
+	spin_unlock_irqrestore(mp-lock, flags);
 
 	/* The PHY may support 1000baseT_Half, but the mv643xx does not */
 	cmd-supported = ~SUPPORTED_1000baseT_Half;
@@ -1594,12 +1599,12 @@
 static int mv643xx_eth_probe(struct platform_device *pdev)
 {
 	struct mv643xx_eth_platform_data *pd;
-	int port_num;
+	unsigned int port_num;
 	struct mv643xx_private *mp;
 	struct net_device *dev;
 	u8 *p;
 	struct resource *res;
-	int err;
+	int err = 0;
 	struct ethtool_cmd cmd;
 	int duplex = DUPLEX_HALF;
 	int speed = 0;			/* default to auto-negotiation */
@@ -1702,7 +1707,7 @@
 	mp-mii.phy_id_mask = 0x3f;
 	mp-mii.reg_num_mask = 0x1f;
 
-	err = ethernet_phy_detect(port_num);
+	err = ethernet_phy_detect(mp);
 	if (err) {
 		pr_debug(MV643xx ethernet port %d: 
 	No PHY detected at addr %d\n,
@@ -1710,7 +1715,7 @@
 		goto out;
 	}
 
-	ethernet_phy_reset(port_num);
+	ethernet_phy_reset(mp);
 	mp-mii.supports_gmii = mii_check_gmii_support(mp-mii);
 	mv643xx_init_ethtool_cmd(dev, mp-mii.phy_id, speed, duplex, cmd);
 	mv643xx_eth_update_pscr(dev, cmd);
@@ -2158,7 +2163,7 @@
 
 	/* save phy settings across reset */
 	mv643xx_get_settings(dev, ethtool_cmd);
-	ethernet_phy_reset(mp-port_num);
+	ethernet_phy_reset(mp);
 	mv643xx_set_settings(dev, ethtool_cmd);
 }
 
@@ -2761,22 +2766,22 @@
  *	-ENODEV on failure
  *
  */
-static int ethernet_phy_detect(unsigned int port_num)
+static int ethernet_phy_detect(struct mv643xx_private *mp)
 {
 	unsigned int phy_reg_data0;
 	int auto_neg;
 
-	eth_port_read_smi_reg(port_num, 0, phy_reg_data0);
+	eth_port_read_smi_reg(mp, 0, phy_reg_data0);
 	auto_neg = phy_reg_data0  0x1000;
 	phy_reg_data0 ^= 0x1000;	/* invert auto_neg */
-	eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
+	eth_port_write_smi_reg(mp, 0, phy_reg_data0);
 
-	eth_port_read_smi_reg(port_num, 0, phy_reg_data0);
+	eth_port_read_smi_reg(mp, 0, phy_reg_data0);
 	if ((phy_reg_data0  0x1000) == auto_neg)
 		return -ENODEV;/* change didn't take */
 
 	phy_reg_data0 ^= 0x1000;
-	eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
+	eth_port_write_smi_reg(mp, 0, phy_reg_data0);
 	return 0;
 }
 
@@ -2849,19 +2854,19 @@
  *	None.
  *
  */
-static void ethernet_phy_reset(unsigned int eth_port_num)
+static void ethernet_phy_reset(struct mv643xx_private *mp)
 {
 	unsigned int phy_reg_data;
 
 	/* Reset the PHY */
-	eth_port_read_smi_reg(eth_port_num, 0, phy_reg_data);
+	eth_port_read_smi_reg(mp, 0, phy_reg_data);
 	phy_reg_data |= 0x8000;	/* Set bit 15 to reset the PHY */
-	eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
+	eth_port_write_smi_reg(mp, 0, phy_reg_data);
 
 	/* wait for PHY to come out of reset */
 	do {
 		udelay(1);
-		eth_port_read_smi_reg(eth_port_num, 0, phy_reg_data);
+		eth_port_read_smi_reg(mp, 0, phy_reg_data);
 	} while (phy_reg_data  0x8000);
 }
 
@@ -3033,15 +3038,18 @@
  *	true otherwise.
  *
  */
-static void eth_port_read_smi_reg(unsigned int port_num,
+static void eth_port_read_smi_reg(struct mv643xx_private *mp,
 unsigned int phy_reg, unsigned int *value)
 {
-	int phy_addr = ethernet_phy_get(port_num);
+	int port_num = mp-port_num;
+	int

[PATCH] Merge GT/MV642xx Support into MV643xx Driver [8/8]

[Steven J. Hill]

Fix long standing panic with regards to descriptors and locking.

Signed-off-by: Steven J. Hill [EMAIL PROTECTED]
---
diff -ur linux-2.6.22.1/drivers/net/mv643xx_eth.c linux-2.6.22.1-rci/drivers/net/mv643xx_eth.c
--- linux-2.6.22.1/drivers/net/mv643xx_eth.c	2007-07-18 22:55:11.0 -0500
+++ linux-2.6.22.1-rci/drivers/net/mv643xx_eth.c	2007-07-18 22:39:37.0 -0500
@@ -350,13 +350,6 @@
 
 	while (mp-tx_desc_count  0) {
 		spin_lock_irqsave(mp-lock, flags);
-
-		/* tx_desc_count might have changed before acquiring the lock */
-		if (mp-tx_desc_count = 0) {
-			spin_unlock_irqrestore(mp-lock, flags);
-			return released;
-		}
-
 		tx_index = mp-tx_used_desc_q;
 		desc = mp-p_tx_desc_area[tx_index];
 #ifdef CONFIG_GT64260
@@ -367,7 +360,7 @@
 
 		if (!force  (cmd_sts  ETH_BUFFER_OWNED_BY_DMA)) {
 			spin_unlock_irqrestore(mp-lock, flags);
-			return released;
+			continue;
 		}
 
 		mp-tx_used_desc_q = (tx_index + 1) % mp-tx_ring_size;
@@ -1488,7 +1481,19 @@
 	BUG_ON(netif_queue_stopped(dev));
 	BUG_ON(skb == NULL);
 
-	if (mp-tx_ring_size - mp-tx_desc_count  MAX_DESCS_PER_SKB) {
+	if (mp-tx_ring_size - mp-tx_desc_count = MAX_DESCS_PER_SKB) {
+		/*
+		 * We are completely out of TX descriptors, however,
+		 * if 'tx_used_desc_q' is zero, most likely the port
+		 * has been configured and is up, but there is no link.
+		 * We attempt to free a single descriptor to keep the
+		 * 'sendto' call and rest of the stack happy. If this
+		 * check is taken out, expect an error and kernel panic
+		 * from 'kernel/softirq.c:141' inside 'local_bh_enable'.
+		 */
+		if (mp-tx_used_desc_q == 0)
+			mv643xx_eth_free_all_tx_descs(dev);
+
 		printk(KERN_ERR %s: transmit with queue full\n, dev-name);
 		netif_stop_queue(dev);
 		return 1;


signature.asc
Description: OpenPGP digital signature

[PATCH] Merge GT/MV642xx Support into MV643xx Driver [3/8]

[Steven J. Hill]

Add 642xx support to 'drivers/net/mv643xx_eth.h'

Signed-off-by: Steven J. Hill [EMAIL PROTECTED]
---
--- linux-2.6.22.1/drivers/net/mv643xx_eth.h	2007-07-11 08:53:06.0 -0500
+++ linux-2.6.22.1-rci/drivers/net/mv643xx_eth.h	2007-07-11 09:28:16.0 -0500
@@ -14,8 +14,13 @@
 /* Checksum offload for Tx works for most packets, but
  * fails if previous packet sent did not use hw csum
  */
+#ifdef CONFIG_GT64260
+#undef	MV643XX_CHECKSUM_OFFLOAD_TX
+#undef	MV643XX_NAPI
+#else
 #define	MV643XX_CHECKSUM_OFFLOAD_TX
 #define	MV643XX_NAPI
+#endif
 #define	MV643XX_TX_FAST_REFILL
 #undef	MV643XX_COAL
 
@@ -54,17 +59,31 @@
 #define ETH_RX_QUEUES_ENABLED	(1  0)	/* use only Q0 for receive */
 #define ETH_TX_QUEUES_ENABLED	(1  0)	/* use only Q0 for transmit */
 
+#ifdef CONFIG_GT64260
+#define ETH_INT_CAUSE_RX_DONE	(ETH_RX_QUEUES_ENABLED  16)
+#define ETH_INT_CAUSE_RX_ERROR	(ETH_RX_QUEUES_ENABLED  20)
+#define ETH_INT_CAUSE_RX	(ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
+#define ETH_INT_UNMASK_ALL	0x30ff010d
+#else
 #define ETH_INT_CAUSE_RX_DONE	(ETH_RX_QUEUES_ENABLED  2)
 #define ETH_INT_CAUSE_RX_ERROR	(ETH_RX_QUEUES_ENABLED  9)
 #define ETH_INT_CAUSE_RX	(ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
 #define ETH_INT_CAUSE_EXT	0x0002
 #define ETH_INT_UNMASK_ALL	(ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
+#endif
 
+#ifdef CONFIG_GT64260
+#define ETH_INT_CAUSE_TX_DONE	(ETH_TX_QUEUES_ENABLED  2)
+#define ETH_INT_CAUSE_TX_ERROR	(ETH_TX_QUEUES_ENABLED  10)
+#define ETH_INT_CAUSE_TX	(ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
+#define ETH_INT_CAUSE_PHY	0x1000
+#else
 #define ETH_INT_CAUSE_TX_DONE	(ETH_TX_QUEUES_ENABLED  0)
 #define ETH_INT_CAUSE_TX_ERROR	(ETH_TX_QUEUES_ENABLED  8)
 #define ETH_INT_CAUSE_TX	(ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
 #define ETH_INT_CAUSE_PHY	0x0001
 #define ETH_INT_UNMASK_ALL_EXT	(ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY)
+#endif
 
 #define ETH_INT_MASK_ALL	0x
 #define ETH_INT_MASK_ALL_EXT	0x
@@ -73,11 +92,42 @@
 #define PHY_WAIT_MICRO_SECONDS	10
 
 /* Buffer offset from buffer pointer */
+#ifdef CONFIG_GT64260
+#define RX_BUF_OFFSET0x4
+#else
 #define RX_BUF_OFFSET0x2
+#endif
 
 /* Gigabit Ethernet Unit Global Registers */
 
 /* MIB Counters register definitions */
+#ifdef CONFIG_GT64260
+#define ETH_MIB_OCTETS_RECEIVED			0x0
+#define ETH_MIB_OCTETS_SENT			0x4
+#define ETH_MIB_FRAMES_RECEIVED			0x8
+#define ETH_MIB_FRAMES_SENT			0xc
+#define ETH_MIB_TOTAL_OCTETS_RECEIVED		0x10
+#define ETH_MIB_TOTAL_FRAMES_RECEIVED		0x14
+#define ETH_MIB_BROADCAST_FRAMES_RECEIVED	0x18
+#define ETH_MIB_MULTICAST_FRAMES_RECEIVED	0x1c
+#define ETH_MIB_BAD_CRC_EVENT			0x20
+#define ETH_MIB_OVERSIZE_RECEIVED		0x24
+#define ETH_MIB_FRAGMENTS_RECEIVED		0x28
+#define ETH_MIB_JABBER_RECEIVED			0x2c
+#define ETH_MIB_COLLISION			0x30
+#define ETH_MIB_LATE_COLLISION			0x34
+#define ETH_MIB_FRAMES_64_OCTETS		0x38
+#define ETH_MIB_FRAMES_65_TO_127_OCTETS		0x3c
+#define ETH_MIB_FRAMES_128_TO_255_OCTETS	0x40
+#define ETH_MIB_FRAMES_256_TO_511_OCTETS	0x44
+#define ETH_MIB_FRAMES_512_TO_1023_OCTETS	0x48
+#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS	0x4c
+#define ETH_MIB_MAC_RECEIVE_ERROR		0x50
+#define ETH_MIB_DROPPED_FRAMES			0x54
+#define ETH_MIB_MULTICAST_FRAMES_SENT		0x58
+#define ETH_MIB_BROADCAST_FRAMES_SENT		0x5c
+#define ETH_MIB_UNDERSIZE_RECEIVED		0x60
+#else
 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW	0x0
 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH	0x4
 #define ETH_MIB_BAD_OCTETS_RECEIVED		0x8
@@ -110,6 +160,7 @@
 #define ETH_MIB_BAD_CRC_EVENT			0x74
 #define ETH_MIB_COLLISION			0x78
 #define ETH_MIB_LATE_COLLISION			0x7c
+#endif
 
 /* Port serial status reg (PSR) */
 #define ETH_INTERFACE_PCM			0x0001
@@ -134,18 +185,35 @@
 /* SDMA command status fields macros */
 
 /* Tx  Rx descriptors status */
+#ifdef CONFIG_GT64260
+#define ETH_ERROR_SUMMARY			0x8000
+#else
 #define ETH_ERROR_SUMMARY			0x0001
+#endif
 
 /* Tx  Rx descriptors command */
 #define ETH_BUFFER_OWNED_BY_DMA			0x8000
 
 /* Tx descriptors status */
+#ifdef CONFIG_GT64260
+#define ETH_LC_ERROR0x0020
+#define ETH_UR_ERROR0x0040
+#define ETH_RL_ERROR0x0100
+#else
 #define ETH_LC_ERROR0
 #define ETH_UR_ERROR0x0002
 #define ETH_RL_ERROR0x0004
 #define ETH_LLC_SNAP_FORMAT			0x0200
+#endif
 
 /* Rx descriptors status */
+#ifdef CONFIG_GT64260
+#define ETH_OVERRUN_ERROR			0x0040
+#define ETH_MAX_FRAME_LENGTH_ERROR		0x0080
+#define ETH_RX_LAST_DESC			0x0001
+#define ETH_RX_FIRST_DESC			0x0002
+#define ETH_RX_ENABLE_INTERRUPT			0x0080
+#else
 #define ETH_OVERRUN_ERROR			0x0002
 #define ETH_MAX_FRAME_LENGTH_ERROR		0x0004
 #define ETH_RESOURCE_ERROR			0x0006
@@ -161,11 +229,19 @@
 #define ETH_UNKNOWN_DESTINATION_ADDR		0x1000
 #define ETH_RX_ENABLE_INTERRUPT			0x2000
 #define ETH_LAYER_4_CHECKSUM_OK			0x4000
+#endif
 
 /* Rx descriptors byte count */
 #define ETH_FRAME_FRAGMENTED			0x0004
 
 /* Tx

[PATCH] Merge GT/MV642xx Support into MV643xx Driver [2/8]

[Steven J. Hill]

Add #defines for RGMII Discovery II/III in 'include/linux/mv643xx.h' file.

Signed-off-by: Steven J. Hill [EMAIL PROTECTED]
---
--- linux-2.6.22.1/include/linux/mv643xx.h	2007-05-10 15:16:24.0 -0500
+++ linux-2.6.22.1-rci/include/linux/mv643xx.h	2007-07-18 15:50:44.0 -0500
@@ -1243,6 +1379,8 @@
 #define MV643XX_ETH_SET_GMII_SPEED_TO_1000		(123)
 #define MV643XX_ETH_SET_MII_SPEED_TO_10			0
 #define MV643XX_ETH_SET_MII_SPEED_TO_100		(124)
+#define MV643XX_ETH_SET_RGMII_TX_DELAY			(126)
+#define MV643XX_ETH_SET_RGMII_RX_DELAY			(127)
 
 #define MV643XX_ETH_MAX_RX_PACKET_MASK			(0x717)
 


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[PATCH] Merge GT/MV642xx Support into MV643xx Driver [1/8]

[Steven J. Hill]

This first patch 642xx #defines to the 'include/linux/mv643xx.h' file.

Signed-off-by: Steven J. Hill [EMAIL PROTECTED]
---

--- linux-2.6.22.1/include/linux/mv643xx.h	2007-05-10 15:16:24.0 -0500
+++ linux-2.6.22.1-rci/include/linux/mv643xx.h	2007-07-18 15:50:44.0 -0500
@@ -666,7 +666,11 @@
 #define MV643XX_ETH_SHARED_REGS_SIZE0x2000
 
 #define MV643XX_ETH_PHY_ADDR_REG0x2000
+#ifdef CONFIG_GT64260
+#define MV643XX_ETH_SMI_REG 0x2010
+#else
 #define MV643XX_ETH_SMI_REG 0x2004
+#endif
 #define MV643XX_ETH_UNIT_DEFAULT_ADDR_REG   0x2008
 #define MV643XX_ETH_UNIT_DEFAULTID_REG  0x200c
 #define MV643XX_ETH_UNIT_INTERRUPT_CAUSE_REG0x2080
@@ -693,6 +697,21 @@
 #define MV643XX_ETH_HIGH_ADDR_REMAP_REG_3   0x228c
 #define MV643XX_ETH_BASE_ADDR_ENABLE_REG0x2290
 #define MV643XX_ETH_ACCESS_PROTECTION_REG(port)(0x2294 + (port2))
+#ifdef CONFIG_GT64260
+#define MV643XX_ETH_PORT_CONFIG_REG(port)  (0x2400 + (port10))
+#define MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port)   (0x2408 + (port10))
+#define MV643XX_ETH_PORT_STATUS_REG(port)  (0x2418 + (port10))
+#define GT64260_ETH_HASH_TABLE_POINTER_REG(port)   (0x2428 + (port10))
+#define MV643XX_ETH_SDMA_CONFIG_REG(port)  (0x2440 + (port10))
+#define MV643XX_ETH_SDMA_COMMAND_REG(port) (0x2448 + (port10))
+#define MV643XX_ETH_INTERRUPT_CAUSE_REG(port)  (0x2450 + (port10))
+#define MV643XX_ETH_INTERRUPT_MASK_REG(port)   (0x2458 + (port10))
+#define MV643XX_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)(0x2470 + (port10))
+#define MV643XX_ETH_RX_FIRST_QUEUE_DESC_PTR_0(port)(0x2480 + (port10))
+#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)  (0x24a0 + (port10))
+#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)  (0x24e0 + (port10))
+#define MV643XX_ETH_MIB_COUNTERS_BASE(port)(0x2500 + (port7))
+#else
 #define MV643XX_ETH_MIB_COUNTERS_BASE(port)(0x3000 + (port7))
 #define MV643XX_ETH_PORT_CONFIG_REG(port)  (0x2400 + (port10))
 #define MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port)   (0x2404 + (port10))
@@ -775,6 +794,7 @@
 #define MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)   (0x3400 + (port10))
 #define MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port10))
 #define MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port10))
+#endif
 
 /***/
 /*  CUNIT  Registers   */
@@ -1094,6 +1114,45 @@
 };
 
 /* These macros describe Ethernet Port configuration reg (Px_cR) bits */
+#define GT64260_ETH_RECEIVE_BC			0
+#define GT64260_ETH_REJECT_BC			(11)
+#define GT64260_ETH_REJECT_BAD_FRAMES		0
+#define GT64260_ETH_RECEIVE_BAD_FRAMES		(12)
+#define GT64260_ETH_DISABLE			0
+#define GT64260_ETH_ENABLE			(17)
+#define GT64260_ETH_CLR_INT_LOOPBACK		0
+#define GT64260_ETH_SET_INT_LOOPBACK		(18)
+#define GT64260_ETH_CLR_EXT_LOOPBACK		0
+#define GT64260_ETH_SET_EXT_LOOPBACK		(19)
+#define GT64260_ETH_DISABLE_FORCE_COLLISION	0
+#define GT64260_ETH_ENABLE_FORCE_COLLISION	(110)
+#define GT64260_ETH_HASH_SIZE_HALFK		0
+#define GT64260_ETH_HASH_SIZE_8K		(112)
+#define GT64260_ETH_HASH_SIZE_SHIFT		12
+#define GT64260_ETH_HASH_MODE_0			0
+#define GT64260_ETH_HASH_MODE_1			(113)
+#define GT64260_ETH_HASH_MODE_SHIFT		13
+#define GT64260_ETH_HASH_DEFAULT_DISCARD	0
+#define GT64260_ETH_HASH_DEFAULT_PASS		(114)
+#define GT64260_ETH_HASH_DEFAULT_SHIFT		14
+#define GT64260_ETH_SET_HALF_DUPLEX_MODE	0
+#define GT64260_ETH_SET_FULL_DUPLEX_MODE	(115)
+#define GT64260_ETH_DISABLE_ACCEL_SLOT_TIME	0
+#define GT64260_ETH_ENABLE_ACCEL_SLOT_TIME	(131)
+
+#define	GT64260_ETH_PORT_CONFIG_DEFAULT_VALUE			\
+		GT64260_ETH_RECEIVE_BC			|	\
+		GT64260_ETH_REJECT_BAD_FRAMES		|	\
+		GT64260_ETH_DISABLE			|	\
+		GT64260_ETH_CLR_INT_LOOPBACK		|	\
+		GT64260_ETH_CLR_EXT_LOOPBACK		|	\
+		GT64260_ETH_DISABLE_FORCE_COLLISION	|	\
+		GT64260_ETH_HASH_SIZE_HALFK		|	\
+		GT64260_ETH_HASH_MODE_0			|	\
+		GT64260_ETH_HASH_DEFAULT_DISCARD	|	\
+		GT64260_ETH_SET_FULL_DUPLEX_MODE	|	\
+		GT64260_ETH_DISABLE_ACCEL_SLOT_TIME
+
 #define MV643XX_ETH_UNICAST_NORMAL_MODE		0
 #define MV643XX_ETH_UNICAST_PROMISCUOUS_MODE	(10)
 #define MV643XX_ETH_DEFAULT_RX_QUEUE_0		0
@@ -1162,6 +1221,59 @@
 		MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0
 
 /* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
+#define GT64260_ETH_IGMP_CAPTURE_ENABLE			0
+#define GT64260_ETH_IGMP_CAPTURE_DISABLE		(10)
+#define