Re: [PATCH net-next 5/5] net: dsa: b53: Add SerDes support
On Tue, Sep 04, 2018 at 04:55:26PM -0700, Florian Fainelli wrote:
> On 09/04/2018 04:32 PM, Andrew Lunn wrote:
> >
> >
> >> +void b53_serdes_phylink_validate(struct b53_device *dev, int port,
> >> + unsigned long *supported,
> >> + struct phylink_link_state *state)
> >> +{
> >> + u8 lane = b53_serdes_map_lane(dev, port);
> >> +
> >> + if (lane == B53_INVALID_LANE)
> >> + return;
> >> +
> >> + switch (lane) {
> >> + case 0:
> >> + phylink_set(supported, 2500baseX_Full);
> >
> > Hi Florian
> >
> > Could you also use it for 2500BaseT_Full with an appropriate copper
> > PHY?
>
> My reading of the datasheet (which only mentions 2.5G with no further
> mention) make me think that is not possible to do copper at 2.5G and
> only 2500baseX since it only talks about fiber and not copper.
>
> Would you recommend a specific SFP that allows that? Like this one:
>
> https://www.flexoptix.net/en/sfp-t-transceiver-2h-gigabit-cat-5e-rj-45-100m-100m-1000m-2500-base-t.html?co8829=85744
I was actually thinking of a 'plain old' copper PHY with a SERDES
interface which can do 25000Base-T. The Marvell 88x3310 or the
Aquantia 10G PHY, for example.
Russell might be able to make a recommendation. I don't have any
Copper SFP modules.
Andrew
Re: [PATCH net-next 5/5] net: dsa: b53: Add SerDes support
On 09/04/2018 04:15 PM, Andrew Lunn wrote: > On Tue, Sep 04, 2018 at 03:11:20PM -0700, Florian Fainelli wrote: >> Add support for the Northstar Plus SerDes which is accessed through a >> special page of the switch. Since this is something that most people >> probably will not want to use, make it a configurable option. >> >> The SerDes supports both SGMII and 1000baseX modes, and is internally >> looking like a seemingly standard MII PHY, except for the few bits that >> got repurposed. > > Hi Florian > > The SERDES in the 6352 also look very similar to a standard MII PHYs. > > Maybe at some point, we should look at the SERDES drivers we have > embedded in different MAC drivers, and see if we can pull them out, > maybe put them in drivers/net/phy. Any SERDES driver being used in > combination with phylink probably has the same API. Yes, that would sound like a good move forward. The SerDes on the Northstar Plus does have a bunch of MII standard registers, but not a whole lot (BMSR, BMCR, MII_PHYSID1/2, AUTONEGADV, AUTONEGLPABIL) and then, it's all custom. It would be good to have possibly a third vendor (Mediatek? Qualcomm?) and see how they did it so we can define an appropriate API. -- Florian
Re: [PATCH net-next 5/5] net: dsa: b53: Add SerDes support
On 09/04/2018 04:32 PM, Andrew Lunn wrote:
>
>
>> +void b53_serdes_phylink_validate(struct b53_device *dev, int port,
>> + unsigned long *supported,
>> + struct phylink_link_state *state)
>> +{
>> +u8 lane = b53_serdes_map_lane(dev, port);
>> +
>> +if (lane == B53_INVALID_LANE)
>> +return;
>> +
>> +switch (lane) {
>> +case 0:
>> +phylink_set(supported, 2500baseX_Full);
>
> Hi Florian
>
> Could you also use it for 2500BaseT_Full with an appropriate copper
> PHY?
My reading of the datasheet (which only mentions 2.5G with no further
mention) make me think that is not possible to do copper at 2.5G and
only 2500baseX since it only talks about fiber and not copper.
Would you recommend a specific SFP that allows that? Like this one:
https://www.flexoptix.net/en/sfp-t-transceiver-2h-gigabit-cat-5e-rj-45-100m-100m-1000m-2500-base-t.html?co8829=85744
--
Florian
Re: [PATCH net-next 5/5] net: dsa: b53: Add SerDes support
> +void b53_serdes_phylink_validate(struct b53_device *dev, int port,
> + unsigned long *supported,
> + struct phylink_link_state *state)
> +{
> + u8 lane = b53_serdes_map_lane(dev, port);
> +
> + if (lane == B53_INVALID_LANE)
> + return;
> +
> + switch (lane) {
> + case 0:
> + phylink_set(supported, 2500baseX_Full);
Hi Florian
Could you also use it for 2500BaseT_Full with an appropriate copper
PHY?
Andrew
Re: [PATCH net-next 5/5] net: dsa: b53: Add SerDes support
On Tue, Sep 04, 2018 at 03:11:20PM -0700, Florian Fainelli wrote: > Add support for the Northstar Plus SerDes which is accessed through a > special page of the switch. Since this is something that most people > probably will not want to use, make it a configurable option. > > The SerDes supports both SGMII and 1000baseX modes, and is internally > looking like a seemingly standard MII PHY, except for the few bits that > got repurposed. Hi Florian The SERDES in the 6352 also look very similar to a standard MII PHYs. Maybe at some point, we should look at the SERDES drivers we have embedded in different MAC drivers, and see if we can pull them out, maybe put them in drivers/net/phy. Any SERDES driver being used in combination with phylink probably has the same API. Andrew
[PATCH net-next 5/5] net: dsa: b53: Add SerDes support
Add support for the Northstar Plus SerDes which is accessed through a
special page of the switch. Since this is something that most people
probably will not want to use, make it a configurable option.
The SerDes supports both SGMII and 1000baseX modes, and is internally
looking like a seemingly standard MII PHY, except for the few bits that
got repurposed.
Signed-off-by: Florian Fainelli
---
drivers/net/dsa/b53/Kconfig | 7 +
drivers/net/dsa/b53/Makefile | 1 +
drivers/net/dsa/b53/b53_common.c | 25
drivers/net/dsa/b53/b53_priv.h | 17 +++
drivers/net/dsa/b53/b53_serdes.c | 217 +++
drivers/net/dsa/b53/b53_serdes.h | 121 +
drivers/net/dsa/b53/b53_srab.c | 109
7 files changed, 497 insertions(+)
create mode 100644 drivers/net/dsa/b53/b53_serdes.c
create mode 100644 drivers/net/dsa/b53/b53_serdes.h
diff --git a/drivers/net/dsa/b53/Kconfig b/drivers/net/dsa/b53/Kconfig
index 37745f4bf4f6..ceb5cee10218 100644
--- a/drivers/net/dsa/b53/Kconfig
+++ b/drivers/net/dsa/b53/Kconfig
@@ -35,3 +35,10 @@ config B53_SRAB_DRIVER
help
Select to enable support for memory-mapped Switch Register Access
Bridge Registers (SRAB) like it is found on the BCM53010
+
+config B53_SERDES
+ tristate "B53 SerDes support"
+ depends on B53
+ default ARCH_BCM_IPROC
+ help
+ Select to enable support for SerDes on e.g: Northstar Plus SoCs.
diff --git a/drivers/net/dsa/b53/Makefile b/drivers/net/dsa/b53/Makefile
index 4256fb42a4dd..b1be13023ae4 100644
--- a/drivers/net/dsa/b53/Makefile
+++ b/drivers/net/dsa/b53/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_B53_SPI_DRIVER)+= b53_spi.o
obj-$(CONFIG_B53_MDIO_DRIVER) += b53_mdio.o
obj-$(CONFIG_B53_MMAP_DRIVER) += b53_mmap.o
obj-$(CONFIG_B53_SRAB_DRIVER) += b53_srab.o
+obj-$(CONFIG_B53_SERDES) += b53_serdes.o
diff --git a/drivers/net/dsa/b53/b53_common.c b/drivers/net/dsa/b53/b53_common.c
index 108d272ca4c7..64d72c713f1e 100644
--- a/drivers/net/dsa/b53/b53_common.c
+++ b/drivers/net/dsa/b53/b53_common.c
@@ -765,6 +765,8 @@ static int b53_reset_switch(struct b53_device *priv)
memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
+ priv->serdes_lane = B53_INVALID_LANE;
+
return b53_switch_reset(priv);
}
@@ -1128,6 +1130,9 @@ void b53_phylink_validate(struct dsa_switch *ds, int port,
struct b53_device *dev = ds->priv;
__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
+ if (dev->ops->serdes_phylink_validate)
+ dev->ops->serdes_phylink_validate(dev, port, mask, state);
+
/* Allow all the expected bits */
phylink_set(mask, Autoneg);
phylink_set_port_modes(mask);
@@ -1164,8 +1169,12 @@ EXPORT_SYMBOL(b53_phylink_validate);
int b53_phylink_mac_link_state(struct dsa_switch *ds, int port,
struct phylink_link_state *state)
{
+ struct b53_device *dev = ds->priv;
int ret = -EOPNOTSUPP;
+ if (dev->ops->serdes_link_state)
+ ret = dev->ops->serdes_link_state(dev, port, state);
+
return ret;
}
EXPORT_SYMBOL(b53_phylink_mac_link_state);
@@ -1182,11 +1191,19 @@ void b53_phylink_mac_config(struct dsa_switch *ds, int
port,
if (mode == MLO_AN_FIXED)
b53_force_port_config(dev, port, state->speed,
state->duplex, state->pause);
+
+ if (phy_interface_mode_is_8023z(state->interface) &&
+ dev->ops->serdes_config)
+ dev->ops->serdes_config(dev, port, mode, state);
}
EXPORT_SYMBOL(b53_phylink_mac_config);
void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port)
{
+ struct b53_device *dev = ds->priv;
+
+ if (dev->ops->serdes_an_restart)
+ dev->ops->serdes_an_restart(dev, port);
}
EXPORT_SYMBOL(b53_phylink_mac_an_restart);
@@ -1203,6 +1220,10 @@ void b53_phylink_mac_link_down(struct dsa_switch *ds,
int port,
b53_force_link(dev, port, false);
return;
}
+
+ if (phy_interface_mode_is_8023z(interface) &&
+ dev->ops->serdes_link_set)
+ dev->ops->serdes_link_set(dev, port, mode, interface, false);
}
EXPORT_SYMBOL(b53_phylink_mac_link_down);
@@ -1220,6 +1241,10 @@ void b53_phylink_mac_link_up(struct dsa_switch *ds, int
port,
b53_force_link(dev, port, true);
return;
}
+
+ if (phy_interface_mode_is_8023z(interface) &&
+ dev->ops->serdes_link_set)
+ dev->ops->serdes_link_set(dev, port, mode, interface, true);
}
EXPORT_SYMBOL(b53_phylink_mac_link_up);
diff --git a/drivers/net/dsa/b53/b53_priv.h b/drivers/net/dsa/b53/b53_priv.h
index 3f79dc07c00f..ec796482792d 100644
--- a/drivers/net/dsa/b53/b53_priv.h
+++ b/drivers/net/dsa/b53/b53_priv.h
@@ -29,6 +29,7 @@
