date:20101223

[OpenWrt-Devel] [PATCH] Update AR7242's Ethernet Setting

2010-12-23 Thread Jess zhu

Hi,

Sorry for many garbage chars in last patch mail. Hope this one has no problem.

Last time I submitted a patch for AR7242 and PB92 but it was not
accepted. I guessed maybe the reason is because of invalid mail
format, so re-submit it again with format revised. This time only
AR7242's Ethernet setting is involved. I will appreciate if anybody
can point out the problem in this patch or this mail.
AR7242 has one GMII/RGMII interface. It is different with
AR7240/AR7241 which have no MII interface.
The frequency of MDC can't be too high, like 50MHz, otherwise AR71xx
would have problem to communicate with external switch devices.
Signed-off-by: Jess Zhu 
Modified:
Index: 
trunk/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
Index: trunk/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c
---

Index: 
trunk/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
===
--- trunk/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h  
(revision
24814)
+++ trunk/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h  
(working
copy)
@@ -152,6 +152,8 @@
 #define AR724X_DDR_DIV_SHIFT   22
 #define AR724X_DDR_DIV_MASK0x3

+#define AR7242_PLL_REG_ETH0_INT_CLOCK  0x2C
+
 #define AR91XX_PLL_REG_CPU_CONFIG  0x00
 #define AR91XX_PLL_REG_ETH_CONFIG  0x04
 #define AR91XX_PLL_REG_ETH0_INT_CLOCK  0x14
Index: trunk/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c
===
--- trunk/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c  (revision 24814)
+++ trunk/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c  (working copy)
@@ -94,7 +94,6 @@
ar71xx_mdio_resources[0].end = AR71XX_GE1_BASE + 0x200 - 1;
break;
case AR71XX_SOC_AR7242:
-   ar71xx_mdio_data.is_ar7240 = 1;
break;
default:
break;
@@ -196,6 +195,19 @@
/* TODO */
 }

+static void ar7242_set_pll_ge0(int speed)
+{
+   u32 val = ar71xx_get_eth_pll(0, speed);
+
+   ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR7242_PLL_REG_ETH0_INT_CLOCK,
+   val, AR71XX_ETH0_PLL_SHIFT);
+}
+
+static void ar7242_set_pll_ge1(int speed)
+{
+   /* TODO */
+}
+
 static void ar91xx_set_pll_ge0(int speed)
 {
u32 val = ar71xx_get_eth_pll(0, speed);
@@ -316,6 +328,10 @@
 #define AR724X_PLL_VAL_100 0x1099
 #define AR724X_PLL_VAL_10  0x00991099

+#define AR7242_PLL_VAL_10000x1600
+#define AR7242_PLL_VAL_100 0x0101
+#define AR7242_PLL_VAL_10  0x1616
+
 #define AR91XX_PLL_VAL_10000x1a00
 #define AR91XX_PLL_VAL_100 0x13000a44
 #define AR91XX_PLL_VAL_10  0x00441099
@@ -347,11 +363,16 @@

case AR71XX_SOC_AR7240:
case AR71XX_SOC_AR7241:
-   case AR71XX_SOC_AR7242:
pll_10 = AR724X_PLL_VAL_10;
pll_100 = AR724X_PLL_VAL_100;
pll_1000 = AR724X_PLL_VAL_1000;
break;
+   
+   case AR71XX_SOC_AR7242: 
+   pll_10 = AR7242_PLL_VAL_10;
+   pll_100 = AR7242_PLL_VAL_100;
+   pll_1000 = AR7242_PLL_VAL_1000;
+   break;  

case AR71XX_SOC_AR9130:
case AR71XX_SOC_AR9132:
@@ -443,7 +464,6 @@
break;

case AR71XX_SOC_AR7241:
-   case AR71XX_SOC_AR7242:
ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO;
ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO;
/* fall through */
@@ -462,6 +482,25 @@
pdata->fifo_cfg3 = 0x01f00140;
break;

+   case AR71XX_SOC_AR7242:
+   ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO;
+   pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
+ : ar724x_ddr_flush_ge0;
+   pdata->set_pll =  id ? ar7242_set_pll_ge1
+: ar7242_set_pll_ge0;
+   pdata->is_ar724x = 1;
+
+   if (!pdata->fifo_cfg1)
+   pdata->fifo_cfg1 = 0x0010;
+   if (!pdata->fifo_cfg2)
+   pdata->fifo_cfg2 = 0x015500aa;
+   if (!pdata->fifo_cfg3)
+   pdata->fifo_cfg3 = 0x01f00140;
+
+   pdata->has_gbit = 1;
+   break;
+   
+
case AR71XX_SOC_AR9130:
pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
  : ar91xx_ddr_flush_ge0;
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[OpenWrt-Devel] [Patch] Update AR7242's Ethernet Setting

2010-12-23 Thread Jess zhu

Hi,

Last time I submitted a patch for AR7242 and PB92 but it was not
accepted. I guessed maybe the reason is because of invalid mail
format, so re-submit it again with format revised. This time only
AR7242's Ethernet setting is involved. I will appreciate if anybody
can point out the problem in this patch or this mail.
AR7242 has one GMII/RGMII interface. It is different with
AR7240/AR7241 which have no MII interface.
The frequency of MDC can't be too high, like 50MHz, otherwise AR71xx
would have problem to communicate with external switch devices.
Signed-off-by: Jess Zhu 
Modified:
Index: 
trunk/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
Index: trunk/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c


Index: 
trunk/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
===
--- trunk/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
 (revision
24814)
+++ trunk/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
 (working
copy)
@@ -152,6 +152,8 @@
 #define AR724X_DDR_DIV_SHIFT           22
 #define AR724X_DDR_DIV_MASK            0x3

+#define AR7242_PLL_REG_ETH0_INT_CLOCK  0x2C
+
 #define AR91XX_PLL_REG_CPU_CONFIG      0x00
 #define AR91XX_PLL_REG_ETH_CONFIG      0x04
 #define AR91XX_PLL_REG_ETH0_INT_CLOCK  0x14
Index: trunk/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c
===
--- trunk/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c  (revision 24814)
+++ trunk/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c  (working copy)
@@ -94,7 +94,6 @@
               ar71xx_mdio_resources[0].end = AR71XX_GE1_BASE + 0x200 - 1;
               break;
       case AR71XX_SOC_AR7242:
-               ar71xx_mdio_data.is_ar7240 = 1;
               break;
       default:
               break;
@@ -196,6 +195,19 @@
       /* TODO */
 }

+static void ar7242_set_pll_ge0(int speed)
+{
+       u32 val = ar71xx_get_eth_pll(0, speed);
+
+       ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR7242_PLL_REG_ETH0_INT_CLOCK,
+                       val, AR71XX_ETH0_PLL_SHIFT);
+}
+
+static void ar7242_set_pll_ge1(int speed)
+{
+       /* TODO */
+}
+
 static void ar91xx_set_pll_ge0(int speed)
 {
       u32 val = ar71xx_get_eth_pll(0, speed);
@@ -316,6 +328,10 @@
 #define AR724X_PLL_VAL_100     0x1099
 #define AR724X_PLL_VAL_10      0x00991099

+#define AR7242_PLL_VAL_1000    0x1600
+#define AR7242_PLL_VAL_100     0x0101
+#define AR7242_PLL_VAL_10      0x1616
+
 #define AR91XX_PLL_VAL_1000    0x1a00
 #define AR91XX_PLL_VAL_100     0x13000a44
 #define AR91XX_PLL_VAL_10      0x00441099
@@ -347,11 +363,16 @@

       case AR71XX_SOC_AR7240:
       case AR71XX_SOC_AR7241:
-       case AR71XX_SOC_AR7242:
               pll_10 = AR724X_PLL_VAL_10;
               pll_100 = AR724X_PLL_VAL_100;
               pll_1000 = AR724X_PLL_VAL_1000;
               break;
+
+       case AR71XX_SOC_AR7242:
+               pll_10 = AR7242_PLL_VAL_10;
+               pll_100 = AR7242_PLL_VAL_100;
+               pll_1000 = AR7242_PLL_VAL_1000;
+               break;

       case AR71XX_SOC_AR9130:
       case AR71XX_SOC_AR9132:
@@ -443,7 +464,6 @@
               break;

       case AR71XX_SOC_AR7241:
-       case AR71XX_SOC_AR7242:
               ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO;
               ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO;
               /* fall through */
@@ -462,6 +482,25 @@
                       pdata->fifo_cfg3 = 0x01f00140;
               break;

+       case AR71XX_SOC_AR7242:
+               ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO;
+               pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
+                                     : ar724x_ddr_flush_ge0;
+               pdata->set_pll =  id ? ar7242_set_pll_ge1
+                                    : ar7242_set_pll_ge0;
+               pdata->is_ar724x = 1;
+
+               if (!pdata->fifo_cfg1)
+                       pdata->fifo_cfg1 = 0x0010;
+               if (!pdata->fifo_cfg2)
+                       pdata->fifo_cfg2 = 0x015500aa;
+               if (!pdata->fifo_cfg3)
+                       pdata->fifo_cfg3 = 0x01f00140;
+
+               pdata->has_gbit = 1;
+               break;
+
+
       case AR71XX_SOC_AR9130:
               pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
                                     : ar91xx_ddr_flush_ge0;
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Re: [OpenWrt-Devel] Broadcom wl driver in trunk

2010-12-23 Thread ch...@martin.cc

On Thu, Dec 23, 2010 at 9:47 PM, Alexey Loukianov  wrote:

> 23.12.2010 13:35, ch...@martin.cc wrote:
> > I am just wondering if the broadom wl driver was working in trunk.
> > I checked out and built trunk this morning without incident
> >
> > However I am unable to associate to the device in AP mode
> >
> > Are there any know issues with this, with regards to supported devices
> >
> > I and using the brcm47xxx target, and running on a Asus WL500gPv2
> > ie: using a brcm 5354.
> >
>
> On Thu, Dec 23, 2010 at 9:47 PM, Alexey Loukianov 
 wrote:

> Was going to ask exactly the same question on the list this morning. I was
> wondering if wl would offer better wifi throughput comparing to the b43 on
> my
> D-Link DIR-320 and had built firmware from trunk rev.24653. After
> configuring
> the wifi config I had been able to spot configured ESSID in the list of
> available wireless networks but any attempts to associate were
> unsuccessful.
> Trying to turn off encryption didn' helped. Looks like something is broken
> with
> wl driver currently in the trunk.
>
>
> I have done a bit more debugging on this issue, and also found two existing
tickets that have been raised against it

https://dev.openwrt.org/ticket/7954
and
https://dev.openwrt.org/ticket/8251

I have added my findings to the first ticket.  Hope fully this will help
someone who knows a bit more about the proprietary broadcom APIs.

cheers
--
Chris Martin
m: 0419812371
--
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[OpenWrt-Devel] coreutils version bump

2010-12-23 Thread Alexander Khryukin

Good day.
coreutils version bump

Index: feeds/packages/utils/coreutils/Makefile
===
--- feeds/packages/utils/coreutils/Makefile(revision 24752)
+++ feeds/packages/utils/coreutils/Makefile(working copy)
@@ -8,12 +8,12 @@
 include $(TOPDIR)/rules.mk

 PKG_NAME:=coreutils
-PKG_VERSION:=8.7
-PKG_RELEASE:=2
+PKG_VERSION:=8.8
+PKG_RELEASE:=1

 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
 PKG_SOURCE_URL:=...@gnu/coreutils
-PKG_MD5SUM:=3c1ae9531159447083ae8f25ae554b81
+PKG_MD5SUM:=bad596d9654e299eedea0eaf93f178fa
 PKG_BUILD_DEPENDS:=libpthread

 include $(INCLUDE_DIR)/package.mk


Signed-off-by: Alexander Khryukin 
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[OpenWrt-Devel] [PATCH] gettext-full: fix header file installation

2010-12-23 Thread Tomasz Moń

Signed-off-by: Tomasz Mon 
diff --git a/libs/gettext-full/Makefile b/libs/gettext-full/Makefile
index 156fafc..77b76d2 100644
--- a/libs/gettext-full/Makefile
+++ b/libs/gettext-full/Makefile
@@ -46,7 +46,7 @@ CONFIGURE_ARGS += \
 
 define Build/InstallDev
$(INSTALL_DIR) $(1)/usr/lib/gettext-full/include
-   $(CP) $(PKG_INSTALL_DIR)/usr/lib/libintl.h 
$(1)/usr/lib/gettext-full/include/
+   $(CP) $(PKG_INSTALL_DIR)/usr/include/libintl.h 
$(1)/usr/lib/gettext-full/include/
 
$(INSTALL_DIR) $(1)/usr/lib/gettext-full/lib
$(CP) $(PKG_INSTALL_DIR)/usr/lib/libintl.{a,so*} 
$(1)/usr/lib/gettext-full/lib/

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Re: [OpenWrt-Devel] [PATCH] update triggerhappy package to version 0.3.2

2010-12-23 Thread Outback Dingo

On Thu, Dec 23, 2010 at 6:03 AM, Stefan Tomanek <
stefan.tomanek+open...@wertarbyte.de
> wrote:

> this introduces several bugfixes
>
> Signed-off-by: Stefan Tomanek 
> 
> >
> ---
>  utils/triggerhappy/Makefile |4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/utils/triggerhappy/Makefile b/utils/triggerhappy/Makefile
> index 58b83b3..2f22fb1 100644
> --- a/utils/triggerhappy/Makefile
> +++ b/utils/triggerhappy/Makefile
> @@ -6,8 +6,8 @@
>  include $(TOPDIR)/rules.mk
>
>  PKG_NAME:=triggerhappy
> -PKG_VERSION:=0.3.1
> -PKG_REV:=168639e0c482ca1668e15c48aaa9ccef286c223a
> +PKG_VERSION:=0.3.2
> +PKG_REV:=c0cedabf8d5bd56ae4cb151ebe708d1ac6a3025d
>  PKG_RELEASE:=1
>
>  PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
> --
> 1.7.1
> ___
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> https://lists.openwrt.org/mailman/listinfo/openwrt-devel


 Committed revision 24812.
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[OpenWrt-Devel] Xen domU and PCI passthrough

2010-12-23 Thread Jean Baptiste Favre (OpenWRT-devel)

Hello,
I'm trying to make openwrt running under Xen with PCI passthrough.
The idea is to give network cards control to openwrt domU and isolate
dom0 and other domUs behind.

Making openwrt domU running works well, but not PCI passthrough.
I need Xen PCI frontend driver which does not seems to be packaged or
activated, even in trunck branch with Linux 2.6.35.

How can I add this driver to OpenWRT ?

Regards,
Jean-Baptiste
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[OpenWrt-Devel] [PATCH] update triggerhappy package to version 0.3.2

2010-12-23 Thread Stefan Tomanek

this introduces several bugfixes

Signed-off-by: Stefan Tomanek 
---
 utils/triggerhappy/Makefile |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/utils/triggerhappy/Makefile b/utils/triggerhappy/Makefile
index 58b83b3..2f22fb1 100644
--- a/utils/triggerhappy/Makefile
+++ b/utils/triggerhappy/Makefile
@@ -6,8 +6,8 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=triggerhappy
-PKG_VERSION:=0.3.1
-PKG_REV:=168639e0c482ca1668e15c48aaa9ccef286c223a
+PKG_VERSION:=0.3.2
+PKG_REV:=c0cedabf8d5bd56ae4cb151ebe708d1ac6a3025d
 PKG_RELEASE:=1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
-- 
1.7.1
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Re: [OpenWrt-Devel] Broadcom wl driver in trunk

2010-12-23 Thread Alexey Loukianov

23.12.2010 13:35, ch...@martin.cc wrote:
> I am just wondering if the broadom wl driver was working in trunk.
> I checked out and built trunk this morning without incident
> 
> However I am unable to associate to the device in AP mode
> 
> Are there any know issues with this, with regards to supported devices
> 
> I and using the brcm47xxx target, and running on a Asus WL500gPv2
> ie: using a brcm 5354.
> 

Was going to ask exactly the same question on the list this morning. I was
wondering if wl would offer better wifi throughput comparing to the b43 on my
D-Link DIR-320 and had built firmware from trunk rev.24653. After configuring
the wifi config I had been able to spot configured ESSID in the list of
available wireless networks but any attempts to associate were unsuccessful.
Trying to turn off encryption didn' helped. Looks like something is broken with
wl driver currently in the trunk.

-- 
Best regards,
Alexey Loukianov  mailto:mooro...@mail.ru
System Engineer,Mob.:+7(926)218-1320
*nix Specialist

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[OpenWrt-Devel] Broadcom wl driver in trunk

2010-12-23 Thread ch...@martin.cc

I am just wondering if the broadom wl driver was working in trunk.
I checked out and built trunk this morning without incident

However I am unable to associate to the device in AP mode

Are there any know issues with this, with regards to supported devices

I and using the brcm47xxx target, and running on a Asus WL500gPv2
ie: using a brcm 5354.

cheers
--
Chris Martin
m: 0419812371
--
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[OpenWrt-Devel] [PATCH] Update AR7242's Ethernet Setting

[OpenWrt-Devel] [Patch] Update AR7242's Ethernet Setting

Re: [OpenWrt-Devel] Broadcom wl driver in trunk

[OpenWrt-Devel] coreutils version bump

[OpenWrt-Devel] [PATCH] gettext-full: fix header file installation

Re: [OpenWrt-Devel] [PATCH] update triggerhappy package to version 0.3.2

[OpenWrt-Devel] Xen domU and PCI passthrough

[OpenWrt-Devel] [PATCH] update triggerhappy package to version 0.3.2

Re: [OpenWrt-Devel] Broadcom wl driver in trunk

[OpenWrt-Devel] Broadcom wl driver in trunk

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