Re: [OpenWrt-Devel] [PATCH] ath79: ar71xx create a separate driver for ar71xx pci interrupt controller.
> > They are similar. I used that code as an example, but the > > irq-ath79-pci has your mask/unmask for pci with reading the registers. > > It is possible to make one driver for both, but is it really needed? > It helps reducing code duplication. If we completely drop that PCI_CORE IRQ that we are not using anyway, I see no reason why we can't define 2 subnodes or the reset controller with the same irq-ath79-misc driver. We'll need only to set PCI IRQs to 0-2 instead of 1-3. That's all. After some other feedback is received, I can do the change. ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] [PATCH v2] build: add mkrasimage
Hi On 2018-08-21, David Bauer wrote: > On 8/21/18 8:31 AM, Stefan Lippers-Hollmann wrote: > > While this passes the version check, the appended git hash does break > > later on in the flashing process - so at the moment only the numerical > > revision (of DISTRIB_REVISION='r7890-40eb9bda44') seems to be safe: > > > > RAS_VERSION := "V1.99(OWRT.$$(shell echo $(REVISION) | sed -e s/^r// -e > > s/\\-.*//))C0" > > Does the version string contained in the RAS-header get exposed to a > user in any way? If not, i would go for using a static (high enough so > it probably never get's used by ZyXEL) version string and call it a day > before we are over-complicating things here. [...] The OEM firmware doesn't expose any information about the other partition set, OpenWrt could make use of it via luci-app-advanced-reboot (but hasn't been doing that so far, as OpenWrt installs and sysupgrades don't update the header partition so far). But hardcoding RAS_VERSION := "V1.99(OWRT.)C0 should be fine for the forseeable future as well. Regards Stefan Lippers-Hollmann pgp5Pz6xkxtHD.pgp Description: Digitale Signatur von OpenPGP ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] [PATCH] ath79: ar71xx create a separate driver for ar71xx pci interrupt controller.
Dmitry Tunin 于2018年8月22日周三 上午12:26写道：
> I am still not very competent in the IRQ handling. I thought that if we set
> interrupts = <4>; and the new partent, your "case 4:" may work.
We have it there because it appears in datasheet. But we don't need it
to work unless we know what it's used for.
>
> > >
> > > + pci_intc: interrupt-controller@18060018 {
> > > + compatible = "qca,ar7100-pci-intc";
> > > + reg = <0x18060018 0x4>;
> > > + interrupt-parent = <>;
> > > + interrupts = <2>;
> > > + interrupt-controller;
> > > + #interrupt-cells = <1>;
> > > + };
> > > +
> > For other chips this node is a subnode of reset-controller. But in
> > this case here we can just put this above reset-controller@18060024.
> > Nodes in dts are supposed to be ordered by register address.
>
> No problem with that, I thought about a child node. But it doesn't
> make any difference IMHO.
> > > +
> > > pcie0: pcie-controller@180c {
> > > compatible = "qca,ar7100-pci";
> > > #address-cells = <3>;
> > > @@ -105,14 +115,16 @@
> > > reg-names = "cfg_base";
> > > ranges = <0x200 0 0x1000
> > > 0x1000 0 0x0700/* pci memory */
> > > 0x100 0 0x
> > > 0x000 0 0x01>; /* io space */
> > > - interrupt-parent = <>;
> > > - interrupts = <2>;
> > > + interrupt-parent = <_intc>;
> > > + interrupts = <4>;
> > Do we really need this? We don't even have a handler that actually do
> > anything for it. I think the above two lines can simply be dropped.
>
> See above. I thought the existing handler could work. I must be wrong.
All the job of the existing handler is now done by the added cascade
driver. And you have removed the existing handler in driver :)
>
> > > diff --git
> > > a/target/linux/ath79/patches-4.14/0020-MIPS-ath79-turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch
> > >
> > > b/target/linux/ath79/patches-4.14/0020-MIPS-ath79-turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch
> > > index ea3514a..95ca6d1 100644
> > > ---
> > > a/target/linux/ath79/patches-4.14/0020-MIPS-ath79-turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch
> > > +++
> > > b/target/linux/ath79/patches-4.14/0020-MIPS-ath79-turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch
> > It's not a good idea to mix the removal of IRQ part into this patch. I
> > suggest using a separated patch to do the removing.
>
> It is a minor issue if everything else looks good. The idea was to
> keep number of patches smaller.
Keeping patches inside that directory less isn't useful at all.(If
it's useful why not squash all of them into one?)
Instead we need each patch did one job and that job is described in
file name/title in mbox header.
As @blogic put in the mbox header, this patch "turns the existing PCI
driver into a pure OF driver" but what you did is "Removing IRQ
dispatcher from PCI driver". Squashing them together only makes the
patch more confusing.
>
>
> > I haven't read the code thoroghly but it seemed that irq-ath79-misc
> > works in a similar way. Is it possible to use the misc intc driver for
> > PCI?
>
> They are similar. I used that code as an example, but the
> irq-ath79-pci has your mask/unmask for pci with reading the registers.
> It is possible to make one driver for both, but is it really needed?
It helps reducing code duplication.
___
openwrt-devel mailing list
openwrt-devel@lists.openwrt.org
https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] [PATCH] ath79: ar71xx create a separate driver for ar71xx pci interrupt controller.
> > This should fix a bug with one IRQ for all PCI devices and also handle the
> > PCI_CORE interrupt.
> No it doesn't. Assigning it in dts doesn't mean that we "handled" it.
> But I still like this patch because it's doing a cleanup of the messy code.
I am still not very competent in the IRQ handling. I thought that if we set
interrupts = <4>; and the new partent, your "case 4:" may work.
> >
> > + pci_intc: interrupt-controller@18060018 {
> > + compatible = "qca,ar7100-pci-intc";
> > + reg = <0x18060018 0x4>;
> > + interrupt-parent = <>;
> > + interrupts = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > +
> For other chips this node is a subnode of reset-controller. But in
> this case here we can just put this above reset-controller@18060024.
> Nodes in dts are supposed to be ordered by register address.
No problem with that, I thought about a child node. But it doesn't
make any difference IMHO.
> > +
> > pcie0: pcie-controller@180c {
> > compatible = "qca,ar7100-pci";
> > #address-cells = <3>;
> > @@ -105,14 +115,16 @@
> > reg-names = "cfg_base";
> > ranges = <0x200 0 0x1000 0x1000
> > 0 0x0700/* pci memory */
> > 0x100 0 0x 0x000
> > 0 0x01>; /* io space */
> > - interrupt-parent = <>;
> > - interrupts = <2>;
> > + interrupt-parent = <_intc>;
> > + interrupts = <4>;
> Do we really need this? We don't even have a handler that actually do
> anything for it. I think the above two lines can simply be dropped.
See above. I thought the existing handler could work. I must be wrong.
> > diff --git
> > a/target/linux/ath79/patches-4.14/0020-MIPS-ath79-turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch
> >
> > b/target/linux/ath79/patches-4.14/0020-MIPS-ath79-turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch
> > index ea3514a..95ca6d1 100644
> > ---
> > a/target/linux/ath79/patches-4.14/0020-MIPS-ath79-turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch
> > +++
> > b/target/linux/ath79/patches-4.14/0020-MIPS-ath79-turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch
> It's not a good idea to mix the removal of IRQ part into this patch. I
> suggest using a separated patch to do the removing.
It is a minor issue if everything else looks good. The idea was to
keep number of patches smaller.
> I haven't read the code thoroghly but it seemed that irq-ath79-misc
> works in a similar way. Is it possible to use the misc intc driver for
> PCI?
They are similar. I used that code as an example, but the
irq-ath79-pci has your mask/unmask for pci with reading the registers.
It is possible to make one driver for both, but is it really needed?
___
openwrt-devel mailing list
openwrt-devel@lists.openwrt.org
https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] [PATCH] ath79: ar71xx create a separate driver for ar71xx pci interrupt controller.
Hi!
Comments inline:
Dmitry Tunin 于2018年8月21日周二 下午10:59写道：
>
> It is based on Chuanhong Guo work.
>
> PCI interrupt controller is not part of PCI. It is a part of reset controller
> with 0x18060018, 0x1806001c control registers.
>
> This should fix a bug with one IRQ for all PCI devices and also handle the
> PCI_CORE interrupt.
No it doesn't. Assigning it in dts doesn't mean that we "handled" it.
But I still like this patch because it's doing a cleanup of the messy code.
>
> I am not sure that this kind of cascading is good for performance, but this
> way we are more flexible when cofiguring IRQs.
It shouldn't affect performance because doing this separation doesn't
change the way it dispatches PCI IRQ.
>
> Run tested on DIR-825 B1.
> ---
> target/linux/ath79/dts/ar7100.dtsi | 22 ++-
> ...turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch | 168 -
> .../0036-MIPS-ath79-add-pci-intc.patch | 205
> +
> 3 files changed, 306 insertions(+), 89 deletions(-)
> create mode 100644
> target/linux/ath79/patches-4.14/0036-MIPS-ath79-add-pci-intc.patch
>
> diff --git a/target/linux/ath79/dts/ar7100.dtsi
> b/target/linux/ath79/dts/ar7100.dtsi
> index 8994a7d..6dc1751 100644
> --- a/target/linux/ath79/dts/ar7100.dtsi
> +++ b/target/linux/ath79/dts/ar7100.dtsi
> @@ -96,6 +96,16 @@
> #reset-cells = <1>;
> };
>
> + pci_intc: interrupt-controller@18060018 {
> + compatible = "qca,ar7100-pci-intc";
> + reg = <0x18060018 0x4>;
> + interrupt-parent = <>;
> + interrupts = <2>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
For other chips this node is a subnode of reset-controller. But in
this case here we can just put this above reset-controller@18060024.
Nodes in dts are supposed to be ordered by register address.
> +
> pcie0: pcie-controller@180c {
> compatible = "qca,ar7100-pci";
> #address-cells = <3>;
> @@ -105,14 +115,16 @@
> reg-names = "cfg_base";
> ranges = <0x200 0 0x1000 0x1000 0
> 0x0700/* pci memory */
> 0x100 0 0x 0x000 0
> 0x01>; /* io space */
> - interrupt-parent = <>;
> - interrupts = <2>;
> + interrupt-parent = <_intc>;
> + interrupts = <4>;
Do we really need this? We don't even have a handler that actually do
anything for it. I think the above two lines can simply be dropped.
>
> - interrupt-controller;
> #interrupt-cells = <1>;
>
> - interrupt-map-mask = <0 0 0 1>;
> - interrupt-map = <0 0 0 0 0>;
> + interrupt-map-mask = <0xf800 0 0 0>;
> + interrupt-map = <0x8800 0 0 0 _intc 1
> +0x9000 0 0 0 _intc 2
> +0x9800 0 0 0 _intc 3>;
> +
> status = "disabled";
> };
> };
> diff --git
> a/target/linux/ath79/patches-4.14/0020-MIPS-ath79-turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch
>
> b/target/linux/ath79/patches-4.14/0020-MIPS-ath79-turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch
> index ea3514a..95ca6d1 100644
> ---
> a/target/linux/ath79/patches-4.14/0020-MIPS-ath79-turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch
> +++
> b/target/linux/ath79/patches-4.14/0020-MIPS-ath79-turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch
It's not a good idea to mix the removal of IRQ part into this patch. I
suggest using a separated patch to do the removing.
> @@ -9,8 +9,10 @@ Signed-off-by: John Crispin
> arch/mips/pci/pci-ar71xx.c | 81
> +++---
> 1 file changed, 40 insertions(+), 41 deletions(-)
>
> a/arch/mips/pci/pci-ar71xx.c
> -+++ b/arch/mips/pci/pci-ar71xx.c
> +Index: linux-4.14.65/arch/mips/pci/pci-ar71xx.c
> +===
> +--- linux-4.14.65.orig/arch/mips/pci/pci-ar71xx.c
> linux-4.14.65/arch/mips/pci/pci-ar71xx.c
> @@ -18,8 +18,11 @@
> #include
> #include
> @@ -38,89 +40,86 @@ Signed-off-by: John Crispin
> };
>
> /* Byte lane enable bits */
> -@@ -228,29 +232,30 @@ static struct pci_ops ar71xx_pci_ops = {
> +@@ -226,96 +230,6 @@ static struct pci_ops ar71xx_pci_ops = {
> + .write = ar71xx_pci_write_config,
> + };
>
Re: [OpenWrt-Devel] [PATCH] ath79: ar71xx create a separate driver for ar71xx pci interrupt controller.
Performance tests look good too.
вт, 21 авг. 2018 г. в 17:59, Dmitry Tunin :
>
> It is based on Chuanhong Guo work.
>
> PCI interrupt controller is not part of PCI. It is a part of reset controller
> with 0x18060018, 0x1806001c control registers.
>
> This should fix a bug with one IRQ for all PCI devices and also handle the
> PCI_CORE interrupt.
>
> I am not sure that this kind of cascading is good for performance, but this
> way we are more flexible when cofiguring IRQs.
>
> Run tested on DIR-825 B1.
> ---
> target/linux/ath79/dts/ar7100.dtsi | 22 ++-
> ...turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch | 168 -
> .../0036-MIPS-ath79-add-pci-intc.patch | 205
> +
> 3 files changed, 306 insertions(+), 89 deletions(-)
> create mode 100644
> target/linux/ath79/patches-4.14/0036-MIPS-ath79-add-pci-intc.patch
>
> diff --git a/target/linux/ath79/dts/ar7100.dtsi
> b/target/linux/ath79/dts/ar7100.dtsi
> index 8994a7d..6dc1751 100644
> --- a/target/linux/ath79/dts/ar7100.dtsi
> +++ b/target/linux/ath79/dts/ar7100.dtsi
> @@ -96,6 +96,16 @@
> #reset-cells = <1>;
> };
>
> + pci_intc: interrupt-controller@18060018 {
> + compatible = "qca,ar7100-pci-intc";
> + reg = <0x18060018 0x4>;
> + interrupt-parent = <>;
> + interrupts = <2>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> +
> pcie0: pcie-controller@180c {
> compatible = "qca,ar7100-pci";
> #address-cells = <3>;
> @@ -105,14 +115,16 @@
> reg-names = "cfg_base";
> ranges = <0x200 0 0x1000 0x1000 0
> 0x0700/* pci memory */
> 0x100 0 0x 0x000 0
> 0x01>; /* io space */
> - interrupt-parent = <>;
> - interrupts = <2>;
> + interrupt-parent = <_intc>;
> + interrupts = <4>;
>
> - interrupt-controller;
> #interrupt-cells = <1>;
>
> - interrupt-map-mask = <0 0 0 1>;
> - interrupt-map = <0 0 0 0 0>;
> + interrupt-map-mask = <0xf800 0 0 0>;
> + interrupt-map = <0x8800 0 0 0 _intc 1
> +0x9000 0 0 0 _intc 2
> +0x9800 0 0 0 _intc 3>;
> +
> status = "disabled";
> };
> };
> diff --git
> a/target/linux/ath79/patches-4.14/0020-MIPS-ath79-turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch
>
> b/target/linux/ath79/patches-4.14/0020-MIPS-ath79-turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch
> index ea3514a..95ca6d1 100644
> ---
> a/target/linux/ath79/patches-4.14/0020-MIPS-ath79-turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch
> +++
> b/target/linux/ath79/patches-4.14/0020-MIPS-ath79-turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch
> @@ -9,8 +9,10 @@ Signed-off-by: John Crispin
> arch/mips/pci/pci-ar71xx.c | 81
> +++---
> 1 file changed, 40 insertions(+), 41 deletions(-)
>
> a/arch/mips/pci/pci-ar71xx.c
> -+++ b/arch/mips/pci/pci-ar71xx.c
> +Index: linux-4.14.65/arch/mips/pci/pci-ar71xx.c
> +===
> +--- linux-4.14.65.orig/arch/mips/pci/pci-ar71xx.c
> linux-4.14.65/arch/mips/pci/pci-ar71xx.c
> @@ -18,8 +18,11 @@
> #include
> #include
> @@ -38,89 +40,86 @@ Signed-off-by: John Crispin
> };
>
> /* Byte lane enable bits */
> -@@ -228,29 +232,30 @@ static struct pci_ops ar71xx_pci_ops = {
> +@@ -226,96 +230,6 @@ static struct pci_ops ar71xx_pci_ops = {
> + .write = ar71xx_pci_write_config,
> + };
>
> - static void ar71xx_pci_irq_handler(struct irq_desc *desc)
> - {
> +-static void ar71xx_pci_irq_handler(struct irq_desc *desc)
> +-{
> - struct ar71xx_pci_controller *apc;
> - void __iomem *base = ath79_reset_base;
> -+ struct irq_chip *chip = irq_desc_get_chip(desc);
> -+ struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);
> - u32 pending;
> -
> +- void __iomem *base = ath79_reset_base;
> +- u32 pending;
> +-
> - apc = irq_desc_get_handler_data(desc);
> -
> -+ chained_irq_enter(chip, desc);
> - pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
> - __raw_readl(base +
[OpenWrt-Devel] [PATCH] ath79: ar71xx create a separate driver for ar71xx pci interrupt controller.
It is based on Chuanhong Guo work.
PCI interrupt controller is not part of PCI. It is a part of reset controller
with 0x18060018, 0x1806001c control registers.
This should fix a bug with one IRQ for all PCI devices and also handle the
PCI_CORE interrupt.
I am not sure that this kind of cascading is good for performance, but this way
we are more flexible when cofiguring IRQs.
Run tested on DIR-825 B1.
---
target/linux/ath79/dts/ar7100.dtsi | 22 ++-
...turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch | 168 -
.../0036-MIPS-ath79-add-pci-intc.patch | 205 +
3 files changed, 306 insertions(+), 89 deletions(-)
create mode 100644
target/linux/ath79/patches-4.14/0036-MIPS-ath79-add-pci-intc.patch
diff --git a/target/linux/ath79/dts/ar7100.dtsi
b/target/linux/ath79/dts/ar7100.dtsi
index 8994a7d..6dc1751 100644
--- a/target/linux/ath79/dts/ar7100.dtsi
+++ b/target/linux/ath79/dts/ar7100.dtsi
@@ -96,6 +96,16 @@
#reset-cells = <1>;
};
+ pci_intc: interrupt-controller@18060018 {
+ compatible = "qca,ar7100-pci-intc";
+ reg = <0x18060018 0x4>;
+ interrupt-parent = <>;
+ interrupts = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+
pcie0: pcie-controller@180c {
compatible = "qca,ar7100-pci";
#address-cells = <3>;
@@ -105,14 +115,16 @@
reg-names = "cfg_base";
ranges = <0x200 0 0x1000 0x1000 0
0x0700/* pci memory */
0x100 0 0x 0x000 0
0x01>; /* io space */
- interrupt-parent = <>;
- interrupts = <2>;
+ interrupt-parent = <_intc>;
+ interrupts = <4>;
- interrupt-controller;
#interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 1>;
- interrupt-map = <0 0 0 0 0>;
+ interrupt-map-mask = <0xf800 0 0 0>;
+ interrupt-map = <0x8800 0 0 0 _intc 1
+0x9000 0 0 0 _intc 2
+0x9800 0 0 0 _intc 3>;
+
status = "disabled";
};
};
diff --git
a/target/linux/ath79/patches-4.14/0020-MIPS-ath79-turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch
b/target/linux/ath79/patches-4.14/0020-MIPS-ath79-turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch
index ea3514a..95ca6d1 100644
---
a/target/linux/ath79/patches-4.14/0020-MIPS-ath79-turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch
+++
b/target/linux/ath79/patches-4.14/0020-MIPS-ath79-turn-pci-ar71xx-driver-into-a-pure-OF-dri.patch
@@ -9,8 +9,10 @@ Signed-off-by: John Crispin
arch/mips/pci/pci-ar71xx.c | 81 +++---
1 file changed, 40 insertions(+), 41 deletions(-)
a/arch/mips/pci/pci-ar71xx.c
-+++ b/arch/mips/pci/pci-ar71xx.c
+Index: linux-4.14.65/arch/mips/pci/pci-ar71xx.c
+===
+--- linux-4.14.65.orig/arch/mips/pci/pci-ar71xx.c
linux-4.14.65/arch/mips/pci/pci-ar71xx.c
@@ -18,8 +18,11 @@
#include
#include
@@ -38,89 +40,86 @@ Signed-off-by: John Crispin
};
/* Byte lane enable bits */
-@@ -228,29 +232,30 @@ static struct pci_ops ar71xx_pci_ops = {
+@@ -226,96 +230,6 @@ static struct pci_ops ar71xx_pci_ops = {
+ .write = ar71xx_pci_write_config,
+ };
- static void ar71xx_pci_irq_handler(struct irq_desc *desc)
- {
+-static void ar71xx_pci_irq_handler(struct irq_desc *desc)
+-{
- struct ar71xx_pci_controller *apc;
- void __iomem *base = ath79_reset_base;
-+ struct irq_chip *chip = irq_desc_get_chip(desc);
-+ struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);
- u32 pending;
-
+- void __iomem *base = ath79_reset_base;
+- u32 pending;
+-
- apc = irq_desc_get_handler_data(desc);
-
-+ chained_irq_enter(chip, desc);
- pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
- __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-
- if (pending & AR71XX_PCI_INT_DEV0)
+- pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
+-__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+-
+- if (pending & AR71XX_PCI_INT_DEV0)
-
Re: [OpenWrt-Devel] [PATCH v2] build: add mkrasimage
Hi, On 8/21/18 8:31 AM, Stefan Lippers-Hollmann wrote: > While this passes the version check, the appended git hash does break > later on in the flashing process - so at the moment only the numerical > revision (of DISTRIB_REVISION='r7890-40eb9bda44') seems to be safe: > > RAS_VERSION := "V1.99(OWRT.$$(shell echo $(REVISION) | sed -e s/^r// -e > s/\\-.*//))C0" Does the version string contained in the RAS-header get exposed to a user in any way? If not, i would go for using a static (high enough so it probably never get's used by ZyXEL) version string and call it a day before we are over-complicating things here. The NBG6617 btw. does not have such a validation (Downgrades using older ZyXEL-firmware are also possible using the Web-UI) Best wishes David ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] [PATCH v3] ath79: ag71xx: apply interface mode to MII0/1_CTRL on ar71xx/ar913x
We currently don't have any code configuring interface mode in ath79,
meaning that we relies on bootloader to set the correct interface mode.
This patch added code to set interface correctly so that everything works
even if bootloader configures it wrong.(e.g. on WNDR3800 u-boot set
the second GMAC mode to RMII but it should be RGMII.)
Introduced "qca,mac-idx" for the difference in MII_CTRL register value.
Signed-off-by: Chuanhong Guo
---
v2-v3: Changed dt binding
target/linux/ath79/dts/ar7100.dtsi| 2 +
target/linux/ath79/dts/ar9132.dtsi| 1 +
.../net/ethernet/atheros/ag71xx/ag71xx_main.c | 64 ++-
3 files changed, 66 insertions(+), 1 deletion(-)
diff --git a/target/linux/ath79/dts/ar7100.dtsi
b/target/linux/ath79/dts/ar7100.dtsi
index 8994a7d688..6402657841 100644
--- a/target/linux/ath79/dts/ar7100.dtsi
+++ b/target/linux/ath79/dts/ar7100.dtsi
@@ -182,6 +182,7 @@
resets = < 9>;
reset-names = "mac";
+ qca,mac-idx = <0>;
};
{
@@ -201,4 +202,5 @@
resets = < 13>;
reset-names = "mac";
+ qca,mac-idx = <1>;
};
diff --git a/target/linux/ath79/dts/ar9132.dtsi
b/target/linux/ath79/dts/ar9132.dtsi
index 9d8ddcf9ba..2264994279 100644
--- a/target/linux/ath79/dts/ar9132.dtsi
+++ b/target/linux/ath79/dts/ar9132.dtsi
@@ -193,4 +193,5 @@
pll-handle = <>;
resets = < 9>;
reset-names = "mac";
+ qca,mac-idx = <0>;
};
diff --git
a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
index 1e0bb6937f..7f64a65817 100644
--- a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
+++ b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
@@ -529,6 +529,60 @@ static void ath79_set_pll(struct ag71xx *ag)
udelay(100);
}
+static void ath79_mii_ctrl_set_if(struct ag71xx *ag, unsigned int mii_if)
+{
+ u32 t;
+
+ t = __raw_readl(ag->mii_base);
+ t &= ~(AR71XX_MII_CTRL_IF_MASK);
+ t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
+ __raw_writel(t, ag->mii_base);
+}
+
+static void ath79_mii0_ctrl_set_if(struct ag71xx *ag)
+{
+ unsigned int mii_if;
+
+ switch (ag->phy_if_mode) {
+ case PHY_INTERFACE_MODE_MII:
+ mii_if = AR71XX_MII0_CTRL_IF_MII;
+ break;
+ case PHY_INTERFACE_MODE_GMII:
+ mii_if = AR71XX_MII0_CTRL_IF_GMII;
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ mii_if = AR71XX_MII0_CTRL_IF_RGMII;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ mii_if = AR71XX_MII0_CTRL_IF_RMII;
+ break;
+ default:
+ WARN(1, "Impossible PHY mode defined.\n");
+ return;
+ }
+
+ ath79_mii_ctrl_set_if(ag, mii_if);
+}
+
+static void ath79_mii1_ctrl_set_if(struct ag71xx *ag)
+{
+ unsigned int mii_if;
+
+ switch (ag->phy_if_mode) {
+ case PHY_INTERFACE_MODE_RMII:
+ mii_if = AR71XX_MII1_CTRL_IF_RMII;
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ mii_if = AR71XX_MII1_CTRL_IF_RGMII;
+ break;
+ default:
+ WARN(1, "Impossible PHY mode defined.\n");
+ return;
+ }
+
+ ath79_mii_ctrl_set_if(ag, mii_if);
+}
+
static void ath79_mii_ctrl_set_speed(struct ag71xx *ag)
{
unsigned int mii_speed;
@@ -1272,7 +1326,7 @@ static int ag71xx_probe(struct platform_device *pdev)
struct resource *res;
struct ag71xx *ag;
const void *mac_addr;
- u32 max_frame_len;
+ u32 max_frame_len, mac_idx;
int tx_size, err;
if (!np)
@@ -1427,6 +1481,14 @@ static int ag71xx_probe(struct platform_device *pdev)
goto err_free;
}
+ if ((ag->mii_base) &&
+ (!of_property_read_u32(np, "qca,mac-idx", _idx))) {
+ if (mac_idx == 0)
+ ath79_mii0_ctrl_set_if(ag);
+ else if (mac_idx == 1)
+ ath79_mii1_ctrl_set_if(ag);
+ }
+
netif_napi_add(dev, >napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);
--
2.17.1
___
openwrt-devel mailing list
openwrt-devel@lists.openwrt.org
https://lists.openwrt.org/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] [PATCH 0/1] ubus/lua: add support for BLOBMSG_TYPE_DOUBLE
From: Marcus Comstedt Hi. I noticed that using luci.util.ubus() does not work correctly when the called function returned doubles (only nils are returned). This patch adds the capability of correctly forwarding BLOBMSG_TYPE_DOUBLE to lua. It is still not possible to send parameters of type BLOBMSG_TYPE_DOUBLE from lua, but this is the same as with parameters of type BLOBMSG_TYPE_INT16 and BLOBMSG_TYPE_INT64, so I consider it a separate issue. I could not find a GitHub mirror of ubus.git to file a PR against, so I'm sending the patch to the list instead. I hope that was the right thing to do. :-) // Marcus Marcus Comstedt (1): ubus/lua: add support for BLOBMSG_TYPE_DOUBLE lua/ubus.c | 13 + 1 file changed, 13 insertions(+) -- 2.16.4 ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] [PATCH 1/1] ubus/lua: add support for BLOBMSG_TYPE_DOUBLE
From: Marcus Comstedt
Signed-off-by: Marcus Comstedt
---
lua/ubus.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/lua/ubus.c b/lua/ubus.c
index 00d9e00..4da3c80 100644
--- a/lua/ubus.c
+++ b/lua/ubus.c
@@ -111,6 +111,17 @@ ubus_lua_parse_blob(lua_State *L, struct blob_attr *attr,
bool table)
lua_pushnumber(L, (double) be64_to_cpu(*(uint64_t *)data));
break;
+ case BLOBMSG_TYPE_DOUBLE:
+ {
+ union {
+ double d;
+ uint64_t u64;
+ } v;
+ v.u64 = be64_to_cpu(*(uint64_t *)data);
+ lua_pushnumber(L, v.d);
+ }
+ break;
+
case BLOBMSG_TYPE_STRING:
lua_pushstring(L, data);
break;
@@ -982,6 +993,8 @@ luaopen_ubus(lua_State *L)
lua_setfield(L, -2, "INT16");
lua_pushinteger(L, BLOBMSG_TYPE_INT8);
lua_setfield(L, -2, "INT8");
+ lua_pushinteger(L, BLOBMSG_TYPE_DOUBLE);
+ lua_setfield(L, -2, "DOUBLE");
lua_pushinteger(L, BLOBMSG_TYPE_BOOL);
lua_setfield(L, -2, "BOOLEAN");
--
2.16.4
___
openwrt-devel mailing list
openwrt-devel@lists.openwrt.org
https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] [PATCH v2] ath79: ag71xx: apply interface mode to MII0/1_CTRL on ar71xx/ar913x
On 19/08/18 12:48, Chuanhong Guo wrote:
We currently don't have any code configuring interface mode in ath79,
meaning that we relies on bootloader to set the correct interface mode.
This patch added code to set interface correctly so that everything works
even if bootloader configures it wrong.(e.g. on WNDR3800 u-boot set
the second GMAC mode to RMII but it should be RGMII.)
Signed-off-by: Chuanhong Guo
Hi,
sorry I am late for the party and am aware that you've sent more than
one version of this patch. please make the binding look as follows
inside the ethX {} node add a property qca,mac-idx = <0 or 1>; and
derive the mii register from that. This is how we solved the problem
updtream for the MTK binding.
John
---
Resend to add commit message.
target/linux/ath79/dts/ar7100.dtsi| 4 +-
target/linux/ath79/dts/ar9132.dtsi| 2 +-
.../net/ethernet/atheros/ag71xx/ag71xx_main.c | 102 +++---
3 files changed, 92 insertions(+), 16 deletions(-)
diff --git a/target/linux/ath79/dts/ar7100.dtsi
b/target/linux/ath79/dts/ar7100.dtsi
index 8994a7d688..bb3c10bdc5 100644
--- a/target/linux/ath79/dts/ar7100.dtsi
+++ b/target/linux/ath79/dts/ar7100.dtsi
@@ -171,7 +171,7 @@
};
{
- compatible = "qca,ar7100-eth";
+ compatible = "qca,ar7100-mii0-eth";
reg = <0x1900 0x200
0x1807 0x4>;
@@ -189,7 +189,7 @@
};
{
- compatible = "qca,ar7100-eth";
+ compatible = "qca,ar7100-mii1-eth";
reg = <0x1a00 0x200
0x18070004 0x4>;
diff --git a/target/linux/ath79/dts/ar9132.dtsi b/target/linux/ath79/dts/ar9132.dtsi
index 9d8ddcf9ba..bf5e9c06fa 100644
--- a/target/linux/ath79/dts/ar9132.dtsi
+++ b/target/linux/ath79/dts/ar9132.dtsi
@@ -185,7 +185,7 @@
};
{
- compatible = "qca,ar9130-eth", "syscon";
+ compatible = "qca,ar9130-mii0-eth", "syscon";
reg = <0x1900 0x200
0x1807 0x4>;
pll-data = <0x1a00 0x13000a44 0x00441099>;
diff --git
a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
index 1e0bb6937f..72c6673037 100644
--- a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
+++ b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
@@ -529,6 +529,60 @@ static void ath79_set_pll(struct ag71xx *ag)
udelay(100);
}
+static void ath79_mii_ctrl_set_if(struct ag71xx *ag, unsigned int mii_if)
+{
+ u32 t;
+
+ t = __raw_readl(ag->mii_base);
+ t &= ~(AR71XX_MII_CTRL_IF_MASK);
+ t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
+ __raw_writel(t, ag->mii_base);
+}
+
+static void ath79_mii0_ctrl_set_if(struct ag71xx *ag)
+{
+ unsigned int mii_if;
+
+ switch (ag->phy_if_mode) {
+ case PHY_INTERFACE_MODE_MII:
+ mii_if = AR71XX_MII0_CTRL_IF_MII;
+ break;
+ case PHY_INTERFACE_MODE_GMII:
+ mii_if = AR71XX_MII0_CTRL_IF_GMII;
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ mii_if = AR71XX_MII0_CTRL_IF_RGMII;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ mii_if = AR71XX_MII0_CTRL_IF_RMII;
+ break;
+ default:
+ WARN(1, "Impossible PHY mode defined.\n");
+ return;
+ }
+
+ ath79_mii_ctrl_set_if(ag, mii_if);
+}
+
+static void ath79_mii1_ctrl_set_if(struct ag71xx *ag)
+{
+ unsigned int mii_if;
+
+ switch (ag->phy_if_mode) {
+ case PHY_INTERFACE_MODE_RMII:
+ mii_if = AR71XX_MII1_CTRL_IF_RMII;
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ mii_if = AR71XX_MII1_CTRL_IF_RGMII;
+ break;
+ default:
+ WARN(1, "Impossible PHY mode defined.\n");
+ return;
+ }
+
+ ath79_mii_ctrl_set_if(ag, mii_if);
+}
+
static void ath79_mii_ctrl_set_speed(struct ag71xx *ag)
{
unsigned int mii_speed;
@@ -573,8 +627,10 @@ __ag71xx_link_adjust(struct ag71xx *ag, bool update)
return;
}
- if (!of_device_is_compatible(np, "qca,ar9130-eth") &&
- !of_device_is_compatible(np, "qca,ar7100-eth"))
+ if (!of_device_is_compatible(np, "qca,ar9130-mii0-eth") &&
+ !of_device_is_compatible(np, "qca,ar9132-mii1-eth") &&
+ !of_device_is_compatible(np, "qca,ar7100-mii0-eth") &&
+ !of_device_is_compatible(np, "qca,ar7100-mii1-eth"))
ag71xx_fast_reset(ag);
cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
@@ -612,8 +668,10 @@ __ag71xx_link_adjust(struct ag71xx *ag, bool update)
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]);
if (update) {
- if (of_device_is_compatible(np, "qca,ar7100-eth") ||
- of_device_is_compatible(np,
Re: [OpenWrt-Devel] [PATCH v2] build: add mkrasimage
Hi On 2018-08-21, Jo-Philipp Wich wrote: > Hi, > > > RAS_VERSION := "V1.99(OWRT.$$(shell echo $(REVISION) | sed s/^r//))C0" While this passes the version check, the appended git hash does break later on in the flashing process - so at the moment only the numerical revision (of DISTRIB_REVISION='r7890-40eb9bda44') seems to be safe: RAS_VERSION := "V1.99(OWRT.$$(shell echo $(REVISION) | sed -e s/^r// -e s/\\-.*//))C0" # hexdump -C /dev/mmcblk0p6 00 00 b4 bc 01 47 18 00 56 31 2e 39 39 28 4f 57 |.G..V1.99(OW| 0010 52 54 2e 37 38 39 30 29 43 30 00 ff ff ff ff ff |RT.7890)C0..| 0020 ff ff ff ff ff ff ff ff 00 00 d4 1d 4e 42 47 36 |NBG6| 0030 38 31 37 00 ff ff ff ff ff ff ff ff ff ff ff ff |817.| 0040 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff || * 0060 ff ff ff ff ff ff ff ff ff ff ff ff 00 00 98 e5 || 0070 00 40 00 00 ff ff ff ff ff ff ff ff ff ff ff ff |.@..| 0080 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff || * 0001 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 || * 0010 > make that RAS_VERSION := "V1.99(OWRT.$(patsubst r%,%,$(REVISION)))C0" > to avoid spawning a shell + sed process. I'll have a look at improving this tonight, thanks. Regards Stefan Lippers-Hollmann ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] [PATCH v2] build: add mkrasimage
Hi, > RAS_VERSION := "V1.99(OWRT.$$(shell echo $(REVISION) | sed s/^r//))C0" make that RAS_VERSION := "V1.99(OWRT.$(patsubst r%,%,$(REVISION)))C0" to avoid spawning a shell + sed process. ~ Jo signature.asc Description: OpenPGP digital signature ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] [PATCH v2] build: add mkrasimage
On 2018-08-21, Stefan Lippers-Hollmann wrote: > Hi > > On 2018-08-21, Stefan Lippers-Hollmann wrote: > > On 2018-08-20, David Bauer wrote: > [...] > > For now, I've supplied a valid/ future firmware version for testing > > > > RAS_VERSION := "V1.00(ABCS.9)C0" > > While perhaps not ideal yet, this is accepted by the OEM webinterface > and should be safe to use for the time being. > > RAS_VERSION := "V1.99(OWRT.7890)C0" Sorry, this was meant to read: RAS_VERSION := "V1.99(OWRT.$$(shell echo $(REVISION) | sed s/^r//))C0" # hexdump -C /dev/mmcblk0p3 00 00 c4 38 01 47 18 00 56 31 2e 39 39 28 4f 57 |...8.G..V1.99(OW| 0010 52 54 2e 37 38 39 30 2d 34 30 65 62 39 62 64 61 |RT.7890-40eb9bda| 0020 34 34 29 43 30 00 ff ff 00 00 cb 60 4e 42 47 36 |44)C0..`NBG6| 0030 38 31 37 00 ff ff ff ff ff ff ff ff ff ff ff ff |817.| 0040 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff || * 0060 ff ff ff ff ff ff ff ff ff ff ff ff 00 00 98 e5 || 0070 00 40 00 00 ff ff ff ff ff ff ff ff ff ff ff ff |.@..| 0080 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff || * 0001 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 || * 0010 Regards Stefan Lippers-Hollmann pgpUy1INt3ylP.pgp Description: Digitale Signatur von OpenPGP ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
