[PEDA] Boardmaker to Protel
Hello to the Protel Forum List! I have just joined this list and have my first query. We have a huge number of PCB designs in Boardmaker (an old DOS package written by Tsien of Cambridge, UK) and require to import them somehow into Protel. It has been suggested that the Gerbers generated by Boardmaker can be imported via Camtastic. How can this method recover the connectivity between layers? How can the plot of a pad on one layer relate to an identically positioned plot of a pad on another layer? (or is Camtastic so fantastic that is knows that such instances are vias?). Any suggestions on how to tackle this problem and any general solutions to importing designs into Protel from nothing but Gerbers would be very much appreciated. Best Regards, Ivor Davies Diplomat UK Ltd * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Snap to metric Grid
I'm making a pcb file containing all the footprints of a specific PCB so that it can be exported into AutoCAD as a DWG file. The footprints are on a 20mil grid and I wish to snap them to a 0.1mm grid before I export the file. Is there a way to do this? I tried selecting all the foot prints after changing the grid and using the "Move to Grid" function but this seem to do nothing. Tim Fifield, CET International Rectifier - EMS Canada * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] TO3 footprint
Good Morning! I have a TO3 schematic part with pins 1, 2, 3. The TO3 footprint has pins 1, 2, and two pin 3's. I thought this would work but the pin 3's do not have netnames in the layout. Do I have to use a schematic and footprint pin 3A and pin 3B? Regards, Jeff Adolphs www.lakeshore.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Snap to metric Grid
Tim, I played a little with the move to grid feature. I discovered that the minimal "move to" grid Protel can handle is 5 mils = 0.127mm. Regards Ben Uijtenhaak [EMAIL PROTECTED] Gatsometer BV P.O. Box 4959 2003EZ Haarlem The Netherlands phone : +31 23 5255050 fax : +31 23 5276961 -Original Message- From: Tim Fifield <[EMAIL PROTECTED]> To: Protel EDA Form <[EMAIL PROTECTED]> Date: donderdag 23 mei 2002 15:31 Subject: [PEDA] Snap to metric Grid >I'm making a pcb file containing all the footprints of a specific PCB so >that it can be exported into AutoCAD as a DWG file. The footprints are on a >20mil grid and I wish to snap them to a 0.1mm grid before I export the file. >Is there a way to do this? I tried selecting all the foot prints after >changing the grid and using the "Move to Grid" function but this seem to do >nothing. > >Tim Fifield, CET >International Rectifier - EMS Canada > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Boardmaker to Protel
Ivor Davies wrote: > ... We have a huge number of PCB designs in Boardmaker and require to import > them somehow into Protel. > It has been suggested that the Gerbers generated by Boardmaker can be imported > via Camtastic. I don't feel strong enough to give you suggestions, except general ones. There were many posts about importing designs to Protel through Gerber files and you may find them either in this forum's archive or (I think more easily) in the mail archive of the forum on: http://www.mail-archive.com/proteledaforum%40techservinc.com/ > Any suggestions on how to tackle this problem and any general solutions to > importing designs into Protel from nothing but Gerbers Is it possible to export your designs in any other format (e.g. ASCII) that could be read by other EDA software (OrCAD, Cadstar, PADS, Tango, etc.)? What I mean is: If you are going to import from your software to Protel with 2 intermediate steps (Gerbers and Camtastic), maybe it's possible to do it another way with 2 or 3 intermediate steps to gain your design with all "knowledge" about logical connections, components etc., which you won't have with Gerber. Protel can directly import very few formats, but there are "third party importers" - starting from freeware up to quite expensive utilities. If you have huge number of PCB's, as you said, maybe it will be reasonable to pay the author of such importer to modify it so, that it will read the format that your old software may produce. Wojciech Oborski * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Autopan in PCB (99SE)
> -Original Message- > From: Terry Creer [mailto:[EMAIL PROTECTED]] > Sent: Wednesday, May 22, 2002 10:32 PM > To: 'Protel EDA Forum' > Subject: Re: [PEDA] Autopan in PCB (99SE) > > > Hmmm, I think you had a bit more success than I, Tom. No go > unfortunately. > Strange, it didn't do it before on the ol' PII 350, now it > seems to get > carried away with the P4 1.6GHz. When it gets stuck, it even > freezes the > system temporarily. I wonder if the Altium chappies know > about this. Altium is aware of this flaw in their software, and they have been aware of it for a very, very long time. Their idea of a repair is to periodically (at the user price of a software upgrade expenditure) increase a fixed divisor value to slow down the flawed panning routine originally devloped back in the late 1980's, but integrated into the Windows product to increase profit margins (reduce development costs). I've been waiting for this problem to rear its head again, as it confirms my suspicions regarding Protel/Altium's motivations for not actually fixing the problem. It's one more clever way for them to strong-arm users into "upgrading" the product. I wonder about Phoenix... aj * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 3D VIEW USING RADEON7000
> -Original Message- > From: Tony Karavidas [mailto:[EMAIL PROTECTED]] > Sent: Wednesday, May 22, 2002 1:09 PM > To: Protel EDA Forum > Subject: Re: [PEDA] 3D VIEW USING RADEON7000 > > > Not at all. However, if Protel is using an aspect of OpenGL > that is not > common or often correctly implemented, then it could be > pointed out that the > flaw is in OpenGL as opposed to Protel code. I would argue that as history shows, it is Protel's use of archane coding, not hardware, at the core of any problems. (note the re-emergent "Pan" thread...) Unless of course, you subcribe to the notion that we should also have to purchase our computers systems from Protel, sans CADAM that is... aj * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Clearance between VIA and power plane (split plane) tr ack
Juha, I think that in order for anybody to help you they must give a few more details to your problem. You do not mention the size of the via (pad and hole), width of the split plane line, are you measuring these distances from the edge or the center of that pad/via, etc., etc.. Then somebody may be able to figure out what may be happening to you. Further to those issues, it almost seems as though your described problem may be a bug. In which case someone may say, just move your via to some point other then 3.6mils or 13.12 mils. Why would your via need to be precisely at those locations? Move them slightly and your problem will go away as you had stated in your earlier post. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com Visit us at Booth 2G2-09 at CommunicAsia 2002 in Singapore June 18-21. > -Original Message- > From: Juha Pajunen [mailto:[EMAIL PROTECTED]] > Sent: Wednesday, May 22, 2002 10:15 PM > To: Protel EDA Forum > Subject: [PEDA] Clearance between VIA and power plane (split plane) > track > > > Hi, > > Can anyone help me with my clearance problem. > Clearance between VIA and power plane (split plane) > track (primitive). If I place a VIA to split plane, > it connects to plane and there is a relief. When I move > that VIA near green track wich is part of defined > split plane, DRC gives a short-circuit error. > When the distance between the VIA and the power plane track > (track is vertical) is 3.6mil, DRC does not give a > short-circuit error. Clearance rule for whole board is 7mil. > > Then there is a track on power plane wich is rotated 45 degree, > if distance between the VIA and the power plane track is 13.12mil, > DRC does not give a short-circuit error. > > If I change the VIA with same size PAD there is NO DRC error. > > What are those distances (3.6 and 13.12mil), where those > are from and how to control them? > Why VIA and PAD does not act same way? > > Hope You can understand what I mean! > > I can send You a *.GIF, if you like to see more... > > Thank you... > > Sincerely, > Juha Pajunen, Hw Engineer > Bitboys Oy > E-mail: [EMAIL PROTECTED] > > NOTE: This message, and any attached files, may contain > privileged or confidential information. It is intended for > use only by the > designated recipients. Any disclosure, copying or distribution of, or > reliance upon, this message by anyone else is strictly prohibited. > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] PICK AND PLACE FILE FROM GERBER
Re: [PEDA] Boardmaker to Protel
- Original Message - From: "Ivor Davies" <[EMAIL PROTECTED]> To: "Protel Forum Ask (E-mail)" <[EMAIL PROTECTED]> Sent: Thursday, May 23, 2002 5:47 AM Subject: [PEDA] Boardmaker to Protel Hello to the Protel Forum List! I have just joined this list and have my first query. We have a huge number of PCB designs in Boardmaker (an old DOS package written by Tsien of Cambridge, UK) and require to import them somehow into Protel. It has been suggested that the Gerbers generated by Boardmaker can be imported via Camtastic. How can this method recover the connectivity between layers? How can the plot of a pad on one layer relate to an identically positioned plot of a pad on another layer? (or is Camtastic so fantastic that is knows that such instances are vias?). Any suggestions on how to tackle this problem and any general solutions to importing designs into Protel from nothing but Gerbers would be very much appreciated. Best Regards, Ivor Davies Diplomat UK Ltd ___ Ivor, I actually enjoy converting gerbers to Protel. Something different from normal everyday design. There are a few issues that need to be considered here. Do you have a new netlist? Will you create a library of parts from the design or use your new library? Does it need to match exactly? Is it multilayer? It is a very daunting task if your not use to this. I've done it many times so I'll mention some things here: Netlist: If you need to create one from the gerbers: I don't know if you'll have success here. There are too many issues with this because of the lack of intelligence of the gerber data itself. There are no reference designators and pin numbers. A CAM package may be able to do this but it would be pretty extensive work. Not a reasonable method. Creating a schematic would probably be better. If you have a netlist: You'll save a huge amount of work. You can load it like any other job after taking care of the library and placing the parts. See below. Library: It greatly helps to have a bill of material and data sheets to verify pinouts and names of packages. Import the gerber data into Protel (may have to use version 2.8). Now you would start to make the footprints. You have to select the entities that make up one package at a time. Copy and paste into the library. Here you will have to give it pin numbers. Use datasheets and /or netlist/schematic to make pinouts correctly (beware of polarization). Exact match: It is a great help to have films to look at. Now you may want to move the gerber data to reference layers. When parts are made place them over the footprint that they represent. You'll play around with moving the routes from the reference layers to their intended layer. Soldermask, pastes and so fourth can be compared to on your new component for a match. You may have to go back to the library part to adjust things or modify rules. You may have a silkscreen problem because of a different font type or size was used. You may have to decide if that is something that can be different from the old design or you will have to use the reference layer for silk and just add new changes. Multi layer: You will need to know what nets are internal if that applies. Are the thermals necessary to be of exact match, size and type? Hopefully Protel provides the type of thermals used. You should be able to address these issues. I think this sound much harder than it is. If you have a lot of experience as a designer and with Protel it should get a lot easier as you start to get into it. I'm sure I left some serious issues out, but I've gotten interrupted many times while writing this and it probably makes no sense at all. Good luck! If not send that work to me.. like I said I like to do this kind of stuff. Bob Jones Digitized Technologies 2 Summit Road P.O.Box 7284 Prospect, CT. 06712-1541 Tel: 203-758-6312 Fax: 203-758-3338 email: [EMAIL PROTECTED] [EMAIL PROTECTED] web: http://www.digitizedtechnologies.com Notice: This message is intended solely for the person to whom it is addressed. Unintended recipients will be legally responsible for unauthorized use, disclosure, copying or distribution. If you have received this message in error, please notify the sender immediately by replying to this message. Then delete this message from your system. Thank you. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] PICK AND PLACE FILE FROM GERBER
Re: [PEDA] Boardmaker to Protel
Ivor, There is a company called Router Solutions Inc. in Southern California (Anaheim I think) that, in times past, has been very successful with format conversions and they may already have something that works or can possibly whip one up in short order. I'm not familiar with Boardmaker at all though so I'm guessing though. They also have a very good and very enhanced Gerber editor caled CadCam that may be of use too. I have had several clients over the last 10 years or so that have used their products and services successfully and I have heard no complaints. I don't have their "address" handy but a quick search for "RSI", CADCAM (one word), or "Router Solutions Inc." should get you there. Best Regards - Evan Scarborough www.e-cadds.com >From: "Ivor Davies" <[EMAIL PROTECTED]> >Reply-To: "Protel EDA Forum" <[EMAIL PROTECTED]> >To: "Protel Forum Ask (E-mail)" <[EMAIL PROTECTED]> >Subject: [PEDA] Boardmaker to Protel >Date: Thu, 23 May 2002 10:47:37 +0100 > >Hello to the Protel Forum List! > >I have just joined this list and have my first query. We have a huge number >of PCB designs in Boardmaker (an old DOS package written by Tsien of >Cambridge, UK) and require to import them somehow into Protel. > >It has been suggested that the Gerbers generated by Boardmaker can be >imported via Camtastic. How can this method recover the connectivity >between layers? How can the plot of a pad on one layer relate to an >identically positioned plot of a pad on another layer? (or is Camtastic so >fantastic that is knows that such instances are vias?). > >Any suggestions on how to tackle this problem and any general solutions to >importing designs into Protel from nothing but Gerbers would be very much >appreciated. > >Best Regards, >Ivor Davies >Diplomat UK Ltd _ Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Re[2]: Boardmaker to Protel
RSI can be found here: http://rsi-inc.com/default.htm ---Phil ES> Ivor, ES> There is a company called Router Solutions Inc. in Southern California ES> (Anaheim I think) that, in times past, has been very successful with format ES> conversions and they may already have something that works or can possibly ES> whip one up in short order. I'm not familiar with Boardmaker at all though ES> so I'm guessing though. ES> They also have a very good and very enhanced Gerber editor caled CadCam that ES> may be of use too. I have had several clients over the last 10 years or so ES> that have used their products and services successfully and I have heard no ES> complaints. ES> I don't have their "address" handy but a quick search for "RSI", CADCAM (one ES> word), or "Router Solutions Inc." should get you there. ES> Best Regards - Evan Scarborough ES> www.e-cadds.com >>From: "Ivor Davies" <[EMAIL PROTECTED]> >>Reply-To: "Protel EDA Forum" <[EMAIL PROTECTED]> >>To: "Protel Forum Ask (E-mail)" <[EMAIL PROTECTED]> >>Subject: [PEDA] Boardmaker to Protel >>Date: Thu, 23 May 2002 10:47:37 +0100 >> >>Hello to the Protel Forum List! >> >>I have just joined this list and have my first query. We have a huge number >>of PCB designs in Boardmaker (an old DOS package written by Tsien of >>Cambridge, UK) and require to import them somehow into Protel. >> >>It has been suggested that the Gerbers generated by Boardmaker can be >>imported via Camtastic. How can this method recover the connectivity >>between layers? How can the plot of a pad on one layer relate to an >>identically positioned plot of a pad on another layer? (or is Camtastic so >>fantastic that is knows that such instances are vias?). >> >>Any suggestions on how to tackle this problem and any general solutions to >>importing designs into Protel from nothing but Gerbers would be very much >>appreciated. >> >>Best Regards, >>Ivor Davies >>Diplomat UK Ltd ES> _ ES> Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Gerber to Protel, was Boardmaker to Protel
At 10:47 AM 5/23/2002 +0100, Ivor Davies wrote: >I have just joined this list and have my first query. We have a huge >number of PCB designs in Boardmaker (an old DOS package written by Tsien >of Cambridge, UK) and require to import them somehow into Protel. BTW, there is a much newer version of Boardmaker. I do know that Boardmaker was interested in writing a Protel translator, but I think CAD companies generally avoid providing translators that translate *from* their own packages. It appears there may be legal issues with writing a proprietary file format; but there would be no such issue if the translator were a Protel server >It has been suggested that the Gerbers generated by Boardmaker can be >imported via Camtastic. How can this method recover the connectivity >between layers? There is a lot of hand work involved, it is not just a matter of doing an import and then being done. > How can the plot of a pad on one layer relate to an identically > positioned plot of a pad on another layer? (or is Camtastic so fantastic > that is knows that such instances are vias?). No, Protel is that fantastic, or, rather, a skilled designer driving Protel. Global edits make a lot of things possible. Here is a general procedure: Bring the gerber into CAMtastic; this step could be skipped if the gerber is compatible with Protel. CAMtastic output can be made compatible. (There are some tools in CAMtastic that might assist in the process, I have not explored them.) Bring in the gerber to Protel. You would ideally want to also bring in the drill data. I wrote a Tango utility that would import a drill file, looking for pads at the drill location. If it found a pad, it converted the pad (which starts out as a surface pad, being brought in from Gerber) into a through-pad with the appropriate hole. Since it is possible to import Tango to Protel, there might be a path to use here, but I'll assume that Tango is not available and one will manually deal with hole sizes. Visually identify footprints and create these footprints in Protel. You can select the pads of a footprint and copy them into a library footprint. Create a footprint for all different components on the board. If the footprint contains through pads, assign the pads the appropriate hole (which will be known from a drill drawing or from a CAMtastic import of the drill file). The holes should also be given the correct pin numbers. You'll need the Boardmaker net list to get those pin numbers, and also to check the finished list. It might be necessary to translate the list to Protel format, I have not researched this point. Once you have all the footprints. Take, say, the top layer of the board and place the footprints over the existing free pads from the gerber import. Identify the via pad size and globally select all the via pads based on pad size (and possibly on drill size). Use the Convert tool to give all these pads the appropriate hole size and then to convert them to vias. Select all remaining free pads on the design. Unselect any free pads you want to keep, such as mounting holes. Delete all the free pads. Keep your work at each stage, since you might easily make a mistake or run into some unanticipated condition and you might have to backtrack. Note that the top layer not only has all the pads but it also has all track and vias for that layer. Delete all pads on other layers. (I've described the import of a through-hole board; with SMT, one will merely need to place all bottom parts before deleting pads. I'd recommend building all the parts as top side parts; if there are bottom parts (footprints that are not used on the top of the PCB) I'd mirror the bottom layer and move it to a top layer (i.e., on a scratch PCB) before building the parts.) The track routing should be correct already. Complications: polygon fills if Boardmaker DOS had that; these could be left as drawn track, but if extensive changes are to be made it might be worth converting them to Protel polygons. split negative layers will require hand work to replace the split track with split plane segments. When the board appears correct, load the net list and verify. Fix any errors. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Adding extra tracks and vias.
I'm working on a layout with two quad flat packs. A substantial number of pins on each chip have no connection. Because of the difficulty of hand-soldering to fine pitch pins, I would like to add a track and a via to each unused pin for possible use later. I'm have two issues: 1. DRC flags these extra tracks and vias as violations. 2. I get no protection from the design rules that specify minimum clearances and such. I think this must be a common problem. Is there an easy way to fix this without changing the schematic? Protel 99 SE sp6. Thanks, Matt __ Do You Yahoo!? LAUNCH - Your Yahoo! Music Experience http://launch.yahoo.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Hole annular ring
OK, I feel like an idiot for asking this question, but I'll use the excuse that I'm only an occasional PCB designer. I mainly write firmware. I have placed a few pads on my PCB with the following properties: X size: 0 Y size: 0 Round Hole size 147 mil Multi-layer Not plated These are supposed to be mounting holes. I get annular ring violations on these pads. Should I not be using pads for mounting holes? Protel 99 SE sp6. Thanks, Matt __ Do You Yahoo!? LAUNCH - Your Yahoo! Music Experience http://launch.yahoo.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Adding extra tracks and vias.
Re: [PEDA] Adding extra tracks and vias.
In the sch editor create net list and check "include single pin nets. In the pcb editor load the net list this will allow you to add tracks and vias with rules applying. Jerry Fisher Assoc. Engineer Pelco 10 Corporate Dr. Orangeburg NY 10962 (845) 398-8700 [EMAIL PROTECTED] -Original Message- From: Embedded Matt [mailto:[EMAIL PROTECTED]] Sent: Thursday, May 23, 2002 2:10 PM To: Protel EDA Forum Subject: [PEDA] Adding extra tracks and vias. I'm working on a layout with two quad flat packs. A substantial number of pins on each chip have no connection. Because of the difficulty of hand-soldering to fine pitch pins, I would like to add a track and a via to each unused pin for possible use later. I'm have two issues: 1. DRC flags these extra tracks and vias as violations. 2. I get no protection from the design rules that specify minimum clearances and such. I think this must be a common problem. Is there an easy way to fix this without changing the schematic? Protel 99 SE sp6. Thanks, Matt __ Do You Yahoo!? LAUNCH - Your Yahoo! Music Experience http://launch.yahoo.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Gerber to Protel, was Boardmaker to Protel
Abd ul-Rahman or others, do you know of a process using Protel V2.8 whereby you can read in gerber type data with a unique name applied to pads or vias of certain sizes. Then you can replace these uniquely named pads and via flashes with Protel pads & vias through global edits? I don't recall the exact process but I did do it once under the guidance of someone who is not here anymore. We used to do this to return intelligence back to gerber flashed pads and vias in the Protel database. That typically just left tracks to globally edit to the correct layers. it's not perfect solution fo this problem but it did take care of multilayer type pad connectivity. Supposedly this process only worked in version 2.8. Sorry I don't recall the exact process as I was guided through it only once for a very small project. At the time I was assured that it only worked in V2.8 and not any newer versions. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com Visit us at Booth 2G2-09 at CommunicAsia 2002 in Singapore June 18-21. > -Original Message- > From: Abd ulRahman Lomax [mailto:[EMAIL PROTECTED]] > Sent: Thursday, May 23, 2002 10:21 AM > To: Protel EDA Forum > Subject: Re: [PEDA] Gerber to Protel, was Boardmaker to Protel > > >It has been suggested that the Gerbers generated by > Boardmaker can be > >imported via Camtastic. How can this method recover the connectivity > >between layers? > > There is a lot of hand work involved, it is not just a matter > of doing an > import and then being done. > > > How can the plot of a pad on one layer relate to an identically > > positioned plot of a pad on another layer? (or is Camtastic > so fantastic > > that is knows that such instances are vias?). > > No, Protel is that fantastic, or, rather, a skilled designer driving > Protel. Global edits make a lot of things possible. > > Here is a general procedure: > > Bring the gerber into CAMtastic; this step could be skipped > if the gerber > is compatible with Protel. CAMtastic output can be made compatible. > > (There are some tools in CAMtastic that might assist in the > process, I have > not explored them.) > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Adding extra tracks and vias.
Matt, what reason does the DRC flag these extra tracks and vias? What is the violation? I believe it would probably be because they are "No Net" connections. This is also 'possibly' why they don't follow your spacing DRC rules. For clearance rules you have to watch the net issues because if you do not have the board - board general clearance rule and other rules are all net related, then the 'no net' connections may not be checked for violations. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com Visit us at Booth 2G2-09 at CommunicAsia 2002 in Singapore June 18-21. > -Original Message- > From: Embedded Matt [mailto:[EMAIL PROTECTED]] > Sent: Thursday, May 23, 2002 11:10 AM > To: Protel EDA Forum > Subject: [PEDA] Adding extra tracks and vias. > > > I'm working on a layout with two quad flat packs. A > substantial number of pins on each chip have no > connection. Because of the difficulty of > hand-soldering to fine pitch pins, I would like to add > a track and a via to each unused pin for possible use > later. > > I'm have two issues: > > 1. DRC flags these extra tracks and vias as > violations. > 2. I get no protection from the design rules that > specify minimum clearances and such. > > I think this must be a common problem. Is there an > easy way to fix this without changing the schematic? > > Protel 99 SE sp6. > > Thanks, > Matt * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Hole annular ring
Re: [PEDA] TO3 footprint
At 09:26 AM 5/23/2002 -0400, Jeff Adolphs wrote: >Good Morning! I have a TO3 schematic part with pins 1, 2, 3. The TO3 >footprint has pins 1, 2, and two pin 3's. I thought this would work but >the pin 3's do not have netnames in the layout. Do I have to use a >schematic and footprint pin 3A and pin 3B? Let me guess. Mr Adolphs used Netlist Load instead of the synchronizer (Schematic/Design/Update PCB). There is a known bug in the Netlist Load routines which causes assignment oscillation: the existing assigment will change state between the correct net name and no-net with each successive load. The easiest fix is to use Update PCB, but if that is not available, as with a net list from another CAD Schematic program, making a fresh load after having cleared out nets will produce correct assignments. The command Design/Netlist Manager/Menu/Update Free primitives... will restore the free primitive assignments (i.e., track and via). Note that non-pad primitives that are part of footprints are also updated in addition to free primitives. A symptom of the problem is that each netlist load produces new macros, even though the same netlist was just loaded already. The macros oscillate the assignments. It is a good practice to reload the net list or resynchronize before beginning routing and after completing a design; if the only macros that are created are the oscillating kind, or no macros are created, the load can be cancelled. It would still be prudent to manually verify those pads. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Hole annular ring
Matt, Just define a pad class for your mounting holes. Then define an appropriate annular ring rule for that class. If you haven't learned about classes yet, this is what they are good for! Richard At 11:14 AM 5/23/2002 -0700, you wrote: >OK, I feel like an idiot for asking this question, but >I'll use the excuse that I'm only an occasional PCB >designer. I mainly write firmware. > >I have placed a few pads on my PCB with the following >properties: > >X size: 0 >Y size: 0 >Round >Hole size 147 mil >Multi-layer >Not plated > >These are supposed to be mounting holes. I get >annular ring violations on these pads. Should I not >be using pads for mounting holes? > >Protel 99 SE sp6. > >Thanks, >Matt > >__ >Do You Yahoo!? >LAUNCH - Your Yahoo! Music Experience >http://launch.yahoo.com Cheesecote Mountain CAMAC, 24 Halley Drive; Pomona, NY 10970 voice: 845 364 0211, fax: 845 362 6947, www.cmcamac.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Hole annular ring
At 11:14 AM 5/23/2002 -0700, Embedded Matt wrote: >I have placed a few pads on my PCB with the following >properties: > >X size: 0 >Y size: 0 Don't do that >Round >Hole size 147 mil >Multi-layer >Not plated > >These are supposed to be mounting holes. I get >annular ring violations on these pads. Of course: your hole violates the annular ring rule that you have set. > Should I not >be using pads for mounting holes? No, you should be using pads. There are a number of solutions to this problem. (1) Make the pad larger than the hole by an amount which matches the *hardware* which will mount to the hole. That way Protel's clearance rules will ensure that you don't have mounting hardware shorting to track or vias or other copper. (2) Use a pad substantially smaller than the hole, even smaller than any other pads used on the board. It will be drilled away, it is harmless. It is unlikely to confuse the fabricators. But this will still generate an annular ring error. You could disable annular ring checking, but it might be better to create a special annular ring rule. If you give these pads a distinctive name, for example "MH" you can make the rule apply to Free-MH. But I have not tested how the annular ring rule works in a case like this, I almost always use the larger pad solution. I prefer (1) for a number of reasons: it checks the hardware clearance automatically, and it does not confuse the Protel DRC even if no special rules are written. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Adding extra tracks and vias.
Another solution, besides those already given, is to use, in the footprint, through pads the size of vias and with the same hole size, given the same net as the SM pad. You will have complete DRC protection Another solution which might be better in some ways is to add a test point (single hole) part, one on each unused pin. Once one knows how to copy and paste, it would be very quick to add these to the schematic, one click per pad or even several pads with a single click. These will then be incorporated into the net list; an advantage is that they can each be given a number which can appear on the legend, making such changes easier to document and recognise. There are also ways to speed up the PCB side of this, but I won't go into detail now. Note that it is an advantage to be able to move the test or wiring points if routing requires it... You can move pads included inside a footprint by unlocking the footprint in the Edit dialog; but I'd prefer adding separate parts; the separate parts can be made into a Union with the flat pack to which they adhere, so they will move around together. At 11:10 AM 5/23/2002 -0700, Embedded Matt wrote: >I'm working on a layout with two quad flat packs. A >substantial number of pins on each chip have no >connection. Because of the difficulty of >hand-soldering to fine pitch pins, I would like to add >a track and a via to each unused pin for possible use >later. > >I'm have two issues: > >1. DRC flags these extra tracks and vias as >violations. >2. I get no protection from the design rules that >specify minimum clearances and such. > >I think this must be a common problem. Is there an >easy way to fix this without changing the schematic? > >Protel 99 SE sp6. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Gerber to Protel, was Boardmaker to Protel
At 11:31 AM 5/23/2002 -0700, Brad Velander wrote: >Abd ul-Rahman or others, > do you know of a process using Protel V2.8 whereby you can read in >gerber type data with a unique name applied to pads or vias of certain >sizes. No. > Then you can replace these uniquely named pads and via flashes with >Protel pads & vias through global edits? I don't recall the exact process >but I did do it once under the guidance of someone who is not here anymore. >We used to do this to return intelligence back to gerber flashed pads and >vias in the Protel database. That typically just left tracks to globally >edit to the correct layers. it's not perfect solution fo this problem but it >did take care of multilayer type pad connectivity. First of all, if the plot layers are appropriately named, they will come in to the proper Protel layer. The difficulty with the process Mr. Velander has described is the hand-waving part: getting the file with unique names applied to pads. He mentioned vias, but vias don't have names If I have a file with pad names and locations, the spreadsheet can be used to bring those names into the pads; likewise, in the spreadsheet, the pads can be made into through-pads if appropriate; the spreadsheet can also be used to bring in drill data (it is not hard to turn a text drill file into a spreadsheet with locations and sizes, which can then be co-sorted with the pad data and merged). I haven't done a major gerber import in some time; but I did use the spreadsheet to assign names to a mass of pads. I was creating a footprint with about 1600 pads (for a MEMS array), and the thought alone of hand-entering all those names made me tired. I had a list of names and locations from the client The spreadsheet could also be used to offset the drill data, if necessary, to match the photoplots; but this can be done in CAMtastic, probably easier. I did just do that with some client gerber, but I was only making a panel, not taking the data into Protel (but I merged it with Protel data for the panel cutouts and holes, CAMtastic is fantastic for that, once one gets behind the weird and poorly documented user interface.) > Supposedly this process only worked in version 2.8. Sorry I don't >recall the exact process as I was guided through it only once for a very >small project. At the time I was assured that it only worked in V2.8 and not >any newer versions. As I said, the hard part is getting that file CAMtastic will generate a net list of sorts, that gives pad locations, so one could use the location as the name I don't think that would improve things much. Tango had a nice little pad naming tool that would assign a sequential pad number with a single click per pad. I've missed it quite a number of times, such a simple procedure that is missing from Protel unless I've overlooked it. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] TO3 footprint
I fixed the TO3 by assigning only one pad as pin 3. Will multiple pins with one pin number work? I have not had a problem with Netlist Load as I force it to browse for the Netlist File not using the netlist it shows. The same bug is in AutoCAD 2000 for inserting a block ...the block does not get updated unless you force it to browse for the file. I think its a Windows type of bug. Am I wrong about this? I will try to remember to use the Update PCB. Must I make sure the Rooms crap is turned off?? Jeff Adolphs www.lakeshore.com -Original Message- From: Abd ulRahman Lomax [mailto:[EMAIL PROTECTED]] Sent: Thursday, May 23, 2002 2:51 PM To: Protel EDA Forum Subject: Re: [PEDA] TO3 footprint At 09:26 AM 5/23/2002 -0400, Jeff Adolphs wrote: >Good Morning! I have a TO3 schematic part with pins 1, 2, 3. The TO3 >footprint has pins 1, 2, and two pin 3's. I thought this would work but >the pin 3's do not have netnames in the layout. Do I have to use a >schematic and footprint pin 3A and pin 3B? Let me guess. Mr Adolphs used Netlist Load instead of the synchronizer (Schematic/Design/Update PCB). There is a known bug in the Netlist Load routines which causes assignment oscillation: the existing assigment will change state between the correct net name and no-net with each successive load. The easiest fix is to use Update PCB, but if that is not available, as with a net list from another CAD Schematic program, making a fresh load after having cleared out nets will produce correct assignments. The command Design/Netlist Manager/Menu/Update Free primitives... will restore the free primitive assignments (i.e., track and via). Note that non-pad primitives that are part of footprints are also updated in addition to free primitives. A symptom of the problem is that each netlist load produces new macros, even though the same netlist was just loaded already. The macros oscillate the assignments. It is a good practice to reload the net list or resynchronize before beginning routing and after completing a design; if the only macros that are created are the oscillating kind, or no macros are created, the load can be cancelled. It would still be prudent to manually verify those pads. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Adding extra tracks and vias.
I have a special schematic component : a single pin connector. On the pcb component side I have two footprints to choose from : 1) a single pad, topside only, rectangular, no hole, 50x100 mil - great to solder a wire 2) a single pad, multilayer, round 32/62mil great for the scope probe to stick in The schematic component lets me choose between the two mentioned bcb footprints. Works great Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com Embedded Matt wrote: > > I'm working on a layout with two quad flat packs. A > substantial number of pins on each chip have no > connection. Because of the difficulty of > hand-soldering to fine pitch pins, I would like to add > a track and a via to each unused pin for possible use > later. > > I'm have two issues: > > 1. DRC flags these extra tracks and vias as > violations. > 2. I get no protection from the design rules that > specify minimum clearances and such. > > I think this must be a common problem. Is there an > easy way to fix this without changing the schematic? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Gerber to Protel, was Boardmaker to Protel
Abd ul-Rahman, the naming is performed on the Gerber data (how I don't remember) such that you have a pad flash with unique names for each different size assignment. Then you can replace those assignments with a multilayer pad globally. I believe there was a manner of making the same thing work for vias as well. It is to bad that I don't recall how it was done because it is ideal for replacing pads (vias?) in the case of a gerber data load. The process also did not involve Camtastic at all. At that time I had never touched Camtastic, it was still in it's shrink wrap. I had simply hoped that someone on the list also knew of this process. I cannot recall the details from the one time I was walked through it by a person who is no longer with our company. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com Visit us at Booth 2G2-09 at CommunicAsia 2002 in Singapore June 18-21. > -Original Message- > From: Abd ulRahman Lomax [mailto:[EMAIL PROTECTED]] > Sent: Thursday, May 23, 2002 12:52 PM > To: Protel EDA Forum > Subject: Re: [PEDA] Gerber to Protel, was Boardmaker to Protel > > > > The difficulty with the process Mr. Velander has described is the > hand-waving part: getting the file with unique names applied > to pads. He > mentioned vias, but vias don't have names > > > > As I said, the hard part is getting that file CAMtastic > will generate a > net list of sorts, that gives pad locations, so one could use > the location > as the name I don't think that would improve things much. > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] TO3 footprint
At 04:29 PM 5/23/2002 -0400, you wrote: >I fixed the TO3 by assigning only one pad as pin 3. Will multiple pins >with one pin number work? Yes. Fully with Schematic/Update PCB, and with a known bug which is harmless once you know what it is with Netlist Load. >I have not had a problem with Netlist Load as I force it to browse for the >Netlist File not using the >netlist it shows. The same bug is in AutoCAD 2000 for inserting a block >...the block does not get updated >unless you force it to browse for the file. I think its a Windows type of >bug. Am I wrong about this? This is not related. >I will try to remember to use the Update PCB. Must I make sure the Rooms >crap is turned off?? Yes. And if it loads rooms because you forget, it is fast to delete them. Get used to the synchronizer, it is the way of the future. Netlist load is a remnant of the old batch processing days. But we still need it for foreign netlists. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Hole annular ring
I have mounting holes : M3 = round pad, 250/125mil, plated I found unplated holes lead to phone calls from the board house. They asked me whether I really wanted unplated holes, until I heard unplated holes are additional work for them. Since it doesn't hurt having them plated, I have them plated. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com Embedded Matt wrote: > > OK, I feel like an idiot for asking this question, but > I'll use the excuse that I'm only an occasional PCB > designer. I mainly write firmware. > > I have placed a few pads on my PCB with the following > properties: > > X size: 0 > Y size: 0 > Round > Hole size 147 mil > Multi-layer > Not plated > > These are supposed to be mounting holes. I get > annular ring violations on these pads. Should I not > be using pads for mounting holes? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Hole annular ring
it can hurt they have to be plugged or masked when wave soldered sometimes the barrel comes out from screw action Dennis Saputelli Rene Tschaggelar wrote: > > I have mounting holes : > > M3 = round pad, 250/125mil, plated > > I found unplated holes lead to phone calls from the board house. > They asked me whether I really wanted unplated holes, until > I heard unplated holes are additional work for them. > Since it doesn't hurt having them plated, I have them plated. > > Rene > -- > Ing.Buero R.Tschaggelar - http://www.ibrtses.com > > Embedded Matt wrote: > > > > OK, I feel like an idiot for asking this question, but > > I'll use the excuse that I'm only an occasional PCB > > designer. I mainly write firmware. > > > > I have placed a few pads on my PCB with the following > > properties: > > > > X size: 0 > > Y size: 0 > > Round > > Hole size 147 mil > > Multi-layer > > Not plated > > > > These are supposed to be mounting holes. I get > > annular ring violations on these pads. Should I not > > be using pads for mounting holes? -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Boardmaker to Protel
Ivor, Camtastic will get your data in verbatim no problem, but it won't be able to make any sense out it regarding components etc - gerber simply doesn't have that information. Don't forget that gerber doesn't even have any info about holes, so you can't expect any linkage in the 'Z' axis. If you've got a large design, then you'll probably find the tracking quite useful but you'll still have your work cut out reinstating the components. If you head down this route, you're best to import a netlist into the finished PCB and blow away all the elements of the old component as you replace it with the new component. In most cases, you'll probably need to redesign new components or at least check hole dimensions etc of the components from the Protel libraries. If the design is small, then just import it into one of the mechanical layers and use it to trace over the tracking - you'll need a layer by layer printout to see what's going on. Out of interest and OT, what put you off the BoardMaker program? I have a colleague whose always goading me about it (and the price) - any ammunition to throw back at him would always be welcome 8) Doug >I have just joined this list and have my first query. We have a huge >number of PCB designs in Boardmaker (an old DOS package written by >Tsien of Cambridge, UK) and require to import them somehow into Protel. >It has been suggested that the Gerbers generated by Boardmaker can be >imported via Camtastic. How can this method recover the connectivity >between layers? How can the plot of a pad on one layer relate to an >identically positioned plot of a pad on another layer? (or is >Camtastic so fantastic that is knows that such instances are vias?). >Any suggestions on how to tackle this problem and any general >solutions to importing designs into Protel from nothing but Gerbers >would be very much appreciated. >Best Regards, Ivor Davies Diplomat UK Ltd _ Chat with friends online, try MSN Messenger: http://messenger.msn.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Hole annular ring
On 11:14 AM 23/05/2002 -0700, Embedded Matt said: >OK, I feel like an idiot for asking this question, but >I'll use the excuse that I'm only an occasional PCB >designer. I mainly write firmware. > >I have placed a few pads on my PCB with the following >properties: > >X size: 0 >Y size: 0 >Round >Hole size 147 mil >Multi-layer >Not plated > >These are supposed to be mounting holes. I get >annular ring violations on these pads. Should I not >be using pads for mounting holes? > >Protel 99 SE sp6. > >Thanks, >Matt In summary. Basic solution is to add an annular ring design rule for the mounting holes. Others have suggested ways of doing that: 1) scope = pad name and make sure all the mounting holes have the same name (my normal solution but ..see below for a comment) 2) create a class and scope the rule on the class 3) scope = pad specification, making sure only the non-plated holes have the given spec. I routinely do what you are doing. If you use the simplest which is method 1) watch out if you ever rename the pad. When you rename things Protel attempts to keep the rules in sync. Say you have 4 mounting holes all implemented as pads named MH. If you have a design rule as per 1) targeting Free-MH all will be fine. But if you then go and rename one of the pads to say MHP as you want one of the pads to be plated for grounding, then Protel will rename the target of the design rule to Free-MHP. This means that your original MH pads are no longer subject to that rule. So there is good reason to consider the other methods and make an informed decision. I will also usually put a keepout arc around the hole (possibly top and bottom layer-specific but often on the keepout layer) to prevent tracks getting close to the washers/screw head/standoff. Making the pad a component helps you to remember the keepout. I usually break the component into free primitives after initial placement to prevent it being deleted by the synchronizer, as I do not put mounting holes on the Sch. (Altium, I request again a NoUpdate component attribute that will allow me to prevent components from being mucked about with by the synchronizer - possibly with a report in the macro window.) Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Hole annular ring
There are two things matt could do. One is to increase the size of the pads for mounting holes from 0 to a value that will not produce DRC error. Look into the DRC rules to find out what the value of the annula ring is and ente the new pad size as 147mil+annular ring value. This would work if you had enough space on board. The other way is to go and make a special rule for the annular ring on the unconnected pads (being mounting holes they are presumably unconnected) and set the annular ring value to 0. At the same time increase the value of the pads to 147mil. Igor -Original Message- From: Rene Tschaggelar [mailto:[EMAIL PROTECTED]] Sent: Friday, 24 May 2002 7:10 AM To: Protel EDA Forum Subject: Re: [PEDA] Hole annular ring I have mounting holes : M3 = round pad, 250/125mil, plated I found unplated holes lead to phone calls from the board house. They asked me whether I really wanted unplated holes, until I heard unplated holes are additional work for them. Since it doesn't hurt having them plated, I have them plated. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com Embedded Matt wrote: > > OK, I feel like an idiot for asking this question, but > I'll use the excuse that I'm only an occasional PCB > designer. I mainly write firmware. > > I have placed a few pads on my PCB with the following > properties: > > X size: 0 > Y size: 0 > Round > Hole size 147 mil > Multi-layer > Not plated > > These are supposed to be mounting holes. I get > annular ring violations on these pads. Should I not > be using pads for mounting holes? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
