[PEDA] Polygon Connect question
It appears that my polygons are in direct connect mode when my design rules state that they are in relief mode. Is there something I'm missing? Tim Fifield * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Gerber output problems
Hi all, I completed the layout of a small PCB (99SE) designed for enclosure in a moulded case, then realised I needed an additional hole for mechanical locking. So I added a free pad, with no copper - just the correct hole size. Everything looks good in PCB, but now, when I output the gerber files I need to panelise in Camtastic, there is no trace of the hole, except for a tiny pin-prick on the top soldermask layer. Why is it so? Regards, Drew * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] (un)hiding part fields
As Abd ul-Rahman Lomax (and others) replied on my question: Sure, use a Global edit. I just *knew* it had to something that ridiculisly simple.. Thank you all, for rejuvenating that knowledge. Leo Potjewijd hardware designer IE Keyprocessor bv. [EMAIL PROTECTED] +31 20 4620700 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Strange Power Plane Connection
At 17:30 14.01.2004 -0500, you wrote: At 02:06 AM 1/14/2004, Juha Pajunen wrote: Pleace see this file: http://groups.yahoo.com/group/protel-users/files/junk/PLANE_ERROR.jpg You are seeing a composite display, not just the plane. You can tell because, inside one of the thermal reliefs, there is a square pad, which would be the multilayer or perhaps solder mask or other aspect of the pad which is not on the power plane. There would never be a square flash on a power plane unless you explicitly place it there as an independent primitive literally on the plane, generally not a good idea. (If you need to place primitives on a power plane, almost always it would be better to place lines; but note that 99SE does not check planes for continuity. If you want continuity checking, you'd have to kludge it with a composite, it can be done.) The other pad blowouts on the plane also show the pad itself On the true plane, you would only see a single round blowout for a pad not connected to the plane, or a thermal relief for a thermally relieved pad. If there is no thermal relief, you won't see *anything* on the plane itself for a via or pad direct-connected to the plane, though it is a good idea to have hole display enabled so you can tell what is going on. The first thought was something is wrong with the pad stack. But there are component pads and also a free pad with the same behaviour (It is a pad in the lowwer right corener, isn't it?). Strange. Do you use pad stacks? Shouldn't have an influence on plane layers anyway. Are you in the single layer mode or do you have the other layers dissabled (I don't think you are in single layer, because the net lines are invisible in this mode)? Do you have a layer with the same colour than the plane (solder/paste mask)? The net connectivity seems to be ok, because there are hair line crosses on the 3.3V pads and via. Just some hints for hunting. By the way, it appears you have vias thermally relieved. That is probably not the best practice, it is better to set a design rule so that all vias are direct-connect. Vias do not generally need thermal relief, and direct connection has the lowest impedance. And also reduces problems with the non existent power plane continuity check. Edi + IH electronic+ Phone: ++41 52 320 90 00 + + Edi Im Hof + Fax: ++41 52 320 90 04 + + Doernlerstrasse 1, Sulz + URL: http://www.ihe.ch + + CH-8544 Rickenbach-Attikon + E-Mail: [EMAIL PROTECTED] + + Switzerland + + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] annular ring or diameter difference?
Help! It may just be my memory playing tricks (already pulled over 40 hours this week), but I thought that the annular ring design rules used the same math (i.e. the difference between the radii) for both pads and vias. During rework of a project that should have been at the fabhouse last week, I noticed a difference between the calculation of a pad and a via: pads still do the right math but vias are calculated by diameter in stead of radius resulting in errors of -50% / +100% Both are pretty undesirable, to say the least. This same error is made in both the online and batch DRC and even in the PCB reports. When I set the scope to 'whole board' and hit 'select affected objects' _all_ copper gets highlighted wether it has a hole or not. Looks weird but relatively harmless. I already tried the DDB repair service (no luck), restarted the PC (no luck) and experimented on a fresh PCB (in the same DDB, true); only to find the same weird stuff. Is this just me being stupid (again) or did some stray cosmic ray toggle a setting somewhere deep inside the works of my P99SE? More importantly: _which_ setting? Help me out here, guys... Leo Potjewijd hardware designer IE Keyprocessor bv. [EMAIL PROTECTED] +31 20 4620700 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Using Protel 99SE with Xilinx 6.1i Project Navigator
At 06:14 PM 1/14/2004 -0600, you wrote: Ray Mitchell wrote: Hello, In the past I've developed my Xilinx FPGAs by creating a schematic in Protel 99SE, generating a netlist in Xilinx XNF 5.0 format, then compiling the XNFs using the Xilinx 3.1i application. To be compatible with the newer Xilinx devices, such as the Coolrunner II series, I have acquired their 6.1i application. However, 6.1i no longer supports XNF files. So my question is how to create something using 99SE that Xilinx 6.1i can handle. I've tried creating the Protel netlist in both VHDL and EDIF 2.0 format but either I'm doing something wrong or they are not compatible with Xilinx 6.1i. Does Protel DSP support this better? All suggestions are welcome. I have done this, but it gets a bit messy. I'm not sure my method is actually any improvement. The only thing I found that worked was VHDL (architectural) netlists. An annoying bug is that P99SE Sp6 will only output one VHDL netlist, then you have to restart P99. If you don't restart P99 each time, it will hang on the netlist step. If you wait half an hour, it outputs 65536 lines of garbage before the valid netlist. But, you get a netlist almost ready for Xilinx isp. You have to manually add the library unisim and the line "use unisim.vcomponents" to get the use of those library components. You can edit away the _sch extension from all VHDL files made from schematic sheets. You have to manually remove duplicate component declarations for all of the user-created components. This only comes up on sheets where you have placed the same user-created library component multiple times. The rough edges are that P99 wants input and output pads on the top level page for sim and ERC, but Xilinx DOESN'T want pads, it assumes any ports on the top page are pads. Jon Jon, Yes, messy but not as messy as trying to use the ISE 6.1i abomination that they're trying to pass off as a schematic tool. From what you describe it seems like it might be reasonable to write a small program to post-process the Protel VHDL files to massage them into a form that ISE wants. If you don't mind, I'd like some clarification on some of the things you mentioned. When I created XNFs for ISE 3.1i Design Manager in the past I had to create a Protel .PRJ sheet that merely contained Sheet Symbols with Sheet Entries. The actual logic was on the .SCH sheets and was tied together by the .PRJ sheet. I always found it annoying Sheet Symbols were needed since they're not needed when doing a schematic for a board layout. I'm most confused about your last statement and I'm not sure what you're telling me about pads. I've always used them for my FPGAs in the past for XNFs. Are you saying that now I should just use IBUFs and OBUFs as my entry and exit components and not attach IPADs and OPADs at all? I didn't think Protel itself cared anything about IPADs and OPADs since they are not used in board schematics. Am I correct in assuming that you regenerated all of the Protel library components for Xilinx as VHDL files also? Thanks for your response, Ray [EMAIL PROTECTED] Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Gerber output problems
Have you got x and y pad sizes same as the hole size? And untick the 'Plated' box. Regards, Igor -Original Message- From: Drew Mills [mailto:[EMAIL PROTECTED] Sent: Thursday, 15 January 2004 2:54 PM To: 'Protel EDA Forum' Subject: [PEDA] Gerber output problems Hi all, I completed the layout of a small PCB (99SE) designed for enclosure in a moulded case, then realised I needed an additional hole for mechanical locking. So I added a free pad, with no copper - just the correct hole size. Everything looks good in PCB, but now, when I output the gerber files I need to panelise in Camtastic, there is no trace of the hole, except for a tiny pin-prick on the top soldermask layer. Why is it so? Regards, Drew _ This e-mail has been scanned for viruses by MCI's Internet Managed Scanning Services - powered by MessageLabs. For further information visit http://www.mci.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Using Protel 99SE with Xilinx 6.1i Project Navigator
Ray Mitchell wrote: At 06:14 PM 1/14/2004 -0600, you wrote: Ray Mitchell wrote: Hello, In the past I've developed my Xilinx FPGAs by creating a schematic in Protel 99SE, generating a netlist in Xilinx XNF 5.0 format, then compiling the XNFs using the Xilinx 3.1i application. To be compatible with the newer Xilinx devices, such as the Coolrunner II series, I have acquired their 6.1i application. However, 6.1i no longer supports XNF files. So my question is how to create something using 99SE that Xilinx 6.1i can handle. I've tried creating the Protel netlist in both VHDL and EDIF 2.0 format but either I'm doing something wrong or they are not compatible with Xilinx 6.1i. Does Protel DSP support this better? All suggestions are welcome. I have done this, but it gets a bit messy. I'm not sure my method is actually any improvement. The only thing I found that worked was VHDL (architectural) netlists. An annoying bug is that P99SE Sp6 will only output one VHDL netlist, then you have to restart P99. If you don't restart P99 each time, it will hang on the netlist step. If you wait half an hour, it outputs 65536 lines of garbage before the valid netlist. But, you get a netlist almost ready for Xilinx isp. You have to manually add the library unisim and the line "use unisim.vcomponents" to get the use of those library components. You can edit away the _sch extension from all VHDL files made from schematic sheets. You have to manually remove duplicate component declarations for all of the user-created components. This only comes up on sheets where you have placed the same user-created library component multiple times. The rough edges are that P99 wants input and output pads on the top level page for sim and ERC, but Xilinx DOESN'T want pads, it assumes any ports on the top page are pads. Jon Jon, Yes, messy but not as messy as trying to use the ISE 6.1i abomination that they're trying to pass off as a schematic tool. From what you describe it seems like it might be reasonable to write a small program to post-process the Protel VHDL files to massage them into a form that ISE wants. If you don't mind, I'd like some clarification on some of the things you mentioned. When I created XNFs for ISE 3.1i Design Manager in the past I had to create a Protel .PRJ sheet that merely contained Sheet Symbols with Sheet Entries. The actual logic was on the .SCH sheets and was tied together by the .PRJ sheet. I always found it annoying Sheet Symbols were needed since they're not needed when doing a schematic for a board layout. Well, I just set up a VHDL project, and then imported copies of all the .VHD files, and ise knew what to do with them from there. For each sheet I imported, if the user symbols hadn't been loaded yet, I got a pink question mark. If the symbols had already been loaded for another sheet that used them, then you got a green check or whatever, to show that the symbol has been linked in. The problem with this is that all sorts of odd things in the Protel schematic pages can cause problems in the VHDL sheets, and some of them are VERY difficult to find. Also, many of the component library parts that are standard with Xilinx, are either missing, badly created or have differences in the port names. Like a 2:1 mux in Protel has the select input as S0, while the Xilinx unisim library part has the port as just S. So, you have to manually recreate a bunch of the standard symbols in Protel, and then import those. I don't know, maybe there is another level of libraries somewhere in the bowels of the inscrutable Xilinx files that defines all of these, but I couldn'tr find it. These are things like 4-bit counters, 8-bit latches, etc. The fundamental units are there, the FFs and single-wide muxes. I'm most confused about your last statement and I'm not sure what you're telling me about pads. I've always used them for my FPGAs in the past for XNFs. Are you saying that now I should just use IBUFs and OBUFs as my entry and exit components and not attach IPADs and OPADs at all? I didn't think Protel itself cared anything about IPADs and OPADs since they are not used in board schematics. It seems that with VHDL, there is no such thing as a "pad", and the ibufs and obufs are totally optional for most signals. In special cases where you need a tri-state output only, or are using a pin for both an input and output, it may be necessary to use the ibuf and obuf parts to clarify how the pin is to be used. Am I correct in assuming that you regenerated all of the Protel library components for Xilinx as VHDL files also? No. I did have to regenerate some parts that were not in the Protel libraries (I used the 4000 library for Spartan parts, for instance), and others that were fouled up enough to need a complete re-do. The Protel libraries are not completely in sync with the libraries that Xilinx has in the ise 4.2i software that I'm using. A l
Re: [PEDA] Gerber output problems
You don't say whether or not you added the hole after you first ran a set of Gerbers. If you went back after generating a Gerber set, did you remember to generate a new aperture file that includes the hole definition? Try selecting the pinprick you mention and see what D code is assigned, then look to see how that D code is defined in the Protel aperture file. At 07:54 PM 1/14/04, you wrote: Hi all, I completed the layout of a small PCB (99SE) designed for enclosure in a moulded case, then realised I needed an additional hole for mechanical locking. So I added a free pad, with no copper - just the correct hole size. Everything looks good in PCB, but now, when I output the gerber files I need to panelise in Camtastic, there is no trace of the hole, except for a tiny pin-prick on the top soldermask layer. Why is it so? snip * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Gerber output problems
At 10:54 PM 1/14/2004, Drew Mills wrote: I completed the layout of a small PCB (99SE) designed for enclosure in a moulded case, then realised I needed an additional hole for mechanical locking. So I added a free pad, with no copper - just the correct hole size. Everything looks good in PCB, but now, when I output the gerber files I need to panelise in Camtastic, there is no trace of the hole, except for a tiny pin-prick on the top soldermask layer. Why is it so? Here is what is going on. The soldermask layer is a calculated layer, it is generated from the pad size. In order to make a "pad with no copper" you made the dimensions of the pad zero. The solder mask is generated as an oversize from the pad size, so that it clears the pad. That's what is creating the "pin-prick," it would probably be a pad with a diameter of twice your solder mask clearance, perhaps 20 mils, about the size of a pinhole. What did you expect to see on the gerbers? I usually create mechanical holes as a pad with clearance, the pad being made the size of, for example, the MMC of a screw head for a screw going into the hole. That way my DRC guarantees that a screw can't bite into a track I've often left it just like that, but there is some thought that hole plating in mounting holes can create problems with fragments of copper. I'm not sure how much of a real problem it is, but if you don't want the hole plated, then you can request that from the fabricators (it may be enough to uncheck the Plated box on the Advanced tab of the pad edit dialog). Unplated holes can be a bit of extra cost, they have to be treated specially. If you don't want the pad to be there, you can made the pad size smaller than the hole. I wouldn't make it zero, though. Invisible pads give me the creeps If you want solder mask to be clear of the hole, you can set a rule for that pad. You might give the pad a name like "MH" for "mounting hole" and then you can create design rules for the pad Free-MH. This would allow you to define sufficient clearance rules to prevent possible shorts, if that is relevant for this design, as well as a solder mask expansion that will make the solder mask opening be larger than the hole. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Gerber output problems
Well my problem is solved, but I still cannot explain why. The pad was on the top layer, instead of multilayer as I intended. Changing to multilayer and re-generating the gerbers sorted it. I would have thought though that it doesn't matter what layer the pad is on, so long as a hole size is specified. Thanks for your replies. Drew -Original Message- From: Harry Selfridge [mailto:[EMAIL PROTECTED] Sent: Friday, 16 January 2004 10:46 AM To: Protel EDA Forum Subject: Re: [PEDA] Gerber output problems You don't say whether or not you added the hole after you first ran a set of Gerbers. If you went back after generating a Gerber set, did you remember to generate a new aperture file that includes the hole definition? Try selecting the pinprick you mention and see what D code is assigned, then look to see how that D code is defined in the Protel aperture file. At 07:54 PM 1/14/04, you wrote: >Hi all, > >I completed the layout of a small PCB (99SE) designed for enclosure in a >moulded case, then realised I needed an additional hole for mechanical >locking. So I added a free pad, with no copper - just the correct hole size. >Everything looks good in PCB, but now, when I output the gerber files I need >to panelise in Camtastic, there is no trace of the hole, except for a tiny >pin-prick on the top soldermask layer. Why is it so? snip * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Polygon Connect question
At 12:50 PM 1/15/2004, Tim Fifield wrote: It appears that my polygons are in direct connect mode when my design rules state that they are in relief mode. Is there something I'm missing? Probably. Let's go over the basics. There are two sets of connection rules: those for copper pour and those for inner planes. You might be confusing the two. "Polygons", I'd assume, would refer to copper pour. Unlike inner planes, which are calculated layers for the most part (created by rules), copper pours -- "polygon planes" are created by defining the vertices and the various settings, and then the polygon is "built." Once it is built, it is in the database as a collection of free primitives -- track and arcs. You can unlock the plane and edit and move the individual primitives, if you want If you change the rules, planes are not automatically rebuilt. You can rebuild a plane simply by double-clicking on it to bring up the edit dialog and then OK'ing it, you'll be asked if you want to rebuild. There are tricks for getting all the polygons to rebuild at once, if you need to know that. As with inner planes, I recommend that vias be set for direct connect to polygons. So the default rule would be thermal relief, and then a Via Specification rule sets all vias for direct connect. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Strange Power Plane Connection
At 03:01 AM 1/15/2004, Edi Im Hof wrote: [I had written:] By the way, it appears you have vias thermally relieved. That is probably not the best practice, it is better to set a design rule so that all vias are direct-connect. Vias do not generally need thermal relief, and direct connection has the lowest impedance. And also reduces problems with the non existent power plane continuity check. In fact, if you have vias direct-connect, and you have placed no blowout primitives on the plane, it is much less likely to happen that there is a continuity problem on an inner plane. The thermal reliefs from vias can pretty well chew up a plane; if they are direct connect, the fact that the vias have some clearance from each other guarantees that they can't interrupt continuity. I think that the use of direct-connect vias on inner planes could make a measureable noise difference over thermally-relieved vias, not only because of the lower impedance from the individual connections, but also because of better performance of the plane, which has more copper remaining. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] annular ring or diameter difference?
At 01:11 PM 1/15/2004, Leo Potjewijd wrote: Help! It may just be my memory playing tricks (already pulled over 40 hours this week), but I thought that the annular ring design rules used the same math (i.e. the difference between the radii) for both pads and vias. Some of the Protel documentation and in-program labelling has been incorrect in the past; but it is traditional that annular ring refers to the width of the ring, so a 10 mil annular ring would mean a diameteric difference of 20 mils. The bad on-screen explanation -- and the actual calculations? -- were corrected not long ago, it might even have been the SE release, I forget. During rework of a project that should have been at the fabhouse last week, I noticed a difference between the calculation of a pad and a via: pads still do the right math but vias are calculated by diameter in stead of radius resulting in errors of -50% / +100% Both are pretty undesirable, to say the least. This same error is made in both the online and batch DRC and even in the PCB reports. I just made a test PCB and the annular ring rules functioned properly, i.e., they reported radial difference. They did this for both pads and vias. I had separate rules for pads and vias. When I set the scope to 'whole board' and hit 'select affected objects' _all_ copper gets highlighted wether it has a hole or not. Looks weird but relatively harmless. Well, not suprising. The annular ring rule applies to pads and vias. If they don't have a hole, the annular ring is simply the radius of the pad The programming was simpler that exempting zero-hole pads, but I do wonder if a pad with no hole that violated the annular ring rule (i.e., the radius was smaller than the rule value) would create a violation. So I tried it. It doesn't. So the rule applies to the pad, but if the hole size is zero, the DRC exempts it from violation. I already tried the DDB repair service (no luck), restarted the PC (no luck) and experimented on a fresh PCB (in the same DDB, true); only to find the same weird stuff. Is this just me being stupid (again) Probably. :-) Join the crowd. I won't bore you with all the stupid things I've done in the past day or did some stray cosmic ray toggle a setting somewhere deep inside the works of my P99SE? More importantly: _which_ setting? I think you're going to need to look again, and I suggest documenting, in a mail to us, *exactly* what is in each rule and exactly what primitives you have -- try it with a small test board, it only really needs a couple of vias and pads -- and exactly what report you get, copy and paste the important parts into your mail. My guess is that before you are done, you'll be slapping your head * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Gerber output problems
> -Original Message- > From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED] > Sent: Friday, 16 January 2004 12:25 > To: Protel EDA Forum > Subject: Re: [PEDA] Gerber output problems > > > At 10:54 PM 1/14/2004, Drew Mills wrote: > >I completed the layout of a small PCB (99SE) designed for > enclosure in a > >moulded case, then realised I needed an additional hole for > mechanical > >locking. So I added a free pad, with no copper - just the > correct hole size. > >Everything looks good in PCB, but now, when I output the > gerber files I need > >to panelise in Camtastic, there is no trace of the hole, > except for a tiny > >pin-prick on the top soldermask layer. Why is it so? > > Here is what is going on. The soldermask layer is a > calculated layer, it is > generated from the pad size. In order to make a "pad with no > copper" you > made the dimensions of the pad zero. The solder mask is > generated as an > oversize from the pad size, so that it clears the pad. That's what is > creating the "pin-prick," it would probably be a pad with a > diameter of > twice your solder mask clearance, perhaps 20 mils, about the > size of a pinhole. > > What did you expect to see on the gerbers? > > I usually create mechanical holes as a pad with clearance, > the pad being > made the size of, for example, the MMC of a screw head for a > screw going > into the hole. That way my DRC guarantees that a screw can't > bite into a > track I've often left it just like that, but there is > some thought that > hole plating in mounting holes can create problems with fragments of > copper. I'm not sure how much of a real problem it is, but if > you don't > want the hole plated, then you can request that from the > fabricators (it > may be enough to uncheck the Plated box on the Advanced tab > of the pad edit > dialog). Unplated holes can be a bit of extra cost, they have > to be treated > specially. > > If you don't want the pad to be there, you can made the pad > size smaller > than the hole. I wouldn't make it zero, though. Invisible > pads give me the > creeps If you want solder mask to be clear of the hole, > you can set a > rule for that pad. You might give the pad a name like "MH" > for "mounting > hole" and then you can create design rules for the pad > Free-MH. This would > allow you to define sufficient clearance rules to prevent > possible shorts, > if that is relevant for this design, as well as a solder mask > expansion > that will make the solder mask opening be larger than the hole. Abdul, being familiar with this design (Drew works in the same office as me), I can comment on the clearence problem - there is not one. The "missing" hole is for a plastic locating pin in a blow moulded housing. Hence no need for copper to allow for screw head size, as there is no screw. Tom L. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Gerber output problems
At 09:12 PM 1/15/2004, Drew Mills wrote: Well my problem is solved, but I still cannot explain why. The pad was on the top layer, instead of multilayer as I intended. Changing to multilayer and re-generating the gerbers sorted it. I would have thought though that it doesn't matter what layer the pad is on, so long as a hole size is specified. The Protel programmers didn't anticipate that you'd have a surface pad with a hole, it seems. If you want a pad only on one side, I think you use a multilayer pad with a padstack Surface pads are supposed to live only on one layer. Really, the program should lock you out from doing it the way you did. In other words, if it is a single-layer pad, the Hole size should be greyed out. But it isn't. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Gerber output problems
> -Original Message- > From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED] > Sent: Friday, 16 January 2004 13:30 > To: Protel EDA Forum > Subject: Re: [PEDA] Gerber output problems > The Protel programmers didn't anticipate that you'd have a > surface pad with > a hole, it seems. If you want a pad only on one side, I think > you use a > multilayer pad with a padstack Surface pads are supposed > to live only > on one layer. Really, the program should lock you out from > doing it the way > you did. In other words, if it is a single-layer pad, the > Hole size should > be greyed out. But it isn't. What!? How are single sided through hole boards supposed to be done then? Tom L. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Gerber output problems
>What!? > >How are single sided through hole boards supposed to be >done then? > We just use Multilayer pads and uncheck "plating" when doing single sided boards. Every manufacturer I've come across has no problem with this. TC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] List Moderator.
-Original Message- From: postmaster+AEA-Biotest-MT.de +AFs-mailto:postmaster+AEA-Biotest-MT.de+AF0- Sent: Friday, 16 January 2004 14:46 To: Thomas Subject: Benachrichtung zum +ANw-bermittlungsstatus (Fehlgeschlagen) Dies ist eine automatisch erstellte Benachrichtigung +APw-ber den Zustellstatus. +ANw-bermittlung an folgende Empf+AOQ-nger fehlgeschlagen. rguetlein+AEA-biotest-mt.de I keep getting the message above when posting to the PEDA forum. Translated (roughly): This is an automatically provided notification over the setting status. Transmission to the following receivers missed. rguetlein+AEA-biotest mt.de Sounds like a nonexistent email address rather than an +ACI-out of the office+ACI- auto responder. Any chance of getting it unsubscribed? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
