Re: [Qemu-devel] [PATCH] scripts/make-release: Stop shipping u-boot source as a tarball

[Michael Roth]

Quoting Peter Maydell (2019-03-14 10:56:28)
> In commit d0dead3b6df7f6cd970e we changed to shipping the u-boot
> sources as a tarball, to work around a problem where they
> contained a file and directory that had the same name except
> for case, which was preventing QEMU's source tarball being
> unpacked on case-insensitive filesystems.
> 
> In commit f2a3b549e357041f86d7e we updated our u-boot blob
> and sources to v2019.01, which no longer has this problem,
> so we can finally remove our workaround (effectively
> reverting d0dead3b6df7f6cd970e).
> 
> Signed-off-by: Peter Maydell 

Reviewed-by: Michael Roth 

> ---
> Tested (with a slightly hand-hacked script) by creating a tarball
> with master as of dbbc277510aa39ea and unpacking it on OSX.
> ---
>  scripts/make-release | 4 
>  1 file changed, 4 deletions(-)
> 
> diff --git a/scripts/make-release b/scripts/make-release
> index c14f75b12c8..b4af9c9e520 100755
> --- a/scripts/make-release
> +++ b/scripts/make-release
> @@ -20,10 +20,6 @@ git checkout "v${version}"
>  git submodule update --init
>  (cd roms/seabios && git describe --tags --long --dirty > .version)
>  (cd roms/skiboot && ./make_version.sh > .version)
> -# FIXME: The following line is a workaround for avoiding filename collisions
> -# when unpacking u-boot sources on case-insensitive filesystems. Once we
> -# update to something with u-boot commit 610eec7f0 we can drop this line.
> -tar --exclude=.git -cjf roms/u-boot.tar.bz2 -C roms u-boot && rm -rf 
> roms/u-boot
>  popd
>  tar --exclude=.git -cjf ${destination}.tar.bz2 ${destination}
>  rm -rf ${destination}
> -- 
> 2.20.1
> 

[Qemu-devel] [Bug 1817865] Re: sorecvfrom freezes guest

[Vic]

Fix committed in slirp/src/socket.c

** Changed in: qemu
   Status: New => Fix Committed

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1817865

Title:
  sorecvfrom freezes guest

Status in QEMU:
  Fix Committed

Bug description:
  QEMU release 3.1.0; Guest running win10.

  Sometimes sorecvfrom() is called from slirp.c because revents ==
  G_IO_IN, however inside sorecvfrom() function, ioctlsocket() returns 0
  bytes available and recvfrom could be blocking indefinitely.

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1817865/+subscriptions

[Qemu-devel] Set up github repo for pmon sources

[Andrew Randrianasulu]

https://github.com/Randrianasulu/pmon/commits/2014

hopefully it will stay this way.

Anyone know what license I must pick for this?
3-clause BSD? 4-clause BSD? (from Copyright file it lists 4 terms)


*  $Id: Copyright,v 1.1.1.1 2006/09/14 01:59:06 root Exp $ */

/*
 * Copyright (c) 2000-2002 Opsycon AB  (www.opsycon.se)
 * Copyright (c) 2000 Rtmx, Inc   (www.rtmx.com)
 * Copyright (c) 2001 ipUnplugged AB (www.ipunplugged.com)
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *notice, this list of conditions and the following disclaimer in the
 *documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *must display the following acknowledgement:
 *  This product includes software developed for Rtmx, Inc by
 *  Opsycon Open System Consulting AB, Sweden.
 *  This product includes software developed by Opsycon AB.
 *  This product includes software developed by ipUnplugged AB.
 * 4. The name of the author may not be used to endorse or promote products
 *derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */


In theory master branch is newer, but it seems ubifs commit in early 2014 broke 
non-nand machines, so I was uanble to solve this. May be I should cherry-pick 
some  master commits to 2014 branch, but I don't know if they fix anything 
useful
for emulated machine or not.

Src where I got tarball with git:
http://www.anheng.com.cn/loongson/pmon/

[Qemu-devel] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4

[Alistair Francis]

v3:
 - Add a patch to remove some dead code
 - Rebase on master
v2:
 - Add a patch for SiFive U SMP support
 - Rebase on master

Alistair Francis (3):
  riscv: pmp: Log pmp access errors as guest errors
  riscv: sifive_u: Allow up to 4 CPUs to be created
  target/riscv: Remove unused struct

Kito Cheng (1):
  RISC-V: linux-user support for RVE ABI

Michael Clark (8):
  RISC-V: Replace __builtin_popcount with ctpop8 in PLIC
  RISC-V: Allow interrupt controllers to claim interrupts
  RISC-V: Remove unnecessary disassembler constraints
  elf: Add RISC-V PSABI ELF header defines
  RISC-V: Change local interrupts from edge to level
  RISC-V: Add support for vectored interrupts
  RISC-V: Convert trap debugging to trace events
  RISC-V: Update load reservation comment in do_interrupt

 Makefile.objs   |   1 +
 disas/riscv.c   | 138 -
 hw/riscv/sifive_plic.c  |  19 +++-
 hw/riscv/sifive_u.c |   5 +-
 include/elf.h   |  10 +++
 linux-user/riscv/cpu_loop.c |  15 +++-
 target/riscv/cpu.c  |   6 --
 target/riscv/cpu.h  |   6 ++
 target/riscv/cpu_helper.c   | 168 +++-
 target/riscv/cpu_user.h |   3 +-
 target/riscv/csr.c  |  22 ++---
 target/riscv/pmp.c  |  20 +++--
 target/riscv/trace-events   |   2 +
 13 files changed, 148 insertions(+), 267 deletions(-)
 create mode 100644 target/riscv/trace-events

-- 
2.21.0

[Qemu-devel] [PATCH v1 01/12] riscv: pmp: Log pmp access errors as guest errors

[Alistair Francis]

Signed-off-by: Alistair Francis 
---
 target/riscv/pmp.c | 20 +---
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 15a5366616..b11c4ae22f 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -113,10 +113,11 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t 
pmp_index, uint8_t val)
 env->pmp_state.pmp[pmp_index].cfg_reg = val;
 pmp_update_rule(env, pmp_index);
 } else {
-PMP_DEBUG("ignoring write - locked");
+qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
 }
 } else {
-PMP_DEBUG("ignoring write - out of bounds");
+qemu_log_mask(LOG_GUEST_ERROR,
+  "ignoring pmpcfg write - out of bounds\n");
 }
 }
 
@@ -249,7 +250,8 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong 
addr,
 
 /* partially inside */
 if ((s + e) == 1) {
-PMP_DEBUG("pmp violation - access is partially inside");
+qemu_log_mask(LOG_GUEST_ERROR,
+  "pmp violation - access is partially inside\n");
 ret = 0;
 break;
 }
@@ -306,7 +308,8 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t 
reg_index,
 env->mhartid, reg_index, val);
 
 if ((reg_index & 1) && (sizeof(target_ulong) == 8)) {
-PMP_DEBUG("ignoring write - incorrect address");
+qemu_log_mask(LOG_GUEST_ERROR,
+  "ignoring pmpcfg write - incorrect address\n");
 return;
 }
 
@@ -353,10 +356,12 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t 
addr_index,
 env->pmp_state.pmp[addr_index].addr_reg = val;
 pmp_update_rule(env, addr_index);
 } else {
-PMP_DEBUG("ignoring write - locked");
+qemu_log_mask(LOG_GUEST_ERROR,
+  "ignoring pmpaddr write - locked\n");
 }
 } else {
-PMP_DEBUG("ignoring write - out of bounds");
+qemu_log_mask(LOG_GUEST_ERROR,
+  "ignoring pmpaddr write - out of bounds\n");
 }
 }
 
@@ -372,7 +377,8 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t 
addr_index)
 if (addr_index < MAX_RISCV_PMPS) {
 return env->pmp_state.pmp[addr_index].addr_reg;
 } else {
-PMP_DEBUG("ignoring read - out of bounds");
+qemu_log_mask(LOG_GUEST_ERROR,
+  "ignoring pmpaddr read - out of bounds\n");
 return 0;
 }
 }
-- 
2.21.0

[Qemu-devel] [PATCH v1 02/12] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC

[Alistair Francis]

From: Michael Clark 

The mode variable only uses the lower 4-bits (M,H,S,U) so
replace the GCC specific __builtin_popcount with ctpop8.

Cc: Palmer Dabbelt 
Cc: Sagar Karandikar 
Cc: Bastian Koppelmann 
Cc: Alistair Francis 
Signed-off-by: Michael Clark 
Signed-off-by: Alistair Francis 
---
 hw/riscv/sifive_plic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index d12ec3fc9a..b859f919a7 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -383,7 +383,7 @@ static void parse_hart_config(SiFivePLICState *plic)
 p = plic->hart_config;
 while ((c = *p++)) {
 if (c == ',') {
-addrid += __builtin_popcount(modes);
+addrid += ctpop8(modes);
 modes = 0;
 hartid++;
 } else {
@@ -397,7 +397,7 @@ static void parse_hart_config(SiFivePLICState *plic)
 }
 }
 if (modes) {
-addrid += __builtin_popcount(modes);
+addrid += ctpop8(modes);
 }
 hartid++;
 
-- 
2.21.0

[Qemu-devel] [PATCH v1 04/12] RISC-V: Remove unnecessary disassembler constraints

[Alistair Francis]

From: Michael Clark 

Remove machine generated constraints that are not
referenced by the pseudo-instruction constraints.

Cc: Palmer Dabbelt 
Cc: Sagar Karandikar 
Cc: Bastian Koppelmann 
Cc: Alistair Francis 
Signed-off-by: Michael Clark 
Signed-off-by: Alistair Francis 
---
 disas/riscv.c | 138 --
 1 file changed, 138 deletions(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index 7fd1019623..27546dd790 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -87,33 +87,10 @@ typedef enum {
 
 typedef enum {
 rvc_end,
-rvc_simm_6,
-rvc_imm_6,
-rvc_imm_7,
-rvc_imm_8,
-rvc_imm_9,
-rvc_imm_10,
-rvc_imm_12,
-rvc_imm_18,
-rvc_imm_nz,
-rvc_imm_x2,
-rvc_imm_x4,
-rvc_imm_x8,
-rvc_imm_x16,
-rvc_rd_b3,
-rvc_rs1_b3,
-rvc_rs2_b3,
-rvc_rd_eq_rs1,
 rvc_rd_eq_ra,
-rvc_rd_eq_sp,
 rvc_rd_eq_x0,
-rvc_rs1_eq_sp,
 rvc_rs1_eq_x0,
 rvc_rs2_eq_x0,
-rvc_rd_ne_x0_x2,
-rvc_rd_ne_x0,
-rvc_rs1_ne_x0,
-rvc_rs2_ne_x0,
 rvc_rs2_eq_rs1,
 rvc_rs1_eq_ra,
 rvc_imm_eq_zero,
@@ -2522,111 +2499,16 @@ static bool check_constraints(rv_decode *dec, const 
rvc_constraint *c)
 uint8_t rd = dec->rd, rs1 = dec->rs1, rs2 = dec->rs2;
 while (*c != rvc_end) {
 switch (*c) {
-case rvc_simm_6:
-if (!(imm >= -32 && imm < 32)) {
-return false;
-}
-break;
-case rvc_imm_6:
-if (!(imm <= 63)) {
-return false;
-}
-break;
-case rvc_imm_7:
-if (!(imm <= 127)) {
-return false;
-}
-break;
-case rvc_imm_8:
-if (!(imm <= 255)) {
-return false;
-}
-break;
-case rvc_imm_9:
-if (!(imm <= 511)) {
-return false;
-}
-break;
-case rvc_imm_10:
-if (!(imm <= 1023)) {
-return false;
-}
-break;
-case rvc_imm_12:
-if (!(imm <= 4095)) {
-return false;
-}
-break;
-case rvc_imm_18:
-if (!(imm <= 262143)) {
-return false;
-}
-break;
-case rvc_imm_nz:
-if (!(imm != 0)) {
-return false;
-}
-break;
-case rvc_imm_x2:
-if (!((imm & 0b1) == 0)) {
-return false;
-}
-break;
-case rvc_imm_x4:
-if (!((imm & 0b11) == 0)) {
-return false;
-}
-break;
-case rvc_imm_x8:
-if (!((imm & 0b111) == 0)) {
-return false;
-}
-break;
-case rvc_imm_x16:
-if (!((imm & 0b) == 0)) {
-return false;
-}
-break;
-case rvc_rd_b3:
-if (!(rd  >= 8 && rd  <= 15)) {
-return false;
-}
-break;
-case rvc_rs1_b3:
-if (!(rs1 >= 8 && rs1 <= 15)) {
-return false;
-}
-break;
-case rvc_rs2_b3:
-if (!(rs2 >= 8 && rs2 <= 15)) {
-return false;
-}
-break;
-case rvc_rd_eq_rs1:
-if (!(rd == rs1)) {
-return false;
-}
-break;
 case rvc_rd_eq_ra:
 if (!(rd == 1)) {
 return false;
 }
 break;
-case rvc_rd_eq_sp:
-if (!(rd == 2)) {
-return false;
-}
-break;
 case rvc_rd_eq_x0:
 if (!(rd == 0)) {
 return false;
 }
 break;
-case rvc_rs1_eq_sp:
-if (!(rs1 == 2)) {
-return false;
-}
-break;
 case rvc_rs1_eq_x0:
 if (!(rs1 == 0)) {
 return false;
@@ -2637,26 +2519,6 @@ static bool check_constraints(rv_decode *dec, const 
rvc_constraint *c)
 return false;
 }
 break;
-case rvc_rd_ne_x0_x2:
-if (!(rd != 0 && rd != 2)) {
-return false;
-}
-break;
-case rvc_rd_ne_x0:
-if (!(rd != 0)) {
-return false;
-}
-break;
-case rvc_rs1_ne_x0:
-if (!(rs1 != 0)) {
-return false;
-}
-break;
-case rvc_rs2_ne_x0:
-if (!(rs2 != 0)) {
-return false;
-}
-break;
 case rvc_rs2_eq_rs1:
 if (!(rs2 == rs1)) {
 return false;
-- 
2.21.0

[Qemu-devel] [PATCH v1 09/12] RISC-V: Convert trap debugging to trace events

[Alistair Francis]

From: Michael Clark 

Cc: Palmer Dabbelt 
Cc: Alistair Francis 
Signed-off-by: Michael Clark 
Signed-off-by: Alistair Francis 
---
 Makefile.objs |  1 +
 target/riscv/cpu_helper.c | 12 +++-
 target/riscv/trace-events |  2 ++
 3 files changed, 6 insertions(+), 9 deletions(-)
 create mode 100644 target/riscv/trace-events

diff --git a/Makefile.objs b/Makefile.objs
index 72debbf5c5..cf065de5ed 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -186,6 +186,7 @@ trace-events-subdirs += target/hppa
 trace-events-subdirs += target/i386
 trace-events-subdirs += target/mips
 trace-events-subdirs += target/ppc
+trace-events-subdirs += target/riscv
 trace-events-subdirs += target/s390x
 trace-events-subdirs += target/sparc
 trace-events-subdirs += ui
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index a02f4dad8c..6d3fbc3401 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -22,8 +22,7 @@
 #include "cpu.h"
 #include "exec/exec-all.h"
 #include "tcg-op.h"
-
-#define RISCV_DEBUG_INTERRUPT 0
+#include "trace.h"
 
 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
 {
@@ -493,13 +492,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
 }
 }
 
-if (RISCV_DEBUG_INTERRUPT) {
-qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": %s %s, "
-"epc 0x" TARGET_FMT_lx ": tval 0x" TARGET_FMT_lx "\n",
-env->mhartid, async ? "intr" : "trap",
-(async ? riscv_intr_names : riscv_excp_names)[cause],
-env->pc, tval);
-}
+trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 16 ?
+(async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)");
 
 if (env->priv <= PRV_S &&
 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
diff --git a/target/riscv/trace-events b/target/riscv/trace-events
new file mode 100644
index 00..48af0373df
--- /dev/null
+++ b/target/riscv/trace-events
@@ -0,0 +1,2 @@
+# target/riscv/cpu_helper.c
+riscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t 
tval, const char *desc) "hart:%"PRId64", async:%d, cause:%"PRId64", 
epc:0x%"PRIx64", tval:0x%"PRIx64", desc=%s"
-- 
2.21.0

[Qemu-devel] [PATCH v1 06/12] RISC-V: linux-user support for RVE ABI

[Alistair Francis]

From: Kito Cheng 

This change checks elf_flags for EF_RISCV_RVE and if
present uses the RVE linux syscall ABI which uses t0
for the syscall number instead of a7.

Warn and exit if a non-RVE ABI binary is run on a
cpu with the RVE extension as it is incompatible.

Cc: Palmer Dabbelt 
Cc: Sagar Karandikar 
Cc: Bastian Koppelmann 
Cc: Alistair Francis 
Co-authored-by: Kito Cheng 
Co-authored-by: Michael Clark 
Signed-off-by: Michael Clark 
Signed-off-by: Alistair Francis 
---
 linux-user/riscv/cpu_loop.c | 15 ++-
 target/riscv/cpu.h  |  4 
 target/riscv/cpu_user.h |  3 ++-
 3 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
index 4cf3e94632..a9bac4ca79 100644
--- a/linux-user/riscv/cpu_loop.c
+++ b/linux-user/riscv/cpu_loop.c
@@ -18,8 +18,10 @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/error-report.h"
 #include "qemu.h"
 #include "cpu_loop-common.h"
+#include "elf.h"
 
 void cpu_loop(CPURISCVState *env)
 {
@@ -53,7 +55,8 @@ void cpu_loop(CPURISCVState *env)
 ret = 0;
 } else {
 ret = do_syscall(env,
- env->gpr[xA7],
+ env->gpr[(env->elf_flags & EF_RISCV_RVE)
+? xT0 : xA7],
  env->gpr[xA0],
  env->gpr[xA1],
  env->gpr[xA2],
@@ -113,6 +116,16 @@ void cpu_loop(CPURISCVState *env)
 
 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
 {
+CPUState *cpu = ENV_GET_CPU(env);
+TaskState *ts = cpu->opaque;
+struct image_info *info = ts->info;
+
 env->pc = regs->sepc;
 env->gpr[xSP] = regs->sp;
+env->elf_flags = info->elf_flags;
+
+if ((env->misa & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
+error_report("Incompatible ELF: RVE cpu requires RVE ABI binary");
+exit(EXIT_FAILURE);
+}
 }
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a0b3c22dec..8e4b5cfe26 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -123,6 +123,10 @@ struct CPURISCVState {
 
 uint32_t features;
 
+#ifdef CONFIG_USER_ONLY
+uint32_t elf_flags;
+#endif
+
 #ifndef CONFIG_USER_ONLY
 target_ulong priv;
 target_ulong resetvec;
diff --git a/target/riscv/cpu_user.h b/target/riscv/cpu_user.h
index c2199610ab..52d380aa98 100644
--- a/target/riscv/cpu_user.h
+++ b/target/riscv/cpu_user.h
@@ -10,4 +10,5 @@
 #define xA4 14
 #define xA5 15
 #define xA6 16
-#define xA7 17  /* syscall number goes here */
+#define xA7 17  /* syscall number for RVI ABI */
+#define xT0 5   /* syscall number for RVE ABI */
-- 
2.21.0

[Qemu-devel] [PATCH v1 03/12] RISC-V: Allow interrupt controllers to claim interrupts

[Alistair Francis]

From: Michael Clark 

We can't allow the supervisor to control SEIP as this would allow the
supervisor to clear a pending external interrupt which will result in
lost a interrupt in the case a PLIC is attached. The SEIP bit must be
hardware controlled when a PLIC is attached.

This logic was previously hard-coded so SEIP was always masked even
if no PLIC was attached. This patch adds riscv_cpu_claim_interrupts
so that the PLIC can register control of SEIP. In the case of models
without a PLIC (spike), the SEIP bit remains software controlled.

This interface allows for hardware control of supervisor timer and
software interrupts by other interrupt controller models.

Cc: Palmer Dabbelt 
Cc: Sagar Karandikar 
Cc: Bastian Koppelmann 
Cc: Alistair Francis 
Signed-off-by: Michael Clark 
Signed-off-by: Alistair Francis 
---
 hw/riscv/sifive_plic.c| 15 +++
 target/riscv/cpu.h|  2 ++
 target/riscv/cpu_helper.c | 11 +++
 target/riscv/csr.c| 10 ++
 4 files changed, 30 insertions(+), 8 deletions(-)

diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index b859f919a7..1c703e1a37 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -23,6 +23,7 @@
 #include "qemu/error-report.h"
 #include "hw/sysbus.h"
 #include "target/riscv/cpu.h"
+#include "sysemu/sysemu.h"
 #include "hw/riscv/sifive_plic.h"
 
 #define RISCV_DEBUG_PLIC 0
@@ -431,6 +432,7 @@ static void sifive_plic_irq_request(void *opaque, int irq, 
int level)
 static void sifive_plic_realize(DeviceState *dev, Error **errp)
 {
 SiFivePLICState *plic = SIFIVE_PLIC(dev);
+int i;
 
 memory_region_init_io(>mmio, OBJECT(dev), _plic_ops, plic,
   TYPE_SIFIVE_PLIC, plic->aperture_size);
@@ -443,6 +445,19 @@ static void sifive_plic_realize(DeviceState *dev, Error 
**errp)
 plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
 sysbus_init_mmio(SYS_BUS_DEVICE(dev), >mmio);
 qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
+
+/* We can't allow the supervisor to control SEIP as this would allow the
+ * supervisor to clear a pending external interrupt which will result in
+ * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
+ * hardware controlled when a PLIC is attached.
+ */
+for (i = 0; i < smp_cpus; i++) {
+RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
+if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
+error_report("SEIP already claimed");
+exit(1);
+}
+}
 }
 
 static void sifive_plic_class_init(ObjectClass *klass, void *data)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5c2aebf132..a0b3c22dec 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -140,6 +140,7 @@ struct CPURISCVState {
  * mip is 32-bits to allow atomic_read on 32-bit hosts.
  */
 uint32_t mip;
+uint32_t miclaim;
 
 target_ulong mie;
 target_ulong mideleg;
@@ -263,6 +264,7 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 #define cpu_mmu_index riscv_cpu_mmu_index
 
 #ifndef CONFIG_USER_ONLY
+int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
 #endif
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index f49e98ed59..555756d40c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -72,6 +72,17 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int 
interrupt_request)
 
 #if !defined(CONFIG_USER_ONLY)
 
+int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
+{
+CPURISCVState *env = >env;
+if (env->miclaim & interrupts) {
+return -1;
+} else {
+env->miclaim |= interrupts;
+return 0;
+}
+}
+
 /* iothread_mutex must be held */
 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
 {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 960d2b0aa9..938c10897c 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -550,16 +550,10 @@ static int rmw_mip(CPURISCVState *env, int csrno, 
target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
 {
 RISCVCPU *cpu = riscv_env_get_cpu(env);
-target_ulong mask = write_mask & delegable_ints;
+/* Allow software control of delegable interrupts not claimed by hardware 
*/
+target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
 uint32_t old_mip;
 
-/* We can't allow the supervisor to control SEIP as this would allow the
- * supervisor to clear a pending external interrupt which will result in
- * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
- * hardware controlled when a PLIC is attached. This should be an option
- * for CPUs with software-delegated Supervisor External 

[Qemu-devel] [PATCH v1 08/12] RISC-V: Add support for vectored interrupts

[Alistair Francis]

From: Michael Clark 

If vectored interrupts are enabled (bits[1:0]
of mtvec/stvec == 1) then use the following
logic for trap entry address calculation:

 pc = mtvec + cause * 4

In addition to adding support for vectored interrupts
this patch simplifies the interrupt delivery logic
by making sync/async cause decoding and encoding
steps distinct.

The cause code and the sign bit indicating sync/async
is split at the beginning of the function and fixed
cause is renamed to cause. The MSB setting for async
traps is delayed until setting mcause/scause to allow
redundant variables to be eliminated. Some variables
are renamed for conciseness and moved so that decls
are at the start of the block.

Cc: Palmer Dabbelt 
Cc: Alistair Francis 
Signed-off-by: Michael Clark 
Signed-off-by: Alistair Francis 
---
 target/riscv/cpu_helper.c | 145 ++
 target/riscv/csr.c|  12 ++--
 2 files changed, 60 insertions(+), 97 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 073bdcfe74..a02f4dad8c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -454,118 +454,81 @@ void riscv_cpu_do_interrupt(CPUState *cs)
 RISCVCPU *cpu = RISCV_CPU(cs);
 CPURISCVState *env = >env;
 
-if (RISCV_DEBUG_INTERRUPT) {
-int log_cause = cs->exception_index & RISCV_EXCP_INT_MASK;
-if (cs->exception_index & RISCV_EXCP_INT_FLAG) {
-qemu_log_mask(LOG_TRACE, "core "
-TARGET_FMT_ld ": trap %s, epc 0x" TARGET_FMT_lx "\n",
-env->mhartid, riscv_intr_names[log_cause], env->pc);
-} else {
-qemu_log_mask(LOG_TRACE, "core "
-TARGET_FMT_ld ": intr %s, epc 0x" TARGET_FMT_lx "\n",
-env->mhartid, riscv_excp_names[log_cause], env->pc);
+/* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
+ * so we mask off the MSB and separate into trap type and cause.
+ */
+bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
+target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
+target_ulong deleg = async ? env->mideleg : env->medeleg;
+target_ulong tval = 0;
+
+static const int ecall_cause_map[] = {
+[PRV_U] = RISCV_EXCP_U_ECALL,
+[PRV_S] = RISCV_EXCP_S_ECALL,
+[PRV_H] = RISCV_EXCP_H_ECALL,
+[PRV_M] = RISCV_EXCP_M_ECALL
+};
+
+if (!async) {
+/* set tval to badaddr for traps with address information */
+switch (cause) {
+case RISCV_EXCP_INST_ADDR_MIS:
+case RISCV_EXCP_INST_ACCESS_FAULT:
+case RISCV_EXCP_LOAD_ADDR_MIS:
+case RISCV_EXCP_STORE_AMO_ADDR_MIS:
+case RISCV_EXCP_LOAD_ACCESS_FAULT:
+case RISCV_EXCP_STORE_AMO_ACCESS_FAULT:
+case RISCV_EXCP_INST_PAGE_FAULT:
+case RISCV_EXCP_LOAD_PAGE_FAULT:
+case RISCV_EXCP_STORE_PAGE_FAULT:
+tval = env->badaddr;
+break;
+default:
+break;
 }
-}
-
-target_ulong fixed_cause = 0;
-if (cs->exception_index & (RISCV_EXCP_INT_FLAG)) {
-/* hacky for now. the MSB (bit 63) indicates interrupt but 
cs->exception
-   index is only 32 bits wide */
-fixed_cause = cs->exception_index & RISCV_EXCP_INT_MASK;
-fixed_cause |= ((target_ulong)1) << (TARGET_LONG_BITS - 1);
-} else {
-/* fixup User ECALL -> correct priv ECALL */
-if (cs->exception_index == RISCV_EXCP_U_ECALL) {
-switch (env->priv) {
-case PRV_U:
-fixed_cause = RISCV_EXCP_U_ECALL;
-break;
-case PRV_S:
-fixed_cause = RISCV_EXCP_S_ECALL;
-break;
-case PRV_H:
-fixed_cause = RISCV_EXCP_H_ECALL;
-break;
-case PRV_M:
-fixed_cause = RISCV_EXCP_M_ECALL;
-break;
-}
-} else {
-fixed_cause = cs->exception_index;
+/* ecall is dispatched as one cause so translate based on mode */
+if (cause == RISCV_EXCP_U_ECALL) {
+assert(env->priv <= 3);
+cause = ecall_cause_map[env->priv];
 }
 }
 
-target_ulong backup_epc = env->pc;
-
-target_ulong bit = fixed_cause;
-target_ulong deleg = env->medeleg;
-
-int hasbadaddr =
-(fixed_cause == RISCV_EXCP_INST_ADDR_MIS) ||
-(fixed_cause == RISCV_EXCP_INST_ACCESS_FAULT) ||
-(fixed_cause == RISCV_EXCP_LOAD_ADDR_MIS) ||
-(fixed_cause == RISCV_EXCP_STORE_AMO_ADDR_MIS) ||
-(fixed_cause == RISCV_EXCP_LOAD_ACCESS_FAULT) ||
-(fixed_cause == RISCV_EXCP_STORE_AMO_ACCESS_FAULT) ||
-(fixed_cause == RISCV_EXCP_INST_PAGE_FAULT) ||
-(fixed_cause == RISCV_EXCP_LOAD_PAGE_FAULT) ||
-(fixed_cause == RISCV_EXCP_STORE_PAGE_FAULT);
-
-if (bit & ((target_ulong)1 << (TARGET_LONG_BITS - 1))) {
-deleg = 

[Qemu-devel] [PATCH v1 07/12] RISC-V: Change local interrupts from edge to level

[Alistair Francis]

From: Michael Clark 

This effectively changes riscv_cpu_update_mip
from edge to level. i.e. cpu_interrupt or
cpu_reset_interrupt are called regardless of
the current interrupt level.

Fixes WFI doesn't return when a IPI is issued:

- https://github.com/riscv/riscv-qemu/issues/132

To test:

1) Apply RISC-V Linux CPU hotplug patch:

- http://lists.infradead.org/pipermail/linux-riscv/2018-May/000603.html

2) Enable CONFIG_CPU_HOTPLUG in linux .config

3) Try to offline and online cpus:

  echo 1 > /sys/devices/system/cpu/cpu2/online
  echo 0 > /sys/devices/system/cpu/cpu2/online
  echo 1 > /sys/devices/system/cpu/cpu2/online

Reported-by: Atish Patra 
Cc: Atish Patra 
Cc: Alistair Francis 
Signed-off-by: Michael Clark 
Signed-off-by: Alistair Francis 
---
 target/riscv/cpu_helper.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 555756d40c..073bdcfe74 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -95,9 +95,9 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, 
uint32_t value)
 cmp = atomic_cmpxchg(>mip, old, new);
 } while (old != cmp);
 
-if (new && !old) {
+if (new) {
 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
-} else if (!new && old) {
+} else {
 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
 }
 
-- 
2.21.0

[Qemu-devel] [PATCH v1 12/12] target/riscv: Remove unused struct

[Alistair Francis]

Signed-off-by: Alistair Francis 
---
 target/riscv/cpu.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cc3ddc0ae4..568c4cd637 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -80,12 +80,6 @@ const char * const riscv_intr_names[] = {
 "reserved"
 };
 
-typedef struct RISCVCPUInfo {
-const int bit_widths;
-const char *name;
-void (*initfn)(Object *obj);
-} RISCVCPUInfo;
-
 static void set_misa(CPURISCVState *env, target_ulong misa)
 {
 env->misa_mask = env->misa = misa;
-- 
2.21.0

[Qemu-devel] [PATCH v1 05/12] elf: Add RISC-V PSABI ELF header defines

[Alistair Francis]

From: Michael Clark 

Refer to the RISC-V PSABI specification for details:

- https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md

Cc: Michael Tokarev 
Cc: Richard Henderson 
Cc: Alistair Francis 
Reviewed-by: Laurent Vivier 
Signed-off-by: Michael Clark 
Signed-off-by: Alistair Francis 
---
 include/elf.h | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/include/elf.h b/include/elf.h
index b35347eee7..ea7708a4ea 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -1393,6 +1393,16 @@ typedef struct {
 #define R_RISCV_SET16 55
 #define R_RISCV_SET32 56
 
+/* RISC-V ELF Flags.  */
+#define EF_RISCV_RVC  0x0001
+#define EF_RISCV_FLOAT_ABI0x0006
+#define EF_RISCV_FLOAT_ABI_SOFT   0x
+#define EF_RISCV_FLOAT_ABI_SINGLE 0x0002
+#define EF_RISCV_FLOAT_ABI_DOUBLE 0x0004
+#define EF_RISCV_FLOAT_ABI_QUAD   0x0006
+#define EF_RISCV_RVE  0x0008
+#define EF_RISCV_TSO  0x0010
+
 typedef struct elf32_rel {
   Elf32_Addr   r_offset;
   Elf32_Word   r_info;
-- 
2.21.0

[Qemu-devel] [PATCH v1 11/12] riscv: sifive_u: Allow up to 4 CPUs to be created

[Alistair Francis]

Signed-off-by: Alistair Francis 
---
 hw/riscv/sifive_u.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7bc25820fe..3199238ba0 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -398,7 +398,10 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
 {
 mc->desc = "RISC-V Board compatible with SiFive U SDK";
 mc->init = riscv_sifive_u_init;
-mc->max_cpus = 1;
+/* The real hardware has 5 CPUs, but one of them is a small embedded power
+ * management CPU.
+ */
+mc->max_cpus = 4;
 }
 
 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
-- 
2.21.0

[Qemu-devel] [PATCH v1 10/12] RISC-V: Update load reservation comment in do_interrupt

[Alistair Francis]

From: Michael Clark 

Cc: Palmer Dabbelt 
Cc: Alistair Francis 
Signed-off-by: Michael Clark 
Signed-off-by: Alistair Francis 
---
 target/riscv/cpu_helper.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 6d3fbc3401..b17f169681 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -525,7 +525,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
 riscv_cpu_set_mode(env, PRV_M);
 }
-/* TODO yield load reservation  */
+
+/* NOTE: it is not necessary to yield load reservations here. It is only
+ * necessary for an SC from "another hart" to cause a load reservation
+ * to be yielded. Refer to the memory consistency model section of the
+ * RISC-V ISA Specification.
+ */
+
 #endif
 cs->exception_index = EXCP_NONE; /* mark handled to qemu */
 }
-- 
2.21.0

Re: [Qemu-devel] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4

[Alistair Francis]

On Fri, Mar 15, 2019 at 6:19 PM Alistair Francis
 wrote:
>
> v3:
>  - Add a patch to remove some dead code
>  - Rebase on master
> v2:
>  - Add a patch for SiFive U SMP support
>  - Rebase on master
>
> Alistair Francis (3):
>   riscv: pmp: Log pmp access errors as guest errors
>   riscv: sifive_u: Allow up to 4 CPUs to be created
>   target/riscv: Remove unused struct
>
> Kito Cheng (1):
>   RISC-V: linux-user support for RVE ABI
>
> Michael Clark (8):
>   RISC-V: Replace __builtin_popcount with ctpop8 in PLIC
>   RISC-V: Allow interrupt controllers to claim interrupts
>   RISC-V: Remove unnecessary disassembler constraints
>   elf: Add RISC-V PSABI ELF header defines
>   RISC-V: Change local interrupts from edge to level
>   RISC-V: Add support for vectored interrupts
>   RISC-V: Convert trap debugging to trace events
>   RISC-V: Update load reservation comment in do_interrupt

Sorry, this series should be v3 in the title. I won't resend it, just pretend :)

Alistair

>
>  Makefile.objs   |   1 +
>  disas/riscv.c   | 138 -
>  hw/riscv/sifive_plic.c  |  19 +++-
>  hw/riscv/sifive_u.c |   5 +-
>  include/elf.h   |  10 +++
>  linux-user/riscv/cpu_loop.c |  15 +++-
>  target/riscv/cpu.c  |   6 --
>  target/riscv/cpu.h  |   6 ++
>  target/riscv/cpu_helper.c   | 168 +++-
>  target/riscv/cpu_user.h |   3 +-
>  target/riscv/csr.c  |  22 ++---
>  target/riscv/pmp.c  |  20 +++--
>  target/riscv/trace-events   |   2 +
>  13 files changed, 148 insertions(+), 267 deletions(-)
>  create mode 100644 target/riscv/trace-events
>
> --
> 2.21.0
>

Re: [Qemu-devel] [PATCH v3 0/2] ati-vga: Implement DDC and EDID info from monitor

[no-reply]

Patchew URL: https://patchew.org/QEMU/cover.1552689690.git.bala...@eik.bme.hu/



Hi,

This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.

=== TEST SCRIPT BEGIN ===
#!/bin/bash
time make docker-test-debug@fedora TARGET_LIST=x86_64-softmmu J=14 NETWORK=1
=== TEST SCRIPT END ===

PASS 1 fdc-test /x86_64/fdc/cmos
PASS 2 fdc-test /x86_64/fdc/no_media_on_start
PASS 3 fdc-test /x86_64/fdc/read_without_media
==7575==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
PASS 4 fdc-test /x86_64/fdc/media_change
PASS 5 fdc-test /x86_64/fdc/sense_interrupt
PASS 6 fdc-test /x86_64/fdc/relative_seek
---
PASS 32 test-opts-visitor /visitor/opts/range/beyond
PASS 33 test-opts-visitor /visitor/opts/dict/unvisited
MALLOC_PERTURB_=${MALLOC_PERTURB_:-$(( ${RANDOM:-0} % 255 + 1))}  
tests/test-coroutine -m=quick -k --tap < /dev/null | ./scripts/tap-driver.pl 
--test-name="test-coroutine" 
==7619==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
==7619==WARNING: ASan is ignoring requested __asan_handle_no_return: stack top: 
0x7ffc910dc000; bottom 0x7fb0c47f8000; size: 0x004bcc8e4000 (325554421760)
False positive error reports may follow
For details see https://github.com/google/sanitizers/issues/189
PASS 1 test-coroutine /basic/no-dangling-access
---
PASS 11 test-aio /aio/event/wait
PASS 12 test-aio /aio/event/flush
PASS 13 test-aio /aio/event/wait/no-flush-cb
==7634==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
PASS 14 test-aio /aio/timer/schedule
PASS 15 test-aio /aio/coroutine/queue-chaining
PASS 16 test-aio /aio-gsource/flush
---
MALLOC_PERTURB_=${MALLOC_PERTURB_:-$(( ${RANDOM:-0} % 255 + 1))}  
QTEST_QEMU_BINARY=x86_64-softmmu/qemu-system-x86_64 QTEST_QEMU_IMG=qemu-img 
tests/ide-test -m=quick -k --tap < /dev/null | ./scripts/tap-driver.pl 
--test-name="ide-test" 
PASS 28 test-aio /aio-gsource/timer/schedule
MALLOC_PERTURB_=${MALLOC_PERTURB_:-$(( ${RANDOM:-0} % 255 + 1))}  
tests/test-aio-multithread -m=quick -k --tap < /dev/null | 
./scripts/tap-driver.pl --test-name="test-aio-multithread" 
==7643==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
==7649==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
PASS 1 test-aio-multithread /aio/multi/lifecycle
PASS 1 ide-test /x86_64/ide/identify
PASS 2 test-aio-multithread /aio/multi/schedule
==7664==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
PASS 2 ide-test /x86_64/ide/flush
PASS 3 test-aio-multithread /aio/multi/mutex/contended
==7675==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
PASS 3 ide-test /x86_64/ide/bmdma/setup
PASS 4 ide-test /x86_64/ide/bmdma/simple_rw
PASS 5 ide-test /x86_64/ide/bmdma/trim
PASS 6 ide-test /x86_64/ide/bmdma/short_prdt
PASS 7 ide-test /x86_64/ide/bmdma/one_sector_short_prdt
PASS 8 ide-test /x86_64/ide/bmdma/long_prdt
==7675==WARNING: ASan is ignoring requested __asan_handle_no_return: stack top: 
0x7ffc7aed8000; bottom 0x7fa3ab4f9000; size: 0x0058cf9df000 (381440356352)
False positive error reports may follow
For details see https://github.com/google/sanitizers/issues/189
PASS 9 ide-test /x86_64/ide/bmdma/no_busmaster
PASS 10 ide-test /x86_64/ide/bmdma/teardown
PASS 11 ide-test /x86_64/ide/flush/nodev
==7691==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
PASS 12 ide-test /x86_64/ide/flush/empty_drive
==7696==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
PASS 4 test-aio-multithread /aio/multi/mutex/handoff
PASS 13 ide-test /x86_64/ide/flush/retry_pci
==7707==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
PASS 5 test-aio-multithread /aio/multi/mutex/mcs
PASS 14 ide-test /x86_64/ide/flush/retry_isa
==7718==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
PASS 6 test-aio-multithread /aio/multi/mutex/pthread
MALLOC_PERTURB_=${MALLOC_PERTURB_:-$(( ${RANDOM:-0} % 255 + 1))}  
tests/test-throttle -m=quick -k --tap < /dev/null | ./scripts/tap-driver.pl 
--test-name="test-throttle" 
==7726==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
PASS 1 test-throttle /throttle/leak_bucket
PASS 2 test-throttle /throttle/compute_wait
PASS 3 test-throttle /throttle/init
---
PASS 15 test-throttle /throttle/config/iops_size
PASS 15 

[Qemu-devel] [PATCH v3 0/2] ati-vga: Implement DDC and EDID info from monitor

[BALATON Zoltan]

Version 3 keeps bitbang_i2c.h and moves it to include/hw/i2c/
otherwise same as version 2.

BALATON Zoltan (2):
  i2c: Move bitbang_i2c.h to include/hw/i2c/
  ati-vga: Implement DDC and EDID info from monitor

 hw/display/Kconfig   |  2 ++
 hw/display/ati.c | 43 ++--
 hw/display/ati_int.h |  4 
 hw/display/ati_regs.h|  1 +
 hw/i2c/bitbang_i2c.c |  2 +-
 hw/i2c/ppc4xx_i2c.c  |  1 -
 hw/i2c/versatile_i2c.c   |  2 +-
 {hw => include/hw}/i2c/bitbang_i2c.h |  2 ++
 include/hw/i2c/i2c.h |  2 --
 include/hw/i2c/ppc4xx_i2c.h  |  2 +-
 10 files changed, 53 insertions(+), 8 deletions(-)
 rename {hw => include/hw}/i2c/bitbang_i2c.h (80%)

-- 
2.13.7

[Qemu-devel] [PATCH v3 2/2] ati-vga: Implement DDC and EDID info from monitor

[BALATON Zoltan]

This adds DDC support to ati-vga and connects i2c-ddc to provide EDID
info that is read by guests to find available screen modes. Not sure
if this is 100% correct yet but at least MorphOS is happy with it and
starts in a high resolution mode instead of 640x480 (although its
splash screen is still not correct). Linux needs support from VESA
vgabios, it seems to be missing INT10 0x4F15 function (see
https://gitlab.freedesktop.org/xorg/xserver/blob/master/hw/xfree86/vbe/vbe.c)
without which no DDC is available that also prevents loading the
accelerated X driver.

Besides, this depends on bitbang_i2c.h which is now in hw/i2c so if
including it from there is not desirable that may need to be moved
somewhere.

Signed-off-by: BALATON Zoltan 
---
 hw/display/Kconfig|  2 ++
 hw/display/ati.c  | 43 +--
 hw/display/ati_int.h  |  4 
 hw/display/ati_regs.h |  1 +
 4 files changed, 48 insertions(+), 2 deletions(-)

diff --git a/hw/display/Kconfig b/hw/display/Kconfig
index 86c1d544c5..f8d65802a9 100644
--- a/hw/display/Kconfig
+++ b/hw/display/Kconfig
@@ -112,3 +112,5 @@ config ATI_VGA
 default y if PCI_DEVICES
 depends on PCI
 select VGA
+select BITBANG_I2C
+select DDC
diff --git a/hw/display/ati.c b/hw/display/ati.c
index 8322f52aff..bef00afd2c 100644
--- a/hw/display/ati.c
+++ b/hw/display/ati.c
@@ -24,6 +24,7 @@
 #include "qapi/error.h"
 #include "hw/hw.h"
 #include "ui/console.h"
+#include "hw/i2c/i2c-ddc.h"
 #include "trace.h"
 
 #define ATI_DEBUG_HW_CURSOR 0
@@ -267,7 +268,12 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr, 
unsigned int size)
 case DAC_CNTL:
 val = s->regs.dac_cntl;
 break;
-/*case GPIO_MONID: FIXME hook up DDC I2C here */
+case GPIO_DVI_DDC:
+val = s->regs.gpio_dvi_ddc;
+break;
+case GPIO_MONID:
+val = s->regs.gpio_monid;
+break;
 case PALETTE_INDEX:
 /* FIXME unaligned access */
 val = vga_ioport_read(>vga, VGA_PEL_IR) << 16;
@@ -501,7 +507,34 @@ static void ati_mm_write(void *opaque, hwaddr addr,
 s->regs.dac_cntl = data & 0xe3ff;
 s->vga.dac_8bit = !!(data & DAC_8BIT_EN);
 break;
-/*case GPIO_MONID: FIXME hook up DDC I2C here */
+case GPIO_DVI_DDC:
+if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
+break;
+}
+s->regs.gpio_dvi_ddc = data & 0xf000f;
+if (data & BIT(17)) {
+s->regs.gpio_dvi_ddc |= !!(data & BIT(1)) << 9;
+bitbang_i2c_set(s->bbi2c, BITBANG_I2C_SCL, (data & BIT(1)) != 0);
+}
+if (data & BIT(16)) {
+s->regs.gpio_dvi_ddc |= bitbang_i2c_set(s->bbi2c, BITBANG_I2C_SDA,
+data & BIT(0)) << 8;
+}
+break;
+case GPIO_MONID:
+if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) {
+break; /* FIXME What does Radeon have here? */
+}
+s->regs.gpio_monid = data & 0x0f0f000f;
+if (data & BIT(2) << 24) {
+s->regs.gpio_monid |= !!(data & BIT(2)) << 10;
+bitbang_i2c_set(s->bbi2c, BITBANG_I2C_SCL, (data & BIT(2)) != 0);
+}
+if (data & BIT(1) << 24) {
+s->regs.gpio_monid |= bitbang_i2c_set(s->bbi2c, BITBANG_I2C_SDA,
+  (data & BIT(1)) != 0) << 9;
+}
+break;
 case PALETTE_INDEX ... PALETTE_INDEX + 3:
 if (size == 4) {
 vga_ioport_write(>vga, VGA_PEL_IR, (data >> 16) & 0xff);
@@ -792,6 +825,12 @@ static void ati_vga_realize(PCIDevice *dev, Error **errp)
 vga->cursor_draw_line = ati_cursor_draw_line;
 }
 
+/* ddc, edid */
+I2CBus *i2cbus = i2c_init_bus(DEVICE(s), "ati-vga.ddc");
+s->bbi2c = bitbang_i2c_init(i2cbus);
+I2CSlave *i2cddc = I2C_SLAVE(qdev_create(BUS(i2cbus), TYPE_I2CDDC));
+i2c_set_slave_address(i2cddc, 0x50);
+
 /* mmio register space */
 memory_region_init_io(>mm, OBJECT(s), _mm_ops, s,
   "ati.mmregs", 0x4000);
diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h
index a6f3e20e63..bad1846c76 100644
--- a/hw/display/ati_int.h
+++ b/hw/display/ati_int.h
@@ -11,6 +11,7 @@
 
 #include "qemu/osdep.h"
 #include "hw/pci/pci.h"
+#include "hw/i2c/bitbang_i2c.h"
 #include "vga_int.h"
 
 /*#define DEBUG_ATI*/
@@ -36,6 +37,8 @@ typedef struct ATIVGARegs {
 uint32_t crtc_gen_cntl;
 uint32_t crtc_ext_cntl;
 uint32_t dac_cntl;
+uint32_t gpio_dvi_ddc;
+uint32_t gpio_monid;
 uint32_t crtc_h_total_disp;
 uint32_t crtc_h_sync_strt_wid;
 uint32_t crtc_v_total_disp;
@@ -84,6 +87,7 @@ typedef struct ATIVGAState {
 uint16_t cursor_size;
 uint32_t cursor_offset;
 QEMUCursor *cursor;
+bitbang_i2c_interface *bbi2c;
 MemoryRegion io;
 MemoryRegion mm;
 ATIVGARegs regs;
diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h
index 

[Qemu-devel] [PATCH v3 1/2] i2c: Move bitbang_i2c.h to include/hw/i2c/

[BALATON Zoltan]

The bitbang i2c implementation is also useful for other device models
such as DDC in display controllers. Move the header to include/hw/i2c/
to allow it to be used from other device models and adjust users of
this include. This also reverts commit 2b4c1125ac which is no longer
needed.

Signed-off-by: BALATON Zoltan 
---
 hw/i2c/bitbang_i2c.c | 2 +-
 hw/i2c/ppc4xx_i2c.c  | 1 -
 hw/i2c/versatile_i2c.c   | 2 +-
 {hw => include/hw}/i2c/bitbang_i2c.h | 2 ++
 include/hw/i2c/i2c.h | 2 --
 include/hw/i2c/ppc4xx_i2c.h  | 2 +-
 6 files changed, 5 insertions(+), 6 deletions(-)
 rename {hw => include/hw}/i2c/bitbang_i2c.h (80%)

diff --git a/hw/i2c/bitbang_i2c.c b/hw/i2c/bitbang_i2c.c
index 8be88ee265..b3534a3bd4 100644
--- a/hw/i2c/bitbang_i2c.c
+++ b/hw/i2c/bitbang_i2c.c
@@ -11,7 +11,7 @@
  */
 #include "qemu/osdep.h"
 #include "hw/hw.h"
-#include "bitbang_i2c.h"
+#include "hw/i2c/bitbang_i2c.h"
 #include "hw/sysbus.h"
 
 //#define DEBUG_BITBANG_I2C
diff --git a/hw/i2c/ppc4xx_i2c.c b/hw/i2c/ppc4xx_i2c.c
index d6dfafab31..a907d0194e 100644
--- a/hw/i2c/ppc4xx_i2c.c
+++ b/hw/i2c/ppc4xx_i2c.c
@@ -30,7 +30,6 @@
 #include "cpu.h"
 #include "hw/hw.h"
 #include "hw/i2c/ppc4xx_i2c.h"
-#include "bitbang_i2c.h"
 
 #define PPC4xx_I2C_MEM_SIZE 18
 
diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c
index da9f298ee5..39cbcf1948 100644
--- a/hw/i2c/versatile_i2c.c
+++ b/hw/i2c/versatile_i2c.c
@@ -23,7 +23,7 @@
 
 #include "qemu/osdep.h"
 #include "hw/sysbus.h"
-#include "bitbang_i2c.h"
+#include "hw/i2c/bitbang_i2c.h"
 #include "qemu/log.h"
 
 #define TYPE_VERSATILE_I2C "versatile_i2c"
diff --git a/hw/i2c/bitbang_i2c.h b/include/hw/i2c/bitbang_i2c.h
similarity index 80%
rename from hw/i2c/bitbang_i2c.h
rename to include/hw/i2c/bitbang_i2c.h
index 9443021710..3a7126d5de 100644
--- a/hw/i2c/bitbang_i2c.h
+++ b/include/hw/i2c/bitbang_i2c.h
@@ -3,6 +3,8 @@
 
 #include "hw/i2c/i2c.h"
 
+typedef struct bitbang_i2c_interface bitbang_i2c_interface;
+
 #define BITBANG_I2C_SDA 0
 #define BITBANG_I2C_SCL 1
 
diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
index 8e236f7bb4..75c5bd638b 100644
--- a/include/hw/i2c/i2c.h
+++ b/include/hw/i2c/i2c.h
@@ -81,8 +81,6 @@ uint8_t i2c_recv(I2CBus *bus);
 
 DeviceState *i2c_create_slave(I2CBus *bus, const char *name, uint8_t addr);
 
-typedef struct bitbang_i2c_interface bitbang_i2c_interface;
-
 /* lm832x.c */
 void lm832x_key_event(DeviceState *dev, int key, int state);
 
diff --git a/include/hw/i2c/ppc4xx_i2c.h b/include/hw/i2c/ppc4xx_i2c.h
index b3450bacf7..368a5598fe 100644
--- a/include/hw/i2c/ppc4xx_i2c.h
+++ b/include/hw/i2c/ppc4xx_i2c.h
@@ -29,7 +29,7 @@
 
 #include "qemu-common.h"
 #include "hw/sysbus.h"
-#include "hw/i2c/i2c.h"
+#include "hw/i2c/bitbang_i2c.h"
 
 #define TYPE_PPC4xx_I2C "ppc4xx-i2c"
 #define PPC4xx_I2C(obj) OBJECT_CHECK(PPC4xxI2CState, (obj), TYPE_PPC4xx_I2C)
-- 
2.13.7

Re: [Qemu-devel] [PATCH v2 0/2] ati-vga: Implement DDC and EDID info from monitor

[no-reply]

Patchew URL: https://patchew.org/QEMU/cover.1552659955.git.bala...@eik.bme.hu/



Hi,

This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.

=== TEST SCRIPT BEGIN ===
#!/bin/bash
time make docker-test-debug@fedora TARGET_LIST=x86_64-softmmu J=14 NETWORK=1
=== TEST SCRIPT END ===

PASS 1 fdc-test /x86_64/fdc/cmos
PASS 2 fdc-test /x86_64/fdc/no_media_on_start
PASS 3 fdc-test /x86_64/fdc/read_without_media
==7548==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
PASS 4 fdc-test /x86_64/fdc/media_change
PASS 5 fdc-test /x86_64/fdc/sense_interrupt
PASS 6 fdc-test /x86_64/fdc/relative_seek
---
PASS 32 test-opts-visitor /visitor/opts/range/beyond
PASS 33 test-opts-visitor /visitor/opts/dict/unvisited
MALLOC_PERTURB_=${MALLOC_PERTURB_:-$(( ${RANDOM:-0} % 255 + 1))}  
tests/test-coroutine -m=quick -k --tap < /dev/null | ./scripts/tap-driver.pl 
--test-name="test-coroutine" 
==7611==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
PASS 1 test-coroutine /basic/no-dangling-access
PASS 2 test-coroutine /basic/lifecycle
==7611==WARNING: ASan is ignoring requested __asan_handle_no_return: stack top: 
0x7ffe17f06000; bottom 0x7fe2ce8f8000; size: 0x001b4960e000 (117195202560)
False positive error reports may follow
For details see https://github.com/google/sanitizers/issues/189
PASS 3 test-coroutine /basic/yield
---
PASS 11 test-aio /aio/event/wait
PASS 12 test-aio /aio/event/flush
PASS 13 test-aio /aio/event/wait/no-flush-cb
==7626==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
PASS 14 test-aio /aio/timer/schedule
PASS 15 test-aio /aio/coroutine/queue-chaining
PASS 16 test-aio /aio-gsource/flush
---
PASS 12 fdc-test /x86_64/fdc/read_no_dma_19
PASS 13 fdc-test /x86_64/fdc/fuzz-registers
MALLOC_PERTURB_=${MALLOC_PERTURB_:-$(( ${RANDOM:-0} % 255 + 1))}  
QTEST_QEMU_BINARY=x86_64-softmmu/qemu-system-x86_64 QTEST_QEMU_IMG=qemu-img 
tests/ide-test -m=quick -k --tap < /dev/null | ./scripts/tap-driver.pl 
--test-name="ide-test" 
==7635==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
PASS 28 test-aio /aio-gsource/timer/schedule
MALLOC_PERTURB_=${MALLOC_PERTURB_:-$(( ${RANDOM:-0} % 255 + 1))}  
tests/test-aio-multithread -m=quick -k --tap < /dev/null | 
./scripts/tap-driver.pl --test-name="test-aio-multithread" 
PASS 1 ide-test /x86_64/ide/identify
==7643==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
PASS 1 test-aio-multithread /aio/multi/lifecycle
==7645==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
PASS 2 ide-test /x86_64/ide/flush
PASS 2 test-aio-multithread /aio/multi/schedule
==7662==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
PASS 3 ide-test /x86_64/ide/bmdma/setup
PASS 4 ide-test /x86_64/ide/bmdma/simple_rw
PASS 5 ide-test /x86_64/ide/bmdma/trim
PASS 6 ide-test /x86_64/ide/bmdma/short_prdt
PASS 7 ide-test /x86_64/ide/bmdma/one_sector_short_prdt
PASS 8 ide-test /x86_64/ide/bmdma/long_prdt
==7662==WARNING: ASan is ignoring requested __asan_handle_no_return: stack top: 
0x7ffd7817b000; bottom 0x7fa7738f9000; size: 0x005604882000 (369443217408)
False positive error reports may follow
For details see https://github.com/google/sanitizers/issues/189
PASS 9 ide-test /x86_64/ide/bmdma/no_busmaster
PASS 3 test-aio-multithread /aio/multi/mutex/contended
PASS 10 ide-test /x86_64/ide/bmdma/teardown
PASS 11 ide-test /x86_64/ide/flush/nodev
==7683==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
PASS 12 ide-test /x86_64/ide/flush/empty_drive
==7688==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
PASS 4 test-aio-multithread /aio/multi/mutex/handoff
PASS 13 ide-test /x86_64/ide/flush/retry_pci
==7699==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
PASS 5 test-aio-multithread /aio/multi/mutex/mcs
PASS 14 ide-test /x86_64/ide/flush/retry_isa
==7710==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false positives in some cases!
PASS 6 test-aio-multithread /aio/multi/mutex/pthread
PASS 15 ide-test /x86_64/ide/cdrom/pio
MALLOC_PERTURB_=${MALLOC_PERTURB_:-$(( ${RANDOM:-0} % 255 + 1))}  
tests/test-throttle -m=quick -k --tap < /dev/null | ./scripts/tap-driver.pl 
--test-name="test-throttle" 
==7719==WARNING: ASan doesn't fully support makecontext/swapcontext functions 
and may produce false 

Re: [Qemu-devel] [PATCH] xen-mapcache: use MAP_FIXED flag so the mmap address hint is always honored

[Igor Druzhinin]

On 15/03/2019 18:38, Anthony PERARD wrote:
> On Fri, Mar 15, 2019 at 06:14:09PM +, Anthony PERARD wrote:
>> On Fri, Mar 15, 2019 at 09:58:47AM +0100, Roger Pau Monne wrote:
>>> Or if it's not possible to honor the hinted address an error is returned
>>> instead. This makes it easier to spot the actual failure, instead of
>>> failing later on when the caller of xen_remap_bucket realizes the
>>> mapping has not been created at the requested address.
>>>
>>> Also note that at least on FreeBSD using MAP_FIXED will cause mmap to
>>> try harder to honor the passed address.
>>>
>>> Signed-off-by: Roger Pau Monné 
>>
>> The patch looks fine, and MAP_FIXED seems to be the expected behavior
>> even on Linux.
>>
>> Acked-by: Anthony PERARD 
>>
>>> diff --git a/hw/i386/xen/xen-mapcache.c b/hw/i386/xen/xen-mapcache.c
>>> @@ -185,8 +185,14 @@ static void xen_remap_bucket(MapCacheEntry *entry,
>>>  }
>>>  
>>>  if (!dummy) {
>>> +/*
>>> + * If the caller has requested the mapping at a specific address 
>>> use
>>> + * MAP_FIXED to make sure it's honored. Note that with MAP_FIXED at
>>> + * least FreeBSD will try harder to honor the passed address.
>>> + */
>>>  vaddr_base = xenforeignmemory_map2(xen_fmem, xen_domid, vaddr,
>>> -   PROT_READ | PROT_WRITE, 0,
>>> +   PROT_READ | PROT_WRITE,
>>> +   vaddr ? MAP_FIXED : 0,
>>> nb_pfn, pfns, err);
> 
> I've noticed that there's a mmap call just after which has also vaddr as
> hint, should that second call also have MAP_FIXED as flags?

I think so, yes. The intended usage of xen_remap_bucket() is to create a
mapcache entry - either dummy or real. So this patch fixes the present
problem for real entry now but not for dummy. In future, there might be
xen_remap_bucket() calls to create dummy entries at a predefined
location so, I think, MAP_FIXED should be passed to mmap() call as well.

Igor

Re: [Qemu-devel] [PATCH for-4.0?] arm: Allow system registers for KVM guests to be changed by QEMU code

[Philippe Mathieu-Daudé]

On 3/15/19 3:30 PM, Peter Maydell wrote:
> At the moment the Arm implementations of kvm_arch_{get,put}_registers()
> don't support having QEMU change the values of system registers
> (aka coprocessor registers for AArch32). This is because although
> kvm_arch_get_registers() calls write_list_to_cpustate() to
> update the CPU state struct fields (so QEMU code can read the
> values in the usual way), kvm_arch_put_registers() does not
> call write_cpustate_to_list(), meaning that any changes to
> the CPU state struct fields will not be passed back to KVM.
> 
> The rationale for this design is documented in a comment in the
> AArch32 kvm_arch_put_registers() -- writing the values in the
> cpregs list into the CPU state struct is "lossy" because the
> write of a register might not succeed, and so if we blindly
> copy the CPU state values back again we will incorrectly
> change register values for the guest. The assumption was that
> no QEMU code would need to write to the registers.
> 
> However, when we implemented debug support for KVM guests, we
> broke that assumption: the code to handle "set the guest up
> to take a breakpoint exception" does so by updating various
> guest registers including ESR_EL1.
> 
> Support this by making kvm_arch_put_registers() synchronize
> CPU state back into the list. We sync only those registers
> where the initial write succeeds, which should be sufficient.
> 
> This commit is the same as commit 823e1b3818f9b10b824ddc which we
> had to revert in commit 942f99c825fc94c8b1a4, except that the bug
> which was preventing EDK2 guest firmware running has been fixed:
> kvm_arm_reset_vcpu() now calls write_list_to_cpustate().
> 
> Signed-off-by: Peter Maydell 
> ---
> Should we try to put this in for rc1? Not sure... Testing
> definitely appreciated.

You might include it for rc1 and we still have rc2/rc3 to revert it.

> 
> ---
>  target/arm/cpu.h |  9 -
>  target/arm/helper.c  | 27 +--
>  target/arm/kvm.c |  8 
>  target/arm/kvm32.c   | 20 ++--
>  target/arm/kvm64.c   |  2 ++
>  target/arm/machine.c |  2 +-
>  6 files changed, 46 insertions(+), 22 deletions(-)
> 
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 5f23c621325..82f40a7ea90 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -2559,18 +2559,25 @@ bool write_list_to_cpustate(ARMCPU *cpu);
>  /**
>   * write_cpustate_to_list:
>   * @cpu: ARMCPU
> + * @kvm_sync: true if this is for syncing back to KVM
>   *
>   * For each register listed in the ARMCPU cpreg_indexes list, write
>   * its value from the ARMCPUState structure into the cpreg_values list.
>   * This is used to copy info from TCG's working data structures into
>   * KVM or for outbound migration.
>   *
> + * @kvm_sync is true if we are doing this in order to sync the
> + * register state back to KVM. In this case we will only update
> + * values in the list if the previous list->cpustate sync actually
> + * successfully wrote the CPU state. Otherwise we will keep the value
> + * that is in the list.
> + *
>   * Returns: true if all register values were read correctly,
>   * false if some register was unknown or could not be read.
>   * Note that we do not stop early on failure -- we will attempt
>   * reading all registers in the list.
>   */
> -bool write_cpustate_to_list(ARMCPU *cpu);
> +bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
>  
>  #define ARM_CPUID_TI915T  0x54029152
>  #define ARM_CPUID_TI925T  0x54029252
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 2607d39ad1c..554f111ea89 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -265,7 +265,7 @@ static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
>  return true;
>  }
>  
> -bool write_cpustate_to_list(ARMCPU *cpu)
> +bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
>  {
>  /* Write the coprocessor state from cpu->env to the (index,value) list. 
> */
>  int i;
> @@ -274,6 +274,7 @@ bool write_cpustate_to_list(ARMCPU *cpu)
>  for (i = 0; i < cpu->cpreg_array_len; i++) {
>  uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
>  const ARMCPRegInfo *ri;
> +uint64_t newval;
>  
>  ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
>  if (!ri) {
> @@ -283,7 +284,29 @@ bool write_cpustate_to_list(ARMCPU *cpu)
>  if (ri->type & ARM_CP_NO_RAW) {
>  continue;
>  }
> -cpu->cpreg_values[i] = read_raw_cp_reg(>env, ri);
> +
> +newval = read_raw_cp_reg(>env, ri);
> +if (kvm_sync) {
> +/*
> + * Only sync if the previous list->cpustate sync succeeded.
> + * Rather than tracking the success/failure state for every
> + * item in the list, we just recheck "does the raw write we must
> + * have made in write_list_to_cpustate() read back OK" here.
> + */
> +uint64_t oldval = 

[Qemu-devel] [PATCH v1 1/1] riscv: plic: Set msi_nonbroken as true

[Alistair Francis]

Set msi_nonbroken as true for the PLIC.

According to the comment located here:
https://git.qemu.org/?p=qemu.git;a=blob;f=hw/pci/msi.c;h=47d2b0f33c664533b8dbd5cb17faa8e6a01afe1f;hb=HEAD#l38
the msi_nonbroken variable should be set to true even if they don't
support MSI. In this case that is what we are doing as we don't support
MSI.

Signed-off-by: Alistair Francis 
Reported-by: Andrea Bolognani 
Reported-by: David Abdurachmanov 
---
This should allow working pcie-root-ports in QEMU and allow libvirt
to start using PCIe by default for RISC-V guests.

hw/riscv/sifive_plic.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index d12ec3fc9a..4b0537c912 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -22,6 +22,7 @@
 #include "qemu/log.h"
 #include "qemu/error-report.h"
 #include "hw/sysbus.h"
+#include "hw/pci/msi.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/sifive_plic.h"
 
@@ -443,6 +444,8 @@ static void sifive_plic_realize(DeviceState *dev, Error 
**errp)
 plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
 sysbus_init_mmio(SYS_BUS_DEVICE(dev), >mmio);
 qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
+
+msi_nonbroken = true;
 }
 
 static void sifive_plic_class_init(ObjectClass *klass, void *data)
-- 
2.21.0

Re: [Qemu-devel] [PATCH for-4.0?] arm: Allow system registers for KVM guests to be changed by QEMU code

[Richard Henderson]

On 3/15/19 7:30 AM, Peter Maydell wrote:
> This commit is the same as commit 823e1b3818f9b10b824ddc which we
> had to revert in commit 942f99c825fc94c8b1a4, except that the bug
> which was preventing EDK2 guest firmware running has been fixed:
> kvm_arm_reset_vcpu() now calls write_list_to_cpustate().

Interesting.
Reviewed-by: Richard Henderson 

> Should we try to put this in for rc1? Not sure... Testing
> definitely appreciated.

Probably should try.
I'll work on that testing next week.


r~

Re: [Qemu-devel] State of QEMU CI as we enter 4.0

[Alex Bennée]

Ed Vielmetti  writes:

> There are a couple of options hosted at Packet - Shippable, Codefresh, and
> Drone. I perhaps know more about Drone than the others. Each of them have a
> supported/sponsored version which can be used to produce arm64 binaries
> natively.
>
> I'll admit to dropping into this conversation in mid-stream though - what
> is the overall goal of this effort? Knowing that it might be easier to
> suggest a specific path.

Apologies I did drop you into the CC half-way. The thread can be viewed
in our archives:

  https://lists.gnu.org/archive/html/qemu-devel/2019-03/msg04909.html

but essentially as we finish another dev cycle we are reviewing our
current CI setup and looking to see how we can add additional
architectures to our current setup which is currently very x86 focused.

Individual developers have access to range of machines and the gitlab
runner approach looks quite promising. However it's proving to be harder
to setup in practice!

>
> On Fri, Mar 15, 2019 at 1:54 PM Alex Bennée  wrote:
>
>>
>> Ed Vielmetti  writes:
>>
>> > We have been trying to merge the Gitlab runner patches for arm64
>> > for over a year now; see
>> >
>> > https://gitlab.com/gitlab-org/gitlab-runner/merge_requests/725
>>
>> Yes I found that one. I'm trying to work out exactly how there build
>> system works. It seems to build all architectures on the same host using
>> QEMU to do so. I suspect this has never actually been run on a non-x86
>> host so I'm seeing if there is anything I can fix.
>>
>> I've already hit a bug with Debian's QEMU packaging which assumes that
>> an AArch64 box always supports AArch32 which isn't true on the TX
>> machines:
>>
>>   https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=924667
>>
>> > I have not yet sorted out who at Gitlab has the ability to get
>> > this change implemented - their management structure is
>> > not something that I have sorted out yet, and I can't tell whether
>> > this lack of forward progress is something best to tackle by
>> > technical merit or by appealing to management.
>>
>> What about Shippable? I saw the press release you guys did but it is not
>> entirely clear if I need a paid licensed Bring You Own Node or if is there
>> a
>> free option for FLOSS projects?
>>
>> >
>> > On Fri, Mar 15, 2019 at 6:24 AM Fam Zheng  wrote:
>> >
>> >>
>> >>
>> >> > On Mar 15, 2019, at 17:58, Alex Bennée 
>> wrote:
>> >> >
>> >> >
>> >> > Fam Zheng  writes:
>> >> >
>> >> >>> On Mar 15, 2019, at 16:57, Alex Bennée 
>> wrote:
>> >> >>>
>> >> >>> I had installed the gitlab-runner from the Debian repo but it was
>> out
>> >> >>> of date and didn't seem to work correctly.
>> >> >>
>> >> >> If there can be a sidecar x86 box next to the test bot, it can be the
>> >> >> controller node which runs gitlab-runner, the test script (in
>> >> >> .gitlab-ci.yml) can then sshs into the actual env to run test
>> >> >> commands.
>> >> >
>> >> > Sure although that just adds complexity compared to spinning up a box
>> in
>> >> > the cloud ;-)
>> >>
>> >> In the middle is one controller node and a number of hetergeneous boxes
>> it
>> >> knows how to control with ssh.
>> >>
>> >> (BTW patchew tester only relies on vanilla python3 to work, though
>> clearly
>> >> it suffers from insufficient manpower assumed the SLA we'll need on the
>> >> merge test. It’s unfortunate that gitlab-runner is a binary.)
>> >>
>> >> Fam
>> >>
>>
>>
>> --
>> Alex Bennée
>>


--
Alex Bennée

Re: [Qemu-devel] [PATCH v2 00/12] bundle edk2 platform firmware with QEMU

[Eric Blake]

On 3/15/19 11:42 AM, Philippe Mathieu-Daudé wrote:
> Hi,
> 
>>From my previous experience with the tests/ patches, I understood we
> could still send PR that improve testing after soft freeze.
> This series doesn't modify the QEMU binaries, it add EDK2 firmware blobs
> in roms/ and rules to rebuild these roms.
> These roms are useful for the ACPI tests introduced in commits
> 09a274d82f and 503bb0b975a on the arm/virt board.
> 
> There is 1 direct change:
> 
> 1/ in the root Makefile, the 'make install' rule installs one new file:
>- edk2-licenses.txt
> 
> And there are 2 other changes which require user specific action:
> 
> 2/ Set the environment variable 'INSTALL_BLOBS', the 'make install' rule
> will install the firmware blobs and the firmware JSON descriptors
> 
> 3/ a new 'efi' target rule in roms/Makefile
> 
> I'm planning to send a PR for this series but I want to check first if
> there is any issue with the current policy/rules.
> 

If this were during -rc2 or -rc3, our goal would be minimizing churn,
and I would lean towards deferral. But for mere softfreeze before -rc0,
and with your justification that this helps downstreams while provably
being independent enough of the main binaries to be low risk, I agree
with the idea of a PR.

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3226
Virtualization:  qemu.org | libvirt.org



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Re: [Qemu-devel] Maintainers, please tell us how to boot your machines!

[Aleksandar Markovic]

> From: Thomas Huth 
> Subject: Re: Maintainers, please tell us how to boot your machines!
> 
> > On Tue, Mar 12, 2019 at 6:44 PM Markus Armbruster 
> > wrote:
> [...]
> > > I gathered the machine types, mapped them to source files, which I
> > > fed to get_maintainer.pl.  Results are appended.  If you're cc'ed,
> > > MAINTAINERS fingers you for at least one machine type's source file.
> > > Please tell us for all of them how to to a "meaningful" boot test.
> [...]
> > > = hw/mips/mips_mipssim.c =
> > > Aleksandar Markovic  (odd fixer:Mipssim)
> > > Aleksandar Rikalo  (reviewer:Mipssim)
> > > Aurelien Jarno  (maintainer:MIPS)
> >
> > See this thread:
> > http://lists.nongnu.org/archive/html/qemu-devel/2018-04/msg04071.html
> 
> You can still create an image for the mipssim machine with "buildroot".
> It's cumbersome, and you've got to use an older Linux kernel (< 3.6
> IIRC), but it's doable. I once built an image for this machine a couple
> of months ago. Let me know if you want it.
> 

Thomas,

That would be great! Please attach the procedure you use, it is a valuable
information. I truly appreciate your participation!

Aleksandar

Re: [Qemu-devel] [PATCH] configure: disallow spaces and colons in source path

[Eric Blake]

On 3/15/19 1:40 PM, Peter Maydell wrote:

> If you do this after the point where we make the source path absolute, you
> can skip the realpath (which avoids the problem that 'realpath' doesn't exist
> on OSX by default). It will also then be after the handling of the
> --source-path option argument.
> 
> Do we also need to check for spaces in the path of the build directory
> (which is always the current working directory of the script) ?

I wasn't thinking about VPATH builds, but yes, in general, we should
ensure that both srcdir and builddir are sane names, while still
allowing symlinks to work around otherwise problematic canonical names.


-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3226
Virtualization:  qemu.org | libvirt.org



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Re: [Qemu-devel] [PATCH] configure: disallow spaces and colons in source path

[Eric Blake]

On 3/15/19 12:50 PM, Antonio Ospite wrote:
> From: Antonio Ospite 
> 
> The configure script breaks when the qemu source directory is in a path
> containing white spaces, in particular the list of targets is not
> correctly generated when calling "./configure --help".
> 
> To avoid this issue, refuse to run the configure script if there are
> spaces or colons in the source path, this is also what kbuild from linux
> does.
> 
> Buglink: https://bugs.launchpad.net/qemu/+bug/1817345
> 
> Signed-off-by: Antonio Ospite 
> ---
>  configure | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/configure b/configure
> index 7071f52584..fbd70a0f51 100755
> --- a/configure
> +++ b/configure
> @@ -295,6 +295,11 @@ libs_qga=""
>  debug_info="yes"
>  stack_protector=""
>  
> +if printf "%s" "$(realpath "$source_path")" | grep -q "[[:space:]:]";

Why realpath? If my sources live in "/home/me/bad dir" but I have a
symlink "/home/me/good", this prevents me from building even though I
won't trip the problem.

Also, grep is not required to operate on non-text files (the POSIX
definition states that if your input does not end in a newline, it is
not a text file, and grep can skip that line) - better is to use "%s\n"
in some form.

So I'd rather see this just use:

if printf %s\\n "$PWD" | grep -q "[[:space:]:]"

-- 
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3226
Virtualization:  qemu.org | libvirt.org



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Re: [Qemu-devel] [PATCH] configure: disallow spaces and colons in source path

[Peter Maydell]

On Fri, 15 Mar 2019 at 18:26, Antonio Ospite  wrote:
>
> From: Antonio Ospite 
>
> The configure script breaks when the qemu source directory is in a path
> containing white spaces, in particular the list of targets is not
> correctly generated when calling "./configure --help".
>
> To avoid this issue, refuse to run the configure script if there are
> spaces or colons in the source path, this is also what kbuild from linux
> does.
>
> Buglink: https://bugs.launchpad.net/qemu/+bug/1817345
>
> Signed-off-by: Antonio Ospite 

Hi Antonio; thanks for this patch.

> ---
>  configure | 5 +
>  1 file changed, 5 insertions(+)
>
> diff --git a/configure b/configure
> index 7071f52584..fbd70a0f51 100755
> --- a/configure
> +++ b/configure
> @@ -295,6 +295,11 @@ libs_qga=""
>  debug_info="yes"
>  stack_protector=""
>
> +if printf "%s" "$(realpath "$source_path")" | grep -q "[[:space:]:]";
> +then
> +  error_exit "main directory cannot contain spaces nor colons"
> +fi
> +

If you do this after the point where we make the source path absolute, you
can skip the realpath (which avoids the problem that 'realpath' doesn't exist
on OSX by default). It will also then be after the handling of the
--source-path option argument.

Do we also need to check for spaces in the path of the build directory
(which is always the current working directory of the script) ?

thanks
-- PMM

Re: [Qemu-devel] [PATCH] xen-mapcache: use MAP_FIXED flag so the mmap address hint is always honored

[Anthony PERARD]

On Fri, Mar 15, 2019 at 06:14:09PM +, Anthony PERARD wrote:
> On Fri, Mar 15, 2019 at 09:58:47AM +0100, Roger Pau Monne wrote:
> > Or if it's not possible to honor the hinted address an error is returned
> > instead. This makes it easier to spot the actual failure, instead of
> > failing later on when the caller of xen_remap_bucket realizes the
> > mapping has not been created at the requested address.
> > 
> > Also note that at least on FreeBSD using MAP_FIXED will cause mmap to
> > try harder to honor the passed address.
> > 
> > Signed-off-by: Roger Pau Monné 
> 
> The patch looks fine, and MAP_FIXED seems to be the expected behavior
> even on Linux.
> 
> Acked-by: Anthony PERARD 
> 
> > diff --git a/hw/i386/xen/xen-mapcache.c b/hw/i386/xen/xen-mapcache.c
> > @@ -185,8 +185,14 @@ static void xen_remap_bucket(MapCacheEntry *entry,
> >  }
> >  
> >  if (!dummy) {
> > +/*
> > + * If the caller has requested the mapping at a specific address 
> > use
> > + * MAP_FIXED to make sure it's honored. Note that with MAP_FIXED at
> > + * least FreeBSD will try harder to honor the passed address.
> > + */
> >  vaddr_base = xenforeignmemory_map2(xen_fmem, xen_domid, vaddr,
> > -   PROT_READ | PROT_WRITE, 0,
> > +   PROT_READ | PROT_WRITE,
> > +   vaddr ? MAP_FIXED : 0,
> > nb_pfn, pfns, err);

I've noticed that there's a mmap call just after which has also vaddr as
hint, should that second call also have MAP_FIXED as flags?

On the other hand, it seems that when vaddr!=NULL, dummy==false, so that
second mmap call will never be called with vaddr!=NULL. But it might be
worse fixing this in the same patch.

>  } else {
>  /*
>   * We create dummy mappings where we are unable to create a foreign
>   * mapping immediately due to certain circumstances (i.e. on resume now)
>   */
>  vaddr_base = mmap(vaddr, size, PROT_READ | PROT_WRITE,
>MAP_ANON | MAP_SHARED, -1, 0);

-- 
Anthony PERARD

Re: [Qemu-devel] [PATCH v5 5/5] RISC-V: Add hooks to use the gdb xml files.

[Alistair Francis]

On Fri, Mar 15, 2019 at 7:01 AM Chih-Min Chao  wrote:
>
> From: Jim Wilson 
>
> The gdb CSR xml file has registers in documentation order, not numerical
> order, so we need a table to map the register numbers.  This also adds
> fairly standard gdb hooks to access xml specified registers.
>
> notice:
> The fpu xml from gdb 8.3 has unused register #, 65 and make first
> csr register # become 69. We register extra register on gdb to correct
> csr offset calculation
>
> Signed-off-by: Jim Wilson 
> Signed-off-by: Chih-Min Chao 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/cpu.c |   9 +-
>  target/riscv/cpu.h |   2 +
>  target/riscv/gdbstub.c | 350 
> +++--
>  3 files changed, 349 insertions(+), 12 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index cc3ddc0..feea169 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -311,6 +311,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>  return;
>  }
>
> +riscv_cpu_register_gdb_regs_for_features(cs);
> +
>  qemu_init_vcpu(cs);
>  cpu_reset(cs);
>
> @@ -351,7 +353,12 @@ static void riscv_cpu_class_init(ObjectClass *c, void 
> *data)
>  cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
>  cc->gdb_read_register = riscv_cpu_gdb_read_register;
>  cc->gdb_write_register = riscv_cpu_gdb_write_register;
> -cc->gdb_num_core_regs = 65;
> +cc->gdb_num_core_regs = 33;
> +#if defined(TARGET_RISCV32)
> +cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
> +#elif defined(TARGET_RISCV64)
> +cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
> +#endif
>  cc->gdb_stop_before_watchpoint = true;
>  cc->disas_set_info = riscv_cpu_disas_set_info;
>  #ifdef CONFIG_USER_ONLY
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 4c5de30..9b673de 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -330,6 +330,8 @@ typedef struct {
>  void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
>  void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
>
> +void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
> +
>  #include "exec/cpu-all.h"
>
>  #endif /* RISCV_CPU_H */
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 3cabb21..dfcdd83 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -21,6 +21,255 @@
>  #include "exec/gdbstub.h"
>  #include "cpu.h"
>
> +/*
> + * The GDB CSR xml files list them in documentation order, not numerical 
> order,
> + * and are missing entries for unnamed CSRs.  So we need to map the gdb 
> numbers
> + * to the hardware numbers.
> + */
> +
> +static int csr_register_map[] = {
> +CSR_USTATUS,
> +CSR_UIE,
> +CSR_UTVEC,
> +CSR_USCRATCH,
> +CSR_UEPC,
> +CSR_UCAUSE,
> +CSR_UTVAL,
> +CSR_UIP,
> +CSR_FFLAGS,
> +CSR_FRM,
> +CSR_FCSR,
> +CSR_CYCLE,
> +CSR_TIME,
> +CSR_INSTRET,
> +CSR_HPMCOUNTER3,
> +CSR_HPMCOUNTER4,
> +CSR_HPMCOUNTER5,
> +CSR_HPMCOUNTER6,
> +CSR_HPMCOUNTER7,
> +CSR_HPMCOUNTER8,
> +CSR_HPMCOUNTER9,
> +CSR_HPMCOUNTER10,
> +CSR_HPMCOUNTER11,
> +CSR_HPMCOUNTER12,
> +CSR_HPMCOUNTER13,
> +CSR_HPMCOUNTER14,
> +CSR_HPMCOUNTER15,
> +CSR_HPMCOUNTER16,
> +CSR_HPMCOUNTER17,
> +CSR_HPMCOUNTER18,
> +CSR_HPMCOUNTER19,
> +CSR_HPMCOUNTER20,
> +CSR_HPMCOUNTER21,
> +CSR_HPMCOUNTER22,
> +CSR_HPMCOUNTER23,
> +CSR_HPMCOUNTER24,
> +CSR_HPMCOUNTER25,
> +CSR_HPMCOUNTER26,
> +CSR_HPMCOUNTER27,
> +CSR_HPMCOUNTER28,
> +CSR_HPMCOUNTER29,
> +CSR_HPMCOUNTER30,
> +CSR_HPMCOUNTER31,
> +CSR_CYCLEH,
> +CSR_TIMEH,
> +CSR_INSTRETH,
> +CSR_HPMCOUNTER3H,
> +CSR_HPMCOUNTER4H,
> +CSR_HPMCOUNTER5H,
> +CSR_HPMCOUNTER6H,
> +CSR_HPMCOUNTER7H,
> +CSR_HPMCOUNTER8H,
> +CSR_HPMCOUNTER9H,
> +CSR_HPMCOUNTER10H,
> +CSR_HPMCOUNTER11H,
> +CSR_HPMCOUNTER12H,
> +CSR_HPMCOUNTER13H,
> +CSR_HPMCOUNTER14H,
> +CSR_HPMCOUNTER15H,
> +CSR_HPMCOUNTER16H,
> +CSR_HPMCOUNTER17H,
> +CSR_HPMCOUNTER18H,
> +CSR_HPMCOUNTER19H,
> +CSR_HPMCOUNTER20H,
> +CSR_HPMCOUNTER21H,
> +CSR_HPMCOUNTER22H,
> +CSR_HPMCOUNTER23H,
> +CSR_HPMCOUNTER24H,
> +CSR_HPMCOUNTER25H,
> +CSR_HPMCOUNTER26H,
> +CSR_HPMCOUNTER27H,
> +CSR_HPMCOUNTER28H,
> +CSR_HPMCOUNTER29H,
> +CSR_HPMCOUNTER30H,
> +CSR_HPMCOUNTER31H,
> +CSR_SSTATUS,
> +CSR_SEDELEG,
> +CSR_SIDELEG,
> +CSR_SIE,
> +CSR_STVEC,
> +CSR_SCOUNTEREN,
> +CSR_SSCRATCH,
> +CSR_SEPC,
> +CSR_SCAUSE,
> +CSR_STVAL,
> +CSR_SIP,
> +CSR_SATP,
> +CSR_MVENDORID,
> +CSR_MARCHID,
> +CSR_MIMPID,
> +CSR_MHARTID,
> +CSR_MSTATUS,
> +CSR_MISA,
> +CSR_MEDELEG,
> +CSR_MIDELEG,
> +CSR_MIE,
> +CSR_MTVEC,
> +CSR_MCOUNTEREN,
> +CSR_MSCRATCH,
> +CSR_MEPC,

Re: [Qemu-devel] [PATCH v8 3/6] ui: add keycodemapdb repository as a GIT submodule

[Peter Maydell]

On Fri, 29 Sep 2017 at 11:12, Daniel P. Berrange  wrote:
>
> The https://gitlab.com/keycodemap/keycodemapdb/ repo contains a
> data file mapping between all the different scancode/keycode/keysym
> sets that are known, and a tool to auto-generate lookup tables for
> different combinations

Hi Dan; apologies for hauling up this commit from 2017, but
I just noticed something while reading through configure:

> diff --git a/configure b/configure
> index b324e057f1..eb420abc47 100755
> --- a/configure
> +++ b/configure
> @@ -264,7 +264,13 @@ cc_i386=i386-pc-linux-gnu-gcc
>  libs_qga=""
>  debug_info="yes"
>  stack_protector=""
> -git_submodules=""
> +
> +if test -e "$source_path/.git"
> +then
> +git_submodules="ui/keycodemapdb"
> +else
> +git_submodules=""
> +fi

Configure has a --source-path option, which overrides the
default $source_path setting (of the directory where the
configure script lives), but this commit (927128222b0a91f56c13a)
added a use of $source_path before the part of configure that
parses the option and updates $source_path accordingly.
Could this lump of code (and the later enhancements to it) be moved
further down in the file?

(Alternatively, we could drop the --source-path option entirely:
I didn't even know it existed and I'm not sure it's very
useful...)

thanks
-- PMM

Re: [Qemu-devel] [PATCH v5 0/5] RISC-V: Add gdb xml files and gdbstub support

[Alistair Francis]

On Fri, Mar 15, 2019 at 6:45 AM Chih-Min Chao  wrote:
>
> This is the 5th version of the patch set, based on the Jim's previous work,
>  http://lists.nongnu.org/archive/html/qemu-riscv/2019-02/msg00059.html
>
> v4 -> v5:
>- rebase 7074ab1
>- update the register xml files to gdb 8.3
>- refine the fpu control registers, fflags/frm/fcsr index calculation
>- fix the csr offset calculcation because of tne regnum field in fpu
>  xml file introducing one useless number

Hey Chih-Min,

I thought this was merged into master, but apparently that never
happened. Thanks for bringing this up again.

Thanks for the corrections on top of the v4. For future reference if
the changes are very minor you can probably keep the reviewed tags.

I have reviewed the changes and this should be ready to go. I have
added Palmer so hopefully he can add this to a PR to get it in for
4.0.

Alistair

>
> Jim Wilson (5):
>   RISC-V: Add 32-bit gdb xml files.
>   RISC-V: Add 64-bit gdb xml files.
>   RISC-V: Fixes to CSR_* register macros.
>   RISC-V: Add debug support for accessing CSRs.
>   RISC-V: Add hooks to use the gdb xml files.
>
>  configure   |   2 +
>  gdb-xml/riscv-32bit-cpu.xml |  47 ++
>  gdb-xml/riscv-32bit-csr.xml | 250 +++
>  gdb-xml/riscv-32bit-fpu.xml |  50 +++
>  gdb-xml/riscv-64bit-cpu.xml |  47 ++
>  gdb-xml/riscv-64bit-csr.xml | 250 +++
>  gdb-xml/riscv-64bit-fpu.xml |  56 +++
>  target/riscv/cpu.c  |   9 +-
>  target/riscv/cpu.h  |   7 +
>  target/riscv/cpu_bits.h |  35 -
>  target/riscv/csr.c  |  32 +++-
>  target/riscv/gdbstub.c  | 350 
> ++--
>  12 files changed, 1114 insertions(+), 21 deletions(-)
>  create mode 100644 gdb-xml/riscv-32bit-cpu.xml
>  create mode 100644 gdb-xml/riscv-32bit-csr.xml
>  create mode 100644 gdb-xml/riscv-32bit-fpu.xml
>  create mode 100644 gdb-xml/riscv-64bit-cpu.xml
>  create mode 100644 gdb-xml/riscv-64bit-csr.xml
>  create mode 100644 gdb-xml/riscv-64bit-fpu.xml
>
> --
> 2.7.4
>
>

Re: [Qemu-devel] Maintainers, please tell us how to boot your machines!

[Thomas Huth]

Am Wed, 13 Mar 2019 02:06:39 +0100
schrieb Philippe Mathieu-Daudé :

> On Tue, Mar 12, 2019 at 6:44 PM Markus Armbruster 
> wrote:
[...]
> > I gathered the machine types, mapped them to source files, which I
> > fed to get_maintainer.pl.  Results are appended.  If you're cc'ed,
> > MAINTAINERS fingers you for at least one machine type's source file.
> > Please tell us for all of them how to to a "meaningful" boot test.  
[...]
> > = hw/mips/mips_mipssim.c =
> > Aleksandar Markovic  (odd fixer:Mipssim)
> > Aleksandar Rikalo  (reviewer:Mipssim)
> > Aurelien Jarno  (maintainer:MIPS)  
> 
> See this thread:
> http://lists.nongnu.org/archive/html/qemu-devel/2018-04/msg04071.html

You can still create an image for the mipssim machine with "buildroot".
It's cumbersome, and you've got to use an older Linux kernel (< 3.6
IIRC), but it's doable. I once built an image for this machine a couple
of months ago. Let me know if you want it.

[...]
> > = hw/arm/digic_boards.c =
> > Antony Pavlov  (odd fixer:Canon DIGIC)
> > Peter Maydell  (odd fixer:Canon DIGIC)
> > qemu-...@nongnu.org (open list:Canon DIGIC)  
> 
> canon-a1100-rom1.bin
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg571908.html

A pre-build binary is now available in the QEMU advent calendar 2018,
too.

> > = hw/m68k/an5206.c =
> > Thomas Huth  (odd fixer:an5206)

wget
https://web.archive.org/web/20180303021225/http://www.uclinux.org/ports/coldfire/image-an5206-small-2706.bin.gz
gunzip image-an5206-small-2706.bin.gz
qemu-system-m68k -M an5206 -kernel image-an5206-small-2706.bin -nographic

> > = hw/m68k/mcf5208.c =
> > Thomas Huth  (odd fixer:mcf5208)

wget https://www.qemu-advent-calendar.org/2018/download/day07.tar.xz
tar -xaf day07.tar.xz
cd day07
qemu-system-m68k -M mcf5208evb -kernel sanity-clause.elf -nographic

> > = hw/ppc/e500plat.c =
> > David Gibson  (odd fixer:e500)
> > qemu-...@nongnu.org (open list:e500)

https://www.qemu-advent-calendar.org/2018/download/day19.tar.xz

> > = hw/ppc/mac_oldworld.c =
> > Mark Cave-Ayland  (odd fixer:Old
> > World (g3beige)) David Gibson 
> > (reviewer:Old World (g3beige)) qemu-...@nongnu.org (open list:Old
> > World (g3beige))

https://www.qemu-advent-calendar.org/2018/download/day15.tar.xz

 Thomas

Re: [Qemu-devel] [PATCH] authz: Use OBJECT_CHECK() on objects

[Markus Armbruster]

Daniel P. Berrangé  writes:

> On Fri, Mar 15, 2019 at 06:12:18PM +0100, Philippe Mathieu-Daudé wrote:
>> TYPE_QAUTHZ is an abstract object of type TYPE_OBJECT. All other
>> are children of TYPE_QAUTHZ, thus also objects.
>> 
>> Keep INTERFACE_CHECK() for interfaces, and use OBJECT_CHECK() on
>> objects.
>
> Hmm
>
>   #define OBJECT_CHECK(type, obj, name) \
> ((type *)object_dynamic_cast_assert(OBJECT(obj), (name), \
> __FILE__, __LINE__, __func__))
>
>   #define INTERFACE_CHECK(interface, obj, name) \
> ((interface *)object_dynamic_cast_assert(OBJECT((obj)), (name), \
>  __FILE__, __LINE__, __func__))
>
> /me now wonders why INTERFACE_CHECK needs to exist at all

Valid question.  See

Subject: Issues around TYPE_INTERFACE
Date: Tue, 12 Mar 2019 11:50:54 +0100
Message-ID: <87h8c82woh@dusky.pond.sub.org>

[...]

Re: [Qemu-devel] [PATCH v5 2/5] RISC-V: Add 64-bit gdb xml files.

[Alistair Francis]

On Fri, Mar 15, 2019 at 7:09 AM Chih-Min Chao  wrote:
>
> From: Jim Wilson 
>
> Signed-off-by: Jim Wilson 
> Signed-off-by: Chih-Min Chao 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  configure   |   1 +
>  gdb-xml/riscv-32bit-fpu.xml |   6 +-
>  gdb-xml/riscv-64bit-cpu.xml |  47 +
>  gdb-xml/riscv-64bit-csr.xml | 250 
> 
>  gdb-xml/riscv-64bit-fpu.xml |  56 ++
>  5 files changed, 357 insertions(+), 3 deletions(-)
>  create mode 100644 gdb-xml/riscv-64bit-cpu.xml
>  create mode 100644 gdb-xml/riscv-64bit-csr.xml
>  create mode 100644 gdb-xml/riscv-64bit-fpu.xml
>
> diff --git a/configure b/configure
> index aed149b..613dd2f 100755
> --- a/configure
> +++ b/configure
> @@ -7521,6 +7521,7 @@ case "$target_name" in
>  TARGET_BASE_ARCH=riscv
>  TARGET_ABI_DIR=riscv
>  mttcg=yes
> +gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml 
> riscv-64bit-csr.xml"
>  target_compiler=$cross_cc_riscv64
>;;
>sh4|sh4eb)
> diff --git a/gdb-xml/riscv-32bit-fpu.xml b/gdb-xml/riscv-32bit-fpu.xml
> index 32a1dee..1eaae91 100644
> --- a/gdb-xml/riscv-32bit-fpu.xml
> +++ b/gdb-xml/riscv-32bit-fpu.xml
> @@ -44,7 +44,7 @@
>
>
>
> -  
> -  
> -  
> +  
> +  
> +  
>  
> diff --git a/gdb-xml/riscv-64bit-cpu.xml b/gdb-xml/riscv-64bit-cpu.xml
> new file mode 100644
> index 000..b8aa424
> --- /dev/null
> +++ b/gdb-xml/riscv-64bit-cpu.xml
> @@ -0,0 +1,47 @@
> +
> +
> +
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> diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml
> new file mode 100644
> index 000..6aa4bed
> --- /dev/null
> +++ b/gdb-xml/riscv-64bit-csr.xml
> @@ -0,0 +1,250 @@
> +
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> +  
> +  
> +
> diff --git a/gdb-xml/riscv-64bit-fpu.xml b/gdb-xml/riscv-64bit-fpu.xml
> new file mode 100644
> index 000..794854c
> --- /dev/null
> +++ b/gdb-xml/riscv-64bit-fpu.xml
> @@ -0,0 +1,56 @@
> +
> +
> +
> +
> +
> +
> +
> +
> +  
> +
> +
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> +
> --
> 2.7.4
>
>

Re: [Qemu-devel] [PATCH v5 1/5] RISC-V: Add 32-bit gdb xml files.

[Alistair Francis]

On Fri, Mar 15, 2019 at 7:42 AM Chih-Min Chao  wrote:
>
> From: Jim Wilson 
>
> Signed-off-by: Jim Wilson 
> Signed-off-by: Chih-Min Chao 

This looks good, I didn't dig into every register here, but I'm
assuming it's correct.

Reviewed-by: Alistair Francis 

Alistair


> ---
>  configure   |   1 +
>  gdb-xml/riscv-32bit-cpu.xml |  47 +
>  gdb-xml/riscv-32bit-csr.xml | 250 
> 
>  gdb-xml/riscv-32bit-fpu.xml |  50 +
>  4 files changed, 348 insertions(+)
>  create mode 100644 gdb-xml/riscv-32bit-cpu.xml
>  create mode 100644 gdb-xml/riscv-32bit-csr.xml
>  create mode 100644 gdb-xml/riscv-32bit-fpu.xml
>
> diff --git a/configure b/configure
> index 7071f52..aed149b 100755
> --- a/configure
> +++ b/configure
> @@ -7514,6 +7514,7 @@ case "$target_name" in
>  TARGET_BASE_ARCH=riscv
>  TARGET_ABI_DIR=riscv
>  mttcg=yes
> +gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml 
> riscv-32bit-csr.xml"
>  target_compiler=$cross_cc_riscv32
>;;
>riscv64)
> diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml
> new file mode 100644
> index 000..0d07aae
> --- /dev/null
> +++ b/gdb-xml/riscv-32bit-cpu.xml
> @@ -0,0 +1,47 @@
> +
> +
> +
> +
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> diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml
> new file mode 100644
> index 000..da1bf19
> --- /dev/null
> +++ b/gdb-xml/riscv-32bit-csr.xml
> @@ -0,0 +1,250 @@
> +
> +
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> diff --git a/gdb-xml/riscv-32bit-fpu.xml b/gdb-xml/riscv-32bit-fpu.xml
> new file mode 100644
> index 000..32a1dee
> --- /dev/null
> +++ b/gdb-xml/riscv-32bit-fpu.xml
> @@ -0,0 +1,50 @@
> +
> +
> +
> +
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> --
> 2.7.4
>
>

Re: [Qemu-devel] [PATCH] xen-mapcache: use MAP_FIXED flag so the mmap address hint is always honored

[Anthony PERARD]

On Fri, Mar 15, 2019 at 09:54:42AM +, Paul Durrant wrote:
> AFAICT xen_remap_bucket() is always called with a NULL vaddr argument
> if entry->vaddr_base == NULL, and called with vaddr ==
> entry->vaddr_base in the other case, so I'd say the vaddr argument is
> superfluous.

I don't think that's true. The call at line 312 [1] may be called with
vaddr_base != NULL. Then, xen_remap_bucket will unmap that entry before
replacing it.

We could maybe figure out if vaddr_base needs to be replaced in-place
based on the flags XEN_MAPCACHE_ENTRY_DUMMY, but that seems more
convoluted than the current approche.

[1] 
https://git.qemu.org/?p=qemu.git;a=blob;f=hw/i386/xen/xen-mapcache.c;h=349f72d00cc2c9fc134df8cff7dd051b1fc2fa41;hb=HEAD#l312

-- 
Anthony PERARD

[Qemu-devel] [PATCH] configure: disallow spaces and colons in source path

[Antonio Ospite]

From: Antonio Ospite 

The configure script breaks when the qemu source directory is in a path
containing white spaces, in particular the list of targets is not
correctly generated when calling "./configure --help".

To avoid this issue, refuse to run the configure script if there are
spaces or colons in the source path, this is also what kbuild from linux
does.

Buglink: https://bugs.launchpad.net/qemu/+bug/1817345

Signed-off-by: Antonio Ospite 
---
 configure | 5 +
 1 file changed, 5 insertions(+)

diff --git a/configure b/configure
index 7071f52584..fbd70a0f51 100755
--- a/configure
+++ b/configure
@@ -295,6 +295,11 @@ libs_qga=""
 debug_info="yes"
 stack_protector=""
 
+if printf "%s" "$(realpath "$source_path")" | grep -q "[[:space:]:]";
+then
+  error_exit "main directory cannot contain spaces nor colons"
+fi
+
 if test -e "$source_path/.git"
 then
 git_update=yes
-- 
2.20.1

Re: [Qemu-devel] State of QEMU CI as we enter 4.0

[Ed Vielmetti]

There are a couple of options hosted at Packet - Shippable, Codefresh, and
Drone. I perhaps know more about Drone than the others. Each of them have a
supported/sponsored version which can be used to produce arm64 binaries
natively.

I'll admit to dropping into this conversation in mid-stream though - what
is the overall goal of this effort? Knowing that it might be easier to
suggest a specific path.

On Fri, Mar 15, 2019 at 1:54 PM Alex Bennée  wrote:

>
> Ed Vielmetti  writes:
>
> > We have been trying to merge the Gitlab runner patches for arm64
> > for over a year now; see
> >
> > https://gitlab.com/gitlab-org/gitlab-runner/merge_requests/725
>
> Yes I found that one. I'm trying to work out exactly how there build
> system works. It seems to build all architectures on the same host using
> QEMU to do so. I suspect this has never actually been run on a non-x86
> host so I'm seeing if there is anything I can fix.
>
> I've already hit a bug with Debian's QEMU packaging which assumes that
> an AArch64 box always supports AArch32 which isn't true on the TX
> machines:
>
>   https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=924667
>
> > I have not yet sorted out who at Gitlab has the ability to get
> > this change implemented - their management structure is
> > not something that I have sorted out yet, and I can't tell whether
> > this lack of forward progress is something best to tackle by
> > technical merit or by appealing to management.
>
> What about Shippable? I saw the press release you guys did but it is not
> entirely clear if I need a paid licensed Bring You Own Node or if is there
> a
> free option for FLOSS projects?
>
> >
> > On Fri, Mar 15, 2019 at 6:24 AM Fam Zheng  wrote:
> >
> >>
> >>
> >> > On Mar 15, 2019, at 17:58, Alex Bennée 
> wrote:
> >> >
> >> >
> >> > Fam Zheng  writes:
> >> >
> >> >>> On Mar 15, 2019, at 16:57, Alex Bennée 
> wrote:
> >> >>>
> >> >>> I had installed the gitlab-runner from the Debian repo but it was
> out
> >> >>> of date and didn't seem to work correctly.
> >> >>
> >> >> If there can be a sidecar x86 box next to the test bot, it can be the
> >> >> controller node which runs gitlab-runner, the test script (in
> >> >> .gitlab-ci.yml) can then sshs into the actual env to run test
> >> >> commands.
> >> >
> >> > Sure although that just adds complexity compared to spinning up a box
> in
> >> > the cloud ;-)
> >>
> >> In the middle is one controller node and a number of hetergeneous boxes
> it
> >> knows how to control with ssh.
> >>
> >> (BTW patchew tester only relies on vanilla python3 to work, though
> clearly
> >> it suffers from insufficient manpower assumed the SLA we'll need on the
> >> merge test. It’s unfortunate that gitlab-runner is a binary.)
> >>
> >> Fam
> >>
>
>
> --
> Alex Bennée
>

Re: [Qemu-devel] [PATCH] xen-mapcache: use MAP_FIXED flag so the mmap address hint is always honored

[Anthony PERARD]

On Fri, Mar 15, 2019 at 09:58:47AM +0100, Roger Pau Monne wrote:
> Or if it's not possible to honor the hinted address an error is returned
> instead. This makes it easier to spot the actual failure, instead of
> failing later on when the caller of xen_remap_bucket realizes the
> mapping has not been created at the requested address.
> 
> Also note that at least on FreeBSD using MAP_FIXED will cause mmap to
> try harder to honor the passed address.
> 
> Signed-off-by: Roger Pau Monné 

The patch looks fine, and MAP_FIXED seems to be the expected behavior
even on Linux.

Acked-by: Anthony PERARD 

> diff --git a/hw/i386/xen/xen-mapcache.c b/hw/i386/xen/xen-mapcache.c
> @@ -185,8 +185,14 @@ static void xen_remap_bucket(MapCacheEntry *entry,
>  }
>  
>  if (!dummy) {
> +/*
> + * If the caller has requested the mapping at a specific address use
> + * MAP_FIXED to make sure it's honored. Note that with MAP_FIXED at
> + * least FreeBSD will try harder to honor the passed address.
> + */

I wonder if the note about FreeBSD is actually useful here. Even Linux
may map at a different address without MAP_FIXED, if I read the man page
correctly. Do you mind if it is removed?

>  vaddr_base = xenforeignmemory_map2(xen_fmem, xen_domid, vaddr,
> -   PROT_READ | PROT_WRITE, 0,
> +   PROT_READ | PROT_WRITE,
> +   vaddr ? MAP_FIXED : 0,
> nb_pfn, pfns, err);

Thanks,

-- 
Anthony PERARD

[Qemu-devel] [PATCH] docs: reST-ify vhost-user documentation

[Marc-André Lureau]

Signed-off-by: Marc-André Lureau 
---
 MAINTAINERS |2 +-
 docs/interop/index.rst  |2 +-
 docs/interop/vhost-user.rst | 1351 +++
 docs/interop/vhost-user.txt | 1219 ---
 4 files changed, 1353 insertions(+), 1221 deletions(-)
 create mode 100644 docs/interop/vhost-user.rst
 delete mode 100644 docs/interop/vhost-user.txt

diff --git a/MAINTAINERS b/MAINTAINERS
index 0e7baa9aa2..ed19e0ece1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1456,7 +1456,7 @@ M: Michael S. Tsirkin 
 S: Supported
 F: hw/*/*vhost*
 F: docs/interop/vhost-user.json
-F: docs/interop/vhost-user.txt
+F: docs/interop/vhost-user.rst
 F: contrib/vhost-user-*/
 
 virtio
diff --git a/docs/interop/index.rst b/docs/interop/index.rst
index 2df977dd52..a037bd67ec 100644
--- a/docs/interop/index.rst
+++ b/docs/interop/index.rst
@@ -15,4 +15,4 @@ Contents:
bitmaps
live-block-operations
pr-helper
-
+   vhost-user
diff --git a/docs/interop/vhost-user.rst b/docs/interop/vhost-user.rst
new file mode 100644
index 00..7f3232c798
--- /dev/null
+++ b/docs/interop/vhost-user.rst
@@ -0,0 +1,1351 @@
+===
+Vhost-user Protocol
+===
+:Copyright: 2014 Virtual Open Systems Sarl.
+:Licence: This work is licensed under the terms of the GNU GPL,
+  version 2 or later. See the COPYING file in the top-level
+  directory.
+
+.. contents:: Table of Contents
+
+Introduction
+
+
+This protocol is aiming to complement the ``ioctl`` interface used to
+control the vhost implementation in the Linux kernel. It implements
+the control plane needed to establish virtqueue sharing with a user
+space process on the same host. It uses communication over a Unix
+domain socket to share file descriptors in the ancillary data of the
+message.
+
+The protocol defines 2 sides of the communication, *master* and
+*slave*. *Master* is the application that shares its virtqueues, in
+our case QEMU. *Slave* is the consumer of the virtqueues.
+
+In the current implementation QEMU is the *master*, and the *slave* is
+the external process consuming the virtio queues, for example a
+software Ethernet switch running in user space, such as Snabbswitch,
+or a block device backend processing read & write to a virtual
+disk. In order to facilitate interoperability between various backend
+implementations, it is recommended to follow the :ref:`Backend program
+conventions `.
+
+*Master* and *slave* can be either a client (i.e. connecting) or
+server (listening) in the socket communication.
+
+Message Specification
+=
+
+.. Note:: All numbers are in the machine native byte order.
+
+A vhost-user message consists of 3 header fields and a payload.
+
++-+---+--+-+
+| request | flags | size | payload |
++-+---+--+-+
+
+Header
+--
+
+:request: 32-bit type of the request
+
+:flags: 32-bit bit field
+
+- Lower 2 bits are the version (currently 0x01)
+- Bit 2 is the reply flag - needs to be sent on each reply from the slave
+- Bit 3 is the need_reply flag - see :ref:`REPLY_ACK ` for
+  details.
+
+:size: 32-bit size of the payload
+
+Payload
+---
+
+Depending on the request type, **payload** can be:
+
+A single 64-bit integer
+^^^
+
++-+
+| u64 |
++-+
+
+:u64: a 64-bit unsigned integer
+
+A vring state description
+^
+
++---+-+
+| index | num |
++---+-+
+
+:index: a 32-bit index
+
+:num: a 32-bit number
+
+A vring address description
+^^^
+
++---+---+--++--+---+-+
+| index | flags | size | descriptor | used | available | log |
++---+---+--++--+---+-+
+
+:index: a 32-bit vring index
+
+:flags: a 32-bit vring flags
+
+:descriptor: a 64-bit ring address of the vring descriptor table
+
+:used: a 64-bit ring address of the vring used ring
+
+:available: a 64-bit ring address of the vring available ring
+
+:log: a 64-bit guest address for logging
+
+Note that a ring address is an IOVA if ``VIRTIO_F_IOMMU_PLATFORM`` has
+been negotiated. Otherwise it is a user address.
+
+Memory regions description
+^^
+
++-+-+-+-+-+
+| num regions | padding | region0 | ... | region7 |
++-+-+-+-+-+
+
+:num regions: a 32-bit number of regions
+
+:padding: 32-bit
+
+A region is:
+
++---+--+--+-+
+| guest address | size | user address | mmap offset |
++---+--+--+-+
+
+:guest address: a 64-bit guest address of the region
+
+:size: a 64-bit size
+
+:user address: a 64-bit user address
+
+:mmap offset: 64-bit offset where region starts in the mapped memory
+
+Log description
+^^^
+
++--++
+| log size | log offset |

Re: [Qemu-devel] State of QEMU CI as we enter 4.0

[Alex Bennée]

Ed Vielmetti  writes:

> We have been trying to merge the Gitlab runner patches for arm64
> for over a year now; see
>
> https://gitlab.com/gitlab-org/gitlab-runner/merge_requests/725

Yes I found that one. I'm trying to work out exactly how there build
system works. It seems to build all architectures on the same host using
QEMU to do so. I suspect this has never actually been run on a non-x86
host so I'm seeing if there is anything I can fix.

I've already hit a bug with Debian's QEMU packaging which assumes that
an AArch64 box always supports AArch32 which isn't true on the TX
machines:

  https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=924667

> I have not yet sorted out who at Gitlab has the ability to get
> this change implemented - their management structure is
> not something that I have sorted out yet, and I can't tell whether
> this lack of forward progress is something best to tackle by
> technical merit or by appealing to management.

What about Shippable? I saw the press release you guys did but it is not
entirely clear if I need a paid licensed Bring You Own Node or if is there a
free option for FLOSS projects?

>
> On Fri, Mar 15, 2019 at 6:24 AM Fam Zheng  wrote:
>
>>
>>
>> > On Mar 15, 2019, at 17:58, Alex Bennée  wrote:
>> >
>> >
>> > Fam Zheng  writes:
>> >
>> >>> On Mar 15, 2019, at 16:57, Alex Bennée  wrote:
>> >>>
>> >>> I had installed the gitlab-runner from the Debian repo but it was out
>> >>> of date and didn't seem to work correctly.
>> >>
>> >> If there can be a sidecar x86 box next to the test bot, it can be the
>> >> controller node which runs gitlab-runner, the test script (in
>> >> .gitlab-ci.yml) can then sshs into the actual env to run test
>> >> commands.
>> >
>> > Sure although that just adds complexity compared to spinning up a box in
>> > the cloud ;-)
>>
>> In the middle is one controller node and a number of hetergeneous boxes it
>> knows how to control with ssh.
>>
>> (BTW patchew tester only relies on vanilla python3 to work, though clearly
>> it suffers from insufficient manpower assumed the SLA we'll need on the
>> merge test. It’s unfortunate that gitlab-runner is a binary.)
>>
>> Fam
>>


--
Alex Bennée

Re: [Qemu-devel] [PATCH 2/2] filemon: ensure watch IDs are unique to QFileMonitor scope

[Daniel P . Berrangé]

On Fri, Mar 15, 2019 at 01:24:42PM -0400, Bandan Das wrote:
> Daniel P. Berrangé  writes:
> ...
> >> Thanks, this fixes it! I had a related question about the way
> >> qemu_file_monitor_add_watch works.
> >> 
> >> Am I correct in understanding that if there is already a watch on a dir,
> >> we return back mon->nextid++ i.e the next free id. Why don't we return
> >> back the originally assigned watchid ?
> >
> > inotify watches are a per-directory scope thing, but this API is aiming
> > to present the ability to have per-file scope watches as it is more
> > convenient to have those semantics for some users in QEMU. Thus many
> > QEMU level watches are mapped to the same low level inotify watch.
> >
> > The watch ID is used to unregister a watch later, and while I could have
> > done ref counting against a common watch ID, I find it clearer to maintain
> > separate watch IDs for every thing the caller watches. If nothing else it
> > makes the debugging easier as you can see the relation between events
> > received and the original watch registration.
> >
> Thanks, this makes sense. I think an advantage of having a refcounting
> mechanism is that we won't run out of watchids because some caller
> ended up adding a watch on the same dir repeatedly.

The watchid number is global to the QFileMonitor object, so if you
repeatedly create & delete watches on the same dir you're still going
to use up watch ids. You'll only save if you create & delete per-file
watches within the dir. Given that the guest OS can trigger create
/ delete of directories though, which in turn triggers create/delete
of watches, it looks like we should at the very least check for
overflow.

BTW, does USB-MTP have any limit on the number of objects it will
permit the guest to access ? something ought to limit the memory
usage of resources allocated per dir, including the watch state.

Regards,
Daniel
-- 
|: https://berrange.com  -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
|: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|

Re: [Qemu-devel] [PATCH] target/riscv: Fix manually parsed 16 bit insn

[Alistair Francis]

On Fri, Mar 15, 2019 at 7:15 AM Bastian Koppelmann
 wrote:
>
> during the refactor to decodetree we removed the manual decoding that is
> necessary for c.jal/c.addiw and removed the translation of c.flw/c.ld
> and c.fsw/c.sd. This reintroduces the manual parsing and the
> omited implementation.
>
> Signed-off-by: Bastian Koppelmann 

Reviewed-by: Alistair Francis 
Tested-by: Alistair Francis 

This fixes the 32-bit failures I was seeing.

Alistair

> ---
>  target/riscv/insn_trans/trans_rvc.inc.c | 30 -
>  1 file changed, 25 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvc.inc.c 
> b/target/riscv/insn_trans/trans_rvc.inc.c
> index bcdf64d3b7..5819f53f90 100644
> --- a/target/riscv/insn_trans/trans_rvc.inc.c
> +++ b/target/riscv/insn_trans/trans_rvc.inc.c
> @@ -44,10 +44,19 @@ static bool trans_c_flw_ld(DisasContext *ctx, 
> arg_c_flw_ld *a)
>  {
>  #ifdef TARGET_RISCV32
>  /* C.FLW ( RV32FC-only ) */
> -return false;
> +REQUIRE_FPU;
> +REQUIRE_EXT(ctx, RVF);
> +
> +arg_c_lw tmp;
> +decode_insn16_extract_cl_w(, ctx->opcode);
> +arg_flw arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
> +return trans_flw(ctx, );
>  #else
>  /* C.LD ( RV64C/RV128C-only ) */
> -return false;
> +arg_c_fld tmp;
> +decode_insn16_extract_cl_d(, ctx->opcode);
> +arg_ld arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
> +return trans_ld(ctx, );
>  #endif
>  }
>
> @@ -67,10 +76,19 @@ static bool trans_c_fsw_sd(DisasContext *ctx, 
> arg_c_fsw_sd *a)
>  {
>  #ifdef TARGET_RISCV32
>  /* C.FSW ( RV32FC-only ) */
> -return false;
> +REQUIRE_FPU;
> +REQUIRE_EXT(ctx, RVF);
> +
> +arg_c_sw tmp;
> +decode_insn16_extract_cs_w(, ctx->opcode);
> +arg_fsw arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
> +return trans_fsw(ctx, );
>  #else
>  /* C.SD ( RV64C/RV128C-only ) */
> -return false;
> +arg_c_fsd tmp;
> +decode_insn16_extract_cs_d(, ctx->opcode);
> +arg_sd arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
> +return trans_sd(ctx, );
>  #endif
>  }
>
> @@ -88,7 +106,9 @@ static bool trans_c_jal_addiw(DisasContext *ctx, 
> arg_c_jal_addiw *a)
>  {
>  #ifdef TARGET_RISCV32
>  /* C.JAL */
> -arg_jal arg = { .rd = 1, .imm = a->imm };
> +arg_c_j tmp;
> +decode_insn16_extract_cj(, ctx->opcode);
> +arg_jal arg = { .rd = 1, .imm = tmp.imm };
>  return trans_jal(ctx, );
>  #else
>  /* C.ADDIW */
> --
> 2.21.0
>
>

Re: [Qemu-devel] [PATCH] authz: Use OBJECT_CHECK() on objects

[Daniel P . Berrangé]

On Fri, Mar 15, 2019 at 06:12:18PM +0100, Philippe Mathieu-Daudé wrote:
> TYPE_QAUTHZ is an abstract object of type TYPE_OBJECT. All other
> are children of TYPE_QAUTHZ, thus also objects.
> 
> Keep INTERFACE_CHECK() for interfaces, and use OBJECT_CHECK() on
> objects.

Hmm

  #define OBJECT_CHECK(type, obj, name) \
((type *)object_dynamic_cast_assert(OBJECT(obj), (name), \
__FILE__, __LINE__, __func__))

  #define INTERFACE_CHECK(interface, obj, name) \
((interface *)object_dynamic_cast_assert(OBJECT((obj)), (name), \
 __FILE__, __LINE__, __func__))

/me now wonders why INTERFACE_CHECK needs to exist at all


> 
> Reported-by: Markus Armbruster 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  include/authz/base.h | 4 ++--
>  include/authz/list.h | 4 ++--
>  include/authz/listfile.h | 4 ++--
>  include/authz/pamacct.h  | 4 ++--
>  include/authz/simple.h   | 4 ++--
>  5 files changed, 10 insertions(+), 10 deletions(-)

Reviewed-by: Daniel P. Berrangé 


Regards,
Daniel
-- 
|: https://berrange.com  -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
|: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|

Re: [Qemu-devel] [PATCH 2/2] filemon: ensure watch IDs are unique to QFileMonitor scope

[Bandan Das]

Daniel P. Berrangé  writes:
...
>> Thanks, this fixes it! I had a related question about the way
>> qemu_file_monitor_add_watch works.
>> 
>> Am I correct in understanding that if there is already a watch on a dir,
>> we return back mon->nextid++ i.e the next free id. Why don't we return
>> back the originally assigned watchid ?
>
> inotify watches are a per-directory scope thing, but this API is aiming
> to present the ability to have per-file scope watches as it is more
> convenient to have those semantics for some users in QEMU. Thus many
> QEMU level watches are mapped to the same low level inotify watch.
>
> The watch ID is used to unregister a watch later, and while I could have
> done ref counting against a common watch ID, I find it clearer to maintain
> separate watch IDs for every thing the caller watches. If nothing else it
> makes the debugging easier as you can see the relation between events
> received and the original watch registration.
>
Thanks, this makes sense. I think an advantage of having a refcounting
mechanism is that we won't run out of watchids because some caller
ended up adding a watch on the same dir repeatedly.

> Regards,
> Daniel

Re: [Qemu-devel] [PATCH 6/8] Clean up ill-advised or unusual header guards

[Markus Armbruster]

Philippe Mathieu-Daudé  writes:

> On 3/15/19 3:51 PM, Markus Armbruster wrote:
>> Leading underscores are ill-advised because such identifiers are
>> reserved.  Trailing underscores are merely ugly.  Strip both.
>> 
>> Our header guards commonly end in _H.  Normalize the exceptions.
>> 
>> Done with scripts/clean-header-guards.pl.
>> 
>> Signed-off-by: Markus Armbruster 
>> ---
>>  block/crypto.h | 6 +++---
>>  hw/i386/amd_iommu.h| 4 ++--
>>  hw/tpm/tpm_ioctl.h | 7 ---
>>  hw/xtensa/xtensa_memory.h  | 4 ++--
>>  include/authz/base.h   | 7 +++
>>  include/authz/list.h   | 7 +++
>>  include/authz/simple.h | 7 +++
>>  include/chardev/spice.h| 4 ++--
>>  include/hw/ppc/pnv.h   | 7 ---
>>  include/hw/ppc/pnv_core.h  | 7 ---
>>  include/hw/ppc/pnv_lpc.h   | 7 ---
>>  include/hw/ppc/pnv_occ.h   | 7 ---
>>  include/hw/ppc/pnv_psi.h   | 7 ---
>>  include/hw/ppc/pnv_xscom.h | 7 ---
>>  include/hw/ppc/spapr_ovec.h| 7 ---
>>  include/hw/timer/pl031.h   | 4 ++--
>>  include/hw/virtio/vhost-vsock.h| 6 +++---
>>  include/hw/virtio/virtio-crypto.h  | 6 +++---
>>  include/hw/xen/start_info.h| 6 +++---
>>  include/hw/xtensa/mx_pic.h | 4 ++--
>>  include/qemu/drm.h | 4 ++--
>>  include/qemu/jhash.h   | 6 +++---
>>  include/sysemu/hvf.h   | 5 +++--
>>  linux-user/xtensa/syscall_nr.h | 6 +++---
>>  linux-user/xtensa/target_structs.h | 4 ++--
>>  linux-user/xtensa/termbits.h   | 6 +++---
>>  qga/vss-win32/vss-handles.h| 4 ++--
>>  slirp/src/debug.h  | 6 +++---
>>  slirp/src/stream.h | 6 +++---
>>  slirp/src/util.h   | 5 +++--
>>  slirp/src/vmstate.h| 5 +++--
>>  target/i386/hax-i386.h | 4 ++--
>>  target/i386/hax-interface.h| 4 ++--
>>  target/i386/hvf/hvf-i386.h | 4 ++--
>>  target/i386/hvf/vmcs.h | 4 ++--
>>  target/i386/hvf/x86_emu.h  | 5 +++--
>>  target/i386/hvf/x86_flags.h| 7 ---
>>  target/i386/hvf/x86_mmu.h  | 7 ---
>>  target/riscv/pmp.h | 4 ++--
>>  target/sparc/asi.h | 6 +++---
>>  tests/libqos/e1000e.h  | 4 ++--
>>  tests/libqos/sdhci.h   | 4 ++--
>>  42 files changed, 121 insertions(+), 110 deletions(-)
>> 
>> diff --git a/block/crypto.h b/block/crypto.h
>> index dd7d47903c..b935695e79 100644
>> --- a/block/crypto.h
>> +++ b/block/crypto.h
>> @@ -18,8 +18,8 @@
>>   *
>>   */
>>  
>> -#ifndef BLOCK_CRYPTO_H__
>> -#define BLOCK_CRYPTO_H__
>> +#ifndef BLOCK_CRYPTO_H
>> +#define BLOCK_CRYPTO_H
>>  
>>  #define BLOCK_CRYPTO_OPT_DEF_KEY_SECRET(prefix, helpstr)\
>>  {   \
>> @@ -94,4 +94,4 @@ block_crypto_create_opts_init(QDict *opts, Error **errp);
>>  QCryptoBlockOpenOptions *
>>  block_crypto_open_opts_init(QDict *opts, Error **errp);
>>  
>> -#endif /* BLOCK_CRYPTO_H__ */
>> +#endif /* BLOCK_CRYPTO_H */
>> diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h
>> index 0ff9095f32..3a694b186b 100644
>> --- a/hw/i386/amd_iommu.h
>> +++ b/hw/i386/amd_iommu.h
>> @@ -18,8 +18,8 @@
>>   * with this program; if not, see .
>>   */
>>  
>> -#ifndef AMD_IOMMU_H_
>> -#define AMD_IOMMU_H_
>> +#ifndef AMD_IOMMU_H
>> +#define AMD_IOMMU_H
>>  
>>  #include "hw/hw.h"
>>  #include "hw/pci/pci.h"
>> diff --git a/hw/tpm/tpm_ioctl.h b/hw/tpm/tpm_ioctl.h
>> index 59a0b0595d..f5f5c553a9 100644
>> --- a/hw/tpm/tpm_ioctl.h
>> +++ b/hw/tpm/tpm_ioctl.h
>> @@ -5,8 +5,9 @@
>>   *
>>   * This file is licensed under the terms of the 3-clause BSD license
>>   */
>> -#ifndef _TPM_IOCTL_H_
>> -#define _TPM_IOCTL_H_
>> +
>> +#ifndef TPM_IOCTL_H
>> +#define TPM_IOCTL_H
>>  
>>  #include 
>>  #include 
>> @@ -267,4 +268,4 @@ enum {
>>  CMD_SET_BUFFERSIZE,
>>  };
>>  
>> -#endif /* _TPM_IOCTL_H */
>> +#endif /* TPM_IOCTL_H */
>> diff --git a/hw/xtensa/xtensa_memory.h b/hw/xtensa/xtensa_memory.h
>> index e9aa08749d..89125c4a0d 100644
>> --- a/hw/xtensa/xtensa_memory.h
>> +++ b/hw/xtensa/xtensa_memory.h
>> @@ -25,8 +25,8 @@
>>   * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>>   */
>>  
>> -#ifndef _XTENSA_MEMORY_H
>> -#define _XTENSA_MEMORY_H
>> +#ifndef XTENSA_MEMORY_H
>> +#define XTENSA_MEMORY_H
>>  
>>  #include "qemu-common.h"
>>  #include "cpu.h"
>> diff --git a/include/authz/base.h b/include/authz/base.h
>> index 77dcd54c4c..05f1df845c 100644
>> --- a/include/authz/base.h
>> +++ b/include/authz/base.h
>> @@ -18,8 +18,8 @@
>>   *
>>   */
>>  
>> -#ifndef QAUTHZ_BASE_H__
>> -#define QAUTHZ_BASE_H__
>> +#ifndef QAUTHZ_BASE_H
>> +#define QAUTHZ_BASE_H
>>  
>>  #include "qemu-common.h"
>>  #include "qapi/error.h"
>> @@ -108,5 +108,4 @@ bool 

[Qemu-devel] [PATCH] authz: Use OBJECT_CHECK() on objects

[Philippe Mathieu-Daudé]

TYPE_QAUTHZ is an abstract object of type TYPE_OBJECT. All other
are children of TYPE_QAUTHZ, thus also objects.

Keep INTERFACE_CHECK() for interfaces, and use OBJECT_CHECK() on
objects.

Reported-by: Markus Armbruster 
Signed-off-by: Philippe Mathieu-Daudé 
---
 include/authz/base.h | 4 ++--
 include/authz/list.h | 4 ++--
 include/authz/listfile.h | 4 ++--
 include/authz/pamacct.h  | 4 ++--
 include/authz/simple.h   | 4 ++--
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/include/authz/base.h b/include/authz/base.h
index 77dcd54c4c..55ac9581ad 100644
--- a/include/authz/base.h
+++ b/include/authz/base.h
@@ -35,8 +35,8 @@
  OBJECT_GET_CLASS(QAuthZClass, (obj), \
   TYPE_QAUTHZ)
 #define QAUTHZ(obj) \
- INTERFACE_CHECK(QAuthZ, (obj), \
- TYPE_QAUTHZ)
+ OBJECT_CHECK(QAuthZ, (obj), \
+  TYPE_QAUTHZ)
 
 typedef struct QAuthZ QAuthZ;
 typedef struct QAuthZClass QAuthZClass;
diff --git a/include/authz/list.h b/include/authz/list.h
index a7225a747c..138ae7047c 100644
--- a/include/authz/list.h
+++ b/include/authz/list.h
@@ -33,8 +33,8 @@
 OBJECT_GET_CLASS(QAuthZListClass, (obj),\
   TYPE_QAUTHZ_LIST)
 #define QAUTHZ_LIST(obj) \
-INTERFACE_CHECK(QAuthZList, (obj),  \
-TYPE_QAUTHZ_LIST)
+OBJECT_CHECK(QAuthZList, (obj), \
+ TYPE_QAUTHZ_LIST)
 
 typedef struct QAuthZList QAuthZList;
 typedef struct QAuthZListClass QAuthZListClass;
diff --git a/include/authz/listfile.h b/include/authz/listfile.h
index bcc8d80743..ebbd5a4288 100644
--- a/include/authz/listfile.h
+++ b/include/authz/listfile.h
@@ -34,8 +34,8 @@
 OBJECT_GET_CLASS(QAuthZListFileClass, (obj),\
   TYPE_QAUTHZ_LIST_FILE)
 #define QAUTHZ_LIST_FILE(obj) \
-INTERFACE_CHECK(QAuthZListFile, (obj),  \
-TYPE_QAUTHZ_LIST_FILE)
+OBJECT_CHECK(QAuthZListFile, (obj), \
+ TYPE_QAUTHZ_LIST_FILE)
 
 typedef struct QAuthZListFile QAuthZListFile;
 typedef struct QAuthZListFileClass QAuthZListFileClass;
diff --git a/include/authz/pamacct.h b/include/authz/pamacct.h
index 6e3046e528..cad5b11d47 100644
--- a/include/authz/pamacct.h
+++ b/include/authz/pamacct.h
@@ -33,8 +33,8 @@
  OBJECT_GET_CLASS(QAuthZPAMClass, (obj), \
   TYPE_QAUTHZ_PAM)
 #define QAUTHZ_PAM(obj) \
- INTERFACE_CHECK(QAuthZPAM, (obj), \
- TYPE_QAUTHZ_PAM)
+ OBJECT_CHECK(QAuthZPAM, (obj), \
+  TYPE_QAUTHZ_PAM)
 
 typedef struct QAuthZPAM QAuthZPAM;
 typedef struct QAuthZPAMClass QAuthZPAMClass;
diff --git a/include/authz/simple.h b/include/authz/simple.h
index ef13958269..30b932dfeb 100644
--- a/include/authz/simple.h
+++ b/include/authz/simple.h
@@ -32,8 +32,8 @@
 OBJECT_GET_CLASS(QAuthZSimpleClass, (obj),\
   TYPE_QAUTHZ_SIMPLE)
 #define QAUTHZ_SIMPLE(obj) \
-INTERFACE_CHECK(QAuthZSimple, (obj),  \
-TYPE_QAUTHZ_SIMPLE)
+OBJECT_CHECK(QAuthZSimple, (obj), \
+ TYPE_QAUTHZ_SIMPLE)
 
 typedef struct QAuthZSimple QAuthZSimple;
 typedef struct QAuthZSimpleClass QAuthZSimpleClass;
-- 
2.20.1

Re: [Qemu-devel] [PATCH v2 00/12] bundle edk2 platform firmware with QEMU

[Philippe Mathieu-Daudé]

Hi,

>From my previous experience with the tests/ patches, I understood we
could still send PR that improve testing after soft freeze.
This series doesn't modify the QEMU binaries, it add EDK2 firmware blobs
in roms/ and rules to rebuild these roms.
These roms are useful for the ACPI tests introduced in commits
09a274d82f and 503bb0b975a on the arm/virt board.

There is 1 direct change:

1/ in the root Makefile, the 'make install' rule installs one new file:
   - edk2-licenses.txt

And there are 2 other changes which require user specific action:

2/ Set the environment variable 'INSTALL_BLOBS', the 'make install' rule
will install the firmware blobs and the firmware JSON descriptors

3/ a new 'efi' target rule in roms/Makefile

I'm planning to send a PR for this series but I want to check first if
there is any issue with the current policy/rules.

Thanks,

Phil.

On 3/13/19 10:00 PM, Laszlo Ersek wrote:
> Repo:   https://github.com/lersek/qemu.git
> Branch: edk2_build_v2
> 
> Version 1, that is:
>   [Qemu-devel] [PATCH 00/10] bundle edk2 platform firmware with QEMU
> 
> was posted at:
>   https://lists.gnu.org/archive/html/qemu-devel/2019-03/msg02846.html
>   20190309004826.9027-1-lersek@redhat.com">http://mid.mail-archive.com/20190309004826.9027-1-lersek@redhat.com
> 
> Updates in v2 are noted on each patch individually, in the Notes
> section.
> 
[...]
>>  .gitignore|   1 +
>>  MAINTAINERS   |  12 
>>  Makefile  |  22 +++---
>>  configure |   1 +
>>  pc-bios/README|   2 +-
>>  pc-bios/edk2-aarch64-code.fd  | Bin 67108864 -> 0 bytes
>>  pc-bios/edk2-aarch64-code.fd.xz   | Bin 0 -> 1146804 bytes
>>  pc-bios/edk2-arm-code.fd  | Bin 67108864 -> 0 bytes
>>  pc-bios/edk2-arm-code.fd.xz   | Bin 0 -> 1147852 bytes
>>  pc-bios/edk2-arm-vars.fd  | Bin 67108864 -> 0 bytes
>>  pc-bios/edk2-arm-vars.fd.xz   | Bin 0 -> 10008 bytes
>>  pc-bios/edk2-i386-code.fd | Bin 3653632 -> 0 bytes
>>  pc-bios/edk2-i386-code.fd.xz  | Bin 0 -> 1674764 bytes
>>  pc-bios/edk2-i386-secure-code.fd  | Bin 3653632 -> 0 bytes
>>  pc-bios/edk2-i386-secure-code.fd.xz   | Bin 0 -> 1870024 bytes
>>  pc-bios/edk2-i386-vars.fd | Bin 540672 -> 0 bytes
>>  pc-bios/edk2-i386-vars.fd.xz  | Bin 0 -> 320 bytes
>>  pc-bios/edk2-x86_64-code.fd   | Bin 3653632 -> 0 bytes
>>  pc-bios/edk2-x86_64-code.fd.xz| Bin 0 -> 1655276 bytes
>>  pc-bios/edk2-x86_64-secure-code.fd| Bin 3653632 -> 0 bytes
>>  pc-bios/edk2-x86_64-secure-code.fd.xz | Bin 0 -> 1889024 bytes
>>  roms/Makefile.edk2|  32 +---
>>  roms/edk2-build.sh|   2 +-
>>  roms/edk2-funcs.sh|   4 +--
>>  tests/Makefile.include|   2 +-
>>  25 files changed, 57 insertions(+), 21 deletions(-)

Re: [Qemu-devel] [PATCH 2/5] trace-events: Shorten file names in comments

[Markus Armbruster]

Stefan Hajnoczi  writes:

> On Thu, Mar 14, 2019 at 07:09:26PM +0100, Markus Armbruster wrote:
>> We spell out sub/dir/ in sub/dir/trace-events' comments pointing to
>> source files.  That's because when trace-events got split up, the
>> comments were moved verbatim.
>> 
>> Delete the sub/dir/ part from these comments.  Gets rid of several
>> misspellings.
>> 
>> Signed-off-by: Markus Armbruster 
>> ---
>
> git-am(1) cannot apply this patch:
>
>   Applying: trace-events: Shorten file names in comments
>   error: sha1 information is lacking or useless (hw/display/trace-events).
>   error: could not build fake ancestor
>   Patch failed at 0002 trace-events: Shorten file names in comments
>
> ?
>
> Stefan

My fault: I silently based on the build fix "[PATCH] ati-vga: fix
tracing".

Based-on: <20190312081143.24850-1-kra...@redhat.com>

Re: [Qemu-devel] [Xen-devel] [PATCH 6/6] xen-pt: Round pci regions sizes to XEN_PAGE_SIZE

[Andrew Cooper]

On 15/03/2019 09:17, Paul Durrant wrote:
>> -Original Message-
>> From: Jason Andryuk [mailto:jandr...@gmail.com]
>> Sent: 14 March 2019 18:16
>> To: Paul Durrant 
>> Cc: qemu-devel@nongnu.org; xen-de...@lists.xenproject.org; 
>> marma...@invisiblethingslab.com; Simon
>> Gaiser ; Stefano Stabellini 
>> ; Anthony Perard
>> 
>> Subject: Re: [PATCH 6/6] xen-pt: Round pci regions sizes to XEN_PAGE_SIZE
>>
>> On Wed, Mar 13, 2019 at 11:09 AM Paul Durrant  
>> wrote:
 -Original Message-
 From: Jason Andryuk [mailto:jandr...@gmail.com]
 Sent: 11 March 2019 18:02
 To: qemu-devel@nongnu.org
 Cc: xen-de...@lists.xenproject.org; marma...@invisiblethingslab.com; Simon 
 Gaiser
 ; Jason Andryuk ; 
 Stefano Stabellini
 ; Anthony Perard ; Paul 
 Durrant
 
 Subject: [PATCH 6/6] xen-pt: Round pci regions sizes to XEN_PAGE_SIZE

 From: Simon Gaiser 

 If a pci memory region has a size < XEN_PAGE_SIZE it can get located at
 an address which is not page aligned.
>>> IIRC the PCI spec says that the minimum memory region size should be at 
>>> least 4k. Should we even be
>> tolerating BARs smaller than that?
>>>   Paul
>>>
>> Hi, Paul.
>>
>> Simon found this, so it affects a real device.  Simon, do you recall
>> which device was affected?
>>
>> I think BARs only need to be power-of-two size and aligned, and 4k is
>> not a minimum.  16bytes may be a minimum, but I don't know what the
>> spec says.
>>
>> On an Ivy Bridge system, here are some of the devices with BARs smaller than 
>> 4K:
>> 00:16.0 Communication controller: Intel Corporation 7 Series/C210
>> Series Chipset Family MEI Controller #1 (rev 04)
>>Memory at d0735000 (64-bit, non-prefetchable) [disabled] [size=16]
>> 00:1d.0 USB controller: Intel Corporation 7 Series/C210 Series Chipset
>> Family USB Enhanced Host Controller #1 (rev 04) (prog-if 20 [EHCI])
>>Memory at d0739000 (32-bit, non-prefetchable) [disabled] [size=1K]
>> 00:1f.3 SMBus: Intel Corporation 7 Series/C210 Series Chipset Family
>> SMBus Controller (rev 04)
>>Memory at d0734000 (64-bit, non-prefetchable) [disabled] [size=256]
>> 02:00.0 System peripheral: JMicron Technology Corp. SD/MMC Host
>> Controller (rev 30)
>>Memory at d0503000 (32-bit, non-prefetchable) [disabled] [size=256]
>>
>> These examples are all 4K aligned, so this is not an issue on this machine.
>>
>> Reviewing the code, I'm now wondering if the following in
>> hw/xen/xen_pt.c:xen_pt_region_update is wrong:rc =
>> xc_domain_memory_mapping(xen_xc, xen_domid,
>>  XEN_PFN(guest_addr + XC_PAGE_SIZE - 1),
>>  XEN_PFN(machine_addr + XC_PAGE_SIZE - 
>> 1),
>>  XEN_PFN(size + XC_PAGE_SIZE - 1),
>>  op);
>>
>> If a bar of size 0x100 is at 0xd0500800, then the machine_addr passed
>> in would be 0xd0501000 which is past the actual location.  Should the
>> call arguments just be XEN_PFN(guest_addr) & XEN_PFN(machine_addr)?
>>
>> BARs smaller than a page would also be a problem if BARs for different
>> devices shared the same page.
> Exactly. We cannot pass them through with any degree of safety (not that 
> passthrough of an arbitrary device is a particularly safe thing to do 
> anyway). The xen-pt code would instead need to trap those BARs and perform 
> the accesses to the real BAR itself. Ultimately though I think we should be 
> retiring the xen-pt code in favour of a standalone emulator.

It doesn't matter if the BAR is smaller than 4k, if there are holes next
to it.

Do we know what the case is in practice for these USB controllers?

If the worst comes to the worst, we can re-enumerate the PCI bus to
ensure that all bars smaller than 4k still have 4k alignment between
them.  That way we can safely pass them through even when they are smaller.

~Andrew

Re: [Qemu-devel] [PATCH v14 00/25] Fixing record/replay and adding reverse debugging

[no-reply]

Patchew URL: 
https://patchew.org/QEMU/155265169782.20013.5884232667053404718.stgit@pasha-VirtualBox/



Hi,

This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.

=== TEST SCRIPT BEGIN ===
#!/bin/bash
time make docker-test-debug@fedora TARGET_LIST=x86_64-softmmu J=14 NETWORK=1
=== TEST SCRIPT END ===

clang -iquote /tmp/qemu-test/build/. -iquote . -iquote /tmp/qemu-test/src/tcg 
-iquote /tmp/qemu-test/src/tcg/i386 -I/tmp/qemu-test/src/linux-headers 
-I/tmp/qemu-test/build/linux-headers -iquote . -iquote /tmp/qemu-test/src 
-iquote /tmp/qemu-test/src/accel/tcg -iquote /tmp/qemu-test/src/include 
-I/tmp/qemu-test/src/tests/fp 
-I/tmp/qemu-test/src/tests/fp/berkeley-softfloat-3/source/include 
-I/tmp/qemu-test/src/tests/fp/berkeley-softfloat-3/source/8086-SSE 
-I/tmp/qemu-test/src/tests/fp/berkeley-testfloat-3/source 
-I/usr/include/pixman-1 -I/tmp/qemu-test/src/dtc/libfdt -Werror 
-DHAS_LIBSSH2_SFTP_FSYNC -pthread -I/usr/include/glib-2.0 
-I/usr/lib64/glib-2.0/include -fPIE -DPIE -m64 -mcx16 -D_GNU_SOURCE 
-D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes 
-Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes 
-fno-strict-aliasing -fno-common -fwrapv -std=gnu99 -Wno-string-plus-int 
-Wno-initializer-overrides -Wexpansion-to-defined -Wendif-labels 
-Wno-shift-negative-value -Wno-missing-include-dirs -Wempty-body 
-Wnested-externs -Wformat-security -Wformat-y2k -Winit-self 
-Wignored-qualifiers -Wold-style-definition -Wtype-limits 
-fstack-protector-strong -I/usr/include/p11-kit-1 -I/usr/include/libpng16 
-I/usr/include/spice-1 -I/usr/include/spice-server -I/usr/include/cacard 
-I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -I/usr/include/nss3 
-I/usr/include/nspr4 -pthread -I/usr/include/libmount -I/usr/include/blkid 
-I/usr/include/uuid -I/usr/include/pixman-1 -DHW_POISON_H -DTARGET_ARM  
-DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 
-DSOFTFLOAT_FAST_DIV64TO32 -DSOFTFLOAT_FAST_INT64  -DFLOAT16 -DFLOAT64 
-DEXTFLOAT80 -DFLOAT128 -DFLOAT_ROUND_ODD -DLONG_DOUBLE_IS_EXTFLOAT80  
-Wno-strict-prototypes -Wno-unknown-pragmas -Wno-uninitialized 
-Wno-missing-prototypes -Wno-return-type -Wno-unused-function -Wno-error -MMD 
-MP -MT writeCase_ab_f16.o -MF ./writeCase_ab_f16.d -fsanitize=undefined 
-fsanitize=address -g   -c -o writeCase_ab_f16.o 
/tmp/qemu-test/src/tests/fp/berkeley-testfloat-3/source/writeCase_ab_f16.c
clang -iquote /tmp/qemu-test/build/. -iquote . -iquote /tmp/qemu-test/src/tcg 
-iquote /tmp/qemu-test/src/tcg/i386 -I/tmp/qemu-test/src/linux-headers 
-I/tmp/qemu-test/build/linux-headers -iquote . -iquote /tmp/qemu-test/src 
-iquote /tmp/qemu-test/src/accel/tcg -iquote /tmp/qemu-test/src/include 
-I/tmp/qemu-test/src/tests/fp 
-I/tmp/qemu-test/src/tests/fp/berkeley-softfloat-3/source/include 
-I/tmp/qemu-test/src/tests/fp/berkeley-softfloat-3/source/8086-SSE 
-I/tmp/qemu-test/src/tests/fp/berkeley-testfloat-3/source 
-I/usr/include/pixman-1 -I/tmp/qemu-test/src/dtc/libfdt -Werror 
-DHAS_LIBSSH2_SFTP_FSYNC -pthread -I/usr/include/glib-2.0 
-I/usr/lib64/glib-2.0/include -fPIE -DPIE -m64 -mcx16 -D_GNU_SOURCE 
-D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes 
-Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes 
-fno-strict-aliasing -fno-common -fwrapv -std=gnu99 -Wno-string-plus-int 
-Wno-initializer-overrides -Wexpansion-to-defined -Wendif-labels 
-Wno-shift-negative-value -Wno-missing-include-dirs -Wempty-body 
-Wnested-externs -Wformat-security -Wformat-y2k -Winit-self 
-Wignored-qualifiers -Wold-style-definition -Wtype-limits 
-fstack-protector-strong -I/usr/include/p11-kit-1 -I/usr/include/libpng16 
-I/usr/include/spice-1 -I/usr/include/spice-server -I/usr/include/cacard 
-I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -I/usr/include/nss3 
-I/usr/include/nspr4 -pthread -I/usr/include/libmount -I/usr/include/blkid 
-I/usr/include/uuid -I/usr/include/pixman-1 -DHW_POISON_H -DTARGET_ARM  
-DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 
-DSOFTFLOAT_FAST_DIV64TO32 -DSOFTFLOAT_FAST_INT64  -DFLOAT16 -DFLOAT64 
-DEXTFLOAT80 -DFLOAT128 -DFLOAT_ROUND_ODD -DLONG_DOUBLE_IS_EXTFLOAT80  
-Wno-strict-prototypes -Wno-unknown-pragmas -Wno-uninitialized 
-Wno-missing-prototypes -Wno-return-type -Wno-unused-function -Wno-error -MMD 
-MP -MT writeCase_abc_f16.o -MF ./writeCase_abc_f16.d -fsanitize=undefined 
-fsanitize=address -g   -c -o writeCase_abc_f16.o 
/tmp/qemu-test/src/tests/fp/berkeley-testfloat-3/source/writeCase_abc_f16.c
clang -iquote /tmp/qemu-test/build/tests -iquote tests -iquote 
/tmp/qemu-test/src/tcg -iquote /tmp/qemu-test/src/tcg/i386 
-I/tmp/qemu-test/src/linux-headers -I/tmp/qemu-test/build/linux-headers -iquote 
. -iquote /tmp/qemu-test/src -iquote /tmp/qemu-test/src/accel/tcg -iquote 
/tmp/qemu-test/src/include -I/usr/include/pixman-1  
-I/tmp/qemu-test/src/dtc/libfdt 

Re: [Qemu-devel] [PATCH v2 08/12] pc-bios: add edk2 firmware binaries and variable store templates

[Philippe Mathieu-Daudé]

Hi Daniel,

On 3/15/19 12:28 PM, Daniel P. Berrangé wrote:
> On Thu, Mar 14, 2019 at 07:43:58PM +0100, Philippe Mathieu-Daudé wrote:
>> On 3/13/19 10:00 PM, Laszlo Ersek wrote:
>>> Add the files built by the last patch: (compressed) binaries, and the
>>> cumulative license text that covers them.
>>>
>>> Signed-off-by: Laszlo Ersek 
>>> ---
>>>
>>> Notes:
>>> v2:
>>> 
>>> - capture the compressed build outputs of the last patch; slightly
>>>   update the commit message [Dan, Michael, Phil]
>>> 
>>> - consequently, do not pick up Michal's and Michael's R-b's
>>
>> Well I was not explicit in my previous review: I simply checked the
>> Licenses match the EDK2 project, but I haven't review the binaries.
>> Ideally I'd rather submit the binaries from a CI system or a Docker
>> image than your workstation.
> 
> I think that point probably applies to all of the binary ROMs
> that QEMU is already distributing.
> 
> We have make rules that build them from the subdir, but we have
> no record of what kind of host they were built on by the maintainer
> which is troublesome for reproducability.
> 
> It would be nice if we had a standard dockerfile that was designated
> as the build environment for each of the ROMs (one docker file might
> be suitable for many of the ROMs in fact).

Actually I use docker to build EDK2:

https://github.com/philmd/edk2-docker/tree/aarch64_builds

Re: [Qemu-devel] [PATCH 2/2] filemon: ensure watch IDs are unique to QFileMonitor scope

[Daniel P . Berrangé]

On Fri, Mar 15, 2019 at 12:27:06PM -0400, Bandan Das wrote:
> Daniel P. Berrangé  writes:
> 
> > The watch IDs are mistakenly only unique within the scope of the
> > directory being monitored. This is not useful for clients which are
> > monitoring multiple directories. They require watch IDs to be unique
> > globally within the QFileMonitor scope.
> >
> > Signed-off-by: Daniel P. Berrangé 
> > ---
> >  tests/test-util-filemonitor.c | 116 +++---
> >  util/filemonitor-inotify.c|   5 +-
> >  2 files changed, 110 insertions(+), 11 deletions(-)
> >
> > diff --git a/tests/test-util-filemonitor.c b/tests/test-util-filemonitor.c
> > index ea3715a8f4..71a7cf5de0 100644
> > --- a/tests/test-util-filemonitor.c
> > +++ b/tests/test-util-filemonitor.c
> > @@ -35,6 +35,8 @@ enum {
> >  QFILE_MONITOR_TEST_OP_RENAME,
> >  QFILE_MONITOR_TEST_OP_TOUCH,
> >  QFILE_MONITOR_TEST_OP_UNLINK,
> > +QFILE_MONITOR_TEST_OP_MKDIR,
> > +QFILE_MONITOR_TEST_OP_RMDIR,
> >  };
> >  
> >  typedef struct {
> > @@ -298,6 +300,54 @@ test_file_monitor_events(void)
> >.eventid = QFILE_MONITOR_EVENT_DELETED },
> >  
> >  
> > +{ .type = QFILE_MONITOR_TEST_OP_MKDIR,
> > +  .filesrc = "fish", },
> > +{ .type = QFILE_MONITOR_TEST_OP_EVENT,
> > +  .filesrc = "fish", .watchid = 0,
> > +  .eventid = QFILE_MONITOR_EVENT_CREATED },
> > +
> > +
> > +{ .type = QFILE_MONITOR_TEST_OP_ADD_WATCH,
> > +  .filesrc = "fish/", .watchid = 4 },
> > +{ .type = QFILE_MONITOR_TEST_OP_ADD_WATCH,
> > +  .filesrc = "fish/one.txt", .watchid = 5 },
> > +{ .type = QFILE_MONITOR_TEST_OP_CREATE,
> > +  .filesrc = "fish/one.txt", },
> > +{ .type = QFILE_MONITOR_TEST_OP_EVENT,
> > +  .filesrc = "one.txt", .watchid = 4,
> > +  .eventid = QFILE_MONITOR_EVENT_CREATED },
> > +{ .type = QFILE_MONITOR_TEST_OP_EVENT,
> > +  .filesrc = "one.txt", .watchid = 5,
> > +  .eventid = QFILE_MONITOR_EVENT_CREATED },
> > +
> > +
> > +{ .type = QFILE_MONITOR_TEST_OP_DEL_WATCH,
> > +  .filesrc = "fish/one.txt", .watchid = 5 },
> > +{ .type = QFILE_MONITOR_TEST_OP_RENAME,
> > +  .filesrc = "fish/one.txt", .filedst = "two.txt", },
> > +{ .type = QFILE_MONITOR_TEST_OP_EVENT,
> > +  .filesrc = "one.txt", .watchid = 4,
> > +  .eventid = QFILE_MONITOR_EVENT_DELETED },
> > +{ .type = QFILE_MONITOR_TEST_OP_EVENT,
> > +  .filesrc = "two.txt", .watchid = 0,
> > +  .eventid = QFILE_MONITOR_EVENT_CREATED },
> > +{ .type = QFILE_MONITOR_TEST_OP_EVENT,
> > +  .filesrc = "two.txt", .watchid = 2,
> > +  .eventid = QFILE_MONITOR_EVENT_CREATED },
> > +
> > +
> > +{ .type = QFILE_MONITOR_TEST_OP_RMDIR,
> > +  .filesrc = "fish", },
> > +{ .type = QFILE_MONITOR_TEST_OP_EVENT,
> > +  .filesrc = "", .watchid = 4,
> > +  .eventid = QFILE_MONITOR_EVENT_IGNORED },
> > +{ .type = QFILE_MONITOR_TEST_OP_EVENT,
> > +  .filesrc = "fish", .watchid = 0,
> > +  .eventid = QFILE_MONITOR_EVENT_DELETED },
> > +{ .type = QFILE_MONITOR_TEST_OP_DEL_WATCH,
> > +  .filesrc = "fish", .watchid = 4 },
> > +
> > +
> >  { .type = QFILE_MONITOR_TEST_OP_UNLINK,
> >.filesrc = "two.txt", },
> >  { .type = QFILE_MONITOR_TEST_OP_EVENT,
> > @@ -366,6 +416,8 @@ test_file_monitor_events(void)
> >  int fd;
> >  int watchid;
> >  struct utimbuf ubuf;
> > +char *watchdir;
> > +const char *watchfile;
> >  
> >  pathsrc = g_strdup_printf("%s/%s", dir, op->filesrc);
> >  if (op->filedst) {
> > @@ -378,13 +430,26 @@ test_file_monitor_events(void)
> >  g_printerr("Add watch %s %s %d\n",
> > dir, op->filesrc, op->watchid);
> >  }
> > +if (op->filesrc && strchr(op->filesrc, '/')) {
> > +watchdir = g_strdup_printf("%s/%s", dir, op->filesrc);
> > +watchfile = strrchr(watchdir, '/');
> > +*(char *)watchfile = '\0';
> > +watchfile++;
> > +if (*watchfile == '\0') {
> > +watchfile = NULL;
> > +}
> > +} else {
> > +watchdir = g_strdup(dir);
> > +watchfile = op->filesrc;
> > +}
> >  watchid =
> >  qemu_file_monitor_add_watch(mon,
> > -dir,
> > -op->filesrc,
> > +watchdir,
> > +watchfile,
> >  qemu_file_monitor_test_handler,
> >  ,
> >  _err);
> 

Re: [Qemu-devel] [PATCH 1/2] target/mips: Optimize ILVOD. MSA instructions

[Richard Henderson]

On 3/15/19 5:02 AM, Mateja Marjanovic wrote:
> From: Mateja Marjanovic 
> 
> Optimize set of MSA instructions ILVOD, using directly
> tcg registers and performing logic on them insted of
> using helpers.
> Performance measurement is done by executing the
> instructions large number of times on a computer
> with Intel Core i7-3770 CPU @ 3.40GHz×8.
> 
>  instruction ||before||after   ||
> ==
>  ilvod.b:  ||   66.97 ms   ||  26.34 ms  ||
>  ilvod.h:  ||   44.75 ms   ||  25.17 ms  ||
>  ilvod.w:  ||   41.27 ms   ||  24.37 ms  ||
>  ilvod.d:  ||   41.75 ms   ||  20.50 ms  ||
> 
> Signed-off-by: Mateja Marjanovic 
> ---
>  target/mips/helper.h |   1 -
>  target/mips/msa_helper.c |  51 
>  target/mips/translate.c  | 119 
> ++-
>  3 files changed, 118 insertions(+), 53 deletions(-)
> 
> diff --git a/target/mips/helper.h b/target/mips/helper.h
> index a6d687e..d162836 100644
> --- a/target/mips/helper.h
> +++ b/target/mips/helper.h
> @@ -865,7 +865,6 @@ DEF_HELPER_5(msa_pckod_df, void, env, i32, i32, i32, i32)
>  DEF_HELPER_5(msa_ilvl_df, void, env, i32, i32, i32, i32)
>  DEF_HELPER_5(msa_ilvr_df, void, env, i32, i32, i32, i32)
>  DEF_HELPER_5(msa_ilvev_df, void, env, i32, i32, i32, i32)
> -DEF_HELPER_5(msa_ilvod_df, void, env, i32, i32, i32, i32)
>  DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
>  DEF_HELPER_5(msa_srar_df, void, env, i32, i32, i32, i32)
>  DEF_HELPER_5(msa_srlr_df, void, env, i32, i32, i32, i32)
> diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
> index 9d9dafe..cbcfd57 100644
> --- a/target/mips/msa_helper.c
> +++ b/target/mips/msa_helper.c
> @@ -1363,57 +1363,6 @@ void helper_msa_ilvev_df(CPUMIPSState *env, uint32_t 
> df, uint32_t wd,
>  }
>  }
>  
> -void helper_msa_ilvod_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
> - uint32_t ws, uint32_t wt)
> -{
> -wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
> -wr_t *pws = &(env->active_fpu.fpr[ws].wr);
> -wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
> -
> -switch (df) {
> -case DF_BYTE:
> -pwd->b[0]  = pwt->b[1];
> -pwd->b[1]  = pws->b[1];
> -pwd->b[2]  = pwt->b[3];
> -pwd->b[3]  = pws->b[3];
> -pwd->b[4]  = pwt->b[5];
> -pwd->b[5]  = pws->b[5];
> -pwd->b[6]  = pwt->b[7];
> -pwd->b[7]  = pws->b[7];
> -pwd->b[8]  = pwt->b[9];
> -pwd->b[9]  = pws->b[9];
> -pwd->b[10] = pwt->b[11];
> -pwd->b[11] = pws->b[11];
> -pwd->b[12] = pwt->b[13];
> -pwd->b[13] = pws->b[13];
> -pwd->b[14] = pwt->b[15];
> -pwd->b[15] = pws->b[15];
> -break;
> -case DF_HALF:
> -pwd->h[0] = pwt->h[1];
> -pwd->h[1] = pws->h[1];
> -pwd->h[2] = pwt->h[3];
> -pwd->h[3] = pws->h[3];
> -pwd->h[4] = pwt->h[5];
> -pwd->h[5] = pws->h[5];
> -pwd->h[6] = pwt->h[7];
> -pwd->h[7] = pws->h[7];
> -break;
> -case DF_WORD:
> -pwd->w[0] = pwt->w[1];
> -pwd->w[1] = pws->w[1];
> -pwd->w[2] = pwt->w[3];
> -pwd->w[3] = pws->w[3];
> -break;
> -case DF_DOUBLE:
> -pwd->d[0] = pwt->d[1];
> -pwd->d[1] = pws->d[1];
> -break;
> -default:
> -assert(0);
> -}
> -}
> -
>  void helper_msa_ilvl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
>  uint32_t ws, uint32_t wt)
>  {
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index b4a1103..101d2de 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -28889,6 +28889,108 @@ static void gen_msa_bit(CPUMIPSState *env, 
> DisasContext *ctx)
>  tcg_temp_free_i32(tws);
>  }
>  
> +static inline void gen_ilvod_b(CPUMIPSState *env, uint32_t wd,
> +   uint32_t ws, uint32_t wt) {

{ on next line.

> +TCGv_i64 t0 = tcg_temp_new_i64();
> +TCGv_i64 t1 = tcg_temp_new_i64();
> +
> +uint64_t mask = (1ULL << 8) - 1;
> +mask |= mask << 16;
> +mask |= mask << 32;
> +mask <<= 8;

This is a constant.  Clearer to just write 0xff00ff00ff00ff00ull;

> +static inline void gen_ilvod_h(CPUMIPSState *env, uint32_t wd,
> +   uint32_t ws, uint32_t wt) {

Likewise.

> +uint64_t mask = (1ULL << 16) - 1;
> +mask |= mask << 32;
> +mask <<= 16;

0xull

> +static inline void gen_ilvod_w(CPUMIPSState *env, uint32_t wd,
> +   uint32_t ws, uint32_t wt) {

Likewise.

> +tcg_gen_andi_i64(t0, msa_wr_d[wt * 2], mask);
> +tcg_gen_shri_i64(t0, t0, 32);
> +tcg_gen_or_i64(t1, t1, t0);
> +tcg_gen_andi_i64(t0, msa_wr_d[ws * 2], mask);
> +tcg_gen_or_i64(t1, t1, t0);

This can fold down to deposit.

tcg_gen_shri_i64(t0, msa_wr_d[wt * 2], 32);
tcg_gen_deposit_i64(msa_wr_d[wd * 2], 

Re: [Qemu-devel] [PATCH 2/2] target/mips: Optimize ILVEV. MSA instructions

[Richard Henderson]

On 3/15/19 5:02 AM, Mateja Marjanovic wrote:
> +static inline void gen_ilvev_b(CPUMIPSState *env, uint32_t wd,
> +   uint32_t ws, uint32_t wt) {
> +TCGv_i64 t0 = tcg_temp_new_i64();
> +TCGv_i64 t1 = tcg_temp_new_i64();
> +
> +uint64_t mask = (1ULL << 8) - 1;
> +mask |= mask << 16;
> +mask |= mask << 32;
> +tcg_gen_movi_i64(t1, 0);

Identical comments as for the previous patch.


r~

Re: [Qemu-devel] State of QEMU CI as we enter 4.0

[Paolo Bonzini]

On 15/03/19 17:28, Peter Maydell wrote:
> On Fri, 15 Mar 2019 at 15:12, Stefan Hajnoczi  wrote:
>> How should all sub-maintainers be checking their pull requests?
>>
>> We should have information and a strict policy on minimum testing of
>> pull requests.  Right now I imagine it varies a lot between
>> sub-maintainers.
>>
>> For my block pull requests I run qemu-iotests locally and also push to
>> GitHub to trigger Travis CI.
> 
> For my arm pullreqs I do light smoke testing on x86-64 typically
> (and let the tests on merge catch any portability issues), unless
> I'm particularly suspicious that something should be tested
> more widely :-)

For my pull requests I do "make docker-test-{full,mingw,clang}@fedora
docker-test-full@{centos7,ubuntu} vm-build-freebsd".  I also have
recently bought a Macincloud account that I use occasionally for build
testing.

Paolo

Re: [Qemu-devel] [PATCH 1/2] target/mips: Optimize ILVOD. MSA instructions

[Aleksandar Markovic]

> From: Mateja Marjanovic 
> Subject: [PATCH 1/2] target/mips: Optimize ILVOD. MSA instructions
> 
> From: Mateja Marjanovic 
> 
> Optimize set of MSA instructions ILVOD, using directly
> tcg registers and performing logic on them insted of
> using helpers.

insted -> instead

> Performance measurement is done by executing the
> instructions large number of times on a computer
> with Intel Core i7-3770 CPU @ 3.40GHz×8.
> 
>  instruction ||before||after   ||
> ==
>  ilvod.b:||   66.97 ms   ||  26.34 ms  ||
>  ilvod.h:||   44.75 ms   ||  25.17 ms  ||
>  ilvod.w:||   41.27 ms   ||  24.37 ms  ||
>  ilvod.d:||   41.75 ms   ||  20.50 ms  ||
> 

Alignment looks wrong.

> Signed-off-by: Mateja Marjanovic 
> ---
>  target/mips/helper.h |   1 -
>  target/mips/msa_helper.c |  51 
>  target/mips/translate.c  | 119 
> ++-
>  3 files changed, 118 insertions(+), 53 deletions(-)
> 
> diff --git a/target/mips/helper.h b/target/mips/helper.h
> index a6d687e..d162836 100644
> --- a/target/mips/helper.h
> +++ b/target/mips/helper.h
> @@ -865,7 +865,6 @@ DEF_HELPER_5(msa_pckod_df, void, env, i32, i32, i32, i32)
>  DEF_HELPER_5(msa_ilvl_df, void, env, i32, i32, i32, i32)
>  DEF_HELPER_5(msa_ilvr_df, void, env, i32, i32, i32, i32)
>  DEF_HELPER_5(msa_ilvev_df, void, env, i32, i32, i32, i32)
> -DEF_HELPER_5(msa_ilvod_df, void, env, i32, i32, i32, i32)
>  DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
>  DEF_HELPER_5(msa_srar_df, void, env, i32, i32, i32, i32)
>  DEF_HELPER_5(msa_srlr_df, void, env, i32, i32, i32, i32)
> diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
> index 9d9dafe..cbcfd57 100644
> --- a/target/mips/msa_helper.c
> +++ b/target/mips/msa_helper.c
> @@ -1363,57 +1363,6 @@ void helper_msa_ilvev_df(CPUMIPSState *env, uint32_t 
> df, uint32_t > wd,
>  }
>  }
> 
> -void helper_msa_ilvod_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
> - uint32_t ws, uint32_t wt)
> -{
> -wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
> -wr_t *pws = &(env->active_fpu.fpr[ws].wr);
> -wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
> -
> -switch (df) {
> -case DF_BYTE:
> -pwd->b[0]  = pwt->b[1];
> -pwd->b[1]  = pws->b[1];
> -pwd->b[2]  = pwt->b[3];
> -pwd->b[3]  = pws->b[3];
> -pwd->b[4]  = pwt->b[5];
> -pwd->b[5]  = pws->b[5];
> -pwd->b[6]  = pwt->b[7];
> -pwd->b[7]  = pws->b[7];
> -pwd->b[8]  = pwt->b[9];
> -pwd->b[9]  = pws->b[9];
> -pwd->b[10] = pwt->b[11];
> -pwd->b[11] = pws->b[11];
> -pwd->b[12] = pwt->b[13];
> -pwd->b[13] = pws->b[13];
> -pwd->b[14] = pwt->b[15];
> -pwd->b[15] = pws->b[15];
> -break;
> -case DF_HALF:
> -pwd->h[0] = pwt->h[1];
> -pwd->h[1] = pws->h[1];
> -pwd->h[2] = pwt->h[3];
> -pwd->h[3] = pws->h[3];
> -pwd->h[4] = pwt->h[5];
> -pwd->h[5] = pws->h[5];
> -pwd->h[6] = pwt->h[7];
> -pwd->h[7] = pws->h[7];
> -break;
> -case DF_WORD:
> -pwd->w[0] = pwt->w[1];
> -pwd->w[1] = pws->w[1];
> -pwd->w[2] = pwt->w[3];
> -pwd->w[3] = pws->w[3];
> -break;
> -case DF_DOUBLE:
> -pwd->d[0] = pwt->d[1];
> -pwd->d[1] = pws->d[1];
> -break;
> -default:
> -assert(0);
> -}
> -}
> -
>  void helper_msa_ilvl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
>  uint32_t ws, uint32_t wt)
>  {
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index b4a1103..101d2de 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -28889,6 +28889,108 @@ static void gen_msa_bit(CPUMIPSState *env, 
> DisasContext *ctx)
>  tcg_temp_free_i32(tws);
>  }
> 
> +static inline void gen_ilvod_b(CPUMIPSState *env, uint32_t wd,
> +   uint32_t ws, uint32_t wt) {

Please insert a brief comment before each handler, like in this example:

/*
 * [MSA] ILVOD.B wd, ws, wt
 *
 *   Vector Interleave Odd (byte data elements)
 *
 */

> +TCGv_i64 t0 = tcg_temp_new_i64();
> +TCGv_i64 t1 = tcg_temp_new_i64();
> +
> +uint64_t mask = (1ULL << 8) - 1;

There shouldn't be a blank line between declarations. The blank line
should be after the last declaration.

> +mask |= mask << 16;
> +mask |= mask << 32;
> +mask <<= 8;
> +tcg_gen_movi_i64(t1, 0);
> +
> +tcg_gen_andi_i64(t0, msa_wr_d[wt * 2], mask);
> +tcg_gen_shri_i64(t0, t0, 8);
> +tcg_gen_or_i64(t1, t1, t0);

If t1 is already initialized to 0, what is the purpose of OR-ing?

> +tcg_gen_andi_i64(t0, msa_wr_d[ws * 2], mask);
> +tcg_gen_or_i64(t1, t1, t0);
> +
> +tcg_gen_mov_i64(msa_wr_d[wd * 2], t1);
> +
> +tcg_gen_movi_i64(t1, 0);
> +
> +tcg_gen_andi_i64(t0, 

Re: [Qemu-devel] [PATCH 6/8] Clean up ill-advised or unusual header guards

[Philippe Mathieu-Daudé]

On 3/15/19 3:51 PM, Markus Armbruster wrote:
> Leading underscores are ill-advised because such identifiers are
> reserved.  Trailing underscores are merely ugly.  Strip both.
> 
> Our header guards commonly end in _H.  Normalize the exceptions.
> 
> Done with scripts/clean-header-guards.pl.
> 
> Signed-off-by: Markus Armbruster 
> ---
>  block/crypto.h | 6 +++---
>  hw/i386/amd_iommu.h| 4 ++--
>  hw/tpm/tpm_ioctl.h | 7 ---
>  hw/xtensa/xtensa_memory.h  | 4 ++--
>  include/authz/base.h   | 7 +++
>  include/authz/list.h   | 7 +++
>  include/authz/simple.h | 7 +++
>  include/chardev/spice.h| 4 ++--
>  include/hw/ppc/pnv.h   | 7 ---
>  include/hw/ppc/pnv_core.h  | 7 ---
>  include/hw/ppc/pnv_lpc.h   | 7 ---
>  include/hw/ppc/pnv_occ.h   | 7 ---
>  include/hw/ppc/pnv_psi.h   | 7 ---
>  include/hw/ppc/pnv_xscom.h | 7 ---
>  include/hw/ppc/spapr_ovec.h| 7 ---
>  include/hw/timer/pl031.h   | 4 ++--
>  include/hw/virtio/vhost-vsock.h| 6 +++---
>  include/hw/virtio/virtio-crypto.h  | 6 +++---
>  include/hw/xen/start_info.h| 6 +++---
>  include/hw/xtensa/mx_pic.h | 4 ++--
>  include/qemu/drm.h | 4 ++--
>  include/qemu/jhash.h   | 6 +++---
>  include/sysemu/hvf.h   | 5 +++--
>  linux-user/xtensa/syscall_nr.h | 6 +++---
>  linux-user/xtensa/target_structs.h | 4 ++--
>  linux-user/xtensa/termbits.h   | 6 +++---
>  qga/vss-win32/vss-handles.h| 4 ++--
>  slirp/src/debug.h  | 6 +++---
>  slirp/src/stream.h | 6 +++---
>  slirp/src/util.h   | 5 +++--
>  slirp/src/vmstate.h| 5 +++--
>  target/i386/hax-i386.h | 4 ++--
>  target/i386/hax-interface.h| 4 ++--
>  target/i386/hvf/hvf-i386.h | 4 ++--
>  target/i386/hvf/vmcs.h | 4 ++--
>  target/i386/hvf/x86_emu.h  | 5 +++--
>  target/i386/hvf/x86_flags.h| 7 ---
>  target/i386/hvf/x86_mmu.h  | 7 ---
>  target/riscv/pmp.h | 4 ++--
>  target/sparc/asi.h | 6 +++---
>  tests/libqos/e1000e.h  | 4 ++--
>  tests/libqos/sdhci.h   | 4 ++--
>  42 files changed, 121 insertions(+), 110 deletions(-)
> 
> diff --git a/block/crypto.h b/block/crypto.h
> index dd7d47903c..b935695e79 100644
> --- a/block/crypto.h
> +++ b/block/crypto.h
> @@ -18,8 +18,8 @@
>   *
>   */
>  
> -#ifndef BLOCK_CRYPTO_H__
> -#define BLOCK_CRYPTO_H__
> +#ifndef BLOCK_CRYPTO_H
> +#define BLOCK_CRYPTO_H
>  
>  #define BLOCK_CRYPTO_OPT_DEF_KEY_SECRET(prefix, helpstr)\
>  {   \
> @@ -94,4 +94,4 @@ block_crypto_create_opts_init(QDict *opts, Error **errp);
>  QCryptoBlockOpenOptions *
>  block_crypto_open_opts_init(QDict *opts, Error **errp);
>  
> -#endif /* BLOCK_CRYPTO_H__ */
> +#endif /* BLOCK_CRYPTO_H */
> diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h
> index 0ff9095f32..3a694b186b 100644
> --- a/hw/i386/amd_iommu.h
> +++ b/hw/i386/amd_iommu.h
> @@ -18,8 +18,8 @@
>   * with this program; if not, see .
>   */
>  
> -#ifndef AMD_IOMMU_H_
> -#define AMD_IOMMU_H_
> +#ifndef AMD_IOMMU_H
> +#define AMD_IOMMU_H
>  
>  #include "hw/hw.h"
>  #include "hw/pci/pci.h"
> diff --git a/hw/tpm/tpm_ioctl.h b/hw/tpm/tpm_ioctl.h
> index 59a0b0595d..f5f5c553a9 100644
> --- a/hw/tpm/tpm_ioctl.h
> +++ b/hw/tpm/tpm_ioctl.h
> @@ -5,8 +5,9 @@
>   *
>   * This file is licensed under the terms of the 3-clause BSD license
>   */
> -#ifndef _TPM_IOCTL_H_
> -#define _TPM_IOCTL_H_
> +
> +#ifndef TPM_IOCTL_H
> +#define TPM_IOCTL_H
>  
>  #include 
>  #include 
> @@ -267,4 +268,4 @@ enum {
>  CMD_SET_BUFFERSIZE,
>  };
>  
> -#endif /* _TPM_IOCTL_H */
> +#endif /* TPM_IOCTL_H */
> diff --git a/hw/xtensa/xtensa_memory.h b/hw/xtensa/xtensa_memory.h
> index e9aa08749d..89125c4a0d 100644
> --- a/hw/xtensa/xtensa_memory.h
> +++ b/hw/xtensa/xtensa_memory.h
> @@ -25,8 +25,8 @@
>   * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>   */
>  
> -#ifndef _XTENSA_MEMORY_H
> -#define _XTENSA_MEMORY_H
> +#ifndef XTENSA_MEMORY_H
> +#define XTENSA_MEMORY_H
>  
>  #include "qemu-common.h"
>  #include "cpu.h"
> diff --git a/include/authz/base.h b/include/authz/base.h
> index 77dcd54c4c..05f1df845c 100644
> --- a/include/authz/base.h
> +++ b/include/authz/base.h
> @@ -18,8 +18,8 @@
>   *
>   */
>  
> -#ifndef QAUTHZ_BASE_H__
> -#define QAUTHZ_BASE_H__
> +#ifndef QAUTHZ_BASE_H
> +#define QAUTHZ_BASE_H
>  
>  #include "qemu-common.h"
>  #include "qapi/error.h"
> @@ -108,5 +108,4 @@ bool qauthz_is_allowed_by_id(const char *authzid,
>   const char *identity,
>   Error **errp);
>  
> -#endif /* 

Re: [Qemu-devel] [libvirt] [PULL 04/14] audio: -audiodev command line option basic implementation

[Markus Armbruster]

Pavel Hrdina  writes:

> On Tue, Mar 12, 2019 at 08:12:40AM +0100, Gerd Hoffmann wrote:
>> From: Kővágó, Zoltán 
>> 
>> Audio drivers now get an Audiodev * as config paramters, instead of the
>> global audio_option structs.  There is some code in audio/audio_legacy.c
>> that converts the old environment variables to audiodev options (this
>> way backends do not have to worry about legacy options).  It also
>> contains a replacement of -audio-help, which prints out the equivalent
>> -audiodev based config of the currently specified environment variables.
>> 
>> Note that backends are not updated and still rely on environment
>> variables.
>> 
>> Also note that (due to moving try-poll from global to backend specific
>> option) currently ALSA and OSS will always try poll mode, regardless of
>> environment variables or -audiodev options.
>
> Hi,
>
> I'm glad that this is merged now and I wanted to start working on
> libvirt patches, but there is one big issue with this command,
> it's not introspectable by query-command-line-options.
>
> My guess based on the QEMU code is that it uses the new function that
> allows you to use JSON on qemu command line.
>
> Without the introspection libvirt cannot implement the new option in
> sensible way (without version check).
>
> Adding Markus to CC so we can figure out how to wire up the
> introspection for such command line options.

query-command-line-options has always been woefully incomplete.  Sadly,
my replacement is still not ready.

A reliable "witness" could serve a stop gap.  Unfortunately,
query-qmp-schema doesn't provide one: the series does not change
generated qapi-introspect.c.

Need to think some more.

Re: [Qemu-devel] State of QEMU CI as we enter 4.0

[Peter Maydell]

On Fri, 15 Mar 2019 at 15:12, Stefan Hajnoczi  wrote:
> How should all sub-maintainers be checking their pull requests?
>
> We should have information and a strict policy on minimum testing of
> pull requests.  Right now I imagine it varies a lot between
> sub-maintainers.
>
> For my block pull requests I run qemu-iotests locally and also push to
> GitHub to trigger Travis CI.

For my arm pullreqs I do light smoke testing on x86-64 typically
(and let the tests on merge catch any portability issues), unless
I'm particularly suspicious that something should be tested
more widely :-)

thanks
-- PMM

Re: [Qemu-devel] State of QEMU CI as we enter 4.0

[Alex Bennée]

Stefan Hajnoczi  writes:

> On Thu, Mar 14, 2019 at 03:57:06PM +, Alex Bennée wrote:
>> As we approach stabilisation for 4.0 I thought it would be worth doing a
>> review of the current state of CI and stimulate some discussion of where
>> it is working for us and what could be improved.
>
> Thanks for this summary and for all the work that is being put into CI.
>
> How should all sub-maintainers be checking their pull requests?
>
> We should have information and a strict policy on minimum testing of
> pull requests.  Right now I imagine it varies a lot between
> sub-maintainers.

I'll try and fill out the various Testing/CI/ subpages with details but
in short:

 Travis: already documented in Testing/CI/Travis
 Shippable/Cirrus: sign-up with your github id, enable repos you want
 testing
 Gitlab: sign-up (you can use github as a SSO)

>
> For my block pull requests I run qemu-iotests locally and also push to
> GitHub to trigger Travis CI.

I'm currently pushing to both github and gitlab and then checking I get
green across all of the services (assuming no current breakage).

>
> Stefan


--
Alex Bennée

Re: [Qemu-devel] [PATCH 7/8] Normalize header guard symbol definition.

[Philippe Mathieu-Daudé]

On 3/15/19 3:51 PM, Markus Armbruster wrote:
> We commonly define the header guard symbol without an explicit value.
> Normalize the exceptions.
> 
> Done with scripts/clean-header-guards.pl.
> 
> Signed-off-by: Markus Armbruster 

Reviewed-by: Philippe Mathieu-Daudé 

> ---
>  hw/timer/m48t59-internal.h| 3 ++-
>  include/disas/capstone.h  | 2 +-
>  include/hw/scsi/emulation.h   | 2 +-
>  include/qemu/stats64.h| 2 +-
>  include/qemu/sys_membarrier.h | 2 +-
>  include/qemu/systemd.h| 2 +-
>  include/scsi/utils.h  | 2 +-
>  include/ui/kbd-state.h| 3 ++-
>  scsi/pr-helper.h  | 3 ++-
>  target/i386/hvf/x86.h | 2 +-
>  target/i386/hvf/x86_decode.h  | 2 +-
>  target/i386/hvf/x86_descr.h   | 2 +-
>  12 files changed, 15 insertions(+), 12 deletions(-)
> 
> diff --git a/hw/timer/m48t59-internal.h b/hw/timer/m48t59-internal.h
> index d0f0caf3c7..4d4f2a6fed 100644
> --- a/hw/timer/m48t59-internal.h
> +++ b/hw/timer/m48t59-internal.h
> @@ -22,8 +22,9 @@
>   * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>   * THE SOFTWARE.
>   */
> +
>  #ifndef HW_M48T59_INTERNAL_H
> -#define HW_M48T59_INTERNAL_H 1
> +#define HW_M48T59_INTERNAL_H
>  
>  #define M48T59_DEBUG 0
>  
> diff --git a/include/disas/capstone.h b/include/disas/capstone.h
> index 84e214956d..e29068dd97 100644
> --- a/include/disas/capstone.h
> +++ b/include/disas/capstone.h
> @@ -1,5 +1,5 @@
>  #ifndef QEMU_CAPSTONE_H
> -#define QEMU_CAPSTONE_H 1
> +#define QEMU_CAPSTONE_H
>  
>  #ifdef CONFIG_CAPSTONE
>  
> diff --git a/include/hw/scsi/emulation.h b/include/hw/scsi/emulation.h
> index 09fba1ff39..9521704326 100644
> --- a/include/hw/scsi/emulation.h
> +++ b/include/hw/scsi/emulation.h
> @@ -1,5 +1,5 @@
>  #ifndef HW_SCSI_EMULATION_H
> -#define HW_SCSI_EMULATION_H 1
> +#define HW_SCSI_EMULATION_H
>  
>  typedef struct SCSIBlockLimits {
>  bool wsnz;
> diff --git a/include/qemu/stats64.h b/include/qemu/stats64.h
> index 4a357b3e9d..19a5ac4c56 100644
> --- a/include/qemu/stats64.h
> +++ b/include/qemu/stats64.h
> @@ -10,7 +10,7 @@
>   */
>  
>  #ifndef QEMU_STATS64_H
> -#define QEMU_STATS64_H 1
> +#define QEMU_STATS64_H
>  
>  #include "qemu/atomic.h"
>  
> diff --git a/include/qemu/sys_membarrier.h b/include/qemu/sys_membarrier.h
> index 316e3dc4a2..b5bfa21d52 100644
> --- a/include/qemu/sys_membarrier.h
> +++ b/include/qemu/sys_membarrier.h
> @@ -7,7 +7,7 @@
>   */
>  
>  #ifndef QEMU_SYS_MEMBARRIER_H
> -#define QEMU_SYS_MEMBARRIER_H 1
> +#define QEMU_SYS_MEMBARRIER_H
>  
>  #ifdef CONFIG_MEMBARRIER
>  /* Only block reordering at the compiler level in the performance-critical
> diff --git a/include/qemu/systemd.h b/include/qemu/systemd.h
> index e6a877e5c6..f0ea1266d5 100644
> --- a/include/qemu/systemd.h
> +++ b/include/qemu/systemd.h
> @@ -11,7 +11,7 @@
>   */
>  
>  #ifndef QEMU_SYSTEMD_H
> -#define QEMU_SYSTEMD_H 1
> +#define QEMU_SYSTEMD_H
>  
>  #define FIRST_SOCKET_ACTIVATION_FD 3 /* defined by systemd ABI */
>  
> diff --git a/include/scsi/utils.h b/include/scsi/utils.h
> index 4b705f5e0f..9351b21ead 100644
> --- a/include/scsi/utils.h
> +++ b/include/scsi/utils.h
> @@ -1,5 +1,5 @@
>  #ifndef SCSI_UTILS_H
> -#define SCSI_UTILS_H 1
> +#define SCSI_UTILS_H
>  
>  #ifdef CONFIG_LINUX
>  #include 
> diff --git a/include/ui/kbd-state.h b/include/ui/kbd-state.h
> index d87833553a..eb9067dd53 100644
> --- a/include/ui/kbd-state.h
> +++ b/include/ui/kbd-state.h
> @@ -3,8 +3,9 @@
>   * (at your option) any later version.  See the COPYING file in the
>   * top-level directory.
>   */
> +
>  #ifndef QEMU_UI_KBD_STATE_H
> -#define QEMU_UI_KBD_STATE_H 1
> +#define QEMU_UI_KBD_STATE_H
>  
>  #include "qapi/qapi-types-ui.h"
>  
> diff --git a/scsi/pr-helper.h b/scsi/pr-helper.h
> index 096d1f1df6..e26e104ec7 100644
> --- a/scsi/pr-helper.h
> +++ b/scsi/pr-helper.h
> @@ -23,8 +23,9 @@
>   * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
> DEALINGS
>   * IN THE SOFTWARE.
>   */
> +
>  #ifndef QEMU_PR_HELPER_H
> -#define QEMU_PR_HELPER_H 1
> +#define QEMU_PR_HELPER_H
>  
>  #define PR_HELPER_CDB_SIZE 16
>  #define PR_HELPER_SENSE_SIZE   96
> diff --git a/target/i386/hvf/x86.h b/target/i386/hvf/x86.h
> index 103ec0976c..c95d5b2116 100644
> --- a/target/i386/hvf/x86.h
> +++ b/target/i386/hvf/x86.h
> @@ -17,7 +17,7 @@
>   */
>  
>  #ifndef HVF_X86_H
> -#define HVF_X86_H 1
> +#define HVF_X86_H
>  
>  typedef struct x86_register {
>  union {
> diff --git a/target/i386/hvf/x86_decode.h b/target/i386/hvf/x86_decode.h
> index ef4bcab310..bc574a7a44 100644
> --- a/target/i386/hvf/x86_decode.h
> +++ b/target/i386/hvf/x86_decode.h
> @@ -16,7 +16,7 @@
>   */
>  
>  #ifndef HVF_X86_DECODE_H
> -#define HVF_X86_DECODE_H 1
> +#define HVF_X86_DECODE_H
>  
>  #include "cpu.h"
>  #include "x86.h"
> diff --git a/target/i386/hvf/x86_descr.h b/target/i386/hvf/x86_descr.h
> index 25a2b1731c..049ef9a417 100644
> --- a/target/i386/hvf/x86_descr.h
> +++ 

Re: [Qemu-devel] [PATCH 2/5] trace-events: Shorten file names in comments

[Stefan Hajnoczi]

On Thu, Mar 14, 2019 at 07:09:26PM +0100, Markus Armbruster wrote:
> We spell out sub/dir/ in sub/dir/trace-events' comments pointing to
> source files.  That's because when trace-events got split up, the
> comments were moved verbatim.
> 
> Delete the sub/dir/ part from these comments.  Gets rid of several
> misspellings.
> 
> Signed-off-by: Markus Armbruster 
> ---

git-am(1) cannot apply this patch:

  Applying: trace-events: Shorten file names in comments
  error: sha1 information is lacking or useless (hw/display/trace-events).
  error: could not build fake ancestor
  Patch failed at 0002 trace-events: Shorten file names in comments

?

Stefan


signature.asc
Description: PGP signature

Re: [Qemu-devel] [PATCHv2] curses ui: always initialize all curses_line fields

[Philippe Mathieu-Daudé]

On 3/15/19 2:09 PM, Samuel Thibault wrote:
> cchar_t can contain not only attr and chars fields, but also ext_color.
> Initialize the whole structure to zero instead of enumerating fields.
> 
> Spotted by Coverity: CID 1399711
> 
> Signed-off-by: Samuel Thibault 
> ---
>  ui/curses.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/ui/curses.c b/ui/curses.c
> index d29098db9f..cc6d6da684 100644
> --- a/ui/curses.c
> +++ b/ui/curses.c
> @@ -75,9 +75,9 @@ static void curses_update(DisplayChangeListener *dcl,
>  if (vga_to_curses[ch].chars[0]) {
>  curses_line[x] = vga_to_curses[ch];
>  } else {
> -curses_line[x].chars[0] = ch;
> -curses_line[x].chars[1] = 0;
> -curses_line[x].attr = 0;
> +curses_line[x] = (cchar_t) {
> +.chars[0] = ch,
> +};
>  }
>  curses_line[x].attr |= at;
>  }
> 

Reviewed-by: Philippe Mathieu-Daudé 

Re: [Qemu-devel] [PATCH v2 1/2] i2c: Move contents of bitbang_i2c.h to include/hw/i2c/i2c.h

[Corey Minyard]

On Fri, Mar 15, 2019 at 03:25:55PM +0100, BALATON Zoltan wrote:
> The bitbang i2c implementation is also useful for other device models
> such as DDC in display controllers. Because of this, part of the file had
> to be moved to the main i2c.h to avoid a warning in commit 2b4c1125ac.
> Move the rest of the hw/i2c/bitbang_i2c.h to the main i2c.h now to allow
> it to be used from other device models.

This patch is ok in principle, however, I would prefer that the
bitbang interface be left in it's own bitbang_i2c.h file and
moved into hw/i2c.  I think it's cleaner and more clear that
way.

-corey

> 
> Signed-off-by: BALATON Zoltan 
> ---
>  hw/i2c/bitbang_i2c.c   |  2 +-
>  hw/i2c/bitbang_i2c.h   | 12 
>  hw/i2c/ppc4xx_i2c.c|  1 -
>  hw/i2c/versatile_i2c.c |  2 +-
>  include/hw/i2c/i2c.h   |  7 +++
>  5 files changed, 9 insertions(+), 15 deletions(-)
>  delete mode 100644 hw/i2c/bitbang_i2c.h
> 
> diff --git a/hw/i2c/bitbang_i2c.c b/hw/i2c/bitbang_i2c.c
> index 8be88ee265..a1fe3ac35c 100644
> --- a/hw/i2c/bitbang_i2c.c
> +++ b/hw/i2c/bitbang_i2c.c
> @@ -11,7 +11,7 @@
>   */
>  #include "qemu/osdep.h"
>  #include "hw/hw.h"
> -#include "bitbang_i2c.h"
> +#include "hw/i2c/i2c.h"
>  #include "hw/sysbus.h"
>  
>  //#define DEBUG_BITBANG_I2C
> diff --git a/hw/i2c/bitbang_i2c.h b/hw/i2c/bitbang_i2c.h
> deleted file mode 100644
> index 9443021710..00
> --- a/hw/i2c/bitbang_i2c.h
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -#ifndef BITBANG_I2C_H
> -#define BITBANG_I2C_H
> -
> -#include "hw/i2c/i2c.h"
> -
> -#define BITBANG_I2C_SDA 0
> -#define BITBANG_I2C_SCL 1
> -
> -bitbang_i2c_interface *bitbang_i2c_init(I2CBus *bus);
> -int bitbang_i2c_set(bitbang_i2c_interface *i2c, int line, int level);
> -
> -#endif
> diff --git a/hw/i2c/ppc4xx_i2c.c b/hw/i2c/ppc4xx_i2c.c
> index d6dfafab31..a907d0194e 100644
> --- a/hw/i2c/ppc4xx_i2c.c
> +++ b/hw/i2c/ppc4xx_i2c.c
> @@ -30,7 +30,6 @@
>  #include "cpu.h"
>  #include "hw/hw.h"
>  #include "hw/i2c/ppc4xx_i2c.h"
> -#include "bitbang_i2c.h"
>  
>  #define PPC4xx_I2C_MEM_SIZE 18
>  
> diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c
> index da9f298ee5..88f0b89f8d 100644
> --- a/hw/i2c/versatile_i2c.c
> +++ b/hw/i2c/versatile_i2c.c
> @@ -23,7 +23,7 @@
>  
>  #include "qemu/osdep.h"
>  #include "hw/sysbus.h"
> -#include "bitbang_i2c.h"
> +#include "hw/i2c/i2c.h"
>  #include "qemu/log.h"
>  
>  #define TYPE_VERSATILE_I2C "versatile_i2c"
> diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
> index 8e236f7bb4..fa102dde80 100644
> --- a/include/hw/i2c/i2c.h
> +++ b/include/hw/i2c/i2c.h
> @@ -81,8 +81,15 @@ uint8_t i2c_recv(I2CBus *bus);
>  
>  DeviceState *i2c_create_slave(I2CBus *bus, const char *name, uint8_t addr);
>  
> +/* generic bitbang i2c interface */
> +#define BITBANG_I2C_SDA 0
> +#define BITBANG_I2C_SCL 1
> +
>  typedef struct bitbang_i2c_interface bitbang_i2c_interface;
>  
> +bitbang_i2c_interface *bitbang_i2c_init(I2CBus *bus);
> +int bitbang_i2c_set(bitbang_i2c_interface *i2c, int line, int level);
> +
>  /* lm832x.c */
>  void lm832x_key_event(DeviceState *dev, int key, int state);
>  
> -- 
> 2.13.7
> 

Re: [Qemu-devel] [PATCH 2/2] filemon: ensure watch IDs are unique to QFileMonitor scope

[Bandan Das]

Daniel P. Berrangé  writes:

> The watch IDs are mistakenly only unique within the scope of the
> directory being monitored. This is not useful for clients which are
> monitoring multiple directories. They require watch IDs to be unique
> globally within the QFileMonitor scope.
>
> Signed-off-by: Daniel P. Berrangé 
> ---
>  tests/test-util-filemonitor.c | 116 +++---
>  util/filemonitor-inotify.c|   5 +-
>  2 files changed, 110 insertions(+), 11 deletions(-)
>
> diff --git a/tests/test-util-filemonitor.c b/tests/test-util-filemonitor.c
> index ea3715a8f4..71a7cf5de0 100644
> --- a/tests/test-util-filemonitor.c
> +++ b/tests/test-util-filemonitor.c
> @@ -35,6 +35,8 @@ enum {
>  QFILE_MONITOR_TEST_OP_RENAME,
>  QFILE_MONITOR_TEST_OP_TOUCH,
>  QFILE_MONITOR_TEST_OP_UNLINK,
> +QFILE_MONITOR_TEST_OP_MKDIR,
> +QFILE_MONITOR_TEST_OP_RMDIR,
>  };
>  
>  typedef struct {
> @@ -298,6 +300,54 @@ test_file_monitor_events(void)
>.eventid = QFILE_MONITOR_EVENT_DELETED },
>  
>  
> +{ .type = QFILE_MONITOR_TEST_OP_MKDIR,
> +  .filesrc = "fish", },
> +{ .type = QFILE_MONITOR_TEST_OP_EVENT,
> +  .filesrc = "fish", .watchid = 0,
> +  .eventid = QFILE_MONITOR_EVENT_CREATED },
> +
> +
> +{ .type = QFILE_MONITOR_TEST_OP_ADD_WATCH,
> +  .filesrc = "fish/", .watchid = 4 },
> +{ .type = QFILE_MONITOR_TEST_OP_ADD_WATCH,
> +  .filesrc = "fish/one.txt", .watchid = 5 },
> +{ .type = QFILE_MONITOR_TEST_OP_CREATE,
> +  .filesrc = "fish/one.txt", },
> +{ .type = QFILE_MONITOR_TEST_OP_EVENT,
> +  .filesrc = "one.txt", .watchid = 4,
> +  .eventid = QFILE_MONITOR_EVENT_CREATED },
> +{ .type = QFILE_MONITOR_TEST_OP_EVENT,
> +  .filesrc = "one.txt", .watchid = 5,
> +  .eventid = QFILE_MONITOR_EVENT_CREATED },
> +
> +
> +{ .type = QFILE_MONITOR_TEST_OP_DEL_WATCH,
> +  .filesrc = "fish/one.txt", .watchid = 5 },
> +{ .type = QFILE_MONITOR_TEST_OP_RENAME,
> +  .filesrc = "fish/one.txt", .filedst = "two.txt", },
> +{ .type = QFILE_MONITOR_TEST_OP_EVENT,
> +  .filesrc = "one.txt", .watchid = 4,
> +  .eventid = QFILE_MONITOR_EVENT_DELETED },
> +{ .type = QFILE_MONITOR_TEST_OP_EVENT,
> +  .filesrc = "two.txt", .watchid = 0,
> +  .eventid = QFILE_MONITOR_EVENT_CREATED },
> +{ .type = QFILE_MONITOR_TEST_OP_EVENT,
> +  .filesrc = "two.txt", .watchid = 2,
> +  .eventid = QFILE_MONITOR_EVENT_CREATED },
> +
> +
> +{ .type = QFILE_MONITOR_TEST_OP_RMDIR,
> +  .filesrc = "fish", },
> +{ .type = QFILE_MONITOR_TEST_OP_EVENT,
> +  .filesrc = "", .watchid = 4,
> +  .eventid = QFILE_MONITOR_EVENT_IGNORED },
> +{ .type = QFILE_MONITOR_TEST_OP_EVENT,
> +  .filesrc = "fish", .watchid = 0,
> +  .eventid = QFILE_MONITOR_EVENT_DELETED },
> +{ .type = QFILE_MONITOR_TEST_OP_DEL_WATCH,
> +  .filesrc = "fish", .watchid = 4 },
> +
> +
>  { .type = QFILE_MONITOR_TEST_OP_UNLINK,
>.filesrc = "two.txt", },
>  { .type = QFILE_MONITOR_TEST_OP_EVENT,
> @@ -366,6 +416,8 @@ test_file_monitor_events(void)
>  int fd;
>  int watchid;
>  struct utimbuf ubuf;
> +char *watchdir;
> +const char *watchfile;
>  
>  pathsrc = g_strdup_printf("%s/%s", dir, op->filesrc);
>  if (op->filedst) {
> @@ -378,13 +430,26 @@ test_file_monitor_events(void)
>  g_printerr("Add watch %s %s %d\n",
> dir, op->filesrc, op->watchid);
>  }
> +if (op->filesrc && strchr(op->filesrc, '/')) {
> +watchdir = g_strdup_printf("%s/%s", dir, op->filesrc);
> +watchfile = strrchr(watchdir, '/');
> +*(char *)watchfile = '\0';
> +watchfile++;
> +if (*watchfile == '\0') {
> +watchfile = NULL;
> +}
> +} else {
> +watchdir = g_strdup(dir);
> +watchfile = op->filesrc;
> +}
>  watchid =
>  qemu_file_monitor_add_watch(mon,
> -dir,
> -op->filesrc,
> +watchdir,
> +watchfile,
>  qemu_file_monitor_test_handler,
>  ,
>  _err);
> +g_free(watchdir);
>  if (watchid < 0) {
>  g_printerr("Unable to add watch %s",
> error_get_pretty(local_err));
> @@ -400,9 +465,17 @@ test_file_monitor_events(void)
>  if (debug) {
>  

Re: [Qemu-devel] [PATCH 3/8] linux-user/nios2 linux-user/riscv: Clean up header guards

[Philippe Mathieu-Daudé]

On 3/15/19 3:51 PM, Markus Armbruster wrote:
> Reuse of the same guard symbol in multiple headers is okay as long as
> they cannot be included together.  scripts/clean-header-guards.pl
> can't tell, so it warns.
> 
> Since we can avoid guard symbol reuse easily, do so: use guard symbol
> ${target^^}_${fname^^} for linux-user/$target/$fname, just like we did
> in commit a9c94277f0..3500385697.
> 
> Signed-off-by: Markus Armbruster 

Reviewed-by: Philippe Mathieu-Daudé 

> ---
>  linux-user/nios2/target_cpu.h | 4 ++--
>  linux-user/nios2/target_signal.h  | 6 +++---
>  linux-user/nios2/target_structs.h | 4 ++--
>  linux-user/nios2/target_syscall.h | 6 +++---
>  linux-user/riscv/target_cpu.h | 4 ++--
>  linux-user/riscv/target_signal.h  | 6 +++---
>  linux-user/riscv/target_structs.h | 4 ++--
>  7 files changed, 17 insertions(+), 17 deletions(-)
> 
> diff --git a/linux-user/nios2/target_cpu.h b/linux-user/nios2/target_cpu.h
> index 14f63338fa..5596c05c9c 100644
> --- a/linux-user/nios2/target_cpu.h
> +++ b/linux-user/nios2/target_cpu.h
> @@ -17,8 +17,8 @@
>   * License along with this library; if not, see 
> .
>   */
>  
> -#ifndef TARGET_CPU_H
> -#define TARGET_CPU_H
> +#ifndef NIOS2_TARGET_CPU_H
> +#define NIOS2_TARGET_CPU_H
>  
>  static inline void cpu_clone_regs(CPUNios2State *env, target_ulong newsp)
>  {
> diff --git a/linux-user/nios2/target_signal.h 
> b/linux-user/nios2/target_signal.h
> index 7776bcdbfd..fe48721b3d 100644
> --- a/linux-user/nios2/target_signal.h
> +++ b/linux-user/nios2/target_signal.h
> @@ -1,5 +1,5 @@
> -#ifndef TARGET_SIGNAL_H
> -#define TARGET_SIGNAL_H
> +#ifndef NIOS2_TARGET_SIGNAL_H
> +#define NIOS2_TARGET_SIGNAL_H
>  
>  /* this struct defines a stack used during syscall handling */
>  
> @@ -18,4 +18,4 @@ typedef struct target_sigaltstack {
>  
>  #include "../generic/signal.h"
>  
> -#endif /* TARGET_SIGNAL_H */
> +#endif /* NIOS2_TARGET_SIGNAL_H */
> diff --git a/linux-user/nios2/target_structs.h 
> b/linux-user/nios2/target_structs.h
> index 8713772089..7145251706 100644
> --- a/linux-user/nios2/target_structs.h
> +++ b/linux-user/nios2/target_structs.h
> @@ -16,8 +16,8 @@
>   * You should have received a copy of the GNU Lesser General Public
>   * License along with this library; if not, see 
> .
>   */
> -#ifndef TARGET_STRUCTS_H
> -#define TARGET_STRUCTS_H
> +#ifndef NIOS2_TARGET_STRUCTS_H
> +#define NIOS2_TARGET_STRUCTS_H
>  
>  struct target_ipc_perm {
>  abi_int __key;  /* Key.  */
> diff --git a/linux-user/nios2/target_syscall.h 
> b/linux-user/nios2/target_syscall.h
> index ca6b7e69f6..f3b2a500f4 100644
> --- a/linux-user/nios2/target_syscall.h
> +++ b/linux-user/nios2/target_syscall.h
> @@ -1,5 +1,5 @@
> -#ifndef TARGET_SYSCALL_H
> -#define TARGET_SYSCALL_H
> +#ifndef NIOS2_TARGET_SYSCALL_H
> +#define NIOS2_TARGET_SYSCALL_H
>  
>  #define UNAME_MACHINE "nios2"
>  #define UNAME_MINIMUM_RELEASE "3.19.0"
> @@ -34,4 +34,4 @@ struct target_pt_regs {
>  #define TARGET_MLOCKALL_MCL_CURRENT 1
>  #define TARGET_MLOCKALL_MCL_FUTURE  2
>  
> -#endif  /* TARGET_SYSCALL_H */
> +#endif /* NIOS2_TARGET_SYSCALL_H */
> diff --git a/linux-user/riscv/target_cpu.h b/linux-user/riscv/target_cpu.h
> index 7e090f376a..90f9a4171e 100644
> --- a/linux-user/riscv/target_cpu.h
> +++ b/linux-user/riscv/target_cpu.h
> @@ -1,5 +1,5 @@
> -#ifndef TARGET_CPU_H
> -#define TARGET_CPU_H
> +#ifndef RISCV_TARGET_CPU_H
> +#define RISCV_TARGET_CPU_H
>  
>  static inline void cpu_clone_regs(CPURISCVState *env, target_ulong newsp)
>  {
> diff --git a/linux-user/riscv/target_signal.h 
> b/linux-user/riscv/target_signal.h
> index c8b1455800..f113ba9a55 100644
> --- a/linux-user/riscv/target_signal.h
> +++ b/linux-user/riscv/target_signal.h
> @@ -1,5 +1,5 @@
> -#ifndef TARGET_SIGNAL_H
> -#define TARGET_SIGNAL_H
> +#ifndef RISCV_TARGET_SIGNAL_H
> +#define RISCV_TARGET_SIGNAL_H
>  
>  typedef struct target_sigaltstack {
>  abi_ulong ss_sp;
> @@ -15,4 +15,4 @@ typedef struct target_sigaltstack {
>  
>  #include "../generic/signal.h"
>  
> -#endif /* TARGET_SIGNAL_H */
> +#endif /* RISCV_TARGET_SIGNAL_H */
> diff --git a/linux-user/riscv/target_structs.h 
> b/linux-user/riscv/target_structs.h
> index 4f0462c497..ea3e5ed17e 100644
> --- a/linux-user/riscv/target_structs.h
> +++ b/linux-user/riscv/target_structs.h
> @@ -4,8 +4,8 @@
>   * This is a copy of ../aarch64/target_structs.h atm.
>   *
>   */
> -#ifndef TARGET_STRUCTS_H
> -#define TARGET_STRUCTS_H
> +#ifndef RISCV_TARGET_STRUCTS_H
> +#define RISCV_TARGET_STRUCTS_H
>  
>  struct target_ipc_perm {
>  abi_int __key;  /* Key.  */
> 

Re: [Qemu-devel] [PATCH 2/8] authz: Normalize #include "authz/trace.h" to "trace.h"

[Philippe Mathieu-Daudé]

On 3/15/19 3:51 PM, Markus Armbruster wrote:
> Include the generated trace.h the same way as we do everywhere else.

I suppose this ended this way as a leftover from when this series
started in 2015. And I missed it while reviewing.

> 
> Signed-off-by: Markus Armbruster 

Reviewed-by: Philippe Mathieu-Daudé 

> ---
>  authz/base.c | 2 +-
>  authz/list.c | 2 +-
>  authz/listfile.c | 2 +-
>  authz/pamacct.c  | 2 +-
>  authz/simple.c   | 2 +-
>  5 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/authz/base.c b/authz/base.c
> index 110dfa4195..baf39fff25 100644
> --- a/authz/base.c
> +++ b/authz/base.c
> @@ -20,7 +20,7 @@
>  
>  #include "qemu/osdep.h"
>  #include "authz/base.h"
> -#include "authz/trace.h"
> +#include "trace.h"
>  
>  bool qauthz_is_allowed(QAuthZ *authz,
> const char *identity,
> diff --git a/authz/list.c b/authz/list.c
> index dc6b0fec13..831da936fe 100644
> --- a/authz/list.c
> +++ b/authz/list.c
> @@ -20,7 +20,7 @@
>  
>  #include "qemu/osdep.h"
>  #include "authz/list.h"
> -#include "authz/trace.h"
> +#include "trace.h"
>  #include "qom/object_interfaces.h"
>  #include "qapi/qapi-visit-authz.h"
>  
> diff --git a/authz/listfile.c b/authz/listfile.c
> index d4579767e7..674683c0ea 100644
> --- a/authz/listfile.c
> +++ b/authz/listfile.c
> @@ -20,7 +20,7 @@
>  
>  #include "qemu/osdep.h"
>  #include "authz/listfile.h"
> -#include "authz/trace.h"
> +#include "trace.h"
>  #include "qemu/error-report.h"
>  #include "qemu/main-loop.h"
>  #include "qemu/sockets.h"
> diff --git a/authz/pamacct.c b/authz/pamacct.c
> index 5038358cdc..7539867923 100644
> --- a/authz/pamacct.c
> +++ b/authz/pamacct.c
> @@ -20,7 +20,7 @@
>  
>  #include "qemu/osdep.h"
>  #include "authz/pamacct.h"
> -#include "authz/trace.h"
> +#include "trace.h"
>  #include "qom/object_interfaces.h"
>  
>  #include 
> diff --git a/authz/simple.c b/authz/simple.c
> index 8ab718803e..c409ce7efc 100644
> --- a/authz/simple.c
> +++ b/authz/simple.c
> @@ -20,7 +20,7 @@
>  
>  #include "qemu/osdep.h"
>  #include "authz/simple.h"
> -#include "authz/trace.h"
> +#include "trace.h"
>  #include "qom/object_interfaces.h"
>  
>  static bool qauthz_simple_is_allowed(QAuthZ *authz,
> 

Re: [Qemu-devel] State of QEMU CI as we enter 4.0

[Ed Vielmetti]

We have been trying to merge the Gitlab runner patches for arm64
for over a year now; see

https://gitlab.com/gitlab-org/gitlab-runner/merge_requests/725

I have not yet sorted out who at Gitlab has the ability to get
this change implemented - their management structure is
not something that I have sorted out yet, and I can't tell whether
this lack of forward progress is something best to tackle by
technical merit or by appealing to management.

On Fri, Mar 15, 2019 at 6:24 AM Fam Zheng  wrote:

>
>
> > On Mar 15, 2019, at 17:58, Alex Bennée  wrote:
> >
> >
> > Fam Zheng  writes:
> >
> >>> On Mar 15, 2019, at 16:57, Alex Bennée  wrote:
> >>>
> >>> I had installed the gitlab-runner from the Debian repo but it was out
> >>> of date and didn't seem to work correctly.
> >>
> >> If there can be a sidecar x86 box next to the test bot, it can be the
> >> controller node which runs gitlab-runner, the test script (in
> >> .gitlab-ci.yml) can then sshs into the actual env to run test
> >> commands.
> >
> > Sure although that just adds complexity compared to spinning up a box in
> > the cloud ;-)
>
> In the middle is one controller node and a number of hetergeneous boxes it
> knows how to control with ssh.
>
> (BTW patchew tester only relies on vanilla python3 to work, though clearly
> it suffers from insufficient manpower assumed the SLA we'll need on the
> merge test. It’s unfortunate that gitlab-runner is a binary.)
>
> Fam
>

Re: [Qemu-devel] AMD SEV's /dev/sev permissions and probing QEMU for capabilities

[Daniel P . Berrangé]

On Fri, Mar 15, 2019 at 03:51:57PM +, Singh, Brijesh wrote:
> Hi Daniel,
> 
> 
> On 3/15/19 7:18 AM, Daniel P. Berrangé wrote:
> > On Fri, Jan 18, 2019 at 12:51:50PM +, Singh, Brijesh wrote:
> >>
> >> On 1/18/19 3:39 AM, Erik Skultety wrote:
> >>> I proceeded with cloning [1] to systemd and creating an udev rule that I 
> >>> planned
> >>> on submitting to systemd upstream - the initial idea was to mimic 
> >>> /dev/kvm and
> >>> make it world accessible to which Brijesh from AMD expressed a concern 
> >>> that
> >>> regular users might deplete the resources (limit on the number of guests
> >>> allowed by the platform).
> > 
> > [snip]
> > 
> >>> But since the limit is claimed to be around 4, Dan
> >>
> >>
> >> FYI, the limit on EPYC is 15.
> > 
> > Do any cRyzen CPUs support SEV, and if so is their limit also 15 ?
> > 
> 
> SEV support is *not* available on any of Ryzen's yet!

Ok, thanks for clarifying.

> > Regardless, I'm assuming this limit is liable to change at any time
> > in future CPU generations, so from the the mgmt app perspective I
> > think is is important that QEMU / libvirt can both report what this
> > limit is.
> > 
> 
> Yes, the limit may change on future CPU generations. We can query the
> limit through the CPUID Fn0x8000_001f[ECX].

That's nice!

> > For QEMU I think query-sev-capabilities probably should report the
> > guest limit.  I guess QEMU would in turn want to ask the kernel,
> > rather than hardcode info itself. So if this info isn't already
> > exposed by the kernel we might need work there too.
> > 
> 
> 
> I don't think we need to add a kernel interface for querying this
> information, it can be obtained using the cpuid instruction or
> access its via /dev/cpuid/.

Agreed, using CPUID direct from QEMU ought to be sufficient.

Regards,
Daniel
-- 
|: https://berrange.com  -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
|: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|

Re: [Qemu-devel] Combining synchronous and asynchronous IO

[Kevin Wolf]

Am 15.03.2019 um 16:33 hat Sergio Lopez geschrieben:
> 
> Stefan Hajnoczi writes:
> 
> > On Thu, Mar 14, 2019 at 06:31:34PM +0100, Sergio Lopez wrote:
> >> Our current AIO path does a great job at unloading the work from the VM,
> >> and combined with IOThreads provides a good performance in most
> >> scenarios. But it also comes with its costs, in both a longer execution
> >> path and the need of the intervention of the scheduler at various
> >> points.
> >> 
> >> There's one particular workload that suffers from this cost, and that's
> >> when you have just 1 or 2 cores on the Guest issuing synchronous
> >> requests. This happens to be a pretty common workload for some DBs and,
> >> in a general sense, on small VMs.
> >> 
> >> I did a quick'n'dirty implementation on top of virtio-blk to get some
> >> numbers. This comes from a VM with 4 CPUs running on an idle server,
> >> with a secondary virtio-blk disk backed by a null_blk device with a
> >> simulated latency of 30us.
> >
> > Can you describe the implementation in more detail?  Does "synchronous"
> > mean that hw/block/virtio_blk.c makes a blocking preadv()/pwritev() call
> > instead of calling blk_aio_preadv/pwritev()?  If so, then you are also
> > bypassing the QEMU block layer (coroutines, request tracking, etc) and
> > that might explain some of the latency.
> 
> The first implementation, the one I've used for getting these numbers,
> it's just preadv/pwrite from virtio_blk.c, as you correctly guessed. I
> know it's unfair, but I wanted to take a look at the best possible
> scenario, and then measure the cost of the other layers.
> 
> I'm working now on writing non-coroutine counterparts for
> blk_co_[preadv|pwrite], so we have SIO without bypassing the block layer.

Maybe try to keep the change local to file-posix.c? I think you would
only have to modify raw_thread_pool_submit() so that it doesn't go
through the thread pool, but just calls func directly.

I don't think avoiding coroutines is possible without bypassing the block
layer altogether because everything is really expecting to be run in
coroutine context.

Kevin

Re: [Qemu-devel] [PATCH] target/riscv: Fix manually parsed 16 bit insn

[Palmer Dabbelt]

On Fri, 15 Mar 2019 06:51:40 PDT (-0700), Bastian Koppelmann wrote:

during the refactor to decodetree we removed the manual decoding that is
necessary for c.jal/c.addiw and removed the translation of c.flw/c.ld
and c.fsw/c.sd. This reintroduces the manual parsing and the
omited implementation.

Signed-off-by: Bastian Koppelmann 
---
 target/riscv/insn_trans/trans_rvc.inc.c | 30 -
 1 file changed, 25 insertions(+), 5 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvc.inc.c 
b/target/riscv/insn_trans/trans_rvc.inc.c
index bcdf64d3b7..5819f53f90 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -44,10 +44,19 @@ static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld 
*a)
 {
 #ifdef TARGET_RISCV32
 /* C.FLW ( RV32FC-only ) */
-return false;
+REQUIRE_FPU;
+REQUIRE_EXT(ctx, RVF);
+
+arg_c_lw tmp;
+decode_insn16_extract_cl_w(, ctx->opcode);
+arg_flw arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
+return trans_flw(ctx, );
 #else
 /* C.LD ( RV64C/RV128C-only ) */
-return false;
+arg_c_fld tmp;
+decode_insn16_extract_cl_d(, ctx->opcode);
+arg_ld arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
+return trans_ld(ctx, );
 #endif
 }

@@ -67,10 +76,19 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd 
*a)
 {
 #ifdef TARGET_RISCV32
 /* C.FSW ( RV32FC-only ) */
-return false;
+REQUIRE_FPU;
+REQUIRE_EXT(ctx, RVF);
+
+arg_c_sw tmp;
+decode_insn16_extract_cs_w(, ctx->opcode);
+arg_fsw arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
+return trans_fsw(ctx, );
 #else
 /* C.SD ( RV64C/RV128C-only ) */
-return false;
+arg_c_fsd tmp;
+decode_insn16_extract_cs_d(, ctx->opcode);
+arg_sd arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
+return trans_sd(ctx, );
 #endif
 }

@@ -88,7 +106,9 @@ static bool trans_c_jal_addiw(DisasContext *ctx, 
arg_c_jal_addiw *a)
 {
 #ifdef TARGET_RISCV32
 /* C.JAL */
-arg_jal arg = { .rd = 1, .imm = a->imm };
+arg_c_j tmp;
+decode_insn16_extract_cj(, ctx->opcode);
+arg_jal arg = { .rd = 1, .imm = tmp.imm };
 return trans_jal(ctx, );
 #else
 /* C.ADDIW */


Thanks!  This fixes my simple test case, so I'm going to pick it up for the 
next PR.  It also sounds like it's time for me to start testing rv32 Linux 
boots, so I'll go do that next...

Re: [Qemu-devel] [PULL 2/4] usb-mtp: fix some usb_mtp_write_data return paths

[Bandan Das]

Peter Maydell  writes:

> On Fri, 8 Mar 2019 at 19:39, Bandan Das  wrote:
>>
>> Peter Maydell  writes:
>> > But the two places in usb_mtp_get_data() that call
>> > usb_mtp_write_metadata() still don't check its return
>> > value: don't they need to handle failure too?
>> >
>> I believe this is ok because:
>> The return value of usb_mtp_write_data is only used to check if mkdir
>> failed and update s->result in usb_mtp_write_metadata().
>> The next time usb_mtp_handle_data is called, it will process s->result.
>
> I think I still don't really understand the error handling
> in this function. Why do we deal with mkdir() failing by
> having the function return -1 and then doing
>  usb_mtp_queue_result(s, RES_STORE_FULL, ...)
> (but only at one callsite), whereas for open() or write()
> failing we do the usb_mtp_queue_result(s, RES_STORE_FULL, ...)
> inside the function itself?
>

usb_mtp_write_metadata() handles the sendobjectinfo phase where the
initiator sends the metadata associated with the incoming object.
For a file, the name and the size is sent and once the responder sends
back OK, the initiator starts the sendobject phase. For a folder,
the name of the folder is sent with size being 0, and
no sendobject phase follows.

So, the reason I am sending back the return
value is because for a folder, I want to send a success or a failure
based on whether mkdir succeeded but for a file object, I want to return
success so that the next phase can continue. Is this rewrite better ?

 static void usb_mtp_object_delete(MTPState *s, uint32_t handle,
@@ -1674,7 +1666,13 @@ static void usb_mtp_write_data(MTPState *s)
 if (s->dataset.filename) {
 path = g_strdup_printf("%s/%s", parent->path, s->dataset.filename);
 if (s->dataset.format == FMT_ASSOCIATION) {
-d->fd = mkdir(path, mask);
+if (mkdir(path, mask)) {
+usb_mtp_queue_result(s, RES_STORE_FULL, d->trans,
+ 0, 0, 0, 0);
+} else {
+usb_mtp_queue_result(s, RES_STORE_FULL, d->trans,
+ 0, 0, 0, 0);
+}
 goto free;
 }
 d->fd = open(path, O_CREAT | O_WRONLY | O_CLOEXEC | O_NOFOLLOW, 
mask);
@@ -1769,17 +1767,10 @@ static void usb_mtp_write_metadata(MTPState *s, 
uint64_t dlen)
 
 if (s->dataset.format == FMT_ASSOCIATION) {
 usb_mtp_write_data(s);
-/* next_handle will be allocated to the newly created dir */
-if (d->fd == -1) {
-usb_mtp_queue_result(s, RES_STORE_FULL, d->trans,
- 0, 0, 0, 0);
-return;
-}
-d->fd = -1;
+} else {
+usb_mtp_queue_result(s, RES_OK, d->trans, 3, QEMU_STORAGE_ID,
+ s->dataset.parent_handle, next_handle);
 }
-
-usb_mtp_queue_result(s, RES_OK, d->trans, 3, QEMU_STORAGE_ID,
- s->dataset.parent_handle, next_handle);
 }
 
 static void usb_mtp_get_data(MTPState *s, mtp_container *container,



> thanks
> -- PMM

Re: [Qemu-devel] AMD SEV's /dev/sev permissions and probing QEMU for capabilities

[Singh, Brijesh]

Hi Daniel,


On 3/15/19 7:18 AM, Daniel P. Berrangé wrote:
> On Fri, Jan 18, 2019 at 12:51:50PM +, Singh, Brijesh wrote:
>>
>> On 1/18/19 3:39 AM, Erik Skultety wrote:
>>> I proceeded with cloning [1] to systemd and creating an udev rule that I 
>>> planned
>>> on submitting to systemd upstream - the initial idea was to mimic /dev/kvm 
>>> and
>>> make it world accessible to which Brijesh from AMD expressed a concern that
>>> regular users might deplete the resources (limit on the number of guests
>>> allowed by the platform).
> 
> [snip]
> 
>>> But since the limit is claimed to be around 4, Dan
>>
>>
>> FYI, the limit on EPYC is 15.
> 
> Do any cRyzen CPUs support SEV, and if so is their limit also 15 ?
> 

SEV support is *not* available on any of Ryzen's yet!


> Regardless, I'm assuming this limit is liable to change at any time
> in future CPU generations, so from the the mgmt app perspective I
> think is is important that QEMU / libvirt can both report what this
> limit is.
> 

Yes, the limit may change on future CPU generations. We can query the
limit through the CPUID Fn0x8000_001f[ECX].


> For QEMU I think query-sev-capabilities probably should report the
> guest limit.  I guess QEMU would in turn want to ask the kernel,
> rather than hardcode info itself. So if this info isn't already
> exposed by the kernel we might need work there too.
> 


I don't think we need to add a kernel interface for querying this
information, it can be obtained using the cpuid instruction or
access its via /dev/cpuid/.


> For libvirt we can then put this in the domain capabilities where
> we report SEV support.
>  > This will enable OpenStack and similar apps to plan which host they
> place a new VM on, to ensure there is SEV resource available for it
> to use.
> 
> Regards,
> Daniel
> 

Re: [Qemu-devel] [PATCH 2/8] authz: Normalize #include "authz/trace.h" to "trace.h"

[Daniel P . Berrangé]

On Fri, Mar 15, 2019 at 03:51:17PM +0100, Markus Armbruster wrote:
> Include the generated trace.h the same way as we do everywhere else.
> 
> Signed-off-by: Markus Armbruster 
> ---
>  authz/base.c | 2 +-
>  authz/list.c | 2 +-
>  authz/listfile.c | 2 +-
>  authz/pamacct.c  | 2 +-
>  authz/simple.c   | 2 +-
>  5 files changed, 5 insertions(+), 5 deletions(-)

Acked-by: Daniel P. Berrangé 


Regards,
Daniel
-- 
|: https://berrange.com  -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
|: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|

Re: [Qemu-devel] Combining synchronous and asynchronous IO

[Sergio Lopez]

Stefan Hajnoczi writes:

> On Thu, Mar 14, 2019 at 06:31:34PM +0100, Sergio Lopez wrote:
>> Our current AIO path does a great job at unloading the work from the VM,
>> and combined with IOThreads provides a good performance in most
>> scenarios. But it also comes with its costs, in both a longer execution
>> path and the need of the intervention of the scheduler at various
>> points.
>> 
>> There's one particular workload that suffers from this cost, and that's
>> when you have just 1 or 2 cores on the Guest issuing synchronous
>> requests. This happens to be a pretty common workload for some DBs and,
>> in a general sense, on small VMs.
>> 
>> I did a quick'n'dirty implementation on top of virtio-blk to get some
>> numbers. This comes from a VM with 4 CPUs running on an idle server,
>> with a secondary virtio-blk disk backed by a null_blk device with a
>> simulated latency of 30us.
>
> Can you describe the implementation in more detail?  Does "synchronous"
> mean that hw/block/virtio_blk.c makes a blocking preadv()/pwritev() call
> instead of calling blk_aio_preadv/pwritev()?  If so, then you are also
> bypassing the QEMU block layer (coroutines, request tracking, etc) and
> that might explain some of the latency.

The first implementation, the one I've used for getting these numbers,
it's just preadv/pwrite from virtio_blk.c, as you correctly guessed. I
know it's unfair, but I wanted to take a look at the best possible
scenario, and then measure the cost of the other layers.

I'm working now on writing non-coroutine counterparts for
blk_co_[preadv|pwrite], so we have SIO without bypassing the block layer.

> It's important for this discussion that we understand what your tried
> out.  "Synchronous" can mean different things.  Since iothread is in
> play the code path is still asynchronous from the vcpu thread's
> perspective (thanks ioeventfd!).  The guest CPU is not stuck during I/O
> (good for quality of service) - however SIO+iothread may need to be
> woken up and scheduled on a host CPU (bad for latency).

I've tried SIO with ioeventfd=off, to make it fully synchronous, but the
performance it's significantly worse. Not sure if this is due to cache
pollution, or simply the guest CPU is able to move on early and be ready
to process the IRQ when it's signalled. Or maybe both.

>>  - Average latency (us)
>> 
>> 
>> || AIO+iothread | SIO+iothread |
>> | 1 job  |  70  |  55  |
>> | 2 jobs |  83  |  82  |
>> | 4 jobs |  90  | 159  |
>> 
>
> BTW recently I've found that the latency distribution can contain
> important clues that a simple average doesn't show (e.g. multiple peaks,
> outliers, etc).  If you continue to investigate this it might be
> interesting to plot the distribution.

Interesting, noted.

>> In this case the intuition matches the reality, and synchronous IO wins
>> when there's just 1 job issuing the requests, while it loses hard when
>> the are 4.
>
> Have you looked at the overhead of AIO+event loop?  ppoll()/epoll(),
> read()ing the eventfd to clear it, and Linux AIO io_submit().

Not since a while, and that reminds me I wanted to check if we could
improve the poll-max-ns heuristics.

> I had some small patches that try to reorder/optimize these operations
> but never got around to benchmarking and publishing them.  They do not
> reduce latency as low as SIO but they shave off a handful of
> microseconds.
>
> Resuming this work might be useful.  Let me know if you'd like me to dig
> out the old patches.

I would definitely like to take a look at those patches.

>> 
>> While my first thought was implementing this as a tunable, turns out we
>> have a hint about the nature of the workload in the number of the
>> requests in the VQ. So I updated the code to use SIO if there's just 1
>> request and AIO otherwise, with these results:
>
> Nice, avoiding tunables is good.  That way it can automatically adjust
> depending on the current workload and we don't need to educate users on
> tweaking a tunable.
>
>> 
>> ---
>> || AIO+iothread | SIO+iothread | AIO+SIO+iothread |
>> | 1 job  |  70  |  55  |55|
>> | 2 jobs |  83  |  82  |78|
>> | 4 jobs |  90  | 159  |90|
>> ---
>> 
>> This data makes me think this is something worth pursuing, but I'd like
>> to hear your opinion on it.
>
> I think it's definitely worth experimenting with more.  One thing to
> consider: the iothread is a shared resource when multiple devices are
> assigned to a single iothread.  In that case we probably do not want SIO
> since it would block the other emulated devices from processing
> requests.

Good point.

> On a related note, there is a summer internship project to 

Re: [Qemu-devel] [Qemu-block] [PATCH] vpc: unlock Coroutine lock to make IO submit Concurrently

[Kevin Wolf]

Am 15.03.2019 um 15:04 hat Zhengui li geschrieben:
> Concurrent IO becomes serial IO because of the qemu Coroutine lock,
> which reduce IO performance severely.
> 
> So unlock Coroutine lock before bdrv_co_pwritev and
> bdrv_co_preadv to fix it.
> 
> Signed-off-by: Zhengui li 

Thanks, applied to the block-next branch for 4.1.

Kevin

Re: [Qemu-devel] Combining synchronous and asynchronous IO

[Stefan Hajnoczi]

On Thu, Mar 14, 2019 at 06:31:34PM +0100, Sergio Lopez wrote:
> Our current AIO path does a great job at unloading the work from the VM,
> and combined with IOThreads provides a good performance in most
> scenarios. But it also comes with its costs, in both a longer execution
> path and the need of the intervention of the scheduler at various
> points.
> 
> There's one particular workload that suffers from this cost, and that's
> when you have just 1 or 2 cores on the Guest issuing synchronous
> requests. This happens to be a pretty common workload for some DBs and,
> in a general sense, on small VMs.
> 
> I did a quick'n'dirty implementation on top of virtio-blk to get some
> numbers. This comes from a VM with 4 CPUs running on an idle server,
> with a secondary virtio-blk disk backed by a null_blk device with a
> simulated latency of 30us.

Can you describe the implementation in more detail?  Does "synchronous"
mean that hw/block/virtio_blk.c makes a blocking preadv()/pwritev() call
instead of calling blk_aio_preadv/pwritev()?  If so, then you are also
bypassing the QEMU block layer (coroutines, request tracking, etc) and
that might explain some of the latency.

It's important for this discussion that we understand what your tried
out.  "Synchronous" can mean different things.  Since iothread is in
play the code path is still asynchronous from the vcpu thread's
perspective (thanks ioeventfd!).  The guest CPU is not stuck during I/O
(good for quality of service) - however SIO+iothread may need to be
woken up and scheduled on a host CPU (bad for latency).

>  - Average latency (us)
> 
> 
> || AIO+iothread | SIO+iothread |
> | 1 job  |  70  |  55  |
> | 2 jobs |  83  |  82  |
> | 4 jobs |  90  | 159  |
> 

BTW recently I've found that the latency distribution can contain
important clues that a simple average doesn't show (e.g. multiple peaks,
outliers, etc).  If you continue to investigate this it might be
interesting to plot the distribution.

> In this case the intuition matches the reality, and synchronous IO wins
> when there's just 1 job issuing the requests, while it loses hard when
> the are 4.

Have you looked at the overhead of AIO+event loop?  ppoll()/epoll(),
read()ing the eventfd to clear it, and Linux AIO io_submit().

I had some small patches that try to reorder/optimize these operations
but never got around to benchmarking and publishing them.  They do not
reduce latency as low as SIO but they shave off a handful of
microseconds.

Resuming this work might be useful.  Let me know if you'd like me to dig
out the old patches.

> 
> While my first thought was implementing this as a tunable, turns out we
> have a hint about the nature of the workload in the number of the
> requests in the VQ. So I updated the code to use SIO if there's just 1
> request and AIO otherwise, with these results:

Nice, avoiding tunables is good.  That way it can automatically adjust
depending on the current workload and we don't need to educate users on
tweaking a tunable.

> 
> ---
> || AIO+iothread | SIO+iothread | AIO+SIO+iothread |
> | 1 job  |  70  |  55  |55|
> | 2 jobs |  83  |  82  |78|
> | 4 jobs |  90  | 159  |90|
> ---
> 
> This data makes me think this is something worth pursuing, but I'd like
> to hear your opinion on it.

I think it's definitely worth experimenting with more.  One thing to
consider: the iothread is a shared resource when multiple devices are
assigned to a single iothread.  In that case we probably do not want SIO
since it would block the other emulated devices from processing
requests.

On a related note, there is a summer internship project to implement
support for the new io_uring API (successor to Linux AIO):
https://wiki.qemu.org/Google_Summer_of_Code_2019#io_uring_AIO_engine

So please *don't* implement io_uring support right now ;-).

Stefan


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Description: PGP signature

[Qemu-devel] [PATCH 4/8] target/xtensa: Clean up core-isa.h header guards

[Markus Armbruster]

scripts/clean-header-guards.pl warns these headers use reserved
identifier _XTENSA_CORE_CONFIGURATION_H as header guard symbol.  It
additionally warns the guard doesn't match the file name.

Reuse of the same guard symbol in multiple headers is okay as long as
they cannot be included together.

Since we can avoid guard symbol reuse easily, do so: use the guard
symbol scripts/clean-header-guards.pl picks, less the TARGET_ prefix.

Signed-off-by: Markus Armbruster 
---
 target/xtensa/core-de212/core-isa.h | 8 +++-
 target/xtensa/core-sample_controller/core-isa.h | 8 +++-
 target/xtensa/core-test_kc705_be/core-isa.h | 8 +++-
 target/xtensa/core-test_mmuhifi_c3/core-isa.h   | 8 +++-
 4 files changed, 12 insertions(+), 20 deletions(-)

diff --git a/target/xtensa/core-de212/core-isa.h 
b/target/xtensa/core-de212/core-isa.h
index 78e7f38310..90ac329230 100644
--- a/target/xtensa/core-de212/core-isa.h
+++ b/target/xtensa/core-de212/core-isa.h
@@ -28,9 +28,8 @@
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
 
-#ifndef _XTENSA_CORE_CONFIGURATION_H
-#define _XTENSA_CORE_CONFIGURATION_H
-
+#ifndef XTENSA_CORE_DE212_CORE_ISA_H
+#define XTENSA_CORE_DE212_CORE_ISA_H
 
 /
Parameters Useful for Any Code, USER or PRIVILEGED
@@ -618,5 +617,4 @@
 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
 
 
-#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
+#endif /* XTENSA_CORE_DE212_CORE_ISA_H */
diff --git a/target/xtensa/core-sample_controller/core-isa.h 
b/target/xtensa/core-sample_controller/core-isa.h
index e681e43209..d53dca8665 100644
--- a/target/xtensa/core-sample_controller/core-isa.h
+++ b/target/xtensa/core-sample_controller/core-isa.h
@@ -28,9 +28,8 @@
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
 
-#ifndef _XTENSA_CORE_CONFIGURATION_H
-#define _XTENSA_CORE_CONFIGURATION_H
-
+#ifndef XTENSA_CORE_SAMPLE_CONTROLLER_CORE_ISA_H
+#define XTENSA_CORE_SAMPLE_CONTROLLER_CORE_ISA_H
 
 /
Parameters Useful for Any Code, USER or PRIVILEGED
@@ -640,5 +639,4 @@
 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
 
 
-#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
+#endif /* XTENSA_CORE_SAMPLE_CONTROLLER_CORE_ISA_H */
diff --git a/target/xtensa/core-test_kc705_be/core-isa.h 
b/target/xtensa/core-test_kc705_be/core-isa.h
index a4ebdf7197..408fed871d 100644
--- a/target/xtensa/core-test_kc705_be/core-isa.h
+++ b/target/xtensa/core-test_kc705_be/core-isa.h
@@ -28,9 +28,8 @@
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
 
-#ifndef _XTENSA_CORE_CONFIGURATION_H
-#define _XTENSA_CORE_CONFIGURATION_H
-
+#ifndef XTENSA_CORE_TEST_KC705_BE_CORE_ISA_H
+#define XTENSA_CORE_TEST_KC705_BE_CORE_ISA_H
 
 /
Parameters Useful for Any Code, USER or PRIVILEGED
@@ -571,5 +570,4 @@
 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
 
 
-#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
+#endif /* XTENSA_CORE_TEST_KC705_BE_CORE_ISA_H */
diff --git a/target/xtensa/core-test_mmuhifi_c3/core-isa.h 
b/target/xtensa/core-test_mmuhifi_c3/core-isa.h
index 309caa1a32..704a31f7c8 100644
--- a/target/xtensa/core-test_mmuhifi_c3/core-isa.h
+++ b/target/xtensa/core-test_mmuhifi_c3/core-isa.h
@@ -7,9 +7,8 @@
  * Copyright (c) 1999-2009 Tensilica Inc.
  */
 
-#ifndef _XTENSA_CORE_CONFIGURATION_H
-#define _XTENSA_CORE_CONFIGURATION_H
-
+#ifndef XTENSA_CORE_TEST_MMUHIFI_C3_CORE_ISA_H
+#define XTENSA_CORE_TEST_MMUHIFI_C3_CORE_ISA_H
 
 /
Parameters Useful for Any Code, USER or PRIVILEGED
@@ -380,5 +379,4 @@
 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
 
 
-#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
+#endif /* XTENSA_CORE_TEST_MMUHIFI_C3_CORE_ISA_H */
-- 
2.17.2

[Qemu-devel] [PATCH 2/8] authz: Normalize #include "authz/trace.h" to "trace.h"

[Markus Armbruster]

Include the generated trace.h the same way as we do everywhere else.

Signed-off-by: Markus Armbruster 
---
 authz/base.c | 2 +-
 authz/list.c | 2 +-
 authz/listfile.c | 2 +-
 authz/pamacct.c  | 2 +-
 authz/simple.c   | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/authz/base.c b/authz/base.c
index 110dfa4195..baf39fff25 100644
--- a/authz/base.c
+++ b/authz/base.c
@@ -20,7 +20,7 @@
 
 #include "qemu/osdep.h"
 #include "authz/base.h"
-#include "authz/trace.h"
+#include "trace.h"
 
 bool qauthz_is_allowed(QAuthZ *authz,
const char *identity,
diff --git a/authz/list.c b/authz/list.c
index dc6b0fec13..831da936fe 100644
--- a/authz/list.c
+++ b/authz/list.c
@@ -20,7 +20,7 @@
 
 #include "qemu/osdep.h"
 #include "authz/list.h"
-#include "authz/trace.h"
+#include "trace.h"
 #include "qom/object_interfaces.h"
 #include "qapi/qapi-visit-authz.h"
 
diff --git a/authz/listfile.c b/authz/listfile.c
index d4579767e7..674683c0ea 100644
--- a/authz/listfile.c
+++ b/authz/listfile.c
@@ -20,7 +20,7 @@
 
 #include "qemu/osdep.h"
 #include "authz/listfile.h"
-#include "authz/trace.h"
+#include "trace.h"
 #include "qemu/error-report.h"
 #include "qemu/main-loop.h"
 #include "qemu/sockets.h"
diff --git a/authz/pamacct.c b/authz/pamacct.c
index 5038358cdc..7539867923 100644
--- a/authz/pamacct.c
+++ b/authz/pamacct.c
@@ -20,7 +20,7 @@
 
 #include "qemu/osdep.h"
 #include "authz/pamacct.h"
-#include "authz/trace.h"
+#include "trace.h"
 #include "qom/object_interfaces.h"
 
 #include 
diff --git a/authz/simple.c b/authz/simple.c
index 8ab718803e..c409ce7efc 100644
--- a/authz/simple.c
+++ b/authz/simple.c
@@ -20,7 +20,7 @@
 
 #include "qemu/osdep.h"
 #include "authz/simple.h"
-#include "authz/trace.h"
+#include "trace.h"
 #include "qom/object_interfaces.h"
 
 static bool qauthz_simple_is_allowed(QAuthZ *authz,
-- 
2.17.2

Re: [Qemu-devel] [PATCH] vpc: unlock Coroutine lock to make IO submit Concurrently

[Paolo Bonzini]

On 15/03/19 15:04, Zhengui li wrote:
> Concurrent IO becomes serial IO because of the qemu Coroutine lock,
> which reduce IO performance severely.
> 
> So unlock Coroutine lock before bdrv_co_pwritev and
> bdrv_co_preadv to fix it.
> 
> Signed-off-by: Zhengui li 
> ---
>  block/vpc.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/block/vpc.c b/block/vpc.c
> index 52ab717..1133855 100644
> --- a/block/vpc.c
> +++ b/block/vpc.c
> @@ -639,8 +639,10 @@ vpc_co_preadv(BlockDriverState *bs, uint64_t offset, 
> uint64_t bytes,
>  qemu_iovec_reset(_qiov);
>  qemu_iovec_concat(_qiov, qiov, bytes_done, n_bytes);
>  
> +qemu_co_mutex_unlock(>lock);
>  ret = bdrv_co_preadv(bs->file, image_offset, n_bytes,
>   _qiov, 0);
> +qemu_co_mutex_lock(>lock);
>  if (ret < 0) {
>  goto fail;
>  }
> @@ -697,8 +699,10 @@ vpc_co_pwritev(BlockDriverState *bs, uint64_t offset, 
> uint64_t bytes,
>  qemu_iovec_reset(_qiov);
>  qemu_iovec_concat(_qiov, qiov, bytes_done, n_bytes);
>  
> +qemu_co_mutex_unlock(>lock);
>  ret = bdrv_co_pwritev(bs->file, image_offset, n_bytes,
>_qiov, 0);
> +qemu_co_mutex_lock(>lock);
>  if (ret < 0) {
>  goto fail;
>  }
> 

This should be okay, because vpc.c is somewhat simple-minded and it
doesn't recycle unused blocks in the middle of the file.

Reviewed-by: Paolo Bonzini 

Paolo

Re: [Qemu-devel] State of QEMU CI as we enter 4.0

[Stefan Hajnoczi]

On Thu, Mar 14, 2019 at 03:57:06PM +, Alex Bennée wrote:
> As we approach stabilisation for 4.0 I thought it would be worth doing a
> review of the current state of CI and stimulate some discussion of where
> it is working for us and what could be improved.

Thanks for this summary and for all the work that is being put into CI.

How should all sub-maintainers be checking their pull requests?

We should have information and a strict policy on minimum testing of
pull requests.  Right now I imagine it varies a lot between
sub-maintainers.

For my block pull requests I run qemu-iotests locally and also push to
GitHub to trigger Travis CI.

Stefan


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Description: PGP signature

Re: [Qemu-devel] [PATCH] block: Silence Coverity in bdrv_drop_intermediate()

[Markus Armbruster]

Kevin Wolf  writes:

> Coverity doesn't like that the return value of bdrv_check_update_perm()
> stays unused only in this place (CID 1399710).
>
> Even if checking local_err should be equivalent to checking ret < 0,
> let's switch to using the return value to be more consistent (and in
> case of a bug somewhere down the call chain, forgetting to assign errp
> is more likely than returning 0 for an error case).
>
> Signed-off-by: Kevin Wolf 
> ---
>  block.c | 7 +++
>  1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/block.c b/block.c
> index ed9253c786..0a93ee9ac8 100644
> --- a/block.c
> +++ b/block.c
> @@ -4350,11 +4350,10 @@ int bdrv_drop_intermediate(BlockDriverState *top, 
> BlockDriverState *base,
>  QLIST_FOREACH_SAFE(c, >parents, next_parent, next) {
>  /* Check whether we are allowed to switch c from top to base */
>  GSList *ignore_children = g_slist_prepend(NULL, c);
> -bdrv_check_update_perm(base, NULL, c->perm, c->shared_perm,
> -   ignore_children, _err);
> +ret = bdrv_check_update_perm(base, NULL, c->perm, c->shared_perm,
> + ignore_children, _err);
>  g_slist_free(ignore_children);
> -if (local_err) {
> -ret = -EPERM;
> +if (ret < 0) {
>  error_report_err(local_err);
>  goto exit;
>  }

Reviewed-by: Markus Armbruster 

Re: [Qemu-devel] [PATCH v3 09/23] util: Add qemu_guest_getrandom and associated routines

[Daniel P . Berrangé]

On Thu, Mar 14, 2019 at 08:26:15PM -0700, Richard Henderson wrote:
> This routine is intended to produce high-quality random numbers to the
> guest.  Normally, such numbers are crypto quality from the host, but a
> command-line option can force the use of a fully deterministic sequence
> for use while debugging.
> 
> Cc: Daniel P. Berrangé 
> Signed-off-by: Richard Henderson 
> ---
>  include/qemu/guest-random.h | 68 +++
>  util/guest-random.c | 93 +
>  util/Makefile.objs  |  1 +
>  3 files changed, 162 insertions(+)
>  create mode 100644 include/qemu/guest-random.h
>  create mode 100644 util/guest-random.c

Reviewed-by: Daniel P. Berrangé 


Regards,
Daniel
-- 
|: https://berrange.com  -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
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Re: [Qemu-devel] [PATCH v3 07/23] ui/vnc: Split out authentication_failure

[Daniel P . Berrangé]

On Thu, Mar 14, 2019 at 08:26:13PM -0700, Richard Henderson wrote:
> There were 3 copies of this code, one of which used the wrong
> data size for the failure indicator.
> 
> Cc: Gerd Hoffmann 
> Signed-off-by: Richard Henderson 
> ---
>  ui/vnc.c | 37 +++--
>  1 file changed, 15 insertions(+), 22 deletions(-)

Reviewed-by: Daniel P. Berrangé 


Regards,
Daniel
-- 
|: https://berrange.com  -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
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Re: [Qemu-devel] [Qemu-block] [PATCH] block: Silence Coverity in bdrv_drop_intermediate()

[Alberto Garcia]

On Fri 15 Mar 2019 12:18:43 PM CET, Kevin Wolf  wrote:
> Coverity doesn't like that the return value of bdrv_check_update_perm()
> stays unused only in this place (CID 1399710).
>
> Even if checking local_err should be equivalent to checking ret < 0,
> let's switch to using the return value to be more consistent (and in
> case of a bug somewhere down the call chain, forgetting to assign errp
> is more likely than returning 0 for an error case).
>
> Signed-off-by: Kevin Wolf 

Reviewed-by: Alberto Garcia 

Berto

[Qemu-devel] [PATCH v2 0/2] ati-vga: Implement DDC and EDID info from monitor

[BALATON Zoltan]

Version 2 of proposed DDC implementation for ati-vga. This now cleans
up the include from hw/i2c/bitbang_i2c.h by moving that to public
header and implement DVI DDC port for rv100 model which supposed to fix
loading the Linux radeonfb driver.

BALATON Zoltan (2):
  i2c: Move contents of bitbang_i2c.h to include/hw/i2c/i2c.h
  ati-vga: Implement DDC and EDID info from monitor

 hw/display/Kconfig |  2 ++
 hw/display/ati.c   | 44 ++--
 hw/display/ati_int.h   |  4 
 hw/display/ati_regs.h  |  1 +
 hw/i2c/bitbang_i2c.c   |  2 +-
 hw/i2c/bitbang_i2c.h   | 12 
 hw/i2c/ppc4xx_i2c.c|  1 -
 hw/i2c/versatile_i2c.c |  2 +-
 include/hw/i2c/i2c.h   |  7 +++
 9 files changed, 58 insertions(+), 17 deletions(-)
 delete mode 100644 hw/i2c/bitbang_i2c.h

-- 
2.13.7

[Qemu-devel] [PATCH 5/8] Clean up header guards that don't match their file name

[Markus Armbruster]

Header guard symbols should match their file name to make guard
collisions less likely.

Cleaned up with scripts/clean-header-guards.pl, followed by some
renaming of new guard symbols picked by the script to better ones.

Signed-off-by: Markus Armbruster 
---
 contrib/elf2dmp/qemu_elf.h| 6 +++---
 disas/nanomips.h  | 4 ++--
 fsdev/qemu-fsdev-throttle.h   | 7 ---
 hw/arm/smmuv3-internal.h  | 4 ++--
 hw/display/vga_regs.h | 6 +++---
 hw/rdma/vmw/pvrdma_qp_ops.h   | 4 ++--
 hw/sd/sdmmc-internal.h| 5 +++--
 include/authz/listfile.h  | 8 +++-
 include/authz/pamacct.h   | 7 +++
 include/hw/audio/soundhw.h| 4 ++--
 include/hw/i386/x86-iommu.h   | 4 ++--
 include/hw/intc/heathrow_pic.h| 6 +++---
 include/hw/intc/xlnx-pmu-iomod-intc.h | 6 +++---
 include/hw/misc/armsse-mhu.h  | 4 ++--
 include/hw/pci-host/sabre.h   | 4 ++--
 include/hw/watchdog/wdt_aspeed.h  | 7 ---
 include/hw/xen/xen-legacy-backend.h   | 6 +++---
 include/hw/xtensa/xtensa-isa.h| 6 +++---
 include/migration/qemu-file-types.h   | 4 ++--
 include/qemu/filemonitor.h| 6 +++---
 include/scsi/constants.h  | 4 ++--
 net/colo.h| 6 +++---
 target/i386/hax-posix.h   | 6 +++---
 target/i386/hvf/x86_task.h| 6 --
 target/nios2/cpu.h| 7 ---
 target/nios2/mmu.h| 7 ---
 target/ppc/mmu-book3s-v3.h| 6 +++---
 tests/libqos/qgraph_internal.h| 4 ++--
 tests/migration/migration-test.h  | 7 ---
 29 files changed, 83 insertions(+), 78 deletions(-)

diff --git a/contrib/elf2dmp/qemu_elf.h b/contrib/elf2dmp/qemu_elf.h
index 2a7963821a..66ee1f0ed5 100644
--- a/contrib/elf2dmp/qemu_elf.h
+++ b/contrib/elf2dmp/qemu_elf.h
@@ -5,8 +5,8 @@
  *
  */
 
-#ifndef ELF2DMP_ELF_H
-#define ELF2DMP_ELF_H
+#ifndef EMPF2DMP_QEMU_ELF_H
+#define EMPF2DMP_QEMU_ELF_H
 
 #include "elf.h"
 
@@ -47,4 +47,4 @@ void QEMU_Elf_exit(QEMU_Elf *qe);
 Elf64_Phdr *elf64_getphdr(void *map);
 Elf64_Half elf_getphdrnum(void *map);
 
-#endif /* ELF2DMP_ELF_H */
+#endif /* ELF2DMP_QEMU_ELF_H */
diff --git a/disas/nanomips.h b/disas/nanomips.h
index 243c3e38d2..a0a2225301 100644
--- a/disas/nanomips.h
+++ b/disas/nanomips.h
@@ -20,8 +20,8 @@
  *
  */
 
-#ifndef NANOMIPS_DISASSEMBLER_H
-#define NANOMIPS_DISASSEMBLER_H
+#ifndef DISAS_NANOMIPS_H
+#define DISAS_NANOMIPS_H
 
 #include 
 
diff --git a/fsdev/qemu-fsdev-throttle.h b/fsdev/qemu-fsdev-throttle.h
index 4e83bdac25..7d6211d499 100644
--- a/fsdev/qemu-fsdev-throttle.h
+++ b/fsdev/qemu-fsdev-throttle.h
@@ -12,8 +12,8 @@
  *
  */
 
-#ifndef _FSDEV_THROTTLE_H
-#define _FSDEV_THROTTLE_H
+#ifndef QEMU_FSDEV_THROTTLE_H
+#define QEMU_FSDEV_THROTTLE_H
 
 #include "block/aio.h"
 #include "qemu/main-loop.h"
@@ -35,4 +35,5 @@ void coroutine_fn fsdev_co_throttle_request(FsThrottle *, 
bool ,
 struct iovec *, int);
 
 void fsdev_throttle_cleanup(FsThrottle *);
-#endif /* _FSDEV_THROTTLE_H */
+
+#endif /* QEMU_FSDEV_THROTTLE_H */
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index 19540f8f41..b160289cd1 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -18,8 +18,8 @@
  * with this program; if not, see .
  */
 
-#ifndef HW_ARM_SMMU_V3_INTERNAL_H
-#define HW_ARM_SMMU_V3_INTERNAL_H
+#ifndef HW_ARM_SMMUV3_INTERNAL_H
+#define HW_ARM_SMMUV3_INTERNAL_H
 
 #include "hw/arm/smmu-common.h"
 
diff --git a/hw/display/vga_regs.h b/hw/display/vga_regs.h
index 16886f5eed..30a98b8736 100644
--- a/hw/display/vga_regs.h
+++ b/hw/display/vga_regs.h
@@ -14,8 +14,8 @@
  *
  */
 
-#ifndef LINUX_VIDEO_VGA_H
-#define LINUX_VIDEO_VGA_H
+#ifndef HW_VGA_REGS_H
+#define HW_VGA_REGS_H
 
 /* Some of the code below is taken from SVGAlib.  The original,
unmodified copyright notice for that code is below. */
@@ -156,4 +156,4 @@
 /* VGA graphics controller bit masks */
 #define VGA_GR06_GRAPHICS_MODE  0x01
 
-#endif /* LINUX_VIDEO_VGA_H */
+#endif /* HW_VGA_REGS_H */
diff --git a/hw/rdma/vmw/pvrdma_qp_ops.h b/hw/rdma/vmw/pvrdma_qp_ops.h
index 31cb48ba29..3a76a59c87 100644
--- a/hw/rdma/vmw/pvrdma_qp_ops.h
+++ b/hw/rdma/vmw/pvrdma_qp_ops.h
@@ -13,8 +13,8 @@
  *
  */
 
-#ifndef PVRDMA_QP_H
-#define PVRDMA_QP_H
+#ifndef PVRDMA_QP_OPS_H
+#define PVRDMA_QP_OPS_H
 
 #include "pvrdma.h"
 
diff --git a/hw/sd/sdmmc-internal.h b/hw/sd/sdmmc-internal.h
index 9aa04766fc..d8bf17d204 100644
--- a/hw/sd/sdmmc-internal.h
+++ b/hw/sd/sdmmc-internal.h
@@ -7,8 +7,9 @@
  * See the COPYING file in the top-level directory.
  * SPDX-License-Identifier: GPL-2.0-or-later
  */
-#ifndef SD_INTERNAL_H
-#define SD_INTERNAL_H
+
+#ifndef SDMMC_INTERNAL_H
+#define SDMMC_INTERNAL_H
 
 #define SDMMC_CMD_MAX 64
 
diff --git a/include/authz/listfile.h b/include/authz/listfile.h
index 

[Qemu-devel] [PATCH v2 1/2] i2c: Move contents of bitbang_i2c.h to include/hw/i2c/i2c.h

[BALATON Zoltan]

The bitbang i2c implementation is also useful for other device models
such as DDC in display controllers. Because of this, part of the file had
to be moved to the main i2c.h to avoid a warning in commit 2b4c1125ac.
Move the rest of the hw/i2c/bitbang_i2c.h to the main i2c.h now to allow
it to be used from other device models.

Signed-off-by: BALATON Zoltan 
---
 hw/i2c/bitbang_i2c.c   |  2 +-
 hw/i2c/bitbang_i2c.h   | 12 
 hw/i2c/ppc4xx_i2c.c|  1 -
 hw/i2c/versatile_i2c.c |  2 +-
 include/hw/i2c/i2c.h   |  7 +++
 5 files changed, 9 insertions(+), 15 deletions(-)
 delete mode 100644 hw/i2c/bitbang_i2c.h

diff --git a/hw/i2c/bitbang_i2c.c b/hw/i2c/bitbang_i2c.c
index 8be88ee265..a1fe3ac35c 100644
--- a/hw/i2c/bitbang_i2c.c
+++ b/hw/i2c/bitbang_i2c.c
@@ -11,7 +11,7 @@
  */
 #include "qemu/osdep.h"
 #include "hw/hw.h"
-#include "bitbang_i2c.h"
+#include "hw/i2c/i2c.h"
 #include "hw/sysbus.h"
 
 //#define DEBUG_BITBANG_I2C
diff --git a/hw/i2c/bitbang_i2c.h b/hw/i2c/bitbang_i2c.h
deleted file mode 100644
index 9443021710..00
--- a/hw/i2c/bitbang_i2c.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef BITBANG_I2C_H
-#define BITBANG_I2C_H
-
-#include "hw/i2c/i2c.h"
-
-#define BITBANG_I2C_SDA 0
-#define BITBANG_I2C_SCL 1
-
-bitbang_i2c_interface *bitbang_i2c_init(I2CBus *bus);
-int bitbang_i2c_set(bitbang_i2c_interface *i2c, int line, int level);
-
-#endif
diff --git a/hw/i2c/ppc4xx_i2c.c b/hw/i2c/ppc4xx_i2c.c
index d6dfafab31..a907d0194e 100644
--- a/hw/i2c/ppc4xx_i2c.c
+++ b/hw/i2c/ppc4xx_i2c.c
@@ -30,7 +30,6 @@
 #include "cpu.h"
 #include "hw/hw.h"
 #include "hw/i2c/ppc4xx_i2c.h"
-#include "bitbang_i2c.h"
 
 #define PPC4xx_I2C_MEM_SIZE 18
 
diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c
index da9f298ee5..88f0b89f8d 100644
--- a/hw/i2c/versatile_i2c.c
+++ b/hw/i2c/versatile_i2c.c
@@ -23,7 +23,7 @@
 
 #include "qemu/osdep.h"
 #include "hw/sysbus.h"
-#include "bitbang_i2c.h"
+#include "hw/i2c/i2c.h"
 #include "qemu/log.h"
 
 #define TYPE_VERSATILE_I2C "versatile_i2c"
diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
index 8e236f7bb4..fa102dde80 100644
--- a/include/hw/i2c/i2c.h
+++ b/include/hw/i2c/i2c.h
@@ -81,8 +81,15 @@ uint8_t i2c_recv(I2CBus *bus);
 
 DeviceState *i2c_create_slave(I2CBus *bus, const char *name, uint8_t addr);
 
+/* generic bitbang i2c interface */
+#define BITBANG_I2C_SDA 0
+#define BITBANG_I2C_SCL 1
+
 typedef struct bitbang_i2c_interface bitbang_i2c_interface;
 
+bitbang_i2c_interface *bitbang_i2c_init(I2CBus *bus);
+int bitbang_i2c_set(bitbang_i2c_interface *i2c, int line, int level);
+
 /* lm832x.c */
 void lm832x_key_event(DeviceState *dev, int key, int state);
 
-- 
2.13.7

[Qemu-devel] [PATCH 3/8] linux-user/nios2 linux-user/riscv: Clean up header guards

[Markus Armbruster]

Reuse of the same guard symbol in multiple headers is okay as long as
they cannot be included together.  scripts/clean-header-guards.pl
can't tell, so it warns.

Since we can avoid guard symbol reuse easily, do so: use guard symbol
${target^^}_${fname^^} for linux-user/$target/$fname, just like we did
in commit a9c94277f0..3500385697.

Signed-off-by: Markus Armbruster 
---
 linux-user/nios2/target_cpu.h | 4 ++--
 linux-user/nios2/target_signal.h  | 6 +++---
 linux-user/nios2/target_structs.h | 4 ++--
 linux-user/nios2/target_syscall.h | 6 +++---
 linux-user/riscv/target_cpu.h | 4 ++--
 linux-user/riscv/target_signal.h  | 6 +++---
 linux-user/riscv/target_structs.h | 4 ++--
 7 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/linux-user/nios2/target_cpu.h b/linux-user/nios2/target_cpu.h
index 14f63338fa..5596c05c9c 100644
--- a/linux-user/nios2/target_cpu.h
+++ b/linux-user/nios2/target_cpu.h
@@ -17,8 +17,8 @@
  * License along with this library; if not, see .
  */
 
-#ifndef TARGET_CPU_H
-#define TARGET_CPU_H
+#ifndef NIOS2_TARGET_CPU_H
+#define NIOS2_TARGET_CPU_H
 
 static inline void cpu_clone_regs(CPUNios2State *env, target_ulong newsp)
 {
diff --git a/linux-user/nios2/target_signal.h b/linux-user/nios2/target_signal.h
index 7776bcdbfd..fe48721b3d 100644
--- a/linux-user/nios2/target_signal.h
+++ b/linux-user/nios2/target_signal.h
@@ -1,5 +1,5 @@
-#ifndef TARGET_SIGNAL_H
-#define TARGET_SIGNAL_H
+#ifndef NIOS2_TARGET_SIGNAL_H
+#define NIOS2_TARGET_SIGNAL_H
 
 /* this struct defines a stack used during syscall handling */
 
@@ -18,4 +18,4 @@ typedef struct target_sigaltstack {
 
 #include "../generic/signal.h"
 
-#endif /* TARGET_SIGNAL_H */
+#endif /* NIOS2_TARGET_SIGNAL_H */
diff --git a/linux-user/nios2/target_structs.h 
b/linux-user/nios2/target_structs.h
index 8713772089..7145251706 100644
--- a/linux-user/nios2/target_structs.h
+++ b/linux-user/nios2/target_structs.h
@@ -16,8 +16,8 @@
  * You should have received a copy of the GNU Lesser General Public
  * License along with this library; if not, see .
  */
-#ifndef TARGET_STRUCTS_H
-#define TARGET_STRUCTS_H
+#ifndef NIOS2_TARGET_STRUCTS_H
+#define NIOS2_TARGET_STRUCTS_H
 
 struct target_ipc_perm {
 abi_int __key;  /* Key.  */
diff --git a/linux-user/nios2/target_syscall.h 
b/linux-user/nios2/target_syscall.h
index ca6b7e69f6..f3b2a500f4 100644
--- a/linux-user/nios2/target_syscall.h
+++ b/linux-user/nios2/target_syscall.h
@@ -1,5 +1,5 @@
-#ifndef TARGET_SYSCALL_H
-#define TARGET_SYSCALL_H
+#ifndef NIOS2_TARGET_SYSCALL_H
+#define NIOS2_TARGET_SYSCALL_H
 
 #define UNAME_MACHINE "nios2"
 #define UNAME_MINIMUM_RELEASE "3.19.0"
@@ -34,4 +34,4 @@ struct target_pt_regs {
 #define TARGET_MLOCKALL_MCL_CURRENT 1
 #define TARGET_MLOCKALL_MCL_FUTURE  2
 
-#endif  /* TARGET_SYSCALL_H */
+#endif /* NIOS2_TARGET_SYSCALL_H */
diff --git a/linux-user/riscv/target_cpu.h b/linux-user/riscv/target_cpu.h
index 7e090f376a..90f9a4171e 100644
--- a/linux-user/riscv/target_cpu.h
+++ b/linux-user/riscv/target_cpu.h
@@ -1,5 +1,5 @@
-#ifndef TARGET_CPU_H
-#define TARGET_CPU_H
+#ifndef RISCV_TARGET_CPU_H
+#define RISCV_TARGET_CPU_H
 
 static inline void cpu_clone_regs(CPURISCVState *env, target_ulong newsp)
 {
diff --git a/linux-user/riscv/target_signal.h b/linux-user/riscv/target_signal.h
index c8b1455800..f113ba9a55 100644
--- a/linux-user/riscv/target_signal.h
+++ b/linux-user/riscv/target_signal.h
@@ -1,5 +1,5 @@
-#ifndef TARGET_SIGNAL_H
-#define TARGET_SIGNAL_H
+#ifndef RISCV_TARGET_SIGNAL_H
+#define RISCV_TARGET_SIGNAL_H
 
 typedef struct target_sigaltstack {
 abi_ulong ss_sp;
@@ -15,4 +15,4 @@ typedef struct target_sigaltstack {
 
 #include "../generic/signal.h"
 
-#endif /* TARGET_SIGNAL_H */
+#endif /* RISCV_TARGET_SIGNAL_H */
diff --git a/linux-user/riscv/target_structs.h 
b/linux-user/riscv/target_structs.h
index 4f0462c497..ea3e5ed17e 100644
--- a/linux-user/riscv/target_structs.h
+++ b/linux-user/riscv/target_structs.h
@@ -4,8 +4,8 @@
  * This is a copy of ../aarch64/target_structs.h atm.
  *
  */
-#ifndef TARGET_STRUCTS_H
-#define TARGET_STRUCTS_H
+#ifndef RISCV_TARGET_STRUCTS_H
+#define RISCV_TARGET_STRUCTS_H
 
 struct target_ipc_perm {
 abi_int __key;  /* Key.  */
-- 
2.17.2

Re: [Qemu-devel] [Qemu-block] [PATCH] xen-block: Replace qdict_put_obj() by qdict_put() where appropriate

[Markus Armbruster]

Anthony PERARD  writes:

> On Thu, Mar 14, 2019 at 08:04:00PM +0100, Markus Armbruster wrote:
>> Kevin Wolf  writes:
>> 
>> > Am 13.03.2019 um 18:44 hat Markus Armbruster geschrieben:
>> >> Patch created mechanically by rerunning:
>> >> 
>> >> $ spatch --sp-file scripts/coccinelle/qobject.cocci \
>> >>  --macro-file scripts/cocci-macro-file.h \
>> >>  --dir hw/block --in-place
>> >> 
>> >> Signed-off-by: Markus Armbruster 
>> >
>> > Reviewed-by: Kevin Wolf 
>> 
>> Thanks!
>> 
>> > Which tree should this go through? The Xen one?
>> 
>> Fine with me.  I could also include it in a "miscellaneous cleanup" pull
>> request along with other cleanup patches I got in flight.
>
> Markus, I don't have any other Xen patches, so could you include this
> one in your pull request?

Sure!

[Qemu-devel] [PATCH 6/8] Clean up ill-advised or unusual header guards

[Markus Armbruster]

Leading underscores are ill-advised because such identifiers are
reserved.  Trailing underscores are merely ugly.  Strip both.

Our header guards commonly end in _H.  Normalize the exceptions.

Done with scripts/clean-header-guards.pl.

Signed-off-by: Markus Armbruster 
---
 block/crypto.h | 6 +++---
 hw/i386/amd_iommu.h| 4 ++--
 hw/tpm/tpm_ioctl.h | 7 ---
 hw/xtensa/xtensa_memory.h  | 4 ++--
 include/authz/base.h   | 7 +++
 include/authz/list.h   | 7 +++
 include/authz/simple.h | 7 +++
 include/chardev/spice.h| 4 ++--
 include/hw/ppc/pnv.h   | 7 ---
 include/hw/ppc/pnv_core.h  | 7 ---
 include/hw/ppc/pnv_lpc.h   | 7 ---
 include/hw/ppc/pnv_occ.h   | 7 ---
 include/hw/ppc/pnv_psi.h   | 7 ---
 include/hw/ppc/pnv_xscom.h | 7 ---
 include/hw/ppc/spapr_ovec.h| 7 ---
 include/hw/timer/pl031.h   | 4 ++--
 include/hw/virtio/vhost-vsock.h| 6 +++---
 include/hw/virtio/virtio-crypto.h  | 6 +++---
 include/hw/xen/start_info.h| 6 +++---
 include/hw/xtensa/mx_pic.h | 4 ++--
 include/qemu/drm.h | 4 ++--
 include/qemu/jhash.h   | 6 +++---
 include/sysemu/hvf.h   | 5 +++--
 linux-user/xtensa/syscall_nr.h | 6 +++---
 linux-user/xtensa/target_structs.h | 4 ++--
 linux-user/xtensa/termbits.h   | 6 +++---
 qga/vss-win32/vss-handles.h| 4 ++--
 slirp/src/debug.h  | 6 +++---
 slirp/src/stream.h | 6 +++---
 slirp/src/util.h   | 5 +++--
 slirp/src/vmstate.h| 5 +++--
 target/i386/hax-i386.h | 4 ++--
 target/i386/hax-interface.h| 4 ++--
 target/i386/hvf/hvf-i386.h | 4 ++--
 target/i386/hvf/vmcs.h | 4 ++--
 target/i386/hvf/x86_emu.h  | 5 +++--
 target/i386/hvf/x86_flags.h| 7 ---
 target/i386/hvf/x86_mmu.h  | 7 ---
 target/riscv/pmp.h | 4 ++--
 target/sparc/asi.h | 6 +++---
 tests/libqos/e1000e.h  | 4 ++--
 tests/libqos/sdhci.h   | 4 ++--
 42 files changed, 121 insertions(+), 110 deletions(-)

diff --git a/block/crypto.h b/block/crypto.h
index dd7d47903c..b935695e79 100644
--- a/block/crypto.h
+++ b/block/crypto.h
@@ -18,8 +18,8 @@
  *
  */
 
-#ifndef BLOCK_CRYPTO_H__
-#define BLOCK_CRYPTO_H__
+#ifndef BLOCK_CRYPTO_H
+#define BLOCK_CRYPTO_H
 
 #define BLOCK_CRYPTO_OPT_DEF_KEY_SECRET(prefix, helpstr)\
 {   \
@@ -94,4 +94,4 @@ block_crypto_create_opts_init(QDict *opts, Error **errp);
 QCryptoBlockOpenOptions *
 block_crypto_open_opts_init(QDict *opts, Error **errp);
 
-#endif /* BLOCK_CRYPTO_H__ */
+#endif /* BLOCK_CRYPTO_H */
diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h
index 0ff9095f32..3a694b186b 100644
--- a/hw/i386/amd_iommu.h
+++ b/hw/i386/amd_iommu.h
@@ -18,8 +18,8 @@
  * with this program; if not, see .
  */
 
-#ifndef AMD_IOMMU_H_
-#define AMD_IOMMU_H_
+#ifndef AMD_IOMMU_H
+#define AMD_IOMMU_H
 
 #include "hw/hw.h"
 #include "hw/pci/pci.h"
diff --git a/hw/tpm/tpm_ioctl.h b/hw/tpm/tpm_ioctl.h
index 59a0b0595d..f5f5c553a9 100644
--- a/hw/tpm/tpm_ioctl.h
+++ b/hw/tpm/tpm_ioctl.h
@@ -5,8 +5,9 @@
  *
  * This file is licensed under the terms of the 3-clause BSD license
  */
-#ifndef _TPM_IOCTL_H_
-#define _TPM_IOCTL_H_
+
+#ifndef TPM_IOCTL_H
+#define TPM_IOCTL_H
 
 #include 
 #include 
@@ -267,4 +268,4 @@ enum {
 CMD_SET_BUFFERSIZE,
 };
 
-#endif /* _TPM_IOCTL_H */
+#endif /* TPM_IOCTL_H */
diff --git a/hw/xtensa/xtensa_memory.h b/hw/xtensa/xtensa_memory.h
index e9aa08749d..89125c4a0d 100644
--- a/hw/xtensa/xtensa_memory.h
+++ b/hw/xtensa/xtensa_memory.h
@@ -25,8 +25,8 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef _XTENSA_MEMORY_H
-#define _XTENSA_MEMORY_H
+#ifndef XTENSA_MEMORY_H
+#define XTENSA_MEMORY_H
 
 #include "qemu-common.h"
 #include "cpu.h"
diff --git a/include/authz/base.h b/include/authz/base.h
index 77dcd54c4c..05f1df845c 100644
--- a/include/authz/base.h
+++ b/include/authz/base.h
@@ -18,8 +18,8 @@
  *
  */
 
-#ifndef QAUTHZ_BASE_H__
-#define QAUTHZ_BASE_H__
+#ifndef QAUTHZ_BASE_H
+#define QAUTHZ_BASE_H
 
 #include "qemu-common.h"
 #include "qapi/error.h"
@@ -108,5 +108,4 @@ bool qauthz_is_allowed_by_id(const char *authzid,
  const char *identity,
  Error **errp);
 
-#endif /* QAUTHZ_BASE_H__ */
-
+#endif /* QAUTHZ_BASE_H */
diff --git a/include/authz/list.h b/include/authz/list.h
index a7225a747c..49c2c6bf02 100644
--- a/include/authz/list.h
+++ b/include/authz/list.h
@@ -18,8 +18,8 @@
  *
  */
 
-#ifndef QAUTHZ_LIST_H__
-#define QAUTHZ_LIST_H__
+#ifndef QAUTHZ_LIST_H
+#define QAUTHZ_LIST_H
 
 #include "authz/base.h"
 

[Qemu-devel] [PATCH 7/8] Normalize header guard symbol definition.

[Markus Armbruster]

We commonly define the header guard symbol without an explicit value.
Normalize the exceptions.

Done with scripts/clean-header-guards.pl.

Signed-off-by: Markus Armbruster 
---
 hw/timer/m48t59-internal.h| 3 ++-
 include/disas/capstone.h  | 2 +-
 include/hw/scsi/emulation.h   | 2 +-
 include/qemu/stats64.h| 2 +-
 include/qemu/sys_membarrier.h | 2 +-
 include/qemu/systemd.h| 2 +-
 include/scsi/utils.h  | 2 +-
 include/ui/kbd-state.h| 3 ++-
 scsi/pr-helper.h  | 3 ++-
 target/i386/hvf/x86.h | 2 +-
 target/i386/hvf/x86_decode.h  | 2 +-
 target/i386/hvf/x86_descr.h   | 2 +-
 12 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/hw/timer/m48t59-internal.h b/hw/timer/m48t59-internal.h
index d0f0caf3c7..4d4f2a6fed 100644
--- a/hw/timer/m48t59-internal.h
+++ b/hw/timer/m48t59-internal.h
@@ -22,8 +22,9 @@
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  * THE SOFTWARE.
  */
+
 #ifndef HW_M48T59_INTERNAL_H
-#define HW_M48T59_INTERNAL_H 1
+#define HW_M48T59_INTERNAL_H
 
 #define M48T59_DEBUG 0
 
diff --git a/include/disas/capstone.h b/include/disas/capstone.h
index 84e214956d..e29068dd97 100644
--- a/include/disas/capstone.h
+++ b/include/disas/capstone.h
@@ -1,5 +1,5 @@
 #ifndef QEMU_CAPSTONE_H
-#define QEMU_CAPSTONE_H 1
+#define QEMU_CAPSTONE_H
 
 #ifdef CONFIG_CAPSTONE
 
diff --git a/include/hw/scsi/emulation.h b/include/hw/scsi/emulation.h
index 09fba1ff39..9521704326 100644
--- a/include/hw/scsi/emulation.h
+++ b/include/hw/scsi/emulation.h
@@ -1,5 +1,5 @@
 #ifndef HW_SCSI_EMULATION_H
-#define HW_SCSI_EMULATION_H 1
+#define HW_SCSI_EMULATION_H
 
 typedef struct SCSIBlockLimits {
 bool wsnz;
diff --git a/include/qemu/stats64.h b/include/qemu/stats64.h
index 4a357b3e9d..19a5ac4c56 100644
--- a/include/qemu/stats64.h
+++ b/include/qemu/stats64.h
@@ -10,7 +10,7 @@
  */
 
 #ifndef QEMU_STATS64_H
-#define QEMU_STATS64_H 1
+#define QEMU_STATS64_H
 
 #include "qemu/atomic.h"
 
diff --git a/include/qemu/sys_membarrier.h b/include/qemu/sys_membarrier.h
index 316e3dc4a2..b5bfa21d52 100644
--- a/include/qemu/sys_membarrier.h
+++ b/include/qemu/sys_membarrier.h
@@ -7,7 +7,7 @@
  */
 
 #ifndef QEMU_SYS_MEMBARRIER_H
-#define QEMU_SYS_MEMBARRIER_H 1
+#define QEMU_SYS_MEMBARRIER_H
 
 #ifdef CONFIG_MEMBARRIER
 /* Only block reordering at the compiler level in the performance-critical
diff --git a/include/qemu/systemd.h b/include/qemu/systemd.h
index e6a877e5c6..f0ea1266d5 100644
--- a/include/qemu/systemd.h
+++ b/include/qemu/systemd.h
@@ -11,7 +11,7 @@
  */
 
 #ifndef QEMU_SYSTEMD_H
-#define QEMU_SYSTEMD_H 1
+#define QEMU_SYSTEMD_H
 
 #define FIRST_SOCKET_ACTIVATION_FD 3 /* defined by systemd ABI */
 
diff --git a/include/scsi/utils.h b/include/scsi/utils.h
index 4b705f5e0f..9351b21ead 100644
--- a/include/scsi/utils.h
+++ b/include/scsi/utils.h
@@ -1,5 +1,5 @@
 #ifndef SCSI_UTILS_H
-#define SCSI_UTILS_H 1
+#define SCSI_UTILS_H
 
 #ifdef CONFIG_LINUX
 #include 
diff --git a/include/ui/kbd-state.h b/include/ui/kbd-state.h
index d87833553a..eb9067dd53 100644
--- a/include/ui/kbd-state.h
+++ b/include/ui/kbd-state.h
@@ -3,8 +3,9 @@
  * (at your option) any later version.  See the COPYING file in the
  * top-level directory.
  */
+
 #ifndef QEMU_UI_KBD_STATE_H
-#define QEMU_UI_KBD_STATE_H 1
+#define QEMU_UI_KBD_STATE_H
 
 #include "qapi/qapi-types-ui.h"
 
diff --git a/scsi/pr-helper.h b/scsi/pr-helper.h
index 096d1f1df6..e26e104ec7 100644
--- a/scsi/pr-helper.h
+++ b/scsi/pr-helper.h
@@ -23,8 +23,9 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  * IN THE SOFTWARE.
  */
+
 #ifndef QEMU_PR_HELPER_H
-#define QEMU_PR_HELPER_H 1
+#define QEMU_PR_HELPER_H
 
 #define PR_HELPER_CDB_SIZE 16
 #define PR_HELPER_SENSE_SIZE   96
diff --git a/target/i386/hvf/x86.h b/target/i386/hvf/x86.h
index 103ec0976c..c95d5b2116 100644
--- a/target/i386/hvf/x86.h
+++ b/target/i386/hvf/x86.h
@@ -17,7 +17,7 @@
  */
 
 #ifndef HVF_X86_H
-#define HVF_X86_H 1
+#define HVF_X86_H
 
 typedef struct x86_register {
 union {
diff --git a/target/i386/hvf/x86_decode.h b/target/i386/hvf/x86_decode.h
index ef4bcab310..bc574a7a44 100644
--- a/target/i386/hvf/x86_decode.h
+++ b/target/i386/hvf/x86_decode.h
@@ -16,7 +16,7 @@
  */
 
 #ifndef HVF_X86_DECODE_H
-#define HVF_X86_DECODE_H 1
+#define HVF_X86_DECODE_H
 
 #include "cpu.h"
 #include "x86.h"
diff --git a/target/i386/hvf/x86_descr.h b/target/i386/hvf/x86_descr.h
index 25a2b1731c..049ef9a417 100644
--- a/target/i386/hvf/x86_descr.h
+++ b/target/i386/hvf/x86_descr.h
@@ -17,7 +17,7 @@
  */
 
 #ifndef HVF_X86_DESCR_H
-#define HVF_X86_DESCR_H 1
+#define HVF_X86_DESCR_H
 
 #include "x86.h"
 
-- 
2.17.2

Re: [Qemu-devel] [PATCH v3 00/23] Add qemu_getrandom and ARMv8.5-RNG etc

[Daniel P . Berrangé]

On Thu, Mar 14, 2019 at 08:26:06PM -0700, Richard Henderson wrote:
> Changes since v2:
>   * Changes from review.
> - getrandom is not exclusive of /dev/urandom fallback.
> - vnc fails gracefully on crypto failure.
> - a great renaming.
>   * Drop the "nonblock" argument, as it's not deliverable from the backend.
>   * Propagate Error back through qemu_guest_getrandom.
>   * Add qemu_guest_getrandom_nofail to centralize "Argh! Death!".
>   * Convert hw/misc/
>   * Implement ppc darn.
>   * Implement x86 rdrand.
> 
> Changes since v1:
>   * Build crypto-obj-y for linux-user as well.
>   * Several patches to tidy crypto/random-platform.c.
>   * Use getrandom(2) in crypto/random-platform.c.
>   * Use qcrypto_random_bytes in ui/vnc.c.
>   * In qemu_getrandom:
> - Use g_rand_int instead of srand48.
> - Use qcrypto_random_bytes instead of getrandom directly.
> 
> 
> r~
> 
> 
> Richard Henderson (23):
>   crypto: Merge crypto-obj-y into libqemuutil.a
>   crypto: Reverse code blocks in random-platform.c
>   crypto: Do not fail for EINTR during qcrypto_random_bytes
>   crypto: Use O_CLOEXEC in qcrypto_random_init
>   crypto: Use getrandom for qcrypto_random_bytes
>   crypto: Change the qcrypto_random_bytes buffer type to void*

Once the full series is acked, I'm fine if you want to do a
pull request with the whole series. If not, I'll take the
crypto patches into my pending queue.

>   ui/vnc: Split out authentication_failure
>   ui/vnc: Use gcrypto_random_bytes for start_auth_vnc
>   util: Add qemu_guest_getrandom and associated routines
>   cpus: Initialize pseudo-random seeds for all guest cpus
>   linux-user: Initialize pseudo-random seeds for all guest cpus
>   linux-user: Call qcrypto_init if not using -seed
>   linux-user: Use qemu_guest_getrandom_nofail for AT_RANDOM
>   linux-user/aarch64: Use qemu_guest_getrandom for PAUTH keys
>   linux-user: Remove srand call
>   aspeed/scu: Use qemu_guest_getrandom_nofail
>   hw/misc/nrf51_rng: Use qemu_guest_getrandom_nofail
>   hw/misc/bcm2835_rng: Use qemu_guest_getrandom_nofail
>   hw/misc/exynos4210_rng: Use qemu_guest_getrandom
>   target/arm: Put all PAC keys into a structure
>   target/arm: Implement ARMv8.5-RNG
>   target/ppc: Use qemu_guest_getrandom for DARN
>   target/i386: Implement CPUID_EXT_RDRAND

Regards,
Daniel
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Re: [Qemu-devel] [PATCH] ati-vga: i2c fix

[BALATON Zoltan]

On Fri, 15 Mar 2019, Gerd Hoffmann wrote:

On Thu, Mar 14, 2019 at 08:11:21PM +0100, BALATON Zoltan wrote:

On Thu, 14 Mar 2019, Gerd Hoffmann wrote:

gets radeonfb going for me, on top of your i2c patches.
---
@@ -512,15 +531,15 @@ static void ati_mm_write(void *opaque, hwaddr addr,
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
break;
}
-s->regs.gpio_vga_ddc = data & 0xf000f;
-if (data & BIT(17)) {
-s->regs.gpio_monid |= !!(data & BIT(1)) << 9;
-bitbang_i2c_set(s->bbi2c, BITBANG_I2C_SCL, (data & BIT(1)) != 0);
-}
-if (data & BIT(16)) {
-s->regs.gpio_monid |= bitbang_i2c_set(s->bbi2c, BITBANG_I2C_SDA,
-  data & BIT(0)) << 8;
+#if 0
+s->regs.gpio_vga_ddc = ati_i2c(s->bbi2c, data);
+#endif


Thanks, I'll try and merge this. What's this #if 0 line?


Avoid the monitor show up on both vga ...



Regards,
BALATON Zoltan


+break;
+case GPIO_DVI_DDC:
+if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
+break;
}
+s->regs.gpio_dvi_ddc = ati_i2c(s->bbi2c, data);


... and dvi.

A more correct model would probably be to create two i2c busses for
that, then hook up the ddc to one of them (possibly depending on a
config option).


Isn't it enough to only emulate the DVI port DDC then? I've sent an 
updated patch as v2 that also cleans up the bitbang_i2c.h header 
inclusion. (I've checked that Linux first checks DVI then VGA so my 
original patch may have also worked if the copy paste error is fixed and 
updated the right reg bits instead of gpio_monid. But let's go with the 
default and use a DVI port, then we likely not need VGA as we don't have 
a mointor there.)


Regards,
BALATON Zoltan