Re: [PATCH 05/12] hw/riscv: Move sifive_clint model to hw/intc

[Alistair Francis]

On Thu, Sep 3, 2020 at 3:45 AM Bin Meng  wrote:
>
> From: Bin Meng 
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_clint model to hw/intc directory.
>
> Signed-off-by: Bin Meng 

Reviewed-by: Alistair Francis 

Alistair

> ---
>
>  include/hw/{riscv => intc}/sifive_clint.h | 0
>  hw/{riscv => intc}/sifive_clint.c | 2 +-
>  hw/riscv/microchip_pfsoc.c| 2 +-
>  hw/riscv/sifive_e.c   | 2 +-
>  hw/riscv/sifive_u.c   | 2 +-
>  hw/riscv/spike.c  | 2 +-
>  hw/riscv/virt.c   | 2 +-
>  hw/intc/Kconfig   | 3 +++
>  hw/intc/meson.build   | 1 +
>  hw/riscv/Kconfig  | 5 +
>  hw/riscv/meson.build  | 1 -
>  11 files changed, 15 insertions(+), 7 deletions(-)
>  rename include/hw/{riscv => intc}/sifive_clint.h (100%)
>  rename hw/{riscv => intc}/sifive_clint.c (99%)
>
> diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/intc/sifive_clint.h
> similarity index 100%
> rename from include/hw/riscv/sifive_clint.h
> rename to include/hw/intc/sifive_clint.h
> diff --git a/hw/riscv/sifive_clint.c b/hw/intc/sifive_clint.c
> similarity index 99%
> rename from hw/riscv/sifive_clint.c
> rename to hw/intc/sifive_clint.c
> index fa1ddf2..0f41e5e 100644
> --- a/hw/riscv/sifive_clint.c
> +++ b/hw/intc/sifive_clint.c
> @@ -26,7 +26,7 @@
>  #include "hw/sysbus.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/qdev-properties.h"
> -#include "hw/riscv/sifive_clint.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "qemu/timer.h"
>
>  static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index da6bd29..131eea1 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -48,9 +48,9 @@
>  #include "hw/misc/unimp.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/sifive_plic.h"
>  #include "hw/riscv/microchip_pfsoc.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "sysemu/sysemu.h"
>
>  /*
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 7f43ed9..3bdb16e 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -40,10 +40,10 @@
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_plic.h"
> -#include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_e.h"
>  #include "hw/riscv/boot.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "hw/misc/sifive_e_prci.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 7997537..7187d1a 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -47,10 +47,10 @@
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_plic.h"
> -#include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_u.h"
>  #include "hw/riscv/boot.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "chardev/char.h"
>  #include "net/eth.h"
>  #include "sysemu/arch_init.h"
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index b54a396..59d9d87 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -33,10 +33,10 @@
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_htif.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/spike.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/numa.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
>  #include "sysemu/device_tree.h"
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index c67a910..bce2020 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -31,11 +31,11 @@
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_plic.h"
> -#include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/sifive_test.h"
>  #include "hw/riscv/virt.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/numa.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
>  #include "sysemu/device_tree.h"
> diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
> index 2ae1e89..f499d0f 100644
> --- a/hw/intc/Kconfig
> +++ b/hw/intc/Kconfig
> @@ -67,3 +67,6 @@ config RX_ICU
>
>  config LOONGSON_LIOINTC
>  bool
> +
> +config SIFIVE_CLINT
> +bool
> diff --git a/hw/intc/meson.build b/hw/intc/meson.build
> index c16f7f0..1e20daa 100644
> --- a/hw/intc/meson.build
> +++ b/hw/intc/meson.build
> @@ -47,6 +47,7 @@ specific_ss.add(when: 'CONFIG_RX_ICU', if_true: 
> files('rx_icu.c'))
>  specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic

Re: [PATCH 06/12] hw/riscv: Move sifive_plic model to hw/intc

[Alistair Francis]

On Thu, Sep 3, 2020 at 3:44 AM Bin Meng  wrote:
>
> From: Bin Meng 
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_plic model to hw/intc directory.
>
> Signed-off-by: Bin Meng 

Reviewed-by: Alistair Francis 

Alistair

> ---
>
>  {include/hw/riscv => hw/intc}/sifive_plic.h | 0
>  hw/{riscv => intc}/sifive_plic.c| 2 +-
>  hw/riscv/microchip_pfsoc.c  | 2 +-
>  hw/riscv/sifive_e.c | 2 +-
>  hw/riscv/sifive_u.c | 2 +-
>  hw/riscv/virt.c | 2 +-
>  hw/intc/Kconfig | 3 +++
>  hw/intc/meson.build | 1 +
>  hw/riscv/Kconfig| 5 +
>  hw/riscv/meson.build| 1 -
>  10 files changed, 14 insertions(+), 6 deletions(-)
>  rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
>  rename hw/{riscv => intc}/sifive_plic.c (99%)
>
> diff --git a/include/hw/riscv/sifive_plic.h b/hw/intc/sifive_plic.h
> similarity index 100%
> rename from include/hw/riscv/sifive_plic.h
> rename to hw/intc/sifive_plic.h
> diff --git a/hw/riscv/sifive_plic.c b/hw/intc/sifive_plic.c
> similarity index 99%
> rename from hw/riscv/sifive_plic.c
> rename to hw/intc/sifive_plic.c
> index 11ef147..af611f8 100644
> --- a/hw/riscv/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -27,9 +27,9 @@
>  #include "hw/pci/msi.h"
>  #include "hw/boards.h"
>  #include "hw/qdev-properties.h"
> +#include "hw/intc/sifive_plic.h"
>  #include "target/riscv/cpu.h"
>  #include "sysemu/sysemu.h"
> -#include "hw/riscv/sifive_plic.h"
>
>  #define RISCV_DEBUG_PLIC 0
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 131eea1..4627179 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -48,9 +48,9 @@
>  #include "hw/misc/unimp.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_plic.h"
>  #include "hw/riscv/microchip_pfsoc.h"
>  #include "hw/intc/sifive_clint.h"
> +#include "hw/intc/sifive_plic.h"
>  #include "sysemu/sysemu.h"
>
>  /*
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 3bdb16e..0ddcf15 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -39,11 +39,11 @@
>  #include "hw/misc/unimp.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_plic.h"
>  #include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_e.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/intc/sifive_clint.h"
> +#include "hw/intc/sifive_plic.h"
>  #include "hw/misc/sifive_e_prci.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 7187d1a..faca2e8 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -46,11 +46,11 @@
>  #include "hw/misc/unimp.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_plic.h"
>  #include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_u.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/intc/sifive_clint.h"
> +#include "hw/intc/sifive_plic.h"
>  #include "chardev/char.h"
>  #include "net/eth.h"
>  #include "sysemu/arch_init.h"
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index bce2020..0caab8e 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -30,12 +30,12 @@
>  #include "hw/char/serial.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_plic.h"
>  #include "hw/riscv/sifive_test.h"
>  #include "hw/riscv/virt.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/numa.h"
>  #include "hw/intc/sifive_clint.h"
> +#include "hw/intc/sifive_plic.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
>  #include "sysemu/device_tree.h"
> diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
> index f499d0f..d079540 100644
> --- a/hw/intc/Kconfig
> +++ b/hw/intc/Kconfig
> @@ -70,3 +70,6 @@ config LOONGSON_LIOINTC
>
>  config SIFIVE_CLINT
>  bool
> +
> +config SIFIVE_PLIC
> +bool
> diff --git a/hw/intc/meson.build b/hw/intc/meson.build
> index 1e20daa..3f82cc2 100644
> --- a/hw/intc/meson.build
> +++ b/hw/intc/meson.build
> @@ -48,6 +48,7 @@ specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: 
> files('s390_flic.c'))
>  specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: 
> files('s390_flic_kvm.c'))
>  specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
>  specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: 
> files('sifive_clint.c'))
> +specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
>  specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
>  specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
>  specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
> diff --git a/hw/ris

Re: [PATCH 07/12] hw/riscv: Move riscv_htif model to hw/char

[Alistair Francis]

On Thu, Sep 3, 2020 at 3:48 AM Bin Meng  wrote:
>
> From: Bin Meng 
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move riscv_htif model to hw/char directory.
>
> Signed-off-by: Bin Meng 

Reviewed-by: Alistair Francis 

Alistair

> ---
>
>  include/hw/{riscv => char}/riscv_htif.h | 0
>  hw/{riscv => char}/riscv_htif.c | 2 +-
>  hw/riscv/spike.c| 2 +-
>  hw/char/Kconfig | 3 +++
>  hw/char/meson.build | 1 +
>  hw/riscv/Kconfig| 3 ---
>  hw/riscv/meson.build| 1 -
>  7 files changed, 6 insertions(+), 6 deletions(-)
>  rename include/hw/{riscv => char}/riscv_htif.h (100%)
>  rename hw/{riscv => char}/riscv_htif.c (99%)
>
> diff --git a/include/hw/riscv/riscv_htif.h b/include/hw/char/riscv_htif.h
> similarity index 100%
> rename from include/hw/riscv/riscv_htif.h
> rename to include/hw/char/riscv_htif.h
> diff --git a/hw/riscv/riscv_htif.c b/hw/char/riscv_htif.c
> similarity index 99%
> rename from hw/riscv/riscv_htif.c
> rename to hw/char/riscv_htif.c
> index ca87a5c..ba1af1c 100644
> --- a/hw/riscv/riscv_htif.c
> +++ b/hw/char/riscv_htif.c
> @@ -24,10 +24,10 @@
>  #include "qapi/error.h"
>  #include "qemu/log.h"
>  #include "hw/sysbus.h"
> +#include "hw/char/riscv_htif.h"
>  #include "hw/char/serial.h"
>  #include "chardev/char.h"
>  #include "chardev/char-fe.h"
> -#include "hw/riscv/riscv_htif.h"
>  #include "qemu/timer.h"
>  #include "qemu/error-report.h"
>
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 59d9d87..3fd152a 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -31,11 +31,11 @@
>  #include "hw/loader.h"
>  #include "hw/sysbus.h"
>  #include "target/riscv/cpu.h"
> -#include "hw/riscv/riscv_htif.h"
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/spike.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/numa.h"
> +#include "hw/char/riscv_htif.h"
>  #include "hw/intc/sifive_clint.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
> diff --git a/hw/char/Kconfig b/hw/char/Kconfig
> index 1d64555..91da92f 100644
> --- a/hw/char/Kconfig
> +++ b/hw/char/Kconfig
> @@ -1,6 +1,9 @@
>  config ESCC
>  bool
>
> +config HTIF
> +bool
> +
>  config PARALLEL
>  bool
>  default y
> diff --git a/hw/char/meson.build b/hw/char/meson.build
> index ae27932..3db623e 100644
> --- a/hw/char/meson.build
> +++ b/hw/char/meson.build
> @@ -34,6 +34,7 @@ softmmu_ss.add(when: 'CONFIG_SH4', if_true: 
> files('sh_serial.c'))
>  softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: 
> files('stm32f2xx_usart.c'))
>  softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: 
> files('mchp_pfsoc_mmuart.c'))
>
> +specific_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c'))
>  specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: 
> files('terminal3270.c'))
>  specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c'))
>  specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_vty.c'))
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 23b7027..a0e256c 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -1,6 +1,3 @@
> -config HTIF
> -bool
> -
>  config HART
>  bool
>
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index 535a142..619bf80 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -8,7 +8,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: 
> files('sifive_test.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
> -riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
>  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
>  riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: 
> files('microchip_pfsoc.c'))
>
> --
> 2.7.4
>
>

Re: [PATCH 08/12] hw/riscv: Move sifive_uart model to hw/char

[Alistair Francis]

On Thu, Sep 3, 2020 at 3:48 AM Bin Meng  wrote:
>
> From: Bin Meng 
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_uart model to hw/char directory.
>
> Signed-off-by: Bin Meng 

Reviewed-by: Alistair Francis 

Alistair

> ---
>
>  include/hw/{riscv => char}/sifive_uart.h | 0
>  hw/{riscv => char}/sifive_uart.c | 2 +-
>  hw/riscv/sifive_e.c  | 2 +-
>  hw/riscv/sifive_u.c  | 2 +-
>  hw/char/Kconfig  | 3 +++
>  hw/char/meson.build  | 1 +
>  hw/riscv/Kconfig | 2 ++
>  hw/riscv/meson.build | 1 -
>  8 files changed, 9 insertions(+), 4 deletions(-)
>  rename include/hw/{riscv => char}/sifive_uart.h (100%)
>  rename hw/{riscv => char}/sifive_uart.c (99%)
>
> diff --git a/include/hw/riscv/sifive_uart.h b/include/hw/char/sifive_uart.h
> similarity index 100%
> rename from include/hw/riscv/sifive_uart.h
> rename to include/hw/char/sifive_uart.h
> diff --git a/hw/riscv/sifive_uart.c b/hw/char/sifive_uart.c
> similarity index 99%
> rename from hw/riscv/sifive_uart.c
> rename to hw/char/sifive_uart.c
> index 9350482..3a00ba7 100644
> --- a/hw/riscv/sifive_uart.c
> +++ b/hw/char/sifive_uart.c
> @@ -24,7 +24,7 @@
>  #include "chardev/char-fe.h"
>  #include "hw/hw.h"
>  #include "hw/irq.h"
> -#include "hw/riscv/sifive_uart.h"
> +#include "hw/char/sifive_uart.h"
>
>  /*
>   * Not yet implemented:
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 0ddcf15..40bbf53 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -39,9 +39,9 @@
>  #include "hw/misc/unimp.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_e.h"
>  #include "hw/riscv/boot.h"
> +#include "hw/char/sifive_uart.h"
>  #include "hw/intc/sifive_clint.h"
>  #include "hw/intc/sifive_plic.h"
>  #include "hw/misc/sifive_e_prci.h"
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index faca2e8..4f12a93 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -46,9 +46,9 @@
>  #include "hw/misc/unimp.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_u.h"
>  #include "hw/riscv/boot.h"
> +#include "hw/char/sifive_uart.h"
>  #include "hw/intc/sifive_clint.h"
>  #include "hw/intc/sifive_plic.h"
>  #include "chardev/char.h"
> diff --git a/hw/char/Kconfig b/hw/char/Kconfig
> index 91da92f..939bc44 100644
> --- a/hw/char/Kconfig
> +++ b/hw/char/Kconfig
> @@ -58,3 +58,6 @@ config AVR_USART
>
>  config MCHP_PFSOC_MMUART
>  bool
> +
> +config SIFIVE_UART
> +bool
> diff --git a/hw/char/meson.build b/hw/char/meson.build
> index 3db623e..196ac91 100644
> --- a/hw/char/meson.build
> +++ b/hw/char/meson.build
> @@ -30,6 +30,7 @@ softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: 
> files('exynos4210_uart.c'))
>  softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_uart.c'))
>  softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c'))
>  softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))
> +softmmu_ss.add(when: 'CONFIG_SIFIVE_UART', if_true: files('sifive_uart.c'))
>  softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
>  softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: 
> files('stm32f2xx_usart.c'))
>  softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: 
> files('mchp_pfsoc_mmuart.c'))
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index a0e256c..a046157 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -15,6 +15,7 @@ config SIFIVE_E
>  select SIFIVE_CLINT
>  select SIFIVE_GPIO
>  select SIFIVE_PLIC
> +select SIFIVE_UART
>  select SIFIVE_E_PRCI
>  select UNIMP
>
> @@ -27,6 +28,7 @@ config SIFIVE_U
>  select SIFIVE_GPIO
>  select SIFIVE_PDMA
>  select SIFIVE_PLIC
> +select SIFIVE_UART
>  select SIFIVE_U_OTP
>  select SIFIVE_U_PRCI
>  select UNIMP
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index 619bf80..da32148 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -5,7 +5,6 @@ riscv_ss.add(when: 'CONFIG_HART', if_true: 
> files('riscv_hart.c'))
>  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
>  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
>  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
> --
> 2.7.4
>
>

[PATCH] qom: Remove ParentClassType argument from OBJECT_DECLARE_SIMPLE_TYPE

[Eduardo Habkost]

The requirement to specify the parent class type makes the macro
harder to use and easy to misuse (by indicating the wrong parent
class type).

Simplify the macro by just not declaring any class struct,
allowing us to remove the class_size field from the TypeInfo
variables for those types.

Signed-off-by: Eduardo Habkost 
---
This patch is based on the machine-next branch, and can be
fetched from the git branch at:
  https://github.com/ehabkost/qemu-hacks work/qom-simplify-declare-simple-type
---
Cc: "Daniel P. Berrangé" 
Cc: "Marc-André Lureau" 
Cc: "Michael S. Tsirkin" 
Cc: Paolo Bonzini 
Cc: Eduardo Habkost 
Cc: Gerd Hoffmann 
Cc: qemu-devel@nongnu.org
---
 include/authz/list.h|  2 +-
 include/authz/listfile.h|  2 +-
 include/authz/pamacct.h |  2 +-
 include/authz/simple.h  |  2 +-
 include/crypto/secret_keyring.h |  2 +-
 include/io/dns-resolver.h   |  2 +-
 include/io/net-listener.h   |  2 +-
 include/qom/object.h| 16 
 include/sysemu/vhost-user-backend.h |  2 +-
 authz/list.c|  1 -
 authz/listfile.c|  1 -
 authz/pamacct.c |  1 -
 authz/simple.c  |  1 -
 backends/dbus-vmstate.c |  3 +--
 backends/vhost-user.c   |  1 -
 crypto/secret_keyring.c |  1 -
 io/dns-resolver.c   |  1 -
 io/net-listener.c   |  1 -
 ui/input-barrier.c  |  3 +--
 ui/input-linux.c|  3 +--
 20 files changed, 19 insertions(+), 30 deletions(-)

diff --git a/include/authz/list.h b/include/authz/list.h
index 5676bb375c..c5eda0f1bf 100644
--- a/include/authz/list.h
+++ b/include/authz/list.h
@@ -28,7 +28,7 @@
 #define TYPE_QAUTHZ_LIST "authz-list"
 
 OBJECT_DECLARE_SIMPLE_TYPE(QAuthZList, qauthz_list,
-   QAUTHZ_LIST, QAuthZClass)
+   QAUTHZ_LIST)
 
 
 
diff --git a/include/authz/listfile.h b/include/authz/listfile.h
index b491227bbe..83d78cfa50 100644
--- a/include/authz/listfile.h
+++ b/include/authz/listfile.h
@@ -28,7 +28,7 @@
 #define TYPE_QAUTHZ_LIST_FILE "authz-list-file"
 
 OBJECT_DECLARE_SIMPLE_TYPE(QAuthZListFile, qauthz_list_file,
-   QAUTHZ_LIST_FILE, QAuthZClass)
+   QAUTHZ_LIST_FILE)
 
 
 
diff --git a/include/authz/pamacct.h b/include/authz/pamacct.h
index 7804853ddf..18087cee20 100644
--- a/include/authz/pamacct.h
+++ b/include/authz/pamacct.h
@@ -28,7 +28,7 @@
 #define TYPE_QAUTHZ_PAM "authz-pam"
 
 OBJECT_DECLARE_SIMPLE_TYPE(QAuthZPAM, qauthz_pam,
-   QAUTHZ_PAM, QAuthZClass)
+   QAUTHZ_PAM)
 
 
 
diff --git a/include/authz/simple.h b/include/authz/simple.h
index 346fcb0c6c..d3ed05b36f 100644
--- a/include/authz/simple.h
+++ b/include/authz/simple.h
@@ -27,7 +27,7 @@
 #define TYPE_QAUTHZ_SIMPLE "authz-simple"
 
 OBJECT_DECLARE_SIMPLE_TYPE(QAuthZSimple, qauthz_simple,
-   QAUTHZ_SIMPLE, QAuthZClass)
+   QAUTHZ_SIMPLE)
 
 
 
diff --git a/include/crypto/secret_keyring.h b/include/crypto/secret_keyring.h
index 73d2a8f501..803f3fc28b 100644
--- a/include/crypto/secret_keyring.h
+++ b/include/crypto/secret_keyring.h
@@ -27,7 +27,7 @@
 
 #define TYPE_QCRYPTO_SECRET_KEYRING "secret_keyring"
 OBJECT_DECLARE_SIMPLE_TYPE(QCryptoSecretKeyring, qcrypto_secret_keyring,
-   QCRYPTO_SECRET_KEYRING, QCryptoSecretCommonClass)
+   QCRYPTO_SECRET_KEYRING)
 
 
 struct QCryptoSecretKeyring {
diff --git a/include/io/dns-resolver.h b/include/io/dns-resolver.h
index e248fba5bd..9d14a8d98f 100644
--- a/include/io/dns-resolver.h
+++ b/include/io/dns-resolver.h
@@ -27,7 +27,7 @@
 
 #define TYPE_QIO_DNS_RESOLVER "qio-dns-resolver"
 OBJECT_DECLARE_SIMPLE_TYPE(QIODNSResolver, qio_dns_resolver,
-   QIO_DNS_RESOLVER, ObjectClass)
+   QIO_DNS_RESOLVER)
 
 
 /**
diff --git a/include/io/net-listener.h b/include/io/net-listener.h
index 60fad29ff4..8145962fbb 100644
--- a/include/io/net-listener.h
+++ b/include/io/net-listener.h
@@ -26,7 +26,7 @@
 
 #define TYPE_QIO_NET_LISTENER "qio-net-listener"
 OBJECT_DECLARE_SIMPLE_TYPE(QIONetListener, qio_net_listener,
-   QIO_NET_LISTENER, ObjectClass)
+   QIO_NET_LISTENER)
 
 
 typedef void (*QIONetListenerClientFunc)(QIONetListener *listener,
diff --git a/include/qom/object.h b/include/qom/object.h
index 056f67ab3b..4a23fed586 100644
--- a/include/qom/object.h
+++ b/include/qom/object.h
@@ -639,19 +639,19 @@ struct Object
  * @InstanceType: instance struct name
  * @module_obj_name: the object name in lowercase with underscore separators
  * @MODULE_OBJ_NAME: the object name in uppercase with underscore separators
- * @ParentClassType: class struct name of parent type
  *
- * This does the same as 

Re: [PATCH 09/12] hw/riscv: Move sifive_test model to hw/misc

[Alistair Francis]

On Thu, Sep 3, 2020 at 3:46 AM Bin Meng  wrote:
>
> From: Bin Meng 
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_test model to hw/misc directory.
>
> Signed-off-by: Bin Meng 

Reviewed-by: Alistair Francis 

Alistair

> ---
>
>  include/hw/{riscv => misc}/sifive_test.h | 0
>  hw/{riscv => misc}/sifive_test.c | 2 +-
>  hw/riscv/virt.c  | 2 +-
>  hw/misc/Kconfig  | 3 +++
>  hw/misc/meson.build  | 1 +
>  hw/riscv/Kconfig | 1 +
>  hw/riscv/meson.build | 1 -
>  7 files changed, 7 insertions(+), 3 deletions(-)
>  rename include/hw/{riscv => misc}/sifive_test.h (100%)
>  rename hw/{riscv => misc}/sifive_test.c (98%)
>
> diff --git a/include/hw/riscv/sifive_test.h b/include/hw/misc/sifive_test.h
> similarity index 100%
> rename from include/hw/riscv/sifive_test.h
> rename to include/hw/misc/sifive_test.h
> diff --git a/hw/riscv/sifive_test.c b/hw/misc/sifive_test.c
> similarity index 98%
> rename from hw/riscv/sifive_test.c
> rename to hw/misc/sifive_test.c
> index 0c78fb2..45d9399 100644
> --- a/hw/riscv/sifive_test.c
> +++ b/hw/misc/sifive_test.c
> @@ -25,7 +25,7 @@
>  #include "qemu/module.h"
>  #include "sysemu/runstate.h"
>  #include "hw/hw.h"
> -#include "hw/riscv/sifive_test.h"
> +#include "hw/misc/sifive_test.h"
>
>  static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int 
> size)
>  {
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 0caab8e..41bd2f3 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -30,12 +30,12 @@
>  #include "hw/char/serial.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_test.h"
>  #include "hw/riscv/virt.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/numa.h"
>  #include "hw/intc/sifive_clint.h"
>  #include "hw/intc/sifive_plic.h"
> +#include "hw/misc/sifive_test.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
>  #include "sysemu/device_tree.h"
> diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
> index fa3d0f4..3185456 100644
> --- a/hw/misc/Kconfig
> +++ b/hw/misc/Kconfig
> @@ -134,6 +134,9 @@ config MAC_VIA
>  config AVR_POWER
>  bool
>
> +config SIFIVE_TEST
> +bool
> +
>  config SIFIVE_E_PRCI
>  bool
>
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index 018a88c..bd24132 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -22,6 +22,7 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: 
> files('arm11scu.c'))
>  softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
>
>  # RISC-V devices
> +softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
>  softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: 
> files('sifive_e_prci.c'))
>  softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
>  softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: 
> files('sifive_u_prci.c'))
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index a046157..8e07100 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -61,6 +61,7 @@ config RISCV_VIRT
>  select SIFIVE
>  select SIFIVE_CLINT
>  select SIFIVE_PLIC
> +select SIFIVE_TEST
>
>  config MICROCHIP_PFSOC
>  bool
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index da32148..3cf9380 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c'))
>  riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
>  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
>  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
>  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
> --
> 2.7.4
>
>

Re: [PATCH 10/12] hw/riscv: Always build riscv_hart.c

[Alistair Francis]

On Thu, Sep 3, 2020 at 3:42 AM Bin Meng  wrote:
>
> From: Bin Meng 
>
> Every RISC-V machine needs riscv_hart hence there is no need to
> have a dedicated Kconfig option for it. Drop the Kconfig option
> and always build riscv_hart.c.
>
> Signed-off-by: Bin Meng 

Reviewed-by: Alistair Francis 

Alistair

> ---
>
>  hw/riscv/Kconfig | 9 -
>  hw/riscv/meson.build | 2 +-
>  2 files changed, 1 insertion(+), 10 deletions(-)
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 8e07100..7d017bc 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -1,6 +1,3 @@
> -config HART
> -bool
> -
>  config IBEX
>  bool
>
> @@ -10,7 +7,6 @@ config SIFIVE
>
>  config SIFIVE_E
>  bool
> -select HART
>  select SIFIVE
>  select SIFIVE_CLINT
>  select SIFIVE_GPIO
> @@ -22,7 +18,6 @@ config SIFIVE_E
>  config SIFIVE_U
>  bool
>  select CADENCE
> -select HART
>  select SIFIVE
>  select SIFIVE_CLINT
>  select SIFIVE_GPIO
> @@ -35,7 +30,6 @@ config SIFIVE_U
>
>  config SPIKE
>  bool
> -select HART
>  select HTIF
>  select SIFIVE
>  select SIFIVE_CLINT
> @@ -44,7 +38,6 @@ config SPIKE
>  config OPENTITAN
>  bool
>  select IBEX
> -select HART
>  select UNIMP
>
>  config RISCV_VIRT
> @@ -52,7 +45,6 @@ config RISCV_VIRT
>  imply PCI_DEVICES
>  imply TEST_DEVICES
>  select PCI
> -select HART
>  select SERIAL
>  select GOLDFISH_RTC
>  select VIRTIO_MMIO
> @@ -65,7 +57,6 @@ config RISCV_VIRT
>
>  config MICROCHIP_PFSOC
>  bool
> -select HART
>  select SIFIVE
>  select SIFIVE_CLINT
>  select UNIMP
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index 3cf9380..dbedf9b 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -1,7 +1,7 @@
>  riscv_ss = ss.source_set()
>  riscv_ss.add(files('boot.c'))
>  riscv_ss.add(files('numa.c'))
> -riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
> +riscv_ss.add(files('riscv_hart.c'))
>  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
>  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
> --
> 2.7.4
>
>

Re: [PATCH 11/12] hw/riscv: Drop CONFIG_SIFIVE

[Alistair Francis]

On Thu, Sep 3, 2020 at 3:49 AM Bin Meng  wrote:
>
> From: Bin Meng 
>
> The name SIFIVE is too vague to convey the required component of
> MSI_NONBROKEN. Let's drop the option, and select MSI_NONBROKEN in
> each machine instead.
>
> Signed-off-by: Bin Meng 

Reviewed-by: Alistair Francis 

Alistair

> ---
>
>  hw/riscv/Kconfig | 14 +-
>  1 file changed, 5 insertions(+), 9 deletions(-)
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 7d017bc..e152fdc 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -1,13 +1,9 @@
>  config IBEX
>  bool
>
> -config SIFIVE
> -bool
> -select MSI_NONBROKEN
> -
>  config SIFIVE_E
>  bool
> -select SIFIVE
> +select MSI_NONBROKEN
>  select SIFIVE_CLINT
>  select SIFIVE_GPIO
>  select SIFIVE_PLIC
> @@ -18,7 +14,7 @@ config SIFIVE_E
>  config SIFIVE_U
>  bool
>  select CADENCE
> -select SIFIVE
> +select MSI_NONBROKEN
>  select SIFIVE_CLINT
>  select SIFIVE_GPIO
>  select SIFIVE_PDMA
> @@ -31,7 +27,7 @@ config SIFIVE_U
>  config SPIKE
>  bool
>  select HTIF
> -select SIFIVE
> +select MSI_NONBROKEN
>  select SIFIVE_CLINT
>  select SIFIVE_PLIC
>
> @@ -44,20 +40,20 @@ config RISCV_VIRT
>  bool
>  imply PCI_DEVICES
>  imply TEST_DEVICES
> +select MSI_NONBROKEN
>  select PCI
>  select SERIAL
>  select GOLDFISH_RTC
>  select VIRTIO_MMIO
>  select PCI_EXPRESS_GENERIC_BRIDGE
>  select PFLASH_CFI01
> -select SIFIVE
>  select SIFIVE_CLINT
>  select SIFIVE_PLIC
>  select SIFIVE_TEST
>
>  config MICROCHIP_PFSOC
>  bool
> -select SIFIVE
> +select MSI_NONBROKEN
>  select SIFIVE_CLINT
>  select UNIMP
>  select MCHP_PFSOC_MMUART
> --
> 2.7.4
>
>

Re: [PATCH 12/12] hw/riscv: Sort the Kconfig options in alphabetical order

[Alistair Francis]

On Thu, Sep 3, 2020 at 3:43 AM Bin Meng  wrote:
>
> From: Bin Meng 
>
> At present the Kconfig file is in disorder. Let's sort the options.
>
> Signed-off-by: Bin Meng 

Reviewed-by: Alistair Francis 

Alistair

>
> ---
>
>  hw/riscv/Kconfig | 58 
> 
>  1 file changed, 29 insertions(+), 29 deletions(-)
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index e152fdc..2df978f 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -1,36 +1,16 @@
>  config IBEX
>  bool
>
> -config SIFIVE_E
> -bool
> -select MSI_NONBROKEN
> -select SIFIVE_CLINT
> -select SIFIVE_GPIO
> -select SIFIVE_PLIC
> -select SIFIVE_UART
> -select SIFIVE_E_PRCI
> -select UNIMP
> -
> -config SIFIVE_U
> +config MICROCHIP_PFSOC
>  bool
> -select CADENCE
> +select CADENCE_SDHCI
> +select MCHP_PFSOC_MMUART
>  select MSI_NONBROKEN
>  select SIFIVE_CLINT
> -select SIFIVE_GPIO
>  select SIFIVE_PDMA
>  select SIFIVE_PLIC
> -select SIFIVE_UART
> -select SIFIVE_U_OTP
> -select SIFIVE_U_PRCI
>  select UNIMP
>
> -config SPIKE
> -bool
> -select HTIF
> -select MSI_NONBROKEN
> -select SIFIVE_CLINT
> -select SIFIVE_PLIC
> -
>  config OPENTITAN
>  bool
>  select IBEX
> @@ -40,23 +20,43 @@ config RISCV_VIRT
>  bool
>  imply PCI_DEVICES
>  imply TEST_DEVICES
> +select GOLDFISH_RTC
>  select MSI_NONBROKEN
>  select PCI
> -select SERIAL
> -select GOLDFISH_RTC
> -select VIRTIO_MMIO
>  select PCI_EXPRESS_GENERIC_BRIDGE
>  select PFLASH_CFI01
> +select SERIAL
>  select SIFIVE_CLINT
>  select SIFIVE_PLIC
>  select SIFIVE_TEST
> +select VIRTIO_MMIO
>
> -config MICROCHIP_PFSOC
> +config SIFIVE_E
>  bool
>  select MSI_NONBROKEN
>  select SIFIVE_CLINT
> +select SIFIVE_GPIO
> +select SIFIVE_PLIC
> +select SIFIVE_UART
> +select SIFIVE_E_PRCI
>  select UNIMP
> -select MCHP_PFSOC_MMUART
> +
> +config SIFIVE_U
> +bool
> +select CADENCE
> +select MSI_NONBROKEN
> +select SIFIVE_CLINT
> +select SIFIVE_GPIO
>  select SIFIVE_PDMA
>  select SIFIVE_PLIC
> -select CADENCE_SDHCI
> +select SIFIVE_UART
> +select SIFIVE_U_OTP
> +select SIFIVE_U_PRCI
> +select UNIMP
> +
> +config SPIKE
> +bool
> +select HTIF
> +select MSI_NONBROKEN
> +select SIFIVE_CLINT
> +select SIFIVE_PLIC
> --
> 2.7.4
>
>

Re: [PATCH v3 05/16] hw/char: Add Microchip PolarFire SoC MMUART emulation

[Alistair Francis]

On Mon, Aug 31, 2020 at 6:44 PM Bin Meng  wrote:
>
> From: Bin Meng 
>
> Microchip PolarFire SoC MMUART is ns16550 compatible, with some
> additional registers. Create a simple MMUART model built on top
> of the existing ns16550 model.
>
> Signed-off-by: Bin Meng 

Reviewed-by: Alistair Francis 

Alistair

>
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - change to update hw/char/meson.build
> - add impl.min_access_size and impl.max_access_size as part of
>   MemoryRegionOps and remove the allignment check
>
>  include/hw/char/mchp_pfsoc_mmuart.h | 61 ++
>  hw/char/mchp_pfsoc_mmuart.c | 86 
> +
>  MAINTAINERS |  2 +
>  hw/char/Kconfig |  3 ++
>  hw/char/meson.build |  1 +
>  5 files changed, 153 insertions(+)
>  create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h
>  create mode 100644 hw/char/mchp_pfsoc_mmuart.c
>
> diff --git a/include/hw/char/mchp_pfsoc_mmuart.h 
> b/include/hw/char/mchp_pfsoc_mmuart.h
> new file mode 100644
> index 000..f619902
> --- /dev/null
> +++ b/include/hw/char/mchp_pfsoc_mmuart.h
> @@ -0,0 +1,61 @@
> +/*
> + * Microchip PolarFire SoC MMUART emulation
> + *
> + * Copyright (c) 2020 Wind River Systems, Inc.
> + *
> + * Author:
> + *   Bin Meng 
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a 
> copy
> + * of this software and associated documentation files (the "Software"), to 
> deal
> + * in the Software without restriction, including without limitation the 
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_MCHP_PFSOC_MMUART_H
> +#define HW_MCHP_PFSOC_MMUART_H
> +
> +#include "hw/char/serial.h"
> +
> +#define MCHP_PFSOC_MMUART_REG_SIZE  52
> +
> +typedef struct MchpPfSoCMMUartState {
> +MemoryRegion iomem;
> +hwaddr base;
> +qemu_irq irq;
> +
> +SerialMM *serial;
> +
> +uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)];
> +} MchpPfSoCMMUartState;
> +
> +/**
> + * mchp_pfsoc_mmuart_create - Create a Microchip PolarFire SoC MMUART
> + *
> + * This is a helper routine for board to create a MMUART device that is
> + * compatible with Microchip PolarFire SoC.
> + *
> + * @sysmem: system memory region to map
> + * @base: base address of the MMUART registers
> + * @irq: IRQ number of the MMUART device
> + * @chr: character device to associate to
> + *
> + * @return: a pointer to the device specific control structure
> + */
> +MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
> +hwaddr base, qemu_irq irq, Chardev *chr);
> +
> +#endif /* HW_MCHP_PFSOC_MMUART_H */
> diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
> new file mode 100644
> index 000..8a002b0
> --- /dev/null
> +++ b/hw/char/mchp_pfsoc_mmuart.c
> @@ -0,0 +1,86 @@
> +/*
> + * Microchip PolarFire SoC MMUART emulation
> + *
> + * Copyright (c) 2020 Wind River Systems, Inc.
> + *
> + * Author:
> + *   Bin Meng 
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see .
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "chardev/char.h"
> +#include "exec/address-spaces.h"
> +#include "hw/char/mchp_pfsoc_mmuart.h"
> +
> +static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned 
> size)
> +{
> +MchpPfSoCMMUartState *s = opaque;
> +
> +if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
> +qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
> +  _

Re: hw/clock: What clock rate for virt machines?

[Alistair Francis]

On Wed, Sep 2, 2020 at 12:48 PM Philippe Mathieu-Daudé  wrote:
>
> On 9/2/20 8:18 PM, Peter Maydell wrote:
> > On Wed, 2 Sep 2020 at 18:03, Philippe Mathieu-Daudé  wrote:
> >>
> >> On 9/2/20 6:49 PM, Peter Maydell wrote:
> >>> On Wed, 2 Sep 2020 at 17:35, Philippe Mathieu-Daudé  
> >>> wrote:
>  Peter said "'clock' is basically meaningless for virt machines",
> 
>  I understand and agree. But how to make that explicit/obvious in
>  the code, when a device expects a clock frequency/period?
> >>>
> >>> When a particular *device* needs a clock, then presumably
> >>> it has a defined purpose for it, and we can pick a
> >>> frequency for it then.
> >>>
>  See for example hw/riscv/virt.c, it uses the following (confusing
>  to me) in virt_machine_init():
> 
> serial_mm_init(system_memory, memmap[VIRT_UART0].base,
> 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
> serial_hd(0), DEVICE_LITTLE_ENDIAN);
> >>>
> >>> In this case, the board has a model of a 16550A UART on it,
> >>> which uses its input clock to determine what the actual baud
> >>> rate is for particular guest settings of the divisor registers.
> >>> So we need to look at:
> >>>  * what does guest software expect the frequency to be?
> >>
> >> QEMU is supposed to model machine with no knowledge of the guest,
> >> but the virt case is a particular one indeed... as it has to know
> >> it is virtualized.
> >>
> >>>  * what is a "good" frequency which gives the guest the best
> >>>possible choices of baud rate?
> >>
> >> I'll think about it...
> >
> > My guess is that guest code assumes "same frequency an
> > x86 PC uses", but a risc-v person might know better...
> >
> > (For QEMU I think it only makes a visible difference when
> > you pass a host serial port through to the guest as
> > otherwise we ignore whatever baud rate the guest sets.)

I think that's the case. I suspect we just ignore whatever the guest
sets. I have never really looked into it though.

>
> It makes a difference with low baudrates (TBH I only tested
> what the firmwares I have use: 9600-8N1). No clue why (from
> design PoV) but some odd fw use the time spent to display
> chars to have a nicer 'user experience' (using polling).
> With incorrect timing everything is displayed at once partly
> scrambled.
>
> The following devices are modeled with timers limiting the
> transmit rate:
>
> $ git grep qemu_clock_get_ns hw/char/
> hw/char/cadence_uart.c:269:uint64_t new_rx_time =
> qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> hw/char/exynos4210_uart.c:393:
> qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout);
> hw/char/ibex_uart.c:155:uint64_t current_time =
> qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);

For the Ibex UART we want  to apply back pressure on the guest (as
that's what the main OT software expects) which is why we use this. I
think most other guest software doesn't care as much.

Alistair

> hw/char/renesas_sci.c:74:if (sci->rx_next >
> qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
> hw/char/renesas_sci.c:84:sci->rx_next =
> qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + sci->trtime;
> hw/char/serial.c:290:s->last_xmit_ts =
> qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> hw/char/serial.c:899:s->last_xmit_ts =
> qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> hw/char/sh_serial.c:352:
> qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->etu);
>
> >
> > thanks
> > -- PMM
> >
>

Re: [PATCH 49/63] stm32f205: Rename STM32F2XXTIMER to STM32F2XX_TIMER

[Alistair Francis]

On Wed, Sep 2, 2020 at 4:04 PM Eduardo Habkost  wrote:
>
> Make the type checking macro name consistent with the TYPE_*
> constant.
>
> Signed-off-by: Eduardo Habkost 

Reviewed-by: Alistair Francis 

Alistair

> ---
> Cc: Alistair Francis 
> Cc: Peter Maydell 
> Cc: qemu-...@nongnu.org
> Cc: qemu-devel@nongnu.org
> ---
>  include/hw/timer/stm32f2xx_timer.h | 2 +-
>  hw/timer/stm32f2xx_timer.c | 6 +++---
>  2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/include/hw/timer/stm32f2xx_timer.h 
> b/include/hw/timer/stm32f2xx_timer.h
> index 90f40f1746..70ef426afc 100644
> --- a/include/hw/timer/stm32f2xx_timer.h
> +++ b/include/hw/timer/stm32f2xx_timer.h
> @@ -63,7 +63,7 @@
>
>  #define TYPE_STM32F2XX_TIMER "stm32f2xx-timer"
>  typedef struct STM32F2XXTimerState STM32F2XXTimerState;
> -DECLARE_INSTANCE_CHECKER(STM32F2XXTimerState, STM32F2XXTIMER,
> +DECLARE_INSTANCE_CHECKER(STM32F2XXTimerState, STM32F2XX_TIMER,
>   TYPE_STM32F2XX_TIMER)
>
>  struct STM32F2XXTimerState {
> diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c
> index ba8694dcd3..d880c0b4d5 100644
> --- a/hw/timer/stm32f2xx_timer.c
> +++ b/hw/timer/stm32f2xx_timer.c
> @@ -96,7 +96,7 @@ static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState 
> *s, int64_t now)
>
>  static void stm32f2xx_timer_reset(DeviceState *dev)
>  {
> -STM32F2XXTimerState *s = STM32F2XXTIMER(dev);
> +STM32F2XXTimerState *s = STM32F2XX_TIMER(dev);
>  int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
>
>  s->tim_cr1 = 0;
> @@ -306,7 +306,7 @@ static Property stm32f2xx_timer_properties[] = {
>
>  static void stm32f2xx_timer_init(Object *obj)
>  {
> -STM32F2XXTimerState *s = STM32F2XXTIMER(obj);
> +STM32F2XXTimerState *s = STM32F2XX_TIMER(obj);
>
>  sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
>
> @@ -317,7 +317,7 @@ static void stm32f2xx_timer_init(Object *obj)
>
>  static void stm32f2xx_timer_realize(DeviceState *dev, Error **errp)
>  {
> -STM32F2XXTimerState *s = STM32F2XXTIMER(dev);
> +STM32F2XXTimerState *s = STM32F2XX_TIMER(dev);
>  s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, 
> s);
>  }
>
> --
> 2.26.2
>
>

Re: [PATCH 0/6] qom: Use typedefs instead of struct names on instance_size/class_size

[Eduardo Habkost]

On Mon, Aug 24, 2020 at 05:59:30PM -0400, Eduardo Habkost wrote:
> This changes existing QOM boilerplate to use existing typedef
> names when setting instance_size and class_size on TypeInfo
> variables.  This makes the code more consistent and will make
> future conversion to QOM type declaration macros easier.

I'm queueing this series, as I consider the patches trivial
cleanups.

-- 
Eduardo

[Bug 1838390] Re: vmx_write_mem: mmu_gva_to_gpa failed when using hvf

[Jordan Williams]

I think I was able to fix this crash by specifying the exact host model
for the cpu argument.

1. Determine the CPU type of the host machine.

$ sysctl -a | grep machdep.cpu.brand_string
machdep.cpu.brand_string: Intel(R) Core(TM) i5-4690 CPU @ 3.50GHz

2. Find the matching CPU model supported by QEMU.

$ qemu-system-x86_64 -cpu help


This CPU corresponds to "x86 Haswell-v4" in this instance.

3. Substitute the CPU model in the QEMU command.

$ qemu-system-x86_64 -cpu Haswell-v4 ...

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1838390

Title:
  vmx_write_mem: mmu_gva_to_gpa failed when using hvf

Status in QEMU:
  New

Bug description:
  Installed qemu 4.0.0 by homebrew, used below commands:

  1. qemu-img create -f raw arch-vm.img 100G
  2. qemu-system-x86_64 -show-cursor -only-migratable -nodefaults -boot order=d 
-cdrom archlinux-2019.07.01-x86_64.iso -cpu host -device virtio-keyboard 
-device virtio-mouse -device virtio-tablet -drive 
file=arch-vm.img,format=raw,if=virtio -m 4096 -machine q35,accel=hvf,vmport=off 
-nic user,ipv6=off,model=virtio -smp 4,sockets=1,cores=2,threads=2 -soundhw hda 
-vga virtio

  Displayed bootloader menu successfully, select "Boot Arch Linux" then
  crashed with message: vmx_write_mem: mmu_gva_to_gpa 91953b54
  failed.

  Use tcg accelerator has no problem but very slow.

  See attachment for full crash report.

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1838390/+subscriptions

Re: [PATCH 4/5] intel_iommu: Skip page walking on device iotlb invalidations

[Peter Xu]

On Thu, Sep 03, 2020 at 06:14:45PM +0200, Eugenio Pérez wrote:
> Although they didn't reach the notifier because of the filtering in
> memory_region_notify_iommu_one, the vt-d was still splitting huge
> memory invalidations in chunks. Skipping it.
> 
> This improves performance in case of netperf with vhost-net:
> * TCP_STREAM: From 1923.6Mbit/s to 2175.13Mbit/s (13%)
> * TCP_RR: From 8464.73 trans/s to 8932.70 trans/s (5.5%)
> * UDP_RR: From 8562.08 trans/s to 9005.62/s (5.1%)
> * UDP_STREAM: No change observed (insignificant 0.1% improvement)
> 
> Signed-off-by: Eugenio Pérez 

Reviewed-by: Peter Xu 

-- 
Peter Xu

[PATCH v3 01/19] target/microblaze: Collected fixes for env->iflags

[Richard Henderson]

There are several problems here that can result in soft lockup,
depending on exactly where an interrupt or exception is delivered:

Include BIMM_FLAG in IFLAGS_TB_MASK, since it needs to follow D_FLAG.
Ensure that iflags is 0 when entering an interrupt/exception handler.
Add mb_cpu_synchronize_from_tb to restore iflags from tb->flags.
The change to t_sync_flags is cosmetic, but makes the code clearer.

This fixes the reported regression in acceptance/replay_kernel.py.

Fixes: 683a247ed7a4 ("target/microblaze: Store "current" iflags in insn_start")
Tested-by: Thomas Huth 
Reported-by: Thomas Huth 
Signed-off-by: Richard Henderson 
---
 target/microblaze/cpu.h   |  3 ++-
 target/microblaze/cpu.c   | 11 +++
 target/microblaze/helper.c| 17 +++--
 target/microblaze/translate.c |  4 ++--
 4 files changed, 26 insertions(+), 9 deletions(-)

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index d11b6fa995..a25a2b427f 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -270,7 +270,8 @@ struct CPUMBState {
 #define D_FLAG (1 << 19)  /* Bit in ESR.  */
 
 /* TB dependent CPUMBState.  */
-#define IFLAGS_TB_MASK  (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
+#define IFLAGS_TB_MASK  (D_FLAG | BIMM_FLAG | IMM_FLAG | \
+ DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
 #define MSR_TB_MASK (MSR_UM | MSR_VM | MSR_EE)
 
 uint32_t iflags;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 67017ecc33..6392524135 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -80,6 +80,16 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value)
 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 
 cpu->env.pc = value;
+/* Ensure D_FLAG and IMM_FLAG are clear for the new PC */
+cpu->env.iflags = 0;
+}
+
+static void mb_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
+{
+MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+
+cpu->env.pc = tb->pc;
+cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
 }
 
 static bool mb_cpu_has_work(CPUState *cs)
@@ -321,6 +331,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
 cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
 cc->dump_state = mb_cpu_dump_state;
 cc->set_pc = mb_cpu_set_pc;
+cc->synchronize_from_tb = mb_cpu_synchronize_from_tb;
 cc->gdb_read_register = mb_cpu_gdb_read_register;
 cc->gdb_write_register = mb_cpu_gdb_write_register;
 cc->tlb_fill = mb_cpu_tlb_fill;
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index 48547385b0..00090526da 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -113,7 +113,10 @@ void mb_cpu_do_interrupt(CPUState *cs)
 uint32_t t, msr = mb_cpu_read_msr(env);
 
 /* IMM flag cannot propagate across a branch and into the dslot.  */
-assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
+assert((env->iflags & (D_FLAG | IMM_FLAG)) != (D_FLAG | IMM_FLAG));
+/* BIMM flag cannot be set without D_FLAG. */
+assert((env->iflags & (D_FLAG | BIMM_FLAG)) != BIMM_FLAG);
+/* RTI flags are private to translate. */
 assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
 env->res_addr = RES_ADDR_NONE;
 switch (cs->exception_index) {
@@ -146,7 +149,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
   env->pc, env->ear,
   env->esr, env->iflags);
 log_cpu_state_mask(CPU_LOG_INT, cs, 0);
-env->iflags &= ~(IMM_FLAG | D_FLAG);
+env->iflags = 0;
 env->pc = cpu->cfg.base_vectors + 0x20;
 break;
 
@@ -186,14 +189,14 @@ void mb_cpu_do_interrupt(CPUState *cs)
   "exception at pc=%x ear=%" PRIx64 " iflags=%x\n",
   env->pc, env->ear, env->iflags);
 log_cpu_state_mask(CPU_LOG_INT, cs, 0);
-env->iflags &= ~(IMM_FLAG | D_FLAG);
+env->iflags = 0;
 env->pc = cpu->cfg.base_vectors + 0x20;
 break;
 
 case EXCP_IRQ:
 assert(!(msr & (MSR_EIP | MSR_BIP)));
 assert(msr & MSR_IE);
-assert(!(env->iflags & D_FLAG));
+assert(!(env->iflags & (D_FLAG | IMM_FLAG)));
 
 t = (msr & (MSR_VM | MSR_UM)) << 1;
 
@@ -226,13 +229,14 @@ void mb_cpu_do_interrupt(CPUState *cs)
 mb_cpu_write_msr(env, msr);
 
 env->regs[14] = env->pc;
+env->iflags = 0;
 env->pc = cpu->cfg.base_vectors + 0x10;
 //log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 break;
 
 case EXCP_HW_BREAK:
-assert(!(env->iflags & IMM_FLAG));
-assert(!(env->iflags & D_FLAG));
+assert(!(env->iflags & (D_FLAG | IMM_FLAG)));
+
 t = (msr & (MSR_VM | MSR_UM)) << 1;
 qemu_log_mask(CPU_LOG_INT,
   "break at pc=%x msr=%x %x iflags=%x\n",
@@ -242,6 +246,7

[PATCH v3 03/19] target/microblaze: Cleanup mb_cpu_do_interrupt

[Richard Henderson]

Reindent; remove dead/commented code.
Use D_FLAG to set ESS[DS].
Sink MSR adjustment for kernel entry, iflags and res_addr clear.
Improve CPU_LOG_INT formatting; report pc and msr before and after.

Signed-off-by: Richard Henderson 
---
 target/microblaze/helper.c | 209 -
 1 file changed, 91 insertions(+), 118 deletions(-)

diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index 00090526da..27a24bb99a 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -111,6 +111,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 CPUMBState *env = &cpu->env;
 uint32_t t, msr = mb_cpu_read_msr(env);
+bool set_esr;
 
 /* IMM flag cannot propagate across a branch and into the dslot.  */
 assert((env->iflags & (D_FLAG | IMM_FLAG)) != (D_FLAG | IMM_FLAG));
@@ -118,142 +119,114 @@ void mb_cpu_do_interrupt(CPUState *cs)
 assert((env->iflags & (D_FLAG | BIMM_FLAG)) != BIMM_FLAG);
 /* RTI flags are private to translate. */
 assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
-env->res_addr = RES_ADDR_NONE;
+
 switch (cs->exception_index) {
-case EXCP_HW_EXCP:
-if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
-qemu_log_mask(LOG_GUEST_ERROR, "Exception raised on system 
without exceptions!\n");
-return;
-}
+case EXCP_HW_EXCP:
+if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
+qemu_log_mask(LOG_GUEST_ERROR,
+  "Exception raised on system without exceptions!\n");
+return;
+}
 
-env->regs[17] = env->pc + 4;
-env->esr &= ~(1 << 12);
+qemu_log_mask(CPU_LOG_INT,
+  "INT: HWE at pc=%08x msr=%08x iflags=%x\n",
+  env->pc, msr, env->iflags);
 
-/* Exception breaks branch + dslot sequence?  */
-if (env->iflags & D_FLAG) {
-env->esr |= 1 << 12 ;
-env->btr = env->btarget;
-}
+/* Exception breaks branch + dslot sequence?  */
+set_esr = true;
+env->esr &= ~D_FLAG;
+if (env->iflags & D_FLAG) {
+env->esr |= D_FLAG;
+env->btr = env->btarget;
+}
 
-/* Disable the MMU.  */
-t = (msr & (MSR_VM | MSR_UM)) << 1;
-msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
-msr |= t;
-/* Exception in progress.  */
-msr |= MSR_EIP;
-mb_cpu_write_msr(env, msr);
+/* Exception in progress. */
+msr |= MSR_EIP;
+env->regs[17] = env->pc + 4;
+env->pc = cpu->cfg.base_vectors + 0x20;
+break;
 
-qemu_log_mask(CPU_LOG_INT,
-  "hw exception at pc=%x ear=%" PRIx64 " "
-  "esr=%x iflags=%x\n",
-  env->pc, env->ear,
-  env->esr, env->iflags);
-log_cpu_state_mask(CPU_LOG_INT, cs, 0);
-env->iflags = 0;
-env->pc = cpu->cfg.base_vectors + 0x20;
-break;
+case EXCP_MMU:
+qemu_log_mask(CPU_LOG_INT,
+  "INT: MMU at pc=%08x msr=%08x "
+  "ear=%" PRIx64 " iflags=%x\n",
+  env->pc, msr, env->ear, env->iflags);
 
-case EXCP_MMU:
+/* Exception breaks branch + dslot sequence? */
+set_esr = true;
+env->esr &= ~D_FLAG;
+if (env->iflags & D_FLAG) {
+env->esr |= D_FLAG;
+env->btr = env->btarget;
+/* Reexecute the branch. */
+env->regs[17] = env->pc - (env->iflags & BIMM_FLAG ? 8 : 4);
+} else if (env->iflags & IMM_FLAG) {
+/* Reexecute the imm. */
+env->regs[17] = env->pc - 4;
+} else {
 env->regs[17] = env->pc;
+}
 
-qemu_log_mask(CPU_LOG_INT,
-  "MMU exception at pc=%x iflags=%x ear=%" PRIx64 "\n",
-  env->pc, env->iflags, env->ear);
+/* Exception in progress. */
+msr |= MSR_EIP;
+env->pc = cpu->cfg.base_vectors + 0x20;
+break;
 
-env->esr &= ~(1 << 12);
-/* Exception breaks branch + dslot sequence?  */
-if (env->iflags & D_FLAG) {
-env->esr |= 1 << 12 ;
-env->btr = env->btarget;
+case EXCP_IRQ:
+assert(!(msr & (MSR_EIP | MSR_BIP)));
+assert(msr & MSR_IE);
+assert(!(env->iflags & (D_FLAG | IMM_FLAG)));
 
-/* Reexecute the branch.  */
-env->regs[17] -= 4;
-/* was the branch immprefixed?.  */
-if (env->iflags & BIMM_FLAG) {
-env->regs[17] -= 4;
-log_cpu_state_mask(CPU_LOG_INT, cs, 0);
-}
-} else if (env->

[PATCH v3 02/19] target/microblaze: Renumber D_FLAG

[Richard Henderson]

ESS[DS] is bit 19 in the manual, but the manual uses big-endian bit
numbering.  This corresponds to bit 12 in little-endian numbering.
Let the comment about matching the ESR be true by renumbering it.

Signed-off-by: Richard Henderson 
---
 target/microblaze/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index a25a2b427f..32811f773d 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -264,10 +264,10 @@ struct CPUMBState {
 /* MSR_UM   (1 << 11) */
 /* MSR_VM   (1 << 13) */
 /* ESR_ESS_MASK [11:5]-- unwind into iflags for unaligned excp */
+#define D_FLAG (1 << 12)  /* Bit in ESR.  */
 #define DRTI_FLAG  (1 << 16)
 #define DRTE_FLAG  (1 << 17)
 #define DRTB_FLAG  (1 << 18)
-#define D_FLAG (1 << 19)  /* Bit in ESR.  */
 
 /* TB dependent CPUMBState.  */
 #define IFLAGS_TB_MASK  (D_FLAG | BIMM_FLAG | IMM_FLAG | \
-- 
2.25.1

[PATCH v3 00/19] target/microblaze improvements

[Richard Henderson]

Version 3:

 * Splits out MicroBlazeCPUConfig, and moves some values
   out of CPUMBState (env) that are constant configuration
   parameters, or derived from configuration parameters.

 * Do not save configuration parameters with vmstate.
 * Pass around MicroBlazeCPUConfig in the translator.
 * Do not set TARGET_ABI32 in configure.

Version 2:

 * Includes fixes for iflags that could cause lockups.

   It seems it was easier to do so with icount=7, which is what we
   do during the replay acceptance tests.  This causes TBs to contain
   no more than 7 insns, and often less to make up for an incomplete
   count elsewhere.  Which stressed the iflags bits around delay slots
   and imm in ways that pure single-step doesn't.

  * cpu vmstate is filled in
  * interrupt logging is tidied.


r~


Richard Henderson (19):
  target/microblaze: Collected fixes for env->iflags
  target/microblaze: Renumber D_FLAG
  target/microblaze: Cleanup mb_cpu_do_interrupt
  target/microblaze: Rename mmu structs
  target/microblaze: Rename DISAS_UPDATE to DISAS_EXIT
  target/microblaze: Introduce DISAS_EXIT_NEXT, DISAS_EXIT_JUMP
  target/microblaze: Replace cpustate_changed with DISAS_EXIT_NEXT
  target/microblaze: Handle DISAS_EXIT_NEXT in delay slot
  target/microblaze: Force rtid, rted, rtbd to exit
  target/microblaze: Use tcg_gen_lookup_and_goto_ptr
  target/microblaze: Diagnose invalid insns in delay slots
  target/microblaze: Split out MicroBlazeCPUConfig
  target/microblaze: Reorg MicroBlazeCPUConfig to minimize holes
  target/microblaze: Move pvr regs to MicroBlazeCPUConfig
  target/microblaze: Treat pvr_regs as constant
  target/microblaze: Move mmu parameters to MicroBlazeCPUConfig
  target/microblaze: Fill in VMStateDescription for cpu
  target/microblaze: Put MicroBlazeCPUConfig into DisasContext
  configure: Do not set TARGET_ABI32 for microblaze

 configure   |   1 -
 target/microblaze/cpu.h |  81 +-
 target/microblaze/mmu.h |  20 +--
 hw/microblaze/petalogix_ml605_mmu.c |   6 +-
 target/microblaze/cpu.c | 120 +++
 target/microblaze/gdbstub.c |   6 +-
 target/microblaze/helper.c  | 220 +---
 target/microblaze/machine.c | 106 ++
 target/microblaze/mmu.c |  39 ++---
 target/microblaze/op_helper.c   |   2 +-
 target/microblaze/translate.c   | 198 -
 target/microblaze/meson.build   |   5 +-
 12 files changed, 482 insertions(+), 322 deletions(-)
 create mode 100644 target/microblaze/machine.c

-- 
2.25.1

[PATCH v3 10/19] target/microblaze: Use tcg_gen_lookup_and_goto_ptr

[Richard Henderson]

Normal indirect jumps, or page-crossing direct jumps, can use
tcg_gen_lookup_and_goto_ptr to avoid returning to the main loop
simply to find an existing TB for the next pc.

Reviewed-by: Edgar E. Iglesias 
Tested-by: Edgar E. Iglesias 
Signed-off-by: Richard Henderson 
---
 target/microblaze/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index da84fdb20b..d98572fab9 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -147,7 +147,7 @@ static void gen_goto_tb(DisasContext *dc, int n, 
target_ulong dest)
 tcg_gen_exit_tb(dc->base.tb, n);
 } else {
 tcg_gen_movi_i32(cpu_pc, dest);
-tcg_gen_exit_tb(NULL, 0);
+tcg_gen_lookup_and_goto_ptr();
 }
 dc->base.is_jmp = DISAS_NORETURN;
 }
@@ -1803,7 +1803,7 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState 
*cs)
 if (unlikely(cs->singlestep_enabled)) {
 gen_raise_exception(dc, EXCP_DEBUG);
 } else {
-tcg_gen_exit_tb(NULL, 0);
+tcg_gen_lookup_and_goto_ptr();
 }
 return;
 
-- 
2.25.1

[PATCH v3 07/19] target/microblaze: Replace cpustate_changed with DISAS_EXIT_NEXT

[Richard Henderson]

Rather than look for the combination of DISAS_NEXT with a separate
variable, go ahead and set is_jmp to the desired state.

Reviewed-by: Edgar E. Iglesias 
Tested-by: Edgar E. Iglesias 
Signed-off-by: Richard Henderson 
---
 target/microblaze/translate.c | 34 ++
 1 file changed, 10 insertions(+), 24 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 2abef328a3..6bf299a826 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -70,7 +70,6 @@ typedef struct DisasContext {
 
 /* Decoder.  */
 uint32_t ext_imm;
-unsigned int cpustate_changed;
 unsigned int tb_flags;
 unsigned int tb_flags_to_set;
 int mem_index;
@@ -1255,7 +1254,7 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *arg)
  *
  * Therefore, choose to end the TB always.
  */
-dc->cpustate_changed = 1;
+dc->base.is_jmp = DISAS_EXIT_NEXT;
 return true;
 }
 
@@ -1307,19 +1306,6 @@ static void msr_read(DisasContext *dc, TCGv_i32 d)
 tcg_temp_free_i32(t);
 }
 
-#ifndef CONFIG_USER_ONLY
-static void msr_write(DisasContext *dc, TCGv_i32 v)
-{
-dc->cpustate_changed = 1;
-
-/* Install MSR_C.  */
-tcg_gen_extract_i32(cpu_msr_c, v, 2, 1);
-
-/* Clear MSR_C and MSR_CC; MSR_PVR is not writable, and is always clear. */
-tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR));
-}
-#endif
-
 static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set)
 {
 uint32_t imm = arg->imm;
@@ -1352,7 +1338,7 @@ static bool do_msrclrset(DisasContext *dc, arg_type_msr 
*arg, bool set)
 } else {
 tcg_gen_andi_i32(cpu_msr, cpu_msr, ~imm);
 }
-dc->cpustate_changed = 1;
+dc->base.is_jmp = DISAS_EXIT_NEXT;
 }
 return true;
 }
@@ -1385,7 +1371,13 @@ static bool trans_mts(DisasContext *dc, arg_mts *arg)
 TCGv_i32 src = reg_for_read(dc, arg->ra);
 switch (arg->rs) {
 case SR_MSR:
-msr_write(dc, src);
+/* Install MSR_C.  */
+tcg_gen_extract_i32(cpu_msr_c, src, 2, 1);
+/*
+ * Clear MSR_C and MSR_CC;
+ * MSR_PVR is not writable, and is always clear.
+ */
+tcg_gen_andi_i32(cpu_msr, src, ~(MSR_C | MSR_CC | MSR_PVR));
 break;
 case SR_FSR:
 tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, fsr));
@@ -1417,7 +1409,7 @@ static bool trans_mts(DisasContext *dc, arg_mts *arg)
 qemu_log_mask(LOG_GUEST_ERROR, "Invalid mts reg 0x%x\n", arg->rs);
 return true;
 }
-dc->cpustate_changed = 1;
+dc->base.is_jmp = DISAS_EXIT_NEXT;
 return true;
 #endif
 }
@@ -1629,7 +1621,6 @@ static void mb_tr_init_disas_context(DisasContextBase 
*dcb, CPUState *cs)
 
 dc->cpu = cpu;
 dc->tb_flags = dc->base.tb->flags;
-dc->cpustate_changed = 0;
 dc->ext_imm = dc->base.tb->cs_base;
 dc->r0 = NULL;
 dc->r0_set = false;
@@ -1714,11 +1705,6 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, 
CPUState *cs)
 }
 dc->base.is_jmp = DISAS_JUMP;
 }
-
-/* Force an exit if the per-tb cpu state has changed.  */
-if (dc->base.is_jmp == DISAS_NEXT && dc->cpustate_changed) {
-dc->base.is_jmp = DISAS_EXIT_NEXT;
-}
 }
 
 static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
-- 
2.25.1

[PATCH v3 04/19] target/microblaze: Rename mmu structs

[Richard Henderson]

Introduce typedefs and follow CODING_STYLE for naming.
Rename struct microblaze_mmu to MicroBlazeMMU.
Rename struct microblaze_mmu_lookup to MicroBlazeMMULookup.

Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Edgar E. Iglesias 
Signed-off-by: Richard Henderson 
---
 target/microblaze/cpu.h|  2 +-
 target/microblaze/mmu.h| 15 ++-
 target/microblaze/helper.c |  4 ++--
 target/microblaze/mmu.c| 11 +--
 4 files changed, 14 insertions(+), 18 deletions(-)

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 32811f773d..20c2979396 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -278,7 +278,7 @@ struct CPUMBState {
 
 #if !defined(CONFIG_USER_ONLY)
 /* Unified MMU.  */
-struct microblaze_mmu mmu;
+MicroBlazeMMU mmu;
 #endif
 
 /* Fields up to this point are cleared by a CPU reset */
diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h
index 75e5301c79..c1feb811b9 100644
--- a/target/microblaze/mmu.h
+++ b/target/microblaze/mmu.h
@@ -63,8 +63,7 @@
 
 #define TLB_ENTRIES64
 
-struct microblaze_mmu
-{
+typedef struct {
 /* Data and tag brams.  */
 uint64_t rams[2][TLB_ENTRIES];
 /* We keep a separate ram for the tids to avoid the 48 bit tag width.  */
@@ -76,10 +75,9 @@ struct microblaze_mmu
 int c_mmu_tlb_access;
 int c_mmu_zones;
 uint64_t c_addr_mask; /* Mask to apply to physical addresses.  */
-};
+} MicroBlazeMMU;
 
-struct microblaze_mmu_lookup
-{
+typedef struct {
 uint32_t paddr;
 uint32_t vaddr;
 unsigned int size;
@@ -88,13 +86,12 @@ struct microblaze_mmu_lookup
 enum {
 ERR_PROT, ERR_MISS, ERR_HIT
 } err;
-};
+} MicroBlazeMMULookup;
 
-unsigned int mmu_translate(struct microblaze_mmu *mmu,
-   struct microblaze_mmu_lookup *lu,
+unsigned int mmu_translate(MicroBlazeMMU *mmu, MicroBlazeMMULookup *lu,
target_ulong vaddr, int rw, int mmu_idx);
 uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn);
 void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v);
-void mmu_init(struct microblaze_mmu *mmu);
+void mmu_init(MicroBlazeMMU *mmu);
 
 #endif
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index 27a24bb99a..3c2fd388fb 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -52,7 +52,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 {
 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 CPUMBState *env = &cpu->env;
-struct microblaze_mmu_lookup lu;
+MicroBlazeMMULookup lu;
 unsigned int hit;
 int prot;
 
@@ -235,7 +235,7 @@ hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 CPUMBState *env = &cpu->env;
 target_ulong vaddr, paddr = 0;
-struct microblaze_mmu_lookup lu;
+MicroBlazeMMULookup lu;
 int mmu_idx = cpu_mmu_index(env, false);
 unsigned int hit;
 
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 6e583d78d9..0546cfd0bc 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -35,7 +35,7 @@ static unsigned int tlb_decode_size(unsigned int f)
 static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
 {
 CPUState *cs = env_cpu(env);
-struct microblaze_mmu *mmu = &env->mmu;
+MicroBlazeMMU *mmu = &env->mmu;
 unsigned int tlb_size;
 uint32_t tlb_tag, end, t;
 
@@ -55,7 +55,7 @@ static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
 
 static void mmu_change_pid(CPUMBState *env, unsigned int newpid) 
 {
-struct microblaze_mmu *mmu = &env->mmu;
+MicroBlazeMMU *mmu = &env->mmu;
 unsigned int i;
 uint32_t t;
 
@@ -73,8 +73,7 @@ static void mmu_change_pid(CPUMBState *env, unsigned int 
newpid)
 }
 
 /* rw - 0 = read, 1 = write, 2 = fetch.  */
-unsigned int mmu_translate(struct microblaze_mmu *mmu,
-   struct microblaze_mmu_lookup *lu,
+unsigned int mmu_translate(MicroBlazeMMU *mmu, MicroBlazeMMULookup *lu,
target_ulong vaddr, int rw, int mmu_idx)
 {
 unsigned int i, hit = 0;
@@ -290,7 +289,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, 
uint32_t v)
 break;
 case MMU_R_TLBSX:
 {
-struct microblaze_mmu_lookup lu;
+MicroBlazeMMULookup lu;
 int hit;
 
 if (env->mmu.c_mmu_tlb_access <= 1) {
@@ -314,7 +313,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, 
uint32_t v)
}
 }
 
-void mmu_init(struct microblaze_mmu *mmu)
+void mmu_init(MicroBlazeMMU *mmu)
 {
 int i;
 for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) {
-- 
2.25.1

[PATCH v3 05/19] target/microblaze: Rename DISAS_UPDATE to DISAS_EXIT

[Richard Henderson]

The name "update" suggests that something needs updating, but
this is not the case.  Use "exit" to emphasize that nothing
needs doing except to exit.

Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Edgar E. Iglesias 
Tested-by: Edgar E. Iglesias 
Signed-off-by: Richard Henderson 
---
 target/microblaze/translate.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index a8a3249185..8ceb04f4f0 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -37,7 +37,7 @@
 
 /* is_jmp field values */
 #define DISAS_JUMPDISAS_TARGET_0 /* only pc was modified dynamically */
-#define DISAS_UPDATE  DISAS_TARGET_1 /* cpu state was modified dynamically */
+#define DISAS_EXITDISAS_TARGET_1 /* all cpu state modified dynamically */
 
 static TCGv_i32 cpu_R[32];
 static TCGv_i32 cpu_pc;
@@ -1161,7 +1161,7 @@ static bool trans_brk(DisasContext *dc, arg_typea_br *arg)
 tcg_gen_ori_i32(cpu_msr, cpu_msr, MSR_BIP);
 tcg_gen_movi_tl(cpu_res_addr, -1);
 
-dc->base.is_jmp = DISAS_UPDATE;
+dc->base.is_jmp = DISAS_EXIT;
 return true;
 }
 
@@ -1202,7 +1202,7 @@ static bool trans_brki(DisasContext *dc, arg_typeb_br 
*arg)
  ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM));
 }
 tcg_gen_ori_i32(cpu_msr, cpu_msr, msr_to_set);
-dc->base.is_jmp = DISAS_UPDATE;
+dc->base.is_jmp = DISAS_EXIT;
 #endif
 
 return true;
@@ -1712,7 +1712,7 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, 
CPUState *cs)
 
 /* Force an exit if the per-tb cpu state has changed.  */
 if (dc->base.is_jmp == DISAS_NEXT && dc->cpustate_changed) {
-dc->base.is_jmp = DISAS_UPDATE;
+dc->base.is_jmp = DISAS_EXIT;
 tcg_gen_movi_i32(cpu_pc, dc->base.pc_next);
 }
 }
@@ -1733,7 +1733,7 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState 
*cs)
 gen_goto_tb(dc, 0, dc->base.pc_next);
 return;
 
-case DISAS_UPDATE:
+case DISAS_EXIT:
 if (unlikely(cs->singlestep_enabled)) {
 gen_raise_exception(dc, EXCP_DEBUG);
 } else {
-- 
2.25.1

[PATCH v3 06/19] target/microblaze: Introduce DISAS_EXIT_NEXT, DISAS_EXIT_JUMP

[Richard Henderson]

Like DISAS_EXIT, except we need to update cpu_pc,
either to pc_next or to btarget respectively.

Reviewed-by: Edgar E. Iglesias 
Tested-by: Edgar E. Iglesias 
Signed-off-by: Richard Henderson 
---
 target/microblaze/translate.c | 29 +
 1 file changed, 21 insertions(+), 8 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 8ceb04f4f0..2abef328a3 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -39,6 +39,11 @@
 #define DISAS_JUMPDISAS_TARGET_0 /* only pc was modified dynamically */
 #define DISAS_EXITDISAS_TARGET_1 /* all cpu state modified dynamically */
 
+/* cpu state besides pc was modified dynamically; update pc to next */
+#define DISAS_EXIT_NEXT DISAS_TARGET_2
+/* cpu state besides pc was modified dynamically; update pc to btarget */
+#define DISAS_EXIT_JUMP DISAS_TARGET_3
+
 static TCGv_i32 cpu_R[32];
 static TCGv_i32 cpu_pc;
 static TCGv_i32 cpu_msr;
@@ -1712,8 +1717,7 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, 
CPUState *cs)
 
 /* Force an exit if the per-tb cpu state has changed.  */
 if (dc->base.is_jmp == DISAS_NEXT && dc->cpustate_changed) {
-dc->base.is_jmp = DISAS_EXIT;
-tcg_gen_movi_i32(cpu_pc, dc->base.pc_next);
+dc->base.is_jmp = DISAS_EXIT_NEXT;
 }
 }
 
@@ -1734,12 +1738,14 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, 
CPUState *cs)
 return;
 
 case DISAS_EXIT:
-if (unlikely(cs->singlestep_enabled)) {
-gen_raise_exception(dc, EXCP_DEBUG);
-} else {
-tcg_gen_exit_tb(NULL, 0);
-}
-return;
+break;
+case DISAS_EXIT_NEXT:
+tcg_gen_movi_i32(cpu_pc, dc->base.pc_next);
+break;
+case DISAS_EXIT_JUMP:
+tcg_gen_mov_i32(cpu_pc, cpu_btarget);
+tcg_gen_discard_i32(cpu_btarget);
+break;
 
 case DISAS_JUMP:
 if (dc->jmp_dest != -1 && !cs->singlestep_enabled) {
@@ -1781,6 +1787,13 @@ static void mb_tr_tb_stop(DisasContextBase *dcb, 
CPUState *cs)
 default:
 g_assert_not_reached();
 }
+
+/* Finish DISAS_EXIT_* */
+if (unlikely(cs->singlestep_enabled)) {
+gen_raise_exception(dc, EXCP_DEBUG);
+} else {
+tcg_gen_exit_tb(NULL, 0);
+}
 }
 
 static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs)
-- 
2.25.1

[PATCH v3 09/19] target/microblaze: Force rtid, rted, rtbd to exit

[Richard Henderson]

These return-from-exception type instructions have modified
MSR to re-enable various forms of interrupt.  Force a return
to the main loop.

Consolidate the cleanup of tb_flags into mb_tr_translate_insn.

Reviewed-by: Edgar E. Iglesias 
Tested-by: Edgar E. Iglesias 
Signed-off-by: Richard Henderson 
---
 target/microblaze/translate.c | 27 ---
 1 file changed, 16 insertions(+), 11 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 608d413c83..da84fdb20b 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1518,7 +1518,6 @@ static void do_rti(DisasContext *dc)
 tcg_gen_or_i32(cpu_msr, cpu_msr, tmp);
 
 tcg_temp_free_i32(tmp);
-dc->tb_flags &= ~DRTI_FLAG;
 }
 
 static void do_rtb(DisasContext *dc)
@@ -1531,7 +1530,6 @@ static void do_rtb(DisasContext *dc)
 tcg_gen_or_i32(cpu_msr, cpu_msr, tmp);
 
 tcg_temp_free_i32(tmp);
-dc->tb_flags &= ~DRTB_FLAG;
 }
 
 static void do_rte(DisasContext *dc)
@@ -1545,7 +1543,6 @@ static void do_rte(DisasContext *dc)
 tcg_gen_or_i32(cpu_msr, cpu_msr, tmp);
 
 tcg_temp_free_i32(tmp);
-dc->tb_flags &= ~DRTE_FLAG;
 }
 
 /* Insns connected to FSL or AXI stream attached devices.  */
@@ -1700,12 +1697,16 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, 
CPUState *cs)
  * Finish any return-from branch.
  * TODO: Diagnose rtXd in delay slot of rtYd earlier.
  */
-if (dc->tb_flags & DRTI_FLAG) {
-do_rti(dc);
-} else if (dc->tb_flags & DRTB_FLAG) {
-do_rtb(dc);
-} else if (dc->tb_flags & DRTE_FLAG) {
-do_rte(dc);
+uint32_t rt_ibe = dc->tb_flags & (DRTI_FLAG | DRTB_FLAG | DRTE_FLAG);
+if (unlikely(rt_ibe != 0)) {
+dc->tb_flags &= ~(DRTI_FLAG | DRTB_FLAG | DRTE_FLAG);
+if (rt_ibe & DRTI_FLAG) {
+do_rti(dc);
+} else if (rt_ibe & DRTB_FLAG) {
+do_rtb(dc);
+} else {
+do_rte(dc);
+}
 }
 
 /* Complete the branch, ending the TB. */
@@ -1723,8 +1724,12 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, 
CPUState *cs)
  */
 break;
 case DISAS_NEXT:
-/* Normal insn a delay slot.  */
-dc->base.is_jmp = DISAS_JUMP;
+/*
+ * Normal insn a delay slot.
+ * However, the return-from-exception type insns should
+ * return to the main loop, as they have adjusted MSR.
+ */
+dc->base.is_jmp = (rt_ibe ? DISAS_EXIT_JUMP : DISAS_JUMP);
 break;
 case DISAS_EXIT_NEXT:
 /*
-- 
2.25.1

[PATCH v3 15/19] target/microblaze: Treat pvr_regs as constant

[Richard Henderson]

Do not allow gdb to set the values, and don't bother dumping
unchanging values with -d cpu.

Signed-off-by: Richard Henderson 
---
 target/microblaze/gdbstub.c   | 4 
 target/microblaze/translate.c | 5 -
 2 files changed, 9 deletions(-)

diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c
index 9e3b9ac824..be39fd4540 100644
--- a/target/microblaze/gdbstub.c
+++ b/target/microblaze/gdbstub.c
@@ -132,10 +132,6 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t 
*mem_buf, int n)
 case GDB_BTR:
 env->btr = tmp;
 break;
-case GDB_PVR0 ... GDB_PVR11:
-/* PVR12 is intentionally skipped */
-cpu->cfg.pvr_regs[n - GDB_PVR0] = tmp;
-break;
 case GDB_EDR:
 env->edr = tmp;
 break;
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 9e4551d99b..eca422b3db 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1919,11 +1919,6 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
  env->esr, env->fsr, env->btr, env->edr,
  env->ear, env->slr, env->shr);
 
-for (i = 0; i < 12; i++) {
-qemu_fprintf(f, "rpvr%-2d=%08x%c",
- i, env->pvr.regs[i], i % 4 == 3 ? '\n' : ' ');
-}
-
 for (i = 0; i < 32; i++) {
 qemu_fprintf(f, "r%2.2d=%08x%c",
  i, env->regs[i], i % 4 == 3 ? '\n' : ' ');
-- 
2.25.1

[PATCH v3 14/19] target/microblaze: Move pvr regs to MicroBlazeCPUConfig

[Richard Henderson]

These values are constant, and are derived from the other
configuration knobs.  Move them into MicroBlazeCPUConfig
to emphasize that they are not variable.

Signed-off-by: Richard Henderson 
---
 target/microblaze/cpu.h |  5 +-
 hw/microblaze/petalogix_ml605_mmu.c |  6 +-
 target/microblaze/cpu.c | 92 ++---
 target/microblaze/gdbstub.c |  4 +-
 target/microblaze/helper.c  |  2 +-
 target/microblaze/op_helper.c   |  2 +-
 target/microblaze/translate.c   |  3 +-
 7 files changed, 54 insertions(+), 60 deletions(-)

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 4d53345f23..ef96f2fe02 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -285,10 +285,6 @@ struct CPUMBState {
 struct {} end_reset_fields;
 
 /* These fields are preserved on reset.  */
-
-struct {
-uint32_t regs[13];
-} pvr;
 };
 
 /*
@@ -301,6 +297,7 @@ typedef struct {
 
 uint32_t base_vectors;
 uint32_t pvr_user2;
+uint32_t pvr_regs[13];
 
 uint8_t addr_size;
 uint8_t use_fpu;
diff --git a/hw/microblaze/petalogix_ml605_mmu.c 
b/hw/microblaze/petalogix_ml605_mmu.c
index e49fc86eb8..159db6cbe2 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -200,9 +200,9 @@ petalogix_ml605_init(MachineState *machine)
 }
 
 /* setup PVR to match kernel settings */
-cpu->env.pvr.regs[4] = 0xc56b8000;
-cpu->env.pvr.regs[5] = 0xc56be000;
-cpu->env.pvr.regs[10] = 0x0e00; /* virtex 6 */
+cpu->cfg.pvr_regs[4] = 0xc56b8000;
+cpu->cfg.pvr_regs[5] = 0xc56be000;
+cpu->cfg.pvr_regs[10] = 0x0e00; /* virtex 6 */
 
 microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size,
machine->initrd_filename,
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 6392524135..b9bb7f0cc7 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -153,7 +153,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 CPUState *cs = CPU(dev);
 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
-CPUMBState *env = &cpu->env;
 uint8_t version_code = 0;
 const char *version;
 int i = 0;
@@ -173,16 +172,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error 
**errp)
 
 qemu_init_vcpu(cs);
 
-env->pvr.regs[0] = PVR0_USE_EXC_MASK
-   | PVR0_USE_ICACHE_MASK
-   | PVR0_USE_DCACHE_MASK;
-env->pvr.regs[2] = PVR2_D_OPB_MASK
-| PVR2_D_LMB_MASK
-| PVR2_I_OPB_MASK
-| PVR2_I_LMB_MASK
-| PVR2_FPU_EXC_MASK
-| 0;
-
 version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION;
 for (i = 0; mb_cpu_lookup[i].name && version; i++) {
 if (strcmp(mb_cpu_lookup[i].name, version) == 0) {
@@ -195,46 +184,53 @@ static void mb_cpu_realizefn(DeviceState *dev, Error 
**errp)
 qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
 }
 
-env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
-(cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
-(cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) |
-(cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) |
-(cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) |
-(cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
-(cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
-(version_code << PVR0_VERSION_SHIFT) |
-(cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
-cpu->cfg.pvr_user1;
+cpu->cfg.pvr_regs[0] =
+(PVR0_USE_EXC_MASK |
+ PVR0_USE_ICACHE_MASK |
+ PVR0_USE_DCACHE_MASK |
+ (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
+ (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
+ (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) |
+ (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) |
+ (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) |
+ (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
+ (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
+ (version_code << PVR0_VERSION_SHIFT) |
+ (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
+ cpu->cfg.pvr_user1);
 
-env->pvr.regs[1] = cpu->cfg.pvr_user2;
-env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
-(cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
-(cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
-(cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
-(cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
-(cpu->cfg.use_div ? PVR2_USE_DIV_MASK

[PATCH v3 08/19] target/microblaze: Handle DISAS_EXIT_NEXT in delay slot

[Richard Henderson]

It is legal to put an mts instruction into a delay slot.
We should continue to return to the main loop in that
case so that we recognize any pending interrupts.

Reviewed-by: Edgar E. Iglesias 
Tested-by: Edgar E. Iglesias 
Signed-off-by: Richard Henderson 
---
 target/microblaze/translate.c | 34 +-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 6bf299a826..608d413c83 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1696,6 +1696,10 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, 
CPUState *cs)
 dc->base.pc_next += 4;
 
 if (dc->jmp_cond != TCG_COND_NEVER && !(dc->tb_flags & D_FLAG)) {
+/*
+ * Finish any return-from branch.
+ * TODO: Diagnose rtXd in delay slot of rtYd earlier.
+ */
 if (dc->tb_flags & DRTI_FLAG) {
 do_rti(dc);
 } else if (dc->tb_flags & DRTB_FLAG) {
@@ -1703,7 +1707,35 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, 
CPUState *cs)
 } else if (dc->tb_flags & DRTE_FLAG) {
 do_rte(dc);
 }
-dc->base.is_jmp = DISAS_JUMP;
+
+/* Complete the branch, ending the TB. */
+switch (dc->base.is_jmp) {
+case DISAS_NORETURN:
+/*
+ * E.g. illegal insn in a delay slot.  We've already exited
+ * and will handle D_FLAG in mb_cpu_do_interrupt.
+ */
+break;
+case DISAS_EXIT:
+/*
+ * TODO: diagnose brk/brki in delay slot earlier.
+ * This would then fold into the illegal insn case above.
+ */
+break;
+case DISAS_NEXT:
+/* Normal insn a delay slot.  */
+dc->base.is_jmp = DISAS_JUMP;
+break;
+case DISAS_EXIT_NEXT:
+/*
+ * E.g. mts insn in a delay slot.  Continue with btarget,
+ * but still return to the main loop.
+ */
+dc->base.is_jmp = DISAS_EXIT_JUMP;
+break;
+default:
+g_assert_not_reached();
+}
 }
 }
 
-- 
2.25.1

[PATCH v3 18/19] target/microblaze: Put MicroBlazeCPUConfig into DisasContext

[Richard Henderson]

The bulk of the translator should not have access to the
complete cpu state, to avoid the temptation to examine bits
that are in run time, but not translation time context.

We do need access to the constant cpu configuration, and
that is sufficient, so put that into DisasContext.

Signed-off-by: Richard Henderson 
---
 target/microblaze/translate.c | 24 
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index eca422b3db..abfcc7e6c8 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -60,7 +60,7 @@ static TCGv_i32 cpu_res_val;
 /* This is the state at translation time.  */
 typedef struct DisasContext {
 DisasContextBase base;
-MicroBlazeCPU *cpu;
+const MicroBlazeCPUConfig *cfg;
 
 /* TCG op of the current insn_start.  */
 TCGOp *insn_start;
@@ -159,7 +159,7 @@ static void gen_goto_tb(DisasContext *dc, int n, 
target_ulong dest)
 static bool trap_illegal(DisasContext *dc, bool cond)
 {
 if (cond && (dc->tb_flags & MSR_EE)
-&& dc->cpu->cfg.illegal_opcode_exception) {
+&& dc->cfg->illegal_opcode_exception) {
 gen_raise_hw_excp(dc, ESR_EC_ILLEGAL_OP);
 }
 return cond;
@@ -291,7 +291,7 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, 
bool side_effects,
 
 #define DO_TYPEA_CFG(NAME, CFG, SE, FN) \
 static bool trans_##NAME(DisasContext *dc, arg_typea *a) \
-{ return dc->cpu->cfg.CFG && do_typea(dc, a, SE, FN); }
+{ return dc->cfg->CFG && do_typea(dc, a, SE, FN); }
 
 #define DO_TYPEA0(NAME, SE, FN) \
 static bool trans_##NAME(DisasContext *dc, arg_typea0 *a) \
@@ -299,7 +299,7 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, 
bool side_effects,
 
 #define DO_TYPEA0_CFG(NAME, CFG, SE, FN) \
 static bool trans_##NAME(DisasContext *dc, arg_typea0 *a) \
-{ return dc->cpu->cfg.CFG && do_typea0(dc, a, SE, FN); }
+{ return dc->cfg->CFG && do_typea0(dc, a, SE, FN); }
 
 #define DO_TYPEBI(NAME, SE, FNI) \
 static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \
@@ -307,7 +307,7 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, 
bool side_effects,
 
 #define DO_TYPEBI_CFG(NAME, CFG, SE, FNI) \
 static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \
-{ return dc->cpu->cfg.CFG && do_typeb_imm(dc, a, SE, FNI); }
+{ return dc->cfg->CFG && do_typeb_imm(dc, a, SE, FNI); }
 
 #define DO_TYPEBV(NAME, SE, FN) \
 static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \
@@ -683,7 +683,7 @@ static TCGv compute_ldst_addr_typea(DisasContext *dc, int 
ra, int rb)
 tcg_gen_movi_tl(ret, 0);
 }
 
-if ((ra == 1 || rb == 1) && dc->cpu->cfg.stackprot) {
+if ((ra == 1 || rb == 1) && dc->cfg->stackprot) {
 gen_helper_stackprot(cpu_env, ret);
 }
 return ret;
@@ -703,7 +703,7 @@ static TCGv compute_ldst_addr_typeb(DisasContext *dc, int 
ra, int imm)
 tcg_gen_movi_tl(ret, (uint32_t)imm);
 }
 
-if (ra == 1 && dc->cpu->cfg.stackprot) {
+if (ra == 1 && dc->cfg->stackprot) {
 gen_helper_stackprot(cpu_env, ret);
 }
 return ret;
@@ -712,7 +712,7 @@ static TCGv compute_ldst_addr_typeb(DisasContext *dc, int 
ra, int imm)
 #ifndef CONFIG_USER_ONLY
 static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb)
 {
-int addr_size = dc->cpu->cfg.addr_size;
+int addr_size = dc->cfg->addr_size;
 TCGv ret = tcg_temp_new();
 
 if (addr_size == 32 || ra == 0) {
@@ -772,7 +772,7 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, 
MemOp mop,
 
 if (size > MO_8 &&
 (dc->tb_flags & MSR_EE) &&
-dc->cpu->cfg.unaligned_exceptions) {
+dc->cfg->unaligned_exceptions) {
 record_unaligned_ess(dc, rd, size, false);
 mop |= MO_ALIGN;
 }
@@ -918,7 +918,7 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, 
MemOp mop,
 
 if (size > MO_8 &&
 (dc->tb_flags & MSR_EE) &&
-dc->cpu->cfg.unaligned_exceptions) {
+dc->cfg->unaligned_exceptions) {
 record_unaligned_ess(dc, rd, size, true);
 mop |= MO_ALIGN;
 }
@@ -1325,7 +1325,7 @@ DO_RTS(rtsd, 0)
 static bool trans_zero(DisasContext *dc, arg_zero *arg)
 {
 /* If opcode_0_illegal, trap.  */
-if (dc->cpu->cfg.opcode_0_illegal) {
+if (dc->cfg->opcode_0_illegal) {
 trap_illegal(dc, true);
 return true;
 }
@@ -1658,7 +1658,7 @@ static void mb_tr_init_disas_context(DisasContextBase 
*dcb, CPUState *cs)
 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 int bound;
 
-dc->cpu = cpu;
+dc->cfg = &cpu->cfg;
 dc->tb_flags = dc->base.tb->flags;
 dc->ext_imm = dc->base.tb->cs_base;
 dc->r0 = NULL;
-- 
2.25.1

[PATCH v3 11/19] target/microblaze: Diagnose invalid insns in delay slots

[Richard Henderson]

These cases result in undefined and undocumented behaviour but the
behaviour is deterministic, i.e cores will not lock-up or expose
security issues.  However, RTL will not raise exceptions either.

Therefore, log a GUEST_ERROR and treat these cases as nops, to
avoid corner cases which could put qemu into an invalid state.

Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Edgar E. Iglesias 
Signed-off-by: Richard Henderson 
---
 target/microblaze/translate.c | 48 ++-
 1 file changed, 41 insertions(+), 7 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index d98572fab9..ff0cb7dbb6 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -179,6 +179,21 @@ static bool trap_userspace(DisasContext *dc, bool cond)
 return cond_user;
 }
 
+/*
+ * Return true, and log an error, if the current insn is
+ * within a delay slot.
+ */
+static bool invalid_delay_slot(DisasContext *dc, const char *insn_type)
+{
+if (dc->tb_flags & D_FLAG) {
+qemu_log_mask(LOG_GUEST_ERROR,
+  "Invalid insn in delay slot: %s at %08x\n",
+  insn_type, (uint32_t)dc->base.pc_next);
+return true;
+}
+return false;
+}
+
 static TCGv_i32 reg_for_read(DisasContext *dc, int reg)
 {
 if (likely(reg != 0)) {
@@ -500,6 +515,9 @@ DO_TYPEA_CFG(idivu, use_div, true, gen_idivu)
 
 static bool trans_imm(DisasContext *dc, arg_imm *arg)
 {
+if (invalid_delay_slot(dc, "imm")) {
+return true;
+}
 dc->ext_imm = arg->imm << 16;
 tcg_gen_movi_i32(cpu_imm, dc->ext_imm);
 dc->tb_flags_to_set = IMM_FLAG;
@@ -1067,6 +1085,9 @@ static bool do_branch(DisasContext *dc, int dest_rb, int 
dest_imm,
 {
 uint32_t add_pc;
 
+if (invalid_delay_slot(dc, "branch")) {
+return true;
+}
 if (delay) {
 setup_dslot(dc, dest_rb < 0);
 }
@@ -1106,6 +1127,9 @@ static bool do_bcc(DisasContext *dc, int dest_rb, int 
dest_imm,
 {
 TCGv_i32 zero, next;
 
+if (invalid_delay_slot(dc, "bcc")) {
+return true;
+}
 if (delay) {
 setup_dslot(dc, dest_rb < 0);
 }
@@ -1158,6 +1182,10 @@ static bool trans_brk(DisasContext *dc, arg_typea_br 
*arg)
 if (trap_userspace(dc, true)) {
 return true;
 }
+if (invalid_delay_slot(dc, "brk")) {
+return true;
+}
+
 tcg_gen_mov_i32(cpu_pc, reg_for_read(dc, arg->rb));
 if (arg->rd) {
 tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next);
@@ -1176,6 +1204,10 @@ static bool trans_brki(DisasContext *dc, arg_typeb_br 
*arg)
 if (trap_userspace(dc, imm != 0x8 && imm != 0x18)) {
 return true;
 }
+if (invalid_delay_slot(dc, "brki")) {
+return true;
+}
+
 tcg_gen_movi_i32(cpu_pc, imm);
 if (arg->rd) {
 tcg_gen_movi_i32(cpu_R[arg->rd], dc->base.pc_next);
@@ -1216,6 +1248,11 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *arg)
 {
 int mbar_imm = arg->imm;
 
+/* Note that mbar is a specialized branch instruction. */
+if (invalid_delay_slot(dc, "mbar")) {
+return true;
+}
+
 /* Data access memory barrier.  */
 if ((mbar_imm & 2) == 0) {
 tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
@@ -1263,6 +1300,10 @@ static bool do_rts(DisasContext *dc, arg_typeb_bc *arg, 
int to_set)
 if (trap_userspace(dc, to_set)) {
 return true;
 }
+if (invalid_delay_slot(dc, "rts")) {
+return true;
+}
+
 dc->tb_flags_to_set |= to_set;
 setup_dslot(dc, true);
 
@@ -1695,7 +1736,6 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, 
CPUState *cs)
 if (dc->jmp_cond != TCG_COND_NEVER && !(dc->tb_flags & D_FLAG)) {
 /*
  * Finish any return-from branch.
- * TODO: Diagnose rtXd in delay slot of rtYd earlier.
  */
 uint32_t rt_ibe = dc->tb_flags & (DRTI_FLAG | DRTB_FLAG | DRTE_FLAG);
 if (unlikely(rt_ibe != 0)) {
@@ -1717,12 +1757,6 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, 
CPUState *cs)
  * and will handle D_FLAG in mb_cpu_do_interrupt.
  */
 break;
-case DISAS_EXIT:
-/*
- * TODO: diagnose brk/brki in delay slot earlier.
- * This would then fold into the illegal insn case above.
- */
-break;
 case DISAS_NEXT:
 /*
  * Normal insn a delay slot.
-- 
2.25.1

[PATCH v3 12/19] target/microblaze: Split out MicroBlazeCPUConfig

[Richard Henderson]

This struct was previously unnamed, and defined in MicroBlazeCPU.
Pull it out to its own typedef so that we can reuse it.

Signed-off-by: Richard Henderson 
---
 target/microblaze/cpu.h | 55 ++---
 1 file changed, 29 insertions(+), 26 deletions(-)

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 20c2979396..59d2a079c4 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -291,6 +291,34 @@ struct CPUMBState {
 } pvr;
 };
 
+/*
+ * Microblaze Configuration Settings
+ */
+typedef struct {
+bool stackprot;
+uint32_t base_vectors;
+uint8_t addr_size;
+uint8_t use_fpu;
+uint8_t use_hw_mul;
+bool use_barrel;
+bool use_div;
+bool use_msr_instr;
+bool use_pcmp_instr;
+bool use_mmu;
+bool dcache_writeback;
+bool endi;
+bool dopb_bus_exception;
+bool iopb_bus_exception;
+bool illegal_opcode_exception;
+bool opcode_0_illegal;
+bool div_zero_exception;
+bool unaligned_exceptions;
+uint8_t pvr_user1;
+uint32_t pvr_user2;
+char *version;
+uint8_t pvr;
+} MicroBlazeCPUConfig;
+
 /**
  * MicroBlazeCPU:
  * @env: #CPUMBState
@@ -305,32 +333,7 @@ struct MicroBlazeCPU {
 
 CPUNegativeOffsetState neg;
 CPUMBState env;
-
-/* Microblaze Configuration Settings */
-struct {
-bool stackprot;
-uint32_t base_vectors;
-uint8_t addr_size;
-uint8_t use_fpu;
-uint8_t use_hw_mul;
-bool use_barrel;
-bool use_div;
-bool use_msr_instr;
-bool use_pcmp_instr;
-bool use_mmu;
-bool dcache_writeback;
-bool endi;
-bool dopb_bus_exception;
-bool iopb_bus_exception;
-bool illegal_opcode_exception;
-bool opcode_0_illegal;
-bool div_zero_exception;
-bool unaligned_exceptions;
-uint8_t pvr_user1;
-uint32_t pvr_user2;
-char *version;
-uint8_t pvr;
-} cfg;
+MicroBlazeCPUConfig cfg;
 };
 
 
-- 
2.25.1

[PATCH v3 13/19] target/microblaze: Reorg MicroBlazeCPUConfig to minimize holes

[Richard Henderson]

Sort the elements by type and size, removing a number of holes
and reducing the size of the entire struct.

Signed-off-by: Richard Henderson 
---
 target/microblaze/cpu.h | 15 ++-
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 59d2a079c4..4d53345f23 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -293,13 +293,22 @@ struct CPUMBState {
 
 /*
  * Microblaze Configuration Settings
+ *
+ * Note that the structure is sorted by type and size to minimize holes.
  */
 typedef struct {
-bool stackprot;
+char *version;
+
 uint32_t base_vectors;
+uint32_t pvr_user2;
+
 uint8_t addr_size;
 uint8_t use_fpu;
 uint8_t use_hw_mul;
+uint8_t pvr_user1;
+uint8_t pvr;
+
+bool stackprot;
 bool use_barrel;
 bool use_div;
 bool use_msr_instr;
@@ -313,10 +322,6 @@ typedef struct {
 bool opcode_0_illegal;
 bool div_zero_exception;
 bool unaligned_exceptions;
-uint8_t pvr_user1;
-uint32_t pvr_user2;
-char *version;
-uint8_t pvr;
 } MicroBlazeCPUConfig;
 
 /**
-- 
2.25.1

[PATCH v3 17/19] target/microblaze: Fill in VMStateDescription for cpu

[Richard Henderson]

Signed-off-by: Richard Henderson 
---
 target/microblaze/cpu.h   |   4 ++
 target/microblaze/cpu.c   |   8 +--
 target/microblaze/machine.c   | 106 ++
 target/microblaze/meson.build |   5 +-
 4 files changed, 115 insertions(+), 8 deletions(-)
 create mode 100644 target/microblaze/machine.c

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index b54f99da61..297b36879a 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -429,4 +429,8 @@ static inline int cpu_mmu_index(CPUMBState *env, bool 
ifetch)
 return MMU_KERNEL_IDX;
 }
 
+#ifndef CONFIG_USER_ONLY
+extern const VMStateDescription vmstate_mb_cpu;
+#endif
+
 #endif
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index fde646a7ad..9b2482159d 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -26,7 +26,6 @@
 #include "cpu.h"
 #include "qemu/module.h"
 #include "hw/qdev-properties.h"
-#include "migration/vmstate.h"
 #include "exec/exec-all.h"
 #include "fpu/softfloat-helpers.h"
 
@@ -251,11 +250,6 @@ static void mb_cpu_initfn(Object *obj)
 #endif
 }
 
-static const VMStateDescription vmstate_mb_cpu = {
-.name = "cpu",
-.unmigratable = 1,
-};
-
 static Property mb_properties[] = {
 DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
 DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
@@ -335,8 +329,8 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
 #ifndef CONFIG_USER_ONLY
 cc->do_transaction_failed = mb_cpu_transaction_failed;
 cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
-#endif
 dc->vmsd = &vmstate_mb_cpu;
+#endif
 device_class_set_props(dc, mb_properties);
 cc->gdb_num_core_regs = 32 + 27;
 
diff --git a/target/microblaze/machine.c b/target/microblaze/machine.c
new file mode 100644
index 00..acdb8d0474
--- /dev/null
+++ b/target/microblaze/machine.c
@@ -0,0 +1,106 @@
+/*
+ *  Microblaze VMState for qemu.
+ *
+ *  Copyright (c) 2020 Linaro, Ltd.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "migration/cpu.h"
+
+
+static VMStateField vmstate_mmu_fields[] = {
+VMSTATE_UINT64_2DARRAY(rams, MicroBlazeMMU, 2, TLB_ENTRIES),
+VMSTATE_UINT8_ARRAY(tids, MicroBlazeMMU, TLB_ENTRIES),
+VMSTATE_UINT32_ARRAY(regs, MicroBlazeMMU, 3),
+VMSTATE_END_OF_LIST()
+};
+
+static const VMStateDescription vmstate_mmu = {
+.name = "mmu",
+.version_id = 0,
+.minimum_version_id = 0,
+.fields = vmstate_mmu_fields,
+};
+
+static int get_msr(QEMUFile *f, void *opaque, size_t size,
+   const VMStateField *field)
+{
+CPUMBState *env = container_of(opaque, CPUMBState, msr);
+
+mb_cpu_write_msr(env, qemu_get_be32(f));
+return 0;
+}
+
+static int put_msr(QEMUFile *f, void *opaque, size_t size,
+   const VMStateField *field, QJSON *vmdesc)
+{
+CPUMBState *env = container_of(opaque, CPUMBState, msr);
+
+qemu_put_be32(f, mb_cpu_read_msr(env));
+return 0;
+}
+
+static const VMStateInfo vmstate_msr = {
+.name = "msr",
+.get = get_msr,
+.put = put_msr,
+};
+
+static VMStateField vmstate_env_fields[] = {
+VMSTATE_UINT32_ARRAY(regs, CPUMBState, 32),
+
+VMSTATE_UINT32(pc, CPUMBState),
+VMSTATE_SINGLE(msr, CPUMBState, 0, vmstate_msr, uint32_t),
+VMSTATE_UINT32(esr, CPUMBState),
+VMSTATE_UINT32(fsr, CPUMBState),
+VMSTATE_UINT32(btr, CPUMBState),
+VMSTATE_UINT32(edr, CPUMBState),
+VMSTATE_UINT32(slr, CPUMBState),
+VMSTATE_UINT32(shr, CPUMBState),
+VMSTATE_UINT64(ear, CPUMBState),
+
+VMSTATE_UINT32(btarget, CPUMBState),
+VMSTATE_UINT32(imm, CPUMBState),
+VMSTATE_UINT32(iflags, CPUMBState),
+
+VMSTATE_UINT32(res_val, CPUMBState),
+VMSTATE_UINTTL(res_addr, CPUMBState),
+
+VMSTATE_STRUCT(mmu, CPUMBState, 0, vmstate_mmu, MicroBlazeMMU),
+
+VMSTATE_END_OF_LIST()
+};
+
+static const VMStateDescription vmstate_env = {
+.name = "env",
+.version_id = 0,
+.minimum_version_id = 0,
+.fields = vmstate_env_fields,
+};
+
+static VMStateField vmstate_cpu_fields[] = {
+VMSTATE_CPU(),
+VMSTATE_STRUCT(env, MicroBlazeCPU, 1, vmstate_env, CPUMBState),
+VMSTATE_END_OF_LIST()
+};
+
+const VMStateDescription vmstate_mb_cpu = {
+.name = "

[PATCH v3 19/19] configure: Do not set TARGET_ABI32 for microblaze

[Richard Henderson]

In 19f27b6c2493 TARGET_ABI_LONG was reduced to 32 bits for
CONFIG_USER_ONLY.  There is no need to set this by hand; it will
now be set automatically by include/exec/user/abitypes.h.

Reported-by: Peter Maydell 
Signed-off-by: Richard Henderson 
---
 configure | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configure b/configure
index f555923311..fbe34dfbbc 100755
--- a/configure
+++ b/configure
@@ -7740,7 +7740,6 @@ case "$target_name" in
 TARGET_SYSTBL_ABI=common
 mttcg="yes"
 bflt="yes"
-echo "TARGET_ABI32=y" >> $config_target_mak
   ;;
   mips|mipsel)
 mttcg="yes"
-- 
2.25.1

[PATCH v3 16/19] target/microblaze: Move mmu parameters to MicroBlazeCPUConfig

[Richard Henderson]

The final 4 fields in MicroBlazeMMU are configuration constants.
Move them into MicroBlazeCPUConfig where they belong.

Remove the leading "c_" from the member names, as that presumably
implied "config", and that should not be explicit in the location.

Signed-off-by: Richard Henderson 
---
 target/microblaze/cpu.h|  5 +
 target/microblaze/mmu.h|  7 +--
 target/microblaze/cpu.c|  9 +
 target/microblaze/helper.c |  4 ++--
 target/microblaze/mmu.c| 30 +-
 5 files changed, 30 insertions(+), 25 deletions(-)

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index ef96f2fe02..b54f99da61 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -295,6 +295,8 @@ struct CPUMBState {
 typedef struct {
 char *version;
 
+uint64_t addr_mask;
+
 uint32_t base_vectors;
 uint32_t pvr_user2;
 uint32_t pvr_regs[13];
@@ -304,6 +306,9 @@ typedef struct {
 uint8_t use_hw_mul;
 uint8_t pvr_user1;
 uint8_t pvr;
+uint8_t mmu;
+uint8_t mmu_tlb_access;
+uint8_t mmu_zones;
 
 bool stackprot;
 bool use_barrel;
diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h
index c1feb811b9..7d0fbb8341 100644
--- a/target/microblaze/mmu.h
+++ b/target/microblaze/mmu.h
@@ -70,11 +70,6 @@ typedef struct {
 uint8_t tids[TLB_ENTRIES];
 /* Control flops.  */
 uint32_t regs[3];
-
-int c_mmu;
-int c_mmu_tlb_access;
-int c_mmu_zones;
-uint64_t c_addr_mask; /* Mask to apply to physical addresses.  */
 } MicroBlazeMMU;
 
 typedef struct {
@@ -88,7 +83,7 @@ typedef struct {
 } err;
 } MicroBlazeMMULookup;
 
-unsigned int mmu_translate(MicroBlazeMMU *mmu, MicroBlazeMMULookup *lu,
+unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
target_ulong vaddr, int rw, int mmu_idx);
 uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn);
 void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v);
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index b9bb7f0cc7..fde646a7ad 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -135,10 +135,6 @@ static void mb_cpu_reset(DeviceState *dev)
 #else
 mb_cpu_write_msr(env, 0);
 mmu_init(&env->mmu);
-env->mmu.c_mmu = 3;
-env->mmu.c_mmu_tlb_access = 3;
-env->mmu.c_mmu_zones = 16;
-env->mmu.c_addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size);
 #endif
 }
 
@@ -232,6 +228,11 @@ static void mb_cpu_realizefn(DeviceState *dev, Error 
**errp)
 cpu->cfg.pvr_regs[11] = ((cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
  16 << 17);
 
+cpu->cfg.mmu = 3;
+cpu->cfg.mmu_tlb_access = 3;
+cpu->cfg.mmu_zones = 16;
+cpu->cfg.addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size);
+
 mcc->parent_realize(dev, errp);
 }
 
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index c9f236c897..3d6ce1b31b 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -64,7 +64,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 return true;
 }
 
-hit = mmu_translate(&env->mmu, &lu, address, access_type, mmu_idx);
+hit = mmu_translate(cpu, &lu, address, access_type, mmu_idx);
 if (likely(hit)) {
 uint32_t vaddr = address & TARGET_PAGE_MASK;
 uint32_t paddr = lu.paddr + vaddr - lu.vaddr;
@@ -240,7 +240,7 @@ hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 unsigned int hit;
 
 if (mmu_idx != MMU_NOMMU_IDX) {
-hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);
+hit = mmu_translate(cpu, &lu, addr, 0, 0);
 if (hit) {
 vaddr = addr & TARGET_PAGE_MASK;
 paddr = lu.paddr + vaddr - lu.vaddr;
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 0546cfd0bc..1dbbb271c4 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -73,9 +73,10 @@ static void mmu_change_pid(CPUMBState *env, unsigned int 
newpid)
 }
 
 /* rw - 0 = read, 1 = write, 2 = fetch.  */
-unsigned int mmu_translate(MicroBlazeMMU *mmu, MicroBlazeMMULookup *lu,
+unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
target_ulong vaddr, int rw, int mmu_idx)
 {
+MicroBlazeMMU *mmu = &cpu->env.mmu;
 unsigned int i, hit = 0;
 unsigned int tlb_ex = 0, tlb_wr = 0, tlb_zsel;
 uint64_t tlb_tag, tlb_rpn, mask;
@@ -114,13 +115,13 @@ unsigned int mmu_translate(MicroBlazeMMU *mmu, 
MicroBlazeMMULookup *lu,
 t0 = mmu->regs[MMU_R_ZPR] >> (30 - (tlb_zsel * 2));
 t0 &= 0x3;
 
-if (tlb_zsel > mmu->c_mmu_zones) {
+if (tlb_zsel > cpu->cfg.mmu_zones) {
 qemu_log_mask(LOG_GUEST_ERROR,
   "tlb zone select out of range! %d\n", tlb_zsel);
 t0 = 1; /* Ignore.  */
 }
 
-if (mmu->c_mmu == 1) {
+if (cpu->cfg.mmu == 1) {
 

Re: [PATCH v3 08/16] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card

[Alistair Francis]

On Mon, Aug 31, 2020 at 6:47 PM Bin Meng  wrote:
>
> From: Bin Meng 
>
> Microchip PolarFire SoC integrates one Cadence SDHCI controller.
> On the Icicle Kit board, one eMMC chip and an external SD card
> connect to this controller depending on different configuration.
>
> As QEMU does not support eMMC yet, we just emulate the SD card
> configuration. To test this, the Hart Software Services (HSS)
> should choose the SD card configuration:
>
> $ cp boards/icicle-kit-es/def_config.sdcard .config
> $ make BOARD=icicle-kit-es
>
> The SD card image can be built from the Yocto BSP at:
> https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp
>
> Note the generated SD card image should be resized before use:
> $ qemu-img resize /path/to/sdcard.img 4G
>
> Launch QEMU with the following command:
> $ qemu-system-riscv64 -nographic -M microchip-icicle-kit -sd sdcard.img
>
> Signed-off-by: Bin Meng 

Reviewed-by: Alistair Francis 

Alistair

>
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - do not initialize TYPE_SYSBUS_SDHCI in the SoC instance_init(),
>   instead move that to the cadence_sdhci model
> - do not access generic-sdhci's state directly,
>   instead move that to the cadence_sdhci model
>
>  include/hw/riscv/microchip_pfsoc.h |  4 
>  hw/riscv/microchip_pfsoc.c | 23 +++
>  hw/riscv/Kconfig   |  1 +
>  3 files changed, 28 insertions(+)
>
> diff --git a/include/hw/riscv/microchip_pfsoc.h 
> b/include/hw/riscv/microchip_pfsoc.h
> index a5efa1d..d810ee8 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -23,6 +23,7 @@
>  #define HW_MICROCHIP_PFSOC_H
>
>  #include "hw/char/mchp_pfsoc_mmuart.h"
> +#include "hw/sd/cadence_sdhci.h"
>
>  typedef struct MicrochipPFSoCState {
>  /*< private >*/
> @@ -39,6 +40,7 @@ typedef struct MicrochipPFSoCState {
>  MchpPfSoCMMUartState *serial2;
>  MchpPfSoCMMUartState *serial3;
>  MchpPfSoCMMUartState *serial4;
> +CadenceSDHCIState sdhci;
>  } MicrochipPFSoCState;
>
>  #define TYPE_MICROCHIP_PFSOC"microchip.pfsoc"
> @@ -74,6 +76,7 @@ enum {
>  MICROCHIP_PFSOC_MMUART0,
>  MICROCHIP_PFSOC_SYSREG,
>  MICROCHIP_PFSOC_MPUCFG,
> +MICROCHIP_PFSOC_EMMC_SD,
>  MICROCHIP_PFSOC_MMUART1,
>  MICROCHIP_PFSOC_MMUART2,
>  MICROCHIP_PFSOC_MMUART3,
> @@ -85,6 +88,7 @@ enum {
>  };
>
>  enum {
> +MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
>  MICROCHIP_PFSOC_MMUART0_IRQ = 90,
>  MICROCHIP_PFSOC_MMUART1_IRQ = 91,
>  MICROCHIP_PFSOC_MMUART2_IRQ = 92,
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index cee959a..0b2e9ca 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -12,6 +12,7 @@
>   * 1) PLIC (Platform Level Interrupt Controller)
>   * 2) eNVM (Embedded Non-Volatile Memory)
>   * 3) MMUARTs (Multi-Mode UART)
> + * 4) Cadence eMMC/SDHC controller and an SD card connected to it
>   *
>   * This board currently generates devicetree dynamically that indicates at 
> least
>   * two harts and up to five harts.
> @@ -75,6 +76,7 @@ static const struct MemmapEntry {
>  [MICROCHIP_PFSOC_MMUART0] = { 0x2000, 0x1000 },
>  [MICROCHIP_PFSOC_SYSREG] =  { 0x20002000, 0x2000 },
>  [MICROCHIP_PFSOC_MPUCFG] =  { 0x20005000, 0x1000 },
> +[MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
>  [MICROCHIP_PFSOC_MMUART1] = { 0x2010, 0x1000 },
>  [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
>  [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
> @@ -111,6 +113,9 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
>  qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type",
>   TYPE_RISCV_CPU_SIFIVE_U54);
>  qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
> +
> +object_initialize_child(obj, "sd-controller", &s->sdhci,
> +TYPE_CADENCE_SDHCI);
>  }
>
>  static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
> @@ -223,6 +228,13 @@ static void microchip_pfsoc_soc_realize(DeviceState 
> *dev, Error **errp)
>  memmap[MICROCHIP_PFSOC_MPUCFG].base,
>  memmap[MICROCHIP_PFSOC_MPUCFG].size);
>
> +/* SDHCI */
> +sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp);
> +sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
> +memmap[MICROCHIP_PFSOC_EMMC_SD].base);
> +sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
> +qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ));
> +
>  /* MMUARTs */
>  s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
>  memmap[MICROCHIP_PFSOC_MMUART0].base,
> @@ -290,6 +302,7 @@ static void 
> microchip_icicle_kit_machine_init(MachineState *machine)
>  MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
>  MemoryRegion *system_memory = get_system_memory();
>

Re: [PATCH v3 07/16] hw/sd: Add Cadence SDHCI emulation

[Alistair Francis]

On Mon, Aug 31, 2020 at 6:45 PM Bin Meng  wrote:
>
> From: Bin Meng 
>
> Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible
> controller. The SDHCI compatible registers start from offset 0x200,
> which are called Slot Register Set (SRS) in its datasheet.
>
> This creates a Cadence SDHCI model built on top of the existing
> generic SDHCI model. Cadence specific Host Register Set (HRS) is
> implemented to make guest software happy.
>
> Signed-off-by: Bin Meng 
> Acked-by: Philippe Mathieu-Daudé 

I could find s apec to compare this with. Overall it looks fine in
terms of QEMU code though.

Acked-by: Alistair Francis 

>
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - change to update hw/sd/meson.build
> - change the name to "generic-sdhci" when calling object_initialize_child()
> - add a container MR to simplify out-of-bounds access checks
>
>  include/hw/sd/cadence_sdhci.h |  47 ++
>  hw/sd/cadence_sdhci.c | 193 
> ++
>  hw/sd/Kconfig |   4 +
>  hw/sd/meson.build |   1 +
>  4 files changed, 245 insertions(+)
>  create mode 100644 include/hw/sd/cadence_sdhci.h
>  create mode 100644 hw/sd/cadence_sdhci.c
>
> diff --git a/include/hw/sd/cadence_sdhci.h b/include/hw/sd/cadence_sdhci.h
> new file mode 100644
> index 000..cd8288b
> --- /dev/null
> +++ b/include/hw/sd/cadence_sdhci.h
> @@ -0,0 +1,47 @@
> +/*
> + * Cadence SDHCI emulation
> + *
> + * Copyright (c) 2020 Wind River Systems, Inc.
> + *
> + * Author:
> + *   Bin Meng 
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see .
> + */
> +
> +#ifndef CADENCE_SDHCI_H
> +#define CADENCE_SDHCI_H
> +
> +#include "hw/sd/sdhci.h"
> +
> +#define CADENCE_SDHCI_REG_SIZE  0x100
> +#define CADENCE_SDHCI_NUM_REGS  (CADENCE_SDHCI_REG_SIZE / sizeof(uint32_t))
> +
> +typedef struct CadenceSDHCIState {
> +SysBusDevice parent;
> +
> +MemoryRegion container;
> +MemoryRegion iomem;
> +BusState *bus;
> +
> +uint32_t regs[CADENCE_SDHCI_NUM_REGS];
> +
> +SDHCIState sdhci;
> +} CadenceSDHCIState;
> +
> +#define TYPE_CADENCE_SDHCI  "cadence.sdhci"
> +#define CADENCE_SDHCI(obj)  OBJECT_CHECK(CadenceSDHCIState, (obj), \
> + TYPE_CADENCE_SDHCI)
> +
> +#endif /* CADENCE_SDHCI_H */
> diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c
> new file mode 100644
> index 000..0b371c8
> --- /dev/null
> +++ b/hw/sd/cadence_sdhci.c
> @@ -0,0 +1,193 @@
> +/*
> + * Cadence SDHCI emulation
> + *
> + * Copyright (c) 2020 Wind River Systems, Inc.
> + *
> + * Author:
> + *   Bin Meng 
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see .
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/bitops.h"
> +#include "qemu/error-report.h"
> +#include "qemu/log.h"
> +#include "qapi/error.h"
> +#include "migration/vmstate.h"
> +#include "hw/irq.h"
> +#include "hw/sd/cadence_sdhci.h"
> +#include "sdhci-internal.h"
> +
> +/* HRS - Host Register Set (specific to Cadence) */
> +
> +#define CADENCE_SDHCI_HRS00 0x00/* general information */
> +#define CADENCE_SDHCI_HRS00_SWR BIT(0)
> +#define CADENCE_SDHCI_HRS00_POR_VAL 0x0001
> +
> +#define CADENCE_SDHCI_HRS04 0x10/* PHY access port */
> +#define CADENCE_SDHCI_HRS04_WR  BIT(24)
> +#define CADENCE_SDHCI_HRS04_RD  BIT(25)
> +#define CADENCE_SDHCI_HRS04_ACK BIT(26)
> +
> +#define CADENCE_SDHCI_HRS06 0x18/* eMMC control */
> +#define CADENCE_SDHCI_HRS06_TUNE_UP BIT(15)

Just for future the REGISTER and FILED macros are useful here.

Alistair

> +
> +/* SRS - Slot Register Set (SDHCI-compatible) */
> +
> +#define CADENCE_SDHCI_SRS_BASE  0x2

Re: [PATCH v3 10/16] hw/riscv: microchip_pfsoc: Connect a DMA controller

[Alistair Francis]

On Mon, Aug 31, 2020 at 6:49 PM Bin Meng  wrote:
>
> From: Bin Meng 
>
> On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA
> controller to move the 2nd stage bootloader in the system memory.
> Let's connect a DMA controller to Microchip PolarFire SoC.
>
> Signed-off-by: Bin Meng 

Reviewed-by: Alistair Francis 

Alistair

>
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - connect 8 IRQs to the PLIC
>
>  include/hw/riscv/microchip_pfsoc.h | 11 +++
>  hw/riscv/microchip_pfsoc.c | 15 +++
>  hw/riscv/Kconfig   |  1 +
>  3 files changed, 27 insertions(+)
>
> diff --git a/include/hw/riscv/microchip_pfsoc.h 
> b/include/hw/riscv/microchip_pfsoc.h
> index d810ee8..63e7860 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -23,6 +23,7 @@
>  #define HW_MICROCHIP_PFSOC_H
>
>  #include "hw/char/mchp_pfsoc_mmuart.h"
> +#include "hw/dma/sifive_pdma.h"
>  #include "hw/sd/cadence_sdhci.h"
>
>  typedef struct MicrochipPFSoCState {
> @@ -40,6 +41,7 @@ typedef struct MicrochipPFSoCState {
>  MchpPfSoCMMUartState *serial2;
>  MchpPfSoCMMUartState *serial3;
>  MchpPfSoCMMUartState *serial4;
> +SiFivePDMAState dma;
>  CadenceSDHCIState sdhci;
>  } MicrochipPFSoCState;
>
> @@ -71,6 +73,7 @@ enum {
>  MICROCHIP_PFSOC_BUSERR_UNIT4,
>  MICROCHIP_PFSOC_CLINT,
>  MICROCHIP_PFSOC_L2CC,
> +MICROCHIP_PFSOC_DMA,
>  MICROCHIP_PFSOC_L2LIM,
>  MICROCHIP_PFSOC_PLIC,
>  MICROCHIP_PFSOC_MMUART0,
> @@ -88,6 +91,14 @@ enum {
>  };
>
>  enum {
> +MICROCHIP_PFSOC_DMA_IRQ0 = 5,
> +MICROCHIP_PFSOC_DMA_IRQ1 = 6,
> +MICROCHIP_PFSOC_DMA_IRQ2 = 7,
> +MICROCHIP_PFSOC_DMA_IRQ3 = 8,
> +MICROCHIP_PFSOC_DMA_IRQ4 = 9,
> +MICROCHIP_PFSOC_DMA_IRQ5 = 10,
> +MICROCHIP_PFSOC_DMA_IRQ6 = 11,
> +MICROCHIP_PFSOC_DMA_IRQ7 = 12,
>  MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
>  MICROCHIP_PFSOC_MMUART0_IRQ = 90,
>  MICROCHIP_PFSOC_MMUART1_IRQ = 91,
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 0b2e9ca..d8ec973 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -13,6 +13,7 @@
>   * 2) eNVM (Embedded Non-Volatile Memory)
>   * 3) MMUARTs (Multi-Mode UART)
>   * 4) Cadence eMMC/SDHC controller and an SD card connected to it
> + * 5) SiFive Platform DMA (Direct Memory Access Controller)
>   *
>   * This board currently generates devicetree dynamically that indicates at 
> least
>   * two harts and up to five harts.
> @@ -71,6 +72,7 @@ static const struct MemmapEntry {
>  [MICROCHIP_PFSOC_BUSERR_UNIT4] ={  0x1704000, 0x1000 },
>  [MICROCHIP_PFSOC_CLINT] =   {  0x200,0x1 },
>  [MICROCHIP_PFSOC_L2CC] ={  0x201, 0x1000 },
> +[MICROCHIP_PFSOC_DMA] = {  0x300,   0x10 },
>  [MICROCHIP_PFSOC_L2LIM] =   {  0x800,  0x200 },
>  [MICROCHIP_PFSOC_PLIC] ={  0xc00,  0x400 },
>  [MICROCHIP_PFSOC_MMUART0] = { 0x2000, 0x1000 },
> @@ -114,6 +116,9 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
>   TYPE_RISCV_CPU_SIFIVE_U54);
>  qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
>
> +object_initialize_child(obj, "dma-controller", &s->dma,
> +TYPE_SIFIVE_PDMA);
> +
>  object_initialize_child(obj, "sd-controller", &s->sdhci,
>  TYPE_CADENCE_SDHCI);
>  }
> @@ -218,6 +223,16 @@ static void microchip_pfsoc_soc_realize(DeviceState 
> *dev, Error **errp)
>  memmap[MICROCHIP_PFSOC_PLIC].size);
>  g_free(plic_hart_config);
>
> +/* DMA */
> +sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
> +sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0,
> +memmap[MICROCHIP_PFSOC_DMA].base);
> +for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
> +sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
> +   qdev_get_gpio_in(DEVICE(s->plic),
> +MICROCHIP_PFSOC_DMA_IRQ0 + i));
> +}
> +
>  /* SYSREG */
>  create_unimplemented_device("microchip.pfsoc.sysreg",
>  memmap[MICROCHIP_PFSOC_SYSREG].base,
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 7412db9..9032cb0 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -55,4 +55,5 @@ config MICROCHIP_PFSOC
>  select SIFIVE
>  select UNIMP
>  select MCHP_PFSOC_MMUART
> +select SIFIVE_PDMA
>  select CADENCE_SDHCI
> --
> 2.7.4
>
>

Re: [PATCH v3 11/16] hw/net: cadence_gem: Add a new 'phy-addr' property

[Alistair Francis]

On Mon, Aug 31, 2020 at 6:42 PM Bin Meng  wrote:
>
> From: Bin Meng 
>
> At present the PHY address of the PHY connected to GEM is hard-coded
> to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for
> all boards. Add a new 'phy-addr' property so that board can specify
> the PHY address for each GEM instance.
>
> Signed-off-by: Bin Meng 

Reviewed-by: Alistair Francis 

Alistair

>
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - change "phy-addr" default value to BOARD_PHY_ADDRESS
>
>  include/hw/net/cadence_gem.h | 2 ++
>  hw/net/cadence_gem.c | 5 +++--
>  2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
> index 54e646f..01c6189 100644
> --- a/include/hw/net/cadence_gem.h
> +++ b/include/hw/net/cadence_gem.h
> @@ -73,6 +73,8 @@ typedef struct CadenceGEMState {
>  /* Mask of register bits which are write 1 to clear */
>  uint32_t regs_w1c[CADENCE_GEM_MAXREG];
>
> +/* PHY address */
> +uint8_t phy_addr;
>  /* PHY registers backing store */
>  uint16_t phy_regs[32];
>
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index a93b5c0..d80096b 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -1446,7 +1446,7 @@ static uint64_t gem_read(void *opaque, hwaddr offset, 
> unsigned size)
>  uint32_t phy_addr, reg_num;
>
>  phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> 
> GEM_PHYMNTNC_ADDR_SHFT;
> -if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
> +if (phy_addr == s->phy_addr || phy_addr == 0) {
>  reg_num = (retval & GEM_PHYMNTNC_REG) >> 
> GEM_PHYMNTNC_REG_SHIFT;
>  retval &= 0x;
>  retval |= gem_phy_read(s, reg_num);
> @@ -1569,7 +1569,7 @@ static void gem_write(void *opaque, hwaddr offset, 
> uint64_t val,
>  uint32_t phy_addr, reg_num;
>
>  phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
> -if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
> +if (phy_addr == s->phy_addr || phy_addr == 0) {
>  reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
>  gem_phy_write(s, reg_num, val);
>  }
> @@ -1682,6 +1682,7 @@ static Property gem_properties[] = {
>  DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
>  DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
> GEM_MODID_VALUE),
> +DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, 
> BOARD_PHY_ADDRESS),
>  DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
>num_priority_queues, 1),
>  DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
> --
> 2.7.4
>
>

Re: [PATCH 08/17] hw/block/nvme: refactor aio submission

[Keith Busch]

On Fri, Sep 04, 2020 at 04:19:47PM +0200, Klaus Jensen wrote:
> diff --git a/hw/block/nvme.c b/hw/block/nvme.c
> index bfac3385cb64..3e32f39c7c1d 100644
> --- a/hw/block/nvme.c
> +++ b/hw/block/nvme.c
> @@ -110,6 +110,7 @@ static const uint32_t nvme_feature_cap[NVME_FID_MAX] = {
>  };
>  
>  static void nvme_process_sq(void *opaque);
> +static void nvme_aio_cb(void *opaque, int ret);

You don't need the forward declaration here. Just move the
implementation above where it's used. It looks safe: nvme_aio_cb()
doesn't have any circular dependencies.

Re: [PATCH v3 16/16] hw/riscv: sifive_u: Connect a DMA controller

[Alistair Francis]

On Mon, Aug 31, 2020 at 6:46 PM Bin Meng  wrote:
>
> From: Bin Meng 
>
> SiFive FU540 SoC integrates a platform DMA controller with 4 DMA
> channels. This connects the exsiting SiFive PDMA model to the SoC,
> and adds its device tree data as well.
>
> Signed-off-by: Bin Meng 

Reviewed-by: Alistair Francis 

Alistair

> ---
>
> (no changes since v1)
>
>  include/hw/riscv/sifive_u.h | 11 +++
>  hw/riscv/sifive_u.c | 30 ++
>  hw/riscv/Kconfig|  1 +
>  3 files changed, 42 insertions(+)
>
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index d3c0c00..793000a 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -19,6 +19,7 @@
>  #ifndef HW_SIFIVE_U_H
>  #define HW_SIFIVE_U_H
>
> +#include "hw/dma/sifive_pdma.h"
>  #include "hw/net/cadence_gem.h"
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_cpu.h"
> @@ -43,6 +44,7 @@ typedef struct SiFiveUSoCState {
>  SiFiveUPRCIState prci;
>  SIFIVEGPIOState gpio;
>  SiFiveUOTPState otp;
> +SiFivePDMAState dma;
>  CadenceGEMState gem;
>
>  uint32_t serial;
> @@ -72,6 +74,7 @@ enum {
>  SIFIVE_U_MROM,
>  SIFIVE_U_CLINT,
>  SIFIVE_U_L2CC,
> +SIFIVE_U_PDMA,
>  SIFIVE_U_L2LIM,
>  SIFIVE_U_PLIC,
>  SIFIVE_U_PRCI,
> @@ -108,6 +111,14 @@ enum {
>  SIFIVE_U_GPIO_IRQ13 = 20,
>  SIFIVE_U_GPIO_IRQ14 = 21,
>  SIFIVE_U_GPIO_IRQ15 = 22,
> +SIFIVE_U_PDMA_IRQ0 = 23,
> +SIFIVE_U_PDMA_IRQ1 = 24,
> +SIFIVE_U_PDMA_IRQ2 = 25,
> +SIFIVE_U_PDMA_IRQ3 = 26,
> +SIFIVE_U_PDMA_IRQ4 = 27,
> +SIFIVE_U_PDMA_IRQ5 = 28,
> +SIFIVE_U_PDMA_IRQ6 = 29,
> +SIFIVE_U_PDMA_IRQ7 = 30,
>  SIFIVE_U_GEM_IRQ = 0x35
>  };
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 2bc3992..7997537 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -14,6 +14,7 @@
>   * 4) GPIO (General Purpose Input/Output Controller)
>   * 5) OTP (One-Time Programmable) memory with stored serial number
>   * 6) GEM (Gigabit Ethernet Controller) and management block
> + * 7) DMA (Direct Memory Access Controller)
>   *
>   * This board currently generates devicetree dynamically that indicates at 
> least
>   * two harts and up to five harts.
> @@ -73,6 +74,7 @@ static const struct MemmapEntry {
>  [SIFIVE_U_MROM] = { 0x1000, 0xf000 },
>  [SIFIVE_U_CLINT] ={  0x200,0x1 },
>  [SIFIVE_U_L2CC] = {  0x201, 0x1000 },
> +[SIFIVE_U_PDMA] = {  0x300,   0x10 },
>  [SIFIVE_U_L2LIM] ={  0x800,  0x200 },
>  [SIFIVE_U_PLIC] = {  0xc00,  0x400 },
>  [SIFIVE_U_PRCI] = { 0x1000, 0x1000 },
> @@ -303,6 +305,22 @@ static void create_fdt(SiFiveUState *s, const struct 
> MemmapEntry *memmap,
>  qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
>  g_free(nodename);
>
> +nodename = g_strdup_printf("/soc/dma@%lx",
> +(long)memmap[SIFIVE_U_PDMA].base);
> +qemu_fdt_add_subnode(fdt, nodename);
> +qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
> +qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
> +SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2,
> +SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5,
> +SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
> +qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> +qemu_fdt_setprop_cells(fdt, nodename, "reg",
> +0x0, memmap[SIFIVE_U_PDMA].base,
> +0x0, memmap[SIFIVE_U_PDMA].size);
> +qemu_fdt_setprop_string(fdt, nodename, "compatible",
> +"sifive,fu540-c000-pdma");
> +g_free(nodename);
> +
>  nodename = g_strdup_printf("/soc/cache-controller@%lx",
>  (long)memmap[SIFIVE_U_L2CC].base);
>  qemu_fdt_add_subnode(fdt, nodename);
> @@ -627,6 +645,7 @@ static void sifive_u_soc_instance_init(Object *obj)
>  object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
>  object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
>  object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
> +object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
>  }
>
>  static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> @@ -730,6 +749,17 @@ static void sifive_u_soc_realize(DeviceState *dev, Error 
> **errp)
>  SIFIVE_U_GPIO_IRQ0 + i));
>  }
>
> +/* PDMA */
> +sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
> +sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_PDMA].base);
> +
> +/* Connect PDMA interrupts to the PLIC */
> +for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
> +sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
> +   qdev_get_gpio_in(DEVICE(s->plic),
> +SIFIVE_U_PDMA_IRQ0 + i));
> +}

Re: [PATCH v2 0/7] CTU CAN FD core support - patchew problem

[Paolo Bonzini]

On 04/09/20 19:31, Pavel Pisa wrote:
> Hello everybody,
> 
> On Thursday 03 of September 2020 23:37:17 p...@cmp.felk.cvut.cz wrote:
>> From: Pavel Pisa 
>>
>> CTU CAN FD is an open source soft core written in VHDL.
>> It originated in 2015 as Ondrej Ille's project at the
>> Department of Measurement of FEE at CTU.
> It seems that there has been problem with QEMU CI
> run by patchew
> 
>No space left on device
> 
> It seems it is resolved for later patches

Yes there seems to be a bug where timeouts fail to stop the
container---eventually they pile up and occupy all disk space.  I should
really just add a cron job until I figure it out.

Paolo

Re: [PATCH v3 09/16] hw/dma: Add SiFive platform DMA controller emulation

[Alistair Francis]

On Mon, Aug 31, 2020 at 6:48 PM Bin Meng  wrote:
>
> From: Bin Meng 
>
> Microchip PolarFire SoC integrates a DMA engine that supports:
> * Independent concurrent DMA transfers using 4 DMA channels
> * Generation of interrupts on various conditions during execution
> which is actually an IP reused from the SiFive FU540 chip.
>
> This creates a model to support both polling and interrupt modes.
>
> Signed-off-by: Bin Meng 

Acked-by: Alistair Francis 

Alistair

>
> ---
>
> Changes in v3:
> - change MCHP_PFSOC_DMA to SIFIVE_PDMA
>
> Changes in v2:
> - change to update hw/dma/meson.build
> - rename the file names to sifive_pdma.[c|h]
> - update irq number to 8 per the SiFive FU540 manual
> - fix the register offset for channel 1/2/3 in the read/write ops
>
>  include/hw/dma/sifive_pdma.h |  57 
>  hw/dma/sifive_pdma.c | 313 
> +++
>  hw/dma/Kconfig   |   3 +
>  hw/dma/meson.build   |   1 +
>  4 files changed, 374 insertions(+)
>  create mode 100644 include/hw/dma/sifive_pdma.h
>  create mode 100644 hw/dma/sifive_pdma.c
>
> diff --git a/include/hw/dma/sifive_pdma.h b/include/hw/dma/sifive_pdma.h
> new file mode 100644
> index 000..e319bbd
> --- /dev/null
> +++ b/include/hw/dma/sifive_pdma.h
> @@ -0,0 +1,57 @@
> +/*
> + * SiFive Platform DMA emulation
> + *
> + * Copyright (c) 2020 Wind River Systems, Inc.
> + *
> + * Author:
> + *   Bin Meng 
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see .
> + */
> +
> +#ifndef SIFIVE_PDMA_H
> +#define SIFIVE_PDMA_H
> +
> +struct sifive_pdma_chan {
> +uint32_t control;
> +uint32_t next_config;
> +uint64_t next_bytes;
> +uint64_t next_dst;
> +uint64_t next_src;
> +uint32_t exec_config;
> +uint64_t exec_bytes;
> +uint64_t exec_dst;
> +uint64_t exec_src;
> +int state;
> +};
> +
> +#define SIFIVE_PDMA_CHANS   4
> +#define SIFIVE_PDMA_IRQS(SIFIVE_PDMA_CHANS * 2)
> +#define SIFIVE_PDMA_REG_SIZE0x10
> +#define SIFIVE_PDMA_CHAN_NO(reg)((reg & (SIFIVE_PDMA_REG_SIZE - 1)) >> 
> 12)
> +
> +typedef struct SiFivePDMAState {
> +SysBusDevice parent;
> +MemoryRegion iomem;
> +qemu_irq irq[SIFIVE_PDMA_IRQS];
> +
> +struct sifive_pdma_chan chan[SIFIVE_PDMA_CHANS];
> +} SiFivePDMAState;
> +
> +#define TYPE_SIFIVE_PDMA"sifive.pdma"
> +
> +#define SIFIVE_PDMA(obj)\
> +OBJECT_CHECK(SiFivePDMAState, (obj), TYPE_SIFIVE_PDMA)
> +
> +#endif /* SIFIVE_PDMA_H */
> diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
> new file mode 100644
> index 000..e1f6fed
> --- /dev/null
> +++ b/hw/dma/sifive_pdma.c
> @@ -0,0 +1,313 @@
> +/*
> + * SiFive Platform DMA emulation
> + *
> + * Copyright (c) 2020 Wind River Systems, Inc.
> + *
> + * Author:
> + *   Bin Meng 
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see .
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/bitops.h"
> +#include "qemu/log.h"
> +#include "qapi/error.h"
> +#include "hw/hw.h"
> +#include "hw/irq.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/sysbus.h"
> +#include "migration/vmstate.h"
> +#include "sysemu/dma.h"
> +#include "hw/dma/sifive_pdma.h"
> +
> +#define DMA_CONTROL 0x000
> +#define   CONTROL_CLAIM BIT(0)
> +#define   CONTROL_RUN   BIT(1)
> +#define   CONTROL_DONE_IE   BIT(14)
> +#define   CONTROL_ERR_IEBIT(15)
> +#define   CONTROL_DONE  BIT(30)
> +#define   CONTROL_ERR   BIT(31)
> +
> +#define DMA_NEXT_CONFIG 0x004
> +#define   CONFIG_REPEAT BIT(2)
> +#define   CONFIG_ORDER  BIT(3)
> +#define   CONFIG_WRSZ_SHIFT 24
> +#define   CONFIG_RDSZ_SHIFT 28
> +#define   CONFIG_SZ_MASK0xf
> +
> +#define DMA_NEXT_BYTES  0x008
> +#define DMA_NEXT_DST0x010
> 

Re: [PATCH 08/17] hw/block/nvme: refactor aio submission

[Klaus Jensen]

On Sep  4 12:47, Keith Busch wrote:
> On Fri, Sep 04, 2020 at 04:19:47PM +0200, Klaus Jensen wrote:
> > diff --git a/hw/block/nvme.c b/hw/block/nvme.c
> > index bfac3385cb64..3e32f39c7c1d 100644
> > --- a/hw/block/nvme.c
> > +++ b/hw/block/nvme.c
> > @@ -110,6 +110,7 @@ static const uint32_t nvme_feature_cap[NVME_FID_MAX] = {
> >  };
> >  
> >  static void nvme_process_sq(void *opaque);
> > +static void nvme_aio_cb(void *opaque, int ret);
> 
> You don't need the forward declaration here. Just move the
> implementation above where it's used. It looks safe: nvme_aio_cb()
> doesn't have any circular dependencies.

You are right, of course. But it is getting a circular dependency in a
later patch. I left it there to reduce code movement later.

Re: [PATCH v3 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support

[Alistair Francis]

On Mon, Aug 31, 2020 at 6:40 PM Bin Meng  wrote:
>
> From: Bin Meng 
>
> This adds support for Microchip PolarFire SoC Icicle Kit board.
> The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
> E51 plus four U54 cores and many on-chip peripherals and an FPGA.
>
> For more details about Microchip PolarFire SoC, please see:
> https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
>
> The Icicle Kit board information can be found here:
> https://www.microsemi.com/existing-parts/parts/152514
>
> Unlike SiFive FU540, the RISC-V core resect vector is at 0x2022.
> The RISC-V CPU and HART codes has been updated to set the core's
> reset vector based on a configurable property from machine codes.
>
> The following perepherals are created as an unimplemented device:
>
> - Bus Error Uint 0/1/2/3/4
> - L2 cache controller
> - SYSREG
> - MPUCFG
> - IOSCBCFG
> - GPIO
>
> The following perepherals are emulated:
> - SiFive CLINT
> - SiFive PLIC
> - PolarFire SoC Multi-Mode UART
> - SiFive PDMA
> - Cadence eMMC/SDHCI controller
> - Cadence Gigabit Ethernet MAC
>
> The BIOS image used by this machine is hss.bin, aka Hart Software
> Services, which can be built from:
> https://github.com/polarfire-soc/hart-software-services
>
> To launch this machine:
> $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
> -bios path/to/hss.bin -sd path/to/sdcard.img \
> -nic tap,ifname=tap,script=no,model=cadence_gem \
> -display none -serial stdio \
> -chardev socket,id=serial1,path=serial1.sock,server,wait \
> -serial chardev:serial1
>
> The memory is set to 1 GiB by default to match the hardware.
> A sanity check on ram size is performed in the machine init routine
> to prompt user to increase the RAM size to > 1 GiB when less than
> 1 GiB ram is detected.
>
> HSS output is on the first serial port (stdio) and U-Boot/Linux
> outputs on the 2nd serial port. OpenSBI outputs on a random serial
> port due to the lottery mechanism used during the multi-core boot.
>
> Please check the QEMU WiKi page for the target specific information:
> https://wiki.qemu.org/Documentation/Platforms/RISCV#Microchip_PolarFire_SoC_Icicle_Kit
>
> Changes in v3:
> - rebase on qemu/master
> - change MCHP_PFSOC_DMA to SIFIVE_PDMA
> - use the correct (Object *) to set the 'phy-addr' in xlnx-zynqmp.c
>
> Changes in v2:
> - change to update hw/char/meson.build
> - add impl.min_access_size and impl.max_access_size as part of
>   MemoryRegionOps and remove the allignment check
> - change to update hw/sd/meson.build
> - change the name to "generic-sdhci" when calling object_initialize_child()
> - add a container MR to simplify out-of-bounds access checks
> - do not initialize TYPE_SYSBUS_SDHCI in the SoC instance_init(),
>   instead move that to the cadence_sdhci model
> - do not access generic-sdhci's state directly,
>   instead move that to the cadence_sdhci model
> - change to update hw/dma/meson.build
> - rename the file names to sifive_pdma.[c|h]
> - update irq number to 8 per the SiFive FU540 manual
> - fix the register offset for channel 1/2/3 in the read/write ops
> - connect 8 IRQs to the PLIC
> - change "phy-addr" default value to BOARD_PHY_ADDRESS
>
> Bin Meng (16):
>   target/riscv: cpu: Add a new 'resetvec' property
>   hw/riscv: hart: Add a new 'resetvec' property
>   target/riscv: cpu: Set reset vector based on the configured property
> value
>   hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board
>   hw/char: Add Microchip PolarFire SoC MMUART emulation
>   hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
>   hw/sd: Add Cadence SDHCI emulation
>   hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an
> SD card
>   hw/dma: Add SiFive platform DMA controller emulation
>   hw/riscv: microchip_pfsoc: Connect a DMA controller
>   hw/net: cadence_gem: Add a new 'phy-addr' property
>   hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
>   hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
>   hw/riscv: microchip_pfsoc: Hook GPIO controllers
>   hw/riscv: clint: Avoid using hard-coded timebase frequency
>   hw/riscv: sifive_u: Connect a DMA controller

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  default-configs/riscv64-softmmu.mak |   1 +
>  include/hw/char/mchp_pfsoc_mmuart.h |  61 +
>  include/hw/dma/sifive_pdma.h|  57 +
>  include/hw/net/cadence_gem.h|   2 +
>  include/hw/riscv/microchip_pfsoc.h  | 133 +++
>  include/hw/riscv/riscv_hart.h   |   1 +
>  include/hw/riscv/sifive_clint.h |   4 +-
>  include/hw/riscv/sifive_u.h |  11 +
>  include/hw/sd/cadence_sdhci.h   |  47 
>  target/riscv/cpu.h  |   7 +-
>  hw/arm/xilinx_zynq.c|   1 +
>  hw/arm/xlnx-versal.c|   1 +
>  hw/arm/xlnx-zynqmp.c|   2 +
>  hw/char/mchp_pfsoc_mmuart.c |  86 +++
>  hw/dma/sifive_pdma.c| 313 ++

Re: [PATCH 08/17] hw/block/nvme: refactor aio submission

[Keith Busch]

On Fri, Sep 04, 2020 at 10:38:39PM +0200, Klaus Jensen wrote:
> On Sep  4 12:47, Keith Busch wrote:
> > On Fri, Sep 04, 2020 at 04:19:47PM +0200, Klaus Jensen wrote:
> > > diff --git a/hw/block/nvme.c b/hw/block/nvme.c
> > > index bfac3385cb64..3e32f39c7c1d 100644
> > > --- a/hw/block/nvme.c
> > > +++ b/hw/block/nvme.c
> > > @@ -110,6 +110,7 @@ static const uint32_t nvme_feature_cap[NVME_FID_MAX] 
> > > = {
> > >  };
> > >  
> > >  static void nvme_process_sq(void *opaque);
> > > +static void nvme_aio_cb(void *opaque, int ret);
> > 
> > You don't need the forward declaration here. Just move the
> > implementation above where it's used. It looks safe: nvme_aio_cb()
> > doesn't have any circular dependencies.
> 
> You are right, of course. But it is getting a circular dependency in a
> later patch. I left it there to reduce code movement later.

Is that coming in a future patch? Not finding it in this series.

About the whole patch in general, are multiple aio's per-request coming
in later patch as well? I didn't see any use for it here, and the
overhead of dynamic allocation and zeroing a new struct in the IO path
is a bit concerning for performance. I'd like to see your intended use
for this.

Re: [PATCH 08/17] hw/block/nvme: refactor aio submission

[Klaus Jensen]

On Sep  4 14:15, Keith Busch wrote:
> On Fri, Sep 04, 2020 at 10:38:39PM +0200, Klaus Jensen wrote:
> > On Sep  4 12:47, Keith Busch wrote:
> > > On Fri, Sep 04, 2020 at 04:19:47PM +0200, Klaus Jensen wrote:
> > > > diff --git a/hw/block/nvme.c b/hw/block/nvme.c
> > > > index bfac3385cb64..3e32f39c7c1d 100644
> > > > --- a/hw/block/nvme.c
> > > > +++ b/hw/block/nvme.c
> > > > @@ -110,6 +110,7 @@ static const uint32_t 
> > > > nvme_feature_cap[NVME_FID_MAX] = {
> > > >  };
> > > >  
> > > >  static void nvme_process_sq(void *opaque);
> > > > +static void nvme_aio_cb(void *opaque, int ret);
> > > 
> > > You don't need the forward declaration here. Just move the
> > > implementation above where it's used. It looks safe: nvme_aio_cb()
> > > doesn't have any circular dependencies.
> > 
> > You are right, of course. But it is getting a circular dependency in a
> > later patch. I left it there to reduce code movement later.
> 
> Is that coming in a future patch? Not finding it in this series.
> 
> About the whole patch in general, are multiple aio's per-request coming
> in later patch as well? I didn't see any use for it here, and the
> overhead of dynamic allocation and zeroing a new struct in the IO path
> is a bit concerning for performance. I'd like to see your intended use
> for this.

Intended use-case was parallel aios. There are a lot of use cases for
this, DSM, metadata, block allocation tracking and zns zoneinfo.

But I'll rip it out of the series and repost so we can focus on multiple
namespaces.

Re: [PATCH v3 14/15] tests: bump avocado version

[Cleber Rosa]

On Wed, Sep 02, 2020 at 11:17:08AM +0300, Pavel Dovgalyuk wrote:
> From: Pavel Dovgalyuk 
> 
> Reverse debugging test uses gdb remote client of avocado framework.
> This client was fixed since the currently used version 76.
> Therefore this patch bumps the version to 81 and fixes command
> line version compatibility issue.
> 
> Signed-off-by: Pavel Dovgalyuk 
> ---
>  tests/Makefile.include |2 +-
>  tests/requirements.txt |2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>

I'm queuing this patch on my queue.  Thanks!

Reviewed-by: Cleber Rosa 
Tested-by: Cleber Rosa 


signature.asc
Description: PGP signature

Re: [PATCH v8 02/14] hw/misc: Add NPCM7xx Clock Controller device model

[Havard Skinnemoen]

On Fri, Sep 4, 2020 at 2:32 AM Philippe Mathieu-Daudé  wrote:
>
> On 8/25/20 2:16 AM, Havard Skinnemoen via wrote:
> > Enough functionality to boot the Linux kernel has been implemented. This
> > includes:
> >
> >   - Correct power-on reset values so the various clock rates can be
> > accurately calculated.
> >   - Clock enables stick around when written.
> >
> > In addition, a best effort attempt to implement SECCNT and CNTR25M was
> > made even though I don't think the kernel needs them.
> >
> > Reviewed-by: Tyrone Ting 
> > Reviewed-by: Joel Stanley 
> > Reviewed-by: Cédric Le Goater 
> > Signed-off-by: Havard Skinnemoen 
> > ---
> >  include/hw/misc/npcm7xx_clk.h |  48 ++
> >  hw/misc/npcm7xx_clk.c | 266 ++
> >  hw/misc/meson.build   |   1 +
> >  hw/misc/trace-events  |   4 +
> >  4 files changed, 319 insertions(+)
> >  create mode 100644 include/hw/misc/npcm7xx_clk.h
> >  create mode 100644 hw/misc/npcm7xx_clk.c
> >
> > diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
> > new file mode 100644
> > index 00..cdcc9e8534
> > --- /dev/null
> > +++ b/include/hw/misc/npcm7xx_clk.h
> > @@ -0,0 +1,48 @@
> > +/*
> > + * Nuvoton NPCM7xx Clock Control Registers.
> > + *
> > + * Copyright 2020 Google LLC
> > + *
> > + * This program is free software; you can redistribute it and/or modify it
> > + * under the terms of the GNU General Public License as published by the
> > + * Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful, but 
> > WITHOUT
> > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
> > + * for more details.
> > + */
> > +#ifndef NPCM7XX_CLK_H
> > +#define NPCM7XX_CLK_H
> > +
> > +#include "exec/memory.h"
> > +#include "hw/sysbus.h"
> > +
> > +/*
> > + * The reference clock frequency for the timer modules, and the SECCNT and
> > + * CNTR25M registers in this module, is always 25 MHz.
> > + */
> > +#define NPCM7XX_TIMER_REF_HZ(2500)
> > +
> > +/*
> > + * Number of registers in our device state structure. Don't change this 
> > without
> > + * incrementing the version_id in the vmstate.
> > + */
> > +#define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t))
> > +
> > +typedef struct NPCM7xxCLKState {
> > +SysBusDevice parent;
> > +
> > +MemoryRegion iomem;
> > +
> > +uint32_t regs[NPCM7XX_CLK_NR_REGS];
> > +
> > +/* Time reference for SECCNT and CNTR25M, initialized by power on 
> > reset */
> > +int64_t ref_ns;
> > +} NPCM7xxCLKState;
> > +
> > +#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
> > +#define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), 
> > TYPE_NPCM7XX_CLK)
> > +
> > +#endif /* NPCM7XX_CLK_H */
> > diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
> > new file mode 100644
> > index 00..21ab4200d1
> > --- /dev/null
> > +++ b/hw/misc/npcm7xx_clk.c
> > @@ -0,0 +1,266 @@
> > +/*
> > + * Nuvoton NPCM7xx Clock Control Registers.
> > + *
> > + * Copyright 2020 Google LLC
> > + *
> > + * This program is free software; you can redistribute it and/or modify it
> > + * under the terms of the GNU General Public License as published by the
> > + * Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful, but 
> > WITHOUT
> > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
> > + * for more details.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +
> > +#include "hw/misc/npcm7xx_clk.h"
> > +#include "migration/vmstate.h"
> > +#include "qemu/error-report.h"
> > +#include "qemu/log.h"
> > +#include "qemu/module.h"
> > +#include "qemu/timer.h"
> > +#include "qemu/units.h"
> > +#include "trace.h"
> > +
> > +#define PLLCON_LOKI BIT(31)
> > +#define PLLCON_LOKS BIT(30)
> > +#define PLLCON_PWDENBIT(12)
> > +
> > +enum NPCM7xxCLKRegisters {
> > +NPCM7XX_CLK_CLKEN1,
> > +NPCM7XX_CLK_CLKSEL,
> > +NPCM7XX_CLK_CLKDIV1,
> > +NPCM7XX_CLK_PLLCON0,
> > +NPCM7XX_CLK_PLLCON1,
> > +NPCM7XX_CLK_SWRSTR,
> > +NPCM7XX_CLK_IPSRST1 = 0x20 / sizeof(uint32_t),
> > +NPCM7XX_CLK_IPSRST2,
> > +NPCM7XX_CLK_CLKEN2,
> > +NPCM7XX_CLK_CLKDIV2,
> > +NPCM7XX_CLK_CLKEN3,
> > +NPCM7XX_CLK_IPSRST3,
> > +NPCM7XX_CLK_WD0RCR,
> > +NPCM7XX_CLK_WD1RCR,
> > +NPCM7XX_CLK_WD2RCR,
> > +NPCM7XX_CLK_SWRSTC1,
> > +NPCM7XX_CLK_SWRSTC2,
> > +NPCM7XX_CLK_SWRSTC3,
> > +NPCM7XX_CLK_SWRSTC4,
> > +NPCM7XX_CLK_PLLCON2,
> > +NPCM7XX_CLK_CLKDIV3,
> > +NPCM7XX_CLK_CORSTC,
> > +NPCM7XX_CLK_PLLCONG,
> > +NPCM7XX_CLK_AHBCKFI,
> > +NPCM7

Re: [PULL 0/9] Linux user for 5.2 patches

[Peter Maydell]

On Thu, 3 Sep 2020 at 00:28, Laurent Vivier  wrote:
>
> The following changes since commit 887adde81d1f1f3897f1688d37ec6851b4fdad86:
>
>   Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' int=
> o staging (2020-09-01 22:50:23 +0100)
>
> are available in the Git repository at:
>
>   git://github.com/vivier/qemu.git tags/linux-user-for-5.2-pull-request
>
> for you to fetch changes up to 9a5a5a05523651d4c887388a6e0d0e446ffb279d:
>
>   linux-user: Add support for btrfs ioctls used to scrub a filesystem (2020-0=
> 9-03 01:09:35 +0200)
>
> 
> Add btrfs support
> Fix MK_ARRAY()
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.2
for any user-visible changes.

-- PMM

Re: [PATCH v8 02/14] hw/misc: Add NPCM7xx Clock Controller device model

[Havard Skinnemoen]

On Fri, Sep 4, 2020 at 3:02 PM Havard Skinnemoen  wrote:
>
> On Fri, Sep 4, 2020 at 2:32 AM Philippe Mathieu-Daudé  wrote:
> >
> > On 8/25/20 2:16 AM, Havard Skinnemoen via wrote:
> > > Enough functionality to boot the Linux kernel has been implemented. This
> > > includes:
> > >
> > >   - Correct power-on reset values so the various clock rates can be
> > > accurately calculated.
> > >   - Clock enables stick around when written.
> > >
> > > In addition, a best effort attempt to implement SECCNT and CNTR25M was
> > > made even though I don't think the kernel needs them.
> > >
> > > Reviewed-by: Tyrone Ting 
> > > Reviewed-by: Joel Stanley 
> > > Reviewed-by: Cédric Le Goater 
> > > Signed-off-by: Havard Skinnemoen 
> > > ---
> > >  include/hw/misc/npcm7xx_clk.h |  48 ++
> > >  hw/misc/npcm7xx_clk.c | 266 ++
> > >  hw/misc/meson.build   |   1 +
> > >  hw/misc/trace-events  |   4 +
> > >  4 files changed, 319 insertions(+)
> > >  create mode 100644 include/hw/misc/npcm7xx_clk.h
> > >  create mode 100644 hw/misc/npcm7xx_clk.c
> > >
> > > diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
> > > new file mode 100644
> > > index 00..cdcc9e8534
> > > --- /dev/null
> > > +++ b/include/hw/misc/npcm7xx_clk.h
> > > @@ -0,0 +1,48 @@
> > > +/*
> > > + * Nuvoton NPCM7xx Clock Control Registers.
> > > + *
> > > + * Copyright 2020 Google LLC
> > > + *
> > > + * This program is free software; you can redistribute it and/or modify 
> > > it
> > > + * under the terms of the GNU General Public License as published by the
> > > + * Free Software Foundation; either version 2 of the License, or
> > > + * (at your option) any later version.
> > > + *
> > > + * This program is distributed in the hope that it will be useful, but 
> > > WITHOUT
> > > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
> > > + * for more details.
> > > + */
> > > +#ifndef NPCM7XX_CLK_H
> > > +#define NPCM7XX_CLK_H
> > > +
> > > +#include "exec/memory.h"
> > > +#include "hw/sysbus.h"
> > > +
> > > +/*
> > > + * The reference clock frequency for the timer modules, and the SECCNT 
> > > and
> > > + * CNTR25M registers in this module, is always 25 MHz.
> > > + */
> > > +#define NPCM7XX_TIMER_REF_HZ(2500)
> > > +
> > > +/*
> > > + * Number of registers in our device state structure. Don't change this 
> > > without
> > > + * incrementing the version_id in the vmstate.
> > > + */
> > > +#define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t))
> > > +
> > > +typedef struct NPCM7xxCLKState {
> > > +SysBusDevice parent;
> > > +
> > > +MemoryRegion iomem;
> > > +
> > > +uint32_t regs[NPCM7XX_CLK_NR_REGS];
> > > +
> > > +/* Time reference for SECCNT and CNTR25M, initialized by power on 
> > > reset */
> > > +int64_t ref_ns;
> > > +} NPCM7xxCLKState;
> > > +
> > > +#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
> > > +#define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), 
> > > TYPE_NPCM7XX_CLK)
> > > +
> > > +#endif /* NPCM7XX_CLK_H */
> > > diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
> > > new file mode 100644
> > > index 00..21ab4200d1
> > > --- /dev/null
> > > +++ b/hw/misc/npcm7xx_clk.c
> > > @@ -0,0 +1,266 @@
> > > +/*
> > > + * Nuvoton NPCM7xx Clock Control Registers.
> > > + *
> > > + * Copyright 2020 Google LLC
> > > + *
> > > + * This program is free software; you can redistribute it and/or modify 
> > > it
> > > + * under the terms of the GNU General Public License as published by the
> > > + * Free Software Foundation; either version 2 of the License, or
> > > + * (at your option) any later version.
> > > + *
> > > + * This program is distributed in the hope that it will be useful, but 
> > > WITHOUT
> > > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
> > > + * for more details.
> > > + */
> > > +
> > > +#include "qemu/osdep.h"
> > > +
> > > +#include "hw/misc/npcm7xx_clk.h"
> > > +#include "migration/vmstate.h"
> > > +#include "qemu/error-report.h"
> > > +#include "qemu/log.h"
> > > +#include "qemu/module.h"
> > > +#include "qemu/timer.h"
> > > +#include "qemu/units.h"
> > > +#include "trace.h"
> > > +
> > > +#define PLLCON_LOKI BIT(31)
> > > +#define PLLCON_LOKS BIT(30)
> > > +#define PLLCON_PWDENBIT(12)
> > > +
> > > +enum NPCM7xxCLKRegisters {
> > > +NPCM7XX_CLK_CLKEN1,
> > > +NPCM7XX_CLK_CLKSEL,
> > > +NPCM7XX_CLK_CLKDIV1,
> > > +NPCM7XX_CLK_PLLCON0,
> > > +NPCM7XX_CLK_PLLCON1,
> > > +NPCM7XX_CLK_SWRSTR,
> > > +NPCM7XX_CLK_IPSRST1 = 0x20 / sizeof(uint32_t),
> > > +NPCM7XX_CLK_IPSRST2,
> > > +NPCM7XX_CLK_CLKEN2,
> > > +NPCM7XX_CLK_CLKDIV2,
> > > +NPCM7XX_CLK_CLKEN3,
> > > +NPCM7XX_CLK_IPSRST3,
> > > +NPCM7XX_C

[REPORT] Nightly Performance Tests - Friday, September 4, 2020

[Ahmed Karaman]

Host CPU : Intel(R) Core(TM) i7-8750H CPU @ 2.20GHz
Host Memory  : 15.49 GB

Start Time (UTC) : 2020-09-04 22:30:01
End Time (UTC)   : 2020-09-04 23:02:43
Execution Time   : 0:32:41.137532

Status   : SUCCESS

Note:
Changes denoted by '-' are less than 0.01%.


SUMMARY REPORT - COMMIT 1133ce5e

AVERAGE RESULTS

Target  Instructions  Latest  v5.1.0
--    --  --
aarch642 158 367 875   - +1.694%
alpha  1 914 974 588   - +3.525%
arm8 076 537 577   - +2.308%
hppa   4 261 662 168   - +3.163%
m68k   2 690 308 642   - +7.135%
mips   1 862 063 208   - +2.496%
mipsel 2 008 248 016   - +2.676%
mips64 1 918 630 831   - +2.818%
mips64el   2 051 549 551   - +3.025%
ppc2 480 175 842   -  +3.11%
ppc64  2 576 710 679   - +3.142%
ppc64le2 558 859 780   - +3.173%
riscv641 406 726 829   - +2.652%
s390x  3 158 144 397   - +3.119%
sh42 364 478 176   - +3.333%
sparc643 318 820 841   - +3.861%
x86_64 1 775 814 279   - +2.157%


   DETAILED RESULTS

Test Program: dijkstra_double

Target  Instructions  Latest  v5.1.0
--    --  --
aarch643 062 601 310   - +1.424%
alpha  3 191 872 263   - +3.696%
arm   16 357 308 169   - +2.348%
hppa   7 228 377 660   - +3.086%
m68k   4 294 075 336   - +9.693%
mips   3 051 477 273   - +2.429%
mipsel 3 231 556 258   -  +2.87%
mips64 3 245 819 354   - +2.596%
mips64el   3 414 210 464   - +3.021%
ppc4 914 559 526   -  +4.74%
ppc64  5 098 149 082   - +4.565%
ppc64le5 082 423 403   -  +4.58%
riscv642 192 311 866   - +1.956%
s390x  4 584 593 271   - +2.898%
sh43 949 069 035   - +3.465%
sparc644 586 226 389   - +4.238%
x86_64 2 484 119 875   - +1.752%


Test Program: dijkstra_int32

Target  Instructions  Latest  v5.1.0
--    --  --
aarch642 210 216 374   - +1.494%
alpha  1 494 141 041   - +2.151%
arm8 263 052 939   - +2.667%
hppa   5 207 295 529   - +3.046%
m68k   1 725 893 071   - +2.529%
mips   1 495 267 687   - +1.495%
mipsel 1 497 173 485   - +1.481%
mips64 1 715 426 577   - +1.894%
mips64el   1 695 203 694   - +1.909%
ppc2 014 602 248   - +1.822%
ppc64  2 206 265 317   - +2.138%
ppc64le2 198 007 387   - +2.146%
riscv641 354 920 226   - +2.396%
s390x  2 916 101 653   - +1.236%
sh41 990 565 618   - +2.671%
sparc642 874 262 720   - +3.831%
x86_64 1 554 012 507   - +2.122%


Test Program: matmult_double

Target  Instructions  Latest  v5.1.0
--    --  --
aarch641 412 273 280   - +0.302%
alpha  3 233 996 524   - +7.473%
arm8 545 311 371   -  +1.09%
hppa   3 483 506 390   - +4.466%
m68k   3 919 126 809   -+18.433%
mips   2 344 804 626   - +4.092%
mipsel 3 329 929 173   - +5.178%
mips64 2 359 036 928   - +4.075%
mips

Re: [PATCH v5 1/4] Add the NVMM vcpu API

[Kamil Rytarowski]

Ping?

On 11.08.2020 15:01, Kamil Rytarowski wrote:
> From: Maxime Villard 
> 
> Adds support for the NetBSD Virtual Machine Monitor (NVMM) stubs and
> introduces the nvmm.h sysemu API for managing the vcpu scheduling and
> management.
> 
> Signed-off-by: Maxime Villard 
> Signed-off-by: Kamil Rytarowski 
> Reviewed-by: Sergio Lopez 
> Reviewed-by: Philippe Mathieu-Daudé 
> Tested-by: Jared McNeill 
> ---
>  accel/stubs/Makefile.objs |  1 +
>  accel/stubs/nvmm-stub.c   | 43 +++
>  include/sysemu/nvmm.h | 35 +++
>  3 files changed, 79 insertions(+)
>  create mode 100644 accel/stubs/nvmm-stub.c
>  create mode 100644 include/sysemu/nvmm.h
> 
> diff --git a/accel/stubs/Makefile.objs b/accel/stubs/Makefile.objs
> index bbd14e71fb..38660a0b9b 100644
> --- a/accel/stubs/Makefile.objs
> +++ b/accel/stubs/Makefile.objs
> @@ -1,6 +1,7 @@
>  obj-$(call lnot,$(CONFIG_HAX))  += hax-stub.o
>  obj-$(call lnot,$(CONFIG_HVF))  += hvf-stub.o
>  obj-$(call lnot,$(CONFIG_WHPX)) += whpx-stub.o
> +obj-$(call lnot,$(CONFIG_NVMM)) += nvmm-stub.o
>  obj-$(call lnot,$(CONFIG_KVM))  += kvm-stub.o
>  obj-$(call lnot,$(CONFIG_TCG))  += tcg-stub.o
>  obj-$(call lnot,$(CONFIG_XEN))  += xen-stub.o
> diff --git a/accel/stubs/nvmm-stub.c b/accel/stubs/nvmm-stub.c
> new file mode 100644
> index 00..c2208b84a3
> --- /dev/null
> +++ b/accel/stubs/nvmm-stub.c
> @@ -0,0 +1,43 @@
> +/*
> + * Copyright (c) 2018-2019 Maxime Villard, All rights reserved.
> + *
> + * NetBSD Virtual Machine Monitor (NVMM) accelerator stub.
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu-common.h"
> +#include "cpu.h"
> +#include "sysemu/nvmm.h"
> +
> +int nvmm_init_vcpu(CPUState *cpu)
> +{
> +return -1;
> +}
> +
> +int nvmm_vcpu_exec(CPUState *cpu)
> +{
> +return -1;
> +}
> +
> +void nvmm_destroy_vcpu(CPUState *cpu)
> +{
> +}
> +
> +void nvmm_cpu_synchronize_state(CPUState *cpu)
> +{
> +}
> +
> +void nvmm_cpu_synchronize_post_reset(CPUState *cpu)
> +{
> +}
> +
> +void nvmm_cpu_synchronize_post_init(CPUState *cpu)
> +{
> +}
> +
> +void nvmm_cpu_synchronize_pre_loadvm(CPUState *cpu)
> +{
> +}
> diff --git a/include/sysemu/nvmm.h b/include/sysemu/nvmm.h
> new file mode 100644
> index 00..10496f3980
> --- /dev/null
> +++ b/include/sysemu/nvmm.h
> @@ -0,0 +1,35 @@
> +/*
> + * Copyright (c) 2018-2019 Maxime Villard, All rights reserved.
> + *
> + * NetBSD Virtual Machine Monitor (NVMM) accelerator support.
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + */
> +
> +#ifndef QEMU_NVMM_H
> +#define QEMU_NVMM_H
> +
> +#include "config-host.h"
> +#include "qemu-common.h"
> +
> +int nvmm_init_vcpu(CPUState *);
> +int nvmm_vcpu_exec(CPUState *);
> +void nvmm_destroy_vcpu(CPUState *);
> +
> +void nvmm_cpu_synchronize_state(CPUState *);
> +void nvmm_cpu_synchronize_post_reset(CPUState *);
> +void nvmm_cpu_synchronize_post_init(CPUState *);
> +void nvmm_cpu_synchronize_pre_loadvm(CPUState *);
> +
> +#ifdef CONFIG_NVMM
> +
> +int nvmm_enabled(void);
> +
> +#else /* CONFIG_NVMM */
> +
> +#define nvmm_enabled() (0)
> +
> +#endif /* CONFIG_NVMM */
> +
> +#endif /* CONFIG_NVMM */
> --
> 2.28.0
> 

QEMU | Pipeline #186015836 has failed for master | 1133ce5e

[GitLab via]

Your pipeline has failed.

Project: QEMU ( https://gitlab.com/qemu-project/qemu )
Branch: master ( https://gitlab.com/qemu-project/qemu/-/commits/master )

Commit: 1133ce5e ( 
https://gitlab.com/qemu-project/qemu/-/commit/1133ce5ec9674d594a84fad2696adc30d292a234
 )
Commit Message: Merge remote-tracking branch 'remotes/vivier2/t...
Commit Author: Peter Maydell ( https://gitlab.com/pm215 )

Pipeline #186015836 ( 
https://gitlab.com/qemu-project/qemu/-/pipelines/186015836 ) triggered by Alex 
Bennée ( https://gitlab.com/stsquad )
had 1 failed build.

Job #721553056 ( https://gitlab.com/qemu-project/qemu/-/jobs/721553056/raw )

Stage: test
Name: acceptance-system-fedora
Trace: 23:17:32 ERROR| 
23:17:32 ERROR| Reproduced traceback from: 
/builds/qemu-project/qemu/build/tests/venv/lib64/python3.8/site-packages/avocado/core/test.py:846
23:17:32 ERROR| Traceback (most recent call last):
23:17:32 ERROR|   File 
"/builds/qemu-project/qemu/build/tests/acceptance/avocado_qemu/__init__.py", 
line 171, in setUp
23:17:32 ERROR| self.cancel("No QEMU binary defined or found in the build 
tree")
23:17:32 ERROR|   File 
"/builds/qemu-project/qemu/build/tests/venv/lib64/python3.8/site-packages/avocado/core/test.py",
 line 1081, in cancel
23:17:32 ERROR| raise exceptions.TestCancel(message)
23:17:32 ERROR| avocado.core.exceptions.TestCancel: No QEMU binary defined or 
found in the build tree
23:17:32 ERROR| 
23:17:32 ERROR| CANCEL 
31-tests/acceptance/vnc.py:Vnc.test_change_password_requires_a_password -> 
TestCancel: No QEMU binary defined or found in the build tree
23:17:32 INFO | 
23:17:32 DEBUG| PARAMS (key=arch, path=*, default=None) => None
23:17:32 DEBUG| PARAMS (key=machine, path=*, default=None) => None
23:17:32 DEBUG| PARAMS (key=qemu_bin, path=*, default=None) => None
23:17:32 ERROR| 
23:17:32 ERROR| Reproduced traceback from: 
/builds/qemu-project/qemu/build/tests/venv/lib64/python3.8/site-packages/avocado/core/test.py:846
23:17:32 ERROR| Traceback (most recent call last):
23:17:32 ERROR|   File 
"/builds/qemu-project/qemu/build/tests/acceptance/avocado_qemu/__init__.py", 
line 171, in setUp
23:17:32 ERROR| self.cancel("No QEMU binary defined or found in the build 
tree")
23:17:32 ERROR|   File 
"/builds/qemu-project/qemu/build/tests/venv/lib64/python3.8/site-packages/avocado/core/test.py",
 line 1081, in cancel
23:17:32 ERROR| raise exceptions.TestCancel(message)
23:17:32 ERROR| avocado.core.exceptions.TestCancel: No QEMU binary defined or 
found in the build tree
23:17:32 ERROR| 
23:17:32 ERROR| CANCEL 32-tests/acceptance/vnc.py:Vnc.test_change_password -> 
TestCancel: No QEMU binary defined or found in the build tree
23:17:32 INFO | 
$ du -chs ${CI_PROJECT_DIR}/avocado-cache
323M/builds/qemu-project/qemu/avocado-cache
323Mtotal
section_end:1599261453:after_script
ERROR: Job failed: exit code 1



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Re: [PATCH] net/filter-rewriter: destroy g_hash_table in colo_rewriter_cleanup

[Li Qiang]

Pan Nengyuan  于2020年9月4日周五 下午3:23写道：
>
> s->connection_track_table forgot to destroy in colo_rewriter_cleanup. Fix it.
>
> Reported-by: Euler Robot 
> Signed-off-by: Pan Nengyuan 

Reviewed-by: Li Qiang 

> ---
>  net/filter-rewriter.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/net/filter-rewriter.c b/net/filter-rewriter.c
> index 1aaad101b6..9ff366d44f 100644
> --- a/net/filter-rewriter.c
> +++ b/net/filter-rewriter.c
> @@ -376,6 +376,8 @@ static void colo_rewriter_cleanup(NetFilterState *nf)
>  filter_rewriter_flush(nf);
>  g_free(s->incoming_queue);
>  }
> +
> +g_hash_table_destroy(s->connection_track_table);
>  }
>
>  static void colo_rewriter_setup(NetFilterState *nf, Error **errp)
> --
> 2.18.2
>
>

Re: [PATCH 1/2] hw/net/e1000e: Remove overwritten read handler for STATUS register

[Li Qiang]

Philippe Mathieu-Daudé  于2020年9月4日周五 下午9:14写道：
>
> The STATUS register readop handler is initialized first with
> the generic e1000e_mac_readreg() handler:
>
>   2861 #define e1000e_getreg(x)[x] = e1000e_mac_readreg
>   2862 typedef uint32_t (*readops)(E1000ECore *, int);
>   2863 static const readops e1000e_macreg_readops[] = {
>   
>   2919 e1000e_getreg(STATUS),
>
> Then overwritten with the specific e1000e_get_status handler:
>
>   3018 [STATUS]  = e1000e_get_status,
>
> To avoid confusion, remove the overwritten initialization.
>
> 6f3fbe4ed0 ("net: Introduce e1000e device emulation")
> Signed-off-by: Philippe Mathieu-Daudé 

Reviewed-by: Li Qiang 

> ---
>  hw/net/e1000e_core.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c
> index bcd186cac52..5170e6a4563 100644
> --- a/hw/net/e1000e_core.c
> +++ b/hw/net/e1000e_core.c
> @@ -2916,7 +2916,6 @@ static const readops e1000e_macreg_readops[] = {
>  e1000e_getreg(TSYNCRXCTL),
>  e1000e_getreg(TDH),
>  e1000e_getreg(LEDCTL),
> -e1000e_getreg(STATUS),
>  e1000e_getreg(TCTL),
>  e1000e_getreg(TDBAL),
>  e1000e_getreg(TDLEN),
> --
> 2.26.2
>
>

Re: [PATCH 2/2] hw/net/e1000e: Remove duplicated write handler for FLSWDATA register

[Li Qiang]

Philippe Mathieu-Daudé  于2020年9月4日周五 下午9:14写道：
>
> The FLSWDATA register writeop handler is initialized twice:
>
>   3067 #define e1000e_putreg(x)[x] = e1000e_mac_writereg
>   3068 typedef void (*writeops)(E1000ECore *, int, uint32_t);
>   3069 static const writeops e1000e_macreg_writeops[] = {
>   
>   3102 e1000e_putreg(FLSWDATA),
>   
>   3145 e1000e_putreg(FLSWDATA),
>
> To avoid confusion, remove the duplicated initialization.
>
> Fixes: 6f3fbe4ed0 ("net: Introduce e1000e device emulation")
> Signed-off-by: Philippe Mathieu-Daudé 

Reviewed-by: Li Qiang 

> ---
> Noticed after looking for other cases of the previous patch.
> ---
>  hw/net/e1000e_core.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c
> index 5170e6a4563..bcfd46696ff 100644
> --- a/hw/net/e1000e_core.c
> +++ b/hw/net/e1000e_core.c
> @@ -3141,7 +3141,6 @@ static const writeops e1000e_macreg_writeops[] = {
>  e1000e_putreg(RXCFGL),
>  e1000e_putreg(TSYNCRXCTL),
>  e1000e_putreg(TSYNCTXCTL),
> -e1000e_putreg(FLSWDATA),
>  e1000e_putreg(EXTCNF_SIZE),
>  e1000e_putreg(EEMNGCTL),
>  e1000e_putreg(RA),
> --
> 2.26.2
>
>

Re: hw/clock: What clock rate for virt machines?

[Palmer Dabbelt]

On Fri, 04 Sep 2020 10:52:06 PDT (-0700), alistai...@gmail.com wrote:

On Wed, Sep 2, 2020 at 12:48 PM Philippe Mathieu-Daudé  wrote:


On 9/2/20 8:18 PM, Peter Maydell wrote:
> On Wed, 2 Sep 2020 at 18:03, Philippe Mathieu-Daudé  wrote:
>>
>> On 9/2/20 6:49 PM, Peter Maydell wrote:
>>> On Wed, 2 Sep 2020 at 17:35, Philippe Mathieu-Daudé  wrote:
 Peter said "'clock' is basically meaningless for virt machines",

 I understand and agree. But how to make that explicit/obvious in
 the code, when a device expects a clock frequency/period?
>>>
>>> When a particular *device* needs a clock, then presumably
>>> it has a defined purpose for it, and we can pick a
>>> frequency for it then.
>>>
 See for example hw/riscv/virt.c, it uses the following (confusing
 to me) in virt_machine_init():

serial_mm_init(system_memory, memmap[VIRT_UART0].base,
0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
serial_hd(0), DEVICE_LITTLE_ENDIAN);
>>>
>>> In this case, the board has a model of a 16550A UART on it,
>>> which uses its input clock to determine what the actual baud
>>> rate is for particular guest settings of the divisor registers.
>>> So we need to look at:
>>>  * what does guest software expect the frequency to be?
>>
>> QEMU is supposed to model machine with no knowledge of the guest,
>> but the virt case is a particular one indeed... as it has to know
>> it is virtualized.
>>
>>>  * what is a "good" frequency which gives the guest the best
>>>possible choices of baud rate?
>>
>> I'll think about it...
>
> My guess is that guest code assumes "same frequency an
> x86 PC uses", but a risc-v person might know better...
>
> (For QEMU I think it only makes a visible difference when
> you pass a host serial port through to the guest as
> otherwise we ignore whatever baud rate the guest sets.)


I think that's the case. I suspect we just ignore whatever the guest
sets. I have never really looked into it though.


IIRC that's essentially what we do for all the clock stuff in QEMU.  Sometimes
we fake things a bit better by doing something like always instantly setting
the "clock has locked" bit pattern or snaping multipliers to something close to
viable, but I don't think it gets a whole lot better than that.


It makes a difference with low baudrates (TBH I only tested
what the firmwares I have use: 9600-8N1). No clue why (from
design PoV) but some odd fw use the time spent to display
chars to have a nicer 'user experience' (using polling).
With incorrect timing everything is displayed at once partly
scrambled.

The following devices are modeled with timers limiting the
transmit rate:

$ git grep qemu_clock_get_ns hw/char/
hw/char/cadence_uart.c:269:uint64_t new_rx_time =
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
hw/char/exynos4210_uart.c:393:
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout);
hw/char/ibex_uart.c:155:uint64_t current_time =
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);


For the Ibex UART we want  to apply back pressure on the guest (as
that's what the main OT software expects) which is why we use this. I
think most other guest software doesn't care as much.


I'd bet a bunch of embedded software blows up when the UART suddenly becomes
very fast, whether it just exposes some bug or because the programmer knows
that's how the system behaves and the software is just taking advantage of it.
While I guess we can fix what we run in to I fell like this is going to be a
losing battle in QEMU -- I guess it's an extreme case, but imagine trying to
emulate the behavior of our DDR controller (right now we just treat all the
control registers as opaque memory, they're far from that).


Alistair


hw/char/renesas_sci.c:74:if (sci->rx_next >
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
hw/char/renesas_sci.c:84:sci->rx_next =
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + sci->trtime;
hw/char/serial.c:290:s->last_xmit_ts =
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
hw/char/serial.c:899:s->last_xmit_ts =
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
hw/char/sh_serial.c:352:
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->etu);

>
> thanks
> -- PMM
>

Re: [RFC PATCH 00/12] hw: Forbid DMA write accesses to MMIO regions

[Li Qiang]

Philippe Mathieu-Daudé  于2020年9月3日周四 下午7:09写道：
>
> Hi,
>
> I'm not suppose to work on this but I couldn't sleep so kept
> wondering about this problem the whole night and eventually
> woke up to write this quickly, so comments are scarce, sorry.
>
> The first part is obvious anyway, simply pass MemTxAttrs argument.
>
> The main patch is:
> "exec/memattrs: Introduce MemTxAttrs::direct_access field".
> This way we can restrict accesses to ROM/RAM by setting the
> 'direct_access' field. Illegal accesses return MEMTX_BUS_ERROR.
>
> Next patch restrict PCI DMA accesses by setting the direct_access
> field.
>
> Finally we add an assertion for any DMA write access to indirect
> memory to kill a class of bug recently found by Alexander while
> fuzzing.
>

Hi Philippe,

I have reviewed your patches.
Your patch just deny the DMA write to MMIO for PCI device.

1. The DMA write to MMIO is allowed for P2P. Unconditionally deny
is not right I think. Maybe we can add some flag for the device as property
so the device can indicate whether it supports DMA to MMIO.
But this method needs define we should apply the restrict to
DMA to MMIO initiator or target. If the target, we need to find the
target PCI device.

2. I think the MMIO read maybe also suffers the reentrant issue If the
MMIO read handler
does complicated work.

3. As your patch just consider the PCI case. This reentrant is quite
complicated if we consider
the no-PCI the qemu_irq cases. I agree to address the PCI cases first.

Thanks,
Li Qiang



> Regards,
>
> Phil.
>
> Klaus Jensen (1):
>   pci: pass along the return value of dma_memory_rw
>
> Philippe Mathieu-Daudé (11):
>   dma: Let dma_memory_valid() take MemTxAttrs argument
>   dma: Let dma_memory_set() take MemTxAttrs argument
>   dma: Let dma_memory_rw_relaxed() take MemTxAttrs argument
>   dma: Let dma_memory_rw() take MemTxAttrs argument
>   dma: Let dma_memory_read/write() take MemTxAttrs argument
>   dma: Let dma_memory_map() take MemTxAttrs argument
>   docs/devel/loads-stores: Add regexp for DMA functions
>   dma: Let load/store DMA functions take MemTxAttrs argument
>   exec/memattrs: Introduce MemTxAttrs::direct_access field
>   hw/pci: Only allow PCI slave devices to write to direct memory
>   dma: Assert when device writes to indirect memory (such MMIO regions)
>
>  docs/devel/loads-stores.rst   |  2 ++
>  include/exec/memattrs.h   |  3 ++
>  include/hw/pci/pci.h  | 21 ++---
>  include/hw/ppc/spapr_vio.h| 26 +--
>  include/sysemu/dma.h  | 59 +--
>  dma-helpers.c | 12 ---
>  exec.c|  8 +
>  hw/arm/musicpal.c | 13 
>  hw/arm/smmu-common.c  |  3 +-
>  hw/arm/smmuv3.c   | 14 ++---
>  hw/core/generic-loader.c  |  3 +-
>  hw/display/virtio-gpu.c   |  8 +++--
>  hw/dma/pl330.c| 12 ---
>  hw/dma/sparc32_dma.c  | 16 ++
>  hw/dma/xlnx-zynq-devcfg.c |  6 ++--
>  hw/dma/xlnx_dpdma.c   | 10 +++---
>  hw/hyperv/vmbus.c |  8 +++--
>  hw/i386/amd_iommu.c   | 16 +-
>  hw/i386/intel_iommu.c | 28 ++---
>  hw/ide/ahci.c |  9 --
>  hw/ide/macio.c|  2 +-
>  hw/intc/pnv_xive.c|  7 +++--
>  hw/intc/spapr_xive.c  |  3 +-
>  hw/intc/xive.c|  7 +++--
>  hw/misc/bcm2835_property.c|  3 +-
>  hw/misc/macio/mac_dbdma.c | 10 +++---
>  hw/net/allwinner-sun8i-emac.c | 21 -
>  hw/net/ftgmac100.c| 25 +--
>  hw/net/imx_fec.c  | 32 ---
>  hw/nvram/fw_cfg.c | 16 ++
>  hw/pci-host/pnv_phb3.c|  5 +--
>  hw/pci-host/pnv_phb3_msi.c|  9 --
>  hw/pci-host/pnv_phb4.c|  7 +++--
>  hw/sd/allwinner-sdhost.c  | 14 +
>  hw/sd/sdhci.c | 35 +
>  hw/usb/hcd-dwc2.c |  8 ++---
>  hw/usb/hcd-ehci.c |  6 ++--
>  hw/usb/hcd-ohci.c | 28 ++---
>  hw/usb/libhw.c|  3 +-
>  hw/virtio/virtio.c|  6 ++--
>  trace-events  |  1 +
>  41 files changed, 334 insertions(+), 191 deletions(-)
>
> --
> 2.26.2
>
>

Re: [PATCH 1/3] pci: Let pci_dma_rw() propagate MemTxResult

[Li Qiang]

Philippe Mathieu-Daudé  于2020年9月5日周六 上午12:26写道：
>
> dma_memory_rw() returns a MemTxResult type.
> Do not discard it, return it to the caller.
>
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  include/hw/pci/pci.h | 18 --
>  1 file changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
> index a221dfb3b08..a85b0bc3c44 100644
> --- a/include/hw/pci/pci.h
> +++ b/include/hw/pci/pci.h
> @@ -785,8 +785,22 @@ static inline AddressSpace 
> *pci_get_address_space(PCIDevice *dev)
>  return &dev->bus_master_as;
>  }
>
> -static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
> - void *buf, dma_addr_t len, DMADirection dir)
> +/**
> + * pci_dma_rw: Read from or write to an address space from PCI device.
> + *
> + * Return a MemTxResult indicating whether the operation succeeded
> + * or failed (eg unassigned memory, device rejected the transaction,
> + * IOMMU fault).
> + *
> + * @dev: #PCIDevice doing the memory access
> + * @addr: address within the #PCIDevice address space
> + * @buf: buffer with the data transferred
> + * @len: the number of bytes to read or write
> + * @dir: indicates the transfer direction
> + */
> +static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
> + void *buf, dma_addr_t len,
> + DMADirection dir)
>  {
>  return dma_memory_rw(pci_get_address_space(dev), addr, buf, len,
>   dir, MEMTXATTRS_UNSPECIFIED);

Reviewed-by: Li Qiang 

> --
> 2.26.2
>
>

Re: [PATCH 2/3] pci: Let pci_dma_read() propagate MemTxResult

[Li Qiang]

Philippe Mathieu-Daudé  于2020年9月5日周六 上午12:27写道：
>
> pci_dma_rw() returns a MemTxResult type.
> Do not discard it, return it to the caller.
>
> Signed-off-by: Philippe Mathieu-Daudé 

Reviewed-by: Li Qiang 

> ---
>  include/hw/pci/pci.h | 16 ++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
> index a85b0bc3c44..bb57525dffd 100644
> --- a/include/hw/pci/pci.h
> +++ b/include/hw/pci/pci.h
> @@ -806,8 +806,20 @@ static inline MemTxResult pci_dma_rw(PCIDevice *dev, 
> dma_addr_t addr,
>   dir, MEMTXATTRS_UNSPECIFIED);
>  }
>
> -static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
> -   void *buf, dma_addr_t len)
> +/**
> + * pci_dma_read: Read from an address space from PCI device.
> + *
> + * Return a MemTxResult indicating whether the operation succeeded
> + * or failed (eg unassigned memory, device rejected the transaction,
> + * IOMMU fault).  Called within RCU critical section.
> + *
> + * @dev: #PCIDevice doing the memory access
> + * @addr: address within the #PCIDevice address space
> + * @buf: buffer with the data transferred
> + * @len: length of the data transferred
> + */
> +static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr,
> +   void *buf, dma_addr_t len)
>  {
>  return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
>  }
> --
> 2.26.2
>
>

Re: [PATCH 3/3] pci: Let pci_dma_write() propagate MemTxResult

[Li Qiang]

Philippe Mathieu-Daudé  于2020年9月5日周六 上午12:26写道：
>
> pci_dma_rw() returns a MemTxResult type.
> Do not discard it, return it to the caller.
>
> Signed-off-by: Philippe Mathieu-Daudé 

Reviewed-by: Li Qiang 

> ---
>  include/hw/pci/pci.h | 16 ++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
> index bb57525dffd..76826e240a9 100644
> --- a/include/hw/pci/pci.h
> +++ b/include/hw/pci/pci.h
> @@ -824,8 +824,20 @@ static inline MemTxResult pci_dma_read(PCIDevice *dev, 
> dma_addr_t addr,
>  return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
>  }
>
> -static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
> -const void *buf, dma_addr_t len)
> +/**
> + * pci_dma_write: Write to address space from PCI device.
> + *
> + * Return a MemTxResult indicating whether the operation succeeded
> + * or failed (eg unassigned memory, device rejected the transaction,
> + * IOMMU fault).
> + *
> + * @dev: #PCIDevice doing the memory access
> + * @addr: address within the #PCIDevice address space
> + * @buf: buffer with the data transferred
> + * @len: the number of bytes to write
> + */
> +static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr,
> +const void *buf, dma_addr_t len)
>  {
>  return pci_dma_rw(dev, addr, (void *) buf, len, 
> DMA_DIRECTION_FROM_DEVICE);
>  }
> --
> 2.26.2
>
>

Re: [PATCH v2] tests: Trying fixes test-replication.c on msys2.

[Yonggang Luo]

On Fri, Sep 4, 2020 at 9:07 PM Thomas Huth  wrote:

> On 04/09/2020 00.06, Yonggang Luo wrote:
> > Signed-off-by: Yonggang Luo 
> > ---
> >  tests/test-replication.c | 17 +
> >  1 file changed, 13 insertions(+), 4 deletions(-)
> >
> > diff --git a/tests/test-replication.c b/tests/test-replication.c
> > index 9ab3666a90..d0e06f8d77 100644
> > --- a/tests/test-replication.c
> > +++ b/tests/test-replication.c
> > @@ -23,14 +23,18 @@
> >
> >  /* primary */
> >  #define P_ID "primary-id"
> > -static char p_local_disk[] = "/tmp/p_local_disk.XX";
> > +#define P_LOCAL_DISK "%s/p_local_disk.XX"
> > +static char p_local_disk[PATH_MAX];
> >
> >  /* secondary */
> >  #define S_ID "secondary-id"
> >  #define S_LOCAL_DISK_ID "secondary-local-disk-id"
> > -static char s_local_disk[] = "/tmp/s_local_disk.XX";
> > -static char s_active_disk[] = "/tmp/s_active_disk.XX";
> > -static char s_hidden_disk[] = "/tmp/s_hidden_disk.XX";
> > +#define S_LOCAL_DISK "%s/s_local_disk.XX"
> > +static char s_local_disk[PATH_MAX];
> > +#define S_ACTIVE_DISK "%s/s_active_disk.XX"
> > +static char s_active_disk[PATH_MAX];
> > +#define S_HIDDEN_DISK "%s/s_hidden_disk.XX"
> > +static char s_hidden_disk[PATH_MAX];
> >
> >  /* FIXME: steal from blockdev.c */
> >  QemuOptsList qemu_drive_opts = {
> > @@ -571,7 +575,12 @@ static void setup_sigabrt_handler(void)
> >  int main(int argc, char **argv)
> >  {
> >  int ret;
> > +const char *tmpdir = g_get_tmp_dir();
> >  qemu_init_main_loop(&error_fatal);
> > +sprintf(p_local_disk, P_LOCAL_DISK, tmpdir);
> > +sprintf(s_local_disk, S_LOCAL_DISK, tmpdir);
> > +sprintf(s_active_disk, S_ACTIVE_DISK, tmpdir);
> > +sprintf(s_hidden_disk, S_HIDDEN_DISK, tmpdir);
>
> Sounds like the right way to go, but I think I'd do it without the
> #defines and simply use the strings directly here, what do you think?
>
I place them at the same place by define is for easily readable, if I
directly place at sprintf,
then the code are harder to read

>
>  Thomas
>
>
> PS: Please use scripts/get_maintainer.pl (or the MAINTAINERS file
> directly) on your patches to find out the right maintainers that you
> should put on CC: for every patch.
>
>

-- 
 此致
礼
罗勇刚
Yours
sincerely,
Yonggang Luo

Re: [PATCH] configure: the error info not consistence with option.

[Yonggang Luo]

On Fri, Sep 4, 2020 at 3:54 PM Paolo Bonzini  wrote:

> On 04/09/20 05:54, 罗勇刚(Yonggang Luo) wrote:
> >
> >  test "$vhost_net_user" = "" && vhost_net_user=$vhost_user
> >  if test "$vhost_net_user" = "yes" && test "$vhost_user" = "no";
> > then
> > -  error_exit "--enable-vhost-net-user requires
> --enable-vhost-user"
> > +  error_exit "--enable-vhost-net requires --enable-vhost-user"
> >  fi
> >
> >
> > This change seems wrong.
> >
> > I didn't found --enable-vhost-net-user option handling?
> > you may grep it?
> >
> >
>
> You're right, it is all dead code.  The four lines are equivalent to
> just vhost_net_user=$vhost_user.  You could also add
> --enable-vhost-net-user though!
>
I remove those four lines and use vhost_net_user=$vhost_user instead for
simplicity,
if we have no strong need of this option, i guess remove it are better

>
> Thanks,
>
> Paolo
>
>

-- 
 此致
礼
罗勇刚
Yours
sincerely,
Yonggang Luo

Re: [PATCH] stubs: Move qemu_timer_notify_cb() and remove qemu_notify_event() stub

[Yonggang Luo]

On Wed, Sep 2, 2020 at 6:33 PM Paolo Bonzini  wrote:

> On 02/09/20 12:24, Thomas Huth wrote:
> > When cross-compiling with MinGW, there are sometimes some weird linker
> > errors like:
> >
> > ibqemuutil.a(util_main-loop.c.obj): In function `qemu_notify_event':
> > /builds/huth/qemu/build/../util/main-loop.c:139: multiple definition of
> >  `qemu_notify_event'
> >
> libqemuutil.a(stubs_notify-event.c.obj):/builds/huth/qemu/stubs/notify-event.c:5:
> >  first defined here
> > collect2: error: ld returned 1 exit status
> > /builds/huth/qemu/rules.mak:88: recipe for target
> 'tests/test-timed-average.exe'
> >  failed
> >
> > It seems like it works better when the qemu_timer_notify_cb() stub (which
> > calls qemu_notify_event()) is in a separate file - then we can also even
> > remove the qemu_notify_event() stub now.
> >
> > This patch is based on ideas from the patch "stubs: Remove
> qemu_notify_event()"
> > by Philippe Mathieu-Daudé and the patch "cpu-timers, icount: new
> modules" from
> > Claudio Fontana.
> >
> > Signed-off-by: Thomas Huth 
> > ---
> >  stubs/cpu-get-icount.c   | 5 -
> >  stubs/meson.build| 2 +-
> >  stubs/notify-event.c | 6 --
> >  stubs/qemu-timer-notify-cb.c | 8 
> >  4 files changed, 9 insertions(+), 12 deletions(-)
> >  delete mode 100644 stubs/notify-event.c
> >  create mode 100644 stubs/qemu-timer-notify-cb.c
> >
> > diff --git a/stubs/cpu-get-icount.c b/stubs/cpu-get-icount.c
> > index b35f844638..4001613240 100644
> > --- a/stubs/cpu-get-icount.c
> > +++ b/stubs/cpu-get-icount.c
> > @@ -14,8 +14,3 @@ int64_t cpu_get_icount_raw(void)
> >  {
> >  abort();
> >  }
> > -
> > -void qemu_timer_notify_cb(void *opaque, QEMUClockType type)
> > -{
> > -qemu_notify_event();
> > -}
> > diff --git a/stubs/meson.build b/stubs/meson.build
> > index 019bd79c7a..e2dfedc2a7 100644
> > --- a/stubs/meson.build
> > +++ b/stubs/meson.build
> > @@ -24,9 +24,9 @@ stub_ss.add(files('machine-init-done.c'))
> >  stub_ss.add(files('migr-blocker.c'))
> >  stub_ss.add(files('monitor.c'))
> >  stub_ss.add(files('monitor-core.c'))
> > -stub_ss.add(files('notify-event.c'))
> >  stub_ss.add(files('pci-bus.c'))
> >  stub_ss.add(files('pci-host-piix.c'))
> > +stub_ss.add(files('qemu-timer-notify-cb.c'))
> >  stub_ss.add(files('qmp_memory_device.c'))
> >  stub_ss.add(files('qtest.c'))
> >  stub_ss.add(files('ram-block.c'))
> > diff --git a/stubs/notify-event.c b/stubs/notify-event.c
> > deleted file mode 100644
> > index 827bb52d1a..00
> > --- a/stubs/notify-event.c
> > +++ /dev/null
> > @@ -1,6 +0,0 @@
> > -#include "qemu/osdep.h"
> > -#include "qemu/main-loop.h"
> > -
> > -void qemu_notify_event(void)
> > -{
> > -}
> > diff --git a/stubs/qemu-timer-notify-cb.c b/stubs/qemu-timer-notify-cb.c
> > new file mode 100644
> > index 00..054b408b1c
> > --- /dev/null
> > +++ b/stubs/qemu-timer-notify-cb.c
> > @@ -0,0 +1,8 @@
> > +#include "qemu/osdep.h"
> > +#include "sysemu/cpus.h"
> > +#include "qemu/main-loop.h"
> > +
> > +void qemu_timer_notify_cb(void *opaque, QEMUClockType type)
> > +{
> > +qemu_notify_event();
> > +}
> >
>
> Acked-by: Paolo Bonzini 
>
LGTM, can you queue this patch,


-- 
 此致
礼
罗勇刚
Yours
sincerely,
Yonggang Luo

Re: make -i check resut for msys2

[Yonggang Luo]

On Fri, Sep 4, 2020 at 4:51 PM Kevin Wolf  wrote:

> Am 04.09.2020 um 08:03 hat Thomas Huth geschrieben:
> > On 04/09/2020 00.53, 罗勇刚(Yonggang Luo) wrote:
> > >
> > >
> > > On Thu, Sep 3, 2020 at 10:33 PM Thomas Huth  > > > wrote:
> > >
> > > On 03/09/2020 11.18, 罗勇刚(Yonggang Luo) wrote:
> > > [...]
> > > >   TESTcheck-unit: tests/test-replication.exe
> > > > **
> > > > ERROR:C:/work/xemu/qemu/tests/test-replication.c:136:make_temp:
> > > > assertion failed: (fd >= 0)
> > > > ERROR test-replication.exe - Bail out!
> > > > ERROR:C:/work/xemu/qemu/tests/test-replication.c:136:make_temp:
> > > > assertion failed: (fd >= 0)
> > >
> > > At least this one should be easy to fix: The test uses /tmp as
> > > hard-coded directory for temporary files. I think it should use
> > > g_get_tmp_dir() from glib to get that directory instead.
> > >
> > >  Thomas
> > >
> > > After fixes tmp path, how to fixes following error:
> > > $ tests/test-replication.exe
>
> > >
> > >
> > >
> > > # random seed: R02Sdf2e4ffc0e6fbe96624598386b538927
> > > 1..13
> > > # Start of replication tests
> > > # Start of primary tests
> > > Unexpected error in bdrv_open_inherit() at ../block.c:3456:
> > > Block protocol 'file' doesn't support the option 'locking'
> >
> > Not sure ... as a temporary test, try to remove the "locking=off"
> > strings from the test. If it then works, it might be worth discussing
> > with the block layer folks how to handle this test on Windows in the
> > best way. If it still does not work, it's maybe simply not worth the
> > effort to try to get this test running on Windows - and thus mark it
> > with CONFIG_POSIX in the Makefile / meson.build.
>
> This is a bug in file-win32. It reads "locking" from the options QDict,
> but doesn't delete it from it.
>
> Does the following help? (Only compile-tested.)
>
> If it works for you, I'll send it as a proper patch.
>
> Kevin
>
> diff --git a/block/file-win32.c b/block/file-win32.c
> index ab69bd811a..e2900c3a51 100644
> --- a/block/file-win32.c
> +++ b/block/file-win32.c
> @@ -299,6 +299,11 @@ static QemuOptsList raw_runtime_opts = {
>  .type = QEMU_OPT_STRING,
>  .help = "host AIO implementation (threads, native)",
>  },
> +{
> +.name = "locking",
> +.type = QEMU_OPT_STRING,
> +.help = "file locking mode (on/off/auto, default: auto)",
> +},
>  { /* end of list */ }
>  },
>  };
> @@ -333,6 +338,7 @@ static int raw_open(BlockDriverState *bs, QDict
> *options, int flags,
>  Error *local_err = NULL;
>  const char *filename;
>  bool use_aio;
> +OnOffAuto locking;
>  int ret;
>
>  s->type = FTYPE_FILE;
> @@ -343,10 +349,24 @@ static int raw_open(BlockDriverState *bs, QDict
> *options, int flags,
>  goto fail;
>  }
>
> -if (qdict_get_try_bool(options, "locking", false)) {
> +locking = qapi_enum_parse(&OnOffAuto_lookup,
> +  qemu_opt_get(opts, "locking"),
> +  ON_OFF_AUTO_AUTO, &local_err);
> +if (local_err) {
> +error_propagate(errp, local_err);
> +ret = -EINVAL;
> +goto fail;
> +}
> +switch (locking) {
> +case ON_OFF_AUTO_ON:
>  error_setg(errp, "locking=on is not supported on Windows");
>  ret = -EINVAL;
>  goto fail;
> +case ON_OFF_AUTO_OFF:
> +case ON_OFF_AUTO_AUTO:
> +break;
> +default:
> +g_assert_not_reached();
>  }
>
>  filename = qemu_opt_get(opts, "filename");
>
> Partial error fixed, new error are coming:
$ ./tests/test-replication.exe
# random seed: R02S3f4d1c01af2b0a046990e0235c481faf
1..13
# Start of replication tests
# Start of primary tests
ok 1 /replication/primary/read
ok 2 /replication/primary/write
ok 3 /replication/primary/start
ok 4 /replication/primary/stop
ok 5 /replication/primary/do_checkpoint
ok 6 /replication/primary/get_error_all
# End of primary tests
# Start of secondary tests
ok 7 /replication/secondary/read
ok 8 /replication/secondary/write
Unexpected error in bdrv_reopen_prepare() at ../block.c:4191:
Block format 'file' used by node '#block4287' does not support reopening
files

-- 
 此致
礼
罗勇刚
Yours
sincerely,
Yonggang Luo

[PATCH v5 00/11] Green the msys2 CI make

[Yonggang Luo]

Also it's fixes issues about make check

Yonggang Luo (11):
  Revert "configure: add --ninja option"
  block: Fixes nfs on msys2/mingw
  ci: fixes msys2 build by upgrading capstone to 4.0.2
  meson: upgrade meson for execute custom ninjatool under msys2 properly
  ci: Enable msys2 ci in cirrus
  tests: Trying fixes test-replication.c on msys2.
  block: get file-win32.c handle locking option consistence with
file-posix.c
  osdep: These function are only available on Non-Win32 system.
  meson: Fixes qapi tests.
  docker: Add win32/msys2/mingw64 docker
  ci: Enable Github actions.

 .cirrus.yml   | 24 +++
 .github/workflows/main.yml| 31 +
 block/file-win32.c| 23 +--
 block/nfs.c   | 26 +
 capstone  |  2 +-
 configure | 18 ++-
 include/qemu/osdep.h  |  2 +-
 meson |  2 +-
 scripts/ci/windows/msys2-build.sh | 27 ++
 scripts/ci/windows/msys2-download.bat |  4 
 scripts/ci/windows/msys2-install.sh   | 33 +++
 tests/docker/dockerfiles/msys2.docker | 11 +
 tests/qapi-schema/meson.build |  3 ++-
 tests/test-replication.c  | 17 ++
 14 files changed, 188 insertions(+), 35 deletions(-)
 create mode 100644 .github/workflows/main.yml
 create mode 100644 scripts/ci/windows/msys2-build.sh
 create mode 100644 scripts/ci/windows/msys2-download.bat
 create mode 100644 scripts/ci/windows/msys2-install.sh
 create mode 100644 tests/docker/dockerfiles/msys2.docker

-- 
2.28.0.windows.1

[PATCH v5 01/11] Revert "configure: add --ninja option"

[Yonggang Luo]

This reverts commit 48328880fddf0145bdccc499160fb24dfabfbd41.

Signed-off-by: Yonggang Luo 
---
 configure | 16 +---
 1 file changed, 1 insertion(+), 15 deletions(-)

diff --git a/configure b/configure
index d3495e107f..5d8bf4d8bb 100755
--- a/configure
+++ b/configure
@@ -517,7 +517,6 @@ rng_none="no"
 secret_keyring=""
 libdaxctl=""
 meson=""
-ninja=""
 skip_meson=no
 gettext=""
 
@@ -984,8 +983,6 @@ for opt do
   ;;
   --meson=*) meson="$optarg"
   ;;
-  --ninja=*) ninja="$optarg"
-  ;;
   --smbd=*) smbd="$optarg"
   ;;
   --extra-cflags=*)
@@ -1758,7 +1755,6 @@ Advanced options (experts only):
   --python=PYTHON  use specified python [$python]
   --sphinx-build=SPHINXuse specified sphinx-build [$sphinx_build]
   --meson=MESONuse specified meson [$meson]
-  --ninja=NINJAuse specified ninja [$ninja]
   --smbd=SMBD  use specified smbd [$smbd]
   --with-git=GIT   use specified git [$git]
   --static enable static build [$static]
@@ -1995,16 +1991,6 @@ case "$meson" in
 *) meson=$(command -v meson) ;;
 esac
 
-# Probe for ninja (used for compdb)
-
-if test -z "$ninja"; then
-for c in ninja ninja-build samu; do
-if has $c; then
-ninja=$(command -v "$c")
-break
-fi
-done
-fi
 
 # Check that the C compiler works. Doing this here before testing
 # the host CPU ensures that we had a valid CC to autodetect the
@@ -7917,7 +7903,7 @@ fi
 mv $cross config-meson.cross
 
 rm -rf meson-private meson-info meson-logs
-NINJA=${ninja:-$PWD/ninjatool} $meson setup \
+NINJA=$PWD/ninjatool $meson setup \
 --prefix "${pre_prefix}$prefix" \
 --libdir "${pre_prefix}$libdir" \
 --libexecdir "${pre_prefix}$libexecdir" \
-- 
2.28.0.windows.1

[PATCH v5 03/11] ci: fixes msys2 build by upgrading capstone to 4.0.2

[Yonggang Luo]

Signed-off-by: Yonggang Luo 
---
 capstone  | 2 +-
 configure | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/capstone b/capstone
index 22ead3e0bf..1d23053284 16
--- a/capstone
+++ b/capstone
@@ -1 +1 @@
-Subproject commit 22ead3e0bfdb87516656453336160e0a37b066bf
+Subproject commit 1d230532840a37ac032c6ab80128238fc930c6c1
diff --git a/configure b/configure
index 5d8bf4d8bb..f8cbd2898c 100755
--- a/configure
+++ b/configure
@@ -5117,7 +5117,7 @@ case "$capstone" in
   LIBCAPSTONE=libcapstone.a
 fi
 capstone_libs="-Lcapstone -lcapstone"
-capstone_cflags="-I${source_path}/capstone/include"
+capstone_cflags="-I${source_path}/capstone/include 
-I${source_path}/capstone/include/capstone"
 ;;
 
   system)
-- 
2.28.0.windows.1

[PATCH v5 04/11] meson: upgrade meson for execute custom ninjatool under msys2 properly

[Yonggang Luo]

The ninja options now have no need anymore.

Signed-off-by: Yonggang Luo 
---
 meson | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/meson b/meson
index 68ed748f84..492afe50a4 16
--- a/meson
+++ b/meson
@@ -1 +1 @@
-Subproject commit 68ed748f84f14c2d4e62dcbd123816e5898eb04c
+Subproject commit 492afe50a439d70df99d6e3e59572aff55e14c6b
-- 
2.28.0.windows.1

[PATCH v5 02/11] block: Fixes nfs on msys2/mingw

[Yonggang Luo]

Signed-off-by: Yonggang Luo 
---
 block/nfs.c | 26 +-
 1 file changed, 17 insertions(+), 9 deletions(-)

diff --git a/block/nfs.c b/block/nfs.c
index 61a249a9fc..34b2cd5708 100644
--- a/block/nfs.c
+++ b/block/nfs.c
@@ -24,7 +24,9 @@
 
 #include "qemu/osdep.h"
 
+#if !defined(_WIN32)
 #include 
+#endif
 #include "qemu/config-file.h"
 #include "qemu/error-report.h"
 #include "qapi/error.h"
@@ -51,6 +53,12 @@
 #define QEMU_NFS_MAX_PAGECACHE_SIZE (8388608 / NFS_BLKSIZE)
 #define QEMU_NFS_MAX_DEBUG_LEVEL 2
 
+#if defined (_WIN32)
+#define nfs_stat __stat64
+#else
+#define nfs_stat stat
+#endif
+
 typedef struct NFSClient {
 struct nfs_context *context;
 struct nfsfh *fh;
@@ -58,7 +66,7 @@ typedef struct NFSClient {
 bool has_zero_init;
 AioContext *aio_context;
 QemuMutex mutex;
-blkcnt_t st_blocks;
+int64_t st_size;
 bool cache_used;
 NFSServer *server;
 char *path;
@@ -70,7 +78,7 @@ typedef struct NFSRPC {
 int ret;
 int complete;
 QEMUIOVector *iov;
-struct stat *st;
+struct nfs_stat *st;
 Coroutine *co;
 NFSClient *client;
 } NFSRPC;
@@ -419,7 +427,7 @@ static int64_t nfs_client_open(NFSClient *client, 
BlockdevOptionsNfs *opts,
int flags, int open_flags, Error **errp)
 {
 int64_t ret = -EINVAL;
-struct stat st;
+struct nfs_stat st;
 char *file = NULL, *strp = NULL;
 
 qemu_mutex_init(&client->mutex);
@@ -545,7 +553,7 @@ static int64_t nfs_client_open(NFSClient *client, 
BlockdevOptionsNfs *opts,
 }
 
 ret = DIV_ROUND_UP(st.st_size, BDRV_SECTOR_SIZE);
-client->st_blocks = st.st_blocks;
+client->st_size = st.st_size;
 client->has_zero_init = S_ISREG(st.st_mode);
 *strp = '/';
 goto out;
@@ -729,11 +737,11 @@ static int64_t 
nfs_get_allocated_file_size(BlockDriverState *bs)
 {
 NFSClient *client = bs->opaque;
 NFSRPC task = {0};
-struct stat st;
+struct nfs_stat st;
 
 if (bdrv_is_read_only(bs) &&
 !(bs->open_flags & BDRV_O_NOCACHE)) {
-return client->st_blocks * 512;
+return client->st_size;
 }
 
 task.bs = bs;
@@ -746,7 +754,7 @@ static int64_t nfs_get_allocated_file_size(BlockDriverState 
*bs)
 nfs_set_events(client);
 BDRV_POLL_WHILE(bs, !task.complete);
 
-return (task.ret < 0 ? task.ret : st.st_blocks * 512);
+return (task.ret < 0 ? task.ret : st.st_size);
 }
 
 static int coroutine_fn
@@ -778,7 +786,7 @@ static int nfs_reopen_prepare(BDRVReopenState *state,
   BlockReopenQueue *queue, Error **errp)
 {
 NFSClient *client = state->bs->opaque;
-struct stat st;
+struct nfs_stat st;
 int ret = 0;
 
 if (state->flags & BDRV_O_RDWR && bdrv_is_read_only(state->bs)) {
@@ -800,7 +808,7 @@ static int nfs_reopen_prepare(BDRVReopenState *state,
nfs_get_error(client->context));
 return ret;
 }
-client->st_blocks = st.st_blocks;
+client->st_size = st.st_size;
 }
 
 return 0;
-- 
2.28.0.windows.1

[PATCH v5 06/11] tests: Trying fixes test-replication.c on msys2.

[Yonggang Luo]

Signed-off-by: Yonggang Luo 
---
 tests/test-replication.c | 17 +
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/tests/test-replication.c b/tests/test-replication.c
index 9ab3666a90..d0e06f8d77 100644
--- a/tests/test-replication.c
+++ b/tests/test-replication.c
@@ -23,14 +23,18 @@
 
 /* primary */
 #define P_ID "primary-id"
-static char p_local_disk[] = "/tmp/p_local_disk.XX";
+#define P_LOCAL_DISK "%s/p_local_disk.XX"
+static char p_local_disk[PATH_MAX];
 
 /* secondary */
 #define S_ID "secondary-id"
 #define S_LOCAL_DISK_ID "secondary-local-disk-id"
-static char s_local_disk[] = "/tmp/s_local_disk.XX";
-static char s_active_disk[] = "/tmp/s_active_disk.XX";
-static char s_hidden_disk[] = "/tmp/s_hidden_disk.XX";
+#define S_LOCAL_DISK "%s/s_local_disk.XX"
+static char s_local_disk[PATH_MAX];
+#define S_ACTIVE_DISK "%s/s_active_disk.XX"
+static char s_active_disk[PATH_MAX];
+#define S_HIDDEN_DISK "%s/s_hidden_disk.XX"
+static char s_hidden_disk[PATH_MAX];
 
 /* FIXME: steal from blockdev.c */
 QemuOptsList qemu_drive_opts = {
@@ -571,7 +575,12 @@ static void setup_sigabrt_handler(void)
 int main(int argc, char **argv)
 {
 int ret;
+const char *tmpdir = g_get_tmp_dir();
 qemu_init_main_loop(&error_fatal);
+sprintf(p_local_disk, P_LOCAL_DISK, tmpdir);
+sprintf(s_local_disk, S_LOCAL_DISK, tmpdir);
+sprintf(s_active_disk, S_ACTIVE_DISK, tmpdir);
+sprintf(s_hidden_disk, S_HIDDEN_DISK, tmpdir);
 bdrv_init();
 
 g_test_init(&argc, &argv, NULL);
-- 
2.28.0.windows.1

[PATCH v5 08/11] osdep: These function are only available on Non-Win32 system.

[Yonggang Luo]

int qemu_lock_fd(int fd, int64_t start, int64_t len, bool exclusive);
int qemu_unlock_fd(int fd, int64_t start, int64_t len);
int qemu_lock_fd_test(int fd, int64_t start, int64_t len, bool exclusive);
bool qemu_has_ofd_lock(void);

Signed-off-by: Yonggang Luo 
---
 include/qemu/osdep.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
index 412962d91a..e80fddd1e8 100644
--- a/include/qemu/osdep.h
+++ b/include/qemu/osdep.h
@@ -502,11 +502,11 @@ int qemu_close(int fd);
 int qemu_unlink(const char *name);
 #ifndef _WIN32
 int qemu_dup(int fd);
-#endif
 int qemu_lock_fd(int fd, int64_t start, int64_t len, bool exclusive);
 int qemu_unlock_fd(int fd, int64_t start, int64_t len);
 int qemu_lock_fd_test(int fd, int64_t start, int64_t len, bool exclusive);
 bool qemu_has_ofd_lock(void);
+#endif
 
 #if defined(__HAIKU__) && defined(__i386__)
 #define FMT_pid "%ld"
-- 
2.28.0.windows.1

[PATCH v5 05/11] ci: Enable msys2 ci in cirrus

[Yonggang Luo]

Install msys2 in a proper way refer to 
https://github.com/cirruslabs/cirrus-ci-docs/issues/699
The https://wiki.qemu.org/Hosts/W32#Native_builds_with_MSYS2 need to be updated.
There is no need of --cross-prefix, open mingw64.exe instead of msys2.exe then 
we don't
need the --cross-prefix, besides we using environment variable settings:
MSYS: winsymlinks:nativestrict
MSYSTEM: MINGW64
CHERE_INVOKING: 1
to opening mingw64 native shell.
We now running tests with make -i check to skip tests errors.

Signed-off-by: Yonggang Luo 
---
 .cirrus.yml | 24 +
 scripts/ci/windows/msys2-build.sh   | 27 +++
 scripts/ci/windows/msys2-install.sh | 33 +
 3 files changed, 84 insertions(+)
 create mode 100644 scripts/ci/windows/msys2-build.sh
 create mode 100644 scripts/ci/windows/msys2-install.sh

diff --git a/.cirrus.yml b/.cirrus.yml
index 3dd9fcff7f..49335e68c9 100644
--- a/.cirrus.yml
+++ b/.cirrus.yml
@@ -63,3 +63,27 @@ macos_xcode_task:
--enable-werror --cc=clang || { cat config.log; exit 1; }
 - gmake -j$(sysctl -n hw.ncpu)
 - gmake check
+
+windows_msys2_task:
+  windows_container:
+image: cirrusci/windowsservercore:cmake
+os_version: 2019
+cpu: 8
+memory: 8G
+  env:
+MSYS: winsymlinks:nativestrict
+MSYSTEM: MINGW64
+CHERE_INVOKING: 1
+  printenv_script:
+- C:\tools\msys64\usr\bin\bash.exe -lc 'printenv'
+  install_script:
+- C:\tools\msys64\usr\bin\bash.exe -lc "cd /c/tools && curl -O 
http://repo.msys2.org/msys/x86_64/msys2-keyring-r21.b39fb11-1-any.pkg.tar.xz";
+- C:\tools\msys64\usr\bin\bash.exe -lc "cd /c/tools && curl -O 
http://repo.msys2.org/msys/x86_64/msys2-keyring-r21.b39fb11-1-any.pkg.tar.xz.sig";
+- C:\tools\msys64\usr\bin\bash.exe -lc "cd /c/tools && pacman -U 
--noconfirm msys2-keyring-r21.b39fb11-1-any.pkg.tar.xz"
+- C:\tools\msys64\usr\bin\bash.exe -lc "pacman -Sy --noconfirm"
+- C:\tools\msys64\usr\bin\bash.exe -lc "pacman --needed --noconfirm -S 
bash pacman pacman-mirrors msys2-runtime"
+- taskkill /F /IM gpg-agent.exe
+- C:\tools\msys64\usr\bin\bash.exe -lc "pacman --noconfirm -Su"
+- C:\tools\msys64\usr\bin\bash.exe -lc "sh 
scripts/ci/windows/msys2-install.sh"
+  script:
+- C:\tools\msys64\usr\bin\bash.exe -lc "sh 
scripts/ci/windows/msys2-build.sh"
diff --git a/scripts/ci/windows/msys2-build.sh 
b/scripts/ci/windows/msys2-build.sh
new file mode 100644
index 00..532cb847c0
--- /dev/null
+++ b/scripts/ci/windows/msys2-build.sh
@@ -0,0 +1,27 @@
+mkdir build
+cd build
+../configure \
+--python=python3 \
+--enable-stack-protector \
+--enable-guest-agent \
+--disable-pie \
+--enable-gnutls --enable-nettle \
+--enable-sdl --enable-sdl-image --enable-gtk --disable-vte --disable-curses 
--enable-iconv \
+--enable-vnc --enable-vnc-sasl --enable-vnc-jpeg --enable-vnc-png \
+--enable-slirp=git \
+--disable-brlapi --enable-curl \
+--enable-fdt \
+--disable-kvm --enable-hax --enable-whpx \
+--enable-libnfs --enable-libusb --enable-live-block-migration 
--enable-usb-redir \
+--enable-lzo --enable-snappy --enable-bzip2 --enable-zstd \
+--enable-membarrier --enable-coroutine-pool \
+--enable-libssh --enable-libxml2 \
+--enable-jemalloc --enable-avx2 \
+--enable-replication \
+--enable-tools \
+--enable-bochs --enable-cloop --enable-dmg --enable-qcow1 --enable-vdi 
--enable-vvfat --enable-qed --enable-parallels \
+--enable-sheepdog \
+--enable-capstone=git
+
+make -j$NUMBER_OF_PROCESSORS
+make -i -j$NUMBER_OF_PROCESSORS check
diff --git a/scripts/ci/windows/msys2-install.sh 
b/scripts/ci/windows/msys2-install.sh
new file mode 100644
index 00..6086452399
--- /dev/null
+++ b/scripts/ci/windows/msys2-install.sh
@@ -0,0 +1,33 @@
+pacman --noconfirm -S --needed \
+base-devel \
+git \
+mingw-w64-x86_64-python \
+mingw-w64-x86_64-python-setuptools \
+mingw-w64-x86_64-toolchain \
+mingw-w64-x86_64-SDL2 \
+mingw-w64-x86_64-SDL2_image \
+mingw-w64-x86_64-gtk3 \
+mingw-w64-x86_64-glib2 \
+mingw-w64-x86_64-ninja \
+mingw-w64-x86_64-make \
+mingw-w64-x86_64-jemalloc \
+mingw-w64-x86_64-lzo2 \
+mingw-w64-x86_64-zstd \
+mingw-w64-x86_64-libjpeg-turbo \
+mingw-w64-x86_64-pixman \
+mingw-w64-x86_64-libgcrypt \
+mingw-w64-x86_64-capstone \
+mingw-w64-x86_64-libpng \
+mingw-w64-x86_64-libssh \
+mingw-w64-x86_64-libxml2 \
+mingw-w64-x86_64-snappy \
+mingw-w64-x86_64-libusb \
+mingw-w64-x86_64-usbredir \
+mingw-w64-x86_64-libtasn1 \
+mingw-w64-x86_64-libnfs \
+mingw-w64-x86_64-nettle \
+mingw-w64-x86_64-cyrus-sasl \
+mingw-w64-x86_64-curl \
+mingw-w64-x86_64-gnutls \
+mingw-w64-x86_64-zstd \
+
-- 
2.28.0.windows.1

[PATCH v5 10/11] docker: Add win32/msys2/mingw64 docker

[Yonggang Luo]

Signed-off-by: Yonggang Luo 
---
 tests/docker/dockerfiles/msys2.docker | 11 +++
 1 file changed, 11 insertions(+)
 create mode 100644 tests/docker/dockerfiles/msys2.docker

diff --git a/tests/docker/dockerfiles/msys2.docker 
b/tests/docker/dockerfiles/msys2.docker
new file mode 100644
index 00..f898e0803d
--- /dev/null
+++ b/tests/docker/dockerfiles/msys2.docker
@@ -0,0 +1,11 @@
+FROM cirrusci/windowsservercore:cmake
+RUN echo | choco install -y --no-progress --ignore-package-exit-codes --params 
"/NoUpdate /InstallDir:C:\tools\msys64" msys2
+COPY msys2_install.sh C:/tools
+RUN C:\tools\msys64\usr\bin\bash.exe -lc "grep -rl 'repo.msys2.org/' 
/etc/pacman.d/mirrorlist.* | xargs sed -i 
's/repo.msys2.org\//mirrors.ustc.edu.cn\/msys2\//g'"
+RUN C:\tools\msys64\usr\bin\bash.exe -lc "pacman -Sy"
+RUN C:\tools\msys64\usr\bin\bash.exe -lc "sh /c/tools/msys2_install.sh"
+RUN C:\tools\msys64\usr\bin\bash.exe -lc "rm -rf /var/cache/pacman/pkg/*"
+
+# docker build --tag lygstate/windowsservercore:msys2 -f 
"../../../tests/docker/dockerfiles/msys2.docker" .
+# docker run -it lygstate/windowsservercore:msys2 cmd
+# docker push lygstate/windowsservercore:msys2
-- 
2.28.0.windows.1

[PATCH v5 07/11] block: get file-win32.c handle locking option consistence with file-posix.c

[Yonggang Luo]

Signed-off-by: Yonggang Luo 
---
 block/file-win32.c | 23 +--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/block/file-win32.c b/block/file-win32.c
index ab69bd811a..14e5f5c3b5 100644
--- a/block/file-win32.c
+++ b/block/file-win32.c
@@ -299,6 +299,11 @@ static QemuOptsList raw_runtime_opts = {
 .type = QEMU_OPT_STRING,
 .help = "host AIO implementation (threads, native)",
 },
+{
+.name = "locking",
+.type = QEMU_OPT_STRING,
+.help = "file locking mode (on/off/auto, default: auto)",
+},
 { /* end of list */ }
 },
 };
@@ -334,6 +339,7 @@ static int raw_open(BlockDriverState *bs, QDict *options, 
int flags,
 const char *filename;
 bool use_aio;
 int ret;
+OnOffAuto locking;
 
 s->type = FTYPE_FILE;
 
@@ -342,11 +348,24 @@ static int raw_open(BlockDriverState *bs, QDict *options, 
int flags,
 ret = -EINVAL;
 goto fail;
 }
-
-if (qdict_get_try_bool(options, "locking", false)) {
+locking = qapi_enum_parse(&OnOffAuto_lookup,
+  qemu_opt_get(opts, "locking"),
+  ON_OFF_AUTO_AUTO, &local_err);
+if (local_err) {
+error_propagate(errp, local_err);
+ret = -EINVAL;
+goto fail;
+}
+switch (locking) {
+case ON_OFF_AUTO_ON:
 error_setg(errp, "locking=on is not supported on Windows");
 ret = -EINVAL;
 goto fail;
+case ON_OFF_AUTO_OFF:
+case ON_OFF_AUTO_AUTO:
+break;
+default:
+g_assert_not_reached();
 }
 
 filename = qemu_opt_get(opts, "filename");
-- 
2.28.0.windows.1

[PATCH v5 11/11] ci: Enable Github actions.

[Yonggang Luo]

Signed-off-by: Yonggang Luo 
---
 .github/workflows/main.yml| 31 +++
 scripts/ci/windows/msys2-download.bat |  4 
 2 files changed, 35 insertions(+)
 create mode 100644 .github/workflows/main.yml
 create mode 100644 scripts/ci/windows/msys2-download.bat

diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
new file mode 100644
index 00..758bbf6641
--- /dev/null
+++ b/.github/workflows/main.yml
@@ -0,0 +1,31 @@
+# This is a basic workflow to help you get started with Actions
+
+name: CI
+
+# Controls when the action will run. Triggers the workflow on push or pull 
request
+# events but only for the master branch
+on:
+  push:
+branches: [ master, msys2 ]
+  pull_request:
+branches: [ master ]
+
+# A workflow run is made up of one or more jobs that can run sequentially or 
in parallel
+jobs:
+  msys2-build:
+name: C++ msys2 (Windows)
+runs-on: windows-latest
+strategy:
+  fail-fast: false
+steps:
+  # Checks-out your repository under $GITHUB_WORKSPACE, so your job can 
access it
+  - uses: actions/checkout@v2
+  - name: Install MSYS2
+run: scripts/ci/windows/msys2-download
+  - name: Build
+env:
+  MSYS: winsymlinks:nativestrict
+  MSYSTEM: MINGW64
+  CHERE_INVOKING: 1
+run: C:\tools\msys64\usr\bin\bash.exe -lc "sh 
scripts/ci/windows/msys2-build.sh"
+
diff --git a/scripts/ci/windows/msys2-download.bat 
b/scripts/ci/windows/msys2-download.bat
new file mode 100644
index 00..2c7c41899e
--- /dev/null
+++ b/scripts/ci/windows/msys2-download.bat
@@ -0,0 +1,4 @@
+mkdir C:\tools
+cd /d C:\tools
+curl -LJ -s 
https://github.com/lygstate/qemu/releases/download/v5.1.0/msys64-v5.1.0.7z 
--output msys64.7z
+7z -mmt8 x msys64.7z
-- 
2.28.0.windows.1

[PATCH v5 09/11] meson: Fixes qapi tests.

[Yonggang Luo]

The error are:
+@end table
+
+@end deftypefn
+
make: *** [Makefile.mtest:63: check-qapi-schema] Error 1

Signed-off-by: Yonggang Luo 
---
 tests/qapi-schema/meson.build | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/tests/qapi-schema/meson.build b/tests/qapi-schema/meson.build
index c87d141417..67ba0a5ebd 100644
--- a/tests/qapi-schema/meson.build
+++ b/tests/qapi-schema/meson.build
@@ -220,6 +220,7 @@ qapi_doc = custom_target('QAPI doc',
 
 # "full_path()" needed here to work around
 # https://github.com/mesonbuild/meson/issues/7585
-test('QAPI doc', diff, args: ['-u', files('doc-good.texi'), 
qapi_doc[0].full_path()],
+test('QAPI doc', diff, args: ['--strip-trailing-cr',
+  '-u', files('doc-good.texi'), 
qapi_doc[0].full_path()],
  depends: qapi_doc,
  suite: ['qapi-schema', 'qapi-doc'])
-- 
2.28.0.windows.1

[PATCH] tests: fixes test-vmstate.c compile error on msys2

[Yonggang Luo]

../tests/test-vmstate.c: In function 'int_cmp':
../tests/test-vmstate.c:884:5: error: unknown type name 'uint'; did you mean 
'uInt'?
  884 | uint ua = GPOINTER_TO_UINT(a);
  | ^~~~
  | uInt
../tests/test-vmstate.c:885:5: error: unknown type name 'uint'; did you mean 
'uInt'?
  885 | uint ub = GPOINTER_TO_UINT(b);
  | ^~~~
  | uInt
make: *** [Makefile.ninja:5461：tests/test-vmstate.exe.p/test-vmstate.c.obj] 错误 1

Signed-off-by: Yonggang Luo 
---
 tests/test-vmstate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tests/test-vmstate.c b/tests/test-vmstate.c
index f7b3868881..f8de709a0b 100644
--- a/tests/test-vmstate.c
+++ b/tests/test-vmstate.c
@@ -881,8 +881,8 @@ static gint interval_cmp(gconstpointer a, gconstpointer b, 
gpointer user_data)
 /* ID comparison function */
 static gint int_cmp(gconstpointer a, gconstpointer b, gpointer user_data)
 {
-uint ua = GPOINTER_TO_UINT(a);
-uint ub = GPOINTER_TO_UINT(b);
+guint ua = GPOINTER_TO_UINT(a);
+guint ub = GPOINTER_TO_UINT(b);
 return (ua > ub) - (ua < ub);
 }
 
-- 
2.28.0.windows.1

[PULL 2/4] vnc-auth-sasl: Plug memleak in vnc_socket_ip_addr_string

[Gerd Hoffmann]

From: Pan Nengyuan 

'addr' is forgot to free in vnc_socket_ip_addr_string error path. Fix that.

Reported-by: Euler Robot 
Signed-off-by: Pan Nengyuan 
Reviewed-by: Li Qiang 
Message-Id: <20200831134315.1221-11-pannengy...@huawei.com>
Signed-off-by: Gerd Hoffmann 
---
 ui/vnc-auth-sasl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/ui/vnc-auth-sasl.c b/ui/vnc-auth-sasl.c
index 7b2b09f24276..0517b2ead9ce 100644
--- a/ui/vnc-auth-sasl.c
+++ b/ui/vnc-auth-sasl.c
@@ -522,6 +522,7 @@ vnc_socket_ip_addr_string(QIOChannelSocket *ioc,
 
 if (addr->type != SOCKET_ADDRESS_TYPE_INET) {
 error_setg(errp, "Not an inet socket type");
+qapi_free_SocketAddress(addr);
 return NULL;
 }
 ret = g_strdup_printf("%s;%s", addr->u.inet.host, addr->u.inet.port);
-- 
2.27.0

[PULL 3/4] ui: Add more mouse buttons to SPICE

[Gerd Hoffmann]

From: Frediano Ziglio 

Add support for SIDE and EXTRA buttons.

The constants for buttons in both SPICE and QEMU are defined as
  LEFT
  MIDDLE
  RIGHT
  UP
  DOWN
  SIDE
  EXTRA
(same order).

"button_mask" contains for each bit the state of a button. Qemu currently
uses bits 0, 1, 2 respectively as LEFT, RIGHT, MIDDLE; also add bits 4
and 5 as UP and DOWN (using wheel movements). SPICE protocol uses
a bitmask based on the order above where LEFT is bit 0, MIDDLE is
bit 1 and so on till EXTRA being bit 6. To avoid clash with Qemu usage
SPICE bitmask from SIDE are move a bit more resulting respectively
in 0x40 and 0x80 values.

Signed-off-by: Frediano Ziglio 
Message-id: 20200820145851.50846-1-fzig...@redhat.com
Signed-off-by: Gerd Hoffmann 
---
 ui/spice-input.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/ui/spice-input.c b/ui/spice-input.c
index cd4bb0043fd9..d5bba231c95c 100644
--- a/ui/spice-input.c
+++ b/ui/spice-input.c
@@ -123,6 +123,8 @@ static void spice_update_buttons(QemuSpicePointer *pointer,
 [INPUT_BUTTON_RIGHT]   = 0x02,
 [INPUT_BUTTON_WHEEL_UP]= 0x10,
 [INPUT_BUTTON_WHEEL_DOWN]  = 0x20,
+[INPUT_BUTTON_SIDE]= 0x40,
+[INPUT_BUTTON_EXTRA]   = 0x80,
 };
 
 if (wheel < 0) {
-- 
2.27.0

[PULL 4/4] ui/gtk: Update refresh interval after widget is realized

[Gerd Hoffmann]

From: Philippe Mathieu-Daudé 

Nikola reported on Windows when gd_vc_gfx_init() is called, the
window is not yet realized, so we run gd_refresh_rate_millihz(NULL)
which returns 0 milli-Hertz.
When a Widget is realized, it fires a 'realized' event. We already
have the gd_draw_event() handler registered for this even, so simply
move the gd_refresh_rate_millihz() there. When the event fires, the
window is known to exist.
This completes commit c4c00922cc original intention.

Reported-by: Nikola Pavlica 
Tested-by: Nikola Pavlica 
Signed-off-by: Philippe Mathieu-Daudé 
Message-id: 20200817172331.598255-1-phi...@redhat.com
Suggested-by: Nikola Pavlica 
Tested-by: Nikola Pavlica 
Signed-off-by: Philippe Mathieu-Daudé 
Signed-off-by: Gerd Hoffmann 
---
 ui/gtk.c | 52 ++--
 1 file changed, 26 insertions(+), 26 deletions(-)

diff --git a/ui/gtk.c b/ui/gtk.c
index b0cc08ad6da7..7a717ce8e5e4 100644
--- a/ui/gtk.c
+++ b/ui/gtk.c
@@ -744,6 +744,25 @@ static void gd_resize_event(GtkGLArea *area,
 
 #endif
 
+/*
+ * If available, return the refresh rate of the display in milli-Hertz,
+ * else return 0.
+ */
+static int gd_refresh_rate_millihz(GtkWidget *window)
+{
+#ifdef GDK_VERSION_3_22
+GdkWindow *win = gtk_widget_get_window(window);
+
+if (win) {
+GdkDisplay *dpy = gtk_widget_get_display(window);
+GdkMonitor *monitor = gdk_display_get_monitor_at_window(dpy, win);
+
+return gdk_monitor_get_refresh_rate(monitor);
+}
+#endif
+return 0;
+}
+
 static gboolean gd_draw_event(GtkWidget *widget, cairo_t *cr, void *opaque)
 {
 VirtualConsole *vc = opaque;
@@ -751,6 +770,7 @@ static gboolean gd_draw_event(GtkWidget *widget, cairo_t 
*cr, void *opaque)
 int mx, my;
 int ww, wh;
 int fbw, fbh;
+int refresh_rate_millihz;
 
 #if defined(CONFIG_OPENGL)
 if (vc->gfx.gls) {
@@ -771,6 +791,12 @@ static gboolean gd_draw_event(GtkWidget *widget, cairo_t 
*cr, void *opaque)
 return FALSE;
 }
 
+refresh_rate_millihz = gd_refresh_rate_millihz(vc->window ?
+   vc->window : s->window);
+if (refresh_rate_millihz) {
+vc->gfx.dcl.update_interval = MILLISEC_PER_SEC / refresh_rate_millihz;
+}
+
 fbw = surface_width(vc->gfx.ds);
 fbh = surface_height(vc->gfx.ds);
 
@@ -1949,31 +1975,11 @@ static GtkWidget 
*gd_create_menu_machine(GtkDisplayState *s)
 return machine_menu;
 }
 
-/*
- * If available, return the refresh rate of the display in milli-Hertz,
- * else return 0.
- */
-static int gd_refresh_rate_millihz(GtkWidget *window)
-{
-#ifdef GDK_VERSION_3_22
-GdkWindow *win = gtk_widget_get_window(window);
-
-if (win) {
-GdkDisplay *dpy = gtk_widget_get_display(window);
-GdkMonitor *monitor = gdk_display_get_monitor_at_window(dpy, win);
-
-return gdk_monitor_get_refresh_rate(monitor);
-}
-#endif
-return 0;
-}
-
 static GSList *gd_vc_gfx_init(GtkDisplayState *s, VirtualConsole *vc,
   QemuConsole *con, int idx,
   GSList *group, GtkWidget *view_menu)
 {
 bool zoom_to_fit = false;
-int refresh_rate_millihz;
 
 vc->label = qemu_console_get_label(con);
 vc->s = s;
@@ -2031,12 +2037,6 @@ static GSList *gd_vc_gfx_init(GtkDisplayState *s, 
VirtualConsole *vc,
 vc->gfx.kbd = qkbd_state_init(con);
 vc->gfx.dcl.con = con;
 
-refresh_rate_millihz = gd_refresh_rate_millihz(vc->window ?
-   vc->window : s->window);
-if (refresh_rate_millihz) {
-vc->gfx.dcl.update_interval = MILLISEC_PER_SEC / refresh_rate_millihz;
-}
-
 register_displaychangelistener(&vc->gfx.dcl);
 
 gd_connect_vc_gfx_signals(vc);
-- 
2.27.0

[PULL 0/4] Ui 20200904 patches

[Gerd Hoffmann]

The following changes since commit 67a7bfe560a1bba59efab085cb3430f45176d382:

  Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-09=
-03' into staging (2020-09-03 16:58:25 +0100)

are available in the Git repository at:

  git://git.kraxel.org/qemu tags/ui-20200904-pull-request

for you to fetch changes up to dc26435edb469ebdadf298dc3945b95d08f743d4:

  ui/gtk: Update refresh interval after widget is realized (2020-09-04 07:32:=
28 +0200)


ui: memleak fixes.
gtk: refresh interval fix.
spice: add mouse buttons.



Frediano Ziglio (1):
  ui: Add more mouse buttons to SPICE

Pan Nengyuan (2):
  ui/gtk-gl-area: Plug memleak in gd_gl_area_create_context()
  vnc-auth-sasl: Plug memleak in vnc_socket_ip_addr_string

Philippe Mathieu-Daud=C3=A9 (1):
  ui/gtk: Update refresh interval after widget is realized

 ui/gtk-gl-area.c   | 11 ++
 ui/gtk.c   | 52 +++---
 ui/spice-input.c   |  2 ++
 ui/vnc-auth-sasl.c |  1 +
 4 files changed, 40 insertions(+), 26 deletions(-)

--=20
2.27.0

[PULL 1/4] ui/gtk-gl-area: Plug memleak in gd_gl_area_create_context()

[Gerd Hoffmann]

From: Pan Nengyuan 

Receiving error in local variable err, and forgot to free it.
This patch check the return value of 'gdk_window_create_gl_context'
and 'gdk_gl_context_realize', then free err to fix it.

Reported-by: Euler Robot 
Signed-off-by: Pan Nengyuan 
Message-Id: <20200831134315.1221-6-pannengy...@huawei.com>
Signed-off-by: Gerd Hoffmann 
---
 ui/gtk-gl-area.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/ui/gtk-gl-area.c b/ui/gtk-gl-area.c
index 85f9d14c51f1..98c22d23f501 100644
--- a/ui/gtk-gl-area.c
+++ b/ui/gtk-gl-area.c
@@ -147,10 +147,21 @@ QEMUGLContext 
gd_gl_area_create_context(DisplayChangeListener *dcl,
 gtk_gl_area_make_current(GTK_GL_AREA(vc->gfx.drawing_area));
 window = gtk_widget_get_window(vc->gfx.drawing_area);
 ctx = gdk_window_create_gl_context(window, &err);
+if (err) {
+g_printerr("Create gdk gl context failed: %s\n", err->message);
+g_error_free(err);
+return NULL;
+}
 gdk_gl_context_set_required_version(ctx,
 params->major_ver,
 params->minor_ver);
 gdk_gl_context_realize(ctx, &err);
+if (err) {
+g_printerr("Realize gdk gl context failed: %s\n", err->message);
+g_error_free(err);
+g_clear_object(&ctx);
+return NULL;
+}
 return ctx;
 }
 
-- 
2.27.0

[PATCH] target-i386: seperate MCIP & MCE_MASK error reason

[zhenwei pi]

Previously we can only get a simple string "Triple fault" in qemu
log. Add detailed message for the two reasons to describe why qemu
has to reset the guest.

Signed-off-by: zhenwei pi 
---
 target/i386/helper.c | 25 ++---
 1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/target/i386/helper.c b/target/i386/helper.c
index 70be53e2c3..0c7fd32491 100644
--- a/target/i386/helper.c
+++ b/target/i386/helper.c
@@ -857,6 +857,8 @@ static void do_inject_x86_mce(CPUState *cs, run_on_cpu_data 
data)
 X86CPU *cpu = X86_CPU(cs);
 CPUX86State *cenv = &cpu->env;
 uint64_t *banks = cenv->mce_banks + 4 * params->bank;
+char msg[64];
+bool need_reset = false;
 
 cpu_synchronize_state(cs);
 
@@ -894,16 +896,25 @@ static void do_inject_x86_mce(CPUState *cs, 
run_on_cpu_data data)
 return;
 }
 
-if ((cenv->mcg_status & MCG_STATUS_MCIP) ||
-!(cenv->cr[4] & CR4_MCE_MASK)) {
-monitor_printf(params->mon,
-   "CPU %d: Previous MCE still in progress, raising"
-   " triple fault\n",
-   cs->cpu_index);
-qemu_log_mask(CPU_LOG_RESET, "Triple fault\n");
+if (cenv->mcg_status & MCG_STATUS_MCIP) {
+need_reset = true;
+snprintf(msg, sizeof(msg), "CPU %d: Previous MCE still in 
progress,"
+ " raising triple fault", cs->cpu_index);
+}
+
+if (!(cenv->cr[4] & CR4_MCE_MASK)) {
+need_reset = true;
+snprintf(msg, sizeof(msg), "CPU %d: MCE capability is not enabled,"
+ " raising triple fault", cs->cpu_index);
+}
+
+if (need_reset) {
+monitor_printf(params->mon, "%s", msg);
+qemu_log_mask(CPU_LOG_RESET, "%s\n", msg);
 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 return;
 }
+
 if (banks[1] & MCI_STATUS_VAL) {
 params->status |= MCI_STATUS_OVER;
 }
-- 
2.11.0

[PATCH] target/i386/cpu: add return value verification and ignore Error objects

[Pan Nengyuan]

'err' is unnecessary in x86_cpu_class_check_missing_features(), we can change 
x86_cpu_expand_features()
to return true on success, false on failure, then pass NULL here to remove it.

Signed-off-by: Pan Nengyuan 
Suggested-by: Markus Armbruster 
---
 target/i386/cpu.c | 15 +++
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 49d8958528..c3d3766133 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4883,7 +4883,7 @@ static void x86_cpu_parse_featurestr(const char 
*typename, char *features,
 }
 }
 
-static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
+static bool x86_cpu_expand_features(X86CPU *cpu, Error **errp);
 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose);
 
 /* Build a list with the name of all features on a feature word array */
@@ -4925,7 +4925,6 @@ static void 
x86_cpu_class_check_missing_features(X86CPUClass *xcc,
  strList **missing_feats)
 {
 X86CPU *xc;
-Error *err = NULL;
 strList **next = missing_feats;
 
 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
@@ -4937,8 +4936,7 @@ static void 
x86_cpu_class_check_missing_features(X86CPUClass *xcc,
 
 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
 
-x86_cpu_expand_features(xc, &err);
-if (err) {
+if (!x86_cpu_expand_features(xc, NULL)) {
 /* Errors at x86_cpu_expand_features should never happen,
  * but in case it does, just report the model as not
  * runnable at all using the "type" property.
@@ -4947,7 +4945,6 @@ static void 
x86_cpu_class_check_missing_features(X86CPUClass *xcc,
 new->value = g_strdup("type");
 *next = new;
 next = &new->next;
-error_free(err);
 }
 
 x86_cpu_filter_features(xc, false);
@@ -6426,7 +6423,7 @@ static void x86_cpu_enable_xsave_components(X86CPU *cpu)
 /* Expand CPU configuration data, based on configured features
  * and host/accelerator capabilities when appropriate.
  */
-static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
+static bool x86_cpu_expand_features(X86CPU *cpu, Error **errp)
 {
 CPUX86State *env = &cpu->env;
 FeatureWord w;
@@ -6436,14 +6433,14 @@ static void x86_cpu_expand_features(X86CPU *cpu, Error 
**errp)
 for (l = plus_features; l; l = l->next) {
 const char *prop = l->data;
 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) {
-return;
+return false;
 }
 }
 
 for (l = minus_features; l; l = l->next) {
 const char *prop = l->data;
 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) {
-return;
+return false;
 }
 }
 
@@ -6540,6 +6537,8 @@ static void x86_cpu_expand_features(X86CPU *cpu, Error 
**errp)
 if (env->cpuid_xlevel2 == UINT32_MAX) {
 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
 }
+
+return true;
 }
 
 /*
-- 
2.18.2

[PATCH] net/filter-rewriter: destroy g_hash_table in colo_rewriter_cleanup

[Pan Nengyuan]

s->connection_track_table forgot to destroy in colo_rewriter_cleanup. Fix it.

Reported-by: Euler Robot 
Signed-off-by: Pan Nengyuan 
---
 net/filter-rewriter.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/net/filter-rewriter.c b/net/filter-rewriter.c
index 1aaad101b6..9ff366d44f 100644
--- a/net/filter-rewriter.c
+++ b/net/filter-rewriter.c
@@ -376,6 +376,8 @@ static void colo_rewriter_cleanup(NetFilterState *nf)
 filter_rewriter_flush(nf);
 g_free(s->incoming_queue);
 }
+
+g_hash_table_destroy(s->connection_track_table);
 }
 
 static void colo_rewriter_setup(NetFilterState *nf, Error **errp)
-- 
2.18.2

Re: [PATCH] meson: install ivshmem-client and ivshmem-server

[Markus Armbruster]

Paolo Bonzini  writes:

> On 03/09/20 17:49, Daniel P. Berrangé wrote:
>> On Thu, Sep 03, 2020 at 05:44:25PM +0200, Paolo Bonzini wrote:
>>> On 03/09/20 17:35, Bruce Rogers wrote:
 Turn on the meson install flag for these executables

 Signed-off-by: Bruce Rogers 
 ---
  contrib/ivshmem-client/meson.build | 2 +-
  contrib/ivshmem-server/meson.build | 2 +-
  2 files changed, 2 insertions(+), 2 deletions(-)

 diff --git a/contrib/ivshmem-client/meson.build 
 b/contrib/ivshmem-client/meson.build
 index 1b171efb4f..83a559117f 100644
 --- a/contrib/ivshmem-client/meson.build
 +++ b/contrib/ivshmem-client/meson.build
 @@ -1,4 +1,4 @@
  executable('ivshmem-client', files('ivshmem-client.c', 'main.c'),
 dependencies: glib,
 build_by_default: targetos == 'linux',
 -   install: false)
 +   install: true)
 diff --git a/contrib/ivshmem-server/meson.build 
 b/contrib/ivshmem-server/meson.build
 index 3a53942201..a1c39aa3b3 100644
 --- a/contrib/ivshmem-server/meson.build
 +++ b/contrib/ivshmem-server/meson.build
 @@ -1,4 +1,4 @@
  executable('ivshmem-server', files('ivshmem-server.c', 'main.c'),
 dependencies: [qemuutil, rt],
 build_by_default: targetos == 'linux',
 -   install: false)
 +   install: true)

>>>
>>> They weren't installed before the conversion, were they?
>> 
>> Unfortunately they were historically installed with --enable-tools.
>> 
>> IMHO nothing in contrib/ should be installed by default. If we consider
>> something maintained and high enough quality for end users, it should
>> migrate out of contrib/ into tools/.
>
> Ah, via the tools variable in configure.  Nice maze.  I've queued the patch.

Please don't.

These programs are examples to help people understand how the ivhsmem
device works.  They might even be useful for debugging.  They are *not*
to be used in production.

docs/specs/ivshmem-spec.txt:

Example server code is in contrib/ivshmem-server/.  Not to be used in
production.  It assumes all clients use the same number of interrupt
vectors.

A standalone client is in contrib/ivshmem-client/.  It can be useful
for debugging.

Installing example *source* might make sense (but I doubt it).
Installing the binaries does not.

Re: [PATCH v6 1/8] monitor: simplify functions for getting a dup'd fdset entry

[Markus Armbruster]

Daniel P. Berrangé  writes:

> Currently code has to call monitor_fdset_get_fd, then dup
> the return fd, and then add the duplicate FD back into the
> fdset. This dance is overly verbose for the caller and
> introduces extra failure modes which can be avoided by
> folding all the logic into monitor_fdset_dup_fd_add and
> removing monitor_fdset_get_fd entirely.
>
> Signed-off-by: Daniel P. Berrangé 

Reviewed-by: Markus Armbruster 

Re: [PATCH] configure: the error info not consistence with option.

[Paolo Bonzini]

On 04/09/20 05:54, 罗勇刚(Yonggang Luo) wrote:
> 
>  test "$vhost_net_user" = "" && vhost_net_user=$vhost_user
>  if test "$vhost_net_user" = "yes" && test "$vhost_user" = "no";
> then
> -  error_exit "--enable-vhost-net-user requires --enable-vhost-user"
> +  error_exit "--enable-vhost-net requires --enable-vhost-user"
>  fi
> 
> 
> This change seems wrong.
> 
> I didn't found --enable-vhost-net-user option handling?
> you may grep it? 
> 
> 

You're right, it is all dead code.  The four lines are equivalent to
just vhost_net_user=$vhost_user.  You could also add
--enable-vhost-net-user though!

Thanks,

Paolo

Re: [PATCH] meson: install ivshmem-client and ivshmem-server

[Paolo Bonzini]

On 04/09/20 09:24, Markus Armbruster wrote:
>> Ah, via the tools variable in configure.  Nice maze.  I've queued the patch.
> Please don't.
> 
> These programs are examples to help people understand how the ivhsmem
> device works.  They might even be useful for debugging.  They are *not*
> to be used in production.

Okay. :)  It needs to be documented in the changelog.

Paolo

> docs/specs/ivshmem-spec.txt:
> 
> Example server code is in contrib/ivshmem-server/.  Not to be used in
> production.  It assumes all clients use the same number of interrupt
> vectors.
> 
> A standalone client is in contrib/ivshmem-client/.  It can be useful
> for debugging.
> 
> Installing example *source* might make sense (but I doubt it).
> Installing the binaries does not.
> 

Re: [PATCH v2] tests: Trying fixes test-replication.c on msys2.

[Paolo Bonzini]

On 04/09/20 00:06, Yonggang Luo wrote:
> Signed-off-by: Yonggang Luo 
> ---
>  tests/test-replication.c | 17 +
>  1 file changed, 13 insertions(+), 4 deletions(-)
> 
> diff --git a/tests/test-replication.c b/tests/test-replication.c
> index 9ab3666a90..d0e06f8d77 100644
> --- a/tests/test-replication.c
> +++ b/tests/test-replication.c
> @@ -23,14 +23,18 @@
>  
>  /* primary */
>  #define P_ID "primary-id"
> -static char p_local_disk[] = "/tmp/p_local_disk.XX";
> +#define P_LOCAL_DISK "%s/p_local_disk.XX"
> +static char p_local_disk[PATH_MAX];
>  
>  /* secondary */
>  #define S_ID "secondary-id"
>  #define S_LOCAL_DISK_ID "secondary-local-disk-id"
> -static char s_local_disk[] = "/tmp/s_local_disk.XX";
> -static char s_active_disk[] = "/tmp/s_active_disk.XX";
> -static char s_hidden_disk[] = "/tmp/s_hidden_disk.XX";
> +#define S_LOCAL_DISK "%s/s_local_disk.XX"
> +static char s_local_disk[PATH_MAX];
> +#define S_ACTIVE_DISK "%s/s_active_disk.XX"
> +static char s_active_disk[PATH_MAX];
> +#define S_HIDDEN_DISK "%s/s_hidden_disk.XX"
> +static char s_hidden_disk[PATH_MAX];
>  
>  /* FIXME: steal from blockdev.c */
>  QemuOptsList qemu_drive_opts = {
> @@ -571,7 +575,12 @@ static void setup_sigabrt_handler(void)
>  int main(int argc, char **argv)
>  {
>  int ret;
> +const char *tmpdir = g_get_tmp_dir();
>  qemu_init_main_loop(&error_fatal);
> +sprintf(p_local_disk, P_LOCAL_DISK, tmpdir);
> +sprintf(s_local_disk, S_LOCAL_DISK, tmpdir);
> +sprintf(s_active_disk, S_ACTIVE_DISK, tmpdir);
> +sprintf(s_hidden_disk, S_HIDDEN_DISK, tmpdir);
>  bdrv_init();
>  
>  g_test_init(&argc, &argv, NULL);
> 

Cc: qemu-bl...@nongnu.org

Re: [PATCH v5 06/20] tests/qapi/doc-good.json: Prepare for qapi-doc Sphinx extension

[Markus Armbruster]

Peter Maydell  writes:

> doc-good.json tests doc comment parser corner cases.  We're about to
> largely replace it by a Sphinx extension, which will have different
> corner cases.  Tweak the test so it passes both with the old parser
> and the Sphinx extension, by making it match the more restrictive
> rST syntax:
>
>  * in a single list the bullet types must all match
>  * lists must have leading and following blank lines
>  * indentation is important

Actually, indentation has always been important, but the conversion to
rST changes where and how it matters.  Perhaps:

   * the rules on when and where indentation matters differ

>  * the '|' example syntax is going to go away entirely, so stop
>testing it
>
> This will avoid the tests spuriously breaking when we tighten up the
> parser code in the following commits.
>
> Reviewed-by: Richard Henderson 
> Reviewed-by: Markus Armbruster 
> Signed-off-by: Peter Maydell 

Re: [PATCH] meson: fix qxl module build

[Gerd Hoffmann]

  Hi,

>  if config_all_devices.has_key('CONFIG_QXL')
>qxl_ss = ss.source_set()
> -  qxl_ss.add(when: 'CONFIG_QXL', if_true: files('qxl.c', 'qxl-logger.c', 
> 'qxl-render.c'))
> +  qxl_ss.add(files('qxl.c', 'qxl-logger.c', 'qxl-render.c'))
>hw_display_modules += {'qxl': qxl_ss}
>  endif
>  
> -softmmu_ss.add(when: 'CONFIG_QXL', if_true: files('qxl.c', 'qxl-logger.c', 
> 'qxl-render.c'))

Damn.  Turned out to not be that easy.  Modular builds work fine, but
with non-modular builds I have the problem that qxl_ss is merged into
softmmu_ss *unconditionally*.  So when building two targets, one with
qxl enabled (i386 for example) and one without pci support (avr for
example) I get missing symbols for pci+vga due to the attempt to link
qxl into avr-softmmu.

Any hints how to solve that one?

thanks,
  Gerd

Re: [PATCH v2 2/2] GitLab Gating CI: initial set of jobs, documentation and scripts

[Daniel P . Berrangé]

On Thu, Sep 03, 2020 at 08:11:39PM -0400, Cleber Rosa wrote:
> On Thu, Jul 09, 2020 at 11:30:29AM +0100, Daniel P. Berrangé wrote:
> > On Wed, Jul 08, 2020 at 10:46:57PM -0400, Cleber Rosa wrote:
> > > This is a mapping of Peter's "remake-merge-builds" and
> > > "pull-buildtest" scripts, gone through some updates, adding some build
> > > option and removing others.
> > > 
> > > The jobs currently cover the machines that the QEMU project owns, and that
> > > are setup and ready to run jobs:
> > > 
> > >  - Ubuntu 18.04 on S390x
> > >  - Ubuntu 20.04 on aarch64
> > > 
> > > During the development of this set of jobs, the GitLab CI was tested
> > > with many other architectures, including ppc64, s390x and aarch64,
> > > along with the other OSs (not included here):
> > > 
> > >  - Fedora 30
> > >  - FreeBSD 12.1
> > > 
> > > More information can be found in the documentation itself.
> > > 
> > > Signed-off-by: Cleber Rosa 
> > > ---
> > >  .gitlab-ci.d/gating.yml| 146 +
> > 
> > AFAIK, the jobs in this file just augment what is already defined
> > in the main .gitlab-ci.yml. Also since we're providing setup info
> > for other people to configure custom runners, these jobs are usable
> > for non-gating CI scenarios too.
> >
> 
> If you mean that they introduced new jobs, you're right.
> 
> > IOW, the jobs in this file happen to be usable for gating, but they
> > are not the only gating jobs, and can be used for non-gating reasons.
> >
> 
> Right, I do not doubt these jobs may be useful to other people and on
> scenarios other than "before merging a patch series".
> 
> > This is a complicated way of saying that gating.yml is not a desirable
> > filename, so I'd suggest splitting it in two and having these files
> > named based on what their contents is, rather than their use case:
> > 
> >.gitlab-ci.d/runners-s390x.yml
> >.gitlab-ci.d/runners-aarch64.yml
> > 
> > The existing jobs in .gitlab-ci.yml could possibly be moved into
> > a .gitlab-ci.d/runners-shared.yml file for consistency.
> >
> 
> Do you imply that every gitlab CI job should be a gating job?  And
> that the same jobs should be used when other people with their own
> forks?  I find this problematic because:
> 
> * It would trigger pipelines with jobs that, unless every user has the
>   same runners configured, would have unfulfilled jobs that don't have
>   a matching hardware.

Jobs that require a custom runner should not be set to run by default,
but individual contributors must absolutely be able to opt-in to running
those jobs simply by registering a runner on their account.

> * It dilutes the idea that those jobs are inherently different with
>   regards to the management of their infrastructure.

I don't really know what yiu mean here, but "Inherantly different"
does not sound like a desirable property.

> * It destroys the notion of layered testing, for whatever people find
>   that worth it, where a faster turnaround could/would be possible
>   with fewer jobs for every push, and many more jobs before a merge.

The key goal of CI is to reduce the burden on maintainers. The biggest
cost is if we merge code and failure is noticed after merge. IT is
still a large cost, however, if Peter only finds a CI failure when he
attempts the pre-merge test. He has to throw out the pull request
putting more work on the subsystem maintainer. The subsystem maintainer
may have to throw it back to the original author.

The ideal scenario that we need to strive towards is that the original
author has tested their code with 100% coverage of all the CI jobs QMEU
has defined.

Any time there is a job that is not run by authors, but only by the
maintainers, we are putting increased burden on the maintainers, so
must be minimize that.

IOW, layered testing is not desirable as goal. Rather layered testing
is just a default setup, but we'd encourage contributors to run the
full set of CI jobs, especially if they are frequent contributors.
The more they run themselves, the less burden on subsystem maintainers
and Peter, and thus the better we all scale.

> Finally, I find the split by runner architecture you suggested
> problematic because different organizations may have jobs for the same
> architecture.  I believe that files for different organizations may be
> a better organization instead.  Entries in the MAINTAINERS are one
> example where the grouping by architecture may not be optimal.

I don't think we should be structuring jobs around organizations. We
should be defining a set of desired jobs we wish to be able to run.
Any organization can bring a runner that is capable of running the
jobs and donate it to the QEMU project for our formal CI runner
The organization is not defining the job though - QEMU is  defining
the jobs we expect to have used for testing.

This is key because any contributor needs to be able to spin up an
identical envrionment to replicate any build failures. We don't want
runners for merge testing 

Re: [PATCH v2 2/2] GitLab Gating CI: initial set of jobs, documentation and scripts

[Daniel P . Berrangé]

On Thu, Sep 03, 2020 at 08:18:17PM -0400, Cleber Rosa wrote:
> On Thu, Jul 09, 2020 at 01:28:27PM +0200, Andrea Bolognani wrote:
> > On Thu, 2020-07-09 at 11:30 +0100, Daniel P. Berrangé wrote:
> > > On Wed, Jul 08, 2020 at 10:46:57PM -0400, Cleber Rosa wrote:
> > > > +- name: Installation of basic packages to build QEMU
> > > > +  hosts: all
> > > > +  vars_files:
> > > > +- vars.yml
> > > > +  tasks:
> > > > +- name: Install basic packages to build QEMU on Ubuntu 18.04/20.04
> > > > +  apt:
> > > > +update_cache: yes
> > > > +# This matches the packages on 
> > > > tests/docker/Dockerfiles/ubuntu1804.docker
> > > 
> > > I'd be inclined to actually use docker on the custom runners.
> > > 
> > > eg. instead of having separate physical machines or VMs for each
> > > (distro, arch) pair, have a single host distro for the arch. Then
> > > use docker to provide the build environment against each distro.
> > > 
> > > IOW, a RHEL-8 aarch64 host, running docker for ubuntu18.04, fedora30
> > > etc.
> > > 
> > > That way we don't end up duplicating all these packages, and instead
> > > can use  tests/docker/Dockerfiles/ubuntu1804.docker.  This ensures
> > > that if a user needs to reproduce a build failure on their own local
> > > aarch64 machine, they can run docker and get the exact same build
> > > architecture.
> > > 
> > > It also has the benefit that we don't need to worry about how to
> > > setup gitlab runners for every distro we care about. We only need to
> > > do gitlab runner for the standard host distro, which spawns a pristine
> > > throwaway docker env.
> > > 
> > > I appreciate this is a big change from what you've done in this patch
> > > though, so don't consider this comment a blocker for initial merge.
> > > I think we should do this as the long term strategy though. Essentially
> > > for Linux builds, everything should always be container based.
> > 
> > Agreed. You should be able to set up a fairly minimal environment,
> > which consists of Docker, gitlab-runner and not much else, using a
> > long-term supported distro such as CentOS and then just schedule
> > whatever container build on it. No need to provision a new machine
> > every time a new Fedora release comes out, just create a container
> > image for it and add it to the mix.
> >
> 
> Hi Andrea,
> 
> There's nothing preventing this from happening, but limiting the
> runners to this configuration, prevents a lot more from happening.
> 
> > Additionally, the gitlab-runner Docker executor provides more
> > isolation than the shell executor, so running untrusted builds
> > becomes a more reasonable proposition - this is how the shared
> > runners on gitlab.com work - and you don't have to worry about your
> > jobs cleaning up properly after themselves nearly as much.
> >
> 
> I understand and agree to the the benefits of using the gitlab-runner
> Docker executor... until you want to run tests on non-Docker
> environments :).
> 
> Hopefully the explanation on my previous reply to Daniel will also
> serve for the points you raised here.  I would have loved to have
> worked on a more abstract, container only environments, but that
> proved to be unrealistic.

For Linux targets, it should be possible to have exclusively container
based testing environments. At worst you can run a privileged container
and expose arbitrary host resources to it, so you can do anything in
the container that you would otherwise do in bare metal. For non-Linux,
we should be able to satisfy our needs with VMs, and indeed VMs can
be used for Linux too if we want to emulate some specific hardware for
testing that we don't have accessible to containers on bare metal.
IOW, the testing environment can be entirely defined by the recipes
we have in tests/docker and tests/vm. Bare metal hosts are simply a
way to host the containers or vms.


Regards,
Daniel
-- 
|: https://berrange.com  -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
|: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|

Re: [PATCH] iotests: Remove 030 from the auto group

[Kevin Wolf]

Am 04.09.2020 um 07:57 hat Thomas Huth geschrieben:
> Test 030 is still occasionally failing in the CI ... so for the
> time being, let's disable it in the "auto" group. We can add it
> back once it got more stable.
> 
> Signed-off-by: Thomas Huth 

I would rather just disable this one test function as 030 is a pretty
important one that tends to catch bugs.

>  I just saw the problem here:
>   https://cirrus-ci.com/task/5449330930745344?command=main#L6482
>  and Peter hit it a couple of weeks ago:
>   https://lists.gnu.org/archive/html/qemu-devel/2020-08/msg00136.html

I wonder how this can still happen. The test should have more than
enough time to complete now. Except if the throttling doesn't work as
expected.

I can't seem to reproduce this even if I add rather long delays. After
40 seconds, all jobs have moved either by 512k (which is STREAM_CHUNK)
or not at all.

What is interesting is that in both cases it's stream-node8, which is
the job streaming from node6 to node8, and node8 is the top-level node.
It's also the last job to be changed to full speed, so all others did
succeed before.

Kevin

i440fx/acpi: don't hot-unplug cold plugged bridges when their hotplug switch is off

[Ani Sinha]

I have seen that when hotplug for pci bridge devices are turned off and devices 
are attached
behind the bridge, I still see Windows trying to hot remove the pci bridge and 
failing. Today
looking at the AML disassembly, I realized that we are addding slot enumeration 
and EJ0
methods even for the slot where the bridge is attached. 

Please see the video: https://youtu.be/pME2sjyQweo

This does not seem right. A cold-plugged bridge should not be hot removable 
under any
conditions. Hence, this patch tries to address this. After the change, as the 
demo video
shows, Windows no longer shows the bridge device as hot removable:  
https://youtu.be/kbgej5B9Hgs
under the same test settings.

Requesting comments for this fix.

--Ani
 

[PATCH v1] i440fx/acpi: don't hot-unplug cold plugged bridges when their hotplug switch is off

[Ani Sinha]

Cold plugged bridges should not be hot unpluggable, even when their hotplug 
property
(acpi-pci-hotplug-with-bridge-support) is turned off. However, with the current
implementaton, windows would try to hot-unplug a pci bridge when it's hotplug 
switch
is off. This is regardless of whether there are devices attached to the bridge. 
When
devices are attached to the bridge, the bridge is ultimately not 
hot-unpluggable. We
have a demo video here: https://youtu.be/pME2sjyQweo

In this fix, we identify a cold plugged bridge and for cold plugged bridges, we 
do not
add the appropriate amls and acpi methods that are used by the OS to identify a 
hot-
unpluggable pci device. After this change, Windows does not show an option to 
eject the
PCI bridge. A demo video is here:  https://youtu.be/kbgej5B9Hgs

While at it, I have also updated a stale comment.

This change is tested with a Windows 2012R2 guest image running on Ubuntu host. 
This
change is based off of upstream qemu master branch tag v5.1.0.

Signed-off-by: Ani Sinha 
---
 hw/i386/acpi-build.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index b7bc2a..90b863f4ec 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -359,6 +359,7 @@ static void build_append_pci_bus_devices(Aml *parent_scope, 
PCIBus *bus,
 int slot = PCI_SLOT(i);
 bool hotplug_enabled_dev;
 bool bridge_in_acpi;
+bool cold_plugged_bridge;
 
 if (!pdev) {
 if (bsel) { /* add hotplug slots for non present devices */
@@ -380,15 +381,14 @@ static void build_append_pci_bus_devices(Aml 
*parent_scope, PCIBus *bus,
 pc = PCI_DEVICE_GET_CLASS(pdev);
 dc = DEVICE_GET_CLASS(pdev);
 
-/* When hotplug for bridges is enabled, bridges are
- * described in ACPI separately (see build_pci_bus_end).
- * In this case they aren't themselves hot-pluggable.
+/*
+ * Cold plugged bridges aren't themselves hot-pluggable.
  * Hotplugged bridges *are* hot-pluggable.
  */
-bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
-!DEVICE(pdev)->hotplugged;
+cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged;
+bridge_in_acpi =  cold_plugged_bridge && pcihp_bridge_en;
 
-hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
+hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge;
 
 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
 continue;
-- 
2.17.1

Re: [PATCH] iotests: Remove 030 from the auto group

[Max Reitz]

On 04.09.20 07:57, Thomas Huth wrote:
> Test 030 is still occasionally failing in the CI ... so for the
> time being, let's disable it in the "auto" group. We can add it
> back once it got more stable.
> 
> Signed-off-by: Thomas Huth 
> ---
>  I just saw the problem here:
>   https://cirrus-ci.com/task/5449330930745344?command=main#L6482
>  and Peter hit it a couple of weeks ago:
>   https://lists.gnu.org/archive/html/qemu-devel/2020-08/msg00136.html
> 
>  tests/qemu-iotests/group | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Thanks, applied to my block branch:

https://git.xanclic.moe/XanClic/qemu/commits/branch/block



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