[PATCH 2/2] hw/riscv: Don't add empty bootargs to device tree
From: Bin Meng
Commit 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
tried to avoid adding *NULL* bootargs to device tree, but unfortunately
the changes were entirely useless, due to MachineState::kernel_cmdline
can't be NULL at all as the default value is given as an empty string.
(see hw/core/machine.c::machine_initfn()).
Note the wording of *NULL* bootargs is wrong. It can't be NULL otherwise
a segfault had already been observed by dereferencing the NULL pointer.
It should be worded as *empty" bootargs.
Fixes: 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
Signed-off-by: Bin Meng
---
hw/riscv/microchip_pfsoc.c | 2 +-
hw/riscv/sifive_u.c| 2 +-
hw/riscv/spike.c | 2 +-
hw/riscv/virt.c| 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index cafd1fc9ae..10a5d0e501 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -571,7 +571,7 @@ static void microchip_icicle_kit_machine_init(MachineState
*machine)
"linux,initrd-end", end);
}
-if (machine->kernel_cmdline) {
+if (machine->kernel_cmdline && *machine->kernel_cmdline) {
qemu_fdt_setprop_string(machine->fdt, "/chosen",
"bootargs", machine->kernel_cmdline);
}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7fbc7dea42..cc8c7637cb 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -511,7 +511,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry
*memmap,
g_free(nodename);
update_bootargs:
-if (cmdline) {
+if (cmdline && *cmdline) {
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
}
}
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 1562b000bb..068ba3493e 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -177,7 +177,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry
*memmap,
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
-if (cmdline) {
+if (cmdline && *cmdline) {
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
}
}
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index da50cbed43..a628a3abdf 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -998,7 +998,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry
*memmap,
create_fdt_flash(s, memmap);
update_bootargs:
-if (cmdline) {
+if (cmdline && *cmdline) {
qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline);
}
}
--
2.25.1
[PATCH 1/2] hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionally
From: Bin Meng
At present the adding '/chosen/stdout-path' property in device tree
is determined by whether a kernel command line is provided, which is
wrong. It should be added unconditionally.
Fixes: 8d8897accb1c ("hw/riscv: spike: Allow using binary firmware as bios")
Signed-off-by: Bin Meng
---
hw/riscv/spike.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index d059a67f9b..1562b000bb 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -174,10 +174,11 @@ static void create_fdt(SpikeState *s, const MemMapEntry
*memmap,
riscv_socket_fdt_write_distance_matrix(mc, fdt);
+qemu_fdt_add_subnode(fdt, "/chosen");
+qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
+
if (cmdline) {
-qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
-qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
}
}
--
2.25.1
Re: [PATCH v4 3/3] tests/qtest: Add test for Aspeed HACE accumulative mode
On Thu, 31 Mar 2022 at 07:49, Steven Lee wrote:
>
> This add two addition test cases for accumulative mode under sg enabled.
>
> The input vector was manually craft with "abc" + bit 1 + padding zeros + L.
> The padding length depends on algorithm, i.e. SHA512 (1024 bit),
> SHA256 (512 bit).
>
> The result was calculated by command line sha512sum/sha256sum utilities
> without padding, i.e. only "abc" ascii text.
>
> Signed-off-by: Troy Lee
> Signed-off-by: Steven Lee
Reviewed-by: Joel Stanley
Thanks for sending this series. I will try to find time to review the
model updates soon.
> ---
> tests/qtest/aspeed_hace-test.c | 145 +
> 1 file changed, 145 insertions(+)
>
> diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspeed_hace-test.c
> index 09ee31545e..6a2f404b93 100644
> --- a/tests/qtest/aspeed_hace-test.c
> +++ b/tests/qtest/aspeed_hace-test.c
> @@ -21,6 +21,7 @@
> #define HACE_ALGO_SHA512(BIT(5) | BIT(6))
> #define HACE_ALGO_SHA384(BIT(5) | BIT(6) | BIT(10))
> #define HACE_SG_EN BIT(18)
> +#define HACE_ACCUM_EN BIT(8)
>
> #define HACE_STS 0x1c
> #define HACE_RSA_ISRBIT(13)
> @@ -96,6 +97,57 @@ static const uint8_t test_result_sg_sha256[] = {
> 0x55, 0x1e, 0x1e, 0xc5, 0x80, 0xdd, 0x6d, 0x5a, 0x6e, 0xcd, 0xe9, 0xf3,
> 0xd3, 0x5e, 0x6e, 0x4a, 0x71, 0x7f, 0xbd, 0xe4};
>
> +/*
> + * The accumulative mode requires firmware to provide internal initial state
> + * and message padding (including length L at the end of padding).
> + *
> + * This test vector is a ascii text "abc" with padding message.
> + *
> + * Expected results were generated using command line utitiles:
> + *
> + * echo -n -e 'abc' | dd of=/tmp/test
> + * for hash in sha512sum sha256sum; do $hash /tmp/test; done
> + */
> +static const uint8_t test_vector_accum_512[] = {
> +0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18};
> +
> +static const uint8_t test_vector_accum_256[] = {
> +0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18};
> +
> +static const uint8_t test_result_accum_sha512[] = {
> +0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49,
> +0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2,
> +0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a,
> +0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd,
> +0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f,
> +0xa5, 0x4c, 0xa4, 0x9f};
> +
> +static const uint8_t test_result_accum_sha256[] = {
> +0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde,
> +0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c,
> +0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad};
>
> static void write_regs(QTestState *s, uint32_t base, uint32_t src,
> uint32_t length, uint32_t out, uint32_t method)
> @@ -308,6 +360,86 @@ static void test_sha512_sg(const char *machine, const
> uint32_t base,
> qtest_quit(s);
> }
>
> +static void test_sha256_accum(const char *machine, const uint32_t base,
> +const uint32_t src_addr)
> +{
> +QTestState *s = qtest_init(machine);
> +
> +const uint32_t buffer_addr = src_addr + 0x100;
> +const uint32_t digest_addr = src_addr + 0x400;
> +uint8_t digest[32] = {0};
> +struct AspeedSgList array[] = {
> +{ cpu_to_le32(sizeof(test_vector_accum_256) | SG_LIST_LEN_LAST),
> + cpu_to_le32(buffer_addr) },
> +};
> +
> +/* Check engine is idle, no busy or irq bits set */
> +g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0);
> +
> +/* Write test vector into memory */
> +
Re: [PULL 0/4] tcg patch queue
On 4/20/22 12:16, Richard Henderson wrote: The following changes since commit 2d20a57453f6a206938cbbf77bed0b378c806c1f: Merge tag 'pull-fixes-for-7.1-200422-1' of https://github.com/stsquad/qemu into staging (2022-04-20 11:13:08 -0700) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220420 for you to fetch changes up to a61532faa5a4d5e021e35b6a4a1e180c72d4a22f: tcg: Add tcg_constant_ptr (2022-04-20 12:12:47 -0700) Cleanup sysemu/tcg.h usage. Fix indirect lowering vs cond branches Remove ATOMIC_MMU_IDX Add tcg_constant_ptr Applied, thanks. Please update the wiki changelog for 7.1 as appropriate. r~ Richard Henderson (3): tcg: Fix indirect lowering vs TCG_OPF_COND_BRANCH accel/tcg: Remove ATOMIC_MMU_IDX tcg: Add tcg_constant_ptr Thomas Huth (1): Don't include sysemu/tcg.h if it is not necessary include/tcg/tcg.h| 4 accel/tcg/cputlb.c | 1 - accel/tcg/hmp.c | 1 - accel/tcg/tcg-accel-ops-icount.c | 1 - accel/tcg/user-exec.c| 1 - bsd-user/main.c | 1 - hw/virtio/vhost.c| 1 - linux-user/main.c| 1 - monitor/misc.c | 1 - target/arm/helper.c | 1 - target/s390x/cpu_models_sysemu.c | 1 - target/s390x/helper.c| 1 - tcg/tcg.c| 34 +++--- 13 files changed, 31 insertions(+), 18 deletions(-)
Re: [PATCH v1 33/43] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)
On 2022/4/20 上午1:14, Richard Henderson wrote:
The emulate of PCH_PIC_CLR in qemu LoongArchPCHPIC struct member is
intirr_lo/hi(we devide 64bits reg to two 32bits reg to match the
linux kernel), it will be changed when we config clear reg or handler
irq.
static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
...
case PCH_PIC_INT_CLEAR_LO:
if (s->intedge_lo & data) {
s->intirr_lo &= (~data);
pch_pic_update_irq(s, data, 0, 0);
s->intisr_lo &= (~data);
}
break;
case PCH_PIC_INT_CLEAR_HI:
if (s->intedge_hi & data) {
s->intirr_hi &= (~data);
pch_pic_update_irq(s, data, 0, 1);
s->intisr_hi &= (~data);
}
break;
One can just as easily do
case PCH_PIC_INT_CLEAR_LO:
data = (uint32_t)data;
goto do_clear;
case PCH_PIC_INT_CLEAR_HI:
data <<= 32;
do_clear:
s->intrr &= ~data;
pch_pic_update_irq(s...);
s->intrs &= ~data;
with the values internal to qemu be represented with uint64_t instead
of a pair of uint32_t. Which would in fact be *much* clearer to read,
and would seem to cut down the number of code lines required by half.
Sorry, I didn't understand your means before.
I will fix it in this way. Repalcing pch_pic uint32 registers with
uint64 and fix its' reading/writing options to keep consistency with the
document.
Thanks.
Xiaojuan
Re: XIVE VFIO kernel resample failure in INTx mode under heavy load
On 14/04/2022 22:41, Cédric Le Goater wrote: After re-reading what I just wrote, I am leaning towards disabling use of KVM_CAP_IRQFD_RESAMPLE as it seems last worked on POWER8 and never since :) Did I miss something in the picture (hey Cedric)? How about disabling it like this? = diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 5bfd4aa9e5aa..c999f7b1ab1b 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -732,7 +732,7 @@ static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); PCIINTxRoute route; - route.mode = PCI_INTX_ENABLED; + route.mode = PCI_INTX_DISABLED; = I like it. The only thing is that this resampling works on POWER8/XICS and removing it there is not great. So far sPAPR PHB was unaware of underlying interrupt controller, or was not it? You now know how to test all the combinations :) Prepare your matrix, variables are : * Host OS POWER8, POWER9+ * KVM device XICS (P8), XICS-on-XIVE (P9), XIVE-on-XIVE (P9) * kernel_irqchip off, on * ic-mode xics, xive * Guest OS msi or nomsi Ideally you should check TCG, but that's like kernel_irqchip=off. Cheers, C. (btw what the heck is PCI_INTX_INVERTED for?) -- Alexey -- Alexey
Re: [PATCH v4 0/6] hw/riscv: Add TPM support to the virt board
On Wed, Apr 20, 2022 at 1:52 PM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> This series adds support for connecting TPM devices to the RISC-V virt
> board. This is similar to how it works for the ARM virt board.
>
> This was tested by first creating an emulated TPM device:
>
> swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \
> --ctrl type=unixio,path=swtpm-sock
>
> Then launching QEMU with:
>
> -chardev socket,id=chrtpm,path=swtpm-sock \
> -tpmdev emulator,id=tpm0,chardev=chrtpm \
> -device tpm-tis-device,tpmdev=tpm0
>
> The TPM device can be seen in the memory tree and the generated device
> tree.
Please include a 'virt' board documentation update patch to mention
above usage for TPM, or dynamically instantiated devices with TPM as
an example.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/942
>
> Alistair Francis (6):
> hw/riscv: virt: Add a machine done notifier
> hw/core: Move the ARM sysbus-fdt to core
> hw/riscv: virt: Create a platform bus
> hw/riscv: virt: Add support for generating platform FDT entries
> hw/riscv: virt: Add device plug support
> hw/riscv: Enable TPM backends
>
> include/hw/{arm => core}/sysbus-fdt.h | 0
> include/hw/riscv/virt.h | 8 +-
> hw/arm/virt.c | 2 +-
> hw/arm/xlnx-versal-virt.c | 1 -
> hw/{arm => core}/sysbus-fdt.c | 2 +-
> hw/riscv/virt.c | 312 +-
> hw/arm/meson.build| 1 -
> hw/core/meson.build | 1 +
> hw/riscv/Kconfig | 2 +
> 9 files changed, 221 insertions(+), 108 deletions(-)
> rename include/hw/{arm => core}/sysbus-fdt.h (100%)
> rename hw/{arm => core}/sysbus-fdt.c (99%)
>
Regards,
Bin
Re: [PATCH v2] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values
On Wed, Apr 20, 2022 at 5:57 PM wrote: > > From: Frank Chang > > Allow user to set core's marchid, mvendorid, mipid CSRs through > -cpu command line option. > > The default values of marchid and mipid are built with QEMU's version > numbers. > > Signed-off-by: Frank Chang > Reviewed-by: Jim Shu > Reviewed-by: Alistair Francis > --- > target/riscv/cpu.c | 9 + > target/riscv/cpu.h | 4 > target/riscv/csr.c | 38 ++ > 3 files changed, 47 insertions(+), 4 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH v4 2/3] aspeed/hace: Support AST2600 HACE
The 04/20/2022 20:53, Cédric Le Goater wrote:
> On 3/31/22 09:48, Steven Lee wrote:
> > The aspeed ast2600 accumulative mode is described in datasheet
> > ast2600v10.pdf section 25.6.4:
> > 1. Allocating and initiating accumulative hash digest write buffer
> > with initial state.
> > * Since QEMU crypto/hash api doesn't provide the API to set initial
> >state of hash library, and the initial state is already setted by
>
> s/setted/set/
>
will fix it.
> >crypto library (gcrypt/glib/...), so skip this step.
> > 2. Calculating accumulative hash digest.
> > (a) When receiving the last accumulative data, software need to add
> > padding message at the end of the accumulative data. Padding
> > message described in specific of MD5, SHA-1, SHA224, SHA256,
> > SHA512, SHA512/224, SHA512/256.
> > * Since the crypto library (gcrypt/glib) already pad the
> >padding message internally.
> > * This patch is to remove the padding message which fed byguest
> >machine driver.
> >
> > Signed-off-by: Troy Lee
> > Signed-off-by: Steven Lee
> > ---
> > hw/misc/aspeed_hace.c | 140 --
> > 1 file changed, 136 insertions(+), 4 deletions(-)
> >
> > diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
> > index 59fe5bfca2..5a7a144602 100644
> > --- a/hw/misc/aspeed_hace.c
> > +++ b/hw/misc/aspeed_hace.c
> > @@ -95,12 +95,115 @@ static int hash_algo_lookup(uint32_t reg)
> > return -1;
> > }
> >
> > -static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode)
> > +/**
> > + * Check whether the request contains padding message.
> > + *
> > + * @param iov iov of current request
> > + * @param idindex of iov of current request
> > + * @param total_req_len length of all acc_mode requests(including padding
> > msg)
> > + * @param req_len length of the current request
> > + * @param total_msg_len length of all acc_mode requests(excluding padding
> > msg)
> > + * @param pad_offsetstart offset of padding message
> > + */
> > +static bool has_padding(struct iovec *iov, uint32_t total_req_len,
> > +hwaddr req_len, uint32_t *total_msg_len,
> > +uint32_t *pad_offset)
> > +{
> > +*total_msg_len = (uint32_t)(ldq_be_p(iov->iov_base + req_len - 8) / 8);
> > +/*
> > + * SG_LIST_LEN_LAST asserted in the request length doesn't mean it is
> > the
> > + * last request. The last request should contain padding message.
> > + * We check whether message contains padding by
> > + * 1. Get total message length. If the current message contains
> > + * padding, the last 8 bytes are total message length.
> > + * 2. Check whether the total message length is valid.
> > + * If it is valid, the value should less than or eaual to
>
> s/eaual/equal/
>
will fix it.
> > + * total_req_len.
> > + * 3. Current request len - padding_size to get padding offset.
> > + * The padding message's first byte should be 0x80
> > + */
> > +if (*total_msg_len <= total_req_len) {
> > +uint32_t padding_size = total_req_len - *total_msg_len;
> > +uint8_t *padding = iov->iov_base;
> > +*pad_offset = req_len - padding_size;
> > +if (padding[*pad_offset] == 0x80) {
> > +return true;
> > +}
> > +}
> > +
> > +return false;
> > +}
> > +
> > +static int reconstruct_iov(struct iovec *cache, struct iovec *iov, int id,
> > + uint32_t *total_req_len,
> > + uint32_t *pad_offset,
> > + int *count)
> > +{
> > +int i, iov_count;
> > +if (pad_offset != 0) {
> > +(cache + *count)->iov_base = (iov + id)->iov_base;
>
> I would prefer the array notation iov[i], like elsewhere in this file..
>
will use iov[i] instead of (iov + i).
> > +(cache + *count)->iov_len = *pad_offset;
> > +++*count;
> > +}
> > +for (i = 0; i < *count; i++) {
> > +(iov + i)->iov_base = (cache + i)->iov_base;
> > +(iov + i)->iov_len = (cache + i)->iov_len;
>
> ditto.
>
will use iov[i] instead of (iov + i).
> > +}
> > +iov_count = *count;
> > +*count = 0;
> > +*total_req_len = 0;
> > +return iov_count;
> > +}
> > +
> > +/**
> > + * Generate iov for accumulative mode.
> > + *
> > + * @param cache cached iov
> > + * @param iov iov of current request
> > + * @param idindex of iov of current request
> > + * @param total_req_len total length of the request(including padding)
> > + * @param req_len length of the current request
> > + * @param count count of cached iov
> > + */
> > +static int gen_acc_mode_iov(struct iovec *cache, struct iovec *iov, int id,
> > +uint32_t *total_req_len, hwaddr *req_len,
> > +
Re: [RFC PATCH v3 1/5] ppc64: Add semihosting support
Excerpts from Leandro Lupori's message of April 21, 2022 4:09 am: > On 4/18/22 17:22, Cédric Le Goater wrote: >> On 4/18/22 21:10, Leandro Lupori wrote: >>> Add semihosting support for PPC64. This implementation is >>> based on the standard for ARM semihosting version 2.0, as >>> implemented by QEMU and documented in >>> >>> https://github.com/ARM-software/abi-aa/releases >>> >>> The PPC64 specific differences are the following: >>> >>> Semihosting Trap Instruction: sc 7 >>> Operation Number Register: r3 >>> Parameter Register: r4 >>> Return Register: r3 >>> Data block field size: 64 bits >> >> 'sc' is a good way to implement semi hosting but we should make sure >> that it is not colliding with future extensions, at least with the >> next POWERPC processor. Is that the case ? if not, then the lev could >> be reserved. >> > > Power ISA 3.1B says that LEV values greater that 2 are reserved. > Level 2 is the ultravisor, so I assumed that level 7 was far enough from > current max level. I don't know if POWER11 will introduce new privilege > levels. Is this info publicly available somewhere? Or do you have a > better level in mind to use instead? It's not available but there are no plans to use LEV=7. It would be fine in practice I think, but it's kind of ugly and not great precedent -- how would we find out all the projects which use reserved instructions or values for something? Nominally the onus is on the software to accept breakage, but in reality important software that breaks causes a headache for the ISA. IBM's systemsim emulator actually has an instruction to call out to the emulator to do various things like IO. It uses the opcode .long 0x000eaeb0 That is the primary op 0 reserved space, and there is actually another op 'attn' or 'sp_attn' there which IBM CPUs implement, it is similar in spirit (it calls out to the service processor and/or chip error handling system to deal with a condition out-of-band). You don't want to use attn here because the core under emulation might implement it, I'm just noting the precedent with similar functionality under this primary opcode. So I think the systemsim emulator instruction should be a good choice. But it should really be documented. I will bring this up at the Open Power ISA working group meeting next week and see what the options are with getting it formally allocated for semihosting emulators (or what the alternatives are). Thanks, Nick
a qemu process has 54 threads, how to know who they are and what they are doing
Hi, i think it is curios for a process to have so many threads. my environment: 5.4.160-1.el7.x86_64, qemu-6.1.0 thanks =cmd== root 11918 0.0 0.0 112720 2280 pts/0S+ 09:30 0:00 grep --color=auto 38032 root 38032 58.0 1.0 8705632 2823304 ? Sl Apr19 1451:10 /opt/kata/bin/qemu-system-x86_64 -name sandbox-598c832569b63321f393b1f ef6d23cb209a9668a17f3b56a8eb87171506baaf8 -uuid 9ab925f1-86f2-4703-801e-be23ce0fdca6 -machine q35,accel=kvm,kernel_irqchip=on,nvdimm=on -cpu host,pmu=off -qmp unix:/run/vc/vm/598c832569b63321f393b1fef6d23cb209a9668a17f3b56a8eb87171506baaf8/qmp.sock,server=on,wait=off -qmp unix:/run/vc/vm/598c832569b63321f393b1fef6d23cb209a9668a17f3b56a8eb87171506baaf8/qmp-guestcsi.sock,server=on,wait=off -qmp unix:/run/vc /vm/598c832569b63321f393b1fef6d23cb209a9668a17f3b56a8eb87171506baaf8/qmp-guestcni.sock,server=on,wait=off -m 4352M,slots=10,maxmem=25856 2M -device pci-bridge,bus=pcie.0,id=pci-bridge-0,chassis_nr=1,shpc=off,addr=2,io-reserve=4k,mem-reserve=1m,pref64-reserve=1m -device vir tio-serial-pci,disable-modern=false,id=serial0 -device virtconsole,chardev=charconsole0,id=console0 -chardev socket,id=charconsole0,path =/run/vc/vm/598c832569b63321f393b1fef6d23cb209a9668a17f3b56a8eb87171506baaf8/console.sock,server=on,wait=off -device nvdimm,id=nv0,memde v=mem0,unarmed=on -object memory-backend-file,id=mem0,mem-path=/opt/kata/share/kata-containers/kata-containers-2.4.img,size=134217728,re adonly=on -object rng-random,id=rng0,filename=/dev/urandom -device virtio-rng-pci,rng=rng0 -device pcie-root-port,id=rp0,bus=pcie.0,chas sis=0,slot=0,multifunction=off -device pcie-root-port,id=rp1,bus=pcie.0,chassis=0,slot=1,multifunction=off -device vhost-vsock-pci,disab le-modern=false,vhostfd=3,id=vsock-2210812542,guest-cid=2210812542 -device virtio-9p-pci,disable-modern=false,fsdev=extra-9p-kataShared, mount_tag=kataShared -fsdev local,id=extra-9p-kataShared,path=/run/kata-containers/shared/sandboxes/598c832569b63321f393b1fef6d23cb209a9 668a17f3b56a8eb87171506baaf8/shared,security_model=none,multidevs=remap -netdev tap,id=network-0,vhost=on,vhostfds=4:5:6,fds=7:8:9 -devi ce driver=virtio-net-pci,netdev=network-0,mac=fa:16:3e:fd:ba:ab,disable-modern=false,mq=on,vectors=8 -rtc base=utc,driftfix=slew,clock=h ost -global kvm-pit.lost_tick_policy=discard -vga none -no-user-config -nodefaults -nographic --no-reboot -daemonize -object memory-back end-ram,id=dimm1,size=4352M -numa node,memdev=dimm1 -kernel /opt/kata/share/kata-containers/vmlinux-5.4.160 -append tsc=reliable no_time r_check rcupdate.rcu_expedited=1 i8042.direct=1 i8042.dumbkbd=1 i8042.nopnp=1 i8042.noaux=1 noreplace-smp reboot=k console=hvc0 console= hvc1 cryptomgr.notests net.ifnames=0 pci=lastbus=0 root=/dev/pmem0p1 rootflags=dax,data=ordered,errors=remount-ro ro rootfstype=ext4 deb ug systemd.show_status=true systemd.log_level=debug panic=1 nr_cpus=40 systemd.unit=kata-containers.target systemd.mask=systemd-networkd .service systemd.mask=systemd-networkd.socket agent.debug_console agent.debug_console_vport=1026 -pidfile /run/vc/vm/598c832569b63321f39 3b1fef6d23cb209a9668a17f3b56a8eb87171506baaf8/pid -D /run/vc/vm/598c832569b63321f393b1fef6d23cb209a9668a17f3b56a8eb87171506baaf8/qemu.lo g -smp 3,cores=1,threads=1,sockets=40,maxcpus=40 root 38038 0.0 0.0 0 0 ?SApr19 0:10 [vhost-38032] root 38040 0.0 0.0 0 0 ?SApr19 0:10 [vhost-38032] root 38041 0.0 0.0 0 0 ?SApr19 0:11 [vhost-38032] root 38046 0.0 0.0 0 0 ?SApr19 0:00 [kvm-pit/38032] root 38047 0.0 0.0 0 0 ?SApr19 0:02 [vhost-38032] [root@os ~]# ps -L -p 38032 | wc -l 54 [root@os ~]# ps -fT -p 38032 | wc -l 54
Re: [PATCH] hw/riscv: boot: Support 64bit fdt address.
On Tue, Apr 19, 2022 at 10:03 PM Dylan Jhong wrote:
>
> The current riscv_load_fdt() forces fdt_load_addr to be placed at a dram
> address within 3GB,
> but not all platforms have dram_base within 3GB.
>
> This patch adds an exception for dram base not within 3GB,
> which will place fdt at dram_end align 16MB.
>
> riscv_setup_rom_reset_vec() also needs to be modified
>
> Signed-off-by: Dylan Jhong
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> hw/riscv/boot.c | 12 +++-
> include/hw/riscv/boot.h | 4 ++--
> 2 files changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index 519fa455a1..852aa92bbe 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -203,9 +203,9 @@ hwaddr riscv_load_initrd(const char *filename, uint64_t
> mem_size,
> return *start + size;
> }
>
> -uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
> +uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
> {
> -uint32_t temp, fdt_addr;
> +uint64_t temp, fdt_addr;
> hwaddr dram_end = dram_base + mem_size;
> int ret, fdtsize = fdt_totalsize(fdt);
>
> @@ -220,7 +220,7 @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t
> mem_size, void *fdt)
> * Thus, put it at an 16MB aligned address that less than fdt size from
> the
> * end of dram or 3GB whichever is lesser.
> */
> -temp = MIN(dram_end, 3072 * MiB);
> +temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
> fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB);
>
> ret = fdt_pack(fdt);
> @@ -276,13 +276,15 @@ void riscv_setup_rom_reset_vec(MachineState *machine,
> RISCVHartArrayState *harts
> hwaddr start_addr,
> hwaddr rom_base, hwaddr rom_size,
> uint64_t kernel_entry,
> - uint32_t fdt_load_addr, void *fdt)
> + uint64_t fdt_load_addr, void *fdt)
> {
> int i;
> uint32_t start_addr_hi32 = 0x;
> +uint32_t fdt_load_addr_hi32 = 0x;
>
> if (!riscv_is_32bit(harts)) {
> start_addr_hi32 = start_addr >> 32;
> +fdt_load_addr_hi32 = fdt_load_addr >> 32;
> }
> /* reset vector */
> uint32_t reset_vec[10] = {
> @@ -295,7 +297,7 @@ void riscv_setup_rom_reset_vec(MachineState *machine,
> RISCVHartArrayState *harts
> start_addr, /* start: .dword */
> start_addr_hi32,
> fdt_load_addr, /* fdt_laddr: .dword */
> -0x,
> +fdt_load_addr_hi32,
> /* fw_dyn: */
> };
> if (riscv_is_32bit(harts)) {
> diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
> index baff11dd8a..346441e369 100644
> --- a/include/hw/riscv/boot.h
> +++ b/include/hw/riscv/boot.h
> @@ -48,12 +48,12 @@ target_ulong riscv_load_kernel(const char
> *kernel_filename,
> symbol_fn_t sym_cb);
> hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
> uint64_t kernel_entry, hwaddr *start);
> -uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
> +uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
> void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState
> *harts,
> hwaddr saddr,
> hwaddr rom_base, hwaddr rom_size,
> uint64_t kernel_entry,
> - uint32_t fdt_load_addr, void *fdt);
> + uint64_t fdt_load_addr, void *fdt);
> void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
>hwaddr rom_size,
>uint32_t reset_vec_size,
> --
> 2.34.1
>
>
Re: [PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs
On Thu, Apr 21, 2022 at 10:35 AM Bin Meng wrote: > > > This adds initial support for the Sdtrig extension via the Trigger Module, > as defined in the RISC-V Debug Specification [1]. > > Only "Address / Data Match" trigger (type 2) is implemented as of now, > which is mainly used for hardware breakpoint and watchpoint. The number > of type 2 triggers implemented is 2, which is the number that we can > find in the SiFive U54/U74 cores. > > [1] > https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf > > Changes in v5: > - rebase against riscv-to-apply.next > - drop patch 1 in v4 which is already in riscv-to-apply.next > - adjust patch order to let patch 2 in v4 come later > > Changes in v4: > - move riscv_trigger_init() call to riscv_cpu_reset() > > Changes in v3: > - add riscv_trigger_init(), moved from patch #1 to this patch > - enable debug feature by default for all CPUs > > Changes in v2: > - use 0 instead of GETPC() > - change the config option to 'disabled' by default > - new patch: add debug state description > > Bin Meng (6): > target/riscv: debug: Implement debug related TCGCPUOps > target/riscv: cpu: Add a config option for native debug > target/riscv: csr: Hook debug CSR read/write > target/riscv: machine: Add debug state description > target/riscv: cpu: Enable native debug feature > hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Thanks! Applied to riscv-to-apply.next Alistair > > include/hw/core/tcg-cpu-ops.h | 1 + > target/riscv/cpu.h| 4 +- > target/riscv/debug.h | 6 ++ > target/riscv/cpu.c| 12 > target/riscv/csr.c| 57 +++ > target/riscv/debug.c | 102 ++ > target/riscv/machine.c| 32 +++ > 7 files changed, 213 insertions(+), 1 deletion(-) > > -- > 2.25.1 > >
PING: [PATCH v4 0/8] Introduce akcipher service for virtio-crypto
Hi Daniel,
Could you please review this series?
On 4/11/22 18:43, zhenwei pi wrote:
v3 -> v4:
- Coding style fix: Akcipher -> AkCipher, struct XXX -> XXX, Rsa -> RSA,
XXX-alg -> XXX-algo.
- Change version info in qapi/crypto.json, from 7.0 -> 7.1.
- Remove ecdsa from qapi/crypto.json, it would be introduced with the
implemetion later.
- Use QCryptoHashAlgothrim instead of QCryptoRSAHashAlgorithm(removed) in
qapi/crypto.json.
- Rename arguments of qcrypto_akcipher_XXX to keep aligned with
qcrypto_cipher_XXX(dec/enc/sign/vefiry -> in/out/in2), and add
qcrypto_akcipher_max_XXX APIs.
- Add new API: qcrypto_akcipher_supports.
- Change the return value of qcrypto_akcipher_enc/dec/sign, these functions
return the actual length of result.
- Separate ASN.1 source code and test case clean.
- Disable RSA raw encoding for akcipher-nettle.
- Separate RSA key parser into rsakey.{hc}, and implememts it with
builtin-asn1-decoder and nettle respectivly.
- Implement RSA(pkcs1 and raw encoding) algorithm by gcrypt. This has higher
priority than nettle.
- For some akcipher operations(eg, decryption of pkcs1pad(rsa)), the length of
returned result maybe less than the dst buffer size, return the actual length
of result instead of the buffer length to the guest side. (in function
virtio_crypto_akcipher_input_data_helper)
- Other minor changes.
Thanks to Daniel!
Eric pointed out this missing part of use case, send it here again.
In our plan, the feature is designed for HTTPS offloading case and other
applications which use kernel RSA/ecdsa by keyctl syscall. The full picture
shows bellow:
Nginx/openssl[1] ... Apps
Guest -
virtio-crypto driver[2]
-
virtio-crypto backend[3]
Host-
/ | \
builtin[4] vhost keyctl[5] ...
[1] User applications can offload RSA calculation to kernel by keyctl syscall.
There is no keyctl engine in openssl currently, we developed a engine and tried
to contribute it to openssl upstream, but openssl 1.x does not accept new
feature. Link:
https://github.com/openssl/openssl/pull/16689
This branch is available and maintained by Lei
https://github.com/TousakaRin/openssl/tree/OpenSSL_1_1_1-kctl_engine
We tested nginx(change config file only) with openssl keyctl engine, it works
fine.
[2] virtio-crypto driver is used to communicate with host side, send requests
to host side to do asymmetric calculation.
https://lkml.org/lkml/2022/3/1/1425
[3] virtio-crypto backend handles requests from guest side, and forwards
request to crypto backend driver of QEMU.
[4] Currently RSA is supported only in builtin driver. This driver is supposed
to test the full feature without other software(Ex vhost process) and hardware
dependence. ecdsa is introduced into qapi type without implementation, this may
be implemented in Q3-2022 or later. If ecdsa type definition should be added
with the implementation together, I'll remove this in next version.
[5] keyctl backend is in development, we will post this feature in Q2-2022.
keyctl backend can use hardware acceleration(Ex, Intel QAT).
Setup the full environment, tested with Intel QAT on host side, the QPS of
HTTPS increase to ~200% in a guest.
VS PCI passthrough: the most important benefit of this solution makes the VM
migratable.
v2 -> v3:
- Introduce akcipher types to qapi
- Add test/benchmark suite for akcipher class
- Seperate 'virtio_crypto: Support virtio crypto asym operation' into:
- crypto: Introduce akcipher crypto class
- virtio-crypto: Introduce RSA algorithm
v1 -> v2:
- Update virtio_crypto.h from v2 version of related kernel patch.
v1:
- Support akcipher for virtio-crypto.
- Introduce akcipher class.
- Introduce ASN1 decoder into QEMU.
- Implement RSA backend by nettle/hogweed.
Lei He (4):
crypto-akcipher: Introduce akcipher types to qapi
crypto: add ASN.1 decoder
crypto: Implement RSA algorithm by hogweed
crypto: Implement RSA algorithm by gcrypt
Zhenwei Pi (3):
virtio-crypto: header update
crypto: Introduce akcipher crypto class
crypto: Introduce RSA algorithm
lei he (1):
tests/crypto: Add test suite for crypto akcipher
backends/cryptodev-builtin.c | 261 ++-
backends/cryptodev-vhost-user.c | 34 +-
backends/cryptodev.c | 32 +-
crypto/akcipher-gcrypt.c.inc | 531 +
crypto/akcipher-nettle.c.inc | 448 +++
crypto/akcipher.c | 108 +++
crypto/akcipherpriv.h | 43 ++
crypto/asn1_decoder.c | 161
crypto/asn1_decoder.h | 75 ++
crypto/meson.build| 6 +
[PATCH] Hexagon (target/hexagon) add overrides for S2_asr_r_r_sat/S2_asl_r_r_sat
These instructions will not be generated by idef-parser, so we override
them manually.
Test cases added to tests/tcg/hexagon/usr.c
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 10 ++-
target/hexagon/genptr.c | 147 +++
tests/tcg/hexagon/usr.c | 22 --
3 files changed, 172 insertions(+), 7 deletions(-)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index c6f0879b6e..9268f49acd 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -1,5 +1,5 @@
/*
- * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+ * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights
Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -610,6 +610,14 @@
tcg_temp_free(tmp); \
} while (0)
+/* r0 = asr(r1, r2):sat */
+#define fGEN_TCG_S2_asr_r_r_sat(SHORTCODE) \
+gen_asr_r_r_sat(RdV, RsV, RtV)
+
+/* r0 = asl(r1, r2):sat */
+#define fGEN_TCG_S2_asl_r_r_sat(SHORTCODE) \
+gen_asl_r_r_sat(RdV, RsV, RtV)
+
/* Floating point */
#define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \
gen_helper_conv_sf2df(RddV, cpu_env, RsV)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index cd6af4bceb..36e6451859 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -468,6 +468,153 @@ static TCGv gen_8bitsof(TCGv result, TCGv value)
return result;
}
+static void gen_set_usr_field(int field, TCGv val)
+{
+tcg_gen_deposit_tl(hex_new_value[HEX_REG_USR], hex_new_value[HEX_REG_USR],
+ val,
+ reg_field_info[field].offset,
+ reg_field_info[field].width);
+}
+
+static void gen_set_usr_fieldi(int field, int x)
+{
+TCGv val = tcg_const_tl(x);
+gen_set_usr_field(field, val);
+tcg_temp_free(val);
+}
+
+static void gen_sat_i64(TCGv_i64 dst, TCGv_i64 src, uint32_t bits)
+{
+TCGLabel *label = gen_new_label();
+
+tcg_gen_sextract_i64(dst, src, 0, bits);
+tcg_gen_brcond_i64(TCG_COND_EQ, dst, src, label);
+{
+TCGv_i64 min = tcg_constant_i64(-(1LL << (bits - 1)));
+TCGv_i64 max = tcg_constant_i64((1LL << (bits - 1)) - 1);
+tcg_gen_movcond_i64(TCG_COND_LT, dst, src, tcg_constant_i64(0),
+min, max);
+gen_set_usr_fieldi(USR_OVF, 1);
+}
+gen_set_label(label);
+}
+
+static void gen_satval(TCGv_i64 dest, TCGv_i64 source, uint32_t bits)
+{
+TCGv_i64 min = tcg_constant_i64(-(1LL << (bits - 1)));
+TCGv_i64 max = tcg_constant_i64((1LL << (bits - 1)) - 1);
+
+gen_set_usr_fieldi(USR_OVF, 1);
+tcg_gen_movcond_i64(TCG_COND_LT, dest, source, tcg_constant_i64(0),
+min, max);
+}
+
+/* Shift left with saturation */
+static void gen_shl_sat(TCGv RdV, TCGv RsV, TCGv shift_amt)
+{
+/*
+ * int64_t A = (fCAST4_8s(RsV) << shift_amt;
+ * if (((int32_t)((fSAT(A)) ^ ((int32_t)(RsV < 0) {
+ * RdV = fSATVALN(32, ((int32_t)(RsV)))
+ * } else if (((RsV) > 0) && ((A) == 0)) {
+ * RdV = fSATVALN(32, (RsV));
+ * } else {
+ * RdV = fSAT(A);
+ * }
+ */
+TCGv_i64 RsV_i64 = tcg_temp_local_new_i64();
+TCGv_i64 shift_amt_i64 = tcg_temp_local_new_i64();
+TCGv_i64 A = tcg_temp_local_new_i64();
+TCGv_i64 A_sat_i64 = tcg_temp_local_new_i64();
+TCGv A_sat = tcg_temp_local_new();
+TCGv_i64 RdV_i64 = tcg_temp_local_new_i64();
+TCGv tmp = tcg_temp_new();
+TCGLabel *label1 = gen_new_label();
+TCGLabel *label2 = gen_new_label();
+TCGLabel *done = gen_new_label();
+
+tcg_gen_ext_i32_i64(RsV_i64, RsV);
+tcg_gen_ext_i32_i64(shift_amt_i64, shift_amt);
+tcg_gen_shl_i64(A, RsV_i64, shift_amt_i64);
+
+/* Check for saturation */
+gen_sat_i64(A_sat_i64, A, 32);
+tcg_gen_extrl_i64_i32(A_sat, A_sat_i64);
+tcg_gen_xor_tl(tmp, A_sat, RsV);
+tcg_gen_brcondi_tl(TCG_COND_GE, tmp, 0, label1);
+gen_satval(RdV_i64, RsV_i64, 32);
+tcg_gen_extrl_i64_i32(RdV, RdV_i64);
+tcg_gen_br(done);
+
+gen_set_label(label1);
+tcg_gen_brcondi_tl(TCG_COND_LE, RsV, 0, label2);
+tcg_gen_brcondi_i64(TCG_COND_NE, A, 0, label2);
+gen_satval(RdV_i64, RsV_i64, 32);
+tcg_gen_extrl_i64_i32(RdV, RdV_i64);
+tcg_gen_br(done);
+
+gen_set_label(label2);
+tcg_gen_mov_tl(RdV, A_sat);
+
+gen_set_label(done);
+
+tcg_temp_free_i64(RsV_i64);
+tcg_temp_free_i64(shift_amt_i64);
+tcg_temp_free_i64(A);
+tcg_temp_free_i64(A_sat_i64);
+tcg_temp_free(A_sat);
+tcg_temp_free_i64(RdV_i64);
+tcg_temp_free(tmp);
+}
+
+/* Bidirectional shift right with saturation */
+static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
+{
+TCGv shift_amt = tcg_temp_local_new();
+TCGLabel *positive = gen_new_label();
+TCGLabel *done = gen_new_label();
+
+
[PATCH] Hexagon (target/hexagon) remove unused encodings
Remove encodings guarded by ifdef that is not defined Signed-off-by: Taylor Simpson --- target/hexagon/imported/encode_pp.def | 23 --- 1 file changed, 23 deletions(-) diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/imported/encode_pp.def index 939c6fc55f..d71c04cd30 100644 --- a/target/hexagon/imported/encode_pp.def +++ b/target/hexagon/imported/encode_pp.def @@ -944,13 +944,6 @@ MPY_ENC(F2_dfmpyfix, "1000","d","0","0","1","0","11") MPY_ENC(F2_dfmin,"1000","d","0","0","1","1","11") MPY_ENC(F2_dfmax,"1000","d","0","1","0","0","11") MPY_ENC(F2_dfmpyll, "1000","d","0","1","0","1","11") -#ifdef ADD_DP_OPS -MPY_ENC(F2_dfdivcheat, "1000","d","0","0","0","1","00") - -MPY_ENC(F2_dffixupn, "1000","d","0","1","0","1","11") -MPY_ENC(F2_dffixupd, "1000","d","0","1","1","0","11") -MPY_ENC(F2_dfrecipa, "1000","d","0","1","1","1","ee") -#endif MPY_ENC(M7_dcmpyrw, "1000","d","0","0","0","1","10") MPY_ENC(M7_dcmpyrwc, "1000","d","0","0","1","1","10") @@ -1024,15 +1017,6 @@ MPY_ENC(M5_vdmacbsu, "1010","x","0","1","0","0","01") MPY_ENC(F2_dfmpylh, "1010","x","0","0","0","0","11") MPY_ENC(F2_dfmpyhh, "1010","x","0","0","0","1","11") -#ifdef ADD_DP_OPS -MPY_ENC(F2_dfmpyhh, "1010","x","0","0","1","0","11") -MPY_ENC(F2_dffma,"1010","x","0","0","0","0","11") -MPY_ENC(F2_dffms,"1010","x","0","0","0","1","11") - -MPY_ENC(F2_dffma_lib,"1010","x","0","0","1","0","11") -MPY_ENC(F2_dffms_lib,"1010","x","0","0","1","1","11") -MPY_ENC(F2_dffma_sc, "1010","x","0","1","1","1","uu") -#endif MPY_ENC(M7_dcmpyrw_acc, "1010","x","0","0","0","1","10") @@ -1547,15 +1531,8 @@ SH2_RR_ENC(F2_conv_df2d, "","111","0","0 00","d") SH2_RR_ENC(F2_conv_df2ud, "","111","0","0 01","d") SH2_RR_ENC(F2_conv_ud2df, "","111","0","0 10","d") SH2_RR_ENC(F2_conv_d2df, "","111","0","0 11","d") -#ifdef ADD_DP_OPS -SH2_RR_ENC(F2_dffixupr, "","111","0","1 00","d") -SH2_RR_ENC(F2_dfsqrtcheat,"","111","0","1 01","d") -#endif SH2_RR_ENC(F2_conv_df2d_chop, "","111","0","1 10","d") SH2_RR_ENC(F2_conv_df2ud_chop,"","111","0","1 11","d") -#ifdef ADD_DP_OPS -SH2_RR_ENC(F2_dfinvsqrta, "","111","1","0 ee","d") -#endif -- 2.17.1
[PATCH] Hexagon (target/hexagon) move store size tracking to translation
The store width is needed for packet commit, so it is stored in ctx->store_width. Currently, it is set when a store has a TCG override instead of a QEMU helper. In the QEMU helper case, the ctx->store_width is not set, we invoke a helper during packet commit that uses the runtime store width. This patch ensures ctx->store_width is set for all store instructions, so performance is improved because packet commit can generate the proper TCG store rather than the generic helper. We do this by - Create new attributes to indicate the store size - During gen_semantics, convert the fSTORE instances to fSTORE - Assign the new attributes to the new macros - Add definitions for the new macros - Use the attributes from the instructions during translation to set ctx->store_width - Remove setting of ctx->store_width from genptr.c Signed-off-by: Taylor Simpson --- target/hexagon/macros.h | 16 ++ target/hexagon/attribs_def.h.inc | 4 target/hexagon/gen_semantics.c | 26 +++ target/hexagon/genptr.c | 36 +++- target/hexagon/translate.c | 26 +++ 5 files changed, 80 insertions(+), 28 deletions(-) diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index a78e84faa4..1d26f59fea 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -139,7 +139,7 @@ __builtin_choose_expr(TYPE_TCGV(X), \ gen_store1, (void)0)) #define MEM_STORE1(VA, DATA, SLOT) \ -MEM_STORE1_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT) +MEM_STORE1_FUNC(DATA)(cpu_env, VA, DATA, SLOT) #define MEM_STORE2_FUNC(X) \ __builtin_choose_expr(TYPE_INT(X), \ @@ -147,7 +147,7 @@ __builtin_choose_expr(TYPE_TCGV(X), \ gen_store2, (void)0)) #define MEM_STORE2(VA, DATA, SLOT) \ -MEM_STORE2_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT) +MEM_STORE2_FUNC(DATA)(cpu_env, VA, DATA, SLOT) #define MEM_STORE4_FUNC(X) \ __builtin_choose_expr(TYPE_INT(X), \ @@ -155,7 +155,7 @@ __builtin_choose_expr(TYPE_TCGV(X), \ gen_store4, (void)0)) #define MEM_STORE4(VA, DATA, SLOT) \ -MEM_STORE4_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT) +MEM_STORE4_FUNC(DATA)(cpu_env, VA, DATA, SLOT) #define MEM_STORE8_FUNC(X) \ __builtin_choose_expr(TYPE_INT(X), \ @@ -163,7 +163,7 @@ __builtin_choose_expr(TYPE_TCGV_I64(X), \ gen_store8, (void)0)) #define MEM_STORE8(VA, DATA, SLOT) \ -MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT) +MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, SLOT) #else #define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, slot, VA)) #define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, slot, VA)) @@ -600,8 +600,16 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift) #ifdef QEMU_GENERATE #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, insn->slot) +#define fSTORE1(EA, SRC) MEM_STORE1(EA, SRC, insn->slot) +#define fSTORE2(EA, SRC) MEM_STORE2(EA, SRC, insn->slot) +#define fSTORE4(EA, SRC) MEM_STORE4(EA, SRC, insn->slot) +#define fSTORE8(EA, SRC) MEM_STORE8(EA, SRC, insn->slot) #else #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, slot) +#define fSTORE1(EA, SRC) MEM_STORE1(EA, SRC, slot) +#define fSTORE2(EA, SRC) MEM_STORE2(EA, SRC, slot) +#define fSTORE4(EA, SRC) MEM_STORE4(EA, SRC, slot) +#define fSTORE8(EA, SRC) MEM_STORE8(EA, SRC, slot) #endif #ifdef QEMU_GENERATE diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc index dc890a557f..9c19e08dd7 100644 --- a/target/hexagon/attribs_def.h.inc +++ b/target/hexagon/attribs_def.h.inc @@ -38,6 +38,10 @@ DEF_ATTRIB(SUBINSN, "sub-instruction", "", "") /* Load and Store attributes */ DEF_ATTRIB(LOAD, "Loads from memory", "", "") DEF_ATTRIB(STORE, "Stores to memory", "", "") +DEF_ATTRIB(STORE_SIZE1, "Stores 1 byte to memory", "", "") +DEF_ATTRIB(STORE_SIZE2, "Stores 2 bytes to memory", "", "") +DEF_ATTRIB(STORE_SIZE4, "Stores 4 bytes to memory", "", "") +DEF_ATTRIB(STORE_SIZE8, "Stores 8 bytes to memory", "", "") DEF_ATTRIB(MEMLIKE, "Memory-like instruction", "", "") DEF_ATTRIB(MEMLIKE_PACKET_RULES, "follows Memory-like packet rules", "", "") diff --git a/target/hexagon/gen_semantics.c b/target/hexagon/gen_semantics.c index 4a2bdd70e9..b4bbd66006 100644 --- a/target/hexagon/gen_semantics.c +++ b/target/hexagon/gen_semantics.c @@ -78,6 +78,10 @@ int main(int argc, char *argv[]) ")\n", \ #TAG, STRINGIZE(ATTRIBS)); \ } while (0); + +/* Change the store macros so we can track the size during translation */ +#define fSTORE(NUM, SIZE, EA, SRC) fSTORE##SIZE(EA, SRC) + #include "imported/allidefs.def" #undef Q6INSN #undef EXTINSN @@ -101,6 +105,28 @@ int main(int argc, char *argv[]) ")\n", \ #MNAME, STRINGIZE(BEH), STRINGIZE(ATTRS)); #include "imported/macros.def" + +/* These macros give the size of the store used during
[PATCH] Hexagon (tests/tcg/hexagon) Fix alignment in load_unpack.c
The increment used in :brev tests was causing unaligned addresses Change the increment and the relevant expected values Signed-off-by: Taylor Simpson --- tests/tcg/hexagon/load_unpack.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/tests/tcg/hexagon/load_unpack.c b/tests/tcg/hexagon/load_unpack.c index 3575a37a28..4aa26fc388 100644 --- a/tests/tcg/hexagon/load_unpack.c +++ b/tests/tcg/hexagon/load_unpack.c @@ -245,7 +245,7 @@ TEST_pr(loadbsw4_pr, long long, S, 4, 0xff00ff00LL, */ #define BxW_LOAD_pbr(SZ, RES, PTR) \ __asm__( \ -"r4 = #(1 << (16 - 3))\n\t" \ +"r4 = #(1 << (16 - 4))\n\t" \ "m0 = r4\n\t" \ "%0 = mem" #SZ "(%1++m0:brev)\n\t" \ : "=r"(RES), "+r"(PTR) \ @@ -273,15 +273,15 @@ void test_##NAME(void) \ } TEST_pbr(loadbzw2_pbr, int, Z, 0x, -0x00020081, 0x00060085, 0x00040083, 0x00080087) +0x00020081, 0x000a0089, 0x00060085, 0x000e008d) TEST_pbr(loadbsw2_pbr, int, S, 0xff00, -0x00020081, 0x00060085, 0x00040083, 0x00080087) +0x00020081, 0x000aff89, 0x0006ff85, 0x000eff8d) TEST_pbr(loadbzw4_pbr, long long, Z, 0xLL, -0x0004008300020081LL, 0x0008008700060085LL, -0x0006008500040083LL, 0x000a008900080087LL) +0x0004008300020081LL, 0x000c008b000a0089LL, +0x0008008700060085LL, 0x0010008f000e008dLL) TEST_pbr(loadbsw4_pbr, long long, S, 0xff00ff00LL, -0x0004008300020081LL, 0x0008008700060085LL, -0x0006008500040083LL, 0x000a008900080087LL) +0x0004008300020081LL, 0x000cff8b000aff89LL, +0x0008ff870006ff85LL, 0x0010ff8f000eff8dLL) /* -- 2.17.1
[PATCH] Hexagon (target/hexagon) make VyV operands use a unique temp
VyV operand is only used in the vshuff and vdeal instructions. These
instructions write to both VyV and VxV operands. In the case where
both operands are the same register, we need a separate location for
VyV. We use the existing vtmp field in CPUHexagonState.
Test case added in tests/tcg/hexagon/hvx_misc.c
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/hvx_misc.c| 45 +
target/hexagon/gen_tcg_funcs.py | 9 +++
2 files changed, 49 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/hexagon/hvx_misc.c b/tests/tcg/hexagon/hvx_misc.c
index b896f5897e..6e2c9ab3cd 100644
--- a/tests/tcg/hexagon/hvx_misc.c
+++ b/tests/tcg/hexagon/hvx_misc.c
@@ -498,6 +498,49 @@ static void test_vsubuwsat_dv(void)
check_output_w(__LINE__, 2);
}
+static void test_vshuff(void)
+{
+/* Test that vshuff works when the two operands are the same register */
+const uint32_t splat = 0x089be55c;
+const uint32_t shuff = 0x454fa926;
+MMVector v0, v1;
+
+memset(expect, 0x12, sizeof(MMVector));
+memset(output, 0x34, sizeof(MMVector));
+
+asm volatile("v25 = vsplat(%0)\n\t"
+ "vshuff(v25, v25, %1)\n\t"
+ "vmem(%2 + #0) = v25\n\t"
+ : /* no outputs */
+ : "r"(splat), "r"(shuff), "r"(output)
+ : "v25", "memory");
+
+/*
+ * The semantics of Hexagon are the operands are pass-by-value, so create
+ * two copies of the vsplat result.
+ */
+for (int i = 0; i < MAX_VEC_SIZE_BYTES / 4; i++) {
+v0.uw[i] = splat;
+v1.uw[i] = splat;
+}
+/* Do the vshuff operation */
+for (int offset = 1; offset < MAX_VEC_SIZE_BYTES; offset <<= 1) {
+if (shuff & offset) {
+for (int k = 0; k < MAX_VEC_SIZE_BYTES; k++) {
+if (!(k & offset)) {
+uint8_t tmp = v0.ub[k];
+v0.ub[k] = v1.ub[k + offset];
+v1.ub[k + offset] = tmp;
+}
+}
+}
+}
+/* Put the result in the expect buffer for verification */
+expect[0] = v1;
+
+check_output_b(__LINE__, 1);
+}
+
int main()
{
init_buffers();
@@ -533,6 +576,8 @@ int main()
test_vadduwsat();
test_vsubuwsat_dv();
+test_vshuff();
+
puts(err ? "FAIL" : "PASS");
return err ? 1 : 0;
}
diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py
index 1fd9de95d5..d72c689ad7 100755
--- a/target/hexagon/gen_tcg_funcs.py
+++ b/target/hexagon/gen_tcg_funcs.py
@@ -1,7 +1,7 @@
#!/usr/bin/env python3
##
-## Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+## Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights
Reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -164,7 +164,9 @@ def genptr_decl(f, tag, regtype, regid, regno):
(regtype, regid, regno))
f.write("const intptr_t %s%sV_off =\n" % \
(regtype, regid))
-if (hex_common.is_tmp_result(tag)):
+if (regid == "y"):
+f.write("offsetof(CPUHexagonState, vtmp);\n")
+elif (hex_common.is_tmp_result(tag)):
f.write("ctx_tmp_vreg_off(ctx, %s%sN, 1, true);\n" % \
(regtype, regid))
else:
@@ -379,9 +381,6 @@ def genptr_src_read(f, tag, regtype, regid):
f.write("vreg_src_off(ctx, %s%sN),\n" % \
(regtype, regid))
f.write("sizeof(MMVector), sizeof(MMVector));\n")
-if (not hex_common.skip_qemu_helper(tag)):
-f.write("tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" %
\
- (regtype, regid, regtype, regid))
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "Q"):
--
2.17.1
[PATCH v2] target/ppc: Fix BookE debug interrupt generation
From: Bin Meng
Per E500 core reference manual [1], chapter 8.4.4 "Branch Taken Debug
Event" and chapter 8.4.5 "Instruction Complete Debug Event":
"A branch taken debug event occurs if both MSR[DE] and DBCR0[BRT]
are set ... Branch taken debug events are not recognized if MSR[DE]
is cleared when the branch instruction executes."
"An instruction complete debug event occurs when any instruction
completes execution so long as MSR[DE] and DBCR0[ICMP] are both
set ... Instruction complete debug events are not recognized if
MSR[DE] is cleared at the time of the instruction execution."
Current codes do not check MSR.DE bit before setting HFLAGS_SE and
HFLAGS_BE flag, which would cause the immediate debug interrupt to
be generated, e.g.: when DBCR0.ICMP bit is set by guest software
and MSR.DE is not set.
[1] https://www.nxp.com/docs/en/reference-manual/E500CORERM.pdf
Signed-off-by: Bin Meng
---
Changes in v2:
- update commit message to use E500CORERM instead of PowerISA 2.07
target/ppc/helper_regs.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 9a691d6833..77bc57415c 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -63,10 +63,10 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *env)
if (ppc_flags & POWERPC_FLAG_DE) {
target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0];
-if (dbcr0 & DBCR0_ICMP) {
+if ((dbcr0 & DBCR0_ICMP) && msr_de) {
hflags |= 1 << HFLAGS_SE;
}
-if (dbcr0 & DBCR0_BRT) {
+if ((dbcr0 & DBCR0_BRT) && msr_de) {
hflags |= 1 << HFLAGS_BE;
}
} else {
--
2.25.1
[PATCH v5 3/6] target/riscv: csr: Hook debug CSR read/write
From: Bin Meng
This adds debug CSR read/write support to the RISC-V CSR RW table.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v4)
Changes in v4:
- move riscv_trigger_init() call to riscv_cpu_reset()
Changes in v3:
- add riscv_trigger_init(), moved from patch #1 to this patch
target/riscv/debug.h | 2 ++
target/riscv/cpu.c | 4
target/riscv/csr.c | 57
target/riscv/debug.c | 27 +
4 files changed, 90 insertions(+)
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
index fb21706e1c..27b9cac6b4 100644
--- a/target/riscv/debug.h
+++ b/target/riscv/debug.h
@@ -109,4 +109,6 @@ void riscv_cpu_debug_excp_handler(CPUState *cs);
bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
+void riscv_trigger_init(CPURISCVState *env);
+
#endif /* RISCV_DEBUG_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 477961b619..85656cdcc3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -466,6 +466,10 @@ static void riscv_cpu_reset(DeviceState *dev)
set_default_nan_mode(1, >fp_status);
#ifndef CONFIG_USER_ONLY
+if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
+riscv_trigger_init(env);
+}
+
if (kvm_enabled()) {
kvm_riscv_reset_vcpu(cpu);
}
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a09126a011..6ba85e7b5d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -290,6 +290,15 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+
+static RISCVException debug(CPURISCVState *env, int csrno)
+{
+if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
+return RISCV_EXCP_NONE;
+}
+
+return RISCV_EXCP_ILLEGAL_INST;
+}
#endif
/* User Floating-Point CSRs */
@@ -2677,6 +2686,48 @@ static RISCVException write_pmpaddr(CPURISCVState *env,
int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException read_tselect(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+*val = tselect_csr_read(env);
+return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_tselect(CPURISCVState *env, int csrno,
+target_ulong val)
+{
+tselect_csr_write(env, val);
+return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_tdata(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+/* return 0 in tdata1 to end the trigger enumeration */
+if (env->trigger_cur >= TRIGGER_NUM && csrno == CSR_TDATA1) {
+*val = 0;
+return RISCV_EXCP_NONE;
+}
+
+if (!tdata_available(env, csrno - CSR_TDATA1)) {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+
+*val = tdata_csr_read(env, csrno - CSR_TDATA1);
+return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_tdata(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+if (!tdata_available(env, csrno - CSR_TDATA1)) {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+
+tdata_csr_write(env, csrno - CSR_TDATA1, val);
+return RISCV_EXCP_NONE;
+}
+
/*
* Functions to access Pointer Masking feature registers
* We have to check if current priv lvl could modify
@@ -3418,6 +3469,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
+/* Debug CSRs */
+[CSR_TSELECT] = { "tselect", debug, read_tselect, write_tselect },
+[CSR_TDATA1]= { "tdata1", debug, read_tdata, write_tdata },
+[CSR_TDATA2]= { "tdata2", debug, read_tdata, write_tdata },
+[CSR_TDATA3]= { "tdata3", debug, read_tdata, write_tdata },
+
/* User Pointer Masking */
[CSR_UMTE]={ "umte",pointer_masking, read_umte,write_umte
},
[CSR_UPMMASK] ={ "upmmask", pointer_masking, read_upmmask,
write_upmmask },
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 1a9392645e..2f2a51c732 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -412,3 +412,30 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs,
CPUWatchpoint *wp)
return false;
}
+
+void riscv_trigger_init(CPURISCVState *env)
+{
+target_ulong type2 = trigger_type(env, TRIGGER_TYPE_AD_MATCH);
+int i;
+
+/* type 2 triggers */
+for (i = 0; i < TRIGGER_TYPE2_NUM; i++) {
+/*
+ * type = TRIGGER_TYPE_AD_MATCH
+ * dmode = 0 (both debug and M-mode can write tdata)
+ * maskmax = 0 (unimplemented, always 0)
+ * sizehi = 0 (match against any size, RV64 only)
+ * hit = 0 (unimplemented, always 0)
+ * select = 0 (always 0, perform match on address)
+ * timing = 0 (always 0, trigger before instruction)
+ * sizelo = 0 (match against any
[PATCH v5 6/6] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
From: Bin Meng
This is now used by RISC-V as well. Update the comments.
Signed-off-by: Bin Meng
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
(no changes since v1)
include/hw/core/tcg-cpu-ops.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index e13898553a..f98671ff32 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -90,6 +90,7 @@ struct TCGCPUOps {
/**
* @debug_check_watchpoint: return true if the architectural
* watchpoint whose address has matched should really fire, used by ARM
+ * and RISC-V
*/
bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
--
2.25.1
[PATCH v5 5/6] target/riscv: cpu: Enable native debug feature
From: Bin Meng
Turn on native debug feature by default for all CPUs.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v3)
Changes in v3:
- enable debug feature by default for all CPUs
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 85656cdcc3..0c774056c5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -803,7 +803,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
-DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false),
+DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
--
2.25.1
[PATCH v5 2/6] target/riscv: cpu: Add a config option for native debug
From: Bin Meng
Add a config option to enable support for native M-mode debug.
This is disabled by default and can be enabled with 'debug=true'.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v2)
Changes in v2:
- change the config option to 'disabled' by default
target/riscv/cpu.h | 4 +++-
target/riscv/cpu.c | 5 +
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 39a9ff17d3..62e53e3653 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -79,7 +79,8 @@ enum {
RISCV_FEATURE_PMP,
RISCV_FEATURE_EPMP,
RISCV_FEATURE_MISA,
-RISCV_FEATURE_AIA
+RISCV_FEATURE_AIA,
+RISCV_FEATURE_DEBUG
};
/* Privileged specification version */
@@ -405,6 +406,7 @@ struct RISCVCPUConfig {
bool pmp;
bool epmp;
bool aia;
+bool debug;
uint64_t resetvec;
};
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8919928f4f..477961b619 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -548,6 +548,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
riscv_set_feature(env, RISCV_FEATURE_AIA);
}
+if (cpu->cfg.debug) {
+riscv_set_feature(env, RISCV_FEATURE_DEBUG);
+}
+
set_resetvec(env, cpu->cfg.resetvec);
/* Validate that MISA_MXL is set properly. */
@@ -795,6 +799,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
--
2.25.1
[PATCH v5 4/6] target/riscv: machine: Add debug state description
From: Bin Meng
Add a subsection to machine.c to migrate debug CSR state.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v2)
Changes in v2:
- new patch: add debug state description
target/riscv/machine.c | 32
1 file changed, 32 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 243f567949..2a437b29a1 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer = {
VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
+VMSTATE_END_OF_LIST()
+}
+};
+
+static bool debug_needed(void *opaque)
+{
+RISCVCPU *cpu = opaque;
+CPURISCVState *env = >env;
+
+return riscv_feature(env, RISCV_FEATURE_DEBUG);
+}
+static const VMStateDescription vmstate_debug_type2 = {
+.name = "cpu/debug/type2",
+.version_id = 1,
+.minimum_version_id = 1,
+.fields = (VMStateField[]) {
+VMSTATE_UINTTL(mcontrol, type2_trigger_t),
+VMSTATE_UINTTL(maddress, type2_trigger_t),
+VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_debug = {
+.name = "cpu/debug",
+.version_id = 1,
+.minimum_version_id = 1,
+.needed = debug_needed,
+.fields = (VMStateField[]) {
+VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
+VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, TRIGGER_TYPE2_NUM,
+ 0, vmstate_debug_type2, type2_trigger_t),
VMSTATE_END_OF_LIST()
}
};
@@ -315,6 +346,7 @@ const VMStateDescription vmstate_riscv_cpu = {
_rv128,
_kvmtimer,
_envcfg,
+_debug,
NULL
}
};
--
2.25.1
[PATCH v5 1/6] target/riscv: debug: Implement debug related TCGCPUOps
From: Bin Meng
Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint}
TCGCPUOps and hook them into riscv_tcg_ops.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v2)
Changes in v2:
- use 0 instead of GETPC()
target/riscv/debug.h | 4 +++
target/riscv/cpu.c | 3 ++
target/riscv/debug.c | 75
3 files changed, 82 insertions(+)
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
index fbc5f946e2..fb21706e1c 100644
--- a/target/riscv/debug.h
+++ b/target/riscv/debug.h
@@ -105,4 +105,8 @@ void tselect_csr_write(CPURISCVState *env, target_ulong
val);
target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index);
void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val);
+void riscv_cpu_debug_excp_handler(CPUState *cs);
+bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
+bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
+
#endif /* RISCV_DEBUG_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 94f9434411..8919928f4f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -880,6 +880,9 @@ static const struct TCGCPUOps riscv_tcg_ops = {
.do_interrupt = riscv_cpu_do_interrupt,
.do_transaction_failed = riscv_cpu_do_transaction_failed,
.do_unaligned_access = riscv_cpu_do_unaligned_access,
+.debug_excp_handler = riscv_cpu_debug_excp_handler,
+.debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
+.debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
#endif /* !CONFIG_USER_ONLY */
};
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index c8cec39217..1a9392645e 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -337,3 +337,78 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index,
target_ulong val)
return write_func(env, env->trigger_cur, tdata_index, val);
}
+
+void riscv_cpu_debug_excp_handler(CPUState *cs)
+{
+RISCVCPU *cpu = RISCV_CPU(cs);
+CPURISCVState *env = >env;
+
+if (cs->watchpoint_hit) {
+if (cs->watchpoint_hit->flags & BP_CPU) {
+cs->watchpoint_hit = NULL;
+riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);
+}
+} else {
+if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) {
+riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);
+}
+}
+}
+
+bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
+{
+RISCVCPU *cpu = RISCV_CPU(cs);
+CPURISCVState *env = >env;
+CPUBreakpoint *bp;
+target_ulong ctrl;
+target_ulong pc;
+int i;
+
+QTAILQ_FOREACH(bp, >breakpoints, entry) {
+for (i = 0; i < TRIGGER_TYPE2_NUM; i++) {
+ctrl = env->type2_trig[i].mcontrol;
+pc = env->type2_trig[i].maddress;
+
+if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
+/* check U/S/M bit against current privilege level */
+if ((ctrl >> 3) & BIT(env->priv)) {
+return true;
+}
+}
+}
+}
+
+return false;
+}
+
+bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
+{
+RISCVCPU *cpu = RISCV_CPU(cs);
+CPURISCVState *env = >env;
+target_ulong ctrl;
+target_ulong addr;
+int flags;
+int i;
+
+for (i = 0; i < TRIGGER_TYPE2_NUM; i++) {
+ctrl = env->type2_trig[i].mcontrol;
+addr = env->type2_trig[i].maddress;
+flags = 0;
+
+if (ctrl & TYPE2_LOAD) {
+flags |= BP_MEM_READ;
+}
+if (ctrl & TYPE2_STORE) {
+flags |= BP_MEM_WRITE;
+}
+
+if ((wp->flags & flags) && (wp->vaddr == addr)) {
+/* check U/S/M bit against current privilege level */
+if ((ctrl >> 3) & BIT(env->priv)) {
+return true;
+}
+}
+}
+
+return false;
+}
--
2.25.1
[PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs
This adds initial support for the Sdtrig extension via the Trigger Module, as defined in the RISC-V Debug Specification [1]. Only "Address / Data Match" trigger (type 2) is implemented as of now, which is mainly used for hardware breakpoint and watchpoint. The number of type 2 triggers implemented is 2, which is the number that we can find in the SiFive U54/U74 cores. [1] https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf Changes in v5: - rebase against riscv-to-apply.next - drop patch 1 in v4 which is already in riscv-to-apply.next - adjust patch order to let patch 2 in v4 come later Changes in v4: - move riscv_trigger_init() call to riscv_cpu_reset() Changes in v3: - add riscv_trigger_init(), moved from patch #1 to this patch - enable debug feature by default for all CPUs Changes in v2: - use 0 instead of GETPC() - change the config option to 'disabled' by default - new patch: add debug state description Bin Meng (6): target/riscv: debug: Implement debug related TCGCPUOps target/riscv: cpu: Add a config option for native debug target/riscv: csr: Hook debug CSR read/write target/riscv: machine: Add debug state description target/riscv: cpu: Enable native debug feature hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() include/hw/core/tcg-cpu-ops.h | 1 + target/riscv/cpu.h| 4 +- target/riscv/debug.h | 6 ++ target/riscv/cpu.c| 12 target/riscv/csr.c| 57 +++ target/riscv/debug.c | 102 ++ target/riscv/machine.c| 32 +++ 7 files changed, 213 insertions(+), 1 deletion(-) -- 2.25.1
Re: [PATCH v4 2/7] target/riscv: machine: Add debug state description
On Thu, Apr 21, 2022 at 8:14 AM Alistair Francis wrote:
>
> On Thu, Apr 21, 2022 at 9:47 AM Bin Meng wrote:
> >
> > Hi Alistair,
> >
> > On Thu, Apr 21, 2022 at 6:45 AM Alistair Francis
> > wrote:
> > >
> > > On Wed, Apr 20, 2022 at 7:52 PM Bin Meng wrote:
> > > >
> > > > Hi Alistair,
> > > >
> > > > On Wed, Apr 20, 2022 at 3:33 PM Bin Meng wrote:
> > > > >
> > > > > On Wed, Apr 20, 2022 at 3:31 PM Alistair Francis
> > > > > wrote:
> > > > > >
> > > > > > On Tue, Mar 15, 2022 at 5:17 PM Bin Meng wrote:
> > > > > > >
> > > > > > > From: Bin Meng
> > > > > > >
> > > > > > > Add a subsection to machine.c to migrate debug CSR state.
> > > > > > >
> > > > > > > Signed-off-by: Bin Meng
> > > > > > > Reviewed-by: Alistair Francis
> > > > > > > ---
> > > > > > >
> > > > > > > (no changes since v2)
> > > > > > >
> > > > > > > Changes in v2:
> > > > > > > - new patch: add debug state description
> > > > > > >
> > > > > > > target/riscv/machine.c | 32
> > > > > > > 1 file changed, 32 insertions(+)
> > > > > > >
> > > > > > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> > > > > > > index 5178b3fec9..4921dad09d 100644
> > > > > > > --- a/target/riscv/machine.c
> > > > > > > +++ b/target/riscv/machine.c
> > > > > > > @@ -216,7 +216,38 @@ static const VMStateDescription
> > > > > > > vmstate_kvmtimer = {
> > > > > > > VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
> > > > > > > VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
> > > > > > > VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
> > > > > > > +VMSTATE_END_OF_LIST()
> > > > > > > +}
> > > > > > > +};
> > > > > > > +
> > > > > > > +static bool debug_needed(void *opaque)
> > > > > > > +{
> > > > > > > +RISCVCPU *cpu = opaque;
> > > > > > > +CPURISCVState *env = >env;
> > > > > > > +
> > > > > > > +return riscv_feature(env, RISCV_FEATURE_DEBUG);
> > > > > >
> > > > > > This fails to build:
> > > > > >
> > > > > > ../target/riscv/machine.c: In function ‘debug_needed’:
> > > > > > ../target/riscv/machine.c:228:31: error: ‘RISCV_FEATURE_DEBUG’
> > > > > > undeclared (first use in this function); did you mean
> > > > > > ‘RISCV_FEATURE_EPMP’?
> > > > > > 228 | return riscv_feature(env, RISCV_FEATURE_DEBUG);
> > > > > > | ^~~
> > > > > > | RISCV_FEATURE_EPMP
> > > > > > ../target/riscv/machine.c:228:31: note: each undeclared identifier
> > > > > > is
> > > > > > reported only once for each function it appears in
> > > > > > ../target/riscv/machine.c:229:1: warning: control reaches end of
> > > > > > non-void function [-Wreturn-type]
> > > > > > 229 | }
> > > > > > | ^
> > > > >
> > > > > That's weird. Maybe it's out of sync or merge conflict? I will take a
> > > > > look.
> > > > >
> > > >
> > > > I rebased the v4 series on top of your riscv-to-apply.next branch,
> > > > indeed there is a merge conflict of target/riscv/machine.c. After I
> > > > resolved the conflict, the build succeeded.
> > >
> > > Looking at this patch series RISCV_FEATURE_DEBUG is only defined in
> > > patch 4, it doesn't currently exist in the tree. I'm not sure how this
> > > can build.
> >
> > Ah, it looks like I should adjust the patch order to have patch 4 come
> > first.
> >
> > >
> > > Are you sure you looked at just this patch and not the entire series?
> >
> > I see. I was looking at the series not this patch.
> >
> > It seems you were trying to build every commit for bisectabliity? Is
> > there an easy way to do such automatically?
>
> Yep, I build test every patch.
>
> I do this automatically with an internal Jenkins server, unfortunately
> I can't really share it publically
>
Okay, I will send a rebased version, plus fixing the patch order.
Regards,
Bin
Re: [PATCH v4 2/7] target/riscv: machine: Add debug state description
On Thu, Apr 21, 2022 at 9:47 AM Bin Meng wrote:
>
> Hi Alistair,
>
> On Thu, Apr 21, 2022 at 6:45 AM Alistair Francis wrote:
> >
> > On Wed, Apr 20, 2022 at 7:52 PM Bin Meng wrote:
> > >
> > > Hi Alistair,
> > >
> > > On Wed, Apr 20, 2022 at 3:33 PM Bin Meng wrote:
> > > >
> > > > On Wed, Apr 20, 2022 at 3:31 PM Alistair Francis
> > > > wrote:
> > > > >
> > > > > On Tue, Mar 15, 2022 at 5:17 PM Bin Meng wrote:
> > > > > >
> > > > > > From: Bin Meng
> > > > > >
> > > > > > Add a subsection to machine.c to migrate debug CSR state.
> > > > > >
> > > > > > Signed-off-by: Bin Meng
> > > > > > Reviewed-by: Alistair Francis
> > > > > > ---
> > > > > >
> > > > > > (no changes since v2)
> > > > > >
> > > > > > Changes in v2:
> > > > > > - new patch: add debug state description
> > > > > >
> > > > > > target/riscv/machine.c | 32
> > > > > > 1 file changed, 32 insertions(+)
> > > > > >
> > > > > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> > > > > > index 5178b3fec9..4921dad09d 100644
> > > > > > --- a/target/riscv/machine.c
> > > > > > +++ b/target/riscv/machine.c
> > > > > > @@ -216,7 +216,38 @@ static const VMStateDescription
> > > > > > vmstate_kvmtimer = {
> > > > > > VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
> > > > > > VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
> > > > > > VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
> > > > > > +VMSTATE_END_OF_LIST()
> > > > > > +}
> > > > > > +};
> > > > > > +
> > > > > > +static bool debug_needed(void *opaque)
> > > > > > +{
> > > > > > +RISCVCPU *cpu = opaque;
> > > > > > +CPURISCVState *env = >env;
> > > > > > +
> > > > > > +return riscv_feature(env, RISCV_FEATURE_DEBUG);
> > > > >
> > > > > This fails to build:
> > > > >
> > > > > ../target/riscv/machine.c: In function ‘debug_needed’:
> > > > > ../target/riscv/machine.c:228:31: error: ‘RISCV_FEATURE_DEBUG’
> > > > > undeclared (first use in this function); did you mean
> > > > > ‘RISCV_FEATURE_EPMP’?
> > > > > 228 | return riscv_feature(env, RISCV_FEATURE_DEBUG);
> > > > > | ^~~
> > > > > | RISCV_FEATURE_EPMP
> > > > > ../target/riscv/machine.c:228:31: note: each undeclared identifier is
> > > > > reported only once for each function it appears in
> > > > > ../target/riscv/machine.c:229:1: warning: control reaches end of
> > > > > non-void function [-Wreturn-type]
> > > > > 229 | }
> > > > > | ^
> > > >
> > > > That's weird. Maybe it's out of sync or merge conflict? I will take a
> > > > look.
> > > >
> > >
> > > I rebased the v4 series on top of your riscv-to-apply.next branch,
> > > indeed there is a merge conflict of target/riscv/machine.c. After I
> > > resolved the conflict, the build succeeded.
> >
> > Looking at this patch series RISCV_FEATURE_DEBUG is only defined in
> > patch 4, it doesn't currently exist in the tree. I'm not sure how this
> > can build.
>
> Ah, it looks like I should adjust the patch order to have patch 4 come first.
>
> >
> > Are you sure you looked at just this patch and not the entire series?
>
> I see. I was looking at the series not this patch.
>
> It seems you were trying to build every commit for bisectabliity? Is
> there an easy way to do such automatically?
Yep, I build test every patch.
I do this automatically with an internal Jenkins server, unfortunately
I can't really share it publically
Alistair
>
> >
> > >
> > > I suspect you missed something during your handling of the merge conflict?
> >
> > That's entirely possible. Can you send a rebased version please
>
> Regards,
> Bin
Re: [PATCH v4 2/7] target/riscv: machine: Add debug state description
Hi Alistair,
On Thu, Apr 21, 2022 at 6:45 AM Alistair Francis wrote:
>
> On Wed, Apr 20, 2022 at 7:52 PM Bin Meng wrote:
> >
> > Hi Alistair,
> >
> > On Wed, Apr 20, 2022 at 3:33 PM Bin Meng wrote:
> > >
> > > On Wed, Apr 20, 2022 at 3:31 PM Alistair Francis
> > > wrote:
> > > >
> > > > On Tue, Mar 15, 2022 at 5:17 PM Bin Meng wrote:
> > > > >
> > > > > From: Bin Meng
> > > > >
> > > > > Add a subsection to machine.c to migrate debug CSR state.
> > > > >
> > > > > Signed-off-by: Bin Meng
> > > > > Reviewed-by: Alistair Francis
> > > > > ---
> > > > >
> > > > > (no changes since v2)
> > > > >
> > > > > Changes in v2:
> > > > > - new patch: add debug state description
> > > > >
> > > > > target/riscv/machine.c | 32
> > > > > 1 file changed, 32 insertions(+)
> > > > >
> > > > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> > > > > index 5178b3fec9..4921dad09d 100644
> > > > > --- a/target/riscv/machine.c
> > > > > +++ b/target/riscv/machine.c
> > > > > @@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer
> > > > > = {
> > > > > VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
> > > > > VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
> > > > > VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
> > > > > +VMSTATE_END_OF_LIST()
> > > > > +}
> > > > > +};
> > > > > +
> > > > > +static bool debug_needed(void *opaque)
> > > > > +{
> > > > > +RISCVCPU *cpu = opaque;
> > > > > +CPURISCVState *env = >env;
> > > > > +
> > > > > +return riscv_feature(env, RISCV_FEATURE_DEBUG);
> > > >
> > > > This fails to build:
> > > >
> > > > ../target/riscv/machine.c: In function ‘debug_needed’:
> > > > ../target/riscv/machine.c:228:31: error: ‘RISCV_FEATURE_DEBUG’
> > > > undeclared (first use in this function); did you mean
> > > > ‘RISCV_FEATURE_EPMP’?
> > > > 228 | return riscv_feature(env, RISCV_FEATURE_DEBUG);
> > > > | ^~~
> > > > | RISCV_FEATURE_EPMP
> > > > ../target/riscv/machine.c:228:31: note: each undeclared identifier is
> > > > reported only once for each function it appears in
> > > > ../target/riscv/machine.c:229:1: warning: control reaches end of
> > > > non-void function [-Wreturn-type]
> > > > 229 | }
> > > > | ^
> > >
> > > That's weird. Maybe it's out of sync or merge conflict? I will take a
> > > look.
> > >
> >
> > I rebased the v4 series on top of your riscv-to-apply.next branch,
> > indeed there is a merge conflict of target/riscv/machine.c. After I
> > resolved the conflict, the build succeeded.
>
> Looking at this patch series RISCV_FEATURE_DEBUG is only defined in
> patch 4, it doesn't currently exist in the tree. I'm not sure how this
> can build.
Ah, it looks like I should adjust the patch order to have patch 4 come first.
>
> Are you sure you looked at just this patch and not the entire series?
I see. I was looking at the series not this patch.
It seems you were trying to build every commit for bisectabliity? Is
there an easy way to do such automatically?
>
> >
> > I suspect you missed something during your handling of the merge conflict?
>
> That's entirely possible. Can you send a rebased version please
Regards,
Bin
Re: [PULL 00/39] Logging cleanup and per-thread logfiles
On 4/20/22 11:05, Richard Henderson wrote: The following changes since commit 40a4b96eb08b3a3e83895f46b2394748dac7a641: Merge tag 'pull-block-2022-04-20' of https://gitlab.com/hreitz/qemu into staging (2022-04-20 09:39:33 -0700) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-log-20220420 for you to fetch changes up to 4e51069d679348d2617512e56e28cdc7bb34c833: util/log: Support per-thread log files (2022-04-20 10:51:11 -0700) Clean up log locking. Use the FILE* from qemu_log_trylock more often. Support per-thread log files with -d tid. Applied, thanks. Please update the wiki changelog for 7.1 as appropriate. r~ Richard Henderson (39): util/log: Drop manual log buffering target/hexagon: Remove qemu_set_log in hexagon_translate_init util/log: Return bool from qemu_set_log_filename util/log: Pass Error pointer to qemu_set_log os-posix: Use qemu_log_enabled util/log: Move qemu_log_lock, qemu_log_unlock out of line util/log: Rename qemu_log_lock to qemu_log_trylock hw/xen: Split out xen_pv_output_msg *: Use fprintf between qemu_log_trylock/unlock util/log: Remove qemu_log_vprintf tcg: Pass the locked filepointer to tcg_dump_ops exec/translator: Pass the locked filepointer to disas_log hook exec/log: Remove log_disas and log_target_disas accel/tcg: Use cpu_dump_state between qemu_log_trylock/unlock target/nios2: Remove log_cpu_state from reset util/log: Use qemu_log_trylock/unlock in qemu_log util/log: Drop return value from qemu_log util/log: Mark qemu_log_trylock as G_GNUC_WARN_UNUSED_RESULT util/log: Remove qemu_log_flush util/log: Drop call to setvbuf bsd-user: Expand log_page_dump inline linux-user: Expand log_page_dump inline tests/unit: Do not reference QemuLogFile directly include/exec/log: Do not reference QemuLogFile directly include/qemu/log: Move entire implementation out-of-line sysemu/os-win32: Test for and use _lock_file/_unlock_file util/log: Introduce qemu_set_log_filename_flags bsd-user: Use qemu_set_log_filename_flags linux-user: Use qemu_set_log_filename_flags softmmu: Use qemu_set_log_filename_flags util/log: Remove qemu_log_close util/log: Rename logfilename to global_filename util/log: Rename qemu_logfile to global_file util/log: Rename qemu_logfile_mutex to global_mutex util/log: Hoist the eval of is_daemonized in qemu_set_log_internal util/log: Combine two logfile closes util/log: Rename QemuLogFile to RCUCloseFILE util/log: Limit RCUCloseFILE to file closing util/log: Support per-thread log files meson.build | 12 ++ include/exec/log.h | 52 + include/exec/translator.h| 2 +- include/qemu/log-for-trace.h | 2 +- include/qemu/log.h | 93 + include/sysemu/os-win32.h| 16 +- accel/tcg/cpu-exec.c | 18 +- accel/tcg/translate-all.c| 118 +-- accel/tcg/translator.c | 12 +- bsd-user/main.c | 54 ++--- cpu.c| 16 +- hw/net/can/can_sja1000.c | 25 +-- hw/xen/xen_pvdev.c | 45 +++-- linux-user/main.c| 55 +++-- linux-user/mmap.c| 7 +- monitor/misc.c | 9 +- net/can/can_socketcan.c | 24 ++- os-posix.c | 2 +- qemu-img.c | 2 +- qemu-io.c| 2 +- qemu-nbd.c | 2 +- scsi/qemu-pr-helper.c| 2 +- softmmu/vl.c | 21 +- storage-daemon/qemu-storage-daemon.c | 2 +- target/alpha/translate.c | 7 +- target/arm/translate-a64.c | 6 +- target/arm/translate.c | 7 +- target/avr/translate.c | 7 +- target/cris/translate.c | 7 +- target/hexagon/translate.c | 13 +- target/hppa/translate.c | 15 +- target/i386/tcg/translate.c | 22 +- target/m68k/translate.c | 7 +- target/microblaze/translate.c| 7 +- target/mips/tcg/translate.c | 7 +- target/nios2/cpu.c | 5 - target/nios2/translate.c | 7 +- target/openrisc/translate.c | 7 +- target/ppc/translate.c | 7 +- target/riscv/translate.c | 10 +- target/rx/translate.c| 7 +- target/s390x/tcg/translate.c | 11 +- target/sh4/translate.c
Re: [PATCH v4 2/7] target/riscv: machine: Add debug state description
On Wed, Apr 20, 2022 at 7:52 PM Bin Meng wrote:
>
> Hi Alistair,
>
> On Wed, Apr 20, 2022 at 3:33 PM Bin Meng wrote:
> >
> > On Wed, Apr 20, 2022 at 3:31 PM Alistair Francis
> > wrote:
> > >
> > > On Tue, Mar 15, 2022 at 5:17 PM Bin Meng wrote:
> > > >
> > > > From: Bin Meng
> > > >
> > > > Add a subsection to machine.c to migrate debug CSR state.
> > > >
> > > > Signed-off-by: Bin Meng
> > > > Reviewed-by: Alistair Francis
> > > > ---
> > > >
> > > > (no changes since v2)
> > > >
> > > > Changes in v2:
> > > > - new patch: add debug state description
> > > >
> > > > target/riscv/machine.c | 32
> > > > 1 file changed, 32 insertions(+)
> > > >
> > > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> > > > index 5178b3fec9..4921dad09d 100644
> > > > --- a/target/riscv/machine.c
> > > > +++ b/target/riscv/machine.c
> > > > @@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer =
> > > > {
> > > > VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
> > > > VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
> > > > VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
> > > > +VMSTATE_END_OF_LIST()
> > > > +}
> > > > +};
> > > > +
> > > > +static bool debug_needed(void *opaque)
> > > > +{
> > > > +RISCVCPU *cpu = opaque;
> > > > +CPURISCVState *env = >env;
> > > > +
> > > > +return riscv_feature(env, RISCV_FEATURE_DEBUG);
> > >
> > > This fails to build:
> > >
> > > ../target/riscv/machine.c: In function ‘debug_needed’:
> > > ../target/riscv/machine.c:228:31: error: ‘RISCV_FEATURE_DEBUG’
> > > undeclared (first use in this function); did you mean
> > > ‘RISCV_FEATURE_EPMP’?
> > > 228 | return riscv_feature(env, RISCV_FEATURE_DEBUG);
> > > | ^~~
> > > | RISCV_FEATURE_EPMP
> > > ../target/riscv/machine.c:228:31: note: each undeclared identifier is
> > > reported only once for each function it appears in
> > > ../target/riscv/machine.c:229:1: warning: control reaches end of
> > > non-void function [-Wreturn-type]
> > > 229 | }
> > > | ^
> >
> > That's weird. Maybe it's out of sync or merge conflict? I will take a look.
> >
>
> I rebased the v4 series on top of your riscv-to-apply.next branch,
> indeed there is a merge conflict of target/riscv/machine.c. After I
> resolved the conflict, the build succeeded.
Looking at this patch series RISCV_FEATURE_DEBUG is only defined in
patch 4, it doesn't currently exist in the tree. I'm not sure how this
can build.
Are you sure you looked at just this patch and not the entire series?
>
> I suspect you missed something during your handling of the merge conflict?
That's entirely possible. Can you send a rebased version please
Alistair
>
> Regards,
> Bin
Re: [PATCH v4 0/4] Support ACLINT 32/64-bit mtimecmp/mtime read/write accesses
On Wed, Apr 20, 2022 at 6:09 PM wrote: > > From: Frank Chang > > This patchset makes ACLINT mtime to be writable as RISC-V privilege > spec defines that mtime is exposed as a memory-mapped machine-mode > read-write register. Also, mtimecmp and mtime should be 32/64-bit memory > accessible registers. ACLINT reset function is also added, which requires > mtime to be resetable if we need to support core power-gating feature in > the future. > > This patchset is the updated verion of: > https://patchew.org/QEMU/20220126095448.2964-1-frank.ch...@sifive.com/ Thanks! Applied to riscv-to-apply.next Alistair > > Changelog: > > v4: > * Replace the error log mask for invalid 8-byte timecmp_hi and time_hi > writes from LOG_UNIMP to LOG_GUEST_ERROR. > > v3: > * Forbid 8-byte write access to timecmp_hi and time_hi. > * Add ACLINT reset function. > > v2: > * Support 32/64-bit mtimecmp/mtime memory accesses. > * Add .impl.[min|max]_access_size declaration. > > Frank Chang (3): > hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT > hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V > ACLINT > hw/intc: Make RISC-V ACLINT mtime MMIO register writable > > Jim Shu (1): > hw/intc: riscv_aclint: Add reset function of ACLINT devices > > hw/intc/riscv_aclint.c | 144 ++--- > include/hw/intc/riscv_aclint.h | 1 + > target/riscv/cpu.h | 8 +- > target/riscv/cpu_helper.c | 4 +- > 4 files changed, 121 insertions(+), 36 deletions(-) > > -- > 2.35.1 > >
[PULL 19/23] ppc/vof: Fix uninitialized string tracing
From: Alexey Kardashevskiy
There are error paths which do not initialize propname but the trace_exit
label prints it anyway. This initializes the problem string.
Spotted by Coverity CID 1487241.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20220406045013.3610172-1-...@ozlabs.ru>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/vof.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/vof.c b/hw/ppc/vof.c
index 8d96593677..18c3f92317 100644
--- a/hw/ppc/vof.c
+++ b/hw/ppc/vof.c
@@ -293,7 +293,7 @@ static uint32_t vof_setprop(MachineState *ms, void *fdt,
Vof *vof,
uint32_t nodeph, uint32_t pname,
uint32_t valaddr, uint32_t vallen)
{
-char propname[OF_PROPNAME_LEN_MAX + 1];
+char propname[OF_PROPNAME_LEN_MAX + 1] = "";
uint32_t ret = PROM_ERROR;
int offset, rc;
char trval[64] = "";
--
2.35.1
[PULL 23/23] hw/ppc: change indentation to spaces from TABs
From: Guo Zhi
There are still some files in the QEMU PPC code base that use TABs for
indentation instead of using spaces. The TABs should be replaced so
that we have a consistent coding style.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/374
Signed-off-by: Guo Zhi
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20220412021240.2080218-1-qtxuning1...@sjtu.edu.cn>
[danielhb: trimmed commit msg to 72 chars per line]
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc440_bamboo.c | 6 +++---
hw/ppc/spapr_rtas.c| 18 +-
include/hw/ppc/ppc.h | 10 +-
3 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index efa90ef5ba..d5973f2484 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -3,9 +3,9 @@
*
* Copyright 2007 IBM Corporation.
* Authors:
- * Jerone Young
- * Christian Ehrhardt
- * Hollis Blanchard
+ * Jerone Young
+ * Christian Ehrhardt
+ * Hollis Blanchard
*
* This work is licensed under the GNU GPL license version 2 or later.
*
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index d7c04237fe..d58b65e88f 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -474,16 +474,16 @@ static void rtas_ibm_nmi_interlock(PowerPCCPU *cpu,
if (spapr->fwnmi_machine_check_interlock != cpu->vcpu_id) {
/*
-* The vCPU that hit the NMI should invoke "ibm,nmi-interlock"
+ * The vCPU that hit the NMI should invoke "ibm,nmi-interlock"
* This should be PARAM_ERROR, but Linux calls "ibm,nmi-interlock"
-* for system reset interrupts, despite them not being interlocked.
-* PowerVM silently ignores this and returns success here. Returning
-* failure causes Linux to print the error "FWNMI: nmi-interlock
-* failed: -3", although no other apparent ill effects, this is a
-* regression for the user when enabling FWNMI. So for now, match
-* PowerVM. When most Linux clients are fixed, this could be
-* changed.
-*/
+ * for system reset interrupts, despite them not being interlocked.
+ * PowerVM silently ignores this and returns success here. Returning
+ * failure causes Linux to print the error "FWNMI: nmi-interlock
+ * failed: -3", although no other apparent ill effects, this is a
+ * regression for the user when enabling FWNMI. So for now, match
+ * PowerVM. When most Linux clients are fixed, this could be
+ * changed.
+ */
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
return;
}
diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
index 364f165b4b..02af03ada2 100644
--- a/include/hw/ppc/ppc.h
+++ b/include/hw/ppc/ppc.h
@@ -99,11 +99,11 @@ enum {
ARCH_MAC99_U3,
};
-#define FW_CFG_PPC_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
-#define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
-#define FW_CFG_PPC_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
-#define FW_CFG_PPC_TBFREQ (FW_CFG_ARCH_LOCAL + 0x03)
-#define FW_CFG_PPC_CLOCKFREQ (FW_CFG_ARCH_LOCAL + 0x04)
+#define FW_CFG_PPC_WIDTH(FW_CFG_ARCH_LOCAL + 0x00)
+#define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
+#define FW_CFG_PPC_DEPTH(FW_CFG_ARCH_LOCAL + 0x02)
+#define FW_CFG_PPC_TBFREQ (FW_CFG_ARCH_LOCAL + 0x03)
+#define FW_CFG_PPC_CLOCKFREQ(FW_CFG_ARCH_LOCAL + 0x04)
#define FW_CFG_PPC_IS_KVM (FW_CFG_ARCH_LOCAL + 0x05)
#define FW_CFG_PPC_KVM_HC (FW_CFG_ARCH_LOCAL + 0x06)
#define FW_CFG_PPC_KVM_PID (FW_CFG_ARCH_LOCAL + 0x07)
--
2.35.1
[PULL 14/23] softfloat: add float128_to_uint128
From: Matheus Ferst
Implements float128_to_uint128 based on parts_float_to_uint logic.
Signed-off-by: Matheus Ferst
Reviewed-by: Richard Henderson
Message-Id: <20220330175932.6995-6-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza
---
fpu/softfloat.c | 65 +
include/fpu/softfloat.h | 2 ++
2 files changed, 67 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 60b4702945..ce21b64e4f 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -3480,6 +3480,61 @@ static uint64_t float128_to_uint64_scalbn(float128 a,
FloatRoundMode rmode,
return parts_float_to_uint(, rmode, scale, UINT64_MAX, s);
}
+static Int128 float128_to_uint128_scalbn(float128 a, FloatRoundMode rmode,
+ int scale, float_status *s)
+{
+int flags = 0;
+Int128 r;
+FloatParts128 p;
+
+float128_unpack_canonical(, a, s);
+
+switch (p.cls) {
+case float_class_snan:
+flags |= float_flag_invalid_snan;
+/* fall through */
+case float_class_qnan:
+flags |= float_flag_invalid;
+r = UINT128_MAX;
+break;
+
+case float_class_inf:
+flags = float_flag_invalid | float_flag_invalid_cvti;
+r = p.sign ? int128_zero() : UINT128_MAX;
+break;
+
+case float_class_zero:
+return int128_zero();
+
+case float_class_normal:
+if (parts_round_to_int_normal(, rmode, scale, 128 - 2)) {
+flags = float_flag_inexact;
+if (p.cls == float_class_zero) {
+r = int128_zero();
+break;
+}
+}
+
+if (p.sign) {
+flags = float_flag_invalid | float_flag_invalid_cvti;
+r = int128_zero();
+} else if (p.exp <= 127) {
+int shift = 127 - p.exp;
+r = int128_urshift(int128_make128(p.frac_lo, p.frac_hi), shift);
+} else {
+flags = float_flag_invalid | float_flag_invalid_cvti;
+r = UINT128_MAX;
+}
+break;
+
+default:
+g_assert_not_reached();
+}
+
+float_raise(flags, s);
+return r;
+}
+
uint8_t float16_to_uint8(float16 a, float_status *s)
{
return float16_to_uint8_scalbn(a, s->float_rounding_mode, 0, s);
@@ -3540,6 +3595,11 @@ uint64_t float128_to_uint64(float128 a, float_status *s)
return float128_to_uint64_scalbn(a, s->float_rounding_mode, 0, s);
}
+Int128 float128_to_uint128(float128 a, float_status *s)
+{
+return float128_to_uint128_scalbn(a, s->float_rounding_mode, 0, s);
+}
+
uint16_t float16_to_uint16_round_to_zero(float16 a, float_status *s)
{
return float16_to_uint16_scalbn(a, float_round_to_zero, 0, s);
@@ -3595,6 +3655,11 @@ uint64_t float128_to_uint64_round_to_zero(float128 a,
float_status *s)
return float128_to_uint64_scalbn(a, float_round_to_zero, 0, s);
}
+Int128 float128_to_uint128_round_to_zero(float128 a, float_status *s)
+{
+return float128_to_uint128_scalbn(a, float_round_to_zero, 0, s);
+}
+
uint16_t bfloat16_to_uint16(bfloat16 a, float_status *s)
{
return bfloat16_to_uint16_scalbn(a, s->float_rounding_mode, 0, s);
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 3994b7235d..6cfe9ee474 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -1206,7 +1206,9 @@ int32_t float128_to_int32_round_to_zero(float128,
float_status *status);
int64_t float128_to_int64(float128, float_status *status);
int64_t float128_to_int64_round_to_zero(float128, float_status *status);
uint64_t float128_to_uint64(float128, float_status *status);
+Int128 float128_to_uint128(float128, float_status *status);
uint64_t float128_to_uint64_round_to_zero(float128, float_status *status);
+Int128 float128_to_uint128_round_to_zero(float128, float_status *status);
uint32_t float128_to_uint32(float128, float_status *status);
uint32_t float128_to_uint32_round_to_zero(float128, float_status *status);
float32 float128_to_float32(float128, float_status *status);
--
2.35.1
[PULL 20/23] pcie: Don't try triggering a LSI when not defined
From: Frederic Barrat
This patch skips [de]asserting a LSI interrupt if the device doesn't
have any LSI defined. Doing so would trigger an assert in
pci_irq_handler().
The PCIE root port implementation in qemu requests a LSI (INTA), but a
subclass may want to change that behavior since it's a valid
configuration. For example on the POWER8/POWER9/POWER10 systems, the
root bridge doesn't request any LSI.
Signed-off-by: Frederic Barrat
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Michael S. Tsirkin
Message-Id: <20220408131303.147840-2-fbar...@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza
---
hw/pci/pcie.c | 5 +++--
hw/pci/pcie_aer.c | 2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 67a5d67372..68a62da0b5 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -353,7 +353,7 @@ static void hotplug_event_notify(PCIDevice *dev)
msix_notify(dev, pcie_cap_flags_get_vector(dev));
} else if (msi_enabled(dev)) {
msi_notify(dev, pcie_cap_flags_get_vector(dev));
-} else {
+} else if (pci_intx(dev) != -1) {
pci_set_irq(dev, dev->exp.hpev_notified);
}
}
@@ -361,7 +361,8 @@ static void hotplug_event_notify(PCIDevice *dev)
static void hotplug_event_clear(PCIDevice *dev)
{
hotplug_event_update_event_status(dev);
-if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) {
+if (!msix_enabled(dev) && !msi_enabled(dev) && pci_intx(dev) != -1 &&
+!dev->exp.hpev_notified) {
pci_irq_deassert(dev);
}
}
diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c
index e1a8a88c8c..92bd0530dd 100644
--- a/hw/pci/pcie_aer.c
+++ b/hw/pci/pcie_aer.c
@@ -290,7 +290,7 @@ static void pcie_aer_root_notify(PCIDevice *dev)
msix_notify(dev, pcie_aer_root_get_vector(dev));
} else if (msi_enabled(dev)) {
msi_notify(dev, pcie_aer_root_get_vector(dev));
-} else {
+} else if (pci_intx(dev) != -1) {
pci_irq_assert(dev);
}
}
--
2.35.1
[PULL 08/23] spapr: Move hypercall_register_softmmu
From: Fabiano Rosas
I'm moving this because next patch will add more code under the ifdef
and it will be cleaner if we keep them together.
Also switch the ifdef branches to make it more convenient to add code
under CONFIG_TCG in the next patch.
Signed-off-by: Fabiano Rosas
Reviewed-by: Nicholas Piggin
Message-Id: <20220325221113.255834-2-faro...@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/spapr_hcall.c | 50 ++--
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 7c8bb76f99..9b24db5e44 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -1473,31 +1473,6 @@ target_ulong spapr_hypercall(PowerPCCPU *cpu,
target_ulong opcode,
return H_FUNCTION;
}
-#ifndef CONFIG_TCG
-static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr,
-target_ulong opcode, target_ulong *args)
-{
-g_assert_not_reached();
-}
-
-static void hypercall_register_softmmu(void)
-{
-/* hcall-pft */
-spapr_register_hypercall(H_ENTER, h_softmmu);
-spapr_register_hypercall(H_REMOVE, h_softmmu);
-spapr_register_hypercall(H_PROTECT, h_softmmu);
-spapr_register_hypercall(H_READ, h_softmmu);
-
-/* hcall-bulk */
-spapr_register_hypercall(H_BULK_REMOVE, h_softmmu);
-}
-#else
-static void hypercall_register_softmmu(void)
-{
-/* DO NOTHING */
-}
-#endif
-
/* TCG only */
#define PRTS_MASK 0x1f
@@ -1825,6 +1800,31 @@ out_restore_l1:
spapr_cpu->nested_host_state = NULL;
}
+#ifdef CONFIG_TCG
+static void hypercall_register_softmmu(void)
+{
+/* DO NOTHING */
+}
+#else
+static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr,
+target_ulong opcode, target_ulong *args)
+{
+g_assert_not_reached();
+}
+
+static void hypercall_register_softmmu(void)
+{
+/* hcall-pft */
+spapr_register_hypercall(H_ENTER, h_softmmu);
+spapr_register_hypercall(H_REMOVE, h_softmmu);
+spapr_register_hypercall(H_PROTECT, h_softmmu);
+spapr_register_hypercall(H_READ, h_softmmu);
+
+/* hcall-bulk */
+spapr_register_hypercall(H_BULK_REMOVE, h_softmmu);
+}
+#endif
+
static void hypercall_register_types(void)
{
hypercall_register_softmmu();
--
2.35.1
[PULL 22/23] target/ppc: Add two missing register callbacks on POWER10
From: Frederic Barrat This patch adds tcg accessors for 2 SPRs which were missing on P10: - the TBU40 register is used to write the upper 40 bits of the timebase register. It is used by kvm to update the timebase when entering/exiting the guest on P9 and above. The missing definition was causing erratic decrementer interrupts in a pseries/kvm guest running in a powernv10/tcg host, typically resulting in hangs. - the missing DPDES SPR was found through code inspection. It exists unchanged on P10. Both existed on previous versions of the processor and a bit of git archaeology hints that they were added while the P10 model was already being worked on so they may have simply fallen through the cracks. Signed-off-by: Frederic Barrat Reviewed-by: Fabiano Rosas Message-Id: <20220411125900.352028-1-fbar...@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 5062d0e478..d42e2ba8e0 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6457,6 +6457,7 @@ static void init_proc_POWER10(CPUPPCState *env) register_power5p_common_sprs(env); register_power5p_lpar_sprs(env); register_power5p_ear_sprs(env); +register_power5p_tb_sprs(env); register_power6_common_sprs(env); register_power6_dbg_sprs(env); register_power8_tce_address_control_sprs(env); @@ -6467,6 +6468,7 @@ static void init_proc_POWER10(CPUPPCState *env) register_power8_pmu_user_sprs(env); register_power8_tm_sprs(env); register_power8_pspb_sprs(env); +register_power8_dpdes_sprs(env); register_vtb_sprs(env); register_power8_ic_sprs(env); register_power8_book4_sprs(env); -- 2.35.1
[PULL 06/23] ppc/pnv: Remove PnvPsiClas::irq_set
From: Cédric Le Goater
All devices raising PSI interrupts are now converted to use GPIO lines
and the pnv_psi_irq_set() routines have become useless. Drop them.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Message-Id: <20220323072846.1780212-5-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pnv_psi.c | 23 ++-
include/hw/ppc/pnv_psi.h | 4
2 files changed, 6 insertions(+), 21 deletions(-)
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 8b6298d4bd..950ecca405 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -211,19 +211,9 @@ static const uint64_t stat_bits[PSI_NUM_INTERRUPTS] = {
[PSIHB_IRQ_EXTERNAL] = PSIHB_IRQ_STAT_EXT,
};
-void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state)
-{
-PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state);
-}
-
-static void __pnv_psi_irq_set(void *opaque, int irq, int state)
-{
-PnvPsi *psi = (PnvPsi *) opaque;
-PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state);
-}
-
-static void pnv_psi_power8_irq_set(PnvPsi *psi, int irq, bool state)
+static void pnv_psi_power8_set_irq(void *opaque, int irq, int state)
{
+PnvPsi *psi = opaque;
uint32_t xivr_reg;
uint32_t stat_reg;
uint32_t src;
@@ -518,7 +508,7 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error
**errp)
ics_set_irq_type(ics, i, true);
}
-qdev_init_gpio_in(dev, __pnv_psi_irq_set, ics->nr_irqs);
+qdev_init_gpio_in(dev, pnv_psi_power8_set_irq, ics->nr_irqs);
psi->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs);
@@ -581,7 +571,6 @@ static void pnv_psi_power8_class_init(ObjectClass *klass,
void *data)
ppc->xscom_pcba = PNV_XSCOM_PSIHB_BASE;
ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE;
ppc->bar_mask = PSIHB_BAR_MASK;
-ppc->irq_set= pnv_psi_power8_irq_set;
ppc->compat = compat;
ppc->compat_size = sizeof(compat);
}
@@ -819,8 +808,9 @@ static const MemoryRegionOps pnv_psi_p9_xscom_ops = {
}
};
-static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state)
+static void pnv_psi_power9_set_irq(void *opaque, int irq, int state)
{
+PnvPsi *psi = opaque;
uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)];
if (irq > PSIHB9_NUM_IRQS) {
@@ -881,7 +871,7 @@ static void pnv_psi_power9_realize(DeviceState *dev, Error
**errp)
psi->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
-qdev_init_gpio_in(dev, __pnv_psi_irq_set, xsrc->nr_irqs);
+qdev_init_gpio_in(dev, pnv_psi_power9_set_irq, xsrc->nr_irqs);
/* XSCOM region for PSI registers */
pnv_xscom_region_init(>xscom_regs, OBJECT(dev), _psi_p9_xscom_ops,
@@ -908,7 +898,6 @@ static void pnv_psi_power9_class_init(ObjectClass *klass,
void *data)
ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE;
ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE;
ppc->bar_mask = PSIHB9_BAR_MASK;
-ppc->irq_set= pnv_psi_power9_irq_set;
ppc->compat = compat;
ppc->compat_size = sizeof(compat);
diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h
index 6d9f8ce7c0..8253469b8f 100644
--- a/include/hw/ppc/pnv_psi.h
+++ b/include/hw/ppc/pnv_psi.h
@@ -79,8 +79,6 @@ struct PnvPsiClass {
uint64_t bar_mask;
const char *compat;
int compat_size;
-
-void (*irq_set)(PnvPsi *psi, int, bool state);
};
/* The PSI and FSP interrupts are muxed on the same IRQ number */
@@ -95,8 +93,6 @@ typedef enum PnvPsiIrq {
#define PSI_NUM_INTERRUPTS 6
-void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state);
-
/* P9 PSI Interrupts */
#define PSIHB9_IRQ_PSI 0
#define PSIHB9_IRQ_OCC 1
--
2.35.1
[PULL 18/23] hw/ppc/ppc405_boards: Initialize g_autofree pointer
From: Bernhard Beschow
Resolves the only compiler warning when building a full QEMU under Arch Linux:
Compiling C object libqemu-ppc-softmmu.fa.p/hw_ppc_ppc405_boards.c.o
In file included from /usr/include/glib-2.0/glib.h:114,
from qemu/include/glib-compat.h:32,
from qemu/include/qemu/osdep.h:132,
from ../src/hw/ppc/ppc405_boards.c:25:
../src/hw/ppc/ppc405_boards.c: In function ‘ref405ep_init’:
/usr/include/glib-2.0/glib/glib-autocleanups.h:28:3: warning: ‘filename’ may
be used uninitialized in this function [-Wmaybe-uninitialized]
28 | g_free (*pp);
| ^~~~
../src/hw/ppc/ppc405_boards.c:265:26: note: ‘filename’ was declared here
265 | g_autofree char *filename;
| ^~~~
Signed-off-by: Bernhard Beschow
Reviewed-by: Peter Maydell
Message-Id: <20220405123534.3395-1-shen...@gmail.com>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc405_boards.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 32013b8983..a66ad05e3a 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -261,13 +261,13 @@ static void ref405ep_init(MachineState *machine)
/* allocate and load BIOS */
if (machine->firmware) {
MemoryRegion *bios = g_new(MemoryRegion, 1);
-g_autofree char *filename;
+g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
+ machine->firmware);
long bios_size;
memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE,
_fatal);
-filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
if (!filename) {
error_report("Could not find firmware '%s'", machine->firmware);
exit(1);
--
2.35.1
[PULL 17/23] target/ppc: implement xscvqp[su]qz
From: Matheus Ferst
Implement the following PowerISA v3.1 instructions:
xscvqpsqz: VSX Scalar Convert with round to zero Quad-Precision to
Signed Quadword
xscvqpuqz: VSX Scalar Convert with round to zero Quad-Precision to
Unsigned Quadword
Signed-off-by: Matheus Ferst
Reviewed-by: Richard Henderson
Message-Id: <20220330175932.6995-9-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/fpu_helper.c | 21 +
target/ppc/helper.h | 2 ++
target/ppc/insn32.decode| 2 ++
target/ppc/translate/vsx-impl.c.inc | 2 ++
4 files changed, 27 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 97892afa95..99281cc37a 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2925,6 +2925,27 @@ VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32,
VsrW(i), VsrW(i), 0x8000U)
VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2 * i), VsrD(i), 0ULL)
VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U)
+#define VSX_CVT_FP_TO_INT128(op, tp, rnan)
\
+void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb)
\
+{
\
+ppc_vsr_t t;
\
+int flags;
\
+
\
+helper_reset_fpstatus(env);
\
+t.s128 = float128_to_##tp##_round_to_zero(xb->f128, >fp_status);
\
+flags = get_float_exception_flags(>fp_status);
\
+if (unlikely(flags & float_flag_invalid)) {
\
+t.VsrD(0) = float_invalid_cvt(env, flags, t.VsrD(0), rnan, 0,
GETPC());\
+t.VsrD(1) = -(t.VsrD(0) & 1);
\
+}
\
+
\
+*xt = t;
\
+do_float_check_status(env, GETPC());
\
+}
+
+VSX_CVT_FP_TO_INT128(XSCVQPUQZ, uint128, 0)
+VSX_CVT_FP_TO_INT128(XSCVQPSQZ, int128, 0x8000ULL);
+
/*
* Likewise, except that the result is duplicated into both subwords.
* Power ISA v3.1 has Programming Notes for these insns:
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 7df0c01819..aa6773c4a5 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -388,6 +388,8 @@ DEF_HELPER_4(xscvqpsdz, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscvqpswz, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscvqpudz, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscvqpuwz, void, env, i32, vsr, vsr)
+DEF_HELPER_3(XSCVQPUQZ, void, env, vsr, vsr)
+DEF_HELPER_3(XSCVQPSQZ, void, env, vsr, vsr)
DEF_HELPER_3(XSCVUQQP, void, env, vsr, vsr)
DEF_HELPER_3(XSCVSQQP, void, env, vsr, vsr)
DEF_HELPER_3(xscvhpdp, void, env, vsr, vsr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 6fb568c1fe..39372fe673 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -695,6 +695,8 @@ XSCMPGTQP 11 . . . 0011100100 - @X
## VSX Binary Floating-Point Convert Instructions
XSCVQPDP11 . 10100 . 1101000100 . @X_tb_rc
+XSCVQPUQZ 11 . 0 . 1101000100 - @X_tb
+XSCVQPSQZ 11 . 01000 . 1101000100 - @X_tb
XSCVUQQP11 . 00011 . 1101000100 - @X_tb
XSCVSQQP11 . 01011 . 1101000100 - @X_tb
XVCVBF16SPN 00 . 1 . 111011011 .. @XX2
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index bda681e65c..3692740736 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -857,6 +857,8 @@ static bool do_helper_env_X_tb(DisasContext *ctx, arg_X_tb
*a,
TRANS(XSCVUQQP, do_helper_env_X_tb, gen_helper_XSCVUQQP)
TRANS(XSCVSQQP, do_helper_env_X_tb, gen_helper_XSCVSQQP)
+TRANS(XSCVQPUQZ, do_helper_env_X_tb, gen_helper_XSCVQPUQZ)
+TRANS(XSCVQPSQZ, do_helper_env_X_tb, gen_helper_XSCVQPSQZ)
#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
static void gen_##name(DisasContext *ctx) \
--
2.35.1
[PULL 05/23] ppc/pnv: Remove PnvOCC::psi link
From: Cédric Le Goater
Use an anonymous output GPIO line to connect the OCC device with the
PSIHB device and raise the appropriate PSI IRQ line depending on the
processor model.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Message-Id: <20220323072846.1780212-4-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pnv.c | 12 ++--
hw/ppc/pnv_occ.c | 16
include/hw/ppc/pnv_occ.h | 7 ++-
3 files changed, 12 insertions(+), 23 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 3469432fbf..7c08a78d6c 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1253,12 +1253,12 @@ static void pnv_chip_power8_realize(DeviceState *dev,
Error **errp)
}
/* Create the simplified OCC model */
-object_property_set_link(OBJECT(>occ), "psi", OBJECT(>psi),
- _abort);
if (!qdev_realize(DEVICE(>occ), NULL, errp)) {
return;
}
pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, >occ.xscom_regs);
+qdev_connect_gpio_out(DEVICE(>occ), 0,
+ qdev_get_gpio_in(DEVICE(>psi),
PSIHB_IRQ_OCC));
/* OCC SRAM model */
memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
@@ -1528,12 +1528,12 @@ static void pnv_chip_power9_realize(DeviceState *dev,
Error **errp)
(uint64_t) PNV9_LPCM_BASE(chip));
/* Create the simplified OCC model */
-object_property_set_link(OBJECT(>occ), "psi", OBJECT(>psi),
- _abort);
if (!qdev_realize(DEVICE(>occ), NULL, errp)) {
return;
}
pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, >occ.xscom_regs);
+qdev_connect_gpio_out(DEVICE(>occ), 0, qdev_get_gpio_in(
+ DEVICE(>psi), PSIHB9_IRQ_OCC));
/* OCC SRAM model */
memory_region_add_subregion(get_system_memory(),
PNV9_OCC_SENSOR_BASE(chip),
@@ -1731,13 +1731,13 @@ static void pnv_chip_power10_realize(DeviceState *dev,
Error **errp)
(uint64_t) PNV10_LPCM_BASE(chip));
/* Create the simplified OCC model */
-object_property_set_link(OBJECT(>occ), "psi", OBJECT(>psi),
- _abort);
if (!qdev_realize(DEVICE(>occ), NULL, errp)) {
return;
}
pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
>occ.xscom_regs);
+qdev_connect_gpio_out(DEVICE(>occ), 0, qdev_get_gpio_in(
+ DEVICE(>psi), PSIHB9_IRQ_OCC));
/* OCC SRAM model */
memory_region_add_subregion(get_system_memory(),
diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
index 4ed66f5e1f..9fa6d91d31 100644
--- a/hw/ppc/pnv_occ.c
+++ b/hw/ppc/pnv_occ.c
@@ -21,6 +21,7 @@
#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
+#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_xscom.h"
@@ -51,13 +52,12 @@
static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val)
{
bool irq_state;
-PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
val &= 0xull;
occ->occmisc = val;
irq_state = !!(val >> 63);
-pnv_psi_irq_set(occ->psi, poc->psi_irq, irq_state);
+qemu_set_irq(occ->psi_irq, irq_state);
}
static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr,
@@ -168,7 +168,6 @@ static void pnv_occ_power8_class_init(ObjectClass *klass,
void *data)
poc->xscom_size = PNV_XSCOM_OCC_SIZE;
poc->xscom_ops = _occ_power8_xscom_ops;
-poc->psi_irq = PSIHB_IRQ_OCC;
}
static const TypeInfo pnv_occ_power8_type_info = {
@@ -241,7 +240,6 @@ static void pnv_occ_power9_class_init(ObjectClass *klass,
void *data)
dc->desc = "PowerNV OCC Controller (POWER9)";
poc->xscom_size = PNV9_XSCOM_OCC_SIZE;
poc->xscom_ops = _occ_power9_xscom_ops;
-poc->psi_irq = PSIHB9_IRQ_OCC;
}
static const TypeInfo pnv_occ_power9_type_info = {
@@ -269,8 +267,6 @@ static void pnv_occ_realize(DeviceState *dev, Error **errp)
PnvOCC *occ = PNV_OCC(dev);
PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
-assert(occ->psi);
-
occ->occmisc = 0;
/* XScom region for OCC registers */
@@ -281,12 +277,9 @@ static void pnv_occ_realize(DeviceState *dev, Error **errp)
memory_region_init_io(>sram_regs, OBJECT(dev), _occ_sram_ops,
occ, "occ-common-area",
PNV_OCC_SENSOR_DATA_BLOCK_SIZE);
-}
-static Property pnv_occ_properties[] = {
-DEFINE_PROP_LINK("psi", PnvOCC, psi, TYPE_PNV_PSI, PnvPsi *),
-DEFINE_PROP_END_OF_LIST(),
-};
+qdev_init_gpio_out(DEVICE(dev), >psi_irq, 1);
+}
static void pnv_occ_class_init(ObjectClass *klass, void *data)
{
@@ -294,7 +287,6 @@ static void pnv_occ_class_init(ObjectClass *klass, void
*data)
dc->realize = pnv_occ_realize;
dc->desc = "PowerNV OCC Controller";
-
[PULL 15/23] softfloat: add float128_to_int128
From: Matheus Ferst
Implements float128_to_int128 based on parts_float_to_int logic.
Signed-off-by: Matheus Ferst
Reviewed-by: Richard Henderson
Message-Id: <20220330175932.6995-7-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza
---
fpu/softfloat.c | 64 +
include/fpu/softfloat.h | 2 ++
include/qemu/int128.h | 2 ++
3 files changed, 68 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index ce21b64e4f..5e2cf20448 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -3154,6 +3154,60 @@ static int64_t float128_to_int64_scalbn(float128 a,
FloatRoundMode rmode,
return parts_float_to_sint(, rmode, scale, INT64_MIN, INT64_MAX, s);
}
+static Int128 float128_to_int128_scalbn(float128 a, FloatRoundMode rmode,
+int scale, float_status *s)
+{
+int flags = 0;
+Int128 r;
+FloatParts128 p;
+
+float128_unpack_canonical(, a, s);
+
+switch (p.cls) {
+case float_class_snan:
+flags |= float_flag_invalid_snan;
+/* fall through */
+case float_class_qnan:
+flags |= float_flag_invalid;
+r = UINT128_MAX;
+break;
+
+case float_class_inf:
+flags = float_flag_invalid | float_flag_invalid_cvti;
+r = p.sign ? INT128_MIN : INT128_MAX;
+break;
+
+case float_class_zero:
+return int128_zero();
+
+case float_class_normal:
+if (parts_round_to_int_normal(, rmode, scale, 128 - 2)) {
+flags = float_flag_inexact;
+}
+
+if (p.exp < 127) {
+int shift = 127 - p.exp;
+r = int128_urshift(int128_make128(p.frac_lo, p.frac_hi), shift);
+if (p.sign) {
+r = int128_neg(r);
+}
+} else if (p.exp == 127 && p.sign && p.frac_lo == 0 &&
+ p.frac_hi == DECOMPOSED_IMPLICIT_BIT) {
+r = INT128_MIN;
+} else {
+flags = float_flag_invalid | float_flag_invalid_cvti;
+r = p.sign ? INT128_MIN : INT128_MAX;
+}
+break;
+
+default:
+g_assert_not_reached();
+}
+
+float_raise(flags, s);
+return r;
+}
+
static int32_t floatx80_to_int32_scalbn(floatx80 a, FloatRoundMode rmode,
int scale, float_status *s)
{
@@ -3236,6 +3290,11 @@ int64_t float128_to_int64(float128 a, float_status *s)
return float128_to_int64_scalbn(a, s->float_rounding_mode, 0, s);
}
+Int128 float128_to_int128(float128 a, float_status *s)
+{
+return float128_to_int128_scalbn(a, s->float_rounding_mode, 0, s);
+}
+
int32_t floatx80_to_int32(floatx80 a, float_status *s)
{
return floatx80_to_int32_scalbn(a, s->float_rounding_mode, 0, s);
@@ -3301,6 +3360,11 @@ int64_t float128_to_int64_round_to_zero(float128 a,
float_status *s)
return float128_to_int64_scalbn(a, float_round_to_zero, 0, s);
}
+Int128 float128_to_int128_round_to_zero(float128 a, float_status *s)
+{
+return float128_to_int128_scalbn(a, float_round_to_zero, 0, s);
+}
+
int32_t floatx80_to_int32_round_to_zero(floatx80 a, float_status *s)
{
return floatx80_to_int32_scalbn(a, float_round_to_zero, 0, s);
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 6cfe9ee474..3dcf20e3a2 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -1204,7 +1204,9 @@ floatx80 floatx80_default_nan(float_status *status);
int32_t float128_to_int32(float128, float_status *status);
int32_t float128_to_int32_round_to_zero(float128, float_status *status);
int64_t float128_to_int64(float128, float_status *status);
+Int128 float128_to_int128(float128, float_status *status);
int64_t float128_to_int64_round_to_zero(float128, float_status *status);
+Int128 float128_to_int128_round_to_zero(float128, float_status *status);
uint64_t float128_to_uint64(float128, float_status *status);
Int128 float128_to_uint128(float128, float_status *status);
uint64_t float128_to_uint64_round_to_zero(float128, float_status *status);
diff --git a/include/qemu/int128.h b/include/qemu/int128.h
index 1f82918c73..ef71f56e3f 100644
--- a/include/qemu/int128.h
+++ b/include/qemu/int128.h
@@ -431,5 +431,7 @@ static inline void bswap128s(Int128 *s)
}
#define UINT128_MAX int128_make128(~0LL, ~0LL)
+#define INT128_MAX int128_make128(UINT64_MAX, INT64_MAX)
+#define INT128_MIN int128_make128(0, INT64_MIN)
#endif /* INT128_H */
--
2.35.1
[PULL 21/23] ppc/pnv: Remove LSI on the PCIE host bridge
From: Frederic Barrat The phb3/phb4/phb5 root ports inherit from the default PCIE root port implementation, which requests a LSI interrupt (#INTA). On real hardware (POWER8/POWER9/POWER10), there is no such LSI. This patch corrects it so that it matches the hardware. As a consequence, the device tree previously generated was bogus, as the root bridge LSI was not properly mapped. On some implementation (powernv9), it was leading to inconsistent interrupt controller (xive) data. With this patch, it is now clean. Signed-off-by: Frederic Barrat Reviewed-by: Daniel Henrique Barboza Message-Id: <20220408131303.147840-3-fbar...@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb3.c | 1 + hw/pci-host/pnv_phb4.c | 1 + 2 files changed, 2 insertions(+) diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index 4e68ad4f03..3f03467dde 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -1161,6 +1161,7 @@ static void pnv_phb3_root_port_realize(DeviceState *dev, Error **errp) error_propagate(errp, local_err); return; } +pci_config_set_interrupt_pin(pci->config, 0); } static void pnv_phb3_root_port_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 3c4c2dace0..13ba9e45d8 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1771,6 +1771,7 @@ static void pnv_phb4_root_port_reset(DeviceState *dev) pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1); pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */ pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0x); +pci_config_set_interrupt_pin(conf, 0); } static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp) -- 2.35.1
[PULL 10/23] target/ppc: Improve KVM hypercall trace
From: Fabiano Rosas Before: kvm_handle_papr_hcall handle PAPR hypercall kvm_handle_papr_hcall handle PAPR hypercall kvm_handle_papr_hcall handle PAPR hypercall kvm_handle_papr_hcall handle PAPR hypercall kvm_handle_papr_hcall handle PAPR hypercall kvm_handle_papr_hcall handle PAPR hypercall After: kvm_handle_papr_hcall 0x3a8 kvm_handle_papr_hcall 0x3ac kvm_handle_papr_hcall 0x108 kvm_handle_papr_hcall 0x104 kvm_handle_papr_hcall 0x104 kvm_handle_papr_hcall 0x108 Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Reviewed-by: Daniel Henrique Barboza Message-Id: <20220325223316.276494-1-faro...@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza --- target/ppc/kvm.c| 2 +- target/ppc/trace-events | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index f905a2af17..a3c31b4e48 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -1680,7 +1680,7 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) break; #if defined(TARGET_PPC64) case KVM_EXIT_PAPR_HCALL: -trace_kvm_handle_papr_hcall(); +trace_kvm_handle_papr_hcall(run->papr_hcall.nr); run->papr_hcall.ret = spapr_hypercall(cpu, run->papr_hcall.nr, run->papr_hcall.args); diff --git a/target/ppc/trace-events b/target/ppc/trace-events index 53b107f56e..a79f1b4370 100644 --- a/target/ppc/trace-events +++ b/target/ppc/trace-events @@ -23,7 +23,7 @@ kvm_failed_get_vpa(void) "Warning: Unable to get VPA information from KVM" kvm_handle_dcr_write(void) "handle dcr write" kvm_handle_dcr_read(void) "handle dcr read" kvm_handle_halt(void) "handle halt" -kvm_handle_papr_hcall(void) "handle PAPR hypercall" +kvm_handle_papr_hcall(uint64_t hcall) "0x%" PRIx64 kvm_handle_epr(void) "handle epr" kvm_handle_watchdog_expiry(void) "handle watchdog expiry" kvm_handle_debug_exception(void) "handle debug exception" -- 2.35.1
[PULL 11/23] qemu/int128: add int128_urshift
From: Matheus Ferst
Implement an unsigned right shift for Int128 values and add the same
tests cases of int128_rshift in the unit test.
Signed-off-by: Matheus Ferst
Reviewed-by: Richard Henderson
Message-Id: <20220330175932.6995-3-matheus.fe...@eldorado.org.br>
[danielhb: fixed long lines in test_urshift()]
Signed-off-by: Daniel Henrique Barboza
---
include/qemu/int128.h| 19 +++
tests/unit/test-int128.c | 50
2 files changed, 69 insertions(+)
diff --git a/include/qemu/int128.h b/include/qemu/int128.h
index 37e07fd6dd..1f82918c73 100644
--- a/include/qemu/int128.h
+++ b/include/qemu/int128.h
@@ -83,6 +83,11 @@ static inline Int128 int128_rshift(Int128 a, int n)
return a >> n;
}
+static inline Int128 int128_urshift(Int128 a, int n)
+{
+return (__uint128_t)a >> n;
+}
+
static inline Int128 int128_lshift(Int128 a, int n)
{
return a << n;
@@ -299,6 +304,20 @@ static inline Int128 int128_rshift(Int128 a, int n)
}
}
+static inline Int128 int128_urshift(Int128 a, int n)
+{
+uint64_t h = a.hi;
+if (!n) {
+return a;
+}
+h = h >> (n & 63);
+if (n >= 64) {
+return int128_make64(h);
+} else {
+return int128_make128((a.lo >> n) | ((uint64_t)a.hi << (64 - n)), h);
+}
+}
+
static inline Int128 int128_lshift(Int128 a, int n)
{
uint64_t l = a.lo << (n & 63);
diff --git a/tests/unit/test-int128.c b/tests/unit/test-int128.c
index b86a3c76e6..25db2455e8 100644
--- a/tests/unit/test-int128.c
+++ b/tests/unit/test-int128.c
@@ -206,6 +206,55 @@ static void test_rshift(void)
test_rshift_one(0xFFFE8000U, 0, 0xFFFEULL,
0x8000ULL);
}
+static void __attribute__((__noinline__)) ATTRIBUTE_NOCLONE
+test_urshift_one(uint32_t x, int n, uint64_t h, uint64_t l)
+{
+Int128 a = expand(x);
+Int128 r = int128_urshift(a, n);
+g_assert_cmpuint(int128_getlo(r), ==, l);
+g_assert_cmpuint(int128_gethi(r), ==, h);
+}
+
+static void test_urshift(void)
+{
+test_urshift_one(0x0001U, 64, 0xULL,
+ 0x0001ULL);
+test_urshift_one(0x8001U, 64, 0xULL,
+ 0x8001ULL);
+test_urshift_one(0x7FFEU, 64, 0xULL,
+ 0x7FFEULL);
+test_urshift_one(0xFFFEU, 64, 0xULL,
+ 0xFFFEULL);
+test_urshift_one(0x0001U, 60, 0xULL,
+ 0x0010ULL);
+test_urshift_one(0x8001U, 60, 0x0008ULL,
+ 0x0010ULL);
+test_urshift_one(0x00018000U, 60, 0xULL,
+ 0x0018ULL);
+test_urshift_one(0x80018000U, 60, 0x0008ULL,
+ 0x0018ULL);
+test_urshift_one(0x7FFEU, 60, 0x0007ULL,
+ 0xFFE0ULL);
+test_urshift_one(0xFFFEU, 60, 0x000FULL,
+ 0xFFE0ULL);
+test_urshift_one(0x7FFE8000U, 60, 0x0007ULL,
+ 0xFFE8ULL);
+test_urshift_one(0xFFFE8000U, 60, 0x000FULL,
+ 0xFFE8ULL);
+test_urshift_one(0x00018000U, 0, 0x0001ULL,
+ 0x8000ULL);
+test_urshift_one(0x80018000U, 0, 0x8001ULL,
+ 0x8000ULL);
+test_urshift_one(0x7FFEU, 0, 0x7FFEULL,
+ 0xULL);
+test_urshift_one(0xFFFEU, 0, 0xFFFEULL,
+ 0xULL);
+test_urshift_one(0x7FFE8000U, 0, 0x7FFEULL,
+ 0x8000ULL);
+test_urshift_one(0xFFFE8000U, 0, 0xFFFEULL,
+ 0x8000ULL);
+}
+
int main(int argc, char **argv)
{
g_test_init(, , NULL);
@@ -219,5 +268,6 @@ int main(int argc, char **argv)
g_test_add_func("/int128/int128_ge", test_ge);
g_test_add_func("/int128/int128_gt", test_gt);
g_test_add_func("/int128/int128_rshift", test_rshift);
+g_test_add_func("/int128/int128_urshift", test_urshift);
return g_test_run();
}
--
2.35.1
[PULL 09/23] spapr: Move nested KVM hypercalls under a TCG only config.
From: Fabiano Rosas
These are the spapr virtual hypervisor implementation of the nested
KVM API. They only make sense when running with TCG.
Signed-off-by: Fabiano Rosas
Reviewed-by: Nicholas Piggin
Message-Id: <20220325221113.255834-3-faro...@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/spapr_hcall.c | 26 --
1 file changed, 20 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 9b24db5e44..d761a7d0c3 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -1473,7 +1473,7 @@ target_ulong spapr_hypercall(PowerPCCPU *cpu,
target_ulong opcode,
return H_FUNCTION;
}
-/* TCG only */
+#ifdef CONFIG_TCG
#define PRTS_MASK 0x1f
static target_ulong h_set_ptbl(PowerPCCPU *cpu,
@@ -1800,18 +1800,35 @@ out_restore_l1:
spapr_cpu->nested_host_state = NULL;
}
-#ifdef CONFIG_TCG
+static void hypercall_register_nested(void)
+{
+spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl);
+spapr_register_hypercall(KVMPPC_H_ENTER_NESTED, h_enter_nested);
+spapr_register_hypercall(KVMPPC_H_TLB_INVALIDATE, h_tlb_invalidate);
+spapr_register_hypercall(KVMPPC_H_COPY_TOFROM_GUEST, h_copy_tofrom_guest);
+}
+
static void hypercall_register_softmmu(void)
{
/* DO NOTHING */
}
#else
+void spapr_exit_nested(PowerPCCPU *cpu, int excp)
+{
+g_assert_not_reached();
+}
+
static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
g_assert_not_reached();
}
+static void hypercall_register_nested(void)
+{
+/* DO NOTHING */
+}
+
static void hypercall_register_softmmu(void)
{
/* hcall-pft */
@@ -1881,10 +1898,7 @@ static void hypercall_register_types(void)
spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt);
-spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl);
-spapr_register_hypercall(KVMPPC_H_ENTER_NESTED, h_enter_nested);
-spapr_register_hypercall(KVMPPC_H_TLB_INVALIDATE, h_tlb_invalidate);
-spapr_register_hypercall(KVMPPC_H_COPY_TOFROM_GUEST, h_copy_tofrom_guest);
+hypercall_register_nested();
}
type_init(hypercall_register_types)
--
2.35.1
[PULL 16/23] target/ppc: implement xscv[su]qqp
From: Matheus Ferst
Implement the following PowerISA v3.1 instructions:
xscvsqqp: VSX Scalar Convert with round Signed Quadword to
Quad-Precision
xscvuqqp: VSX Scalar Convert with round Unsigned Quadword to
Quad-Precision format
Signed-off-by: Matheus Ferst
Reviewed-by: Richard Henderson
Message-Id: <20220330175932.6995-8-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/fpu_helper.c | 12
target/ppc/helper.h | 2 ++
target/ppc/insn32.decode| 5 +
target/ppc/translate/vsx-impl.c.inc | 20
4 files changed, 39 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 7e8be99cc0..97892afa95 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -3058,6 +3058,18 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt,
ppc_vsr_t *xb)\
VSX_CVT_INT_TO_FP2(xvcvsxdsp, int64, float32)
VSX_CVT_INT_TO_FP2(xvcvuxdsp, uint64, float32)
+#define VSX_CVT_INT128_TO_FP(op, tp)\
+void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb)\
+{ \
+helper_reset_fpstatus(env); \
+xt->f128 = tp##_to_float128(xb->s128, >fp_status); \
+helper_compute_fprf_float128(env, xt->f128);\
+do_float_check_status(env, GETPC());\
+}
+
+VSX_CVT_INT128_TO_FP(XSCVUQQP, uint128);
+VSX_CVT_INT128_TO_FP(XSCVSQQP, int128);
+
/*
* VSX_CVT_INT_TO_FP_VECTOR - VSX integer to floating point conversion
* op- instruction mnemonic
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 57da11c77e..7df0c01819 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -388,6 +388,8 @@ DEF_HELPER_4(xscvqpsdz, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscvqpswz, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscvqpudz, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscvqpuwz, void, env, i32, vsr, vsr)
+DEF_HELPER_3(XSCVUQQP, void, env, vsr, vsr)
+DEF_HELPER_3(XSCVSQQP, void, env, vsr, vsr)
DEF_HELPER_3(xscvhpdp, void, env, vsr, vsr)
DEF_HELPER_4(xscvsdqp, void, env, i32, vsr, vsr)
DEF_HELPER_3(xscvspdp, void, env, vsr, vsr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index ac2d3da9a7..6fb568c1fe 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -91,6 +91,9 @@
@X_tp_a_bp_rc .. 0 ra:5 0 .. rc:1 _rc
rt=%x_frtp rb=%x_frbp
+_tb rt rb
+@X_tb .. rt:5 . rb:5 .. . _tb
+
_tb_rcrt rb rc:bool
@X_tb_rc.. rt:5 . rb:5 .. rc:1 _tb_rc
@@ -692,6 +695,8 @@ XSCMPGTQP 11 . . . 0011100100 - @X
## VSX Binary Floating-Point Convert Instructions
XSCVQPDP11 . 10100 . 1101000100 . @X_tb_rc
+XSCVUQQP11 . 00011 . 1101000100 - @X_tb
+XSCVSQQP11 . 01011 . 1101000100 - @X_tb
XVCVBF16SPN 00 . 1 . 111011011 .. @XX2
XVCVSPBF16 00 . 10001 . 111011011 .. @XX2
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index 7181a672d8..bda681e65c 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -838,6 +838,26 @@ static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc
*a)
return true;
}
+static bool do_helper_env_X_tb(DisasContext *ctx, arg_X_tb *a,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr,
TCGv_ptr))
+{
+TCGv_ptr xt, xb;
+
+REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+REQUIRE_VSX(ctx);
+
+xt = gen_avr_ptr(a->rt);
+xb = gen_avr_ptr(a->rb);
+gen_helper(cpu_env, xt, xb);
+tcg_temp_free_ptr(xt);
+tcg_temp_free_ptr(xb);
+
+return true;
+}
+
+TRANS(XSCVUQQP, do_helper_env_X_tb, gen_helper_XSCVUQQP)
+TRANS(XSCVSQQP, do_helper_env_X_tb, gen_helper_XSCVSQQP)
+
#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
static void gen_##name(DisasContext *ctx) \
{ \
--
2.35.1
[PULL 04/23] ppc/pnv: Remove PnvLpcController::psi link
From: Cédric Le Goater
Create an anonymous output GPIO line to connect the LPC device with
the PSIHB device and raise the appropriate PSI IRQ line depending on
the processor model.
A temporary __pnv_psi_irq_set() routine is introduced to handle the
transition. It will be removed when all devices raising PSI interrupts
are converted to use GPIOs.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Message-Id: <20220323072846.1780212-3-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pnv.c | 18 --
hw/ppc/pnv_lpc.c | 19 ---
hw/ppc/pnv_psi.c | 10 ++
include/hw/ppc/pnv_lpc.h | 8 ++--
4 files changed, 28 insertions(+), 27 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index c5e48992d9..3469432fbf 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -614,24 +614,36 @@ static void pnv_reset(MachineState *machine)
static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
{
Pnv8Chip *chip8 = PNV8_CHIP(chip);
+qemu_irq irq = qdev_get_gpio_in(DEVICE(>psi), PSIHB_IRQ_EXTERNAL);
+
+qdev_connect_gpio_out(DEVICE(>lpc), 0, irq);
return pnv_lpc_isa_create(>lpc, true, errp);
}
static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
{
Pnv8Chip *chip8 = PNV8_CHIP(chip);
+qemu_irq irq = qdev_get_gpio_in(DEVICE(>psi), PSIHB_IRQ_LPC_I2C);
+
+qdev_connect_gpio_out(DEVICE(>lpc), 0, irq);
return pnv_lpc_isa_create(>lpc, false, errp);
}
static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
{
Pnv9Chip *chip9 = PNV9_CHIP(chip);
+qemu_irq irq = qdev_get_gpio_in(DEVICE(>psi), PSIHB9_IRQ_LPCHC);
+
+qdev_connect_gpio_out(DEVICE(>lpc), 0, irq);
return pnv_lpc_isa_create(>lpc, false, errp);
}
static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
{
Pnv10Chip *chip10 = PNV10_CHIP(chip);
+qemu_irq irq = qdev_get_gpio_in(DEVICE(>psi), PSIHB9_IRQ_LPCHC);
+
+qdev_connect_gpio_out(DEVICE(>lpc), 0, irq);
return pnv_lpc_isa_create(>lpc, false, errp);
}
@@ -1222,8 +1234,6 @@ static void pnv_chip_power8_realize(DeviceState *dev,
Error **errp)
_PSI(psi8)->xscom_regs);
/* Create LPC controller */
-object_property_set_link(OBJECT(>lpc), "psi", OBJECT(>psi),
- _abort);
qdev_realize(DEVICE(>lpc), NULL, _fatal);
pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, >lpc.xscom_regs);
@@ -1507,8 +1517,6 @@ static void pnv_chip_power9_realize(DeviceState *dev,
Error **errp)
_PSI(psi9)->xscom_regs);
/* LPC */
-object_property_set_link(OBJECT(>lpc), "psi", OBJECT(>psi),
- _abort);
if (!qdev_realize(DEVICE(>lpc), NULL, errp)) {
return;
}
@@ -1712,8 +1720,6 @@ static void pnv_chip_power10_realize(DeviceState *dev,
Error **errp)
_PSI(>psi)->xscom_regs);
/* LPC */
-object_property_set_link(OBJECT(>lpc), "psi",
- OBJECT(>psi), _abort);
if (!qdev_realize(DEVICE(>lpc), NULL, errp)) {
return;
}
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index bcbca3db97..ee890e7ab4 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -422,7 +422,6 @@ static const MemoryRegionOps pnv_lpc_mmio_ops = {
static void pnv_lpc_eval_irqs(PnvLpcController *lpc)
{
bool lpc_to_opb_irq = false;
-PnvLpcClass *plc = PNV_LPC_GET_CLASS(lpc);
/* Update LPC controller to OPB line */
if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) {
@@ -445,7 +444,7 @@ static void pnv_lpc_eval_irqs(PnvLpcController *lpc)
lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask;
/* Reflect the interrupt */
-pnv_psi_irq_set(lpc->psi, plc->psi_irq, lpc->opb_irq_stat != 0);
+qemu_set_irq(lpc->psi_irq, lpc->opb_irq_stat != 0);
}
static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size)
@@ -637,8 +636,6 @@ static void pnv_lpc_power8_class_init(ObjectClass *klass,
void *data)
xdc->dt_xscom = pnv_lpc_dt_xscom;
-plc->psi_irq = PSIHB_IRQ_LPC_I2C;
-
device_class_set_parent_realize(dc, pnv_lpc_power8_realize,
>parent_realize);
}
@@ -677,8 +674,6 @@ static void pnv_lpc_power9_class_init(ObjectClass *klass,
void *data)
dc->desc = "PowerNV LPC Controller POWER9";
-plc->psi_irq = PSIHB9_IRQ_LPCHC;
-
device_class_set_parent_realize(dc, pnv_lpc_power9_realize,
>parent_realize);
}
@@ -706,8 +701,6 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp)
{
PnvLpcController *lpc = PNV_LPC(dev);
-assert(lpc->psi);
-
/* Reg inits */
lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B;
@@ -746,12 +739,9 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp)
"lpc-hc",
[PULL 13/23] softfloat: add int128_to_float128
From: Matheus Ferst
Based on parts_sint_to_float, implements int128_to_float128 to convert a
signed 128-bit value received through an Int128 argument.
Signed-off-by: Matheus Ferst
Message-Id: <20220330175932.6995-5-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza
---
fpu/softfloat.c | 29 +
include/fpu/softfloat.h | 1 +
2 files changed, 30 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 57445b36e7..60b4702945 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -3780,6 +3780,35 @@ bfloat16 int16_to_bfloat16(int16_t a, float_status
*status)
return int64_to_bfloat16_scalbn(a, 0, status);
}
+float128 int128_to_float128(Int128 a, float_status *status)
+{
+FloatParts128 p = { };
+int shift;
+
+if (int128_nz(a)) {
+p.cls = float_class_normal;
+if (!int128_nonneg(a)) {
+p.sign = true;
+a = int128_neg(a);
+}
+
+shift = clz64(int128_gethi(a));
+if (shift == 64) {
+shift += clz64(int128_getlo(a));
+}
+
+p.exp = 127 - shift;
+a = int128_lshift(a, shift);
+
+p.frac_hi = int128_gethi(a);
+p.frac_lo = int128_getlo(a);
+} else {
+p.cls = float_class_zero;
+}
+
+return float128_round_pack_canonical(, status);
+}
+
float128 int64_to_float128(int64_t a, float_status *status)
{
FloatParts128 p;
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 8e026e5610..3994b7235d 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -183,6 +183,7 @@ floatx80 int64_to_floatx80(int64_t, float_status *status);
float128 int32_to_float128(int32_t, float_status *status);
float128 int64_to_float128(int64_t, float_status *status);
+float128 int128_to_float128(Int128, float_status *status);
float128 uint64_to_float128(uint64_t, float_status *status);
float128 uint128_to_float128(Int128, float_status *status);
--
2.35.1
[PULL 07/23] ppc/pnv: Remove useless checks in set_irq handlers
From: Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Message-Id: <20220323072846.1780212-6-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pnv_psi.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 950ecca405..98045ed3d2 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -219,11 +219,6 @@ static void pnv_psi_power8_set_irq(void *opaque, int irq,
int state)
uint32_t src;
bool masked;
-if (irq > PSIHB_IRQ_EXTERNAL) {
-qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
-return;
-}
-
xivr_reg = xivr_regs[irq];
stat_reg = stat_regs[irq];
@@ -813,11 +808,6 @@ static void pnv_psi_power9_set_irq(void *opaque, int irq,
int state)
PnvPsi *psi = opaque;
uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)];
-if (irq > PSIHB9_NUM_IRQS) {
-qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
-return;
-}
-
if (irq_method & PSIHB9_IRQ_METHOD) {
qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n");
return;
--
2.35.1
[PULL 03/23] ppc/pnv: Fix PSI IRQ definition
From: Cédric Le Goater
On HW, the PSI and FSP interrupt levels are muxed under the same
interrupt number. For coding reasons, an extra IRQ number was
introduced to index register values in an array. It increased the
count of IRQs which do not fit in the PSI IRQ range anymore.
The PSI and FSP interrupts should be modeled with an extra level of
GPIO lines but since QEMU does not support them, simply drop the extra
number to stay within the IRQ range.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Message-Id: <20220323072846.1780212-2-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pnv_psi.c | 9 +++--
include/hw/ppc/pnv_psi.h | 3 +--
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 466fb79798..c588a506c7 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -184,8 +184,7 @@ static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val)
/*
* FSP and PSI interrupts are muxed under the same number.
*/
-static const uint32_t xivr_regs[] = {
-[PSIHB_IRQ_PSI] = PSIHB_XSCOM_XIVR_FSP,
+static const uint32_t xivr_regs[PSI_NUM_INTERRUPTS] = {
[PSIHB_IRQ_FSP] = PSIHB_XSCOM_XIVR_FSP,
[PSIHB_IRQ_OCC] = PSIHB_XSCOM_XIVR_OCC,
[PSIHB_IRQ_FSI] = PSIHB_XSCOM_XIVR_FSI,
@@ -194,8 +193,7 @@ static const uint32_t xivr_regs[] = {
[PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_XIVR_EXT,
};
-static const uint32_t stat_regs[] = {
-[PSIHB_IRQ_PSI] = PSIHB_XSCOM_CR,
+static const uint32_t stat_regs[PSI_NUM_INTERRUPTS] = {
[PSIHB_IRQ_FSP] = PSIHB_XSCOM_CR,
[PSIHB_IRQ_OCC] = PSIHB_XSCOM_IRQ_STAT,
[PSIHB_IRQ_FSI] = PSIHB_XSCOM_IRQ_STAT,
@@ -204,8 +202,7 @@ static const uint32_t stat_regs[] = {
[PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_IRQ_STAT,
};
-static const uint64_t stat_bits[] = {
-[PSIHB_IRQ_PSI] = PSIHB_CR_PSI_IRQ,
+static const uint64_t stat_bits[PSI_NUM_INTERRUPTS] = {
[PSIHB_IRQ_FSP] = PSIHB_CR_FSP_IRQ,
[PSIHB_IRQ_OCC] = PSIHB_IRQ_STAT_OCC,
[PSIHB_IRQ_FSI] = PSIHB_IRQ_STAT_FSI,
diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h
index eb841b34a1..6d9f8ce7c0 100644
--- a/include/hw/ppc/pnv_psi.h
+++ b/include/hw/ppc/pnv_psi.h
@@ -1,7 +1,7 @@
/*
* QEMU PowerPC PowerNV Processor Service Interface (PSI) model
*
- * Copyright (c) 2015-2017, IBM Corporation.
+ * Copyright (c) 2015-2022, IBM Corporation.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -85,7 +85,6 @@ struct PnvPsiClass {
/* The PSI and FSP interrupts are muxed on the same IRQ number */
typedef enum PnvPsiIrq {
-PSIHB_IRQ_PSI, /* internal use only */
PSIHB_IRQ_FSP, /* internal use only */
PSIHB_IRQ_OCC,
PSIHB_IRQ_FSI,
--
2.35.1
[PULL 12/23] softfloat: add uint128_to_float128
From: Matheus Ferst
Based on parts_uint_to_float, implements uint128_to_float128 to convert
an unsigned 128-bit value received through an Int128 argument.
Signed-off-by: Matheus Ferst
Reviewed-by: Richard Henderson
Message-Id: <20220330175932.6995-4-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza
---
fpu/softfloat.c | 25 +
include/fpu/softfloat.h | 2 ++
2 files changed, 27 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 7f524d4377..57445b36e7 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -3969,6 +3969,31 @@ float128 uint64_to_float128(uint64_t a, float_status
*status)
return float128_round_pack_canonical(, status);
}
+float128 uint128_to_float128(Int128 a, float_status *status)
+{
+FloatParts128 p = { };
+int shift;
+
+if (int128_nz(a)) {
+p.cls = float_class_normal;
+
+shift = clz64(int128_gethi(a));
+if (shift == 64) {
+shift += clz64(int128_getlo(a));
+}
+
+p.exp = 127 - shift;
+a = int128_lshift(a, shift);
+
+p.frac_hi = int128_gethi(a);
+p.frac_lo = int128_getlo(a);
+} else {
+p.cls = float_class_zero;
+}
+
+return float128_round_pack_canonical(, status);
+}
+
/*
* Minimum and maximum
*/
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index d34b2c44d2..8e026e5610 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -95,6 +95,7 @@ typedef enum {
#include "fpu/softfloat-types.h"
#include "fpu/softfloat-helpers.h"
+#include "qemu/int128.h"
/*
| Routine to raise any or all of the software IEC/IEEE floating-point
@@ -183,6 +184,7 @@ floatx80 int64_to_floatx80(int64_t, float_status *status);
float128 int32_to_float128(int32_t, float_status *status);
float128 int64_to_float128(int64_t, float_status *status);
float128 uint64_to_float128(uint64_t, float_status *status);
+float128 uint128_to_float128(Int128, float_status *status);
/*
| Software half-precision conversion routines.
--
2.35.1
[PULL 00/23] ppc queue
The following changes since commit 2d20a57453f6a206938cbbf77bed0b378c806c1f: Merge tag 'pull-fixes-for-7.1-200422-1' of https://github.com/stsquad/qemu into staging (2022-04-20 11:13:08 -0700) are available in the Git repository at: https://gitlab.com/danielhb/qemu.git tags/pull-ppc-20220420-2 for you to fetch changes up to 2d94af4b16c40758eee3a8591307ae173090d4ad: hw/ppc: change indentation to spaces from TABs (2022-04-20 18:00:30 -0300) ppc patch queue for 2022-04-20 First batch of ppc patches for QEMU 7.1: - skiboot firmware version bump - pseries: add 2M DDW pagesize - pseries: make virtual hypervisor code TCG only - powernv: introduce GPIO lines for PSIHB device - powernv: remove PCIE root bridge LSI - target/ppc: alternative softfloat 128 bit integer support - assorted fixes Alexey Kardashevskiy (2): ppc/spapr/ddw: Add 2M pagesize ppc/vof: Fix uninitialized string tracing Bernhard Beschow (1): hw/ppc/ppc405_boards: Initialize g_autofree pointer Cédric Le Goater (5): ppc/pnv: Fix PSI IRQ definition ppc/pnv: Remove PnvLpcController::psi link ppc/pnv: Remove PnvOCC::psi link ppc/pnv: Remove PnvPsiClas::irq_set ppc/pnv: Remove useless checks in set_irq handlers Fabiano Rosas (3): spapr: Move hypercall_register_softmmu spapr: Move nested KVM hypercalls under a TCG only config. target/ppc: Improve KVM hypercall trace Frederic Barrat (3): pcie: Don't try triggering a LSI when not defined ppc/pnv: Remove LSI on the PCIE host bridge target/ppc: Add two missing register callbacks on POWER10 Guo Zhi (1): hw/ppc: change indentation to spaces from TABs Joel Stanley (1): ppc/pnv: Update skiboot to v7.0 Matheus Ferst (7): qemu/int128: add int128_urshift softfloat: add uint128_to_float128 softfloat: add int128_to_float128 softfloat: add float128_to_uint128 softfloat: add float128_to_int128 target/ppc: implement xscv[su]qqp target/ppc: implement xscvqp[su]qz fpu/softfloat.c | 183 hw/pci-host/pnv_phb3.c | 1 + hw/pci-host/pnv_phb4.c | 1 + hw/pci/pcie.c | 5 +- hw/pci/pcie_aer.c | 2 +- hw/ppc/pnv.c| 30 +++--- hw/ppc/pnv_lpc.c| 19 +--- hw/ppc/pnv_occ.c| 16 +--- hw/ppc/pnv_psi.c| 36 +++ hw/ppc/ppc405_boards.c | 4 +- hw/ppc/ppc440_bamboo.c | 6 +- hw/ppc/spapr_hcall.c| 74 +-- hw/ppc/spapr_rtas.c | 18 ++-- hw/ppc/spapr_rtas_ddw.c | 1 + hw/ppc/vof.c| 2 +- include/fpu/softfloat.h | 7 ++ include/hw/ppc/pnv_lpc.h| 8 +- include/hw/ppc/pnv_occ.h| 7 +- include/hw/ppc/pnv_psi.h| 7 +- include/hw/ppc/ppc.h| 10 +- include/hw/ppc/spapr.h | 1 + include/qemu/int128.h | 21 + pc-bios/skiboot.lid | Bin 2528128 -> 2527240 bytes roms/skiboot| 2 +- target/ppc/cpu_init.c | 2 + target/ppc/fpu_helper.c | 33 +++ target/ppc/helper.h | 4 + target/ppc/insn32.decode| 7 ++ target/ppc/kvm.c| 2 +- target/ppc/trace-events | 2 +- target/ppc/translate/vsx-impl.c.inc | 22 + tests/unit/test-int128.c| 50 ++ 32 files changed, 446 insertions(+), 137 deletions(-)
[PULL 02/23] ppc/spapr/ddw: Add 2M pagesize
From: Alexey Kardashevskiy
Recently the LoPAPR spec got a new 2MB pagesize to support in Dynamic DMA
Windows API (DDW), this adds the new flag.
Linux supports it since
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=38727311871
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Alexey Kardashevskiy
Message-Id: <20220321071945.918669-1-...@ozlabs.ru>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/spapr_rtas_ddw.c | 1 +
include/hw/ppc/spapr.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/hw/ppc/spapr_rtas_ddw.c b/hw/ppc/spapr_rtas_ddw.c
index 3e826e1308..13d339c807 100644
--- a/hw/ppc/spapr_rtas_ddw.c
+++ b/hw/ppc/spapr_rtas_ddw.c
@@ -72,6 +72,7 @@ static uint32_t spapr_page_mask_to_query_mask(uint64_t
page_mask)
const struct { int shift; uint32_t mask; } masks[] = {
{ 12, RTAS_DDW_PGSIZE_4K },
{ 16, RTAS_DDW_PGSIZE_64K },
+{ 21, RTAS_DDW_PGSIZE_2M },
{ 24, RTAS_DDW_PGSIZE_16M },
{ 25, RTAS_DDW_PGSIZE_32M },
{ 26, RTAS_DDW_PGSIZE_64M },
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index f5c33dcc86..14b01c3f59 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -745,6 +745,7 @@ void push_sregs_to_kvm_pr(SpaprMachineState *spapr);
#define RTAS_DDW_PGSIZE_128M 0x20
#define RTAS_DDW_PGSIZE_256M 0x40
#define RTAS_DDW_PGSIZE_16G 0x80
+#define RTAS_DDW_PGSIZE_2M 0x100
/* RTAS tokens */
#define RTAS_TOKEN_BASE 0x2000
--
2.35.1
Re: Future of libslirp in QEMU
Awesome, thanks. Apparently I'm not properly performing a date-sorted search on the list archives. I started here: https://lists.gnu.org/archive/html/qemu-devel/ Then entered "slirp" and searched with chronological order, but the latest entry is from 2020. What am I doing wrong? Thanks, //anders On Wed, Apr 20, 2022, at 2:21 PM, Daniel Henrique Barboza wrote: > > > On 4/20/22 16:08, Anders Pitman wrote: > > I noticed in the 7.0 changelog that libslirp might be removed as a > > submodule in the future. Since user networking is very important for my > > project, I'm wondering if this is simply an implementation detail, or if > > there are plans to eventually remove slirp support entirely from QEMU > > (which would be bad for me)? > > > > Is there somewhere I can read the discussion about this? I searched the > > mailing list archives but didn't see anything obvious. > > QEMU will still be supporting libslirp. The difference is that now QEMU will > be > using libslirp from the distro instead of packaging it itself. > > The relevant thread is here: > > https://lists.gnu.org/archive/html/qemu-devel/2022-04/msg00974.html > > > Thanks, > > > Daniel > >
Re: [PATCH v4 19/19] tests: Add postcopy preempt tests
On Wed, Apr 20, 2022 at 12:43:39PM +0100, Daniel P. Berrangé wrote:
> > static void test_baddest(void)
> > {
> > MigrateStart args = {
> > @@ -2176,6 +2219,12 @@ int main(int argc, char **argv)
> >
> > qtest_add_func("/migration/postcopy/unix", test_postcopy);
> > qtest_add_func("/migration/postcopy/recovery", test_postcopy_recovery);
> > +qtest_add_func("/migration/postcopy/preempt/unix",
> > test_postcopy_preempt);
> > +qtest_add_func("/migration/postcopy/preempt/recovery",
> > + test_postcopy_preempt_recovery);
> > +qtest_add_func("/migration/postcopy/preempt/tls",
> > test_postcopy_preempt_tls);
> > +qtest_add_func("/migration/postcopy/preempt/tls+recovery",
> > + test_postcopy_preempt_all);
>
> On test naming again I think we want these four tests to have names
>
> /migration/postcopy/preempt/plain
> /migration/postcopy/preempt/tls/psk
> /migration/postcopy/preempt/recovery/plain
> /migration/postcopy/preempt/recovery/tls/psk
Well to think it again, logically if we prefer to spell out tls/psk, then
we may also want to spell out preempt/unix because of the same reason..
Similarly to all the vanilla postcopy/* tests, where if we keep tls/psk,
then we should keep postcopy/unix rather than postcopy/plain.
But let's not bother much with it.. I'll apply all the changes above in the
new version.
Thanks a lot for reviewing the series,
--
Peter Xu
Re: [PATCH v4 18/19] tests: Add postcopy tls recovery migration test
On Wed, Apr 20, 2022 at 12:42:15PM +0100, Daniel P. Berrangé wrote:
> On Thu, Mar 31, 2022 at 11:08:56AM -0400, Peter Xu wrote:
> > It's easy to build this upon the postcopy tls test.
> >
> > Signed-off-by: Peter Xu
> > ---
> > tests/qtest/migration-test.c | 27 +--
> > 1 file changed, 21 insertions(+), 6 deletions(-)
> >
> > diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c
> > index 80c4244871..7288c64e97 100644
> > --- a/tests/qtest/migration-test.c
> > +++ b/tests/qtest/migration-test.c
> > @@ -1058,15 +1058,15 @@ static void test_postcopy_tls(void)
> > test_postcopy_common();
> > }
> >
> > -static void test_postcopy_recovery(void)
> > +static void test_postcopy_recovery_common(MigrateStart *args)
> > {
> > -MigrateStart args = {
> > -.hide_stderr = true,
> > -};
> > QTestState *from, *to;
> > g_autofree char *uri = NULL;
> >
> > -if (migrate_postcopy_prepare(, , )) {
> > +/* Always hide errors for postcopy recover tests since they're
> > expected */
> > +args->hide_stderr = true;
> > +
> > +if (migrate_postcopy_prepare(, , args)) {
> > return;
> > }
> >
> > @@ -1117,7 +1117,21 @@ static void test_postcopy_recovery(void)
> > /* Restore the postcopy bandwidth to unlimited */
> > migrate_set_parameter_int(from, "max-postcopy-bandwidth", 0);
> >
> > -migrate_postcopy_complete(from, to, );
> > +migrate_postcopy_complete(from, to, args);
> > +}
> > +
> > +static void test_postcopy_recovery(void)
> > +{
> > +MigrateStart args = { };
> > +
> > +test_postcopy_recovery_common();
> > +}
> > +
> > +static void test_postcopy_recovery_tls(void)
> > +{
> > +MigrateStart args = { .postcopy_tls = true };
> > +
> > +test_postcopy_recovery_common();
> > }
> >
> > static void test_baddest(void)
> > @@ -2164,6 +2178,7 @@ int main(int argc, char **argv)
> > qtest_add_func("/migration/postcopy/recovery", test_postcopy_recovery);
> > #ifdef CONFIG_GNUTLS
> > qtest_add_func("/migration/postcopy/tls", test_postcopy_tls);
> > +qtest_add_func("/migration/postcopy/tls/recovery",
> > test_postcopy_recovery_tls);
>
> It is important that a test name is *NOT* a prefix for another
> test name, as that makes it harder to selectively run individual
> tests with '-p' as it does a pattern match.
>
> Bearing in mind my comments on the previous patch, I think we want
>
> /migration/postcopy/recovery/plain
> /migration/postcopy/recovery/tls/psk
Again, I can try to take all the suggestions in the next version, but note
that there's no obvious reason on how we name them.. It's:
/XXX/Feature1
/XXX/Feature2
...
Now what we're saying is: /XXX/Feature1/Feature2 is better than
/XXX/Feature2/Feature1.
And IMHO that really does not matter..
To be strict, for features that are compatible between each other, the only
sane way to write them is:
/XXX/Feature1
/XXX/Feature2
/XXX/Feature1+Feature2
And we make sure there's an ordered list of features. But then we still
lose the ultimate goal of allowing us to specify one "-p something" to run
any tests that FeatureX is enabled. Sometimes we simply run a superset or
subset then it's good enough at least to me.
IOW, we may need something better than the path-form (-p) of qtest to
achieve what you wanted, IMHO.
Thanks,
--
Peter Xu
Re: Future of libslirp in QEMU
On 4/20/22 16:08, Anders Pitman wrote: I noticed in the 7.0 changelog that libslirp might be removed as a submodule in the future. Since user networking is very important for my project, I'm wondering if this is simply an implementation detail, or if there are plans to eventually remove slirp support entirely from QEMU (which would be bad for me)? Is there somewhere I can read the discussion about this? I searched the mailing list archives but didn't see anything obvious. QEMU will still be supporting libslirp. The difference is that now QEMU will be using libslirp from the distro instead of packaging it itself. The relevant thread is here: https://lists.gnu.org/archive/html/qemu-devel/2022-04/msg00974.html Thanks, Daniel
[PATCH v4 2/5] i386/pc: create pci-host qdev prior to pc_memory_init()
At the start of pc_memory_init() we usually pass a range of
0..UINT64_MAX as pci_memory, when really its 2G (i440fx) or
32G (q35). To get the real user value, we need to get pci-host
passed property for default pci_hole64_size. Thus to get that,
create the qdev prior to memory init to better make estimations
on max used/phys addr.
This is in preparation to determine that host-phys-bits are
enough and also for pci-hole64-size to be considered to relocate
ram-above-4g to be at 1T (on AMD platforms).
Signed-off-by: Joao Martins
---
hw/i386/pc_piix.c| 5 -
hw/i386/pc_q35.c | 6 +++---
hw/pci-host/i440fx.c | 3 +--
include/hw/pci-host/i440fx.h | 2 +-
4 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 4c185c72d014..8f985ff939cc 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -91,6 +91,7 @@ static void pc_init1(MachineState *machine,
MemoryRegion *pci_memory;
MemoryRegion *rom_memory;
ram_addr_t lowmem;
+DeviceState *i440fx_dev;
/*
* Calculate ram split, for memory below and above 4G. It's a bit
@@ -164,9 +165,11 @@ static void pc_init1(MachineState *machine,
pci_memory = g_new(MemoryRegion, 1);
memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
rom_memory = pci_memory;
+i440fx_dev = qdev_new(host_type);
} else {
pci_memory = NULL;
rom_memory = system_memory;
+i440fx_dev = NULL;
}
pc_guest_info_init(pcms);
@@ -199,7 +202,7 @@ static void pc_init1(MachineState *machine,
pci_bus = i440fx_init(host_type,
pci_type,
- _state,
+ i440fx_dev, _state,
system_memory, system_io, machine->ram_size,
x86ms->below_4g_mem_size,
x86ms->above_4g_mem_size,
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 302288342a91..62b85ad6bede 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -203,12 +203,12 @@ static void pc_q35_init(MachineState *machine)
pcms->smbios_entry_point_type);
}
-/* allocate ram and load rom/bios */
-pc_memory_init(pcms, get_system_memory(), rom_memory, _memory);
-
/* create pci host bus */
q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE));
+/* allocate ram and load rom/bios */
+pc_memory_init(pcms, get_system_memory(), rom_memory, _memory);
+
object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host));
object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM,
OBJECT(ram_memory), NULL);
diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c
index e08716142b6e..5c1bab5c58ed 100644
--- a/hw/pci-host/i440fx.c
+++ b/hw/pci-host/i440fx.c
@@ -238,6 +238,7 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
}
PCIBus *i440fx_init(const char *host_type, const char *pci_type,
+DeviceState *dev,
PCII440FXState **pi440fx_state,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
@@ -247,7 +248,6 @@ PCIBus *i440fx_init(const char *host_type, const char
*pci_type,
MemoryRegion *pci_address_space,
MemoryRegion *ram_memory)
{
-DeviceState *dev;
PCIBus *b;
PCIDevice *d;
PCIHostState *s;
@@ -255,7 +255,6 @@ PCIBus *i440fx_init(const char *host_type, const char
*pci_type,
unsigned i;
I440FXState *i440fx;
-dev = qdev_new(host_type);
s = PCI_HOST_BRIDGE(dev);
b = pci_root_bus_new(dev, NULL, pci_address_space,
address_space_io, 0, TYPE_PCI_BUS);
diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h
index f068aaba8fda..c4710445e30a 100644
--- a/include/hw/pci-host/i440fx.h
+++ b/include/hw/pci-host/i440fx.h
@@ -36,7 +36,7 @@ struct PCII440FXState {
#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
PCIBus *i440fx_init(const char *host_type, const char *pci_type,
-PCII440FXState **pi440fx_state,
+DeviceState *dev, PCII440FXState **pi440fx_state,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
--
2.17.2
Re: [PATCH v4 16/19] migration: Enable TLS for preempt channel
On Wed, Apr 20, 2022 at 12:35:21PM +0100, Daniel P. Berrangé wrote:
> On Thu, Mar 31, 2022 at 11:08:54AM -0400, Peter Xu wrote:
> > This patch is based on the async preempt channel creation. It continues
> > wiring up the new channel with TLS handshake to destionation when enabled.
> >
> > Note that only the src QEMU needs such operation; the dest QEMU does not
> > need any change for TLS support due to the fact that all channels are
> > established synchronously there, so all the TLS magic is already properly
> > handled by migration_tls_channel_process_incoming().
> >
> > Signed-off-by: Peter Xu
> > ---
> > migration/postcopy-ram.c | 60 +++-
> > migration/trace-events | 1 +
> > 2 files changed, 54 insertions(+), 7 deletions(-)
> >
> > diff --git a/migration/postcopy-ram.c b/migration/postcopy-ram.c
> > index ab2a50cf45..f5ba176862 100644
> > --- a/migration/postcopy-ram.c
> > +++ b/migration/postcopy-ram.c
> > @@ -36,6 +36,7 @@
> > #include "socket.h"
> > #include "qemu-file-channel.h"
> > #include "yank_functions.h"
> > +#include "tls.h"
> >
> > /* Arbitrary limit on size of each discard command,
> > * keeps them around ~200 bytes
> > @@ -1552,15 +1553,15 @@ bool
> > postcopy_preempt_new_channel(MigrationIncomingState *mis, QEMUFile *file)
> > return true;
> > }
> >
> > +/*
> > + * Setup the postcopy preempt channel with the IOC. If ERROR is specified,
> > + * setup the error instead. This helper will free the ERROR if specified.
> > + */
> > static void
> > -postcopy_preempt_send_channel_new(QIOTask *task, gpointer opaque)
> > +postcopy_preempt_send_channel_done(MigrationState *s,
> > + QIOChannel *ioc, Error *local_err)
> > {
> > -MigrationState *s = opaque;
> > -QIOChannel *ioc = QIO_CHANNEL(qio_task_get_source(task));
> > -Error *local_err = NULL;
> > -
> > -if (qio_task_propagate_error(task, _err)) {
> > -/* Something wrong happened.. */
> > +if (local_err) {
> > migrate_set_error(s, local_err);
> > error_free(local_err);
> > } else {
> > @@ -1574,6 +1575,51 @@ postcopy_preempt_send_channel_new(QIOTask *task,
> > gpointer opaque)
> > * postcopy_qemufile_src to know whether it failed or not.
> > */
> > qemu_sem_post(>postcopy_qemufile_src_sem);
> > +}
> > +
> > +static void
> > +postcopy_preempt_tls_handshake(QIOTask *task, gpointer opaque)
> > +{
> > +MigrationState *s = opaque;
> > +QIOChannel *ioc = QIO_CHANNEL(qio_task_get_source(task));
>
> If using g_autoptr(QIOChannel) ioc = ...
New magic learned..
>
> > +Error *err = NULL;
>
> local_err is normal naming
OK.
>
> > +
> > +qio_task_propagate_error(task, );
> > +postcopy_preempt_send_channel_done(s, ioc, err);
> > +object_unref(OBJECT(ioc));
>
> ...not needed with g_autoptr
>
> > +}
> > +
> > +static void
> > +postcopy_preempt_send_channel_new(QIOTask *task, gpointer opaque)
> > +{
> > +MigrationState *s = opaque;
> > +QIOChannel *ioc = QIO_CHANNEL(qio_task_get_source(task));
>
> If you use g_autoptr(QIOChannel)
Will use it here too.
>
> > +QIOChannelTLS *tioc;
> > +Error *local_err = NULL;
> > +
> > +if (qio_task_propagate_error(task, _err)) {
> > +assert(local_err);
>
> I don't think we really need to add these asserts everywhere we
> handle a failure path do we ?
Maybe I'm just over-cautious, yeah let me drop those.
Thanks,
--
Peter Xu
[PATCH v4 1/5] hw/i386: add 4g boundary start to X86MachineState
Rather than hardcoding the 4G boundary everywhere, introduce a
X86MachineState property @above_4g_mem_start and use it
accordingly.
This is in preparation for relocating ram-above-4g to be
dynamically start at 1T on AMD platforms.
Signed-off-by: Joao Martins
---
hw/i386/acpi-build.c | 2 +-
hw/i386/pc.c | 9 +
hw/i386/sgx.c | 2 +-
hw/i386/x86.c | 1 +
include/hw/i386/x86.h | 3 +++
5 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index dcf6ece3d043..d8d4c4a7ffc7 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -2071,7 +2071,7 @@ build_srat(GArray *table_data, BIOSLinker *linker,
MachineState *machine)
build_srat_memory(table_data, mem_base, mem_len, i - 1,
MEM_AFFINITY_ENABLED);
}
-mem_base = 1ULL << 32;
+mem_base = x86ms->above_4g_mem_start;
mem_len = next_base - x86ms->below_4g_mem_size;
next_base = mem_base + mem_len;
}
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 23bba9d82c12..177d98164bdf 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -838,9 +838,10 @@ void pc_memory_init(PCMachineState *pcms,
machine->ram,
x86ms->below_4g_mem_size,
x86ms->above_4g_mem_size);
-memory_region_add_subregion(system_memory, 0x1ULL,
+memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start,
ram_above_4g);
-e820_add_entry(0x1ULL, x86ms->above_4g_mem_size, E820_RAM);
+e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size,
+ E820_RAM);
}
if (pcms->sgx_epc.size != 0) {
@@ -881,7 +882,7 @@ void pc_memory_init(PCMachineState *pcms,
machine->device_memory->base =
sgx_epc_above_4g_end(>sgx_epc);
} else {
machine->device_memory->base =
-0x1ULL + x86ms->above_4g_mem_size;
+x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
}
machine->device_memory->base =
@@ -973,7 +974,7 @@ uint64_t pc_pci_hole64_start(void)
} else if (pcms->sgx_epc.size != 0) {
hole64_start = sgx_epc_above_4g_end(>sgx_epc);
} else {
-hole64_start = 0x1ULL + x86ms->above_4g_mem_size;
+hole64_start = x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
}
return ROUND_UP(hole64_start, 1 * GiB);
diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c
index a44d66ba2afc..09d9c7c73d9f 100644
--- a/hw/i386/sgx.c
+++ b/hw/i386/sgx.c
@@ -295,7 +295,7 @@ void pc_machine_init_sgx_epc(PCMachineState *pcms)
return;
}
-sgx_epc->base = 0x1ULL + x86ms->above_4g_mem_size;
+sgx_epc->base = x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
memory_region_init(_epc->mr, OBJECT(pcms), "sgx-epc", UINT64_MAX);
memory_region_add_subregion(get_system_memory(), sgx_epc->base,
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index bb6727279097..2790250a0457 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -1305,6 +1305,7 @@ static void x86_machine_initfn(Object *obj)
x86ms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
x86ms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
x86ms->bus_lock_ratelimit = 0;
+x86ms->above_4g_mem_start = 0x1ULL;
}
static void x86_machine_class_init(ObjectClass *oc, void *data)
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
index 916cc325eeb1..86de493c39f0 100644
--- a/include/hw/i386/x86.h
+++ b/include/hw/i386/x86.h
@@ -56,6 +56,9 @@ struct X86MachineState {
/* RAM information (sizes, addresses, configuration): */
ram_addr_t below_4g_mem_size, above_4g_mem_size;
+/* Start address of the initial RAM above 4G */
+ram_addr_t above_4g_mem_start;
+
/* CPU and apic information: */
bool apic_xrupt_override;
unsigned pci_irq_mask;
--
2.17.2
Re: [RFC PATCH v3 2/5] ppc64: Fix semihosting on ppc64le
On 4/20/22 12:42, Peter Maydell wrote: On Mon, 18 Apr 2022 at 20:19, Leandro Lupori wrote: PPC64 CPUs can change its endian dynamically, so semihosting code must check its MSR at run time to determine if byte swapping is needed. Arm CPUs also change endianness dynamically, so why is this change PPC-specific ? I'm reasonably certain that we simply don't test armbe or aarch64_be semihosting. Leandro found this because qemu-system-ppc64 defaults to BE and qemu-system-aarch64 defaults to LE. r~
Re: [PATCH v4 15/19] migration: Export tls-[creds|hostname|authz] params to cmdline too
On Wed, Apr 20, 2022 at 12:13:07PM +0100, Daniel P. Berrangé wrote: > On Thu, Mar 31, 2022 at 11:08:53AM -0400, Peter Xu wrote: > > It's useful for specifying tls credentials all in the cmdline (along with > > the -object tls-creds-*), especially for debugging purpose. > > > > The trick here is we must remember to not free these fields again in the > > finalize() function of migration object, otherwise it'll cause double-free. > > > > The thing is when destroying an object, we'll first destroy the properties > > that bound to the object, then the object itself. To be explicit, when > > destroy the object in object_finalize() we have such sequence of > > operations: > > > > object_property_del_all(obj); > > object_deinit(obj, ti); > > > > So after this change the two fields are properly released already even > > before reaching the finalize() function but in object_property_del_all(), > > hence we don't need to free them anymore in finalize() or it's double-free. > > > I believe this is also fixing a small memory leak Yes I think so. I didn't even mention it since it's one global tiny variable and IIUC QEMU does have other similar cases of keeping vars around. As long as it'll not grow dynamically, then doesn't sound like a huge problem. But yeah, doing proper free is still ideal. So I'll add one more sentence to the commit message in next version. Thanks, -- Peter Xu
Re: [PATCH v4 14/19] migration: Add helpers to detect TLS capability
On Wed, Apr 20, 2022 at 12:10:14PM +0100, Daniel P. Berrangé wrote:
> On Thu, Mar 31, 2022 at 11:08:52AM -0400, Peter Xu wrote:
> > Add migrate_tls_enabled() to detect whether TLS is configured.
> >
> > Add migrate_channel_requires_tls() to detect whether the specific channel
> > requires TLS.
> >
> > No functional change intended.
> >
> > Signed-off-by: Peter Xu
> > ---
> > migration/channel.c | 10 ++
> > migration/migration.c | 17 +
> > migration/migration.h | 4
> > migration/multifd.c | 7 +--
> > 4 files changed, 24 insertions(+), 14 deletions(-)
> >
> > diff --git a/migration/channel.c b/migration/channel.c
> > index c6a8dcf1d7..36e59eaeec 100644
> > --- a/migration/channel.c
> > +++ b/migration/channel.c
> > @@ -38,10 +38,7 @@ void migration_channel_process_incoming(QIOChannel *ioc)
> > trace_migration_set_incoming_channel(
> > ioc, object_get_typename(OBJECT(ioc)));
> >
> > -if (s->parameters.tls_creds &&
> > -*s->parameters.tls_creds &&
> > -!object_dynamic_cast(OBJECT(ioc),
> > - TYPE_QIO_CHANNEL_TLS)) {
> > +if (migrate_channel_requires_tls(ioc)) {
> > migration_tls_channel_process_incoming(s, ioc, _err);
> > } else {
> > migration_ioc_register_yank(ioc);
> > @@ -71,10 +68,7 @@ void migration_channel_connect(MigrationState *s,
> > ioc, object_get_typename(OBJECT(ioc)), hostname, error);
> >
> > if (!error) {
> > -if (s->parameters.tls_creds &&
> > -*s->parameters.tls_creds &&
> > -!object_dynamic_cast(OBJECT(ioc),
> > - TYPE_QIO_CHANNEL_TLS)) {
> > +if (migrate_channel_requires_tls(ioc)) {
> > migration_tls_channel_connect(s, ioc, hostname, );
> >
> > if (!error) {
> > diff --git a/migration/migration.c b/migration/migration.c
> > index ee3df9e229..899084f993 100644
> > --- a/migration/migration.c
> > +++ b/migration/migration.c
> > @@ -49,6 +49,7 @@
> > #include "trace.h"
> > #include "exec/target_page.h"
> > #include "io/channel-buffer.h"
> > +#include "io/channel-tls.h"
> > #include "migration/colo.h"
> > #include "hw/boards.h"
> > #include "hw/qdev-properties.h"
> > @@ -4251,6 +4252,22 @@ void migration_global_dump(Monitor *mon)
> > ms->clear_bitmap_shift);
> > }
> >
> > +bool migrate_tls_enabled(void)
> > +{
> > +MigrationState *s = migrate_get_current();
> > +
> > +return s->parameters.tls_creds && *s->parameters.tls_creds;
> > +}
> > +
> > +bool migrate_channel_requires_tls(QIOChannel *ioc)
> > +{
> > +if (!migrate_tls_enabled()) {
>
> This is the only place migrate_tls_enabled is called. Does it
> really need to exist as an exported method, as opposed to
> inlining it here ?
IMHO the helper could help code readers to easier understand when TLS is
enabled, and it's not super obvious as TLS doesn't have a capability bit
bound to it. No strong opinions, though.
>
> > +return false;
> > +}
> > +
> > +return !object_dynamic_cast(OBJECT(ioc), TYPE_QIO_CHANNEL_TLS);
> > +}
> > +
> > #define DEFINE_PROP_MIG_CAP(name, x) \
> > DEFINE_PROP_BOOL(name, MigrationState, enabled_capabilities[x], false)
> >
> > diff --git a/migration/migration.h b/migration/migration.h
> > index 6ee520642f..8b9ad7fe31 100644
> > --- a/migration/migration.h
> > +++ b/migration/migration.h
> > @@ -436,6 +436,10 @@ bool migrate_use_events(void);
> > bool migrate_postcopy_blocktime(void);
> > bool migrate_background_snapshot(void);
> > bool migrate_postcopy_preempt(void);
> > +/* Whether TLS is enabled for migration? */
> > +bool migrate_tls_enabled(void);
> > +/* Whether the QIO channel requires further TLS handshake? */
> > +bool migrate_channel_requires_tls(QIOChannel *ioc);
>
> How about having it in tls.{c,h} as 'migration_tls_channel_enabled()' ?
I can do the movement, but the new name can be confusing when we read it in
the codes, it'll look like:
if (migration_tls_channel_enabled(ioc)) {
/* create the tls channel */
...
}
The thing is migration_tls_channel_enabled() on a TLS channel will return
false.. which seems to be against the gut feelings.
migrate_channel_requires_tls() feels better but maybe not so much..
Would migrate_channel_requires_tls_wrapper() be better (but longer..)?
Thanks,
--
Peter Xu
[PATCH v4 4/5] i386/pc: relocate 4g start to 1T where applicable
It is assumed that the whole GPA space is available to be DMA
addressable, within a given address space limit, expect for a
tiny region before the 4G. Since Linux v5.4, VFIO validates
whether the selected GPA is indeed valid i.e. not reserved by
IOMMU on behalf of some specific devices or platform-defined
restrictions, and thus failing the ioctl(VFIO_DMA_MAP) with
-EINVAL.
AMD systems with an IOMMU are examples of such platforms and
particularly may only have these ranges as allowed:
- fedf (0 .. 3.982G)
fef0 - 00fc (3.983G .. 1011.9G)
0100 - (1Tb.. 16Pb[*])
We already account for the 4G hole, albeit if the guest is big
enough we will fail to allocate a guest with >1010G due to the
~12G hole at the 1Tb boundary, reserved for HyperTransport (HT).
[*] there is another reserved region unrelated to HT that exists
in the 256T boundaru in Fam 17h according to Errata #1286,
documeted also in "Open-Source Register Reference for AMD Family
17h Processors (PUB)"
When creating the region above 4G, take into account that on AMD
platforms the HyperTransport range is reserved and hence it
cannot be used either as GPAs. On those cases rather than
establishing the start of ram-above-4g to be 4G, relocate instead
to 1Tb. See AMD IOMMU spec, section 2.1.2 "IOMMU Logical
Topology", for more information on the underlying restriction of
IOVAs.
After accounting for the 1Tb hole on AMD hosts, mtree should
look like:
-7fff (prio 0, i/o):
alias ram-below-4g @pc.ram -7fff
0100-01ff7fff (prio 0, i/o):
alias ram-above-4g @pc.ram 8000-00ff
If the relocation is done, we also add the the reserved HT
e820 range as reserved.
Default phys-bits on Qemu is TCG_PHYS_BITS (40) which is enough
to address 1Tb (0xff ). On AMD platforms, if a
ram-above-4g relocation may be desired and the CPU wasn't configured
with a big enough phys-bits, print an error message to the user
and do not make the relocation of the above-4g-region if phys-bits
is too low.
Suggested-by: Igor Mammedov
Signed-off-by: Joao Martins
---
hw/i386/pc.c | 111 +++
1 file changed, 111 insertions(+)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 8eaa32ee2106..aac32ba0bd02 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -803,6 +803,110 @@ void xen_load_linux(PCMachineState *pcms)
#define PC_ROM_ALIGN 0x800
#define PC_ROM_SIZE(PC_ROM_MAX - PC_ROM_MIN_VGA)
+/*
+ * AMD systems with an IOMMU have an additional hole close to the
+ * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
+ * on kernel version, VFIO may or may not let you DMA map those ranges.
+ * Starting Linux v5.4 we validate it, and can't create guests on AMD machines
+ * with certain memory sizes. It's also wrong to use those IOVA ranges
+ * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
+ * The ranges reserved for Hyper-Transport are:
+ *
+ * FD__h - FF__h
+ *
+ * The ranges represent the following:
+ *
+ * Base Address Top Address Use
+ *
+ * FD__h FD_F7FF_h Reserved interrupt address space
+ * FD_F800_h FD_F8FF_h Interrupt/EOI IntCtl
+ * FD_F900_h FD_F90F_h Legacy PIC IACK
+ * FD_F910_h FD_F91F_h System Management
+ * FD_F920_h FD_FAFF_h Reserved Page Tables
+ * FD_FB00_h FD_FBFF_h Address Translation
+ * FD_FC00_h FD_FDFF_h I/O Space
+ * FD_FE00_h FD__h Configuration
+ * FE__h FE_1FFF_h Extended Configuration/Device Messages
+ * FE_2000_h FF__h Reserved
+ *
+ * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology",
+ * Table 3: Special Address Controls (GPA) for more information.
+ */
+#define AMD_HT_START 0xfdUL
+#define AMD_HT_END 0xffUL
+#define AMD_ABOVE_1TB_START (AMD_HT_END + 1)
+#define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START)
+
+static hwaddr x86_max_phys_addr(PCMachineState *pcms,
+hwaddr above_4g_mem_start,
+uint64_t pci_hole64_size)
+{
+PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
+X86MachineState *x86ms = X86_MACHINE(pcms);
+MachineState *machine = MACHINE(pcms);
+ram_addr_t device_mem_size = 0;
+hwaddr base;
+
+if (!x86ms->above_4g_mem_size) {
+ /*
+* 32-bit pci hole goes from
+* end-of-low-ram (@below_4g_mem_size) to IOAPIC.
+*/
+return IO_APIC_DEFAULT_ADDRESS - 1;
+}
+
+if (pcmc->has_reserved_memory &&
+ (machine->ram_size < machine->maxram_size)) {
+device_mem_size = machine->maxram_size - machine->ram_size;
+}
+
+base = ROUND_UP(above_4g_mem_start + x86ms->above_4g_mem_size +
+pcms->sgx_epc.size, 1 *
Re: [RFC PATCH v3 2/5] ppc64: Fix semihosting on ppc64le
On Mon, 18 Apr 2022 at 20:19, Leandro Lupori wrote: > > PPC64 CPUs can change its endian dynamically, so semihosting code > must check its MSR at run time to determine if byte swapping is > needed. Arm CPUs also change endianness dynamically, so why is this change PPC-specific ? thanks -- PMM
Re: [PATCH v4 17/19] tests: Add postcopy tls migration test
On Wed, Apr 20, 2022 at 12:39:07PM +0100, Daniel P. Berrangé wrote:
> On Thu, Mar 31, 2022 at 11:08:55AM -0400, Peter Xu wrote:
> > We just added TLS tests for precopy but not postcopy. Add the
> > corresponding test for vanilla postcopy.
> >
> > Signed-off-by: Peter Xu
> > ---
> > tests/qtest/migration-test.c | 43 +++-
> > 1 file changed, 37 insertions(+), 6 deletions(-)
> >
> > diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c
> > index d9f444ea14..80c4244871 100644
> > --- a/tests/qtest/migration-test.c
> > +++ b/tests/qtest/migration-test.c
> > @@ -481,6 +481,10 @@ typedef struct {
> > bool only_target;
> > /* Use dirty ring if true; dirty logging otherwise */
> > bool use_dirty_ring;
> > +/* Whether use TLS channels for postcopy test? */
> > +bool postcopy_tls;
> > +/* Used only if postcopy_tls==true, to cache the data object */
> > +void *postcopy_tls_data;
> > const char *opts_source;
> > const char *opts_target;
> > } MigrateStart;
> > @@ -980,6 +984,10 @@ static int migrate_postcopy_prepare(QTestState
> > **from_ptr,
> > return -1;
> > }
> >
> > +if (args->postcopy_tls) {
> > +args->postcopy_tls_data = test_migrate_tls_psk_start_match(from,
> > to);
> > +}
> > +
> > migrate_set_capability(from, "postcopy-ram", true);
> > migrate_set_capability(to, "postcopy-ram", true);
> > migrate_set_capability(to, "postcopy-blocktime", true);
> > @@ -1004,7 +1012,8 @@ static int migrate_postcopy_prepare(QTestState
> > **from_ptr,
> > return 0;
> > }
> >
> > -static void migrate_postcopy_complete(QTestState *from, QTestState *to)
> > +static void migrate_postcopy_complete(QTestState *from, QTestState *to,
> > + MigrateStart *args)
> > {
> > wait_for_migration_complete(from);
> >
> > @@ -1015,19 +1024,38 @@ static void migrate_postcopy_complete(QTestState
> > *from, QTestState *to)
> > read_blocktime(to);
> > }
> >
> > +if (args->postcopy_tls) {
> > +assert(args->postcopy_tls_data);
> > +test_migrate_tls_psk_finish(from, to, args->postcopy_tls_data);
> > +args->postcopy_tls_data = NULL;
> > +}
> > +
> > test_migrate_end(from, to, true);
> > }
> >
> > -static void test_postcopy(void)
> > +static void test_postcopy_common(MigrateStart *args)
> > {
> > -MigrateStart args = {};
> > QTestState *from, *to;
> >
> > -if (migrate_postcopy_prepare(, , )) {
> > +if (migrate_postcopy_prepare(, , args)) {
> > return;
> > }
> > migrate_postcopy_start(from, to);
> > -migrate_postcopy_complete(from, to);
> > +migrate_postcopy_complete(from, to, args);
> > +}
> > +
> > +static void test_postcopy(void)
> > +{
> > +MigrateStart args = { };
> > +
> > +test_postcopy_common();
> > +}
> > +
> > +static void test_postcopy_tls(void)
>
> test_postcopy_tls_psk()
>
> > +{
> > +MigrateStart args = { .postcopy_tls = true };
> > +
> > +test_postcopy_common();
> > }
> >
> > static void test_postcopy_recovery(void)
> > @@ -1089,7 +1117,7 @@ static void test_postcopy_recovery(void)
> > /* Restore the postcopy bandwidth to unlimited */
> > migrate_set_parameter_int(from, "max-postcopy-bandwidth", 0);
> >
> > -migrate_postcopy_complete(from, to);
> > +migrate_postcopy_complete(from, to, );
> > }
> >
> > static void test_baddest(void)
> > @@ -2134,6 +2162,9 @@ int main(int argc, char **argv)
> >
> > qtest_add_func("/migration/postcopy/unix", test_postcopy);
>
> Rename this to /migration/postcopy/unix/plain
>
> > qtest_add_func("/migration/postcopy/recovery", test_postcopy_recovery);
> > +#ifdef CONFIG_GNUTLS
> > +qtest_add_func("/migration/postcopy/tls", test_postcopy_tls);
>
> And this to /migration/postcopy/unix/tls/psk so we match the precopy test
> naming convention I started
I can do all the renamings.
But note that I explicitly didn't add psk just because for postcopy it's
the same to use either psk or other ways to do encryption - we're testing
the tls channel paths not any specific type of TLS channels.
I wanted to use that trick to make sure people are aware we don't really
need other types of tls tests for postcopy, because the tls-type specific
code paths should have been covered in tls specific precopy tests.
I guess I'll add a comment showing that instead of using a vague naming.
Thanks,
--
Peter Xu
[PATCH v4 0/5] i386/pc: Fix creation of >= 1010G guests on AMD systems with IOMMU
v3[4] -> v4: (changes in patch 4 and 5 only) * Rebased to 7.1.0, hence move compat machine attribute to <= 7.0.0 versions * Check guest vCPU vendor rather than host CPU vendor (Michael Tsirkin) * Squash previous patch 5 into patch 4 to tie in the phys-bits check into the relocate-4g-start logic: We now error out if the phys-bits aren't enough on configurations that require above-4g ram relocation. (Michael Tsirkin) * Make the error message more explicit when phys-bits isn't enough to also mention: "cannot avoid AMD HT range" * Add comments inside x86_update_above_4g_mem_start() explaining the logic behind it. (Michael Tsirkin) * Tested on old guests old guests with Linux 2.6.32/3.10/4.14.35/4.1 based kernels alongside Win2008/2K12/2K16/2K19 on configs spanning 1T and 2T (Michael Tsirkin) Validated -numa topologies too as well as making sure qtests observe no regressions; Notes: * the machine attribute that enables this new logic (see last patch) is called ::enforce_valid_iova since the RFC. Let me know if folks think it is poorly named, and whether something a bit more obvious is preferred (e.g. ::amd_relocate_1t). * @mst one of the comments you said was to add "host checks" in vdpa/vfio devices. In discussion with Alex and you over the last version of the patches it seems that we weren't keen on making this device-specific or behind any machine property flags (besides machine-compat). Just to reiterate there, making sure we do the above-4g relocation requiring properly sized phys-bits and AMD as vCPU vendor (as this series) already ensures thtat this is going to be right for offending configuration with VDPA/VFIO device that might be configured/hotplugged. Unless you were thinking that somehow vfio/vdpa devices start poking into machine-specific details when we fail to relocate due to the lack of phys-bits? Otherwise Qemu, just doesn't have enough information to tell what's a valid IOVA or not, in which case kernel vhost-iotlb/vhost-vdpa is the one that needs fixing (as VFIO did in v5.4). --- This series lets Qemu spawn i386 guests with >= 1010G with VFIO, particularly when running on AMD systems with an IOMMU. Since Linux v5.4, VFIO validates whether the IOVA in DMA_MAP ioctl is valid and it will return -EINVAL on those cases. On x86, Intel hosts aren't particularly affected by this extra validation. But AMD systems with IOMMU have a hole in the 1TB boundary which is *reserved* for HyperTransport I/O addresses located here: FD__h - FF__h. See IOMMU manual [1], specifically section '2.1.2 IOMMU Logical Topology', Table 3 on what those addresses mean. VFIO DMA_MAP calls in this IOVA address range fall through this check and hence return -EINVAL, consequently failing the creation the guests bigger than 1010G. Example of the failure: qemu-system-x86_64: -device vfio-pci,host=:41:10.1,bootindex=-1: VFIO_MAP_DMA: -22 qemu-system-x86_64: -device vfio-pci,host=:41:10.1,bootindex=-1: vfio :41:10.1: failed to setup container for group 258: memory listener initialization failed: Region pc.ram: vfio_dma_map(0x55ba53e7a9d0, 0x1, 0xff3000, 0x7ed243e0) = -22 (Invalid argument) Prior to v5.4, we could map to these IOVAs *but* that's still not the right thing to do and could trigger certain IOMMU events (e.g. INVALID_DEVICE_REQUEST), or spurious guest VF failures from the resultant IOMMU target abort (see Errata 1155[2]) as documented on the links down below. This small series tries to address that by dealing with this AMD-specific 1Tb hole, but rather than dealing like the 4G hole, it instead relocates RAM above 4G to be above the 1T if the maximum RAM range crosses the HT reserved range. It is organized as following: patch 1: Introduce a @above_4g_mem_start which defaults to 4 GiB as starting address of the 4G boundary patches 2-3: Move pci-host qdev creation to be before pc_memory_init(), to get accessing to pci_hole64_size. The actual pci-host initialization is kept as is, only the qdev_new. patch 4: Change @above_4g_mem_start to 1TiB /if we are on AMD and the max possible address acrosses the HT region. Errors out if the phys-bits is too low, which is only the case for >=1010G configurations or something that crosses the HT region. patch 5: Ensure valid IOVAs only on new machine types, but not older ones (<= v7.0.0) The 'consequence' of this approach is that we may need more than the default phys-bits e.g. a guest with >1010G, will have most of its RAM after the 1TB address, consequently needing 41 phys-bits as opposed to the default of 40 (TCG_PHYS_BITS). Today there's already a precedent to depend on the user to pick the right value of phys-bits (regardless of this series), so we warn in case phys-bits aren't enough. Finally, CMOS loosing its meaning of the above 4G ram blocks, but it was mentioned over RFC that CMOS is only useful for very old seabios.
[PATCH v3 7/9] target/ppc: Implemented remaining vector divide extended
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
vdivesd: Vector Divide Extended Signed Doubleword
vdiveud: Vector Divide Extended Unsigned Doubleword
vdivesq: Vector Divide Extended Signed Quadword
vdiveuq: Vector Divide Extended Unsigned Quadword
Signed-off-by: Lucas Mateus Castro (alqotel)
Reviewed-by: Richard Henderson
---
target/ppc/helper.h | 4 ++
target/ppc/insn32.decode| 4 ++
target/ppc/int_helper.c | 64 +
target/ppc/translate/vmx-impl.c.inc | 4 ++
4 files changed, 76 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 4cfdf7b3ec..67ecff2c9a 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -173,6 +173,10 @@ DEF_HELPER_FLAGS_3(VMULOUH, TCG_CALL_NO_RWG, void, avr,
avr, avr)
DEF_HELPER_FLAGS_3(VMULOUW, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VDIVSQ, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VDIVUQ, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VDIVESD, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VDIVEUD, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VDIVESQ, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VDIVEUQ, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_3(vslo, void, avr, avr, avr)
DEF_HELPER_3(vsro, void, avr, avr, avr)
DEF_HELPER_3(vsrv, void, avr, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 8c115c9c60..3eb920ac76 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -715,3 +715,7 @@ VDIVUQ 000100 . . . 0001011@VX
VDIVESW 000100 . . . 01110001011@VX
VDIVEUW 000100 . . . 01010001011@VX
+VDIVESD 000100 . . . 0001011@VX
+VDIVEUD 000100 . . . 01011001011@VX
+VDIVESQ 000100 . . . 0111011@VX
+VDIVEUQ 000100 . . . 0101011@VX
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 55149c4fc7..27c8ce96ac 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1057,6 +1057,70 @@ void helper_VDIVUQ(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t
*b)
}
}
+void helper_VDIVESD(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b)
+{
+int i;
+int64_t high;
+uint64_t low;
+for (i = 0; i < 2; i++) {
+high = a->s64[i];
+low = 0;
+if (unlikely((high == INT64_MIN && b->s64[i] == -1) || !b->s64[i])) {
+t->s64[i] = a->s64[i]; /* Undefined behavior */
+} else {
+divs128(, , b->s64[i]);
+t->s64[i] = low;
+}
+}
+}
+
+void helper_VDIVEUD(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b)
+{
+int i;
+uint64_t high, low;
+for (i = 0; i < 2; i++) {
+high = a->u64[i];
+low = 0;
+if (unlikely(!b->u64[i])) {
+t->u64[i] = a->u64[i]; /* Undefined behavior */
+} else {
+divu128(, , b->u64[i]);
+t->u64[i] = low;
+}
+}
+}
+
+void helper_VDIVESQ(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b)
+{
+Int128 high, low;
+Int128 int128_min = int128_make128(0, INT64_MIN);
+Int128 neg1 = int128_makes64(-1);
+
+high = a->s128;
+low = int128_zero();
+if (unlikely(!int128_nz(b->s128) ||
+ (int128_eq(b->s128, neg1) && int128_eq(high, int128_min {
+t->s128 = a->s128; /* Undefined behavior */
+} else {
+divs256(, , b->s128);
+t->s128 = low;
+}
+}
+
+void helper_VDIVEUQ(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b)
+{
+Int128 high, low;
+
+high = a->s128;
+low = int128_zero();
+if (unlikely(!int128_nz(b->s128))) {
+t->s128 = a->s128; /* Undefined behavior */
+} else {
+divu256(, , b->s128);
+t->s128 = low;
+}
+}
+
void helper_VPERM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
ppc_avr_t result;
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index d1c1c6cf03..566a2e6d23 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -3365,6 +3365,10 @@ DIVU32(do_diveuw, do_diveu_i32)
TRANS_FLAGS2(ISA310, VDIVESW, do_vdiv_vmod, MO_32, do_divesw, NULL)
TRANS_FLAGS2(ISA310, VDIVEUW, do_vdiv_vmod, MO_32, do_diveuw, NULL)
+TRANS_FLAGS2(ISA310, VDIVESD, do_vx_helper, gen_helper_VDIVESD)
+TRANS_FLAGS2(ISA310, VDIVEUD, do_vx_helper, gen_helper_VDIVEUD)
+TRANS_FLAGS2(ISA310, VDIVESQ, do_vx_helper, gen_helper_VDIVESQ)
+TRANS_FLAGS2(ISA310, VDIVEUQ, do_vx_helper, gen_helper_VDIVEUQ)
#undef DIVS32
#undef DIVU32
--
2.31.1
[PATCH v3 4/9] target/ppc: Implemented vector divide extended word
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
vdivesw: Vector Divide Extended Signed Word
vdiveuw: Vector Divide Extended Unsigned Word
Signed-off-by: Lucas Mateus Castro (alqotel)
---
target/ppc/insn32.decode| 3 ++
target/ppc/translate/vmx-impl.c.inc | 48 +
2 files changed, 51 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 3a88a0b5bc..8c115c9c60 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -712,3 +712,6 @@ VDIVSD 000100 . . . 00111001011@VX
VDIVUD 000100 . . . 00011001011@VX
VDIVSQ 000100 . . . 0011011@VX
VDIVUQ 000100 . . . 0001011@VX
+
+VDIVESW 000100 . . . 01110001011@VX
+VDIVEUW 000100 . . . 01010001011@VX
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index cfd3c3ea6f..d1c1c6cf03 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -3318,6 +3318,54 @@ TRANS_FLAGS2(ISA310, VDIVUD, do_vdiv_vmod, MO_64, NULL,
do_divud)
TRANS_FLAGS2(ISA310, VDIVSQ, do_vx_helper, gen_helper_VDIVSQ)
TRANS_FLAGS2(ISA310, VDIVUQ, do_vx_helper, gen_helper_VDIVUQ)
+static void do_dives_i32(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b)
+{
+TCGv_i64 val1, val2;
+
+val1 = tcg_temp_new_i64();
+val2 = tcg_temp_new_i64();
+
+tcg_gen_ext_i32_i64(val1, a);
+tcg_gen_ext_i32_i64(val2, b);
+
+/* (a << 32)/b */
+tcg_gen_shli_i64(val1, val1, 32);
+tcg_gen_div_i64(val1, val1, val2);
+
+/* if quotient doesn't fit in 32 bits the result is undefined */
+tcg_gen_extrl_i64_i32(t, val1);
+
+tcg_temp_free_i64(val1);
+tcg_temp_free_i64(val2);
+}
+
+static void do_diveu_i32(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b)
+{
+TCGv_i64 val1, val2;
+
+val1 = tcg_temp_new_i64();
+val2 = tcg_temp_new_i64();
+
+tcg_gen_extu_i32_i64(val1, a);
+tcg_gen_extu_i32_i64(val2, b);
+
+/* (a << 32)/b */
+tcg_gen_shli_i64(val1, val1, 32);
+tcg_gen_divu_i64(val1, val1, val2);
+
+/* if quotient doesn't fit in 32 bits the result is undefined */
+tcg_gen_extrl_i64_i32(t, val1);
+
+tcg_temp_free_i64(val1);
+tcg_temp_free_i64(val2);
+}
+
+DIVS32(do_divesw, do_dives_i32)
+DIVU32(do_diveuw, do_diveu_i32)
+
+TRANS_FLAGS2(ISA310, VDIVESW, do_vdiv_vmod, MO_32, do_divesw, NULL)
+TRANS_FLAGS2(ISA310, VDIVEUW, do_vdiv_vmod, MO_32, do_diveuw, NULL)
+
#undef DIVS32
#undef DIVU32
#undef DIVS64
--
2.31.1
[PATCH v4 5/5] i386/pc: restrict AMD only enforcing of valid IOVAs to new machine type
The added enforcing is only relevant in the case of AMD where the
range right before the 1TB is restricted and cannot be DMA mapped
by the kernel consequently leading to IOMMU INVALID_DEVICE_REQUEST
or possibly other kinds of IOMMU events in the AMD IOMMU.
Although, there's a case where it may make sense to disable the
IOVA relocation/validation when migrating from a
non-valid-IOVA-aware qemu to one that supports it.
Relocating RAM regions to after the 1Tb hole has consequences for
guest ABI because we are changing the memory mapping, so make
sure that only new machine enforce but not older ones.
Signed-off-by: Joao Martins
---
hw/i386/pc.c | 7 +--
hw/i386/pc_piix.c| 2 ++
hw/i386/pc_q35.c | 2 ++
include/hw/i386/pc.h | 1 +
4 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index aac32ba0bd02..77d8747ef79b 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -869,6 +869,7 @@ static hwaddr x86_max_phys_addr(PCMachineState *pcms,
static void x86_update_above_4g_mem_start(PCMachineState *pcms,
uint64_t pci_hole64_size)
{
+PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
X86MachineState *x86ms = X86_MACHINE(pcms);
CPUX86State *env = _CPU(first_cpu)->env;
hwaddr start = x86ms->above_4g_mem_start;
@@ -877,9 +878,10 @@ static void x86_update_above_4g_mem_start(PCMachineState
*pcms,
/*
* The HyperTransport range close to the 1T boundary is unique to AMD
* hosts with IOMMUs enabled. Restrict the ram-above-4g relocation
- * to above 1T to AMD vCPUs only.
+ * to above 1T to AMD vCPUs only. @enforce_valid_iova is only false in
+ * older machine types (<= 7.0) for compatibility purposes.
*/
-if (!IS_AMD_CPU(env)) {
+if (!IS_AMD_CPU(env) || !pcmc->enforce_valid_iova) {
return;
}
@@ -1848,6 +1850,7 @@ static void pc_machine_class_init(ObjectClass *oc, void
*data)
pcmc->has_reserved_memory = true;
pcmc->kvmclock_enabled = true;
pcmc->enforce_aligned_dimm = true;
+pcmc->enforce_valid_iova = true;
/* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
* to be used at the moment, 32K should be enough for a while. */
pcmc->acpi_data_size = 0x2 + 0x8000;
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 00b4391e2e78..e12a40103be1 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -435,9 +435,11 @@ DEFINE_I440FX_MACHINE(v7_1, "pc-i440fx-7.1", NULL,
static void pc_i440fx_7_0_machine_options(MachineClass *m)
{
+PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_i440fx_7_1_machine_options(m);
m->alias = NULL;
m->is_default = false;
+pcmc->enforce_valid_iova = false;
compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len);
compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len);
}
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 233aaf5ac50b..e7ff131601ec 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -379,8 +379,10 @@ DEFINE_Q35_MACHINE(v7_1, "pc-q35-7.1", NULL,
static void pc_q35_7_0_machine_options(MachineClass *m)
{
+PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_q35_7_1_machine_options(m);
m->alias = NULL;
+pcmc->enforce_valid_iova = false;
compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len);
compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len);
}
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index b707d690a6d3..29b45a7847c4 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -119,6 +119,7 @@ struct PCMachineClass {
bool has_reserved_memory;
bool enforce_aligned_dimm;
bool broken_reserved_end;
+bool enforce_valid_iova;
/* generate legacy CPU hotplug AML */
bool legacy_cpu_hotplug;
--
2.17.2
[PATCH v3 6/9] host-utils: Implemented signed 256-by-128 division
From: "Lucas Mateus Castro (alqotel)"
Based on already existing QEMU implementation created a signed
256 bit by 128 bit division needed to implement the vector divide
extended signed quadword instruction from PowerISA 3.1
Signed-off-by: Lucas Mateus Castro (alqotel)
Reviewed-by: Richard Henderson
---
include/qemu/host-utils.h | 1 +
util/host-utils.c | 51 +++
2 files changed, 52 insertions(+)
diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h
index 9767af7573..bc743f5e32 100644
--- a/include/qemu/host-utils.h
+++ b/include/qemu/host-utils.h
@@ -851,4 +851,5 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1,
}
Int128 divu256(Int128 *plow, Int128 *phigh, Int128 divisor);
+Int128 divs256(Int128 *plow, Int128 *phigh, Int128 divisor);
#endif
diff --git a/util/host-utils.c b/util/host-utils.c
index 93dfb1b6ab..fb91bcba82 100644
--- a/util/host-utils.c
+++ b/util/host-utils.c
@@ -395,3 +395,54 @@ Int128 divu256(Int128 *plow, Int128 *phigh, Int128 divisor)
return rem;
}
}
+
+/*
+ * Signed 256-by-128 division.
+ * Returns quotient via plow and phigh.
+ * Also returns the remainder via the function return value.
+ */
+Int128 divs256(Int128 *plow, Int128 *phigh, Int128 divisor)
+{
+bool neg_quotient = false, neg_remainder = false;
+Int128 unsig_hi = *phigh, unsig_lo = *plow;
+Int128 rem;
+
+if (!int128_nonneg(*phigh)) {
+neg_quotient = !neg_quotient;
+neg_remainder = !neg_remainder;
+
+if (!int128_nz(unsig_lo)) {
+unsig_hi = int128_neg(unsig_hi);
+} else {
+unsig_hi = int128_not(unsig_hi);
+unsig_lo = int128_neg(unsig_lo);
+}
+}
+
+if (!int128_nonneg(divisor)) {
+neg_quotient = !neg_quotient;
+
+divisor = int128_neg(divisor);
+}
+
+rem = divu256(_lo, _hi, divisor);
+
+if (neg_quotient) {
+if (!int128_nz(unsig_lo)) {
+*phigh = int128_neg(unsig_hi);
+*plow = int128_zero();
+} else {
+*phigh = int128_not(unsig_hi);
+*plow = int128_neg(unsig_lo);
+}
+} else {
+*phigh = unsig_hi;
+*plow = unsig_lo;
+}
+
+if (neg_remainder) {
+return int128_neg(rem);
+} else {
+return rem;
+}
+}
--
2.31.1
[PATCH v3 9/9] target/ppc: Implemented vector module quadword
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
vmodsq: Vector Modulo Signed Quadword
vmoduq: Vector Modulo Unsigned Quadword
Signed-off-by: Lucas Mateus Castro (alqotel)
Reviewed-by: Richard Henderson
---
target/ppc/helper.h | 2 ++
target/ppc/insn32.decode| 2 ++
target/ppc/int_helper.c | 21 +
target/ppc/translate/vmx-impl.c.inc | 2 ++
4 files changed, 27 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 67ecff2c9a..881e03959a 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -177,6 +177,8 @@ DEF_HELPER_FLAGS_3(VDIVESD, TCG_CALL_NO_RWG, void, avr,
avr, avr)
DEF_HELPER_FLAGS_3(VDIVEUD, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VDIVESQ, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VDIVEUQ, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMODSQ, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMODUQ, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_3(vslo, void, avr, avr, avr)
DEF_HELPER_3(vsro, void, avr, avr, avr)
DEF_HELPER_3(vsrv, void, avr, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 36b42e41d2..b53efe1915 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -724,3 +724,5 @@ VMODSW 000100 . . . 0001011@VX
VMODUW 000100 . . . 11010001011@VX
VMODSD 000100 . . . 1001011@VX
VMODUD 000100 . . . 11011001011@VX
+VMODSQ 000100 . . . 1111011@VX
+VMODUQ 000100 . . . 1101011@VX
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 27c8ce96ac..fc4d887eeb 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1121,6 +1121,27 @@ void helper_VDIVEUQ(ppc_avr_t *t, ppc_avr_t *a,
ppc_avr_t *b)
}
}
+void helper_VMODSQ(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b)
+{
+Int128 neg1 = int128_makes64(-1);
+Int128 int128_min = int128_make128(0, INT64_MIN);
+if (likely(int128_nz(b->s128) &&
+ (int128_ne(a->s128, int128_min) || int128_ne(b->s128, neg1 {
+t->s128 = int128_rems(a->s128, b->s128);
+} else {
+t->s128 = int128_zero(); /* Undefined behavior */
+}
+}
+
+void helper_VMODUQ(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b)
+{
+if (likely(int128_nz(b->s128))) {
+t->s128 = int128_remu(a->s128, b->s128);
+} else {
+t->s128 = int128_zero(); /* Undefined behavior */
+}
+}
+
void helper_VPERM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
ppc_avr_t result;
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index 69f71dc216..07fe9c1c44 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -3379,6 +3379,8 @@ TRANS_FLAGS2(ISA310, VMODSW, do_vdiv_vmod, MO_32,
do_modsw , NULL)
TRANS_FLAGS2(ISA310, VMODUW, do_vdiv_vmod, MO_32, do_moduw, NULL)
TRANS_FLAGS2(ISA310, VMODSD, do_vdiv_vmod, MO_64, NULL, do_modsd)
TRANS_FLAGS2(ISA310, VMODUD, do_vdiv_vmod, MO_64, NULL, do_modud)
+TRANS_FLAGS2(ISA310, VMODSQ, do_vx_helper, gen_helper_VMODSQ)
+TRANS_FLAGS2(ISA310, VMODUQ, do_vx_helper, gen_helper_VMODUQ)
#undef DIVS32
#undef DIVU32
--
2.31.1
Re: [PATCH v4 04/19] migration: Move migrate_allow_multifd and helpers into migration.c
On Wed, Apr 20, 2022 at 11:41:30AM +0100, Daniel P. Berrangé wrote:
> On Thu, Mar 31, 2022 at 11:08:42AM -0400, Peter Xu wrote:
> > This variable, along with its helpers, is used to detect whether multiple
> > channel will be supported for migration. In follow up patches, there'll be
> > other capability that requires multi-channels. Hence move it outside
> > multifd
> > specific code and make it public. Meanwhile rename it from "multifd" to
> > "multi_channels" to show its real meaning.
>
> FWIW, I would generally suggest separating the rename from the code
> movement into distinct patches.
Okay. To still cherish Dave's R-b, I'll try to keep as-is this time, but
I'll remember it next time.
>
> >
> > Reviewed-by: Dr. David Alan Gilbert
> > Signed-off-by: Peter Xu
> > ---
> > migration/migration.c | 22 +-
> > migration/migration.h | 3 +++
> > migration/multifd.c | 19 ---
> > migration/multifd.h | 2 --
> > 4 files changed, 24 insertions(+), 22 deletions(-)
> >
> > diff --git a/migration/migration.c b/migration/migration.c
> > index 281d33326b..596d3d30b4 100644
> > --- a/migration/migration.c
> > +++ b/migration/migration.c
> > @@ -180,6 +180,18 @@ static int migration_maybe_pause(MigrationState *s,
> > int new_state);
> > static void migrate_fd_cancel(MigrationState *s);
> >
> > +static bool migrate_allow_multi_channels = true;
>
> This is a pre-existing thing, but I'm curious why we default this to
> 'true', when the first thing qemu_start_incoming_migration() and
> qmp_migrate() do, is to set it to 'false' and then selectively
> put it back to 'true'.
Agreed, FWICT it's not needed, it just doesn't hurt either.
>
>
> > static gint page_request_addr_cmp(gconstpointer ap, gconstpointer bp)
> > {
> > uintptr_t a = (uintptr_t) ap, b = (uintptr_t) bp;
> > @@ -469,12 +481,12 @@ static void qemu_start_incoming_migration(const char
> > *uri, Error **errp)
> > {
> > const char *p = NULL;
> >
> > -migrate_protocol_allow_multifd(false); /* reset it anyway */
> > +migrate_protocol_allow_multi_channels(false); /* reset it anyway */
> > qapi_event_send_migration(MIGRATION_STATUS_SETUP);
> > if (strstart(uri, "tcp:", ) ||
> > strstart(uri, "unix:", NULL) ||
> > strstart(uri, "vsock:", NULL)) {
> > -migrate_protocol_allow_multifd(true);
> > +migrate_protocol_allow_multi_channels(true);
> > socket_start_incoming_migration(p ? p : uri, errp);
>
>
>
> > @@ -2324,11 +2336,11 @@ void qmp_migrate(const char *uri, bool has_blk,
> > bool blk,
> > }
> > }
> >
> > -migrate_protocol_allow_multifd(false);
> > +migrate_protocol_allow_multi_channels(false);
> > if (strstart(uri, "tcp:", ) ||
> > strstart(uri, "unix:", NULL) ||
> > strstart(uri, "vsock:", NULL)) {
> > -migrate_protocol_allow_multifd(true);
> > +migrate_protocol_allow_multi_channels(true);
> > socket_start_outgoing_migration(s, p ? p : uri, _err);
> > #ifdef CONFIG_RDMA
> > } else if (strstart(uri, "rdma:", )) {
>
> Regardless of comments above
>
> Reviewed-by: Daniel P. Berrangé
Thanks,
--
Peter Xu
[PATCH v4 3/5] i386/pc: pass pci_hole64_size to pc_memory_init()
Use the pre-initialized pci-host qdev and fetch the
pci-hole64-size into pc_memory_init() newly added argument.
piix needs a bit of care given all the !pci_enabled()
and that the pci_hole64_size is private to i440fx.
This is in preparation to determine that host-phys-bits are
enough and for pci-hole64-size to be considered to relocate
ram-above-4g to be at 1T (on AMD platforms).
Signed-off-by: Joao Martins
---
hw/i386/pc.c | 3 ++-
hw/i386/pc_piix.c| 5 -
hw/i386/pc_q35.c | 8 +++-
hw/pci-host/i440fx.c | 7 +++
include/hw/i386/pc.h | 3 ++-
include/hw/pci-host/i440fx.h | 1 +
6 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 177d98164bdf..8eaa32ee2106 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -806,7 +806,8 @@ void xen_load_linux(PCMachineState *pcms)
void pc_memory_init(PCMachineState *pcms,
MemoryRegion *system_memory,
MemoryRegion *rom_memory,
-MemoryRegion **ram_memory)
+MemoryRegion **ram_memory,
+uint64_t pci_hole64_size)
{
int linux_boot, i;
MemoryRegion *option_rom_mr;
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 8f985ff939cc..00b4391e2e78 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -91,6 +91,7 @@ static void pc_init1(MachineState *machine,
MemoryRegion *pci_memory;
MemoryRegion *rom_memory;
ram_addr_t lowmem;
+uint64_t hole64_size;
DeviceState *i440fx_dev;
/*
@@ -166,10 +167,12 @@ static void pc_init1(MachineState *machine,
memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
rom_memory = pci_memory;
i440fx_dev = qdev_new(host_type);
+hole64_size = i440fx_pci_hole64_size(i440fx_dev);
} else {
pci_memory = NULL;
rom_memory = system_memory;
i440fx_dev = NULL;
+hole64_size = 0;
}
pc_guest_info_init(pcms);
@@ -186,7 +189,7 @@ static void pc_init1(MachineState *machine,
/* allocate ram and load rom/bios */
if (!xen_enabled()) {
pc_memory_init(pcms, system_memory,
- rom_memory, _memory);
+ rom_memory, _memory, hole64_size);
} else {
pc_system_flash_cleanup_unused(pcms);
if (machine->kernel_filename != NULL) {
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 62b85ad6bede..233aaf5ac50b 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -138,6 +138,7 @@ static void pc_q35_init(MachineState *machine)
MachineClass *mc = MACHINE_GET_CLASS(machine);
bool acpi_pcihp;
bool keep_pci_slot_hpc;
+uint64_t pci_hole64_size = 0;
/* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
* and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
@@ -206,8 +207,13 @@ static void pc_q35_init(MachineState *machine)
/* create pci host bus */
q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE));
+if (pcmc->pci_enabled) {
+pci_hole64_size = q35_host->mch.pci_hole64_size;
+}
+
/* allocate ram and load rom/bios */
-pc_memory_init(pcms, get_system_memory(), rom_memory, _memory);
+pc_memory_init(pcms, get_system_memory(), rom_memory, _memory,
+ pci_hole64_size);
object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host));
object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM,
diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c
index 5c1bab5c58ed..c5cc28250d5c 100644
--- a/hw/pci-host/i440fx.c
+++ b/hw/pci-host/i440fx.c
@@ -237,6 +237,13 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
}
}
+uint64_t i440fx_pci_hole64_size(DeviceState *i440fx_dev)
+{
+I440FXState *i440fx = I440FX_PCI_HOST_BRIDGE(i440fx_dev);
+
+return i440fx->pci_hole64_size;
+}
+
PCIBus *i440fx_init(const char *host_type, const char *pci_type,
DeviceState *dev,
PCII440FXState **pi440fx_state,
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 637367dc5fae..b707d690a6d3 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -160,7 +160,8 @@ void xen_load_linux(PCMachineState *pcms);
void pc_memory_init(PCMachineState *pcms,
MemoryRegion *system_memory,
MemoryRegion *rom_memory,
-MemoryRegion **ram_memory);
+MemoryRegion **ram_memory,
+uint64_t pci_hole64_size);
uint64_t pc_pci_hole64_start(void);
DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
void pc_basic_device_init(struct PCMachineState *pcms,
diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h
index c4710445e30a..1299d6a2b0e4 100644
--- a/include/hw/pci-host/i440fx.h
+++ b/include/hw/pci-host/i440fx.h
@@ -45,5 +45,6 @@ PCIBus *i440fx_init(const
[PATCH v3 0/9] VDIV/VMOD Implementation
From: "Lucas Mateus Castro (alqotel)" This patch series is an implementation of the vector divide, vector divide extended and vector modulo instructions from PowerISA 3.1 The first patch are Matheus' patch, used here since the divs256 and divu256 functions use int128_urshift. Patches without review: 2, 4, 5 and 8 v3 changes: - Divided DO_VDIV_VMOD macro in 4 different new macros - Turned TRANS_VDIV_VMOD into a function and the instructions are now implemented with the TRANS macro and do_vdiv_vmod function - Moved clz128 to int128.h v2 changes: - Dropped int128_lshift patch - Added missing int_min/-1 check - Changed invalid division to a division by 1 - Created new macro responsible for invalid division check (replacing DIV_VEC, REM_VEC and the check in dives_i32/diveu_i32) - Turned GVecGen3 array into single element Lucas Mateus Castro (alqotel) (8): target/ppc: Implemented vector divide instructions target/ppc: Implemented vector divide quadword target/ppc: Implemented vector divide extended word host-utils: Implemented unsigned 256-by-128 division host-utils: Implemented signed 256-by-128 division target/ppc: Implemented remaining vector divide extended target/ppc: Implemented vector module word/doubleword target/ppc: Implemented vector module quadword Matheus Ferst (1): qemu/int128: add int128_urshift include/qemu/host-utils.h | 3 + include/qemu/int128.h | 57 + target/ppc/helper.h | 8 ++ target/ppc/insn32.decode| 23 target/ppc/int_helper.c | 106 target/ppc/translate/vmx-impl.c.inc | 155 tests/unit/test-int128.c| 32 + util/host-utils.c | 180 8 files changed, 564 insertions(+) -- 2.31.1
[PATCH v3 8/9] target/ppc: Implemented vector module word/doubleword
From: "Lucas Mateus Castro (alqotel)" Implement the following PowerISA v3.1 instructions: vmodsw: Vector Modulo Signed Word vmoduw: Vector Modulo Unsigned Word vmodsd: Vector Modulo Signed Doubleword vmodud: Vector Modulo Unsigned Doubleword Signed-off-by: Lucas Mateus Castro (alqotel) --- target/ppc/insn32.decode| 5 + target/ppc/translate/vmx-impl.c.inc | 10 ++ 2 files changed, 15 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 3eb920ac76..36b42e41d2 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -719,3 +719,8 @@ VDIVESD 000100 . . . 0001011@VX VDIVEUD 000100 . . . 01011001011@VX VDIVESQ 000100 . . . 0111011@VX VDIVEUQ 000100 . . . 0101011@VX + +VMODSW 000100 . . . 0001011@VX +VMODUW 000100 . . . 11010001011@VX +VMODSD 000100 . . . 1001011@VX +VMODUD 000100 . . . 11011001011@VX diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index 566a2e6d23..69f71dc216 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -3363,6 +3363,11 @@ static void do_diveu_i32(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b) DIVS32(do_divesw, do_dives_i32) DIVU32(do_diveuw, do_diveu_i32) +DIVS32(do_modsw, tcg_gen_rem_i32) +DIVU32(do_moduw, tcg_gen_remu_i32) +DIVS64(do_modsd, tcg_gen_rem_i64) +DIVU64(do_modud, tcg_gen_remu_i64) + TRANS_FLAGS2(ISA310, VDIVESW, do_vdiv_vmod, MO_32, do_divesw, NULL) TRANS_FLAGS2(ISA310, VDIVEUW, do_vdiv_vmod, MO_32, do_diveuw, NULL) TRANS_FLAGS2(ISA310, VDIVESD, do_vx_helper, gen_helper_VDIVESD) @@ -3370,6 +3375,11 @@ TRANS_FLAGS2(ISA310, VDIVEUD, do_vx_helper, gen_helper_VDIVEUD) TRANS_FLAGS2(ISA310, VDIVESQ, do_vx_helper, gen_helper_VDIVESQ) TRANS_FLAGS2(ISA310, VDIVEUQ, do_vx_helper, gen_helper_VDIVEUQ) +TRANS_FLAGS2(ISA310, VMODSW, do_vdiv_vmod, MO_32, do_modsw , NULL) +TRANS_FLAGS2(ISA310, VMODUW, do_vdiv_vmod, MO_32, do_moduw, NULL) +TRANS_FLAGS2(ISA310, VMODSD, do_vdiv_vmod, MO_64, NULL, do_modsd) +TRANS_FLAGS2(ISA310, VMODUD, do_vdiv_vmod, MO_64, NULL, do_modud) + #undef DIVS32 #undef DIVU32 #undef DIVS64 -- 2.31.1
Re: [PATCH] target/ppc: Add two missing register callbacks on POWER10
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 4/11/22 09:59, Frederic Barrat wrote: This patch adds tcg accessors for 2 SPRs which were missing on P10: - the TBU40 register is used to write the upper 40 bits of the timebase register. It is used by kvm to update the timebase when entering/exiting the guest on P9 and above. The missing definition was causing erratic decrementer interrupts in a pseries/kvm guest running in a powernv10/tcg host, typically resulting in hangs. - the missing DPDES SPR was found through code inspection. It exists unchanged on P10. Both existed on previous versions of the processor and a bit of git archaeology hints that they were added while the P10 model was already being worked on so they may have simply fallen through the cracks. Signed-off-by: Frederic Barrat --- target/ppc/cpu_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 073fd10168..2e9a3ded54 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6457,6 +6457,7 @@ static void init_proc_POWER10(CPUPPCState *env) register_power5p_common_sprs(env); register_power5p_lpar_sprs(env); register_power5p_ear_sprs(env); +register_power5p_tb_sprs(env); register_power6_common_sprs(env); register_power6_dbg_sprs(env); register_power8_tce_address_control_sprs(env); @@ -6467,6 +6468,7 @@ static void init_proc_POWER10(CPUPPCState *env) register_power8_pmu_user_sprs(env); register_power8_tm_sprs(env); register_power8_pspb_sprs(env); +register_power8_dpdes_sprs(env); register_vtb_sprs(env); register_power8_ic_sprs(env); register_power8_book4_sprs(env);
Re: [PATCH v4 10/19] migration: Postcopy preemption enablement
On Wed, Apr 20, 2022 at 12:05:24PM +0100, Daniel P. Berrangé wrote: > On Thu, Mar 31, 2022 at 11:08:48AM -0400, Peter Xu wrote: > > This patch enables postcopy-preempt feature. > > > > It contains two major changes to the migration logic: > > > > (1) Postcopy requests are now sent via a different socket from precopy > > background migration stream, so as to be isolated from very high page > > request delays. > > > > (2) For huge page enabled hosts: when there's postcopy requests, they can > > now > > intercept a partial sending of huge host pages on src QEMU. > > > > After this patch, we'll live migrate a VM with two channels for postcopy: > > (1) > > PRECOPY channel, which is the default channel that transfers background > > pages; > > and (2) POSTCOPY channel, which only transfers requested pages. > > > > There's no strict rule of which channel to use, e.g., if a requested page is > > already being transferred on precopy channel, then we will keep using the > > same > > precopy channel to transfer the page even if it's explicitly requested. In > > 99% > > of the cases we'll prioritize the channels so we send requested page via the > > postcopy channel as long as possible. > > > > On the source QEMU, when we found a postcopy request, we'll interrupt the > > PRECOPY channel sending process and quickly switch to the POSTCOPY channel. > > After we serviced all the high priority postcopy pages, we'll switch back to > > PRECOPY channel so that we'll continue to send the interrupted huge page > > again. > > There's no new thread introduced on src QEMU. > > Implicit in this approach is that the delay in sending postcopy > OOB pages is from the pending socket buffers the kernel already > has, and not any delay caused by the QEMU sending thread being > busy doing other stuff. Yes. > > Is there any scenario in which the QEMU sending thread is stalled > in sendmsg() with a 1GB huge page waiting for the kernel to > get space in the socket outgoing buffer ? Another yes.. It doesn't necessarily to be during sending a 1GB huge page, the guest can be using small pages and IMHO we could get stuck at sendmsg() for a precopy small page while there's actually postcopy requests in the queue. We can't solve this as long as we keep using 1 single thread for sending page. This patchset doesn't solve this issue, yet. And it's actually the chunk discussed and mention in the cover letter too in the section "Avoid precopy write() blocks postcopy" as an TODO item. Logically in the future we could try to make two or more sender threads so postcopy pages can use a separate sender thread. Note that this change will _not_ require interface change either from qemu cmdline or on migration protocol, because this patchset should have handled all the migration protocol already even for that, but then if it'll work well we could get pure speed up on further shrinked latency when preempt mode enabled comparing to before. The other thing is I never measured such an effect, so I can't tell how would it perform at last. We need more work on top if we'd like to persue it, mostly on doing proper synchronizations on senders. Thanks, -- Peter Xu
Re: [PATCH v4 08/19] migration: Add postcopy-preempt capability
On Wed, Apr 20, 2022 at 11:51:28AM +0100, Daniel P. Berrangé wrote: > > diff --git a/qapi/migration.json b/qapi/migration.json > > index 18e2610e88..3523f23386 100644 > > --- a/qapi/migration.json > > +++ b/qapi/migration.json > > @@ -463,6 +463,12 @@ > > # procedure starts. The VM RAM is saved with running > > VM. > > # (since 6.0) > > # > > +# @postcopy-preempt: If enabled, the migration process will allow postcopy > > +#requests to preempt precopy stream, so postcopy > > requests > > +#will be handled faster. This is a performance > > feature and > > +#should not affect the correctness of postcopy > > migration. > > +#(since 7.0) > > Now 7.1 Fixed. > > Reviewed-by: Daniel P. Berrangé Thanks, -- Peter Xu
[PATCH v3 5/9] host-utils: Implemented unsigned 256-by-128 division
From: "Lucas Mateus Castro (alqotel)"
Based on already existing QEMU implementation, created an unsigned 256
bit by 128 bit division needed to implement the vector divide extended
unsigned instruction from PowerISA3.1
Signed-off-by: Lucas Mateus Castro (alqotel)
---
This patch had received Reviewed-by by Richard Henderson pending on the
placemente of clz128 being moved to int128.h, but clz128 ended up being changed
to accommodate to int128.h (i.e. the lack of clz64), so out of precaution I'd
like to request a review of the clz128 implementation
---
include/qemu/host-utils.h | 2 +
include/qemu/int128.h | 38 +++
util/host-utils.c | 129 ++
3 files changed, 169 insertions(+)
diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h
index f19bd29105..9767af7573 100644
--- a/include/qemu/host-utils.h
+++ b/include/qemu/host-utils.h
@@ -32,6 +32,7 @@
#include "qemu/compiler.h"
#include "qemu/bswap.h"
+#include "qemu/int128.h"
#ifdef CONFIG_INT128
static inline void mulu64(uint64_t *plow, uint64_t *phigh,
@@ -849,4 +850,5 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1,
#endif
}
+Int128 divu256(Int128 *plow, Int128 *phigh, Int128 divisor);
#endif
diff --git a/include/qemu/int128.h b/include/qemu/int128.h
index 1f82918c73..840871688c 100644
--- a/include/qemu/int128.h
+++ b/include/qemu/int128.h
@@ -128,11 +128,21 @@ static inline bool int128_ge(Int128 a, Int128 b)
return a >= b;
}
+static inline bool int128_uge(Int128 a, Int128 b)
+{
+return ((__uint128_t)a) >= ((__uint128_t)b);
+}
+
static inline bool int128_lt(Int128 a, Int128 b)
{
return a < b;
}
+static inline bool int128_ult(Int128 a, Int128 b)
+{
+return (__uint128_t)a < (__uint128_t)b;
+}
+
static inline bool int128_le(Int128 a, Int128 b)
{
return a <= b;
@@ -177,6 +187,15 @@ static inline Int128 bswap128(Int128 a)
#endif
}
+static inline int clz128(Int128 a)
+{
+if (a >> 64) {
+return __builtin_clzll(a >> 64);
+} else {
+return (a) ? __builtin_clzll((uint64_t)a) + 64 : 128;
+}
+}
+
static inline Int128 int128_divu(Int128 a, Int128 b)
{
return (__uint128_t)a / (__uint128_t)b;
@@ -373,11 +392,21 @@ static inline bool int128_ge(Int128 a, Int128 b)
return a.hi > b.hi || (a.hi == b.hi && a.lo >= b.lo);
}
+static inline bool int128_uge(Int128 a, Int128 b)
+{
+return (uint64_t)a.hi > (uint64_t)b.hi || (a.hi == b.hi && a.lo >= b.lo);
+}
+
static inline bool int128_lt(Int128 a, Int128 b)
{
return !int128_ge(a, b);
}
+static inline bool int128_ult(Int128 a, Int128 b)
+{
+return !int128_uge(a, b);
+}
+
static inline bool int128_le(Int128 a, Int128 b)
{
return int128_ge(b, a);
@@ -418,6 +447,15 @@ static inline Int128 bswap128(Int128 a)
return int128_make128(bswap64(a.hi), bswap64(a.lo));
}
+static inline int clz128(Int128 a)
+{
+if (a.hi) {
+return __builtin_clzll(a.hi);
+} else {
+return (a.lo) ? __builtin_clzll(a.lo) + 64 : 128;
+}
+}
+
Int128 int128_divu(Int128, Int128);
Int128 int128_remu(Int128, Int128);
Int128 int128_divs(Int128, Int128);
diff --git a/util/host-utils.c b/util/host-utils.c
index 96d5dc0bed..93dfb1b6ab 100644
--- a/util/host-utils.c
+++ b/util/host-utils.c
@@ -266,3 +266,132 @@ void ulshift(uint64_t *plow, uint64_t *phigh, int32_t
shift, bool *overflow)
*plow = *plow << shift;
}
}
+
+/*
+ * Unsigned 256-by-128 division.
+ * Returns the remainder via r.
+ * Returns lower 128 bit of quotient.
+ * Needs a normalized divisor (most significant bit set to 1).
+ *
+ * Adapted from include/qemu/host-utils.h udiv_qrnnd,
+ * from the GNU Multi Precision Library - longlong.h __udiv_qrnnd
+ * (https://gmplib.org/repo/gmp/file/tip/longlong.h)
+ *
+ * Licensed under the GPLv2/LGPLv3
+ */
+static Int128 udiv256_qrnnd(Int128 *r, Int128 n1, Int128 n0, Int128 d)
+{
+Int128 d0, d1, q0, q1, r1, r0, m;
+uint64_t mp0, mp1;
+
+d0 = int128_make64(int128_getlo(d));
+d1 = int128_make64(int128_gethi(d));
+
+r1 = int128_remu(n1, d1);
+q1 = int128_divu(n1, d1);
+mp0 = int128_getlo(q1);
+mp1 = int128_gethi(q1);
+mulu128(, , int128_getlo(d0));
+m = int128_make128(mp0, mp1);
+r1 = int128_make128(int128_gethi(n0), int128_getlo(r1));
+if (int128_ult(r1, m)) {
+q1 = int128_sub(q1, int128_one());
+r1 = int128_add(r1, d);
+if (int128_uge(r1, d)) {
+if (int128_ult(r1, m)) {
+q1 = int128_sub(q1, int128_one());
+r1 = int128_add(r1, d);
+}
+}
+}
+r1 = int128_sub(r1, m);
+
+r0 = int128_remu(r1, d1);
+q0 = int128_divu(r1, d1);
+mp0 = int128_getlo(q0);
+mp1 = int128_gethi(q0);
+mulu128(, , int128_getlo(d0));
+m = int128_make128(mp0, mp1);
+r0 = int128_make128(int128_getlo(n0), int128_getlo(r0));
+if (int128_ult(r0, m)) {
+q0 = int128_sub(q0,
[PATCH v3 2/9] target/ppc: Implemented vector divide instructions
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
vdivsw: Vector Divide Signed Word
vdivuw: Vector Divide Unsigned Word
vdivsd: Vector Divide Signed Doubleword
vdivud: Vector Divide Unsigned Doubleword
Signed-off-by: Lucas Mateus Castro (alqotel)
---
target/ppc/insn32.decode| 7 +++
target/ppc/translate/vmx-impl.c.inc | 85 +
2 files changed, 92 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index ac2d3da9a7..597768558b 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -703,3 +703,10 @@ XVTLSBB 00 ... -- 00010 . 111011011 . -
@XX2_bf_xb
_s s:uint8_t
@XL_s ..-- s:1 .. - _s
RFEBB 010011-- . 0010010010 - @XL_s
+
+## Vector Division Instructions
+
+VDIVSW 000100 . . . 00110001011@VX
+VDIVUW 000100 . . . 00010001011@VX
+VDIVSD 000100 . . . 00111001011@VX
+VDIVUD 000100 . . . 00011001011@VX
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index 764ac45409..0b18705c8e 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -3236,6 +3236,91 @@ TRANS(VMULHSD, do_vx_mulh, true , do_vx_vmulhd_i64)
TRANS(VMULHUW, do_vx_mulh, false, do_vx_vmulhw_i64)
TRANS(VMULHUD, do_vx_mulh, false, do_vx_vmulhd_i64)
+static bool do_vdiv_vmod(DisasContext *ctx, arg_VX *a, const int vece,
+ void (*func_32)(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b),
+ void (*func_64)(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b))
+{
+const GVecGen3 op = {
+.fni4 = func_32,
+.fni8 = func_64,
+.vece = vece
+};
+
+REQUIRE_VECTOR(ctx);
+
+tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
+ avr_full_offset(a->vrb), 16, 16, );
+
+return true;
+}
+
+#define DIVU32(NAME, DIV) \
+static void NAME(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b)\
+{ \
+TCGv_i32 zero = tcg_constant_i32(0);\
+TCGv_i32 one = tcg_constant_i32(1); \
+tcg_gen_movcond_i32(TCG_COND_EQ, b, b, zero, one, b); \
+DIV(t, a, b); \
+}
+
+#define DIVS32(NAME, DIV) \
+static void NAME(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b)\
+{ \
+TCGv_i32 t0 = tcg_temp_new_i32(); \
+TCGv_i32 t1 = tcg_temp_new_i32(); \
+tcg_gen_setcondi_i32(TCG_COND_EQ, t0, a, INT32_MIN);\
+tcg_gen_setcondi_i32(TCG_COND_EQ, t1, b, -1); \
+tcg_gen_and_i32(t0, t0, t1);\
+tcg_gen_setcondi_i32(TCG_COND_EQ, t1, b, 0);\
+tcg_gen_or_i32(t0, t0, t1); \
+tcg_gen_movi_i32(t1, 0);\
+tcg_gen_movcond_i32(TCG_COND_NE, b, t0, t1, t0, b); \
+DIV(t, a, b); \
+tcg_temp_free_i32(t0); \
+tcg_temp_free_i32(t1); \
+}
+
+#define DIVU64(NAME, DIV) \
+static void NAME(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b)\
+{ \
+TCGv_i64 zero = tcg_constant_i64(0);\
+TCGv_i64 one = tcg_constant_i64(1); \
+tcg_gen_movcond_i64(TCG_COND_EQ, b, b, zero, one, b); \
+DIV(t, a, b); \
+}
+
+#define DIVS64(NAME, DIV) \
+static void NAME(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b)\
+{ \
+TCGv_i64 t0 = tcg_temp_new_i64(); \
+TCGv_i64 t1 = tcg_temp_new_i64(); \
+tcg_gen_setcondi_i64(TCG_COND_EQ, t0, a, INT64_MIN);\
+tcg_gen_setcondi_i64(TCG_COND_EQ, t1, b, -1); \
+tcg_gen_and_i64(t0, t0, t1);\
+tcg_gen_setcondi_i64(TCG_COND_EQ, t1, b, 0);\
+tcg_gen_or_i64(t0, t0, t1); \
+
Re: [PULL 00/25] Various testing, doc and gdbstub fixes
On 4/20/22 11:08, Alex Bennée wrote: The following changes since commit 1be5a765c08cee3a9587c8a8d3fc2ea247b13f9c: Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2022-04-19 18:22:16 -0700) are available in the Git repository at: https://github.com/stsquad/qemu.git tags/pull-fixes-for-7.1-200422-1 for you to fetch changes up to caccf599181e2ea5f236345de9d9957a4c23e5ec: tests/guest-debug: better handle gdb crashes (2022-04-20 16:04:20 +0100) Testing, docs and gdbstub updates: - make -M virt test exercise -cpu max - document how binfmt_misc docker works - clean-up the devel TOC generation - clean-up check-tcg cross-compile behaviour - fix byte swap error in xmm gdbstub access - add float_convd test with reference files - more reference files for float_convs - more cleanly handle gdb crashing during check-tcg Applied, thanks. Please update the wiki changelog for 7.1 as appropriate. r~ Alex Bennée (8): tests/avocado: update aarch64_virt test to exercise -cpu max docs/devel: add some notes on the binfmt-image-debian targets docs/devel: drop :hidden: and :includehidden: tags tests/tcg: remove duplicate sha512-sse case tests/tcg: add float_convd test tests/tcg: add missing reference files for float_convs target/i386: fix byte swap issue with XMM register access tests/guest-debug: better handle gdb crashes Paolo Bonzini (17): tests/docker: remove dead code for linux-user containers tests/docker: remove test targets tests/docker: remove dead variable tests/docker: remove unnecessary default definitions tests/docker: inline variable definitions or move close to use tests/docker: remove unnecessary filtering of $(DOCKER_IMAGES) tests/docker: simplify docker-TEST@IMAGE targets tests/docker: do not duplicate rules for hexagon-cross tests/tcg: add compiler test variables when using containers tests/tcg: remove CONFIG_LINUX_USER from config-target.mak tests/tcg: remove CONFIG_USER_ONLY from config-target.mak tests/tcg: prepare Makefile.prereqs at configure time tests/tcg: list test targets in Makefile.prereqs tests/tcg: invoke Makefile.target directly from QEMU's makefile tests/tcg: isolate from QEMU's config-host.mak tests/docker: remove SKIP_DOCKER_BUILD tests/tcg: fix non-static build docs/devel/index-api.rst | 1 - docs/devel/index-build.rst | 3 +- docs/devel/index-internals.rst | 1 - docs/devel/index-process.rst | 1 - docs/devel/index-tcg.rst | 1 - docs/devel/index.rst | 2 - docs/devel/qtest.rst | 1 - docs/devel/testing.rst | 38 + configure | 3 +- target/i386/gdbstub.c | 4 +- tests/tcg/multiarch/float_convd.c | 106 +++ MAINTAINERS| 1 + tests/Makefile.include | 63 +- tests/avocado/boot_linux_console.py| 25 - tests/avocado/machine_aarch64_virt.py | 51 ++ tests/docker/Makefile.include | 115 +-- tests/docker/docker.py | 57 -- .../build-toolchain.sh | 0 tests/docker/dockerfiles/empty.docker | 8 - tests/guest-debug/run-test.py | 11 +- tests/tcg/Makefile.prereqs | 18 - tests/tcg/Makefile.qemu| 121 --- tests/tcg/Makefile.target | 14 +- tests/tcg/aarch64/Makefile.softmmu-target | 2 +- tests/tcg/aarch64/Makefile.target | 10 +- tests/tcg/aarch64/float_convd.ref | 988 + tests/tcg/arm/float_convd.ref | 988 + tests/tcg/configure.sh | 78 +- tests/tcg/i386/Makefile.target | 2 +- tests/tcg/i386/float_convd.conf| 988 + tests/tcg/i386/float_convs.ref | 748 tests/tcg/multiarch/Makefile.target| 2 +- tests/tcg/ppc64/Makefile.target| 4 +- tests/tcg/ppc64le/Makefile.target | 4 +- tests/tcg/x86_64/Makefile.target | 9 +- tests/tcg/x86_64/float_convd.ref | 988 + tests/tcg/x86_64/float_convs.ref | 748 37 files
Re: [PATCH v2] hw/ppc/ppc405_boards: Initialize g_autofree pointer
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 4/5/22 09:35, Bernhard Beschow wrote:
Resolves the only compiler warning when building a full QEMU under Arch Linux:
Compiling C object libqemu-ppc-softmmu.fa.p/hw_ppc_ppc405_boards.c.o
In file included from /usr/include/glib-2.0/glib.h:114,
from qemu/include/glib-compat.h:32,
from qemu/include/qemu/osdep.h:132,
from ../src/hw/ppc/ppc405_boards.c:25:
../src/hw/ppc/ppc405_boards.c: In function ‘ref405ep_init’:
/usr/include/glib-2.0/glib/glib-autocleanups.h:28:3: warning: ‘filename’ may
be used uninitialized in this function [-Wmaybe-uninitialized]
28 | g_free (*pp);
| ^~~~
../src/hw/ppc/ppc405_boards.c:265:26: note: ‘filename’ was declared here
265 | g_autofree char *filename;
| ^~~~
Signed-off-by: Bernhard Beschow
---
hw/ppc/ppc405_boards.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 7e1a4ac955..3bed7002d2 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -262,13 +262,13 @@ static void ref405ep_init(MachineState *machine)
/* allocate and load BIOS */
if (machine->firmware) {
MemoryRegion *bios = g_new(MemoryRegion, 1);
-g_autofree char *filename;
+g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
+ machine->firmware);
long bios_size;
memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE,
_fatal);
-filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
if (!filename) {
error_report("Could not find firmware '%s'", machine->firmware);
exit(1);
Re: [PATCH 0/5] ppc/pnv: Introduce GPIO lines to drive the PSIHB device
On 3/23/22 04:28, Cédric Le Goater wrote: Hello, The PSIHB OCC and LPC interrupts are driven by a complex framework using Object links and class handlers. Simplify the whole with GPIO lines. Thanks, Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel C. Cédric Le Goater (5): ppc/pnv: Fix PSI IRQ definition ppc/pnv: Remove PnvLpcController::psi link ppc/pnv: Remove PnvOCC::psi link ppc/pnv: Remove PnvPsiClas::irq_set ppc/pnv: Remove usless checks in set_irq handlers include/hw/ppc/pnv_lpc.h | 8 ++-- include/hw/ppc/pnv_occ.h | 7 ++- include/hw/ppc/pnv_psi.h | 7 +-- hw/ppc/pnv.c | 30 ++ hw/ppc/pnv_lpc.c | 19 --- hw/ppc/pnv_occ.c | 16 hw/ppc/pnv_psi.c | 36 +++- 7 files changed, 42 insertions(+), 81 deletions(-)
[PATCH v3 1/9] qemu/int128: add int128_urshift
From: Matheus Ferst
Implement an unsigned right shift for Int128 values and add the same
tests cases of int128_rshift in the unit test.
Signed-off-by: Matheus Ferst
Signed-off-by: Lucas Mateus Castro (alqotel)
Reviewed-by: Richard Henderson
---
include/qemu/int128.h| 19 +++
tests/unit/test-int128.c | 32
2 files changed, 51 insertions(+)
diff --git a/include/qemu/int128.h b/include/qemu/int128.h
index 37e07fd6dd..1f82918c73 100644
--- a/include/qemu/int128.h
+++ b/include/qemu/int128.h
@@ -83,6 +83,11 @@ static inline Int128 int128_rshift(Int128 a, int n)
return a >> n;
}
+static inline Int128 int128_urshift(Int128 a, int n)
+{
+return (__uint128_t)a >> n;
+}
+
static inline Int128 int128_lshift(Int128 a, int n)
{
return a << n;
@@ -299,6 +304,20 @@ static inline Int128 int128_rshift(Int128 a, int n)
}
}
+static inline Int128 int128_urshift(Int128 a, int n)
+{
+uint64_t h = a.hi;
+if (!n) {
+return a;
+}
+h = h >> (n & 63);
+if (n >= 64) {
+return int128_make64(h);
+} else {
+return int128_make128((a.lo >> n) | ((uint64_t)a.hi << (64 - n)), h);
+}
+}
+
static inline Int128 int128_lshift(Int128 a, int n)
{
uint64_t l = a.lo << (n & 63);
diff --git a/tests/unit/test-int128.c b/tests/unit/test-int128.c
index b86a3c76e6..ae0f552193 100644
--- a/tests/unit/test-int128.c
+++ b/tests/unit/test-int128.c
@@ -206,6 +206,37 @@ static void test_rshift(void)
test_rshift_one(0xFFFE8000U, 0, 0xFFFEULL,
0x8000ULL);
}
+static void __attribute__((__noinline__)) ATTRIBUTE_NOCLONE
+test_urshift_one(uint32_t x, int n, uint64_t h, uint64_t l)
+{
+Int128 a = expand(x);
+Int128 r = int128_urshift(a, n);
+g_assert_cmpuint(int128_getlo(r), ==, l);
+g_assert_cmpuint(int128_gethi(r), ==, h);
+}
+
+static void test_urshift(void)
+{
+test_urshift_one(0x0001U, 64, 0xULL,
0x0001ULL);
+test_urshift_one(0x8001U, 64, 0xULL,
0x8001ULL);
+test_urshift_one(0x7FFEU, 64, 0xULL,
0x7FFEULL);
+test_urshift_one(0xFFFEU, 64, 0xULL,
0xFFFEULL);
+test_urshift_one(0x0001U, 60, 0xULL,
0x0010ULL);
+test_urshift_one(0x8001U, 60, 0x0008ULL,
0x0010ULL);
+test_urshift_one(0x00018000U, 60, 0xULL,
0x0018ULL);
+test_urshift_one(0x80018000U, 60, 0x0008ULL,
0x0018ULL);
+test_urshift_one(0x7FFEU, 60, 0x0007ULL,
0xFFE0ULL);
+test_urshift_one(0xFFFEU, 60, 0x000FULL,
0xFFE0ULL);
+test_urshift_one(0x7FFE8000U, 60, 0x0007ULL,
0xFFE8ULL);
+test_urshift_one(0xFFFE8000U, 60, 0x000FULL,
0xFFE8ULL);
+test_urshift_one(0x00018000U, 0, 0x0001ULL,
0x8000ULL);
+test_urshift_one(0x80018000U, 0, 0x8001ULL,
0x8000ULL);
+test_urshift_one(0x7FFEU, 0, 0x7FFEULL,
0xULL);
+test_urshift_one(0xFFFEU, 0, 0xFFFEULL,
0xULL);
+test_urshift_one(0x7FFE8000U, 0, 0x7FFEULL,
0x8000ULL);
+test_urshift_one(0xFFFE8000U, 0, 0xFFFEULL,
0x8000ULL);
+}
+
int main(int argc, char **argv)
{
g_test_init(, , NULL);
@@ -219,5 +250,6 @@ int main(int argc, char **argv)
g_test_add_func("/int128/int128_ge", test_ge);
g_test_add_func("/int128/int128_gt", test_gt);
g_test_add_func("/int128/int128_rshift", test_rshift);
+g_test_add_func("/int128/int128_urshift", test_urshift);
return g_test_run();
}
--
2.31.1
Re: [PATCH v2 0/2] Remove PCIE root bridge LSI on powernv
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 4/8/22 10:13, Frederic Barrat wrote: The powernv8/powernv9/powernv10 machines allocate a LSI for their root port bridge, which is not the case on real hardware. The default root port implementation in qemu requests a LSI. Since the powernv implementation derives from it, that's where the LSI is coming from. This series fixes it, so that the model matches the hardware. However, the code in hw/pci to handle AER and hotplug events assume a LSI is defined. It tends to assert/deassert a LSI if MSI or MSIX is not enabled. Since we have hardware where that is not true, this patch also fixes a few code paths to check if a LSI is configured before trying to trigger it. Changes from v1: - addressed comments from Daniel Frederic Barrat (2): pcie: Don't try triggering a LSI when not defined ppc/pnv: Remove LSI on the PCIE host bridge hw/pci-host/pnv_phb3.c | 1 + hw/pci-host/pnv_phb4.c | 1 + hw/pci/pcie.c | 5 +++-- hw/pci/pcie_aer.c | 2 +- 4 files changed, 6 insertions(+), 3 deletions(-)
[PATCH v3 3/9] target/ppc: Implemented vector divide quadword
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
vdivsq: Vector Divide Signed Quadword
vdivuq: Vector Divide Unsigned Quadword
Signed-off-by: Lucas Mateus Castro (alqotel)
Reviewed-by: Richard Henderson
---
target/ppc/helper.h | 2 ++
target/ppc/insn32.decode| 2 ++
target/ppc/int_helper.c | 21 +
target/ppc/translate/vmx-impl.c.inc | 2 ++
4 files changed, 27 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 57da11c77e..4cfdf7b3ec 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -171,6 +171,8 @@ DEF_HELPER_FLAGS_3(VMULOSW, TCG_CALL_NO_RWG, void, avr,
avr, avr)
DEF_HELPER_FLAGS_3(VMULOUB, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VMULOUH, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VMULOUW, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VDIVSQ, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VDIVUQ, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_3(vslo, void, avr, avr, avr)
DEF_HELPER_3(vsro, void, avr, avr, avr)
DEF_HELPER_3(vsrv, void, avr, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 597768558b..3a88a0b5bc 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -710,3 +710,5 @@ VDIVSW 000100 . . . 00110001011@VX
VDIVUW 000100 . . . 00010001011@VX
VDIVSD 000100 . . . 00111001011@VX
VDIVUD 000100 . . . 00011001011@VX
+VDIVSQ 000100 . . . 0011011@VX
+VDIVUQ 000100 . . . 0001011@VX
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 8c1674510b..55149c4fc7 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1036,6 +1036,27 @@ void helper_XXPERMX(ppc_vsr_t *t, ppc_vsr_t *s0,
ppc_vsr_t *s1, ppc_vsr_t *pcv,
*t = tmp;
}
+void helper_VDIVSQ(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b)
+{
+Int128 neg1 = int128_makes64(-1);
+Int128 int128_min = int128_make128(0, INT64_MIN);
+if (likely(int128_nz(b->s128) &&
+ (int128_ne(a->s128, int128_min) || int128_ne(b->s128, neg1 {
+t->s128 = int128_divs(a->s128, b->s128);
+} else {
+t->s128 = a->s128; /* Undefined behavior */
+}
+}
+
+void helper_VDIVUQ(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b)
+{
+if (int128_nz(b->s128)) {
+t->s128 = int128_divu(a->s128, b->s128);
+} else {
+t->s128 = a->s128; /* Undefined behavior */
+}
+}
+
void helper_VPERM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
ppc_avr_t result;
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index 0b18705c8e..cfd3c3ea6f 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -3315,6 +3315,8 @@ TRANS_FLAGS2(ISA310, VDIVSW, do_vdiv_vmod, MO_32,
do_divsw, NULL)
TRANS_FLAGS2(ISA310, VDIVUW, do_vdiv_vmod, MO_32, do_divuw, NULL)
TRANS_FLAGS2(ISA310, VDIVSD, do_vdiv_vmod, MO_64, NULL, do_divsd)
TRANS_FLAGS2(ISA310, VDIVUD, do_vdiv_vmod, MO_64, NULL, do_divud)
+TRANS_FLAGS2(ISA310, VDIVSQ, do_vx_helper, gen_helper_VDIVSQ)
+TRANS_FLAGS2(ISA310, VDIVUQ, do_vx_helper, gen_helper_VDIVUQ)
#undef DIVS32
#undef DIVU32
--
2.31.1
[PULL 3/4] accel/tcg: Remove ATOMIC_MMU_IDX
The last use of this macro was removed in f3e182b10013
("accel/tcg: Push trace info building into atomic_common.c.inc")
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c| 1 -
accel/tcg/user-exec.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 2035b2ac0a..dd45e0467b 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -2552,7 +2552,6 @@ void cpu_stq_le_mmu(CPUArchState *env, target_ulong addr,
uint64_t val,
glue(glue(glue(cpu_atomic_ ## X, SUFFIX), END), _mmu)
#define ATOMIC_MMU_CLEANUP
-#define ATOMIC_MMU_IDX get_mmuidx(oi)
#include "atomic_common.c.inc"
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 8edf0bbaa1..ac57324d4f 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -506,7 +506,6 @@ static void *atomic_mmu_lookup(CPUArchState *env,
target_ulong addr,
#define ATOMIC_NAME(X) \
glue(glue(glue(cpu_atomic_ ## X, SUFFIX), END), _mmu)
#define ATOMIC_MMU_CLEANUP do { clear_helper_retaddr(); } while (0)
-#define ATOMIC_MMU_IDX MMU_USER_IDX
#define DATA_SIZE 1
#include "atomic_template.h"
--
2.34.1
Re: [PULL 01/53] qapi, target/i386/sev: Add cpu0-id to query-sev-capabilities
On 19/04/2022 10:16, Dov Murik wrote:
> Thanks Paolo.
>
> On 19/04/2022 8:50, Paolo Bonzini wrote:
>> From: Dov Murik
>>
>> Add a new field 'cpu0-id' to the response of query-sev-capabilities QMP
>> command. The value of the field is the base64-encoded unique ID of CPU0
>> (socket 0), which can be used to retrieve the signed CEK of the CPU from
>> AMD's Key Distribution Service (KDS).
>>
>> Signed-off-by: Dov Murik
>>
>> Reviewed-by: Daniel P. Berrangé
>> Message-Id: <20220228093014.882288-1-dovmu...@linux.ibm.com>
>> Signed-off-by: Paolo Bonzini
>> ---
>> qapi/misc-target.json | 4
>> target/i386/sev.c | 42 +-
>> 2 files changed, 45 insertions(+), 1 deletion(-)
>>
>> diff --git a/qapi/misc-target.json b/qapi/misc-target.json
>> index 036c5e4a91..bc9355b595 100644
>> --- a/qapi/misc-target.json
>> +++ b/qapi/misc-target.json
>> @@ -144,6 +144,8 @@
>> #
>> # @cert-chain: PDH certificate chain (base64 encoded)
>> #
>> +# @cpu0-id: Unique ID of CPU0 (base64 encoded) (since 7.0)
>> +#
>
> Should this be changed to "since 7.1" ?
>
> Paolo, can you modify the patch in your tree, or should I submit a new
> version?
I see the original is already merged to master, so I sent another fix-up patch:
Subject: [PATCH] qapi: Fix version of cpu0-id field
Message-ID: 20220420190129.3532623-1-dovmu...@linux.ibm.com
-Dov
>
> -Dov
>
>> # @cbitpos: C-bit location in page table entry
>> #
>> # @reduced-phys-bits: Number of physical Address bit reduction when SEV is
>> @@ -154,6 +156,7 @@
>> { 'struct': 'SevCapability',
>>'data': { 'pdh': 'str',
>> 'cert-chain': 'str',
>> +'cpu0-id': 'str',
>> 'cbitpos': 'int',
>> 'reduced-phys-bits': 'int'},
>>'if': 'TARGET_I386' }
>> @@ -172,6 +175,7 @@
>> #
>> # -> { "execute": "query-sev-capabilities" }
>> # <- { "return": { "pdh": "8CCDD8DDD", "cert-chain": "888CCCDDDEE",
>> +# "cpu0-id": "2lvmGwo+...61iEinw==",
>> # "cbitpos": 47, "reduced-phys-bits": 5}}
>> #
>> ##
>> diff --git a/target/i386/sev.c b/target/i386/sev.c
>> index 025ff7a6f8..32f7dbac4e 100644
>> --- a/target/i386/sev.c
>> +++ b/target/i386/sev.c
>> @@ -531,12 +531,46 @@ e_free:
>> return 1;
>> }
>>
>> +static int sev_get_cpu0_id(int fd, guchar **id, size_t *id_len, Error
>> **errp)
>> +{
>> +guchar *id_data;
>> +struct sev_user_data_get_id2 get_id2 = {};
>> +int err, r;
>> +
>> +/* query the ID length */
>> +r = sev_platform_ioctl(fd, SEV_GET_ID2, _id2, );
>> +if (r < 0 && err != SEV_RET_INVALID_LEN) {
>> +error_setg(errp, "SEV: Failed to get ID ret=%d fw_err=%d (%s)",
>> + r, err, fw_error_to_str(err));
>> +return 1;
>> +}
>> +
>> +id_data = g_new(guchar, get_id2.length);
>> +get_id2.address = (unsigned long)id_data;
>> +
>> +r = sev_platform_ioctl(fd, SEV_GET_ID2, _id2, );
>> +if (r < 0) {
>> +error_setg(errp, "SEV: Failed to get ID ret=%d fw_err=%d (%s)",
>> + r, err, fw_error_to_str(err));
>> +goto err;
>> +}
>> +
>> +*id = id_data;
>> +*id_len = get_id2.length;
>> +return 0;
>> +
>> +err:
>> +g_free(id_data);
>> +return 1;
>> +}
>> +
>> static SevCapability *sev_get_capabilities(Error **errp)
>> {
>> SevCapability *cap = NULL;
>> guchar *pdh_data = NULL;
>> guchar *cert_chain_data = NULL;
>> -size_t pdh_len = 0, cert_chain_len = 0;
>> +guchar *cpu0_id_data = NULL;
>> +size_t pdh_len = 0, cert_chain_len = 0, cpu0_id_len = 0;
>> uint32_t ebx;
>> int fd;
>>
>> @@ -561,9 +595,14 @@ static SevCapability *sev_get_capabilities(Error **errp)
>> goto out;
>> }
>>
>> +if (sev_get_cpu0_id(fd, _id_data, _id_len, errp)) {
>> +goto out;
>> +}
>> +
>> cap = g_new0(SevCapability, 1);
>> cap->pdh = g_base64_encode(pdh_data, pdh_len);
>> cap->cert_chain = g_base64_encode(cert_chain_data, cert_chain_len);
>> +cap->cpu0_id = g_base64_encode(cpu0_id_data, cpu0_id_len);
>>
>> host_cpuid(0x801F, 0, NULL, , NULL, NULL);
>> cap->cbitpos = ebx & 0x3f;
>> @@ -575,6 +614,7 @@ static SevCapability *sev_get_capabilities(Error **errp)
>> cap->reduced_phys_bits = 1;
>>
>> out:
>> +g_free(cpu0_id_data);
>> g_free(pdh_data);
>> g_free(cert_chain_data);
>> close(fd);
Future of libslirp in QEMU
I noticed in the 7.0 changelog that libslirp might be removed as a submodule in the future. Since user networking is very important for my project, I'm wondering if this is simply an implementation detail, or if there are plans to eventually remove slirp support entirely from QEMU (which would be bad for me)? Is there somewhere I can read the discussion about this? I searched the mailing list archives but didn't see anything obvious.
[PULL 2/4] tcg: Fix indirect lowering vs TCG_OPF_COND_BRANCH
With TCG_OPF_COND_BRANCH, we extended the lifetimes of
globals across extended basic blocks. This means that
the liveness computed in pass 1 does not kill globals
in the same way as normal temps.
Introduce TYPE_EBB to match this lifetime, so that we
get correct register allocation for the temps that we
introduce during the indirect lowering pass.
Reviewed-by: Peter Maydell
Fixes: b4cb76e6208 ("tcg: Do not kill globals at conditional branches")
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 2 ++
tcg/tcg.c | 34 +++---
2 files changed, 29 insertions(+), 7 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 73869fd9d0..27de13fae0 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -433,6 +433,8 @@ typedef enum TCGTempVal {
typedef enum TCGTempKind {
/* Temp is dead at the end of all basic blocks. */
TEMP_NORMAL,
+/* Temp is live across conditional branch, but dead otherwise. */
+TEMP_EBB,
/* Temp is saved across basic blocks but dead at the end of TBs. */
TEMP_LOCAL,
/* Temp is saved across both basic blocks and translation blocks. */
diff --git a/tcg/tcg.c b/tcg/tcg.c
index f8542529d0..f2d9ce19b8 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1024,9 +1024,18 @@ void tcg_temp_free_internal(TCGTemp *ts)
TCGContext *s = tcg_ctx;
int k, idx;
-/* In order to simplify users of tcg_constant_*, silently ignore free. */
-if (ts->kind == TEMP_CONST) {
+switch (ts->kind) {
+case TEMP_CONST:
+/*
+ * In order to simplify users of tcg_constant_*,
+ * silently ignore free.
+ */
return;
+case TEMP_NORMAL:
+case TEMP_LOCAL:
+break;
+default:
+g_assert_not_reached();
}
#if defined(CONFIG_DEBUG_TCG)
@@ -1036,7 +1045,6 @@ void tcg_temp_free_internal(TCGTemp *ts)
}
#endif
-tcg_debug_assert(ts->kind < TEMP_GLOBAL);
tcg_debug_assert(ts->temp_allocated != 0);
ts->temp_allocated = 0;
@@ -1674,6 +1682,7 @@ static void tcg_reg_alloc_start(TCGContext *s)
case TEMP_GLOBAL:
break;
case TEMP_NORMAL:
+case TEMP_EBB:
val = TEMP_VAL_DEAD;
/* fall through */
case TEMP_LOCAL:
@@ -1701,6 +1710,9 @@ static char *tcg_get_arg_str_ptr(TCGContext *s, char
*buf, int buf_size,
case TEMP_LOCAL:
snprintf(buf, buf_size, "loc%d", idx - s->nb_globals);
break;
+case TEMP_EBB:
+snprintf(buf, buf_size, "ebb%d", idx - s->nb_globals);
+break;
case TEMP_NORMAL:
snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals);
break;
@@ -2378,6 +2390,7 @@ static void la_bb_end(TCGContext *s, int ng, int nt)
state = TS_DEAD | TS_MEM;
break;
case TEMP_NORMAL:
+case TEMP_EBB:
case TEMP_CONST:
state = TS_DEAD;
break;
@@ -2405,8 +2418,9 @@ static void la_global_sync(TCGContext *s, int ng)
}
/*
- * liveness analysis: conditional branch: all temps are dead,
- * globals and local temps should be synced.
+ * liveness analysis: conditional branch: all temps are dead unless
+ * explicitly live-across-conditional-branch, globals and local temps
+ * should be synced.
*/
static void la_bb_sync(TCGContext *s, int ng, int nt)
{
@@ -2427,6 +2441,7 @@ static void la_bb_sync(TCGContext *s, int ng, int nt)
case TEMP_NORMAL:
s->temps[i].state = TS_DEAD;
break;
+case TEMP_EBB:
case TEMP_CONST:
continue;
default:
@@ -2797,6 +2812,7 @@ static bool liveness_pass_2(TCGContext *s)
TCGTemp *dts = tcg_temp_alloc(s);
dts->type = its->type;
dts->base_type = its->base_type;
+dts->kind = TEMP_EBB;
its->state_ptr = dts;
} else {
its->state_ptr = NULL;
@@ -3107,6 +3123,7 @@ static void temp_free_or_dead(TCGContext *s, TCGTemp *ts,
int free_or_dead)
new_type = TEMP_VAL_MEM;
break;
case TEMP_NORMAL:
+case TEMP_EBB:
new_type = free_or_dead < 0 ? TEMP_VAL_MEM : TEMP_VAL_DEAD;
break;
case TEMP_CONST:
@@ -3353,6 +3370,7 @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet
allocated_regs)
temp_save(s, ts, allocated_regs);
break;
case TEMP_NORMAL:
+case TEMP_EBB:
/* The liveness analysis already ensures that temps are dead.
Keep an tcg_debug_assert for safety. */
tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD);
@@ -3370,8 +3388,9 @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet
allocated_regs)
}
/*
- * At a conditional branch, we assume all temporaries are dead and
- * all globals and local temps are synced to their location.
+ * At a conditional branch, we assume all temporaries are dead unless
+ * explicitly live-across-conditional-branch;
Re: [RFC PATCH v3 1/5] ppc64: Add semihosting support
On Wed, 20 Apr 2022 at 19:20, Leandro Lupori wrote: > > On 4/19/22 06:26, Peter Maydell wrote: > > On Mon, 18 Apr 2022 at 20:15, Leandro Lupori > > wrote: > >> > >> Add semihosting support for PPC64. This implementation is > >> based on the standard for ARM semihosting version 2.0, as > >> implemented by QEMU and documented in > >> > >> https://github.com/ARM-software/abi-aa/releases > >> > >> The PPC64 specific differences are the following: > >> > >> Semihosting Trap Instruction: sc 7 > >> Operation Number Register: r3 > >> Parameter Register: r4 > >> Return Register: r3 > >> Data block field size: 64 bits > > > > Where is the independent specification which defines that > > this is the ABI for PPC semihosting? You should provide the > > URL for that in a comment somewhere. > > > > AFAIK, there is no official PPC semihosting specification. Would it be > ok to just document it somewhere else, e.g. GitHub, as an unofficial > specification? I'm going to push back on this in the same way I did for the RISC-V folks. If this is an official PPC semihosting specification, intended to be supported by multiple different pieces of software, it needs to have an independent spec document somewhere (even if that spec document just cross-refers to the Arm spec for most of the detail). If this is an ad-hoc "add this thing for PPC in a purely QEMU-specific way" patchset, then no, we shouldn't implement it. Semihosting is an ABI, and when QEMU implements an ABI it should be because it's an external pre-existing one. thanks -- PMM
[PULL 1/4] Don't include sysemu/tcg.h if it is not necessary
From: Thomas Huth
This header only defines the tcg_allowed variable and the tcg_enabled()
function - which are not required in many files that include this
header. Drop the #include statement there.
Signed-off-by: Thomas Huth
Reviewed-by: Markus Armbruster
Message-Id: <20220315144107.1012530-1-th...@redhat.com>
Signed-off-by: Richard Henderson
---
accel/tcg/hmp.c | 1 -
accel/tcg/tcg-accel-ops-icount.c | 1 -
bsd-user/main.c | 1 -
hw/virtio/vhost.c| 1 -
linux-user/main.c| 1 -
monitor/misc.c | 1 -
target/arm/helper.c | 1 -
target/s390x/cpu_models_sysemu.c | 1 -
target/s390x/helper.c| 1 -
9 files changed, 9 deletions(-)
diff --git a/accel/tcg/hmp.c b/accel/tcg/hmp.c
index d2ea352655..bb67941420 100644
--- a/accel/tcg/hmp.c
+++ b/accel/tcg/hmp.c
@@ -4,7 +4,6 @@
#include "qapi/qapi-commands-machine.h"
#include "exec/exec-all.h"
#include "monitor/monitor.h"
-#include "sysemu/tcg.h"
static void hmp_tcg_register(void)
{
diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-icount.c
index 6436cd9349..24520ea112 100644
--- a/accel/tcg/tcg-accel-ops-icount.c
+++ b/accel/tcg/tcg-accel-ops-icount.c
@@ -24,7 +24,6 @@
*/
#include "qemu/osdep.h"
-#include "sysemu/tcg.h"
#include "sysemu/replay.h"
#include "sysemu/cpu-timers.h"
#include "qemu/main-loop.h"
diff --git a/bsd-user/main.c b/bsd-user/main.c
index 88d347d05e..e274dd92d7 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -27,7 +27,6 @@
#include "qemu-common.h"
#include "qemu/units.h"
#include "qemu/accel.h"
-#include "sysemu/tcg.h"
#include "qemu-version.h"
#include
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
index e55ac32bf3..2bc72c27c5 100644
--- a/hw/virtio/vhost.c
+++ b/hw/virtio/vhost.c
@@ -26,7 +26,6 @@
#include "migration/blocker.h"
#include "migration/qemu-file-types.h"
#include "sysemu/dma.h"
-#include "sysemu/tcg.h"
#include "trace.h"
/* enabled until disconnected backend stabilizes */
diff --git a/linux-user/main.c b/linux-user/main.c
index fbc9bcfd5f..f1711b82ec 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -21,7 +21,6 @@
#include "qemu-common.h"
#include "qemu/units.h"
#include "qemu/accel.h"
-#include "sysemu/tcg.h"
#include "qemu-version.h"
#include
#include
diff --git a/monitor/misc.c b/monitor/misc.c
index b0fc0e5843..ebd49e13b6 100644
--- a/monitor/misc.c
+++ b/monitor/misc.c
@@ -48,7 +48,6 @@
#include "qapi/util.h"
#include "sysemu/blockdev.h"
#include "sysemu/sysemu.h"
-#include "sysemu/tcg.h"
#include "sysemu/tpm.h"
#include "qapi/qmp/qdict.h"
#include "qapi/qmp/qerror.h"
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 50d287f289..d7715c911a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -27,7 +27,6 @@
#include "sysemu/cpus.h"
#include "sysemu/cpu-timers.h"
#include "sysemu/kvm.h"
-#include "sysemu/tcg.h"
#include "qemu/range.h"
#include "qapi/qapi-commands-machine-target.h"
#include "qapi/error.h"
diff --git a/target/s390x/cpu_models_sysemu.c b/target/s390x/cpu_models_sysemu.c
index 05c3ccaaff..d8a141a023 100644
--- a/target/s390x/cpu_models_sysemu.c
+++ b/target/s390x/cpu_models_sysemu.c
@@ -15,7 +15,6 @@
#include "s390x-internal.h"
#include "kvm/kvm_s390x.h"
#include "sysemu/kvm.h"
-#include "sysemu/tcg.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
#include "qapi/qmp/qerror.h"
diff --git a/target/s390x/helper.c b/target/s390x/helper.c
index 6e35473c7f..473c8e51b0 100644
--- a/target/s390x/helper.c
+++ b/target/s390x/helper.c
@@ -27,7 +27,6 @@
#include "hw/s390x/pv.h"
#include "sysemu/hw_accel.h"
#include "sysemu/runstate.h"
-#include "sysemu/tcg.h"
void s390x_tod_timer(void *opaque)
{
--
2.34.1
Re: [PATCH v2] hw/ppc: change indentation to spaces from TABs
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 4/11/22 23:12, Guo Zhi wrote:
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/374
There are still some files in the QEMU PPC code base that use TABs for
indentation instead of using spaces. The TABs should be replaced so that we
have a consistent coding style.
Signed-off-by: Guo Zhi
---
hw/ppc/ppc440_bamboo.c | 6 +++---
hw/ppc/spapr_rtas.c| 18 +-
include/hw/ppc/ppc.h | 10 +-
3 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 7fb620b9a0..5ec3a9a17f 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -3,9 +3,9 @@
*
* Copyright 2007 IBM Corporation.
* Authors:
- * Jerone Young
- * Christian Ehrhardt
- * Hollis Blanchard
+ * Jerone Young
+ * Christian Ehrhardt
+ * Hollis Blanchard
*
* This work is licensed under the GNU GPL license version 2 or later.
*
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index d7c04237fe..d58b65e88f 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -474,16 +474,16 @@ static void rtas_ibm_nmi_interlock(PowerPCCPU *cpu,
if (spapr->fwnmi_machine_check_interlock != cpu->vcpu_id) {
/*
-* The vCPU that hit the NMI should invoke "ibm,nmi-interlock"
+ * The vCPU that hit the NMI should invoke "ibm,nmi-interlock"
* This should be PARAM_ERROR, but Linux calls "ibm,nmi-interlock"
-* for system reset interrupts, despite them not being interlocked.
-* PowerVM silently ignores this and returns success here. Returning
-* failure causes Linux to print the error "FWNMI: nmi-interlock
-* failed: -3", although no other apparent ill effects, this is a
-* regression for the user when enabling FWNMI. So for now, match
-* PowerVM. When most Linux clients are fixed, this could be
-* changed.
-*/
+ * for system reset interrupts, despite them not being interlocked.
+ * PowerVM silently ignores this and returns success here. Returning
+ * failure causes Linux to print the error "FWNMI: nmi-interlock
+ * failed: -3", although no other apparent ill effects, this is a
+ * regression for the user when enabling FWNMI. So for now, match
+ * PowerVM. When most Linux clients are fixed, this could be
+ * changed.
+ */
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
return;
}
diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
index 364f165b4b..02af03ada2 100644
--- a/include/hw/ppc/ppc.h
+++ b/include/hw/ppc/ppc.h
@@ -99,11 +99,11 @@ enum {
ARCH_MAC99_U3,
};
-#define FW_CFG_PPC_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
-#define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
-#define FW_CFG_PPC_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
-#define FW_CFG_PPC_TBFREQ (FW_CFG_ARCH_LOCAL + 0x03)
-#define FW_CFG_PPC_CLOCKFREQ (FW_CFG_ARCH_LOCAL + 0x04)
+#define FW_CFG_PPC_WIDTH(FW_CFG_ARCH_LOCAL + 0x00)
+#define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
+#define FW_CFG_PPC_DEPTH(FW_CFG_ARCH_LOCAL + 0x02)
+#define FW_CFG_PPC_TBFREQ (FW_CFG_ARCH_LOCAL + 0x03)
+#define FW_CFG_PPC_CLOCKFREQ(FW_CFG_ARCH_LOCAL + 0x04)
#define FW_CFG_PPC_IS_KVM (FW_CFG_ARCH_LOCAL + 0x05)
#define FW_CFG_PPC_KVM_HC (FW_CFG_ARCH_LOCAL + 0x06)
#define FW_CFG_PPC_KVM_PID (FW_CFG_ARCH_LOCAL + 0x07)
[PULL 0/4] tcg patch queue
The following changes since commit 2d20a57453f6a206938cbbf77bed0b378c806c1f: Merge tag 'pull-fixes-for-7.1-200422-1' of https://github.com/stsquad/qemu into staging (2022-04-20 11:13:08 -0700) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220420 for you to fetch changes up to a61532faa5a4d5e021e35b6a4a1e180c72d4a22f: tcg: Add tcg_constant_ptr (2022-04-20 12:12:47 -0700) Cleanup sysemu/tcg.h usage. Fix indirect lowering vs cond branches Remove ATOMIC_MMU_IDX Add tcg_constant_ptr Richard Henderson (3): tcg: Fix indirect lowering vs TCG_OPF_COND_BRANCH accel/tcg: Remove ATOMIC_MMU_IDX tcg: Add tcg_constant_ptr Thomas Huth (1): Don't include sysemu/tcg.h if it is not necessary include/tcg/tcg.h| 4 accel/tcg/cputlb.c | 1 - accel/tcg/hmp.c | 1 - accel/tcg/tcg-accel-ops-icount.c | 1 - accel/tcg/user-exec.c| 1 - bsd-user/main.c | 1 - hw/virtio/vhost.c| 1 - linux-user/main.c| 1 - monitor/misc.c | 1 - target/arm/helper.c | 1 - target/s390x/cpu_models_sysemu.c | 1 - target/s390x/helper.c| 1 - tcg/tcg.c| 34 +++--- 13 files changed, 31 insertions(+), 18 deletions(-)
Re: [PATCH 07/34] configure, meson: move OpenGL check to meson
Il 20 aprile 2022 18:13:30 CEST, "Marc-André Lureau"
ha scritto:
>> -if config_host.has_key('CONFIG_OPENGL')
>> +softmmu_ss.add(opengl)
>>
>
>I guess this line is superfluous
It's needed for the include path, iirc.
Paolo
>
>
>> +if opengl.found()
>>opengl_ss = ss.source_set()
>>opengl_ss.add(gbm)
>> - opengl_ss.add(when: [opengl, pixman, 'CONFIG_OPENGL'],
>> + opengl_ss.add(when: [opengl, pixman],
>> if_true: files('shader.c', 'console-gl.c',
>> 'egl-helpers.c', 'egl-context.c'))
>>ui_modules += {'opengl' : opengl_ss}
>> endif
>>
>> -if config_host.has_key('CONFIG_OPENGL') and gbm.found()
>> +if opengl.found() and gbm.found()
>>egl_headless_ss = ss.source_set()
>> - egl_headless_ss.add(when: [opengl, gbm, pixman, 'CONFIG_OPENGL'],
>> + egl_headless_ss.add(when: [opengl, gbm, pixman],
>>if_true: files('egl-headless.c'))
>>ui_modules += {'egl-headless' : egl_headless_ss}
>> endif
>> @@ -98,8 +99,8 @@ if gtk.found()
>>gtk_ss = ss.source_set()
>>gtk_ss.add(gtk, vte, pixman, files('gtk.c', 'gtk-clipboard.c'))
>>gtk_ss.add(when: x11, if_true: files('x_keymap.c'))
>> - gtk_ss.add(when: [opengl, 'CONFIG_OPENGL'], if_true:
>> files('gtk-gl-area.c'))
>> - gtk_ss.add(when: [x11, opengl, 'CONFIG_OPENGL'], if_true:
>> files('gtk-egl.c'))
>> + gtk_ss.add(when: opengl, if_true: files('gtk-gl-area.c'))
>> + gtk_ss.add(when: [x11, opengl], if_true: files('gtk-egl.c'))
>>ui_modules += {'gtk' : gtk_ss}
>> endif
>>
>> @@ -112,7 +113,7 @@ if sdl.found()
>> 'sdl2-input.c',
>> 'sdl2.c',
>>))
>> - sdl_ss.add(when: [opengl, 'CONFIG_OPENGL'], if_true: files('sdl2-gl.c'))
>> + sdl_ss.add(when: opengl, if_true: files('sdl2-gl.c'))
>>sdl_ss.add(when: x11, if_true: files('x_keymap.c'))
>>ui_modules += {'sdl' : sdl_ss}
>> endif
>> --
>> 2.35.1
>>
>>
>>
>>
>Reviewed-by: Marc-André Lureau
>
Re: [PATCH 23/34] meson: always combine directories with prefix
On Wed, Apr 20, 2022 at 7:51 PM Paolo Bonzini wrote:
> Meson allows directories such as "bindir" to be relative to the prefix.
> Right
> now configure is forcing an absolute path, but that is not really
> necessary:
> just make sure all uses of the directory variables are prefixed
> appropriately.
> Do the same also for the options that are custom for QEMU, i.e. docdir and
> qemu_firmwarepath.
>
> Signed-off-by: Paolo Bonzini
>
Reviewed-by: Marc-André Lureau
> ---
> meson.build | 20 ++--
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/meson.build b/meson.build
> index 869cc10128..2545ac2848 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -1618,7 +1618,7 @@ config_host_data.set_quoted('CONFIG_PREFIX',
> get_option('prefix'))
> config_host_data.set_quoted('CONFIG_QEMU_CONFDIR', get_option('prefix') /
> qemu_confdir)
> config_host_data.set_quoted('CONFIG_QEMU_DATADIR', get_option('prefix') /
> qemu_datadir)
> config_host_data.set_quoted('CONFIG_QEMU_DESKTOPDIR',
> get_option('prefix') / qemu_desktopdir)
> -config_host_data.set_quoted('CONFIG_QEMU_FIRMWAREPATH',
> get_option('qemu_firmwarepath'))
> +config_host_data.set_quoted('CONFIG_QEMU_FIRMWAREPATH',
> get_option('prefix') / get_option('qemu_firmwarepath'))
> config_host_data.set_quoted('CONFIG_QEMU_HELPERDIR', get_option('prefix')
> / get_option('libexecdir'))
> config_host_data.set_quoted('CONFIG_QEMU_ICONDIR', get_option('prefix') /
> qemu_icondir)
> config_host_data.set_quoted('CONFIG_QEMU_LOCALEDIR', get_option('prefix')
> / get_option('localedir'))
> @@ -3615,20 +3615,20 @@ endif
> summary_info = {}
> summary_info += {'Install prefix':get_option('prefix')}
> summary_info += {'BIOS directory':qemu_datadir}
> -summary_info += {'firmware path': get_option('qemu_firmwarepath')}
> -summary_info += {'binary directory': get_option('bindir')}
> -summary_info += {'library directory': get_option('libdir')}
> +summary_info += {'firmware path': get_option('prefix') /
> get_option('qemu_firmwarepath')}
> +summary_info += {'binary directory': get_option('prefix') /
> get_option('bindir')}
> +summary_info += {'library directory': get_option('prefix') /
> get_option('libdir')}
> summary_info += {'module directory': qemu_moddir}
> -summary_info += {'libexec directory': get_option('libexecdir')}
> -summary_info += {'include directory': get_option('includedir')}
> -summary_info += {'config directory': get_option('sysconfdir')}
> +summary_info += {'libexec directory': get_option('prefix') /
> get_option('libexecdir')}
> +summary_info += {'include directory': get_option('prefix') /
> get_option('includedir')}
> +summary_info += {'config directory': get_option('prefix') /
> get_option('sysconfdir')}
> if targetos != 'windows'
> - summary_info += {'local state directory': get_option('localstatedir')}
> - summary_info += {'Manual directory': get_option('mandir')}
> + summary_info += {'local state directory': get_option('prefix') /
> get_option('localstatedir')}
> + summary_info += {'Manual directory': get_option('prefix') /
> get_option('mandir')}
> else
>summary_info += {'local state directory': 'queried at runtime'}
> endif
> -summary_info += {'Doc directory': get_option('docdir')}
> +summary_info += {'Doc directory': get_option('prefix') /
> get_option('docdir')}
> summary_info += {'Build directory': meson.current_build_dir()}
> summary_info += {'Source path': meson.current_source_dir()}
> summary_info += {'GIT submodules':config_host['GIT_SUBMODULES']}
> --
> 2.35.1
>
>
>
>
--
Marc-André Lureau
