Building QEMU as a shared library
Hi, Before sending a patch, I would like to check if it's of interest to the community. My goal is to simulate a mixed architecture system. Today QEMU strongly assumes that the simulated system is a *single architecture*. Changing this assumption and supporting mixed architecture in QEMU proved to be non-trivial and may require significant development effort. Common code such as TCG and others explicitly include architecture specific header files, for example. A possible solution, discussed on https://stackoverflow.com/q/63229262/619493 is to separate the simulation to multiple processes (as done by Xilinx) and to use some form of Interprocess Communication channel between them. Such solution has several disadvantages: - Harder to synchronize simulation between processes - Performance impact of Interprocess Communication - Harder to debug, profile and maintain Instead, I would like to suggest a new approach we use at Neuroblade to achieve this: Build QEMU as a shared library that can be loaded and used directly in a larger simulation. Today we build qemu-system-nios2 shared library and load it from qemu-system-x86_64 in order to simulate an x86_64 system that also consists of multiple nios2 cores. In our simulation, two independent "main" functions are running on different threads, and simulation synchronization is reduced to synchronizing threads. To achieve this, I needed to do the following changes in QEMU: 1. Avoid Glib global context. Use a different context (g_main_context_new) for each QEMU instance. 2. Change meson.build to build QEMU as a shared library (with PIC enabled for static libraries) 3. Define a C API for the library and export it (with a -Wl,--version-script) These changes seem enough for simulating mixed architecture system on a single process. If this approach sounds useful, I'll be happy to send patches. I'd appreciate if you could provide your feedback! Thanks, Amir The contents of this email message and any attachments are intended solely for the addressee(s) and may contain confidential and/or privileged information and may be legally protected from disclosure. If you are not the intended recipient of this message or their agent, or if this message has been addressed to you in error, please immediately alert the sender by reply email and then delete this message and any attachments. If you are not the intended recipient, you are hereby notified that any use, dissemination, copying, or storage of this message or its attachments is strictly prohibited.
RE: Building QEMU as a shared library
Hi Stefan, Easier/faster synchronization is just one side of the issue. It's much easier to debug a single process or profile it, for example. It's also easier to deploy and maintain a single process. For now, the only "global state" problem I had to fix was Glib global context. I didn't see an issue with posix signals. Any other global state you think I should take care of? Of course, I only tested it for my own simple use case (qemu-system-nios2 + qemu-system-x86_64 with no GUI) As a first step , I intend to send a patch that removes the Glib context global state. Thanks, Amir -Original Message- From: Stefan Hajnoczi Sent: Wednesday, December 15, 2021 11:46 AM To: Amir Gonnen Cc: qemu-devel@nongnu.org; peter.mayd...@linaro.org; f4...@amsat.org Subject: Re: Building QEMU as a shared library On Wed, Dec 15, 2021 at 08:18:53AM +, Amir Gonnen wrote: > Before sending a patch, I would like to check if it's of interest to the > community. > > My goal is to simulate a mixed architecture system. > Today QEMU strongly assumes that the simulated system is a *single > architecture*. > Changing this assumption and supporting mixed architecture in QEMU > proved to be non-trivial and may require significant development > effort. Common code such as TCG and others explicitly include architecture > specific header files, for example. Hi Amir, Simulating heterogenous machines comes up from periodically. So far no one has upstreamed a solution but there is definitely interest. I suggest going ahead and posting the code even if it's not cleaned up. > A possible solution, discussed on > https://stackoverflow.com/q/63229262/619493 is to separate the > simulation to multiple processes (as done by Xilinx) and to use some form of > Interprocess Communication channel between them. > Such solution has several disadvantages: > > - Harder to synchronize simulation between processes > - Performance impact of Interprocess Communication > - Harder to debug, profile and maintain > > Instead, I would like to suggest a new approach we use at Neuroblade to > achieve this: > Build QEMU as a shared library that can be loaded and used directly in a > larger simulation. > Today we build qemu-system-nios2 shared library and load it from > qemu-system-x86_64 in order to simulate an x86_64 system that also consists > of multiple nios2 cores. > In our simulation, two independent "main" functions are running on > different threads, and simulation synchronization is reduced to synchronizing > threads. > > To achieve this, I needed to do the following changes in QEMU: > > 1. Avoid Glib global context. Use a different context (g_main_context_new) > for each QEMU instance. > 2. Change meson.build to build QEMU as a shared library (with PIC > enabled for static libraries) 3. Define a C API for the library and > export it (with a -Wl,--version-script) > > These changes seem enough for simulating mixed architecture system on a > single process. > > If this approach sounds useful, I'll be happy to send patches. > I'd appreciate if you could provide your feedback! I'm curious how much synchronization and IPC there is between the QEMU shared libraries? I would have guessed that the pain of making communication work efficiently between processes would be less than the pain of solving global state bugs related to shared libraries within a single process. Were there issues with POSIX signal handlers? Stefan The contents of this email message and any attachments are intended solely for the addressee(s) and may contain confidential and/or privileged information and may be legally protected from disclosure. If you are not the intended recipient of this message or their agent, or if this message has been addressed to you in error, please immediately alert the sender by reply email and then delete this message and any attachments. If you are not the intended recipient, you are hereby notified that any use, dissemination, copying, or storage of this message or its attachments is strictly prohibited.
[PATCH] target/nios2: Shadow register set, EIC and VIC
>From 99efcd655e83f034bce25271fe592d8789529e54 Mon Sep 17 00:00:00 2001
From: Amir Gonnen
Date: Thu, 17 Feb 2022 15:43:14 +0200
Subject: [PATCH] target/nios2: Shadow register set, EIC and VIC
Implement nios2 Vectored Interrupt Controller (VIC).
This includes Exteral Interrupt Controller interface (EIC) and Shadow
Register set implementation on the nios2 cpu.
Implemented missing wrprs and rdprs instructions, and fixed eret.
Added intc_present property, true by default. When set to false, nios2
uses the EIC interface when handling IRQ.
To use VIC, the nios2 board should set VIC cpu property, disable
intc_present, connect VIC irq to cpu and connect VIC gpios.
Signed-off-by: Amir Gonnen
---
hw/intc/Kconfig | 4 +
hw/intc/meson.build | 1 +
hw/intc/nios2_vic.c | 327 +++
target/nios2/cpu.c | 59 +--
target/nios2/cpu.h | 69 -
target/nios2/helper.c| 33 +++-
target/nios2/helper.h| 3 +
target/nios2/op_helper.c | 31 +++-
target/nios2/translate.c | 32 +++-
9 files changed, 537 insertions(+), 22 deletions(-)
create mode 100644 hw/intc/nios2_vic.c
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 528e77b4a6..8000241428 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -81,3 +81,7 @@ config GOLDFISH_PIC
config M68K_IRQC
bool
+
+config NIOS2_VIC
+default y
+depends on NIOS2 && TCG
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 7466024402..547e16eb2d 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -61,3 +61,4 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'],
if_true: files('spapr_xive_kvm.c'))
specific_ss.add(when: 'CONFIG_GOLDFISH_PIC', if_true: files('goldfish_pic.c'))
specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
+specific_ss.add(when: 'CONFIG_NIOS2_VIC', if_true: files('nios2_vic.c'))
diff --git a/hw/intc/nios2_vic.c b/hw/intc/nios2_vic.c
new file mode 100644
index 00..a9c9b3e7ac
--- /dev/null
+++ b/hw/intc/nios2_vic.c
@@ -0,0 +1,327 @@
+/*
+ * Vectored Interrupt Controller for nios2 processor
+ *
+ * Copyright (c) 2022 Neuroblade
+ *
+ * Interface:
+ * QOM property "cpu": link to the Nios2 CPU (must be set)
+ * Unnamed GPIO inputs 0..NIOS2_VIC_MAX_IRQ-1: input IRQ lines
+ * IRQ should be connected to nios2 IRQ0.
+ *
+ * Reference: "Embedded Peripherals IP User Guide
+ * for Intel® Quartus® Prime Design Suite: 21.4"
+ * Chapter 38 "Vectored Interrupt Controller Core"
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qapi/error.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qom/object.h"
+#include "cpu.h"
+
+#define LOG_VIC(...) qemu_log_mask(CPU_LOG_INT, ##__VA_ARGS__)
+
+#define TYPE_NIOS2_VIC "nios2-vic"
+
+OBJECT_DECLARE_SIMPLE_TYPE(Nios2Vic, NIOS2_VIC)
+
+#define NIOS2_VIC_MAX_IRQ 32
+
+enum {
+INT_CONFIG0 = 0,
+INT_CONFIG31 = 31,
+INT_ENABLE = 32,
+INT_ENABLE_SET = 33,
+INT_ENABLE_CLR = 34,
+INT_PENDING = 35,
+INT_RAW_STATUS = 36,
+SW_INTERRUPT = 37,
+SW_INTERRUPT_SET = 38,
+SW_INTERRUPT_CLR = 39,
+VIC_CONFIG = 40,
+VIC_STATUS = 41,
+VEC_TBL_BASE = 42,
+VEC_TBL_ADDR = 43,
+CSR_COUNT /* Last! */
+};
+
+struct Nios2Vic {
+/*< private >*/
+SysBusDevice parent_obj;
+
+/*< public >*/
+qemu_irq output_int;
+
+/* properties */
+CPUState *cpu;
+MemoryRegion csr;
+
+uint32_t int_config[32];
+uint32_t vic_config;
+uint32_t int_r
RE: [PATCH] target/nios2: Shadow register set, EIC and VIC
Hi Peter,
I can split the VIC from the core+EIC changes, although the core+EIC changes
make little sense without a VIC to interact with them.
However, I'm not sure how to split the changes to the nios2 core into multiple
patches.
The shadow register set, together with the EIC interface and interrupt handling
are very much tied together.
Regarding the "fixed eret" - perhaps I didn't phrase it right. What I meant is
that eret was changed to work correctly in the presence of a shadow register
set.
So, the changes to eret are part of the shadow register set support on the core
and cannot exist on their own.
I tested this on Neuroblade board with JUART. I did not wire it to an existing
demo board.
> https://www.qemu.org/docs/master/devel/submitting-a-patch.html
> is our guidelines on patch formatting.
In fact, I tried to follow them. I've also run checkpatch.pl, etc.
Could you please point out where I failed to follow them or what I'm missing?
Thanks,
Amir
-Original Message-
From: Peter Maydell
Sent: Sunday, February 20, 2022 5:13 PM
To: Amir Gonnen
Cc: qemu-devel@nongnu.org; Chris Wulff ; Marek Vasut
Subject: Re: [PATCH] target/nios2: Shadow register set, EIC and VIC
[EXTERNAL]
On Sun, 20 Feb 2022 at 13:07, wrote:
>
> From 99efcd655e83f034bce25271fe592d8789529e54 Mon Sep 17 00:00:00 2001
> From: Amir Gonnen
> Date: Thu, 17 Feb 2022 15:43:14 +0200
> Subject: [PATCH] target/nios2: Shadow register set, EIC and VIC
>
> Implement nios2 Vectored Interrupt Controller (VIC).
> This includes Exteral Interrupt Controller interface (EIC) and Shadow
> Register set implementation on the nios2 cpu.
> Implemented missing wrprs and rdprs instructions, and fixed eret.
> Added intc_present property, true by default. When set to false, nios2
> uses the EIC interface when handling IRQ.
Hi; this patch seems to be trying to fix multiple things at once. Could you
split it up into a multi-patch patch series, where each patch does one logical
thing, please? In particular bug fixes to existing code ("fixed eret") should
be their own patches, separate from patches adding new features.
> To use VIC, the nios2 board should set VIC cpu property, disable
> intc_present, connect VIC irq to cpu and connect VIC gpios.
Is there a patch which wires up one of the nios2 boards to do this ?
https://www.qemu.org/docs/master/devel/submitting-a-patch.html
is our guidelines on patch formatting.
thanks
-- PMM
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[PATCH v2 4/4] hw/nios2: Machine with a Vectored Interrupt Controller
Demonstrate how to use nios2 VIC on a machine.
Introduce a new machine "10m50-ghrd-vic" which is based on "10m50-ghrd"
with a VIC attached and internal interrupt controller removed.
When VIC is present, irq0 connects the VIC to the cpu, intc_present
is set to false to disable the internal interrupt controller, and the
devices on the machine are attached to the VIC (and not directly to cpu).
To allow VIC update EIC fields, we set the "cpu" property of the VIC
with a reference to the nios2 cpu.
Signed-off-by: Amir Gonnen
---
hw/nios2/10m50_devboard.c | 64 ---
1 file changed, 60 insertions(+), 4 deletions(-)
diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c
index 3d1205b8bd..9f62a2993f 100644
--- a/hw/nios2/10m50_devboard.c
+++ b/hw/nios2/10m50_devboard.c
@@ -36,10 +36,23 @@
#include "boot.h"
+#define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd")
+typedef struct Nios2MachineClass Nios2MachineClass;
+DECLARE_OBJ_CHECKERS(MachineState, Nios2MachineClass,
+ NIOS2_MACHINE, TYPE_NIOS2_MACHINE)
+
#define BINARY_DEVICE_TREE_FILE"10m50-devboard.dtb"
+struct Nios2MachineClass {
+MachineClass parent_obj;
+
+bool vic;
+};
+
static void nios2_10m50_ghrd_init(MachineState *machine)
{
+Nios2MachineClass *nmc = NIOS2_MACHINE_GET_CLASS(machine);
+
Nios2CPU *cpu;
DeviceState *dev;
MemoryRegion *address_space_mem = get_system_memory();
@@ -74,8 +87,24 @@ static void nios2_10m50_ghrd_init(MachineState *machine)
/* Create CPU -- FIXME */
cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU));
-for (i = 0; i < 32; i++) {
-irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i);
+
+if (nmc->vic) {
+DeviceState *dev = qdev_new("nios2-vic");
+
+object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu),
&error_fatal);
+sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+cpu->intc_present = false;
+qemu_irq cpu_irq = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", 0);
+sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq);
+for (int i = 0; i < 32; i++) {
+irq[i] = qdev_get_gpio_in(dev, i);
+}
+MemoryRegion *dev_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+memory_region_add_subregion(address_space_mem, 0x18002000, dev_mr);
+} else {
+for (i = 0; i < 32; i++) {
+irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i);
+}
}
/* Register: Altera 16550 UART */
@@ -105,11 +134,38 @@ static void nios2_10m50_ghrd_init(MachineState *machine)
BINARY_DEVICE_TREE_FILE, NULL);
}
-static void nios2_10m50_ghrd_machine_init(struct MachineClass *mc)
+static void nios2_10m50_ghrd_machine_class_init(ObjectClass *oc, void *data)
{
+MachineClass *mc = MACHINE_CLASS(oc);
+Nios2MachineClass *nmc = NIOS2_MACHINE_CLASS(oc);
mc->desc = "Altera 10M50 GHRD Nios II design";
mc->init = nios2_10m50_ghrd_init;
mc->is_default = true;
+nmc->vic = false;
}
-DEFINE_MACHINE("10m50-ghrd", nios2_10m50_ghrd_machine_init);
+static void nios2_10m50_ghrd_vic_machine_class_init(ObjectClass *oc, void
*data)
+{
+MachineClass *mc = MACHINE_CLASS(oc);
+Nios2MachineClass *nmc = NIOS2_MACHINE_CLASS(oc);
+mc->desc = "Altera 10M50 GHRD Nios II design with VIC";
+mc->init = nios2_10m50_ghrd_init;
+mc->is_default = false;
+nmc->vic = true;
+}
+
+static const TypeInfo nios_machine_types[] = {
+{
+.name = MACHINE_TYPE_NAME("10m50-ghrd"),
+.parent= TYPE_MACHINE,
+.class_size= sizeof(Nios2MachineClass),
+.class_init= nios2_10m50_ghrd_machine_class_init,
+}, {
+.name = MACHINE_TYPE_NAME("10m50-ghrd-vic"),
+.parent= TYPE_MACHINE,
+.class_size= sizeof(Nios2MachineClass),
+.class_init= nios2_10m50_ghrd_vic_machine_class_init,
+}
+};
+
+DEFINE_TYPES(nios_machine_types)
--
2.25.1
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[PATCH v2 3/4] hw/intc: Vectored Interrupt Controller (VIC)
Implement nios2 Vectored Interrupt Controller (VIC).
VIC is connected to EIC. It needs to update rha, ril, rrs and rnmi
fields on Nios2CPU before raising an IRQ.
For that purpose, VIC has a "cpu" property which should refer to the
nios2 cpu and set by the board that connects VIC.
Signed-off-by: Amir Gonnen
---
hw/intc/Kconfig | 4 +
hw/intc/meson.build | 1 +
hw/intc/nios2_vic.c | 327
3 files changed, 332 insertions(+)
create mode 100644 hw/intc/nios2_vic.c
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 528e77b4a6..8000241428 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -81,3 +81,7 @@ config GOLDFISH_PIC
config M68K_IRQC
bool
+
+config NIOS2_VIC
+default y
+depends on NIOS2 && TCG
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 7466024402..547e16eb2d 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -61,3 +61,4 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'],
if_true: files('spapr_xive_kvm.c'))
specific_ss.add(when: 'CONFIG_GOLDFISH_PIC', if_true: files('goldfish_pic.c'))
specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
+specific_ss.add(when: 'CONFIG_NIOS2_VIC', if_true: files('nios2_vic.c'))
diff --git a/hw/intc/nios2_vic.c b/hw/intc/nios2_vic.c
new file mode 100644
index 00..a9c9b3e7ac
--- /dev/null
+++ b/hw/intc/nios2_vic.c
@@ -0,0 +1,327 @@
+/*
+ * Vectored Interrupt Controller for nios2 processor
+ *
+ * Copyright (c) 2022 Neuroblade
+ *
+ * Interface:
+ * QOM property "cpu": link to the Nios2 CPU (must be set)
+ * Unnamed GPIO inputs 0..NIOS2_VIC_MAX_IRQ-1: input IRQ lines
+ * IRQ should be connected to nios2 IRQ0.
+ *
+ * Reference: "Embedded Peripherals IP User Guide
+ * for Intel® Quartus® Prime Design Suite: 21.4"
+ * Chapter 38 "Vectored Interrupt Controller Core"
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qapi/error.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qom/object.h"
+#include "cpu.h"
+
+#define LOG_VIC(...) qemu_log_mask(CPU_LOG_INT, ##__VA_ARGS__)
+
+#define TYPE_NIOS2_VIC "nios2-vic"
+
+OBJECT_DECLARE_SIMPLE_TYPE(Nios2Vic, NIOS2_VIC)
+
+#define NIOS2_VIC_MAX_IRQ 32
+
+enum {
+INT_CONFIG0 = 0,
+INT_CONFIG31 = 31,
+INT_ENABLE = 32,
+INT_ENABLE_SET = 33,
+INT_ENABLE_CLR = 34,
+INT_PENDING = 35,
+INT_RAW_STATUS = 36,
+SW_INTERRUPT = 37,
+SW_INTERRUPT_SET = 38,
+SW_INTERRUPT_CLR = 39,
+VIC_CONFIG = 40,
+VIC_STATUS = 41,
+VEC_TBL_BASE = 42,
+VEC_TBL_ADDR = 43,
+CSR_COUNT /* Last! */
+};
+
+struct Nios2Vic {
+/*< private >*/
+SysBusDevice parent_obj;
+
+/*< public >*/
+qemu_irq output_int;
+
+/* properties */
+CPUState *cpu;
+MemoryRegion csr;
+
+uint32_t int_config[32];
+uint32_t vic_config;
+uint32_t int_raw_status;
+uint32_t int_enable;
+uint32_t sw_int;
+uint32_t vic_status;
+uint32_t vec_tbl_base;
+uint32_t vec_tbl_addr;
+};
+
+/* Requested interrupt level (INT_CONFIG[0:5]) */
+static inline uint32_t vic_int_config_ril(const Nios2Vic *vic, int irq_num)
+{
+return extract32(vic->int_config[irq_num], 0, 6);
+}
+
+/* Requested NMI (INT_CONFIG[6]) */
+static inline uint32_t vic_int_config_rnmi(const Nios2Vic *vic, int irq_num)
+{
+return extract32(vic->int_config[irq_num], 6, 1);
+}
+
+/* Requested register set (INT_CONFIG[7:12]) */
+static inline uint32_t vic_int_config_rrs(const Nios2Vic *vic,
[PATCH v2 2/4] target/nios2: Exteral Interrupt Controller (EIC)
Implement Exteral Interrupt Controller interface (EIC).
Added intc_present property, true by default. When set to false, nios2
uses the EIC interface when handling IRQ. When set to true (default)
it uses the internal interrupt controller.
When nios2 recieves irq, it first checks intc_present to decide whether
to use the internal interrupt controller or the EIC.
The EIC is triggered by IRQ gpio but also recieves additional data from
the external interrupt controller (such as VIC): rha, ril, rrs and rnmi.
The interrupt controller is expected to raise IRQ after setting these
fields on Nios2CPU.
rha, ril, rrs and rnmi are used when EIC handles external interrupt, in
order to decide if to take the interrupt now, which shadow register set
to use, which PC to jump to, whether to set NMI flag, etc.
Signed-off-by: Amir Gonnen
---
target/nios2/cpu.c | 58 +---
target/nios2/cpu.h | 22 +++
target/nios2/helper.c| 33 ---
target/nios2/op_helper.c | 7 +++--
4 files changed, 105 insertions(+), 15 deletions(-)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 0886705818..9bd8a6301a 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -55,6 +55,7 @@ static void nios2_cpu_reset(DeviceState *dev)
memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS);
memset(env->shadow_regs, 0, sizeof(uint32_t) * NUM_REG_SETS * NUM_GP_REGS);
+env->regs[CR_STATUS] |= CR_STATUS_RSIE;
env->regs[R_PC] = cpu->reset_addr;
#if defined(CONFIG_USER_ONLY)
@@ -65,10 +66,28 @@ static void nios2_cpu_reset(DeviceState *dev)
#endif
}
+bool nios2_take_eic_irq(const Nios2CPU *cpu)
+{
+const CPUNios2State *env = &cpu->env;
+
+if (cpu->rnmi) {
+return !(env->regs[CR_STATUS] & CR_STATUS_NMI);
+}
+
+if (((env->regs[CR_STATUS] & CR_STATUS_PIE) == 0) ||
+(cpu->ril <= cpu_get_il(env)) ||
+(cpu->rrs == cpu_get_crs(env) &&
+ !(env->regs[CR_STATUS] & CR_STATUS_RSIE))) {
+
+return false;
+}
+
+return true;
+}
+
#ifndef CONFIG_USER_ONLY
-static void nios2_cpu_set_irq(void *opaque, int irq, int level)
+static void nios2_cpu_set_intc_irq(Nios2CPU *cpu, int irq, int level)
{
-Nios2CPU *cpu = opaque;
CPUNios2State *env = &cpu->env;
CPUState *cs = CPU(cpu);
@@ -83,6 +102,32 @@ static void nios2_cpu_set_irq(void *opaque, int irq, int
level)
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
+
+static void nios2_cpu_set_eic_irq(Nios2CPU *cpu, int level)
+{
+CPUNios2State *env = &cpu->env;
+CPUState *cs = CPU(cpu);
+
+env->irq_pending = level;
+
+if (env->irq_pending && nios2_take_eic_irq(cpu)) {
+env->irq_pending = 0;
+cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+} else if (!env->irq_pending) {
+cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+}
+}
+
+static void nios2_cpu_set_irq(void *opaque, int irq, int level)
+{
+Nios2CPU *cpu = opaque;
+
+if (cpu->intc_present) {
+nios2_cpu_set_intc_irq(cpu, irq, level);
+} else {
+nios2_cpu_set_eic_irq(cpu, level);
+}
+}
#endif
static void nios2_cpu_initfn(Object *obj)
@@ -94,13 +139,6 @@ static void nios2_cpu_initfn(Object *obj)
#if !defined(CONFIG_USER_ONLY)
mmu_init(&cpu->env);
-/*
- * These interrupt lines model the IIC (internal interrupt
- * controller). QEMU does not currently support the EIC
- * (external interrupt controller) -- if we did it would be
- * a separate device in hw/intc with a custom interface to
- * the CPU, and boards using it would not wire up these IRQ lines.
- */
qdev_init_gpio_in_named(DEVICE(cpu), nios2_cpu_set_irq, "IRQ", 32);
#endif
}
@@ -202,6 +240,8 @@ static Property nios2_properties[] = {
DEFINE_PROP_UINT32("mmu_tlb_num_ways", Nios2CPU, tlb_num_ways, 16),
/* ALTR,tlb-num-entries */
DEFINE_PROP_UINT32("mmu_pid_num_entries", Nios2CPU, tlb_num_entries, 256),
+/* interrupt-controller (internal) */
+DEFINE_PROP_BOOL("intc_present", Nios2CPU, intc_present, true),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 1d3503825b..1b3d0ed25e 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -92,12 +92,14 @@ struct Nios2CPUClass {
#define CR_STATUS_EH (1 << 2)
#define CR_STATUS_IH (1 << 3)
#define CR_STATUS_IL (63 << 4)
+#define CR_STATUS_IL_OFFSET 6
#define CR_STATUS_CRS (63 << 10)
#define CR_STATUS_CRS_OFFSET 10
#define CR_STATUS_PRS (63 << 16)
#define CR_STATUS_PRS_OFFSET 16
#define CR_STATUS_NMI (1 << 22)
#define CR_STATUS_RSIE (1 << 23)
+#define CR_STATUS_SRS (1 << 31)
#define CR_ESTATUS (CR_BASE + 1)
#define CR_BSTATUS (CR_BASE + 2)
#define CR_IENABLE
[PATCH v2 1/4] target/nios2: Shadow register set
Implement shadow register set and related instructions
rdprs, wrprs. Fix eret to update either status or sstatus
according to current register set.
eret also changes register set when needed.
Signed-off-by: Amir Gonnen
---
target/nios2/cpu.c | 1 +
target/nios2/cpu.h | 47 ++--
target/nios2/helper.h| 3 +++
target/nios2/op_helper.c | 24
target/nios2/translate.c | 32 ++-
5 files changed, 100 insertions(+), 7 deletions(-)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 4cade61e93..0886705818 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -54,6 +54,7 @@ static void nios2_cpu_reset(DeviceState *dev)
ncc->parent_reset(dev);
memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS);
+memset(env->shadow_regs, 0, sizeof(uint32_t) * NUM_REG_SETS * NUM_GP_REGS);
env->regs[R_PC] = cpu->reset_addr;
#if defined(CONFIG_USER_ONLY)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index d2ba0c5bbd..1d3503825b 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -57,9 +57,14 @@ struct Nios2CPUClass {
#define EXCEPTION_ADDRESS 0x0004
#define FAST_TLB_MISS_ADDRESS 0x0008
+#define NUM_GP_REGS 32
+#define NUM_CR_REGS 32
/* GP regs + CR regs + PC */
-#define NUM_CORE_REGS (32 + 32 + 1)
+#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS + 1)
+
+/* 63 shadow register sets. 0 is the primary set */
+#define NUM_REG_SETS 64
/* General purpose register aliases */
#define R_ZERO 0
@@ -80,7 +85,7 @@ struct Nios2CPUClass {
#define R_RA 31
/* Control register aliases */
-#define CR_BASE 32
+#define CR_BASE NUM_GP_REGS
#define CR_STATUS(CR_BASE + 0)
#define CR_STATUS_PIE (1 << 0)
#define CR_STATUS_U(1 << 1)
@@ -88,7 +93,9 @@ struct Nios2CPUClass {
#define CR_STATUS_IH (1 << 3)
#define CR_STATUS_IL (63 << 4)
#define CR_STATUS_CRS (63 << 10)
+#define CR_STATUS_CRS_OFFSET 10
#define CR_STATUS_PRS (63 << 16)
+#define CR_STATUS_PRS_OFFSET 16
#define CR_STATUS_NMI (1 << 22)
#define CR_STATUS_RSIE (1 << 23)
#define CR_ESTATUS (CR_BASE + 1)
@@ -131,6 +138,7 @@ struct Nios2CPUClass {
/* Other registers */
#define R_PC 64
+#define R_SSTATUS30
/* Exceptions */
#define EXCP_BREAK0x1000
@@ -157,6 +165,7 @@ struct Nios2CPUClass {
struct CPUNios2State {
uint32_t regs[NUM_CORE_REGS];
+uint32_t shadow_regs[NUM_REG_SETS][NUM_GP_REGS];
#if !defined(CONFIG_USER_ONLY)
Nios2MMU mmu;
@@ -246,4 +255,38 @@ static inline void cpu_get_tb_cpu_state(CPUNios2State
*env, target_ulong *pc,
*flags = (env->regs[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U));
}
+static inline uint32_t cpu_get_crs(const CPUNios2State *env)
+{
+return (env->regs[CR_STATUS] & CR_STATUS_CRS)
+>> CR_STATUS_CRS_OFFSET;
+}
+
+static inline uint32_t cpu_get_prs(const CPUNios2State *env)
+{
+return (env->regs[CR_STATUS] & CR_STATUS_PRS)
+>> CR_STATUS_PRS_OFFSET;
+}
+
+static inline void cpu_change_reg_set(CPUNios2State *env, uint32_t prev_set,
+ uint32_t new_set)
+{
+if (new_set == prev_set) {
+return;
+}
+memcpy(env->shadow_regs[prev_set], env->regs,
+ sizeof(uint32_t) * NUM_GP_REGS);
+memcpy(env->regs, env->shadow_regs[new_set],
+ sizeof(uint32_t) * NUM_GP_REGS);
+env->regs[CR_STATUS] = (env->regs[CR_STATUS] & (~CR_STATUS_PRS))
+ | ((prev_set << CR_STATUS_PRS_OFFSET) & CR_STATUS_PRS);
+env->regs[CR_STATUS] = (env->regs[CR_STATUS] & (~CR_STATUS_CRS))
+ | ((new_set << CR_STATUS_CRS_OFFSET) & CR_STATUS_CRS);
+}
+
+static inline void cpu_set_crs(CPUNios2State *env, uint32_t value)
+{
+uint32_t crs = cpu_get_crs(env);
+cpu_change_reg_set(env, crs, value);
+}
+
#endif /* NIOS2_CPU_H */
diff --git a/target/nios2/helper.h b/target/nios2/helper.h
index 6c8f0b5b35..3e5c016e9c 100644
--- a/target/nios2/helper.h
+++ b/target/nios2/helper.h
@@ -18,6 +18,9 @@
* <http://www.gnu.org/licenses/lgpl-2.1.html>
*/
+DEF_HELPER_2(eret, void, env, i32)
+DEF_HELPER_3(wrprs, void, env, i32, i32)
+DEF_HELPER_2(rdprs, i32, env, i32)
DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32)
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c
index a59003855a..5e4f7a47ae 100644
--- a/target/nios2/op_helper.c
+++ b/target/nios2/op_helper.c
@@ -59,3 +59,27 @@ void helper_raise_exception(CPUNios2State *env, uint32_t
index)
cs->exception_index = index;
cpu_loop_exit(cs);
}
+
+void helper_wrprs(CPUNios2State *env, uint32_t reg_index, uint32_t value)
+{
+uint32_t prs = cpu_get_prs(env);
+env->shadow_regs[prs][reg_index] =
[PATCH v2 0/4] target/nios2: Shadow register set, EIC and VIC
Implement nios2 Shadow register set, EIC and VIC. Currently nios2 on QEMU contains an internal Interrupt Controller. The nios2 architecture can support a more powerful External Interrupt Controller (EIC) instead of the internal, and implements special cpu features to support it: Shadow register set and External Interrupt Controller Interface. This patch series introduces the necessary changes to the nios2 cpu to support an External Interrupt Controller, and includes a Vectored Interrupt Controller (VIC) device that can be attach to the EIC. Following Peter's suggestion in the previous version, I've splitted this into several independant patches that rely on each other incrementally and added a board that wires up the VIC: 1. Shadow Register Set support on the nios2 core 2. External Interrupt Controller interface on the nios2 core 3. Vectored Interrupt Controller 4. A board that uses the VIC instead of the default internal interrupt controller Signed-off-by: Amir Gonnen Amir Gonnen (4): target/nios2: Shadow register set target/nios2: Exteral Interrupt Controller (EIC) hw/intc: Vectored Interrupt Controller (VIC) hw/nios2: Machine with a Vectored Interrupt Controller hw/intc/Kconfig | 4 + hw/intc/meson.build | 1 + hw/intc/nios2_vic.c | 327 ++ hw/nios2/10m50_devboard.c | 64 +++- target/nios2/cpu.c| 59 +-- target/nios2/cpu.h| 69 +++- target/nios2/helper.c | 33 +++- target/nios2/helper.h | 3 + target/nios2/op_helper.c | 31 +++- target/nios2/translate.c | 32 +++- 10 files changed, 597 insertions(+), 26 deletions(-) create mode 100644 hw/intc/nios2_vic.c -- 2.25.1 The contents of this email message and any attachments are intended solely for the addressee(s) and may contain confidential and/or privileged information and may be legally protected from disclosure. If you are not the intended recipient of this message or their agent, or if this message has been addressed to you in error, please immediately alert the sender by reply email and then delete this message and any attachments. If you are not the intended recipient, you are hereby notified that any use, dissemination, copying, or storage of this message or its attachments is strictly prohibited.
RE: [PATCH v2 4/4] hw/nios2: Machine with a Vectored Interrupt Controller
Hi Peter, > Is a VIC a configurable option on the real hardware (well, FPGA image, I > guess) that this board is modelling ? > I couldn't find any docs on it with a quick google. This specific example-board from Intel does not provide a VIC option, as far as I know. (https://fpgacloud.intel.com/devstore/platform/15.1.0/Standard/max10-10m50-development-kit-ghrd-with-nios-iiddr3qspi-flashethernetmsgdmauartadc-with-linux/) Unfortunately, I couldn't find a publicly available nios2 board with a VIC. I've added "10m50-ghrd-vic" as an example to demonstrate how to wire VIC. In practice, we use Intel tooling (Quartus Prime) to generate both the hardware (nios2 + vic + other devices) and the software BSP that works with it. That is probably the regular workflow. Since nios2 is a "soft" cpu on an FPGA, each one generates their own custom "board" wired with the devices they need, memories etc. In the future I may be able to share Neuroblade's QEMU nios2 board because it is quite generic - it consumes a device tree, parses it, and wires devices according to it, so it can automatically match the generated HW. > Also, I wonder if we should have a vic machine option to the machine rather > than creating a whole new machine type? Sure, if you think it makes more sense. How do you suggest doing that? A class property for the nios2 machine class? Or is there some other standard way for adding a machine specific option? Thanks, Amir The contents of this email message and any attachments are intended solely for the addressee(s) and may contain confidential and/or privileged information and may be legally protected from disclosure. If you are not the intended recipient of this message or their agent, or if this message has been addressed to you in error, please immediately alert the sender by reply email and then delete this message and any attachments. If you are not the intended recipient, you are hereby notified that any use, dissemination, copying, or storage of this message or its attachments is strictly prohibited.
RE: [PATCH v2 1/4] target/nios2: Shadow register set
Hi Richard, Thank you for your review and comments! > You're missing a gen_check_supervisor here and in wrprs. There's something I don't understand about gen_check_supervisor - it looks like it checks CR_STATUS_U when generating code instead of generating code that checks CR_STATUS_U. Is that correct to assume that CR_STATUS_U would remain the same between generation and runtime? > As an existing bug to be fixed by a separate patch, eret should also check > for supervisor. Do you suggest I shouldn't fix this here? Why not fix this anyway? > You really need to suppress these footers when posting to a public mailing > list. I'm sorry about that. I've worked with IT team to disable this automatic footer when sending to the mailing list so it shouldn't appear any more in the list, but it may still appear for individual recipients. So, if this still annoys anyone please let me know and I'll contact them again for a different solution.
RE: [PATCH v5 41/48] target/nios2: Introduce shadow register sets
(Continue discussion from Re: [PATCH v4 24/33] target/nios2: Introduce shadow register sets) > > How does "cpu_crs_R" work? > > ... Otherwise, each gpr access would be indirect. I'm probably missing > > something here. > They are indirect, but with some optimization. Why not always access directly? With an EIC each interrupt handler is associated with a specific shadow register set, so we can expect that (on a sane use case) each block always executes on the same register set. If we update cpu_get_tb_cpu_state to translate differently based on STATUS.CRS we would still end up with a single translation for each block. This way the translator could emit direct registers access for shadow registers, and we won't need to rely on optimizations to lower indirect access. Thanks, Amir
RE: [PATCH v5 42/48] target/nios2: Implement rdprs, wrprs
Something is wrong when translating rdprs in an interrupt handler when CRS is 0x1. I'm hitting "../tcg/tcg.c:3466: tcg_reg_alloc_mov: Assertion `ts->val_type == TEMP_VAL_REG' failed." When stopped on that assertion I can see that : - ts->val_type = TEMP_VAL_DEAD - op->opc = INDEX_op_mov_i32 - ots->name = "pc" - cpu->ctrl[0] = 0x5f9 (that's STATUS so CRS = 1) - pc = 0xa2d5c so, it looks related to an assignment to PC a little after rdprs. When running with -d in_asm,op_ind,op_opt: IN: 0x000a2d5c: ldwr16,4(et) 0x000a2d60: rdprs sp,sp,0 0x000a2d64: ldwr4,8(et) 0x000a2d68: callr r16 OP before indirect lowering: ld_i32 tmp0,env,$0xfff0 brcond_i32 tmp0,$0x0,lt,$L0 dead: 0 000a2d5c add_i32 tmp0,et,$0x4 dead: 2 qemu_ld_i32 r16,tmp0,leul,0 sync: 0 dead: 1 000a2d60 call rdprs,$0x2,$1,sp,env,$0x1b sync: 0 dead: 0 2 000a2d64 add_i32 tmp0,et,$0x8 dead: 1 2 qemu_ld_i32 r4,tmp0,leul,0 sync: 0 dead: 0 1 000a2d68 and_i32 tmp0,r16,$0x3dead: 2 brcond_i32 tmp0,$0x0,ne,$L1 dead: 0 1 mov_i32 pc,r16 sync: 0 dead: 0 1 mov_i32 ra,$0xa2d6c sync: 0 dead: 0 1 call lookup_tb_ptr,$0x6,$1,tmp7,env dead: 1 goto_ptr tmp7dead: 0 set_label $L1 st_i32 r16,env,$0x2038 dead: 0 mov_i32 pc,$0xa2d68 sync: 0 dead: 0 1 call raise_exception,$0xa,$0,env,$0x7dead: 0 1 set_label $L0 exit_tb $0x7f1878027e43 OP after optimization and liveness analysis: ld_i32 tmp0,env,$0xfff0 pref=0x brcond_i32 tmp0,$0x0,lt,$L0 dead: 0 000a2d5c ld_i32 tmp34,crs,$0x60 pref=0xf038 add_i32 tmp0,tmp34,$0x4 dead: 2 pref=0xff3f qemu_ld_i32 tmp26,tmp0,leul,0dead: 1 pref=0xf038 st_i32 tmp26,crs,$0x40 000a2d60 call rdprs,$0x2,$1,tmp37,env,$0x1b dead: 2 pref=none st_i32 tmp37,crs,$0x6c dead: 0 000a2d64 add_i32 tmp0,tmp34,$0x8 dead: 1 2 pref=0xff3f qemu_ld_i32 tmp14,tmp0,leul,0dead: 1 pref=0x st_i32 tmp14,crs,$0x10 dead: 0 000a2d68 and_i32 tmp0,tmp26,$0x3 dead: 1 2 pref=0x brcond_i32 tmp0,$0x0,ne,$L1 dead: 0 1 mov_i32 pc,tmp26 sync: 0 dead: 0 1 pref=0x st_i32 $0xa2d6c,crs,$0x7cdead: 0 1 call lookup_tb_ptr,$0x6,$1,tmp7,env dead: 1 pref=none goto_ptr tmp7dead: 0 set_label $L1 ld_i32 tmp26,crs,$0x40 dead: 1 pref=0x st_i32 tmp26,env,$0x2038 dead: 0 mov_i32 pc,$0xa2d68 sync: 0 dead: 0 1 pref=0x call raise_exception,$0xa,$0,env,$0x7dead: 0 1 set_label $L0 exit_tb $0x7f1878027e43
RE: [PATCH for-7.1 v6 00/51] target/nios2: Shadow register set, EIC and VIC
I tested this with Intel tooling (Quartus Prime EDS) to build the nios2 firmware. Shadow register set, EIC, VIC work as expected. Looking forward to seeing this merged! Thanks, Amir
RE: [PATCH v2 2/4] target/nios2: Exteral Interrupt Controller (EIC)
> This looks wrong. Of course, so does nios2_cpu_set_irq, from which you've
> cribbed this.
> For our purposes, I think simply re-using env->regs[CR_IPENDING] as the
> external hw
> request word is the right thing to do. But we need to update RDCTL to
> compute the
> correct value from CR_IPENDING & CR_IENABLE, and update WRCTL to ignore
> writes.
Since you've already fixed that on " target/nios2: Rewrite interrupt handling"
patchset, I guess I'll need to rebase on it once it's merged.
Until then for my next version I plan to just keep that with a "TODO" comment.
> > +if (cpu->rnmi) {
> > +return !(env->regs[CR_STATUS] & CR_STATUS_NMI);
> > +}
> I think this should be a separate
> #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_0
The NMI is not a separate interrupt line. It's part of the interrupt sideband
and is set just like the Requested-Handler-Address or any other EIC field.
Could you explain why NMI should be separate? What makes it different from
other EIC fields?
Amir
[PATCH v3 1/5] target/nios2: Check supervisor on eret
eret instruction is only allowed in supervisor mode.
Signed-off-by: Amir Gonnen
---
target/nios2/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index ce3aacf59d..007c17e6e9 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -384,6 +384,8 @@ static const Nios2Instruction i_type_instructions[] = {
*/
static void eret(DisasContext *dc, uint32_t code, uint32_t flags)
{
+gen_check_supervisor(dc);
+
tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]);
tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_EA]);
--
2.25.1
[PATCH v3 3/5] target/nios2: Exteral Interrupt Controller (EIC)
Implement Exteral Interrupt Controller interface (EIC).
Added intc_present property, true by default. When set to false, nios2
uses the EIC interface when handling IRQ. When set to true (default)
it uses the internal interrupt controller.
When nios2 recieves irq, it first checks intc_present to decide whether
to use the internal interrupt controller or the EIC.
The EIC is triggered by IRQ gpio but also recieves additional data from
the external interrupt controller (such as VIC): rha, ril, rrs and rnmi.
The interrupt controller is expected to raise IRQ after setting these
fields on Nios2CPU.
rha, ril, rrs and rnmi are used when EIC handles external interrupt, in
order to decide if to take the interrupt now, which shadow register set
to use, which PC to jump to, whether to set NMI flag, etc.
Signed-off-by: Amir Gonnen
---
target/nios2/cpu.c| 54 ---
target/nios2/cpu.h| 21 -
target/nios2/helper.c | 33 ++
3 files changed, 90 insertions(+), 18 deletions(-)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 026ee18b01..d09f20c8db 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -55,6 +55,7 @@ static void nios2_cpu_reset(DeviceState *dev)
memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS);
memset(env->shadow_regs, 0, sizeof(uint32_t) * NUM_REG_SETS * NUM_GP_REGS);
+env->regs[CR_STATUS] |= CR_STATUS_RSIE;
env->regs[R_PC] = cpu->reset_addr;
#if defined(CONFIG_USER_ONLY)
@@ -65,6 +66,25 @@ static void nios2_cpu_reset(DeviceState *dev)
#endif
}
+static bool nios2_take_eic_irq(const Nios2CPU *cpu)
+{
+const CPUNios2State *env = &cpu->env;
+
+if (cpu->rnmi) {
+return !(env->regs[CR_STATUS] & CR_STATUS_NMI);
+}
+
+if (((env->regs[CR_STATUS] & CR_STATUS_PIE) == 0) ||
+(cpu->ril <= cpu_get_il(env)) ||
+(cpu->rrs == cpu_get_crs(env) &&
+ !(env->regs[CR_STATUS] & CR_STATUS_RSIE))) {
+
+return false;
+}
+
+return true;
+}
+
#ifndef CONFIG_USER_ONLY
static void nios2_cpu_set_irq(void *opaque, int irq, int level)
{
@@ -91,13 +111,6 @@ static void nios2_cpu_initfn(Object *obj)
#if !defined(CONFIG_USER_ONLY)
mmu_init(&cpu->env);
-/*
- * These interrupt lines model the IIC (internal interrupt
- * controller). QEMU does not currently support the EIC
- * (external interrupt controller) -- if we did it would be
- * a separate device in hw/intc with a custom interface to
- * the CPU, and boards using it would not wire up these IRQ lines.
- */
qdev_init_gpio_in_named(DEVICE(cpu), nios2_cpu_set_irq, "IRQ", 32);
#endif
}
@@ -131,13 +144,26 @@ static bool nios2_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
Nios2CPU *cpu = NIOS2_CPU(cs);
CPUNios2State *env = &cpu->env;
-if ((interrupt_request & CPU_INTERRUPT_HARD) &&
-(env->regs[CR_STATUS] & CR_STATUS_PIE) &&
-(env->regs[CR_IPENDING] & env->regs[CR_IENABLE])) {
-cs->exception_index = EXCP_IRQ;
-nios2_cpu_do_interrupt(cs);
-return true;
+if (cpu->intc_present) {
+if ((interrupt_request & CPU_INTERRUPT_HARD) &&
+(env->regs[CR_STATUS] & CR_STATUS_PIE) &&
+(env->regs[CR_IPENDING] & env->regs[CR_IENABLE])) {
+cs->exception_index = EXCP_IRQ;
+nios2_cpu_do_interrupt(cs);
+return true;
+}
+} else {
+/*
+ * IPENDING does not exist with external interrupt controller
+ * but we still use it to signal an external interrupt
+ */
+if (env->regs[CR_IPENDING] && nios2_take_eic_irq(cpu)) {
+cs->exception_index = EXCP_IRQ;
+nios2_cpu_do_interrupt(cs);
+return true;
+}
}
+
return false;
}
#endif /* !CONFIG_USER_ONLY */
@@ -200,6 +226,8 @@ static Property nios2_properties[] = {
DEFINE_PROP_UINT32("mmu_tlb_num_ways", Nios2CPU, tlb_num_ways, 16),
/* ALTR,tlb-num-entries */
DEFINE_PROP_UINT32("mmu_pid_num_entries", Nios2CPU, tlb_num_entries, 256),
+/* interrupt-controller (internal) */
+DEFINE_PROP_BOOL("intc_present", Nios2CPU, intc_present, true),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index dbb4c968df..24d2d65aa9 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -92,11 +92,12 @@ struct Nios2CPUClass {
#define CR_STATUS_U(1 << 1)
#define CR_STATUS_EH (1 << 2)
#define CR_STATUS_IH (1 << 3)
-#define CR_STATUS_IL (63 << 4)
+FIELD(CR_STATUS, IL, 4, 6)
FIELD(CR_STATUS, CRS, 10, 6)
FIELD(CR_STATUS, PRS, 16, 6)
#define CR_STATUS_NMI (1 << 22)
#define CR_STATUS_
[PATCH v3 4/5] hw/intc: Vectored Interrupt Controller (VIC)
Implement nios2 Vectored Interrupt Controller (VIC).
VIC is connected to EIC. It needs to update rha, ril, rrs and rnmi
fields on Nios2CPU before raising an IRQ.
For that purpose, VIC has a "cpu" property which should refer to the
nios2 cpu and set by the board that connects VIC.
Signed-off-by: Amir Gonnen
---
hw/intc/Kconfig | 3 +
hw/intc/meson.build | 1 +
hw/intc/nios2_vic.c | 341
3 files changed, 345 insertions(+)
create mode 100644 hw/intc/nios2_vic.c
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 528e77b4a6..0a8e8d1d84 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -81,3 +81,6 @@ config GOLDFISH_PIC
config M68K_IRQC
bool
+
+config NIOS2_VIC
+bool
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index d953197413..c33b075859 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -61,3 +61,4 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'],
if_true: files('spapr_xive_kvm.c'))
specific_ss.add(when: 'CONFIG_GOLDFISH_PIC', if_true: files('goldfish_pic.c'))
specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
+specific_ss.add(when: 'CONFIG_NIOS2_VIC', if_true: files('nios2_vic.c'))
diff --git a/hw/intc/nios2_vic.c b/hw/intc/nios2_vic.c
new file mode 100644
index 00..b59d3f6f4c
--- /dev/null
+++ b/hw/intc/nios2_vic.c
@@ -0,0 +1,341 @@
+/*
+ * Vectored Interrupt Controller for nios2 processor
+ *
+ * Copyright (c) 2022 Neuroblade
+ *
+ * Interface:
+ * QOM property "cpu": link to the Nios2 CPU (must be set)
+ * Unnamed GPIO inputs 0..NIOS2_VIC_MAX_IRQ-1: input IRQ lines
+ * IRQ should be connected to nios2 IRQ0.
+ *
+ * Reference: "Embedded Peripherals IP User Guide
+ * for Intel® Quartus® Prime Design Suite: 21.4"
+ * Chapter 38 "Vectored Interrupt Controller Core"
+ * See:
https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/vectored-interrupt-controller-core.html
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qapi/error.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qom/object.h"
+#include "cpu.h"
+
+#define TYPE_NIOS2_VIC "nios2-vic"
+
+OBJECT_DECLARE_SIMPLE_TYPE(Nios2Vic, NIOS2_VIC)
+
+#define NIOS2_VIC_MAX_IRQ 32
+
+enum {
+INT_CONFIG0 = 0,
+INT_CONFIG31 = 31,
+INT_ENABLE = 32,
+INT_ENABLE_SET = 33,
+INT_ENABLE_CLR = 34,
+INT_PENDING = 35,
+INT_RAW_STATUS = 36,
+SW_INTERRUPT = 37,
+SW_INTERRUPT_SET = 38,
+SW_INTERRUPT_CLR = 39,
+VIC_CONFIG = 40,
+VIC_STATUS = 41,
+VEC_TBL_BASE = 42,
+VEC_TBL_ADDR = 43,
+CSR_COUNT /* Last! */
+};
+
+struct Nios2Vic {
+/*< private >*/
+SysBusDevice parent_obj;
+
+/*< public >*/
+qemu_irq output_int;
+
+/* properties */
+CPUState *cpu;
+MemoryRegion csr;
+
+uint32_t int_config[32];
+uint32_t vic_config;
+uint32_t int_raw_status;
+uint32_t int_enable;
+uint32_t sw_int;
+uint32_t vic_status;
+uint32_t vec_tbl_base;
+uint32_t vec_tbl_addr;
+};
+
+/* Requested interrupt level (INT_CONFIG[0:5]) */
+static inline uint32_t vic_int_config_ril(const Nios2Vic *vic, int irq_num)
+{
+return extract32(vic->int_config[irq_num], 0, 6);
+}
+
+/* Requested NMI (INT_CONFIG[6]) */
+static inline uint32_t vic_int_config_rnmi(const Nios2Vic *vic, int irq_num)
+{
+return extract32(vic->int_config[irq_num], 6, 1);
+}
+
+/* Requested register set (INT_CONFIG[7:12]) */
+static inline uint32_t vic_int_config_rrs(const Ni
[PATCH v3 5/5] hw/nios2: Machine with a Vectored Interrupt Controller
Demonstrate how to use nios2 VIC on a machine.
Introduce a new machine "10m50-ghrd-vic" which is based on "10m50-ghrd"
with a VIC attached and internal interrupt controller removed.
When VIC is present, irq0 connects the VIC to the cpu, intc_present
is set to false to disable the internal interrupt controller, and the
devices on the machine are attached to the VIC (and not directly to cpu).
To allow VIC update EIC fields, we set the "cpu" property of the VIC
with a reference to the nios2 cpu.
Signed-off-by: Amir Gonnen
---
hw/nios2/10m50_devboard.c | 64 ---
hw/nios2/Kconfig | 1 +
2 files changed, 61 insertions(+), 4 deletions(-)
diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c
index 3d1205b8bd..9f62a2993f 100644
--- a/hw/nios2/10m50_devboard.c
+++ b/hw/nios2/10m50_devboard.c
@@ -36,10 +36,23 @@
#include "boot.h"
+#define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd")
+typedef struct Nios2MachineClass Nios2MachineClass;
+DECLARE_OBJ_CHECKERS(MachineState, Nios2MachineClass,
+ NIOS2_MACHINE, TYPE_NIOS2_MACHINE)
+
#define BINARY_DEVICE_TREE_FILE"10m50-devboard.dtb"
+struct Nios2MachineClass {
+MachineClass parent_obj;
+
+bool vic;
+};
+
static void nios2_10m50_ghrd_init(MachineState *machine)
{
+Nios2MachineClass *nmc = NIOS2_MACHINE_GET_CLASS(machine);
+
Nios2CPU *cpu;
DeviceState *dev;
MemoryRegion *address_space_mem = get_system_memory();
@@ -74,8 +87,24 @@ static void nios2_10m50_ghrd_init(MachineState *machine)
/* Create CPU -- FIXME */
cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU));
-for (i = 0; i < 32; i++) {
-irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i);
+
+if (nmc->vic) {
+DeviceState *dev = qdev_new("nios2-vic");
+
+object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu),
&error_fatal);
+sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+cpu->intc_present = false;
+qemu_irq cpu_irq = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", 0);
+sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq);
+for (int i = 0; i < 32; i++) {
+irq[i] = qdev_get_gpio_in(dev, i);
+}
+MemoryRegion *dev_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+memory_region_add_subregion(address_space_mem, 0x18002000, dev_mr);
+} else {
+for (i = 0; i < 32; i++) {
+irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i);
+}
}
/* Register: Altera 16550 UART */
@@ -105,11 +134,38 @@ static void nios2_10m50_ghrd_init(MachineState *machine)
BINARY_DEVICE_TREE_FILE, NULL);
}
-static void nios2_10m50_ghrd_machine_init(struct MachineClass *mc)
+static void nios2_10m50_ghrd_machine_class_init(ObjectClass *oc, void *data)
{
+MachineClass *mc = MACHINE_CLASS(oc);
+Nios2MachineClass *nmc = NIOS2_MACHINE_CLASS(oc);
mc->desc = "Altera 10M50 GHRD Nios II design";
mc->init = nios2_10m50_ghrd_init;
mc->is_default = true;
+nmc->vic = false;
}
-DEFINE_MACHINE("10m50-ghrd", nios2_10m50_ghrd_machine_init);
+static void nios2_10m50_ghrd_vic_machine_class_init(ObjectClass *oc, void
*data)
+{
+MachineClass *mc = MACHINE_CLASS(oc);
+Nios2MachineClass *nmc = NIOS2_MACHINE_CLASS(oc);
+mc->desc = "Altera 10M50 GHRD Nios II design with VIC";
+mc->init = nios2_10m50_ghrd_init;
+mc->is_default = false;
+nmc->vic = true;
+}
+
+static const TypeInfo nios_machine_types[] = {
+{
+.name = MACHINE_TYPE_NAME("10m50-ghrd"),
+.parent= TYPE_MACHINE,
+.class_size= sizeof(Nios2MachineClass),
+.class_init= nios2_10m50_ghrd_machine_class_init,
+}, {
+.name = MACHINE_TYPE_NAME("10m50-ghrd-vic"),
+.parent= TYPE_MACHINE,
+.class_size= sizeof(Nios2MachineClass),
+.class_init= nios2_10m50_ghrd_vic_machine_class_init,
+}
+};
+
+DEFINE_TYPES(nios_machine_types)
diff --git a/hw/nios2/Kconfig b/hw/nios2/Kconfig
index b10ea640da..4748ae27b6 100644
--- a/hw/nios2/Kconfig
+++ b/hw/nios2/Kconfig
@@ -3,6 +3,7 @@ config NIOS2_10M50
select NIOS2
select SERIAL
select ALTERA_TIMER
+select NIOS2_VIC
config NIOS2_GENERIC_NOMMU
bool
--
2.25.1
[PATCH v3 2/5] target/nios2: Shadow register set
Implement shadow register set and related instructions
rdprs, wrprs. Fix eret to update either status or sstatus
according to current register set.
eret also changes register set when needed.
Signed-off-by: Amir Gonnen
---
target/nios2/cpu.c | 1 +
target/nios2/cpu.h | 48 +++---
target/nios2/helper.h| 1 +
target/nios2/op_helper.c | 18 +++
target/nios2/translate.c | 64
5 files changed, 123 insertions(+), 9 deletions(-)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 6975ae4bdb..026ee18b01 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -54,6 +54,7 @@ static void nios2_cpu_reset(DeviceState *dev)
ncc->parent_reset(dev);
memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS);
+memset(env->shadow_regs, 0, sizeof(uint32_t) * NUM_REG_SETS * NUM_GP_REGS);
env->regs[R_PC] = cpu->reset_addr;
#if defined(CONFIG_USER_ONLY)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index a00e4229ce..dbb4c968df 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -23,6 +23,7 @@
#include "exec/cpu-defs.h"
#include "hw/core/cpu.h"
+#include "hw/registerfields.h"
#include "qom/object.h"
typedef struct CPUNios2State CPUNios2State;
@@ -57,9 +58,14 @@ struct Nios2CPUClass {
#define EXCEPTION_ADDRESS 0x0004
#define FAST_TLB_MISS_ADDRESS 0x0008
+#define NUM_GP_REGS 32
+#define NUM_CR_REGS 32
/* GP regs + CR regs + PC */
-#define NUM_CORE_REGS (32 + 32 + 1)
+#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS + 1)
+
+/* 63 shadow register sets. 0 is the primary set */
+#define NUM_REG_SETS 64
/* General purpose register aliases */
#define R_ZERO 0
@@ -80,15 +86,15 @@ struct Nios2CPUClass {
#define R_RA 31
/* Control register aliases */
-#define CR_BASE 32
+#define CR_BASE NUM_GP_REGS
#define CR_STATUS(CR_BASE + 0)
#define CR_STATUS_PIE (1 << 0)
#define CR_STATUS_U(1 << 1)
#define CR_STATUS_EH (1 << 2)
#define CR_STATUS_IH (1 << 3)
#define CR_STATUS_IL (63 << 4)
-#define CR_STATUS_CRS (63 << 10)
-#define CR_STATUS_PRS (63 << 16)
+FIELD(CR_STATUS, CRS, 10, 6)
+FIELD(CR_STATUS, PRS, 16, 6)
#define CR_STATUS_NMI (1 << 22)
#define CR_STATUS_RSIE (1 << 23)
#define CR_ESTATUS (CR_BASE + 1)
@@ -131,6 +137,7 @@ struct Nios2CPUClass {
/* Other registers */
#define R_PC 64
+#define R_SSTATUS30
/* Exceptions */
#define EXCP_BREAK0x1000
@@ -157,6 +164,7 @@ struct Nios2CPUClass {
struct CPUNios2State {
uint32_t regs[NUM_CORE_REGS];
+uint32_t shadow_regs[NUM_REG_SETS][NUM_GP_REGS];
#if !defined(CONFIG_USER_ONLY)
Nios2MMU mmu;
@@ -245,4 +253,36 @@ static inline void cpu_get_tb_cpu_state(CPUNios2State
*env, target_ulong *pc,
*flags = (env->regs[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U));
}
+static inline uint32_t cpu_get_crs(const CPUNios2State *env)
+{
+return FIELD_EX32(env->regs[CR_STATUS], CR_STATUS, CRS);
+}
+
+static inline uint32_t cpu_get_prs(const CPUNios2State *env)
+{
+return FIELD_EX32(env->regs[CR_STATUS], CR_STATUS, PRS);
+}
+
+static inline void cpu_change_reg_set(CPUNios2State *env, uint32_t prev_set,
+ uint32_t new_set)
+{
+if (new_set == prev_set) {
+return;
+}
+memcpy(env->shadow_regs[prev_set], env->regs,
+ sizeof(uint32_t) * NUM_GP_REGS);
+memcpy(env->regs, env->shadow_regs[new_set],
+ sizeof(uint32_t) * NUM_GP_REGS);
+env->regs[CR_STATUS] =
+FIELD_DP32(env->regs[CR_STATUS], CR_STATUS, PRS, prev_set);
+env->regs[CR_STATUS] =
+FIELD_DP32(env->regs[CR_STATUS], CR_STATUS, CRS, new_set);
+}
+
+static inline void cpu_set_crs(CPUNios2State *env, uint32_t value)
+{
+uint32_t crs = cpu_get_crs(env);
+cpu_change_reg_set(env, crs, value);
+}
+
#endif /* NIOS2_CPU_H */
diff --git a/target/nios2/helper.h b/target/nios2/helper.h
index a44ecfdf7a..2e400b1f12 100644
--- a/target/nios2/helper.h
+++ b/target/nios2/helper.h
@@ -18,6 +18,7 @@
* <http://www.gnu.org/licenses/lgpl-2.1.html>
*/
+DEF_HELPER_2(eret, void, env, i32)
DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32)
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c
index caa885f7b4..c8ce399332 100644
--- a/target/nios2/op_helper.c
+++ b/target/nios2/op_helper.c
@@ -30,3 +30,21 @@ void helper_raise_exception(CPUNios2State *env, uint32_t
index)
cs->exception_index = index;
cpu_loop_exit(cs);
}
+
+void helper_eret(CPUNios2State *env, uint32_t new_pc)
+{
+uint32_t crs = cpu_get_crs(env);
+if (crs == 0) {
+env->regs[CR_STATUS] = env->regs[CR_ESTATUS];
+} else {
+env->regs[CR_STATUS] = env->regs[R_SSTATUS];
[PATCH v3 0/5] target/nios2: Shadow register set, EIC and VIC
Based-on: 20220227182125.21809-1-richard.hender...@linaro.org
("target/nios2: Rewrite interrupt handling")
Implement nios2 Shadow register set, EIC and VIC.
Currently nios2 on QEMU contains an internal Interrupt Controller.
The nios2 architecture can support a more powerful External Interrupt
Controller (EIC) instead of the internal, and implements special cpu
features to support it: Shadow register set and External Interrupt
Controller Interface.
This patch series introduces the necessary changes to the nios2 cpu to
support an External Interrupt Controller, and includes a Vectored
Interrupt Controller (VIC) device that can be attached to the EIC.
Changes from v2
===
- Rebase patchest on "target/nios2: Rewrite interrupt handling", which
introduces fixes to nios2 interrupt handling
- Check supervisor on eret as a separate patch
- Check supervisor on rdprs and wrprs
- Use FIELD_EX32 and FIELD_DP32 to access IL, CRS and PRS
- Added a comment on helper_eret
- Compute rdprs and wrprs inline, without helper functions
- Check nios2_take_eic_irq on nios2_cpu_exec_interrupt
- Check regs[CR_IPENDING] instead of env->irq_pending
- Fix Kconfig (remove defaults and depends)
- Added URL to VIC documentaion on Intel website
- Removed LOG_VIC
- Added comments in nios_vic.c
- Report an error in case of write to invalid CSR address
Changes from v1
===
- Splitted into several independant patches
- Added a board that wires up the VIC
Signed-off-by: Amir Gonnen
Amir Gonnen (5):
target/nios2: Check supervisor on eret
target/nios2: Shadow register set
target/nios2: Exteral Interrupt Controller (EIC)
hw/intc: Vectored Interrupt Controller (VIC)
hw/nios2: Machine with a Vectored Interrupt Controller
hw/intc/Kconfig | 3 +
hw/intc/meson.build | 1 +
hw/intc/nios2_vic.c | 341 ++
hw/nios2/10m50_devboard.c | 64 ++-
hw/nios2/Kconfig | 1 +
target/nios2/cpu.c| 55 --
target/nios2/cpu.h| 69 +++-
target/nios2/helper.c | 33 +++-
target/nios2/helper.h | 1 +
target/nios2/op_helper.c | 18 ++
target/nios2/translate.c | 66 +++-
11 files changed, 621 insertions(+), 31 deletions(-)
create mode 100644 hw/intc/nios2_vic.c
--
2.25.1
RE: [PATCH v4 24/33] target/nios2: Introduce shadow register sets
Hi Richard, How does "cpu_crs_R" work? In your version you hold a pointer to the current register set instead of copying registers back and forth like I did, which makes sense. But how does TCG know which set to refer to when it generates code? It looks like it's always accessing the same cpu_crs_R, so how does it relate to the correct register set on "shadow_regs"? In fact, I imagined it would be necessary to change "cpu_get_tb_cpu_state" and set "cs_base" or "flags" to STATUS.CRS such that different code would be generated for each shadow instance. Otherwise, each gpr access would be indirect. I'm probably missing something here. Thanks, Amir
Migrating NVME device
Hi,
I'm looking into making NVME device "migratable".
Following previous discussion on
https://lists.gnu.org/archive/html/qemu-devel/2017-08/msg05091.html, I would
like to implement the VMStateDescription to save and restore the entire
controller state, including all the queues.
"NvmeCtrl" defines the queues like this:
...
NvmeSQueue **sq;
NvmeCQueue **cq;
NvmeSQueue admin_sq;
NvmeCQueue admin_cq;
...
typedef struct NvmeCQueue {
struct NvmeCtrl *ctrl;
uint8_t phase;
...
My understanding is that I should use VMSTATE_STRUCT to save "admin_sq" and
"admin_cq", but how do I save/restore the "ctrl" field of "NvmeCQueue"?
And is there a VMSTATE_ macro I could use for handling "sq" and "cq" fields of
"NvmeCtrl"? These are dynamic allocated arrays of pointers to struct, whose
size is a device parameter. VMSTATE_STRUCT_VARRAY_ALLOC is close but not
exactly what I need here.
Is there a simple way to achieve this? Or do I need to use pre_save/post_load
to convert these into a more "serializable" form? Or create a new VMStateInfo
customized for this purpose?
I'd appreciate any hint or advice!
Thanks,
Amir
[Qemu-devel] [Bug 1803872] [NEW] gcc 8.2 reports stringop-truncation when building qemu
Public bug reported: QEMU 3.0 block/sheepdog.c: In function 'find_vdi_name': block/sheepdog.c:1239:5: error: 'strncpy' specified bound 256 equals destination size [-Werror=stringop-truncation] strncpy(buf + SD_MAX_VDI_LEN, tag, SD_MAX_VDI_TAG_LEN); ^~ If this is the intended behavior, please suppress the warning. For example: #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wstringop-truncation" strncpy(buf + SD_MAX_VDI_LEN, tag, SD_MAX_VDI_TAG_LEN); #pragma GCC diagnostic pop ** Affects: qemu Importance: Undecided Status: New -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1803872 Title: gcc 8.2 reports stringop-truncation when building qemu Status in QEMU: New Bug description: QEMU 3.0 block/sheepdog.c: In function 'find_vdi_name': block/sheepdog.c:1239:5: error: 'strncpy' specified bound 256 equals destination size [-Werror=stringop-truncation] strncpy(buf + SD_MAX_VDI_LEN, tag, SD_MAX_VDI_TAG_LEN); ^~ If this is the intended behavior, please suppress the warning. For example: #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wstringop-truncation" strncpy(buf + SD_MAX_VDI_LEN, tag, SD_MAX_VDI_TAG_LEN); #pragma GCC diagnostic pop To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1803872/+subscriptions
[Qemu-devel] [Bug 1803872] Re: gcc 8.2 reports stringop-truncation when building qemu
** Description changed: QEMU 3.0 block/sheepdog.c: In function 'find_vdi_name': block/sheepdog.c:1239:5: error: 'strncpy' specified bound 256 equals destination size [-Werror=stringop-truncation] - strncpy(buf + SD_MAX_VDI_LEN, tag, SD_MAX_VDI_TAG_LEN); - ^~ + strncpy(buf + SD_MAX_VDI_LEN, tag, SD_MAX_VDI_TAG_LEN); + ^~ - - If this is the intended behavior, please suppress the warning. For example: + If this is the intended behavior, please suppress the warning. For + example: #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wstringop-truncation" - strncpy(buf + SD_MAX_VDI_LEN, tag, SD_MAX_VDI_TAG_LEN); + strncpy(buf + SD_MAX_VDI_LEN, tag, SD_MAX_VDI_TAG_LEN); #pragma GCC diagnostic pop + + This also happens on other sources, for example hw/acpi/core.c, so + another option is to suppress it globally on CFLAGS (-Wno-stringop- + truncation) -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1803872 Title: gcc 8.2 reports stringop-truncation when building qemu Status in QEMU: New Bug description: QEMU 3.0 block/sheepdog.c: In function 'find_vdi_name': block/sheepdog.c:1239:5: error: 'strncpy' specified bound 256 equals destination size [-Werror=stringop-truncation] strncpy(buf + SD_MAX_VDI_LEN, tag, SD_MAX_VDI_TAG_LEN); ^~ If this is the intended behavior, please suppress the warning. For example: #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wstringop-truncation" strncpy(buf + SD_MAX_VDI_LEN, tag, SD_MAX_VDI_TAG_LEN); #pragma GCC diagnostic pop This also happens on other sources, for example hw/acpi/core.c, so another option is to suppress it globally on CFLAGS (-Wno-stringop- truncation) To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1803872/+subscriptions
