Re: [Qemu-devel] [PATCH] target-tilegx: Implement prefetch instructions in pipe y2
On 10/23/15 01:53, Richard Henderson wrote: > On 10/20/2015 05:26 AM, Chen Gang wrote: >>> From 14fe2a651b3f5729f1d402dfcd6eb5f7da0f42b1 Mon Sep 17 00:00:00 2001 >> From: Chen Gang <gang.chen.5...@gmail.com> >> Date: Tue, 20 Oct 2015 23:19:02 +0800 >> Subject: [PATCH] target-tilegx: Implement prefetch instructions in pipe y2 >> >> Originally, tilegx qemu only implement prefetch instructions in pipe x1, >> did not implement them in pipe y2. >> >> Signed-off-by: Chen Gang <gang.chen.5...@gmail.com> > > Applied. > OK, thanks. And at present, I am trying to implement floating point insns within this month. Hope I can succeed. Welcome any members' additional ideas, suggestions, and completions. Thanks. -- Chen Gang (陈刚) Open, share, and attitude like air, water, and life which God blessed
[Qemu-devel] [PATCH] target-tilegx: Implement prefetch instructions in pipe y2
>From 14fe2a651b3f5729f1d402dfcd6eb5f7da0f42b1 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Tue, 20 Oct 2015 23:19:02 +0800
Subject: [PATCH] target-tilegx: Implement prefetch instructions in pipe y2
Originally, tilegx qemu only implement prefetch instructions in pipe x1,
did not implement them in pipe y2.
Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
---
target-tilegx/translate.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 34d45f8..b8ca401 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -2105,6 +2105,7 @@ static TileExcp decode_y2(DisasContext *dc,
tilegx_bundle_bits bundle)
unsigned srcbdest = get_SrcBDest_Y2(bundle);
const char *mnemonic;
TCGMemOp memop;
+ bool prefetch_nofault = false;
switch (OEY2(opc, mode)) {
case OEY2(LD1S_OPCODE_Y2, MODE_OPCODE_YA2):
@@ -2114,6 +2115,7 @@ static TileExcp decode_y2(DisasContext *dc,
tilegx_bundle_bits bundle)
case OEY2(LD1U_OPCODE_Y2, MODE_OPCODE_YA2):
memop = MO_UB;
mnemonic = "ld1u";
+ prefetch_nofault = (srcbdest == TILEGX_R_ZERO);
goto do_load;
case OEY2(LD2S_OPCODE_Y2, MODE_OPCODE_YA2):
memop = MO_TESW;
@@ -2122,6 +2124,7 @@ static TileExcp decode_y2(DisasContext *dc,
tilegx_bundle_bits bundle)
case OEY2(LD2U_OPCODE_Y2, MODE_OPCODE_YA2):
memop = MO_TEUW;
mnemonic = "ld2u";
+ prefetch_nofault = (srcbdest == TILEGX_R_ZERO);
goto do_load;
case OEY2(LD4S_OPCODE_Y2, MODE_OPCODE_YB2):
memop = MO_TESL;
@@ -2130,13 +2133,16 @@ static TileExcp decode_y2(DisasContext *dc,
tilegx_bundle_bits bundle)
case OEY2(LD4U_OPCODE_Y2, MODE_OPCODE_YB2):
memop = MO_TEUL;
mnemonic = "ld4u";
+ prefetch_nofault = (srcbdest == TILEGX_R_ZERO);
goto do_load;
case OEY2(LD_OPCODE_Y2, MODE_OPCODE_YB2):
memop = MO_TEQ;
mnemonic = "ld";
do_load:
- tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca),
- dc->mmuidx, memop);
+ if (!prefetch_nofault) {
+ tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca),
+ dc->mmuidx, memop);
+ }
qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
reg_names[srcbdest], reg_names[srca]);
return TILEGX_EXCP_NONE;
--
1.9.3
0001-target-tilegx-Implement-prefetch-instructions-in-pip.patch
Description: Binary data
[Qemu-devel] [PATCH] temporary-floating-point: Use "0 - val" for the negtive value
>From 5bfae9eaa7c6757c83b1b3d958dd24988394fb03 Mon Sep 17 00:00:00 2001 From: Chen Gang <gang.chen.5...@gmail.com> Date: Sat, 17 Oct 2015 21:39:25 +0800 Subject: [PATCH] temporary-floating-point: Use "0 - val" for the negtive value It is a bug, original implementation is incorrect. Signed-off-by: Chen Gang <gang.chen.5...@gmail.com> --- target-tilegx/fpu_helper.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target-tilegx/fpu_helper.c b/target-tilegx/fpu_helper.c index 095085d..4aafda4 100644 --- a/target-tilegx/fpu_helper.c +++ b/target-tilegx/fpu_helper.c @@ -23,7 +23,6 @@ #include "exec/helper-proto.h" #include "fpu/softfloat.h" -#define SIGNBIT32 0x8000 #define FP_STATUS (fpu->fp_status) static void fdouble_ana(FPUTLGState *fpu, @@ -129,8 +128,7 @@ uint64_t helper_fdouble_pack1(CPUTLGState *env, case 0x21b00: return float64_val(uint32_to_float64(rsrc>> 4, _STATUS)); case 0x121b00: - return float64_val(int32_to_float64((rsrc>> 4) | SIGNBIT32, - _STATUS)); + return float64_val(int32_to_float64(0 - (rsrc>> 4), _STATUS)); default: qemu_log_mask(LOG_UNIMP, "\nUIMP: in %s.\n", __FUNCTION__); helper_exception(env, TILEGX_EXCP_OPCODE_UNIMPLEMENTED); @@ -217,7 +215,7 @@ uint64_t helper_fsingle_pack2(CPUTLGState *env, uint64_t rsrc) case 0x9e: return float32_val(uint32_to_float32(ctx.data, _STATUS)); case 0x49e: - return float32_val(int32_to_float32(ctx.data | SIGNBIT32, _STATUS)); + return float32_val(int32_to_float32(0 - ctx.data, _STATUS)); default: qemu_log_mask(LOG_UNIMP, "\nUIMP: in %s.\n", __FUNCTION__); helper_exception(env, TILEGX_EXCP_OPCODE_UNIMPLEMENTED); -- 1.9.3 0001-temporary-floating-point-Use-0-val-for-the-negtive-v.patch Description: Binary data
Re: [Qemu-devel] [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register
Hello all: It looks I have to spend quite a few free time resources on tilegx gcc testsuite issues, next (may 2-3 months at least, I guess). So for tilegx qemu, I guess, I need to start to implement the floating point, at present. I shall try to finish within this month (although it seems not quite easy to me). By the way, excuse me, my English is not quite well, so: - I have to try to 'speak' as clearly as I can, so sometimes what I said may be not quite polite, please understand. - If any members find any issues/bugs which may be related with me, please say directly and clearly (or sometimes, I maybe misunderstand, then waste our time resources). Thanks. On 10/10/15 06:50, Chen Gang wrote: > > On 10/10/15 06:10, Richard Henderson wrote: >> On 10/09/2015 09:48 AM, Chen Gang wrote: >>> On 10/7/15 18:17, Chen Gang wrote: >>>> On 10/7/15 17:19, Richard Henderson wrote: >>>>> On 10/04/2015 10:15 PM, Chen Gang wrote: >>>>>>> From 40ec3f1c75b4c97e3e0495c9e465be898f48a652 Mon Sep 17 00:00:00 2001 >>>>>> From: Chen Gang<gang.chen.5...@gmail.com> >>>>>> Date: Sun, 4 Oct 2015 17:34:17 +0800 >>>>>> Subject: [PATCH] target-tilegx: Let prefetch nop instructions return >>>>>> before allocating dest temporary register >>>>>> >>>>>> Or it will cause issue by the dest temporary registers. >>>>>> >>>>>> Signed-off-by: Chen Gang<gang.chen.5...@gmail.com> >>>>>> --- >>>>>> target-tilegx/translate.c | 85 >>>>>> +-- >>>>>> 1 file changed, 46 insertions(+), 39 deletions(-) >>>>> >>>>> Isn't my patch 14/14 from the last patch set sufficient? >>>>> >>> >>> At present, all patches (include 14/14) are integrated into master tree, >>> so I guess, we have to integrate this patch into master tree next, it >>> fix the dest temporary registers' issue. >> >> What issue? The prefetch instructions "load" to the zero register, >> which is never written back to the register file. >> > > OK, really. But for me, the code is very easy to lead other members to > make mistakes. > > Thanks. > -- Chen Gang (陈刚) Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register
On 10/10/15 06:10, Richard Henderson wrote: > On 10/09/2015 09:48 AM, Chen Gang wrote: >> On 10/7/15 18:17, Chen Gang wrote: >>> On 10/7/15 17:19, Richard Henderson wrote: >>>> On 10/04/2015 10:15 PM, Chen Gang wrote: >>>>>> From 40ec3f1c75b4c97e3e0495c9e465be898f48a652 Mon Sep 17 00:00:00 2001 >>>>> From: Chen Gang<gang.chen.5...@gmail.com> >>>>> Date: Sun, 4 Oct 2015 17:34:17 +0800 >>>>> Subject: [PATCH] target-tilegx: Let prefetch nop instructions return >>>>> before allocating dest temporary register >>>>> >>>>> Or it will cause issue by the dest temporary registers. >>>>> >>>>> Signed-off-by: Chen Gang<gang.chen.5...@gmail.com> >>>>> --- >>>>> target-tilegx/translate.c | 85 >>>>> +-- >>>>> 1 file changed, 46 insertions(+), 39 deletions(-) >>>> >>>> Isn't my patch 14/14 from the last patch set sufficient? >>>> >> >> At present, all patches (include 14/14) are integrated into master tree, >> so I guess, we have to integrate this patch into master tree next, it >> fix the dest temporary registers' issue. > > What issue? The prefetch instructions "load" to the zero register, > which is never written back to the register file. > OK, really. But for me, the code is very easy to lead other members to make mistakes. Thanks. -- Chen Gang (陈刚) Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register
On 10/7/15 18:17, Chen Gang wrote: > On 10/7/15 17:19, Richard Henderson wrote: >> On 10/04/2015 10:15 PM, Chen Gang wrote: >>>> From 40ec3f1c75b4c97e3e0495c9e465be898f48a652 Mon Sep 17 00:00:00 2001 >>> From: Chen Gang<gang.chen.5...@gmail.com> >>> Date: Sun, 4 Oct 2015 17:34:17 +0800 >>> Subject: [PATCH] target-tilegx: Let prefetch nop instructions return before >>> allocating dest temporary register >>> >>> Or it will cause issue by the dest temporary registers. >>> >>> Signed-off-by: Chen Gang<gang.chen.5...@gmail.com> >>> --- >>> target-tilegx/translate.c | 85 >>> +-- >>> 1 file changed, 46 insertions(+), 39 deletions(-) >> >> Isn't my patch 14/14 from the last patch set sufficient? >> At present, all patches (include 14/14) are integrated into master tree, so I guess, we have to integrate this patch into master tree next, it fix the dest temporary registers' issue. > > It is related with your patch 14/14. If possible, for me, we can merge > them together. > Thanks. -- Chen Gang (陈刚) Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH v2] temp-floating-point: Use make_float32/64 and float32/64_val for the input register values
On 10/7/15 17:29, Richard Henderson wrote: > On 10/07/2015 01:56 AM, Chen Gang wrote: >>> From 3655bbab04063bc0878510ab260832c7a6a2a925 Mon Sep 17 00:00:00 2001 >> From: Chen Gang<gang.chen.5...@gmail.com> >> Date: Tue, 6 Oct 2015 21:45:11 +0800 >> Subject: [PATCH v2] temp-floating-point: Use make_float32/64 and >> float32/64_val for the input register values >> >> Original implementation use int*_to_float32 and float32_to_int*, which >> will generate incorrect result. >> >> Also remove t_to_float64 and float64_to_t, use make_float64 and float64 >> instead of. >> >> Signed-off-by: Chen Gang<gang.chen.5...@gmail.com> >> --- >> target-tilegx/fpu_helper.c | 63 >> +++--- >> 1 file changed, 15 insertions(+), 48 deletions(-) > > This is relative to... what? The v1 patch? > Yes, it is related with v1 patch (has the same name). The v1 patch is based on patch "target-tilegx: Implement floating point temporarily". Since they are temporary implementations, I guess, we can just left it (do not integrate them into main line). I sent these temporary implementations, because if someone need test qemu tilegx, they can use these temporary patches (but of cause, I am very glad if they can be integrated into main line, too). Thanks. -- Chen Gang (陈刚) Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register
On 10/7/15 17:19, Richard Henderson wrote: > On 10/04/2015 10:15 PM, Chen Gang wrote: >>> From 40ec3f1c75b4c97e3e0495c9e465be898f48a652 Mon Sep 17 00:00:00 2001 >> From: Chen Gang<gang.chen.5...@gmail.com> >> Date: Sun, 4 Oct 2015 17:34:17 +0800 >> Subject: [PATCH] target-tilegx: Let prefetch nop instructions return before >> allocating dest temporary register >> >> Or it will cause issue by the dest temporary registers. >> >> Signed-off-by: Chen Gang<gang.chen.5...@gmail.com> >> --- >> target-tilegx/translate.c | 85 >> +-- >> 1 file changed, 46 insertions(+), 39 deletions(-) > > Isn't my patch 14/14 from the last patch set sufficient? > It is related with your patch 14/14. If possible, for me, we can merge them together. Thanks. -- Chen Gang (陈刚) Open, share, and attitude like air, water, and life which God blessed
[Qemu-devel] [PATCH v5] target-tilegx: Support iret instruction and related special registers
>From fa0950e403bbb98989117f632215ae0e698457d7 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Sun, 4 Oct 2015 17:41:14 +0800
Subject: [PATCH v5] target-tilegx: Support iret instruction and related special
registers
Acording to the __longjmp tilegx libc implementation, and reference from
tilegx ISA document, and suggested by tilegx architecture member, we can
treat iret instruction as "jrp lr". The related code is below:
ENTRY (__longjmp)
FEEDBACK_ENTER(__longjmp)
#define RESTORE(r) { LD r, r0 ; ADDI_PTR r0, r0, REGSIZE }
FOR_EACH_CALLEE_SAVED_REG(RESTORE)
{
LD r2, r0 ; retrieve ICS bit from jmp_buf
movei r3, 1
CMPEQI r0, r1, 0
}
{
mtspr INTERRUPT_CRITICAL_SECTION, r3
shli r2, r2, SPR_EX_CONTEXT_0_1__ICS_SHIFT
}
{
mtspr EX_CONTEXT_0_0, lr
ori r2, r2, RETURN_PL
}
{
or r0, r1, r0
mtspr EX_CONTEXT_0_1, r2
}
iret
jrp lr
EX_CONTEXT_0_0 is used for jumping address, and EX_CONTEXT_0_1 is for
INTERRUPT_CRITICAL_SECTION, which should only be 0 or 1 in user mode, or
it will cause target SEGV (and the patch doesn't implement system mode).
iret will "jrp EX_CONTEXT_0_0", for __longjmp, it is lr (but in other
cases, it may be not). And the last "jrp lr" in __longjmp is for
historical reasons, and might get removed in the future.
Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
---
target-tilegx/cpu.h | 2 ++
target-tilegx/helper.c | 22 ++
target-tilegx/helper.h | 1 +
target-tilegx/translate.c | 14 +-
4 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
index 6f04fe7..6c0fd53 100644
--- a/target-tilegx/cpu.h
+++ b/target-tilegx/cpu.h
@@ -53,6 +53,8 @@ enum {
TILEGX_SPR_CMPEXCH = 0,
TILEGX_SPR_CRITICAL_SEC = 1,
TILEGX_SPR_SIM_CONTROL = 2,
+ TILEGX_SPR_EX_CONTEXT_0_0 = 3,
+ TILEGX_SPR_EX_CONTEXT_0_1 = 4,
TILEGX_SPR_COUNT
};
diff --git a/target-tilegx/helper.c b/target-tilegx/helper.c
index 36b287f..dda821f 100644
--- a/target-tilegx/helper.c
+++ b/target-tilegx/helper.c
@@ -22,6 +22,7 @@
#include "qemu-common.h"
#include "exec/helper-proto.h"
#include /* For crc32 */
+#include "syscall_defs.h"
void helper_exception(CPUTLGState *env, uint32_t excp)
{
@@ -31,6 +32,27 @@ void helper_exception(CPUTLGState *env, uint32_t excp)
cpu_loop_exit(cs);
}
+void helper_ext01_ics(CPUTLGState *env)
+{
+ uint64_t val = env->spregs[TILEGX_SPR_EX_CONTEXT_0_1];
+
+ switch (val) {
+ case 0:
+ case 1:
+ env->spregs[TILEGX_SPR_CRITICAL_SEC] = val;
+ break;
+ default:
+#if defined(CONFIG_USER_ONLY)
+ env->signo = TARGET_SIGILL;
+ env->sigcode = TARGET_ILL_ILLOPC;
+ helper_exception(env, TILEGX_EXCP_SIGNAL);
+#else
+ helper_exception(env, TILEGX_EXCP_OPCODE_UNIMPLEMENTED);
+#endif
+ break;
+ }
+}
+
uint64_t helper_cntlz(uint64_t arg)
{
return clz64(arg);
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
index bbcc476..9281d0f 100644
--- a/target-tilegx/helper.h
+++ b/target-tilegx/helper.h
@@ -1,4 +1,5 @@
DEF_HELPER_2(exception, noreturn, env, i32)
+DEF_HELPER_1(ext01_ics, void, env)
DEF_HELPER_FLAGS_1(cntlz, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(cnttz, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(pcnt, TCG_CALL_NO_RWG_SE, i64, i64)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index ab3fc81..acb9ec4 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -529,6 +529,15 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
/* ??? This should yield, especially in system mode. */
mnemonic = "nap";
goto done0;
+ case OE_RR_X1(IRET):
+ gen_helper_ext01_ics(cpu_env);
+ dc->jmp.cond = TCG_COND_ALWAYS;
+ dc->jmp.dest = tcg_temp_new();
+ tcg_gen_ld_tl(dc->jmp.dest, cpu_env,
+ offsetof(CPUTLGState,
spregs[TILEGX_SPR_EX_CONTEXT_0_0]));
+ tcg_gen_andi_tl(dc->jmp.dest, dc->jmp.dest, ~7);
+ mnemonic = "iret";
+ goto done0;
case OE_RR_X1(SWINT0):
case OE_RR_X1(SWINT2):
case OE_RR_X1(SWINT3):
@@ -606,7 +615,6 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
break;
case OE_RR_X0(FSINGLE_PACK1):
case OE_RR_Y0(FSINGLE_PACK1):
- case OE_RR_X1(IRET):
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RR_X1(LD1S):
memop = MO_SB;
@@ -1947,6 +1955,10 @@ static const TileSPR *find_spr(unsigned spr)
offsetof(CPUTLGState, spregs[TILEGX_SPR_CRITICAL_SEC]), 0, 0)
D(SIM_CONTROL,
offsetof(CPUTLGState, spregs[TI
Re: [Qemu-devel] [PATCH v5] target-tilegx: Support iret instruction and related special registers
Oh, sorry. I will send patch v6 for it.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
> Subject: Re: [PATCH v5] target-tilegx: Support iret instruction and related
> special registers
> To: xili_gchen_5...@hotmail.com; r...@twiddle.net; peter.mayd...@linaro.org
> CC: qemu-devel@nongnu.org
> From: cmetc...@ezchip.com
> Date: Tue, 6 Oct 2015 12:13:34 -0400
>
> Comments just on the commit message:
>
> On 10/06/2015 10:55 AM, Chen Gang wrote:
>> From fa0950e403bbb98989117f632215ae0e698457d7 Mon Sep 17 00:00:00 2001
>> From: Chen Gang <gang.chen.5...@gmail.com>
>> Date: Sun, 4 Oct 2015 17:41:14 +0800
>> Subject: [PATCH v5] target-tilegx: Support iret instruction and related
>> special registers
>>
>> Acording to the __longjmp tilegx libc implementation, and reference from
>> tilegx ISA document, and suggested by tilegx architecture member, we can
>> treat iret instruction as "jrp lr".
>
> You need to update this comment to reflect the actual code in the
> commit. You aren't treating iret as jrp lr anymore.
>
>> The related code is below:
>>
>> ENTRY (__longjmp)
>> FEEDBACK_ENTER(__longjmp)
>>
>> #define RESTORE(r) { LD r, r0 ; ADDI_PTR r0, r0, REGSIZE }
>> FOR_EACH_CALLEE_SAVED_REG(RESTORE)
>>
>> {
>> LD r2, r0 ; retrieve ICS bit from jmp_buf
>> movei r3, 1
>> CMPEQI r0, r1, 0
>> }
>>
>> {
>> mtspr INTERRUPT_CRITICAL_SECTION, r3
>> shli r2, r2, SPR_EX_CONTEXT_0_1__ICS_SHIFT
>> }
>>
>> {
>> mtspr EX_CONTEXT_0_0, lr
>> ori r2, r2, RETURN_PL
>> }
>>
>> {
>> or r0, r1, r0
>> mtspr EX_CONTEXT_0_1, r2
>> }
>>
>> iret
>>
>> jrp lr
>
> I don't think this code snippet is helpful to the commit message.
>
>> EX_CONTEXT_0_0 is used for jumping address, and EX_CONTEXT_0_1 is for
>> INTERRUPT_CRITICAL_SECTION, which should only be 0 or 1 in user mode, or
>> it will cause target SEGV (and the patch doesn't implement system mode).
>
> You correctly modified the change to raise SIGILL, so you should
> also update the commit message the same way.
>
> --
> Chris Metcalf, EZChip Semiconductor
> http://www.ezchip.com
>
[Qemu-devel] [PATCH v6] target-tilegx: Support iret instruction and related special registers
>From fa0950e403bbb98989117f632215ae0e698457d7 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Sun, 4 Oct 2015 17:41:14 +0800
Subject: [PATCH v6] target-tilegx: Support iret instruction and related special
registers
EX_CONTEXT_0_0 is used for jumping address, and EX_CONTEXT_0_1 is for
INTERRUPT_CRITICAL_SECTION, which should only be 0 or 1 in user mode, or
it will cause target SIGILL (and the patch doesn't support system mode).
Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
---
target-tilegx/cpu.h | 2 ++
target-tilegx/helper.c | 22 ++
target-tilegx/helper.h | 1 +
target-tilegx/translate.c | 14 +-
4 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
index 6f04fe7..6c0fd53 100644
--- a/target-tilegx/cpu.h
+++ b/target-tilegx/cpu.h
@@ -53,6 +53,8 @@ enum {
TILEGX_SPR_CMPEXCH = 0,
TILEGX_SPR_CRITICAL_SEC = 1,
TILEGX_SPR_SIM_CONTROL = 2,
+ TILEGX_SPR_EX_CONTEXT_0_0 = 3,
+ TILEGX_SPR_EX_CONTEXT_0_1 = 4,
TILEGX_SPR_COUNT
};
diff --git a/target-tilegx/helper.c b/target-tilegx/helper.c
index 36b287f..dda821f 100644
--- a/target-tilegx/helper.c
+++ b/target-tilegx/helper.c
@@ -22,6 +22,7 @@
#include "qemu-common.h"
#include "exec/helper-proto.h"
#include /* For crc32 */
+#include "syscall_defs.h"
void helper_exception(CPUTLGState *env, uint32_t excp)
{
@@ -31,6 +32,27 @@ void helper_exception(CPUTLGState *env, uint32_t excp)
cpu_loop_exit(cs);
}
+void helper_ext01_ics(CPUTLGState *env)
+{
+ uint64_t val = env->spregs[TILEGX_SPR_EX_CONTEXT_0_1];
+
+ switch (val) {
+ case 0:
+ case 1:
+ env->spregs[TILEGX_SPR_CRITICAL_SEC] = val;
+ break;
+ default:
+#if defined(CONFIG_USER_ONLY)
+ env->signo = TARGET_SIGILL;
+ env->sigcode = TARGET_ILL_ILLOPC;
+ helper_exception(env, TILEGX_EXCP_SIGNAL);
+#else
+ helper_exception(env, TILEGX_EXCP_OPCODE_UNIMPLEMENTED);
+#endif
+ break;
+ }
+}
+
uint64_t helper_cntlz(uint64_t arg)
{
return clz64(arg);
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
index bbcc476..9281d0f 100644
--- a/target-tilegx/helper.h
+++ b/target-tilegx/helper.h
@@ -1,4 +1,5 @@
DEF_HELPER_2(exception, noreturn, env, i32)
+DEF_HELPER_1(ext01_ics, void, env)
DEF_HELPER_FLAGS_1(cntlz, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(cnttz, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(pcnt, TCG_CALL_NO_RWG_SE, i64, i64)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index ab3fc81..acb9ec4 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -529,6 +529,15 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
/* ??? This should yield, especially in system mode. */
mnemonic = "nap";
goto done0;
+ case OE_RR_X1(IRET):
+ gen_helper_ext01_ics(cpu_env);
+ dc->jmp.cond = TCG_COND_ALWAYS;
+ dc->jmp.dest = tcg_temp_new();
+ tcg_gen_ld_tl(dc->jmp.dest, cpu_env,
+ offsetof(CPUTLGState,
spregs[TILEGX_SPR_EX_CONTEXT_0_0]));
+ tcg_gen_andi_tl(dc->jmp.dest, dc->jmp.dest, ~7);
+ mnemonic = "iret";
+ goto done0;
case OE_RR_X1(SWINT0):
case OE_RR_X1(SWINT2):
case OE_RR_X1(SWINT3):
@@ -606,7 +615,6 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
break;
case OE_RR_X0(FSINGLE_PACK1):
case OE_RR_Y0(FSINGLE_PACK1):
- case OE_RR_X1(IRET):
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RR_X1(LD1S):
memop = MO_SB;
@@ -1947,6 +1955,10 @@ static const TileSPR *find_spr(unsigned spr)
offsetof(CPUTLGState, spregs[TILEGX_SPR_CRITICAL_SEC]), 0, 0)
D(SIM_CONTROL,
offsetof(CPUTLGState, spregs[TILEGX_SPR_SIM_CONTROL]), 0, 0)
+ D(EX_CONTEXT_0_0,
+ offsetof(CPUTLGState, spregs[TILEGX_SPR_EX_CONTEXT_0_0]), 0, 0)
+ D(EX_CONTEXT_0_1,
+ offsetof(CPUTLGState, spregs[TILEGX_SPR_EX_CONTEXT_0_1]), 0, 0)
}
#undef D
--
1.9.3
0001-target-tilegx-Support-iret-instruction-and-related-s.patch
Description: Binary data
[Qemu-devel] [PATCH v2] temp-floating-point: Use make_float32/64 and float32/64_val for the input register values
>From 3655bbab04063bc0878510ab260832c7a6a2a925 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Tue, 6 Oct 2015 21:45:11 +0800
Subject: [PATCH v2] temp-floating-point: Use make_float32/64 and float32/64_val
for the input register values
Original implementation use int*_to_float32 and float32_to_int*, which
will generate incorrect result.
Also remove t_to_float64 and float64_to_t, use make_float64 and float64
instead of.
Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
---
target-tilegx/fpu_helper.c | 63 +++---
1 file changed, 15 insertions(+), 48 deletions(-)
diff --git a/target-tilegx/fpu_helper.c b/target-tilegx/fpu_helper.c
index daae570..095085d 100644
--- a/target-tilegx/fpu_helper.c
+++ b/target-tilegx/fpu_helper.c
@@ -54,20 +54,6 @@ static void fdouble_ana(FPUTLGState *fpu,
}
}
-static float64 t_to_float64(uint64_t a)
-{
- CPU_DoubleU r;
- r.ll = a;
- return r.d;
-}
-
-static uint64_t float64_to_t(float64 fa)
-{
- CPU_DoubleU r;
- r.d = fa;
- return r.ll;
-}
-
static uint64_t ctx_to_uint64(TileGXFPCtx a)
{
union {
@@ -108,21 +94,21 @@ static uint64_t fdouble_calc(FPUTLGState *fpu,
uint64_t helper_fdouble_add_flags(CPUTLGState *env,
uint64_t rsrc, uint64_t rsrcb)
{
- return fdouble_calc(>fpu, t_to_float64(rsrc), t_to_float64(rsrcb),
+ return fdouble_calc(>fpu, make_float64(rsrc), make_float64(rsrcb),
float64_add);
}
uint64_t helper_fdouble_sub_flags(CPUTLGState *env,
uint64_t rsrc, uint64_t rsrcb)
{
- return fdouble_calc(>fpu, t_to_float64(rsrc), t_to_float64(rsrcb),
+ return fdouble_calc(>fpu, make_float64(rsrc), make_float64(rsrcb),
float64_sub);
}
uint64_t helper_fdouble_mul_flags(CPUTLGState *env,
uint64_t rsrc, uint64_t rsrcb)
{
- return fdouble_calc(>fpu, t_to_float64(rsrc), t_to_float64(rsrcb),
+ return fdouble_calc(>fpu, make_float64(rsrc), make_float64(rsrcb),
float64_mul);
}
@@ -136,17 +122,17 @@ uint64_t helper_fdouble_pack1(CPUTLGState *env,
if (ctx.data>= TILEGX_F_COUNT) {
helper_exception(env, TILEGX_EXCP_OPCODE_INVALID_VALUE);
}
- return float64_to_t(fpu->val64s[ctx.data]);
+ return float64_val(fpu->val64s[ctx.data]);
}
switch (ctx.exp) {
case 0x21b00:
- return float64_to_t(uint32_to_float64(rsrc>> 4, _STATUS));
+ return float64_val(uint32_to_float64(rsrc>> 4, _STATUS));
case 0x121b00:
- return float64_to_t(int32_to_float64((rsrc>> 4) | SIGNBIT32,
- _STATUS));
+ return float64_val(int32_to_float64((rsrc>> 4) | SIGNBIT32,
+ _STATUS));
default:
- fprintf(stderr, "\nUIMP: in helper_fdouble_pack2().\n");
+ qemu_log_mask(LOG_UNIMP, "\nUIMP: in %s.\n", __FUNCTION__);
helper_exception(env, TILEGX_EXCP_OPCODE_UNIMPLEMENTED);
return 0;
}
@@ -199,35 +185,19 @@ static uint64_t fsingle_calc(FPUTLGState *fpu,
uint64_t helper_fsingle_add1(CPUTLGState *env, uint64_t rsrc, uint64_t rsrcb)
{
- FPUTLGState *fpu = >fpu;
- return fsingle_calc(fpu, int64_to_float32(rsrc, _STATUS),
- int64_to_float32(rsrcb, _STATUS),
+ return fsingle_calc(>fpu, make_float32(rsrc), make_float32(rsrcb),
float32_add);
}
uint64_t helper_fsingle_sub1(CPUTLGState *env, uint64_t rsrc, uint64_t rsrcb)
{
- FPUTLGState *fpu = >fpu;
- return fsingle_calc(fpu, int64_to_float32(rsrc, _STATUS),
- int64_to_float32(rsrcb, _STATUS),
+ return fsingle_calc(>fpu, make_float32(rsrc), make_float32(rsrcb),
float32_sub);
}
uint64_t helper_fsingle_mul1(CPUTLGState *env, uint64_t rsrc, uint64_t rsrcb)
{
- FPUTLGState *fpu = >fpu;
-#if 0
- {
- float32 v;
- fprintf(stderr, "\ncall helper_fsingle_mul1(), %lx, %lx\n", rsrc,
rsrcb);
- v = float32_mul(int64_to_float32(rsrc, _STATUS),
- int64_to_float32(rsrcb, _STATUS),
- _STATUS);
- fprintf(stderr, "result: %lx.\n", float32_to_int64(v, _STATUS));
- }
-#endif
- return fsingle_calc(fpu, int64_to_float32(rsrc, _STATUS),
- int64_to_float32(rsrcb, _STATUS),
+ return fsingle_calc(>fpu, make_float32(rsrc), make_float32(rsrcb),
float32_mul);
}
@@ -240,19 +210,16 @@ uint64_t helper_fsingle_pack2(CPUTLGState *env, uint64_t
rsrc)
if (ctx.data>= TILEGX_F_COUNT) {
helper_exception(env, TILEGX_EXCP_OPCODE_INVALID_VALUE);
}
- return float32_to_int32(fpu-&
Re: [Qemu-devel] [PATCH] temp-floating-point: Use float32_to_t and t_to_float32 for the input register value
> On 5 October 2015 at 12:21, Chen Gang <xili_gchen_5...@hotmail.com> wrote:
>> +static float32 t_to_float32 (uint32_t a)
>> +{
>> + CPU_FloatU r;
>> + r.l = a;
>> + return r.f;
>> +}
>
> This appears to be reimplementing make_float32().
>
OK, thanks.
>> +
>> +static uint32_t float32_to_t(float32 a)
>> +{
>> + CPU_FloatU r;
>> + r.f = a;
>> + return r.l;
>> +}
>
> And this is just float32_val().
>
OK, thanks.
>> uint64_t helper_fsingle_add1(CPUTLGState *env, uint64_t rsrc, uint64_t rsrcb)
>> {
>> - FPUTLGState *fpu = >fpu;
>> - return fsingle_calc(fpu, int64_to_float32(rsrc, _STATUS),
>> - int64_to_float32(rsrcb, _STATUS),
>> - float32_add);
>> + return fsingle_calc(>fpu, t_to_float32((uint32_t)rsrc),
>> + t_to_float32((uint32_t)rsrcb), float32_add);
>> }
>
> Why is the helper for a single-precision operation taking a 64-bit
> argument anyway?
>
Oh, the register are uint64_t, so I guess the input register value are 64-bit,
too.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH] temp-floating-point: Use float32_to_t and t_to_float32 for the input register value
> From: peter.mayd...@linaro.org > On 5 October 2015 at 12:54, Chen Gang <xili_gchen_5...@hotmail.com> wrote: >>> On 5 October 2015 at 12:21, Chen Gang <xili_gchen_5...@hotmail.com> wrote: >>> Why is the helper for a single-precision operation taking a 64-bit >>> argument anyway? >>> >> >> Oh, the register are uint64_t, so I guess the input register value are >> 64-bit, too. > > Usually for single precision the generated code is also working > with 32-bit values. What you have is not necessarily > wrong, but it is odd. I'd have to check the architecture > manual and the translate.c code to be sure. > OK, thanks. Originally, I referenced alpha and s390x for it. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
[Qemu-devel] [PATCH] temp-floating-point: Use float32_to_t and t_to_float32 for the input register value
>From 6bb2ed5b7046cda545f6a12721b773fde40f07f1 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Mon, 5 Oct 2015 19:12:07 +0800
Subject: [PATCH] temp-floating-point: Use float32_to_t and t_to_float32 for
the input register value
Original implementation use int*_to_float32 and float32_to_int*, which
will generate incorrect result.
Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
---
target-tilegx/fpu_helper.c | 51 +-
1 file changed, 23 insertions(+), 28 deletions(-)
diff --git a/target-tilegx/fpu_helper.c b/target-tilegx/fpu_helper.c
index daae570..2707f30 100644
--- a/target-tilegx/fpu_helper.c
+++ b/target-tilegx/fpu_helper.c
@@ -68,6 +68,20 @@ static uint64_t float64_to_t(float64 fa)
return r.ll;
}
+static float32 t_to_float32 (uint32_t a)
+{
+ CPU_FloatU r;
+ r.l = a;
+ return r.f;
+}
+
+static uint32_t float32_to_t(float32 a)
+{
+ CPU_FloatU r;
+ r.f = a;
+ return r.l;
+}
+
static uint64_t ctx_to_uint64(TileGXFPCtx a)
{
union {
@@ -199,36 +213,20 @@ static uint64_t fsingle_calc(FPUTLGState *fpu,
uint64_t helper_fsingle_add1(CPUTLGState *env, uint64_t rsrc, uint64_t rsrcb)
{
- FPUTLGState *fpu = >fpu;
- return fsingle_calc(fpu, int64_to_float32(rsrc, _STATUS),
- int64_to_float32(rsrcb, _STATUS),
- float32_add);
+ return fsingle_calc(>fpu, t_to_float32((uint32_t)rsrc),
+ t_to_float32((uint32_t)rsrcb), float32_add);
}
uint64_t helper_fsingle_sub1(CPUTLGState *env, uint64_t rsrc, uint64_t rsrcb)
{
- FPUTLGState *fpu = >fpu;
- return fsingle_calc(fpu, int64_to_float32(rsrc, _STATUS),
- int64_to_float32(rsrcb, _STATUS),
- float32_sub);
+ return fsingle_calc(>fpu, t_to_float32((uint32_t)rsrc),
+ t_to_float32((uint32_t)rsrcb), float32_sub);
}
uint64_t helper_fsingle_mul1(CPUTLGState *env, uint64_t rsrc, uint64_t rsrcb)
{
- FPUTLGState *fpu = >fpu;
-#if 0
- {
- float32 v;
- fprintf(stderr, "\ncall helper_fsingle_mul1(), %lx, %lx\n", rsrc,
rsrcb);
- v = float32_mul(int64_to_float32(rsrc, _STATUS),
- int64_to_float32(rsrcb, _STATUS),
- _STATUS);
- fprintf(stderr, "result: %lx.\n", float32_to_int64(v, _STATUS));
- }
-#endif
- return fsingle_calc(fpu, int64_to_float32(rsrc, _STATUS),
- int64_to_float32(rsrcb, _STATUS),
- float32_mul);
+ return fsingle_calc(>fpu, t_to_float32((uint32_t)rsrc),
+ t_to_float32((uint32_t)rsrcb), float32_mul);
}
uint64_t helper_fsingle_pack2(CPUTLGState *env, uint64_t rsrc)
@@ -240,17 +238,14 @@ uint64_t helper_fsingle_pack2(CPUTLGState *env, uint64_t
rsrc)
if (ctx.data>= TILEGX_F_COUNT) {
helper_exception(env, TILEGX_EXCP_OPCODE_INVALID_VALUE);
}
- return float32_to_int32(fpu->val32s[ctx.data], _STATUS);
+ return float32_to_t(fpu->val32s[ctx.data]);
}
switch (ctx.exp) {
case 0x9e:
- return float32_to_int64(uint32_to_float32(ctx.data, _STATUS),
- _STATUS);
+ return float32_to_t(uint32_to_float32(ctx.data, _STATUS));
case 0x49e:
- return float32_to_int64(int32_to_float32(ctx.data | SIGNBIT32,
- _STATUS),
- _STATUS);
+ return float32_to_t(int32_to_float32(ctx.data | SIGNBIT32,
_STATUS));
default:
fprintf(stderr, "\nUIMP: in helper_fsingle_pack2().\n");
helper_exception(env, TILEGX_EXCP_OPCODE_UNIMPLEMENTED);
--
1.9.3
0001-temp-floating-point-Use-float32_to_t-and-t_to_float3.patch
Description: Binary data
[Qemu-devel] [PATCH] target-tilegx: Implement floating point temporarily
>From 4d12af14f361fb5e3a893fc68a599be9ea17d1dc Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Sun, 4 Oct 2015 18:00:53 +0800
Subject: [PATCH] target-tilegx: Implement floating point temporarily
It is a temporary implementation, but it can pass gcc testsuite.
Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
---
target-tilegx/Makefile.objs | 2 +-
target-tilegx/cpu.h | 5 +-
target-tilegx/fpu.h | 149 +
target-tilegx/fpu_helper.c | 259
target-tilegx/helper.h | 9 ++
target-tilegx/translate.c | 70 +---
6 files changed, 479 insertions(+), 15 deletions(-)
create mode 100644 target-tilegx/fpu.h
create mode 100644 target-tilegx/fpu_helper.c
diff --git a/target-tilegx/Makefile.objs b/target-tilegx/Makefile.objs
index 0db778f..1573c36 100644
--- a/target-tilegx/Makefile.objs
+++ b/target-tilegx/Makefile.objs
@@ -1 +1 @@
-obj-y += cpu.o translate.o helper.o simd_helper.o
+obj-y += cpu.o translate.o helper.o simd_helper.o fpu_helper.o
diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
index 6c0fd53..b752ef3 100644
--- a/target-tilegx/cpu.h
+++ b/target-tilegx/cpu.h
@@ -27,7 +27,7 @@
#define CPUArchState struct CPUTLGState
#include "exec/cpu-defs.h"
-
+#include "fpu.h"
/* TILE-Gx common register alias */
#define TILEGX_R_RE 0 /* 0 register, for function/syscall return value */
@@ -77,6 +77,7 @@ typedef enum {
TILEGX_EXCP_OPCODE_FETCHAND4 = 0x10c,
TILEGX_EXCP_OPCODE_FETCHOR = 0x10d,
TILEGX_EXCP_OPCODE_FETCHOR4 = 0x10e,
+ TILEGX_EXCP_OPCODE_INVALID_VALUE = 0x10f,
TILEGX_EXCP_REG_IDN_ACCESS = 0x181,
TILEGX_EXCP_REG_UDN_ACCESS = 0x182,
TILEGX_EXCP_UNALIGNMENT = 0x201,
@@ -88,6 +89,8 @@ typedef struct CPUTLGState {
uint64_t spregs[TILEGX_SPR_COUNT]; /* Special used registers by outside */
uint64_t pc; /* Current pc */
+ FPUTLGState fpu; /* fpu context */
+
#if defined(CONFIG_USER_ONLY)
uint64_t excaddr; /* exception address */
uint64_t atomic_srca; /* Arguments to atomic "exceptions" */
diff --git a/target-tilegx/fpu.h b/target-tilegx/fpu.h
new file mode 100644
index 000..41076bd
--- /dev/null
+++ b/target-tilegx/fpu.h
@@ -0,0 +1,149 @@
+/*
+ * TILE-Gx virtual FPU header
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef FPU_TILEGX_H
+#define FPU_TILEGX_H
+
+/*
+ * Single floaing point instructions decription.
+ *
+ * - fsingle_add1, fsingle_sub1, and fsingle_pack1/2 can be used individually.
+ *
+ * - when fsingle_pack1/2 is used individually, it is for type cast.
+ *
+ * - the old 4Kth result is alrealy useless for caller.
+ *
+ * fsingle_add1 ; make context and calc result from rsrca and rsrcb.
+ * ; save result in roundup array, and add index to
context.
+ * ; move context to rdst.
+ *
+ * fsingle_sub1 ; make context and calc result from rsrca and rsrcb.
+ * ; save result in roundup array, and add index to
context.
+ * ; move context to rdst.
+ *
+ * fsingle_addsub2 ; skipped.
+ *
+ * fsingle_mul1 ; make context and calc result from rsrca and srcb.
+ * ; save result in roundup array, and add index to
context.
+ * ; move context to rdst.
+ *
+ * fsingle_mul2 ; move rsrca to rdst.
+ *
+ * fsingle_pack1 ; skipped.
+ *
+ * fsingle_pack2 ; get context from rsrca (rsrca is context).
+ * ; if context for add/sub/mul
+ * ; get result from roundup array based on index.
+ * ; move result to rdst.
+ * ; else
+ * ; get (u)int32_t interger from context,
+ * ; (u)int32_to_float32.
+ */
+
+/*
+ * Double floating point instructions' description.
+ *
+ * - fdouble_add_flags, fdouble_sub_flags, and fdouble_pack1/2 can be used
+ * individually.
+ *
+ * - when fdouble_pack1/2 is used individually, it is for type cast.
+ *
+ * - the old 4Kth result is alrealy useless for caller.
+ *
+ * fdouble_unpack_ma
[Qemu-devel] [PATCH v2] target-tilegx: Implement v?int_* instructions
>From 418c1600c481f0acbde42987db286b48f1848399 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Fri, 2 Oct 2015 11:00:37 +0800
Subject: [PATCH v2] target-tilegx: Implement v?int_* instructions.
Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
---
target-tilegx/helper.h | 5
target-tilegx/simd_helper.c | 56 +
target-tilegx/translate.c | 14
3 files changed, 75 insertions(+)
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
index 82d84f1..c58ee20 100644
--- a/target-tilegx/helper.h
+++ b/target-tilegx/helper.h
@@ -10,6 +10,11 @@ DEF_HELPER_FLAGS_3(cmula, TCG_CALL_NO_RWG_SE, i64, i64, i64,
i64)
DEF_HELPER_FLAGS_3(cmulaf, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
DEF_HELPER_FLAGS_4(cmul2, TCG_CALL_NO_RWG_SE, i64, i64, i64, int, int)
+DEF_HELPER_FLAGS_2(v1int_h, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v1int_l, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v2int_h, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v2int_l, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+
DEF_HELPER_FLAGS_2(v1multu, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target-tilegx/simd_helper.c b/target-tilegx/simd_helper.c
index 23c20bd..6fa6318 100644
--- a/target-tilegx/simd_helper.c
+++ b/target-tilegx/simd_helper.c
@@ -102,3 +102,59 @@ uint64_t helper_v2shrs(uint64_t a, uint64_t b)
}
return r;
}
+
+uint64_t helper_v1int_h(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0, tmp;
+ int i;
+
+ for (i = 0; i < 32; i += 8) {
+ tmp = (uint8_t)(a>> (i + 32));
+ r |= tmp << (2 * i + 8);
+ tmp = (uint8_t)(b>> (i + 32));
+ r |= tmp << 2 * i;
+ }
+ return r;
+}
+
+uint64_t helper_v1int_l(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0, tmp;
+ int i;
+
+ for (i = 0; i < 32; i += 8) {
+ tmp = (uint8_t)(a>> i);
+ r |= tmp << (2 * i + 8);
+ tmp = (uint8_t)(b>> i);
+ r |= tmp << 2 * i;
+ }
+ return r;
+}
+
+uint64_t helper_v2int_h(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0, tmp;
+ int i;
+
+ for (i = 0; i < 32; i += 16) {
+ tmp = (uint16_t)(a>> (i + 32));
+ r |= tmp << (2 * i + 16);
+ tmp = (uint16_t)(b>> (i + 32));
+ r |= tmp << 2 * i;
+ }
+ return r;
+}
+
+uint64_t helper_v2int_l(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0, tmp;
+ int i;
+
+ for (i = 0; i < 32; i += 16) {
+ tmp = (uint16_t)(a>> i);
+ r |= tmp << (2 * i + 16);
+ tmp = (uint16_t)(b>> i);
+ r |= tmp << 2 * i;
+ }
+ return r;
+}
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 9bb8857..034cbc2 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -1260,10 +1260,17 @@ static TileExcp gen_rrr_opcode(DisasContext *dc,
unsigned opext,
case OE_RRR(V1DOTPUS, 0, X0):
case OE_RRR(V1DOTPU, 0, X0):
case OE_RRR(V1DOTP, 0, X0):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V1INT_H, 0, X0):
case OE_RRR(V1INT_H, 0, X1):
+ gen_helper_v1int_h(tdest, tsrca, tsrcb);
+ mnemonic = "v1int_h";
+ break;
case OE_RRR(V1INT_L, 0, X0):
case OE_RRR(V1INT_L, 0, X1):
+ gen_helper_v1int_l(tdest, tsrca, tsrcb);
+ mnemonic = "v1int_l";
+ break;
case OE_RRR(V1MAXU, 0, X0):
case OE_RRR(V1MAXU, 0, X1):
case OE_RRR(V1MINU, 0, X0):
@@ -1329,10 +1336,17 @@ static TileExcp gen_rrr_opcode(DisasContext *dc,
unsigned opext,
case OE_RRR(V2CMPNE, 0, X1):
case OE_RRR(V2DOTPA, 0, X0):
case OE_RRR(V2DOTP, 0, X0):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V2INT_H, 0, X0):
case OE_RRR(V2INT_H, 0, X1):
+ gen_helper_v2int_h(tdest, tsrca, tsrcb);
+ mnemonic = "v2int_h";
+ break;
case OE_RRR(V2INT_L, 0, X0):
case OE_RRR(V2INT_L, 0, X1):
+ gen_helper_v2int_l(tdest, tsrca, tsrcb);
+ mnemonic = "v2int_l";
+ break;
case OE_RRR(V2MAXS, 0, X0):
case OE_RRR(V2MAXS, 0, X1):
case OE_RRR(V2MINS, 0, X0):
--
1.9.3
0002-target-tilegx-Implement-v-int_-instructions.patch
Description: Binary data
[Qemu-devel] [PATCH v2] target-tilegx: Implement v2sh* instructions
>From be4b6be54c79d9ca22431f749f31e0c7b9fdd091 Mon Sep 17 00:00:00 2001 From: Chen Gang <gang.chen.5...@gmail.com> Date: Fri, 2 Oct 2015 09:19:56 +0800 Subject: [PATCH v2] target-tilegx: Implement v2sh* instructions It is just according to v1sh* instructions implementation. Signed-off-by: Chen Gang <gang.chen.5...@gmail.com> --- target-tilegx/translate.c | 18 +- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 6ab66f9..9bb8857 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -1686,11 +1686,27 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext, break; case OE_SH(V2SHLI, X0): case OE_SH(V2SHLI, X1): + i2 = imm & 15; + i3 = 0x>> i2; + tcg_gen_andi_tl(tdest, tsrca, V2_IMM(i3)); + tcg_gen_shli_tl(tdest, tdest, i2); + mnemonic = "v2shli"; + break; case OE_SH(V2SHRSI, X0): case OE_SH(V2SHRSI, X1): + t0 = tcg_const_tl(imm & 15); + gen_helper_v2shrs(tdest, tsrca, t0); + tcg_temp_free(t0); + mnemonic = "v2shrsi"; + break; case OE_SH(V2SHRUI, X0): case OE_SH(V2SHRUI, X1): - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; + i2 = imm & 15; + i3 = (0x << i2) & 0x; + tcg_gen_andi_tl(tdest, tsrca, V2_IMM(i3)); + tcg_gen_shri_tl(tdest, tdest, i2); + mnemonic = "v2shrui"; + break; case OE(ADDLI_OPCODE_X0, 0, X0): case OE(ADDLI_OPCODE_X1, 0, X1): -- 1.9.3 0001-target-tilegx-Implement-v2sh-instructions.patch Description: Binary data
[Qemu-devel] [PATCH v2] target-tilegx: Use TILEGX_EXCP_OPCODE_UNKNOWN and TILEGX_EXCP_OPCODE_UNIMPLEMENTED correctly
>From 0f53a45b3c29e3355cc6b2183ee084e62b86e5fe Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Sun, 4 Oct 2015 13:34:33 +0800
Subject: [PATCH v2] target-tilegx: Use TILEGX_EXCP_OPCODE_UNKNOWN and
TILEGX_EXCP_OPCODE_UNIMPLEMENTED correctly
For some cases, they are for TILEGX_EXCP_OPCODE_UNKNOWN, not for
TILEGX_EXCP_OPCODE_UNIMPLEMENTED.
Also for some cases, they are for TILEGX_EXCP_OPCODE_UNIMPLEMENTED, not
for TILEGX_EXCP_OPCODE_UNKNOWN.
When analyzing issues, the correct printing information is necessary,
e.g. grep UIMP in gcc testsuite output log for finding qemu tilegx
umimplementation issues, grep UNKNOWN for finding unknown instructions.
Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
---
target-tilegx/translate.c | 41 -
1 file changed, 24 insertions(+), 17 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index eb2d0b1..ab3fc81 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -291,7 +291,7 @@ static TileExcp gen_st_opcode(DisasContext *dc, unsigned
dest, unsigned srca,
unsigned srcb, TCGMemOp memop, const char *name)
{
if (dest) {
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ return TILEGX_EXCP_OPCODE_UNKNOWN;
}
tcg_gen_qemu_st_tl(load_gr(dc, srcb), load_gr(dc, srca),
@@ -538,7 +538,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
mnemonic = "swint1";
done0:
if (srca || dest) {
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ return TILEGX_EXCP_OPCODE_UNKNOWN;
}
qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
return ret;
@@ -584,7 +584,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
tcg_gen_andi_tl(dc->jmp.dest, load_gr(dc, srca), ~7);
done1:
if (dest) {
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ return TILEGX_EXCP_OPCODE_UNKNOWN;
}
qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s", mnemonic, reg_names[srca]);
return ret;
@@ -679,7 +679,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
case OE_RR_X1(LNK):
case OE_RR_Y1(LNK):
if (srca) {
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ return TILEGX_EXCP_OPCODE_UNKNOWN;
}
tcg_gen_movi_tl(tdest, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
mnemonic = "lnk";
@@ -723,7 +723,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
mnemonic = "tblidxb3";
break;
default:
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ return TILEGX_EXCP_OPCODE_UNKNOWN;
}
qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
@@ -1453,7 +1453,7 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned
opext,
mnemonic = "xor";
break;
default:
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ return TILEGX_EXCP_OPCODE_UNKNOWN;
}
qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %s", mnemonic,
@@ -1745,7 +1745,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned
opext,
break;
default:
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ return TILEGX_EXCP_OPCODE_UNKNOWN;
}
qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", mnemonic,
@@ -1839,7 +1839,7 @@ static TileExcp gen_bf_opcode_x0(DisasContext *dc,
unsigned ext,
break;
default:
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ return TILEGX_EXCP_OPCODE_UNKNOWN;
}
qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %u, %u", mnemonic,
@@ -1895,7 +1895,7 @@ static TileExcp gen_branch_opcode_x1(DisasContext *dc,
unsigned ext,
mnemonic = "blbs";
break;
default:
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ return TILEGX_EXCP_OPCODE_UNKNOWN;
}
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
@@ -1962,7 +1962,7 @@ static TileExcp gen_mtspr_x1(DisasContext *dc, unsigned
spr, unsigned srca)
if (def == NULL) {
qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr spr[%u], %s", spr,
reg_names[srca]);
- return TILEGX_EXCP_OPCODE_UNKNOWN;
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
}
tsrca = load_gr(dc, srca);
@@ -1982,7 +1982,7 @@ static TileExcp gen_mfspr_x1(DisasContext *dc, unsigned
dest, unsigned spr)
if (def == NULL) {
qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr %s, spr[%u]", reg_names[dest],
spr);
- return TILEGX_EXCP_OPCODE_UNKNOWN;
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
}
tdest = dest_gr(dc, dest);
@@ -2037,7 +2037,7 @@ static TileExcp decode_y0(DisasContext *dc,
tilegx_bundle_bits bundle)
return gen_rri_opcode(dc, OE(opc, 0, Y0),
[Qemu-devel] [PATCH v2] target-tilegx: Implement v2mults instruction
>From 298aa5e9be6373fea7b30236bd3e90352c6e693a Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Sat, 3 Oct 2015 10:42:01 +0800
Subject: [PATCH v2] target-tilegx: Implement v2mults instruction
Just according to v1multu instruction implementation.
Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
---
target-tilegx/helper.h | 1 +
target-tilegx/simd_helper.c | 13 +
target-tilegx/translate.c | 4
3 files changed, 18 insertions(+)
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
index c58ee20..bbcc476 100644
--- a/target-tilegx/helper.h
+++ b/target-tilegx/helper.h
@@ -16,6 +16,7 @@ DEF_HELPER_FLAGS_2(v2int_h, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v2int_l, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1multu, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v2mults, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target-tilegx/simd_helper.c b/target-tilegx/simd_helper.c
index 6fa6318..4f226eb 100644
--- a/target-tilegx/simd_helper.c
+++ b/target-tilegx/simd_helper.c
@@ -41,6 +41,19 @@ uint64_t helper_v1multu(uint64_t a, uint64_t b)
return r;
}
+uint64_t helper_v2mults(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0;
+ int i;
+
+ for (i = 0; i < 64; i += 16) {
+ int64_t ae = (int16_t)(a>> i);
+ int64_t be = (int16_t)(b>> i);
+ r |= ((ae * be) & 0x) << i;
+ }
+ return r;
+}
+
uint64_t helper_v1shl(uint64_t a, uint64_t b)
{
uint64_t m;
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 034cbc2..eb2d0b1 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -1355,7 +1355,11 @@ static TileExcp gen_rrr_opcode(DisasContext *dc,
unsigned opext,
case OE_RRR(V2MNZ, 0, X1):
case OE_RRR(V2MULFSC, 0, X0):
case OE_RRR(V2MULS, 0, X0):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V2MULTS, 0, X0):
+ gen_helper_v2mults(tdest, tsrca, tsrcb);
+ mnemonic = "v2mults";
+ break;
case OE_RRR(V2MZ, 0, X0):
case OE_RRR(V2MZ, 0, X1):
case OE_RRR(V2PACKH, 0, X0):
--
1.9.3
0003-target-tilegx-Implement-v2mults-instruction.patch
Description: Binary data
[Qemu-devel] [PATCH v4] target-tilegx: Support iret instruction and related special registers
>From 8e8d35fffd735df997c78324b301f22cf270b515 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Sun, 4 Oct 2015 17:41:14 +0800
Subject: [PATCH v4] target-tilegx: Support iret instruction and related special
registers
Acording to the __longjmp tilegx libc implementation, and reference from
tilegx ISA document, and suggested by tilegx architecture member, we can
treat iret instruction as "jrp lr". The related code is below:
ENTRY (__longjmp)
FEEDBACK_ENTER(__longjmp)
#define RESTORE(r) { LD r, r0 ; ADDI_PTR r0, r0, REGSIZE }
FOR_EACH_CALLEE_SAVED_REG(RESTORE)
{
LD r2, r0 ; retrieve ICS bit from jmp_buf
movei r3, 1
CMPEQI r0, r1, 0
}
{
mtspr INTERRUPT_CRITICAL_SECTION, r3
shli r2, r2, SPR_EX_CONTEXT_0_1__ICS_SHIFT
}
{
mtspr EX_CONTEXT_0_0, lr
ori r2, r2, RETURN_PL
}
{
or r0, r1, r0
mtspr EX_CONTEXT_0_1, r2
}
iret
jrp lr
EX_CONTEXT_0_0 is used for jumping address, and EX_CONTEXT_0_1 is for
INTERRUPT_CRITICAL_SECTION, which should only be 0 or 1 in user mode, or
it will cause target SEGV (and the patch doesn't implement system mode).
"jrp lr" in __longjmp is for historical reasons, and might get removed
in the future.
Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
---
target-tilegx/cpu.h | 2 ++
target-tilegx/helper.c | 22 ++
target-tilegx/helper.h | 1 +
target-tilegx/translate.c | 14 +-
4 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
index 6f04fe7..6c0fd53 100644
--- a/target-tilegx/cpu.h
+++ b/target-tilegx/cpu.h
@@ -53,6 +53,8 @@ enum {
TILEGX_SPR_CMPEXCH = 0,
TILEGX_SPR_CRITICAL_SEC = 1,
TILEGX_SPR_SIM_CONTROL = 2,
+ TILEGX_SPR_EX_CONTEXT_0_0 = 3,
+ TILEGX_SPR_EX_CONTEXT_0_1 = 4,
TILEGX_SPR_COUNT
};
diff --git a/target-tilegx/helper.c b/target-tilegx/helper.c
index 36b287f..3c043f8 100644
--- a/target-tilegx/helper.c
+++ b/target-tilegx/helper.c
@@ -22,6 +22,7 @@
#include "qemu-common.h"
#include "exec/helper-proto.h"
#include /* For crc32 */
+#include "syscall_defs.h"
void helper_exception(CPUTLGState *env, uint32_t excp)
{
@@ -31,6 +32,27 @@ void helper_exception(CPUTLGState *env, uint32_t excp)
cpu_loop_exit(cs);
}
+void helper_ext01_ics(CPUTLGState *env)
+{
+ uint64_t val = env->spregs[TILEGX_SPR_EX_CONTEXT_0_1];
+
+ switch (val) {
+ case 0:
+ case 1:
+ env->spregs[TILEGX_SPR_CRITICAL_SEC] = val;
+ break;
+ default:
+#if defined(CONFIG_USER_ONLY)
+ env->signo = TARGET_SIGSEGV;
+ env->sigcode = 0;
+ helper_exception(env, TILEGX_EXCP_SIGNAL);
+#else
+ helper_exception(env, TILEGX_EXCP_OPCODE_UNIMPLEMENTED);
+#endif
+ break;
+ }
+}
+
uint64_t helper_cntlz(uint64_t arg)
{
return clz64(arg);
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
index bbcc476..9281d0f 100644
--- a/target-tilegx/helper.h
+++ b/target-tilegx/helper.h
@@ -1,4 +1,5 @@
DEF_HELPER_2(exception, noreturn, env, i32)
+DEF_HELPER_1(ext01_ics, void, env)
DEF_HELPER_FLAGS_1(cntlz, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(cnttz, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(pcnt, TCG_CALL_NO_RWG_SE, i64, i64)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index ab3fc81..acb9ec4 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -529,6 +529,15 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
/* ??? This should yield, especially in system mode. */
mnemonic = "nap";
goto done0;
+ case OE_RR_X1(IRET):
+ gen_helper_ext01_ics(cpu_env);
+ dc->jmp.cond = TCG_COND_ALWAYS;
+ dc->jmp.dest = tcg_temp_new();
+ tcg_gen_ld_tl(dc->jmp.dest, cpu_env,
+ offsetof(CPUTLGState,
spregs[TILEGX_SPR_EX_CONTEXT_0_0]));
+ tcg_gen_andi_tl(dc->jmp.dest, dc->jmp.dest, ~7);
+ mnemonic = "iret";
+ goto done0;
case OE_RR_X1(SWINT0):
case OE_RR_X1(SWINT2):
case OE_RR_X1(SWINT3):
@@ -606,7 +615,6 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
break;
case OE_RR_X0(FSINGLE_PACK1):
case OE_RR_Y0(FSINGLE_PACK1):
- case OE_RR_X1(IRET):
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RR_X1(LD1S):
memop = MO_SB;
@@ -1947,6 +1955,10 @@ static const TileSPR *find_spr(unsigned spr)
offsetof(CPUTLGState, spregs[TILEGX_SPR_CRITICAL_SEC]), 0, 0)
D(SIM_CONTROL,
offsetof(CPUTLGState, spregs[TILEGX_SPR_SIM_CONTROL]), 0, 0)
+ D(EX_CONTEXT_0_0,
+ offsetof(CPUTLGState, spregs[TILEGX_SPR_EX_CONTEXT_0_0]), 0, 0)
+ D(EX_
[Qemu-devel] [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register
>From 40ec3f1c75b4c97e3e0495c9e465be898f48a652 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5...@gmail.com>
Date: Sun, 4 Oct 2015 17:34:17 +0800
Subject: [PATCH] target-tilegx: Let prefetch nop instructions return before
allocating dest temporary register
Or it will cause issue by the dest temporary registers.
Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
---
target-tilegx/translate.c | 85 +--
1 file changed, 46 insertions(+), 39 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index acb9ec4..2913902 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -496,7 +496,6 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
const char *mnemonic;
TCGMemOp memop;
TileExcp ret = TILEGX_EXCP_NONE;
- bool prefetch_nofault = false;
/* Eliminate instructions with no output before doing anything else. */
switch (opext) {
@@ -597,6 +596,26 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
}
qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s", mnemonic, reg_names[srca]);
return ret;
+
+ case OE_RR_X1(LD1U):
+ memop = MO_UB;
+ mnemonic = "ld1u"; /* prefetch, prefetch_l1 */
+ goto do_load_nofault;
+ case OE_RR_X1(LD2U):
+ memop = MO_TEUW;
+ mnemonic = "ld2u"; /* prefetch_l2 */
+ goto do_load_nofault;
+ case OE_RR_X1(LD4U):
+ memop = MO_TEUL;
+ mnemonic = "ld4u"; /* prefetch_l3 */
+ do_load_nofault:
+ if (dest != TILEGX_R_ZERO) {
+ tcg_gen_qemu_ld_tl(dest_gr(dc, dest), load_gr(dc, srca),
+ dc->mmuidx, memop);
+ }
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
+ reg_names[dest], reg_names[srca]);
+ return ret;
}
tdest = dest_gr(dc, dest);
@@ -620,29 +639,14 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
memop = MO_SB;
mnemonic = "ld1s"; /* prefetch_l1_fault */
goto do_load;
- case OE_RR_X1(LD1U):
- memop = MO_UB;
- mnemonic = "ld1u"; /* prefetch, prefetch_l1 */
- prefetch_nofault = (dest == TILEGX_R_ZERO);
- goto do_load;
case OE_RR_X1(LD2S):
memop = MO_TESW;
mnemonic = "ld2s"; /* prefetch_l2_fault */
goto do_load;
- case OE_RR_X1(LD2U):
- memop = MO_TEUW;
- mnemonic = "ld2u"; /* prefetch_l2 */
- prefetch_nofault = (dest == TILEGX_R_ZERO);
- goto do_load;
case OE_RR_X1(LD4S):
memop = MO_TESL;
mnemonic = "ld4s"; /* prefetch_l3_fault */
goto do_load;
- case OE_RR_X1(LD4U):
- memop = MO_TEUL;
- mnemonic = "ld4u"; /* prefetch_l3 */
- prefetch_nofault = (dest == TILEGX_R_ZERO);
- goto do_load;
case OE_RR_X1(LDNT1S):
memop = MO_SB;
mnemonic = "ldnt1s";
@@ -675,9 +679,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
memop = MO_TEQ;
mnemonic = "ld";
do_load:
- if (!prefetch_nofault) {
- tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
- }
+ tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
break;
case OE_RR_X1(LDNA):
tcg_gen_andi_tl(tdest, tsrca, ~7);
@@ -1472,15 +1474,36 @@ static TileExcp gen_rrr_opcode(DisasContext *dc,
unsigned opext,
static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
unsigned dest, unsigned srca, int imm)
{
- TCGv tdest = dest_gr(dc, dest);
+ TCGv tdest;
TCGv tsrca = load_gr(dc, srca);
- bool prefetch_nofault = false;
const char *mnemonic;
TCGMemOp memop;
int i2, i3;
TCGv t0;
switch (opext) {
+ case OE_IM(LD1U_ADD, X1):
+ memop = MO_UB;
+ mnemonic = "ld1u_add"; /* prefetch_add_l1 */
+ goto do_load_add_nofault;
+ case OE_IM(LD2U_ADD, X1):
+ memop = MO_TEUW;
+ mnemonic = "ld2u_add"; /* prefetch_add_l2 */
+ goto do_load_add_nofault;
+ case OE_IM(LD4U_ADD, X1):
+ memop = MO_TEUL;
+ mnemonic = "ld4u_add"; /* prefetch_add_l3 */
+ do_load_add_nofault:
+ if (dest != TILEGX_R_ZERO) {
+ tcg_gen_qemu_ld_tl(dest_gr(dc, dest), tsrca, dc->mmuidx, memop);
+ }
+ tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
+ goto done2;
+ }
+
+ tdest = dest_gr(dc, dest);
+
+ switch (opext) {
case OE(ADDI_OPCODE_Y0, 0, Y0):
case OE(ADDI_OPCODE_Y1, 0, Y1):
case OE_IM(ADDI, X0):
@@ -1526,29 +1549,14 @@ static TileExcp gen_rri_opcode(DisasContext *dc,
unsigned opext,
memop = MO_SB;
mnemonic = "ld1s_add";
Re: [Qemu-devel] [PATCH] target-tilegx: Implement floating point temporarily
After the temporary floating point patch, our tilegx qemu can test the
gcc testsuite successfully (no any unimplementation issues). The test
result is:
=== gcc Summary ===
# of expected passes 77012
# of unexpected failures 622
# of unexpected successes 7
# of expected failures 113
# of unresolved testcases 143
# of unsupported tests 1476
For the 622 left issues:
- Maybe still tilegx implementation issue, e.g.
the floating point single mul instruction cann't get the result which
tilegx gcc expected (it is only related with calculating: float32_mul
calculation result is not match tilegx gcc expected).
- Maybe envorintments configuration issues, e.g.
for gcc guality_check, it may call gdb outside, so I need config the
related gdb correctlly.
- Maybe tilegx gcc issues, e.g.
for some UNKNOWN instructions, probably generated by incorrect jump
instructions, one sample is "-fpic -mcmodel=large" for gcc nested-5
test.
Next, I shall:
- continue to fix the left 622 issues, and send related patches to
qemu-devel mailing list or gcc-patches mailing list.
- then rewrite the floating point instructions implementation, and try
to let the related code merged into qemu mainline with the qemu
members' help.
- at last, try to finish all left unimplemented instructions (there are
still some unimplement insns left, but at present, gcc testsuite does
not use them), and start tilegx qemu system mode, next.
Thanks
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
> From: xili_gchen_5...@hotmail.com
> To: r...@twiddle.net; peter.mayd...@linaro.org; cmetc...@ezchip.com
> CC: qemu-devel@nongnu.org
> Subject: [PATCH] target-tilegx: Implement floating point temporarily
> Date: Sun, 4 Oct 2015 19:16:35 +0800
>
> From 4d12af14f361fb5e3a893fc68a599be9ea17d1dc Mon Sep 17 00:00:00 2001
> From: Chen Gang <gang.chen.5...@gmail.com>
> Date: Sun, 4 Oct 2015 18:00:53 +0800
> Subject: [PATCH] target-tilegx: Implement floating point temporarily
>
> It is a temporary implementation, but it can pass gcc testsuite.
>
> Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
> ---
> target-tilegx/Makefile.objs | 2 +-
> target-tilegx/cpu.h | 5 +-
> target-tilegx/fpu.h | 149 +
> target-tilegx/fpu_helper.c | 259
> target-tilegx/helper.h | 9 ++
> target-tilegx/translate.c | 70 +---
> 6 files changed, 479 insertions(+), 15 deletions(-)
> create mode 100644 target-tilegx/fpu.h
> create mode 100644 target-tilegx/fpu_helper.c
>
> diff --git a/target-tilegx/Makefile.objs b/target-tilegx/Makefile.objs
> index 0db778f..1573c36 100644
> --- a/target-tilegx/Makefile.objs
> +++ b/target-tilegx/Makefile.objs
> @@ -1 +1 @@
> -obj-y += cpu.o translate.o helper.o simd_helper.o
> +obj-y += cpu.o translate.o helper.o simd_helper.o fpu_helper.o
> diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
> index 6c0fd53..b752ef3 100644
> --- a/target-tilegx/cpu.h
> +++ b/target-tilegx/cpu.h
> @@ -27,7 +27,7 @@
> #define CPUArchState struct CPUTLGState
>
> #include "exec/cpu-defs.h"
> -
> +#include "fpu.h"
>
> /* TILE-Gx common register alias */
> #define TILEGX_R_RE 0 /* 0 register, for function/syscall return value */
> @@ -77,6 +77,7 @@ typedef enum {
> TILEGX_EXCP_OPCODE_FETCHAND4 = 0x10c,
> TILEGX_EXCP_OPCODE_FETCHOR = 0x10d,
> TILEGX_EXCP_OPCODE_FETCHOR4 = 0x10e,
> + TILEGX_EXCP_OPCODE_INVALID_VALUE = 0x10f,
> TILEGX_EXCP_REG_IDN_ACCESS = 0x181,
> TILEGX_EXCP_REG_UDN_ACCESS = 0x182,
> TILEGX_EXCP_UNALIGNMENT = 0x201,
> @@ -88,6 +89,8 @@ typedef struct CPUTLGState {
> uint64_t spregs[TILEGX_SPR_COUNT]; /* Special used registers by outside */
> uint64_t pc; /* Current pc */
>
> + FPUTLGState fpu; /* fpu context */
> +
> #if defined(CONFIG_USER_ONLY)
> uint64_t excaddr; /* exception address */
> uint64_t atomic_srca; /* Arguments to atomic "exceptions" */
> diff --git a/target-tilegx/fpu.h b/target-tilegx/fpu.h
> new file mode 100644
> index 000..41076bd
> --- /dev/null
> +++ b/target-tilegx/fpu.h
> @@ -0,0 +1,149 @@
> +/*
> + * TILE-Gx virtual FPU header
> + *
> + * Copyright (c) 2015 Chen Gang
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the impli
Re: [Qemu-devel] [PATCH] target-tilegx: Use TILEGX_EXCP_OPCODE_UNKNOWN instead of TILEGX_EXCP_OPCODE_UNIMPLEMENTED for some cases
Oh, sorry, also one modification about TILEGX_EXCP_OPCODE_UNIMPLEMENTED
left. I shall send patch v2 for it.
Thanks.
On 10/3/15 16:54, gang.chen.5...@gmail.com wrote:
> From: Chen Gang <gang.chen.5...@gmail.com>
>
> For some cases, they are for TILEGX_EXCP_OPCODE_UNKNOWN, not for
> TILEGX_EXCP_OPCODE_UNIMPLEMENTED.
>
> When analyzing issues, the related output is incorrect (e.g. grep UIMP
> in the output log for finding qemu tilegx umimplementation issues).
>
> Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
> ---
> target-tilegx/translate.c | 35 +--
> 1 file changed, 21 insertions(+), 14 deletions(-)
>
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> index 40f9b12..d2aeae0 100644
> --- a/target-tilegx/translate.c
> +++ b/target-tilegx/translate.c
> @@ -293,7 +293,7 @@ static TileExcp gen_st_opcode(DisasContext *dc, unsigned
> dest, unsigned srca,
>unsigned srcb, TCGMemOp memop, const char
> *name)
> {
> if (dest) {
> -return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> +return TILEGX_EXCP_OPCODE_UNKNOWN;
> }
>
> tcg_gen_qemu_st_tl(load_gr(dc, srcb), load_gr(dc, srca),
> @@ -540,7 +540,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
> opext,
> mnemonic = "swint1";
> done0:
> if (srca || dest) {
> -return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> +return TILEGX_EXCP_OPCODE_UNKNOWN;
> }
> qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
> return ret;
> @@ -586,7 +586,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
> opext,
> tcg_gen_andi_tl(dc->jmp.dest, load_gr(dc, srca), ~7);
> done1:
> if (dest) {
> -return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> +return TILEGX_EXCP_OPCODE_UNKNOWN;
> }
> qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s", mnemonic, reg_names[srca]);
> return ret;
> @@ -688,7 +688,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
> opext,
> case OE_RR_X1(LNK):
> case OE_RR_Y1(LNK):
> if (srca) {
> -return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> +return TILEGX_EXCP_OPCODE_UNKNOWN;
> }
> tcg_gen_movi_tl(TDEST, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
> mnemonic = "lnk";
> @@ -735,7 +735,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
> opext,
> mnemonic = "tblidxb3";
> break;
> default:
> -return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> +return TILEGX_EXCP_OPCODE_UNKNOWN;
> }
>
> qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
> @@ -1833,7 +1833,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc,
> unsigned opext,
> break;
>
> default:
> -return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> +return TILEGX_EXCP_OPCODE_UNKNOWN;
> }
>
> qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", mnemonic,
> @@ -1927,7 +1927,7 @@ static TileExcp gen_bf_opcode_x0(DisasContext *dc,
> unsigned ext,
> break;
>
> default:
> -return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> +return TILEGX_EXCP_OPCODE_UNKNOWN;
> }
>
> qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %u, %u", mnemonic,
> @@ -1983,7 +1983,7 @@ static TileExcp gen_branch_opcode_x1(DisasContext *dc,
> unsigned ext,
> mnemonic = "blbs";
> break;
> default:
> -return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> +return TILEGX_EXCP_OPCODE_UNKNOWN;
> }
>
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
> @@ -2131,7 +2131,7 @@ static TileExcp decode_y0(DisasContext *dc,
> tilegx_bundle_bits bundle)
> return gen_rri_opcode(dc, OE(opc, 0, Y0), dest, srca, imm);
>
> default:
> -return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> +return TILEGX_EXCP_OPCODE_UNKNOWN;
> }
> }
>
> @@ -2175,7 +2175,7 @@ static TileExcp decode_y1(DisasContext *dc,
> tilegx_bundle_bits bundle)
> return gen_rri_opcode(dc, OE(opc, 0, Y1), dest, srca, imm);
>
> default:
> -return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> +return TILEGX_EXCP_OPCODE_UNKNOWN;
> }
> }
>
> @@ -2233,7 +2233,7 @@ static TileExcp decode_y2(DisasContext *dc,
> tilegx_bundle_bits bundle)
> return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEQ, "st");
>
> default:
> -return TILEGX_EXCP_OPCODE_UNIMPLEME
Re: [Qemu-devel] [PATCH] target-tilegx: Implement v2mults instruction
On 10/3/15 10:43, gang.chen.5...@gmail.com wrote: > diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c > index 6853628..40f9b12 100644 > --- a/target-tilegx/translate.c > +++ b/target-tilegx/translate.c > @@ -990,6 +990,7 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned > opext, > mnemonic = "fsingle_mul1"; > break; > case OE_RRR(FSINGLE_MUL2, 0, X0): > +tcg_gen_mov_i64(TDEST, tsrca); Oh, sorry, it is wast contents, needs to be deleted. I shall send patch v2 for it. > mnemonic = "fsingle_mul2"; > break; > case OE_RRR(FSINGLE_PACK2, 0, X0): > @@ -1429,7 +1430,11 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, > unsigned opext, > case OE_RRR(V2MNZ, 0, X1): > case OE_RRR(V2MULFSC, 0, X0): > case OE_RRR(V2MULS, 0, X0): > +return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; > case OE_RRR(V2MULTS, 0, X0): > +gen_helper_v2mults(TDEST, tsrca, tsrcb); > +mnemonic = "v2shl"; > +break; > case OE_RRR(V2MZ, 0, X0): > case OE_RRR(V2MZ, 0, X1): > case OE_RRR(V2PACKH, 0, X0): > -- Chen Gang (陈刚) Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH] target-tilegx: Check zero dest register for ld instructions
On 10/1/15 10:29, Richard Henderson wrote:
> On 09/28/2015 11:51 PM, gang.chen.5...@gmail.com wrote:
>> From: Chen Gang <gang.chen.5...@gmail.com>
>>
>> At present, qemu x86_64 host backend can not remove the related dummy
>> instructions. Even the worse, sometimes, it will generate the incorrect
>> instructions which will cause segment fault for prefetch_l3 instruction.
>>
>> Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
>> ---
>> target-tilegx/translate.c | 10 +++---
>> 1 file changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
>> index 86da6b5..7232361 100644
>> --- a/target-tilegx/translate.c
>> +++ b/target-tilegx/translate.c
>> @@ -620,7 +620,9 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
>> opext,
>> memop = MO_TEQ;
>> mnemonic = "ld";
>> do_load:
>> - tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
>> + if (dest != TILEGX_R_ZERO) {
>> + tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
>> + }
>
> This isn't right. Not all load instructions are nofault prefetches.
>
OK, thanks.
--
Chen Gang (陈刚)
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH] target-tilegx: Call dest_gr() later when have to use it
Oh, sorry, when I sent this patch, I did not merge it to RTH's latest
patches. So this patch could not merge with RTH's patches.
If necessary to send patch v2, please let me know.
Thanks.
On 10/1/15 21:49, gang.chen.5...@gmail.com wrote:
> From: Chen Gang <gang.chen.5...@gmail.com>
>
> When a nop instruction is generated, but the 'dest' is a valid (e.g. for
> any qemu skipped instructions, but still be useful in real machine),
> always allocate dest_gr() will cause issue for these nop instructions.
>
> After fix this issue, the temporary implementation of floating point
> instructions (which have skipped instructions) can work correctlly.
>
> Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
> ---
> target-tilegx/translate.c | 214 +++---
> 1 file changed, 127 insertions(+), 87 deletions(-)
>
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> index b7bb4f3..2ca5d43 100644
> --- a/target-tilegx/translate.c
> +++ b/target-tilegx/translate.c
> @@ -30,6 +30,8 @@
>
> #define FMT64X "%016" PRIx64
>
> +#define TDEST dest_gr(dc, dest)
> +
> static TCGv_ptr cpu_env;
> static TCGv cpu_pc;
> static TCGv cpu_regs[TILEGX_R_COUNT];
> @@ -547,18 +549,17 @@ static TileExcp gen_rr_opcode(DisasContext *dc,
> unsigned opext,
> return ret;
> }
>
> - tdest = dest_gr(dc, dest);
> tsrca = load_gr(dc, srca);
>
> switch (opext) {
> case OE_RR_X0(CNTLZ):
> case OE_RR_Y0(CNTLZ):
> - gen_helper_cntlz(tdest, tsrca);
> + gen_helper_cntlz(TDEST, tsrca);
> mnemonic = "cntlz";
> break;
> case OE_RR_X0(CNTTZ):
> case OE_RR_Y0(CNTTZ):
> - gen_helper_cnttz(tdest, tsrca);
> + gen_helper_cnttz(TDEST, tsrca);
> mnemonic = "cnttz";
> break;
> case OE_RR_X0(FSINGLE_PACK1):
> @@ -631,10 +632,11 @@ static TileExcp gen_rr_opcode(DisasContext *dc,
> unsigned opext,
> mnemonic = "ld";
> do_load:
> if (!prefetch_nofault) {
> - tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
> + tcg_gen_qemu_ld_tl(TDEST, tsrca, dc->mmuidx, memop);
> }
> break;
> case OE_RR_X1(LDNA):
> + tdest = dest_gr(dc, dest);
> tcg_gen_andi_tl(tdest, tsrca, ~7);
> tcg_gen_qemu_ld_tl(tdest, tdest, dc->mmuidx, MO_TEQ);
> mnemonic = "ldna";
> @@ -644,22 +646,22 @@ static TileExcp gen_rr_opcode(DisasContext *dc,
> unsigned opext,
> if (srca) {
> return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> }
> - tcg_gen_movi_tl(tdest, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
> + tcg_gen_movi_tl(TDEST, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
> mnemonic = "lnk";
> break;
> case OE_RR_X0(PCNT):
> case OE_RR_Y0(PCNT):
> - gen_helper_pcnt(tdest, tsrca);
> + gen_helper_pcnt(TDEST, tsrca);
> mnemonic = "pcnt";
> break;
> case OE_RR_X0(REVBITS):
> case OE_RR_Y0(REVBITS):
> - gen_helper_revbits(tdest, tsrca);
> + gen_helper_revbits(TDEST, tsrca);
> mnemonic = "revbits";
> break;
> case OE_RR_X0(REVBYTES):
> case OE_RR_Y0(REVBYTES):
> - tcg_gen_bswap64_tl(tdest, tsrca);
> + tcg_gen_bswap64_tl(TDEST, tsrca);
> mnemonic = "revbytes";
> break;
> case OE_RR_X0(TBLIDXB0):
> @@ -682,7 +684,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
> opext,
> static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
> unsigned dest, unsigned srca, unsigned srcb)
> {
> - TCGv tdest = dest_gr(dc, dest);
> + TCGv tdest;
> TCGv tsrca = load_gr(dc, srca);
> TCGv tsrcb = load_gr(dc, srcb);
> TCGv t0;
> @@ -691,13 +693,14 @@ static TileExcp gen_rrr_opcode(DisasContext *dc,
> unsigned opext,
> switch (opext) {
> case OE_RRR(ADDXSC, 0, X0):
> case OE_RRR(ADDXSC, 0, X1):
> - gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_add_tl);
> + gen_saturate_op(TDEST, tsrca, tsrcb, tcg_gen_add_tl);
> mnemonic = "addxsc";
> break;
> case OE_RRR(ADDX, 0, X0):
> case OE_RRR(ADDX, 0, X1):
> case OE_RRR(ADDX, 0, Y0):
> case OE_RRR(ADDX, 0, Y1):
> + tdest = dest_gr(dc, dest);
> tcg_gen_add_tl(tdest, tsrca, tsrcb);
> tcg_gen_ext32s_tl(tdest, tdest);
> mnemonic = "addx";
> @@ -706,25 +709,25 @@ static TileExcp gen_rrr_opcode(DisasContext *dc,
> unsigned opext,
> case OE_RRR(ADD, 0, X1):
> case OE_RRR(ADD, 0, Y0):
> case OE_RRR(ADD, 0, Y1):
> - tcg_gen_add_tl(tdest, tsrca, tsrcb);
> + tcg_gen_add_tl(TDEST, tsrca, tsrcb);
> mnemonic = "add";
> break;
> case OE_RRR(AND, 0, X0):
> case OE_RRR(AND, 0, X1):
> case OE_RRR(AND, 5, Y0):
> case OE_RRR(AND, 5, Y1):
> - tcg_gen_and_tl(tdest, tsrca, tsrcb);
> + tcg_gen_and_tl(TDEST, tsrca, tsrcb);
> mnemonic = "and";
> break;
> case OE_RRR(CMOVEQZ, 0, X0):
> case OE_RRR(CMOVEQ
Re: [Qemu-devel] [PATCH v2] target-tilegx: Support iret instruction and related special registers
Oh, sorry, according to the architecture member's reply, this patch is
incorrect. I shall implement iret as "jrp lr".
Thanks.
On 10/1/15 19:01, gang.chen.5...@gmail.com wrote:
> From: Chen Gang <gang.chen.5...@gmail.com>
>
> Acording to the __longjmp tilegx libc implementation, and reference from
> tilegx ISA document, we can left iret instruction empty. The related
> code is below:
>
> ENTRY (__longjmp)
> FEEDBACK_ENTER(__longjmp)
>
> #define RESTORE(r) { LD r, r0 ; ADDI_PTR r0, r0, REGSIZE }
> FOR_EACH_CALLEE_SAVED_REG(RESTORE)
>
> {
> LD r2, r0 ; retrieve ICS bit from jmp_buf
> movei r3, 1
> CMPEQI r0, r1, 0
> }
>
> {
> mtspr INTERRUPT_CRITICAL_SECTION, r3
> shli r2, r2, SPR_EX_CONTEXT_0_1__ICS_SHIFT
> }
>
> {
> mtspr EX_CONTEXT_0_0, lr
> ori r2, r2, RETURN_PL
> }
>
> {
> or r0, r1, r0
> mtspr EX_CONTEXT_0_1, r2
> }
>
> iret
>
> jrp lr
>
> Until now, EX_CONTEXT_0_0 and EX_CONTEXT_0_1 are only used in mtspr, so
> just skip them, at present.
>
> After this patch, busybox sh can run correctly.
>
> Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
> ---
> target-tilegx/translate.c | 14 +++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> index 421766b..3ae59fe 100644
> --- a/target-tilegx/translate.c
> +++ b/target-tilegx/translate.c
> @@ -563,8 +563,10 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
> opext,
> break;
> case OE_RR_X0(FSINGLE_PACK1):
> case OE_RR_Y0(FSINGLE_PACK1):
> - case OE_RR_X1(IRET):
> return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> + case OE_RR_X1(IRET):
> + mnemonic = "iret";
> + break;
> case OE_RR_X1(LD1S):
> memop = MO_SB;
> mnemonic = "ld1s"; /* prefetch_l1_fault */
> @@ -1823,6 +1825,8 @@ static const TileSPR *find_spr(unsigned spr)
> offsetof(CPUTLGState, spregs[TILEGX_SPR_CRITICAL_SEC]), 0, 0)
> D(SIM_CONTROL,
> offsetof(CPUTLGState, spregs[TILEGX_SPR_SIM_CONTROL]), 0, 0)
> + D(EX_CONTEXT_0_0, -1, 0, 0) /* Skip it */
> + D(EX_CONTEXT_0_1, -1, 0, 0) /* Skip it */
> }
>
> #undef D
> @@ -1836,9 +1840,11 @@ static TileExcp gen_mtspr_x1(DisasContext *dc,
> unsigned spr, unsigned srca)
> const TileSPR *def = find_spr(spr);
> TCGv tsrca;
>
> - if (def == NULL) {
> + if (!def) {
> qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr spr[%u], %s", spr, reg_names[srca]);
> return TILEGX_EXCP_OPCODE_UNKNOWN;
> + } else if (def->offset == -1) {
> + goto tail;
> }
>
> tsrca = load_gr(dc, srca);
> @@ -1847,6 +1853,8 @@ static TileExcp gen_mtspr_x1(DisasContext *dc, unsigned
> spr, unsigned srca)
> } else {
> tcg_gen_st_tl(tsrca, cpu_env, def->offset);
> }
> +
> +tail:
> qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr %s, %s", def->name, reg_names[srca]);
> return TILEGX_EXCP_NONE;
> }
> @@ -1856,7 +1864,7 @@ static TileExcp gen_mfspr_x1(DisasContext *dc, unsigned
> dest, unsigned spr)
> const TileSPR *def = find_spr(spr);
> TCGv tdest;
>
> - if (def == NULL) {
> + if (!def || def->offset == -1) {
> qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr %s, spr[%u]", reg_names[dest], spr);
> return TILEGX_EXCP_OPCODE_UNKNOWN;
> }
>
--
Chen Gang (陈刚)
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 00/14] Collected tilegx patches
On 10/1/15 10:38, Richard Henderson wrote: > I've taken the liberty of modifying some of the patches that Chen Gang > has posted. Some of these are new cleanups that I saw along the way. > A few are filling out the final user-level non-fp, non-vector insns. > Thank you very much for your work. > Please give them a look over and re-test, Mr Chen. > OK, I shall try. > > Chen Gang (8): > target-tilegx: Implement v*shl, v*shru, and v*shrs instructions > target-tilegx: Implement v*add and v*sub instructions > target-tilegx: Implement v1multu instruction > target-tilegx: Let x1 pipe process bpt instruction only > linux-user/syscall_defs.h: Sync the latest si_code from Linux kernel > linux-user/tilegx: Implement tilegx signal features > target-tilegx: Decode ill pseudo-instructions > target-tilegx: Fix a typo for mnemonic about "ld_add" > > Richard Henderson (6): > target-tilegx: Use V1 in simd_helper.c > target-tilegx: Implement crc instructions > target-tilegx: Implement table index instructions > target-tilegx: Implement complex multiply instructions > target-tilegx: Use TILEGX_EXCP_SIGNAL instead of TILEGX_EXCP_SEGV > target-tilegx: Handle nofault prefetch instructions > > linux-user/main.c | 39 +++-- > linux-user/signal.c | 160 +++- > linux-user/syscall_defs.h | 11 ++ > linux-user/tilegx/syscall.h | 3 + > target-tilegx/cpu.c | 7 +- > target-tilegx/cpu.h | 6 +- > target-tilegx/helper.c | 59 > target-tilegx/helper.h | 9 ++ > target-tilegx/simd_helper.c | 53 ++- > target-tilegx/translate.c | 349 ++++++-- > 10 files changed, 635 insertions(+), 61 deletions(-) > Thanks. -- Chen Gang (陈刚) Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH v3] target-tilegx: Support iret instruction and related special registers
On 10/2/15 08:36, Richard Henderson wrote:
> On 10/01/2015 10:37 PM, gang.chen.5...@gmail.com wrote:
>> {
>> mtspr INTERRUPT_CRITICAL_SECTION, r3
>> shli r2, r2, SPR_EX_CONTEXT_0_1__ICS_SHIFT
>> }
>>
>> {
>> mtspr EX_CONTEXT_0_0, lr
>> ori r2, r2, RETURN_PL
>> }
>>
>> {
>> or r0, r1, r0
>> mtspr EX_CONTEXT_0_1, r2
>> }
>>
>> iret
>>
>> jrp lr
>>
>> Until now, EX_CONTEXT_0_0 and EX_CONTEXT_0_1 are only used in mtspr, so
>> just skip them, at present. "jrp lr" in __longjmp is for historical
>> reasons, and might get removed in the future.
>
> So, really, iret is supposed to branch to EX_CONTEXT_0_0, and (presumably)
> validate the privilege level in EX_CONTEXT_0_1 continues to be user-mode.
>
Oh, really.
>> + case OE_RR_X1(IRET):
>> + if (srca) {
>> + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
>> + }
>> + srca = TILEGX_R_LR;
>> + mnemonic = "iret";
>> + goto do_jr;
>
> which means this is wrong, but just happens to work for __longjmp.
>
> It appears that the entire point of this iret path is to atomically branch
> and set INTERRUPT_CRITICAL_SECTION at the same time. So, this isn't complete.
>
OK, thanks.
> What INTERRUPT_CRITICAL_SECTION is supposed to *do* at user mode, I don't
> know.
>
Welcome any other members' ideas, suggestions and completions.
Thanks.
--
Chen Gang (陈刚)
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH v3] target-tilegx: Support iret instruction and related special registers
OK, thanks. I shall try to send patch v4 for it within 2 days.
On 10/2/15 09:31, Chris Metcalf wrote:
> On 10/1/2015 8:36 PM, Richard Henderson wrote:
>> On 10/01/2015 10:37 PM, gang.chen.5...@gmail.com wrote:
>>> {
>>>mtspr INTERRUPT_CRITICAL_SECTION, r3
>>>shli r2, r2, SPR_EX_CONTEXT_0_1__ICS_SHIFT
>>> }
>>>
>>> {
>>>mtspr EX_CONTEXT_0_0, lr
>>>ori r2, r2, RETURN_PL
>>> }
>>>
>>> {
>>>or r0, r1, r0
>>>mtspr EX_CONTEXT_0_1, r2
>>> }
>>>
>>> iret
>>>
>>> jrp lr
>>>
>>> Until now, EX_CONTEXT_0_0 and EX_CONTEXT_0_1 are only used in mtspr, so
>>> just skip them, at present. "jrp lr" in __longjmp is for historical
>>> reasons, and might get removed in the future.
>>
>> So, really, iret is supposed to branch to EX_CONTEXT_0_0, and (presumably)
>> validate the privilege level in EX_CONTEXT_0_1 continues to be user-mode.
>
> Yes, I gave the same feedback earlier today. EX_CONTEXT_0_1 should be either
> 0 or 1 to set INTERRUPT_CRITICAL_SECTION appropriately, and raise GPV for any
> other value. (Obviously it's more complex if you're really emulating system
> software, but for now that's out of scope, I think.)
>
>>
>>> +case OE_RR_X1(IRET):
>>> +if (srca) {
>>> +return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
>>> +}
>>> +srca = TILEGX_R_LR;
>>> +mnemonic = "iret";
>>> +goto do_jr;
>>
>> which means this is wrong, but just happens to work for __longjmp.
>>
>> It appears that the entire point of this iret path is to atomically branch
>> and set INTERRUPT_CRITICAL_SECTION at the same time. So, this isn't
>> complete.
>>
>> What INTERRUPT_CRITICAL_SECTION is supposed to *do* at user mode, I don't
>> know.
>
> It disables interrupts from being delivered. This means asynchronous
> interrupts get deferred until ICS is set back to zero, and synchronous
> interrupts (page fault, etc) cause a double-fault instead. ICS is
> automatically set on entry to interrupt handlers, so the handler has time to
> acquire any information about the interrupt from SPRs, and it is expected
> that ICS is cleared as soon as possible. ICS can also be used before
> returning from interrupts if you need to do something like adjust the
> interrupt mask prior to returning.
>
--
Chen Gang (陈刚)
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH] target-tilegx: Call dest_gr() later when have to use it
On 10/2/15 03:30, Richard Henderson wrote: > On 10/01/2015 11:49 PM, gang.chen.5...@gmail.com wrote: >> From: Chen Gang <gang.chen.5...@gmail.com> >> >> When a nop instruction is generated, but the 'dest' is a valid (e.g. for >> any qemu skipped instructions, but still be useful in real machine), >> always allocate dest_gr() will cause issue for these nop instructions. >> >> After fix this issue, the temporary implementation of floating point >> instructions (which have skipped instructions) can work correctlly. > > Um, no. See the gen_rrr_opcode where we simply use two switch statements for > this. OK, thanks. -- Chen Gang (陈刚) Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH] target-tilegx: Support iret instruction and related special registers
On 9/29/15 14:34, Richard Henderson wrote:
> On 09/28/2015 03:06 PM, gang.chen.5...@gmail.com wrote:
>> From: Chen Gang <gang.chen.5...@gmail.com>
>>
>> Acording to the __longjmp tilegx libc implementation, and reference from
>> tilegx ISA document, we can left iret instruction empty. The related
>> code is below:
>>
>>ENTRY (__longjmp)
>> FEEDBACK_ENTER(__longjmp)
>>
>>#define RESTORE(r) { LD r, r0 ; ADDI_PTR r0, r0, REGSIZE }
>> FOR_EACH_CALLEE_SAVED_REG(RESTORE)
>>
>> {
>>LD r2, r0 ; retrieve ICS bit from jmp_buf
>>movei r3, 1
>>CMPEQI r0, r1, 0
>> }
>>
>> {
>>mtspr INTERRUPT_CRITICAL_SECTION, r3
>>shli r2, r2, SPR_EX_CONTEXT_0_1__ICS_SHIFT
>> }
>>
>> {
>>mtspr EX_CONTEXT_0_0, lr
>>ori r2, r2, RETURN_PL
>> }
>>
>> {
>> or r0, r1, r0
>>mtspr EX_CONTEXT_0_1, r2
>> }
>>
>> iret
>>
>> jrp lr
>>
>> So can let busybox sh run correctly.
>>
>> Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
>> ---
>> target-tilegx/cpu.h | 2 ++
>> target-tilegx/translate.c | 8 +++-
>> 2 files changed, 9 insertions(+), 1 deletion(-)
>>
>> diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
>> index 4b05cd2..02e1a18 100644
>> --- a/target-tilegx/cpu.h
>> +++ b/target-tilegx/cpu.h
>> @@ -54,6 +54,8 @@ enum {
>> TILEGX_SPR_CRITICAL_SEC = 1,
>> TILEGX_SPR_SIM_CONTROL = 2,
>> TILEGX_SPR_EX_CONTEXT_1 = 3,
>> +TILEGX_SPR_EX_CONTEXT_0_0 = 4,
>> +TILEGX_SPR_EX_CONTEXT_0_1 = 5,
>
> Don't add spr's you're not going to use.
>
OK, thanks.
--
Chen Gang (陈刚)
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PULL 00/35] TileGX basic instructions
On 9/27/15 19:48, Chen Gang wrote: > > After fix v1addi issue, try-pending will cause segment fault instead of > abort, I shall continue analyzing try-pending issue, next. > After we check the zero dest register for ld insns, this issue can be fixed -- at least, it is not tilegx's issue, tilegx can bypass it successfully. Next I shall continue for gcc testsuite. I am not quite sure whether I can finish it within this month, but I guess, I shall finish it within Chinese National Day (which I can get more free time resources on it). Thanks. -- Chen Gang (陈刚) Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PULL 00/35] TileGX basic instructions
On 9/17/15 06:36, Chen Gang wrote: > > > need analyzing (it is easy, I guess): > > mm: abort (origin has no issue) > pcnt:abort (origin has no issue) > v1addi: abort (origin has no issue) > After fix v1addi insn issue, the 3 abort cases are all fixed. :-) > let analyzing easier: > > try-pending: abort (origin causes pending). > > I shall try to fix them, and send patches. Then continue gcc testsuite. > After fix v1addi issue, try-pending will cause segment fault instead of abort, I shall continue analyzing try-pending issue, next. Thanks. -- Chen Gang (陈刚) Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH] linux-user/syscall_defs.h: Sync the latest si_code from Linux kernel
On 9/27/15 00:06, Peter Maydell wrote:
> On 25 September 2015 at 21:10, <gang.chen.5...@gmail.com> wrote:
>> From: Chen Gang <gang.chen.5...@gmail.com>
>>
>> They content several new macro members, also contents TARGET_N*.
>>
>> Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
>> ---
>> linux-user/syscall_defs.h | 44 ++--
>> 1 file changed, 30 insertions(+), 14 deletions(-)
>>
>> diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
>> index cdc8db4..6bec3f2 100644
>> --- a/linux-user/syscall_defs.h
>> +++ b/linux-user/syscall_defs.h
>> @@ -736,14 +736,21 @@ typedef struct target_siginfo {
>> /*
>> * SIGILL si_codes
>> */
>> -#define TARGET_ILL_ILLOPC (1) /* illegal opcode */
>> -#define TARGET_ILL_ILLOPN (2) /* illegal operand */
>> -#define TARGET_ILL_ILLADR (3) /* illegal addressing mode */
>> -#define TARGET_ILL_ILLTRP (4) /* illegal trap */
>> -#define TARGET_ILL_PRVOPC (5) /* privileged opcode */
>> -#define TARGET_ILL_PRVREG (6) /* privileged register */
>> -#define TARGET_ILL_COPROC (7) /* coprocessor error */
>> -#define TARGET_ILL_BADSTK (8) /* internal stack error */
>> +#define TARGET_ILL_ILLOPC (1) /* illegal opcode */
>> +#define TARGET_ILL_ILLOPN (2) /* illegal operand */
>> +#define TARGET_ILL_ILLADR (3) /* illegal addressing mode */
>> +#define TARGET_ILL_ILLTRP (4) /* illegal trap */
>> +#define TARGET_ILL_PRVOPC (5) /* privileged opcode */
>> +#define TARGET_ILL_PRVREG (6) /* privileged register */
>> +#define TARGET_ILL_COPROC (7) /* coprocessor error */
>> +#define TARGET_ILL_BADSTK (8) /* internal stack error */
>> +#ifdef TARGET_TILEGX
>> +#define TARGET_ILL_DBLFLT (9) /* double fault */
>> +#define TARGET_ILL_HARDWALL (10)/* user networks hardwall violation
>> */
>> +#define TARGET_NSIGILL 10
>> +#else
>> +#define TARGET_NSIGILL 8
>> +#endif
>
> Please don't change lines which haven't actually changed;
> it makes it hard to see what has been added.
>
"scripts/checkpatch.pl" will check '\t', so when we add new lines, we
have to consider about it. And all related lines (at least in a "group")
have to changed, too.
I guess, I need mention about it in comments (but I did not originally).
So for me, please add related comments for it when you apply the patch
(if it passes review). If it is necessary to send patch v2, please let
me know.
Thanks
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH] tilegx: Support raise instruction
On 9/24/15 02:34, Richard Henderson wrote:
> You forgot to cc qemu-devel.
>
Oh, we can not find it in qemu mail archive list. But I really cc
qemu-devel.
When I send the next patches, I'll notice about it, if still "can not cc
qemu-devel", I shall try to send patches from my hotmail client.
> This patch needs to be split.
>
OK.
> On 09/22/2015 03:38 PM, gang.chen.5...@gmail.com wrote:
>>
>> +static int sigdata_code(uint64_t sigdata)
>> +{
>> +return (sigdata & 0x3ff) >> 6;
>> +}
>> +
>> +static int sigdata_no(uint64_t sigdata)
>> +{
>> +return sigdata & 0x3f;
>> +}
>> +
>> +static void do_raise(CPUTLGState *env)
>> +{
>> +target_siginfo_t info;
>> +
>> +info.si_signo = sigdata_no(env->sigdata);
>> +info.si_errno = 0;
>> +info.si_code = sigdata_code(env->sigdata);
>> +info._sifields._sigfault._addr = env->pc;
>> +queue_signal(env, info.si_signo, );
>> +}
>
>
> This should look much more like the linux kernel code, where instead of
> passing
> "sigdata", we load the instruction that faulted and parse out the data. You
> should only need TILEGX_EXCP_OPCODE_ILL.
>
OK, thank, I will try, next.
>>
>> +env->spregs[TILEGX_SPR_EX_CONTEXT_1] =
>> TILEGX_PL_ICS_EX1(TILEGX_USER_PL, 1);
>> +env->regs[TILEGX_R_SP] = (unsigned long) frame;
>> +env->regs[TILEGX_R_LR] = restorer;
>> +env->regs[0] = (unsigned long) sig;
>> +env->regs[1] = (unsigned long) >info;
>> +env->regs[2] = (unsigned long) >uc;
>> +/* regs->flags |= PT_FLAGS_CALLER_SAVES; FIXME: we can skip it? */
>> +
>> +unlock_user_struct(frame, frame_addr, 1);
>> +return;
>> +
>> +give_sigsegv:
>> +if (sig == TARGET_SIGSEGV) {
>> +ka->_sa_handler = TARGET_SIG_DFL;
>> +}
>> +force_sig(TARGET_SIGSEGV /* , current */);
>> +}
>> +
>> +/* kernel: arch/tile/kernel/signal.c */
>> +long do_rt_sigreturn(CPUArchState *env)
>> +{
>> +fprintf(stderr, "do_rt_sigreturn: not implemented\n");
>> +return -TARGET_ENOSYS;
>> +}
>> +
>
> The introduction of signal handling needs to be it's own patch.
>
OK, thanks.
> I'm also disapointed that you didn't fill in rt_sigreturn; there's no point in
> not doing them together.
>
This patch is only for raise insn, so I only implement the related code
for raise.
But, OK, I will let them together in one patch, next.
>>
>> #include "exec/cpu-defs.h"
>> +#include "spr_def_64.h"
>>
>> +#define TILEGX_EX1_PL(ex1) \
>> + (((ex1) >> SPR_EX_CONTEXT_1_1__PL_SHIFT) & SPR_EX_CONTEXT_1_1__PL_RMASK)
>> +#define TILEGX_EX1_ICS(ex1) \
>> + (((ex1) >> SPR_EX_CONTEXT_1_1__ICS_SHIFT) & SPR_EX_CONTEXT_1_1__ICS_RMASK)
>> +#define TILEGX_PL_ICS_EX1(pl, ics) \
>> + (((pl) << SPR_EX_CONTEXT_1_1__PL_SHIFT) | \
>> + ((ics) << SPR_EX_CONTEXT_1_1__ICS_SHIFT))
>> +
>> +#define TILEGX_USER_PL 0
>
> What's this for? It appears to be something unrelated and not used.
>
The previous setup_rt_frame() will use some of them.
But it is OK for me to move them to the related file.
>>
>> case OE(ADDLI_OPCODE_X0, 0, X0):
>> case OE(ADDLI_OPCODE_X1, 0, X1):
>> -tcg_gen_addi_tl(tdest, tsrca, imm);
>> +if ((srca == TILEGX_R_ZERO) && (dest == TILEGX_R_ZERO)) {
>> +t0 = tcg_const_tl(imm & 0x);
>> +tcg_gen_st_tl(t0, cpu_env, offsetof(CPUTLGState, sigdata));
>> +tcg_temp_free(t0);
>> +} else {
>> +tcg_gen_addi_tl(tdest, tsrca, imm);
>> +}
>> mnemonic = "addli";
>> break;
>> case OE(ADDXLI_OPCODE_X0, 0, X0):
>>
>
> Certainly you should not be complicating addli like this.
>
OK, I'll try.
Thanks.
--
Chen Gang (陈刚)
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH] target-tilegx: Implement v*add and v*sub instructions
On 9/22/15 22:45, Richard Henderson wrote: > On 09/21/2015 10:54 PM, Chen Gang wrote: >> On 2015年09月19日 10:34, Richard Henderson wrote: >>> >>> There's a trick for this that's more efficient for 4 or more elements >>> per vector (i.e. good for v2 and v1, but not v4): >>> >>>a + b = (a & 0x7f7f7f7f) + (b & 0x7f7f7f7f)) ^ ((a ^ b) & 0x80808080) >>> >>>a - b = (a | 0x80808080) - (b & 0x7f7f7f7f)) ^ ((a ^ ~b) & 0x80808080) >>> >> >> For me, we need use "(a ^ b) & 0x80..." instead of "(a ^ ~b) & 0x80...". > > No. What you did wrong was not use (a | 0x80808080). > Oh, sorry. I shall send patch v3 for it. :-) Thanks. -- Chen Gang (陈刚) Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH] target-tilegx: Implement v*add and v*sub instructions
On 2015年09月19日 10:34, Richard Henderson wrote: > > There's a trick for this that's more efficient for 4 or more elements > per vector (i.e. good for v2 and v1, but not v4): > >a + b = (a & 0x7f7f7f7f) + (b & 0x7f7f7f7f)) ^ ((a ^ b) & 0x80808080) > >a - b = (a | 0x80808080) - (b & 0x7f7f7f7f)) ^ ((a ^ ~b) & 0x80808080) > For me, we need use "(a ^ b) & 0x80..." instead of "(a ^ ~b) & 0x80...". Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH v2] target-tilegx: Implement v1multu instruction
The related code are changed, so this patch has to be reconstructed.
Thanks
On 9/22/15 06:26, gang.chen.5...@gmail.com wrote:
> From: Chen Gang <gang.chen.5...@gmail.com>
>
> Only according to v1shrs implementation.
>
> Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
> Reviewed-by: Richard Henderson <r...@twiddle.net>
> ---
> target-tilegx/helper.h | 2 ++
> target-tilegx/simd_helper.c | 13 +
> target-tilegx/translate.c | 4
> 3 files changed, 19 insertions(+)
>
> diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
> index 6d98f3a..90e558d 100644
> --- a/target-tilegx/helper.h
> +++ b/target-tilegx/helper.h
> @@ -16,3 +16,5 @@ DEF_HELPER_FLAGS_2(v1add, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> DEF_HELPER_FLAGS_2(v1sub, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> DEF_HELPER_FLAGS_2(v2add, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> DEF_HELPER_FLAGS_2(v2sub, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> +
> +DEF_HELPER_FLAGS_2(v1multu, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> diff --git a/target-tilegx/simd_helper.c b/target-tilegx/simd_helper.c
> index 00265fe..b98573e 100644
> --- a/target-tilegx/simd_helper.c
> +++ b/target-tilegx/simd_helper.c
> @@ -107,3 +107,16 @@ uint64_t helper_v2shrs(uint64_t a, uint64_t b)
> }
> return r;
> }
> +
> +uint64_t helper_v1multu(uint64_t a, uint64_t b)
> +{
> + uint64_t r = 0;
> + int i;
> +
> + for (i = 0; i < 64; i += 8) {
> + uint64_t ae = (uint8_t)(a>> i);
> + uint64_t be = (uint8_t)(b>> i);
> + r |= ((ae * be) & 0xff) << i;
> + }
> + return r;
> +}
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> index 297de5c..a9fc4ce 100644
> --- a/target-tilegx/translate.c
> +++ b/target-tilegx/translate.c
> @@ -1113,7 +1113,11 @@ static TileExcp gen_rrr_opcode(DisasContext *dc,
> unsigned opext,
> case OE_RRR(V1MINU, 0, X1):
> case OE_RRR(V1MNZ, 0, X0):
> case OE_RRR(V1MNZ, 0, X1):
> + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> case OE_RRR(V1MULTU, 0, X0):
> + gen_helper_v1multu(tdest, tsrca, tsrcb);
> + mnemonic = "v1multu";
> + break;
> case OE_RRR(V1MULUS, 0, X0):
> case OE_RRR(V1MULU, 0, X0):
> case OE_RRR(V1MZ, 0, X0):
>
--
Chen Gang (陈刚)
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH v2] target-tilegx: Implement v*add and v*sub instructions
Oh, v1sub and v2sub look incorrect, need use ^b instead of ^~b.
Thanks.
> From: gang.chen.5...@gmail.com
> To: peter.mayd...@linaro.org; r...@twiddle.net
> CC: qemu-devel@nongnu.org; xili_gchen_5...@hotmail.com;
> gang.chen.5...@gmail.com
> Subject: [PATCH v2] target-tilegx: Implement v*add and v*sub instructions
> Date: Tue, 22 Sep 2015 06:18:38 +0800
>
> From: Chen Gang <gang.chen.5...@gmail.com>
>
> v4* are implemented in normal code, another are implemented in helper
> functions.
>
> Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
> ---
> target-tilegx/helper.h | 5 +
> target-tilegx/simd_helper.c | 23 +++
> target-tilegx/translate.c | 46
> +++--
> 3 files changed, 72 insertions(+), 2 deletions(-)
>
> diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
> index b253722..6d98f3a 100644
> --- a/target-tilegx/helper.h
> +++ b/target-tilegx/helper.h
> @@ -11,3 +11,8 @@ DEF_HELPER_FLAGS_2(v1shrs, TCG_CALL_NO_RWG_SE, i64, i64,
> i64)
> DEF_HELPER_FLAGS_2(v2shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> DEF_HELPER_FLAGS_2(v2shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> DEF_HELPER_FLAGS_2(v2shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> +
> +DEF_HELPER_FLAGS_2(v1add, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> +DEF_HELPER_FLAGS_2(v1sub, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> +DEF_HELPER_FLAGS_2(v2add, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> +DEF_HELPER_FLAGS_2(v2sub, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> diff --git a/target-tilegx/simd_helper.c b/target-tilegx/simd_helper.c
> index c03e31a..00265fe 100644
> --- a/target-tilegx/simd_helper.c
> +++ b/target-tilegx/simd_helper.c
> @@ -22,6 +22,29 @@
> #include "qemu-common.h"
> #include "exec/helper-proto.h"
>
> +uint64_t helper_v1add(uint64_t a, uint64_t b)
> +{
> +return ((a & 0x7f7f7f7f7f7f7f7fULL) + (b & 0x7f7f7f7f7f7f7f7fULL))
> + ^ ((a ^ b) & 0x8080808080808080ULL);
> +}
> +
> +uint64_t helper_v1sub(uint64_t a, uint64_t b)
> +{
> +return ((a & 0x7f7f7f7f7f7f7f7fULL) - (b & 0x7f7f7f7f7f7f7f7fULL))
> + ^ ((a ^ ~b) & 0x8080808080808080ULL);
> +}
> +
> +uint64_t helper_v2add(uint64_t a, uint64_t b)
> +{
> +return ((a & 0x7fff7fff7fff7fffULL) + (b & 0x7fff7fff7fff7fffULL))
> + ^ ((a ^ b) & 0x8000800080008000ULL);
> +}
> +
> +uint64_t helper_v2sub(uint64_t a, uint64_t b)
> +{
> +return ((a & 0x7fff7fff7fff7fffULL) - (b & 0x7fff7fff7fff7fffULL))
> + ^ ((a ^ ~b) & 0x8000800080008000ULL);
> +}
>
> uint64_t helper_v1shl(uint64_t a, uint64_t b)
> {
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> index 9228751..297de5c 100644
> --- a/target-tilegx/translate.c
> +++ b/target-tilegx/translate.c
> @@ -358,6 +358,26 @@ static void gen_v4sh(TCGv d64, TCGv a64, TCGv b64,
> tcg_temp_free_i32(bl);
> }
>
> +static void gen_v4op(TCGv d64, TCGv a64, TCGv b64,
> + void (*generate)(TCGv_i32, TCGv_i32, TCGv_i32))
> +{
> +TCGv_i32 al = tcg_temp_new_i32();
> +TCGv_i32 ah = tcg_temp_new_i32();
> +TCGv_i32 bl = tcg_temp_new_i32();
> +TCGv_i32 bh = tcg_temp_new_i32();
> +
> +tcg_gen_extr_i64_i32(al, ah, a64);
> +tcg_gen_extr_i64_i32(bl, bh, b64);
> +generate(al, al, bl);
> +generate(ah, ah, bh);
> +tcg_gen_concat_i32_i64(d64, al, ah);
> +
> +tcg_temp_free_i32(al);
> +tcg_temp_free_i32(ah);
> +tcg_temp_free_i32(bl);
> +tcg_temp_free_i32(bh);
> +}
> +
> static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
>unsigned dest, unsigned srca)
> {
> @@ -1043,8 +1063,12 @@ static TileExcp gen_rrr_opcode(DisasContext *dc,
> unsigned opext,
> break;
> case OE_RRR(V1ADDUC, 0, X0):
> case OE_RRR(V1ADDUC, 0, X1):
> +return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> case OE_RRR(V1ADD, 0, X0):
> case OE_RRR(V1ADD, 0, X1):
> +gen_helper_v1add(tdest, tsrca, tsrcb);
> +mnemonic = "v1add";
> +break;
> case OE_RRR(V1ADIFFU, 0, X0):
> case OE_RRR(V1AVGU, 0, X0):
> return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> @@ -1114,12 +1138,20 @@ static TileExcp gen_rrr_opcode(DisasContext *dc,
> unsigned opext,
> break;
> case OE_RRR(V1SUBUC, 0, X0):
> case OE_RRR(V1SUBUC, 0, X1):
> +return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> case OE_RRR(V1SUB, 0, X0):
> case OE_RRR(V1SUB, 0, X1):
> +gen_helper_v1sub(tdest, tsrca, tsrcb);
> +mnemonic = "v1sub";
>
Re: [Qemu-devel] [PATCH] target-tilegx: Implement v*add and v*sub instructions
On 9/19/15 10:34, Richard Henderson wrote:
> On 09/18/2015 05:03 PM, gang.chen.5...@gmail.com wrote:
>> +uint64_t helper_v1add(uint64_t a, uint64_t b)
>> +{
>> +uint64_t r = 0;
>> +int i;
>> +
>> +for (i = 0; i < 64; i += 8) {
>> +int64_t ae = (int8_t)(a >> i);
>> +int64_t be = (int8_t)(b >> i);
>> +r |= ((ae + be) & 0xff) << i;
>> +}
>> +return r;
>> +}
>> +
>> +uint64_t helper_v2add(uint64_t a, uint64_t b)
>> +{
>> +uint64_t r = 0;
>> +int i;
>> +
>> +for (i = 0; i < 64; i += 16) {
>> +int64_t ae = (int16_t)(a >> i);
>> +int64_t be = (int16_t)(b >> i);
>> +r |= ((ae + be) & 0x) << i;
>> +}
>> +return r;
>> +}
>
> There's a trick for this that's more efficient for 4 or more elements per
> vector (i.e. good for v2 and v1, but not v4):
>
>a + b = (a & 0x7f7f7f7f) + (b & 0x7f7f7f7f)) ^ ((a ^ b) & 0x80808080)
>
>a - b = (a | 0x80808080) - (b & 0x7f7f7f7f)) ^ ((a ^ ~b) & 0x80808080)
>
OK, thanks, for me, it is a good idea. :-)
>> +uint64_t helper_v4add(uint64_t a, uint64_t b)
>> +{
>> +uint64_t r = 0;
>> +int i;
>> +
>> +for (i = 0; i < 64; i += 32) {
>> +int64_t ae = (int32_t)(a >> i);
>> +int64_t be = (int32_t)(b >> i);
>> +r |= ((ae + be) & 0x) << i;
>> +}
>> +return r;
>> +}
>
> I should have mentioned this in the previous patch...
>
mm... maybe, but at least, I forgot.
> I think probably it would be best to open-code all, or most of, the v4
> operations. Something like
>
> static void gen_v4op(TCGv d64, TCGv a64, TCGv b64,
> void (*generate)(TCGv_i32, TCGv_i32, TCGv_i32))
> {
> TCGv_i32 al = tcg_temp_new_i32();
> TCGv_i32 ah = tcg_temp_new_i32();
> TCGv_i32 bl = tcg_temp_new_i32();
> TCGv_i32 bh = tcg_temp_new_i32();
>
> tcg_gen_extr_i64_i32(al, ah, a64);
> tcg_gen_extr_i64_i32(bl, bh, b64);
> generate(al, al, bl);
> generate(ah, ah, bh);
> tcg_gen_concat_i32_i64(d64, al, ah);
>
> tcg_temp_free_i32(al);
> tcg_temp_free_i32(ah);
> tcg_temp_free_i32(bl);
> tcg_temp_free_i32(bh);
> }
>
>> case OE_RRR(V4ADD, 0, X0):
>> case OE_RRR(V4ADD, 0, X1):
>> -return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
>> +gen_helper_v4add(tdest, tsrca, tsrcb);
>
> And then
>
> gen_v4op(tdest, tsrca, tsrcb, tcg_gen_add_i32);
>
OK, thanks. At least for me, what you said sounds reasonalbe.
Thanks.
--
Chen Gang (陈刚)
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH] target-tilegx: Implement v*shl, v*shru, and v*shrs instructions
On 9/19/15 10:09, Richard Henderson wrote:
> On 09/18/2015 04:41 PM, gang.chen.5...@gmail.com wrote:
>> +uint64_t helper_v4shl(uint64_t a, uint64_t b)
>> +{
>> +uint64_t m;
>> +
>> +b &= 63;
>
> 31. All of the v4 functions have the same error.
>
OK, thank you very much, I shall send patch v2 for it within the 2 days.
And sorry for replying late, (during this week end, I had to do some
personal things -- met some friends, and drunk).
Thanks.
--
Chen Gang (陈刚)
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PULL 00/35] TileGX basic instructions
OK, thanks. I got them in qemu master tree, and they have passed several simple tests. Next, I shall send several patches based on it (except floating point insns) for my current steps. Then continue to test gcc testsuite, hope we can finish it within this month. Thanks. On 9/15/15 23:03, Richard Henderson wrote: > With typos fixed from final review. > > > r~ > > > The following changes since commit b76a0d5db25ad9f81346930230092fdf1e88a5a1: > > Merge remote-tracking branch 'remotes/stefanha/tags/net-pull-request' into > staging (2015-09-15 13:03:53 +0100) > > are available in the git repository at: > > git://github.com/rth7680/qemu.git tags/pull-tile-20150915 > > for you to fetch changes up to 461aa6783eec27f209b026c6647fc7a83b2997cd: > > target-tilegx: Handle v1shl, v1shru, v1shrs (2015-09-15 07:45:34 -0700) > > > TileGX basic instructions > > ---- > Chen Gang (9): > linux-user: tilegx: Add architecture related features > linux-user: Support tilegx architecture in linux-user > linux-user: Conditionalize syscalls which are not defined in tilegx > target-tilegx: Add opcode basic implementation from Tilera Corporation > target-tilegx: Modify opcode_tilegx.h to fit QEMU usage > target-tilegx: Add special register information from Tilera Corporation > target-tilegx: Add cpu basic features for linux-user > target-tilegx: Add several helpers for instructions translation > target-tilegx: Add TILE-Gx building files > > Richard Henderson (26): > target-tilegx: Modify _SPECIAL_ opcodes > target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1 > target-tilegx: Framework for decoding bundles > target-tilegx: Generate SEGV properly > target-tilegx: Handle simple logical operations > target-tilegx: Handle arithmetic instructions > host-utils: Add revbit functions > target-arm: Use new revbit functions > target-tilegx: Handle most bit manipulation instructions > target-tilegx: Handle basic load and store instructions > target-tilegx: Handle post-increment load and store instructions > target-tilegx: Handle unconditional jump instructions > target-tilegx: Handle conditional branch instructions > target-tilegx: Handle comparison instructions > target-tilegx: Implement system and memory management instructions > target-tilegx: Handle bitfield instructions > target-tilegx: Handle shift instructions > target-tilegx: Handle conditional move instructions > target-tilegx: Handle scalar multiply instructions > target-tilegx: Handle mask instructions > target-tilegx: Handle v1cmpeq, v1cmpne > target-tilegx: Handle mtspr, mfspr > target-tilegx: Handle atomic instructions > target-tilegx: Handle v4int_l/h > target-tilegx: Handle v1shli, v1shrui > target-tilegx: Handle v1shl, v1shru, v1shrs > > configure |2 + > default-configs/tilegx-linux-user.mak |1 + > include/elf.h |2 + > include/qemu/host-utils.h | 77 ++ > linux-user/elfload.c | 23 + > linux-user/main.c | 238 > linux-user/syscall.c | 50 +- > linux-user/syscall_defs.h | 14 +- > linux-user/tilegx/syscall.h | 40 + > linux-user/tilegx/syscall_nr.h| 324 + > linux-user/tilegx/target_cpu.h| 35 + > linux-user/tilegx/target_signal.h | 28 + > linux-user/tilegx/target_structs.h| 46 + > linux-user/tilegx/termbits.h | 274 + > target-arm/helper-a64.c | 15 +- > target-arm/helper.c | 12 +- > target-tilegx/Makefile.objs |1 + > target-tilegx/cpu.c | 173 +++ > target-tilegx/cpu.h | 179 +++ > target-tilegx/helper.c| 80 ++ > target-tilegx/helper.h| 10 + > target-tilegx/opcode_tilegx.h | 1406 + > target-tilegx/simd_helper.c | 55 + > target-tilegx/spr_def_64.h| 216 > target-tilegx/translate.c | 2161 > + > 25 files changed, 5431 insertions(+), 31 deletions(-) > create mode 100644 default-configs/tilegx-linux-user.mak > create mode 100644 linux-user/tilegx/syscall.h > create mode 100644 linux-user/tilegx/syscall_nr.h > create mode 100644 linux-user/tilegx/target_cpu.h > create mode 100644 linux-user/tilegx/target_sign
Re: [Qemu-devel] [PULL 35/35] target-tilegx: Handle v1shl, v1shru, v1shrs
On 9/15/15 23:04, Richard Henderson wrote: [...] > +/* > + * QEMU TILE-Gx helpers > + * > + * Copyright (c) 2015 Chen Gang This file is totally implemented by you, so I guess, the Copyright name need be changed, too. :-) > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of [...] Thanks. -- Chen Gang (陈刚) Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PULL 11/35] target-tilegx: Framework for decoding bundles
On 9/15/15 23:03, Richard Henderson wrote: [...] > +/* > + * QEMU TILE-Gx CPU > + * > + * Copyright (c) 2015 Chen Gang > + * Since you rewrite this file, I guess, the copyright name need be also improved. > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see > + * <http://www.gnu.org/licenses/lgpl-2.1.html> > + */ [...] Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PULL 00/35] TileGX basic instructions
According to RTH implementation, I am sure, his current implementation must have fixed some issues which my original implementation will meet, next. At present, I shall firstly focus on the current status - merge original implementation to current implementation. And after comparing the test, the result is: send patches directly: raise: unimp (origin is ok) v1multu: unimp (origin is ok) v4add: unimp (origin is ok) vshl-vshr: unimp (origin is ok) need analyzing (it is easy, I guess): mm: abort (origin has no issue) pcnt:abort (origin has no issue) v1addi: abort (origin has no issue) let analyzing easier: try-pending: abort (origin causes pending). I shall try to fix them, and send patches. Then continue gcc testsuite. Thanks. On 9/16/15 23:20, Chen Gang wrote: > > OK, thanks. I got them in qemu master tree, and they have passed several > simple tests. > > Next, I shall send several patches based on it (except floating point > insns) for my current steps. > > Then continue to test gcc testsuite, hope we can finish it within this > month. > > > Thanks. > > On 9/15/15 23:03, Richard Henderson wrote: >> With typos fixed from final review. >> >> >> r~ >> >> >> The following changes since commit b76a0d5db25ad9f81346930230092fdf1e88a5a1: >> >> Merge remote-tracking branch 'remotes/stefanha/tags/net-pull-request' into >> staging (2015-09-15 13:03:53 +0100) >> >> are available in the git repository at: >> >> git://github.com/rth7680/qemu.git tags/pull-tile-20150915 >> >> for you to fetch changes up to 461aa6783eec27f209b026c6647fc7a83b2997cd: >> >> target-tilegx: Handle v1shl, v1shru, v1shrs (2015-09-15 07:45:34 -0700) >> >> ---- >> TileGX basic instructions >> >> >> Chen Gang (9): >> linux-user: tilegx: Add architecture related features >> linux-user: Support tilegx architecture in linux-user >> linux-user: Conditionalize syscalls which are not defined in tilegx >> target-tilegx: Add opcode basic implementation from Tilera Corporation >> target-tilegx: Modify opcode_tilegx.h to fit QEMU usage >> target-tilegx: Add special register information from Tilera Corporation >> target-tilegx: Add cpu basic features for linux-user >> target-tilegx: Add several helpers for instructions translation >> target-tilegx: Add TILE-Gx building files >> >> Richard Henderson (26): >> target-tilegx: Modify _SPECIAL_ opcodes >> target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1 >> target-tilegx: Framework for decoding bundles >> target-tilegx: Generate SEGV properly >> target-tilegx: Handle simple logical operations >> target-tilegx: Handle arithmetic instructions >> host-utils: Add revbit functions >> target-arm: Use new revbit functions >> target-tilegx: Handle most bit manipulation instructions >> target-tilegx: Handle basic load and store instructions >> target-tilegx: Handle post-increment load and store instructions >> target-tilegx: Handle unconditional jump instructions >> target-tilegx: Handle conditional branch instructions >> target-tilegx: Handle comparison instructions >> target-tilegx: Implement system and memory management instructions >> target-tilegx: Handle bitfield instructions >> target-tilegx: Handle shift instructions >> target-tilegx: Handle conditional move instructions >> target-tilegx: Handle scalar multiply instructions >> target-tilegx: Handle mask instructions >> target-tilegx: Handle v1cmpeq, v1cmpne >> target-tilegx: Handle mtspr, mfspr >> target-tilegx: Handle atomic instructions >> target-tilegx: Handle v4int_l/h >> target-tilegx: Handle v1shli, v1shrui >> target-tilegx: Handle v1shl, v1shru, v1shrs >> >> configure |2 + >> default-configs/tilegx-linux-user.mak |1 + >> include/elf.h |2 + >> include/qemu/host-utils.h | 77 ++ >> linux-user/elfload.c | 23 + >> linux-user/main.c | 238 >> linux-user/syscall.c | 50 +- >> linux-user/syscall_defs.h | 14 +- >> linux-user/tilegx/syscall.h | 40 + >> linux-user/tilegx/syscall_nr.h| 324 + >&
Re: [Qemu-devel] [PATCH] linux-user/syscall.c: Fix issue for checking ptr in different address spaces in TARGET_CMSG_NXTHDR
yes, foe me, they are the same. :-) Thanks. > From: peter.mayd...@linaro.org > Date: Tue, 15 Sep 2015 09:10:40 +0100 > Subject: Re: [PATCH] linux-user/syscall.c: Fix issue for checking ptr in > different address spaces in TARGET_CMSG_NXTHDR > To: gang.chen.5...@gmail.com > CC: riku.voi...@iki.fi; r...@twiddle.net; xili_gchen_5...@hotmail.com; > qemu-devel@nongnu.org > > On 15 September 2015 at 04:01, <gang.chen.5...@gmail.com> wrote: > > From: Chen Gang <gang.chen.5...@gmail.com> > > > > After fix this issue, qemu can run i386 wine notepad.exe successfully. > > But the initialization performance is not quite well. > > > > Signed-off-by: Chen Gang <gang.chen.5...@gmail.com> > > --- > > linux-user/syscall.c | 30 +- > > linux-user/syscall_defs.h | 20 +--- > > 2 files changed, 26 insertions(+), 24 deletions(-) > > Isn't this duplication of fixes in this patch currently on-list? > > https://lists.gnu.org/archive/html/qemu-devel/2015-09/msg00680.html > > thanks > -- PMM
Re: [Qemu-devel] [PATCH] linux-user/signal.c: Fix several issues for target alpha
On 9/15/15 01:13, Richard Henderson wrote:
> On 09/12/2015 08:15 PM, gang.chen.5...@gmail.com wrote:
>> env->ir[IR_RA] = r26;
>> env->ir[IR_PV] = env->pc = ka->_sa_handler;
>> env->ir[IR_A0] = sig;
>> env->ir[IR_A1] = 0;
>> env->ir[IR_A2] = frame_addr + offsetof(struct target_sigframe, sc);
>> env->ir[IR_SP] = frame_addr;
>> +
>> +give_sigsegv:
>> +if (sig == TARGET_SIGSEGV) {
>> +ka->_sa_handler = TARGET_SIG_DFL;
>> +}
>> +force_sig(TARGET_SIGSEGV);
>> }
>
> Fallthrough into the sigsegv handler?
> That's clearly wrong.
>
OK, thanks. Need add "return" before "give_sigsegv". I shall send patch
v2 for it.
Thanks.
--
Chen Gang (陈刚)
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH] linux-user/signal.c: Use setup_rt_frame() instead of setup_frame() for target openrisc
On 9/13/15 00:23, Peter Maydell wrote: > On 12 September 2015 at 16:32, <gang.chen.5...@gmail.com> wrote: >> From: Chen Gang <gang.chen.5...@gmail.com> >> >> qemu has already considered about some targets may have no traditional >> signals. And openrisc's setup_frame() is dummy, but it can be supported >> by setup_rt_frame(). >> >> Signed-off-by: Chen Gang <gang.chen.5...@gmail.com> >> --- >> linux-user/signal.c | 9 ++--- >> 1 file changed, 2 insertions(+), 7 deletions(-) > > Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> > Thank you very much. I am just analyzing the raise insn about tilegx, and shall implement the related code in signal.c, your Reviewed-by is very helpful for it. :-) Thanks. -- Chen Gang (陈刚) Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH] linux-user/main.c: Always set QEMU_LD_PREFIX when interp_prefix is changed
From: peter.mayd...@linaro.org > Date: Thu, 10 Sep 2015 10:02:27 +0100 > > On 10 September 2015 at 06:43, <gang.chen.5...@gmail.com> wrote: >> From: Chen Gang <gang.chen.5...@gmail.com> >> >> If qemu sets interp_prfix via command line '-L' instead of environments >> variable QEMU_LD_PREFIX, it will cause syscall execve() failed. Because >> the 2nd qemu has no command line '-L'. >> >> So qemu need always set QEMU_LD_PREFIX when interp_prefix is changed. > > I think this is user error. If you want exec to work automatically > onto a second QEMU then you need to set up binfmt misc with a > wrapper and probably the environment variables. I don't > think we need to turn all our command line switches into > environment variables: they're not supposed to be somehow > magically inherited by child QEMU processes. > For me, when users type a command line under Linux shell, they always assume all related executions will know about their commands, they need not set the environments again (at least, in one process, they assume so). execve() will not change the pid, so the users will 'feel': they are using only one process. I guess all 'users' will support me (this patch will let them a little easier). ;-) Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH] linux-user/main.c: Always set QEMU_LD_PREFIX when interp_prefix is changed
Oh, this issue may be for all command lines (e.g. -d option), I guess, we need process them all in main() when process command line options. > Subject: Re: [PATCH] linux-user/main.c: Always set QEMU_LD_PREFIX when > interp_prefix is changed > To: riku.voi...@iki.fi > CC: r...@twiddle.net; peter.mayd...@linaro.org; qemu-devel@nongnu.org > From: xili_gchen_5...@hotmail.com > Date: Thu, 10 Sep 2015 13:49:18 +0800 > > On 2015年09月10日 13:43, gang.chen.5...@gmail.com wrote: >> From: Chen Gang <gang.chen.5...@gmail.com> >> >> If qemu sets interp_prfix via command line '-L' instead of environments >> variable QEMU_LD_PREFIX, it will cause syscall execve() failed. Because >> the 2nd qemu has no command line '-L'. >> > > Oh, sorry for typo, "the 2nd" -> "the second". > >> So qemu need always set QEMU_LD_PREFIX when interp_prefix is changed. >> >> Signed-off-by: Chen Gang <gang.chen.5...@gmail.com> > > > Thanks. > -- > Chen Gang > > Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH v2] linux-user/main.c: Set environments variables from command line options
Oh, very sorry! The patch v2 did not process simple options (e.g. -strace).
I should send patch v3 for it.
Thanks.
> From: gang.chen.5...@gmail.com
> To: riku.voi...@iki.fi
> CC: r...@twiddle.net; peter.mayd...@linaro.org; xili_gchen_5...@hotmail.com;
> qemu-devel@nongnu.org; gang.chen.5...@gmail.com
> Subject: [PATCH v2] linux-user/main.c: Set environments variables from
> command line options
> Date: Thu, 10 Sep 2015 16:10:22 +0800
>
> From: Chen Gang <gang.chen.5...@gmail.com>
>
> When qemu execute execve() system call, the related command line options
> can not be passed to the second qemu process, which causes the second
> process fail.
>
> Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
> ---
> linux-user/main.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/linux-user/main.c b/linux-user/main.c
> index 06dd296..f1f5496 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -3767,6 +3767,7 @@ static void usage(void)
> static int parse_args(int argc, char **argv)
> {
> const char *r;
> + char *buf;
> int optind;
> const struct qemu_argument *arginfo;
>
> @@ -3802,6 +3803,9 @@ static int parse_args(int argc, char **argv)
> if (optind>= argc) {
> usage();
> }
> + buf = g_strdup_printf("%s=%s", arginfo->env, argv[optind]);
> + (void) envlist_setenv(envlist, buf);
> + g_free(buf);
> arginfo->handle_opt(argv[optind]);
> optind++;
> } else {
> --
> 1.9.1
>
>
Re: [Qemu-devel] [PATCH] linux-user/main.c: Always set QEMU_LD_PREFIX when interp_prefix is changed
On 9/10/15 23:24, Peter Maydell wrote: > On 10 September 2015 at 16:15, Chen Gang <xili_gchen_5...@hotmail.com> wrote: >> Yes, we have to use binfmt_misc to let execve() run correctly. After >> let execve() run correctly, I am analyzing another issue when let qemu >> run wine (it is a pending issue, I guess, it is related with mmu). >> >> At present, I often change the input parameters (e.g. -strace, -d ...), >> if we let a qemu process itself always know about its input parameters, >> it will be really useful. > > If you want settings to apply to all child qemu processes, use the > environment variables... that is one of the things they are for. > Yes it will be work well. :-) >> For qemu, I still feel that we need notice about the mismatch between >> env variables and input parameters. >> >> - If we are sure the input parameters are only for one normal process, >>we need not care about the mismatch between env variables and input >>parameters (I guess, most of programs need not care about it). >> >> - But if we have to process the un-normal process (e.g. our qemu), we >>have to notice about the mismatch between evn variables and input >>parameters. Or command line users may meet various strange things. >> >> - Since we provide the command line options, we have to always let them >>be correct within one normal or un-normal process. > > I think it would be unexpected behaviour for command line arguments > provided to one QEMU program to affect the execution of a different > QEMU process. > For me, I guess, it should be still OK: - For execve(), the input parameters should always have effect with ( since we treate it as one un-normal process). - For other QEMU cases (really different QEMU child processes). If they have their own command line options, the will override the env variables which may be set by original command line parameters. If they have no their own command line options, they need inherit the parent QEMU process's command line options (e.g. -strace, -d ...). Thanks. -- Chen Gang (陈刚) Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions
Hello all: It looks tilegx still outside of qemu master tree. I guess, I have to still use my own implementation to continue analyzing gcc testsuite (or I am not quite sure whether I can finish analyzing within this month). Welcome any ideas, suggestions and completions. Thanks. On 8/30/15 12:09, Chen Gang wrote: > > After download and merge the all related patches to my local qemu, for > me: > > - The refactor code is really very good to me! :-) > > - It cause "hello world" test program "segment fault". > > Do we need fix all related issues before merge the code? > > - If I need fix them after finish merging the refactor code into qemu >master, please let me know, I shall try, next. > > - If it is necessary to provide related test programs, please let me >know, I shall provide them to. > > Thanks. > > On 8/29/15 21:19, Chen Gang wrote: >> >> Is tilegx patches OK to qemu mater tree? >> >> Or shall I do anything for it? If I should do something for it, please >> let me know, I shall try. >> >> I almost finished analyzing one gcc bug (found root cause, got correct >> result with my patch), it was waiting review. If I needn't do anything >> for tilegx merging, I shall continue to analyze tilegx gcc testsuite. >> >> Thanks. >> >> On 8/25/15 06:12, Chen Gang wrote: >>> >>> On 8/25/15 00:17, Richard Henderson wrote: >>>> I've flushed out the v13 I posted last Thursday to handle all the >>>> instructions required to execute Hello World. In the process I >>>> found a number of bugs and design flaws in v13, and reshaped the >>>> translation a bit to better handle insns with no register outputs. >>>> >>> >>> OK, thank you for your work (originally, I really did not kown that it >>> would generate so many patches -- almost 3 times that I supposed). >>> >>> >>>> Please review. >>>> >>>> After this, I would hope that Chen Gang will follow up to implement >>>> the rest of the instructions that he has identified running the >>>> gcc testsuite, and then start in on the floating point. >>>> >>> >>> OK, thanks, I shall continue based on it, after it is integrated into >>> qemu master (after Reviewed-by another members). >>> >>> During the next 2-4 days I shall try to fix one gcc bugzilla issue, then >>> turn back to qemu, hope I can succeed. (during these passed days, I sent >>> 3 paches to kernel, and 2 of them are applied, one is waiting review). >>> >>> >>> Thanks. >>> >>>> >>>> r~ >>>> >>>> >>>> Chen Gang (9): >>>> linux-user: tilegx: Firstly add architecture related features >>>> linux-user: Support tilegx architecture in linux-user >>>> linux-user: Conditionalize syscalls which are not defined in tilegx >>>> target-tilegx: Add opcode basic implementation from Tilera Corporation >>>> target-tilegx: Modify opcode_tilegx.h to fit QEMU usage >>>> target-tilegx: Add special register information from Tilera >>>> Corporation >>>> target-tilegx: Add cpu basic features for linux-user >>>> target-tilegx: Add several helpers for instructions translation >>>> target-tilegx: Add TILE-Gx building files >>>> >>>> Richard Henderson (24): >>>> target-tilegx: Modify _SPECIAL_ opcodes >>>> target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1 >>>> target-tilegx: Framework for decoding bundles >>>> target-tilegx: Generate SEGV properly >>>> target-tilegx: Handle simple logical operations >>>> target-tilegx: Handle arithmetic instructions >>>> target-tilegx: Handle most bit manipulation instructions >>>> target-tilegx: Handle basic load and store instructions >>>> target-tilegx: Handle post-increment load and store instructions >>>> target-tilegx: Handle unconditional jump instructions >>>> target-tilegx: Handle conditional branch instructions >>>> target-tilegx: Handle comparison instructions >>>> target-tilegx: Implement system and memory management instructions >>>> target-tilegx: Handle bitfield instructions >>>> target-tilegx: Handle shift instructions >>>> target-tilegx: Handle conditional move instructions >>>> target-tilegx: Handle scalar multiply instructions >>>> target-tilegx: Handle mask instructions >>>> target-tilegx: Handle v1cmpeq, v1cmpne &g
Re: [Qemu-devel] [PATCH] linux-user/main.c: Always set QEMU_LD_PREFIX when interp_prefix is changed
On 9/10/15 20:35, Peter Maydell wrote: > On 10 September 2015 at 10:32, Chen Gang <xili_gchen_5...@hotmail.com> wrote: >> >> For me, when users type a command line under Linux shell, they always >> assume all related executions will know about their commands, they need >> not set the environments again (at least, in one process, they assume so). >> >> execve() will not change the pid, so the users will 'feel': they are using >> only >> one process. > > But execve won't do the right thing if it's another target binary, > unless you've set up binfmt_misc. And if you're setting up > binfmt_misc then (a) you should just do it right and (b) you > wouldn't have been directly running QEMU with command line > arguments in the first place. > Yes, we have to use binfmt_misc to let execve() run correctly. After let execve() run correctly, I am analyzing another issue when let qemu run wine (it is a pending issue, I guess, it is related with mmu). At present, I often change the input parameters (e.g. -strace, -d ...), if we let a qemu process itself always know about its input parameters, it will be really useful. For qemu, I still feel that we need notice about the mismatch between env variables and input parameters. - If we are sure the input parameters are only for one normal process, we need not care about the mismatch between env variables and input parameters (I guess, most of programs need not care about it). - But if we have to process the un-normal process (e.g. our qemu), we have to notice about the mismatch between evn variables and input parameters. Or command line users may meet various strange things. - Since we provide the command line options, we have to always let them be correct within one normal or un-normal process. Thanks -- Chen Gang (陈刚) Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH] linux-user: elfload: Still use TARGET_PAGE_SIZE for i386 guest
On 2015年08月12日 17:00, gchen gchen wrote: > > - At present, x86_64 laptop run arm linux-user run i386 linux-user run >wine run Windows i386 graphic programs are OK, the performance is >acceptable! the qemu code keeps no touch -- our qemu is very good!!!. > Oh, sorry, wine will use execve(), then qemu will use host execve(), under x86_64, the i386 wine will be executed directly. But I guess, at present, the performance is still OK, I have let i386 xcalc run successfully under sw_64. It looks very good. :-) Next, I shall have to analyze wine, too, so can let wine and qemu work together correctly. Welcome any ideas, suggestions, and completions. Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH] linux-user/main.c: Always set QEMU_LD_PREFIX when interp_prefix is changed
On 2015年09月10日 13:43, gang.chen.5...@gmail.com wrote: > From: Chen Gang <gang.chen.5...@gmail.com> > > If qemu sets interp_prfix via command line '-L' instead of environments > variable QEMU_LD_PREFIX, it will cause syscall execve() failed. Because > the 2nd qemu has no command line '-L'. > Oh, sorry for typo, "the 2nd" -> "the second". > So qemu need always set QEMU_LD_PREFIX when interp_prefix is changed. > > Signed-off-by: Chen Gang <gang.chen.5...@gmail.com> Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 0/2] alpha-host: Add Alpha host tcg backend to latest QEMU
Hello: Could any members tell me whether he/she can receive the patches (patch 1/2, 2/2 for alpha-host) via my qq mail address? It only seems OK, but I am not quite sure (really not sure). Thanks. On 8/31/15 17:17, Chen Gang wrote: > On 2015年08月31日 16:59, gang.chen.5...@gmail.com wrote: >> From: Chen Gang <gang.chen.5...@gmail.com> >> >> It is only for version merging, no any functional modification. >> >> Chen Gang (2): >> alpha-host: Add Alpha host tcg backend. >> alpha-host: Fix alpha host related merging issues. >> > > It is only for version merging, so I only split it into 2 patches, if > more splitting patches are necessary, please let me know, I shall send > patches v2 for it. > > And also, it is my first time to send patches with git client via my qq > mail address, if it causes any issues which I don't know (e.g. it cann't > be accepted by qemu-devel mailing list), please let me know. > > Thanks. > >> configure | 16 +- >> include/exec/exec-all.h | 11 +- >> include/qemu-common.h | 4 +- >> tcg/alpha/tcg-target.c | 1934 +++ >> tcg/alpha/tcg-target.h | 169 + >> translate-all.c | 2 + >> user-exec.c | 4 +- >> 7 files changed, 2128 insertions(+), 12 deletions(-) >> create mode 100644 tcg/alpha/tcg-target.c >> create mode 100644 tcg/alpha/tcg-target.h >> > > -- > Chen Gang > > Open, share, and attitude like air, water, and life which God blessed > > -- Chen Gang (陈刚) Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 0/2] alpha-host: Add Alpha host tcg backend to latest QEMU
On 9/5/15 21:18, Max Filippov wrote: > On Sat, Sep 5, 2015 at 1:18 PM, Chen Gang <xili_gchen_5...@hotmail.com> wrote: >> Could any members tell me whether he/she can receive the patches (patch >> 1/2, 2/2 for alpha-host) via my qq mail address? >> >> It only seems OK, but I am not quite sure (really not sure). > > I saw these: > http://lists.nongnu.org/archive/html/qemu-devel/2015-08/msg03924.html > OK, thank you very much for your reply. :-) From you reply, I not only know about qemu accept git client from qq email, but also know how to check whether my mail is really sent or not (check the mail archive list in the web site). Thanks. -- Chen Gang (陈刚) Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH v15 01/33] linux-user: tilegx: Firstly add architecture related features
On 9/3/15 22:53, Eric Blake wrote: > On 09/02/2015 07:30 PM, Richard Henderson wrote: >> From: Chen Gang <xili_gchen_5...@hotmail.com> > > s/Firstly add/Add/ in the subject line > Thank you for your careful notification. :-) I guess, it will be modified by RTH, before the patches v15 (or v16) are integrated into qemu master tree. If I should do anything for it, please let me know. Thanks -- Chen Gang (陈刚) Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 0/2] alpha-host: Add Alpha host tcg backend to latest QEMU
On 2015年08月31日 16:59, gang.chen.5...@gmail.com wrote: > From: Chen Gang <gang.chen.5...@gmail.com> > > It is only for version merging, no any functional modification. > > Chen Gang (2): > alpha-host: Add Alpha host tcg backend. > alpha-host: Fix alpha host related merging issues. > It is only for version merging, so I only split it into 2 patches, if more splitting patches are necessary, please let me know, I shall send patches v2 for it. And also, it is my first time to send patches with git client via my qq mail address, if it causes any issues which I don't know (e.g. it cann't be accepted by qemu-devel mailing list), please let me know. Thanks. > configure | 16 +- > include/exec/exec-all.h | 11 +- > include/qemu-common.h |4 +- > tcg/alpha/tcg-target.c | 1934 > +++ > tcg/alpha/tcg-target.h | 169 + > translate-all.c |2 + > user-exec.c |4 +- > 7 files changed, 2128 insertions(+), 12 deletions(-) > create mode 100644 tcg/alpha/tcg-target.c > create mode 100644 tcg/alpha/tcg-target.h > -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions
Is tilegx patches OK to qemu mater tree? Or shall I do anything for it? If I should do something for it, please let me know, I shall try. I almost finished analyzing one gcc bug (found root cause, got correct result with my patch), it was waiting review. If I needn't do anything for tilegx merging, I shall continue to analyze tilegx gcc testsuite. Thanks. On 8/25/15 06:12, Chen Gang wrote: On 8/25/15 00:17, Richard Henderson wrote: I've flushed out the v13 I posted last Thursday to handle all the instructions required to execute Hello World. In the process I found a number of bugs and design flaws in v13, and reshaped the translation a bit to better handle insns with no register outputs. OK, thank you for your work (originally, I really did not kown that it would generate so many patches -- almost 3 times that I supposed). Please review. After this, I would hope that Chen Gang will follow up to implement the rest of the instructions that he has identified running the gcc testsuite, and then start in on the floating point. OK, thanks, I shall continue based on it, after it is integrated into qemu master (after Reviewed-by another members). During the next 2-4 days I shall try to fix one gcc bugzilla issue, then turn back to qemu, hope I can succeed. (during these passed days, I sent 3 paches to kernel, and 2 of them are applied, one is waiting review). Thanks. r~ Chen Gang (9): linux-user: tilegx: Firstly add architecture related features linux-user: Support tilegx architecture in linux-user linux-user: Conditionalize syscalls which are not defined in tilegx target-tilegx: Add opcode basic implementation from Tilera Corporation target-tilegx: Modify opcode_tilegx.h to fit QEMU usage target-tilegx: Add special register information from Tilera Corporation target-tilegx: Add cpu basic features for linux-user target-tilegx: Add several helpers for instructions translation target-tilegx: Add TILE-Gx building files Richard Henderson (24): target-tilegx: Modify _SPECIAL_ opcodes target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1 target-tilegx: Framework for decoding bundles target-tilegx: Generate SEGV properly target-tilegx: Handle simple logical operations target-tilegx: Handle arithmetic instructions target-tilegx: Handle most bit manipulation instructions target-tilegx: Handle basic load and store instructions target-tilegx: Handle post-increment load and store instructions target-tilegx: Handle unconditional jump instructions target-tilegx: Handle conditional branch instructions target-tilegx: Handle comparison instructions target-tilegx: Implement system and memory management instructions target-tilegx: Handle bitfield instructions target-tilegx: Handle shift instructions target-tilegx: Handle conditional move instructions target-tilegx: Handle scalar multiply instructions target-tilegx: Handle mask instructions target-tilegx: Handle v1cmpeq, v1cmpne target-tilegx: Handle mtspr, mfspr target-tilegx: Handle atomic instructions target-tilegx: Handle v4int_l/h target-tilegx: Handle v1shli, v1shrui target-tilegx: Handle v1shl, v1shru, v1shrs configure | 2 + default-configs/tilegx-linux-user.mak | 1 + include/elf.h | 2 + linux-user/elfload.c | 23 + linux-user/main.c | 298 + linux-user/syscall.c | 50 +- linux-user/syscall_defs.h | 14 +- linux-user/tilegx/syscall.h | 40 + linux-user/tilegx/syscall_nr.h | 324 + linux-user/tilegx/target_cpu.h | 35 + linux-user/tilegx/target_signal.h | 28 + linux-user/tilegx/target_structs.h | 46 + linux-user/tilegx/termbits.h | 274 + target-tilegx/Makefile.objs | 1 + target-tilegx/cpu.c | 173 +++ target-tilegx/cpu.h | 177 +++ target-tilegx/helper.c | 93 ++ target-tilegx/helper.h | 10 + target-tilegx/opcode_tilegx.h | 1406 ++ target-tilegx/simd_helper.c | 63 + target-tilegx/spr_def_64.h | 216 target-tilegx/translate.c | 2135 + 22 files changed, 5405 insertions(+), 6 deletions(-) create mode 100644 default-configs/tilegx-linux-user.mak create mode 100644 linux-user/tilegx/syscall.h create mode 100644 linux-user/tilegx/syscall_nr.h create mode 100644 linux-user/tilegx/target_cpu.h create mode 100644 linux-user/tilegx/target_signal.h create mode 100644 linux-user/tilegx/target_structs.h create mode 100644 linux-user/tilegx/termbits.h create mode 100644 target-tilegx/Makefile.objs create mode 100644 target-tilegx/cpu.c create mode 100644 target-tilegx/cpu.h create mode 100644 target-tilegx/helper.c create mode 100644 target-tilegx/helper.h create mode 100644 target-tilegx/opcode_tilegx.h create mode 100644 target-tilegx/simd_helper.c create mode 100644 target-tilegx/spr_def_64.h create mode 100644 target-tilegx/translate.c -- Chen Gang Open, share, and attitude like air, water, and life which God blessed -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions
After download and merge the all related patches to my local qemu, for me: - The refactor code is really very good to me! :-) - It cause hello world test program segment fault. Do we need fix all related issues before merge the code? - If I need fix them after finish merging the refactor code into qemu master, please let me know, I shall try, next. - If it is necessary to provide related test programs, please let me know, I shall provide them to. Thanks. On 8/29/15 21:19, Chen Gang wrote: Is tilegx patches OK to qemu mater tree? Or shall I do anything for it? If I should do something for it, please let me know, I shall try. I almost finished analyzing one gcc bug (found root cause, got correct result with my patch), it was waiting review. If I needn't do anything for tilegx merging, I shall continue to analyze tilegx gcc testsuite. Thanks. On 8/25/15 06:12, Chen Gang wrote: On 8/25/15 00:17, Richard Henderson wrote: I've flushed out the v13 I posted last Thursday to handle all the instructions required to execute Hello World. In the process I found a number of bugs and design flaws in v13, and reshaped the translation a bit to better handle insns with no register outputs. OK, thank you for your work (originally, I really did not kown that it would generate so many patches -- almost 3 times that I supposed). Please review. After this, I would hope that Chen Gang will follow up to implement the rest of the instructions that he has identified running the gcc testsuite, and then start in on the floating point. OK, thanks, I shall continue based on it, after it is integrated into qemu master (after Reviewed-by another members). During the next 2-4 days I shall try to fix one gcc bugzilla issue, then turn back to qemu, hope I can succeed. (during these passed days, I sent 3 paches to kernel, and 2 of them are applied, one is waiting review). Thanks. r~ Chen Gang (9): linux-user: tilegx: Firstly add architecture related features linux-user: Support tilegx architecture in linux-user linux-user: Conditionalize syscalls which are not defined in tilegx target-tilegx: Add opcode basic implementation from Tilera Corporation target-tilegx: Modify opcode_tilegx.h to fit QEMU usage target-tilegx: Add special register information from Tilera Corporation target-tilegx: Add cpu basic features for linux-user target-tilegx: Add several helpers for instructions translation target-tilegx: Add TILE-Gx building files Richard Henderson (24): target-tilegx: Modify _SPECIAL_ opcodes target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1 target-tilegx: Framework for decoding bundles target-tilegx: Generate SEGV properly target-tilegx: Handle simple logical operations target-tilegx: Handle arithmetic instructions target-tilegx: Handle most bit manipulation instructions target-tilegx: Handle basic load and store instructions target-tilegx: Handle post-increment load and store instructions target-tilegx: Handle unconditional jump instructions target-tilegx: Handle conditional branch instructions target-tilegx: Handle comparison instructions target-tilegx: Implement system and memory management instructions target-tilegx: Handle bitfield instructions target-tilegx: Handle shift instructions target-tilegx: Handle conditional move instructions target-tilegx: Handle scalar multiply instructions target-tilegx: Handle mask instructions target-tilegx: Handle v1cmpeq, v1cmpne target-tilegx: Handle mtspr, mfspr target-tilegx: Handle atomic instructions target-tilegx: Handle v4int_l/h target-tilegx: Handle v1shli, v1shrui target-tilegx: Handle v1shl, v1shru, v1shrs configure | 2 + default-configs/tilegx-linux-user.mak | 1 + include/elf.h | 2 + linux-user/elfload.c | 23 + linux-user/main.c | 298 + linux-user/syscall.c | 50 +- linux-user/syscall_defs.h | 14 +- linux-user/tilegx/syscall.h | 40 + linux-user/tilegx/syscall_nr.h | 324 + linux-user/tilegx/target_cpu.h | 35 + linux-user/tilegx/target_signal.h | 28 + linux-user/tilegx/target_structs.h | 46 + linux-user/tilegx/termbits.h | 274 + target-tilegx/Makefile.objs | 1 + target-tilegx/cpu.c | 173 +++ target-tilegx/cpu.h | 177 +++ target-tilegx/helper.c | 93 ++ target-tilegx/helper.h | 10 + target-tilegx/opcode_tilegx.h | 1406 ++ target-tilegx/simd_helper.c | 63 + target-tilegx/spr_def_64.h | 216 target-tilegx/translate.c | 2135 + 22 files changed, 5405 insertions(+), 6 deletions(-) create mode 100644 default-configs/tilegx-linux-user.mak create mode 100644 linux-user/tilegx/syscall.h create mode 100644 linux-user/tilegx/syscall_nr.h create mode 100644 linux-user/tilegx/target_cpu.h create mode 100644 linux-user/tilegx/target_signal.h create mode 100644 linux-user/tilegx/target_structs.h create mode 100644 linux-user/tilegx/termbits.h create mode 100644 target-tilegx/Makefile.objs create mode 100644 target
Re: [Qemu-devel] [PATCH v14 11/33] target-tilegx: Framework for decoding bundles
On 8/29/15 22:50, Peter Maydell wrote:
On 24 August 2015 at 17:17, Richard Henderson r...@twiddle.net wrote:
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, % PRIx64 : { , dc-pc);
+ if (get_Mode(bundle)) {
+ notice_excp(dc, bundle, y0, decode_y0(dc, bundle));
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, ; );
+ notice_excp(dc, bundle, y1, decode_y1(dc, bundle));
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, ; );
+ notice_excp(dc, bundle, y2, decode_y2(dc, bundle));
+ } else {
+ notice_excp(dc, bundle, x0, decode_x0(dc, bundle));
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, ; );
+ notice_excp(dc, bundle, x1, decode_x1(dc, bundle));
+ }
I notice that even if the first insn in a bundle generates an
exception we'll go ahead and generate unreachable code for
the rest.
I haven't tried to find and compare against any instruction
set documentation, but structurally it looks good, so
For me, I am not quite sure it is really safe, more explanations are
welcomed.
And for each bundle, I still suggest to:
- buffering dest regs in temp regs for each pipe.
- buffering 1st exception information in env for the related pipe.
- flush temp regs to dest regs.
- gen exception based on the env information.
I assumed all exceptions which can still let working flow continue are
all in pipe x1 (at present, it should be corret), so it is enough for us
to only process 1st exception of bundle.
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] Plan for using softmmu with linux-user
On 2015年08月19日 16:01, gchen gchen wrote: On 2015年08月15日 04:45, Chen Gang wrote: On 8/14/15 22:44, Richard Henderson wrote: On 08/14/2015 02:37 AM, gchen gchen wrote: - If I implement SW64 tcg backend, I guess, I cann't get help from qemu upstream: I don't think SW64 is valuable enough for upstream (either I am not sure that I can implment Alpha tcg backend in working time). It'll need some updating to apply to master, but I started an alpha backend a couple of years ago. It looks like it was last rebased in May 2014. git://github.com/rth7680/qemu.git tcg-alpha-2 Really thank you very much again!! I have implemented sw_64 tcg back end, its performance is much better than tci (10 times faster for testing i386 bash). I guess at present, our qemu performance should be enough for my current using. :-) And next, I shall try to merge alpha related code to the latest qemu, and send patches for it. Hope it is useful for our qemu (since no any additional reply for it, I guess I should try to send patches for it). Thanks. After get sw_64 pc, it is much slower than I guess (it is much slower than my intel x86_64 laptop which was made in 2007-2008). So I have to use tcg backend instead of tci. Will qemu upstream accept alpha tcg backend to master tree? If possible I can do it in my working time (after simply trying, I am sure, alpha tcg backend can not work if only simply merge and let it pass building). By the way, for me, I have to process alpha/sw_64 tcg backend firstly, then process softmmu + linux-user. Welcome any ideas, suggestions, and completions. Thanks. Thank you very much, I shall clone it. I guess, it will save my much time resources. If possible, it will be better to merge the alpha tcg backend to qemu master main branch (at least for me, it is useful). :-) -- Chen Gang Open, share, and attitude like air, water, and life which God blessed -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions
On 8/25/15 12:15, Richard Henderson wrote:
On 08/24/2015 09:17 AM, Richard Henderson wrote:
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-tilegx/translate.c | 50
++-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 210e912..2a0798a 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -180,6 +180,19 @@ static void gen_saturate_op(TCGv tdest, TCGv tsrca,
TCGv tsrcb,
tcg_temp_free(t0);
}
+static void gen_atomic_excp(DisasContext *dc, unsigned dest, unsigned srca,
+ unsigned srcb, TileExcp excp)
+{
+#ifdef CONFIG_USER_ONLY
+ TCGv_i32 t = tcg_const_i32((dest 16) | (srca 8) | srcb);
+ tcg_gen_st_i32(t, cpu_env, offsetof(CPUTLGState, excparam));
+ tcg_temp_free_i32(t);
+ gen_exception(dc, excp);
+#else
+ gen_exception(dc, TILEGX_EXCP_OPCODE_UNIMPLEMENTED);
+#endif
+}
Originally, I used set_exception(), not gen_exception().
This is broken. While it does work well enough for Hello World, implementing
a non-trap instruction with an exception is extremely dicey for TileGX. The
issue is that TileGX bundles operate atomically, with no RAW issues between
the instructions of the bundle.
Consider a bundle like
{ add r0, r0, r1 ; exch r2, r0, r3 }
In Chen's implementation, the writeback to r0 would occur before the
exception, and so the exch would happen to the wrong address. In my
implementation here, the exception would occur before the writeback, and so
the result of the add would be discarded.
We use tmp regs for buffering the r0.
- calculate x1 pipe, and save result to r0 tmp reg.
- exch the original r0 and r3 to r2 tmp reg.
- set exception flag (which will cause exception, later).
- save the result tmp regs to r0 or r2.
- gen exception.
While retaining the current start_exclusive scheme, it would appear that we
need to store more data here -- to wit, the contents of the registers not
their numbers -- and delay the exception until after writeback.
Even better, of course, would be to not exit the TB at all, and use host
atomic instructions... I suppose that multi-threading patch set is still in
limbo?
I guess, we need not.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions
From: xili_gchen_5...@hotmail.com
To: r...@twiddle.net; qemu-devel@nongnu.org
CC: w...@tilera.com; cmetc...@ezchip.com; peter.mayd...@linaro.org
Subject: Re: [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic
instructions
Date: Tue, 25 Aug 2015 21:11:11 +0800
On 8/25/15 12:15, Richard Henderson wrote:
On 08/24/2015 09:17 AM, Richard Henderson wrote:
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-tilegx/translate.c | 50
++-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 210e912..2a0798a 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -180,6 +180,19 @@ static void gen_saturate_op(TCGv tdest, TCGv tsrca,
TCGv tsrcb,
tcg_temp_free(t0);
}
+static void gen_atomic_excp(DisasContext *dc, unsigned dest, unsigned srca,
+ unsigned srcb, TileExcp excp)
+{
+#ifdef CONFIG_USER_ONLY
+ TCGv_i32 t = tcg_const_i32((dest 16) | (srca 8) | srcb);
+ tcg_gen_st_i32(t, cpu_env, offsetof(CPUTLGState, excparam));
+ tcg_temp_free_i32(t);
+ gen_exception(dc, excp);
+#else
+ gen_exception(dc, TILEGX_EXCP_OPCODE_UNIMPLEMENTED);
+#endif
+}
Originally, I used set_exception(), not gen_exception().
This is broken. While it does work well enough for Hello World, implementing
a non-trap instruction with an exception is extremely dicey for TileGX. The
issue is that TileGX bundles operate atomically, with no RAW issues between
the instructions of the bundle.
Consider a bundle like
{ add r0, r0, r1 ; exch r2, r0, r3 }
In Chen's implementation, the writeback to r0 would occur before the
exception, and so the exch would happen to the wrong address. In my
implementation here, the exception would occur before the writeback, and so
the result of the add would be discarded.
We use tmp regs for buffering the r0.
- calculate x1 pipe, and save result to r0 tmp reg.
Oh, typo, calculate x0 pipe, and save result to r0 tmp reg.
- exch the original r0 and r3 to r2 tmp reg.
- set exception flag (which will cause exception, later).
- save the result tmp regs to r0 or r2.
- gen exception.
While retaining the current start_exclusive scheme, it would appear that we
need to store more data here -- to wit, the contents of the registers not
their numbers -- and delay the exception until after writeback.
Even better, of course, would be to not exit the TB at all, and use host
atomic instructions... I suppose that multi-threading patch set is still in
limbo?
I guess, we need not.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions
On 8/25/15 22:28, Richard Henderson wrote:
On 08/25/2015 06:12 AM, Chen Gang wrote:
Consider a bundle like
{ add r0, r0, r1 ; exch r2, r0, r3 }
In Chen's implementation, the writeback to r0 would occur before the
exception, and so the exch would happen to the wrong address. In my
implementation here, the exception would occur before the writeback, and
so the result of the add would be discarded.
We use tmp regs for buffering the r0.
- calculate x1 pipe, and save result to r0 tmp reg.
Oh, typo, calculate x0 pipe, and save result to r0 tmp reg.
- exch the original r0 and r3 to r2 tmp reg.
- set exception flag (which will cause exception, later).
- save the result tmp regs to r0 or r2.
- gen exception.
Exactly. Now re-read what I wrote and see if you can spot the problem with
this.
OK, thanks. In my memory, originally, we discussed about related things,
you provided several good ideas (temp regs, and gen exceptions ...).
Based on them, I implemented it in this way, hope it is correct.
At present, for gcc testsuite, I met several (10+) pending issues, which
need to be fixed, next. So I guess, there must be still any issues which
we did not find in the current whole tilegx code.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions
On 8/25/15 00:17, Richard Henderson wrote: I've flushed out the v13 I posted last Thursday to handle all the instructions required to execute Hello World. In the process I found a number of bugs and design flaws in v13, and reshaped the translation a bit to better handle insns with no register outputs. OK, thank you for your work (originally, I really did not kown that it would generate so many patches -- almost 3 times that I supposed). Please review. After this, I would hope that Chen Gang will follow up to implement the rest of the instructions that he has identified running the gcc testsuite, and then start in on the floating point. OK, thanks, I shall continue based on it, after it is integrated into qemu master (after Reviewed-by another members). During the next 2-4 days I shall try to fix one gcc bugzilla issue, then turn back to qemu, hope I can succeed. (during these passed days, I sent 3 paches to kernel, and 2 of them are applied, one is waiting review). Thanks. r~ Chen Gang (9): linux-user: tilegx: Firstly add architecture related features linux-user: Support tilegx architecture in linux-user linux-user: Conditionalize syscalls which are not defined in tilegx target-tilegx: Add opcode basic implementation from Tilera Corporation target-tilegx: Modify opcode_tilegx.h to fit QEMU usage target-tilegx: Add special register information from Tilera Corporation target-tilegx: Add cpu basic features for linux-user target-tilegx: Add several helpers for instructions translation target-tilegx: Add TILE-Gx building files Richard Henderson (24): target-tilegx: Modify _SPECIAL_ opcodes target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1 target-tilegx: Framework for decoding bundles target-tilegx: Generate SEGV properly target-tilegx: Handle simple logical operations target-tilegx: Handle arithmetic instructions target-tilegx: Handle most bit manipulation instructions target-tilegx: Handle basic load and store instructions target-tilegx: Handle post-increment load and store instructions target-tilegx: Handle unconditional jump instructions target-tilegx: Handle conditional branch instructions target-tilegx: Handle comparison instructions target-tilegx: Implement system and memory management instructions target-tilegx: Handle bitfield instructions target-tilegx: Handle shift instructions target-tilegx: Handle conditional move instructions target-tilegx: Handle scalar multiply instructions target-tilegx: Handle mask instructions target-tilegx: Handle v1cmpeq, v1cmpne target-tilegx: Handle mtspr, mfspr target-tilegx: Handle atomic instructions target-tilegx: Handle v4int_l/h target-tilegx: Handle v1shli, v1shrui target-tilegx: Handle v1shl, v1shru, v1shrs configure | 2 + default-configs/tilegx-linux-user.mak | 1 + include/elf.h | 2 + linux-user/elfload.c | 23 + linux-user/main.c | 298 + linux-user/syscall.c | 50 +- linux-user/syscall_defs.h | 14 +- linux-user/tilegx/syscall.h | 40 + linux-user/tilegx/syscall_nr.h | 324 + linux-user/tilegx/target_cpu.h | 35 + linux-user/tilegx/target_signal.h | 28 + linux-user/tilegx/target_structs.h | 46 + linux-user/tilegx/termbits.h | 274 + target-tilegx/Makefile.objs | 1 + target-tilegx/cpu.c | 173 +++ target-tilegx/cpu.h | 177 +++ target-tilegx/helper.c | 93 ++ target-tilegx/helper.h | 10 + target-tilegx/opcode_tilegx.h | 1406 ++ target-tilegx/simd_helper.c | 63 + target-tilegx/spr_def_64.h | 216 target-tilegx/translate.c | 2135 + 22 files changed, 5405 insertions(+), 6 deletions(-) create mode 100644 default-configs/tilegx-linux-user.mak create mode 100644 linux-user/tilegx/syscall.h create mode 100644 linux-user/tilegx/syscall_nr.h create mode 100644 linux-user/tilegx/target_cpu.h create mode 100644 linux-user/tilegx/target_signal.h create mode 100644 linux-user/tilegx/target_structs.h create mode 100644 linux-user/tilegx/termbits.h create mode 100644 target-tilegx/Makefile.objs create mode 100644 target-tilegx/cpu.c create mode 100644 target-tilegx/cpu.h create mode 100644 target-tilegx/helper.c create mode 100644 target-tilegx/helper.h create mode 100644 target-tilegx/opcode_tilegx.h create mode 100644 target-tilegx/simd_helper.c create mode 100644 target-tilegx/spr_def_64.h create mode 100644 target-tilegx/translate.c -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
[Qemu-devel] [PATCH 01/16 v1] linux-user: tilegx: Firstly add architecture related features
They are based on Linux kernel tilegx architecture for 64 bit binary,
and also based on tilegx ABI reference document, and also reference from
other targets implementations.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
linux-user/tilegx/syscall.h| 40 +
linux-user/tilegx/syscall_nr.h | 324 +
linux-user/tilegx/target_cpu.h | 35
linux-user/tilegx/target_signal.h | 28
linux-user/tilegx/target_structs.h | 46 ++
linux-user/tilegx/termbits.h | 274 +++
6 files changed, 747 insertions(+)
create mode 100644 linux-user/tilegx/syscall.h
create mode 100644 linux-user/tilegx/syscall_nr.h
create mode 100644 linux-user/tilegx/target_cpu.h
create mode 100644 linux-user/tilegx/target_signal.h
create mode 100644 linux-user/tilegx/target_structs.h
create mode 100644 linux-user/tilegx/termbits.h
diff --git a/linux-user/tilegx/syscall.h b/linux-user/tilegx/syscall.h
new file mode 100644
index 000..653ece1
--- /dev/null
+++ b/linux-user/tilegx/syscall.h
@@ -0,0 +1,40 @@
+#ifndef TILEGX_SYSCALLS_H
+#define TILEGX_SYSCALLS_H
+
+#define UNAME_MACHINE tilegx
+#define UNAME_MINIMUM_RELEASE 3.19
+
+#define MMAP_SHIFT TARGET_PAGE_BITS
+
+#define TILEGX_IS_ERRNO(ret) \
+ ((ret) 0xf000ULL) /* errno is 0 -- 4096 */
+
+typedef uint64_t tilegx_reg_t;
+
+struct target_pt_regs {
+
+union {
+/* Saved main processor registers; 56..63 are special. */
+tilegx_reg_t regs[56];
+struct {
+tilegx_reg_t __regs[53];
+tilegx_reg_t tp;/* aliases regs[TREG_TP] */
+tilegx_reg_t sp;/* aliases regs[TREG_SP] */
+tilegx_reg_t lr;/* aliases regs[TREG_LR] */
+};
+};
+
+/* Saved special registers. */
+tilegx_reg_t pc;/* stored in EX_CONTEXT_K_0 */
+tilegx_reg_t ex1; /* stored in EX_CONTEXT_K_1 (PL and ICS bit) */
+tilegx_reg_t faultnum; /* fault number (INT_SWINT_1 for syscall) */
+tilegx_reg_t orig_r0; /* r0 at syscall entry, else zero */
+tilegx_reg_t flags; /* flags (see below) */
+tilegx_reg_t cmpexch; /* value of CMPEXCH_VALUE SPR at interrupt */
+tilegx_reg_t pad[2];
+};
+
+#define TARGET_MLOCKALL_MCL_CURRENT 1
+#define TARGET_MLOCKALL_MCL_FUTURE 2
+
+#endif
diff --git a/linux-user/tilegx/syscall_nr.h b/linux-user/tilegx/syscall_nr.h
new file mode 100644
index 000..1dca348
--- /dev/null
+++ b/linux-user/tilegx/syscall_nr.h
@@ -0,0 +1,324 @@
+#ifndef TILEGX_SYSCALL_NR
+#define TILEGX_SYSCALL_NR
+
+/*
+ * Copy from linux kernel asm-generic/unistd.h, which tilegx uses.
+ */
+#define TARGET_NR_io_setup 0
+#define TARGET_NR_io_destroy1
+#define TARGET_NR_io_submit 2
+#define TARGET_NR_io_cancel 3
+#define TARGET_NR_io_getevents 4
+#define TARGET_NR_setxattr 5
+#define TARGET_NR_lsetxattr 6
+#define TARGET_NR_fsetxattr 7
+#define TARGET_NR_getxattr 8
+#define TARGET_NR_lgetxattr 9
+#define TARGET_NR_fgetxattr 10
+#define TARGET_NR_listxattr 11
+#define TARGET_NR_llistxattr12
+#define TARGET_NR_flistxattr13
+#define TARGET_NR_removexattr 14
+#define TARGET_NR_lremovexattr 15
+#define TARGET_NR_fremovexattr 16
+#define TARGET_NR_getcwd17
+#define TARGET_NR_lookup_dcookie18
+#define TARGET_NR_eventfd2 19
+#define TARGET_NR_epoll_create1 20
+#define TARGET_NR_epoll_ctl 21
+#define TARGET_NR_epoll_pwait 22
+#define TARGET_NR_dup 23
+#define TARGET_NR_dup3 24
+#define TARGET_NR_fcntl 25
+#define TARGET_NR_inotify_init1 26
+#define TARGET_NR_inotify_add_watch 27
+#define TARGET_NR_inotify_rm_watch 28
+#define TARGET_NR_ioctl 29
+#define TARGET_NR_ioprio_set30
+#define TARGET_NR_ioprio_get31
+#define TARGET_NR_flock 32
+#define TARGET_NR_mknodat 33
+#define TARGET_NR_mkdirat 34
+#define TARGET_NR_unlinkat 35
+#define TARGET_NR_symlinkat 36
+#define TARGET_NR_linkat37
+#define TARGET_NR_renameat 38
+#define TARGET_NR_umount2 39
+#define TARGET_NR_mount 40
+#define TARGET_NR_pivot_root41
+#define TARGET_NR_nfsservctl42
[Qemu-devel] [PATCH 06/16 v1] target-tilegx: Add special register information from Tilera Corporation
The related copy is from Linux kernel arch/tile/include/uapi/arch/ spr_def_64.h. Signed-off-by: Chen Gang gang.chen.5...@gmail.com Reviewed-by: Peter Maydell peter.mayd...@linaro.org --- target-tilegx/spr_def_64.h | 216 + 1 file changed, 216 insertions(+) create mode 100644 target-tilegx/spr_def_64.h diff --git a/target-tilegx/spr_def_64.h b/target-tilegx/spr_def_64.h new file mode 100644 index 000..67a6c17 --- /dev/null +++ b/target-tilegx/spr_def_64.h @@ -0,0 +1,216 @@ +/* + * Copyright 2011 Tilera Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or + * NON INFRINGEMENT. See the GNU General Public License for + * more details. + */ + +#ifndef __DOXYGEN__ + +#ifndef __ARCH_SPR_DEF_64_H__ +#define __ARCH_SPR_DEF_64_H__ + +#define SPR_AUX_PERF_COUNT_0 0x2105 +#define SPR_AUX_PERF_COUNT_1 0x2106 +#define SPR_AUX_PERF_COUNT_CTL 0x2107 +#define SPR_AUX_PERF_COUNT_STS 0x2108 +#define SPR_CMPEXCH_VALUE 0x2780 +#define SPR_CYCLE 0x2781 +#define SPR_DONE 0x2705 +#define SPR_DSTREAM_PF 0x2706 +#define SPR_EVENT_BEGIN 0x2782 +#define SPR_EVENT_END 0x2783 +#define SPR_EX_CONTEXT_0_0 0x2580 +#define SPR_EX_CONTEXT_0_1 0x2581 +#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0 +#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3 +#define SPR_EX_CONTEXT_0_1__PL_MASK 0x3 +#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2 +#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1 +#define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4 +#define SPR_EX_CONTEXT_1_0 0x2480 +#define SPR_EX_CONTEXT_1_1 0x2481 +#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0 +#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3 +#define SPR_EX_CONTEXT_1_1__PL_MASK 0x3 +#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2 +#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1 +#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4 +#define SPR_EX_CONTEXT_2_0 0x2380 +#define SPR_EX_CONTEXT_2_1 0x2381 +#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0 +#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3 +#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3 +#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2 +#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1 +#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4 +#define SPR_FAIL 0x2707 +#define SPR_IDN_AVAIL_EN 0x1a05 +#define SPR_IDN_DATA_AVAIL 0x0a80 +#define SPR_IDN_DEADLOCK_TIMEOUT 0x1806 +#define SPR_IDN_DEMUX_COUNT_0 0x0a05 +#define SPR_IDN_DEMUX_COUNT_1 0x0a06 +#define SPR_IDN_DIRECTION_PROTECT 0x1405 +#define SPR_IDN_PENDING 0x0a08 +#define SPR_ILL_TRANS_REASON__I_STREAM_VA_RMASK 0x1 +#define SPR_INTCTRL_0_STATUS 0x2505 +#define SPR_INTCTRL_1_STATUS 0x2405 +#define SPR_INTCTRL_2_STATUS 0x2305 +#define SPR_INTERRUPT_CRITICAL_SECTION 0x2708 +#define SPR_INTERRUPT_MASK_0 0x2506 +#define SPR_INTERRUPT_MASK_1 0x2406 +#define SPR_INTERRUPT_MASK_2 0x2306 +#define SPR_INTERRUPT_MASK_RESET_0 0x2507 +#define SPR_INTERRUPT_MASK_RESET_1 0x2407 +#define SPR_INTERRUPT_MASK_RESET_2 0x2307 +#define SPR_INTERRUPT_MASK_SET_0 0x2508 +#define SPR_INTERRUPT_MASK_SET_1 0x2408 +#define SPR_INTERRUPT_MASK_SET_2 0x2308 +#define SPR_INTERRUPT_VECTOR_BASE_0 0x2509 +#define SPR_INTERRUPT_VECTOR_BASE_1 0x2409 +#define SPR_INTERRUPT_VECTOR_BASE_2 0x2309 +#define SPR_INTERRUPT_VECTOR_BASE_3 0x2209 +#define SPR_IPI_EVENT_0 0x1f05 +#define SPR_IPI_EVENT_1 0x1e05 +#define SPR_IPI_EVENT_2 0x1d05 +#define SPR_IPI_EVENT_RESET_0 0x1f06 +#define SPR_IPI_EVENT_RESET_1 0x1e06 +#define SPR_IPI_EVENT_RESET_2 0x1d06 +#define SPR_IPI_EVENT_SET_0 0x1f07 +#define SPR_IPI_EVENT_SET_1 0x1e07 +#define SPR_IPI_EVENT_SET_2 0x1d07 +#define SPR_IPI_MASK_0 0x1f08 +#define SPR_IPI_MASK_1 0x1e08 +#define SPR_IPI_MASK_2 0x1d08 +#define SPR_IPI_MASK_RESET_0 0x1f09 +#define SPR_IPI_MASK_RESET_1 0x1e09 +#define SPR_IPI_MASK_RESET_2 0x1d09 +#define SPR_IPI_MASK_SET_0 0x1f0a +#define SPR_IPI_MASK_SET_1 0x1e0a +#define SPR_IPI_MASK_SET_2 0x1d0a +#define SPR_MPL_AUX_PERF_COUNT_SET_0 0x2100 +#define SPR_MPL_AUX_PERF_COUNT_SET_1 0x2101 +#define SPR_MPL_AUX_PERF_COUNT_SET_2 0x2102 +#define SPR_MPL_AUX_TILE_TIMER_SET_0 0x1700 +#define SPR_MPL_AUX_TILE_TIMER_SET_1 0x1701 +#define SPR_MPL_AUX_TILE_TIMER_SET_2 0x1702 +#define SPR_MPL_IDN_ACCESS_SET_0 0x0a00 +#define SPR_MPL_IDN_ACCESS_SET_1 0x0a01 +#define SPR_MPL_IDN_ACCESS_SET_2 0x0a02 +#define SPR_MPL_IDN_AVAIL_SET_0 0x1a00 +#define SPR_MPL_IDN_AVAIL_SET_1 0x1a01 +#define SPR_MPL_IDN_AVAIL_SET_2 0x1a02 +#define SPR_MPL_IDN_COMPLETE_SET_0 0x0500 +#define SPR_MPL_IDN_COMPLETE_SET_1 0x0501 +#define SPR_MPL_IDN_COMPLETE_SET_2 0x0502 +#define SPR_MPL_IDN_FIREWALL_SET_0 0x1400 +#define SPR_MPL_IDN_FIREWALL_SET_1 0x1401 +#define SPR_MPL_IDN_FIREWALL_SET_2 0x1402 +#define SPR_MPL_IDN_TIMER_SET_0 0x1800 +#define SPR_MPL_IDN_TIMER_SET_1 0x1801
[Qemu-devel] [PATCH 16/16 v1] target-tilegx: Implement additional instructions in normal working flow
They are vectors, pcnt, revbytes, icoh, and drain.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/helper.c| 12 +-
target-tilegx/helper.h| 4 +-
target-tilegx/translate.c | 431 ++
3 files changed, 331 insertions(+), 116 deletions(-)
diff --git a/target-tilegx/helper.c b/target-tilegx/helper.c
index 5ab41cd..98dd805 100644
--- a/target-tilegx/helper.c
+++ b/target-tilegx/helper.c
@@ -24,7 +24,7 @@
#define SIGNBIT32 0x8000
-int64_t helper_add_saturate(CPUTLGState *env, uint64_t rsrc, uint64_t rsrcb)
+int64_t helper_add_saturate(uint64_t rsrc, uint64_t rsrcb)
{
uint32_t rdst = rsrc + rsrcb;
@@ -53,6 +53,16 @@ uint64_t helper_cnttz(uint64_t arg)
return ctz64(arg);
}
+uint64_t helper_pcnt(uint64_t arg)
+{
+return ctpop64(arg);
+}
+
+uint64_t helper_revbytes(uint64_t arg)
+{
+return bswap64(arg);
+}
+
/*
* Functional Description
* uint64_t a = rf[SrcA];
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
index 1411c19..fbd995a 100644
--- a/target-tilegx/helper.h
+++ b/target-tilegx/helper.h
@@ -1,5 +1,7 @@
DEF_HELPER_2(exception, noreturn, env, i32)
DEF_HELPER_FLAGS_1(cntlz, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(cnttz, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_FLAGS_1(pcnt, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_FLAGS_1(revbytes, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
-DEF_HELPER_3(add_saturate, s64, env, i64, i64)
+DEF_HELPER_FLAGS_2(add_saturate, TCG_CALL_NO_RWG_SE, s64, i64, i64)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 9ae1c6d..6d993b4 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -302,20 +302,104 @@ static void gen_mtspr(struct DisasContext *dc, uint8_t
rsrc, uint16_t imm14)
set_exception(dc, TILEGX_EXCP_OPCODE_UNIMPLEMENTED);
}
-static void extract_v1(TCGv out, TCGv in, unsigned byte)
+static void extract_v(TCGv out, TCGv in, int count, int v)
{
-tcg_gen_shri_i64(out, in, byte * 8);
-tcg_gen_ext8u_i64(out, out);
+tcg_gen_shri_i64(out, in, count * v * 8);
+switch (v) {
+case 1:
+tcg_gen_ext8u_i64(out, out);
+break;
+case 2:
+tcg_gen_ext16u_i64(out, out);
+break;
+case 4:
+tcg_gen_ext32u_i64(out, out);
+break;
+default:
+g_assert_not_reached();
+}
}
-static void insert_v1(TCGv out, TCGv in, unsigned byte)
+static void insert_v(TCGv out, TCGv in, int count, int v)
{
-tcg_gen_deposit_i64(out, out, in, byte * 8, 8);
+tcg_gen_deposit_i64(out, out, in, count * v * 8, v * 8);
}
-static void gen_v1cmpi(struct DisasContext *dc,
- uint8_t rdst, uint8_t rsrc, int8_t imm8,
- TCGCond cond, const char *code)
+static void gen_vadd(struct DisasContext *dc,
+ uint8_t rdst, uint8_t rsrc, uint8_t rsrcb, int v)
+{
+int count;
+TCGv vdst = dest_gr(dc, rdst);
+TCGv vsrc = load_gr(dc, rsrc);
+TCGv vsrcb = load_gr(dc, rsrcb);
+TCGv tmp = tcg_temp_new_i64();
+TCGv tmpb = tcg_temp_new_i64();
+
+qemu_log_mask(CPU_LOG_TB_IN_ASM, v%dadd r%d, r%d, r%d\n,
+ v, rdst, rsrc, rsrcb);
+
+tcg_gen_movi_i64(vdst, 0);
+
+for (count = 0; count sizeof(uint64_t) / v; count++) {
+extract_v(tmp, vsrc, count, v);
+extract_v(tmpb, vsrcb, count, v);
+tcg_gen_add_i64(tmp, tmp, tmpb);
+insert_v(vdst, tmp, count, v);
+}
+
+tcg_temp_free_i64(tmpb);
+tcg_temp_free_i64(tmp);
+}
+
+static void gen_vsub(struct DisasContext *dc,
+ uint8_t rdst, uint8_t rsrc, uint8_t rsrcb, int v)
+{
+int count;
+TCGv vdst = dest_gr(dc, rdst);
+TCGv vsrc = load_gr(dc, rsrc);
+TCGv vsrcb = load_gr(dc, rsrcb);
+TCGv tmp = tcg_temp_new_i64();
+TCGv tmpb = tcg_temp_new_i64();
+
+qemu_log_mask(CPU_LOG_TB_IN_ASM, v%dsub r%d, r%d, r%d\n,
+ v, rdst, rsrc, rsrcb);
+
+tcg_gen_movi_i64(vdst, 0);
+
+for (count = 0; count sizeof(uint64_t) / v; count++) {
+extract_v(tmp, vsrc, count, v);
+extract_v(tmpb, vsrcb, count, v);
+tcg_gen_sub_i64(tmp, tmp, tmpb);
+insert_v(vdst, tmp, count, v);
+}
+
+tcg_temp_free_i64(tmpb);
+tcg_temp_free_i64(tmp);
+}
+
+static void gen_vaddi(struct DisasContext *dc,
+ uint8_t rdst, uint8_t rsrc, int8_t imm8, int v)
+{
+int count;
+TCGv vdst = dest_gr(dc, rdst);
+TCGv vsrc = load_gr(dc, rsrc);
+TCGv tmp = tcg_temp_new_i64();
+
+qemu_log_mask(CPU_LOG_TB_IN_ASM, v%daddi r%d, r%d, %d\n,
+ v, rdst, rsrc, imm8);
+
+tcg_gen_movi_i64(vdst, 0);
+for (count = 0; count sizeof(uint64_t) / v; count++) {
+extract_v(tmp, vsrc, count, v);
+tcg_gen_addi_i64(tmp, tmp, imm8);
+insert_v(vdst, tmp, count, v);
+}
+tcg_temp_free_i64
[Qemu-devel] [PATCH 08/16 v1] target-tilegx: Add several helpers for instructions translation
The related instructions are exception, cntlz, cnttz, shufflebytes, and
add_saturate.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/helper.c | 83 ++
target-tilegx/helper.h | 5 +++
2 files changed, 88 insertions(+)
create mode 100644 target-tilegx/helper.c
create mode 100644 target-tilegx/helper.h
diff --git a/target-tilegx/helper.c b/target-tilegx/helper.c
new file mode 100644
index 000..5ab41cd
--- /dev/null
+++ b/target-tilegx/helper.c
@@ -0,0 +1,83 @@
+/*
+ * QEMU TILE-Gx helpers
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * http://www.gnu.org/licenses/lgpl-2.1.html
+ */
+
+#include cpu.h
+#include qemu-common.h
+#include exec/helper-proto.h
+
+#define SIGNBIT32 0x8000
+
+int64_t helper_add_saturate(CPUTLGState *env, uint64_t rsrc, uint64_t rsrcb)
+{
+uint32_t rdst = rsrc + rsrcb;
+
+if (((rdst ^ rsrc) SIGNBIT32) !((rsrc ^ rsrcb) SIGNBIT32)) {
+rdst = ~(((int32_t)rsrc 31) ^ SIGNBIT32);
+}
+
+return (int64_t)rdst;
+}
+
+void helper_exception(CPUTLGState *env, uint32_t excp)
+{
+CPUState *cs = CPU(tilegx_env_get_cpu(env));
+
+cs-exception_index = excp;
+cpu_loop_exit(cs);
+}
+
+uint64_t helper_cntlz(uint64_t arg)
+{
+return clz64(arg);
+}
+
+uint64_t helper_cnttz(uint64_t arg)
+{
+return ctz64(arg);
+}
+
+/*
+ * Functional Description
+ * uint64_t a = rf[SrcA];
+ * uint64_t b = rf[SrcB];
+ * uint64_t d = rf[Dest];
+ * uint64_t output = 0;
+ * unsigned int counter;
+ * for (counter = 0; counter (WORD_SIZE / BYTE_SIZE); counter++)
+ * {
+ * int sel = getByte (b, counter) 0xf;
+ * uint8_t byte = (sel 8) ? getByte (d, sel) : getByte (a, (sel -
8));
+ * output = setByte (output, counter, byte);
+ * }
+ * rf[Dest] = output;
+ */
+uint64_t helper_shufflebytes(uint64_t rdst, uint64_t rsrc, uint64_t rsrcb)
+{
+uint64_t vdst = 0;
+int count;
+
+for (count = 0; count 64; count += 8) {
+uint64_t sel = rsrcb count;
+uint64_t src = (sel 8) ? rsrc : rdst;
+vdst |= ((src ((sel 7) * 8)) 0xff) count;
+}
+
+return vdst;
+}
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
new file mode 100644
index 000..1411c19
--- /dev/null
+++ b/target-tilegx/helper.h
@@ -0,0 +1,5 @@
+DEF_HELPER_2(exception, noreturn, env, i32)
+DEF_HELPER_FLAGS_1(cntlz, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_FLAGS_1(cnttz, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
+DEF_HELPER_3(add_saturate, s64, env, i64, i64)
--
1.9.3
[Qemu-devel] [PATCH 02/16 v1] linux-user: Support tilegx architecture in linux-user
Add main working flow feature, system call processing feature, and elf64
tilegx binary loading feature, based on Linux kernel tilegx 64-bit
implementation.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
include/elf.h | 2 +
linux-user/elfload.c | 23
linux-user/main.c | 295 ++
linux-user/syscall_defs.h | 14 ++-
4 files changed, 329 insertions(+), 5 deletions(-)
diff --git a/include/elf.h b/include/elf.h
index 4afd474..79859f0 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -133,6 +133,8 @@ typedef int64_t Elf64_Sxword;
#define EM_AARCH64 183
+#define EM_TILEGX 191 /* TILE-Gx */
+
/* This is the info that is needed to parse the dynamic section of the file */
#define DT_NULL0
#define DT_NEEDED 1
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 1788368..bfb8d1f 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1218,6 +1218,29 @@ static inline void init_thread(struct target_pt_regs
*regs, struct image_info *i
#endif /* TARGET_S390X */
+#ifdef TARGET_TILEGX
+
+/* 42 bits real used address, a half for user mode */
+#define ELF_START_MMAP (0x00200ULL)
+
+#define elf_check_arch(x) ((x) == EM_TILEGX)
+
+#define ELF_CLASS ELFCLASS64
+#define ELF_DATAELFDATA2LSB
+#define ELF_ARCHEM_TILEGX
+
+static inline void init_thread(struct target_pt_regs *regs,
+ struct image_info *infop)
+{
+regs-pc = infop-entry;
+regs-sp = infop-start_stack;
+
+}
+
+#define ELF_EXEC_PAGESIZE65536 /* TILE-Gx page size is 64KB */
+
+#endif /* TARGET_TILEGX */
+
#ifndef ELF_PLATFORM
#define ELF_PLATFORM (NULL)
#endif
diff --git a/linux-user/main.c b/linux-user/main.c
index fdee981..253aade 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3411,6 +3411,290 @@ void cpu_loop(CPUS390XState *env)
#endif /* TARGET_S390X */
+#ifdef TARGET_TILEGX
+
+static void gen_sigsegv_mapper(CPUTLGState *env, target_ulong addr)
+{
+target_siginfo_t info;
+
+info.si_signo = TARGET_SIGSEGV;
+info.si_errno = 0;
+info.si_code = TARGET_SEGV_MAPERR;
+info._sifields._sigfault._addr = addr;
+queue_signal(env, info.si_signo, info);
+}
+
+static void gen_sigill_reg(CPUTLGState *env)
+{
+target_siginfo_t info;
+
+info.si_signo = TARGET_SIGILL;
+info.si_errno = 0;
+info.si_code = TARGET_ILL_PRVREG;
+info._sifields._sigfault._addr = env-pc;
+queue_signal(env, info.si_signo, info);
+}
+
+static int get_regval(CPUTLGState *env, uint8_t reg, target_ulong *val)
+{
+if (likely(reg TILEGX_R_COUNT)) {
+*val = env-regs[reg];
+return 0;
+}
+
+switch (reg) {
+case TILEGX_R_SN:
+case TILEGX_R_ZERO:
+*val = 0;
+return 0;
+case TILEGX_R_IDN0:
+case TILEGX_R_IDN1:
+case TILEGX_R_UDN0:
+case TILEGX_R_UDN1:
+case TILEGX_R_UDN2:
+case TILEGX_R_UDN3:
+return -1;
+default:
+g_assert_not_reached();
+}
+}
+
+static int set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
+{
+if (unlikely(reg = TILEGX_R_COUNT)) {
+switch (reg) {
+case TILEGX_R_SN:
+case TILEGX_R_ZERO:
+return 0;
+case TILEGX_R_IDN0:
+case TILEGX_R_IDN1:
+case TILEGX_R_UDN0:
+case TILEGX_R_UDN1:
+case TILEGX_R_UDN2:
+case TILEGX_R_UDN3:
+return -1;
+default:
+g_assert_not_reached();
+}
+}
+
+env-regs[reg] = val;
+return 0;
+}
+
+/*
+ * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
+ * memory at the address held in the first source register. If the values are
+ * not equal, then no memory operation is performed. If the values are equal,
+ * the 8-byte quantity from the second source register is written into memory
+ * at the address held in the first source register. In either case, the result
+ * of the instruction is the value read from memory. The compare and write to
+ * memory are atomic and thus can be used for synchronization purposes. This
+ * instruction only operates for addresses aligned to a 8-byte boundary.
+ * Unaligned memory access causes an Unaligned Data Reference interrupt.
+ *
+ * Functional Description (64-bit)
+ * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
+ * rf[Dest] = memVal;
+ * if (memVal == SPR[CmpValueSPR])
+ * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
+ *
+ * Functional Description (32-bit)
+ * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
+ * rf[Dest] = memVal;
+ * if (memVal == signExtend32 (SPR[CmpValueSPR]))
+ * memoryWriteWord (rf[SrcA], rf[SrcB]);
+ *
+ *
+ * This function also processes exch and exch4 which need not process SPR.
+ */
+static void do_exch(CPUTLGState *env, bool quad, bool cmp)
+{
+uint8_t rdst
[Qemu-devel] [PATCH 07/16 v1] target-tilegx: Add cpu basic features for linux-user
It implements minimized cpu features for linux-user.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
target-tilegx/cpu.c | 143 ++
target-tilegx/cpu.h | 175
2 files changed, 318 insertions(+)
create mode 100644 target-tilegx/cpu.c
create mode 100644 target-tilegx/cpu.h
diff --git a/target-tilegx/cpu.c b/target-tilegx/cpu.c
new file mode 100644
index 000..663fcb6
--- /dev/null
+++ b/target-tilegx/cpu.c
@@ -0,0 +1,143 @@
+/*
+ * QEMU TILE-Gx CPU
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * http://www.gnu.org/licenses/lgpl-2.1.html
+ */
+
+#include cpu.h
+#include qemu-common.h
+#include hw/qdev-properties.h
+#include migration/vmstate.h
+
+TileGXCPU *cpu_tilegx_init(const char *cpu_model)
+{
+TileGXCPU *cpu;
+
+cpu = TILEGX_CPU(object_new(TYPE_TILEGX_CPU));
+
+object_property_set_bool(OBJECT(cpu), true, realized, NULL);
+
+return cpu;
+}
+
+static void tilegx_cpu_set_pc(CPUState *cs, vaddr value)
+{
+TileGXCPU *cpu = TILEGX_CPU(cs);
+
+cpu-env.pc = value;
+}
+
+static bool tilegx_cpu_has_work(CPUState *cs)
+{
+return true;
+}
+
+static void tilegx_cpu_reset(CPUState *s)
+{
+TileGXCPU *cpu = TILEGX_CPU(s);
+TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu);
+CPUTLGState *env = cpu-env;
+
+tcc-parent_reset(s);
+
+memset(env, 0, sizeof(CPUTLGState));
+tlb_flush(s, 1);
+}
+
+static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+CPUState *cs = CPU(dev);
+TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev);
+
+cpu_reset(cs);
+qemu_init_vcpu(cs);
+
+tcc-parent_realize(dev, errp);
+}
+
+static void tilegx_cpu_initfn(Object *obj)
+{
+CPUState *cs = CPU(obj);
+TileGXCPU *cpu = TILEGX_CPU(obj);
+CPUTLGState *env = cpu-env;
+static bool tcg_initialized;
+
+cs-env_ptr = env;
+cpu_exec_init(env);
+
+if (tcg_enabled() !tcg_initialized) {
+tcg_initialized = true;
+tilegx_tcg_init();
+}
+}
+
+static void tilegx_cpu_do_interrupt(CPUState *cs)
+{
+cs-exception_index = -1;
+}
+
+static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
+ int mmu_idx)
+{
+cpu_dump_state(cs, stderr, fprintf, 0);
+return 1;
+}
+
+static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+if (interrupt_request CPU_INTERRUPT_HARD) {
+tilegx_cpu_do_interrupt(cs);
+return true;
+}
+return false;
+}
+
+static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(oc);
+CPUClass *cc = CPU_CLASS(oc);
+TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc);
+
+tcc-parent_realize = dc-realize;
+dc-realize = tilegx_cpu_realizefn;
+
+tcc-parent_reset = cc-reset;
+cc-reset = tilegx_cpu_reset;
+
+cc-has_work = tilegx_cpu_has_work;
+cc-do_interrupt = tilegx_cpu_do_interrupt;
+cc-cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
+cc-set_pc = tilegx_cpu_set_pc;
+cc-handle_mmu_fault = tilegx_cpu_handle_mmu_fault;
+cc-gdb_num_core_regs = 0;
+}
+
+static const TypeInfo tilegx_cpu_type_info = {
+.name = TYPE_TILEGX_CPU,
+.parent = TYPE_CPU,
+.instance_size = sizeof(TileGXCPU),
+.instance_init = tilegx_cpu_initfn,
+.class_size = sizeof(TileGXCPUClass),
+.class_init = tilegx_cpu_class_init,
+};
+
+static void tilegx_cpu_register_types(void)
+{
+type_register_static(tilegx_cpu_type_info);
+}
+
+type_init(tilegx_cpu_register_types)
diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
new file mode 100644
index 000..e404025
--- /dev/null
+++ b/target-tilegx/cpu.h
@@ -0,0 +1,175 @@
+/*
+ * TILE-Gx virtual CPU header
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
[Qemu-devel] [PATCH 05/16 v1] target-tilegx/opcode_tilegx.h: Modify it to fit QEMU usage
Use 'inline' instead of '__inline', and also use 'uint64_t' instead of
unsigned long long
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
target-tilegx/opcode_tilegx.h | 220 +-
1 file changed, 110 insertions(+), 110 deletions(-)
diff --git a/target-tilegx/opcode_tilegx.h b/target-tilegx/opcode_tilegx.h
index d76ff2d..33b71a9 100644
--- a/target-tilegx/opcode_tilegx.h
+++ b/target-tilegx/opcode_tilegx.h
@@ -23,7 +23,7 @@
#ifndef __ASSEMBLER__
-typedef unsigned long long tilegx_bundle_bits;
+typedef uint64_t tilegx_bundle_bits;
/* These are the bits that determine if a bundle is in the X encoding. */
#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 62)
@@ -66,360 +66,360 @@ typedef tilegx_bundle_bits tile_bundle_bits;
/* 64-bit pattern for a { bpt ; nop } bundle. */
#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
-static __inline unsigned int
+static inline unsigned int
get_BFEnd_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 12)) 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 24)) 0xf);
}
-static __inline unsigned int
+static inline unsigned int
get_BFStart_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 18)) 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_BrOff_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 31)) 0x003f) |
(((unsigned int)(n 37)) 0x0001ffc0);
}
-static __inline unsigned int
+static inline unsigned int
get_BrType_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 54)) 0x1f);
}
-static __inline unsigned int
+static inline unsigned int
get_Dest_Imm8_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 31)) 0x003f) |
(((unsigned int)(n 43)) 0x00c0);
}
-static __inline unsigned int
+static inline unsigned int
get_Dest_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 0)) 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_Dest_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 31)) 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_Dest_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 0)) 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_Dest_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 31)) 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm16_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 12)) 0x);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm16_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 43)) 0x);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 20)) 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 51)) 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 12)) 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 43)) 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 12)) 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 43)) 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_JumpOff_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 31)) 0x7ff);
}
-static __inline unsigned int
+static inline unsigned int
get_JumpOpcodeExtension_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 58)) 0x1);
}
-static __inline unsigned int
+static inline unsigned int
get_MF_Imm14_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 37)) 0x3fff);
}
-static __inline unsigned int
+static inline unsigned int
get_MT_Imm14_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 31)) 0x003f) |
(((unsigned int)(n 37)) 0x3fc0);
}
-static __inline unsigned int
+static inline unsigned int
get_Mode(tilegx_bundle_bits n)
{
return (((unsigned int)(n 62)) 0x3);
}
-static __inline unsigned int
+static inline unsigned int
get_Opcode_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 28)) 0x7);
}
-static
[Qemu-devel] [PATCH 03/16 v1] linux-user/syscall.c: conditionalize syscalls which are not defined in tilegx
Some of architectures (e.g. tilegx), several syscall macros are not
supported, so switch them.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
linux-user/syscall.c | 50 +-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index f62c698..64e28f8 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -213,7 +213,7 @@ static int gettid(void) {
return -ENOSYS;
}
#endif
-#ifdef __NR_getdents
+#if defined(TARGET_NR_getdents) defined(__NR_getdents)
_syscall3(int, sys_getdents, uint, fd, struct linux_dirent *, dirp, uint,
count);
#endif
#if !defined(__NR_getdents) || \
@@ -5639,6 +5639,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
ret = get_errno(write(arg1, p, arg3));
unlock_user(p, arg2, 0);
break;
+#ifdef TARGET_NR_open
case TARGET_NR_open:
if (!(p = lock_user_string(arg1)))
goto efault;
@@ -5647,6 +5648,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
arg3));
unlock_user(p, arg1, 0);
break;
+#endif
case TARGET_NR_openat:
if (!(p = lock_user_string(arg2)))
goto efault;
@@ -5661,9 +5663,11 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
case TARGET_NR_brk:
ret = do_brk(arg1);
break;
+#ifdef TARGET_NR_fork
case TARGET_NR_fork:
ret = get_errno(do_fork(cpu_env, SIGCHLD, 0, 0, 0, 0));
break;
+#endif
#ifdef TARGET_NR_waitpid
case TARGET_NR_waitpid:
{
@@ -5698,6 +5702,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
break;
#endif
+#ifdef TARGET_NR_link
case TARGET_NR_link:
{
void * p2;
@@ -5711,6 +5716,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
+#endif
#if defined(TARGET_NR_linkat)
case TARGET_NR_linkat:
{
@@ -5728,12 +5734,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
}
break;
#endif
+#ifdef TARGET_NR_unlink
case TARGET_NR_unlink:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(unlink(p));
unlock_user(p, arg1, 0);
break;
+#endif
#if defined(TARGET_NR_unlinkat)
case TARGET_NR_unlinkat:
if (!(p = lock_user_string(arg2)))
@@ -5850,12 +5858,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
}
break;
#endif
+#ifdef TARGET_NR_mknod
case TARGET_NR_mknod:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(mknod(p, arg2, arg3));
unlock_user(p, arg1, 0);
break;
+#endif
#if defined(TARGET_NR_mknodat)
case TARGET_NR_mknodat:
if (!(p = lock_user_string(arg2)))
@@ -5864,12 +5874,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
unlock_user(p, arg2, 0);
break;
#endif
+#ifdef TARGET_NR_chmod
case TARGET_NR_chmod:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(chmod(p, arg2));
unlock_user(p, arg1, 0);
break;
+#endif
#ifdef TARGET_NR_break
case TARGET_NR_break:
goto unimplemented;
@@ -6004,6 +6016,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
break;
#endif
+#ifdef TARGET_NR_utimes
case TARGET_NR_utimes:
{
struct timeval *tvp, tv[2];
@@ -6022,6 +6035,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
+#endif
#if defined(TARGET_NR_futimesat)
case TARGET_NR_futimesat:
{
@@ -6050,12 +6064,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
case TARGET_NR_gtty:
goto unimplemented;
#endif
+#ifdef TARGET_NR_access
case TARGET_NR_access:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(access(path(p), arg2));
unlock_user(p, arg1, 0);
break;
+#endif
#if defined(TARGET_NR_faccessat) defined(__NR_faccessat)
case TARGET_NR_faccessat:
if (!(p = lock_user_string(arg2)))
@@ -6080,6 +6096,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
case TARGET_NR_kill:
ret = get_errno(kill(arg1, target_to_host_signal(arg2)));
break;
+#ifdef TARGET_NR_rename
case TARGET_NR_rename:
{
void *p2;
@@ -6093,6 +6110,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
+#endif
#if defined(TARGET_NR_renameat)
case TARGET_NR_renameat:
{
@@ -6108,12 +6126,14 @@ abi_long do_syscall(void *cpu_env
[Qemu-devel] [PATCH 11/16 v1] target-tilegx: Add related feature to support iret instruction
In fact, iret itself needs nothing, but the related previous and next
instructions need to be implemented.
SPR_EX_CONTEXT_0_0 and SPR_EX_CONTEXT_0_1 are related with iret, so let
them in a patch.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/cpu.h | 2 ++
target-tilegx/translate.c | 86 +--
2 files changed, 86 insertions(+), 2 deletions(-)
diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
index e404025..808f4e5 100644
--- a/target-tilegx/cpu.h
+++ b/target-tilegx/cpu.h
@@ -53,6 +53,8 @@ enum {
TILEGX_SPR_CMPEXCH = 0,
TILEGX_SPR_CRITICAL_SEC = 1,
TILEGX_SPR_SIM_CONTROL = 2,
+TILEGX_SPR_EX_CONTEXT_0_0 = 3,
+TILEGX_SPR_EX_CONTEXT_0_1 = 4,
TILEGX_SPR_COUNT
};
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 1dd3a43..541d603 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -48,7 +48,7 @@ static const char * const reg_names[] = {
};
static const char * const spreg_names[] = {
-cmpexch, criticalsec, simcontrol
+cmpexch, criticalsec, simcontrol, excontext00, excontext01
};
/* It is for temporary registers */
@@ -174,6 +174,71 @@ static void gen_swint1(struct DisasContext *dc)
}
/*
+ * Description
+ *
+ * Returns from an interrupt. Transfers control flow to the program counter
+ * location and protection level contained in the current PL ’s EX_CONTEXT
+ * registers, and restores the interrupt critical section bit to the value
+ * contained in those registers.
+ *
+ * Functional Description
+ *
+ * setNextPC(sprf [EX_CONTEXT_SPRF_OFFSET +
+ * (getCurrentProtectionLevel() * EX_CONTEXT_SIZE) +
+ * PC_EX_CONTEXT_OFFSET]);
+ * branchPredictedIncorrect();
+ * setProtectionLevel(sprf [EX_CONTEXT_SPRF_OFFSET +
+ * (getCurrentProtectionLevel() * EX_CONTEXT_SIZE) +
+ * PROTECTION_LEVEL_EX_CONTEXT_OFFSET]);
+ * setInterruptCriticalSection(
+ * sprf [EX_CONTEXT_SPRF_OFFSET +
+ * (getCurrentProtectionLevel() * EX_CONTEXT_SIZE) +
+ * INTERRUPT_CRITICAL_SECTION_EX_CONTEXT_OFFSET]);
+ *
+ * besides the PC we need to set our new protection level, and set the
interrupt
+ * critical section bit atomically inside of this instruction
+ */
+static void gen_iret(struct DisasContext *dc)
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, iret\n);
+/*
+ * In user mode, all related things are already done by previous and next
+ * instructions, so just skip it. Can reference __longjmp code for it.
+ *
+ * ENTRY (__longjmp)
+ * FEEDBACK_ENTER(__longjmp)
+ *
+ * #define RESTORE(r) { LD r, r0 ; ADDI_PTR r0, r0, REGSIZE }
+ * FOR_EACH_CALLEE_SAVED_REG(RESTORE)
+ *
+ * {
+ * LD r2, r0 ; retrieve ICS bit from jmp_buf
+ * movei r3, 1
+ * CMPEQI r0, r1, 0
+ * }
+ *
+ * {
+ * mtspr INTERRUPT_CRITICAL_SECTION, r3
+ * shli r2, r2, SPR_EX_CONTEXT_0_1__ICS_SHIFT
+ * }
+ *
+ * {
+ * mtspr EX_CONTEXT_0_0, lr
+ * ori r2, r2, RETURN_PL
+ * }
+ *
+ * {
+ * or r0, r1, r0
+ * mtspr EX_CONTEXT_0_1, r2
+ * }
+ *
+ * iret
+ *
+ * jrp lr
+ */
+}
+
+/*
* Many SPR reads/writes have side effects and cannot be buffered. However,
they
* are all in the X1 pipe, which we are excuting last, therefore we need not do
* additional buffering.
@@ -197,6 +262,12 @@ static void gen_mfspr(struct DisasContext *dc, uint8_t
rdst, uint16_t imm14)
case SPR_SIM_CONTROL:
tcg_gen_mov_i64(cpu_regs[rdst], cpu_spregs[TILEGX_SPR_SIM_CONTROL]);
return;
+case SPR_EX_CONTEXT_0_0:
+tcg_gen_mov_i64(cpu_regs[rdst], cpu_spregs[TILEGX_SPR_EX_CONTEXT_0_0]);
+return;
+case SPR_EX_CONTEXT_0_1:
+tcg_gen_mov_i64(cpu_regs[rdst], cpu_spregs[TILEGX_SPR_EX_CONTEXT_0_1]);
+return;
default:
qemu_log_mask(LOG_UNIMP, UNIMP mfspr 0x%x.\n, imm14);
}
@@ -218,6 +289,12 @@ static void gen_mtspr(struct DisasContext *dc, uint8_t
rsrc, uint16_t imm14)
case SPR_SIM_CONTROL:
tcg_gen_mov_i64(cpu_spregs[TILEGX_SPR_SIM_CONTROL], load_gr(dc, rsrc));
return;
+case SPR_EX_CONTEXT_0_0:
+tcg_gen_mov_i64(cpu_spregs[TILEGX_SPR_EX_CONTEXT_0_0], load_gr(dc,
rsrc));
+return;
+case SPR_EX_CONTEXT_0_1:
+tcg_gen_mov_i64(cpu_spregs[TILEGX_SPR_EX_CONTEXT_0_1], load_gr(dc,
rsrc));
+return;
default:
qemu_log_mask(LOG_UNIMP, UNIMP mtspr 0x%x.\n, imm14);
}
@@ -2257,6 +2334,12 @@ static void decode_u_opcode_ex_x1(struct DisasContext
*dc,
return;
}
break;
+case IRET_UNARY_OPCODE_X1:
+if (!rdst !rsrc
[Qemu-devel] [PATCH 14/16 v1] linux-user: main: Use negative qemu errno for syscall return errno
The qemu errno is negative of normal errno, so revert it before return from syscall, or the related user mode checking will fail, e.g. cp/mv will call stat64 and check errno ENOENT (not -ENOENT). Signed-of-by Chen Gang gang.chen.5...@gmail.com --- linux-user/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux-user/main.c b/linux-user/main.c index 253aade..f0bda09 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3654,7 +3654,7 @@ void cpu_loop(CPUTLGState *env) env-regs[4], env-regs[5], env-regs[6], env-regs[7]); env-regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(env-regs[TILEGX_R_RE]) - ? env-regs[TILEGX_R_RE] + ? - env-regs[TILEGX_R_RE] : 0; break; case TILEGX_EXCP_OPCODE_EXCH: -- 1.9.3
[Qemu-devel] [PATCH 00/16 v1] tilegx: Firstly add tilegx target for linux-user
After the implementation, it can let normal tilegx program working (e.g. sh, vi, cp, mv ...). And the known left issues are: - At present, it can not pass gcc testsuite (it causes some programs pending). - The floating point implementation is not included, since at present, it is only the temporary implementation. - There are still some instructions which are not implemented. Chen Gang (16): linux-user: tilegx: Firstly add architecture related features linux-user: Support tilegx architecture in linux-user linux-user/syscall.c: conditionalize syscalls which are not defined in tilegx target-tilegx: Add opcode basic implementation from Tilera Corporation target-tilegx/opcode_tilegx.h: Modify it to fit QEMU usage target-tilegx: Add special register information from Tilera Corporation target-tilegx: Add cpu basic features for linux-user target-tilegx: Add several helpers for instructions translation target-tilegx: Generate tcg instructions to finish Hello world target-tilegx: Add TILE-Gx building files target-tilegx: Add related feature to support iret instruction target-tilegx: Implement decode_rrr_8_opcode_y0 target-tilegx: Use int8_t instead of uint8_t for imm8 in gen_st_add() linux-user: main: Use negative qemu errno for syscall return errno tilegx: Match with the latest qemu master tree target-tilegx: Implement additional instructions in normal working flow configure |2 + default-configs/tilegx-linux-user.mak |1 + include/elf.h |2 + linux-user/elfload.c | 23 + linux-user/main.c | 295 +++ linux-user/syscall.c | 50 +- linux-user/syscall_defs.h | 14 +- linux-user/tilegx/syscall.h | 40 + linux-user/tilegx/syscall_nr.h| 324 linux-user/tilegx/target_cpu.h| 35 + linux-user/tilegx/target_signal.h | 28 + linux-user/tilegx/target_structs.h| 46 + linux-user/tilegx/termbits.h | 274 +++ target-tilegx/Makefile.objs |1 + target-tilegx/cpu.c | 143 ++ target-tilegx/cpu.h | 177 ++ target-tilegx/helper.c| 93 + target-tilegx/helper.h|7 + target-tilegx/opcode_tilegx.h | 1406 ++ target-tilegx/spr_def_64.h| 216 +++ target-tilegx/translate.c | 3282 + 21 files changed, 6453 insertions(+), 6 deletions(-) create mode 100644 default-configs/tilegx-linux-user.mak create mode 100644 linux-user/tilegx/syscall.h create mode 100644 linux-user/tilegx/syscall_nr.h create mode 100644 linux-user/tilegx/target_cpu.h create mode 100644 linux-user/tilegx/target_signal.h create mode 100644 linux-user/tilegx/target_structs.h create mode 100644 linux-user/tilegx/termbits.h create mode 100644 target-tilegx/Makefile.objs create mode 100644 target-tilegx/cpu.c create mode 100644 target-tilegx/cpu.h create mode 100644 target-tilegx/helper.c create mode 100644 target-tilegx/helper.h create mode 100644 target-tilegx/opcode_tilegx.h create mode 100644 target-tilegx/spr_def_64.h create mode 100644 target-tilegx/translate.c -- 1.9.3
[Qemu-devel] [PATCH 09/16 v1] target-tilegx: Generate tcg instructions to finish Hello world
Generate related tcg instructions, and qemu tilegx can finish running
Hello world. The elf64 binary can be static or shared.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/translate.c | 2966 +
1 file changed, 2966 insertions(+)
create mode 100644 target-tilegx/translate.c
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
new file mode 100644
index 000..1dd3a43
--- /dev/null
+++ b/target-tilegx/translate.c
@@ -0,0 +1,2966 @@
+/*
+ * QEMU TILE-Gx CPU
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * http://www.gnu.org/licenses/lgpl-2.1.html
+ */
+
+#include cpu.h
+#include qemu/log.h
+#include disas/disas.h
+#include tcg-op.h
+#include exec/cpu_ldst.h
+#include opcode_tilegx.h
+#include spr_def_64.h
+
+#define FMT64X %016 PRIx64
+#define TILEGX_TMP_REGS(TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE + 1)
+
+static TCGv_ptr cpu_env;
+static TCGv cpu_pc;
+static TCGv cpu_regs[TILEGX_R_COUNT];
+static TCGv cpu_spregs[TILEGX_SPR_COUNT];
+#if defined(CONFIG_USER_ONLY)
+static TCGv_i32 cpu_excparam;
+#endif
+
+static const char * const reg_names[] = {
+ r0, r1, r2, r3, r4, r5, r6, r7,
+ r8, r9, r10, r11, r12, r13, r14, r15,
+r16, r17, r18, r19, r20, r21, r22, r23,
+r24, r25, r26, r27, r28, r29, r30, r31,
+r32, r33, r34, r35, r36, r37, r38, r39,
+r40, r41, r42, r43, r44, r45, r46, r47,
+r48, r49, r50, r51, bp, tp, sp, lr
+};
+
+static const char * const spreg_names[] = {
+cmpexch, criticalsec, simcontrol
+};
+
+/* It is for temporary registers */
+typedef struct DisasContextTemp {
+uint8_t idx; /* index */
+TCGv val; /* value */
+} DisasContextTemp;
+
+/* This is the state at translation time. */
+typedef struct DisasContext {
+uint64_t pc; /* Current pc */
+int exception; /* Current exception */
+
+TCGv zero; /* For zero register */
+
+DisasContextTemp *tmp_regcur; /* Current temporary registers */
+DisasContextTemp tmp_regs[TILEGX_TMP_REGS]; /* All temporary registers */
+struct {
+TCGCond cond; /* Branch condition */
+TCGv dest; /* pc jump destination, if will jump */
+TCGv val1; /* Firt value for condition comparing */
+TCGv val2; /* Second value for condition comparing */
+} jmp; /* Jump object, only once in each TB block
*/
+} DisasContext;
+
+#include exec/gen-icount.h
+
+static void gen_exception(DisasContext *dc, int num)
+{
+TCGv_i32 tmp = tcg_const_i32(num);
+
+gen_helper_exception(cpu_env, tmp);
+tcg_temp_free_i32(tmp);
+}
+
+/*
+ * All exceptions which can still let working flow continue are all in pipe x1,
+ * which is the last pipe of a bundle. So it is OK to only process the first
+ * exception within a bundle.
+ */
+static void set_exception(DisasContext *dc, int num)
+{
+if (dc-exception == TILEGX_EXCP_NONE) {
+dc-exception = num;
+}
+}
+
+static bool check_gr(DisasContext *dc, uint8_t reg)
+{
+if (likely(reg TILEGX_R_COUNT)) {
+return true;
+}
+
+switch (reg) {
+case TILEGX_R_SN:
+case TILEGX_R_ZERO:
+break;
+case TILEGX_R_IDN0:
+case TILEGX_R_IDN1:
+set_exception(dc, TILEGX_EXCP_REG_IDN_ACCESS);
+break;
+case TILEGX_R_UDN0:
+case TILEGX_R_UDN1:
+case TILEGX_R_UDN2:
+case TILEGX_R_UDN3:
+set_exception(dc, TILEGX_EXCP_REG_UDN_ACCESS);
+break;
+default:
+g_assert_not_reached();
+}
+return false;
+}
+
+static TCGv load_zero(DisasContext *dc)
+{
+if (TCGV_IS_UNUSED_I64(dc-zero)) {
+dc-zero = tcg_const_i64(0);
+}
+return dc-zero;
+}
+
+static TCGv load_gr(DisasContext *dc, uint8_t reg)
+{
+if (check_gr(dc, reg)) {
+return cpu_regs[reg];
+}
+return load_zero(dc);
+}
+
+static TCGv dest_gr(DisasContext *dc, uint8_t rdst)
+{
+DisasContextTemp *tmp = dc-tmp_regcur++;
+
+/* Skip the result, mark the exception if necessary, and continue */
+check_gr(dc, rdst);
+assert((dc-tmp_regcur - dc-tmp_regs) TILEGX_TMP_REGS);
+tmp-idx = rdst;
+tmp-val = tcg_temp_new_i64();
+return
[Qemu-devel] [PATCH 04/16 v1] target-tilegx: Add opcode basic implementation from Tilera Corporation
It is copied from Linux kernel arch/tile/include/uapi/arch/
opcode_tilegx.h.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
target-tilegx/opcode_tilegx.h | 1406 +
1 file changed, 1406 insertions(+)
create mode 100644 target-tilegx/opcode_tilegx.h
diff --git a/target-tilegx/opcode_tilegx.h b/target-tilegx/opcode_tilegx.h
new file mode 100644
index 000..d76ff2d
--- /dev/null
+++ b/target-tilegx/opcode_tilegx.h
@@ -0,0 +1,1406 @@
+/* TILE-Gx opcode information.
+ *
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ *
+ *
+ *
+ *
+ *
+ */
+
+#ifndef __ARCH_OPCODE_H__
+#define __ARCH_OPCODE_H__
+
+#ifndef __ASSEMBLER__
+
+typedef unsigned long long tilegx_bundle_bits;
+
+/* These are the bits that determine if a bundle is in the X encoding. */
+#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 62)
+
+enum
+{
+ /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
+ TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
+
+ /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
+ TILEGX_NUM_PIPELINE_ENCODINGS = 5,
+
+ /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */
+ TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
+
+ /* Instructions take this many bytes. */
+ TILEGX_BUNDLE_SIZE_IN_BYTES = 1 TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES,
+
+ /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */
+ TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
+
+ /* Bundles should be aligned modulo this number of bytes. */
+ TILEGX_BUNDLE_ALIGNMENT_IN_BYTES =
+(1 TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
+
+ /* Number of registers (some are magic, such as network I/O). */
+ TILEGX_NUM_REGISTERS = 64,
+};
+
+/* Make a few tile_ variables to simplify common code between
+ architectures. */
+
+typedef tilegx_bundle_bits tile_bundle_bits;
+#define TILE_BUNDLE_SIZE_IN_BYTES TILEGX_BUNDLE_SIZE_IN_BYTES
+#define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES
+#define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \
+ TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES
+#define TILE_BPT_BUNDLE TILEGX_BPT_BUNDLE
+
+/* 64-bit pattern for a { bpt ; nop } bundle. */
+#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
+
+static __inline unsigned int
+get_BFEnd_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 12)) 0x3f);
+}
+
+static __inline unsigned int
+get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 24)) 0xf);
+}
+
+static __inline unsigned int
+get_BFStart_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 18)) 0x3f);
+}
+
+static __inline unsigned int
+get_BrOff_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 31)) 0x003f) |
+ (((unsigned int)(n 37)) 0x0001ffc0);
+}
+
+static __inline unsigned int
+get_BrType_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 54)) 0x1f);
+}
+
+static __inline unsigned int
+get_Dest_Imm8_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 31)) 0x003f) |
+ (((unsigned int)(n 43)) 0x00c0);
+}
+
+static __inline unsigned int
+get_Dest_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 0)) 0x3f);
+}
+
+static __inline unsigned int
+get_Dest_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 31)) 0x3f);
+}
+
+static __inline unsigned int
+get_Dest_Y0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 0)) 0x3f);
+}
+
+static __inline unsigned int
+get_Dest_Y1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 31)) 0x3f);
+}
+
+static __inline unsigned int
+get_Imm16_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 12)) 0x);
+}
+
+static __inline unsigned int
+get_Imm16_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 43)) 0x);
+}
+
+static __inline unsigned int
+get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 20)) 0xff);
+}
+
+static __inline unsigned int
+get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 51)) 0xff);
+}
+
+static __inline unsigned int
+get_Imm8_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 12)) 0xff);
+}
+
+static __inline unsigned int
+get_Imm8_X1(tilegx_bundle_bits n
[Qemu-devel] [PATCH 15/16 v1] tilegx: Match with the latest qemu master tree
The interface of cpu_exec and cpu_exec_init are changed, so qemu tilegx
should match with them.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
linux-user/main.c | 2 +-
target-tilegx/cpu.c | 2 +-
target-tilegx/cpu.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index f0bda09..2d4b0b4 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3644,7 +3644,7 @@ void cpu_loop(CPUTLGState *env)
while (1) {
cpu_exec_start(cs);
-trapnr = cpu_tilegx_exec(env);
+trapnr = cpu_tilegx_exec(cs);
cpu_exec_end(cs);
switch (trapnr) {
case TILEGX_EXCP_SYSCALL:
diff --git a/target-tilegx/cpu.c b/target-tilegx/cpu.c
index 663fcb6..4793909 100644
--- a/target-tilegx/cpu.c
+++ b/target-tilegx/cpu.c
@@ -77,7 +77,7 @@ static void tilegx_cpu_initfn(Object *obj)
static bool tcg_initialized;
cs-env_ptr = env;
-cpu_exec_init(env);
+cpu_exec_init(cs, error_abort);
if (tcg_enabled() !tcg_initialized) {
tcg_initialized = true;
diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
index 808f4e5..a7c812b 100644
--- a/target-tilegx/cpu.h
+++ b/target-tilegx/cpu.h
@@ -153,7 +153,7 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState
*env)
#include exec/cpu-all.h
void tilegx_tcg_init(void);
-int cpu_tilegx_exec(CPUTLGState *s);
+int cpu_tilegx_exec(CPUState *s);
int cpu_tilegx_signal_handler(int host_signum, void *pinfo, void *puc);
TileGXCPU *cpu_tilegx_init(const char *cpu_model);
--
1.9.3
Re: [Qemu-devel] [Consult] tilegx: About floating point instructions
On 8/18/15 22:32, Peter Maydell wrote: On 18 August 2015 at 15:27, Chen Gang xili_gchen_5...@hotmail.com wrote: Welcome any ideas, suggestions and completions. You should stop working on adding new features and instructions, and concentrate on getting a coherent set of patches for some subset of the instruction set reviewed and into QEMU. OK, thanks. It sounds good. But I guess, it is not executable: - I have already send a set of patches, but they are not integrated into qemu (or not reviewed). - I have to continue, although they are not integrated into (it means I have to add new features and instructions, at present). - For me, when tilegx qemu pass gcc testsuite, and finish floating point insns in the preciser way, I guess, that is a reasonable point to send new patches to qemu. Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [Consult] tilegx: About floating point instructions
OK, thanks. What you said sounds reasonable to me. I shall try to send patches to qemu, firstly. :-) On 8/19/15 06:15, Peter Maydell wrote: On 18 August 2015 at 22:29, Chen Gang xili_gchen_5...@hotmail.com wrote: On 8/18/15 22:32, Peter Maydell wrote: On 18 August 2015 at 15:27, Chen Gang xili_gchen_5...@hotmail.com wrote: Welcome any ideas, suggestions and completions. You should stop working on adding new features and instructions, and concentrate on getting a coherent set of patches for some subset of the instruction set reviewed and into QEMU. OK, thanks. It sounds good. But I guess, it is not executable: - I have already send a set of patches, but they are not integrated into qemu (or not reviewed). You need to concentrate on getting these in. That means: * check whether there are outstanding review comments (or trivial bugs you found yourself in the instructions covered by these parts) -- if so, then respin the patchset and resend it * 'ping' the patch series to remind people to review it (Specifically, IIRC, RTH needs to review the codegen bits of the integer patches.) - I have to continue, although they are not integrated into (it means I have to add new features and instructions, at present). If you do this then you are drawing the attention and time of reviewers away from the patches which are nearly ready to go into QEMU and towards the new stuff you post. This means that the older patchsets are less likely to move forward. - For me, when tilegx qemu pass gcc testsuite, and finish floating point insns in the preciser way, I guess, that is a reasonable point to send new patches to qemu. This will result in a huge patchset which is very hard to review (and which is likely to get requests from me to split it up and send a smaller subset which is reviewable). thanks -- PMM -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [Consult] tilegx: About floating point instructions
On 8/18/15 05:43, Richard Henderson wrote: I repeat: This is an extremely bad idea. I will certainly not sign off on any patch that includes this. OK. At least it is not the professional implementation. But for me, it can always get the correct result: - It 'guess' the 'flag' format instead of 'guess' whole data format, so this is an easier way (although it wastes resources, and it is UN-professional). - The 'flag' has 'room' for callee to save its information, so we can use the 'room' for recognizing each different 'flag' type (so we can treat 'flag' as callee's context). - The caller must keep the 'flag' consistent for all floating point insns. So if caller finds new using way (it is almost impossible), our implementation can still adapt the new using way, automatically. If it is really can always get the correct result (else I have to implement with your suggested way, right now): - I can use it for gcc testsuite (now, it fixed 100+ gcc testsuite failures -- I guess, all floating point tests are passed test). - And within this month, I shall try to finish gcc testsuite with qemu in my free time (still 700- issues left), and also make patches for kernel mm for learning (may be helpful for softmmu linux user). - Next month (after finish gcc testsuite with tilegx qemu), I shall implement the floating point in the preciser ways (you suggested), instead of current temporary implementation. By the way, I have delay quite much for Linux kernel and gcc in my free time: - Originally, I want to cross compile kernel under another archs in my free time within this month, but until now, I do nothing for it (but next, I shall try some mm patches instead of, hope I can succeed). - Originally, I want to fix one gcc bug under bugzilla, but until now, I do nothing for it (it is really delayed quite too much). Welcome any ideas, suggestions and completions. Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [Consult] tilegx: About floating point instructions
On 8/18/15 01:31, Richard Henderson wrote:
On 08/15/2015 11:16 AM, Chen Gang wrote:
But what you said is really quite valuable to me!! we can treat the flag
as a caller saved context, then can let the caller can use callee freely
(in fact, I guess, the real hardware treats it as caller context, too).
- we have to define the flag format based on the existing format in the
related docs and tilegx.md (reserve 0-20 and 25-31 bits).
- We can only use 21-24 for mark addsub, mul, or typecast result. If
21-24 bits are all zero, it means typecast result. For fsingle: 32-63
bits is the input integer; for fdouble: srca is the input integer.
Plausible.
- For addsub and mul result, we use 32-63 bits for an index of resource
handler (like 'fd' returned by open). fsingle_addsub2, fsingle_mul1,
fdouble_mul_flags, fdouble_addsub allocate resource, and pack1 free.
No, that's a bad idea. No state external to the inputs to the insns.
We can use 21-24 bits for the state external to the inputs to the insns.
My idea is below:
/*
* Single floaing point instructions decription.
*
* - fsingle_add1, fsingle_sub1, and fsingle_pack1/2 can be used individually.
*
* - when fsingle_pack1/2 is used individually, it is for type cast.
*
* - the old 4Kth result is alrealy useless for caller.
*
* fsingle_add1; make context and calc result from rsrca and rsrcb.
* ; save result in roundup array, and add index to context.
* ; move context to rdst.
*
* fsingle_sub1; make context and calc result from rsrca and rsrcb.
* ; save result in roundup array, and add index to context.
* ; move context to rdst.
*
* fsingle_addsub2 ; skipped.
*
* fsingle_mul1; make context and calc result from rsrca and srcb.
* ; save result in roundup array, and add index to context.
* ; move context to rdst.
*
* fsingle_mul2; move rsrca to rdst.
*
* fsingle_pack1 ; skipped.
*
* fsingle_pack2 ; get context from rsrca (rsrca is context).
* ; if context for add/sub/mul
* ; get result from roundup array based on index.
* ; move result to rdst.
* ; else
* ; get (u)int32_t interger from context,
* ; (u)int32_to_float32.
*/
/*
* Double floating point instructions' description.
*
* - fdouble_add_flags, fdouble_sub_flags, and fdouble_pack1/2 can be used
*individually.
*
* - when fdouble_pack1/2 is used individually, it is for type cast.
*
* - the old 4Kth result is alrealy useless for caller.
*
* fdouble_unpack_max: ; skipped.
*
* fdouble_unpack_min: ; skipped.
*
* fdouble_add_flags: ; make context and calc result from rsrca and rsrcb.
* ; save result in roundup array, and add index to context.
* ; move context to rdst.
*
* fdouble_sub_flags: ; make context and calc result from rsrca and rsrcb.
* ; save result in roundup array, and add index to context.
* ; move context to rdst.
*
* fdouble_addsub: ; skipped.
*
* fdouble_mul_flags: ; make context and calc result from rsrca and rsrcb.
* ; save result in roundup array, and add index to context.
* ; move context to rdst.
*
* fdouble_pack1: ; get context from rsrcb.
* ; if context for add/sub/mul
* ; get result from roundup array based on index.
* ; move result to rdst.
* ; else
* ; get (u)int32_t interger from rsrca
* ; (u)int32_to_float64.
*
* fdouble_pack2: ; skipped.
*/
#define TILEGX_F_COUNT 0x1000 /* Maximized results count for fdouble */
#define TILEGX_F_DUINT 0x21b00 /* exp is for uint32_t to double */
#define TILEGX_F_DINT 0xa1b00 /* exp is for int32_t to double */
#define TILEGX_F_SUINT 0x9e/* exp is for uint32_t to single */
#define TILEGX_F_SINT 0x29e /* exp is for int32_t to single */
#define TILEGX_F_TCAST 0 /* Result type is for typecast, MUST BE 0 */
#define TILEGX_F_TCALC 1 /* Result type is for add/sub/mul */
#pragma pack(push, 1)
typedef struct TileGXFPCtx {
/* According to float(uns)sisf2 and float(uns)sidf2 in gcc tilegx.md */
uint64_t exp : 20; /* Exponent, for TILEGX_F_(D/S)(U)INT */
/* Context type, defined and used by callee */
uint64_t type : 5; /* For TILEGX_F_T(CAST/CALC) */
/* Come from TILE-Gx ISA document, Table 7-2 for floating point */
uint64_t unordered : 1;/* The two are unordered */
uint64_t lt : 1; /* 1st is less than 2nd */
uint64_t le : 1; /* 1st is less than or equal to 2nd */
uint64_t gt : 1
Re: [Qemu-devel] [Consult] tilegx: About floating point instructions
On 8/16/15 09:41, Chen Gang wrote: On 8/16/15 02:16, Chen Gang wrote: On 8/15/15 23:47, Richard Henderson wrote: On Aug 15, 2015 2:56 AM, Chen Gang xili_gchen_5...@hotmail.com Oh, we are unlucky, after continue gcc testsuite, add/sub floating point insns also can be mixed together! The related C code, -save-temps, and objdump files are in attachments (is it gcc's issue? I guess not). So, I guess, we have to 'crack' all floating point insns, precisely, or we can not pass gcc testsuite. If you go back to my first message to you on the subject, you'll find that my suggestion was to not split the operation at all, using move for pack1. Which would nicely handle any such interleaving. OK, thanks, but for float(uns)sisf2 and float(uns)sidf2, we can not only simply move. :-( But what you said is really quite valuable to me!! we can treat the flag as a caller saved context, then can let the caller can use callee freely (in fact, I guess, the real hardware treats it as caller context, too). - we have to define the flag format based on the existing format in the related docs and tilegx.md (reserve 0-20 and 25-31 bits). - We can only use 21-24 for mark addsub, mul, or typecast result. If 21-24 bits are all zero, it means typecast result. For fsingle: 32-63 bits is the input integer; for fdouble: srca is the input integer. - For addsub and mul result, we use 32-63 bits for an index of resource handler (like 'fd' returned by open). fsingle_addsub2, fsingle_mul1, fdouble_mul_flags, fdouble_addsub allocate resource, and pack1 free. But if caller make mistakes, our implementation can not avoid related resource leak (but the real hardware can, it also lets caller save all related resources; when it needs them, it can let caller pass them to). If we assume that the optimization for the floating point insns can not cross the basic blocks (I guess so), we can reset all related resources when start a basic block. Oh, sorry, even qemu itself, my split a basic block into 2 basic blocks, when the basic block is too big. And we also have to assume a same value may call fdouble_pack1 individually with multiple times. So for the resource management, we can do like this: - For fsingle, it can be saved in 32-63 bits of caller context (it is float32 which is 32-bit). - For fdouble, we can allocate a 'bit' buffer for it (e.g. 8KB), when the saved values count overflow 1K, let it roundup to 0 again -- of cause, the old 1Kth value should be already useless. I guess, in this way, we can emulate the tilgex floating points insns!! :-) Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [Consult] tilegx: About floating point instructions
On 8/16/15 02:16, Chen Gang wrote: On 8/15/15 23:47, Richard Henderson wrote: On Aug 15, 2015 2:56 AM, Chen Gang xili_gchen_5...@hotmail.com Oh, we are unlucky, after continue gcc testsuite, add/sub floating point insns also can be mixed together! The related C code, -save-temps, and objdump files are in attachments (is it gcc's issue? I guess not). So, I guess, we have to 'crack' all floating point insns, precisely, or we can not pass gcc testsuite. If you go back to my first message to you on the subject, you'll find that my suggestion was to not split the operation at all, using move for pack1. Which would nicely handle any such interleaving. OK, thanks, but for float(uns)sisf2 and float(uns)sidf2, we can not only simply move. :-( But what you said is really quite valuable to me!! we can treat the flag as a caller saved context, then can let the caller can use callee freely (in fact, I guess, the real hardware treats it as caller context, too). - we have to define the flag format based on the existing format in the related docs and tilegx.md (reserve 0-20 and 25-31 bits). - We can only use 21-24 for mark addsub, mul, or typecast result. If 21-24 bits are all zero, it means typecast result. For fsingle: 32-63 bits is the input integer; for fdouble: srca is the input integer. - For addsub and mul result, we use 32-63 bits for an index of resource handler (like 'fd' returned by open). fsingle_addsub2, fsingle_mul1, fdouble_mul_flags, fdouble_addsub allocate resource, and pack1 free. But if caller make mistakes, our implementation can not avoid related resource leak (but the real hardware can, it also lets caller save all related resources; when it needs them, it can let caller pass them to). If we assume that the optimization for the floating point insns can not cross the basic blocks (I guess so), we can reset all related resources when start a basic block. Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [Consult] tilegx: About floating point instructions
On 8/13/15 22:59, Chen Gang wrote:
Hello all:
For me, I guess for single insns, they are simple, and each calculation
insns group can not be mixed with each other. So current implementation
should be OK.
For double insns, I guess, only mul calculation can be mixed with other
calculation groups (add/sub groups or int2float/double groups), because
of optimization -- the mul calculation group have many insns.
Oh, we are unlucky, after continue gcc testsuite, add/sub floating point
insns also can be mixed together! The related C code, -save-temps, and
objdump files are in attachments (is it gcc's issue? I guess not).
So, I guess, we have to 'crack' all floating point insns, precisely, or
we can not pass gcc testsuite.
At present, for me, I shall try to fix another issues which are found by
gcc testsuite, at last 'crack' the floating point insns. I guess, I can
not finish it in this month (I shall try to finish in the next month).
Thanks.
So the implementation is below:
/*
* Assume floating point mul operation group can mix with other groups.
*
* fdouble_unpack_max: ; skipped.
*
* fdouble_unpack_min: ; skipped.
*
* fdouble_add_flags: ; move calc flags to dest.
* save calc flags.
* save calc addsub result.
*
* fdouble_sub_flags: ; move calc flags to dest.
* save calc flags.
* save calc addsub result.
*
* fdouble_addsub: ; move calc addsub result to dest.
* set addsub result flag.
*
* fdouble_mul_flags: ; move calc mul result to dest.
*
* fdouble_pack1: ; if addsub result set
* srca == saved addsub result
* srcb == saved calc flags
* move srca to dest.
* else
* move srcb to dest.
*
* fdouble_pack2: ; if srcb == r63 addsub result flag
* reset addsub result flag.
* else if srcb == r63
* pack srca dest (dest is orig srcb of pack1)
* reference from tilegx.md: float(uns)sidf2.
* get (u)int32_t a, then (u)int32_to_float64.
* else
* skipped.
*/
On 8/11/15 21:18, Chen Gang wrote:
Oh, it seems a little complex, for a testsuite case, it lets double add
and double mul together! We need save more information for the correct
calculation in pack1.
It is 20020314-1.exe, the related code (I guess it is correct):
...
fdouble_unpack_max r10, r3, zero
.LVL2:
fdouble_unpack_max r15, r2, zero
fdouble_add_flags r12, r0, r1
mul_hu_lu r13, r15, r10
mul_lu_lu r16, r15, r10
mula_hu_lu r13, r10, r15
fdouble_unpack_min r11, r0, r1
{
shlir14, r13, 32
fdouble_unpack_max r17, r0, r1
}
{
mul_hu_hu r15, r15, r10
add r16, r16, r14
}
{
shrui r13, r13, 32
fdouble_addsub r17, r11, r12
}
{
cmpltu r14, r16, r14
fdouble_mul_flags r3, r2, r3
}
.LVL3:
{
add r13, r15, r13
fdouble_pack1 r12, r17, r12
}
{
add r13, r13, r14
fdouble_unpack_max r10, r0, zero
}
fdouble_pack1 r3, r13, r3
fdouble_pack2 r12, r17, zero
fdouble_pack2 r3, r13, r16
...
Welcome any additional ideas, suggestions and completions.
Thanks.
On 8/9/15 09:14, Chen Gang wrote:
On 8/9/15 09:10, Chen Gang wrote:
On 8/9/15 01:23, Chen Gang wrote:
Hello all:
Below is my current idea for all floating point insns. For me, it is not
the precise implementation, even not completely implement -- assume pack
insns can only for packing (u)int32_t when they are used individually:
fsingle_add1; return calc flags, save calc result to env.
fsingle_sub1; return calc flags, save calc result to env.
fsingle_addsub2 ; set has result flag.
fsingle_mul1; skip return value, save calc result to env.
set has result flag.
fsingle_mul2; skipped.
fsingle_pack1 ; skipped.
fsingle_pack1 ; if has result
reset has result flag.
return calc result from env.
else
pack srca
reference from tilegx.md: float(uns)sisf2.
get (u)int32_t a, then (u)int32_to_float32.
For pack srca and srcb, the related demo like below (srca and srcb
are uint64_t):
Oh, sorry, for pack srca (not for pack srca and srcb
Re: [Qemu-devel] [Consult] tilegx: About floating point instructions
On 8/15/15 23:47, Richard Henderson wrote: On Aug 15, 2015 2:56 AM, Chen Gang xili_gchen_5...@hotmail.com Oh, we are unlucky, after continue gcc testsuite, add/sub floating point insns also can be mixed together! The related C code, -save-temps, and objdump files are in attachments (is it gcc's issue? I guess not). So, I guess, we have to 'crack' all floating point insns, precisely, or we can not pass gcc testsuite. If you go back to my first message to you on the subject, you'll find that my suggestion was to not split the operation at all, using move for pack1. Which would nicely handle any such interleaving. OK, thanks, but for float(uns)sisf2 and float(uns)sidf2, we can not only simply move. :-( But what you said is really quite valuable to me!! we can treat the flag as a caller saved context, then can let the caller can use callee freely (in fact, I guess, the real hardware treats it as caller context, too). - we have to define the flag format based on the existing format in the related docs and tilegx.md (reserve 0-20 and 25-31 bits). - We can only use 21-24 for mark addsub, mul, or typecast result. If 21-24 bits are all zero, it means typecast result. For fsingle: 32-63 bits is the input integer; for fdouble: srca is the input integer. - For addsub and mul result, we use 32-63 bits for an index of resource handler (like 'fd' returned by open). fsingle_addsub2, fsingle_mul1, fdouble_mul_flags, fdouble_addsub allocate resource, and pack1 free. But if caller make mistakes, our implementation can not avoid related resource leak (but the real hardware can, it also lets caller save all related resources; when it needs them, it can let caller pass them to). Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] Plan for using softmmu with linux-user
On 8/14/15 22:44, Richard Henderson wrote: On 08/14/2015 02:37 AM, gchen gchen wrote: - If I implement SW64 tcg backend, I guess, I cann't get help from qemu upstream: I don't think SW64 is valuable enough for upstream (either I am not sure that I can implment Alpha tcg backend in working time). It'll need some updating to apply to master, but I started an alpha backend a couple of years ago. It looks like it was last rebased in May 2014. git://github.com/rth7680/qemu.git tcg-alpha-2 Thank you very much, I shall clone it. I guess, it will save my much time resources. If possible, it will be better to merge the alpha tcg backend to qemu master main branch (at least for me, it is useful). :-) Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [Consult] tilegx: About floating point instructions
Hello all:
For me, I guess for single insns, they are simple, and each calculation
insns group can not be mixed with each other. So current implementation
should be OK.
For double insns, I guess, only mul calculation can be mixed with other
calculation groups (add/sub groups or int2float/double groups), because
of optimization -- the mul calculation group have many insns.
So the implementation is below:
/*
* Assume floating point mul operation group can mix with other groups.
*
* fdouble_unpack_max: ; skipped.
*
* fdouble_unpack_min: ; skipped.
*
* fdouble_add_flags: ; move calc flags to dest.
* save calc flags.
* save calc addsub result.
*
* fdouble_sub_flags: ; move calc flags to dest.
* save calc flags.
* save calc addsub result.
*
* fdouble_addsub: ; move calc addsub result to dest.
* set addsub result flag.
*
* fdouble_mul_flags: ; move calc mul result to dest.
*
* fdouble_pack1: ; if addsub result set
* srca == saved addsub result
* srcb == saved calc flags
* move srca to dest.
* else
* move srcb to dest.
*
* fdouble_pack2: ; if srcb == r63 addsub result flag
* reset addsub result flag.
* else if srcb == r63
* pack srca dest (dest is orig srcb of pack1)
* reference from tilegx.md: float(uns)sidf2.
* get (u)int32_t a, then (u)int32_to_float64.
* else
* skipped.
*/
On 8/11/15 21:18, Chen Gang wrote:
Oh, it seems a little complex, for a testsuite case, it lets double add
and double mul together! We need save more information for the correct
calculation in pack1.
It is 20020314-1.exe, the related code (I guess it is correct):
...
fdouble_unpack_max r10, r3, zero
.LVL2:
fdouble_unpack_max r15, r2, zero
fdouble_add_flags r12, r0, r1
mul_hu_lu r13, r15, r10
mul_lu_lu r16, r15, r10
mula_hu_lu r13, r10, r15
fdouble_unpack_min r11, r0, r1
{
shlir14, r13, 32
fdouble_unpack_max r17, r0, r1
}
{
mul_hu_hu r15, r15, r10
add r16, r16, r14
}
{
shrui r13, r13, 32
fdouble_addsub r17, r11, r12
}
{
cmpltu r14, r16, r14
fdouble_mul_flags r3, r2, r3
}
.LVL3:
{
add r13, r15, r13
fdouble_pack1 r12, r17, r12
}
{
add r13, r13, r14
fdouble_unpack_max r10, r0, zero
}
fdouble_pack1 r3, r13, r3
fdouble_pack2 r12, r17, zero
fdouble_pack2 r3, r13, r16
...
Welcome any additional ideas, suggestions and completions.
Thanks.
On 8/9/15 09:14, Chen Gang wrote:
On 8/9/15 09:10, Chen Gang wrote:
On 8/9/15 01:23, Chen Gang wrote:
Hello all:
Below is my current idea for all floating point insns. For me, it is not
the precise implementation, even not completely implement -- assume pack
insns can only for packing (u)int32_t when they are used individually:
fsingle_add1; return calc flags, save calc result to env.
fsingle_sub1; return calc flags, save calc result to env.
fsingle_addsub2 ; set has result flag.
fsingle_mul1; skip return value, save calc result to env.
set has result flag.
fsingle_mul2; skipped.
fsingle_pack1 ; skipped.
fsingle_pack1 ; if has result
reset has result flag.
return calc result from env.
else
pack srca
reference from tilegx.md: float(uns)sisf2.
get (u)int32_t a, then (u)int32_to_float32.
For pack srca and srcb, the related demo like below (srca and srcb
are uint64_t):
Oh, sorry, for pack srca (not for pack srca and srcb)
switch (srca 0x3ff) {
/* treat it as uint32_t */
case 0x9e:
return uint32_to_float32(srca 32, FP_STATUS);
/* treat it as int32_t, must be negative number */
case 0x29e:
return int32_to_float32(srca 32 | 0x8000, FP_STATUS);
default:
unimplemented (gen_exception).
}
fdouble_unpack_max: ; skipped.
fdouble_unpack_min: ; skipped.
fdouble_add_flags: ; return calc flags, save calc result to env.
fdouble_sub_flags: ; return calc flags, save calc result to env.
fdouble_addsub: ; set has result flag.
fdouble_mul_flags: ; skip
Re: [Qemu-devel] [Consult] tilegx: About floating point instructions
Oh, it seems a little complex, for a testsuite case, it lets double add
and double mul together! We need save more information for the correct
calculation in pack1.
It is 20020314-1.exe, the related code (I guess it is correct):
...
fdouble_unpack_max r10, r3, zero
.LVL2:
fdouble_unpack_max r15, r2, zero
fdouble_add_flags r12, r0, r1
mul_hu_lu r13, r15, r10
mul_lu_lu r16, r15, r10
mula_hu_lu r13, r10, r15
fdouble_unpack_min r11, r0, r1
{
shlir14, r13, 32
fdouble_unpack_max r17, r0, r1
}
{
mul_hu_hu r15, r15, r10
add r16, r16, r14
}
{
shrui r13, r13, 32
fdouble_addsub r17, r11, r12
}
{
cmpltu r14, r16, r14
fdouble_mul_flags r3, r2, r3
}
.LVL3:
{
add r13, r15, r13
fdouble_pack1 r12, r17, r12
}
{
add r13, r13, r14
fdouble_unpack_max r10, r0, zero
}
fdouble_pack1 r3, r13, r3
fdouble_pack2 r12, r17, zero
fdouble_pack2 r3, r13, r16
...
Welcome any additional ideas, suggestions and completions.
Thanks.
On 8/9/15 09:14, Chen Gang wrote:
On 8/9/15 09:10, Chen Gang wrote:
On 8/9/15 01:23, Chen Gang wrote:
Hello all:
Below is my current idea for all floating point insns. For me, it is not
the precise implementation, even not completely implement -- assume pack
insns can only for packing (u)int32_t when they are used individually:
fsingle_add1; return calc flags, save calc result to env.
fsingle_sub1; return calc flags, save calc result to env.
fsingle_addsub2 ; set has result flag.
fsingle_mul1; skip return value, save calc result to env.
set has result flag.
fsingle_mul2; skipped.
fsingle_pack1 ; skipped.
fsingle_pack1 ; if has result
reset has result flag.
return calc result from env.
else
pack srca
reference from tilegx.md: float(uns)sisf2.
get (u)int32_t a, then (u)int32_to_float32.
For pack srca and srcb, the related demo like below (srca and srcb
are uint64_t):
Oh, sorry, for pack srca (not for pack srca and srcb)
switch (srca 0x3ff) {
/* treat it as uint32_t */
case 0x9e:
return uint32_to_float32(srca 32, FP_STATUS);
/* treat it as int32_t, must be negative number */
case 0x29e:
return int32_to_float32(srca 32 | 0x8000, FP_STATUS);
default:
unimplemented (gen_exception).
}
fdouble_unpack_max: ; skipped.
fdouble_unpack_min: ; skipped.
fdouble_add_flags: ; return calc flags, save calc result to env.
fdouble_sub_flags: ; return calc flags, save calc result to env.
fdouble_addsub: ; set has result flag.
fdouble_mul_flags: ; skip return flags, save calc result to env.
set has result flag.
fdouble_pack1: ; if has result
reset has result flag.
return calc result from env.
else
pack srca and srcb.
reference from tilegx.md: float(uns)sidf2.
get (u)int32_t a, then (u)int32_to_float64.
For pack srca and srcb, the related demo like below (srca and srcb
are uint64_t):
switch (srcb 0x) {
Oh, sorry, should use 0xf instead of 0x.
/* treat it as uint32_t */
case 0x21b00:
return uint32_to_float64(srca 4, FP_STATUS);
/* treat it as int32_t, must be negative number */
case 0xa1b00:
return int32_to_float64(srca 4 | 0x8000, FP_STATUS);
default:
unimplemented (gen_exception).
}
fdouble_pack2: ; skipped.
(fsingle_add1/sub1, fdouble_add/sub_flags can be used individually,
e.g gcc testsuit for complex number).
Next, I shall implement the floating point insns, welcome any related
ideas, suggestions, and completions.
Thanks.
On 8/5/15 22:16, Chen Gang wrote:
On 8/4/15 23:04, Richard Henderson wrote:
On 08/04/2015 06:56 AM, Chen Gang wrote:
On 8/4/15 04:47, Chen Gang wrote:
On 8/4/15 00:40, Richard Henderson wrote:
On 08/01/2015 02:47 AM, Chen Gang wrote:
I am just adding floating point instructions (e.g. fsingle_add1),
but for me, I can not find any details about them (the ISA
documents only give a summary description, but not details), e.g.
The tilegx splits the four/six cycle arithmetic into multiple
black-box instructions. You need only really implement one of the
four, with the rest of them being implemented as nops or moves
Re: [Qemu-devel] [Consult] tilegx: About floating point instructions
Hello all: Below is my current idea for all floating point insns. For me, it is not the precise implementation, even not completely implement -- assume pack insns can only for packing (u)int32_t when they are used individually: fsingle_add1; return calc flags, save calc result to env. fsingle_sub1; return calc flags, save calc result to env. fsingle_addsub2 ; set has result flag. fsingle_mul1; skip return value, save calc result to env. set has result flag. fsingle_mul2; skipped. fsingle_pack1 ; skipped. fsingle_pack1 ; if has result reset has result flag. return calc result from env. else pack srca reference from tilegx.md: float(uns)sisf2. get (u)int32_t a, then (u)int32_to_float32. fdouble_unpack_max: ; skipped. fdouble_unpack_min: ; skipped. fdouble_add_flags: ; return calc flags, save calc result to env. fdouble_sub_flags: ; return calc flags, save calc result to env. fdouble_addsub: ; set has result flag. fdouble_mul_flags: ; skip return flags, save calc result to env. set has result flag. fdouble_pack1: ; if has result reset has result flag. return calc result from env. else pack srca and srcb. reference from tilegx.md: float(uns)sidf2. get (u)int32_t a, then (u)int32_to_float64. fdouble_pack2: ; skipped. (fsingle_add1/sub1, fdouble_add/sub_flags can be used individually, e.g gcc testsuit for complex number). Next, I shall implement the floating point insns, welcome any related ideas, suggestions, and completions. Thanks. On 8/5/15 22:16, Chen Gang wrote: On 8/4/15 23:04, Richard Henderson wrote: On 08/04/2015 06:56 AM, Chen Gang wrote: On 8/4/15 04:47, Chen Gang wrote: On 8/4/15 00:40, Richard Henderson wrote: On 08/01/2015 02:47 AM, Chen Gang wrote: I am just adding floating point instructions (e.g. fsingle_add1), but for me, I can not find any details about them (the ISA documents only give a summary description, but not details), e.g. The tilegx splits the four/six cycle arithmetic into multiple black-box instructions. You need only really implement one of the four, with the rest of them being implemented as nops or moves. Looking at what gcc produces gives the hints: fdouble_unpack_minmin, srca, srcb fdouble_unpack_max max, srca, srcb fdouble_add_flagsflg, srca, srcb fdouble_addsub max, min, flg fdouble_pack1 dst, max, flg fdouble_pack2 dst, max, zero The unpack, addsub, and pack2 insns can be ignored, the add_flags insn can perform the whole operation, the pack1 insn performs a move from flg to dst. Similarly for the single-precision: fsingle_add1 tmp, srca, srcb fsingle_addsub2 tmp, srca, srcb fsingle_pack1 flg, tmp fsingle_pack2 dst, tmp, flg The add1 insn performs the whole operation, the addsub2 and pack1 insns are ignored, and the pack2 insn is a move from tmp to dst. After check the tilegx.md completely, for me, we still need implement each of them precisely, or we can not emulate all cases (e.g. muldf3). No, you can still implement all of muldf3 in fdouble_mul_flags. Again, the fdouble_pack1 copies from the flag input to the output. Yes, there is a 64-bit multiply in there, but the tcg optimizer should be able to delete all of that as unused. Especially if you have the fdouble_unpack* insns store zero into their destinations. For me, I am not quite sure. But I guess, what you said should be OK (at least, what you said is very useful for the implementation). Don't get me wrong -- more accurate implementation of the actual insns would be nice, especially for debugging. But if the insns aren't accurately documented I don't see what choice we have. For me, I guess, we can still try to implement the details. - The document has all floating point instructions' summary, so we can think of, or guess its implementation entirely. - gcc uses them all and completely, so it is our good sample and good reference (but we should not assume gcc must be correct, since we just use qemu for gcc testsuite). - Tilegx floating point format should be standard (at least, reference to the standard format), so we can reference the related information from google/baidu. On the good side, implementing the entire operation as part of the flags step probably results in faster emulation. I guess so, too. I shall try to finish the simple implementation, firstly. Then try to implement the floating point instructions
Re: [Qemu-devel] [Consult] tilegx: About floating point instructions
On 8/9/15 01:23, Chen Gang wrote:
Hello all:
Below is my current idea for all floating point insns. For me, it is not
the precise implementation, even not completely implement -- assume pack
insns can only for packing (u)int32_t when they are used individually:
fsingle_add1; return calc flags, save calc result to env.
fsingle_sub1; return calc flags, save calc result to env.
fsingle_addsub2 ; set has result flag.
fsingle_mul1; skip return value, save calc result to env.
set has result flag.
fsingle_mul2; skipped.
fsingle_pack1 ; skipped.
fsingle_pack1 ; if has result
reset has result flag.
return calc result from env.
else
pack srca
reference from tilegx.md: float(uns)sisf2.
get (u)int32_t a, then (u)int32_to_float32.
For pack srca and srcb, the related demo like below (srca and srcb
are uint64_t):
switch (srca 0x3ff) {
/* treat it as uint32_t */
case 0x9e:
return uint32_to_float32(srca 32, FP_STATUS);
/* treat it as int32_t, must be negative number */
case 0x29e:
return int32_to_float32(srca 32 | 0x8000, FP_STATUS);
default:
unimplemented (gen_exception).
}
fdouble_unpack_max: ; skipped.
fdouble_unpack_min: ; skipped.
fdouble_add_flags: ; return calc flags, save calc result to env.
fdouble_sub_flags: ; return calc flags, save calc result to env.
fdouble_addsub: ; set has result flag.
fdouble_mul_flags: ; skip return flags, save calc result to env.
set has result flag.
fdouble_pack1: ; if has result
reset has result flag.
return calc result from env.
else
pack srca and srcb.
reference from tilegx.md: float(uns)sidf2.
get (u)int32_t a, then (u)int32_to_float64.
For pack srca and srcb, the related demo like below (srca and srcb
are uint64_t):
switch (srcb 0x) {
/* treat it as uint32_t */
case 0x21b00:
return uint32_to_float64(srca 4, FP_STATUS);
/* treat it as int32_t, must be negative number */
case 0xa1b00:
return int32_to_float64(srca 4 | 0x8000, FP_STATUS);
default:
unimplemented (gen_exception).
}
fdouble_pack2: ; skipped.
(fsingle_add1/sub1, fdouble_add/sub_flags can be used individually,
e.g gcc testsuit for complex number).
Next, I shall implement the floating point insns, welcome any related
ideas, suggestions, and completions.
Thanks.
On 8/5/15 22:16, Chen Gang wrote:
On 8/4/15 23:04, Richard Henderson wrote:
On 08/04/2015 06:56 AM, Chen Gang wrote:
On 8/4/15 04:47, Chen Gang wrote:
On 8/4/15 00:40, Richard Henderson wrote:
On 08/01/2015 02:47 AM, Chen Gang wrote:
I am just adding floating point instructions (e.g. fsingle_add1),
but for me, I can not find any details about them (the ISA
documents only give a summary description, but not details), e.g.
The tilegx splits the four/six cycle arithmetic into multiple
black-box instructions. You need only really implement one of the
four, with the rest of them being implemented as nops or moves.
Looking at what gcc produces gives the hints:
fdouble_unpack_min min, srca, srcb fdouble_unpack_max max,
srca,
srcb fdouble_add_flags flg, srca, srcb fdouble_addsub max,
min, flg
fdouble_pack1dst, max, flg fdouble_pack2 dst,
max, zero
The unpack, addsub, and pack2 insns can be ignored, the add_flags
insn can perform the whole operation, the pack1 insn performs a move
from flg to dst.
Similarly for the single-precision:
fsingle_add1 tmp, srca, srcb fsingle_addsub2 tmp,
srca, srcb
fsingle_pack1flg, tmp fsingle_pack2 dst, tmp, flg
The add1 insn performs the whole operation, the addsub2 and pack1
insns are ignored, and the pack2 insn is a move from tmp to dst.
After check the tilegx.md completely, for me, we still need implement
each of them precisely, or we can not emulate all cases (e.g. muldf3).
No, you can still implement all of muldf3 in fdouble_mul_flags.
Again, the fdouble_pack1 copies from the flag input to the output.
Yes, there is a 64-bit multiply in there, but the tcg optimizer
should be able to delete all of that as unused. Especially if you have the
fdouble_unpack* insns store zero into their destinations.
For me, I am not quite sure. But I guess, what you said should be OK (at
least, what you said is very useful for the implementation).
Don't get me wrong -- more accurate implementation of the actual
insns would
Re: [Qemu-devel] [Consult] tilegx: About floating point instructions
On 8/9/15 09:10, Chen Gang wrote:
On 8/9/15 01:23, Chen Gang wrote:
Hello all:
Below is my current idea for all floating point insns. For me, it is not
the precise implementation, even not completely implement -- assume pack
insns can only for packing (u)int32_t when they are used individually:
fsingle_add1; return calc flags, save calc result to env.
fsingle_sub1; return calc flags, save calc result to env.
fsingle_addsub2 ; set has result flag.
fsingle_mul1; skip return value, save calc result to env.
set has result flag.
fsingle_mul2; skipped.
fsingle_pack1 ; skipped.
fsingle_pack1 ; if has result
reset has result flag.
return calc result from env.
else
pack srca
reference from tilegx.md: float(uns)sisf2.
get (u)int32_t a, then (u)int32_to_float32.
For pack srca and srcb, the related demo like below (srca and srcb
are uint64_t):
Oh, sorry, for pack srca (not for pack srca and srcb)
switch (srca 0x3ff) {
/* treat it as uint32_t */
case 0x9e:
return uint32_to_float32(srca 32, FP_STATUS);
/* treat it as int32_t, must be negative number */
case 0x29e:
return int32_to_float32(srca 32 | 0x8000, FP_STATUS);
default:
unimplemented (gen_exception).
}
fdouble_unpack_max: ; skipped.
fdouble_unpack_min: ; skipped.
fdouble_add_flags: ; return calc flags, save calc result to env.
fdouble_sub_flags: ; return calc flags, save calc result to env.
fdouble_addsub: ; set has result flag.
fdouble_mul_flags: ; skip return flags, save calc result to env.
set has result flag.
fdouble_pack1: ; if has result
reset has result flag.
return calc result from env.
else
pack srca and srcb.
reference from tilegx.md: float(uns)sidf2.
get (u)int32_t a, then (u)int32_to_float64.
For pack srca and srcb, the related demo like below (srca and srcb
are uint64_t):
switch (srcb 0x) {
Oh, sorry, should use 0xf instead of 0x.
/* treat it as uint32_t */
case 0x21b00:
return uint32_to_float64(srca 4, FP_STATUS);
/* treat it as int32_t, must be negative number */
case 0xa1b00:
return int32_to_float64(srca 4 | 0x8000, FP_STATUS);
default:
unimplemented (gen_exception).
}
fdouble_pack2: ; skipped.
(fsingle_add1/sub1, fdouble_add/sub_flags can be used individually,
e.g gcc testsuit for complex number).
Next, I shall implement the floating point insns, welcome any related
ideas, suggestions, and completions.
Thanks.
On 8/5/15 22:16, Chen Gang wrote:
On 8/4/15 23:04, Richard Henderson wrote:
On 08/04/2015 06:56 AM, Chen Gang wrote:
On 8/4/15 04:47, Chen Gang wrote:
On 8/4/15 00:40, Richard Henderson wrote:
On 08/01/2015 02:47 AM, Chen Gang wrote:
I am just adding floating point instructions (e.g. fsingle_add1),
but for me, I can not find any details about them (the ISA
documents only give a summary description, but not details), e.g.
The tilegx splits the four/six cycle arithmetic into multiple
black-box instructions. You need only really implement one of the
four, with the rest of them being implemented as nops or moves.
Looking at what gcc produces gives the hints:
fdouble_unpack_min min, srca, srcb fdouble_unpack_max max,
srca,
srcb fdouble_add_flags flg, srca, srcb fdouble_addsub max,
min, flg
fdouble_pack1 dst, max, flg fdouble_pack2 dst,
max, zero
The unpack, addsub, and pack2 insns can be ignored, the add_flags
insn can perform the whole operation, the pack1 insn performs a move
from flg to dst.
Similarly for the single-precision:
fsingle_add1tmp, srca, srcb fsingle_addsub2 tmp,
srca, srcb
fsingle_pack1 flg, tmp fsingle_pack2 dst, tmp, flg
The add1 insn performs the whole operation, the addsub2 and pack1
insns are ignored, and the pack2 insn is a move from tmp to dst.
After check the tilegx.md completely, for me, we still need implement
each of them precisely, or we can not emulate all cases (e.g. muldf3).
No, you can still implement all of muldf3 in fdouble_mul_flags.
Again, the fdouble_pack1 copies from the flag input to the output.
Yes, there is a 64-bit multiply in there, but the tcg optimizer
should be able to delete all of that as unused. Especially if you have the
fdouble_unpack* insns store zero into their destinations.
For me, I am not quite sure. But I guess, what you said should be OK
Re: [Qemu-devel] [Consult] tilegx: About floating point instructions
On 8/4/15 23:04, Richard Henderson wrote: On 08/04/2015 06:56 AM, Chen Gang wrote: On 8/4/15 04:47, Chen Gang wrote: On 8/4/15 00:40, Richard Henderson wrote: On 08/01/2015 02:47 AM, Chen Gang wrote: I am just adding floating point instructions (e.g. fsingle_add1), but for me, I can not find any details about them (the ISA documents only give a summary description, but not details), e.g. The tilegx splits the four/six cycle arithmetic into multiple black-box instructions. You need only really implement one of the four, with the rest of them being implemented as nops or moves. Looking at what gcc produces gives the hints: fdouble_unpack_min min, srca, srcb fdouble_unpack_max max, srca, srcb fdouble_add_flags flg, srca, srcb fdouble_addsub max, min, flg fdouble_pack1 dst, max, flg fdouble_pack2 dst, max, zero The unpack, addsub, and pack2 insns can be ignored, the add_flags insn can perform the whole operation, the pack1 insn performs a move from flg to dst. Similarly for the single-precision: fsingle_add1 tmp, srca, srcb fsingle_addsub2 tmp, srca, srcb fsingle_pack1 flg, tmp fsingle_pack2 dst, tmp, flg The add1 insn performs the whole operation, the addsub2 and pack1 insns are ignored, and the pack2 insn is a move from tmp to dst. After check the tilegx.md completely, for me, we still need implement each of them precisely, or we can not emulate all cases (e.g. muldf3). No, you can still implement all of muldf3 in fdouble_mul_flags. Again, the fdouble_pack1 copies from the flag input to the output. Yes, there is a 64-bit multiply in there, but the tcg optimizer should be able to delete all of that as unused. Especially if you have the fdouble_unpack* insns store zero into their destinations. For me, I am not quite sure. But I guess, what you said should be OK (at least, what you said is very useful for the implementation). Don't get me wrong -- more accurate implementation of the actual insns would be nice, especially for debugging. But if the insns aren't accurately documented I don't see what choice we have. For me, I guess, we can still try to implement the details. - The document has all floating point instructions' summary, so we can think of, or guess its implementation entirely. - gcc uses them all and completely, so it is our good sample and good reference (but we should not assume gcc must be correct, since we just use qemu for gcc testsuite). - Tilegx floating point format should be standard (at least, reference to the standard format), so we can reference the related information from google/baidu. On the good side, implementing the entire operation as part of the flags step probably results in faster emulation. I guess so, too. I shall try to finish the simple implementation, firstly. Then try to implement the floating point instructions in details in the future (it should be lower priority). Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [Consult] tilegx: About floating point instructions
On 8/4/15 04:47, Chen Gang wrote: On 8/4/15 00:40, Richard Henderson wrote: On 08/01/2015 02:47 AM, Chen Gang wrote: I am just adding floating point instructions (e.g. fsingle_add1), but for me, I can not find any details about them (the ISA documents only give a summary description, but not details), e.g. The tilegx splits the four/six cycle arithmetic into multiple black-box instructions. You need only really implement one of the four, with the rest of them being implemented as nops or moves. Looking at what gcc produces gives the hints: fdouble_unpack_min min, srca, srcb fdouble_unpack_max max, srca, srcb fdouble_add_flags flg, srca, srcb fdouble_addsub max, min, flg fdouble_pack1dst, max, flg fdouble_pack2 dst, max, zero The unpack, addsub, and pack2 insns can be ignored, the add_flags insn can perform the whole operation, the pack1 insn performs a move from flg to dst. Similarly for the single-precision: fsingle_add1 tmp, srca, srcb fsingle_addsub2 tmp, srca, srcb fsingle_pack1flg, tmp fsingle_pack2 dst, tmp, flg The add1 insn performs the whole operation, the addsub2 and pack1 insns are ignored, and the pack2 insn is a move from tmp to dst. After check the tilegx.md completely, for me, we still need implement each of them precisely, or we can not emulate all cases (e.g. muldf3). But it doesn't matter. Based on tilegx.md, the summary contents in ISA document, and your explanation, I guess, it is enough for me to finish them. :-) And still welcome additional information for it. Thanks. Thank you very much. I am just analyzing the template file (tilegx.md) and testsuite executable file (2603-1.exe) for it. Your information is really valuable to me! :-) And still welcome any additional information for it: especially related details documentations which should be more 'standard' than the third- party's implementation (e.g. gcc implementation). I shall try to let qemu tilegx support gcc testsuite successfully within this month. Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
