from:"Hesham Almatary"

[PATCH 2/2] tests: acpi: Fixup for tables in Arm HMAT series

2022-11-01 Thread Hesham Almatary via

Updates to issues with earlier patches in the pull request:
tests: virt: Update expected *.acpihmatvirt tables

Signed-off-by: Hesham Almatary 
---
 tests/data/acpi/virt/APIC.acpihmatvirt | Bin 396 -> 412 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/tests/data/acpi/virt/APIC.acpihmatvirt 
b/tests/data/acpi/virt/APIC.acpihmatvirt
index 
873e12f67c3838351a3ab4b7a43ee76e7730849a..68200204c6f8f2706c9896dbbccc5ecbec130d26
 100644
GIT binary patch
delta 90
zcmeBSp2N)L7~ttVhmnDSrF$ZmHAesg1WYz$v=)W3!4x-82B?aG5hTM0V!;4+z{GoA
RY#<(Yz+^2(ugL|BG5{#E3(f!l

delta 46
wcmbQk+{4V}7~tvL!^ptEyk;VoHKWf&H!mh`pNZ4J

[PATCH 1/2] tests: q35: acpi: Fixup for tables in noinitiator test.

2022-11-01 Thread Hesham Almatary via

Updates to issues with earlier patches in the pull request:
tests: acpi: q35: update expected blobs *.hmat-noinitiators expected HMAT

Signed-off-by: Hesham Almatary 
---
 tests/data/acpi/q35/DSDT.acpihmat-noinitiator | Bin 8553 -> 8691 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/tests/data/acpi/q35/DSDT.acpihmat-noinitiator 
b/tests/data/acpi/q35/DSDT.acpihmat-noinitiator
index 
c767d11cb1d088f613c49e55a7139cccababf66c..8efa1c5ded52b8a9dfbb6945a3c75cdc6ef9b277
 100644
GIT binary patch
delta 459
zcmaFq^x2uqCD#RZ$>5`k;y-qcGNp@2Dk+K@-A>;o1Dc^Ajr(fkWj#o
zxIk*sD~dnn)%T
zBtevM1b8~TF^KTQ18K&B3=mJCDQvSg%Syh@0>V4kCWkWi35&$L2e@*?dw9C=Iywh<
z8W
z&!9jit^_Wg=thId4~6vW*#d$B9b@!B`amoY*9p#b0&$(;TxSs11P}{$J4M(6oc%%=1nfcHoh&17
F1px9@hSC54

delta 280
zcmezD{L+cbCDCpbBraYu>^TYyWjFW&+m*2x)y!dwCu%uhZIHm&lVDE`V<^02dSfupBOL{4tP
z0_DkB3=1SDXL2zu5S~;!Ie}qv0?&USU|1r^%-9Gb7#4~z5S^UG#a)_8AMER7z!C50
z62!yIAisI1get43KTEuOfGbD5ho=j#qjP|#fq{V;!{nWcR-5n29%bb6V~GLzRKSg8
Q@)~(tb`iD!XTJ~z0E?YeUH||9

-- 
2.25.1

[PATCH v3 7/8] tests: acpi: aarch64/virt: add a test for hmat nodes with no initiators

2022-10-27 Thread Hesham Almatary via

This patch imitates the "tests: acpi: q35: add test for hmat nodes
without initiators" commit to test numa nodes with different HMAT
attributes, but on AArch64/virt.

Tested with:
qemu-system-aarch64 -accel tcg \
-machine virt,hmat=on,gic-version=3  -cpu cortex-a57 \
-bios qemu-efi-aarch64/QEMU_EFI.fd \
-kernel Image -append "root=/dev/vda2 console=ttyAMA0" \
-drive if=virtio,file=aarch64.qcow2,format=qcow2,id=hd \
-device virtio-rng-pci \
-net user,hostfwd=tcp::10022-:22 -net nic \
-device intel-hda -device hda-duplex -nographic \
-smp 4 \
-m 3G \
-object memory-backend-ram,size=1G,id=ram0 \
-object memory-backend-ram,size=1G,id=ram1 \
-object memory-backend-ram,size=1G,id=ram2 \
-numa node,nodeid=0,memdev=ram0,cpus=0-1 \
-numa node,nodeid=1,memdev=ram1,cpus=2-3 \
-numa node,nodeid=2,memdev=ram2 \
-numa
hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,latency=10
 \
-numa 
hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760
 \
-numa 
hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,latency=20
 \
-numa 
hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880
 \
-numa 
hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,latency=30
 \
-numa 
hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
 \
-numa 
hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,latency=20
 \
-numa 
hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880
 \
-numa 
hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,latency=10
 \
-numa 
hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760
 \
-numa 
hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,latency=30
 \
-numa 
hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576

Signed-off-by: Hesham Almatary 
---
 tests/qtest/bios-tables-test.c | 59 ++
 1 file changed, 59 insertions(+)

diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 02fe59fbf8..e805b3efec 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1461,6 +1461,63 @@ static void test_acpi_piix4_tcg_acpi_hmat(void)
 test_acpi_tcg_acpi_hmat(MACHINE_PC);
 }
 
+static void test_acpi_virt_tcg_acpi_hmat(void)
+{
+test_data data = {
+.machine = "virt",
+.tcg_only = true,
+.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
+.uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
+.cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2",
+.ram_start = 0x4000ULL,
+.scan_len = 128ULL * 1024 * 1024,
+};
+
+data.variant = ".acpihmatvirt";
+
+test_acpi_one(" -machine hmat=on"
+  " -cpu cortex-a57"
+  " -smp 4,sockets=2"
+  " -m 256M"
+  " -object memory-backend-ram,size=64M,id=ram0"
+  " -object memory-backend-ram,size=64M,id=ram1"
+  " -object memory-backend-ram,size=128M,id=ram2"
+  " -numa node,nodeid=0,memdev=ram0"
+  " -numa node,nodeid=1,memdev=ram1"
+  " -numa node,nodeid=2,memdev=ram2"
+  " -numa cpu,node-id=0,socket-id=0"
+  " -numa cpu,node-id=0,socket-id=0"
+  " -numa cpu,node-id=1,socket-id=1"
+  " -numa cpu,node-id=1,socket-id=1"
+  " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
+  "data-type=access-latency,latency=10"
+  " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=10485760"
+  " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
+  "data-type=access-latency,latency=20"
+  " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=5242880"
+  " -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
+  "data-type=access-latency,latency=30"
+  " -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=1048576"
+  " -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
+  "data-type=access-latency,latency=20"
+  " -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
+  "d

[PATCH v3 5/8] tests: Add HMAT AArch64/virt empty table files

2022-10-27 Thread Hesham Almatary via

Signed-off-by: Hesham Almatary 
---
 tests/data/acpi/virt/APIC.acpihmatvirt  | 0
 tests/data/acpi/virt/DSDT.acpihmatvirt  | 0
 tests/data/acpi/virt/HMAT.acpihmatvirt  | 0
 tests/data/acpi/virt/PPTT.acpihmatvirt  | 0
 tests/data/acpi/virt/SRAT.acpihmatvirt  | 0
 tests/qtest/bios-tables-test-allowed-diff.h | 5 +
 6 files changed, 5 insertions(+)
 create mode 100644 tests/data/acpi/virt/APIC.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/DSDT.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/HMAT.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/PPTT.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/SRAT.acpihmatvirt

diff --git a/tests/data/acpi/virt/APIC.acpihmatvirt 
b/tests/data/acpi/virt/APIC.acpihmatvirt
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/data/acpi/virt/DSDT.acpihmatvirt 
b/tests/data/acpi/virt/DSDT.acpihmatvirt
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/data/acpi/virt/HMAT.acpihmatvirt 
b/tests/data/acpi/virt/HMAT.acpihmatvirt
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/data/acpi/virt/PPTT.acpihmatvirt 
b/tests/data/acpi/virt/PPTT.acpihmatvirt
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/data/acpi/virt/SRAT.acpihmatvirt 
b/tests/data/acpi/virt/SRAT.acpihmatvirt
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..4f849715bd 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,6 @@
 /* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/virt/APIC.acpihmatvirt",
+"tests/data/acpi/virt/DSDT.acpihmatvirt",
+"tests/data/acpi/virt/HMAT.acpihmatvirt",
+"tests/data/acpi/virt/PPTT.acpihmatvirt",
+"tests/data/acpi/virt/SRAT.acpihmatvirt",
-- 
2.25.1

[PATCH v3 2/8] tests: acpi: add and whitelist *.hmat-noinitiator expected blobs

2022-10-27 Thread Hesham Almatary via

From: Brice Goglin 

.. which will be used by follow up hmat-noinitiator test-case.

Signed-off-by: Brice Goglin 
Signed-off-by: Hesham Almatary 
---
 tests/data/acpi/q35/APIC.acpihmat-noinitiator | 0
 tests/data/acpi/q35/DSDT.acpihmat-noinitiator | 0
 tests/data/acpi/q35/HMAT.acpihmat-noinitiator | 0
 tests/data/acpi/q35/SRAT.acpihmat-noinitiator | 0
 tests/qtest/bios-tables-test-allowed-diff.h   | 4 
 5 files changed, 4 insertions(+)
 create mode 100644 tests/data/acpi/q35/APIC.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/q35/DSDT.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/q35/HMAT.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/q35/SRAT.acpihmat-noinitiator

diff --git a/tests/data/acpi/q35/APIC.acpihmat-noinitiator 
b/tests/data/acpi/q35/APIC.acpihmat-noinitiator
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/data/acpi/q35/DSDT.acpihmat-noinitiator 
b/tests/data/acpi/q35/DSDT.acpihmat-noinitiator
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/data/acpi/q35/HMAT.acpihmat-noinitiator 
b/tests/data/acpi/q35/HMAT.acpihmat-noinitiator
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/data/acpi/q35/SRAT.acpihmat-noinitiator 
b/tests/data/acpi/q35/SRAT.acpihmat-noinitiator
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..245fa66bcc 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,5 @@
 /* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/APIC.acpihmat-noinitiator",
+"tests/data/acpi/q35/DSDT.acpihmat-noinitiator",
+"tests/data/acpi/q35/HMAT.acpihmat-noinitiator",
+"tests/data/acpi/q35/SRAT.acpihmat-noinitiator",
-- 
2.25.1

[PATCH v3 4/8] tests: acpi: q35: update expected blobs *.hmat-noinitiators expected HMAT:

2022-10-27 Thread Hesham Almatary via

 Entry : 0005
[11Ch 0284   2]Entry : 000A
[11Eh 0286   2]Entry : 0001

Raw Table Data: Length 288 (0x120)

: 48 4D 41 54 20 01 00 00 02 4F 42 4F 43 48 53 20  // HMAT OBOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43  // BXPCBXPC
0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00  // (...
0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // 
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // 
0050: 00 00 00 00 28 00 00 00 01 00 00 00 01 00 00 00  // (...
0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // 
0070: 00 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00  // (...
0080: 00 00 00 00 80 00 00 00 02 00 00 00 00 00 00 00  // 
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // 
00A0: 01 00 00 00 40 00 00 00 00 00 00 00 02 00 00 00  // @...
00B0: 03 00 00 00 00 00 00 00 10 27 00 00 00 00 00 00  // .'..
00C0: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00  // 
00D0: 02 00 00 00 01 00 02 00 03 00 02 00 01 00 03 00  // 
00E0: 01 00 00 00 40 00 00 00 00 03 00 00 02 00 00 00  // @...
00F0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00  // 
0100: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00  // 
0110: 02 00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00  // 

Signed-off-by: Brice Goglin 
Signed-off-by: Hesham Almatary 
---
 tests/data/acpi/q35/APIC.acpihmat-noinitiator | Bin 0 -> 144 bytes
 tests/data/acpi/q35/DSDT.acpihmat-noinitiator | Bin 0 -> 8553 bytes
 tests/data/acpi/q35/HMAT.acpihmat-noinitiator | Bin 0 -> 288 bytes
 tests/data/acpi/q35/SRAT.acpihmat-noinitiator | Bin 0 -> 312 bytes
 tests/qtest/bios-tables-test-allowed-diff.h   |   4 
 5 files changed, 4 deletions(-)

diff --git a/tests/data/acpi/q35/APIC.acpihmat-noinitiator 
b/tests/data/acpi/q35/APIC.acpihmat-noinitiator
index 
e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..d904d4a70ddecbb79a83a267af8e26f925e9f4c6
 100644
GIT binary patch
literal 144
zcmZ<^@N}NQz`(%h?d0$55v<@85#X!<1dKp25F11@Fg*ANra6G>KwJ(+MhMNs1fiLk
tK{O)|Nb|r~o3y%?)O;u>A)b0RWi;3;_TD

literal 0
HcmV?d1

diff --git a/tests/data/acpi/q35/DSDT.acpihmat-noinitiator 
b/tests/data/acpi/q35/DSDT.acpihmat-noinitiator
index 
e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..c767d11cb1d088f613c49e55a7139cccababf66c
 100644
GIT binary patch
literal 8553
zcmb7JOKcm*8J^`sS}m8-lA^$0{LCIadERkMusn`Jpkg}Xsa#CcG
z#6TVhAj?4F_)s)q67)z13ea17>a_-XX>YzYKu;$gY0nd~tOIw46@kU+2F&
zd-_*jUVf)|@0b7l^_|zP1OTh}HSv2sq_5rwJ?l(w;C$BKGd?6bKesYi{H)JUi#CVO
zggt7xYl|jIwQ~4+=inu;RdjhD(|*%0xP=w;%WVajv)1X4ml?BZaOm^r;c)m@ambwa
znA0$Y%CcGW%WbLBfHqRq*{}KS2D2Hv|1iZ8otqBDi?5WMUfyqc-F)taZqP2WkXm{n
zHEqA&vz*?*{?=OI4%Cddx7Y
z#x-^gzvp5|-#K`yacOhJT3FOrrjbzjgZa7)e2M&7S`SMnXB
zwC=94+|#~Wz8LE~Nzrf^?h+z=&)8#>qw_;*K4iIPir`E`QLd1_dJ(pl^JaW6Xv`1R
zqkG~0i~smf@cjFYPnW-KocNpD2r1VazwHg4>|bYt6a76ahAICcpEx$=>5v^};>Jz-
zVt1DZOa1HCY?w{PSek8zz1!Q29d4U`-L0^k-NmmF?o#CZ?p1?kk>h^L?_9st_Ookm
z?`Km9Oh>lfTq`qiY~Z-UvNp9_F$7f^#1Yh3Hl08}aO((M6cG!+d2x>O0F@yzk)LB@
zoC$0c5mQ2Aj57h{OoYTlZ#Xv2nX(6QMobBf3nrkPiIAAG3T`BU<#`gEDWM6$l$}SY
z>P%`nlbk7`Nx_tzN2uzY(R9vmri9MuIuWWmXEmL(n$B5WCqh-Hsp&K|ou;l6p{f&)
z9A%{EG@Wz0PK2sXOVep-IxSr%LRDu<)0xtArgWVMRh@YBDc951blSR3gsRT8rZcVS
zOzS!ksygR2o%5Q`d0i($Rp)}Hb3xO&pzB1a>U1=nj;7Pmbs|)CW;C4{O=m{eiBQ#<
z)pTYxompKcLRIIYrgKr#xv1+zsOrpVI&+%NoURk0s&h%xxuoe_(sd$Kbsp1n9@BIl
z({&h_lvrj&UmNlKrx=w_u&f}WS`n-#`zR!)
z7hz9o%##}Pq|QXBGEZsDQyTM>&P1p(PixH68uPTyM5r>K(3nqX%qMgvLX~-jGo{O%
z;Y|6AKO>m(!HtlZ@(P~SYM#|`0y;8Kgy@YlP=Spis;L^NfQ}3lA$r8I
zFi?SwqDUi$l7R}S3{{;lP?451VW0|>3>2YsMKVx?QYQ>lU^x>8szAv=1(eq$14Srx
z!axOlU^x>8szAv=1(Y+%KoLrvFi?TzOcu
z&LjgxD0RX>1(q{mpbC@>R6seC3>2Z%2?G^a&V+#~P%=;f=3{*fllMEE0)CmI>Sk8oj
zDo`>|0p(0GP=rz^3{+q_69%e4$v_2^Gs!>^N}VuJf#pmXr~)Me6;RG314Srx!axO<
zGhv_#lnhirIg<<&q0|Wj6M_lrzad5lWpf
zP=V!47^ngz0~JutBm+e#b;3XqDF%v2HBf}Afg)54RAItE6($*|!XyJ#m@rU<2?JG_
zWS|O@3{+vlKouqoRAG{VDoip^g$V;ym@rU1;Px-d{gxMF-T$v_d}
zGRTmaa%^Fsh~(J9KoQBYB?Cn$$CeBfA=ZXYc447xVE6f-)kFG2dUu9?ik+K3e=bh{
zQfaA!mNyK)wNZrQZj|WDr7zE9SZvuS({Y8qs`OPebBpy2tOg9`KCt$8v8pn6Xr*!&
z>Kkrr4uDo6GjF9nnPGE$>E}ImhuW+pzU$!!yVe4uBXpvLrIz(sydxCll824;8Cv}@
z(d{5}%v$_pp3TMKZVbVJjUA?4KFY)Rn^iQo`%1y6c>KrskyI4EJ`d*~niakbo
zS1IrE^6pr9_lWXtRNfmCZ(%{}d#m@9@*Xemjg|L~DDOq(%j4w}k5Rs?lrQu0<+1YR
zBg&Vf@|E%O$;T*PQOZ|%`N~-N$`R!&QTgh4`I*NkUscLidHL#C`RWnnt5Nydc=_4K
zC|^^`*LeBbSozu!YH+~yi89g1|
zH73%DwyEhR?#ry64lf`R=|tPqbQAX(mVoI#lfv*;GLcTSO-(m(-{kakcvYE5C)%c_
zo45~_^mKTCnMfzvrly;i*T?j9c&V94C)%c_o0zA|dOE!6Or#TSdOGKnvc|scf+0>HHfTy9YOaL_v||UBBEk+uZO-Tq8-!AFq%xo(dVJ=Fe4+xq;g>kC0)y
z&GO}JY#6eg(

[PATCH v3 8/8] tests: virt: Update expected *.acpihmatvirt tables

2022-10-27 Thread Hesham Almatary via

h 0218   2]Entry : 0002
[0DCh 0220   2]Entry : 0001
[0DEh 0222   2]Entry : 0003

[0E0h 0224   2]   Structure Type : 0001 [System Locality
Latency and Bandwidth Information]
[0E2h 0226   2] Reserved : 
[0E4h 0228   4]   Length : 0040
[0E8h 0232   1]Flags (decoded below) : 00
Memory Hierarchy : 0
[0E9h 0233   1]Data Type : 03
[0EAh 0234   2]Reserved1 : 
[0ECh 0236   4] Initiator Proximity Domains # : 0002
[0F0h 0240   4]   Target Proximity Domains # : 0003
[0F4h 0244   4]Reserved2 : 
[0F8h 0248   8]  Entry Base Unit : 0001
[100h 0256   4] Initiator Proximity Domain List : 
[104h 0260   4] Initiator Proximity Domain List : 0001
[108h 0264   4] Target Proximity Domain List : 
[10Ch 0268   4] Target Proximity Domain List : 0001
[110h 0272   4] Target Proximity Domain List : 0002
[114h 0276   2]Entry : 000A
[116h 0278   2]Entry : 0005
[118h 0280   2]Entry : 0001
[11Ah 0282   2]Entry : 0005
[11Ch 0284   2]Entry : 000A
[11Eh 0286   2]Entry : 0001

Raw Table Data: Length 288 (0x120)

: 48 4D 41 54 20 01 00 00 02 4F 42 4F 43 48 53 20  // HMAT
OBOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43  // BXPC
BXPC
0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00  //
(...
0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  //

0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  //

0050: 00 00 00 00 28 00 00 00 01 00 00 00 01 00 00 00  //
(...
0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  //

0070: 00 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00  //
(...
0080: 00 00 00 00 80 00 00 00 02 00 00 00 00 00 00 00  //

0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  //

00A0: 01 00 00 00 40 00 00 00 00 00 00 00 02 00 00 00  //
@...
00B0: 03 00 00 00 00 00 00 00 10 27 00 00 00 00 00 00  //
.'..
00C0: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00  //

00D0: 02 00 00 00 01 00 02 00 03 00 02 00 01 00 03 00  //

00E0: 01 00 00 00 40 00 00 00 00 03 00 00 02 00 00 00  //
@...
00F0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00  //

0100: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00  //

0110: 02 00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00  //
....

Signed-off-by: Hesham Almatary 
---
 tests/data/acpi/virt/APIC.acpihmatvirt  | Bin 0 -> 396 bytes
 tests/data/acpi/virt/DSDT.acpihmatvirt  | Bin 0 -> 5282 bytes
 tests/data/acpi/virt/HMAT.acpihmatvirt  | Bin 0 -> 288 bytes
 tests/data/acpi/virt/PPTT.acpihmatvirt  | Bin 0 -> 196 bytes
 tests/data/acpi/virt/SRAT.acpihmatvirt  | Bin 0 -> 240 bytes
 tests/qtest/bios-tables-test-allowed-diff.h |   5 -
 6 files changed, 5 deletions(-)

diff --git a/tests/data/acpi/virt/APIC.acpihmatvirt 
b/tests/data/acpi/virt/APIC.acpihmatvirt
index 
e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..873e12f67c3838351a3ab4b7a43ee76e7730849a
 100644
GIT binary patch
literal 396
zcmZ<^@O18BWME)kGD%s#!2MfXo894}@W2q?!fN3j!dsn1M71lWP`8
TF9`6$!;uLb4j}U!7y=joChH0T

literal 0
HcmV?d1

diff --git a/tests/data/acpi/virt/DSDT.acpihmatvirt 
b/tests/data/acpi/virt/DSDT.acpihmatvirt
index 
e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..aee6ba017cd730948bfa93e91551eb10a6809293
 100644
GIT binary patch
literal 5282
zcmZvg%WoT16o>EFlh__VVmr?J;S@^6vl`n?la{u`9y^IkoET5iAUTpNArK{-N>oUt
zLJCD*Gs*9?XQYhh%)RHE`;Cv|<7xWM-JeTJ
z#SR)f-lo6Q_^|6O(Pk;7^s#=;f4^ZJ4E)BRe?05CuA3Zewwu|y*KJdS;>pWu{bKsqaRW
zWnH4^F|BBIecxL*;161zJz8y*a{b-9lcr>^ZW%u
zu9+M80>hRVNnl(<#0#5|#QSFy2LmT&Edn9n-+Lg$%h)vl3$#
z7`Krj*J(~-%md>NGUPfPlNgJ@cn=wJo#rLR5-`?~A=ha^V!Q&3Ix^%sElP~bz-S;t
zuG4XeaRnG2FsgE$mL$gOz-S^vuG0yL@g^`@$dK!FQewOfjCEwlbvh+6t^#8N8FHOY
zOAHqno5+ysbVg!Sfzd{WT&J@V;~FsTB15jzIf-!{81ExPuG4vmu?mbWWXN^8ATe$N
zqXUeZT&If?;}$Tsks;Sw=DW&MZS}EQQZD^9>F5jfKz&57N<)IiqubjZ-}>A+DyHr9aHux?wyVss
zMaLCY%;@t@jDl(u#3`t$V%E+KhnCVgG%t*F7ER2Vu^^A8Mxo9melVB1Br`XRbY?V_
zS|EKzni^zMs57Ih#DmOe1#zV_qp5L|NmGMN3Uwx}D7cCpWJW8ngUo0uwM?O9kVzqW
zjxf)WAT#nDF`3cgDMZgv=1EN{ttXmFEf#uGh@J`NnP8p??nxnfCYfiFc~VP;o)n^I
zig{8yZSG!hOH$mELiBW)r^7s{g+osY(KF3F)66r?Jt;)b4D-w|PipzllS1^&GS4jY
z%yLf((KE+9bIg-kMD(N(J;#{m81o$Co)n@d{hTp19#nCjc~VP>o)n^Ifq52~XMuZC
zh@M5}S!ABnf}$sd=sC_j$C>9i_oNU#>E|bSmY65CtmsK0dQLFU3FbM$Jt;)bN#;4p
zJgLP+PYTgx#fK=R#H~KkyoLbw>X~
zRep_j=5}l*oJZegRgC_f(>ByQ>l^xXWvIIdw)}ATpZ-}!+wdxlSQ+X8%tlQMZ9^Kh
z

[PATCH v3 6/8] hw/arm/virt: Enable HMAT on arm virt machine

2022-10-27 Thread Hesham Almatary via

From: Xiang Chen 

Since the patchset ("Build ACPI Heterogeneous Memory Attribute Table (HMAT)"),
HMAT is supported, but only x86 is enabled. Enable HMAT on arm virt machine.

Signed-off-by: Xiang Chen 
Signed-off-by: Hesham Almatary 
Reviewed-by: Igor Mammedov 
---
 hw/arm/Kconfig   | 1 +
 hw/arm/virt-acpi-build.c | 7 +++
 2 files changed, 8 insertions(+)

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 15fa79afd3..17fcde8e1c 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -30,6 +30,7 @@ config ARM_VIRT
 select ACPI_VIOT
 select VIRTIO_MEM_SUPPORTED
 select ACPI_CXL
+select ACPI_HMAT
 
 config CHEETAH
 bool
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 13c6e3e468..7f706f72bb 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -42,6 +42,7 @@
 #include "hw/acpi/memory_hotplug.h"
 #include "hw/acpi/generic_event_device.h"
 #include "hw/acpi/tpm.h"
+#include "hw/acpi/hmat.h"
 #include "hw/pci/pcie_host.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_bus.h"
@@ -989,6 +990,12 @@ void virt_acpi_build(VirtMachineState *vms, 
AcpiBuildTables *tables)
 build_slit(tables_blob, tables->linker, ms, vms->oem_id,
vms->oem_table_id);
 }
+
+if (ms->numa_state->hmat_enabled) {
+acpi_add_table(table_offsets, tables_blob);
+build_hmat(tables_blob, tables->linker, ms->numa_state,
+   vms->oem_id, vms->oem_table_id);
+}
 }
 
 if (ms->nvdimms_state->is_enabled) {
-- 
2.25.1

[PATCH v3 0/8] AArch64/HMAT support and tests

2022-10-27 Thread Hesham Almatary via

This patchset adds support for AArch64/HMAT including a test.
It relies on other two patch sets from:

Brice Goglin: to support -numa without initiators on q35/x86.
  https://lore.kernel.org/all/ed23accb-2c8b-90f4-a7a3-f81cc57bf...@inria.fr/
Xiang Chen: to enable/support HMAT on AArch64.
  
https://lore.kernel.org/all/1643102134-15506-1-git-send-email-chenxian...@hisilicon.com/

I further add a test with ACPI/HMAT tables that uses the two
patch sets.

Changes from v2:
- Rebased and fixed a merge conflict

Changes from v1:
- Generate APIC and PPTT ACPI tables for AArch64/virt
- Avoid using legacy syntax in numa/bios tests
- Delete unchanged FACP tables

Brice Goglin (4):
  hmat acpi: Don't require initiator value in -numa
  tests: acpi: add and whitelist *.hmat-noinitiator expected blobs
  tests: acpi: q35: add test for hmat nodes without initiators
  tests: acpi: q35: update expected blobs *.hmat-noinitiators expected
HMAT:

Hesham Almatary (3):
  tests: Add HMAT AArch64/virt empty table files
  tests: acpi: aarch64/virt: add a test for hmat nodes with no
initiators
  tests: virt: Update expected *.acpihmatvirt tables

Xiang Chen (1):
  hw/arm/virt: Enable HMAT on arm virt machine

 hw/arm/Kconfig|   1 +
 hw/arm/virt-acpi-build.c  |   7 ++
 hw/core/machine.c |   4 +-
 tests/data/acpi/q35/APIC.acpihmat-noinitiator | Bin 0 -> 144 bytes
 tests/data/acpi/q35/DSDT.acpihmat-noinitiator | Bin 0 -> 8553 bytes
 tests/data/acpi/q35/HMAT.acpihmat-noinitiator | Bin 0 -> 288 bytes
 tests/data/acpi/q35/SRAT.acpihmat-noinitiator | Bin 0 -> 312 bytes
 tests/data/acpi/virt/APIC.acpihmatvirt| Bin 0 -> 396 bytes
 tests/data/acpi/virt/DSDT.acpihmatvirt| Bin 0 -> 5282 bytes
 tests/data/acpi/virt/HMAT.acpihmatvirt| Bin 0 -> 288 bytes
 tests/data/acpi/virt/PPTT.acpihmatvirt| Bin 0 -> 196 bytes
 tests/data/acpi/virt/SRAT.acpihmatvirt| Bin 0 -> 240 bytes
 tests/qtest/bios-tables-test.c| 109 ++
 13 files changed, 118 insertions(+), 3 deletions(-)
 create mode 100644 tests/data/acpi/q35/APIC.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/q35/DSDT.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/q35/HMAT.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/q35/SRAT.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/virt/APIC.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/DSDT.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/HMAT.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/PPTT.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/SRAT.acpihmatvirt

-- 
2.25.1

[PATCH v3 3/8] tests: acpi: q35: add test for hmat nodes without initiators

2022-10-27 Thread Hesham Almatary via

 Entry : 0005
[11Ch 0284   2]Entry : 000A
[11Eh 0286   2]Entry : 0001

Raw Table Data: Length 288 (0x120)

: 48 4D 41 54 20 01 00 00 02 4F 42 4F 43 48 53 20  // HMAT OBOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43  // BXPCBXPC
0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00  // (...
0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // 
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // 
0050: 00 00 00 00 28 00 00 00 01 00 00 00 01 00 00 00  // (...
0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // 
0070: 00 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00  // (...
0080: 00 00 00 00 80 00 00 00 02 00 00 00 00 00 00 00  // 
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // 
00A0: 01 00 00 00 40 00 00 00 00 00 00 00 02 00 00 00  // @...
00B0: 03 00 00 00 00 00 00 00 10 27 00 00 00 00 00 00  // .'..
00C0: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00  // 
00D0: 02 00 00 00 01 00 02 00 03 00 02 00 01 00 03 00  // 
00E0: 01 00 00 00 40 00 00 00 00 03 00 00 02 00 00 00  // @...
00F0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00  // 
0100: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00  // 
0110: 02 00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00  // 

Signed-off-by: Brice Goglin 
Signed-off-by: Hesham Almatary 
---
 tests/qtest/bios-tables-test.c | 50 ++
 1 file changed, 50 insertions(+)

diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index e6096e7f73..02fe59fbf8 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1461,6 +1461,54 @@ static void test_acpi_piix4_tcg_acpi_hmat(void)
 test_acpi_tcg_acpi_hmat(MACHINE_PC);
 }
 
+static void test_acpi_q35_tcg_acpi_hmat_noinitiator(void)
+{
+test_data data;
+
+memset(&data, 0, sizeof(data));
+data.machine = MACHINE_Q35;
+data.variant = ".acpihmat-noinitiator";
+test_acpi_one(" -machine hmat=on"
+  " -smp 4,sockets=2"
+  " -m 128M"
+  " -object memory-backend-ram,size=32M,id=ram0"
+  " -object memory-backend-ram,size=32M,id=ram1"
+  " -object memory-backend-ram,size=64M,id=ram2"
+  " -numa node,nodeid=0,memdev=ram0"
+  " -numa node,nodeid=1,memdev=ram1"
+  " -numa node,nodeid=2,memdev=ram2"
+  " -numa cpu,node-id=0,socket-id=0"
+  " -numa cpu,node-id=0,socket-id=0"
+  " -numa cpu,node-id=1,socket-id=1"
+  " -numa cpu,node-id=1,socket-id=1"
+  " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
+  "data-type=access-latency,latency=10"
+  " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=10485760"
+  " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
+  "data-type=access-latency,latency=20"
+  " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=5242880"
+  " -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
+  "data-type=access-latency,latency=30"
+  " -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=1048576"
+  " -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
+  "data-type=access-latency,latency=20"
+  " -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=5242880"
+  " -numa hmat-lb,initiator=1,target=1,hierarchy=memory,"
+  "data-type=access-latency,latency=10"
+  " -numa hmat-lb,initiator=1,target=1,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=10485760"
+  " -numa hmat-lb,initiator=1,target=2,hierarchy=memory,"
+  "data-type=access-latency,latency=30"
+  " -numa hmat-lb,initiator=1,target=2,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=1048576",
+  &am

[PATCH v3 1/8] hmat acpi: Don't require initiator value in -numa

2022-10-27 Thread Hesham Almatary via

Entry : 0002
[0DCh 0220   2]Entry : 0001
[0DEh 0222   2]Entry : 0003

[0E0h 0224   2]   Structure Type : 0001 [System Locality Latency 
and Bandwidth Information]
[0E2h 0226   2] Reserved : 
[0E4h 0228   4]   Length : 0040
[0E8h 0232   1]Flags (decoded below) : 00
Memory Hierarchy : 0
[0E9h 0233   1]Data Type : 03
[0EAh 0234   2]Reserved1 : 
[0ECh 0236   4] Initiator Proximity Domains # : 0002
[0F0h 0240   4]   Target Proximity Domains # : 0003
[0F4h 0244   4]Reserved2 : 
[0F8h 0248   8]  Entry Base Unit : 0001
[100h 0256   4] Initiator Proximity Domain List : 
[104h 0260   4] Initiator Proximity Domain List : 0001
[108h 0264   4] Target Proximity Domain List : 
[10Ch 0268   4] Target Proximity Domain List : 0001
[110h 0272   4] Target Proximity Domain List : 0002
[114h 0276   2]Entry : 000A
[116h 0278   2]Entry : 0005
[118h 0280   2]Entry : 0001
[11Ah 0282   2]Entry : 0005
[11Ch 0284   2]Entry : 000A
[11Eh 0286   2]Entry : 0001

Signed-off-by: Brice Goglin 
Signed-off-by: Hesham Almatary 
Reviewed-by: Jingqi Liu 
---
 hw/core/machine.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/hw/core/machine.c b/hw/core/machine.c
index aa520e74a8..e686bb48a0 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -1176,9 +1176,7 @@ static void numa_validate_initiator(NumaState *numa_state)
 
 for (i = 0; i < numa_state->num_nodes; i++) {
 if (numa_info[i].initiator == MAX_NODES) {
-error_report("The initiator of NUMA node %d is missing, use "
- "'-numa node,initiator' option to declare it", i);
-exit(1);
+continue;
 }
 
 if (!numa_info[numa_info[i].initiator].present) {
-- 
2.25.1

Re: [PATCH v2 0/8] AArch64/HMAT support and tests

2022-09-26 Thread Hesham Almatary via


Hello Michael,

On 7/26/2022 4:04 PM, Michael S. Tsirkin wrote:

On Tue, Jul 19, 2022 at 10:49:42AM +0100, Hesham Almatary wrote:

This patchset adds support for AArch64/HMAT including a test.
It relies on other two patch sets from:

Brice Goglin: to support -numa without initiators on q35/x86.
   https://lore.kernel.org/all/ed23accb-2c8b-90f4-a7a3-f81cc57bf...@inria.fr/
Xiang Chen: to enable/support HMAT on AArch64.
   
https://lore.kernel.org/all/1643102134-15506-1-git-send-email-chenxian...@hisilicon.com/

Thanks!
I think it's best to merge this all after the release.
I've tagged this but please ping me after the release
just to make sure. Thanks everyone!

Ping

I further add a test with ACPI/HMAT tables that uses the two
patch sets.

Changes from v1:
- Generate APIC and PPTT ACPI tables for AArch64/virt
- Avoid using legacy syntax in numa/bios tests
- Delete unchanged FACP tables

Brice Goglin (4):
   hmat acpi: Don't require initiator value in -numa
   tests: acpi: add and whitelist *.hmat-noinitiator expected blobs
   tests: acpi: q35: add test for hmat nodes without initiators
   tests: acpi: q35: update expected blobs *.hmat-noinitiators expected
     HMAT:

Hesham Almatary (3):
   tests: Add HMAT AArch64/virt empty table files
   tests: acpi: aarch64/virt: add a test for hmat nodes with no initiators
   tests: virt: Update expected *.acpihmatvirt tables

Xiang Chen (1):
   hw/arm/virt: Enable HMAT on arm virt machine

  hw/arm/Kconfig|   1 +
  hw/arm/virt-acpi-build.c  |   7 ++
  hw/core/machine.c |   4 +-
  tests/data/acpi/q35/APIC.acpihmat-noinitiator | Bin 0 -> 144 bytes
  tests/data/acpi/q35/DSDT.acpihmat-noinitiator | Bin 0 -> 8553 bytes
  tests/data/acpi/q35/HMAT.acpihmat-noinitiator | Bin 0 -> 288 bytes
  tests/data/acpi/q35/SRAT.acpihmat-noinitiator | Bin 0 -> 312 bytes
  tests/data/acpi/virt/APIC.acpihmatvirt| Bin 0 -> 396 bytes
  tests/data/acpi/virt/DSDT.acpihmatvirt| Bin 0 -> 5282 bytes
  tests/data/acpi/virt/HMAT.acpihmatvirt| Bin 0 -> 288 bytes
  tests/data/acpi/virt/PPTT.acpihmatvirt| Bin 0 -> 196 bytes
  tests/data/acpi/virt/SRAT.acpihmatvirt| Bin 0 -> 240 bytes
  tests/qtest/bios-tables-test.c| 109 ++
  13 files changed, 118 insertions(+), 3 deletions(-)
  create mode 100644 tests/data/acpi/q35/APIC.acpihmat-noinitiator
  create mode 100644 tests/data/acpi/q35/DSDT.acpihmat-noinitiator
  create mode 100644 tests/data/acpi/q35/HMAT.acpihmat-noinitiator
  create mode 100644 tests/data/acpi/q35/SRAT.acpihmat-noinitiator
  create mode 100644 tests/data/acpi/virt/APIC.acpihmatvirt
  create mode 100644 tests/data/acpi/virt/DSDT.acpihmatvirt
  create mode 100644 tests/data/acpi/virt/HMAT.acpihmatvirt
  create mode 100644 tests/data/acpi/virt/PPTT.acpihmatvirt
  create mode 100644 tests/data/acpi/virt/SRAT.acpihmatvirt

--
2.25.1

Re: [PATCH v2 0/8] AArch64/HMAT support and tests

2022-09-02 Thread Hesham Almatary via


Hello Michael,

On 7/26/2022 4:04 PM, Michael S. Tsirkin wrote:

On Tue, Jul 19, 2022 at 10:49:42AM +0100, Hesham Almatary wrote:

This patchset adds support for AArch64/HMAT including a test.
It relies on other two patch sets from:

Brice Goglin: to support -numa without initiators on q35/x86.
   https://lore.kernel.org/all/ed23accb-2c8b-90f4-a7a3-f81cc57bf...@inria.fr/
Xiang Chen: to enable/support HMAT on AArch64.
   
https://lore.kernel.org/all/1643102134-15506-1-git-send-email-chenxian...@hisilicon.com/

Thanks!
I think it's best to merge this all after the release.
I've tagged this but please ping me after the release
just to make sure. Thanks everyone!


Just a reminder of that could make it now.



I further add a test with ACPI/HMAT tables that uses the two
patch sets.

Changes from v1:
- Generate APIC and PPTT ACPI tables for AArch64/virt
- Avoid using legacy syntax in numa/bios tests
- Delete unchanged FACP tables

Brice Goglin (4):
   hmat acpi: Don't require initiator value in -numa
   tests: acpi: add and whitelist *.hmat-noinitiator expected blobs
   tests: acpi: q35: add test for hmat nodes without initiators
   tests: acpi: q35: update expected blobs *.hmat-noinitiators expected
     HMAT:

Hesham Almatary (3):
   tests: Add HMAT AArch64/virt empty table files
   tests: acpi: aarch64/virt: add a test for hmat nodes with no initiators
   tests: virt: Update expected *.acpihmatvirt tables

Xiang Chen (1):
   hw/arm/virt: Enable HMAT on arm virt machine

  hw/arm/Kconfig|   1 +
  hw/arm/virt-acpi-build.c  |   7 ++
  hw/core/machine.c |   4 +-
  tests/data/acpi/q35/APIC.acpihmat-noinitiator | Bin 0 -> 144 bytes
  tests/data/acpi/q35/DSDT.acpihmat-noinitiator | Bin 0 -> 8553 bytes
  tests/data/acpi/q35/HMAT.acpihmat-noinitiator | Bin 0 -> 288 bytes
  tests/data/acpi/q35/SRAT.acpihmat-noinitiator | Bin 0 -> 312 bytes
  tests/data/acpi/virt/APIC.acpihmatvirt| Bin 0 -> 396 bytes
  tests/data/acpi/virt/DSDT.acpihmatvirt| Bin 0 -> 5282 bytes
  tests/data/acpi/virt/HMAT.acpihmatvirt| Bin 0 -> 288 bytes
  tests/data/acpi/virt/PPTT.acpihmatvirt| Bin 0 -> 196 bytes
  tests/data/acpi/virt/SRAT.acpihmatvirt| Bin 0 -> 240 bytes
  tests/qtest/bios-tables-test.c| 109 ++
  13 files changed, 118 insertions(+), 3 deletions(-)
  create mode 100644 tests/data/acpi/q35/APIC.acpihmat-noinitiator
  create mode 100644 tests/data/acpi/q35/DSDT.acpihmat-noinitiator
  create mode 100644 tests/data/acpi/q35/HMAT.acpihmat-noinitiator
  create mode 100644 tests/data/acpi/q35/SRAT.acpihmat-noinitiator
  create mode 100644 tests/data/acpi/virt/APIC.acpihmatvirt
  create mode 100644 tests/data/acpi/virt/DSDT.acpihmatvirt
  create mode 100644 tests/data/acpi/virt/HMAT.acpihmatvirt
  create mode 100644 tests/data/acpi/virt/PPTT.acpihmatvirt
  create mode 100644 tests/data/acpi/virt/SRAT.acpihmatvirt

--
2.25.1

[PATCH v2 3/8] tests: acpi: q35: add test for hmat nodes without initiators

2022-07-19 Thread Hesham Almatary

 Entry : 0005
[11Ch 0284   2]Entry : 000A
[11Eh 0286   2]Entry : 0001

Raw Table Data: Length 288 (0x120)

: 48 4D 41 54 20 01 00 00 02 4F 42 4F 43 48 53 20  // HMAT OBOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43  // BXPCBXPC
0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00  // (...
0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // 
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // 
0050: 00 00 00 00 28 00 00 00 01 00 00 00 01 00 00 00  // (...
0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // 
0070: 00 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00  // (...
0080: 00 00 00 00 80 00 00 00 02 00 00 00 00 00 00 00  // 
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // 
00A0: 01 00 00 00 40 00 00 00 00 00 00 00 02 00 00 00  // @...
00B0: 03 00 00 00 00 00 00 00 10 27 00 00 00 00 00 00  // .'..
00C0: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00  // 
00D0: 02 00 00 00 01 00 02 00 03 00 02 00 01 00 03 00  // 
00E0: 01 00 00 00 40 00 00 00 00 03 00 00 02 00 00 00  // @...
00F0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00  // 
0100: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00  // 
0110: 02 00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00  // 

Signed-off-by: Brice Goglin 
Signed-off-by: Hesham Almatary 
---
 tests/qtest/bios-tables-test.c | 50 ++
 1 file changed, 50 insertions(+)

diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 359916c228..db14908bb4 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1461,6 +1461,54 @@ static void test_acpi_piix4_tcg_acpi_hmat(void)
 test_acpi_tcg_acpi_hmat(MACHINE_PC);
 }
 
+static void test_acpi_q35_tcg_acpi_hmat_noinitiator(void)
+{
+test_data data;
+
+memset(&data, 0, sizeof(data));
+data.machine = MACHINE_Q35;
+data.variant = ".acpihmat-noinitiator";
+test_acpi_one(" -machine hmat=on"
+  " -smp 4,sockets=2"
+  " -m 128M"
+  " -object memory-backend-ram,size=32M,id=ram0"
+  " -object memory-backend-ram,size=32M,id=ram1"
+  " -object memory-backend-ram,size=64M,id=ram2"
+  " -numa node,nodeid=0,memdev=ram0"
+  " -numa node,nodeid=1,memdev=ram1"
+  " -numa node,nodeid=2,memdev=ram2"
+  " -numa cpu,node-id=0,socket-id=0"
+  " -numa cpu,node-id=0,socket-id=0"
+  " -numa cpu,node-id=1,socket-id=1"
+  " -numa cpu,node-id=1,socket-id=1"
+  " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
+  "data-type=access-latency,latency=10"
+  " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=10485760"
+  " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
+  "data-type=access-latency,latency=20"
+  " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=5242880"
+  " -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
+  "data-type=access-latency,latency=30"
+  " -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=1048576"
+  " -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
+  "data-type=access-latency,latency=20"
+  " -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=5242880"
+  " -numa hmat-lb,initiator=1,target=1,hierarchy=memory,"
+  "data-type=access-latency,latency=10"
+  " -numa hmat-lb,initiator=1,target=1,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=10485760"
+  " -numa hmat-lb,initiator=1,target=2,hierarchy=memory,"
+  "data-type=access-latency,latency=30"
+  " -numa hmat-lb,initiator=1,target=2,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=1048576",
+

[PATCH v2 7/8] tests: acpi: aarch64/virt: add a test for hmat nodes with no initiators

2022-07-19 Thread Hesham Almatary

This patch imitates the "tests: acpi: q35: add test for hmat nodes
without initiators" commit to test numa nodes with different HMAT
attributes, but on AArch64/virt.

Tested with:
qemu-system-aarch64 -accel tcg \
-machine virt,hmat=on,gic-version=3  -cpu cortex-a57 \
-bios qemu-efi-aarch64/QEMU_EFI.fd \
-kernel Image -append "root=/dev/vda2 console=ttyAMA0" \
-drive if=virtio,file=aarch64.qcow2,format=qcow2,id=hd \
-device virtio-rng-pci \
-net user,hostfwd=tcp::10022-:22 -net nic \
-device intel-hda -device hda-duplex -nographic \
-smp 4 \
-m 3G \
-object memory-backend-ram,size=1G,id=ram0 \
-object memory-backend-ram,size=1G,id=ram1 \
-object memory-backend-ram,size=1G,id=ram2 \
-numa node,nodeid=0,memdev=ram0,cpus=0-1 \
-numa node,nodeid=1,memdev=ram1,cpus=2-3 \
-numa node,nodeid=2,memdev=ram2 \
-numa
hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,latency=10
 \
-numa 
hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760
 \
-numa 
hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,latency=20
 \
-numa 
hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880
 \
-numa 
hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,latency=30
 \
-numa 
hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
 \
-numa 
hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,latency=20
 \
-numa 
hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880
 \
-numa 
hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,latency=10
 \
-numa 
hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760
 \
-numa 
hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,latency=30
 \
-numa 
hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576

Signed-off-by: Hesham Almatary 
---
 tests/qtest/bios-tables-test.c | 59 ++
 1 file changed, 59 insertions(+)

diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index db14908bb4..ca0a66d5e3 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1461,6 +1461,63 @@ static void test_acpi_piix4_tcg_acpi_hmat(void)
 test_acpi_tcg_acpi_hmat(MACHINE_PC);
 }
 
+static void test_acpi_virt_tcg_acpi_hmat(void)
+{
+test_data data = {
+.machine = "virt",
+.tcg_only = true,
+.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
+.uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
+.cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2",
+.ram_start = 0x4000ULL,
+.scan_len = 128ULL * 1024 * 1024,
+};
+
+data.variant = ".acpihmatvirt";
+
+test_acpi_one(" -machine hmat=on"
+  " -cpu cortex-a57"
+  " -smp 4,sockets=2"
+  " -m 256M"
+  " -object memory-backend-ram,size=64M,id=ram0"
+  " -object memory-backend-ram,size=64M,id=ram1"
+  " -object memory-backend-ram,size=128M,id=ram2"
+  " -numa node,nodeid=0,memdev=ram0"
+  " -numa node,nodeid=1,memdev=ram1"
+  " -numa node,nodeid=2,memdev=ram2"
+  " -numa cpu,node-id=0,socket-id=0"
+  " -numa cpu,node-id=0,socket-id=0"
+  " -numa cpu,node-id=1,socket-id=1"
+  " -numa cpu,node-id=1,socket-id=1"
+  " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
+  "data-type=access-latency,latency=10"
+  " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=10485760"
+  " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
+  "data-type=access-latency,latency=20"
+  " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=5242880"
+  " -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
+  "data-type=access-latency,latency=30"
+  " -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=1048576"
+  " -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
+  "data-type=access-latency,latency=20"
+  " -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
+  "d

[PATCH v2 8/8] tests: virt: Update expected *.acpihmatvirt tables

2022-07-19 Thread Hesham Almatary

h 0218   2]Entry : 0002
[0DCh 0220   2]Entry : 0001
[0DEh 0222   2]Entry : 0003

[0E0h 0224   2]   Structure Type : 0001 [System Locality
Latency and Bandwidth Information]
[0E2h 0226   2] Reserved : 
[0E4h 0228   4]   Length : 0040
[0E8h 0232   1]Flags (decoded below) : 00
Memory Hierarchy : 0
[0E9h 0233   1]Data Type : 03
[0EAh 0234   2]Reserved1 : 
[0ECh 0236   4] Initiator Proximity Domains # : 0002
[0F0h 0240   4]   Target Proximity Domains # : 0003
[0F4h 0244   4]Reserved2 : 
[0F8h 0248   8]  Entry Base Unit : 0001
[100h 0256   4] Initiator Proximity Domain List : 
[104h 0260   4] Initiator Proximity Domain List : 0001
[108h 0264   4] Target Proximity Domain List : 
[10Ch 0268   4] Target Proximity Domain List : 0001
[110h 0272   4] Target Proximity Domain List : 0002
[114h 0276   2]Entry : 000A
[116h 0278   2]Entry : 0005
[118h 0280   2]Entry : 0001
[11Ah 0282   2]Entry : 0005
[11Ch 0284   2]Entry : 000A
[11Eh 0286   2]Entry : 0001

Raw Table Data: Length 288 (0x120)

: 48 4D 41 54 20 01 00 00 02 4F 42 4F 43 48 53 20  // HMAT
OBOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43  // BXPC
BXPC
0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00  //
(...
0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  //

0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  //

0050: 00 00 00 00 28 00 00 00 01 00 00 00 01 00 00 00  //
(...
0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  //

0070: 00 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00  //
(...
0080: 00 00 00 00 80 00 00 00 02 00 00 00 00 00 00 00  //

0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  //

00A0: 01 00 00 00 40 00 00 00 00 00 00 00 02 00 00 00  //
@...
00B0: 03 00 00 00 00 00 00 00 10 27 00 00 00 00 00 00  //
.'..
00C0: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00  //

00D0: 02 00 00 00 01 00 02 00 03 00 02 00 01 00 03 00  //

00E0: 01 00 00 00 40 00 00 00 00 03 00 00 02 00 00 00  //
@...
00F0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00  //

0100: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00  //

0110: 02 00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00  //
....

Signed-off-by: Hesham Almatary 
---
 tests/data/acpi/virt/APIC.acpihmatvirt  | Bin 0 -> 396 bytes
 tests/data/acpi/virt/DSDT.acpihmatvirt  | Bin 0 -> 5282 bytes
 tests/data/acpi/virt/HMAT.acpihmatvirt  | Bin 0 -> 288 bytes
 tests/data/acpi/virt/PPTT.acpihmatvirt  | Bin 0 -> 196 bytes
 tests/data/acpi/virt/SRAT.acpihmatvirt  | Bin 0 -> 240 bytes
 tests/qtest/bios-tables-test-allowed-diff.h |   5 -
 6 files changed, 5 deletions(-)

diff --git a/tests/data/acpi/virt/APIC.acpihmatvirt 
b/tests/data/acpi/virt/APIC.acpihmatvirt
index 
e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..873e12f67c3838351a3ab4b7a43ee76e7730849a
 100644
GIT binary patch
literal 396
zcmZ<^@O18BWME)kGD%s#!2MfXo894}@W2q?!fN3j!dsn1M71lWP`8
TF9`6$!;uLb4j}U!7y=joChH0T

literal 0
HcmV?d1

diff --git a/tests/data/acpi/virt/DSDT.acpihmatvirt 
b/tests/data/acpi/virt/DSDT.acpihmatvirt
index 
e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..aee6ba017cd730948bfa93e91551eb10a6809293
 100644
GIT binary patch
literal 5282
zcmZvg%WoT16o>EFlh__VVmr?J;S@^6vl`n?la{u`9y^IkoET5iAUTpNArK{-N>oUt
zLJCD*Gs*9?XQYhh%)RHE`;Cv|<7xWM-JeTJ
z#SR)f-lo6Q_^|6O(Pk;7^s#=;f4^ZJ4E)BRe?05CuA3Zewwu|y*KJdS;>pWu{bKsqaRW
zWnH4^F|BBIecxL*;161zJz8y*a{b-9lcr>^ZW%u
zu9+M80>hRVNnl(<#0#5|#QSFy2LmT&Edn9n-+Lg$%h)vl3$#
z7`Krj*J(~-%md>NGUPfPlNgJ@cn=wJo#rLR5-`?~A=ha^V!Q&3Ix^%sElP~bz-S;t
zuG4XeaRnG2FsgE$mL$gOz-S^vuG0yL@g^`@$dK!FQewOfjCEwlbvh+6t^#8N8FHOY
zOAHqno5+ysbVg!Sfzd{WT&J@V;~FsTB15jzIf-!{81ExPuG4vmu?mbWWXN^8ATe$N
zqXUeZT&If?;}$Tsks;Sw=DW&MZS}EQQZD^9>F5jfKz&57N<)IiqubjZ-}>A+DyHr9aHux?wyVss
zMaLCY%;@t@jDl(u#3`t$V%E+KhnCVgG%t*F7ER2Vu^^A8Mxo9melVB1Br`XRbY?V_
zS|EKzni^zMs57Ih#DmOe1#zV_qp5L|NmGMN3Uwx}D7cCpWJW8ngUo0uwM?O9kVzqW
zjxf)WAT#nDF`3cgDMZgv=1EN{ttXmFEf#uGh@J`NnP8p??nxnfCYfiFc~VP;o)n^I
zig{8yZSG!hOH$mELiBW)r^7s{g+osY(KF3F)66r?Jt;)b4D-w|PipzllS1^&GS4jY
z%yLf((KE+9bIg-kMD(N(J;#{m81o$Co)n@d{hTp19#nCjc~VP>o)n^Ifq52~XMuZC
zh@M5}S!ABnf}$sd=sC_j$C>9i_oNU#>E|bSmY65CtmsK0dQLFU3FbM$Jt;)bN#;4p
zJgLP+PYTgx#fK=R#H~KkyoLbw>X~
zRep_j=5}l*oJZegRgC_f(>ByQ>l^xXWvIIdw)}ATpZ-}!+wdxlSQ+X8%tlQMZ9^Kh
z

[PATCH v2 2/8] tests: acpi: add and whitelist *.hmat-noinitiator expected blobs

2022-07-19 Thread Hesham Almatary

From: Brice Goglin 

.. which will be used by follow up hmat-noinitiator test-case.

Signed-off-by: Brice Goglin 
Signed-off-by: Hesham Almatary 
---
 tests/data/acpi/q35/APIC.acpihmat-noinitiator | 0
 tests/data/acpi/q35/DSDT.acpihmat-noinitiator | 0
 tests/data/acpi/q35/HMAT.acpihmat-noinitiator | 0
 tests/data/acpi/q35/SRAT.acpihmat-noinitiator | 0
 tests/qtest/bios-tables-test-allowed-diff.h   | 4 
 5 files changed, 4 insertions(+)
 create mode 100644 tests/data/acpi/q35/APIC.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/q35/DSDT.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/q35/HMAT.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/q35/SRAT.acpihmat-noinitiator

diff --git a/tests/data/acpi/q35/APIC.acpihmat-noinitiator 
b/tests/data/acpi/q35/APIC.acpihmat-noinitiator
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/data/acpi/q35/DSDT.acpihmat-noinitiator 
b/tests/data/acpi/q35/DSDT.acpihmat-noinitiator
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/data/acpi/q35/HMAT.acpihmat-noinitiator 
b/tests/data/acpi/q35/HMAT.acpihmat-noinitiator
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/data/acpi/q35/SRAT.acpihmat-noinitiator 
b/tests/data/acpi/q35/SRAT.acpihmat-noinitiator
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..245fa66bcc 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,5 @@
 /* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/APIC.acpihmat-noinitiator",
+"tests/data/acpi/q35/DSDT.acpihmat-noinitiator",
+"tests/data/acpi/q35/HMAT.acpihmat-noinitiator",
+"tests/data/acpi/q35/SRAT.acpihmat-noinitiator",
-- 
2.25.1

[PATCH v2 5/8] tests: Add HMAT AArch64/virt empty table files

2022-07-19 Thread Hesham Almatary

Signed-off-by: Hesham Almatary 
---
 tests/data/acpi/virt/APIC.acpihmatvirt  | 0
 tests/data/acpi/virt/DSDT.acpihmatvirt  | 0
 tests/data/acpi/virt/HMAT.acpihmatvirt  | 0
 tests/data/acpi/virt/PPTT.acpihmatvirt  | 0
 tests/data/acpi/virt/SRAT.acpihmatvirt  | 0
 tests/qtest/bios-tables-test-allowed-diff.h | 5 +
 6 files changed, 5 insertions(+)
 create mode 100644 tests/data/acpi/virt/APIC.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/DSDT.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/HMAT.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/PPTT.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/SRAT.acpihmatvirt

diff --git a/tests/data/acpi/virt/APIC.acpihmatvirt 
b/tests/data/acpi/virt/APIC.acpihmatvirt
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/data/acpi/virt/DSDT.acpihmatvirt 
b/tests/data/acpi/virt/DSDT.acpihmatvirt
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/data/acpi/virt/HMAT.acpihmatvirt 
b/tests/data/acpi/virt/HMAT.acpihmatvirt
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/data/acpi/virt/PPTT.acpihmatvirt 
b/tests/data/acpi/virt/PPTT.acpihmatvirt
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/data/acpi/virt/SRAT.acpihmatvirt 
b/tests/data/acpi/virt/SRAT.acpihmatvirt
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..4f849715bd 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,6 @@
 /* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/virt/APIC.acpihmatvirt",
+"tests/data/acpi/virt/DSDT.acpihmatvirt",
+"tests/data/acpi/virt/HMAT.acpihmatvirt",
+"tests/data/acpi/virt/PPTT.acpihmatvirt",
+"tests/data/acpi/virt/SRAT.acpihmatvirt",
-- 
2.25.1

[PATCH v2 6/8] hw/arm/virt: Enable HMAT on arm virt machine

2022-07-19 Thread Hesham Almatary

From: Xiang Chen 

Since the patchset ("Build ACPI Heterogeneous Memory Attribute Table (HMAT)"),
HMAT is supported, but only x86 is enabled. Enable HMAT on arm virt machine.

Signed-off-by: Xiang Chen 
Signed-off-by: Hesham Almatary 
Reviewed-by: Igor Mammedov 
---
 hw/arm/Kconfig   | 1 +
 hw/arm/virt-acpi-build.c | 7 +++
 2 files changed, 8 insertions(+)

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 15fa79afd3..17fcde8e1c 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -30,6 +30,7 @@ config ARM_VIRT
 select ACPI_VIOT
 select VIRTIO_MEM_SUPPORTED
 select ACPI_CXL
+select ACPI_HMAT
 
 config CHEETAH
 bool
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 449fab0080..f19b55e486 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -42,6 +42,7 @@
 #include "hw/acpi/memory_hotplug.h"
 #include "hw/acpi/generic_event_device.h"
 #include "hw/acpi/tpm.h"
+#include "hw/acpi/hmat.h"
 #include "hw/pci/pcie_host.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_bus.h"
@@ -990,6 +991,12 @@ void virt_acpi_build(VirtMachineState *vms, 
AcpiBuildTables *tables)
 build_slit(tables_blob, tables->linker, ms, vms->oem_id,
vms->oem_table_id);
 }
+
+if (ms->numa_state->hmat_enabled) {
+acpi_add_table(table_offsets, tables_blob);
+build_hmat(tables_blob, tables->linker, ms->numa_state,
+   vms->oem_id, vms->oem_table_id);
+}
 }
 
 if (ms->nvdimms_state->is_enabled) {
-- 
2.25.1

[PATCH v2 4/8] tests: acpi: q35: update expected blobs *.hmat-noinitiators

2022-07-19 Thread Hesham Almatary

 Entry : 0005
[11Ch 0284   2]Entry : 000A
[11Eh 0286   2]Entry : 0001

Raw Table Data: Length 288 (0x120)

: 48 4D 41 54 20 01 00 00 02 4F 42 4F 43 48 53 20  // HMAT OBOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43  // BXPCBXPC
0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00  // (...
0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // 
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // 
0050: 00 00 00 00 28 00 00 00 01 00 00 00 01 00 00 00  // (...
0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // 
0070: 00 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00  // (...
0080: 00 00 00 00 80 00 00 00 02 00 00 00 00 00 00 00  // 
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // 
00A0: 01 00 00 00 40 00 00 00 00 00 00 00 02 00 00 00  // @...
00B0: 03 00 00 00 00 00 00 00 10 27 00 00 00 00 00 00  // .'..
00C0: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00  // 
00D0: 02 00 00 00 01 00 02 00 03 00 02 00 01 00 03 00  // 
00E0: 01 00 00 00 40 00 00 00 00 03 00 00 02 00 00 00  // @...
00F0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00  // 
0100: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00  // 
0110: 02 00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00  // 

Signed-off-by: Brice Goglin 
Signed-off-by: Hesham Almatary 
---
 tests/data/acpi/q35/APIC.acpihmat-noinitiator | Bin 0 -> 144 bytes
 tests/data/acpi/q35/DSDT.acpihmat-noinitiator | Bin 0 -> 8553 bytes
 tests/data/acpi/q35/HMAT.acpihmat-noinitiator | Bin 0 -> 288 bytes
 tests/data/acpi/q35/SRAT.acpihmat-noinitiator | Bin 0 -> 312 bytes
 tests/qtest/bios-tables-test-allowed-diff.h   |   4 
 5 files changed, 4 deletions(-)

diff --git a/tests/data/acpi/q35/APIC.acpihmat-noinitiator 
b/tests/data/acpi/q35/APIC.acpihmat-noinitiator
index 
e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..d904d4a70ddecbb79a83a267af8e26f925e9f4c6
 100644
GIT binary patch
literal 144
zcmZ<^@N}NQz`(%h?d0$55v<@85#X!<1dKp25F11@Fg*ANra6G>KwJ(+MhMNs1fiLk
tK{O)|Nb|r~o3y%?)O;u>A)b0RWi;3;_TD

literal 0
HcmV?d1

diff --git a/tests/data/acpi/q35/DSDT.acpihmat-noinitiator 
b/tests/data/acpi/q35/DSDT.acpihmat-noinitiator
index 
e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..c767d11cb1d088f613c49e55a7139cccababf66c
 100644
GIT binary patch
literal 8553
zcmb7JOKcm*8J^`sS}m8-lA^$0{LCIadERkMusn`Jpkg}Xsa#CcG
z#6TVhAj?4F_)s)q67)z13ea17>a_-XX>YzYKu;$gY0nd~tOIw46@kU+2F&
zd-_*jUVf)|@0b7l^_|zP1OTh}HSv2sq_5rwJ?l(w;C$BKGd?6bKesYi{H)JUi#CVO
zggt7xYl|jIwQ~4+=inu;RdjhD(|*%0xP=w;%WVajv)1X4ml?BZaOm^r;c)m@ambwa
znA0$Y%CcGW%WbLBfHqRq*{}KS2D2Hv|1iZ8otqBDi?5WMUfyqc-F)taZqP2WkXm{n
zHEqA&vz*?*{?=OI4%Cddx7Y
z#x-^gzvp5|-#K`yacOhJT3FOrrjbzjgZa7)e2M&7S`SMnXB
zwC=94+|#~Wz8LE~Nzrf^?h+z=&)8#>qw_;*K4iIPir`E`QLd1_dJ(pl^JaW6Xv`1R
zqkG~0i~smf@cjFYPnW-KocNpD2r1VazwHg4>|bYt6a76ahAICcpEx$=>5v^};>Jz-
zVt1DZOa1HCY?w{PSek8zz1!Q29d4U`-L0^k-NmmF?o#CZ?p1?kk>h^L?_9st_Ookm
z?`Km9Oh>lfTq`qiY~Z-UvNp9_F$7f^#1Yh3Hl08}aO((M6cG!+d2x>O0F@yzk)LB@
zoC$0c5mQ2Aj57h{OoYTlZ#Xv2nX(6QMobBf3nrkPiIAAG3T`BU<#`gEDWM6$l$}SY
z>P%`nlbk7`Nx_tzN2uzY(R9vmri9MuIuWWmXEmL(n$B5WCqh-Hsp&K|ou;l6p{f&)
z9A%{EG@Wz0PK2sXOVep-IxSr%LRDu<)0xtArgWVMRh@YBDc951blSR3gsRT8rZcVS
zOzS!ksygR2o%5Q`d0i($Rp)}Hb3xO&pzB1a>U1=nj;7Pmbs|)CW;C4{O=m{eiBQ#<
z)pTYxompKcLRIIYrgKr#xv1+zsOrpVI&+%NoURk0s&h%xxuoe_(sd$Kbsp1n9@BIl
z({&h_lvrj&UmNlKrx=w_u&f}WS`n-#`zR!)
z7hz9o%##}Pq|QXBGEZsDQyTM>&P1p(PixH68uPTyM5r>K(3nqX%qMgvLX~-jGo{O%
z;Y|6AKO>m(!HtlZ@(P~SYM#|`0y;8Kgy@YlP=Spis;L^NfQ}3lA$r8I
zFi?SwqDUi$l7R}S3{{;lP?451VW0|>3>2YsMKVx?QYQ>lU^x>8szAv=1(eq$14Srx
z!axOlU^x>8szAv=1(Y+%KoLrvFi?TzOcu
z&LjgxD0RX>1(q{mpbC@>R6seC3>2Z%2?G^a&V+#~P%=;f=3{*fllMEE0)CmI>Sk8oj
zDo`>|0p(0GP=rz^3{+q_69%e4$v_2^Gs!>^N}VuJf#pmXr~)Me6;RG314Srx!axO<
zGhv_#lnhirIg<<&q0|Wj6M_lrzad5lWpf
zP=V!47^ngz0~JutBm+e#b;3XqDF%v2HBf}Afg)54RAItE6($*|!XyJ#m@rU<2?JG_
zWS|O@3{+vlKouqoRAG{VDoip^g$V;ym@rU1;Px-d{gxMF-T$v_d}
zGRTmaa%^Fsh~(J9KoQBYB?Cn$$CeBfA=ZXYc447xVE6f-)kFG2dUu9?ik+K3e=bh{
zQfaA!mNyK)wNZrQZj|WDr7zE9SZvuS({Y8qs`OPebBpy2tOg9`KCt$8v8pn6Xr*!&
z>Kkrr4uDo6GjF9nnPGE$>E}ImhuW+pzU$!!yVe4uBXpvLrIz(sydxCll824;8Cv}@
z(d{5}%v$_pp3TMKZVbVJjUA?4KFY)Rn^iQo`%1y6c>KrskyI4EJ`d*~niakbo
zS1IrE^6pr9_lWXtRNfmCZ(%{}d#m@9@*Xemjg|L~DDOq(%j4w}k5Rs?lrQu0<+1YR
zBg&Vf@|E%O$;T*PQOZ|%`N~-N$`R!&QTgh4`I*NkUscLidHL#C`RWnnt5Nydc=_4K
zC|^^`*LeBbSozu!YH+~yi89g1|
zH73%DwyEhR?#ry64lf`R=|tPqbQAX(mVoI#lfv*;GLcTSO-(m(-{kakcvYE5C)%c_
zo45~_^mKTCnMfzvrly;i*T?j9c&V94C)%c_o0zA|dOE!6Or#TSdOGKnvc|scf+0>HHfTy9YOaL_v||UBBEk+uZO-Tq8-!AFq%xo(dVJ=Fe4+xq;g>kC0)y
z&

[PATCH v2 1/8] hmat acpi: Don't require initiator value in -numa

2022-07-19 Thread Hesham Almatary

Entry : 0002
[0DCh 0220   2]Entry : 0001
[0DEh 0222   2]Entry : 0003

[0E0h 0224   2]   Structure Type : 0001 [System Locality Latency 
and Bandwidth Information]
[0E2h 0226   2] Reserved : 
[0E4h 0228   4]   Length : 0040
[0E8h 0232   1]Flags (decoded below) : 00
Memory Hierarchy : 0
[0E9h 0233   1]Data Type : 03
[0EAh 0234   2]Reserved1 : 
[0ECh 0236   4] Initiator Proximity Domains # : 0002
[0F0h 0240   4]   Target Proximity Domains # : 0003
[0F4h 0244   4]Reserved2 : 
[0F8h 0248   8]  Entry Base Unit : 0001
[100h 0256   4] Initiator Proximity Domain List : 
[104h 0260   4] Initiator Proximity Domain List : 0001
[108h 0264   4] Target Proximity Domain List : 
[10Ch 0268   4] Target Proximity Domain List : 0001
[110h 0272   4] Target Proximity Domain List : 0002
[114h 0276   2]Entry : 000A
[116h 0278   2]Entry : 0005
[118h 0280   2]Entry : 0001
[11Ah 0282   2]Entry : 0005
[11Ch 0284   2]Entry : 000A
[11Eh 0286   2]Entry : 0001

Signed-off-by: Brice Goglin 
Signed-off-by: Hesham Almatary 
Reviewed-by: Jingqi Liu 
---
 hw/core/machine.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/hw/core/machine.c b/hw/core/machine.c
index a673302cce..d4d7e77401 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -1173,9 +1173,7 @@ static void numa_validate_initiator(NumaState *numa_state)
 
 for (i = 0; i < numa_state->num_nodes; i++) {
 if (numa_info[i].initiator == MAX_NODES) {
-error_report("The initiator of NUMA node %d is missing, use "
- "'-numa node,initiator' option to declare it", i);
-exit(1);
+continue;
 }
 
 if (!numa_info[numa_info[i].initiator].present) {
-- 
2.25.1

[PATCH v2 0/8] AArch64/HMAT support and tests

2022-07-19 Thread Hesham Almatary

This patchset adds support for AArch64/HMAT including a test.
It relies on other two patch sets from:

Brice Goglin: to support -numa without initiators on q35/x86.
  https://lore.kernel.org/all/ed23accb-2c8b-90f4-a7a3-f81cc57bf...@inria.fr/
Xiang Chen: to enable/support HMAT on AArch64.
  
https://lore.kernel.org/all/1643102134-15506-1-git-send-email-chenxian...@hisilicon.com/

I further add a test with ACPI/HMAT tables that uses the two
patch sets.

Changes from v1:
- Generate APIC and PPTT ACPI tables for AArch64/virt
- Avoid using legacy syntax in numa/bios tests
- Delete unchanged FACP tables

Brice Goglin (4):
  hmat acpi: Don't require initiator value in -numa
  tests: acpi: add and whitelist *.hmat-noinitiator expected blobs
  tests: acpi: q35: add test for hmat nodes without initiators
  tests: acpi: q35: update expected blobs *.hmat-noinitiators expected
HMAT:

Hesham Almatary (3):
  tests: Add HMAT AArch64/virt empty table files
  tests: acpi: aarch64/virt: add a test for hmat nodes with no initiators
  tests: virt: Update expected *.acpihmatvirt tables

Xiang Chen (1):
  hw/arm/virt: Enable HMAT on arm virt machine

 hw/arm/Kconfig|   1 +
 hw/arm/virt-acpi-build.c  |   7 ++
 hw/core/machine.c |   4 +-
 tests/data/acpi/q35/APIC.acpihmat-noinitiator | Bin 0 -> 144 bytes
 tests/data/acpi/q35/DSDT.acpihmat-noinitiator | Bin 0 -> 8553 bytes
 tests/data/acpi/q35/HMAT.acpihmat-noinitiator | Bin 0 -> 288 bytes
 tests/data/acpi/q35/SRAT.acpihmat-noinitiator | Bin 0 -> 312 bytes
 tests/data/acpi/virt/APIC.acpihmatvirt| Bin 0 -> 396 bytes
 tests/data/acpi/virt/DSDT.acpihmatvirt| Bin 0 -> 5282 bytes
 tests/data/acpi/virt/HMAT.acpihmatvirt| Bin 0 -> 288 bytes
 tests/data/acpi/virt/PPTT.acpihmatvirt| Bin 0 -> 196 bytes
 tests/data/acpi/virt/SRAT.acpihmatvirt| Bin 0 -> 240 bytes
 tests/qtest/bios-tables-test.c| 109 ++
 13 files changed, 118 insertions(+), 3 deletions(-)
 create mode 100644 tests/data/acpi/q35/APIC.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/q35/DSDT.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/q35/HMAT.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/q35/SRAT.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/virt/APIC.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/DSDT.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/HMAT.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/PPTT.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/SRAT.acpihmatvirt

-- 
2.25.1

Re: [PATCH 1/8] hmat acpi: Don't require initiator value in -numa

2022-07-18 Thread Hesham Almatary via




On 7/18/2022 2:54 PM, Igor Mammedov wrote:

On Mon, 11 Jul 2022 11:44:29 +0100
Hesham Almatary  wrote:


From: Brice Goglin 

The "Memory Proximity Domain Attributes" structure of the ACPI HMAT
has a "Processor Proximity Domain Valid" flag that is currently
always set because Qemu -numa requires an initiator=X value
when hmat=on. Unsetting this flag allows to create more complex
memory topologies by having multiple best initiators for a single
memory target.

This patch allows -numa without initiator=X when hmat=on by keeping
the default value MAX_NODES in numa_state->nodes[i].initiator.
All places reading numa_state->nodes[i].initiator already check
whether it's different from MAX_NODES before using it.

[...]

Signed-off-by: Brice Goglin 

when re-posting patches from someone else, I think one is supposed to add
his/her own SoB at the end


Sure, I can do that in v2. I wasn't sure as I haven't modified any of these 
patches.

---
  hw/core/machine.c | 4 +---
  1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/hw/core/machine.c b/hw/core/machine.c
index a673302cce..d4d7e77401 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -1173,9 +1173,7 @@ static void numa_validate_initiator(NumaState *numa_state)
  
  for (i = 0; i < numa_state->num_nodes; i++) {

  if (numa_info[i].initiator == MAX_NODES) {
-error_report("The initiator of NUMA node %d is missing, use "
- "'-numa node,initiator' option to declare it", i);
-exit(1);
+continue;
  }
  
  if (!numa_info[numa_info[i].initiator].present) {

[PATCH 8/8] tests: virt: Update expected *.acpihmatvirt tables

2022-07-11 Thread Hesham Almatary via

.@..
0050: 00 00 00 00 00 08 00 00 00 00 00 00 00 00 01 00  // 
0060: 00 00 00 00 00 00 00 00 00 00// ..

Signed-off-by: Hesham Almatary 
---
 tests/data/acpi/virt/DSDT.acpihmatvirt  | Bin 0 -> 5282 bytes
 tests/data/acpi/virt/FACP.acpihmatvirt  | Bin 0 -> 268 bytes
 tests/data/acpi/virt/HMAT.acpihmatvirt  | Bin 0 -> 288 bytes
 tests/data/acpi/virt/SRAT.acpihmatvirt  | Bin 0 -> 240 bytes
 tests/qtest/bios-tables-test-allowed-diff.h |   4 
 5 files changed, 4 deletions(-)

diff --git a/tests/data/acpi/virt/DSDT.acpihmatvirt 
b/tests/data/acpi/virt/DSDT.acpihmatvirt
index 
e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..aee6ba017cd730948bfa93e91551eb10a6809293
 100644
GIT binary patch
literal 5282
zcmZvg%WoT16o>EFlh__VVmr?J;S@^6vl`n?la{u`9y^IkoET5iAUTpNArK{-N>oUt
zLJCD*Gs*9?XQYhh%)RHE`;Cv|<7xWM-JeTJ
z#SR)f-lo6Q_^|6O(Pk;7^s#=;f4^ZJ4E)BRe?05CuA3Zewwu|y*KJdS;>pWu{bKsqaRW
zWnH4^F|BBIecxL*;161zJz8y*a{b-9lcr>^ZW%u
zu9+M80>hRVNnl(<#0#5|#QSFy2LmT&Edn9n-+Lg$%h)vl3$#
z7`Krj*J(~-%md>NGUPfPlNgJ@cn=wJo#rLR5-`?~A=ha^V!Q&3Ix^%sElP~bz-S;t
zuG4XeaRnG2FsgE$mL$gOz-S^vuG0yL@g^`@$dK!FQewOfjCEwlbvh+6t^#8N8FHOY
zOAHqno5+ysbVg!Sfzd{WT&J@V;~FsTB15jzIf-!{81ExPuG4vmu?mbWWXN^8ATe$N
zqXUeZT&If?;}$Tsks;Sw=DW&MZS}EQQZD^9>F5jfKz&57N<)IiqubjZ-}>A+DyHr9aHux?wyVss
zMaLCY%;@t@jDl(u#3`t$V%E+KhnCVgG%t*F7ER2Vu^^A8Mxo9melVB1Br`XRbY?V_
zS|EKzni^zMs57Ih#DmOe1#zV_qp5L|NmGMN3Uwx}D7cCpWJW8ngUo0uwM?O9kVzqW
zjxf)WAT#nDF`3cgDMZgv=1EN{ttXmFEf#uGh@J`NnP8p??nxnfCYfiFc~VP;o)n^I
zig{8yZSG!hOH$mELiBW)r^7s{g+osY(KF3F)66r?Jt;)b4D-w|PipzllS1^&GS4jY
z%yLf((KE+9bIg-kMD(N(J;#{m81o$Co)n@d{hTp19#nCjc~VP>o)n^Ifq52~XMuZC
zh@M5}S!ABnf}$sd=sC_j$C>9i_oNU#>E|bSmY65CtmsK0dQLFU3FbM$Jt;)bN#;4p
zJgLP+PYTgx#fK=R#H~KkyoLbw>X~
zRep_j=5}l*oJZegRgC_f(>ByQ>l^xXWvIIdw)}ATpZ-}!+wdxlSQ+X8%tlQMZ9^Kh
z)U&rBCm24`V|ojsi=96ISS9_vZdWC}-QJcet)~V%zGpu>R9kxA31(ML
zC!e20^UUeI9(<@L>+@%aKjqAMeUZx9VdT?A)L9{JS$angx;l2R<+Ezk54v>C)g1Sw`xCqeba%>Y7q>PzVzO{N^X|8-i2UdwN7EtM7qt$Vwv
hhdQ`_nm>7R-_iZv)9!w+;T-jkXY>Jno;-6c^*?7DCOrTE

literal 0
HcmV?d1

diff --git a/tests/data/acpi/virt/FACP.acpihmatvirt 
b/tests/data/acpi/virt/FACP.acpihmatvirt
index 
e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..1f764220f8533c427168e80ccf298604826a00b4
 100644
GIT binary patch
literal 268
ycmZ>BbPnKQWME(ob@F%i2v%^42yj*a0-z8Bhz+8t3j|P&V`iYf6{t24%>w}Cy9NOO

literal 0
HcmV?d1

diff --git a/tests/data/acpi/virt/HMAT.acpihmatvirt 
b/tests/data/acpi/virt/HMAT.acpihmatvirt
index 
e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..6494d11b9fff54f8c403ec9e4893fdff72bde9c9
 100644
GIT binary patch
literal 288
zcmaJ)F%Ezr5IZ0&Og@24pP{g@7)*5VIX>Ms;S4dxCU-4Odz5uKq7kt*)m-+N&Mij(
zmQa%w6GZ=3|IM0X_Ak#IabYaQ2iTvR&x~t&7@Gj;A7o|>w!;|gr;lRa*AB0!)_xEV
I&r86*0dKzu0RR91

literal 0
HcmV?d1

diff --git a/tests/data/acpi/virt/SRAT.acpihmatvirt 
b/tests/data/acpi/virt/SRAT.acpihmatvirt
index 
e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..691ef56e34bc84509270db316d908f5979c209bb
 100644
GIT binary patch
literal 240
zcmWFzat!&vz`($~%E{l^BUr&HBEVSz2pEB4AU22wVHjW*g0Wzt5D{c`%t9a@6A&ZR
rfLP2(B8(b94g@$rX%;9A*9GD;YQW53aKWz*WFHuKKxqyrjba`E3*rd@

literal 0
HcmV?d1

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index 44594cae59..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,5 +1 @@
 /* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/virt/DSDT.acpihmatvirt",
-"tests/data/acpi/virt/FACP.acpihmatvirt",
-"tests/data/acpi/virt/HMAT.acpihmatvirt",
-"tests/data/acpi/virt/SRAT.acpihmatvirt",
-- 
2.25.1

[PATCH 7/8] tests: acpi: aarch64/virt: add a test for hmat nodes with no initiators

2022-07-11 Thread Hesham Almatary via

This patch imitates the "tests: acpi: q35: add test for hmat nodes
without initiators" commit to test numa nodes with different HMAT
attributes, but on AArch64/virt.

Tested with:
qemu-system-aarch64 -accel tcg \
 -machine virt,hmat=on,gic-version=3  -cpu cortex-a57 \
 -bios qemu-efi-aarch64/QEMU_EFI.fd \
 -kernel Image -append "root=/dev/vda2 console=ttyAMA0" \
 -drive if=virtio,file=aarch64.qcow2,format=qcow2,id=hd \
 -device virtio-rng-pci \
 -net user,hostfwd=tcp::10022-:22 -net nic \
 -device intel-hda -device hda-duplex -nographic \
 -smp 4 \
 -m 3G \
 -object memory-backend-ram,size=1G,id=ram0 \
 -object memory-backend-ram,size=1G,id=ram1 \
 -object memory-backend-ram,size=1G,id=ram2 \
 -numa node,nodeid=0,memdev=ram0,cpus=0-1 \
 -numa node,nodeid=1,memdev=ram1,cpus=2-3 \
 -numa node,nodeid=2,memdev=ram2 \
 -numa 
hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,latency=10
 \
 -numa 
hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760
 \
 -numa 
hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,latency=20
 \
 -numa 
hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880
 \
 -numa 
hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,latency=30
 \
 -numa 
hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
 \
 -numa 
hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,latency=20
 \
 -numa 
hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880
 \
 -numa 
hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,latency=10
 \
 -numa 
hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760
 \
 -numa 
hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,latency=30
 \
 -numa 
hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576

Signed-off-by: Hesham Almatary 
---
 tests/qtest/bios-tables-test.c | 55 ++
 1 file changed, 55 insertions(+)

diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index f02b386d75..ed843c2abf 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1461,6 +1461,59 @@ static void test_acpi_piix4_tcg_acpi_hmat(void)
 test_acpi_tcg_acpi_hmat(MACHINE_PC);
 }
 
+static void test_acpi_virt_tcg_acpi_hmat(void)
+{
+test_data data = {
+.machine = "virt",
+.tcg_only = true,
+.uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
+.uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
+.cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2",
+.ram_start = 0x4000ULL,
+.scan_len = 128ULL * 1024 * 1024,
+};
+
+data.variant = ".acpihmatvirt";
+
+test_acpi_one(" -machine hmat=on"
+  " -cpu cortex-a57"
+  " -smp 4"
+  " -m 256M"
+  " -object memory-backend-ram,size=64M,id=ram0"
+  " -object memory-backend-ram,size=64M,id=ram1"
+  " -object memory-backend-ram,size=128M,id=ram2"
+  " -numa node,nodeid=0,memdev=ram0,cpus=0-1"
+  " -numa node,nodeid=1,memdev=ram1,cpus=2-3"
+  " -numa node,nodeid=2,memdev=ram2"
+  " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
+  "data-type=access-latency,latency=10"
+  " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=10485760"
+  " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
+  "data-type=access-latency,latency=20"
+  " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=5242880"
+  " -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
+  "data-type=access-latency,latency=30"
+  " -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=1048576"
+  " -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
+  "data-type=access-latency,latency=20"
+  " -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
+  "data-type=access-bandwidth,bandwidth=5242880"
+  " -numa hmat-lb,initiator=1,target=1,hierarchy=memory,"
+  "data-type=access-latency,latency=10"
+  &quo

[PATCH 5/8] tests: Add HMAT AArch64/virt empty table files

2022-07-11 Thread Hesham Almatary via

Signed-off-by: Hesham Almatary 
---
 tests/data/acpi/virt/DSDT.acpihmatvirt  | 0
 tests/data/acpi/virt/FACP.acpihmatvirt  | 0
 tests/data/acpi/virt/HMAT.acpihmatvirt  | 0
 tests/data/acpi/virt/SRAT.acpihmatvirt  | 0
 tests/qtest/bios-tables-test-allowed-diff.h | 4 
 5 files changed, 4 insertions(+)
 create mode 100644 tests/data/acpi/virt/DSDT.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/FACP.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/HMAT.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/SRAT.acpihmatvirt

diff --git a/tests/data/acpi/virt/DSDT.acpihmatvirt 
b/tests/data/acpi/virt/DSDT.acpihmatvirt
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/data/acpi/virt/FACP.acpihmatvirt 
b/tests/data/acpi/virt/FACP.acpihmatvirt
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/data/acpi/virt/HMAT.acpihmatvirt 
b/tests/data/acpi/virt/HMAT.acpihmatvirt
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/data/acpi/virt/SRAT.acpihmatvirt 
b/tests/data/acpi/virt/SRAT.acpihmatvirt
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..44594cae59 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,5 @@
 /* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/virt/DSDT.acpihmatvirt",
+"tests/data/acpi/virt/FACP.acpihmatvirt",
+"tests/data/acpi/virt/HMAT.acpihmatvirt",
+"tests/data/acpi/virt/SRAT.acpihmatvirt",
-- 
2.25.1

[PATCH 6/8] hw/arm/virt: Enable HMAT on arm virt machine

2022-07-11 Thread Hesham Almatary via

From: Xiang Chen 

Since the patchset ("Build ACPI Heterogeneous Memory Attribute Table (HMAT)"),
HMAT is supported, but only x86 is enabled. Enable HMAT on arm virt machine.

Signed-off-by: Xiang Chen 
---
 hw/arm/Kconfig   | 1 +
 hw/arm/virt-acpi-build.c | 7 +++
 2 files changed, 8 insertions(+)

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 15fa79afd3..17fcde8e1c 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -30,6 +30,7 @@ config ARM_VIRT
 select ACPI_VIOT
 select VIRTIO_MEM_SUPPORTED
 select ACPI_CXL
+select ACPI_HMAT
 
 config CHEETAH
 bool
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 449fab0080..f19b55e486 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -42,6 +42,7 @@
 #include "hw/acpi/memory_hotplug.h"
 #include "hw/acpi/generic_event_device.h"
 #include "hw/acpi/tpm.h"
+#include "hw/acpi/hmat.h"
 #include "hw/pci/pcie_host.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_bus.h"
@@ -990,6 +991,12 @@ void virt_acpi_build(VirtMachineState *vms, 
AcpiBuildTables *tables)
 build_slit(tables_blob, tables->linker, ms, vms->oem_id,
vms->oem_table_id);
 }
+
+if (ms->numa_state->hmat_enabled) {
+acpi_add_table(table_offsets, tables_blob);
+build_hmat(tables_blob, tables->linker, ms->numa_state,
+   vms->oem_id, vms->oem_table_id);
+}
 }
 
 if (ms->nvdimms_state->is_enabled) {
-- 
2.25.1

[PATCH 3/8] tests: acpi: q35: add test for hmat nodes without initiators

2022-07-11 Thread Hesham Almatary via

From: Brice Goglin 

expected HMAT:

[000h    4]Signature : "HMAT"[Heterogeneous Memory 
Attributes Table]
[004h 0004   4] Table Length : 0120
[008h 0008   1] Revision : 02
[009h 0009   1] Checksum : 4F
[00Ah 0010   6]   Oem ID : "BOCHS "
[010h 0016   8] Oem Table ID : "BXPC"
[018h 0024   4] Oem Revision : 0001
[01Ch 0028   4]  Asl Compiler ID : "BXPC"
[020h 0032   4]Asl Compiler Revision : 0001

[024h 0036   4] Reserved : 

[028h 0040   2]   Structure Type :  [Memory Proximity Domain 
Attributes]
[02Ah 0042   2] Reserved : 
[02Ch 0044   4]   Length : 0028
[030h 0048   2]Flags (decoded below) : 0001
Processor Proximity Domain Valid : 1
[032h 0050   2]Reserved1 : 
[034h 0052   4] Attached Initiator Proximity Domain : 
[038h 0056   4]  Memory Proximity Domain : 
[03Ch 0060   4]Reserved2 : 
[040h 0064   8]Reserved3 : 
[048h 0072   8]Reserved4 : 

[050h 0080   2]   Structure Type :  [Memory Proximity Domain 
Attributes]
[052h 0082   2] Reserved : 
[054h 0084   4]   Length : 0028
[058h 0088   2]Flags (decoded below) : 0001
Processor Proximity Domain Valid : 1
[05Ah 0090   2]Reserved1 : 
[05Ch 0092   4] Attached Initiator Proximity Domain : 0001
[060h 0096   4]  Memory Proximity Domain : 0001
[064h 0100   4]Reserved2 : 
[068h 0104   8]Reserved3 : 
[070h 0112   8]Reserved4 : 

[078h 0120   2]   Structure Type :  [Memory Proximity Domain 
Attributes]
[07Ah 0122   2] Reserved : 
[07Ch 0124   4]   Length : 0028
[080h 0128   2]Flags (decoded below) : 
Processor Proximity Domain Valid : 0
[082h 0130   2]Reserved1 : 
[084h 0132   4] Attached Initiator Proximity Domain : 0080
[088h 0136   4]  Memory Proximity Domain : 0002
[08Ch 0140   4]Reserved2 : 
[090h 0144   8]Reserved3 : 
[098h 0152   8]Reserved4 : 

[0A0h 0160   2]   Structure Type : 0001 [System Locality Latency 
and Bandwidth Information]
[0A2h 0162   2] Reserved : 
[0A4h 0164   4]   Length : 0040
[0A8h 0168   1]Flags (decoded below) : 00
Memory Hierarchy : 0
[0A9h 0169   1]Data Type : 00
[0AAh 0170   2]Reserved1 : 
[0ACh 0172   4] Initiator Proximity Domains # : 0002
[0B0h 0176   4]   Target Proximity Domains # : 0003
[0B4h 0180   4]Reserved2 : 
[0B8h 0184   8]  Entry Base Unit : 2710
[0C0h 0192   4] Initiator Proximity Domain List : 
[0C4h 0196   4] Initiator Proximity Domain List : 0001
[0C8h 0200   4] Target Proximity Domain List : 
[0CCh 0204   4] Target Proximity Domain List : 0001
[0D0h 0208   4] Target Proximity Domain List : 0002
[0D4h 0212   2]Entry : 0001
[0D6h 0214   2]Entry : 0002
[0D8h 0216   2]Entry : 0003
[0DAh 0218   2]Entry : 0002
[0DCh 0220   2]Entry : 0001
[0DEh 0222   2]Entry : 0003

[0E0h 0224   2]   Structure Type : 0001 [System Locality Latency 
and Bandwidth Information]
[0E2h 0226   2] Reserved : 
[0E4h 0228   4]   Length : 0040
[0E8h 0232   1]Flags (decoded below) : 00
Memory Hierarchy : 0
[0E9h 0233   1]Data Type : 03
[0EAh 0234   2]Reserved1 : 
[0ECh 0236   4] Initiator Proximity Domains # : 0002
[0F0h 0240   4]   Target Proximity Domains # : 0003
[0F4h 0244   4]Reserved2 : 
[0F8h 0248   8]  Entry Base Unit : 0001
[100h 0256   4] Initiator Proximity Domain List : 
[104h 0260   4] Initiator Proximity Domain List : 0001
[108h 0264   4] Target Proximity Domain List : 
[10Ch 0268   4] Target Proximity Domain List : 0001
[110h 0272   4] Target Proximity Domain List : 0002
[114h 0276   2]Entry : 000A
[116h 0278   2]Entry : 0005
[118h 0280   2]Entry : 0001
[11Ah 0282   2]Entry : 0005
[11Ch 0284   2]

[PATCH 4/8] tests: acpi: q35: update expected blobs *.hmat-noinitiators

2022-07-11 Thread Hesham Almatary via

From: Brice Goglin 

expected HMAT:

[000h    4]Signature : "HMAT"[Heterogeneous Memory 
Attributes Table]
[004h 0004   4] Table Length : 0120
[008h 0008   1] Revision : 02
[009h 0009   1] Checksum : 4F
[00Ah 0010   6]   Oem ID : "BOCHS "
[010h 0016   8] Oem Table ID : "BXPC"
[018h 0024   4] Oem Revision : 0001
[01Ch 0028   4]  Asl Compiler ID : "BXPC"
[020h 0032   4]Asl Compiler Revision : 0001

[024h 0036   4] Reserved : 

[028h 0040   2]   Structure Type :  [Memory Proximity Domain 
Attributes]
[02Ah 0042   2] Reserved : 
[02Ch 0044   4]   Length : 0028
[030h 0048   2]Flags (decoded below) : 0001
Processor Proximity Domain Valid : 1
[032h 0050   2]Reserved1 : 
[034h 0052   4] Attached Initiator Proximity Domain : 
[038h 0056   4]  Memory Proximity Domain : 
[03Ch 0060   4]Reserved2 : 
[040h 0064   8]Reserved3 : 
[048h 0072   8]Reserved4 : 

[050h 0080   2]   Structure Type :  [Memory Proximity Domain 
Attributes]
[052h 0082   2] Reserved : 
[054h 0084   4]   Length : 0028
[058h 0088   2]Flags (decoded below) : 0001
Processor Proximity Domain Valid : 1
[05Ah 0090   2]Reserved1 : 
[05Ch 0092   4] Attached Initiator Proximity Domain : 0001
[060h 0096   4]  Memory Proximity Domain : 0001
[064h 0100   4]Reserved2 : 
[068h 0104   8]Reserved3 : 
[070h 0112   8]Reserved4 : 

[078h 0120   2]   Structure Type :  [Memory Proximity Domain 
Attributes]
[07Ah 0122   2] Reserved : 
[07Ch 0124   4]   Length : 0028
[080h 0128   2]Flags (decoded below) : 
Processor Proximity Domain Valid : 0
[082h 0130   2]Reserved1 : 
[084h 0132   4] Attached Initiator Proximity Domain : 0080
[088h 0136   4]  Memory Proximity Domain : 0002
[08Ch 0140   4]Reserved2 : 
[090h 0144   8]Reserved3 : 
[098h 0152   8]Reserved4 : 

[0A0h 0160   2]   Structure Type : 0001 [System Locality Latency 
and Bandwidth Information]
[0A2h 0162   2] Reserved : 
[0A4h 0164   4]   Length : 0040
[0A8h 0168   1]Flags (decoded below) : 00
Memory Hierarchy : 0
[0A9h 0169   1]Data Type : 00
[0AAh 0170   2]Reserved1 : 
[0ACh 0172   4] Initiator Proximity Domains # : 0002
[0B0h 0176   4]   Target Proximity Domains # : 0003
[0B4h 0180   4]Reserved2 : 
[0B8h 0184   8]  Entry Base Unit : 2710
[0C0h 0192   4] Initiator Proximity Domain List : 
[0C4h 0196   4] Initiator Proximity Domain List : 0001
[0C8h 0200   4] Target Proximity Domain List : 
[0CCh 0204   4] Target Proximity Domain List : 0001
[0D0h 0208   4] Target Proximity Domain List : 0002
[0D4h 0212   2]Entry : 0001
[0D6h 0214   2]Entry : 0002
[0D8h 0216   2]Entry : 0003
[0DAh 0218   2]Entry : 0002
[0DCh 0220   2]Entry : 0001
[0DEh 0222   2]Entry : 0003

[0E0h 0224   2]   Structure Type : 0001 [System Locality Latency 
and Bandwidth Information]
[0E2h 0226   2] Reserved : 
[0E4h 0228   4]   Length : 0040
[0E8h 0232   1]Flags (decoded below) : 00
Memory Hierarchy : 0
[0E9h 0233   1]Data Type : 03
[0EAh 0234   2]Reserved1 : 
[0ECh 0236   4] Initiator Proximity Domains # : 0002
[0F0h 0240   4]   Target Proximity Domains # : 0003
[0F4h 0244   4]Reserved2 : 
[0F8h 0248   8]  Entry Base Unit : 0001
[100h 0256   4] Initiator Proximity Domain List : 
[104h 0260   4] Initiator Proximity Domain List : 0001
[108h 0264   4] Target Proximity Domain List : 
[10Ch 0268   4] Target Proximity Domain List : 0001
[110h 0272   4] Target Proximity Domain List : 0002
[114h 0276   2]Entry : 000A
[116h 0278   2]Entry : 0005
[118h 0280   2]Entry : 0001
[11Ah 0282   2]Entry : 0005
[11Ch 0284   2]

[PATCH 0/8] AArch64/HMAT support and tests

2022-07-11 Thread Hesham Almatary via

This patch set adds support for AArch64/HMAT including a test.
It relies on other two patch sets from:

Brice Goglin: to support -numa without initiators on q35/x86.
  https://lore.kernel.org/all/ed23accb-2c8b-90f4-a7a3-f81cc57bf...@inria.fr/
Xiang Chen: to enable/support HMAT on AArch64.
  
https://lore.kernel.org/all/1643102134-15506-1-git-send-email-chenxian...@hisilicon.com/

I further add a test with ACPI/HMAT tables that uses the two
patch sets.

Brice Goglin (4):
  hmat acpi: Don't require initiator value in -numa
  tests: acpi: add and whitelist *.hmat-noinitiator expected blobs
  tests: acpi: q35: add test for hmat nodes without initiators
  tests: acpi: q35: update expected blobs *.hmat-noinitiators

Hesham Almatary (3):
  tests: Add HMAT AArch64/virt empty table files
  tests: acpi: aarch64/virt: add a test for hmat nodes with no
initiators
  tests: virt: Update expected *.acpihmatvirt tables

Xiang Chen (1):
  hw/arm/virt: Enable HMAT on arm virt machine

 hw/arm/Kconfig|   1 +
 hw/arm/virt-acpi-build.c  |   7 ++
 hw/core/machine.c |   4 +-
 tests/data/acpi/q35/APIC.acpihmat-noinitiator | Bin 0 -> 144 bytes
 tests/data/acpi/q35/DSDT.acpihmat-noinitiator | Bin 0 -> 8553 bytes
 tests/data/acpi/q35/FACP.acpihmat-noinitiator | Bin 0 -> 244 bytes
 tests/data/acpi/q35/HMAT.acpihmat-noinitiator | Bin 0 -> 288 bytes
 tests/data/acpi/q35/SRAT.acpihmat-noinitiator | Bin 0 -> 312 bytes
 tests/data/acpi/virt/DSDT.acpihmatvirt| Bin 0 -> 5282 bytes
 tests/data/acpi/virt/FACP.acpihmatvirt| Bin 0 -> 268 bytes
 tests/data/acpi/virt/HMAT.acpihmatvirt| Bin 0 -> 288 bytes
 tests/data/acpi/virt/SRAT.acpihmatvirt| Bin 0 -> 240 bytes
 tests/qtest/bios-tables-test.c|  99 ++
 13 files changed, 108 insertions(+), 3 deletions(-)
 create mode 100644 tests/data/acpi/q35/APIC.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/q35/DSDT.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/q35/FACP.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/q35/HMAT.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/q35/SRAT.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/virt/DSDT.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/FACP.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/HMAT.acpihmatvirt
 create mode 100644 tests/data/acpi/virt/SRAT.acpihmatvirt

-- 
2.25.1

[PATCH 1/8] hmat acpi: Don't require initiator value in -numa

2022-07-11 Thread Hesham Almatary via

From: Brice Goglin 

The "Memory Proximity Domain Attributes" structure of the ACPI HMAT
has a "Processor Proximity Domain Valid" flag that is currently
always set because Qemu -numa requires an initiator=X value
when hmat=on. Unsetting this flag allows to create more complex
memory topologies by having multiple best initiators for a single
memory target.

This patch allows -numa without initiator=X when hmat=on by keeping
the default value MAX_NODES in numa_state->nodes[i].initiator.
All places reading numa_state->nodes[i].initiator already check
whether it's different from MAX_NODES before using it.

Tested with
qemu-system-x86_64 -accel kvm \
 -machine pc,hmat=on \
 -drive if=pflash,format=raw,file=./OVMF.fd \
 -drive media=disk,format=qcow2,file=efi.qcow2 \
 -smp 4 \
 -m 3G \
 -object memory-backend-ram,size=1G,id=ram0 \
 -object memory-backend-ram,size=1G,id=ram1 \
 -object memory-backend-ram,size=1G,id=ram2 \
 -numa node,nodeid=0,memdev=ram0,cpus=0-1 \
 -numa node,nodeid=1,memdev=ram1,cpus=2-3 \
 -numa node,nodeid=2,memdev=ram2 \
 -numa 
hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,latency=10
 \
 -numa 
hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760
 \
 -numa 
hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,latency=20
 \
 -numa 
hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880
 \
 -numa 
hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,latency=30
 \
 -numa 
hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
 \
 -numa 
hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,latency=20
 \
 -numa 
hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880
 \
 -numa 
hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,latency=10
 \
 -numa 
hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760
 \
 -numa 
hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,latency=30
 \
 -numa 
hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
which reports NUMA node2 at same distance from both node0 and node1 as seen in 
lstopo:
Machine (2966MB total) + Package P#0
  NUMANode P#2 (979MB)
  Group0
NUMANode P#0 (980MB)
Core P#0 + PU P#0
Core P#1 + PU P#1
  Group0
NUMANode P#1 (1007MB)
Core P#2 + PU P#2
Core P#3 + PU P#3

Before this patch, we had to add ",initiator=X" to "-numa 
node,nodeid=2,memdev=ram2".
The lstopo output difference between initiator=1 and no initiator is:
@@ -1,10 +1,10 @@
 Machine (2966MB total) + Package P#0
+  NUMANode P#2 (979MB)
   Group0
 NUMANode P#0 (980MB)
 Core P#0 + PU P#0
 Core P#1 + PU P#1
   Group0
 NUMANode P#1 (1007MB)
-NUMANode P#2 (979MB)
 Core P#2 + PU P#2
 Core P#3 + PU P#3

Corresponding changes in the HMAT MPDA structure:
@@ -49,10 +49,10 @@
 [078h 0120   2]   Structure Type :  [Memory Proximity Domain 
Attributes]
 [07Ah 0122   2] Reserved : 
 [07Ch 0124   4]   Length : 0028
-[080h 0128   2]Flags (decoded below) : 0001
-Processor Proximity Domain Valid : 1
+[080h 0128   2]Flags (decoded below) : 
+Processor Proximity Domain Valid : 0
 [082h 0130   2]Reserved1 : 
-[084h 0132   4] Attached Initiator Proximity Domain : 0001
+[084h 0132   4] Attached Initiator Proximity Domain : 0080
 [088h 0136   4]  Memory Proximity Domain : 0002
 [08Ch 0140   4]Reserved2 : 
 [090h 0144   8]Reserved3 : 

Final HMAT SLLB structures:
[0A0h 0160   2]   Structure Type : 0001 [System Locality Latency 
and Bandwidth Information]
[0A2h 0162   2] Reserved : 
[0A4h 0164   4]   Length : 0040
[0A8h 0168   1]Flags (decoded below) : 00
Memory Hierarchy : 0
[0A9h 0169   1]Data Type : 00
[0AAh 0170   2]Reserved1 : 
[0ACh 0172   4] Initiator Proximity Domains # : 0002
[0B0h 0176   4]   Target Proximity Domains # : 0003
[0B4h 0180   4]Reserved2 : 
[0B8h 0184   8]  Entry Base Unit : 2710
[0C0h 0192   4] Initiator Proximity Domain List : 
[0C4h 0196   4] Initiator Proximity Domain List : 0001
[0C8h 0200   4] Target Proximity Domain List : 
[0CCh 0204   4] Target Proximity Domain List : 0001
[0D0h 0208   4] Target Proximity Domain List : 0002
[0D4h 0212   2]Entry : 0001
[0D6h 0214   2]Entry : 0002
[0D8h 0216   2]Entry : 0003
[0DAh 0218   2]Entry : 0002
[0DCh 0220   2]

[PATCH 2/8] tests: acpi: add and whitelist *.hmat-noinitiator expected blobs

2022-07-11 Thread Hesham Almatary via

From: Brice Goglin 

.. which will be used by follow up hmat-noinitiator test-case.

Signed-off-by: Brice Goglin 
---
 tests/data/acpi/q35/APIC.acpihmat-noinitiator | 0
 tests/data/acpi/q35/DSDT.acpihmat-noinitiator | 0
 tests/data/acpi/q35/FACP.acpihmat-noinitiator | 0
 tests/data/acpi/q35/HMAT.acpihmat-noinitiator | 0
 tests/data/acpi/q35/SRAT.acpihmat-noinitiator | 0
 tests/qtest/bios-tables-test-allowed-diff.h   | 5 +
 6 files changed, 5 insertions(+)
 create mode 100644 tests/data/acpi/q35/APIC.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/q35/DSDT.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/q35/FACP.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/q35/HMAT.acpihmat-noinitiator
 create mode 100644 tests/data/acpi/q35/SRAT.acpihmat-noinitiator

diff --git a/tests/data/acpi/q35/APIC.acpihmat-noinitiator 
b/tests/data/acpi/q35/APIC.acpihmat-noinitiator
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/data/acpi/q35/DSDT.acpihmat-noinitiator 
b/tests/data/acpi/q35/DSDT.acpihmat-noinitiator
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/data/acpi/q35/FACP.acpihmat-noinitiator 
b/tests/data/acpi/q35/FACP.acpihmat-noinitiator
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/data/acpi/q35/HMAT.acpihmat-noinitiator 
b/tests/data/acpi/q35/HMAT.acpihmat-noinitiator
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/data/acpi/q35/SRAT.acpihmat-noinitiator 
b/tests/data/acpi/q35/SRAT.acpihmat-noinitiator
new file mode 100644
index 00..e69de29bb2
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..ae025e3a3e 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,6 @@
 /* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/APIC.acpihmat-noinitiator",
+"tests/data/acpi/q35/DSDT.acpihmat-noinitiator",
+"tests/data/acpi/q35/FACP.acpihmat-noinitiator",
+"tests/data/acpi/q35/HMAT.acpihmat-noinitiator",
+"tests/data/acpi/q35/SRAT.acpihmat-noinitiator",
-- 
2.25.1

[Qemu-devel] [PATCHv4 5/6] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off

2019-06-27 Thread Hesham Almatary

The current implementation returns 1 (PMP check success) if the address is in
range even if the PMP entry is off. This is a bug.

For example, if there is a PMP check in S-Mode which is in range, but its PMP
entry is off, this will succeed, which it should not.

The patch fixes this bug by only checking the PMP permissions if the address is
in range and its corresponding PMP entry it not off. Otherwise, it will keep
the ret = -1 which will be checked and handled correctly at the end of the
function.

Signed-off-by: Hesham Almatary 
Reviewed-by: Alistair Francis 
---
 target/riscv/pmp.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 89170bc11d..0a8e7a2dc4 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -259,11 +259,12 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong 
addr,
 /* fully inside */
 const uint8_t a_field =
 pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
-if ((s + e) == 2) {
-if (PMP_AMATCH_OFF == a_field) {
-return 1;
-}

+/*
+ * If the PMP entry is not off and the address is in range, do the priv
+ * check
+ */
+if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
 allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
 if ((mode != PRV_M) || pmp_is_locked(env, i)) {
 allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
--
2.17.1

[Qemu-devel] [PATCHv4 6/6] RISC-V: Fix a PMP check with the correct access size

2019-06-27 Thread Hesham Almatary

The PMP check should be of the memory access size rather
than TARGET_PAGE_SIZE.

Signed-off-by: Hesham Almatary 
Reviewed-by: Alistair Francis 
---
 target/riscv/cpu_helper.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 00bc4f1712..64c12d83dc 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -417,8 +417,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,

 if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 (ret == TRANSLATE_SUCCESS) &&
-!pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type,
-mode)) {
+!pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
 ret = TRANSLATE_PMP_FAIL;
 }
 if (ret == TRANSLATE_PMP_FAIL) {
--
2.17.1

[Qemu-devel] [PATCHv4 3/6] RISC-V: Check for the effective memory privilege mode during PMP checks

2019-06-27 Thread Hesham Almatary

The current PMP check function checks for env->priv which is not the effective
memory privilege mode.

For example, mstatus.MPRV could be set while executing in M-Mode, and in that
case the privilege mode for the PMP check should be S-Mode rather than M-Mode
(in env->priv) if mstatus.MPP == PRV_S.

This patch passes the effective memory privilege mode to the PMP check.
Functions that call the PMP check should pass the correct memory privilege mode
after reading mstatus' MPRV/MPP or hstatus.SPRV (if Hypervisor mode exists).

Suggested-by: Alistair Francis 
Signed-off-by: Hesham Almatary 
---
 target/riscv/cpu_helper.c | 10 +-
 target/riscv/pmp.c|  6 +++---
 target/riscv/pmp.h|  2 +-
 3 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 7c7282c680..5a1cd7cf96 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -392,19 +392,27 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 int prot;
 bool pmp_violation = false;
 int ret = TRANSLATE_FAIL;
+int mode = mmu_idx;

 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
   __func__, address, access_type, mmu_idx);

 ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx);

+if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+if (get_field(env->mstatus, MSTATUS_MPRV)) {
+mode = get_field(env->mstatus, MSTATUS_MPP);
+}
+}
+
 qemu_log_mask(CPU_LOG_MMU,
   "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
   " prot %d\n", __func__, address, ret, pa, prot);

 if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 (ret == TRANSLATE_SUCCESS) &&
-!pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) {
+!pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type,
+mode)) {
 pmp_violation = true;
 ret = TRANSLATE_FAIL;
 }
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index b11c4ae22f..89170bc11d 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -229,7 +229,7 @@ static int pmp_is_in_range(CPURISCVState *env, int 
pmp_index, target_ulong addr)
  * Check if the address has required RWX privs to complete desired operation
  */
 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-target_ulong size, pmp_priv_t privs)
+target_ulong size, pmp_priv_t privs, target_ulong mode)
 {
 int i = 0;
 int ret = -1;
@@ -265,7 +265,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong 
addr,
 }

 allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
-if ((env->priv != PRV_M) || pmp_is_locked(env, i)) {
+if ((mode != PRV_M) || pmp_is_locked(env, i)) {
 allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
 }

@@ -281,7 +281,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong 
addr,

 /* No rule matched */
 if (ret == -1) {
-if (env->priv == PRV_M) {
+if (mode == PRV_M) {
 ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
   * M-Mode access, the access succeeds */
 } else {
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index 66790950eb..8e19793132 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -59,6 +59,6 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t 
addr_index,
 target_ulong val);
 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-target_ulong size, pmp_priv_t priv);
+target_ulong size, pmp_priv_t priv, target_ulong mode);

 #endif
--
2.17.1

[Qemu-devel] [PATCHv4 1/6] RISC-V: Only Check PMP if MMU translation succeeds

2019-06-27 Thread Hesham Almatary

The current implementation unnecessarily checks for PMP even if MMU translation
failed. This may trigger a wrong PMP access exception instead of
a page exception.

For example, the very first instruction fetched after the first satp write in
S-Mode will trigger a PMP access fault instead of an instruction fetch page
fault.

This patch prioritises MMU exceptions over PMP exceptions and only checks for
PMP if MMU translation succeeds. This patch is required for future commits
that properly report PMP exception violations if PTW succeeds.

Signed-off-by: Hesham Almatary 
Reviewed-by: Alistair Francis 
---
 target/riscv/cpu_helper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 41d6db41c3..40fb47e794 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -401,6 +401,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
   " prot %d\n", __func__, address, ret, pa, prot);

 if (riscv_feature(env, RISCV_FEATURE_PMP) &&
+(ret == TRANSLATE_SUCCESS) &&
 !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) {
 ret = TRANSLATE_FAIL;
 }
--
2.17.1

[Qemu-devel] [PATCHv4 4/6] RISC-V: Check PMP during Page Table Walks

2019-06-27 Thread Hesham Almatary

The PMP should be checked when doing a page table walk, and report access
fault exception if the to-be-read PTE failed the PMP check.

Suggested-by: Jonathan Behrens 
Signed-off-by: Hesham Almatary 
Reviewed-by: Alistair Francis 
---
 target/riscv/cpu.h|  1 +
 target/riscv/cpu_helper.c | 10 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c17184f4e4..ab3ba3f15a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -94,6 +94,7 @@ enum {
 #define PRIV_VERSION_1_09_1 0x00010901
 #define PRIV_VERSION_1_10_0 0x00011000

+#define TRANSLATE_PMP_FAIL 2
 #define TRANSLATE_FAIL 1
 #define TRANSLATE_SUCCESS 0
 #define NB_MMU_MODES 4
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 5a1cd7cf96..00bc4f1712 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -211,6 +211,12 @@ restart:

 /* check that physical address of PTE is legal */
 target_ulong pte_addr = base + idx * ptesize;
+
+if (riscv_feature(env, RISCV_FEATURE_PMP) &&
+!pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
+1 << MMU_DATA_LOAD, PRV_S)) {
+return TRANSLATE_PMP_FAIL;
+}
 #if defined(TARGET_RISCV32)
 target_ulong pte = ldl_phys(cs->as, pte_addr);
 #elif defined(TARGET_RISCV64)
@@ -413,8 +419,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 (ret == TRANSLATE_SUCCESS) &&
 !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type,
 mode)) {
+ret = TRANSLATE_PMP_FAIL;
+}
+if (ret == TRANSLATE_PMP_FAIL) {
 pmp_violation = true;
-ret = TRANSLATE_FAIL;
 }
 if (ret == TRANSLATE_SUCCESS) {
 tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
--
2.17.1

[Qemu-devel] [PATCHv4 2/6] RISC-V: Raise access fault exceptions on PMP violations

2019-06-27 Thread Hesham Almatary

Section 3.6 in RISC-V v1.10 privilege specification states that PMP violations
report "access exceptions." The current PMP implementation has
a bug which wrongly reports "page exceptions" on PMP violations.

This patch fixes this bug by reporting the correct PMP access exceptions
trap values.

Signed-off-by: Hesham Almatary 
Reviewed-by: Alistair Francis 
---
 target/riscv/cpu_helper.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 40fb47e794..7c7282c680 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -318,12 +318,13 @@ restart:
 }

 static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
-MMUAccessType access_type)
+MMUAccessType access_type, bool pmp_violation)
 {
 CPUState *cs = CPU(riscv_env_get_cpu(env));
 int page_fault_exceptions =
 (env->priv_ver >= PRIV_VERSION_1_10_0) &&
-get_field(env->satp, SATP_MODE) != VM_1_10_MBARE;
+get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
+!pmp_violation;
 switch (access_type) {
 case MMU_INST_FETCH:
 cs->exception_index = page_fault_exceptions ?
@@ -389,6 +390,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 CPURISCVState *env = &cpu->env;
 hwaddr pa = 0;
 int prot;
+bool pmp_violation = false;
 int ret = TRANSLATE_FAIL;

 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
@@ -403,6 +405,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 (ret == TRANSLATE_SUCCESS) &&
 !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) {
+pmp_violation = true;
 ret = TRANSLATE_FAIL;
 }
 if (ret == TRANSLATE_SUCCESS) {
@@ -412,7 +415,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 } else if (probe) {
 return false;
 } else {
-raise_mmu_exception(env, address, access_type);
+raise_mmu_exception(env, address, access_type, pmp_violation);
 riscv_raise_exception(env, cs->exception_index, retaddr);
 }
 #else
--
2.17.1

Re: [Qemu-devel] [PATCHv4 4/6] RISC-V: Check PMP during Page Table Walks

2019-06-05 Thread Hesham Almatary

On Wed, 5 Jun 2019 at 23:07, Alistair Francis  wrote:
>
> On Thu, May 30, 2019 at 6:52 AM Hesham Almatary
>  wrote:
> >
> > The PMP should be checked when doing a page table walk, and report access
> > fault exception if the to-be-read PTE failed the PMP check.
> >
> > Suggested-by: Jonathan Behrens 
> > Signed-off-by: Hesham Almatary 
> > ---
> >  target/riscv/cpu.h|  1 +
> >  target/riscv/cpu_helper.c | 10 +-
> >  2 files changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index c17184f4e4..ab3ba3f15a 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -94,6 +94,7 @@ enum {
> >  #define PRIV_VERSION_1_09_1 0x00010901
> >  #define PRIV_VERSION_1_10_0 0x00011000
> >
> > +#define TRANSLATE_PMP_FAIL 2
> >  #define TRANSLATE_FAIL 1
> >  #define TRANSLATE_SUCCESS 0
> >  #define NB_MMU_MODES 4
> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> > index 5a1cd7cf96..00bc4f1712 100644
> > --- a/target/riscv/cpu_helper.c
> > +++ b/target/riscv/cpu_helper.c
> > @@ -211,6 +211,12 @@ restart:
> >
> >  /* check that physical address of PTE is legal */
> >  target_ulong pte_addr = base + idx * ptesize;
> > +
> > +if (riscv_feature(env, RISCV_FEATURE_PMP) &&
> > +!pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
> > +1 << MMU_DATA_LOAD, PRV_S)) {
>
> Shouldn't we be passing mode in here?
>
I actually thought this way at the start. But then I made it PRV_S for
intentionality; as in PTW (in the current master, without hypervisor
extensions) always goes under PMP protection in S-Mode.
This also aligns with Spike implementation here [1].

[1] 
https://github.com/riscv/riscv-isa-sim/blob/8ac902f6ff877e976af434bfe8fa8445930174a1/riscv/mmu.cc#L288


> Alistair
>
> > +return TRANSLATE_PMP_FAIL;
> > +}
> >  #if defined(TARGET_RISCV32)
> >  target_ulong pte = ldl_phys(cs->as, pte_addr);
> >  #elif defined(TARGET_RISCV64)
> > @@ -413,8 +419,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, 
> > int size,
> >  (ret == TRANSLATE_SUCCESS) &&
> >  !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type,
> >  mode)) {
> > +ret = TRANSLATE_PMP_FAIL;
> > +}
> > +if (ret == TRANSLATE_PMP_FAIL) {
> >  pmp_violation = true;
> > -ret = TRANSLATE_FAIL;
> >  }
> >  if (ret == TRANSLATE_SUCCESS) {
> >  tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
> > --
> > 2.17.1
> >
> >

[Qemu-devel] [PATCHv4 6/6] RISC-V: Fix a PMP check with the correct access size

2019-05-30 Thread Hesham Almatary

The PMP check should be of the memory access size rather
than TARGET_PAGE_SIZE.

Signed-off-by: Hesham Almatary 
Reviewed-by: Alistair Francis 
---
 target/riscv/cpu_helper.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 00bc4f1712..64c12d83dc 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -417,8 +417,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,

 if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 (ret == TRANSLATE_SUCCESS) &&
-!pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type,
-mode)) {
+!pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
 ret = TRANSLATE_PMP_FAIL;
 }
 if (ret == TRANSLATE_PMP_FAIL) {
--
2.17.1

[Qemu-devel] [PATCHv4 5/6] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off

2019-05-30 Thread Hesham Almatary

The current implementation returns 1 (PMP check success) if the address is in
range even if the PMP entry is off. This is a bug.

For example, if there is a PMP check in S-Mode which is in range, but its PMP
entry is off, this will succeed, which it should not.

The patch fixes this bug by only checking the PMP permissions if the address is
in range and its corresponding PMP entry it not off. Otherwise, it will keep
the ret = -1 which will be checked and handled correctly at the end of the
function.

Signed-off-by: Hesham Almatary 
Reviewed-by: Alistair Francis 
---
 target/riscv/pmp.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 89170bc11d..0a8e7a2dc4 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -259,11 +259,12 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong 
addr,
 /* fully inside */
 const uint8_t a_field =
 pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
-if ((s + e) == 2) {
-if (PMP_AMATCH_OFF == a_field) {
-return 1;
-}

+/*
+ * If the PMP entry is not off and the address is in range, do the priv
+ * check
+ */
+if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
 allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
 if ((mode != PRV_M) || pmp_is_locked(env, i)) {
 allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
--
2.17.1

[Qemu-devel] [PATCHv4 1/6] RISC-V: Only Check PMP if MMU translation succeeds

2019-05-30 Thread Hesham Almatary

The current implementation unnecessarily checks for PMP even if MMU translation
failed. This may trigger a wrong PMP access exception instead of
a page exception.

For example, the very first instruction fetched after the first satp write in
S-Mode will trigger a PMP access fault instead of an instruction fetch page
fault.

This patch prioritises MMU exceptions over PMP exceptions and only checks for
PMP if MMU translation succeeds. This patch is required for future commits
that properly report PMP exception violations if PTW succeeds.

Signed-off-by: Hesham Almatary 
Reviewed-by: Alistair Francis 
---
 target/riscv/cpu_helper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 41d6db41c3..40fb47e794 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -401,6 +401,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
   " prot %d\n", __func__, address, ret, pa, prot);

 if (riscv_feature(env, RISCV_FEATURE_PMP) &&
+(ret == TRANSLATE_SUCCESS) &&
 !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) {
 ret = TRANSLATE_FAIL;
 }
--
2.17.1

[Qemu-devel] [PATCHv4 2/6] RISC-V: Raise access fault exceptions on PMP violations

2019-05-30 Thread Hesham Almatary

Section 3.6 in RISC-V v1.10 privilege specification states that PMP violations
report "access exceptions." The current PMP implementation has
a bug which wrongly reports "page exceptions" on PMP violations.

This patch fixes this bug by reporting the correct PMP access exceptions
trap values.

Signed-off-by: Hesham Almatary 
Reviewed-by: Alistair Francis 
---
 target/riscv/cpu_helper.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 40fb47e794..7c7282c680 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -318,12 +318,13 @@ restart:
 }

 static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
-MMUAccessType access_type)
+MMUAccessType access_type, bool pmp_violation)
 {
 CPUState *cs = CPU(riscv_env_get_cpu(env));
 int page_fault_exceptions =
 (env->priv_ver >= PRIV_VERSION_1_10_0) &&
-get_field(env->satp, SATP_MODE) != VM_1_10_MBARE;
+get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
+!pmp_violation;
 switch (access_type) {
 case MMU_INST_FETCH:
 cs->exception_index = page_fault_exceptions ?
@@ -389,6 +390,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 CPURISCVState *env = &cpu->env;
 hwaddr pa = 0;
 int prot;
+bool pmp_violation = false;
 int ret = TRANSLATE_FAIL;

 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
@@ -403,6 +405,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 (ret == TRANSLATE_SUCCESS) &&
 !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) {
+pmp_violation = true;
 ret = TRANSLATE_FAIL;
 }
 if (ret == TRANSLATE_SUCCESS) {
@@ -412,7 +415,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 } else if (probe) {
 return false;
 } else {
-raise_mmu_exception(env, address, access_type);
+raise_mmu_exception(env, address, access_type, pmp_violation);
 riscv_raise_exception(env, cs->exception_index, retaddr);
 }
 #else
--
2.17.1

[Qemu-devel] [PATCHv4 4/6] RISC-V: Check PMP during Page Table Walks

2019-05-30 Thread Hesham Almatary

The PMP should be checked when doing a page table walk, and report access
fault exception if the to-be-read PTE failed the PMP check.

Suggested-by: Jonathan Behrens 
Signed-off-by: Hesham Almatary 
---
 target/riscv/cpu.h|  1 +
 target/riscv/cpu_helper.c | 10 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c17184f4e4..ab3ba3f15a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -94,6 +94,7 @@ enum {
 #define PRIV_VERSION_1_09_1 0x00010901
 #define PRIV_VERSION_1_10_0 0x00011000

+#define TRANSLATE_PMP_FAIL 2
 #define TRANSLATE_FAIL 1
 #define TRANSLATE_SUCCESS 0
 #define NB_MMU_MODES 4
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 5a1cd7cf96..00bc4f1712 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -211,6 +211,12 @@ restart:

 /* check that physical address of PTE is legal */
 target_ulong pte_addr = base + idx * ptesize;
+
+if (riscv_feature(env, RISCV_FEATURE_PMP) &&
+!pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
+1 << MMU_DATA_LOAD, PRV_S)) {
+return TRANSLATE_PMP_FAIL;
+}
 #if defined(TARGET_RISCV32)
 target_ulong pte = ldl_phys(cs->as, pte_addr);
 #elif defined(TARGET_RISCV64)
@@ -413,8 +419,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 (ret == TRANSLATE_SUCCESS) &&
 !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type,
 mode)) {
+ret = TRANSLATE_PMP_FAIL;
+}
+if (ret == TRANSLATE_PMP_FAIL) {
 pmp_violation = true;
-ret = TRANSLATE_FAIL;
 }
 if (ret == TRANSLATE_SUCCESS) {
 tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
--
2.17.1

[Qemu-devel] [PATCHv4 3/6] RISC-V: Check for the effective memory privilege mode during PMP checks

2019-05-30 Thread Hesham Almatary

The current PMP check function checks for env->priv which is not the effective
memory privilege mode.

For example, mstatus.MPRV could be set while executing in M-Mode, and in that
case the privilege mode for the PMP check should be S-Mode rather than M-Mode
(in env->priv) if mstatus.MPP == PRV_S.

This patch passes the effective memory privilege mode to the PMP check.
Functions that call the PMP check should pass the correct memory privilege mode
after reading mstatus' MPRV/MPP or hstatus.SPRV (if Hypervisor mode exists).

Suggested-by: Alistair Francis 
Signed-off-by: Hesham Almatary 
---
 target/riscv/cpu_helper.c | 10 +-
 target/riscv/pmp.c|  6 +++---
 target/riscv/pmp.h|  2 +-
 3 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 7c7282c680..5a1cd7cf96 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -392,19 +392,27 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 int prot;
 bool pmp_violation = false;
 int ret = TRANSLATE_FAIL;
+int mode = mmu_idx;

 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
   __func__, address, access_type, mmu_idx);

 ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx);

+if (mode == PRV_M && access_type != MMU_INST_FETCH) {
+if (get_field(env->mstatus, MSTATUS_MPRV)) {
+mode = get_field(env->mstatus, MSTATUS_MPP);
+}
+}
+
 qemu_log_mask(CPU_LOG_MMU,
   "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
   " prot %d\n", __func__, address, ret, pa, prot);

 if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 (ret == TRANSLATE_SUCCESS) &&
-!pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) {
+!pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type,
+mode)) {
 pmp_violation = true;
 ret = TRANSLATE_FAIL;
 }
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index b11c4ae22f..89170bc11d 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -229,7 +229,7 @@ static int pmp_is_in_range(CPURISCVState *env, int 
pmp_index, target_ulong addr)
  * Check if the address has required RWX privs to complete desired operation
  */
 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-target_ulong size, pmp_priv_t privs)
+target_ulong size, pmp_priv_t privs, target_ulong mode)
 {
 int i = 0;
 int ret = -1;
@@ -265,7 +265,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong 
addr,
 }

 allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
-if ((env->priv != PRV_M) || pmp_is_locked(env, i)) {
+if ((mode != PRV_M) || pmp_is_locked(env, i)) {
 allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
 }

@@ -281,7 +281,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong 
addr,

 /* No rule matched */
 if (ret == -1) {
-if (env->priv == PRV_M) {
+if (mode == PRV_M) {
 ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
   * M-Mode access, the access succeeds */
 } else {
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index 66790950eb..8e19793132 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -59,6 +59,6 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t 
addr_index,
 target_ulong val);
 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-target_ulong size, pmp_priv_t priv);
+target_ulong size, pmp_priv_t priv, target_ulong mode);

 #endif
--
2.17.1

Re: [Qemu-devel] [PATCHv3 3/5] RISC-V: Check PMP during Page Table Walks

2019-05-30 Thread Hesham Almatary

On Thu, 30 May 2019 at 05:07, Alistair Francis  wrote:
>
> On Wed, May 22, 2019 at 2:27 AM Hesham Almatary
>  wrote:
> >
> > On Tue, 21 May 2019 at 23:40, Alistair Francis  wrote:
> > >
> > > On Tue, May 21, 2019 at 3:44 AM Hesham Almatary
> > >  wrote:
> > > >
> > > > The PMP should be checked when doing a page table walk, and report 
> > > > access
> > > > fault exception if the to-be-read PTE failed the PMP check.
> > > >
> > > > Suggested-by: Jonathan Behrens 
> > > > Signed-off-by: Hesham Almatary 
> > > > ---
> > > >  target/riscv/cpu.h|  1 +
> > > >  target/riscv/cpu_helper.c | 10 +-
> > > >  2 files changed, 10 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > > > index c17184f4e4..ab3ba3f15a 100644
> > > > --- a/target/riscv/cpu.h
> > > > +++ b/target/riscv/cpu.h
> > > > @@ -94,6 +94,7 @@ enum {
> > > >  #define PRIV_VERSION_1_09_1 0x00010901
> > > >  #define PRIV_VERSION_1_10_0 0x00011000
> > > >
> > > > +#define TRANSLATE_PMP_FAIL 2
> > > >  #define TRANSLATE_FAIL 1
> > > >  #define TRANSLATE_SUCCESS 0
> > > >  #define NB_MMU_MODES 4
> > > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> > > > index 7c7282c680..d0b0f9cf88 100644
> > > > --- a/target/riscv/cpu_helper.c
> > > > +++ b/target/riscv/cpu_helper.c
> > > > @@ -211,6 +211,12 @@ restart:
> > > >
> > > >  /* check that physical address of PTE is legal */
> > > >  target_ulong pte_addr = base + idx * ptesize;
> > > > +
> > > > +if (riscv_feature(env, RISCV_FEATURE_PMP) &&
> > > > +!pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
> > > > +1 << MMU_DATA_LOAD)) {
> > >
> > > I see a problem here.
> > >
> > > pmp_hart_has_privs() checks permissions based on the current value of
> > > env->priv. This might not always be the correct permissions to check,
> > > we should instead use the current mode to check permissions.
> > >
> > That is not clear to me. Isn't env->priv the current privildge mode?
> > Could you please elaborate on what other cases this might not be the case?
>
> Sorry for the delay. The RISC-V Hypervisor Extension allows load/store
> operations to be carried out as a previous privilege. The mstatus.MPRV
> and hstatus.SPRV allow this.
>
No problem, thanks for the clarification.
You are right, I haven't considered MPRV. I fixed that in a separate
commit in a v4 series of patches.
> Alistair
>
> >
> > > The best way to do this to me is to probably provide a privileged mode
> > > override to the function, can you add that?
> > >
> > > Alistair
> > >
> > > > +return TRANSLATE_PMP_FAIL;
> > > > +}
> > > >  #if defined(TARGET_RISCV32)
> > > >  target_ulong pte = ldl_phys(cs->as, pte_addr);
> > > >  #elif defined(TARGET_RISCV64)
> > > > @@ -405,8 +411,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr 
> > > > address, int size,
> > > >  if (riscv_feature(env, RISCV_FEATURE_PMP) &&
> > > >  (ret == TRANSLATE_SUCCESS) &&
> > > >  !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << 
> > > > access_type)) {
> > > > +ret = TRANSLATE_PMP_FAIL;
> > > > +}
> > > > +if (ret == TRANSLATE_PMP_FAIL) {
> > > >  pmp_violation = true;
> > > > -ret = TRANSLATE_FAIL;
> > > >  }
> > > >  if (ret == TRANSLATE_SUCCESS) {
> > > >  tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & 
> > > > TARGET_PAGE_MASK,
> > > > --
> > > > 2.17.1
> > > >
> > > >

Re: [Qemu-devel] [PATCHv3 3/5] RISC-V: Check PMP during Page Table Walks

2019-05-29 Thread Hesham Almatary

ping

On Wed, 22 May 2019 at 11:26, Hesham Almatary
 wrote:
>
> On Tue, 21 May 2019 at 23:40, Alistair Francis  wrote:
> >
> > On Tue, May 21, 2019 at 3:44 AM Hesham Almatary
> >  wrote:
> > >
> > > The PMP should be checked when doing a page table walk, and report access
> > > fault exception if the to-be-read PTE failed the PMP check.
> > >
> > > Suggested-by: Jonathan Behrens 
> > > Signed-off-by: Hesham Almatary 
> > > ---
> > >  target/riscv/cpu.h|  1 +
> > >  target/riscv/cpu_helper.c | 10 +-
> > >  2 files changed, 10 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > > index c17184f4e4..ab3ba3f15a 100644
> > > --- a/target/riscv/cpu.h
> > > +++ b/target/riscv/cpu.h
> > > @@ -94,6 +94,7 @@ enum {
> > >  #define PRIV_VERSION_1_09_1 0x00010901
> > >  #define PRIV_VERSION_1_10_0 0x00011000
> > >
> > > +#define TRANSLATE_PMP_FAIL 2
> > >  #define TRANSLATE_FAIL 1
> > >  #define TRANSLATE_SUCCESS 0
> > >  #define NB_MMU_MODES 4
> > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> > > index 7c7282c680..d0b0f9cf88 100644
> > > --- a/target/riscv/cpu_helper.c
> > > +++ b/target/riscv/cpu_helper.c
> > > @@ -211,6 +211,12 @@ restart:
> > >
> > >  /* check that physical address of PTE is legal */
> > >  target_ulong pte_addr = base + idx * ptesize;
> > > +
> > > +if (riscv_feature(env, RISCV_FEATURE_PMP) &&
> > > +!pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
> > > +1 << MMU_DATA_LOAD)) {
> >
> > I see a problem here.
> >
> > pmp_hart_has_privs() checks permissions based on the current value of
> > env->priv. This might not always be the correct permissions to check,
> > we should instead use the current mode to check permissions.
> >
> That is not clear to me. Isn't env->priv the current privildge mode?
> Could you please elaborate on what other cases this might not be the case?
>
> > The best way to do this to me is to probably provide a privileged mode
> > override to the function, can you add that?
> >
> > Alistair
> >
> > > +return TRANSLATE_PMP_FAIL;
> > > +}
> > >  #if defined(TARGET_RISCV32)
> > >  target_ulong pte = ldl_phys(cs->as, pte_addr);
> > >  #elif defined(TARGET_RISCV64)
> > > @@ -405,8 +411,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, 
> > > int size,
> > >  if (riscv_feature(env, RISCV_FEATURE_PMP) &&
> > >  (ret == TRANSLATE_SUCCESS) &&
> > >  !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << 
> > > access_type)) {
> > > +ret = TRANSLATE_PMP_FAIL;
> > > +}
> > > +if (ret == TRANSLATE_PMP_FAIL) {
> > >  pmp_violation = true;
> > > -ret = TRANSLATE_FAIL;
> > >  }
> > >  if (ret == TRANSLATE_SUCCESS) {
> > >  tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & 
> > > TARGET_PAGE_MASK,
> > > --
> > > 2.17.1
> > >
> > >

Re: [Qemu-devel] [PATCHv3 3/5] RISC-V: Check PMP during Page Table Walks

2019-05-22 Thread Hesham Almatary

On Tue, 21 May 2019 at 23:40, Alistair Francis  wrote:
>
> On Tue, May 21, 2019 at 3:44 AM Hesham Almatary
>  wrote:
> >
> > The PMP should be checked when doing a page table walk, and report access
> > fault exception if the to-be-read PTE failed the PMP check.
> >
> > Suggested-by: Jonathan Behrens 
> > Signed-off-by: Hesham Almatary 
> > ---
> >  target/riscv/cpu.h|  1 +
> >  target/riscv/cpu_helper.c | 10 +-
> >  2 files changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index c17184f4e4..ab3ba3f15a 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -94,6 +94,7 @@ enum {
> >  #define PRIV_VERSION_1_09_1 0x00010901
> >  #define PRIV_VERSION_1_10_0 0x00011000
> >
> > +#define TRANSLATE_PMP_FAIL 2
> >  #define TRANSLATE_FAIL 1
> >  #define TRANSLATE_SUCCESS 0
> >  #define NB_MMU_MODES 4
> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> > index 7c7282c680..d0b0f9cf88 100644
> > --- a/target/riscv/cpu_helper.c
> > +++ b/target/riscv/cpu_helper.c
> > @@ -211,6 +211,12 @@ restart:
> >
> >  /* check that physical address of PTE is legal */
> >  target_ulong pte_addr = base + idx * ptesize;
> > +
> > +if (riscv_feature(env, RISCV_FEATURE_PMP) &&
> > +!pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
> > +1 << MMU_DATA_LOAD)) {
>
> I see a problem here.
>
> pmp_hart_has_privs() checks permissions based on the current value of
> env->priv. This might not always be the correct permissions to check,
> we should instead use the current mode to check permissions.
>
That is not clear to me. Isn't env->priv the current privildge mode?
Could you please elaborate on what other cases this might not be the case?

> The best way to do this to me is to probably provide a privileged mode
> override to the function, can you add that?
>
> Alistair
>
> > +return TRANSLATE_PMP_FAIL;
> > +}
> >  #if defined(TARGET_RISCV32)
> >  target_ulong pte = ldl_phys(cs->as, pte_addr);
> >  #elif defined(TARGET_RISCV64)
> > @@ -405,8 +411,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, 
> > int size,
> >  if (riscv_feature(env, RISCV_FEATURE_PMP) &&
> >  (ret == TRANSLATE_SUCCESS) &&
> >  !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) {
> > +ret = TRANSLATE_PMP_FAIL;
> > +}
> > +if (ret == TRANSLATE_PMP_FAIL) {
> >  pmp_violation = true;
> > -ret = TRANSLATE_FAIL;
> >  }
> >  if (ret == TRANSLATE_SUCCESS) {
> >  tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
> > --
> > 2.17.1
> >
> >

[Qemu-devel] [PATCHv3 1/5] RISC-V: Only Check PMP if MMU translation succeeds

2019-05-22 Thread Hesham Almatary

The current implementation unnecessarily checks for PMP even if MMU translation
failed. This may trigger a wrong PMP access exception instead of
a page exception.

For example, the very first instruction fetched after the first satp write in
S-Mode will trigger a PMP access fault instead of an instruction fetch page
fault.

This patch prioritises MMU exceptions over PMP exceptions and only checks for
PMP if MMU translation succeeds. This patch is required for future commits
that properly report PMP exception violations if PTW succeeds.

Signed-off-by: Hesham Almatary 
---
 target/riscv/cpu_helper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 41d6db41c3..40fb47e794 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -401,6 +401,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
   " prot %d\n", __func__, address, ret, pa, prot);

 if (riscv_feature(env, RISCV_FEATURE_PMP) &&
+(ret == TRANSLATE_SUCCESS) &&
 !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) {
 ret = TRANSLATE_FAIL;
 }
--
2.17.1

[Qemu-devel] [PATCHv3 4/5] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off

2019-05-22 Thread Hesham Almatary

The current implementation returns 1 (PMP check success) if the address is in
range even if the PMP entry is off. This is a bug.

For example, if there is a PMP check in S-Mode which is in range, but its PMP
entry is off, this will succeed, which it should not.

The patch fixes this bug by only checking the PMP permissions if the address is
in range and its corresponding PMP entry it not off. Otherwise, it will keep
the ret = -1 which will be checked and handled correctly at the end of the
function.

Signed-off-by: Hesham Almatary 
Reviewed-by: Alistair Francis 
---
 target/riscv/pmp.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index b11c4ae22f..8668f0dd7c 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -259,11 +259,12 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong 
addr,
 /* fully inside */
 const uint8_t a_field =
 pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
-if ((s + e) == 2) {
-if (PMP_AMATCH_OFF == a_field) {
-return 1;
-}

+/*
+ * If the PMP entry is not off and the address is in range, do the priv
+ * check
+ */
+if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
 allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
 if ((env->priv != PRV_M) || pmp_is_locked(env, i)) {
 allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
--
2.17.1

Re: [Qemu-devel] [Qemu-riscv] [PATCHv3 5/5] RISC-V: Fix a PMP check with the correct access size

2019-05-22 Thread Hesham Almatary

On Wed, 22 May 2019 at 03:25, Jonathan Behrens  wrote:
>
> Hesham,
>
> I don't think this is quite right. If I understand correctly, PMP permissions 
> are only validated on TLB fills, not on all accesses. (Is anyone able to 
> confirm this?) If so, this function can't just validate the range of a single 
> access and then place the entire page into the TLB. However, the current code 
> is also wrong because an access should succeed/fail based on the permissions 
> only for the range it actually touches even regardless of the permissions on 
> the rest of the page. Now that I think about it, I'd also expect that 
> somewhere in the PMP logic would flush the TLB every time any of the related 
> control registers change though I can't find anywhere that this is 
> happening...
>
I believe the TLB fill function is called on all accesses, but I might
be wrong. I will wait for someone to confirm otherwise.

It's mentioned in the spec that sfence.vma has to be executed after
changing PMP configs, so it's a SW concern (i.e., not QEMU's).

> Sorry to keep raising complaints about this patch set, the interaction 
> between physical memory protection and paging is very subtle. Even some real 
> hardware has had errata related to it!
>
> Jonathan
>
> On Tue, May 21, 2019 at 6:33 PM Alistair Francis  wrote:
>>
>> On Tue, May 21, 2019 at 3:45 AM Hesham Almatary
>>  wrote:
>> >
>> > The PMP check should be of the memory access size rather
>> > than TARGET_PAGE_SIZE.
>> >
>> > Signed-off-by: Hesham Almatary 
>>
>> Reviewed-by: Alistair Francis 
>>
>> Alistair
>>
>> > ---
>> >  target/riscv/cpu_helper.c | 2 +-
>> >  1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>> > index d0b0f9cf88..ce1f47e4e3 100644
>> > --- a/target/riscv/cpu_helper.c
>> > +++ b/target/riscv/cpu_helper.c
>> > @@ -410,7 +410,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, 
>> > int size,
>> >
>> >  if (riscv_feature(env, RISCV_FEATURE_PMP) &&
>> >  (ret == TRANSLATE_SUCCESS) &&
>> > -!pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) 
>> > {
>> > +!pmp_hart_has_privs(env, pa, size, 1 << access_type)) {
>> >  ret = TRANSLATE_PMP_FAIL;
>> >  }
>> >  if (ret == TRANSLATE_PMP_FAIL) {
>> > --
>> > 2.17.1
>> >
>> >
>>

[Qemu-devel] [PATCHv3 4/5] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off

2019-05-21 Thread Hesham Almatary

The current implementation returns 1 (PMP check success) if the address is in
range even if the PMP entry is off. This is a bug.

For example, if there is a PMP check in S-Mode which is in range, but its PMP
entry is off, this will succeed, which it should not.

The patch fixes this bug by only checking the PMP permissions if the address is
in range and its corresponding PMP entry it not off. Otherwise, it will keep
the ret = -1 which will be checked and handled correctly at the end of the
function.

Signed-off-by: Hesham Almatary 
---
 target/riscv/pmp.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index b11c4ae22f..8668f0dd7c 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -259,11 +259,12 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong 
addr,
 /* fully inside */
 const uint8_t a_field =
 pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
-if ((s + e) == 2) {
-if (PMP_AMATCH_OFF == a_field) {
-return 1;
-}

+/*
+ * If the PMP entry is not off and the address is in range, do the priv
+ * check
+ */
+if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
 allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
 if ((env->priv != PRV_M) || pmp_is_locked(env, i)) {
 allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
--
2.17.1

[Qemu-devel] [PATCHv3 2/5] RISC-V: Raise access fault exceptions on PMP violations

2019-05-21 Thread Hesham Almatary

Section 3.6 in RISC-V v1.10 privilege specification states that PMP violations
report "access exceptions." The current PMP implementation has
a bug which wrongly reports "page exceptions" on PMP violations.

This patch fixes this bug by reporting the correct PMP access exceptions
trap values.

Reviewed-by: Alistair Francis 
Signed-off-by: Hesham Almatary 
---
 target/riscv/cpu_helper.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 40fb47e794..7c7282c680 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -318,12 +318,13 @@ restart:
 }

 static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
-MMUAccessType access_type)
+MMUAccessType access_type, bool pmp_violation)
 {
 CPUState *cs = CPU(riscv_env_get_cpu(env));
 int page_fault_exceptions =
 (env->priv_ver >= PRIV_VERSION_1_10_0) &&
-get_field(env->satp, SATP_MODE) != VM_1_10_MBARE;
+get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
+!pmp_violation;
 switch (access_type) {
 case MMU_INST_FETCH:
 cs->exception_index = page_fault_exceptions ?
@@ -389,6 +390,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 CPURISCVState *env = &cpu->env;
 hwaddr pa = 0;
 int prot;
+bool pmp_violation = false;
 int ret = TRANSLATE_FAIL;

 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
@@ -403,6 +405,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 (ret == TRANSLATE_SUCCESS) &&
 !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) {
+pmp_violation = true;
 ret = TRANSLATE_FAIL;
 }
 if (ret == TRANSLATE_SUCCESS) {
@@ -412,7 +415,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 } else if (probe) {
 return false;
 } else {
-raise_mmu_exception(env, address, access_type);
+raise_mmu_exception(env, address, access_type, pmp_violation);
 riscv_raise_exception(env, cs->exception_index, retaddr);
 }
 #else
--
2.17.1

[Qemu-devel] [PATCHv3 5/5] RISC-V: Fix a PMP check with the correct access size

2019-05-21 Thread Hesham Almatary

The PMP check should be of the memory access size rather
than TARGET_PAGE_SIZE.

Signed-off-by: Hesham Almatary 
---
 target/riscv/cpu_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d0b0f9cf88..ce1f47e4e3 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -410,7 +410,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,

 if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 (ret == TRANSLATE_SUCCESS) &&
-!pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) {
+!pmp_hart_has_privs(env, pa, size, 1 << access_type)) {
 ret = TRANSLATE_PMP_FAIL;
 }
 if (ret == TRANSLATE_PMP_FAIL) {
--
2.17.1

[Qemu-devel] [PATCHv3 3/5] RISC-V: Check PMP during Page Table Walks

2019-05-21 Thread Hesham Almatary

The PMP should be checked when doing a page table walk, and report access
fault exception if the to-be-read PTE failed the PMP check.

Suggested-by: Jonathan Behrens 
Signed-off-by: Hesham Almatary 
---
 target/riscv/cpu.h|  1 +
 target/riscv/cpu_helper.c | 10 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c17184f4e4..ab3ba3f15a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -94,6 +94,7 @@ enum {
 #define PRIV_VERSION_1_09_1 0x00010901
 #define PRIV_VERSION_1_10_0 0x00011000

+#define TRANSLATE_PMP_FAIL 2
 #define TRANSLATE_FAIL 1
 #define TRANSLATE_SUCCESS 0
 #define NB_MMU_MODES 4
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 7c7282c680..d0b0f9cf88 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -211,6 +211,12 @@ restart:

 /* check that physical address of PTE is legal */
 target_ulong pte_addr = base + idx * ptesize;
+
+if (riscv_feature(env, RISCV_FEATURE_PMP) &&
+!pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
+1 << MMU_DATA_LOAD)) {
+return TRANSLATE_PMP_FAIL;
+}
 #if defined(TARGET_RISCV32)
 target_ulong pte = ldl_phys(cs->as, pte_addr);
 #elif defined(TARGET_RISCV64)
@@ -405,8 +411,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 (ret == TRANSLATE_SUCCESS) &&
 !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) {
+ret = TRANSLATE_PMP_FAIL;
+}
+if (ret == TRANSLATE_PMP_FAIL) {
 pmp_violation = true;
-ret = TRANSLATE_FAIL;
 }
 if (ret == TRANSLATE_SUCCESS) {
 tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
--
2.17.1

[Qemu-devel] [PATCHv3 1/5] RISC-V: Only Check PMP if MMU translation succeeds

2019-05-21 Thread Hesham Almatary

The current implementation unnecessarily checks for PMP even if MMU translation
failed. This may trigger a wrong PMP access exception instead of
a page exception.

For example, the very first instruction fetched after the first satp write in
S-Mode will trigger a PMP access fault instead of an instruction fetch page
fault.

This patch prioritises MMU exceptions over PMP exceptions and only checks for
PMP if MMU translation succeeds.

Signed-off-by: Hesham Almatary 
---
 target/riscv/cpu_helper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 41d6db41c3..40fb47e794 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -401,6 +401,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
   " prot %d\n", __func__, address, ret, pa, prot);

 if (riscv_feature(env, RISCV_FEATURE_PMP) &&
+(ret == TRANSLATE_SUCCESS) &&
 !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) {
 ret = TRANSLATE_FAIL;
 }
--
2.17.1

[Qemu-devel] [PATCHv2 1/3] RISC-V: Raise access fault exceptions on PMP violations

2019-05-18 Thread Hesham Almatary

Section 3.6 in RISC-V v1.10 privilege specification states that PMP violations
report "access exceptions." The current PMP implementation has
a bug which wrongly reports "page exceptions" on PMP violations.

This patch fixes this bug by reporting the correct PMP access exceptions
trap values.

Signed-off-by: Hesham Almatary 
---
 target/riscv/cpu_helper.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 41d6db41c3..b48de36114 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -318,12 +318,13 @@ restart:
 }

 static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
-MMUAccessType access_type)
+MMUAccessType access_type, bool pmp_violation)
 {
 CPUState *cs = CPU(riscv_env_get_cpu(env));
 int page_fault_exceptions =
 (env->priv_ver >= PRIV_VERSION_1_10_0) &&
-get_field(env->satp, SATP_MODE) != VM_1_10_MBARE;
+get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
+!pmp_violation;
 switch (access_type) {
 case MMU_INST_FETCH:
 cs->exception_index = page_fault_exceptions ?
@@ -389,6 +390,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 CPURISCVState *env = &cpu->env;
 hwaddr pa = 0;
 int prot;
+bool pmp_violation = false;
 int ret = TRANSLATE_FAIL;

 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
@@ -402,6 +404,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,

 if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) {
+pmp_violation = true;
 ret = TRANSLATE_FAIL;
 }
 if (ret == TRANSLATE_SUCCESS) {
@@ -411,7 +414,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 } else if (probe) {
 return false;
 } else {
-raise_mmu_exception(env, address, access_type);
+raise_mmu_exception(env, address, access_type, pmp_violation);
 riscv_raise_exception(env, cs->exception_index, retaddr);
 }
 #else
--
2.17.1

[Qemu-devel] [PATCHv2 2/3] RISC-V: Only Check PMP if MMU translation succeeds

2019-05-18 Thread Hesham Almatary

The current implementation unnecessarily checks for PMP even if MMU translation
failed. This may trigger a wrong PMP access exception instead of
a page exception.

For example, the very first instruction fetched after the first satp write in
S-Mode will trigger a PMP access fault instead of an instruction fetch page
fault.

This patch prioritises MMU exceptions over PMP exceptions and only checks for
PMP if MMU translation succeeds.

Signed-off-by: Hesham Almatary 
---
 target/riscv/cpu_helper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index b48de36114..7c7282c680 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -403,6 +403,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
   " prot %d\n", __func__, address, ret, pa, prot);

 if (riscv_feature(env, RISCV_FEATURE_PMP) &&
+(ret == TRANSLATE_SUCCESS) &&
 !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) {
 pmp_violation = true;
 ret = TRANSLATE_FAIL;
--
2.17.1

[Qemu-devel] [PATCHv3 3/3] RISC-V: Check PMP during Page Table Walks

2019-05-18 Thread Hesham Almatary

The PMP should be checked when doing a page table walk, and report access
fault exception if the to-be-read PTE address failed the PMP check.

Suggested-by: Jonathan Behrens 
Signed-off-by: Hesham Almatary 
---
 target/riscv/cpu.h|  1 +
 target/riscv/cpu_helper.c | 10 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c17184f4e4..ab3ba3f15a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -94,6 +94,7 @@ enum {
 #define PRIV_VERSION_1_09_1 0x00010901
 #define PRIV_VERSION_1_10_0 0x00011000

+#define TRANSLATE_PMP_FAIL 2
 #define TRANSLATE_FAIL 1
 #define TRANSLATE_SUCCESS 0
 #define NB_MMU_MODES 4
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 7c7282c680..d0b0f9cf88 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -211,6 +211,12 @@ restart:

 /* check that physical address of PTE is legal */
 target_ulong pte_addr = base + idx * ptesize;
+
+if (riscv_feature(env, RISCV_FEATURE_PMP) &&
+!pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
+1 << MMU_DATA_LOAD)) {
+return TRANSLATE_PMP_FAIL;
+}
 #if defined(TARGET_RISCV32)
 target_ulong pte = ldl_phys(cs->as, pte_addr);
 #elif defined(TARGET_RISCV64)
@@ -405,8 +411,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 (ret == TRANSLATE_SUCCESS) &&
 !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) {
+ret = TRANSLATE_PMP_FAIL;
+}
+if (ret == TRANSLATE_PMP_FAIL) {
 pmp_violation = true;
-ret = TRANSLATE_FAIL;
 }
 if (ret == TRANSLATE_SUCCESS) {
 tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
--
2.17.1

Re: [Qemu-devel] [Qemu-riscv] [PATCH 1/2] RISC-V: Raise access fault exceptions on PMP violations

2019-05-18 Thread Hesham Almatary

Hi Jonathan,

Thanks for your feedback.

On Sat, 18 May 2019 at 22:51, Jonathan Behrens  wrote:
>
> This patch assumes that translation failure should always raise a paging 
> fault, but it should be possible for it to raise an access fault as well 
> (since according to the spec "PMP  checks  are  also  applied  to  page-table 
>  accesses  for  virtual-address translation, for which the effective 
> privilege mode is S."). I think the code to actually do the PMP checking 
> during page table walks is currently unimplemented though...
>

The patch actually fixes (rather than assumes) one issue of the
current implementation which always raises a paging fault "when
translation succeeds and PMP fails". The second issue that you report
here which happens "when the PTW fails the PMP check" could be another
future separate fix.

I am happy to submit another patch to fix the second issue.

> Jonathan
>
> On Sat, May 18, 2019 at 3:14 PM Hesham Almatary 
>  wrote:
>>
>> Section 3.6 in RISC-V v1.10 privilege specification states that PMP 
>> violations
>> report "access exceptions." The current PMP implementation has
>> a bug which wrongly reports "page exceptions" on PMP violations.
>>
>> This patch fixes this bug by reporting the correct PMP access exceptions
>> trap values.
>>
>> Signed-off-by: Hesham Almatary 
>> ---
>>  target/riscv/cpu_helper.c | 9 ++---
>>  1 file changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>> index 41d6db41c3..b48de36114 100644
>> --- a/target/riscv/cpu_helper.c
>> +++ b/target/riscv/cpu_helper.c
>> @@ -318,12 +318,13 @@ restart:
>>  }
>>
>>  static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
>> -MMUAccessType access_type)
>> +MMUAccessType access_type, bool 
>> pmp_violation)
>>  {
>>  CPUState *cs = CPU(riscv_env_get_cpu(env));
>>  int page_fault_exceptions =
>>  (env->priv_ver >= PRIV_VERSION_1_10_0) &&
>> -get_field(env->satp, SATP_MODE) != VM_1_10_MBARE;
>> +get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
>> +!pmp_violation;
>>  switch (access_type) {
>>  case MMU_INST_FETCH:
>>  cs->exception_index = page_fault_exceptions ?
>> @@ -389,6 +390,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
>> size,
>>  CPURISCVState *env = &cpu->env;
>>  hwaddr pa = 0;
>>  int prot;
>> +bool pmp_violation = false;
>>  int ret = TRANSLATE_FAIL;
>>
>>  qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
>> @@ -402,6 +404,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
>> size,
>>
>>  if (riscv_feature(env, RISCV_FEATURE_PMP) &&
>>  !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) {
>> +pmp_violation = true;
>>  ret = TRANSLATE_FAIL;
>>  }
>>  if (ret == TRANSLATE_SUCCESS) {
>> @@ -411,7 +414,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
>> size,
>>  } else if (probe) {
>>  return false;
>>  } else {
>> -raise_mmu_exception(env, address, access_type);
>> +raise_mmu_exception(env, address, access_type, pmp_violation);
>>  riscv_raise_exception(env, cs->exception_index, retaddr);
>>  }
>>  #else
>> --
>> 2.17.1
>>
>>

[Qemu-devel] [PATCH 2/2] RISC-V: Only Check PMP if MMU translation succeeds

2019-05-18 Thread Hesham Almatary

The current implementation unnecessarily checks for PMP even if MMU translation
failed. This may trigger a wrong PMP access exception instead of
a page exception.

For example, the very first instruction fetched after the first satp write in
S-Mode will trigger a PMP access fault instead of an instruction fetch page
fault.

This patch prioritises MMU exceptions over PMP exceptions and only checks for
PMP if MMU translation succeeds.

Signed-off-by: Hesham Almatary 
---
 target/riscv/cpu_helper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index b48de36114..7c7282c680 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -403,6 +403,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
   " prot %d\n", __func__, address, ret, pa, prot);

 if (riscv_feature(env, RISCV_FEATURE_PMP) &&
+(ret == TRANSLATE_SUCCESS) &&
 !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) {
 pmp_violation = true;
 ret = TRANSLATE_FAIL;
--
2.17.1

[Qemu-devel] [PATCH 1/2] RISC-V: Raise access fault exceptions on PMP violations

2019-05-18 Thread Hesham Almatary

Section 3.6 in RISC-V v1.10 privilege specification states that PMP violations
report "access exceptions." The current PMP implementation has
a bug which wrongly reports "page exceptions" on PMP violations.

This patch fixes this bug by reporting the correct PMP access exceptions
trap values.

Signed-off-by: Hesham Almatary 
---
 target/riscv/cpu_helper.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 41d6db41c3..b48de36114 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -318,12 +318,13 @@ restart:
 }

 static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
-MMUAccessType access_type)
+MMUAccessType access_type, bool pmp_violation)
 {
 CPUState *cs = CPU(riscv_env_get_cpu(env));
 int page_fault_exceptions =
 (env->priv_ver >= PRIV_VERSION_1_10_0) &&
-get_field(env->satp, SATP_MODE) != VM_1_10_MBARE;
+get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
+!pmp_violation;
 switch (access_type) {
 case MMU_INST_FETCH:
 cs->exception_index = page_fault_exceptions ?
@@ -389,6 +390,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 CPURISCVState *env = &cpu->env;
 hwaddr pa = 0;
 int prot;
+bool pmp_violation = false;
 int ret = TRANSLATE_FAIL;

 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
@@ -402,6 +404,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,

 if (riscv_feature(env, RISCV_FEATURE_PMP) &&
 !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) {
+pmp_violation = true;
 ret = TRANSLATE_FAIL;
 }
 if (ret == TRANSLATE_SUCCESS) {
@@ -411,7 +414,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 } else if (probe) {
 return false;
 } else {
-raise_mmu_exception(env, address, access_type);
+raise_mmu_exception(env, address, access_type, pmp_violation);
 riscv_raise_exception(env, cs->exception_index, retaddr);
 }
 #else
--
2.17.1

[Qemu-devel] [PATCH] openrisc: terminate qemu process upon receiving a halt signal.

2015-04-02 Thread Hesham ALMatary

or1ksim simulator currently handles "l.nop 0xC" instruction as
a halt signal. Do the same for QEMU.

Signed-off-by: Hesham ALMatary  
---
 target-openrisc/translate.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index dc76789..5fa8ede 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -750,6 +750,11 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
 switch (op1) {
 case 0x01:/* l.nop */
 LOG_DIS("l.nop %d\n", I16);
+
+if(I16 == 0xC) {
+exit(0);
+}
+
 break;
 
 default:
-- 
2.1.0

[Qemu-devel] [PATCH] openrisc: terminate qemu process upon receiving a halt signal.

2015-04-02 Thread Hesham ALMatary

or1ksim simulator currently handles "l.nop 0xC" instruction as a halt signal. Do
the same for QEMU.

Signed-off-by: Hesham ALMatary  
---
 target-openrisc/translate.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index dc76789..b024f11 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -750,6 +750,11 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
 switch (op1) {
 case 0x01:/* l.nop */
 LOG_DIS("l.nop %d\n", I16);
+
+   if(I16 == 0xC) {
+exit(0);
+}
+
 break;
 
 default:
-- 
2.1.0

64 matches

Mail list logo